db_interface.c revision 1.47
1 /* $NetBSD: db_interface.c,v 1.47 2009/03/14 15:36:01 dsl Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.47 2009/03/14 15:36:01 dsl Exp $"); 39 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 43 #include <sys/param.h> 44 #include <sys/proc.h> 45 #include <sys/reboot.h> 46 #include <sys/systm.h> /* just for boothowto */ 47 #include <sys/exec.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <arm/arm32/db_machdep.h> 52 #include <arm/arm32/katelib.h> 53 #include <arm/undefined.h> 54 #include <ddb/db_access.h> 55 #include <ddb/db_command.h> 56 #include <ddb/db_output.h> 57 #include <ddb/db_variables.h> 58 #include <ddb/db_sym.h> 59 #include <ddb/db_extern.h> 60 #include <ddb/db_interface.h> 61 #include <dev/cons.h> 62 63 #if defined(KGDB) || !defined(DDB) 64 #define db_printf printf 65 #endif 66 67 static long nil; 68 69 int db_access_und_sp(const struct db_variable *, db_expr_t *, int); 70 int db_access_abt_sp(const struct db_variable *, db_expr_t *, int); 71 int db_access_irq_sp(const struct db_variable *, db_expr_t *, int); 72 u_int db_fetch_reg(int, db_regs_t *); 73 74 int db_trapper(u_int, u_int, trapframe_t *, int); 75 76 const struct db_variable db_regs[] = { 77 { "spsr", (long *)&DDB_REGS->tf_spsr, FCN_NULL, }, 78 { "r0", (long *)&DDB_REGS->tf_r0, FCN_NULL, }, 79 { "r1", (long *)&DDB_REGS->tf_r1, FCN_NULL, }, 80 { "r2", (long *)&DDB_REGS->tf_r2, FCN_NULL, }, 81 { "r3", (long *)&DDB_REGS->tf_r3, FCN_NULL, }, 82 { "r4", (long *)&DDB_REGS->tf_r4, FCN_NULL, }, 83 { "r5", (long *)&DDB_REGS->tf_r5, FCN_NULL, }, 84 { "r6", (long *)&DDB_REGS->tf_r6, FCN_NULL, }, 85 { "r7", (long *)&DDB_REGS->tf_r7, FCN_NULL, }, 86 { "r8", (long *)&DDB_REGS->tf_r8, FCN_NULL, }, 87 { "r9", (long *)&DDB_REGS->tf_r9, FCN_NULL, }, 88 { "r10", (long *)&DDB_REGS->tf_r10, FCN_NULL, }, 89 { "r11", (long *)&DDB_REGS->tf_r11, FCN_NULL, }, 90 { "r12", (long *)&DDB_REGS->tf_r12, FCN_NULL, }, 91 { "usr_sp", (long *)&DDB_REGS->tf_usr_sp, FCN_NULL, }, 92 { "usr_lr", (long *)&DDB_REGS->tf_usr_lr, FCN_NULL, }, 93 { "svc_sp", (long *)&DDB_REGS->tf_svc_sp, FCN_NULL, }, 94 { "svc_lr", (long *)&DDB_REGS->tf_svc_lr, FCN_NULL, }, 95 { "pc", (long *)&DDB_REGS->tf_pc, FCN_NULL, }, 96 { "und_sp", &nil, db_access_und_sp, }, 97 { "abt_sp", &nil, db_access_abt_sp, }, 98 { "irq_sp", &nil, db_access_irq_sp, }, 99 }; 100 101 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 102 103 int db_active = 0; 104 db_regs_t ddb_regs; /* register state */ 105 106 int 107 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 108 { 109 110 if (rw == DB_VAR_GET) 111 *valp = get_stackptr(PSR_UND32_MODE); 112 return(0); 113 } 114 115 int 116 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 117 { 118 119 if (rw == DB_VAR_GET) 120 *valp = get_stackptr(PSR_ABT32_MODE); 121 return(0); 122 } 123 124 int 125 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 126 { 127 128 if (rw == DB_VAR_GET) 129 *valp = get_stackptr(PSR_IRQ32_MODE); 130 return(0); 131 } 132 133 #ifdef DDB 134 /* 135 * kdb_trap - field a TRACE or BPT trap 136 */ 137 int 138 kdb_trap(int type, db_regs_t *regs) 139 { 140 int s; 141 142 switch (type) { 143 case T_BREAKPOINT: /* breakpoint */ 144 case -1: /* keyboard interrupt */ 145 break; 146 default: 147 if (db_recover != 0) { 148 /* This will longjmp back into db_command_loop() */ 149 db_error("Faulted in DDB; continuing...\n"); 150 /*NOTREACHED*/ 151 } 152 } 153 154 /* Should switch to kdb`s own stack here. */ 155 156 ddb_regs = *regs; 157 158 s = splhigh(); 159 db_active++; 160 cnpollc(true); 161 db_trap(type, 0/*code*/); 162 cnpollc(false); 163 db_active--; 164 splx(s); 165 166 *regs = ddb_regs; 167 168 return (1); 169 } 170 #endif 171 172 int 173 db_validate_address(vaddr_t addr) 174 { 175 struct proc *p = curproc; 176 struct pmap *pmap; 177 178 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 179 #ifndef ARM32_NEW_VM_LAYOUT 180 addr >= VM_MAXUSER_ADDRESS 181 #else 182 addr >= VM_MIN_KERNEL_ADDRESS 183 #endif 184 ) 185 pmap = pmap_kernel(); 186 else 187 pmap = p->p_vmspace->vm_map.pmap; 188 189 return (pmap_extract(pmap, addr, NULL) == false); 190 } 191 192 /* 193 * Read bytes from kernel address space for debugger. 194 */ 195 void 196 db_read_bytes(vaddr_t addr, size_t size, char *data) 197 { 198 char *src = (char *)addr; 199 200 if (db_validate_address((u_int)src)) { 201 db_printf("address %p is invalid\n", src); 202 return; 203 } 204 205 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) { 206 *((int*)data) = *((int*)src); 207 return; 208 } 209 210 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) { 211 *((short*)data) = *((short*)src); 212 return; 213 } 214 215 while (size-- > 0) { 216 if (db_validate_address((u_int)src)) { 217 db_printf("address %p is invalid\n", src); 218 return; 219 } 220 *data++ = *src++; 221 } 222 } 223 224 static void 225 db_write_text(vaddr_t addr, size_t size, const char *data) 226 { 227 struct pmap *pmap = pmap_kernel(); 228 pd_entry_t *pde, oldpde, tmppde; 229 pt_entry_t *pte, oldpte, tmppte; 230 vaddr_t pgva; 231 size_t limit, savesize; 232 char *dst; 233 234 /* XXX: gcc */ 235 oldpte = 0; 236 237 if ((savesize = size) == 0) 238 return; 239 240 dst = (char *) addr; 241 242 do { 243 /* Get the PDE of the current VA. */ 244 if (pmap_get_pde_pte(pmap, (vaddr_t) dst, &pde, &pte) == false) 245 goto no_mapping; 246 switch ((oldpde = *pde) & L1_TYPE_MASK) { 247 case L1_TYPE_S: 248 pgva = (vaddr_t)dst & L1_S_FRAME; 249 limit = L1_S_SIZE - ((vaddr_t)dst & L1_S_OFFSET); 250 251 tmppde = oldpde | L1_S_PROT_W; 252 *pde = tmppde; 253 PTE_SYNC(pde); 254 break; 255 256 case L1_TYPE_C: 257 pgva = (vaddr_t)dst & L2_S_FRAME; 258 limit = L2_S_SIZE - ((vaddr_t)dst & L2_S_OFFSET); 259 260 if (pte == NULL) 261 goto no_mapping; 262 oldpte = *pte; 263 tmppte = oldpte | L2_S_PROT_W; 264 *pte = tmppte; 265 PTE_SYNC(pte); 266 break; 267 268 default: 269 no_mapping: 270 printf(" address 0x%08lx not a valid page\n", 271 (vaddr_t) dst); 272 return; 273 } 274 cpu_tlb_flushD_SE(pgva); 275 cpu_cpwait(); 276 277 if (limit > size) 278 limit = size; 279 size -= limit; 280 281 /* 282 * Page is now writable. Do as much access as we 283 * can in this page. 284 */ 285 for (; limit > 0; limit--) 286 *dst++ = *data++; 287 288 /* 289 * Restore old mapping permissions. 290 */ 291 switch (oldpde & L1_TYPE_MASK) { 292 case L1_TYPE_S: 293 *pde = oldpde; 294 PTE_SYNC(pde); 295 break; 296 297 case L1_TYPE_C: 298 *pte = oldpte; 299 PTE_SYNC(pte); 300 break; 301 } 302 cpu_tlb_flushD_SE(pgva); 303 cpu_cpwait(); 304 } while (size != 0); 305 306 /* Sync the I-cache. */ 307 cpu_icache_sync_range(addr, savesize); 308 } 309 310 /* 311 * Write bytes to kernel address space for debugger. 312 */ 313 void 314 db_write_bytes(vaddr_t addr, size_t size, const char *data) 315 { 316 extern char kernel_text[]; 317 extern char etext[]; 318 char *dst; 319 size_t loop; 320 321 /* If any part is in kernel text, use db_write_text() */ 322 if (addr >= (vaddr_t) kernel_text && addr < (vaddr_t) etext) { 323 db_write_text(addr, size, data); 324 return; 325 } 326 327 dst = (char *)addr; 328 if (db_validate_address((u_int)dst)) { 329 db_printf("address %p is invalid\n", dst); 330 return; 331 } 332 333 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) 334 *((int*)dst) = *((const int *)data); 335 else 336 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) 337 *((short*)dst) = *((const short *)data); 338 else { 339 loop = size; 340 while (loop-- > 0) { 341 if (db_validate_address((u_int)dst)) { 342 db_printf("address %p is invalid\n", dst); 343 return; 344 } 345 *dst++ = *data++; 346 } 347 } 348 349 /* make sure the caches and memory are in sync */ 350 cpu_icache_sync_range(addr, size); 351 352 /* In case the current page tables have been modified ... */ 353 cpu_tlb_flushID(); 354 cpu_cpwait(); 355 } 356 357 #ifdef DDB 358 void 359 cpu_Debugger(void) 360 { 361 __asm(".word 0xe7ffffff"); 362 } 363 364 const struct db_command db_machine_command_table[] = { 365 { DDB_ADD_CMD("frame", db_show_frame_cmd, 0, 366 "Displays the contents of a trapframe", 367 "[address]", 368 " address:\taddress of trapfame to display")}, 369 { DDB_ADD_CMD("panic", db_show_panic_cmd, 0, 370 "Displays the last panic string", 371 NULL,NULL) }, 372 #ifdef ARM32_DB_COMMANDS 373 ARM32_DB_COMMANDS, 374 #endif 375 { DDB_ADD_CMD(NULL, NULL, 0,NULL,NULL,NULL) } 376 }; 377 378 int 379 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 380 { 381 382 if (fault_code == 0) { 383 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 384 kdb_trap(T_BREAKPOINT, frame); 385 else 386 kdb_trap(-1, frame); 387 } else 388 return (1); 389 return (0); 390 } 391 392 extern u_int esym; 393 extern u_int end; 394 395 static struct undefined_handler db_uh; 396 397 void 398 db_machine_init(void) 399 { 400 401 /* 402 * We get called before malloc() is available, so supply a static 403 * struct undefined_handler. 404 */ 405 db_uh.uh_handler = db_trapper; 406 install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &db_uh); 407 } 408 #endif 409 410 u_int 411 db_fetch_reg(int reg, db_regs_t *regs) 412 { 413 414 switch (reg) { 415 case 0: 416 return (regs->tf_r0); 417 case 1: 418 return (regs->tf_r1); 419 case 2: 420 return (regs->tf_r2); 421 case 3: 422 return (regs->tf_r3); 423 case 4: 424 return (regs->tf_r4); 425 case 5: 426 return (regs->tf_r5); 427 case 6: 428 return (regs->tf_r6); 429 case 7: 430 return (regs->tf_r7); 431 case 8: 432 return (regs->tf_r8); 433 case 9: 434 return (regs->tf_r9); 435 case 10: 436 return (regs->tf_r10); 437 case 11: 438 return (regs->tf_r11); 439 case 12: 440 return (regs->tf_r12); 441 case 13: 442 return (regs->tf_svc_sp); 443 case 14: 444 return (regs->tf_svc_lr); 445 case 15: 446 return (regs->tf_pc); 447 default: 448 panic("db_fetch_reg: botch"); 449 } 450 } 451 452 u_int 453 branch_taken(u_int insn, u_int pc, db_regs_t *regs) 454 { 455 u_int addr, nregs; 456 457 switch ((insn >> 24) & 0xf) { 458 case 0xa: /* b ... */ 459 case 0xb: /* bl ... */ 460 addr = ((insn << 2) & 0x03ffffff); 461 if (addr & 0x02000000) 462 addr |= 0xfc000000; 463 return (pc + 8 + addr); 464 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 465 addr = db_fetch_reg(insn & 0xf, regs); 466 addr = pc + 8 + (addr << 2); 467 db_read_bytes(addr, 4, (char *)&addr); 468 return (addr); 469 case 0x5: /* ldr pc, [reg] */ 470 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 471 db_read_bytes(addr, 4, (char *)&addr); 472 return (addr); 473 case 0x1: /* mov pc, reg */ 474 addr = db_fetch_reg(insn & 0xf, regs); 475 return (addr); 476 case 0x8: /* ldmxx reg, {..., pc} */ 477 case 0x9: 478 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 479 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 480 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 481 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 482 nregs = (nregs + (nregs >> 8)) & 0x001f; 483 switch ((insn >> 23) & 0x3) { 484 case 0x0: /* ldmda */ 485 addr = addr - 0; 486 break; 487 case 0x1: /* ldmia */ 488 addr = addr + 0 + ((nregs - 1) << 2); 489 break; 490 case 0x2: /* ldmdb */ 491 addr = addr - 4; 492 break; 493 case 0x3: /* ldmib */ 494 addr = addr + 4 + ((nregs - 1) << 2); 495 break; 496 } 497 db_read_bytes(addr, 4, (char *)&addr); 498 return (addr); 499 default: 500 panic("branch_taken: botch"); 501 } 502 } 503
Indexes created Tue Sep 30 07:10:03 GMT 2025