db_interface.c revision 1.50
1 /* $NetBSD: db_interface.c,v 1.50 2013/12/15 09:13:47 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.50 2013/12/15 09:13:47 skrll Exp $"); 39 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 43 #include <sys/param.h> 44 #include <sys/proc.h> 45 #include <sys/reboot.h> 46 #include <sys/systm.h> /* just for boothowto */ 47 #include <sys/exec.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <arm/arm32/db_machdep.h> 52 #include <arm/arm32/katelib.h> 53 #include <arm/undefined.h> 54 #include <ddb/db_access.h> 55 #include <ddb/db_command.h> 56 #include <ddb/db_output.h> 57 #include <ddb/db_variables.h> 58 #include <ddb/db_sym.h> 59 #include <ddb/db_extern.h> 60 #include <ddb/db_interface.h> 61 #include <dev/cons.h> 62 63 #if defined(KGDB) || !defined(DDB) 64 #define db_printf printf 65 #endif 66 67 u_int db_fetch_reg(int, db_regs_t *); 68 69 int db_trapper(u_int, u_int, trapframe_t *, int); 70 71 int db_active = 0; 72 db_regs_t ddb_regs; /* register state */ 73 74 75 #ifdef DDB 76 /* 77 * kdb_trap - field a TRACE or BPT trap 78 */ 79 int 80 kdb_trap(int type, db_regs_t *regs) 81 { 82 int s; 83 84 switch (type) { 85 case T_BREAKPOINT: /* breakpoint */ 86 case -1: /* keyboard interrupt */ 87 break; 88 default: 89 if (db_recover != 0) { 90 /* This will longjmp back into db_command_loop() */ 91 db_error("Faulted in DDB; continuing...\n"); 92 /*NOTREACHED*/ 93 } 94 } 95 96 /* Should switch to kdb`s own stack here. */ 97 98 ddb_regs = *regs; 99 100 s = splhigh(); 101 db_active++; 102 cnpollc(true); 103 db_trap(type, 0/*code*/); 104 cnpollc(false); 105 db_active--; 106 splx(s); 107 108 *regs = ddb_regs; 109 110 return (1); 111 } 112 #endif 113 114 int 115 db_validate_address(vaddr_t addr) 116 { 117 struct proc *p = curproc; 118 struct pmap *pmap; 119 120 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 121 #ifndef ARM32_NEW_VM_LAYOUT 122 addr >= VM_MAXUSER_ADDRESS 123 #else 124 addr >= VM_MIN_KERNEL_ADDRESS 125 #endif 126 ) 127 pmap = pmap_kernel(); 128 else 129 pmap = p->p_vmspace->vm_map.pmap; 130 131 return (pmap_extract(pmap, addr, NULL) == false); 132 } 133 134 /* 135 * Read bytes from kernel address space for debugger. 136 */ 137 void 138 db_read_bytes(vaddr_t addr, size_t size, char *data) 139 { 140 char *src = (char *)addr; 141 142 if (db_validate_address((u_int)src)) { 143 db_printf("address %p is invalid\n", src); 144 return; 145 } 146 147 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) { 148 *((int*)data) = *((int*)src); 149 return; 150 } 151 152 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) { 153 *((short*)data) = *((short*)src); 154 return; 155 } 156 157 while (size-- > 0) { 158 if (db_validate_address((u_int)src)) { 159 db_printf("address %p is invalid\n", src); 160 return; 161 } 162 *data++ = *src++; 163 } 164 } 165 166 static void 167 db_write_text(vaddr_t addr, size_t size, const char *data) 168 { 169 struct pmap *pmap = pmap_kernel(); 170 pd_entry_t *pde, oldpde, tmppde; 171 pt_entry_t *pte, oldpte, tmppte; 172 vaddr_t pgva; 173 size_t limit, savesize; 174 char *dst; 175 176 /* XXX: gcc */ 177 oldpte = 0; 178 179 if ((savesize = size) == 0) 180 return; 181 182 dst = (char *) addr; 183 184 do { 185 /* Get the PDE of the current VA. */ 186 if (pmap_get_pde_pte(pmap, (vaddr_t) dst, &pde, &pte) == false) 187 goto no_mapping; 188 switch ((oldpde = *pde) & L1_TYPE_MASK) { 189 case L1_TYPE_S: 190 pgva = (vaddr_t)dst & L1_S_FRAME; 191 limit = L1_S_SIZE - ((vaddr_t)dst & L1_S_OFFSET); 192 193 tmppde = l1pte_set_writable(oldpde); 194 *pde = tmppde; 195 PTE_SYNC(pde); 196 break; 197 198 case L1_TYPE_C: 199 pgva = (vaddr_t)dst & L2_S_FRAME; 200 limit = L2_S_SIZE - ((vaddr_t)dst & L2_S_OFFSET); 201 202 if (pte == NULL) 203 goto no_mapping; 204 oldpte = *pte; 205 tmppte = l2pte_set_writable(oldpte); 206 *pte = tmppte; 207 PTE_SYNC(pte); 208 break; 209 210 default: 211 no_mapping: 212 printf(" address 0x%08lx not a valid page\n", 213 (vaddr_t) dst); 214 return; 215 } 216 cpu_tlb_flushD_SE(pgva); 217 cpu_cpwait(); 218 219 if (limit > size) 220 limit = size; 221 size -= limit; 222 223 /* 224 * Page is now writable. Do as much access as we 225 * can in this page. 226 */ 227 for (; limit > 0; limit--) 228 *dst++ = *data++; 229 230 /* 231 * Restore old mapping permissions. 232 */ 233 switch (oldpde & L1_TYPE_MASK) { 234 case L1_TYPE_S: 235 *pde = oldpde; 236 PTE_SYNC(pde); 237 break; 238 239 case L1_TYPE_C: 240 *pte = oldpte; 241 PTE_SYNC(pte); 242 break; 243 } 244 cpu_tlb_flushD_SE(pgva); 245 cpu_cpwait(); 246 } while (size != 0); 247 248 /* Sync the I-cache. */ 249 cpu_icache_sync_range(addr, savesize); 250 } 251 252 /* 253 * Write bytes to kernel address space for debugger. 254 */ 255 void 256 db_write_bytes(vaddr_t addr, size_t size, const char *data) 257 { 258 extern char kernel_text[]; 259 extern char etext[]; 260 char *dst; 261 size_t loop; 262 263 /* If any part is in kernel text, use db_write_text() */ 264 if (addr >= (vaddr_t) kernel_text && addr < (vaddr_t) etext) { 265 db_write_text(addr, size, data); 266 return; 267 } 268 269 dst = (char *)addr; 270 if (db_validate_address((u_int)dst)) { 271 db_printf("address %p is invalid\n", dst); 272 return; 273 } 274 275 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) 276 *((int*)dst) = *((const int *)data); 277 else 278 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) 279 *((short*)dst) = *((const short *)data); 280 else { 281 loop = size; 282 while (loop-- > 0) { 283 if (db_validate_address((u_int)dst)) { 284 db_printf("address %p is invalid\n", dst); 285 return; 286 } 287 *dst++ = *data++; 288 } 289 } 290 291 /* make sure the caches and memory are in sync */ 292 cpu_icache_sync_range(addr, size); 293 294 /* In case the current page tables have been modified ... */ 295 cpu_tlb_flushID(); 296 cpu_cpwait(); 297 } 298 299 #ifdef DDB 300 void 301 cpu_Debugger(void) 302 { 303 __asm(".word 0xe7ffffff"); 304 } 305 306 int 307 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 308 { 309 310 if (fault_code == 0) { 311 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 312 kdb_trap(T_BREAKPOINT, frame); 313 else 314 kdb_trap(-1, frame); 315 } else 316 return (1); 317 return (0); 318 } 319 320 extern u_int esym; 321 extern u_int end; 322 323 static struct undefined_handler db_uh; 324 325 void 326 db_machine_init(void) 327 { 328 329 /* 330 * We get called before malloc() is available, so supply a static 331 * struct undefined_handler. 332 */ 333 db_uh.uh_handler = db_trapper; 334 install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &db_uh); 335 } 336 #endif 337 338 u_int 339 db_fetch_reg(int reg, db_regs_t *regs) 340 { 341 342 switch (reg) { 343 case 0: 344 return (regs->tf_r0); 345 case 1: 346 return (regs->tf_r1); 347 case 2: 348 return (regs->tf_r2); 349 case 3: 350 return (regs->tf_r3); 351 case 4: 352 return (regs->tf_r4); 353 case 5: 354 return (regs->tf_r5); 355 case 6: 356 return (regs->tf_r6); 357 case 7: 358 return (regs->tf_r7); 359 case 8: 360 return (regs->tf_r8); 361 case 9: 362 return (regs->tf_r9); 363 case 10: 364 return (regs->tf_r10); 365 case 11: 366 return (regs->tf_r11); 367 case 12: 368 return (regs->tf_r12); 369 case 13: 370 return (regs->tf_svc_sp); 371 case 14: 372 return (regs->tf_svc_lr); 373 case 15: 374 return (regs->tf_pc); 375 default: 376 panic("db_fetch_reg: botch"); 377 } 378 } 379 380 u_int 381 branch_taken(u_int insn, u_int pc, db_regs_t *regs) 382 { 383 u_int addr, nregs; 384 385 switch ((insn >> 24) & 0xf) { 386 case 0xa: /* b ... */ 387 case 0xb: /* bl ... */ 388 addr = ((insn << 2) & 0x03ffffff); 389 if (addr & 0x02000000) 390 addr |= 0xfc000000; 391 return (pc + 8 + addr); 392 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 393 addr = db_fetch_reg(insn & 0xf, regs); 394 addr = pc + 8 + (addr << 2); 395 db_read_bytes(addr, 4, (char *)&addr); 396 return (addr); 397 case 0x5: /* ldr pc, [reg] */ 398 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 399 db_read_bytes(addr, 4, (char *)&addr); 400 return (addr); 401 case 0x1: /* mov pc, reg */ 402 addr = db_fetch_reg(insn & 0xf, regs); 403 return (addr); 404 case 0x8: /* ldmxx reg, {..., pc} */ 405 case 0x9: 406 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 407 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 408 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 409 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 410 nregs = (nregs + (nregs >> 8)) & 0x001f; 411 switch ((insn >> 23) & 0x3) { 412 case 0x0: /* ldmda */ 413 addr = addr - 0; 414 break; 415 case 0x1: /* ldmia */ 416 addr = addr + 0 + ((nregs - 1) << 2); 417 break; 418 case 0x2: /* ldmdb */ 419 addr = addr - 4; 420 break; 421 case 0x3: /* ldmib */ 422 addr = addr + 4 + ((nregs - 1) << 2); 423 break; 424 } 425 db_read_bytes(addr, 4, (char *)&addr); 426 return (addr); 427 default: 428 panic("branch_taken: botch"); 429 } 430 } 431
Indexes created Tue Sep 30 10:09:55 GMT 2025