db_interface.c revision 1.57
1 /* $NetBSD: db_interface.c,v 1.57 2018/01/17 20:30:16 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.57 2018/01/17 20:30:16 skrll Exp $"); 39 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 #include "opt_multiprocessor.h" 43 44 #include <sys/param.h> 45 #include <sys/proc.h> 46 #include <sys/reboot.h> 47 #include <sys/systm.h> /* just for boothowto */ 48 #include <sys/exec.h> 49 #include <sys/atomic.h> 50 #include <sys/intr.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <arm/arm32/db_machdep.h> 55 #include <arm/undefined.h> 56 #include <ddb/db_access.h> 57 #include <ddb/db_command.h> 58 #include <ddb/db_output.h> 59 #include <ddb/db_variables.h> 60 #include <ddb/db_sym.h> 61 #include <ddb/db_extern.h> 62 #include <ddb/db_interface.h> 63 #include <dev/cons.h> 64 65 #if defined(KGDB) || !defined(DDB) 66 #define db_printf printf 67 #endif 68 69 u_int db_fetch_reg(int, db_regs_t *); 70 71 int db_trapper(u_int, u_int, trapframe_t *, int); 72 73 int db_active = 0; 74 db_regs_t ddb_regs; /* register state */ 75 db_regs_t *ddb_regp; 76 77 #ifdef MULTIPROCESSOR 78 volatile struct cpu_info *db_onproc; 79 volatile struct cpu_info *db_newcpu; 80 #endif 81 82 83 84 85 #ifdef DDB 86 /* 87 * kdb_trap - field a TRACE or BPT trap 88 */ 89 int 90 kdb_trap(int type, db_regs_t *regs) 91 { 92 struct cpu_info * const ci = curcpu(); 93 db_regs_t dbreg; 94 int s; 95 96 switch (type) { 97 case T_BREAKPOINT: /* breakpoint */ 98 case -1: /* keyboard interrupt */ 99 break; 100 #ifdef MULTIPROCESSOR 101 case -2: 102 /* 103 * We called to enter ddb from another process but by the time 104 * we got here, no one was in ddb. So ignore the request. 105 */ 106 if (db_onproc == NULL) 107 return 1; 108 break; 109 #endif 110 default: 111 if (db_recover != 0) { 112 /* This will longjmp back into db_command_loop() */ 113 db_error("Faulted in DDB; continuing...\n"); 114 /*NOTREACHED*/ 115 } 116 } 117 118 /* Should switch to kdb`s own stack here. */ 119 120 #ifdef MULTIPROCESSOR 121 const bool is_mp_p = ncpu > 1; 122 if (is_mp_p) { 123 /* 124 * Try to take ownership of DDB. If we do, tell all other 125 * CPUs to enter DDB too. 126 */ 127 if (atomic_cas_ptr(&db_onproc, NULL, ci) == NULL) { 128 intr_ipi_send(NULL, IPI_DDB); 129 } 130 } 131 for (;;) { 132 if (is_mp_p) { 133 /* 134 * While we aren't the master, wait until the master 135 * gives control to us or exits. If it exited, we 136 * just exit too. Otherwise this cpu will enter DDB. 137 */ 138 membar_consumer(); 139 while (db_onproc != ci) { 140 if (db_onproc == NULL) 141 return 1; 142 #ifdef _ARM_ARCH_6 143 __asm __volatile("wfe"); 144 membar_consumer(); 145 #endif 146 if (db_onproc == ci) { 147 printf("%s: switching to %s\n", 148 __func__, ci->ci_cpuname); 149 } 150 } 151 } 152 #endif 153 154 s = splhigh(); 155 ci->ci_ddb_regs = &dbreg; 156 ddb_regp = &dbreg; 157 ddb_regs = *regs; 158 159 atomic_inc_32(&db_active); 160 cnpollc(true); 161 db_trap(type, 0/*code*/); 162 cnpollc(false); 163 atomic_dec_32(&db_active); 164 165 ci->ci_ddb_regs = NULL; 166 ddb_regp = &dbreg; 167 *regs = ddb_regs; 168 splx(s); 169 170 #ifdef MULTIPROCESSOR 171 if (is_mp_p && db_newcpu != NULL) { 172 db_onproc = db_newcpu; 173 db_newcpu = NULL; 174 #ifdef _ARM_ARCH_6 175 membar_producer(); 176 __asm __volatile("sev; sev"); 177 #endif 178 continue; 179 } 180 break; 181 } 182 183 if (is_mp_p) { 184 /* 185 * We are exiting DDB so there is noone onproc. Tell 186 * the other CPUs to exit. 187 */ 188 db_onproc = NULL; 189 #ifdef _ARM_ARCH_6 190 __asm __volatile("sev; sev"); 191 #endif 192 } 193 #endif 194 195 return 1; 196 } 197 #endif 198 199 int 200 db_validate_address(vaddr_t addr) 201 { 202 struct proc *p = curproc; 203 struct pmap *pmap; 204 205 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 206 addr >= VM_MIN_KERNEL_ADDRESS 207 ) 208 pmap = pmap_kernel(); 209 else 210 pmap = p->p_vmspace->vm_map.pmap; 211 212 return (pmap_extract(pmap, addr, NULL) == false); 213 } 214 215 /* 216 * Read bytes from kernel address space for debugger. 217 */ 218 void 219 db_read_bytes(vaddr_t addr, size_t size, char *data) 220 { 221 char *src = (char *)addr; 222 223 if (db_validate_address((u_int)src)) { 224 db_printf("address %p is invalid\n", src); 225 return; 226 } 227 228 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) { 229 *((int*)data) = *((int*)src); 230 return; 231 } 232 233 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) { 234 *((short*)data) = *((short*)src); 235 return; 236 } 237 238 while (size-- > 0) { 239 if (db_validate_address((u_int)src)) { 240 db_printf("address %p is invalid\n", src); 241 return; 242 } 243 *data++ = *src++; 244 } 245 } 246 247 static void 248 db_write_text(vaddr_t addr, size_t size, const char *data) 249 { 250 struct pmap *pmap = pmap_kernel(); 251 pd_entry_t *pde, oldpde, tmppde; 252 pt_entry_t *pte, oldpte, tmppte; 253 vaddr_t pgva; 254 size_t limit, savesize; 255 char *dst; 256 257 /* XXX: gcc */ 258 oldpte = 0; 259 260 if ((savesize = size) == 0) 261 return; 262 263 dst = (char *) addr; 264 265 do { 266 /* Get the PDE of the current VA. */ 267 if (pmap_get_pde_pte(pmap, (vaddr_t) dst, &pde, &pte) == false) 268 goto no_mapping; 269 switch ((oldpde = *pde) & L1_TYPE_MASK) { 270 case L1_TYPE_S: 271 pgva = (vaddr_t)dst & L1_S_FRAME; 272 limit = L1_S_SIZE - ((vaddr_t)dst & L1_S_OFFSET); 273 274 tmppde = l1pte_set_writable(oldpde); 275 *pde = tmppde; 276 PTE_SYNC(pde); 277 break; 278 279 case L1_TYPE_C: 280 pgva = (vaddr_t)dst & L2_S_FRAME; 281 limit = L2_S_SIZE - ((vaddr_t)dst & L2_S_OFFSET); 282 283 if (pte == NULL) 284 goto no_mapping; 285 oldpte = *pte; 286 tmppte = l2pte_set_writable(oldpte); 287 *pte = tmppte; 288 PTE_SYNC(pte); 289 break; 290 291 default: 292 no_mapping: 293 printf(" address 0x%08lx not a valid page\n", 294 (vaddr_t) dst); 295 return; 296 } 297 cpu_tlb_flushD_SE(pgva); 298 cpu_cpwait(); 299 300 if (limit > size) 301 limit = size; 302 size -= limit; 303 304 /* 305 * Page is now writable. Do as much access as we 306 * can in this page. 307 */ 308 for (; limit > 0; limit--) 309 *dst++ = *data++; 310 311 /* 312 * Restore old mapping permissions. 313 */ 314 switch (oldpde & L1_TYPE_MASK) { 315 case L1_TYPE_S: 316 *pde = oldpde; 317 PTE_SYNC(pde); 318 break; 319 320 case L1_TYPE_C: 321 *pte = oldpte; 322 PTE_SYNC(pte); 323 break; 324 } 325 cpu_tlb_flushD_SE(pgva); 326 cpu_cpwait(); 327 } while (size != 0); 328 329 /* Sync the I-cache. */ 330 cpu_icache_sync_range(addr, savesize); 331 } 332 333 /* 334 * Write bytes to kernel address space for debugger. 335 */ 336 void 337 db_write_bytes(vaddr_t addr, size_t size, const char *data) 338 { 339 extern char kernel_text[]; 340 extern char etext[]; 341 char *dst; 342 size_t loop; 343 344 /* If any part is in kernel text, use db_write_text() */ 345 if (addr >= (vaddr_t) kernel_text && addr < (vaddr_t) etext) { 346 db_write_text(addr, size, data); 347 return; 348 } 349 350 dst = (char *)addr; 351 if (db_validate_address((u_int)dst)) { 352 db_printf("address %p is invalid\n", dst); 353 return; 354 } 355 356 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) 357 *((int*)dst) = *((const int *)data); 358 else 359 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) 360 *((short*)dst) = *((const short *)data); 361 else { 362 loop = size; 363 while (loop-- > 0) { 364 if (db_validate_address((u_int)dst)) { 365 db_printf("address %p is invalid\n", dst); 366 return; 367 } 368 *dst++ = *data++; 369 } 370 } 371 372 /* make sure the caches and memory are in sync */ 373 cpu_icache_sync_range(addr, size); 374 375 /* In case the current page tables have been modified ... */ 376 cpu_tlb_flushID(); 377 cpu_cpwait(); 378 } 379 380 #ifdef DDB 381 void 382 cpu_Debugger(void) 383 { 384 __asm(".word 0xe7ffffff"); 385 } 386 387 int 388 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 389 { 390 391 if (fault_code == 0) { 392 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 393 kdb_trap(T_BREAKPOINT, frame); 394 else 395 kdb_trap(-1, frame); 396 } else 397 return 1; 398 return 0; 399 } 400 401 extern u_int esym; 402 extern u_int end; 403 404 static struct undefined_handler db_uh; 405 406 void 407 db_machine_init(void) 408 { 409 410 /* 411 * We get called before malloc() is available, so supply a static 412 * struct undefined_handler. 413 */ 414 db_uh.uh_handler = db_trapper; 415 install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &db_uh); 416 } 417 #endif 418 419 u_int 420 db_fetch_reg(int reg, db_regs_t *regs) 421 { 422 423 switch (reg) { 424 case 0: 425 return regs->tf_r0; 426 case 1: 427 return regs->tf_r1; 428 case 2: 429 return regs->tf_r2; 430 case 3: 431 return regs->tf_r3; 432 case 4: 433 return regs->tf_r4; 434 case 5: 435 return regs->tf_r5; 436 case 6: 437 return regs->tf_r6; 438 case 7: 439 return regs->tf_r7; 440 case 8: 441 return regs->tf_r8; 442 case 9: 443 return regs->tf_r9; 444 case 10: 445 return regs->tf_r10; 446 case 11: 447 return regs->tf_r11; 448 case 12: 449 return regs->tf_r12; 450 case 13: 451 return regs->tf_svc_sp; 452 case 14: 453 return regs->tf_svc_lr; 454 case 15: 455 return regs->tf_pc; 456 default: 457 panic("db_fetch_reg: botch"); 458 } 459 } 460 461 u_int 462 branch_taken(u_int insn, u_int pc, db_regs_t *regs) 463 { 464 u_int addr, nregs; 465 466 switch ((insn >> 24) & 0xf) { 467 case 0xa: /* b ... */ 468 case 0xb: /* bl ... */ 469 addr = ((insn << 2) & 0x03ffffff); 470 if (addr & 0x02000000) 471 addr |= 0xfc000000; 472 return pc + 8 + addr; 473 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 474 addr = db_fetch_reg(insn & 0xf, regs); 475 addr = pc + 8 + (addr << 2); 476 db_read_bytes(addr, 4, (char *)&addr); 477 return addr; 478 case 0x5: /* ldr pc, [reg] */ 479 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 480 db_read_bytes(addr, 4, (char *)&addr); 481 return addr; 482 case 0x1: /* mov pc, reg */ 483 addr = db_fetch_reg(insn & 0xf, regs); 484 return addr; 485 case 0x8: /* ldmxx reg, {..., pc} */ 486 case 0x9: 487 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 488 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 489 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 490 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 491 nregs = (nregs + (nregs >> 8)) & 0x001f; 492 switch ((insn >> 23) & 0x3) { 493 case 0x0: /* ldmda */ 494 addr = addr - 0; 495 break; 496 case 0x1: /* ldmia */ 497 addr = addr + 0 + ((nregs - 1) << 2); 498 break; 499 case 0x2: /* ldmdb */ 500 addr = addr - 4; 501 break; 502 case 0x3: /* ldmib */ 503 addr = addr + 4 + ((nregs - 1) << 2); 504 break; 505 } 506 db_read_bytes(addr, 4, (char *)&addr); 507 return addr; 508 default: 509 panic("branch_taken: botch"); 510 } 511 } 512
Indexes created Tue Sep 30 20:09:53 GMT 2025