db_machdep.c revision 1.24
1 /* $NetBSD: db_machdep.c,v 1.24 2017/04/25 09:02:34 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Mark Brinicombe 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #ifdef _KERNEL_OPT 32 #include "opt_multiprocessor.h" 33 #endif 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.24 2017/04/25 09:02:34 skrll Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/cpu.h> 40 #include <sys/proc.h> 41 #include <sys/vnode.h> 42 #include <sys/systm.h> 43 44 #include <arm/arm32/db_machdep.h> 45 #include <arm/cpufunc.h> 46 47 #include <ddb/db_access.h> 48 #include <ddb/db_sym.h> 49 #include <ddb/db_output.h> 50 #include <ddb/db_variables.h> 51 #include <ddb/db_command.h> 52 #include <ddb/db_run.h> 53 54 #ifndef _KERNEL 55 #include <stddef.h> 56 #endif 57 58 #ifdef _KERNEL 59 static long nil; 60 61 int db_access_und_sp(const struct db_variable *, db_expr_t *, int); 62 int db_access_abt_sp(const struct db_variable *, db_expr_t *, int); 63 int db_access_irq_sp(const struct db_variable *, db_expr_t *, int); 64 #endif 65 66 static int 67 ddb_reg_var(const struct db_variable *v, db_expr_t *ep, int op) 68 { 69 register_t * const rp = (register_t *)DDB_REGS; 70 if (op == DB_VAR_SET) { 71 rp[(uintptr_t)v->valuep] = *ep; 72 } else { 73 *ep = rp[(uintptr_t)v->valuep]; 74 } 75 return 0; 76 } 77 78 79 #define XO(f) ((long *)(offsetof(db_regs_t, f) / sizeof(register_t))) 80 const struct db_variable db_regs[] = { 81 { "spsr", XO(tf_spsr), ddb_reg_var, NULL }, 82 { "r0", XO(tf_r0), ddb_reg_var, NULL }, 83 { "r1", XO(tf_r1), ddb_reg_var, NULL }, 84 { "r2", XO(tf_r2), ddb_reg_var, NULL }, 85 { "r3", XO(tf_r3), ddb_reg_var, NULL }, 86 { "r4", XO(tf_r4), ddb_reg_var, NULL }, 87 { "r5", XO(tf_r5), ddb_reg_var, NULL }, 88 { "r6", XO(tf_r6), ddb_reg_var, NULL }, 89 { "r7", XO(tf_r7), ddb_reg_var, NULL }, 90 { "r8", XO(tf_r8), ddb_reg_var, NULL }, 91 { "r9", XO(tf_r9), ddb_reg_var, NULL }, 92 { "r10", XO(tf_r10), ddb_reg_var, NULL }, 93 { "r11", XO(tf_r11), ddb_reg_var, NULL }, 94 { "r12", XO(tf_r12), ddb_reg_var, NULL }, 95 { "usr_sp", XO(tf_usr_sp), ddb_reg_var, NULL }, 96 { "usr_lr", XO(tf_usr_lr), ddb_reg_var, NULL }, 97 { "svc_sp", XO(tf_svc_sp), ddb_reg_var, NULL }, 98 { "svc_lr", XO(tf_svc_lr), ddb_reg_var, NULL }, 99 { "pc", XO(tf_pc), ddb_reg_var, NULL }, 100 #ifdef _KERNEL 101 { "und_sp", &nil, db_access_und_sp, NULL }, 102 { "abt_sp", &nil, db_access_abt_sp, NULL }, 103 { "irq_sp", &nil, db_access_irq_sp, NULL }, 104 #endif 105 }; 106 #undef XO 107 108 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 109 110 const struct db_command db_machine_command_table[] = { 111 { DDB_ADD_CMD("frame", db_show_frame_cmd, 0, 112 "Displays the contents of a trapframe", 113 "[address]", 114 " address:\taddress of trapfame to display")}, 115 #ifdef _KERNEL 116 { DDB_ADD_CMD("fault", db_show_fault_cmd, 0, 117 "Displays the fault registers", 118 NULL,NULL) }, 119 #endif 120 #if defined(_KERNEL) && (defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7)) 121 { DDB_ADD_CMD("tlb", db_show_tlb_cmd, 0, 122 "Displays the TLB", 123 NULL,NULL) }, 124 #endif 125 #if defined(_KERNEL) && defined(MULTIPROCESSOR) 126 { DDB_ADD_CMD("cpu", db_switch_cpu_cmd, 0, 127 "switch to a different cpu", 128 NULL,NULL) }, 129 #endif 130 131 #ifdef ARM32_DB_COMMANDS 132 ARM32_DB_COMMANDS, 133 #endif 134 { DDB_ADD_CMD(NULL, NULL, 0,NULL,NULL,NULL) } 135 }; 136 137 #ifdef _KERNEL 138 int 139 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 140 { 141 142 if (rw == DB_VAR_GET) 143 *valp = get_stackptr(PSR_UND32_MODE); 144 return(0); 145 } 146 147 int 148 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 149 { 150 151 if (rw == DB_VAR_GET) 152 *valp = get_stackptr(PSR_ABT32_MODE); 153 return(0); 154 } 155 156 int 157 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 158 { 159 160 if (rw == DB_VAR_GET) 161 *valp = get_stackptr(PSR_IRQ32_MODE); 162 return(0); 163 } 164 165 void 166 db_show_fault_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 167 { 168 db_printf("DFAR=%#x DFSR=%#x IFAR=%#x IFSR=%#x\n", 169 armreg_dfar_read(), armreg_dfsr_read(), 170 armreg_ifar_read(), armreg_ifsr_read()); 171 db_printf("CONTEXTIDR=%#x TTBCR=%#x TTBR=%#x\n", 172 armreg_contextidr_read(), armreg_ttbcr_read(), 173 armreg_ttbr_read()); 174 } 175 176 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) 177 static void 178 tlb_print_common_header(const char *str) 179 { 180 db_printf("-W/I-- ----VA---- ----PA---- --SIZE-- D AP XN ASD %s\n", str); 181 } 182 183 static void 184 tlb_print_addr(size_t way, size_t va_index, vaddr_t vpn, paddr_t pfn) 185 { 186 db_printf("[%1zu:%02zx] 0x%05lx000 0x%05lx000", way, va_index, vpn, pfn); 187 } 188 189 static void 190 tlb_print_size_domain_prot(const char *sizestr, u_int domain, u_int ap, 191 bool xn_p) 192 { 193 db_printf(" %8s %1x %2d %s", sizestr, domain, ap, (xn_p ? "XN" : "--")); 194 } 195 196 static void 197 tlb_print_asid(bool ng_p, tlb_asid_t asid) 198 { 199 if (ng_p) { 200 db_printf(" %3d", asid); 201 } else { 202 db_printf(" ---"); 203 } 204 } 205 206 struct db_tlbinfo { 207 vaddr_t (*dti_decode_vpn)(size_t, uint32_t, uint32_t); 208 void (*dti_print_header)(void); 209 void (*dti_print_entry)(size_t, size_t, uint32_t, uint32_t); 210 u_int dti_index; 211 }; 212 213 #if defined(CPU_CORTEXA5) 214 static void 215 tlb_print_cortex_a5_header(void) 216 { 217 tlb_print_common_header(" S TEX C B"); 218 } 219 220 static vaddr_t 221 tlb_decode_cortex_a5_vpn(size_t va_index, uint32_t d0, uint32_t d1) 222 { 223 const uint64_t d = ((uint64_t)d1 << 32) | d0; 224 225 const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE); 226 return __SHIFTOUT(d, ARM_A5_TLBDATA_VA) * (ARM_A5_TLBDATAOP_INDEX + 1) 227 + (va_index << (4*size)); 228 } 229 230 static void 231 tlb_print_cortex_a5_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1) 232 { 233 static const char size_strings[4][8] = { 234 " 4KB ", " 64KB ", " 1MB ", " 16MB ", 235 }; 236 237 const uint64_t d = ((uint64_t)d1 << 32) | d0; 238 239 const paddr_t pfn = __SHIFTOUT(d, ARM_A5_TLBDATA_PA); 240 const vaddr_t vpn = tlb_decode_cortex_a5_vpn(va_index, d0, d1); 241 242 tlb_print_addr(way, va_index, vpn, pfn); 243 244 const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE); 245 const u_int domain = __SHIFTOUT(d, ARM_A5_TLBDATA_DOM); 246 const u_int ap = __SHIFTOUT(d, ARM_A5_TLBDATA_AP); 247 const bool xn_p = (d & ARM_A5_TLBDATA_XN) != 0; 248 249 tlb_print_size_domain_prot(size_strings[size], domain, ap, xn_p); 250 251 const bool ng_p = (d & ARM_A5_TLBDATA_nG) != 0; 252 const tlb_asid_t asid = __SHIFTOUT(d, ARM_A5_TLBDATA_ASID); 253 254 tlb_print_asid(ng_p, asid); 255 256 const u_int tex = __SHIFTOUT(d, ARM_A5_TLBDATA_TEX); 257 const bool c_p = (d & ARM_A5_TLBDATA_C) != 0; 258 const bool b_p = (d & ARM_A5_TLBDATA_B) != 0; 259 const bool s_p = (d & ARM_A5_TLBDATA_S) != 0; 260 261 db_printf(" %c %d %c %c\n", (s_p ? 'S' : '-'), tex, 262 (c_p ? 'C' : '-'), (b_p ? 'B' : '-')); 263 } 264 265 static const struct db_tlbinfo tlb_cortex_a5_info = { 266 .dti_decode_vpn = tlb_decode_cortex_a5_vpn, 267 .dti_print_header = tlb_print_cortex_a5_header, 268 .dti_print_entry = tlb_print_cortex_a5_entry, 269 .dti_index = ARM_A5_TLBDATAOP_INDEX, 270 }; 271 #endif /* CPU_CORTEXA5 */ 272 273 #if defined(CPU_CORTEXA7) 274 static const char tlb_cortex_a7_esizes[8][8] = { 275 " 4KB(S)", " 4KB(L)", "64KB(S)", "64KB(L)", 276 " 1MB(S)", " 2MB(L)", "16MB(S)", " 1GB(L)", 277 }; 278 279 static void 280 tlb_print_cortex_a7_header(void) 281 { 282 tlb_print_common_header("IS --OS- SH"); 283 } 284 285 static inline vaddr_t 286 tlb_decode_cortex_a7_vpn(size_t va_index, uint32_t d0, uint32_t d1) 287 { 288 const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE); 289 const u_int shift = (size & 1) 290 ? ((0x12090400 >> (8*size)) & 0x1f) 291 : (2 * size); 292 293 return __SHIFTOUT(d0, ARM_A7_TLBDATA0_VA) * (ARM_A7_TLBDATAOP_INDEX + 1) 294 + (va_index << shift); 295 } 296 297 static void 298 tlb_print_cortex_a7_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1) 299 { 300 const uint32_t d2 = armreg_tlbdata2_read(); 301 const uint64_t d01 = ((uint64_t)d1 << 32) | d0; 302 const uint64_t d12 = ((uint64_t)d2 << 32) | d1; 303 304 const paddr_t pfn = __SHIFTOUT(d12, ARM_A7_TLBDATA12_PA); 305 const vaddr_t vpn = tlb_decode_cortex_a7_vpn(va_index, d0, d1); 306 307 tlb_print_addr(way, va_index, vpn, pfn); 308 309 const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE); 310 const u_int domain = __SHIFTOUT(d2, ARM_A7_TLBDATA2_DOM); 311 const u_int ap = __SHIFTOUT(d1, ARM_A7_TLBDATA1_AP); 312 const bool xn_p = (d2 & ARM_A7_TLBDATA2_XN1) != 0; 313 314 tlb_print_size_domain_prot(tlb_cortex_a7_esizes[size], domain, ap, xn_p); 315 316 const bool ng_p = (d1 & ARM_A7_TLBDATA1_nG) != 0; 317 const tlb_asid_t asid = __SHIFTOUT(d01, ARM_A7_TLBDATA01_ASID); 318 319 tlb_print_asid(ng_p, asid); 320 321 const u_int is = __SHIFTOUT(d2, ARM_A7_TLBDATA2_IS); 322 if (is == ARM_A7_TLBDATA2_IS_DSO) { 323 u_int mt = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SDO_MT); 324 switch (mt) { 325 case ARM_A7_TLBDATA2_SDO_MT_D: 326 db_printf(" DV\n"); 327 return; 328 case ARM_A7_TLBDATA2_SDO_MT_SO: 329 db_printf(" SO\n"); 330 return; 331 default: 332 db_printf(" %02u\n", mt); 333 return; 334 } 335 } 336 const u_int os = __SHIFTOUT(d2, ARM_A7_TLBDATA2_OS); 337 const u_int sh = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SH); 338 static const char is_types[3][3] = { "NC", "WB", "WT" }; 339 static const char os_types[4][6] = { "NC", "WB+WA", "WT", "WB" }; 340 static const char sh_types[4][3] = { "NS", "na", "OS", "IS" }; 341 db_printf(" %2s %5s %2s\n", is_types[is], os_types[os], sh_types[sh]); 342 } 343 344 static const struct db_tlbinfo tlb_cortex_a7_info = { 345 .dti_decode_vpn = tlb_decode_cortex_a7_vpn, 346 .dti_print_header = tlb_print_cortex_a7_header, 347 .dti_print_entry = tlb_print_cortex_a7_entry, 348 .dti_index = ARM_A7_TLBDATAOP_INDEX, 349 }; 350 #endif /* CPU_CORTEXA7 */ 351 352 static inline const struct db_tlbinfo * 353 tlb_lookup_tlbinfo(void) 354 { 355 #if defined(CPU_CORTEXA5) && defined(CPU_CORTEXA7) 356 const bool cortex_a5_p = CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid); 357 const bool cortex_a7_p = CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid); 358 #elif defined(CPU_CORTEXA5) 359 const bool cortex_a5_p = true; 360 #else 361 const bool cortex_a7_p = true; 362 #endif 363 #ifdef CPU_CORTEXA5 364 if (cortex_a5_p) { 365 return &tlb_cortex_a5_info; 366 } 367 #endif 368 #ifdef CPU_CORTEXA7 369 if (cortex_a7_p) { 370 return &tlb_cortex_a7_info; 371 } 372 #endif 373 return NULL; 374 } 375 376 void 377 db_show_tlb_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 378 { 379 const struct db_tlbinfo * const dti = tlb_lookup_tlbinfo(); 380 381 if (have_addr) { 382 const vaddr_t vpn = (vaddr_t)addr >> L2_S_SHIFT; 383 const u_int va_index = vpn & dti->dti_index; 384 for (size_t way = 0; way < 2; way++) { 385 armreg_tlbdataop_write( 386 __SHIFTIN(va_index, dti->dti_index) 387 | __SHIFTIN(way, ARM_TLBDATAOP_WAY)); 388 arm_isb(); 389 const uint32_t d0 = armreg_tlbdata0_read(); 390 const uint32_t d1 = armreg_tlbdata1_read(); 391 if ((d0 & ARM_TLBDATA_VALID) 392 && vpn == (*dti->dti_decode_vpn)(va_index, d0, d1)) { 393 (*dti->dti_print_header)(); 394 (*dti->dti_print_entry)(way, va_index, d0, d1); 395 return; 396 } 397 } 398 db_printf("VA %#"DDB_EXPR_FMT"x not found in TLB\n", addr); 399 return; 400 } 401 402 bool first = true; 403 size_t n = 0; 404 for (size_t va_index = 0; va_index <= dti->dti_index; va_index++) { 405 for (size_t way = 0; way < 2; way++) { 406 armreg_tlbdataop_write( 407 __SHIFTIN(way, ARM_TLBDATAOP_WAY) 408 | __SHIFTIN(va_index, dti->dti_index)); 409 arm_isb(); 410 const uint32_t d0 = armreg_tlbdata0_read(); 411 const uint32_t d1 = armreg_tlbdata1_read(); 412 if (d0 & ARM_TLBDATA_VALID) { 413 if (first) { 414 (*dti->dti_print_header)(); 415 first = false; 416 } 417 (*dti->dti_print_entry)(way, va_index, d0, d1); 418 n++; 419 } 420 } 421 } 422 db_printf("%zu TLB valid entries found\n", n); 423 } 424 #endif /* CPU_CORTEXA5 || CPU_CORTEXA7 */ 425 #endif /* _KERNEL */ 426 427 428 void 429 db_show_frame_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 430 { 431 struct trapframe *frame; 432 433 if (!have_addr) { 434 db_printf("frame address must be specified\n"); 435 return; 436 } 437 438 frame = (struct trapframe *)addr; 439 440 db_printf("frame address = %08x ", (u_int)frame); 441 db_printf("spsr=%08x\n", frame->tf_spsr); 442 db_printf("r0 =%08x r1 =%08x r2 =%08x r3 =%08x\n", 443 frame->tf_r0, frame->tf_r1, frame->tf_r2, frame->tf_r3); 444 db_printf("r4 =%08x r5 =%08x r6 =%08x r7 =%08x\n", 445 frame->tf_r4, frame->tf_r5, frame->tf_r6, frame->tf_r7); 446 db_printf("r8 =%08x r9 =%08x r10=%08x r11=%08x\n", 447 frame->tf_r8, frame->tf_r9, frame->tf_r10, frame->tf_r11); 448 db_printf("r12=%08x r13=%08x r14=%08x r15=%08x\n", 449 frame->tf_r12, frame->tf_usr_sp, frame->tf_usr_lr, frame->tf_pc); 450 db_printf("slr=%08x ssp=%08x\n", frame->tf_svc_lr, frame->tf_svc_sp); 451 } 452 453 #if defined(_KERNEL) && defined(MULTIPROCESSOR) 454 void 455 db_switch_cpu_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 456 { 457 if (addr >= maxcpus) { 458 db_printf("cpu %"DDB_EXPR_FMT"d out of range", addr); 459 return; 460 } 461 struct cpu_info *new_ci = cpu_lookup(addr); 462 if (new_ci == NULL) { 463 db_printf("cpu %"DDB_EXPR_FMT"d does not exist", addr); 464 return; 465 } 466 if (DDB_REGS->tf_spsr & PSR_T_bit) { 467 DDB_REGS->tf_pc -= 2; /* XXX */ 468 } else { 469 DDB_REGS->tf_pc -= 4; 470 } 471 db_newcpu = new_ci; 472 db_continue_cmd(0, false, 0, ""); 473 } 474 #endif 475
Indexes created Fri Sep 26 20:09:58 GMT 2025