db_machdep.c revision 1.24.12.1
1 /* $NetBSD: db_machdep.c,v 1.24.12.1 2019/06/10 22:05:51 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Mark Brinicombe 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #ifdef _KERNEL_OPT 32 #include "opt_cputypes.h" 33 #include "opt_multiprocessor.h" 34 #endif 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.24.12.1 2019/06/10 22:05:51 christos Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/cpu.h> 41 #include <sys/proc.h> 42 #include <sys/vnode.h> 43 #include <sys/systm.h> 44 45 #include <arm/arm32/db_machdep.h> 46 #include <arm/cpufunc.h> 47 48 #include <ddb/db_access.h> 49 #include <ddb/db_sym.h> 50 #include <ddb/db_output.h> 51 #include <ddb/db_variables.h> 52 #include <ddb/db_command.h> 53 #include <ddb/db_run.h> 54 55 #ifndef _KERNEL 56 #include <stddef.h> 57 #endif 58 59 #ifdef _KERNEL 60 static long nil; 61 62 int db_access_und_sp(const struct db_variable *, db_expr_t *, int); 63 int db_access_abt_sp(const struct db_variable *, db_expr_t *, int); 64 int db_access_irq_sp(const struct db_variable *, db_expr_t *, int); 65 #endif 66 67 static int 68 ddb_reg_var(const struct db_variable *v, db_expr_t *ep, int op) 69 { 70 register_t * const rp = (register_t *)DDB_REGS; 71 if (op == DB_VAR_SET) { 72 rp[(uintptr_t)v->valuep] = *ep; 73 } else { 74 *ep = rp[(uintptr_t)v->valuep]; 75 } 76 return 0; 77 } 78 79 80 #define XO(f) ((long *)(offsetof(db_regs_t, f) / sizeof(register_t))) 81 const struct db_variable db_regs[] = { 82 { "spsr", XO(tf_spsr), ddb_reg_var, NULL }, 83 { "r0", XO(tf_r0), ddb_reg_var, NULL }, 84 { "r1", XO(tf_r1), ddb_reg_var, NULL }, 85 { "r2", XO(tf_r2), ddb_reg_var, NULL }, 86 { "r3", XO(tf_r3), ddb_reg_var, NULL }, 87 { "r4", XO(tf_r4), ddb_reg_var, NULL }, 88 { "r5", XO(tf_r5), ddb_reg_var, NULL }, 89 { "r6", XO(tf_r6), ddb_reg_var, NULL }, 90 { "r7", XO(tf_r7), ddb_reg_var, NULL }, 91 { "r8", XO(tf_r8), ddb_reg_var, NULL }, 92 { "r9", XO(tf_r9), ddb_reg_var, NULL }, 93 { "r10", XO(tf_r10), ddb_reg_var, NULL }, 94 { "r11", XO(tf_r11), ddb_reg_var, NULL }, 95 { "r12", XO(tf_r12), ddb_reg_var, NULL }, 96 { "usr_sp", XO(tf_usr_sp), ddb_reg_var, NULL }, 97 { "usr_lr", XO(tf_usr_lr), ddb_reg_var, NULL }, 98 { "svc_sp", XO(tf_svc_sp), ddb_reg_var, NULL }, 99 { "svc_lr", XO(tf_svc_lr), ddb_reg_var, NULL }, 100 { "pc", XO(tf_pc), ddb_reg_var, NULL }, 101 #ifdef _KERNEL 102 { "und_sp", &nil, db_access_und_sp, NULL }, 103 { "abt_sp", &nil, db_access_abt_sp, NULL }, 104 { "irq_sp", &nil, db_access_irq_sp, NULL }, 105 #endif 106 }; 107 #undef XO 108 109 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 110 111 const struct db_command db_machine_command_table[] = { 112 { DDB_ADD_CMD("frame", db_show_frame_cmd, 0, 113 "Displays the contents of a trapframe", 114 "[address]", 115 " address:\taddress of trapfame to display")}, 116 #ifdef _KERNEL 117 { DDB_ADD_CMD("fault", db_show_fault_cmd, 0, 118 "Displays the fault registers", 119 NULL,NULL) }, 120 #endif 121 #if defined(_KERNEL) && (defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7)) 122 { DDB_ADD_CMD("tlb", db_show_tlb_cmd, 0, 123 "Displays the TLB", 124 NULL,NULL) }, 125 #endif 126 #if defined(_KERNEL) && defined(MULTIPROCESSOR) 127 { DDB_ADD_CMD("cpu", db_switch_cpu_cmd, 0, 128 "switch to a different cpu", 129 NULL,NULL) }, 130 #endif 131 132 #ifdef ARM32_DB_COMMANDS 133 ARM32_DB_COMMANDS, 134 #endif 135 { DDB_ADD_CMD(NULL, NULL, 0,NULL,NULL,NULL) } 136 }; 137 138 #ifdef _KERNEL 139 int 140 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 141 { 142 143 if (rw == DB_VAR_GET) 144 *valp = get_stackptr(PSR_UND32_MODE); 145 return(0); 146 } 147 148 int 149 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 150 { 151 152 if (rw == DB_VAR_GET) 153 *valp = get_stackptr(PSR_ABT32_MODE); 154 return(0); 155 } 156 157 int 158 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 159 { 160 161 if (rw == DB_VAR_GET) 162 *valp = get_stackptr(PSR_IRQ32_MODE); 163 return(0); 164 } 165 166 void 167 db_show_fault_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 168 { 169 db_printf("DFAR=%#x DFSR=%#x IFAR=%#x IFSR=%#x\n", 170 armreg_dfar_read(), armreg_dfsr_read(), 171 armreg_ifar_read(), armreg_ifsr_read()); 172 db_printf("CONTEXTIDR=%#x TTBCR=%#x TTBR=%#x\n", 173 armreg_contextidr_read(), armreg_ttbcr_read(), 174 armreg_ttbr_read()); 175 } 176 177 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) 178 static void 179 tlb_print_common_header(const char *str) 180 { 181 db_printf("-W/I-- ----VA---- ----PA---- --SIZE-- D AP XN ASD %s\n", str); 182 } 183 184 static void 185 tlb_print_addr(size_t way, size_t va_index, vaddr_t vpn, paddr_t pfn) 186 { 187 db_printf("[%1zu:%02zx] 0x%05lx000 0x%05lx000", way, va_index, vpn, pfn); 188 } 189 190 static void 191 tlb_print_size_domain_prot(const char *sizestr, u_int domain, u_int ap, 192 bool xn_p) 193 { 194 db_printf(" %8s %1x %2d %s", sizestr, domain, ap, (xn_p ? "XN" : "--")); 195 } 196 197 static void 198 tlb_print_asid(bool ng_p, tlb_asid_t asid) 199 { 200 if (ng_p) { 201 db_printf(" %3d", asid); 202 } else { 203 db_printf(" ---"); 204 } 205 } 206 207 struct db_tlbinfo { 208 vaddr_t (*dti_decode_vpn)(size_t, uint32_t, uint32_t); 209 void (*dti_print_header)(void); 210 void (*dti_print_entry)(size_t, size_t, uint32_t, uint32_t); 211 u_int dti_index; 212 }; 213 214 #if defined(CPU_CORTEXA5) 215 static void 216 tlb_print_cortex_a5_header(void) 217 { 218 tlb_print_common_header(" S TEX C B"); 219 } 220 221 static vaddr_t 222 tlb_decode_cortex_a5_vpn(size_t va_index, uint32_t d0, uint32_t d1) 223 { 224 const uint64_t d = ((uint64_t)d1 << 32) | d0; 225 226 const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE); 227 return __SHIFTOUT(d, ARM_A5_TLBDATA_VA) * (ARM_A5_TLBDATAOP_INDEX + 1) 228 + (va_index << (4*size)); 229 } 230 231 static void 232 tlb_print_cortex_a5_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1) 233 { 234 static const char size_strings[4][8] = { 235 " 4KB ", " 64KB ", " 1MB ", " 16MB ", 236 }; 237 238 const uint64_t d = ((uint64_t)d1 << 32) | d0; 239 240 const paddr_t pfn = __SHIFTOUT(d, ARM_A5_TLBDATA_PA); 241 const vaddr_t vpn = tlb_decode_cortex_a5_vpn(va_index, d0, d1); 242 243 tlb_print_addr(way, va_index, vpn, pfn); 244 245 const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE); 246 const u_int domain = __SHIFTOUT(d, ARM_A5_TLBDATA_DOM); 247 const u_int ap = __SHIFTOUT(d, ARM_A5_TLBDATA_AP); 248 const bool xn_p = (d & ARM_A5_TLBDATA_XN) != 0; 249 250 tlb_print_size_domain_prot(size_strings[size], domain, ap, xn_p); 251 252 const bool ng_p = (d & ARM_A5_TLBDATA_nG) != 0; 253 const tlb_asid_t asid = __SHIFTOUT(d, ARM_A5_TLBDATA_ASID); 254 255 tlb_print_asid(ng_p, asid); 256 257 const u_int tex = __SHIFTOUT(d, ARM_A5_TLBDATA_TEX); 258 const bool c_p = (d & ARM_A5_TLBDATA_C) != 0; 259 const bool b_p = (d & ARM_A5_TLBDATA_B) != 0; 260 const bool s_p = (d & ARM_A5_TLBDATA_S) != 0; 261 262 db_printf(" %c %d %c %c\n", (s_p ? 'S' : '-'), tex, 263 (c_p ? 'C' : '-'), (b_p ? 'B' : '-')); 264 } 265 266 static const struct db_tlbinfo tlb_cortex_a5_info = { 267 .dti_decode_vpn = tlb_decode_cortex_a5_vpn, 268 .dti_print_header = tlb_print_cortex_a5_header, 269 .dti_print_entry = tlb_print_cortex_a5_entry, 270 .dti_index = ARM_A5_TLBDATAOP_INDEX, 271 }; 272 #endif /* CPU_CORTEXA5 */ 273 274 #if defined(CPU_CORTEXA7) 275 static const char tlb_cortex_a7_esizes[8][8] = { 276 " 4KB(S)", " 4KB(L)", "64KB(S)", "64KB(L)", 277 " 1MB(S)", " 2MB(L)", "16MB(S)", " 1GB(L)", 278 }; 279 280 static void 281 tlb_print_cortex_a7_header(void) 282 { 283 tlb_print_common_header("IS --OS- SH"); 284 } 285 286 static inline vaddr_t 287 tlb_decode_cortex_a7_vpn(size_t va_index, uint32_t d0, uint32_t d1) 288 { 289 const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE); 290 const u_int shift = (size & 1) 291 ? ((0x12090400 >> (8*size)) & 0x1f) 292 : (2 * size); 293 294 return __SHIFTOUT(d0, ARM_A7_TLBDATA0_VA) * (ARM_A7_TLBDATAOP_INDEX + 1) 295 + (va_index << shift); 296 } 297 298 static void 299 tlb_print_cortex_a7_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1) 300 { 301 const uint32_t d2 = armreg_tlbdata2_read(); 302 const uint64_t d01 = ((uint64_t)d1 << 32) | d0; 303 const uint64_t d12 = ((uint64_t)d2 << 32) | d1; 304 305 const paddr_t pfn = __SHIFTOUT(d12, ARM_A7_TLBDATA12_PA); 306 const vaddr_t vpn = tlb_decode_cortex_a7_vpn(va_index, d0, d1); 307 308 tlb_print_addr(way, va_index, vpn, pfn); 309 310 const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE); 311 const u_int domain = __SHIFTOUT(d2, ARM_A7_TLBDATA2_DOM); 312 const u_int ap = __SHIFTOUT(d1, ARM_A7_TLBDATA1_AP); 313 const bool xn_p = (d2 & ARM_A7_TLBDATA2_XN1) != 0; 314 315 tlb_print_size_domain_prot(tlb_cortex_a7_esizes[size], domain, ap, xn_p); 316 317 const bool ng_p = (d1 & ARM_A7_TLBDATA1_nG) != 0; 318 const tlb_asid_t asid = __SHIFTOUT(d01, ARM_A7_TLBDATA01_ASID); 319 320 tlb_print_asid(ng_p, asid); 321 322 const u_int is = __SHIFTOUT(d2, ARM_A7_TLBDATA2_IS); 323 if (is == ARM_A7_TLBDATA2_IS_DSO) { 324 u_int mt = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SDO_MT); 325 switch (mt) { 326 case ARM_A7_TLBDATA2_SDO_MT_D: 327 db_printf(" DV\n"); 328 return; 329 case ARM_A7_TLBDATA2_SDO_MT_SO: 330 db_printf(" SO\n"); 331 return; 332 default: 333 db_printf(" %02u\n", mt); 334 return; 335 } 336 } 337 const u_int os = __SHIFTOUT(d2, ARM_A7_TLBDATA2_OS); 338 const u_int sh = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SH); 339 static const char is_types[3][3] = { "NC", "WB", "WT" }; 340 static const char os_types[4][6] = { "NC", "WB+WA", "WT", "WB" }; 341 static const char sh_types[4][3] = { "NS", "na", "OS", "IS" }; 342 db_printf(" %2s %5s %2s\n", is_types[is], os_types[os], sh_types[sh]); 343 } 344 345 static const struct db_tlbinfo tlb_cortex_a7_info = { 346 .dti_decode_vpn = tlb_decode_cortex_a7_vpn, 347 .dti_print_header = tlb_print_cortex_a7_header, 348 .dti_print_entry = tlb_print_cortex_a7_entry, 349 .dti_index = ARM_A7_TLBDATAOP_INDEX, 350 }; 351 #endif /* CPU_CORTEXA7 */ 352 353 static inline const struct db_tlbinfo * 354 tlb_lookup_tlbinfo(void) 355 { 356 #if defined(CPU_CORTEXA5) && defined(CPU_CORTEXA7) 357 const bool cortex_a5_p = CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid); 358 const bool cortex_a7_p = CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid); 359 #elif defined(CPU_CORTEXA5) 360 const bool cortex_a5_p = true; 361 #else 362 const bool cortex_a7_p = true; 363 #endif 364 #ifdef CPU_CORTEXA5 365 if (cortex_a5_p) { 366 return &tlb_cortex_a5_info; 367 } 368 #endif 369 #ifdef CPU_CORTEXA7 370 if (cortex_a7_p) { 371 return &tlb_cortex_a7_info; 372 } 373 #endif 374 return NULL; 375 } 376 377 void 378 db_show_tlb_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 379 { 380 const struct db_tlbinfo * const dti = tlb_lookup_tlbinfo(); 381 382 if (have_addr) { 383 const vaddr_t vpn = (vaddr_t)addr >> L2_S_SHIFT; 384 const u_int va_index = vpn & dti->dti_index; 385 for (size_t way = 0; way < 2; way++) { 386 armreg_tlbdataop_write( 387 __SHIFTIN(va_index, dti->dti_index) 388 | __SHIFTIN(way, ARM_TLBDATAOP_WAY)); 389 arm_isb(); 390 const uint32_t d0 = armreg_tlbdata0_read(); 391 const uint32_t d1 = armreg_tlbdata1_read(); 392 if ((d0 & ARM_TLBDATA_VALID) 393 && vpn == (*dti->dti_decode_vpn)(va_index, d0, d1)) { 394 (*dti->dti_print_header)(); 395 (*dti->dti_print_entry)(way, va_index, d0, d1); 396 return; 397 } 398 } 399 db_printf("VA %#"DDB_EXPR_FMT"x not found in TLB\n", addr); 400 return; 401 } 402 403 bool first = true; 404 size_t n = 0; 405 for (size_t va_index = 0; va_index <= dti->dti_index; va_index++) { 406 for (size_t way = 0; way < 2; way++) { 407 armreg_tlbdataop_write( 408 __SHIFTIN(way, ARM_TLBDATAOP_WAY) 409 | __SHIFTIN(va_index, dti->dti_index)); 410 arm_isb(); 411 const uint32_t d0 = armreg_tlbdata0_read(); 412 const uint32_t d1 = armreg_tlbdata1_read(); 413 if (d0 & ARM_TLBDATA_VALID) { 414 if (first) { 415 (*dti->dti_print_header)(); 416 first = false; 417 } 418 (*dti->dti_print_entry)(way, va_index, d0, d1); 419 n++; 420 } 421 } 422 } 423 db_printf("%zu TLB valid entries found\n", n); 424 } 425 #endif /* CPU_CORTEXA5 || CPU_CORTEXA7 */ 426 #endif /* _KERNEL */ 427 428 429 void 430 db_show_frame_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 431 { 432 struct trapframe *frame; 433 434 if (!have_addr) { 435 db_printf("frame address must be specified\n"); 436 return; 437 } 438 439 frame = (struct trapframe *)addr; 440 441 db_printf("frame address = %08x ", (u_int)frame); 442 db_printf("spsr=%08x\n", frame->tf_spsr); 443 db_printf("r0 =%08x r1 =%08x r2 =%08x r3 =%08x\n", 444 frame->tf_r0, frame->tf_r1, frame->tf_r2, frame->tf_r3); 445 db_printf("r4 =%08x r5 =%08x r6 =%08x r7 =%08x\n", 446 frame->tf_r4, frame->tf_r5, frame->tf_r6, frame->tf_r7); 447 db_printf("r8 =%08x r9 =%08x r10=%08x r11=%08x\n", 448 frame->tf_r8, frame->tf_r9, frame->tf_r10, frame->tf_r11); 449 db_printf("r12=%08x r13=%08x r14=%08x r15=%08x\n", 450 frame->tf_r12, frame->tf_usr_sp, frame->tf_usr_lr, frame->tf_pc); 451 db_printf("slr=%08x ssp=%08x\n", frame->tf_svc_lr, frame->tf_svc_sp); 452 } 453 454 #if defined(_KERNEL) && defined(MULTIPROCESSOR) 455 void 456 db_switch_cpu_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 457 { 458 if (addr >= maxcpus) { 459 db_printf("cpu %"DDB_EXPR_FMT"d out of range", addr); 460 return; 461 } 462 struct cpu_info *new_ci = cpu_lookup(addr); 463 if (new_ci == NULL) { 464 db_printf("cpu %"DDB_EXPR_FMT"d does not exist", addr); 465 return; 466 } 467 if (DDB_REGS->tf_spsr & PSR_T_bit) { 468 DDB_REGS->tf_pc -= 2; /* XXX */ 469 } else { 470 DDB_REGS->tf_pc -= 4; 471 } 472 db_newcpu = new_ci; 473 db_continue_cmd(0, false, 0, ""); 474 } 475 #endif 476
Indexes created Tue Oct 21 06:10:07 GMT 2025