db_machdep.c revision 1.24.12.2
1 /* $NetBSD: db_machdep.c,v 1.24.12.2 2020/04/08 14:07:28 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Mark Brinicombe 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #ifdef _KERNEL_OPT 32 #include "opt_cputypes.h" 33 #include "opt_multiprocessor.h" 34 #endif 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.24.12.2 2020/04/08 14:07:28 martin Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/cpu.h> 41 #include <sys/proc.h> 42 #include <sys/vnode.h> 43 #include <sys/systm.h> 44 45 #include <arm/arm32/db_machdep.h> 46 #include <arm/cpufunc.h> 47 48 #include <ddb/db_access.h> 49 #include <ddb/db_sym.h> 50 #include <ddb/db_output.h> 51 #include <ddb/db_variables.h> 52 #include <ddb/db_command.h> 53 #include <ddb/db_run.h> 54 55 #ifndef _KERNEL 56 #include <stddef.h> 57 #endif 58 59 #ifdef _KERNEL 60 static long nil; 61 62 int db_access_und_sp(const struct db_variable *, db_expr_t *, int); 63 int db_access_abt_sp(const struct db_variable *, db_expr_t *, int); 64 int db_access_irq_sp(const struct db_variable *, db_expr_t *, int); 65 #endif 66 67 static int 68 ddb_reg_var(const struct db_variable *v, db_expr_t *ep, int op) 69 { 70 register_t * const rp = (register_t *)DDB_REGS; 71 if (op == DB_VAR_SET) { 72 rp[(uintptr_t)v->valuep] = *ep; 73 } else { 74 *ep = rp[(uintptr_t)v->valuep]; 75 } 76 return 0; 77 } 78 79 80 #define XO(f) ((long *)(offsetof(db_regs_t, f) / sizeof(register_t))) 81 const struct db_variable db_regs[] = { 82 { "spsr", XO(tf_spsr), ddb_reg_var, NULL }, 83 { "r0", XO(tf_r0), ddb_reg_var, NULL }, 84 { "r1", XO(tf_r1), ddb_reg_var, NULL }, 85 { "r2", XO(tf_r2), ddb_reg_var, NULL }, 86 { "r3", XO(tf_r3), ddb_reg_var, NULL }, 87 { "r4", XO(tf_r4), ddb_reg_var, NULL }, 88 { "r5", XO(tf_r5), ddb_reg_var, NULL }, 89 { "r6", XO(tf_r6), ddb_reg_var, NULL }, 90 { "r7", XO(tf_r7), ddb_reg_var, NULL }, 91 { "r8", XO(tf_r8), ddb_reg_var, NULL }, 92 { "r9", XO(tf_r9), ddb_reg_var, NULL }, 93 { "r10", XO(tf_r10), ddb_reg_var, NULL }, 94 { "r11", XO(tf_r11), ddb_reg_var, NULL }, 95 { "r12", XO(tf_r12), ddb_reg_var, NULL }, 96 { "usr_sp", XO(tf_usr_sp), ddb_reg_var, NULL }, 97 { "usr_lr", XO(tf_usr_lr), ddb_reg_var, NULL }, 98 { "svc_sp", XO(tf_svc_sp), ddb_reg_var, NULL }, 99 { "svc_lr", XO(tf_svc_lr), ddb_reg_var, NULL }, 100 { "pc", XO(tf_pc), ddb_reg_var, NULL }, 101 #ifdef _KERNEL 102 { "und_sp", &nil, db_access_und_sp, NULL }, 103 { "abt_sp", &nil, db_access_abt_sp, NULL }, 104 { "irq_sp", &nil, db_access_irq_sp, NULL }, 105 #endif 106 }; 107 #undef XO 108 109 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 110 111 const struct db_command db_machine_command_table[] = { 112 { DDB_ADD_CMD("frame", db_show_frame_cmd, 0, 113 "Displays the contents of a trapframe", 114 "[address]", 115 " address:\taddress of trapfame to display")}, 116 #ifdef _KERNEL 117 { DDB_ADD_CMD("fault", db_show_fault_cmd, 0, 118 "Displays the fault registers", 119 NULL,NULL) }, 120 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) 121 { DDB_ADD_CMD("tlb", db_show_tlb_cmd, 0, 122 "Displays the TLB", 123 NULL,NULL) }, 124 #endif 125 #if defined(MULTIPROCESSOR) 126 { DDB_ADD_CMD("cpu", db_switch_cpu_cmd, 0, 127 "switch to a different cpu", 128 NULL,NULL) }, 129 #endif 130 #endif /* _KERNEL */ 131 132 #ifdef ARM32_DB_COMMANDS 133 ARM32_DB_COMMANDS, 134 #endif 135 { DDB_ADD_CMD(NULL, NULL, 0,NULL,NULL,NULL) } 136 }; 137 138 void 139 db_show_frame_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 140 { 141 struct trapframe *frame; 142 143 if (!have_addr) { 144 db_printf("frame address must be specified\n"); 145 return; 146 } 147 148 frame = (struct trapframe *)addr; 149 150 db_printf("frame address = %08x ", (u_int)frame); 151 db_printf("spsr=%08x\n", frame->tf_spsr); 152 db_printf("r0 =%08x r1 =%08x r2 =%08x r3 =%08x\n", 153 frame->tf_r0, frame->tf_r1, frame->tf_r2, frame->tf_r3); 154 db_printf("r4 =%08x r5 =%08x r6 =%08x r7 =%08x\n", 155 frame->tf_r4, frame->tf_r5, frame->tf_r6, frame->tf_r7); 156 db_printf("r8 =%08x r9 =%08x r10=%08x r11=%08x\n", 157 frame->tf_r8, frame->tf_r9, frame->tf_r10, frame->tf_r11); 158 db_printf("r12=%08x r13=%08x r14=%08x r15=%08x\n", 159 frame->tf_r12, frame->tf_usr_sp, frame->tf_usr_lr, frame->tf_pc); 160 db_printf("slr=%08x ssp=%08x\n", frame->tf_svc_lr, frame->tf_svc_sp); 161 } 162 163 #ifdef _KERNEL 164 int 165 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 166 { 167 168 if (rw == DB_VAR_GET) 169 *valp = get_stackptr(PSR_UND32_MODE); 170 return(0); 171 } 172 173 int 174 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 175 { 176 177 if (rw == DB_VAR_GET) 178 *valp = get_stackptr(PSR_ABT32_MODE); 179 return(0); 180 } 181 182 int 183 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 184 { 185 186 if (rw == DB_VAR_GET) 187 *valp = get_stackptr(PSR_IRQ32_MODE); 188 return(0); 189 } 190 191 void 192 db_show_fault_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 193 { 194 db_printf("DFAR=%#x DFSR=%#x IFAR=%#x IFSR=%#x\n", 195 armreg_dfar_read(), armreg_dfsr_read(), 196 armreg_ifar_read(), armreg_ifsr_read()); 197 db_printf("CONTEXTIDR=%#x TTBCR=%#x TTBR=%#x\n", 198 armreg_contextidr_read(), armreg_ttbcr_read(), 199 armreg_ttbr_read()); 200 } 201 202 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) 203 static void 204 tlb_print_common_header(const char *str) 205 { 206 db_printf("-W/I-- ----VA---- ----PA---- --SIZE-- D AP XN ASD %s\n", str); 207 } 208 209 static void 210 tlb_print_addr(size_t way, size_t va_index, vaddr_t vpn, paddr_t pfn) 211 { 212 db_printf("[%1zu:%02zx] 0x%05lx000 0x%05lx000", way, va_index, vpn, pfn); 213 } 214 215 static void 216 tlb_print_size_domain_prot(const char *sizestr, u_int domain, u_int ap, 217 bool xn_p) 218 { 219 db_printf(" %8s %1x %2d %s", sizestr, domain, ap, (xn_p ? "XN" : "--")); 220 } 221 222 static void 223 tlb_print_asid(bool ng_p, tlb_asid_t asid) 224 { 225 if (ng_p) { 226 db_printf(" %3d", asid); 227 } else { 228 db_printf(" ---"); 229 } 230 } 231 232 struct db_tlbinfo { 233 vaddr_t (*dti_decode_vpn)(size_t, uint32_t, uint32_t); 234 void (*dti_print_header)(void); 235 void (*dti_print_entry)(size_t, size_t, uint32_t, uint32_t); 236 u_int dti_index; 237 }; 238 239 #if defined(CPU_CORTEXA5) 240 static void 241 tlb_print_cortex_a5_header(void) 242 { 243 tlb_print_common_header(" S TEX C B"); 244 } 245 246 static vaddr_t 247 tlb_decode_cortex_a5_vpn(size_t va_index, uint32_t d0, uint32_t d1) 248 { 249 const uint64_t d = ((uint64_t)d1 << 32) | d0; 250 251 const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE); 252 return __SHIFTOUT(d, ARM_A5_TLBDATA_VA) * (ARM_A5_TLBDATAOP_INDEX + 1) 253 + (va_index << (4*size)); 254 } 255 256 static void 257 tlb_print_cortex_a5_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1) 258 { 259 static const char size_strings[4][8] = { 260 " 4KB ", " 64KB ", " 1MB ", " 16MB ", 261 }; 262 263 const uint64_t d = ((uint64_t)d1 << 32) | d0; 264 265 const paddr_t pfn = __SHIFTOUT(d, ARM_A5_TLBDATA_PA); 266 const vaddr_t vpn = tlb_decode_cortex_a5_vpn(va_index, d0, d1); 267 268 tlb_print_addr(way, va_index, vpn, pfn); 269 270 const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE); 271 const u_int domain = __SHIFTOUT(d, ARM_A5_TLBDATA_DOM); 272 const u_int ap = __SHIFTOUT(d, ARM_A5_TLBDATA_AP); 273 const bool xn_p = (d & ARM_A5_TLBDATA_XN) != 0; 274 275 tlb_print_size_domain_prot(size_strings[size], domain, ap, xn_p); 276 277 const bool ng_p = (d & ARM_A5_TLBDATA_nG) != 0; 278 const tlb_asid_t asid = __SHIFTOUT(d, ARM_A5_TLBDATA_ASID); 279 280 tlb_print_asid(ng_p, asid); 281 282 const u_int tex = __SHIFTOUT(d, ARM_A5_TLBDATA_TEX); 283 const bool c_p = (d & ARM_A5_TLBDATA_C) != 0; 284 const bool b_p = (d & ARM_A5_TLBDATA_B) != 0; 285 const bool s_p = (d & ARM_A5_TLBDATA_S) != 0; 286 287 db_printf(" %c %d %c %c\n", (s_p ? 'S' : '-'), tex, 288 (c_p ? 'C' : '-'), (b_p ? 'B' : '-')); 289 } 290 291 static const struct db_tlbinfo tlb_cortex_a5_info = { 292 .dti_decode_vpn = tlb_decode_cortex_a5_vpn, 293 .dti_print_header = tlb_print_cortex_a5_header, 294 .dti_print_entry = tlb_print_cortex_a5_entry, 295 .dti_index = ARM_A5_TLBDATAOP_INDEX, 296 }; 297 #endif /* CPU_CORTEXA5 */ 298 299 #if defined(CPU_CORTEXA7) 300 static const char tlb_cortex_a7_esizes[8][8] = { 301 " 4KB(S)", " 4KB(L)", "64KB(S)", "64KB(L)", 302 " 1MB(S)", " 2MB(L)", "16MB(S)", " 1GB(L)", 303 }; 304 305 static void 306 tlb_print_cortex_a7_header(void) 307 { 308 tlb_print_common_header("IS --OS- SH"); 309 } 310 311 static inline vaddr_t 312 tlb_decode_cortex_a7_vpn(size_t va_index, uint32_t d0, uint32_t d1) 313 { 314 const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE); 315 const u_int shift = (size & 1) 316 ? ((0x12090400 >> (8*size)) & 0x1f) 317 : (2 * size); 318 319 return __SHIFTOUT(d0, ARM_A7_TLBDATA0_VA) * (ARM_A7_TLBDATAOP_INDEX + 1) 320 + (va_index << shift); 321 } 322 323 static void 324 tlb_print_cortex_a7_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1) 325 { 326 const uint32_t d2 = armreg_tlbdata2_read(); 327 const uint64_t d01 = ((uint64_t)d1 << 32) | d0; 328 const uint64_t d12 = ((uint64_t)d2 << 32) | d1; 329 330 const paddr_t pfn = __SHIFTOUT(d12, ARM_A7_TLBDATA12_PA); 331 const vaddr_t vpn = tlb_decode_cortex_a7_vpn(va_index, d0, d1); 332 333 tlb_print_addr(way, va_index, vpn, pfn); 334 335 const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE); 336 const u_int domain = __SHIFTOUT(d2, ARM_A7_TLBDATA2_DOM); 337 const u_int ap = __SHIFTOUT(d1, ARM_A7_TLBDATA1_AP); 338 const bool xn_p = (d2 & ARM_A7_TLBDATA2_XN1) != 0; 339 340 tlb_print_size_domain_prot(tlb_cortex_a7_esizes[size], domain, ap, xn_p); 341 342 const bool ng_p = (d1 & ARM_A7_TLBDATA1_nG) != 0; 343 const tlb_asid_t asid = __SHIFTOUT(d01, ARM_A7_TLBDATA01_ASID); 344 345 tlb_print_asid(ng_p, asid); 346 347 const u_int is = __SHIFTOUT(d2, ARM_A7_TLBDATA2_IS); 348 if (is == ARM_A7_TLBDATA2_IS_DSO) { 349 u_int mt = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SDO_MT); 350 switch (mt) { 351 case ARM_A7_TLBDATA2_SDO_MT_D: 352 db_printf(" DV\n"); 353 return; 354 case ARM_A7_TLBDATA2_SDO_MT_SO: 355 db_printf(" SO\n"); 356 return; 357 default: 358 db_printf(" %02u\n", mt); 359 return; 360 } 361 } 362 const u_int os = __SHIFTOUT(d2, ARM_A7_TLBDATA2_OS); 363 const u_int sh = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SH); 364 static const char is_types[3][3] = { "NC", "WB", "WT" }; 365 static const char os_types[4][6] = { "NC", "WB+WA", "WT", "WB" }; 366 static const char sh_types[4][3] = { "NS", "na", "OS", "IS" }; 367 db_printf(" %2s %5s %2s\n", is_types[is], os_types[os], sh_types[sh]); 368 } 369 370 static const struct db_tlbinfo tlb_cortex_a7_info = { 371 .dti_decode_vpn = tlb_decode_cortex_a7_vpn, 372 .dti_print_header = tlb_print_cortex_a7_header, 373 .dti_print_entry = tlb_print_cortex_a7_entry, 374 .dti_index = ARM_A7_TLBDATAOP_INDEX, 375 }; 376 #endif /* CPU_CORTEXA7 */ 377 378 static inline const struct db_tlbinfo * 379 tlb_lookup_tlbinfo(void) 380 { 381 #if defined(CPU_CORTEXA5) && defined(CPU_CORTEXA7) 382 const bool cortex_a5_p = CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid); 383 const bool cortex_a7_p = CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid); 384 #elif defined(CPU_CORTEXA5) 385 const bool cortex_a5_p = true; 386 #else 387 const bool cortex_a7_p = true; 388 #endif 389 #ifdef CPU_CORTEXA5 390 if (cortex_a5_p) { 391 return &tlb_cortex_a5_info; 392 } 393 #endif 394 #ifdef CPU_CORTEXA7 395 if (cortex_a7_p) { 396 return &tlb_cortex_a7_info; 397 } 398 #endif 399 return NULL; 400 } 401 402 void 403 db_show_tlb_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 404 { 405 const struct db_tlbinfo * const dti = tlb_lookup_tlbinfo(); 406 407 if (have_addr) { 408 const vaddr_t vpn = (vaddr_t)addr >> L2_S_SHIFT; 409 const u_int va_index = vpn & dti->dti_index; 410 for (size_t way = 0; way < 2; way++) { 411 armreg_tlbdataop_write( 412 __SHIFTIN(va_index, dti->dti_index) 413 | __SHIFTIN(way, ARM_TLBDATAOP_WAY)); 414 arm_isb(); 415 const uint32_t d0 = armreg_tlbdata0_read(); 416 const uint32_t d1 = armreg_tlbdata1_read(); 417 if ((d0 & ARM_TLBDATA_VALID) 418 && vpn == (*dti->dti_decode_vpn)(va_index, d0, d1)) { 419 (*dti->dti_print_header)(); 420 (*dti->dti_print_entry)(way, va_index, d0, d1); 421 return; 422 } 423 } 424 db_printf("VA %#"DDB_EXPR_FMT"x not found in TLB\n", addr); 425 return; 426 } 427 428 bool first = true; 429 size_t n = 0; 430 for (size_t va_index = 0; va_index <= dti->dti_index; va_index++) { 431 for (size_t way = 0; way < 2; way++) { 432 armreg_tlbdataop_write( 433 __SHIFTIN(way, ARM_TLBDATAOP_WAY) 434 | __SHIFTIN(va_index, dti->dti_index)); 435 arm_isb(); 436 const uint32_t d0 = armreg_tlbdata0_read(); 437 const uint32_t d1 = armreg_tlbdata1_read(); 438 if (d0 & ARM_TLBDATA_VALID) { 439 if (first) { 440 (*dti->dti_print_header)(); 441 first = false; 442 } 443 (*dti->dti_print_entry)(way, va_index, d0, d1); 444 n++; 445 } 446 } 447 } 448 db_printf("%zu TLB valid entries found\n", n); 449 } 450 #endif /* CPU_CORTEXA5 || CPU_CORTEXA7 */ 451 452 #if defined(MULTIPROCESSOR) 453 void 454 db_switch_cpu_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 455 { 456 if (addr >= maxcpus) { 457 db_printf("cpu %"DDB_EXPR_FMT"d out of range", addr); 458 return; 459 } 460 struct cpu_info *new_ci = cpu_lookup(addr); 461 if (new_ci == NULL) { 462 db_printf("cpu %"DDB_EXPR_FMT"d does not exist", addr); 463 return; 464 } 465 if (DDB_REGS->tf_spsr & PSR_T_bit) { 466 DDB_REGS->tf_pc -= 2; /* XXX */ 467 } else { 468 DDB_REGS->tf_pc -= 4; 469 } 470 db_newcpu = new_ci; 471 db_continue_cmd(0, false, 0, ""); 472 } 473 #endif 474 #endif /* _KERNEL */ 475
Indexes created Thu Oct 16 14:10:15 GMT 2025