db_machdep.c revision 1.28
1 /* $NetBSD: db_machdep.c,v 1.28 2020/04/14 07:59:43 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Mark Brinicombe 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #ifdef _KERNEL_OPT 32 #include "opt_cputypes.h" 33 #include "opt_multiprocessor.h" 34 #endif 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.28 2020/04/14 07:59:43 skrll Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/cpu.h> 41 #include <sys/proc.h> 42 #include <sys/vnode.h> 43 #include <sys/systm.h> 44 45 #include <arm/arm32/db_machdep.h> 46 #include <arm/cpufunc.h> 47 48 #include <ddb/db_access.h> 49 #include <ddb/db_sym.h> 50 #include <ddb/db_output.h> 51 #include <ddb/db_variables.h> 52 #include <ddb/db_command.h> 53 #include <ddb/db_run.h> 54 55 #ifndef _KERNEL 56 #include <stddef.h> 57 #endif 58 59 #ifdef _KERNEL 60 static long nil; 61 62 int db_access_und_sp(const struct db_variable *, db_expr_t *, int); 63 int db_access_abt_sp(const struct db_variable *, db_expr_t *, int); 64 int db_access_irq_sp(const struct db_variable *, db_expr_t *, int); 65 #endif 66 67 static int 68 ddb_reg_var(const struct db_variable *v, db_expr_t *ep, int op) 69 { 70 register_t * const rp = (register_t *)DDB_REGS; 71 if (op == DB_VAR_SET) { 72 rp[(uintptr_t)v->valuep] = *ep; 73 } else { 74 *ep = rp[(uintptr_t)v->valuep]; 75 } 76 return 0; 77 } 78 79 80 #define XO(f) ((long *)(offsetof(db_regs_t, f) / sizeof(register_t))) 81 const struct db_variable db_regs[] = { 82 { "spsr", XO(tf_spsr), ddb_reg_var, NULL }, 83 { "r0", XO(tf_r0), ddb_reg_var, NULL }, 84 { "r1", XO(tf_r1), ddb_reg_var, NULL }, 85 { "r2", XO(tf_r2), ddb_reg_var, NULL }, 86 { "r3", XO(tf_r3), ddb_reg_var, NULL }, 87 { "r4", XO(tf_r4), ddb_reg_var, NULL }, 88 { "r5", XO(tf_r5), ddb_reg_var, NULL }, 89 { "r6", XO(tf_r6), ddb_reg_var, NULL }, 90 { "r7", XO(tf_r7), ddb_reg_var, NULL }, 91 { "r8", XO(tf_r8), ddb_reg_var, NULL }, 92 { "r9", XO(tf_r9), ddb_reg_var, NULL }, 93 { "r10", XO(tf_r10), ddb_reg_var, NULL }, 94 { "r11", XO(tf_r11), ddb_reg_var, NULL }, 95 { "r12", XO(tf_r12), ddb_reg_var, NULL }, 96 { "usr_sp", XO(tf_usr_sp), ddb_reg_var, NULL }, 97 { "usr_lr", XO(tf_usr_lr), ddb_reg_var, NULL }, 98 { "svc_sp", XO(tf_svc_sp), ddb_reg_var, NULL }, 99 { "svc_lr", XO(tf_svc_lr), ddb_reg_var, NULL }, 100 { "pc", XO(tf_pc), ddb_reg_var, NULL }, 101 #ifdef _KERNEL 102 { "und_sp", &nil, db_access_und_sp, NULL }, 103 { "abt_sp", &nil, db_access_abt_sp, NULL }, 104 { "irq_sp", &nil, db_access_irq_sp, NULL }, 105 #endif 106 }; 107 #undef XO 108 109 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 110 111 const struct db_command db_machine_command_table[] = { 112 #ifdef _KERNEL 113 #if defined(MULTIPROCESSOR) 114 { DDB_ADD_CMD("cpu", db_switch_cpu_cmd, 0, 115 "switch to a different cpu", 116 NULL,NULL) }, 117 #endif /* MULTIPROCESSOR */ 118 { DDB_ADD_CMD("fault", db_show_fault_cmd, 0, 119 "Displays the fault registers", 120 NULL,NULL) }, 121 #endif 122 { DDB_ADD_CMD("frame", db_show_frame_cmd, 0, 123 "Displays the contents of a trapframe", 124 "[address]", 125 " address:\taddress of trapfame to display")}, 126 #ifdef _KERNEL 127 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) 128 { DDB_ADD_CMD("tlb", db_show_tlb_cmd, 0, 129 "Displays the TLB", 130 NULL,NULL) }, 131 #endif 132 #endif /* _KERNEL */ 133 134 #ifdef ARM32_DB_COMMANDS 135 ARM32_DB_COMMANDS, 136 #endif 137 { DDB_ADD_CMD(NULL, NULL, 0,NULL,NULL,NULL) } 138 }; 139 140 void 141 db_show_frame_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 142 { 143 struct trapframe *frame; 144 145 if (!have_addr) { 146 db_printf("frame address must be specified\n"); 147 return; 148 } 149 150 frame = (struct trapframe *)addr; 151 152 db_printf("frame address = %08x ", (u_int)frame); 153 db_printf("spsr=%08x\n", frame->tf_spsr); 154 db_printf("r0 =%08x r1 =%08x r2 =%08x r3 =%08x\n", 155 frame->tf_r0, frame->tf_r1, frame->tf_r2, frame->tf_r3); 156 db_printf("r4 =%08x r5 =%08x r6 =%08x r7 =%08x\n", 157 frame->tf_r4, frame->tf_r5, frame->tf_r6, frame->tf_r7); 158 db_printf("r8 =%08x r9 =%08x r10=%08x r11=%08x\n", 159 frame->tf_r8, frame->tf_r9, frame->tf_r10, frame->tf_r11); 160 db_printf("r12=%08x r13=%08x r14=%08x r15=%08x\n", 161 frame->tf_r12, frame->tf_usr_sp, frame->tf_usr_lr, frame->tf_pc); 162 db_printf("slr=%08x ssp=%08x\n", frame->tf_svc_lr, frame->tf_svc_sp); 163 } 164 165 #ifdef _KERNEL 166 int 167 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 168 { 169 170 if (rw == DB_VAR_GET) 171 *valp = get_stackptr(PSR_UND32_MODE); 172 return(0); 173 } 174 175 int 176 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 177 { 178 179 if (rw == DB_VAR_GET) 180 *valp = get_stackptr(PSR_ABT32_MODE); 181 return(0); 182 } 183 184 int 185 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 186 { 187 188 if (rw == DB_VAR_GET) 189 *valp = get_stackptr(PSR_IRQ32_MODE); 190 return(0); 191 } 192 193 void 194 db_show_fault_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 195 { 196 db_printf("DFAR=%#x DFSR=%#x IFAR=%#x IFSR=%#x\n", 197 armreg_dfar_read(), armreg_dfsr_read(), 198 armreg_ifar_read(), armreg_ifsr_read()); 199 db_printf("CONTEXTIDR=%#x TTBCR=%#x TTBR=%#x\n", 200 armreg_contextidr_read(), armreg_ttbcr_read(), 201 armreg_ttbr_read()); 202 } 203 204 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) 205 static void 206 tlb_print_common_header(const char *str) 207 { 208 db_printf("-W/I-- ----VA---- ----PA---- --SIZE-- D AP XN ASD %s\n", str); 209 } 210 211 static void 212 tlb_print_addr(size_t way, size_t va_index, vaddr_t vpn, paddr_t pfn) 213 { 214 db_printf("[%1zu:%02zx] 0x%05lx000 0x%05lx000", way, va_index, vpn, pfn); 215 } 216 217 static void 218 tlb_print_size_domain_prot(const char *sizestr, u_int domain, u_int ap, 219 bool xn_p) 220 { 221 db_printf(" %8s %1x %2d %s", sizestr, domain, ap, (xn_p ? "XN" : "--")); 222 } 223 224 static void 225 tlb_print_asid(bool ng_p, tlb_asid_t asid) 226 { 227 if (ng_p) { 228 db_printf(" %3d", asid); 229 } else { 230 db_printf(" ---"); 231 } 232 } 233 234 struct db_tlbinfo { 235 vaddr_t (*dti_decode_vpn)(size_t, uint32_t, uint32_t); 236 void (*dti_print_header)(void); 237 void (*dti_print_entry)(size_t, size_t, uint32_t, uint32_t); 238 u_int dti_index; 239 }; 240 241 #if defined(CPU_CORTEXA5) 242 static void 243 tlb_print_cortex_a5_header(void) 244 { 245 tlb_print_common_header(" S TEX C B"); 246 } 247 248 static vaddr_t 249 tlb_decode_cortex_a5_vpn(size_t va_index, uint32_t d0, uint32_t d1) 250 { 251 const uint64_t d = ((uint64_t)d1 << 32) | d0; 252 253 const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE); 254 return __SHIFTOUT(d, ARM_A5_TLBDATA_VA) * (ARM_A5_TLBDATAOP_INDEX + 1) 255 + (va_index << (4*size)); 256 } 257 258 static void 259 tlb_print_cortex_a5_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1) 260 { 261 static const char size_strings[4][8] = { 262 " 4KB ", " 64KB ", " 1MB ", " 16MB ", 263 }; 264 265 const uint64_t d = ((uint64_t)d1 << 32) | d0; 266 267 const paddr_t pfn = __SHIFTOUT(d, ARM_A5_TLBDATA_PA); 268 const vaddr_t vpn = tlb_decode_cortex_a5_vpn(va_index, d0, d1); 269 270 tlb_print_addr(way, va_index, vpn, pfn); 271 272 const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE); 273 const u_int domain = __SHIFTOUT(d, ARM_A5_TLBDATA_DOM); 274 const u_int ap = __SHIFTOUT(d, ARM_A5_TLBDATA_AP); 275 const bool xn_p = (d & ARM_A5_TLBDATA_XN) != 0; 276 277 tlb_print_size_domain_prot(size_strings[size], domain, ap, xn_p); 278 279 const bool ng_p = (d & ARM_A5_TLBDATA_nG) != 0; 280 const tlb_asid_t asid = __SHIFTOUT(d, ARM_A5_TLBDATA_ASID); 281 282 tlb_print_asid(ng_p, asid); 283 284 const u_int tex = __SHIFTOUT(d, ARM_A5_TLBDATA_TEX); 285 const bool c_p = (d & ARM_A5_TLBDATA_C) != 0; 286 const bool b_p = (d & ARM_A5_TLBDATA_B) != 0; 287 const bool s_p = (d & ARM_A5_TLBDATA_S) != 0; 288 289 db_printf(" %c %d %c %c\n", (s_p ? 'S' : '-'), tex, 290 (c_p ? 'C' : '-'), (b_p ? 'B' : '-')); 291 } 292 293 static const struct db_tlbinfo tlb_cortex_a5_info = { 294 .dti_decode_vpn = tlb_decode_cortex_a5_vpn, 295 .dti_print_header = tlb_print_cortex_a5_header, 296 .dti_print_entry = tlb_print_cortex_a5_entry, 297 .dti_index = ARM_A5_TLBDATAOP_INDEX, 298 }; 299 #endif /* CPU_CORTEXA5 */ 300 301 #if defined(CPU_CORTEXA7) 302 static const char tlb_cortex_a7_esizes[8][8] = { 303 " 4KB(S)", " 4KB(L)", "64KB(S)", "64KB(L)", 304 " 1MB(S)", " 2MB(L)", "16MB(S)", " 1GB(L)", 305 }; 306 307 static void 308 tlb_print_cortex_a7_header(void) 309 { 310 tlb_print_common_header("IS --OS- SH"); 311 } 312 313 static inline vaddr_t 314 tlb_decode_cortex_a7_vpn(size_t va_index, uint32_t d0, uint32_t d1) 315 { 316 const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE); 317 const u_int shift = (size & 1) 318 ? ((0x12090400 >> (8*size)) & 0x1f) 319 : (2 * size); 320 321 return __SHIFTOUT(d0, ARM_A7_TLBDATA0_VA) * (ARM_A7_TLBDATAOP_INDEX + 1) 322 + (va_index << shift); 323 } 324 325 static void 326 tlb_print_cortex_a7_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1) 327 { 328 const uint32_t d2 = armreg_tlbdata2_read(); 329 const uint64_t d01 = ((uint64_t)d1 << 32) | d0; 330 const uint64_t d12 = ((uint64_t)d2 << 32) | d1; 331 332 const paddr_t pfn = __SHIFTOUT(d12, ARM_A7_TLBDATA12_PA); 333 const vaddr_t vpn = tlb_decode_cortex_a7_vpn(va_index, d0, d1); 334 335 tlb_print_addr(way, va_index, vpn, pfn); 336 337 const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE); 338 const u_int domain = __SHIFTOUT(d2, ARM_A7_TLBDATA2_DOM); 339 const u_int ap = __SHIFTOUT(d1, ARM_A7_TLBDATA1_AP); 340 const bool xn_p = (d2 & ARM_A7_TLBDATA2_XN1) != 0; 341 342 tlb_print_size_domain_prot(tlb_cortex_a7_esizes[size], domain, ap, xn_p); 343 344 const bool ng_p = (d1 & ARM_A7_TLBDATA1_nG) != 0; 345 const tlb_asid_t asid = __SHIFTOUT(d01, ARM_A7_TLBDATA01_ASID); 346 347 tlb_print_asid(ng_p, asid); 348 349 const u_int is = __SHIFTOUT(d2, ARM_A7_TLBDATA2_IS); 350 if (is == ARM_A7_TLBDATA2_IS_DSO) { 351 u_int mt = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SDO_MT); 352 switch (mt) { 353 case ARM_A7_TLBDATA2_SDO_MT_D: 354 db_printf(" DV\n"); 355 return; 356 case ARM_A7_TLBDATA2_SDO_MT_SO: 357 db_printf(" SO\n"); 358 return; 359 default: 360 db_printf(" %02u\n", mt); 361 return; 362 } 363 } 364 const u_int os = __SHIFTOUT(d2, ARM_A7_TLBDATA2_OS); 365 const u_int sh = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SH); 366 static const char is_types[3][3] = { "NC", "WB", "WT" }; 367 static const char os_types[4][6] = { "NC", "WB+WA", "WT", "WB" }; 368 static const char sh_types[4][3] = { "NS", "na", "OS", "IS" }; 369 db_printf(" %2s %5s %2s\n", is_types[is], os_types[os], sh_types[sh]); 370 } 371 372 static const struct db_tlbinfo tlb_cortex_a7_info = { 373 .dti_decode_vpn = tlb_decode_cortex_a7_vpn, 374 .dti_print_header = tlb_print_cortex_a7_header, 375 .dti_print_entry = tlb_print_cortex_a7_entry, 376 .dti_index = ARM_A7_TLBDATAOP_INDEX, 377 }; 378 #endif /* CPU_CORTEXA7 */ 379 380 static inline const struct db_tlbinfo * 381 tlb_lookup_tlbinfo(void) 382 { 383 #if defined(CPU_CORTEXA5) && defined(CPU_CORTEXA7) 384 const bool cortex_a5_p = CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid); 385 const bool cortex_a7_p = CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid); 386 #elif defined(CPU_CORTEXA5) 387 const bool cortex_a5_p = true; 388 #else 389 const bool cortex_a7_p = true; 390 #endif 391 #ifdef CPU_CORTEXA5 392 if (cortex_a5_p) { 393 return &tlb_cortex_a5_info; 394 } 395 #endif 396 #ifdef CPU_CORTEXA7 397 if (cortex_a7_p) { 398 return &tlb_cortex_a7_info; 399 } 400 #endif 401 return NULL; 402 } 403 404 void 405 db_show_tlb_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 406 { 407 const struct db_tlbinfo * const dti = tlb_lookup_tlbinfo(); 408 409 if (have_addr) { 410 const vaddr_t vpn = (vaddr_t)addr >> L2_S_SHIFT; 411 const u_int va_index = vpn & dti->dti_index; 412 for (size_t way = 0; way < 2; way++) { 413 armreg_tlbdataop_write( 414 __SHIFTIN(va_index, dti->dti_index) 415 | __SHIFTIN(way, ARM_TLBDATAOP_WAY)); 416 arm_isb(); 417 const uint32_t d0 = armreg_tlbdata0_read(); 418 const uint32_t d1 = armreg_tlbdata1_read(); 419 if ((d0 & ARM_TLBDATA_VALID) 420 && vpn == (*dti->dti_decode_vpn)(va_index, d0, d1)) { 421 (*dti->dti_print_header)(); 422 (*dti->dti_print_entry)(way, va_index, d0, d1); 423 return; 424 } 425 } 426 db_printf("VA %#"DDB_EXPR_FMT"x not found in TLB\n", addr); 427 return; 428 } 429 430 bool first = true; 431 size_t n = 0; 432 for (size_t va_index = 0; va_index <= dti->dti_index; va_index++) { 433 for (size_t way = 0; way < 2; way++) { 434 armreg_tlbdataop_write( 435 __SHIFTIN(way, ARM_TLBDATAOP_WAY) 436 | __SHIFTIN(va_index, dti->dti_index)); 437 arm_isb(); 438 const uint32_t d0 = armreg_tlbdata0_read(); 439 const uint32_t d1 = armreg_tlbdata1_read(); 440 if (d0 & ARM_TLBDATA_VALID) { 441 if (first) { 442 (*dti->dti_print_header)(); 443 first = false; 444 } 445 (*dti->dti_print_entry)(way, va_index, d0, d1); 446 n++; 447 } 448 } 449 } 450 db_printf("%zu TLB valid entries found\n", n); 451 } 452 #endif /* CPU_CORTEXA5 || CPU_CORTEXA7 */ 453 454 #if defined(MULTIPROCESSOR) 455 void 456 db_switch_cpu_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 457 { 458 if (addr >= maxcpus) { 459 db_printf("cpu %"DDB_EXPR_FMT"d out of range", addr); 460 return; 461 } 462 struct cpu_info *new_ci = cpu_lookup(addr); 463 if (new_ci == NULL) { 464 db_printf("cpu %"DDB_EXPR_FMT"d does not exist", addr); 465 return; 466 } 467 if (DDB_REGS->tf_spsr & PSR_T_bit) { 468 DDB_REGS->tf_pc -= 2; /* XXX */ 469 } else { 470 DDB_REGS->tf_pc -= 4; 471 } 472 db_newcpu = new_ci; 473 db_continue_cmd(0, false, 0, ""); 474 } 475 #endif 476 #endif /* _KERNEL */ 477
Indexes created Mon Sep 29 03:10:08 GMT 2025