exception.S revision 1.14.52.1
1 /* $NetBSD: exception.S,v 1.14.52.1 2007/08/28 18:51:57 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * exception.S 40 * 41 * Low level handlers for exception vectors 42 * 43 * Created : 24/09/94 44 * 45 * Based on kate/display/abort.s 46 */ 47 48 #include "opt_cpuoptions.h" 49 #include "opt_ipkdb.h" 50 #include "assym.h" 51 #include <machine/asm.h> 52 #include <machine/cpu.h> 53 #include <machine/frame.h> 54 55 .text 56 .align 0 57 58 AST_ALIGNMENT_FAULT_LOCALS 59 60 /* 61 * reset_entry: 62 * 63 * Handler for Reset exception. 64 */ 65 ASENTRY_NP(reset_entry) 66 adr r0, Lreset_panicmsg 67 mov r1, lr 68 bl _C_LABEL(panic) 69 /* NOTREACHED */ 70 Lreset_panicmsg: 71 .asciz "Reset vector called, LR = 0x%08x" 72 .balign 4 73 74 /* 75 * swi_entry 76 * 77 * Handler for the Software Interrupt exception. 78 */ 79 ASENTRY_NP(swi_entry) 80 PUSHFRAME 81 ENABLE_ALIGNMENT_FAULTS 82 83 mov r0, sp /* Pass the frame to any function */ 84 bl _C_LABEL(swi_handler) /* It's a SWI ! */ 85 86 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 87 PULLFRAME 88 movs pc, lr /* Exit */ 89 90 /* 91 * prefetch_abort_entry: 92 * 93 * Handler for the Prefetch Abort exception. 94 */ 95 ASENTRY_NP(prefetch_abort_entry) 96 #ifdef __XSCALE__ 97 nop /* Make absolutely sure any pending */ 98 nop /* imprecise aborts have occurred. */ 99 #endif 100 sub lr, lr, #0x00000004 /* Adjust the lr */ 101 102 PUSHFRAMEINSVC 103 ENABLE_ALIGNMENT_FAULTS 104 105 ldr r1, Lprefetch_abort_handler_address 106 adr lr, exception_exit 107 mov r0, sp /* pass the stack pointer as r0 */ 108 ldr pc, [r1] 109 110 Lprefetch_abort_handler_address: 111 .word _C_LABEL(prefetch_abort_handler_address) 112 113 .data 114 .global _C_LABEL(prefetch_abort_handler_address) 115 116 _C_LABEL(prefetch_abort_handler_address): 117 .word abortprefetch 118 119 .text 120 abortprefetch: 121 adr r0, abortprefetchmsg 122 b _C_LABEL(panic) 123 124 abortprefetchmsg: 125 .asciz "abortprefetch" 126 .align 0 127 128 /* 129 * data_abort_entry: 130 * 131 * Handler for the Data Abort exception. 132 */ 133 ASENTRY_NP(data_abort_entry) 134 #ifdef __XSCALE__ 135 nop /* Make absolutely sure any pending */ 136 nop /* imprecise aborts have occurred. */ 137 #endif 138 sub lr, lr, #0x00000008 /* Adjust the lr */ 139 140 PUSHFRAMEINSVC /* Push trap frame and switch */ 141 /* to SVC32 mode */ 142 ENABLE_ALIGNMENT_FAULTS 143 144 ldr r1, Ldata_abort_handler_address 145 adr lr, exception_exit 146 mov r0, sp /* pass the stack pointer as r0 */ 147 ldr pc, [r1] 148 149 Ldata_abort_handler_address: 150 .word _C_LABEL(data_abort_handler_address) 151 152 .data 153 .global _C_LABEL(data_abort_handler_address) 154 _C_LABEL(data_abort_handler_address): 155 .word abortdata 156 157 .text 158 abortdata: 159 adr r0, abortdatamsg 160 b _C_LABEL(panic) 161 162 abortdatamsg: 163 .asciz "abortdata" 164 .align 0 165 166 /* 167 * address_exception_entry: 168 * 169 * Handler for the Address Exception exception. 170 * 171 * NOTE: This exception isn't really used on arm32. We 172 * print a warning message to the console and then treat 173 * it like a Data Abort. 174 */ 175 ASENTRY_NP(address_exception_entry) 176 mrs r1, cpsr_all 177 mrs r2, spsr_all 178 mov r3, lr 179 adr r0, Laddress_exception_msg 180 bl _C_LABEL(printf) /* XXX CLOBBERS LR!! */ 181 b data_abort_entry 182 Laddress_exception_msg: 183 .asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n" 184 .balign 4 185 186 /* 187 * General exception exit handler 188 * (Placed here to be within range of all the references to it) 189 * 190 * It exits straight away if not returning to USR mode. 191 * This loops around delivering any pending ASTs. 192 * Interrupts are disabled at suitable points to avoid ASTs 193 * being posted between testing and exit to user mode. 194 * 195 * This function uses PULLFRAMEFROMSVCANDEXIT and 196 * DO_AST_AND_RESTORE_ALIGNMENT_FAULTS thus should 197 * only be called if the exception handler used PUSHFRAMEINSVC 198 * followed by ENABLE_ALIGNMENT_FAULTS. 199 */ 200 201 exception_exit: 202 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 203 PULLFRAMEFROMSVCANDEXIT 204 205 /* 206 * undefined_entry: 207 * 208 * Handler for the Undefined Instruction exception. 209 * 210 * We indirect the undefined vector via the handler address 211 * in the data area. Entry to the undefined handler must 212 * look like direct entry from the vector. 213 */ 214 ASENTRY_NP(undefined_entry) 215 #ifdef IPKDB 216 /* 217 * IPKDB must be hooked in at the earliest possible entry point. 218 * 219 */ 220 /* 221 * Make room for all registers saving real r0-r7 and r15. 222 * The remaining registers are updated later. 223 */ 224 stmfd sp!, {r0,r1} /* psr & spsr */ 225 stmfd sp!, {lr} /* pc */ 226 stmfd sp!, {r0-r14} /* r0-r7, r8-r14 */ 227 /* 228 * Get previous psr. 229 */ 230 mrs r7, cpsr_all 231 mrs r0, spsr_all 232 str r0, [sp, #(16*4)] 233 /* 234 * Test for user mode. 235 */ 236 tst r0, #0xf 237 bne .Lprenotuser_push 238 add r1, sp, #(8*4) 239 stmia r1,{r8-r14}^ /* store user mode r8-r14*/ 240 b .Lgoipkdb 241 /* 242 * Switch to previous mode to get r8-r13. 243 */ 244 .Lprenotuser_push: 245 orr r0, r0, #(I32_bit) /* disable interrupts */ 246 msr cpsr_all, r0 247 mov r1, r8 248 mov r2, r9 249 mov r3, r10 250 mov r4, r11 251 mov r5, r12 252 mov r6, r13 253 msr cpsr_all, r7 /* back to undefined mode */ 254 add r8, sp, #(8*4) 255 stmia r8, {r1-r6} /* r8-r13 */ 256 /* 257 * Now back to previous mode to get r14 and spsr. 258 */ 259 msr cpsr_all, r0 260 mov r1, r14 261 mrs r2, spsr 262 msr cpsr_all, r7 /* back to undefined mode */ 263 str r1, [sp, #(14*4)] /* r14 */ 264 str r2, [sp, #(17*4)] /* spsr */ 265 /* 266 * Now to IPKDB. 267 */ 268 .Lgoipkdb: 269 mov r0, sp 270 bl _C_LABEL(ipkdb_trap_glue) 271 ldr r1, .Lipkdb_trap_return 272 str r0,[r1] 273 274 /* 275 * Have to load all registers from the stack. 276 * 277 * Start with spsr and pc. 278 */ 279 ldr r0, [sp, #(16*4)] /* spsr */ 280 ldr r1, [sp, #(15*4)] /* r15 */ 281 msr spsr_all, r0 282 mov r14, r1 283 /* 284 * Test for user mode. 285 */ 286 tst r0, #0xf 287 bne .Lprenotuser_pull 288 add r1, sp, #(8*4) 289 ldmia r1, {r8-r14}^ /* load user mode r8-r14 */ 290 b .Lpull_r0r7 291 .Lprenotuser_pull: 292 /* 293 * Now previous mode spsr and r14. 294 */ 295 ldr r1, [sp, #(17*4)] /* spsr */ 296 ldr r2, [sp, #(14*4)] /* r14 */ 297 orr r0, r0, #(I32_bit) 298 msr cpsr_all, r0 /* switch to previous mode */ 299 msr spsr_all, r1 300 mov r14, r2 301 msr cpsr_all, r7 /* back to undefined mode */ 302 /* 303 * Now r8-r13. 304 */ 305 add r8, sp, #(8*4) 306 ldmia r8, {r1-r6} /* r8-r13 */ 307 msr cpsr_all, r0 308 mov r8, r1 309 mov r9, r2 310 mov r10, r3 311 mov r11, r4 312 mov r12, r5 313 mov r13, r6 314 msr cpsr_all, r7 315 .Lpull_r0r7: 316 /* 317 * Now the rest of the registers. 318 */ 319 ldr r1,Lipkdb_trap_return 320 ldr r0,[r1] 321 tst r0,r0 322 ldmfd sp!, {r0-r7} /* r0-r7 */ 323 add sp, sp, #(10*4) /* adjust sp */ 324 325 /* 326 * Did IPKDB handle it? 327 */ 328 movnes pc, lr /* return */ 329 330 #endif 331 stmfd sp!, {r0, r1} 332 ldr r0, Lundefined_handler_indirection 333 ldr r1, [sp], #0x0004 334 str r1, [r0, #0x0000] 335 ldr r1, [sp], #0x0004 336 str r1, [r0, #0x0004] 337 ldmia r0, {r0, r1, pc} 338 339 #ifdef IPKDB 340 Lipkdb_trap_return: 341 .word Lipkdb_trap_return_data 342 #endif 343 344 Lundefined_handler_indirection: 345 .word Lundefined_handler_indirection_data 346 347 /* 348 * assembly bounce code for calling the kernel 349 * undefined instruction handler. This uses 350 * a standard trap frame and is called in SVC mode. 351 */ 352 353 ENTRY_NP(undefinedinstruction_bounce) 354 PUSHFRAMEINSVC 355 ENABLE_ALIGNMENT_FAULTS 356 357 mov r0, sp 358 adr lr, exception_exit 359 b _C_LABEL(undefinedinstruction) 360 361 .data 362 .align 0 363 364 #ifdef IPKDB 365 Lipkdb_trap_return_data: 366 .word 0 367 #endif 368 369 /* 370 * Indirection data 371 * 2 words use for preserving r0 and r1 372 * 3rd word contains the undefined handler address. 373 */ 374 375 Lundefined_handler_indirection_data: 376 .word 0 377 .word 0 378 379 .global _C_LABEL(undefined_handler_address) 380 _C_LABEL(undefined_handler_address): 381 .word _C_LABEL(undefinedinstruction_bounce) 382
Indexes created Thu Oct 02 07:10:07 GMT 2025