exception.S revision 1.2
1 /* $NetBSD: exception.S,v 1.2 2001/11/28 01:06:19 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * exception.S 40 * 41 * Low level handlers for exception vectors 42 * 43 * Created : 24/09/94 44 * 45 * Based on kate/display/abort.s 46 */ 47 48 #include "opt_ipkdb.h" 49 #include <machine/asm.h> 50 #include <machine/cpu.h> 51 #include <machine/frame.h> 52 #include "assym.h" 53 54 .text 55 .align 0 56 57 Lastpending: 58 .word _C_LABEL(astpending) 59 60 /* 61 * General exception exit handler 62 * 63 * It exits straight away if not returning to USR mode. 64 * This loops around delivering any pending ASTs. 65 * Interrupts are disabled at suitable points to avoid ASTs 66 * being posted between testing and exit to user mode. 67 * 68 * This function uses PULLFRAMEFROMSVCANDEXIT thus should 69 * only be called if the exception handler used PUSHFRAMEINSVC 70 */ 71 72 exception_exit: 73 mrs r4, cpsr_all /* Get CPSR */ 74 75 ldr r0, [sp] /* Get the SPSR from stack */ 76 and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the AST */ 77 teq r0, #(PSR_USR32_MODE) 78 bne do_exit /* Not USR mode so no AST delivery */ 79 80 ldr r5, Lastpending /* Get address of astpending */ 81 82 Lexception_exit_loop: 83 orr r0, r4, #(I32_bit) /* Block IRQs */ 84 msr cpsr_all, r0 85 86 ldr r1, [r5] /* Do we have an AST pending */ 87 teq r1, #0x00000000 88 bne do_ast 89 90 PULLFRAMEFROMSVCANDEXIT /* No AST so exit */ 91 92 do_ast: 93 mov r1, #0x00000000 /* Clear ast pending */ 94 str r1, [r5] 95 96 msr cpsr_all, r4 /* Restore interrupts */ 97 98 mov r0, sp /* arg 0 = trap frame */ 99 bl _C_LABEL(ast) /* call the AST handler */ 100 b Lexception_exit_loop /* Try and exit again */ 101 102 do_exit: 103 orr r0, r4, #(I32_bit) /* Disable interupts */ 104 msr cpsr_all, r0 105 106 PULLFRAMEFROMSVCANDEXIT /* Restore the trap frame and exit */ 107 108 109 /* entry point for CPU data abort */ 110 111 ASENTRY_NP(data_abort_entry) 112 sub lr, lr, #0x00000008 /* Adjust the lr */ 113 114 PUSHFRAMEINSVC /* Push trap frame and switch */ 115 /* to SVC32 mode */ 116 117 mov r0, sp /* pass the stack pointer as r0 */ 118 119 add lr, pc, #exception_exit - . - 8 120 ldr r1, Ldata_abort_handler_address 121 ldr pc, [r1] 122 123 Ldata_abort_handler_address: 124 .word _C_LABEL(data_abort_handler_address) 125 126 .data 127 .global _C_LABEL(data_abort_handler_address) 128 _C_LABEL(data_abort_handler_address): 129 .word abortdata 130 131 .text 132 abortdata: 133 add r0, pc, #abortdatamsg - . - 8 134 b _C_LABEL(panic) 135 136 abortdatamsg: 137 .asciz "abortdata" 138 .align 0 139 140 141 ASENTRY_NP(prefetch_abort_entry) 142 sub lr, lr, #0x00000004 /* Adjust the lr */ 143 144 PUSHFRAMEINSVC 145 146 mov r0, sp /* pass the stack pointer as r0 */ 147 148 add lr, pc, #exception_exit - . - 8 149 ldr r1, Lprefetch_abort_handler_address 150 ldr pc, [r1] 151 152 Lprefetch_abort_handler_address: 153 .word _C_LABEL(prefetch_abort_handler_address) 154 155 .data 156 .global _C_LABEL(prefetch_abort_handler_address) 157 158 _C_LABEL(prefetch_abort_handler_address): 159 .word abortprefetch 160 161 .text 162 abortprefetch: 163 add r0, pc, #abortprefetchmsg - . - 8 164 b _C_LABEL(panic) 165 166 abortprefetchmsg: 167 .asciz "abortprefetch" 168 .align 0 169 170 171 /* 172 * swi_entry 173 * 174 * Main entry point for the SWI vector 175 */ 176 177 ASENTRY_NP(swi_entry) 178 PUSHFRAME 179 180 sub r0, lr, #0x00000004 /* Get the address of the SWI */ 181 ldr r4, [r0] /* Get the instruction */ 182 183 bic r1, r4, #0xff000000 /* Extract the comment field */ 184 185 mov r0, sp /* Pass the frame to any function */ 186 187 bl _C_LABEL(syscall) /* It's a syscall ! */ 188 189 ldr r5, Lastpending /* Get address of astpending */ 190 mrs r4, cpsr_all /* Get CPSR */ 191 192 swi_exit_loop: 193 orr r0, r4, #(I32_bit) /* Disable IRQs */ 194 msr cpsr_all, r0 195 196 ldr r1, [r5] /* Do we have an AST pending */ 197 teq r1, #0x00000000 198 bne do_swi_ast 199 200 PULLFRAME 201 movs pc, lr /* Exit */ 202 203 do_swi_ast: 204 mov r1, #0x00000000 /* Clear ast pending */ 205 str r1, [r5] 206 207 msr cpsr_all, r4 /* Restore interrupts */ 208 209 mov r0, sp /* arg 0 = trap frame */ 210 bl _C_LABEL(ast) /* call the AST handler */ 211 b swi_exit_loop /* Try and exit again */ 212 213 214 /* 215 * We indirect the undefined vector via the handler address 216 * in the data area. 217 * Entry to the undefined handler must look like direct 218 * entry from the vector. 219 */ 220 221 ASENTRY_NP(undefined_entry) 222 #ifdef IPKDB 223 /* 224 * IPKDB must be hooked in at the earliest possible entry point. 225 * 226 */ 227 /* 228 * Make room for all registers saving real r0-r7 and r15. 229 * The remaining registers are updated later. 230 */ 231 stmfd sp!, {r0,r1} /* psr & spsr */ 232 stmfd sp!, {lr} /* pc */ 233 stmfd sp!, {r0-r14} /* r0-r7, r8-r14 */ 234 /* 235 * Get previous psr. 236 */ 237 mrs r7, cpsr_all 238 mrs r0, spsr_all 239 str r0, [sp, #(16*4)] 240 /* 241 * Test for user mode. 242 */ 243 tst r0, #0xf 244 bne Lprenotuser_push 245 add r1, sp, #(8*4) 246 stmia r1,{r8-r14}^ /* store user mode r8-r14*/ 247 b Lgoipkdb 248 /* 249 * Switch to previous mode to get r8-r13. 250 */ 251 Lprenotuser_push: 252 orr r0, r0, #(I32_bit) /* disable interrupts */ 253 msr cpsr_all, r0 254 mov r1, r8 255 mov r2, r9 256 mov r3, r10 257 mov r4, r11 258 mov r5, r12 259 mov r6, r13 260 msr cpsr_all, r7 /* back to undefined mode */ 261 add r8, sp, #(8*4) 262 stmia r8, {r1-r6} /* r8-r13 */ 263 /* 264 * Now back to previous mode to get r14 and spsr. 265 */ 266 msr cpsr_all, r0 267 mov r1, r14 268 mrs r2, spsr 269 msr cpsr_all, r7 /* back to undefined mode */ 270 str r1, [sp, #(14*4)] /* r14 */ 271 str r2, [sp, #(17*4)] /* spsr */ 272 /* 273 * Now to IPKDB. 274 */ 275 Lgoipkdb: 276 mov r0, sp 277 bl _C_LABEL(ipkdb_trap_glue) 278 ldr r1, Lipkdb_trap_return 279 str r0,[r1] 280 /* 281 * Have to load all registers from the stack. 282 * 283 * Start with spsr and pc. 284 */ 285 ldr r0, [sp, #(16*4)] /* spsr */ 286 ldr r1, [sp, #(15*4)] /* r15 */ 287 msr spsr_all, r0 288 mov r14, r1 289 /* 290 * Test for user mode. 291 */ 292 tst r0, #0xf 293 bne Lprenotuser_pull 294 add r1, sp, #(8*4) 295 ldmia r1, {r8-r14}^ /* load user mode r8-r14 */ 296 b Lpull_r0r7 297 Lprenotuser_pull: 298 /* 299 * Now previous mode spsr and r14. 300 */ 301 ldr r1, [sp, #(17*4)] /* spsr */ 302 ldr r2, [sp, #(14*4)] /* r14 */ 303 orr r0, r0, #(I32_bit) 304 msr cpsr_all, r0 /* switch to previous mode */ 305 msr spsr_all, r1 306 mov r14, r2 307 msr cpsr_all, r7 /* back to undefined mode */ 308 /* 309 * Now r8-r13. 310 */ 311 add r8, sp, #(8*4) 312 ldmia r8, {r1-r6} /* r8-r13 */ 313 msr cpsr_all, r0 314 mov r8, r1 315 mov r9, r2 316 mov r10, r3 317 mov r11, r4 318 mov r12, r5 319 mov r13, r6 320 msr cpsr_all, r7 321 Lpull_r0r7: 322 /* 323 * Now the rest of the registers. 324 */ 325 ldr r1,Lipkdb_trap_return 326 ldr r0,[r1] 327 tst r0,r0 328 ldmfd sp!, {r0-r7} /* r0-r7 */ 329 add sp, sp, #(10*4) /* adjust sp */ 330 331 /* 332 * Did IPKDB handle it? 333 */ 334 movnes pc, lr /* return */ 335 336 #endif 337 stmfd sp!, {r0, r1} 338 ldr r0, Lundefined_handler_indirection 339 ldr r1, [sp], #0x0004 340 str r1, [r0, #0x0000] 341 ldr r1, [sp], #0x0004 342 str r1, [r0, #0x0004] 343 ldmia r0, {r0, r1, pc} 344 345 #ifdef IPKDB 346 Lipkdb_trap_return: 347 .word Lipkdb_trap_return_data 348 #endif 349 350 Lundefined_handler_indirection: 351 .word Lundefined_handler_indirection_data 352 353 /* 354 * assembly bounce code for calling the kernel 355 * undefined instruction handler. This uses 356 * a standard trap frame and is called in SVC mode. 357 */ 358 359 ENTRY_NP(undefinedinstruction_bounce) 360 PUSHFRAMEINSVC 361 mov r0, sp 362 bl _C_LABEL(undefinedinstruction) 363 364 b exception_exit 365 366 .data 367 .align 0 368 369 #ifdef IPKDB 370 Lipkdb_trap_return_data: 371 .word 0 372 #endif 373 374 /* 375 * Indirection data 376 * 2 words use for preserving r0 and r1 377 * 3rd word contains the undefined handler address. 378 */ 379 380 Lundefined_handler_indirection_data: 381 .word 0 382 .word 0 383 384 .global _C_LABEL(undefined_handler_address) 385 _C_LABEL(undefined_handler_address): 386 .word _C_LABEL(undefinedinstruction_bounce) 387 388 /* End of exception.S */ 389
Indexes created Thu Oct 02 07:10:07 GMT 2025