fault.c revision 1.104 1 1.104 skrll /* $NetBSD: fault.c,v 1.104 2017/07/02 16:16:44 skrll Exp $ */
2 1.1 chris
3 1.1 chris /*
4 1.27 scw * Copyright 2003 Wasabi Systems, Inc.
5 1.27 scw * All rights reserved.
6 1.27 scw *
7 1.27 scw * Written by Steve C. Woodford for Wasabi Systems, Inc.
8 1.27 scw *
9 1.27 scw * Redistribution and use in source and binary forms, with or without
10 1.27 scw * modification, are permitted provided that the following conditions
11 1.27 scw * are met:
12 1.27 scw * 1. Redistributions of source code must retain the above copyright
13 1.27 scw * notice, this list of conditions and the following disclaimer.
14 1.27 scw * 2. Redistributions in binary form must reproduce the above copyright
15 1.27 scw * notice, this list of conditions and the following disclaimer in the
16 1.27 scw * documentation and/or other materials provided with the distribution.
17 1.27 scw * 3. All advertising materials mentioning features or use of this software
18 1.27 scw * must display the following acknowledgement:
19 1.27 scw * This product includes software developed for the NetBSD Project by
20 1.27 scw * Wasabi Systems, Inc.
21 1.27 scw * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.27 scw * or promote products derived from this software without specific prior
23 1.27 scw * written permission.
24 1.27 scw *
25 1.27 scw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.27 scw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.27 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.27 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.27 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.27 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.27 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.27 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.27 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.27 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.27 scw * POSSIBILITY OF SUCH DAMAGE.
36 1.27 scw */
37 1.27 scw /*
38 1.1 chris * Copyright (c) 1994-1997 Mark Brinicombe.
39 1.1 chris * Copyright (c) 1994 Brini.
40 1.1 chris * All rights reserved.
41 1.1 chris *
42 1.1 chris * This code is derived from software written for Brini by Mark Brinicombe
43 1.1 chris *
44 1.1 chris * Redistribution and use in source and binary forms, with or without
45 1.1 chris * modification, are permitted provided that the following conditions
46 1.1 chris * are met:
47 1.1 chris * 1. Redistributions of source code must retain the above copyright
48 1.1 chris * notice, this list of conditions and the following disclaimer.
49 1.1 chris * 2. Redistributions in binary form must reproduce the above copyright
50 1.1 chris * notice, this list of conditions and the following disclaimer in the
51 1.1 chris * documentation and/or other materials provided with the distribution.
52 1.1 chris * 3. All advertising materials mentioning features or use of this software
53 1.1 chris * must display the following acknowledgement:
54 1.1 chris * This product includes software developed by Brini.
55 1.1 chris * 4. The name of the company nor the name of the author may be used to
56 1.1 chris * endorse or promote products derived from this software without specific
57 1.1 chris * prior written permission.
58 1.1 chris *
59 1.1 chris * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
60 1.1 chris * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
61 1.1 chris * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
62 1.1 chris * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
63 1.1 chris * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
64 1.1 chris * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
65 1.1 chris * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 1.1 chris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 1.1 chris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 1.1 chris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 1.1 chris * SUCH DAMAGE.
70 1.1 chris *
71 1.1 chris * RiscBSD kernel project
72 1.1 chris *
73 1.1 chris * fault.c
74 1.1 chris *
75 1.1 chris * Fault handlers
76 1.1 chris *
77 1.1 chris * Created : 28/11/94
78 1.1 chris */
79 1.1 chris
80 1.1 chris #include "opt_ddb.h"
81 1.28 briggs #include "opt_kgdb.h"
82 1.1 chris
83 1.1 chris #include <sys/types.h>
84 1.104 skrll __KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.104 2017/07/02 16:16:44 skrll Exp $");
85 1.21 bjh21
86 1.1 chris #include <sys/param.h>
87 1.1 chris #include <sys/systm.h>
88 1.1 chris #include <sys/proc.h>
89 1.1 chris #include <sys/kernel.h>
90 1.60 yamt #include <sys/kauth.h>
91 1.65 matt #include <sys/cpu.h>
92 1.90 matt #include <sys/intr.h>
93 1.1 chris
94 1.1 chris #include <uvm/uvm_extern.h>
95 1.50 rearnsha #include <uvm/uvm_stat.h>
96 1.50 rearnsha #ifdef UVMHIST
97 1.50 rearnsha #include <uvm/uvm.h>
98 1.50 rearnsha #endif
99 1.18 thorpej
100 1.90 matt #include <arm/locore.h>
101 1.1 chris
102 1.83 matt #include <machine/pcb.h>
103 1.28 briggs #if defined(DDB) || defined(KGDB)
104 1.1 chris #include <machine/db_machdep.h>
105 1.28 briggs #ifdef KGDB
106 1.28 briggs #include <sys/kgdb.h>
107 1.28 briggs #endif
108 1.28 briggs #if !defined(DDB)
109 1.28 briggs #define kdb_trap kgdb_trap
110 1.28 briggs #endif
111 1.1 chris #endif
112 1.1 chris
113 1.1 chris #include <arch/arm/arm/disassem.h>
114 1.7 chris #include <arm/arm32/machdep.h>
115 1.100 skrll
116 1.1 chris extern char fusubailout[];
117 1.1 chris
118 1.27 scw #ifdef DEBUG
119 1.27 scw int last_fault_code; /* For the benefit of pmap_fault_fixup() */
120 1.27 scw #endif
121 1.27 scw
122 1.39 scw #if defined(CPU_ARM3) || defined(CPU_ARM6) || \
123 1.39 scw defined(CPU_ARM7) || defined(CPU_ARM7TDMI)
124 1.39 scw /* These CPUs may need data/prefetch abort fixups */
125 1.39 scw #define CPU_ABORT_FIXUP_REQUIRED
126 1.39 scw #endif
127 1.7 chris
128 1.39 scw struct data_abort {
129 1.39 scw int (*func)(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
130 1.39 scw const char *desc;
131 1.39 scw };
132 1.1 chris
133 1.39 scw static int dab_fatal(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
134 1.39 scw static int dab_align(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
135 1.39 scw static int dab_buserr(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
136 1.39 scw
137 1.39 scw static const struct data_abort data_aborts[] = {
138 1.39 scw {dab_fatal, "Vector Exception"},
139 1.39 scw {dab_align, "Alignment Fault 1"},
140 1.39 scw {dab_fatal, "Terminal Exception"},
141 1.39 scw {dab_align, "Alignment Fault 3"},
142 1.39 scw {dab_buserr, "External Linefetch Abort (S)"},
143 1.39 scw {NULL, "Translation Fault (S)"},
144 1.39 scw {dab_buserr, "External Linefetch Abort (P)"},
145 1.39 scw {NULL, "Translation Fault (P)"},
146 1.39 scw {dab_buserr, "External Non-Linefetch Abort (S)"},
147 1.39 scw {NULL, "Domain Fault (S)"},
148 1.39 scw {dab_buserr, "External Non-Linefetch Abort (P)"},
149 1.39 scw {NULL, "Domain Fault (P)"},
150 1.39 scw {dab_buserr, "External Translation Abort (L1)"},
151 1.39 scw {NULL, "Permission Fault (S)"},
152 1.39 scw {dab_buserr, "External Translation Abort (L2)"},
153 1.39 scw {NULL, "Permission Fault (P)"}
154 1.39 scw };
155 1.1 chris
156 1.39 scw /* Determine if 'x' is a permission fault */
157 1.39 scw #define IS_PERMISSION_FAULT(x) \
158 1.39 scw (((1 << ((x) & FAULT_TYPE_MASK)) & \
159 1.39 scw ((1 << FAULT_PERM_P) | (1 << FAULT_PERM_S))) != 0)
160 1.1 chris
161 1.39 scw #if 0
162 1.39 scw /* maybe one day we'll do emulations */
163 1.39 scw #define TRAPSIGNAL(l,k) (*(l)->l_proc->p_emul->e_trapsignal)((l), (k))
164 1.39 scw #else
165 1.39 scw #define TRAPSIGNAL(l,k) trapsignal((l), (k))
166 1.1 chris #endif
167 1.3 thorpej
168 1.56 perry static inline void
169 1.93 matt call_trapsignal(struct lwp *l, const struct trapframe *tf, ksiginfo_t *ksi)
170 1.3 thorpej {
171 1.93 matt if (l->l_proc->p_pid == 1 || cpu_printfataltraps) {
172 1.93 matt printf("%d.%d(%s): trap: signo=%d code=%d addr=%p trap=%#x\n",
173 1.93 matt l->l_proc->p_pid, l->l_lid, l->l_proc->p_comm,
174 1.93 matt ksi->ksi_signo, ksi->ksi_code, ksi->ksi_addr,
175 1.93 matt ksi->ksi_trap);
176 1.93 matt printf("r0=%08x r1=%08x r2=%08x r3=%08x\n",
177 1.93 matt tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3);
178 1.93 matt printf("r4=%08x r5=%08x r6=%08x r7=%08x\n",
179 1.93 matt tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7);
180 1.93 matt printf("r8=%08x r9=%08x rA=%08x rB=%08x\n",
181 1.93 matt tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11);
182 1.93 matt printf("ip=%08x sp=%08x lr=%08x pc=%08x spsr=%08x\n",
183 1.93 matt tf->tf_r12, tf->tf_usr_sp, tf->tf_usr_lr, tf->tf_pc,
184 1.93 matt tf->tf_spsr);
185 1.93 matt }
186 1.3 thorpej
187 1.39 scw TRAPSIGNAL(l, ksi);
188 1.39 scw }
189 1.3 thorpej
190 1.56 perry static inline int
191 1.39 scw data_abort_fixup(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l)
192 1.39 scw {
193 1.39 scw #ifdef CPU_ABORT_FIXUP_REQUIRED
194 1.39 scw int error;
195 1.3 thorpej
196 1.48 wiz /* Call the CPU specific data abort fixup routine */
197 1.39 scw error = cpu_dataabt_fixup(tf);
198 1.39 scw if (__predict_true(error != ABORT_FIXUP_FAILED))
199 1.39 scw return (error);
200 1.3 thorpej
201 1.39 scw /*
202 1.39 scw * Oops, couldn't fix up the instruction
203 1.39 scw */
204 1.79 christos printf("%s: fixup for %s mode data abort failed.\n", __func__,
205 1.39 scw TRAP_USERMODE(tf) ? "user" : "kernel");
206 1.51 rearnsha #ifdef THUMB_CODE
207 1.51 rearnsha if (tf->tf_spsr & PSR_T_bit) {
208 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%04x, 0x%04x, insn = ",
209 1.86 skrll tf->tf_pc, *((uint16 *)(tf->tf_pc & ~1)),
210 1.86 skrll *((uint16 *)((tf->tf_pc + 2) & ~1)));
211 1.51 rearnsha }
212 1.51 rearnsha else
213 1.51 rearnsha #endif
214 1.51 rearnsha {
215 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc,
216 1.51 rearnsha *((u_int *)tf->tf_pc));
217 1.51 rearnsha }
218 1.39 scw disassemble(tf->tf_pc);
219 1.39 scw
220 1.39 scw /* Die now if this happened in kernel mode */
221 1.39 scw if (!TRAP_USERMODE(tf))
222 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
223 1.3 thorpej
224 1.39 scw return (error);
225 1.39 scw #else
226 1.39 scw return (ABORT_FIXUP_OK);
227 1.39 scw #endif /* CPU_ABORT_FIXUP_REQUIRED */
228 1.3 thorpej }
229 1.3 thorpej
230 1.1 chris void
231 1.39 scw data_abort_handler(trapframe_t *tf)
232 1.1 chris {
233 1.39 scw struct vm_map *map;
234 1.83 matt struct lwp * const l = curlwp;
235 1.83 matt struct cpu_info * const ci = curcpu();
236 1.83 matt u_int far, fsr;
237 1.39 scw vm_prot_t ftype;
238 1.1 chris void *onfault;
239 1.27 scw vaddr_t va;
240 1.39 scw int error;
241 1.34 matt ksiginfo_t ksi;
242 1.3 thorpej
243 1.97 matt UVMHIST_FUNC(__func__);
244 1.98 matt UVMHIST_CALLED(maphist);
245 1.50 rearnsha
246 1.39 scw /* Grab FAR/FSR before enabling interrupts */
247 1.39 scw far = cpu_faultaddress();
248 1.39 scw fsr = cpu_faultstatus();
249 1.1 chris
250 1.39 scw /* Update vmmeter statistics */
251 1.83 matt ci->ci_data.cpu_ntrap++;
252 1.1 chris
253 1.39 scw /* Re-enable interrupts if they were enabled previously */
254 1.101 matt KASSERT(!TRAP_USERMODE(tf) || VALID_R15_PSR(tf->tf_pc, tf->tf_spsr));
255 1.101 matt #ifdef __NO_FIQ
256 1.101 matt if (__predict_true((tf->tf_spsr & I32_bit) != I32_bit))
257 1.101 matt restore_interrupts(tf->tf_spsr & IF32_bits);
258 1.101 matt #else
259 1.72 matt if (__predict_true((tf->tf_spsr & IF32_bits) != IF32_bits))
260 1.72 matt restore_interrupts(tf->tf_spsr & IF32_bits);
261 1.101 matt #endif
262 1.1 chris
263 1.67 matt /* Get the current lwp structure */
264 1.1 chris
265 1.98 matt UVMHIST_LOG(maphist, " (l=%#x, far=%#x, fsr=%#x",
266 1.98 matt l, far, fsr, 0);
267 1.98 matt UVMHIST_LOG(maphist, " tf=%#x, pc=%#x)",
268 1.98 matt tf, tf->tf_pc, 0, 0);
269 1.50 rearnsha
270 1.39 scw /* Data abort came from user mode? */
271 1.83 matt bool user = (TRAP_USERMODE(tf) != 0);
272 1.83 matt if (user)
273 1.61 ad LWP_CACHE_CREDS(l, l->l_proc);
274 1.1 chris
275 1.39 scw /* Grab the current pcb */
276 1.83 matt struct pcb * const pcb = lwp_getpcb(l);
277 1.1 chris
278 1.85 matt curcpu()->ci_abt_evs[fsr & FAULT_TYPE_MASK].ev_count++;
279 1.85 matt
280 1.39 scw /* Invoke the appropriate handler, if necessary */
281 1.39 scw if (__predict_false(data_aborts[fsr & FAULT_TYPE_MASK].func != NULL)) {
282 1.79 christos #ifdef DIAGNOSTIC
283 1.79 christos printf("%s: data_aborts fsr=0x%x far=0x%x\n",
284 1.79 christos __func__, fsr, far);
285 1.79 christos #endif
286 1.39 scw if ((data_aborts[fsr & FAULT_TYPE_MASK].func)(tf, fsr, far,
287 1.39 scw l, &ksi))
288 1.39 scw goto do_trapsignal;
289 1.39 scw goto out;
290 1.39 scw }
291 1.1 chris
292 1.1 chris /*
293 1.39 scw * At this point, we're dealing with one of the following data aborts:
294 1.39 scw *
295 1.39 scw * FAULT_TRANS_S - Translation -- Section
296 1.39 scw * FAULT_TRANS_P - Translation -- Page
297 1.39 scw * FAULT_DOMAIN_S - Domain -- Section
298 1.39 scw * FAULT_DOMAIN_P - Domain -- Page
299 1.39 scw * FAULT_PERM_S - Permission -- Section
300 1.39 scw * FAULT_PERM_P - Permission -- Page
301 1.39 scw *
302 1.39 scw * These are the main virtual memory-related faults signalled by
303 1.39 scw * the MMU.
304 1.1 chris */
305 1.1 chris
306 1.1 chris /* fusubailout is used by [fs]uswintr to avoid page faulting */
307 1.39 scw if (__predict_false(pcb->pcb_onfault == fusubailout)) {
308 1.39 scw tf->tf_r0 = EFAULT;
309 1.83 matt tf->tf_pc = (intptr_t) pcb->pcb_onfault;
310 1.1 chris return;
311 1.1 chris }
312 1.1 chris
313 1.104 skrll KASSERTMSG(!user || tf == lwp_trapframe(l), "tf %p vs %p", tf,
314 1.104 skrll lwp_trapframe(l));
315 1.1 chris
316 1.40 scw /*
317 1.40 scw * Make sure the Program Counter is sane. We could fall foul of
318 1.40 scw * someone executing Thumb code, in which case the PC might not
319 1.40 scw * be word-aligned. This would cause a kernel alignment fault
320 1.40 scw * further down if we have to decode the current instruction.
321 1.40 scw */
322 1.51 rearnsha #ifdef THUMB_CODE
323 1.100 skrll /*
324 1.51 rearnsha * XXX: It would be nice to be able to support Thumb in the kernel
325 1.51 rearnsha * at some point.
326 1.51 rearnsha */
327 1.51 rearnsha if (__predict_false(!user && (tf->tf_pc & 3) != 0)) {
328 1.79 christos printf("\n%s: Misaligned Kernel-mode Program Counter\n",
329 1.79 christos __func__);
330 1.51 rearnsha dab_fatal(tf, fsr, far, l, NULL);
331 1.51 rearnsha }
332 1.51 rearnsha #else
333 1.40 scw if (__predict_false((tf->tf_pc & 3) != 0)) {
334 1.40 scw if (user) {
335 1.40 scw /*
336 1.40 scw * Give the user an illegal instruction signal.
337 1.40 scw */
338 1.40 scw /* Deliver a SIGILL to the process */
339 1.40 scw KSI_INIT_TRAP(&ksi);
340 1.40 scw ksi.ksi_signo = SIGILL;
341 1.40 scw ksi.ksi_code = ILL_ILLOPC;
342 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
343 1.40 scw ksi.ksi_trap = fsr;
344 1.40 scw goto do_trapsignal;
345 1.40 scw }
346 1.40 scw
347 1.40 scw /*
348 1.40 scw * The kernel never executes Thumb code.
349 1.40 scw */
350 1.79 christos printf("\n%s: Misaligned Kernel-mode Program Counter\n",
351 1.79 christos __func__);
352 1.40 scw dab_fatal(tf, fsr, far, l, NULL);
353 1.27 scw }
354 1.51 rearnsha #endif
355 1.27 scw
356 1.48 wiz /* See if the CPU state needs to be fixed up */
357 1.41 scw switch (data_abort_fixup(tf, fsr, far, l)) {
358 1.41 scw case ABORT_FIXUP_RETURN:
359 1.41 scw return;
360 1.41 scw case ABORT_FIXUP_FAILED:
361 1.41 scw /* Deliver a SIGILL to the process */
362 1.41 scw KSI_INIT_TRAP(&ksi);
363 1.41 scw ksi.ksi_signo = SIGILL;
364 1.41 scw ksi.ksi_code = ILL_ILLOPC;
365 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
366 1.41 scw ksi.ksi_trap = fsr;
367 1.41 scw goto do_trapsignal;
368 1.41 scw default:
369 1.41 scw break;
370 1.41 scw }
371 1.41 scw
372 1.39 scw va = trunc_page((vaddr_t)far);
373 1.1 chris
374 1.27 scw /*
375 1.27 scw * It is only a kernel address space fault iff:
376 1.27 scw * 1. user == 0 and
377 1.27 scw * 2. pcb_onfault not set or
378 1.41 scw * 3. pcb_onfault set and not LDRT/LDRBT/STRT/STRBT instruction.
379 1.27 scw */
380 1.83 matt if (!user && (va >= VM_MIN_KERNEL_ADDRESS ||
381 1.41 scw (va < VM_MIN_ADDRESS && vector_page == ARM_VECTORS_LOW)) &&
382 1.41 scw __predict_true((pcb->pcb_onfault == NULL ||
383 1.93 matt (read_insn(tf->tf_pc, false) & 0x05200000) != 0x04200000))) {
384 1.39 scw map = kernel_map;
385 1.39 scw
386 1.27 scw /* Was the fault due to the FPE/IPKDB ? */
387 1.39 scw if (__predict_false((tf->tf_spsr & PSR_MODE)==PSR_UND32_MODE)) {
388 1.35 thorpej KSI_INIT_TRAP(&ksi);
389 1.34 matt ksi.ksi_signo = SIGSEGV;
390 1.39 scw ksi.ksi_code = SEGV_ACCERR;
391 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
392 1.39 scw ksi.ksi_trap = fsr;
393 1.27 scw
394 1.27 scw /*
395 1.27 scw * Force exit via userret()
396 1.39 scw * This is necessary as the FPE is an extension to
397 1.39 scw * userland that actually runs in a priveledged mode
398 1.39 scw * but uses USR mode permissions for its accesses.
399 1.27 scw */
400 1.83 matt user = true;
401 1.39 scw goto do_trapsignal;
402 1.27 scw }
403 1.70 wrstuden } else {
404 1.39 scw map = &l->l_proc->p_vmspace->vm_map;
405 1.70 wrstuden }
406 1.1 chris
407 1.27 scw /*
408 1.94 matt * We need to know whether the page should be mapped as R or R/W.
409 1.94 matt * Before ARMv6, the MMU did not give us the info as to whether the
410 1.94 matt * fault was caused by a read or a write.
411 1.39 scw *
412 1.94 matt * However, we know that a permission fault can only be the result of
413 1.94 matt * a write to a read-only location, so we can deal with those quickly.
414 1.39 scw *
415 1.94 matt * Otherwise we need to disassemble the instruction responsible to
416 1.94 matt * determine if it was a write.
417 1.27 scw */
418 1.96 skrll if (CPU_IS_ARMV6_P() || CPU_IS_ARMV7_P()) {
419 1.94 matt ftype = (fsr & FAULT_WRITE) ? VM_PROT_WRITE : VM_PROT_READ;
420 1.94 matt } else if (IS_PERMISSION_FAULT(fsr)) {
421 1.100 skrll ftype = VM_PROT_WRITE;
422 1.94 matt } else {
423 1.51 rearnsha #ifdef THUMB_CODE
424 1.51 rearnsha /* Fast track the ARM case. */
425 1.51 rearnsha if (__predict_false(tf->tf_spsr & PSR_T_bit)) {
426 1.93 matt u_int insn = read_thumb_insn(tf->tf_pc, user);
427 1.51 rearnsha u_int insn_f8 = insn & 0xf800;
428 1.51 rearnsha u_int insn_fe = insn & 0xfe00;
429 1.51 rearnsha
430 1.51 rearnsha if (insn_f8 == 0x6000 || /* STR(1) */
431 1.51 rearnsha insn_f8 == 0x7000 || /* STRB(1) */
432 1.51 rearnsha insn_f8 == 0x8000 || /* STRH(1) */
433 1.51 rearnsha insn_f8 == 0x9000 || /* STR(3) */
434 1.51 rearnsha insn_f8 == 0xc000 || /* STM */
435 1.51 rearnsha insn_fe == 0x5000 || /* STR(2) */
436 1.51 rearnsha insn_fe == 0x5200 || /* STRH(2) */
437 1.51 rearnsha insn_fe == 0x5400) /* STRB(2) */
438 1.51 rearnsha ftype = VM_PROT_WRITE;
439 1.51 rearnsha else
440 1.51 rearnsha ftype = VM_PROT_READ;
441 1.51 rearnsha }
442 1.51 rearnsha else
443 1.51 rearnsha #endif
444 1.51 rearnsha {
445 1.93 matt u_int insn = read_insn(tf->tf_pc, user);
446 1.39 scw
447 1.51 rearnsha if (((insn & 0x0c100000) == 0x04000000) || /* STR[B] */
448 1.51 rearnsha ((insn & 0x0e1000b0) == 0x000000b0) || /* STR[HD]*/
449 1.81 matt ((insn & 0x0a100000) == 0x08000000) || /* STM/CDT*/
450 1.81 matt ((insn & 0x0f9000f0) == 0x01800090)) /* STREX[BDH] */
451 1.100 skrll ftype = VM_PROT_WRITE;
452 1.51 rearnsha else if ((insn & 0x0fb00ff0) == 0x01000090)/* SWP */
453 1.100 skrll ftype = VM_PROT_READ | VM_PROT_WRITE;
454 1.51 rearnsha else
455 1.100 skrll ftype = VM_PROT_READ;
456 1.51 rearnsha }
457 1.39 scw }
458 1.39 scw
459 1.39 scw /*
460 1.39 scw * See if the fault is as a result of ref/mod emulation,
461 1.39 scw * or domain mismatch.
462 1.39 scw */
463 1.39 scw #ifdef DEBUG
464 1.39 scw last_fault_code = fsr;
465 1.1 chris #endif
466 1.42 briggs if (pmap_fault_fixup(map->pmap, va, ftype, user)) {
467 1.98 matt UVMHIST_LOG(maphist, " <- ref/mod emul", 0, 0, 0, 0);
468 1.27 scw goto out;
469 1.42 briggs }
470 1.1 chris
471 1.67 matt if (__predict_false(curcpu()->ci_intr_depth > 0)) {
472 1.45 scw if (pcb->pcb_onfault) {
473 1.45 scw tf->tf_r0 = EINVAL;
474 1.45 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
475 1.45 scw return;
476 1.45 scw }
477 1.39 scw printf("\nNon-emulated page fault with intr_depth > 0\n");
478 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
479 1.27 scw }
480 1.1 chris
481 1.27 scw onfault = pcb->pcb_onfault;
482 1.27 scw pcb->pcb_onfault = NULL;
483 1.57 he error = uvm_fault(map, va, ftype);
484 1.27 scw pcb->pcb_onfault = onfault;
485 1.39 scw
486 1.39 scw if (__predict_true(error == 0)) {
487 1.39 scw if (user)
488 1.39 scw uvm_grow(l->l_proc, va); /* Record any stack growth */
489 1.77 chs else
490 1.77 chs ucas_ras_check(tf);
491 1.98 matt UVMHIST_LOG(maphist, " <- uvm", 0, 0, 0, 0);
492 1.27 scw goto out;
493 1.27 scw }
494 1.39 scw
495 1.27 scw if (user == 0) {
496 1.27 scw if (pcb->pcb_onfault) {
497 1.39 scw tf->tf_r0 = error;
498 1.39 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
499 1.39 scw return;
500 1.1 chris }
501 1.39 scw
502 1.58 drochner printf("\nuvm_fault(%p, %lx, %x) -> %x\n", map, va, ftype,
503 1.39 scw error);
504 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
505 1.27 scw }
506 1.1 chris
507 1.43 scw KSI_INIT_TRAP(&ksi);
508 1.43 scw
509 1.103 martin switch (error) {
510 1.103 martin case ENOMEM:
511 1.39 scw printf("UVM: pid %d (%s), uid %d killed: "
512 1.39 scw "out of swap\n", l->l_proc->p_pid, l->l_proc->p_comm,
513 1.62 ad l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1);
514 1.43 scw ksi.ksi_signo = SIGKILL;
515 1.103 martin break;
516 1.103 martin case EACCES:
517 1.103 martin ksi.ksi_signo = SIGSEGV;
518 1.103 martin ksi.ksi_code = SEGV_ACCERR;
519 1.103 martin break;
520 1.103 martin case EINVAL:
521 1.103 martin ksi.ksi_signo = SIGBUS;
522 1.103 martin ksi.ksi_code = BUS_ADRERR;
523 1.103 martin break;
524 1.103 martin default:
525 1.43 scw ksi.ksi_signo = SIGSEGV;
526 1.103 martin ksi.ksi_code = SEGV_MAPERR;
527 1.103 martin break;
528 1.103 martin }
529 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
530 1.39 scw ksi.ksi_trap = fsr;
531 1.98 matt UVMHIST_LOG(maphist, " <- error (%d)", error, 0, 0, 0);
532 1.39 scw
533 1.39 scw do_trapsignal:
534 1.93 matt call_trapsignal(l, tf, &ksi);
535 1.39 scw out:
536 1.39 scw /* If returning to user mode, make sure to invoke userret() */
537 1.39 scw if (user)
538 1.39 scw userret(l);
539 1.39 scw }
540 1.39 scw
541 1.39 scw /*
542 1.39 scw * dab_fatal() handles the following data aborts:
543 1.39 scw *
544 1.39 scw * FAULT_WRTBUF_0 - Vector Exception
545 1.39 scw * FAULT_WRTBUF_1 - Terminal Exception
546 1.39 scw *
547 1.39 scw * We should never see these on a properly functioning system.
548 1.39 scw *
549 1.39 scw * This function is also called by the other handlers if they
550 1.39 scw * detect a fatal problem.
551 1.39 scw *
552 1.39 scw * Note: If 'l' is NULL, we assume we're dealing with a prefetch abort.
553 1.39 scw */
554 1.39 scw static int
555 1.39 scw dab_fatal(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l, ksiginfo_t *ksi)
556 1.39 scw {
557 1.83 matt const char * const mode = TRAP_USERMODE(tf) ? "user" : "kernel";
558 1.39 scw
559 1.39 scw if (l != NULL) {
560 1.39 scw printf("Fatal %s mode data abort: '%s'\n", mode,
561 1.39 scw data_aborts[fsr & FAULT_TYPE_MASK].desc);
562 1.44 scw printf("trapframe: %p\nFSR=%08x, FAR=", tf, fsr);
563 1.39 scw if ((fsr & FAULT_IMPRECISE) == 0)
564 1.44 scw printf("%08x, ", far);
565 1.39 scw else
566 1.44 scw printf("Invalid, ");
567 1.44 scw printf("spsr=%08x\n", tf->tf_spsr);
568 1.39 scw } else {
569 1.44 scw printf("Fatal %s mode prefetch abort at 0x%08x\n",
570 1.44 scw mode, tf->tf_pc);
571 1.44 scw printf("trapframe: %p, spsr=%08x\n", tf, tf->tf_spsr);
572 1.44 scw }
573 1.44 scw
574 1.44 scw printf("r0 =%08x, r1 =%08x, r2 =%08x, r3 =%08x\n",
575 1.44 scw tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3);
576 1.44 scw printf("r4 =%08x, r5 =%08x, r6 =%08x, r7 =%08x\n",
577 1.44 scw tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7);
578 1.44 scw printf("r8 =%08x, r9 =%08x, r10=%08x, r11=%08x\n",
579 1.44 scw tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11);
580 1.44 scw printf("r12=%08x, ", tf->tf_r12);
581 1.44 scw
582 1.44 scw if (TRAP_USERMODE(tf))
583 1.44 scw printf("usp=%08x, ulr=%08x",
584 1.44 scw tf->tf_usr_sp, tf->tf_usr_lr);
585 1.44 scw else
586 1.44 scw printf("ssp=%08x, slr=%08x",
587 1.44 scw tf->tf_svc_sp, tf->tf_svc_lr);
588 1.44 scw printf(", pc =%08x\n\n", tf->tf_pc);
589 1.34 matt
590 1.39 scw #if defined(DDB) || defined(KGDB)
591 1.39 scw kdb_trap(T_FAULT, tf);
592 1.34 matt #endif
593 1.39 scw panic("Fatal abort");
594 1.39 scw /*NOTREACHED*/
595 1.39 scw }
596 1.39 scw
597 1.39 scw /*
598 1.39 scw * dab_align() handles the following data aborts:
599 1.39 scw *
600 1.39 scw * FAULT_ALIGN_0 - Alignment fault
601 1.39 scw * FAULT_ALIGN_0 - Alignment fault
602 1.39 scw *
603 1.39 scw * These faults are fatal if they happen in kernel mode. Otherwise, we
604 1.39 scw * deliver a bus error to the process.
605 1.39 scw */
606 1.39 scw static int
607 1.39 scw dab_align(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l, ksiginfo_t *ksi)
608 1.39 scw {
609 1.39 scw /* Alignment faults are always fatal if they occur in kernel mode */
610 1.39 scw if (!TRAP_USERMODE(tf))
611 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
612 1.39 scw
613 1.39 scw /* pcb_onfault *must* be NULL at this point */
614 1.83 matt KDASSERT(((struct pcb *)lwp_getpcb(l))->pcb_onfault == NULL);
615 1.39 scw
616 1.48 wiz /* See if the CPU state needs to be fixed up */
617 1.39 scw (void) data_abort_fixup(tf, fsr, far, l);
618 1.39 scw
619 1.39 scw /* Deliver a bus error signal to the process */
620 1.39 scw KSI_INIT_TRAP(ksi);
621 1.39 scw ksi->ksi_signo = SIGBUS;
622 1.39 scw ksi->ksi_code = BUS_ADRALN;
623 1.86 skrll ksi->ksi_addr = (uint32_t *)(intptr_t)far;
624 1.39 scw ksi->ksi_trap = fsr;
625 1.39 scw
626 1.104 skrll KASSERTMSG(tf == lwp_trapframe(l), "tf %p vs %p", tf, lwp_trapframe(l));
627 1.39 scw
628 1.39 scw return (1);
629 1.39 scw }
630 1.39 scw
631 1.39 scw /*
632 1.39 scw * dab_buserr() handles the following data aborts:
633 1.39 scw *
634 1.39 scw * FAULT_BUSERR_0 - External Abort on Linefetch -- Section
635 1.39 scw * FAULT_BUSERR_1 - External Abort on Linefetch -- Page
636 1.39 scw * FAULT_BUSERR_2 - External Abort on Non-linefetch -- Section
637 1.39 scw * FAULT_BUSERR_3 - External Abort on Non-linefetch -- Page
638 1.39 scw * FAULT_BUSTRNL1 - External abort on Translation -- Level 1
639 1.39 scw * FAULT_BUSTRNL2 - External abort on Translation -- Level 2
640 1.39 scw *
641 1.39 scw * If pcb_onfault is set, flag the fault and return to the handler.
642 1.39 scw * If the fault occurred in user mode, give the process a SIGBUS.
643 1.39 scw *
644 1.39 scw * Note: On XScale, FAULT_BUSERR_0, FAULT_BUSERR_1, and FAULT_BUSERR_2
645 1.39 scw * can be flagged as imprecise in the FSR. This causes a real headache
646 1.39 scw * since some of the machine state is lost. In this case, tf->tf_pc
647 1.39 scw * may not actually point to the offending instruction. In fact, if
648 1.39 scw * we've taken a double abort fault, it generally points somewhere near
649 1.39 scw * the top of "data_abort_entry" in exception.S.
650 1.39 scw *
651 1.39 scw * In all other cases, these data aborts are considered fatal.
652 1.39 scw */
653 1.39 scw static int
654 1.39 scw dab_buserr(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l,
655 1.39 scw ksiginfo_t *ksi)
656 1.39 scw {
657 1.73 rmind struct pcb *pcb = lwp_getpcb(l);
658 1.39 scw
659 1.39 scw #ifdef __XSCALE__
660 1.39 scw if ((fsr & FAULT_IMPRECISE) != 0 &&
661 1.39 scw (tf->tf_spsr & PSR_MODE) == PSR_ABT32_MODE) {
662 1.39 scw /*
663 1.39 scw * Oops, an imprecise, double abort fault. We've lost the
664 1.39 scw * r14_abt/spsr_abt values corresponding to the original
665 1.39 scw * abort, and the spsr saved in the trapframe indicates
666 1.39 scw * ABT mode.
667 1.39 scw */
668 1.39 scw tf->tf_spsr &= ~PSR_MODE;
669 1.39 scw
670 1.39 scw /*
671 1.39 scw * We use a simple heuristic to determine if the double abort
672 1.39 scw * happened as a result of a kernel or user mode access.
673 1.39 scw * If the current trapframe is at the top of the kernel stack,
674 1.39 scw * the fault _must_ have come from user mode.
675 1.39 scw */
676 1.87 matt if (tf != ((trapframe_t *)pcb->pcb_ksp) - 1) {
677 1.39 scw /*
678 1.39 scw * Kernel mode. We're either about to die a
679 1.39 scw * spectacular death, or pcb_onfault will come
680 1.39 scw * to our rescue. Either way, the current value
681 1.39 scw * of tf->tf_pc is irrelevant.
682 1.39 scw */
683 1.39 scw tf->tf_spsr |= PSR_SVC32_MODE;
684 1.39 scw if (pcb->pcb_onfault == NULL)
685 1.39 scw printf("\nKernel mode double abort!\n");
686 1.39 scw } else {
687 1.39 scw /*
688 1.39 scw * User mode. We've lost the program counter at the
689 1.39 scw * time of the fault (not that it was accurate anyway;
690 1.39 scw * it's not called an imprecise fault for nothing).
691 1.39 scw * About all we can do is copy r14_usr to tf_pc and
692 1.39 scw * hope for the best. The process is about to get a
693 1.39 scw * SIGBUS, so it's probably history anyway.
694 1.39 scw */
695 1.39 scw tf->tf_spsr |= PSR_USR32_MODE;
696 1.39 scw tf->tf_pc = tf->tf_usr_lr;
697 1.51 rearnsha #ifdef THUMB_CODE
698 1.51 rearnsha tf->tf_spsr &= ~PSR_T_bit;
699 1.51 rearnsha if (tf->tf_usr_lr & 1)
700 1.51 rearnsha tf->tf_spsr |= PSR_T_bit;
701 1.51 rearnsha #endif
702 1.39 scw }
703 1.39 scw }
704 1.39 scw
705 1.39 scw /* FAR is invalid for imprecise exceptions */
706 1.39 scw if ((fsr & FAULT_IMPRECISE) != 0)
707 1.39 scw far = 0;
708 1.39 scw #endif /* __XSCALE__ */
709 1.39 scw
710 1.39 scw if (pcb->pcb_onfault) {
711 1.39 scw KDASSERT(TRAP_USERMODE(tf) == 0);
712 1.39 scw tf->tf_r0 = EFAULT;
713 1.39 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
714 1.39 scw return (0);
715 1.39 scw }
716 1.39 scw
717 1.48 wiz /* See if the CPU state needs to be fixed up */
718 1.39 scw (void) data_abort_fixup(tf, fsr, far, l);
719 1.39 scw
720 1.39 scw /*
721 1.39 scw * At this point, if the fault happened in kernel mode, we're toast
722 1.39 scw */
723 1.39 scw if (!TRAP_USERMODE(tf))
724 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
725 1.39 scw
726 1.39 scw /* Deliver a bus error signal to the process */
727 1.39 scw KSI_INIT_TRAP(ksi);
728 1.39 scw ksi->ksi_signo = SIGBUS;
729 1.39 scw ksi->ksi_code = BUS_ADRERR;
730 1.86 skrll ksi->ksi_addr = (uint32_t *)(intptr_t)far;
731 1.39 scw ksi->ksi_trap = fsr;
732 1.39 scw
733 1.104 skrll KASSERTMSG(tf == lwp_trapframe(l), "tf %p vs %p", tf, lwp_trapframe(l));
734 1.27 scw
735 1.39 scw return (1);
736 1.1 chris }
737 1.1 chris
738 1.56 perry static inline int
739 1.39 scw prefetch_abort_fixup(trapframe_t *tf)
740 1.39 scw {
741 1.39 scw #ifdef CPU_ABORT_FIXUP_REQUIRED
742 1.39 scw int error;
743 1.39 scw
744 1.48 wiz /* Call the CPU specific prefetch abort fixup routine */
745 1.39 scw error = cpu_prefetchabt_fixup(tf);
746 1.39 scw if (__predict_true(error != ABORT_FIXUP_FAILED))
747 1.39 scw return (error);
748 1.39 scw
749 1.39 scw /*
750 1.39 scw * Oops, couldn't fix up the instruction
751 1.39 scw */
752 1.79 christos printf("%s: fixup for %s mode prefetch abort failed.\n", __func__,
753 1.39 scw TRAP_USERMODE(tf) ? "user" : "kernel");
754 1.51 rearnsha #ifdef THUMB_CODE
755 1.51 rearnsha if (tf->tf_spsr & PSR_T_bit) {
756 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%04x, 0x%04x, insn = ",
757 1.86 skrll tf->tf_pc, *((uint16 *)(tf->tf_pc & ~1)),
758 1.86 skrll *((uint16 *)((tf->tf_pc + 2) & ~1)));
759 1.51 rearnsha }
760 1.51 rearnsha else
761 1.51 rearnsha #endif
762 1.51 rearnsha {
763 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc,
764 1.51 rearnsha *((u_int *)tf->tf_pc));
765 1.51 rearnsha }
766 1.39 scw disassemble(tf->tf_pc);
767 1.39 scw
768 1.39 scw /* Die now if this happened in kernel mode */
769 1.39 scw if (!TRAP_USERMODE(tf))
770 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
771 1.39 scw
772 1.39 scw return (error);
773 1.39 scw #else
774 1.39 scw return (ABORT_FIXUP_OK);
775 1.39 scw #endif /* CPU_ABORT_FIXUP_REQUIRED */
776 1.39 scw }
777 1.1 chris
778 1.1 chris /*
779 1.39 scw * void prefetch_abort_handler(trapframe_t *tf)
780 1.1 chris *
781 1.1 chris * Abort handler called when instruction execution occurs at
782 1.1 chris * a non existent or restricted (access permissions) memory page.
783 1.1 chris * If the address is invalid and we were in SVC mode then panic as
784 1.1 chris * the kernel should never prefetch abort.
785 1.1 chris * If the address is invalid and the page is mapped then the user process
786 1.1 chris * does no have read permission so send it a signal.
787 1.1 chris * Otherwise fault the page in and try again.
788 1.1 chris */
789 1.1 chris void
790 1.39 scw prefetch_abort_handler(trapframe_t *tf)
791 1.1 chris {
792 1.26 thorpej struct lwp *l;
793 1.91 christos struct pcb *pcb __diagused;
794 1.14 thorpej struct vm_map *map;
795 1.14 thorpej vaddr_t fault_pc, va;
796 1.39 scw ksiginfo_t ksi;
797 1.61 ad int error, user;
798 1.39 scw
799 1.97 matt UVMHIST_FUNC(__func__);
800 1.98 matt UVMHIST_CALLED(maphist);
801 1.50 rearnsha
802 1.39 scw /* Update vmmeter statistics */
803 1.78 matt curcpu()->ci_data.cpu_ntrap++;
804 1.1 chris
805 1.61 ad l = curlwp;
806 1.73 rmind pcb = lwp_getpcb(l);
807 1.61 ad
808 1.61 ad if ((user = TRAP_USERMODE(tf)) != 0)
809 1.61 ad LWP_CACHE_CREDS(l, l->l_proc);
810 1.61 ad
811 1.1 chris /*
812 1.1 chris * Enable IRQ's (disabled by the abort) This always comes
813 1.1 chris * from user mode so we know interrupts were not disabled.
814 1.1 chris * But we check anyway.
815 1.1 chris */
816 1.101 matt KASSERT(!TRAP_USERMODE(tf) || VALID_R15_PSR(tf->tf_pc, tf->tf_spsr));
817 1.101 matt #ifdef __NO_FIQ
818 1.101 matt if (__predict_true((tf->tf_spsr & I32_bit) != I32_bit))
819 1.72 matt restore_interrupts(tf->tf_spsr & IF32_bits);
820 1.101 matt #else
821 1.101 matt if (__predict_true((tf->tf_spsr & IF32_bits) != IF32_bits))
822 1.101 matt restore_interrupts(tf->tf_spsr & IF32_bits);
823 1.101 matt #endif
824 1.1 chris
825 1.48 wiz /* See if the CPU state needs to be fixed up */
826 1.39 scw switch (prefetch_abort_fixup(tf)) {
827 1.39 scw case ABORT_FIXUP_RETURN:
828 1.101 matt KASSERT(!TRAP_USERMODE(tf) || VALID_R15_PSR(tf->tf_pc, tf->tf_spsr));
829 1.1 chris return;
830 1.39 scw case ABORT_FIXUP_FAILED:
831 1.39 scw /* Deliver a SIGILL to the process */
832 1.39 scw KSI_INIT_TRAP(&ksi);
833 1.39 scw ksi.ksi_signo = SIGILL;
834 1.39 scw ksi.ksi_code = ILL_ILLOPC;
835 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) tf->tf_pc;
836 1.104 skrll KASSERTMSG(tf == lwp_trapframe(l), "tf %p vs %p", tf,
837 1.104 skrll lwp_trapframe(l));
838 1.39 scw goto do_trapsignal;
839 1.39 scw default:
840 1.39 scw break;
841 1.1 chris }
842 1.1 chris
843 1.39 scw /* Prefetch aborts cannot happen in kernel mode */
844 1.61 ad if (__predict_false(!user))
845 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
846 1.1 chris
847 1.4 thorpej /* Get fault address */
848 1.39 scw fault_pc = tf->tf_pc;
849 1.104 skrll KASSERTMSG(tf == lwp_trapframe(l), "tf %p vs %p", tf, lwp_trapframe(l));
850 1.98 matt UVMHIST_LOG(maphist, " (pc=0x%x, l=0x%x, tf=0x%x)",
851 1.98 matt fault_pc, l, tf, 0);
852 1.14 thorpej
853 1.1 chris /* Ok validate the address, can only execute in USER space */
854 1.39 scw if (__predict_false(fault_pc >= VM_MAXUSER_ADDRESS ||
855 1.39 scw (fault_pc < VM_MIN_ADDRESS && vector_page == ARM_VECTORS_LOW))) {
856 1.35 thorpej KSI_INIT_TRAP(&ksi);
857 1.34 matt ksi.ksi_signo = SIGSEGV;
858 1.34 matt ksi.ksi_code = SEGV_ACCERR;
859 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) fault_pc;
860 1.34 matt ksi.ksi_trap = fault_pc;
861 1.39 scw goto do_trapsignal;
862 1.39 scw }
863 1.34 matt
864 1.39 scw map = &l->l_proc->p_vmspace->vm_map;
865 1.39 scw va = trunc_page(fault_pc);
866 1.1 chris
867 1.27 scw /*
868 1.27 scw * See if the pmap can handle this fault on its own...
869 1.27 scw */
870 1.39 scw #ifdef DEBUG
871 1.39 scw last_fault_code = -1;
872 1.39 scw #endif
873 1.88 matt if (pmap_fault_fixup(map->pmap, va, VM_PROT_READ|VM_PROT_EXECUTE, 1)) {
874 1.98 matt UVMHIST_LOG (maphist, " <- emulated", 0, 0, 0, 0);
875 1.39 scw goto out;
876 1.50 rearnsha }
877 1.27 scw
878 1.39 scw #ifdef DIAGNOSTIC
879 1.84 matt if (__predict_false(curcpu()->ci_intr_depth > 0)) {
880 1.39 scw printf("\nNon-emulated prefetch abort with intr_depth > 0\n");
881 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
882 1.39 scw }
883 1.1 chris #endif
884 1.72 matt
885 1.76 chs KASSERT(pcb->pcb_onfault == NULL);
886 1.99 matt error = uvm_fault(map, va, VM_PROT_READ|VM_PROT_EXECUTE);
887 1.53 joff
888 1.50 rearnsha if (__predict_true(error == 0)) {
889 1.98 matt UVMHIST_LOG (maphist, " <- uvm", 0, 0, 0, 0);
890 1.39 scw goto out;
891 1.50 rearnsha }
892 1.43 scw KSI_INIT_TRAP(&ksi);
893 1.43 scw
894 1.98 matt UVMHIST_LOG (maphist, " <- fatal (%d)", error, 0, 0, 0);
895 1.98 matt
896 1.39 scw if (error == ENOMEM) {
897 1.39 scw printf("UVM: pid %d (%s), uid %d killed: "
898 1.39 scw "out of swap\n", l->l_proc->p_pid, l->l_proc->p_comm,
899 1.62 ad l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1);
900 1.43 scw ksi.ksi_signo = SIGKILL;
901 1.43 scw } else
902 1.43 scw ksi.ksi_signo = SIGSEGV;
903 1.1 chris
904 1.39 scw ksi.ksi_code = SEGV_MAPERR;
905 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) fault_pc;
906 1.39 scw ksi.ksi_trap = fault_pc;
907 1.39 scw
908 1.39 scw do_trapsignal:
909 1.93 matt call_trapsignal(l, tf, &ksi);
910 1.39 scw
911 1.39 scw out:
912 1.101 matt KASSERT(!TRAP_USERMODE(tf) || VALID_R15_PSR(tf->tf_pc, tf->tf_spsr));
913 1.39 scw userret(l);
914 1.39 scw }
915 1.39 scw
916 1.39 scw /*
917 1.39 scw * Tentatively read an 8, 16, or 32-bit value from 'addr'.
918 1.39 scw * If the read succeeds, the value is written to 'rptr' and zero is returned.
919 1.39 scw * Else, return EFAULT.
920 1.39 scw */
921 1.39 scw int
922 1.39 scw badaddr_read(void *addr, size_t size, void *rptr)
923 1.39 scw {
924 1.39 scw extern int badaddr_read_1(const uint8_t *, uint8_t *);
925 1.39 scw extern int badaddr_read_2(const uint16_t *, uint16_t *);
926 1.39 scw extern int badaddr_read_4(const uint32_t *, uint32_t *);
927 1.39 scw union {
928 1.39 scw uint8_t v1;
929 1.39 scw uint16_t v2;
930 1.39 scw uint32_t v4;
931 1.39 scw } u;
932 1.47 scw int rv, s;
933 1.39 scw
934 1.39 scw cpu_drain_writebuf();
935 1.39 scw
936 1.47 scw s = splhigh();
937 1.47 scw
938 1.39 scw /* Read from the test address. */
939 1.39 scw switch (size) {
940 1.39 scw case sizeof(uint8_t):
941 1.39 scw rv = badaddr_read_1(addr, &u.v1);
942 1.39 scw if (rv == 0 && rptr)
943 1.39 scw *(uint8_t *) rptr = u.v1;
944 1.39 scw break;
945 1.39 scw
946 1.39 scw case sizeof(uint16_t):
947 1.39 scw rv = badaddr_read_2(addr, &u.v2);
948 1.39 scw if (rv == 0 && rptr)
949 1.39 scw *(uint16_t *) rptr = u.v2;
950 1.39 scw break;
951 1.39 scw
952 1.39 scw case sizeof(uint32_t):
953 1.39 scw rv = badaddr_read_4(addr, &u.v4);
954 1.39 scw if (rv == 0 && rptr)
955 1.39 scw *(uint32_t *) rptr = u.v4;
956 1.39 scw break;
957 1.39 scw
958 1.39 scw default:
959 1.82 matt panic("%s: invalid size (%zu)", __func__, size);
960 1.34 matt }
961 1.39 scw
962 1.47 scw splx(s);
963 1.47 scw
964 1.39 scw /* Return EFAULT if the address was invalid, else zero */
965 1.39 scw return (rv);
966 1.1 chris }
967