fault.c revision 1.107 1 1.107 maxv /* $NetBSD: fault.c,v 1.107 2018/08/10 16:17:30 maxv Exp $ */
2 1.1 chris
3 1.1 chris /*
4 1.27 scw * Copyright 2003 Wasabi Systems, Inc.
5 1.27 scw * All rights reserved.
6 1.27 scw *
7 1.27 scw * Written by Steve C. Woodford for Wasabi Systems, Inc.
8 1.27 scw *
9 1.27 scw * Redistribution and use in source and binary forms, with or without
10 1.27 scw * modification, are permitted provided that the following conditions
11 1.27 scw * are met:
12 1.27 scw * 1. Redistributions of source code must retain the above copyright
13 1.27 scw * notice, this list of conditions and the following disclaimer.
14 1.27 scw * 2. Redistributions in binary form must reproduce the above copyright
15 1.27 scw * notice, this list of conditions and the following disclaimer in the
16 1.27 scw * documentation and/or other materials provided with the distribution.
17 1.27 scw * 3. All advertising materials mentioning features or use of this software
18 1.27 scw * must display the following acknowledgement:
19 1.27 scw * This product includes software developed for the NetBSD Project by
20 1.27 scw * Wasabi Systems, Inc.
21 1.27 scw * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.27 scw * or promote products derived from this software without specific prior
23 1.27 scw * written permission.
24 1.27 scw *
25 1.27 scw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.27 scw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.27 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.27 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.27 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.27 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.27 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.27 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.27 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.27 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.27 scw * POSSIBILITY OF SUCH DAMAGE.
36 1.27 scw */
37 1.27 scw /*
38 1.1 chris * Copyright (c) 1994-1997 Mark Brinicombe.
39 1.1 chris * Copyright (c) 1994 Brini.
40 1.1 chris * All rights reserved.
41 1.1 chris *
42 1.1 chris * This code is derived from software written for Brini by Mark Brinicombe
43 1.1 chris *
44 1.1 chris * Redistribution and use in source and binary forms, with or without
45 1.1 chris * modification, are permitted provided that the following conditions
46 1.1 chris * are met:
47 1.1 chris * 1. Redistributions of source code must retain the above copyright
48 1.1 chris * notice, this list of conditions and the following disclaimer.
49 1.1 chris * 2. Redistributions in binary form must reproduce the above copyright
50 1.1 chris * notice, this list of conditions and the following disclaimer in the
51 1.1 chris * documentation and/or other materials provided with the distribution.
52 1.1 chris * 3. All advertising materials mentioning features or use of this software
53 1.1 chris * must display the following acknowledgement:
54 1.1 chris * This product includes software developed by Brini.
55 1.1 chris * 4. The name of the company nor the name of the author may be used to
56 1.1 chris * endorse or promote products derived from this software without specific
57 1.1 chris * prior written permission.
58 1.1 chris *
59 1.1 chris * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
60 1.1 chris * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
61 1.1 chris * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
62 1.1 chris * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
63 1.1 chris * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
64 1.1 chris * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
65 1.1 chris * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 1.1 chris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 1.1 chris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 1.1 chris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 1.1 chris * SUCH DAMAGE.
70 1.1 chris *
71 1.1 chris * RiscBSD kernel project
72 1.1 chris *
73 1.1 chris * fault.c
74 1.1 chris *
75 1.1 chris * Fault handlers
76 1.1 chris *
77 1.1 chris * Created : 28/11/94
78 1.1 chris */
79 1.1 chris
80 1.1 chris #include "opt_ddb.h"
81 1.28 briggs #include "opt_kgdb.h"
82 1.1 chris
83 1.1 chris #include <sys/types.h>
84 1.107 maxv __KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.107 2018/08/10 16:17:30 maxv Exp $");
85 1.21 bjh21
86 1.1 chris #include <sys/param.h>
87 1.1 chris #include <sys/systm.h>
88 1.1 chris #include <sys/proc.h>
89 1.1 chris #include <sys/kernel.h>
90 1.60 yamt #include <sys/kauth.h>
91 1.65 matt #include <sys/cpu.h>
92 1.90 matt #include <sys/intr.h>
93 1.1 chris
94 1.1 chris #include <uvm/uvm_extern.h>
95 1.50 rearnsha #include <uvm/uvm_stat.h>
96 1.50 rearnsha #ifdef UVMHIST
97 1.50 rearnsha #include <uvm/uvm.h>
98 1.50 rearnsha #endif
99 1.18 thorpej
100 1.90 matt #include <arm/locore.h>
101 1.1 chris
102 1.83 matt #include <machine/pcb.h>
103 1.28 briggs #if defined(DDB) || defined(KGDB)
104 1.1 chris #include <machine/db_machdep.h>
105 1.28 briggs #ifdef KGDB
106 1.28 briggs #include <sys/kgdb.h>
107 1.28 briggs #endif
108 1.28 briggs #if !defined(DDB)
109 1.28 briggs #define kdb_trap kgdb_trap
110 1.28 briggs #endif
111 1.1 chris #endif
112 1.1 chris
113 1.1 chris #include <arch/arm/arm/disassem.h>
114 1.7 chris #include <arm/arm32/machdep.h>
115 1.100 skrll
116 1.1 chris extern char fusubailout[];
117 1.1 chris
118 1.27 scw #ifdef DEBUG
119 1.27 scw int last_fault_code; /* For the benefit of pmap_fault_fixup() */
120 1.27 scw #endif
121 1.27 scw
122 1.107 maxv #if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI)
123 1.39 scw /* These CPUs may need data/prefetch abort fixups */
124 1.39 scw #define CPU_ABORT_FIXUP_REQUIRED
125 1.39 scw #endif
126 1.7 chris
127 1.39 scw struct data_abort {
128 1.39 scw int (*func)(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
129 1.39 scw const char *desc;
130 1.39 scw };
131 1.1 chris
132 1.39 scw static int dab_fatal(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
133 1.39 scw static int dab_align(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
134 1.39 scw static int dab_buserr(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
135 1.39 scw
136 1.39 scw static const struct data_abort data_aborts[] = {
137 1.39 scw {dab_fatal, "Vector Exception"},
138 1.39 scw {dab_align, "Alignment Fault 1"},
139 1.39 scw {dab_fatal, "Terminal Exception"},
140 1.39 scw {dab_align, "Alignment Fault 3"},
141 1.39 scw {dab_buserr, "External Linefetch Abort (S)"},
142 1.39 scw {NULL, "Translation Fault (S)"},
143 1.39 scw {dab_buserr, "External Linefetch Abort (P)"},
144 1.39 scw {NULL, "Translation Fault (P)"},
145 1.39 scw {dab_buserr, "External Non-Linefetch Abort (S)"},
146 1.39 scw {NULL, "Domain Fault (S)"},
147 1.39 scw {dab_buserr, "External Non-Linefetch Abort (P)"},
148 1.39 scw {NULL, "Domain Fault (P)"},
149 1.39 scw {dab_buserr, "External Translation Abort (L1)"},
150 1.39 scw {NULL, "Permission Fault (S)"},
151 1.39 scw {dab_buserr, "External Translation Abort (L2)"},
152 1.39 scw {NULL, "Permission Fault (P)"}
153 1.39 scw };
154 1.1 chris
155 1.39 scw /* Determine if 'x' is a permission fault */
156 1.39 scw #define IS_PERMISSION_FAULT(x) \
157 1.39 scw (((1 << ((x) & FAULT_TYPE_MASK)) & \
158 1.39 scw ((1 << FAULT_PERM_P) | (1 << FAULT_PERM_S))) != 0)
159 1.1 chris
160 1.39 scw #if 0
161 1.39 scw /* maybe one day we'll do emulations */
162 1.39 scw #define TRAPSIGNAL(l,k) (*(l)->l_proc->p_emul->e_trapsignal)((l), (k))
163 1.39 scw #else
164 1.39 scw #define TRAPSIGNAL(l,k) trapsignal((l), (k))
165 1.1 chris #endif
166 1.3 thorpej
167 1.56 perry static inline void
168 1.93 matt call_trapsignal(struct lwp *l, const struct trapframe *tf, ksiginfo_t *ksi)
169 1.3 thorpej {
170 1.93 matt if (l->l_proc->p_pid == 1 || cpu_printfataltraps) {
171 1.93 matt printf("%d.%d(%s): trap: signo=%d code=%d addr=%p trap=%#x\n",
172 1.93 matt l->l_proc->p_pid, l->l_lid, l->l_proc->p_comm,
173 1.93 matt ksi->ksi_signo, ksi->ksi_code, ksi->ksi_addr,
174 1.93 matt ksi->ksi_trap);
175 1.93 matt printf("r0=%08x r1=%08x r2=%08x r3=%08x\n",
176 1.93 matt tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3);
177 1.93 matt printf("r4=%08x r5=%08x r6=%08x r7=%08x\n",
178 1.93 matt tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7);
179 1.93 matt printf("r8=%08x r9=%08x rA=%08x rB=%08x\n",
180 1.93 matt tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11);
181 1.93 matt printf("ip=%08x sp=%08x lr=%08x pc=%08x spsr=%08x\n",
182 1.93 matt tf->tf_r12, tf->tf_usr_sp, tf->tf_usr_lr, tf->tf_pc,
183 1.93 matt tf->tf_spsr);
184 1.93 matt }
185 1.3 thorpej
186 1.39 scw TRAPSIGNAL(l, ksi);
187 1.39 scw }
188 1.3 thorpej
189 1.56 perry static inline int
190 1.39 scw data_abort_fixup(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l)
191 1.39 scw {
192 1.39 scw #ifdef CPU_ABORT_FIXUP_REQUIRED
193 1.39 scw int error;
194 1.3 thorpej
195 1.48 wiz /* Call the CPU specific data abort fixup routine */
196 1.39 scw error = cpu_dataabt_fixup(tf);
197 1.39 scw if (__predict_true(error != ABORT_FIXUP_FAILED))
198 1.39 scw return (error);
199 1.3 thorpej
200 1.39 scw /*
201 1.39 scw * Oops, couldn't fix up the instruction
202 1.39 scw */
203 1.79 christos printf("%s: fixup for %s mode data abort failed.\n", __func__,
204 1.39 scw TRAP_USERMODE(tf) ? "user" : "kernel");
205 1.51 rearnsha #ifdef THUMB_CODE
206 1.51 rearnsha if (tf->tf_spsr & PSR_T_bit) {
207 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%04x, 0x%04x, insn = ",
208 1.86 skrll tf->tf_pc, *((uint16 *)(tf->tf_pc & ~1)),
209 1.86 skrll *((uint16 *)((tf->tf_pc + 2) & ~1)));
210 1.51 rearnsha }
211 1.51 rearnsha else
212 1.51 rearnsha #endif
213 1.51 rearnsha {
214 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc,
215 1.51 rearnsha *((u_int *)tf->tf_pc));
216 1.51 rearnsha }
217 1.39 scw disassemble(tf->tf_pc);
218 1.39 scw
219 1.39 scw /* Die now if this happened in kernel mode */
220 1.39 scw if (!TRAP_USERMODE(tf))
221 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
222 1.3 thorpej
223 1.39 scw return (error);
224 1.39 scw #else
225 1.39 scw return (ABORT_FIXUP_OK);
226 1.39 scw #endif /* CPU_ABORT_FIXUP_REQUIRED */
227 1.3 thorpej }
228 1.3 thorpej
229 1.1 chris void
230 1.39 scw data_abort_handler(trapframe_t *tf)
231 1.1 chris {
232 1.39 scw struct vm_map *map;
233 1.83 matt struct lwp * const l = curlwp;
234 1.83 matt struct cpu_info * const ci = curcpu();
235 1.83 matt u_int far, fsr;
236 1.39 scw vm_prot_t ftype;
237 1.1 chris void *onfault;
238 1.27 scw vaddr_t va;
239 1.39 scw int error;
240 1.34 matt ksiginfo_t ksi;
241 1.3 thorpej
242 1.97 matt UVMHIST_FUNC(__func__);
243 1.98 matt UVMHIST_CALLED(maphist);
244 1.50 rearnsha
245 1.39 scw /* Grab FAR/FSR before enabling interrupts */
246 1.39 scw far = cpu_faultaddress();
247 1.39 scw fsr = cpu_faultstatus();
248 1.1 chris
249 1.39 scw /* Update vmmeter statistics */
250 1.83 matt ci->ci_data.cpu_ntrap++;
251 1.1 chris
252 1.39 scw /* Re-enable interrupts if they were enabled previously */
253 1.101 matt KASSERT(!TRAP_USERMODE(tf) || VALID_R15_PSR(tf->tf_pc, tf->tf_spsr));
254 1.101 matt #ifdef __NO_FIQ
255 1.101 matt if (__predict_true((tf->tf_spsr & I32_bit) != I32_bit))
256 1.101 matt restore_interrupts(tf->tf_spsr & IF32_bits);
257 1.101 matt #else
258 1.72 matt if (__predict_true((tf->tf_spsr & IF32_bits) != IF32_bits))
259 1.72 matt restore_interrupts(tf->tf_spsr & IF32_bits);
260 1.101 matt #endif
261 1.1 chris
262 1.67 matt /* Get the current lwp structure */
263 1.1 chris
264 1.105 pgoyette UVMHIST_LOG(maphist, " (l=%#jx, far=%#jx, fsr=%#jx",
265 1.105 pgoyette (uintptr_t)l, far, fsr, 0);
266 1.105 pgoyette UVMHIST_LOG(maphist, " tf=%#jx, pc=%#jx)",
267 1.105 pgoyette (uintptr_t)tf, (uintptr_t)tf->tf_pc, 0, 0);
268 1.50 rearnsha
269 1.39 scw /* Data abort came from user mode? */
270 1.83 matt bool user = (TRAP_USERMODE(tf) != 0);
271 1.83 matt if (user)
272 1.61 ad LWP_CACHE_CREDS(l, l->l_proc);
273 1.1 chris
274 1.39 scw /* Grab the current pcb */
275 1.83 matt struct pcb * const pcb = lwp_getpcb(l);
276 1.1 chris
277 1.85 matt curcpu()->ci_abt_evs[fsr & FAULT_TYPE_MASK].ev_count++;
278 1.85 matt
279 1.39 scw /* Invoke the appropriate handler, if necessary */
280 1.39 scw if (__predict_false(data_aborts[fsr & FAULT_TYPE_MASK].func != NULL)) {
281 1.79 christos #ifdef DIAGNOSTIC
282 1.79 christos printf("%s: data_aborts fsr=0x%x far=0x%x\n",
283 1.79 christos __func__, fsr, far);
284 1.79 christos #endif
285 1.39 scw if ((data_aborts[fsr & FAULT_TYPE_MASK].func)(tf, fsr, far,
286 1.39 scw l, &ksi))
287 1.39 scw goto do_trapsignal;
288 1.39 scw goto out;
289 1.39 scw }
290 1.1 chris
291 1.1 chris /*
292 1.39 scw * At this point, we're dealing with one of the following data aborts:
293 1.39 scw *
294 1.39 scw * FAULT_TRANS_S - Translation -- Section
295 1.39 scw * FAULT_TRANS_P - Translation -- Page
296 1.39 scw * FAULT_DOMAIN_S - Domain -- Section
297 1.39 scw * FAULT_DOMAIN_P - Domain -- Page
298 1.39 scw * FAULT_PERM_S - Permission -- Section
299 1.39 scw * FAULT_PERM_P - Permission -- Page
300 1.39 scw *
301 1.39 scw * These are the main virtual memory-related faults signalled by
302 1.39 scw * the MMU.
303 1.1 chris */
304 1.1 chris
305 1.1 chris /* fusubailout is used by [fs]uswintr to avoid page faulting */
306 1.39 scw if (__predict_false(pcb->pcb_onfault == fusubailout)) {
307 1.39 scw tf->tf_r0 = EFAULT;
308 1.83 matt tf->tf_pc = (intptr_t) pcb->pcb_onfault;
309 1.1 chris return;
310 1.1 chris }
311 1.1 chris
312 1.104 skrll KASSERTMSG(!user || tf == lwp_trapframe(l), "tf %p vs %p", tf,
313 1.104 skrll lwp_trapframe(l));
314 1.1 chris
315 1.40 scw /*
316 1.40 scw * Make sure the Program Counter is sane. We could fall foul of
317 1.40 scw * someone executing Thumb code, in which case the PC might not
318 1.40 scw * be word-aligned. This would cause a kernel alignment fault
319 1.40 scw * further down if we have to decode the current instruction.
320 1.40 scw */
321 1.51 rearnsha #ifdef THUMB_CODE
322 1.100 skrll /*
323 1.51 rearnsha * XXX: It would be nice to be able to support Thumb in the kernel
324 1.51 rearnsha * at some point.
325 1.51 rearnsha */
326 1.51 rearnsha if (__predict_false(!user && (tf->tf_pc & 3) != 0)) {
327 1.79 christos printf("\n%s: Misaligned Kernel-mode Program Counter\n",
328 1.79 christos __func__);
329 1.51 rearnsha dab_fatal(tf, fsr, far, l, NULL);
330 1.51 rearnsha }
331 1.51 rearnsha #else
332 1.40 scw if (__predict_false((tf->tf_pc & 3) != 0)) {
333 1.40 scw if (user) {
334 1.40 scw /*
335 1.40 scw * Give the user an illegal instruction signal.
336 1.40 scw */
337 1.40 scw /* Deliver a SIGILL to the process */
338 1.40 scw KSI_INIT_TRAP(&ksi);
339 1.40 scw ksi.ksi_signo = SIGILL;
340 1.40 scw ksi.ksi_code = ILL_ILLOPC;
341 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
342 1.40 scw ksi.ksi_trap = fsr;
343 1.40 scw goto do_trapsignal;
344 1.40 scw }
345 1.40 scw
346 1.40 scw /*
347 1.40 scw * The kernel never executes Thumb code.
348 1.40 scw */
349 1.79 christos printf("\n%s: Misaligned Kernel-mode Program Counter\n",
350 1.79 christos __func__);
351 1.40 scw dab_fatal(tf, fsr, far, l, NULL);
352 1.27 scw }
353 1.51 rearnsha #endif
354 1.27 scw
355 1.48 wiz /* See if the CPU state needs to be fixed up */
356 1.41 scw switch (data_abort_fixup(tf, fsr, far, l)) {
357 1.41 scw case ABORT_FIXUP_RETURN:
358 1.41 scw return;
359 1.41 scw case ABORT_FIXUP_FAILED:
360 1.41 scw /* Deliver a SIGILL to the process */
361 1.41 scw KSI_INIT_TRAP(&ksi);
362 1.41 scw ksi.ksi_signo = SIGILL;
363 1.41 scw ksi.ksi_code = ILL_ILLOPC;
364 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
365 1.41 scw ksi.ksi_trap = fsr;
366 1.41 scw goto do_trapsignal;
367 1.41 scw default:
368 1.41 scw break;
369 1.41 scw }
370 1.41 scw
371 1.39 scw va = trunc_page((vaddr_t)far);
372 1.1 chris
373 1.27 scw /*
374 1.27 scw * It is only a kernel address space fault iff:
375 1.27 scw * 1. user == 0 and
376 1.27 scw * 2. pcb_onfault not set or
377 1.41 scw * 3. pcb_onfault set and not LDRT/LDRBT/STRT/STRBT instruction.
378 1.27 scw */
379 1.83 matt if (!user && (va >= VM_MIN_KERNEL_ADDRESS ||
380 1.41 scw (va < VM_MIN_ADDRESS && vector_page == ARM_VECTORS_LOW)) &&
381 1.41 scw __predict_true((pcb->pcb_onfault == NULL ||
382 1.93 matt (read_insn(tf->tf_pc, false) & 0x05200000) != 0x04200000))) {
383 1.39 scw map = kernel_map;
384 1.39 scw
385 1.106 maxv /* Was the fault due to the FPE ? */
386 1.39 scw if (__predict_false((tf->tf_spsr & PSR_MODE)==PSR_UND32_MODE)) {
387 1.35 thorpej KSI_INIT_TRAP(&ksi);
388 1.34 matt ksi.ksi_signo = SIGSEGV;
389 1.39 scw ksi.ksi_code = SEGV_ACCERR;
390 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
391 1.39 scw ksi.ksi_trap = fsr;
392 1.27 scw
393 1.27 scw /*
394 1.27 scw * Force exit via userret()
395 1.39 scw * This is necessary as the FPE is an extension to
396 1.39 scw * userland that actually runs in a priveledged mode
397 1.39 scw * but uses USR mode permissions for its accesses.
398 1.27 scw */
399 1.83 matt user = true;
400 1.39 scw goto do_trapsignal;
401 1.27 scw }
402 1.70 wrstuden } else {
403 1.39 scw map = &l->l_proc->p_vmspace->vm_map;
404 1.70 wrstuden }
405 1.1 chris
406 1.27 scw /*
407 1.94 matt * We need to know whether the page should be mapped as R or R/W.
408 1.94 matt * Before ARMv6, the MMU did not give us the info as to whether the
409 1.94 matt * fault was caused by a read or a write.
410 1.39 scw *
411 1.94 matt * However, we know that a permission fault can only be the result of
412 1.94 matt * a write to a read-only location, so we can deal with those quickly.
413 1.39 scw *
414 1.94 matt * Otherwise we need to disassemble the instruction responsible to
415 1.94 matt * determine if it was a write.
416 1.27 scw */
417 1.96 skrll if (CPU_IS_ARMV6_P() || CPU_IS_ARMV7_P()) {
418 1.94 matt ftype = (fsr & FAULT_WRITE) ? VM_PROT_WRITE : VM_PROT_READ;
419 1.94 matt } else if (IS_PERMISSION_FAULT(fsr)) {
420 1.100 skrll ftype = VM_PROT_WRITE;
421 1.94 matt } else {
422 1.51 rearnsha #ifdef THUMB_CODE
423 1.51 rearnsha /* Fast track the ARM case. */
424 1.51 rearnsha if (__predict_false(tf->tf_spsr & PSR_T_bit)) {
425 1.93 matt u_int insn = read_thumb_insn(tf->tf_pc, user);
426 1.51 rearnsha u_int insn_f8 = insn & 0xf800;
427 1.51 rearnsha u_int insn_fe = insn & 0xfe00;
428 1.51 rearnsha
429 1.51 rearnsha if (insn_f8 == 0x6000 || /* STR(1) */
430 1.51 rearnsha insn_f8 == 0x7000 || /* STRB(1) */
431 1.51 rearnsha insn_f8 == 0x8000 || /* STRH(1) */
432 1.51 rearnsha insn_f8 == 0x9000 || /* STR(3) */
433 1.51 rearnsha insn_f8 == 0xc000 || /* STM */
434 1.51 rearnsha insn_fe == 0x5000 || /* STR(2) */
435 1.51 rearnsha insn_fe == 0x5200 || /* STRH(2) */
436 1.51 rearnsha insn_fe == 0x5400) /* STRB(2) */
437 1.51 rearnsha ftype = VM_PROT_WRITE;
438 1.51 rearnsha else
439 1.51 rearnsha ftype = VM_PROT_READ;
440 1.51 rearnsha }
441 1.51 rearnsha else
442 1.51 rearnsha #endif
443 1.51 rearnsha {
444 1.93 matt u_int insn = read_insn(tf->tf_pc, user);
445 1.39 scw
446 1.51 rearnsha if (((insn & 0x0c100000) == 0x04000000) || /* STR[B] */
447 1.51 rearnsha ((insn & 0x0e1000b0) == 0x000000b0) || /* STR[HD]*/
448 1.81 matt ((insn & 0x0a100000) == 0x08000000) || /* STM/CDT*/
449 1.81 matt ((insn & 0x0f9000f0) == 0x01800090)) /* STREX[BDH] */
450 1.100 skrll ftype = VM_PROT_WRITE;
451 1.51 rearnsha else if ((insn & 0x0fb00ff0) == 0x01000090)/* SWP */
452 1.100 skrll ftype = VM_PROT_READ | VM_PROT_WRITE;
453 1.51 rearnsha else
454 1.100 skrll ftype = VM_PROT_READ;
455 1.51 rearnsha }
456 1.39 scw }
457 1.39 scw
458 1.39 scw /*
459 1.39 scw * See if the fault is as a result of ref/mod emulation,
460 1.39 scw * or domain mismatch.
461 1.39 scw */
462 1.39 scw #ifdef DEBUG
463 1.39 scw last_fault_code = fsr;
464 1.1 chris #endif
465 1.42 briggs if (pmap_fault_fixup(map->pmap, va, ftype, user)) {
466 1.98 matt UVMHIST_LOG(maphist, " <- ref/mod emul", 0, 0, 0, 0);
467 1.27 scw goto out;
468 1.42 briggs }
469 1.1 chris
470 1.67 matt if (__predict_false(curcpu()->ci_intr_depth > 0)) {
471 1.45 scw if (pcb->pcb_onfault) {
472 1.45 scw tf->tf_r0 = EINVAL;
473 1.45 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
474 1.45 scw return;
475 1.45 scw }
476 1.39 scw printf("\nNon-emulated page fault with intr_depth > 0\n");
477 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
478 1.27 scw }
479 1.1 chris
480 1.27 scw onfault = pcb->pcb_onfault;
481 1.27 scw pcb->pcb_onfault = NULL;
482 1.57 he error = uvm_fault(map, va, ftype);
483 1.27 scw pcb->pcb_onfault = onfault;
484 1.39 scw
485 1.39 scw if (__predict_true(error == 0)) {
486 1.39 scw if (user)
487 1.39 scw uvm_grow(l->l_proc, va); /* Record any stack growth */
488 1.77 chs else
489 1.77 chs ucas_ras_check(tf);
490 1.98 matt UVMHIST_LOG(maphist, " <- uvm", 0, 0, 0, 0);
491 1.27 scw goto out;
492 1.27 scw }
493 1.39 scw
494 1.27 scw if (user == 0) {
495 1.27 scw if (pcb->pcb_onfault) {
496 1.39 scw tf->tf_r0 = error;
497 1.39 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
498 1.39 scw return;
499 1.1 chris }
500 1.39 scw
501 1.58 drochner printf("\nuvm_fault(%p, %lx, %x) -> %x\n", map, va, ftype,
502 1.39 scw error);
503 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
504 1.27 scw }
505 1.1 chris
506 1.43 scw KSI_INIT_TRAP(&ksi);
507 1.43 scw
508 1.103 martin switch (error) {
509 1.103 martin case ENOMEM:
510 1.39 scw printf("UVM: pid %d (%s), uid %d killed: "
511 1.39 scw "out of swap\n", l->l_proc->p_pid, l->l_proc->p_comm,
512 1.62 ad l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1);
513 1.43 scw ksi.ksi_signo = SIGKILL;
514 1.103 martin break;
515 1.103 martin case EACCES:
516 1.103 martin ksi.ksi_signo = SIGSEGV;
517 1.103 martin ksi.ksi_code = SEGV_ACCERR;
518 1.103 martin break;
519 1.103 martin case EINVAL:
520 1.103 martin ksi.ksi_signo = SIGBUS;
521 1.103 martin ksi.ksi_code = BUS_ADRERR;
522 1.103 martin break;
523 1.103 martin default:
524 1.43 scw ksi.ksi_signo = SIGSEGV;
525 1.103 martin ksi.ksi_code = SEGV_MAPERR;
526 1.103 martin break;
527 1.103 martin }
528 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
529 1.39 scw ksi.ksi_trap = fsr;
530 1.105 pgoyette UVMHIST_LOG(maphist, " <- error (%jd)", error, 0, 0, 0);
531 1.39 scw
532 1.39 scw do_trapsignal:
533 1.93 matt call_trapsignal(l, tf, &ksi);
534 1.39 scw out:
535 1.39 scw /* If returning to user mode, make sure to invoke userret() */
536 1.39 scw if (user)
537 1.39 scw userret(l);
538 1.39 scw }
539 1.39 scw
540 1.39 scw /*
541 1.39 scw * dab_fatal() handles the following data aborts:
542 1.39 scw *
543 1.39 scw * FAULT_WRTBUF_0 - Vector Exception
544 1.39 scw * FAULT_WRTBUF_1 - Terminal Exception
545 1.39 scw *
546 1.39 scw * We should never see these on a properly functioning system.
547 1.39 scw *
548 1.39 scw * This function is also called by the other handlers if they
549 1.39 scw * detect a fatal problem.
550 1.39 scw *
551 1.39 scw * Note: If 'l' is NULL, we assume we're dealing with a prefetch abort.
552 1.39 scw */
553 1.39 scw static int
554 1.39 scw dab_fatal(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l, ksiginfo_t *ksi)
555 1.39 scw {
556 1.83 matt const char * const mode = TRAP_USERMODE(tf) ? "user" : "kernel";
557 1.39 scw
558 1.39 scw if (l != NULL) {
559 1.39 scw printf("Fatal %s mode data abort: '%s'\n", mode,
560 1.39 scw data_aborts[fsr & FAULT_TYPE_MASK].desc);
561 1.44 scw printf("trapframe: %p\nFSR=%08x, FAR=", tf, fsr);
562 1.39 scw if ((fsr & FAULT_IMPRECISE) == 0)
563 1.44 scw printf("%08x, ", far);
564 1.39 scw else
565 1.44 scw printf("Invalid, ");
566 1.44 scw printf("spsr=%08x\n", tf->tf_spsr);
567 1.39 scw } else {
568 1.44 scw printf("Fatal %s mode prefetch abort at 0x%08x\n",
569 1.44 scw mode, tf->tf_pc);
570 1.44 scw printf("trapframe: %p, spsr=%08x\n", tf, tf->tf_spsr);
571 1.44 scw }
572 1.44 scw
573 1.44 scw printf("r0 =%08x, r1 =%08x, r2 =%08x, r3 =%08x\n",
574 1.44 scw tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3);
575 1.44 scw printf("r4 =%08x, r5 =%08x, r6 =%08x, r7 =%08x\n",
576 1.44 scw tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7);
577 1.44 scw printf("r8 =%08x, r9 =%08x, r10=%08x, r11=%08x\n",
578 1.44 scw tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11);
579 1.44 scw printf("r12=%08x, ", tf->tf_r12);
580 1.44 scw
581 1.44 scw if (TRAP_USERMODE(tf))
582 1.44 scw printf("usp=%08x, ulr=%08x",
583 1.44 scw tf->tf_usr_sp, tf->tf_usr_lr);
584 1.44 scw else
585 1.44 scw printf("ssp=%08x, slr=%08x",
586 1.44 scw tf->tf_svc_sp, tf->tf_svc_lr);
587 1.44 scw printf(", pc =%08x\n\n", tf->tf_pc);
588 1.34 matt
589 1.39 scw #if defined(DDB) || defined(KGDB)
590 1.39 scw kdb_trap(T_FAULT, tf);
591 1.34 matt #endif
592 1.39 scw panic("Fatal abort");
593 1.39 scw /*NOTREACHED*/
594 1.39 scw }
595 1.39 scw
596 1.39 scw /*
597 1.39 scw * dab_align() handles the following data aborts:
598 1.39 scw *
599 1.39 scw * FAULT_ALIGN_0 - Alignment fault
600 1.39 scw * FAULT_ALIGN_0 - Alignment fault
601 1.39 scw *
602 1.39 scw * These faults are fatal if they happen in kernel mode. Otherwise, we
603 1.39 scw * deliver a bus error to the process.
604 1.39 scw */
605 1.39 scw static int
606 1.39 scw dab_align(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l, ksiginfo_t *ksi)
607 1.39 scw {
608 1.39 scw /* Alignment faults are always fatal if they occur in kernel mode */
609 1.39 scw if (!TRAP_USERMODE(tf))
610 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
611 1.39 scw
612 1.39 scw /* pcb_onfault *must* be NULL at this point */
613 1.83 matt KDASSERT(((struct pcb *)lwp_getpcb(l))->pcb_onfault == NULL);
614 1.39 scw
615 1.48 wiz /* See if the CPU state needs to be fixed up */
616 1.39 scw (void) data_abort_fixup(tf, fsr, far, l);
617 1.39 scw
618 1.39 scw /* Deliver a bus error signal to the process */
619 1.39 scw KSI_INIT_TRAP(ksi);
620 1.39 scw ksi->ksi_signo = SIGBUS;
621 1.39 scw ksi->ksi_code = BUS_ADRALN;
622 1.86 skrll ksi->ksi_addr = (uint32_t *)(intptr_t)far;
623 1.39 scw ksi->ksi_trap = fsr;
624 1.39 scw
625 1.104 skrll KASSERTMSG(tf == lwp_trapframe(l), "tf %p vs %p", tf, lwp_trapframe(l));
626 1.39 scw
627 1.39 scw return (1);
628 1.39 scw }
629 1.39 scw
630 1.39 scw /*
631 1.39 scw * dab_buserr() handles the following data aborts:
632 1.39 scw *
633 1.39 scw * FAULT_BUSERR_0 - External Abort on Linefetch -- Section
634 1.39 scw * FAULT_BUSERR_1 - External Abort on Linefetch -- Page
635 1.39 scw * FAULT_BUSERR_2 - External Abort on Non-linefetch -- Section
636 1.39 scw * FAULT_BUSERR_3 - External Abort on Non-linefetch -- Page
637 1.39 scw * FAULT_BUSTRNL1 - External abort on Translation -- Level 1
638 1.39 scw * FAULT_BUSTRNL2 - External abort on Translation -- Level 2
639 1.39 scw *
640 1.39 scw * If pcb_onfault is set, flag the fault and return to the handler.
641 1.39 scw * If the fault occurred in user mode, give the process a SIGBUS.
642 1.39 scw *
643 1.39 scw * Note: On XScale, FAULT_BUSERR_0, FAULT_BUSERR_1, and FAULT_BUSERR_2
644 1.39 scw * can be flagged as imprecise in the FSR. This causes a real headache
645 1.39 scw * since some of the machine state is lost. In this case, tf->tf_pc
646 1.39 scw * may not actually point to the offending instruction. In fact, if
647 1.39 scw * we've taken a double abort fault, it generally points somewhere near
648 1.39 scw * the top of "data_abort_entry" in exception.S.
649 1.39 scw *
650 1.39 scw * In all other cases, these data aborts are considered fatal.
651 1.39 scw */
652 1.39 scw static int
653 1.39 scw dab_buserr(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l,
654 1.39 scw ksiginfo_t *ksi)
655 1.39 scw {
656 1.73 rmind struct pcb *pcb = lwp_getpcb(l);
657 1.39 scw
658 1.39 scw #ifdef __XSCALE__
659 1.39 scw if ((fsr & FAULT_IMPRECISE) != 0 &&
660 1.39 scw (tf->tf_spsr & PSR_MODE) == PSR_ABT32_MODE) {
661 1.39 scw /*
662 1.39 scw * Oops, an imprecise, double abort fault. We've lost the
663 1.39 scw * r14_abt/spsr_abt values corresponding to the original
664 1.39 scw * abort, and the spsr saved in the trapframe indicates
665 1.39 scw * ABT mode.
666 1.39 scw */
667 1.39 scw tf->tf_spsr &= ~PSR_MODE;
668 1.39 scw
669 1.39 scw /*
670 1.39 scw * We use a simple heuristic to determine if the double abort
671 1.39 scw * happened as a result of a kernel or user mode access.
672 1.39 scw * If the current trapframe is at the top of the kernel stack,
673 1.39 scw * the fault _must_ have come from user mode.
674 1.39 scw */
675 1.87 matt if (tf != ((trapframe_t *)pcb->pcb_ksp) - 1) {
676 1.39 scw /*
677 1.39 scw * Kernel mode. We're either about to die a
678 1.39 scw * spectacular death, or pcb_onfault will come
679 1.39 scw * to our rescue. Either way, the current value
680 1.39 scw * of tf->tf_pc is irrelevant.
681 1.39 scw */
682 1.39 scw tf->tf_spsr |= PSR_SVC32_MODE;
683 1.39 scw if (pcb->pcb_onfault == NULL)
684 1.39 scw printf("\nKernel mode double abort!\n");
685 1.39 scw } else {
686 1.39 scw /*
687 1.39 scw * User mode. We've lost the program counter at the
688 1.39 scw * time of the fault (not that it was accurate anyway;
689 1.39 scw * it's not called an imprecise fault for nothing).
690 1.39 scw * About all we can do is copy r14_usr to tf_pc and
691 1.39 scw * hope for the best. The process is about to get a
692 1.39 scw * SIGBUS, so it's probably history anyway.
693 1.39 scw */
694 1.39 scw tf->tf_spsr |= PSR_USR32_MODE;
695 1.39 scw tf->tf_pc = tf->tf_usr_lr;
696 1.51 rearnsha #ifdef THUMB_CODE
697 1.51 rearnsha tf->tf_spsr &= ~PSR_T_bit;
698 1.51 rearnsha if (tf->tf_usr_lr & 1)
699 1.51 rearnsha tf->tf_spsr |= PSR_T_bit;
700 1.51 rearnsha #endif
701 1.39 scw }
702 1.39 scw }
703 1.39 scw
704 1.39 scw /* FAR is invalid for imprecise exceptions */
705 1.39 scw if ((fsr & FAULT_IMPRECISE) != 0)
706 1.39 scw far = 0;
707 1.39 scw #endif /* __XSCALE__ */
708 1.39 scw
709 1.39 scw if (pcb->pcb_onfault) {
710 1.39 scw KDASSERT(TRAP_USERMODE(tf) == 0);
711 1.39 scw tf->tf_r0 = EFAULT;
712 1.39 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
713 1.39 scw return (0);
714 1.39 scw }
715 1.39 scw
716 1.48 wiz /* See if the CPU state needs to be fixed up */
717 1.39 scw (void) data_abort_fixup(tf, fsr, far, l);
718 1.39 scw
719 1.39 scw /*
720 1.39 scw * At this point, if the fault happened in kernel mode, we're toast
721 1.39 scw */
722 1.39 scw if (!TRAP_USERMODE(tf))
723 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
724 1.39 scw
725 1.39 scw /* Deliver a bus error signal to the process */
726 1.39 scw KSI_INIT_TRAP(ksi);
727 1.39 scw ksi->ksi_signo = SIGBUS;
728 1.39 scw ksi->ksi_code = BUS_ADRERR;
729 1.86 skrll ksi->ksi_addr = (uint32_t *)(intptr_t)far;
730 1.39 scw ksi->ksi_trap = fsr;
731 1.39 scw
732 1.104 skrll KASSERTMSG(tf == lwp_trapframe(l), "tf %p vs %p", tf, lwp_trapframe(l));
733 1.27 scw
734 1.39 scw return (1);
735 1.1 chris }
736 1.1 chris
737 1.56 perry static inline int
738 1.39 scw prefetch_abort_fixup(trapframe_t *tf)
739 1.39 scw {
740 1.39 scw #ifdef CPU_ABORT_FIXUP_REQUIRED
741 1.39 scw int error;
742 1.39 scw
743 1.48 wiz /* Call the CPU specific prefetch abort fixup routine */
744 1.39 scw error = cpu_prefetchabt_fixup(tf);
745 1.39 scw if (__predict_true(error != ABORT_FIXUP_FAILED))
746 1.39 scw return (error);
747 1.39 scw
748 1.39 scw /*
749 1.39 scw * Oops, couldn't fix up the instruction
750 1.39 scw */
751 1.79 christos printf("%s: fixup for %s mode prefetch abort failed.\n", __func__,
752 1.39 scw TRAP_USERMODE(tf) ? "user" : "kernel");
753 1.51 rearnsha #ifdef THUMB_CODE
754 1.51 rearnsha if (tf->tf_spsr & PSR_T_bit) {
755 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%04x, 0x%04x, insn = ",
756 1.86 skrll tf->tf_pc, *((uint16 *)(tf->tf_pc & ~1)),
757 1.86 skrll *((uint16 *)((tf->tf_pc + 2) & ~1)));
758 1.51 rearnsha }
759 1.51 rearnsha else
760 1.51 rearnsha #endif
761 1.51 rearnsha {
762 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc,
763 1.51 rearnsha *((u_int *)tf->tf_pc));
764 1.51 rearnsha }
765 1.39 scw disassemble(tf->tf_pc);
766 1.39 scw
767 1.39 scw /* Die now if this happened in kernel mode */
768 1.39 scw if (!TRAP_USERMODE(tf))
769 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
770 1.39 scw
771 1.39 scw return (error);
772 1.39 scw #else
773 1.39 scw return (ABORT_FIXUP_OK);
774 1.39 scw #endif /* CPU_ABORT_FIXUP_REQUIRED */
775 1.39 scw }
776 1.1 chris
777 1.1 chris /*
778 1.39 scw * void prefetch_abort_handler(trapframe_t *tf)
779 1.1 chris *
780 1.1 chris * Abort handler called when instruction execution occurs at
781 1.1 chris * a non existent or restricted (access permissions) memory page.
782 1.1 chris * If the address is invalid and we were in SVC mode then panic as
783 1.1 chris * the kernel should never prefetch abort.
784 1.1 chris * If the address is invalid and the page is mapped then the user process
785 1.1 chris * does no have read permission so send it a signal.
786 1.1 chris * Otherwise fault the page in and try again.
787 1.1 chris */
788 1.1 chris void
789 1.39 scw prefetch_abort_handler(trapframe_t *tf)
790 1.1 chris {
791 1.26 thorpej struct lwp *l;
792 1.91 christos struct pcb *pcb __diagused;
793 1.14 thorpej struct vm_map *map;
794 1.14 thorpej vaddr_t fault_pc, va;
795 1.39 scw ksiginfo_t ksi;
796 1.61 ad int error, user;
797 1.39 scw
798 1.97 matt UVMHIST_FUNC(__func__);
799 1.98 matt UVMHIST_CALLED(maphist);
800 1.50 rearnsha
801 1.39 scw /* Update vmmeter statistics */
802 1.78 matt curcpu()->ci_data.cpu_ntrap++;
803 1.1 chris
804 1.61 ad l = curlwp;
805 1.73 rmind pcb = lwp_getpcb(l);
806 1.61 ad
807 1.61 ad if ((user = TRAP_USERMODE(tf)) != 0)
808 1.61 ad LWP_CACHE_CREDS(l, l->l_proc);
809 1.61 ad
810 1.1 chris /*
811 1.1 chris * Enable IRQ's (disabled by the abort) This always comes
812 1.1 chris * from user mode so we know interrupts were not disabled.
813 1.1 chris * But we check anyway.
814 1.1 chris */
815 1.101 matt KASSERT(!TRAP_USERMODE(tf) || VALID_R15_PSR(tf->tf_pc, tf->tf_spsr));
816 1.101 matt #ifdef __NO_FIQ
817 1.101 matt if (__predict_true((tf->tf_spsr & I32_bit) != I32_bit))
818 1.72 matt restore_interrupts(tf->tf_spsr & IF32_bits);
819 1.101 matt #else
820 1.101 matt if (__predict_true((tf->tf_spsr & IF32_bits) != IF32_bits))
821 1.101 matt restore_interrupts(tf->tf_spsr & IF32_bits);
822 1.101 matt #endif
823 1.1 chris
824 1.48 wiz /* See if the CPU state needs to be fixed up */
825 1.39 scw switch (prefetch_abort_fixup(tf)) {
826 1.39 scw case ABORT_FIXUP_RETURN:
827 1.101 matt KASSERT(!TRAP_USERMODE(tf) || VALID_R15_PSR(tf->tf_pc, tf->tf_spsr));
828 1.1 chris return;
829 1.39 scw case ABORT_FIXUP_FAILED:
830 1.39 scw /* Deliver a SIGILL to the process */
831 1.39 scw KSI_INIT_TRAP(&ksi);
832 1.39 scw ksi.ksi_signo = SIGILL;
833 1.39 scw ksi.ksi_code = ILL_ILLOPC;
834 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) tf->tf_pc;
835 1.104 skrll KASSERTMSG(tf == lwp_trapframe(l), "tf %p vs %p", tf,
836 1.104 skrll lwp_trapframe(l));
837 1.39 scw goto do_trapsignal;
838 1.39 scw default:
839 1.39 scw break;
840 1.1 chris }
841 1.1 chris
842 1.39 scw /* Prefetch aborts cannot happen in kernel mode */
843 1.61 ad if (__predict_false(!user))
844 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
845 1.1 chris
846 1.4 thorpej /* Get fault address */
847 1.39 scw fault_pc = tf->tf_pc;
848 1.104 skrll KASSERTMSG(tf == lwp_trapframe(l), "tf %p vs %p", tf, lwp_trapframe(l));
849 1.105 pgoyette UVMHIST_LOG(maphist, " (pc=0x%jx, l=0x%#jx, tf=0x%#jx)",
850 1.105 pgoyette fault_pc, (uintptr_t)l, (uintptr_t)tf, 0);
851 1.14 thorpej
852 1.1 chris /* Ok validate the address, can only execute in USER space */
853 1.39 scw if (__predict_false(fault_pc >= VM_MAXUSER_ADDRESS ||
854 1.39 scw (fault_pc < VM_MIN_ADDRESS && vector_page == ARM_VECTORS_LOW))) {
855 1.35 thorpej KSI_INIT_TRAP(&ksi);
856 1.34 matt ksi.ksi_signo = SIGSEGV;
857 1.34 matt ksi.ksi_code = SEGV_ACCERR;
858 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) fault_pc;
859 1.34 matt ksi.ksi_trap = fault_pc;
860 1.39 scw goto do_trapsignal;
861 1.39 scw }
862 1.34 matt
863 1.39 scw map = &l->l_proc->p_vmspace->vm_map;
864 1.39 scw va = trunc_page(fault_pc);
865 1.1 chris
866 1.27 scw /*
867 1.27 scw * See if the pmap can handle this fault on its own...
868 1.27 scw */
869 1.39 scw #ifdef DEBUG
870 1.39 scw last_fault_code = -1;
871 1.39 scw #endif
872 1.88 matt if (pmap_fault_fixup(map->pmap, va, VM_PROT_READ|VM_PROT_EXECUTE, 1)) {
873 1.98 matt UVMHIST_LOG (maphist, " <- emulated", 0, 0, 0, 0);
874 1.39 scw goto out;
875 1.50 rearnsha }
876 1.27 scw
877 1.39 scw #ifdef DIAGNOSTIC
878 1.84 matt if (__predict_false(curcpu()->ci_intr_depth > 0)) {
879 1.39 scw printf("\nNon-emulated prefetch abort with intr_depth > 0\n");
880 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
881 1.39 scw }
882 1.1 chris #endif
883 1.72 matt
884 1.76 chs KASSERT(pcb->pcb_onfault == NULL);
885 1.99 matt error = uvm_fault(map, va, VM_PROT_READ|VM_PROT_EXECUTE);
886 1.53 joff
887 1.50 rearnsha if (__predict_true(error == 0)) {
888 1.98 matt UVMHIST_LOG (maphist, " <- uvm", 0, 0, 0, 0);
889 1.39 scw goto out;
890 1.50 rearnsha }
891 1.43 scw KSI_INIT_TRAP(&ksi);
892 1.43 scw
893 1.105 pgoyette UVMHIST_LOG (maphist, " <- fatal (%jd)", error, 0, 0, 0);
894 1.98 matt
895 1.39 scw if (error == ENOMEM) {
896 1.39 scw printf("UVM: pid %d (%s), uid %d killed: "
897 1.39 scw "out of swap\n", l->l_proc->p_pid, l->l_proc->p_comm,
898 1.62 ad l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1);
899 1.43 scw ksi.ksi_signo = SIGKILL;
900 1.43 scw } else
901 1.43 scw ksi.ksi_signo = SIGSEGV;
902 1.1 chris
903 1.39 scw ksi.ksi_code = SEGV_MAPERR;
904 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) fault_pc;
905 1.39 scw ksi.ksi_trap = fault_pc;
906 1.39 scw
907 1.39 scw do_trapsignal:
908 1.93 matt call_trapsignal(l, tf, &ksi);
909 1.39 scw
910 1.39 scw out:
911 1.101 matt KASSERT(!TRAP_USERMODE(tf) || VALID_R15_PSR(tf->tf_pc, tf->tf_spsr));
912 1.39 scw userret(l);
913 1.39 scw }
914 1.39 scw
915 1.39 scw /*
916 1.39 scw * Tentatively read an 8, 16, or 32-bit value from 'addr'.
917 1.39 scw * If the read succeeds, the value is written to 'rptr' and zero is returned.
918 1.39 scw * Else, return EFAULT.
919 1.39 scw */
920 1.39 scw int
921 1.39 scw badaddr_read(void *addr, size_t size, void *rptr)
922 1.39 scw {
923 1.39 scw extern int badaddr_read_1(const uint8_t *, uint8_t *);
924 1.39 scw extern int badaddr_read_2(const uint16_t *, uint16_t *);
925 1.39 scw extern int badaddr_read_4(const uint32_t *, uint32_t *);
926 1.39 scw union {
927 1.39 scw uint8_t v1;
928 1.39 scw uint16_t v2;
929 1.39 scw uint32_t v4;
930 1.39 scw } u;
931 1.47 scw int rv, s;
932 1.39 scw
933 1.39 scw cpu_drain_writebuf();
934 1.39 scw
935 1.47 scw s = splhigh();
936 1.47 scw
937 1.39 scw /* Read from the test address. */
938 1.39 scw switch (size) {
939 1.39 scw case sizeof(uint8_t):
940 1.39 scw rv = badaddr_read_1(addr, &u.v1);
941 1.39 scw if (rv == 0 && rptr)
942 1.39 scw *(uint8_t *) rptr = u.v1;
943 1.39 scw break;
944 1.39 scw
945 1.39 scw case sizeof(uint16_t):
946 1.39 scw rv = badaddr_read_2(addr, &u.v2);
947 1.39 scw if (rv == 0 && rptr)
948 1.39 scw *(uint16_t *) rptr = u.v2;
949 1.39 scw break;
950 1.39 scw
951 1.39 scw case sizeof(uint32_t):
952 1.39 scw rv = badaddr_read_4(addr, &u.v4);
953 1.39 scw if (rv == 0 && rptr)
954 1.39 scw *(uint32_t *) rptr = u.v4;
955 1.39 scw break;
956 1.39 scw
957 1.39 scw default:
958 1.82 matt panic("%s: invalid size (%zu)", __func__, size);
959 1.34 matt }
960 1.39 scw
961 1.47 scw splx(s);
962 1.47 scw
963 1.39 scw /* Return EFAULT if the address was invalid, else zero */
964 1.39 scw return (rv);
965 1.1 chris }
966