fault.c revision 1.82 1 1.82 matt /* $NetBSD: fault.c,v 1.82 2012/08/14 20:42:33 matt Exp $ */
2 1.1 chris
3 1.1 chris /*
4 1.27 scw * Copyright 2003 Wasabi Systems, Inc.
5 1.27 scw * All rights reserved.
6 1.27 scw *
7 1.27 scw * Written by Steve C. Woodford for Wasabi Systems, Inc.
8 1.27 scw *
9 1.27 scw * Redistribution and use in source and binary forms, with or without
10 1.27 scw * modification, are permitted provided that the following conditions
11 1.27 scw * are met:
12 1.27 scw * 1. Redistributions of source code must retain the above copyright
13 1.27 scw * notice, this list of conditions and the following disclaimer.
14 1.27 scw * 2. Redistributions in binary form must reproduce the above copyright
15 1.27 scw * notice, this list of conditions and the following disclaimer in the
16 1.27 scw * documentation and/or other materials provided with the distribution.
17 1.27 scw * 3. All advertising materials mentioning features or use of this software
18 1.27 scw * must display the following acknowledgement:
19 1.27 scw * This product includes software developed for the NetBSD Project by
20 1.27 scw * Wasabi Systems, Inc.
21 1.27 scw * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.27 scw * or promote products derived from this software without specific prior
23 1.27 scw * written permission.
24 1.27 scw *
25 1.27 scw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.27 scw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.27 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.27 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.27 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.27 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.27 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.27 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.27 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.27 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.27 scw * POSSIBILITY OF SUCH DAMAGE.
36 1.27 scw */
37 1.27 scw /*
38 1.1 chris * Copyright (c) 1994-1997 Mark Brinicombe.
39 1.1 chris * Copyright (c) 1994 Brini.
40 1.1 chris * All rights reserved.
41 1.1 chris *
42 1.1 chris * This code is derived from software written for Brini by Mark Brinicombe
43 1.1 chris *
44 1.1 chris * Redistribution and use in source and binary forms, with or without
45 1.1 chris * modification, are permitted provided that the following conditions
46 1.1 chris * are met:
47 1.1 chris * 1. Redistributions of source code must retain the above copyright
48 1.1 chris * notice, this list of conditions and the following disclaimer.
49 1.1 chris * 2. Redistributions in binary form must reproduce the above copyright
50 1.1 chris * notice, this list of conditions and the following disclaimer in the
51 1.1 chris * documentation and/or other materials provided with the distribution.
52 1.1 chris * 3. All advertising materials mentioning features or use of this software
53 1.1 chris * must display the following acknowledgement:
54 1.1 chris * This product includes software developed by Brini.
55 1.1 chris * 4. The name of the company nor the name of the author may be used to
56 1.1 chris * endorse or promote products derived from this software without specific
57 1.1 chris * prior written permission.
58 1.1 chris *
59 1.1 chris * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
60 1.1 chris * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
61 1.1 chris * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
62 1.1 chris * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
63 1.1 chris * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
64 1.1 chris * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
65 1.1 chris * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 1.1 chris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 1.1 chris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 1.1 chris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 1.1 chris * SUCH DAMAGE.
70 1.1 chris *
71 1.1 chris * RiscBSD kernel project
72 1.1 chris *
73 1.1 chris * fault.c
74 1.1 chris *
75 1.1 chris * Fault handlers
76 1.1 chris *
77 1.1 chris * Created : 28/11/94
78 1.1 chris */
79 1.1 chris
80 1.1 chris #include "opt_ddb.h"
81 1.28 briggs #include "opt_kgdb.h"
82 1.1 chris
83 1.1 chris #include <sys/types.h>
84 1.82 matt __KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.82 2012/08/14 20:42:33 matt Exp $");
85 1.21 bjh21
86 1.1 chris #include <sys/param.h>
87 1.1 chris #include <sys/systm.h>
88 1.1 chris #include <sys/proc.h>
89 1.1 chris #include <sys/kernel.h>
90 1.60 yamt #include <sys/kauth.h>
91 1.65 matt #include <sys/cpu.h>
92 1.1 chris
93 1.1 chris #include <uvm/uvm_extern.h>
94 1.50 rearnsha #include <uvm/uvm_stat.h>
95 1.50 rearnsha #ifdef UVMHIST
96 1.50 rearnsha #include <uvm/uvm.h>
97 1.50 rearnsha #endif
98 1.18 thorpej
99 1.18 thorpej #include <arm/cpuconf.h>
100 1.1 chris
101 1.1 chris #include <machine/frame.h>
102 1.5 thorpej #include <arm/arm32/katelib.h>
103 1.2 matt #include <machine/intr.h>
104 1.28 briggs #if defined(DDB) || defined(KGDB)
105 1.1 chris #include <machine/db_machdep.h>
106 1.28 briggs #ifdef KGDB
107 1.28 briggs #include <sys/kgdb.h>
108 1.28 briggs #endif
109 1.28 briggs #if !defined(DDB)
110 1.28 briggs #define kdb_trap kgdb_trap
111 1.28 briggs #endif
112 1.1 chris #endif
113 1.1 chris
114 1.1 chris #include <arch/arm/arm/disassem.h>
115 1.7 chris #include <arm/arm32/machdep.h>
116 1.7 chris
117 1.1 chris extern char fusubailout[];
118 1.1 chris
119 1.27 scw #ifdef DEBUG
120 1.27 scw int last_fault_code; /* For the benefit of pmap_fault_fixup() */
121 1.27 scw #endif
122 1.27 scw
123 1.39 scw #if defined(CPU_ARM3) || defined(CPU_ARM6) || \
124 1.39 scw defined(CPU_ARM7) || defined(CPU_ARM7TDMI)
125 1.39 scw /* These CPUs may need data/prefetch abort fixups */
126 1.39 scw #define CPU_ABORT_FIXUP_REQUIRED
127 1.39 scw #endif
128 1.7 chris
129 1.39 scw struct data_abort {
130 1.39 scw int (*func)(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
131 1.39 scw const char *desc;
132 1.39 scw };
133 1.1 chris
134 1.39 scw static int dab_fatal(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
135 1.39 scw static int dab_align(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
136 1.39 scw static int dab_buserr(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
137 1.39 scw
138 1.39 scw static const struct data_abort data_aborts[] = {
139 1.39 scw {dab_fatal, "Vector Exception"},
140 1.39 scw {dab_align, "Alignment Fault 1"},
141 1.39 scw {dab_fatal, "Terminal Exception"},
142 1.39 scw {dab_align, "Alignment Fault 3"},
143 1.39 scw {dab_buserr, "External Linefetch Abort (S)"},
144 1.39 scw {NULL, "Translation Fault (S)"},
145 1.39 scw {dab_buserr, "External Linefetch Abort (P)"},
146 1.39 scw {NULL, "Translation Fault (P)"},
147 1.39 scw {dab_buserr, "External Non-Linefetch Abort (S)"},
148 1.39 scw {NULL, "Domain Fault (S)"},
149 1.39 scw {dab_buserr, "External Non-Linefetch Abort (P)"},
150 1.39 scw {NULL, "Domain Fault (P)"},
151 1.39 scw {dab_buserr, "External Translation Abort (L1)"},
152 1.39 scw {NULL, "Permission Fault (S)"},
153 1.39 scw {dab_buserr, "External Translation Abort (L2)"},
154 1.39 scw {NULL, "Permission Fault (P)"}
155 1.39 scw };
156 1.1 chris
157 1.39 scw /* Determine if a fault came from user mode */
158 1.39 scw #define TRAP_USERMODE(tf) ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE)
159 1.39 scw
160 1.39 scw /* Determine if 'x' is a permission fault */
161 1.39 scw #define IS_PERMISSION_FAULT(x) \
162 1.39 scw (((1 << ((x) & FAULT_TYPE_MASK)) & \
163 1.39 scw ((1 << FAULT_PERM_P) | (1 << FAULT_PERM_S))) != 0)
164 1.1 chris
165 1.39 scw #if 0
166 1.39 scw /* maybe one day we'll do emulations */
167 1.39 scw #define TRAPSIGNAL(l,k) (*(l)->l_proc->p_emul->e_trapsignal)((l), (k))
168 1.39 scw #else
169 1.39 scw #define TRAPSIGNAL(l,k) trapsignal((l), (k))
170 1.1 chris #endif
171 1.3 thorpej
172 1.56 perry static inline void
173 1.39 scw call_trapsignal(struct lwp *l, ksiginfo_t *ksi)
174 1.3 thorpej {
175 1.3 thorpej
176 1.39 scw TRAPSIGNAL(l, ksi);
177 1.39 scw }
178 1.3 thorpej
179 1.56 perry static inline int
180 1.39 scw data_abort_fixup(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l)
181 1.39 scw {
182 1.39 scw #ifdef CPU_ABORT_FIXUP_REQUIRED
183 1.39 scw int error;
184 1.3 thorpej
185 1.48 wiz /* Call the CPU specific data abort fixup routine */
186 1.39 scw error = cpu_dataabt_fixup(tf);
187 1.39 scw if (__predict_true(error != ABORT_FIXUP_FAILED))
188 1.39 scw return (error);
189 1.3 thorpej
190 1.39 scw /*
191 1.39 scw * Oops, couldn't fix up the instruction
192 1.39 scw */
193 1.79 christos printf("%s: fixup for %s mode data abort failed.\n", __func__,
194 1.39 scw TRAP_USERMODE(tf) ? "user" : "kernel");
195 1.51 rearnsha #ifdef THUMB_CODE
196 1.51 rearnsha if (tf->tf_spsr & PSR_T_bit) {
197 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%04x, 0x%04x, insn = ",
198 1.66 chris tf->tf_pc, *((u_int16 *)(tf->tf_pc & ~1)),
199 1.66 chris *((u_int16 *)((tf->tf_pc + 2) & ~1)));
200 1.51 rearnsha }
201 1.51 rearnsha else
202 1.51 rearnsha #endif
203 1.51 rearnsha {
204 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc,
205 1.51 rearnsha *((u_int *)tf->tf_pc));
206 1.51 rearnsha }
207 1.39 scw disassemble(tf->tf_pc);
208 1.39 scw
209 1.39 scw /* Die now if this happened in kernel mode */
210 1.39 scw if (!TRAP_USERMODE(tf))
211 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
212 1.3 thorpej
213 1.39 scw return (error);
214 1.39 scw #else
215 1.39 scw return (ABORT_FIXUP_OK);
216 1.39 scw #endif /* CPU_ABORT_FIXUP_REQUIRED */
217 1.3 thorpej }
218 1.3 thorpej
219 1.1 chris void
220 1.39 scw data_abort_handler(trapframe_t *tf)
221 1.1 chris {
222 1.39 scw struct vm_map *map;
223 1.39 scw struct pcb *pcb;
224 1.26 thorpej struct lwp *l;
225 1.39 scw u_int user, far, fsr;
226 1.39 scw vm_prot_t ftype;
227 1.1 chris void *onfault;
228 1.27 scw vaddr_t va;
229 1.39 scw int error;
230 1.34 matt ksiginfo_t ksi;
231 1.3 thorpej
232 1.50 rearnsha UVMHIST_FUNC("data_abort_handler");
233 1.50 rearnsha
234 1.39 scw /* Grab FAR/FSR before enabling interrupts */
235 1.39 scw far = cpu_faultaddress();
236 1.39 scw fsr = cpu_faultstatus();
237 1.1 chris
238 1.50 rearnsha UVMHIST_CALLED(maphist);
239 1.39 scw /* Update vmmeter statistics */
240 1.78 matt curcpu()->ci_data.cpu_ntrap++;
241 1.1 chris
242 1.39 scw /* Re-enable interrupts if they were enabled previously */
243 1.72 matt KASSERT(!TRAP_USERMODE(tf) || (tf->tf_spsr & IF32_bits) == 0);
244 1.72 matt if (__predict_true((tf->tf_spsr & IF32_bits) != IF32_bits))
245 1.72 matt restore_interrupts(tf->tf_spsr & IF32_bits);
246 1.1 chris
247 1.67 matt /* Get the current lwp structure */
248 1.67 matt KASSERT(curlwp != NULL);
249 1.67 matt l = curlwp;
250 1.1 chris
251 1.50 rearnsha UVMHIST_LOG(maphist, " (pc=0x%x, l=0x%x, far=0x%x, fsr=0x%x)",
252 1.50 rearnsha tf->tf_pc, l, far, fsr);
253 1.50 rearnsha
254 1.39 scw /* Data abort came from user mode? */
255 1.61 ad if ((user = TRAP_USERMODE(tf)) != 0)
256 1.61 ad LWP_CACHE_CREDS(l, l->l_proc);
257 1.1 chris
258 1.39 scw /* Grab the current pcb */
259 1.74 mbalmer pcb = lwp_getpcb(l);
260 1.1 chris
261 1.39 scw /* Invoke the appropriate handler, if necessary */
262 1.39 scw if (__predict_false(data_aborts[fsr & FAULT_TYPE_MASK].func != NULL)) {
263 1.79 christos #ifdef DIAGNOSTIC
264 1.79 christos printf("%s: data_aborts fsr=0x%x far=0x%x\n",
265 1.79 christos __func__, fsr, far);
266 1.79 christos #endif
267 1.39 scw if ((data_aborts[fsr & FAULT_TYPE_MASK].func)(tf, fsr, far,
268 1.39 scw l, &ksi))
269 1.39 scw goto do_trapsignal;
270 1.39 scw goto out;
271 1.39 scw }
272 1.1 chris
273 1.1 chris /*
274 1.39 scw * At this point, we're dealing with one of the following data aborts:
275 1.39 scw *
276 1.39 scw * FAULT_TRANS_S - Translation -- Section
277 1.39 scw * FAULT_TRANS_P - Translation -- Page
278 1.39 scw * FAULT_DOMAIN_S - Domain -- Section
279 1.39 scw * FAULT_DOMAIN_P - Domain -- Page
280 1.39 scw * FAULT_PERM_S - Permission -- Section
281 1.39 scw * FAULT_PERM_P - Permission -- Page
282 1.39 scw *
283 1.39 scw * These are the main virtual memory-related faults signalled by
284 1.39 scw * the MMU.
285 1.1 chris */
286 1.1 chris
287 1.1 chris /* fusubailout is used by [fs]uswintr to avoid page faulting */
288 1.39 scw if (__predict_false(pcb->pcb_onfault == fusubailout)) {
289 1.39 scw tf->tf_r0 = EFAULT;
290 1.39 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
291 1.1 chris return;
292 1.1 chris }
293 1.1 chris
294 1.73 rmind if (user) {
295 1.73 rmind pcb->pcb_tf = tf;
296 1.73 rmind }
297 1.1 chris
298 1.40 scw /*
299 1.40 scw * Make sure the Program Counter is sane. We could fall foul of
300 1.40 scw * someone executing Thumb code, in which case the PC might not
301 1.40 scw * be word-aligned. This would cause a kernel alignment fault
302 1.40 scw * further down if we have to decode the current instruction.
303 1.40 scw */
304 1.51 rearnsha #ifdef THUMB_CODE
305 1.51 rearnsha /*
306 1.51 rearnsha * XXX: It would be nice to be able to support Thumb in the kernel
307 1.51 rearnsha * at some point.
308 1.51 rearnsha */
309 1.51 rearnsha if (__predict_false(!user && (tf->tf_pc & 3) != 0)) {
310 1.79 christos printf("\n%s: Misaligned Kernel-mode Program Counter\n",
311 1.79 christos __func__);
312 1.51 rearnsha dab_fatal(tf, fsr, far, l, NULL);
313 1.51 rearnsha }
314 1.51 rearnsha #else
315 1.40 scw if (__predict_false((tf->tf_pc & 3) != 0)) {
316 1.40 scw if (user) {
317 1.40 scw /*
318 1.40 scw * Give the user an illegal instruction signal.
319 1.40 scw */
320 1.40 scw /* Deliver a SIGILL to the process */
321 1.40 scw KSI_INIT_TRAP(&ksi);
322 1.40 scw ksi.ksi_signo = SIGILL;
323 1.40 scw ksi.ksi_code = ILL_ILLOPC;
324 1.40 scw ksi.ksi_addr = (u_int32_t *)(intptr_t) far;
325 1.40 scw ksi.ksi_trap = fsr;
326 1.40 scw goto do_trapsignal;
327 1.40 scw }
328 1.40 scw
329 1.40 scw /*
330 1.40 scw * The kernel never executes Thumb code.
331 1.40 scw */
332 1.79 christos printf("\n%s: Misaligned Kernel-mode Program Counter\n",
333 1.79 christos __func__);
334 1.40 scw dab_fatal(tf, fsr, far, l, NULL);
335 1.27 scw }
336 1.51 rearnsha #endif
337 1.27 scw
338 1.48 wiz /* See if the CPU state needs to be fixed up */
339 1.41 scw switch (data_abort_fixup(tf, fsr, far, l)) {
340 1.41 scw case ABORT_FIXUP_RETURN:
341 1.41 scw return;
342 1.41 scw case ABORT_FIXUP_FAILED:
343 1.41 scw /* Deliver a SIGILL to the process */
344 1.41 scw KSI_INIT_TRAP(&ksi);
345 1.41 scw ksi.ksi_signo = SIGILL;
346 1.41 scw ksi.ksi_code = ILL_ILLOPC;
347 1.41 scw ksi.ksi_addr = (u_int32_t *)(intptr_t) far;
348 1.41 scw ksi.ksi_trap = fsr;
349 1.41 scw goto do_trapsignal;
350 1.41 scw default:
351 1.41 scw break;
352 1.41 scw }
353 1.41 scw
354 1.39 scw va = trunc_page((vaddr_t)far);
355 1.1 chris
356 1.27 scw /*
357 1.27 scw * It is only a kernel address space fault iff:
358 1.27 scw * 1. user == 0 and
359 1.27 scw * 2. pcb_onfault not set or
360 1.41 scw * 3. pcb_onfault set and not LDRT/LDRBT/STRT/STRBT instruction.
361 1.27 scw */
362 1.39 scw if (user == 0 && (va >= VM_MIN_KERNEL_ADDRESS ||
363 1.41 scw (va < VM_MIN_ADDRESS && vector_page == ARM_VECTORS_LOW)) &&
364 1.41 scw __predict_true((pcb->pcb_onfault == NULL ||
365 1.41 scw (ReadWord(tf->tf_pc) & 0x05200000) != 0x04200000))) {
366 1.39 scw map = kernel_map;
367 1.39 scw
368 1.27 scw /* Was the fault due to the FPE/IPKDB ? */
369 1.39 scw if (__predict_false((tf->tf_spsr & PSR_MODE)==PSR_UND32_MODE)) {
370 1.35 thorpej KSI_INIT_TRAP(&ksi);
371 1.34 matt ksi.ksi_signo = SIGSEGV;
372 1.39 scw ksi.ksi_code = SEGV_ACCERR;
373 1.39 scw ksi.ksi_addr = (u_int32_t *)(intptr_t) far;
374 1.39 scw ksi.ksi_trap = fsr;
375 1.27 scw
376 1.27 scw /*
377 1.27 scw * Force exit via userret()
378 1.39 scw * This is necessary as the FPE is an extension to
379 1.39 scw * userland that actually runs in a priveledged mode
380 1.39 scw * but uses USR mode permissions for its accesses.
381 1.27 scw */
382 1.39 scw user = 1;
383 1.39 scw goto do_trapsignal;
384 1.27 scw }
385 1.70 wrstuden } else {
386 1.39 scw map = &l->l_proc->p_vmspace->vm_map;
387 1.70 wrstuden }
388 1.1 chris
389 1.27 scw /*
390 1.27 scw * We need to know whether the page should be mapped
391 1.27 scw * as R or R/W. The MMU does not give us the info as
392 1.27 scw * to whether the fault was caused by a read or a write.
393 1.39 scw *
394 1.39 scw * However, we know that a permission fault can only be
395 1.39 scw * the result of a write to a read-only location, so
396 1.39 scw * we can deal with those quickly.
397 1.39 scw *
398 1.39 scw * Otherwise we need to disassemble the instruction
399 1.39 scw * responsible to determine if it was a write.
400 1.27 scw */
401 1.39 scw if (IS_PERMISSION_FAULT(fsr))
402 1.27 scw ftype = VM_PROT_WRITE;
403 1.39 scw else {
404 1.51 rearnsha #ifdef THUMB_CODE
405 1.51 rearnsha /* Fast track the ARM case. */
406 1.51 rearnsha if (__predict_false(tf->tf_spsr & PSR_T_bit)) {
407 1.51 rearnsha u_int insn = fusword((void *)(tf->tf_pc & ~1));
408 1.51 rearnsha u_int insn_f8 = insn & 0xf800;
409 1.51 rearnsha u_int insn_fe = insn & 0xfe00;
410 1.51 rearnsha
411 1.51 rearnsha if (insn_f8 == 0x6000 || /* STR(1) */
412 1.51 rearnsha insn_f8 == 0x7000 || /* STRB(1) */
413 1.51 rearnsha insn_f8 == 0x8000 || /* STRH(1) */
414 1.51 rearnsha insn_f8 == 0x9000 || /* STR(3) */
415 1.51 rearnsha insn_f8 == 0xc000 || /* STM */
416 1.51 rearnsha insn_fe == 0x5000 || /* STR(2) */
417 1.51 rearnsha insn_fe == 0x5200 || /* STRH(2) */
418 1.51 rearnsha insn_fe == 0x5400) /* STRB(2) */
419 1.51 rearnsha ftype = VM_PROT_WRITE;
420 1.51 rearnsha else
421 1.51 rearnsha ftype = VM_PROT_READ;
422 1.51 rearnsha }
423 1.51 rearnsha else
424 1.51 rearnsha #endif
425 1.51 rearnsha {
426 1.51 rearnsha u_int insn = ReadWord(tf->tf_pc);
427 1.39 scw
428 1.51 rearnsha if (((insn & 0x0c100000) == 0x04000000) || /* STR[B] */
429 1.51 rearnsha ((insn & 0x0e1000b0) == 0x000000b0) || /* STR[HD]*/
430 1.81 matt ((insn & 0x0a100000) == 0x08000000) || /* STM/CDT*/
431 1.81 matt ((insn & 0x0f9000f0) == 0x01800090)) /* STREX[BDH] */
432 1.51 rearnsha ftype = VM_PROT_WRITE;
433 1.51 rearnsha else if ((insn & 0x0fb00ff0) == 0x01000090)/* SWP */
434 1.51 rearnsha ftype = VM_PROT_READ | VM_PROT_WRITE;
435 1.51 rearnsha else
436 1.51 rearnsha ftype = VM_PROT_READ;
437 1.51 rearnsha }
438 1.39 scw }
439 1.39 scw
440 1.39 scw /*
441 1.39 scw * See if the fault is as a result of ref/mod emulation,
442 1.39 scw * or domain mismatch.
443 1.39 scw */
444 1.39 scw #ifdef DEBUG
445 1.39 scw last_fault_code = fsr;
446 1.1 chris #endif
447 1.42 briggs if (pmap_fault_fixup(map->pmap, va, ftype, user)) {
448 1.50 rearnsha UVMHIST_LOG(maphist, " <- ref/mod emul", 0, 0, 0, 0);
449 1.27 scw goto out;
450 1.42 briggs }
451 1.1 chris
452 1.67 matt if (__predict_false(curcpu()->ci_intr_depth > 0)) {
453 1.45 scw if (pcb->pcb_onfault) {
454 1.45 scw tf->tf_r0 = EINVAL;
455 1.45 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
456 1.45 scw return;
457 1.45 scw }
458 1.39 scw printf("\nNon-emulated page fault with intr_depth > 0\n");
459 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
460 1.27 scw }
461 1.1 chris
462 1.27 scw onfault = pcb->pcb_onfault;
463 1.27 scw pcb->pcb_onfault = NULL;
464 1.57 he error = uvm_fault(map, va, ftype);
465 1.27 scw pcb->pcb_onfault = onfault;
466 1.39 scw
467 1.39 scw if (__predict_true(error == 0)) {
468 1.39 scw if (user)
469 1.39 scw uvm_grow(l->l_proc, va); /* Record any stack growth */
470 1.77 chs else
471 1.77 chs ucas_ras_check(tf);
472 1.50 rearnsha UVMHIST_LOG(maphist, " <- uvm", 0, 0, 0, 0);
473 1.27 scw goto out;
474 1.27 scw }
475 1.39 scw
476 1.27 scw if (user == 0) {
477 1.27 scw if (pcb->pcb_onfault) {
478 1.39 scw tf->tf_r0 = error;
479 1.39 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
480 1.39 scw return;
481 1.1 chris }
482 1.39 scw
483 1.58 drochner printf("\nuvm_fault(%p, %lx, %x) -> %x\n", map, va, ftype,
484 1.39 scw error);
485 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
486 1.27 scw }
487 1.1 chris
488 1.43 scw KSI_INIT_TRAP(&ksi);
489 1.43 scw
490 1.39 scw if (error == ENOMEM) {
491 1.39 scw printf("UVM: pid %d (%s), uid %d killed: "
492 1.39 scw "out of swap\n", l->l_proc->p_pid, l->l_proc->p_comm,
493 1.62 ad l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1);
494 1.43 scw ksi.ksi_signo = SIGKILL;
495 1.43 scw } else
496 1.43 scw ksi.ksi_signo = SIGSEGV;
497 1.34 matt
498 1.39 scw ksi.ksi_code = (error == EACCES) ? SEGV_ACCERR : SEGV_MAPERR;
499 1.39 scw ksi.ksi_addr = (u_int32_t *)(intptr_t) far;
500 1.39 scw ksi.ksi_trap = fsr;
501 1.69 is UVMHIST_LOG(maphist, " <- error (%d)", error, 0, 0, 0);
502 1.39 scw
503 1.39 scw do_trapsignal:
504 1.39 scw call_trapsignal(l, &ksi);
505 1.39 scw out:
506 1.39 scw /* If returning to user mode, make sure to invoke userret() */
507 1.39 scw if (user)
508 1.39 scw userret(l);
509 1.39 scw }
510 1.39 scw
511 1.39 scw /*
512 1.39 scw * dab_fatal() handles the following data aborts:
513 1.39 scw *
514 1.39 scw * FAULT_WRTBUF_0 - Vector Exception
515 1.39 scw * FAULT_WRTBUF_1 - Terminal Exception
516 1.39 scw *
517 1.39 scw * We should never see these on a properly functioning system.
518 1.39 scw *
519 1.39 scw * This function is also called by the other handlers if they
520 1.39 scw * detect a fatal problem.
521 1.39 scw *
522 1.39 scw * Note: If 'l' is NULL, we assume we're dealing with a prefetch abort.
523 1.39 scw */
524 1.39 scw static int
525 1.39 scw dab_fatal(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l, ksiginfo_t *ksi)
526 1.39 scw {
527 1.39 scw const char *mode;
528 1.39 scw
529 1.39 scw mode = TRAP_USERMODE(tf) ? "user" : "kernel";
530 1.39 scw
531 1.39 scw if (l != NULL) {
532 1.39 scw printf("Fatal %s mode data abort: '%s'\n", mode,
533 1.39 scw data_aborts[fsr & FAULT_TYPE_MASK].desc);
534 1.44 scw printf("trapframe: %p\nFSR=%08x, FAR=", tf, fsr);
535 1.39 scw if ((fsr & FAULT_IMPRECISE) == 0)
536 1.44 scw printf("%08x, ", far);
537 1.39 scw else
538 1.44 scw printf("Invalid, ");
539 1.44 scw printf("spsr=%08x\n", tf->tf_spsr);
540 1.39 scw } else {
541 1.44 scw printf("Fatal %s mode prefetch abort at 0x%08x\n",
542 1.44 scw mode, tf->tf_pc);
543 1.44 scw printf("trapframe: %p, spsr=%08x\n", tf, tf->tf_spsr);
544 1.44 scw }
545 1.44 scw
546 1.44 scw printf("r0 =%08x, r1 =%08x, r2 =%08x, r3 =%08x\n",
547 1.44 scw tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3);
548 1.44 scw printf("r4 =%08x, r5 =%08x, r6 =%08x, r7 =%08x\n",
549 1.44 scw tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7);
550 1.44 scw printf("r8 =%08x, r9 =%08x, r10=%08x, r11=%08x\n",
551 1.44 scw tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11);
552 1.44 scw printf("r12=%08x, ", tf->tf_r12);
553 1.44 scw
554 1.44 scw if (TRAP_USERMODE(tf))
555 1.44 scw printf("usp=%08x, ulr=%08x",
556 1.44 scw tf->tf_usr_sp, tf->tf_usr_lr);
557 1.44 scw else
558 1.44 scw printf("ssp=%08x, slr=%08x",
559 1.44 scw tf->tf_svc_sp, tf->tf_svc_lr);
560 1.44 scw printf(", pc =%08x\n\n", tf->tf_pc);
561 1.34 matt
562 1.39 scw #if defined(DDB) || defined(KGDB)
563 1.39 scw kdb_trap(T_FAULT, tf);
564 1.34 matt #endif
565 1.39 scw panic("Fatal abort");
566 1.39 scw /*NOTREACHED*/
567 1.39 scw }
568 1.39 scw
569 1.39 scw /*
570 1.39 scw * dab_align() handles the following data aborts:
571 1.39 scw *
572 1.39 scw * FAULT_ALIGN_0 - Alignment fault
573 1.39 scw * FAULT_ALIGN_0 - Alignment fault
574 1.39 scw *
575 1.39 scw * These faults are fatal if they happen in kernel mode. Otherwise, we
576 1.39 scw * deliver a bus error to the process.
577 1.39 scw */
578 1.39 scw static int
579 1.39 scw dab_align(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l, ksiginfo_t *ksi)
580 1.39 scw {
581 1.73 rmind struct pcb *pcb = lwp_getpcb(l);
582 1.39 scw
583 1.39 scw /* Alignment faults are always fatal if they occur in kernel mode */
584 1.39 scw if (!TRAP_USERMODE(tf))
585 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
586 1.39 scw
587 1.39 scw /* pcb_onfault *must* be NULL at this point */
588 1.73 rmind KDASSERT(pcb->pcb_onfault == NULL);
589 1.39 scw
590 1.48 wiz /* See if the CPU state needs to be fixed up */
591 1.39 scw (void) data_abort_fixup(tf, fsr, far, l);
592 1.39 scw
593 1.39 scw /* Deliver a bus error signal to the process */
594 1.39 scw KSI_INIT_TRAP(ksi);
595 1.39 scw ksi->ksi_signo = SIGBUS;
596 1.39 scw ksi->ksi_code = BUS_ADRALN;
597 1.39 scw ksi->ksi_addr = (u_int32_t *)(intptr_t)far;
598 1.39 scw ksi->ksi_trap = fsr;
599 1.39 scw
600 1.73 rmind pcb->pcb_tf = tf;
601 1.39 scw
602 1.39 scw return (1);
603 1.39 scw }
604 1.39 scw
605 1.39 scw /*
606 1.39 scw * dab_buserr() handles the following data aborts:
607 1.39 scw *
608 1.39 scw * FAULT_BUSERR_0 - External Abort on Linefetch -- Section
609 1.39 scw * FAULT_BUSERR_1 - External Abort on Linefetch -- Page
610 1.39 scw * FAULT_BUSERR_2 - External Abort on Non-linefetch -- Section
611 1.39 scw * FAULT_BUSERR_3 - External Abort on Non-linefetch -- Page
612 1.39 scw * FAULT_BUSTRNL1 - External abort on Translation -- Level 1
613 1.39 scw * FAULT_BUSTRNL2 - External abort on Translation -- Level 2
614 1.39 scw *
615 1.39 scw * If pcb_onfault is set, flag the fault and return to the handler.
616 1.39 scw * If the fault occurred in user mode, give the process a SIGBUS.
617 1.39 scw *
618 1.39 scw * Note: On XScale, FAULT_BUSERR_0, FAULT_BUSERR_1, and FAULT_BUSERR_2
619 1.39 scw * can be flagged as imprecise in the FSR. This causes a real headache
620 1.39 scw * since some of the machine state is lost. In this case, tf->tf_pc
621 1.39 scw * may not actually point to the offending instruction. In fact, if
622 1.39 scw * we've taken a double abort fault, it generally points somewhere near
623 1.39 scw * the top of "data_abort_entry" in exception.S.
624 1.39 scw *
625 1.39 scw * In all other cases, these data aborts are considered fatal.
626 1.39 scw */
627 1.39 scw static int
628 1.39 scw dab_buserr(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l,
629 1.39 scw ksiginfo_t *ksi)
630 1.39 scw {
631 1.73 rmind struct pcb *pcb = lwp_getpcb(l);
632 1.39 scw
633 1.39 scw #ifdef __XSCALE__
634 1.39 scw if ((fsr & FAULT_IMPRECISE) != 0 &&
635 1.39 scw (tf->tf_spsr & PSR_MODE) == PSR_ABT32_MODE) {
636 1.39 scw /*
637 1.39 scw * Oops, an imprecise, double abort fault. We've lost the
638 1.39 scw * r14_abt/spsr_abt values corresponding to the original
639 1.39 scw * abort, and the spsr saved in the trapframe indicates
640 1.39 scw * ABT mode.
641 1.39 scw */
642 1.39 scw tf->tf_spsr &= ~PSR_MODE;
643 1.39 scw
644 1.39 scw /*
645 1.39 scw * We use a simple heuristic to determine if the double abort
646 1.39 scw * happened as a result of a kernel or user mode access.
647 1.39 scw * If the current trapframe is at the top of the kernel stack,
648 1.39 scw * the fault _must_ have come from user mode.
649 1.39 scw */
650 1.39 scw if (tf != ((trapframe_t *)pcb->pcb_un.un_32.pcb32_sp) - 1) {
651 1.39 scw /*
652 1.39 scw * Kernel mode. We're either about to die a
653 1.39 scw * spectacular death, or pcb_onfault will come
654 1.39 scw * to our rescue. Either way, the current value
655 1.39 scw * of tf->tf_pc is irrelevant.
656 1.39 scw */
657 1.39 scw tf->tf_spsr |= PSR_SVC32_MODE;
658 1.39 scw if (pcb->pcb_onfault == NULL)
659 1.39 scw printf("\nKernel mode double abort!\n");
660 1.39 scw } else {
661 1.39 scw /*
662 1.39 scw * User mode. We've lost the program counter at the
663 1.39 scw * time of the fault (not that it was accurate anyway;
664 1.39 scw * it's not called an imprecise fault for nothing).
665 1.39 scw * About all we can do is copy r14_usr to tf_pc and
666 1.39 scw * hope for the best. The process is about to get a
667 1.39 scw * SIGBUS, so it's probably history anyway.
668 1.39 scw */
669 1.39 scw tf->tf_spsr |= PSR_USR32_MODE;
670 1.39 scw tf->tf_pc = tf->tf_usr_lr;
671 1.51 rearnsha #ifdef THUMB_CODE
672 1.51 rearnsha tf->tf_spsr &= ~PSR_T_bit;
673 1.51 rearnsha if (tf->tf_usr_lr & 1)
674 1.51 rearnsha tf->tf_spsr |= PSR_T_bit;
675 1.51 rearnsha #endif
676 1.39 scw }
677 1.39 scw }
678 1.39 scw
679 1.39 scw /* FAR is invalid for imprecise exceptions */
680 1.39 scw if ((fsr & FAULT_IMPRECISE) != 0)
681 1.39 scw far = 0;
682 1.39 scw #endif /* __XSCALE__ */
683 1.39 scw
684 1.39 scw if (pcb->pcb_onfault) {
685 1.39 scw KDASSERT(TRAP_USERMODE(tf) == 0);
686 1.39 scw tf->tf_r0 = EFAULT;
687 1.39 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
688 1.39 scw return (0);
689 1.39 scw }
690 1.39 scw
691 1.48 wiz /* See if the CPU state needs to be fixed up */
692 1.39 scw (void) data_abort_fixup(tf, fsr, far, l);
693 1.39 scw
694 1.39 scw /*
695 1.39 scw * At this point, if the fault happened in kernel mode, we're toast
696 1.39 scw */
697 1.39 scw if (!TRAP_USERMODE(tf))
698 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
699 1.39 scw
700 1.39 scw /* Deliver a bus error signal to the process */
701 1.39 scw KSI_INIT_TRAP(ksi);
702 1.39 scw ksi->ksi_signo = SIGBUS;
703 1.39 scw ksi->ksi_code = BUS_ADRERR;
704 1.39 scw ksi->ksi_addr = (u_int32_t *)(intptr_t)far;
705 1.39 scw ksi->ksi_trap = fsr;
706 1.39 scw
707 1.73 rmind pcb->pcb_tf = tf;
708 1.27 scw
709 1.39 scw return (1);
710 1.1 chris }
711 1.1 chris
712 1.56 perry static inline int
713 1.39 scw prefetch_abort_fixup(trapframe_t *tf)
714 1.39 scw {
715 1.39 scw #ifdef CPU_ABORT_FIXUP_REQUIRED
716 1.39 scw int error;
717 1.39 scw
718 1.48 wiz /* Call the CPU specific prefetch abort fixup routine */
719 1.39 scw error = cpu_prefetchabt_fixup(tf);
720 1.39 scw if (__predict_true(error != ABORT_FIXUP_FAILED))
721 1.39 scw return (error);
722 1.39 scw
723 1.39 scw /*
724 1.39 scw * Oops, couldn't fix up the instruction
725 1.39 scw */
726 1.79 christos printf("%s: fixup for %s mode prefetch abort failed.\n", __func__,
727 1.39 scw TRAP_USERMODE(tf) ? "user" : "kernel");
728 1.51 rearnsha #ifdef THUMB_CODE
729 1.51 rearnsha if (tf->tf_spsr & PSR_T_bit) {
730 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%04x, 0x%04x, insn = ",
731 1.75 wiz tf->tf_pc, *((u_int16 *)(tf->tf_pc & ~1)),
732 1.75 wiz *((u_int16 *)((tf->tf_pc + 2) & ~1)));
733 1.51 rearnsha }
734 1.51 rearnsha else
735 1.51 rearnsha #endif
736 1.51 rearnsha {
737 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc,
738 1.51 rearnsha *((u_int *)tf->tf_pc));
739 1.51 rearnsha }
740 1.39 scw disassemble(tf->tf_pc);
741 1.39 scw
742 1.39 scw /* Die now if this happened in kernel mode */
743 1.39 scw if (!TRAP_USERMODE(tf))
744 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
745 1.39 scw
746 1.39 scw return (error);
747 1.39 scw #else
748 1.39 scw return (ABORT_FIXUP_OK);
749 1.39 scw #endif /* CPU_ABORT_FIXUP_REQUIRED */
750 1.39 scw }
751 1.1 chris
752 1.1 chris /*
753 1.39 scw * void prefetch_abort_handler(trapframe_t *tf)
754 1.1 chris *
755 1.1 chris * Abort handler called when instruction execution occurs at
756 1.1 chris * a non existent or restricted (access permissions) memory page.
757 1.1 chris * If the address is invalid and we were in SVC mode then panic as
758 1.1 chris * the kernel should never prefetch abort.
759 1.1 chris * If the address is invalid and the page is mapped then the user process
760 1.1 chris * does no have read permission so send it a signal.
761 1.1 chris * Otherwise fault the page in and try again.
762 1.1 chris */
763 1.1 chris void
764 1.39 scw prefetch_abort_handler(trapframe_t *tf)
765 1.1 chris {
766 1.26 thorpej struct lwp *l;
767 1.73 rmind struct pcb *pcb;
768 1.14 thorpej struct vm_map *map;
769 1.14 thorpej vaddr_t fault_pc, va;
770 1.39 scw ksiginfo_t ksi;
771 1.61 ad int error, user;
772 1.39 scw
773 1.50 rearnsha UVMHIST_FUNC("prefetch_abort_handler"); UVMHIST_CALLED(maphist);
774 1.50 rearnsha
775 1.39 scw /* Update vmmeter statistics */
776 1.78 matt curcpu()->ci_data.cpu_ntrap++;
777 1.1 chris
778 1.61 ad l = curlwp;
779 1.73 rmind pcb = lwp_getpcb(l);
780 1.61 ad
781 1.61 ad if ((user = TRAP_USERMODE(tf)) != 0)
782 1.61 ad LWP_CACHE_CREDS(l, l->l_proc);
783 1.61 ad
784 1.1 chris /*
785 1.1 chris * Enable IRQ's (disabled by the abort) This always comes
786 1.1 chris * from user mode so we know interrupts were not disabled.
787 1.1 chris * But we check anyway.
788 1.1 chris */
789 1.72 matt KASSERT(!TRAP_USERMODE(tf) || (tf->tf_spsr & IF32_bits) == 0);
790 1.72 matt if (__predict_true((tf->tf_spsr & I32_bit) != IF32_bits))
791 1.72 matt restore_interrupts(tf->tf_spsr & IF32_bits);
792 1.1 chris
793 1.48 wiz /* See if the CPU state needs to be fixed up */
794 1.39 scw switch (prefetch_abort_fixup(tf)) {
795 1.39 scw case ABORT_FIXUP_RETURN:
796 1.72 matt KASSERT(!TRAP_USERMODE(tf) || (tf->tf_spsr & IF32_bits) == 0);
797 1.1 chris return;
798 1.39 scw case ABORT_FIXUP_FAILED:
799 1.39 scw /* Deliver a SIGILL to the process */
800 1.39 scw KSI_INIT_TRAP(&ksi);
801 1.39 scw ksi.ksi_signo = SIGILL;
802 1.39 scw ksi.ksi_code = ILL_ILLOPC;
803 1.39 scw ksi.ksi_addr = (u_int32_t *)(intptr_t) tf->tf_pc;
804 1.73 rmind pcb->pcb_tf = tf;
805 1.39 scw goto do_trapsignal;
806 1.39 scw default:
807 1.39 scw break;
808 1.1 chris }
809 1.1 chris
810 1.39 scw /* Prefetch aborts cannot happen in kernel mode */
811 1.61 ad if (__predict_false(!user))
812 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
813 1.1 chris
814 1.4 thorpej /* Get fault address */
815 1.39 scw fault_pc = tf->tf_pc;
816 1.73 rmind pcb->pcb_tf = tf;
817 1.50 rearnsha UVMHIST_LOG(maphist, " (pc=0x%x, l=0x%x, tf=0x%x)", fault_pc, l, tf,
818 1.50 rearnsha 0);
819 1.14 thorpej
820 1.1 chris /* Ok validate the address, can only execute in USER space */
821 1.39 scw if (__predict_false(fault_pc >= VM_MAXUSER_ADDRESS ||
822 1.39 scw (fault_pc < VM_MIN_ADDRESS && vector_page == ARM_VECTORS_LOW))) {
823 1.35 thorpej KSI_INIT_TRAP(&ksi);
824 1.34 matt ksi.ksi_signo = SIGSEGV;
825 1.34 matt ksi.ksi_code = SEGV_ACCERR;
826 1.39 scw ksi.ksi_addr = (u_int32_t *)(intptr_t) fault_pc;
827 1.34 matt ksi.ksi_trap = fault_pc;
828 1.39 scw goto do_trapsignal;
829 1.39 scw }
830 1.34 matt
831 1.39 scw map = &l->l_proc->p_vmspace->vm_map;
832 1.39 scw va = trunc_page(fault_pc);
833 1.1 chris
834 1.27 scw /*
835 1.27 scw * See if the pmap can handle this fault on its own...
836 1.27 scw */
837 1.39 scw #ifdef DEBUG
838 1.39 scw last_fault_code = -1;
839 1.39 scw #endif
840 1.50 rearnsha if (pmap_fault_fixup(map->pmap, va, VM_PROT_READ, 1)) {
841 1.50 rearnsha UVMHIST_LOG (maphist, " <- emulated", 0, 0, 0, 0);
842 1.39 scw goto out;
843 1.50 rearnsha }
844 1.27 scw
845 1.39 scw #ifdef DIAGNOSTIC
846 1.67 matt if (__predict_false(l->l_cpu->ci_intr_depth > 0)) {
847 1.39 scw printf("\nNon-emulated prefetch abort with intr_depth > 0\n");
848 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
849 1.39 scw }
850 1.1 chris #endif
851 1.72 matt
852 1.76 chs KASSERT(pcb->pcb_onfault == NULL);
853 1.57 he error = uvm_fault(map, va, VM_PROT_READ);
854 1.53 joff
855 1.50 rearnsha if (__predict_true(error == 0)) {
856 1.50 rearnsha UVMHIST_LOG (maphist, " <- uvm", 0, 0, 0, 0);
857 1.39 scw goto out;
858 1.50 rearnsha }
859 1.43 scw KSI_INIT_TRAP(&ksi);
860 1.43 scw
861 1.50 rearnsha UVMHIST_LOG (maphist, " <- fatal (%d)", error, 0, 0, 0);
862 1.39 scw if (error == ENOMEM) {
863 1.39 scw printf("UVM: pid %d (%s), uid %d killed: "
864 1.39 scw "out of swap\n", l->l_proc->p_pid, l->l_proc->p_comm,
865 1.62 ad l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1);
866 1.43 scw ksi.ksi_signo = SIGKILL;
867 1.43 scw } else
868 1.43 scw ksi.ksi_signo = SIGSEGV;
869 1.1 chris
870 1.39 scw ksi.ksi_code = SEGV_MAPERR;
871 1.39 scw ksi.ksi_addr = (u_int32_t *)(intptr_t) fault_pc;
872 1.39 scw ksi.ksi_trap = fault_pc;
873 1.39 scw
874 1.39 scw do_trapsignal:
875 1.39 scw call_trapsignal(l, &ksi);
876 1.39 scw
877 1.39 scw out:
878 1.72 matt KASSERT(!TRAP_USERMODE(tf) || (tf->tf_spsr & IF32_bits) == 0);
879 1.39 scw userret(l);
880 1.39 scw }
881 1.39 scw
882 1.39 scw /*
883 1.39 scw * Tentatively read an 8, 16, or 32-bit value from 'addr'.
884 1.39 scw * If the read succeeds, the value is written to 'rptr' and zero is returned.
885 1.39 scw * Else, return EFAULT.
886 1.39 scw */
887 1.39 scw int
888 1.39 scw badaddr_read(void *addr, size_t size, void *rptr)
889 1.39 scw {
890 1.39 scw extern int badaddr_read_1(const uint8_t *, uint8_t *);
891 1.39 scw extern int badaddr_read_2(const uint16_t *, uint16_t *);
892 1.39 scw extern int badaddr_read_4(const uint32_t *, uint32_t *);
893 1.39 scw union {
894 1.39 scw uint8_t v1;
895 1.39 scw uint16_t v2;
896 1.39 scw uint32_t v4;
897 1.39 scw } u;
898 1.47 scw int rv, s;
899 1.39 scw
900 1.39 scw cpu_drain_writebuf();
901 1.39 scw
902 1.47 scw s = splhigh();
903 1.47 scw
904 1.39 scw /* Read from the test address. */
905 1.39 scw switch (size) {
906 1.39 scw case sizeof(uint8_t):
907 1.39 scw rv = badaddr_read_1(addr, &u.v1);
908 1.39 scw if (rv == 0 && rptr)
909 1.39 scw *(uint8_t *) rptr = u.v1;
910 1.39 scw break;
911 1.39 scw
912 1.39 scw case sizeof(uint16_t):
913 1.39 scw rv = badaddr_read_2(addr, &u.v2);
914 1.39 scw if (rv == 0 && rptr)
915 1.39 scw *(uint16_t *) rptr = u.v2;
916 1.39 scw break;
917 1.39 scw
918 1.39 scw case sizeof(uint32_t):
919 1.39 scw rv = badaddr_read_4(addr, &u.v4);
920 1.39 scw if (rv == 0 && rptr)
921 1.39 scw *(uint32_t *) rptr = u.v4;
922 1.39 scw break;
923 1.39 scw
924 1.39 scw default:
925 1.82 matt panic("%s: invalid size (%zu)", __func__, size);
926 1.34 matt }
927 1.39 scw
928 1.47 scw splx(s);
929 1.47 scw
930 1.39 scw /* Return EFAULT if the address was invalid, else zero */
931 1.39 scw return (rv);
932 1.1 chris }
933