fault.c revision 1.97 1 1.97 matt /* $NetBSD: fault.c,v 1.97 2014/03/05 02:10:39 matt Exp $ */
2 1.1 chris
3 1.1 chris /*
4 1.27 scw * Copyright 2003 Wasabi Systems, Inc.
5 1.27 scw * All rights reserved.
6 1.27 scw *
7 1.27 scw * Written by Steve C. Woodford for Wasabi Systems, Inc.
8 1.27 scw *
9 1.27 scw * Redistribution and use in source and binary forms, with or without
10 1.27 scw * modification, are permitted provided that the following conditions
11 1.27 scw * are met:
12 1.27 scw * 1. Redistributions of source code must retain the above copyright
13 1.27 scw * notice, this list of conditions and the following disclaimer.
14 1.27 scw * 2. Redistributions in binary form must reproduce the above copyright
15 1.27 scw * notice, this list of conditions and the following disclaimer in the
16 1.27 scw * documentation and/or other materials provided with the distribution.
17 1.27 scw * 3. All advertising materials mentioning features or use of this software
18 1.27 scw * must display the following acknowledgement:
19 1.27 scw * This product includes software developed for the NetBSD Project by
20 1.27 scw * Wasabi Systems, Inc.
21 1.27 scw * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.27 scw * or promote products derived from this software without specific prior
23 1.27 scw * written permission.
24 1.27 scw *
25 1.27 scw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.27 scw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.27 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.27 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.27 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.27 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.27 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.27 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.27 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.27 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.27 scw * POSSIBILITY OF SUCH DAMAGE.
36 1.27 scw */
37 1.27 scw /*
38 1.1 chris * Copyright (c) 1994-1997 Mark Brinicombe.
39 1.1 chris * Copyright (c) 1994 Brini.
40 1.1 chris * All rights reserved.
41 1.1 chris *
42 1.1 chris * This code is derived from software written for Brini by Mark Brinicombe
43 1.1 chris *
44 1.1 chris * Redistribution and use in source and binary forms, with or without
45 1.1 chris * modification, are permitted provided that the following conditions
46 1.1 chris * are met:
47 1.1 chris * 1. Redistributions of source code must retain the above copyright
48 1.1 chris * notice, this list of conditions and the following disclaimer.
49 1.1 chris * 2. Redistributions in binary form must reproduce the above copyright
50 1.1 chris * notice, this list of conditions and the following disclaimer in the
51 1.1 chris * documentation and/or other materials provided with the distribution.
52 1.1 chris * 3. All advertising materials mentioning features or use of this software
53 1.1 chris * must display the following acknowledgement:
54 1.1 chris * This product includes software developed by Brini.
55 1.1 chris * 4. The name of the company nor the name of the author may be used to
56 1.1 chris * endorse or promote products derived from this software without specific
57 1.1 chris * prior written permission.
58 1.1 chris *
59 1.1 chris * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
60 1.1 chris * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
61 1.1 chris * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
62 1.1 chris * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
63 1.1 chris * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
64 1.1 chris * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
65 1.1 chris * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 1.1 chris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 1.1 chris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 1.1 chris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 1.1 chris * SUCH DAMAGE.
70 1.1 chris *
71 1.1 chris * RiscBSD kernel project
72 1.1 chris *
73 1.1 chris * fault.c
74 1.1 chris *
75 1.1 chris * Fault handlers
76 1.1 chris *
77 1.1 chris * Created : 28/11/94
78 1.1 chris */
79 1.1 chris
80 1.1 chris #include "opt_ddb.h"
81 1.28 briggs #include "opt_kgdb.h"
82 1.1 chris
83 1.1 chris #include <sys/types.h>
84 1.97 matt __KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.97 2014/03/05 02:10:39 matt Exp $");
85 1.21 bjh21
86 1.1 chris #include <sys/param.h>
87 1.1 chris #include <sys/systm.h>
88 1.1 chris #include <sys/proc.h>
89 1.1 chris #include <sys/kernel.h>
90 1.60 yamt #include <sys/kauth.h>
91 1.65 matt #include <sys/cpu.h>
92 1.90 matt #include <sys/intr.h>
93 1.1 chris
94 1.1 chris #include <uvm/uvm_extern.h>
95 1.50 rearnsha #include <uvm/uvm_stat.h>
96 1.50 rearnsha #ifdef UVMHIST
97 1.50 rearnsha #include <uvm/uvm.h>
98 1.50 rearnsha #endif
99 1.18 thorpej
100 1.90 matt #include <arm/locore.h>
101 1.1 chris
102 1.5 thorpej #include <arm/arm32/katelib.h>
103 1.83 matt
104 1.83 matt #include <machine/pcb.h>
105 1.28 briggs #if defined(DDB) || defined(KGDB)
106 1.1 chris #include <machine/db_machdep.h>
107 1.28 briggs #ifdef KGDB
108 1.28 briggs #include <sys/kgdb.h>
109 1.28 briggs #endif
110 1.28 briggs #if !defined(DDB)
111 1.28 briggs #define kdb_trap kgdb_trap
112 1.28 briggs #endif
113 1.1 chris #endif
114 1.1 chris
115 1.1 chris #include <arch/arm/arm/disassem.h>
116 1.7 chris #include <arm/arm32/machdep.h>
117 1.7 chris
118 1.1 chris extern char fusubailout[];
119 1.1 chris
120 1.27 scw #ifdef DEBUG
121 1.27 scw int last_fault_code; /* For the benefit of pmap_fault_fixup() */
122 1.27 scw #endif
123 1.27 scw
124 1.39 scw #if defined(CPU_ARM3) || defined(CPU_ARM6) || \
125 1.39 scw defined(CPU_ARM7) || defined(CPU_ARM7TDMI)
126 1.39 scw /* These CPUs may need data/prefetch abort fixups */
127 1.39 scw #define CPU_ABORT_FIXUP_REQUIRED
128 1.39 scw #endif
129 1.7 chris
130 1.39 scw struct data_abort {
131 1.39 scw int (*func)(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
132 1.39 scw const char *desc;
133 1.39 scw };
134 1.1 chris
135 1.39 scw static int dab_fatal(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
136 1.39 scw static int dab_align(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
137 1.39 scw static int dab_buserr(trapframe_t *, u_int, u_int, struct lwp *, ksiginfo_t *);
138 1.39 scw
139 1.39 scw static const struct data_abort data_aborts[] = {
140 1.39 scw {dab_fatal, "Vector Exception"},
141 1.39 scw {dab_align, "Alignment Fault 1"},
142 1.39 scw {dab_fatal, "Terminal Exception"},
143 1.39 scw {dab_align, "Alignment Fault 3"},
144 1.39 scw {dab_buserr, "External Linefetch Abort (S)"},
145 1.39 scw {NULL, "Translation Fault (S)"},
146 1.39 scw {dab_buserr, "External Linefetch Abort (P)"},
147 1.39 scw {NULL, "Translation Fault (P)"},
148 1.39 scw {dab_buserr, "External Non-Linefetch Abort (S)"},
149 1.39 scw {NULL, "Domain Fault (S)"},
150 1.39 scw {dab_buserr, "External Non-Linefetch Abort (P)"},
151 1.39 scw {NULL, "Domain Fault (P)"},
152 1.39 scw {dab_buserr, "External Translation Abort (L1)"},
153 1.39 scw {NULL, "Permission Fault (S)"},
154 1.39 scw {dab_buserr, "External Translation Abort (L2)"},
155 1.39 scw {NULL, "Permission Fault (P)"}
156 1.39 scw };
157 1.1 chris
158 1.39 scw /* Determine if 'x' is a permission fault */
159 1.39 scw #define IS_PERMISSION_FAULT(x) \
160 1.39 scw (((1 << ((x) & FAULT_TYPE_MASK)) & \
161 1.39 scw ((1 << FAULT_PERM_P) | (1 << FAULT_PERM_S))) != 0)
162 1.1 chris
163 1.39 scw #if 0
164 1.39 scw /* maybe one day we'll do emulations */
165 1.39 scw #define TRAPSIGNAL(l,k) (*(l)->l_proc->p_emul->e_trapsignal)((l), (k))
166 1.39 scw #else
167 1.39 scw #define TRAPSIGNAL(l,k) trapsignal((l), (k))
168 1.1 chris #endif
169 1.3 thorpej
170 1.56 perry static inline void
171 1.93 matt call_trapsignal(struct lwp *l, const struct trapframe *tf, ksiginfo_t *ksi)
172 1.3 thorpej {
173 1.93 matt if (l->l_proc->p_pid == 1 || cpu_printfataltraps) {
174 1.93 matt printf("%d.%d(%s): trap: signo=%d code=%d addr=%p trap=%#x\n",
175 1.93 matt l->l_proc->p_pid, l->l_lid, l->l_proc->p_comm,
176 1.93 matt ksi->ksi_signo, ksi->ksi_code, ksi->ksi_addr,
177 1.93 matt ksi->ksi_trap);
178 1.93 matt printf("r0=%08x r1=%08x r2=%08x r3=%08x\n",
179 1.93 matt tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3);
180 1.93 matt printf("r4=%08x r5=%08x r6=%08x r7=%08x\n",
181 1.93 matt tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7);
182 1.93 matt printf("r8=%08x r9=%08x rA=%08x rB=%08x\n",
183 1.93 matt tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11);
184 1.93 matt printf("ip=%08x sp=%08x lr=%08x pc=%08x spsr=%08x\n",
185 1.93 matt tf->tf_r12, tf->tf_usr_sp, tf->tf_usr_lr, tf->tf_pc,
186 1.93 matt tf->tf_spsr);
187 1.93 matt }
188 1.3 thorpej
189 1.39 scw TRAPSIGNAL(l, ksi);
190 1.39 scw }
191 1.3 thorpej
192 1.56 perry static inline int
193 1.39 scw data_abort_fixup(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l)
194 1.39 scw {
195 1.39 scw #ifdef CPU_ABORT_FIXUP_REQUIRED
196 1.39 scw int error;
197 1.3 thorpej
198 1.48 wiz /* Call the CPU specific data abort fixup routine */
199 1.39 scw error = cpu_dataabt_fixup(tf);
200 1.39 scw if (__predict_true(error != ABORT_FIXUP_FAILED))
201 1.39 scw return (error);
202 1.3 thorpej
203 1.39 scw /*
204 1.39 scw * Oops, couldn't fix up the instruction
205 1.39 scw */
206 1.79 christos printf("%s: fixup for %s mode data abort failed.\n", __func__,
207 1.39 scw TRAP_USERMODE(tf) ? "user" : "kernel");
208 1.51 rearnsha #ifdef THUMB_CODE
209 1.51 rearnsha if (tf->tf_spsr & PSR_T_bit) {
210 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%04x, 0x%04x, insn = ",
211 1.86 skrll tf->tf_pc, *((uint16 *)(tf->tf_pc & ~1)),
212 1.86 skrll *((uint16 *)((tf->tf_pc + 2) & ~1)));
213 1.51 rearnsha }
214 1.51 rearnsha else
215 1.51 rearnsha #endif
216 1.51 rearnsha {
217 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc,
218 1.51 rearnsha *((u_int *)tf->tf_pc));
219 1.51 rearnsha }
220 1.39 scw disassemble(tf->tf_pc);
221 1.39 scw
222 1.39 scw /* Die now if this happened in kernel mode */
223 1.39 scw if (!TRAP_USERMODE(tf))
224 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
225 1.3 thorpej
226 1.39 scw return (error);
227 1.39 scw #else
228 1.39 scw return (ABORT_FIXUP_OK);
229 1.39 scw #endif /* CPU_ABORT_FIXUP_REQUIRED */
230 1.3 thorpej }
231 1.3 thorpej
232 1.1 chris void
233 1.39 scw data_abort_handler(trapframe_t *tf)
234 1.1 chris {
235 1.39 scw struct vm_map *map;
236 1.83 matt struct lwp * const l = curlwp;
237 1.83 matt struct cpu_info * const ci = curcpu();
238 1.83 matt u_int far, fsr;
239 1.39 scw vm_prot_t ftype;
240 1.1 chris void *onfault;
241 1.27 scw vaddr_t va;
242 1.39 scw int error;
243 1.34 matt ksiginfo_t ksi;
244 1.3 thorpej
245 1.97 matt UVMHIST_FUNC(__func__);
246 1.97 matt #ifdef UVMHIST
247 1.97 matt if (__predict_true(maphist.e)) {
248 1.97 matt UVMHIST_CALLED(maphist);
249 1.97 matt }
250 1.97 matt #endif
251 1.50 rearnsha
252 1.39 scw /* Grab FAR/FSR before enabling interrupts */
253 1.39 scw far = cpu_faultaddress();
254 1.39 scw fsr = cpu_faultstatus();
255 1.1 chris
256 1.39 scw /* Update vmmeter statistics */
257 1.83 matt ci->ci_data.cpu_ntrap++;
258 1.1 chris
259 1.39 scw /* Re-enable interrupts if they were enabled previously */
260 1.72 matt KASSERT(!TRAP_USERMODE(tf) || (tf->tf_spsr & IF32_bits) == 0);
261 1.72 matt if (__predict_true((tf->tf_spsr & IF32_bits) != IF32_bits))
262 1.72 matt restore_interrupts(tf->tf_spsr & IF32_bits);
263 1.1 chris
264 1.67 matt /* Get the current lwp structure */
265 1.1 chris
266 1.97 matt #ifdef UVMHIST
267 1.97 matt if (__predict_true(maphist.e)) {
268 1.97 matt UVMHIST_LOG(maphist, " (l=%#x, far=%#x, fsr=%#x",
269 1.97 matt l, far, fsr, 0);
270 1.97 matt UVMHIST_LOG(maphist, " tf=%#x, pc=%#x)",
271 1.97 matt tf, tf->tf_pc, 0, 0);
272 1.97 matt }
273 1.97 matt #endif
274 1.50 rearnsha
275 1.39 scw /* Data abort came from user mode? */
276 1.83 matt bool user = (TRAP_USERMODE(tf) != 0);
277 1.83 matt if (user)
278 1.61 ad LWP_CACHE_CREDS(l, l->l_proc);
279 1.1 chris
280 1.39 scw /* Grab the current pcb */
281 1.83 matt struct pcb * const pcb = lwp_getpcb(l);
282 1.1 chris
283 1.85 matt curcpu()->ci_abt_evs[fsr & FAULT_TYPE_MASK].ev_count++;
284 1.85 matt
285 1.39 scw /* Invoke the appropriate handler, if necessary */
286 1.39 scw if (__predict_false(data_aborts[fsr & FAULT_TYPE_MASK].func != NULL)) {
287 1.79 christos #ifdef DIAGNOSTIC
288 1.79 christos printf("%s: data_aborts fsr=0x%x far=0x%x\n",
289 1.79 christos __func__, fsr, far);
290 1.79 christos #endif
291 1.39 scw if ((data_aborts[fsr & FAULT_TYPE_MASK].func)(tf, fsr, far,
292 1.39 scw l, &ksi))
293 1.39 scw goto do_trapsignal;
294 1.39 scw goto out;
295 1.39 scw }
296 1.1 chris
297 1.1 chris /*
298 1.39 scw * At this point, we're dealing with one of the following data aborts:
299 1.39 scw *
300 1.39 scw * FAULT_TRANS_S - Translation -- Section
301 1.39 scw * FAULT_TRANS_P - Translation -- Page
302 1.39 scw * FAULT_DOMAIN_S - Domain -- Section
303 1.39 scw * FAULT_DOMAIN_P - Domain -- Page
304 1.39 scw * FAULT_PERM_S - Permission -- Section
305 1.39 scw * FAULT_PERM_P - Permission -- Page
306 1.39 scw *
307 1.39 scw * These are the main virtual memory-related faults signalled by
308 1.39 scw * the MMU.
309 1.1 chris */
310 1.1 chris
311 1.1 chris /* fusubailout is used by [fs]uswintr to avoid page faulting */
312 1.39 scw if (__predict_false(pcb->pcb_onfault == fusubailout)) {
313 1.39 scw tf->tf_r0 = EFAULT;
314 1.83 matt tf->tf_pc = (intptr_t) pcb->pcb_onfault;
315 1.1 chris return;
316 1.1 chris }
317 1.1 chris
318 1.73 rmind if (user) {
319 1.83 matt lwp_settrapframe(l, tf);
320 1.73 rmind }
321 1.1 chris
322 1.40 scw /*
323 1.40 scw * Make sure the Program Counter is sane. We could fall foul of
324 1.40 scw * someone executing Thumb code, in which case the PC might not
325 1.40 scw * be word-aligned. This would cause a kernel alignment fault
326 1.40 scw * further down if we have to decode the current instruction.
327 1.40 scw */
328 1.51 rearnsha #ifdef THUMB_CODE
329 1.51 rearnsha /*
330 1.51 rearnsha * XXX: It would be nice to be able to support Thumb in the kernel
331 1.51 rearnsha * at some point.
332 1.51 rearnsha */
333 1.51 rearnsha if (__predict_false(!user && (tf->tf_pc & 3) != 0)) {
334 1.79 christos printf("\n%s: Misaligned Kernel-mode Program Counter\n",
335 1.79 christos __func__);
336 1.51 rearnsha dab_fatal(tf, fsr, far, l, NULL);
337 1.51 rearnsha }
338 1.51 rearnsha #else
339 1.40 scw if (__predict_false((tf->tf_pc & 3) != 0)) {
340 1.40 scw if (user) {
341 1.40 scw /*
342 1.40 scw * Give the user an illegal instruction signal.
343 1.40 scw */
344 1.40 scw /* Deliver a SIGILL to the process */
345 1.40 scw KSI_INIT_TRAP(&ksi);
346 1.40 scw ksi.ksi_signo = SIGILL;
347 1.40 scw ksi.ksi_code = ILL_ILLOPC;
348 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
349 1.40 scw ksi.ksi_trap = fsr;
350 1.40 scw goto do_trapsignal;
351 1.40 scw }
352 1.40 scw
353 1.40 scw /*
354 1.40 scw * The kernel never executes Thumb code.
355 1.40 scw */
356 1.79 christos printf("\n%s: Misaligned Kernel-mode Program Counter\n",
357 1.79 christos __func__);
358 1.40 scw dab_fatal(tf, fsr, far, l, NULL);
359 1.27 scw }
360 1.51 rearnsha #endif
361 1.27 scw
362 1.48 wiz /* See if the CPU state needs to be fixed up */
363 1.41 scw switch (data_abort_fixup(tf, fsr, far, l)) {
364 1.41 scw case ABORT_FIXUP_RETURN:
365 1.41 scw return;
366 1.41 scw case ABORT_FIXUP_FAILED:
367 1.41 scw /* Deliver a SIGILL to the process */
368 1.41 scw KSI_INIT_TRAP(&ksi);
369 1.41 scw ksi.ksi_signo = SIGILL;
370 1.41 scw ksi.ksi_code = ILL_ILLOPC;
371 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
372 1.41 scw ksi.ksi_trap = fsr;
373 1.41 scw goto do_trapsignal;
374 1.41 scw default:
375 1.41 scw break;
376 1.41 scw }
377 1.41 scw
378 1.39 scw va = trunc_page((vaddr_t)far);
379 1.1 chris
380 1.27 scw /*
381 1.27 scw * It is only a kernel address space fault iff:
382 1.27 scw * 1. user == 0 and
383 1.27 scw * 2. pcb_onfault not set or
384 1.41 scw * 3. pcb_onfault set and not LDRT/LDRBT/STRT/STRBT instruction.
385 1.27 scw */
386 1.83 matt if (!user && (va >= VM_MIN_KERNEL_ADDRESS ||
387 1.41 scw (va < VM_MIN_ADDRESS && vector_page == ARM_VECTORS_LOW)) &&
388 1.41 scw __predict_true((pcb->pcb_onfault == NULL ||
389 1.93 matt (read_insn(tf->tf_pc, false) & 0x05200000) != 0x04200000))) {
390 1.39 scw map = kernel_map;
391 1.39 scw
392 1.27 scw /* Was the fault due to the FPE/IPKDB ? */
393 1.39 scw if (__predict_false((tf->tf_spsr & PSR_MODE)==PSR_UND32_MODE)) {
394 1.35 thorpej KSI_INIT_TRAP(&ksi);
395 1.34 matt ksi.ksi_signo = SIGSEGV;
396 1.39 scw ksi.ksi_code = SEGV_ACCERR;
397 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
398 1.39 scw ksi.ksi_trap = fsr;
399 1.27 scw
400 1.27 scw /*
401 1.27 scw * Force exit via userret()
402 1.39 scw * This is necessary as the FPE is an extension to
403 1.39 scw * userland that actually runs in a priveledged mode
404 1.39 scw * but uses USR mode permissions for its accesses.
405 1.27 scw */
406 1.83 matt user = true;
407 1.39 scw goto do_trapsignal;
408 1.27 scw }
409 1.70 wrstuden } else {
410 1.39 scw map = &l->l_proc->p_vmspace->vm_map;
411 1.70 wrstuden }
412 1.1 chris
413 1.27 scw /*
414 1.94 matt * We need to know whether the page should be mapped as R or R/W.
415 1.94 matt * Before ARMv6, the MMU did not give us the info as to whether the
416 1.94 matt * fault was caused by a read or a write.
417 1.39 scw *
418 1.94 matt * However, we know that a permission fault can only be the result of
419 1.94 matt * a write to a read-only location, so we can deal with those quickly.
420 1.39 scw *
421 1.94 matt * Otherwise we need to disassemble the instruction responsible to
422 1.94 matt * determine if it was a write.
423 1.27 scw */
424 1.96 skrll if (CPU_IS_ARMV6_P() || CPU_IS_ARMV7_P()) {
425 1.94 matt ftype = (fsr & FAULT_WRITE) ? VM_PROT_WRITE : VM_PROT_READ;
426 1.94 matt } else if (IS_PERMISSION_FAULT(fsr)) {
427 1.27 scw ftype = VM_PROT_WRITE;
428 1.94 matt } else {
429 1.51 rearnsha #ifdef THUMB_CODE
430 1.51 rearnsha /* Fast track the ARM case. */
431 1.51 rearnsha if (__predict_false(tf->tf_spsr & PSR_T_bit)) {
432 1.93 matt u_int insn = read_thumb_insn(tf->tf_pc, user);
433 1.51 rearnsha u_int insn_f8 = insn & 0xf800;
434 1.51 rearnsha u_int insn_fe = insn & 0xfe00;
435 1.51 rearnsha
436 1.51 rearnsha if (insn_f8 == 0x6000 || /* STR(1) */
437 1.51 rearnsha insn_f8 == 0x7000 || /* STRB(1) */
438 1.51 rearnsha insn_f8 == 0x8000 || /* STRH(1) */
439 1.51 rearnsha insn_f8 == 0x9000 || /* STR(3) */
440 1.51 rearnsha insn_f8 == 0xc000 || /* STM */
441 1.51 rearnsha insn_fe == 0x5000 || /* STR(2) */
442 1.51 rearnsha insn_fe == 0x5200 || /* STRH(2) */
443 1.51 rearnsha insn_fe == 0x5400) /* STRB(2) */
444 1.51 rearnsha ftype = VM_PROT_WRITE;
445 1.51 rearnsha else
446 1.51 rearnsha ftype = VM_PROT_READ;
447 1.51 rearnsha }
448 1.51 rearnsha else
449 1.51 rearnsha #endif
450 1.51 rearnsha {
451 1.93 matt u_int insn = read_insn(tf->tf_pc, user);
452 1.39 scw
453 1.51 rearnsha if (((insn & 0x0c100000) == 0x04000000) || /* STR[B] */
454 1.51 rearnsha ((insn & 0x0e1000b0) == 0x000000b0) || /* STR[HD]*/
455 1.81 matt ((insn & 0x0a100000) == 0x08000000) || /* STM/CDT*/
456 1.81 matt ((insn & 0x0f9000f0) == 0x01800090)) /* STREX[BDH] */
457 1.51 rearnsha ftype = VM_PROT_WRITE;
458 1.51 rearnsha else if ((insn & 0x0fb00ff0) == 0x01000090)/* SWP */
459 1.51 rearnsha ftype = VM_PROT_READ | VM_PROT_WRITE;
460 1.51 rearnsha else
461 1.51 rearnsha ftype = VM_PROT_READ;
462 1.51 rearnsha }
463 1.39 scw }
464 1.39 scw
465 1.39 scw /*
466 1.39 scw * See if the fault is as a result of ref/mod emulation,
467 1.39 scw * or domain mismatch.
468 1.39 scw */
469 1.39 scw #ifdef DEBUG
470 1.39 scw last_fault_code = fsr;
471 1.1 chris #endif
472 1.42 briggs if (pmap_fault_fixup(map->pmap, va, ftype, user)) {
473 1.97 matt #ifdef UVMHIST
474 1.97 matt if (__predict_true(maphist.e)) {
475 1.97 matt UVMHIST_LOG(maphist, " <- ref/mod emul", 0, 0, 0, 0);
476 1.97 matt }
477 1.97 matt #endif
478 1.27 scw goto out;
479 1.42 briggs }
480 1.1 chris
481 1.67 matt if (__predict_false(curcpu()->ci_intr_depth > 0)) {
482 1.45 scw if (pcb->pcb_onfault) {
483 1.45 scw tf->tf_r0 = EINVAL;
484 1.45 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
485 1.45 scw return;
486 1.45 scw }
487 1.39 scw printf("\nNon-emulated page fault with intr_depth > 0\n");
488 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
489 1.27 scw }
490 1.1 chris
491 1.27 scw onfault = pcb->pcb_onfault;
492 1.27 scw pcb->pcb_onfault = NULL;
493 1.57 he error = uvm_fault(map, va, ftype);
494 1.27 scw pcb->pcb_onfault = onfault;
495 1.39 scw
496 1.39 scw if (__predict_true(error == 0)) {
497 1.39 scw if (user)
498 1.39 scw uvm_grow(l->l_proc, va); /* Record any stack growth */
499 1.77 chs else
500 1.77 chs ucas_ras_check(tf);
501 1.97 matt #ifdef UVMHIST
502 1.97 matt if (__predict_true(maphist.e)) {
503 1.97 matt UVMHIST_LOG(maphist, " <- uvm", 0, 0, 0, 0);
504 1.97 matt }
505 1.97 matt #endif
506 1.27 scw goto out;
507 1.27 scw }
508 1.39 scw
509 1.27 scw if (user == 0) {
510 1.27 scw if (pcb->pcb_onfault) {
511 1.39 scw tf->tf_r0 = error;
512 1.39 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
513 1.39 scw return;
514 1.1 chris }
515 1.39 scw
516 1.58 drochner printf("\nuvm_fault(%p, %lx, %x) -> %x\n", map, va, ftype,
517 1.39 scw error);
518 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
519 1.27 scw }
520 1.1 chris
521 1.43 scw KSI_INIT_TRAP(&ksi);
522 1.43 scw
523 1.39 scw if (error == ENOMEM) {
524 1.39 scw printf("UVM: pid %d (%s), uid %d killed: "
525 1.39 scw "out of swap\n", l->l_proc->p_pid, l->l_proc->p_comm,
526 1.62 ad l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1);
527 1.43 scw ksi.ksi_signo = SIGKILL;
528 1.43 scw } else
529 1.43 scw ksi.ksi_signo = SIGSEGV;
530 1.34 matt
531 1.39 scw ksi.ksi_code = (error == EACCES) ? SEGV_ACCERR : SEGV_MAPERR;
532 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) far;
533 1.39 scw ksi.ksi_trap = fsr;
534 1.97 matt #ifdef UVMHIST
535 1.97 matt if (__predict_true(maphist.e)) {
536 1.97 matt UVMHIST_LOG(maphist, " <- error (%d)", error, 0, 0, 0);
537 1.97 matt }
538 1.97 matt #endif
539 1.39 scw
540 1.39 scw do_trapsignal:
541 1.93 matt call_trapsignal(l, tf, &ksi);
542 1.39 scw out:
543 1.39 scw /* If returning to user mode, make sure to invoke userret() */
544 1.39 scw if (user)
545 1.39 scw userret(l);
546 1.39 scw }
547 1.39 scw
548 1.39 scw /*
549 1.39 scw * dab_fatal() handles the following data aborts:
550 1.39 scw *
551 1.39 scw * FAULT_WRTBUF_0 - Vector Exception
552 1.39 scw * FAULT_WRTBUF_1 - Terminal Exception
553 1.39 scw *
554 1.39 scw * We should never see these on a properly functioning system.
555 1.39 scw *
556 1.39 scw * This function is also called by the other handlers if they
557 1.39 scw * detect a fatal problem.
558 1.39 scw *
559 1.39 scw * Note: If 'l' is NULL, we assume we're dealing with a prefetch abort.
560 1.39 scw */
561 1.39 scw static int
562 1.39 scw dab_fatal(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l, ksiginfo_t *ksi)
563 1.39 scw {
564 1.83 matt const char * const mode = TRAP_USERMODE(tf) ? "user" : "kernel";
565 1.39 scw
566 1.39 scw if (l != NULL) {
567 1.39 scw printf("Fatal %s mode data abort: '%s'\n", mode,
568 1.39 scw data_aborts[fsr & FAULT_TYPE_MASK].desc);
569 1.44 scw printf("trapframe: %p\nFSR=%08x, FAR=", tf, fsr);
570 1.39 scw if ((fsr & FAULT_IMPRECISE) == 0)
571 1.44 scw printf("%08x, ", far);
572 1.39 scw else
573 1.44 scw printf("Invalid, ");
574 1.44 scw printf("spsr=%08x\n", tf->tf_spsr);
575 1.39 scw } else {
576 1.44 scw printf("Fatal %s mode prefetch abort at 0x%08x\n",
577 1.44 scw mode, tf->tf_pc);
578 1.44 scw printf("trapframe: %p, spsr=%08x\n", tf, tf->tf_spsr);
579 1.44 scw }
580 1.44 scw
581 1.44 scw printf("r0 =%08x, r1 =%08x, r2 =%08x, r3 =%08x\n",
582 1.44 scw tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3);
583 1.44 scw printf("r4 =%08x, r5 =%08x, r6 =%08x, r7 =%08x\n",
584 1.44 scw tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7);
585 1.44 scw printf("r8 =%08x, r9 =%08x, r10=%08x, r11=%08x\n",
586 1.44 scw tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11);
587 1.44 scw printf("r12=%08x, ", tf->tf_r12);
588 1.44 scw
589 1.44 scw if (TRAP_USERMODE(tf))
590 1.44 scw printf("usp=%08x, ulr=%08x",
591 1.44 scw tf->tf_usr_sp, tf->tf_usr_lr);
592 1.44 scw else
593 1.44 scw printf("ssp=%08x, slr=%08x",
594 1.44 scw tf->tf_svc_sp, tf->tf_svc_lr);
595 1.44 scw printf(", pc =%08x\n\n", tf->tf_pc);
596 1.34 matt
597 1.39 scw #if defined(DDB) || defined(KGDB)
598 1.39 scw kdb_trap(T_FAULT, tf);
599 1.34 matt #endif
600 1.39 scw panic("Fatal abort");
601 1.39 scw /*NOTREACHED*/
602 1.39 scw }
603 1.39 scw
604 1.39 scw /*
605 1.39 scw * dab_align() handles the following data aborts:
606 1.39 scw *
607 1.39 scw * FAULT_ALIGN_0 - Alignment fault
608 1.39 scw * FAULT_ALIGN_0 - Alignment fault
609 1.39 scw *
610 1.39 scw * These faults are fatal if they happen in kernel mode. Otherwise, we
611 1.39 scw * deliver a bus error to the process.
612 1.39 scw */
613 1.39 scw static int
614 1.39 scw dab_align(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l, ksiginfo_t *ksi)
615 1.39 scw {
616 1.39 scw /* Alignment faults are always fatal if they occur in kernel mode */
617 1.39 scw if (!TRAP_USERMODE(tf))
618 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
619 1.39 scw
620 1.39 scw /* pcb_onfault *must* be NULL at this point */
621 1.83 matt KDASSERT(((struct pcb *)lwp_getpcb(l))->pcb_onfault == NULL);
622 1.39 scw
623 1.48 wiz /* See if the CPU state needs to be fixed up */
624 1.39 scw (void) data_abort_fixup(tf, fsr, far, l);
625 1.39 scw
626 1.39 scw /* Deliver a bus error signal to the process */
627 1.39 scw KSI_INIT_TRAP(ksi);
628 1.39 scw ksi->ksi_signo = SIGBUS;
629 1.39 scw ksi->ksi_code = BUS_ADRALN;
630 1.86 skrll ksi->ksi_addr = (uint32_t *)(intptr_t)far;
631 1.39 scw ksi->ksi_trap = fsr;
632 1.39 scw
633 1.83 matt lwp_settrapframe(l, tf);
634 1.39 scw
635 1.39 scw return (1);
636 1.39 scw }
637 1.39 scw
638 1.39 scw /*
639 1.39 scw * dab_buserr() handles the following data aborts:
640 1.39 scw *
641 1.39 scw * FAULT_BUSERR_0 - External Abort on Linefetch -- Section
642 1.39 scw * FAULT_BUSERR_1 - External Abort on Linefetch -- Page
643 1.39 scw * FAULT_BUSERR_2 - External Abort on Non-linefetch -- Section
644 1.39 scw * FAULT_BUSERR_3 - External Abort on Non-linefetch -- Page
645 1.39 scw * FAULT_BUSTRNL1 - External abort on Translation -- Level 1
646 1.39 scw * FAULT_BUSTRNL2 - External abort on Translation -- Level 2
647 1.39 scw *
648 1.39 scw * If pcb_onfault is set, flag the fault and return to the handler.
649 1.39 scw * If the fault occurred in user mode, give the process a SIGBUS.
650 1.39 scw *
651 1.39 scw * Note: On XScale, FAULT_BUSERR_0, FAULT_BUSERR_1, and FAULT_BUSERR_2
652 1.39 scw * can be flagged as imprecise in the FSR. This causes a real headache
653 1.39 scw * since some of the machine state is lost. In this case, tf->tf_pc
654 1.39 scw * may not actually point to the offending instruction. In fact, if
655 1.39 scw * we've taken a double abort fault, it generally points somewhere near
656 1.39 scw * the top of "data_abort_entry" in exception.S.
657 1.39 scw *
658 1.39 scw * In all other cases, these data aborts are considered fatal.
659 1.39 scw */
660 1.39 scw static int
661 1.39 scw dab_buserr(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l,
662 1.39 scw ksiginfo_t *ksi)
663 1.39 scw {
664 1.73 rmind struct pcb *pcb = lwp_getpcb(l);
665 1.39 scw
666 1.39 scw #ifdef __XSCALE__
667 1.39 scw if ((fsr & FAULT_IMPRECISE) != 0 &&
668 1.39 scw (tf->tf_spsr & PSR_MODE) == PSR_ABT32_MODE) {
669 1.39 scw /*
670 1.39 scw * Oops, an imprecise, double abort fault. We've lost the
671 1.39 scw * r14_abt/spsr_abt values corresponding to the original
672 1.39 scw * abort, and the spsr saved in the trapframe indicates
673 1.39 scw * ABT mode.
674 1.39 scw */
675 1.39 scw tf->tf_spsr &= ~PSR_MODE;
676 1.39 scw
677 1.39 scw /*
678 1.39 scw * We use a simple heuristic to determine if the double abort
679 1.39 scw * happened as a result of a kernel or user mode access.
680 1.39 scw * If the current trapframe is at the top of the kernel stack,
681 1.39 scw * the fault _must_ have come from user mode.
682 1.39 scw */
683 1.87 matt if (tf != ((trapframe_t *)pcb->pcb_ksp) - 1) {
684 1.39 scw /*
685 1.39 scw * Kernel mode. We're either about to die a
686 1.39 scw * spectacular death, or pcb_onfault will come
687 1.39 scw * to our rescue. Either way, the current value
688 1.39 scw * of tf->tf_pc is irrelevant.
689 1.39 scw */
690 1.39 scw tf->tf_spsr |= PSR_SVC32_MODE;
691 1.39 scw if (pcb->pcb_onfault == NULL)
692 1.39 scw printf("\nKernel mode double abort!\n");
693 1.39 scw } else {
694 1.39 scw /*
695 1.39 scw * User mode. We've lost the program counter at the
696 1.39 scw * time of the fault (not that it was accurate anyway;
697 1.39 scw * it's not called an imprecise fault for nothing).
698 1.39 scw * About all we can do is copy r14_usr to tf_pc and
699 1.39 scw * hope for the best. The process is about to get a
700 1.39 scw * SIGBUS, so it's probably history anyway.
701 1.39 scw */
702 1.39 scw tf->tf_spsr |= PSR_USR32_MODE;
703 1.39 scw tf->tf_pc = tf->tf_usr_lr;
704 1.51 rearnsha #ifdef THUMB_CODE
705 1.51 rearnsha tf->tf_spsr &= ~PSR_T_bit;
706 1.51 rearnsha if (tf->tf_usr_lr & 1)
707 1.51 rearnsha tf->tf_spsr |= PSR_T_bit;
708 1.51 rearnsha #endif
709 1.39 scw }
710 1.39 scw }
711 1.39 scw
712 1.39 scw /* FAR is invalid for imprecise exceptions */
713 1.39 scw if ((fsr & FAULT_IMPRECISE) != 0)
714 1.39 scw far = 0;
715 1.39 scw #endif /* __XSCALE__ */
716 1.39 scw
717 1.39 scw if (pcb->pcb_onfault) {
718 1.39 scw KDASSERT(TRAP_USERMODE(tf) == 0);
719 1.39 scw tf->tf_r0 = EFAULT;
720 1.39 scw tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
721 1.39 scw return (0);
722 1.39 scw }
723 1.39 scw
724 1.48 wiz /* See if the CPU state needs to be fixed up */
725 1.39 scw (void) data_abort_fixup(tf, fsr, far, l);
726 1.39 scw
727 1.39 scw /*
728 1.39 scw * At this point, if the fault happened in kernel mode, we're toast
729 1.39 scw */
730 1.39 scw if (!TRAP_USERMODE(tf))
731 1.39 scw dab_fatal(tf, fsr, far, l, NULL);
732 1.39 scw
733 1.39 scw /* Deliver a bus error signal to the process */
734 1.39 scw KSI_INIT_TRAP(ksi);
735 1.39 scw ksi->ksi_signo = SIGBUS;
736 1.39 scw ksi->ksi_code = BUS_ADRERR;
737 1.86 skrll ksi->ksi_addr = (uint32_t *)(intptr_t)far;
738 1.39 scw ksi->ksi_trap = fsr;
739 1.39 scw
740 1.83 matt lwp_settrapframe(l, tf);
741 1.27 scw
742 1.39 scw return (1);
743 1.1 chris }
744 1.1 chris
745 1.56 perry static inline int
746 1.39 scw prefetch_abort_fixup(trapframe_t *tf)
747 1.39 scw {
748 1.39 scw #ifdef CPU_ABORT_FIXUP_REQUIRED
749 1.39 scw int error;
750 1.39 scw
751 1.48 wiz /* Call the CPU specific prefetch abort fixup routine */
752 1.39 scw error = cpu_prefetchabt_fixup(tf);
753 1.39 scw if (__predict_true(error != ABORT_FIXUP_FAILED))
754 1.39 scw return (error);
755 1.39 scw
756 1.39 scw /*
757 1.39 scw * Oops, couldn't fix up the instruction
758 1.39 scw */
759 1.79 christos printf("%s: fixup for %s mode prefetch abort failed.\n", __func__,
760 1.39 scw TRAP_USERMODE(tf) ? "user" : "kernel");
761 1.51 rearnsha #ifdef THUMB_CODE
762 1.51 rearnsha if (tf->tf_spsr & PSR_T_bit) {
763 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%04x, 0x%04x, insn = ",
764 1.86 skrll tf->tf_pc, *((uint16 *)(tf->tf_pc & ~1)),
765 1.86 skrll *((uint16 *)((tf->tf_pc + 2) & ~1)));
766 1.51 rearnsha }
767 1.51 rearnsha else
768 1.51 rearnsha #endif
769 1.51 rearnsha {
770 1.51 rearnsha printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc,
771 1.51 rearnsha *((u_int *)tf->tf_pc));
772 1.51 rearnsha }
773 1.39 scw disassemble(tf->tf_pc);
774 1.39 scw
775 1.39 scw /* Die now if this happened in kernel mode */
776 1.39 scw if (!TRAP_USERMODE(tf))
777 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
778 1.39 scw
779 1.39 scw return (error);
780 1.39 scw #else
781 1.39 scw return (ABORT_FIXUP_OK);
782 1.39 scw #endif /* CPU_ABORT_FIXUP_REQUIRED */
783 1.39 scw }
784 1.1 chris
785 1.1 chris /*
786 1.39 scw * void prefetch_abort_handler(trapframe_t *tf)
787 1.1 chris *
788 1.1 chris * Abort handler called when instruction execution occurs at
789 1.1 chris * a non existent or restricted (access permissions) memory page.
790 1.1 chris * If the address is invalid and we were in SVC mode then panic as
791 1.1 chris * the kernel should never prefetch abort.
792 1.1 chris * If the address is invalid and the page is mapped then the user process
793 1.1 chris * does no have read permission so send it a signal.
794 1.1 chris * Otherwise fault the page in and try again.
795 1.1 chris */
796 1.1 chris void
797 1.39 scw prefetch_abort_handler(trapframe_t *tf)
798 1.1 chris {
799 1.26 thorpej struct lwp *l;
800 1.91 christos struct pcb *pcb __diagused;
801 1.14 thorpej struct vm_map *map;
802 1.14 thorpej vaddr_t fault_pc, va;
803 1.39 scw ksiginfo_t ksi;
804 1.61 ad int error, user;
805 1.39 scw
806 1.97 matt UVMHIST_FUNC(__func__);
807 1.97 matt #ifdef UVMHIST
808 1.97 matt if (__predict_true(maphist.e)) {
809 1.97 matt UVMHIST_CALLED(maphist);
810 1.97 matt }
811 1.97 matt #endif
812 1.50 rearnsha
813 1.39 scw /* Update vmmeter statistics */
814 1.78 matt curcpu()->ci_data.cpu_ntrap++;
815 1.1 chris
816 1.61 ad l = curlwp;
817 1.73 rmind pcb = lwp_getpcb(l);
818 1.61 ad
819 1.61 ad if ((user = TRAP_USERMODE(tf)) != 0)
820 1.61 ad LWP_CACHE_CREDS(l, l->l_proc);
821 1.61 ad
822 1.1 chris /*
823 1.1 chris * Enable IRQ's (disabled by the abort) This always comes
824 1.1 chris * from user mode so we know interrupts were not disabled.
825 1.1 chris * But we check anyway.
826 1.1 chris */
827 1.72 matt KASSERT(!TRAP_USERMODE(tf) || (tf->tf_spsr & IF32_bits) == 0);
828 1.72 matt if (__predict_true((tf->tf_spsr & I32_bit) != IF32_bits))
829 1.72 matt restore_interrupts(tf->tf_spsr & IF32_bits);
830 1.1 chris
831 1.48 wiz /* See if the CPU state needs to be fixed up */
832 1.39 scw switch (prefetch_abort_fixup(tf)) {
833 1.39 scw case ABORT_FIXUP_RETURN:
834 1.72 matt KASSERT(!TRAP_USERMODE(tf) || (tf->tf_spsr & IF32_bits) == 0);
835 1.1 chris return;
836 1.39 scw case ABORT_FIXUP_FAILED:
837 1.39 scw /* Deliver a SIGILL to the process */
838 1.39 scw KSI_INIT_TRAP(&ksi);
839 1.39 scw ksi.ksi_signo = SIGILL;
840 1.39 scw ksi.ksi_code = ILL_ILLOPC;
841 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) tf->tf_pc;
842 1.83 matt lwp_settrapframe(l, tf);
843 1.39 scw goto do_trapsignal;
844 1.39 scw default:
845 1.39 scw break;
846 1.1 chris }
847 1.1 chris
848 1.39 scw /* Prefetch aborts cannot happen in kernel mode */
849 1.61 ad if (__predict_false(!user))
850 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
851 1.1 chris
852 1.4 thorpej /* Get fault address */
853 1.39 scw fault_pc = tf->tf_pc;
854 1.83 matt lwp_settrapframe(l, tf);
855 1.97 matt #ifdef UVMHIST
856 1.97 matt if (__predict_true(maphist.e)) {
857 1.97 matt UVMHIST_LOG(maphist, " (pc=0x%x, l=0x%x, tf=0x%x)",
858 1.97 matt fault_pc, l, tf, 0);
859 1.97 matt }
860 1.97 matt #endif
861 1.14 thorpej
862 1.1 chris /* Ok validate the address, can only execute in USER space */
863 1.39 scw if (__predict_false(fault_pc >= VM_MAXUSER_ADDRESS ||
864 1.39 scw (fault_pc < VM_MIN_ADDRESS && vector_page == ARM_VECTORS_LOW))) {
865 1.35 thorpej KSI_INIT_TRAP(&ksi);
866 1.34 matt ksi.ksi_signo = SIGSEGV;
867 1.34 matt ksi.ksi_code = SEGV_ACCERR;
868 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) fault_pc;
869 1.34 matt ksi.ksi_trap = fault_pc;
870 1.39 scw goto do_trapsignal;
871 1.39 scw }
872 1.34 matt
873 1.39 scw map = &l->l_proc->p_vmspace->vm_map;
874 1.39 scw va = trunc_page(fault_pc);
875 1.1 chris
876 1.27 scw /*
877 1.27 scw * See if the pmap can handle this fault on its own...
878 1.27 scw */
879 1.39 scw #ifdef DEBUG
880 1.39 scw last_fault_code = -1;
881 1.39 scw #endif
882 1.88 matt if (pmap_fault_fixup(map->pmap, va, VM_PROT_READ|VM_PROT_EXECUTE, 1)) {
883 1.97 matt #ifdef UVMHIST
884 1.97 matt if (__predict_true(maphist.e)) {
885 1.97 matt UVMHIST_LOG (maphist, " <- emulated", 0, 0, 0, 0);
886 1.97 matt }
887 1.97 matt #endif
888 1.39 scw goto out;
889 1.50 rearnsha }
890 1.27 scw
891 1.39 scw #ifdef DIAGNOSTIC
892 1.84 matt if (__predict_false(curcpu()->ci_intr_depth > 0)) {
893 1.39 scw printf("\nNon-emulated prefetch abort with intr_depth > 0\n");
894 1.39 scw dab_fatal(tf, 0, tf->tf_pc, NULL, NULL);
895 1.39 scw }
896 1.1 chris #endif
897 1.72 matt
898 1.76 chs KASSERT(pcb->pcb_onfault == NULL);
899 1.57 he error = uvm_fault(map, va, VM_PROT_READ);
900 1.53 joff
901 1.50 rearnsha if (__predict_true(error == 0)) {
902 1.97 matt #ifdef UVMHIST
903 1.97 matt if (__predict_true(maphist.e)) {
904 1.97 matt UVMHIST_LOG (maphist, " <- uvm", 0, 0, 0, 0);
905 1.97 matt }
906 1.97 matt #endif
907 1.39 scw goto out;
908 1.50 rearnsha }
909 1.43 scw KSI_INIT_TRAP(&ksi);
910 1.43 scw
911 1.97 matt #ifdef UVMHIST
912 1.97 matt if (__predict_true(maphist.e)) {
913 1.97 matt UVMHIST_LOG (maphist, " <- fatal (%d)", error, 0, 0, 0);
914 1.97 matt }
915 1.97 matt #endif
916 1.39 scw if (error == ENOMEM) {
917 1.39 scw printf("UVM: pid %d (%s), uid %d killed: "
918 1.39 scw "out of swap\n", l->l_proc->p_pid, l->l_proc->p_comm,
919 1.62 ad l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1);
920 1.43 scw ksi.ksi_signo = SIGKILL;
921 1.43 scw } else
922 1.43 scw ksi.ksi_signo = SIGSEGV;
923 1.1 chris
924 1.39 scw ksi.ksi_code = SEGV_MAPERR;
925 1.86 skrll ksi.ksi_addr = (uint32_t *)(intptr_t) fault_pc;
926 1.39 scw ksi.ksi_trap = fault_pc;
927 1.39 scw
928 1.39 scw do_trapsignal:
929 1.93 matt call_trapsignal(l, tf, &ksi);
930 1.39 scw
931 1.39 scw out:
932 1.72 matt KASSERT(!TRAP_USERMODE(tf) || (tf->tf_spsr & IF32_bits) == 0);
933 1.39 scw userret(l);
934 1.39 scw }
935 1.39 scw
936 1.39 scw /*
937 1.39 scw * Tentatively read an 8, 16, or 32-bit value from 'addr'.
938 1.39 scw * If the read succeeds, the value is written to 'rptr' and zero is returned.
939 1.39 scw * Else, return EFAULT.
940 1.39 scw */
941 1.39 scw int
942 1.39 scw badaddr_read(void *addr, size_t size, void *rptr)
943 1.39 scw {
944 1.39 scw extern int badaddr_read_1(const uint8_t *, uint8_t *);
945 1.39 scw extern int badaddr_read_2(const uint16_t *, uint16_t *);
946 1.39 scw extern int badaddr_read_4(const uint32_t *, uint32_t *);
947 1.39 scw union {
948 1.39 scw uint8_t v1;
949 1.39 scw uint16_t v2;
950 1.39 scw uint32_t v4;
951 1.39 scw } u;
952 1.47 scw int rv, s;
953 1.39 scw
954 1.39 scw cpu_drain_writebuf();
955 1.39 scw
956 1.47 scw s = splhigh();
957 1.47 scw
958 1.39 scw /* Read from the test address. */
959 1.39 scw switch (size) {
960 1.39 scw case sizeof(uint8_t):
961 1.39 scw rv = badaddr_read_1(addr, &u.v1);
962 1.39 scw if (rv == 0 && rptr)
963 1.39 scw *(uint8_t *) rptr = u.v1;
964 1.39 scw break;
965 1.39 scw
966 1.39 scw case sizeof(uint16_t):
967 1.39 scw rv = badaddr_read_2(addr, &u.v2);
968 1.39 scw if (rv == 0 && rptr)
969 1.39 scw *(uint16_t *) rptr = u.v2;
970 1.39 scw break;
971 1.39 scw
972 1.39 scw case sizeof(uint32_t):
973 1.39 scw rv = badaddr_read_4(addr, &u.v4);
974 1.39 scw if (rv == 0 && rptr)
975 1.39 scw *(uint32_t *) rptr = u.v4;
976 1.39 scw break;
977 1.39 scw
978 1.39 scw default:
979 1.82 matt panic("%s: invalid size (%zu)", __func__, size);
980 1.34 matt }
981 1.39 scw
982 1.47 scw splx(s);
983 1.47 scw
984 1.39 scw /* Return EFAULT if the address was invalid, else zero */
985 1.39 scw return (rv);
986 1.1 chris }
987