pmap.c revision 1.154
1 /* $NetBSD: pmap.c,v 1.154 2005/07/04 00:42:37 bsh Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 3. All advertising materials mentioning features or use of this software 82 * must display the following acknowledgement: 83 * This product includes software developed by the NetBSD 84 * Foundation, Inc. and its contributors. 85 * 4. Neither the name of The NetBSD Foundation nor the names of its 86 * contributors may be used to endorse or promote products derived 87 * from this software without specific prior written permission. 88 * 89 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 90 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 91 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 92 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 93 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 94 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 95 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 96 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 97 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 98 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 99 * POSSIBILITY OF SUCH DAMAGE. 100 */ 101 102 /* 103 * Copyright (c) 1994-1998 Mark Brinicombe. 104 * Copyright (c) 1994 Brini. 105 * All rights reserved. 106 * 107 * This code is derived from software written for Brini by Mark Brinicombe 108 * 109 * Redistribution and use in source and binary forms, with or without 110 * modification, are permitted provided that the following conditions 111 * are met: 112 * 1. Redistributions of source code must retain the above copyright 113 * notice, this list of conditions and the following disclaimer. 114 * 2. Redistributions in binary form must reproduce the above copyright 115 * notice, this list of conditions and the following disclaimer in the 116 * documentation and/or other materials provided with the distribution. 117 * 3. All advertising materials mentioning features or use of this software 118 * must display the following acknowledgement: 119 * This product includes software developed by Mark Brinicombe. 120 * 4. The name of the author may not be used to endorse or promote products 121 * derived from this software without specific prior written permission. 122 * 123 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 124 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 125 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 126 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 127 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 128 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 129 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 130 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 131 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 132 * 133 * RiscBSD kernel project 134 * 135 * pmap.c 136 * 137 * Machine dependant vm stuff 138 * 139 * Created : 20/09/94 140 */ 141 142 /* 143 * Performance improvements, UVM changes, overhauls and part-rewrites 144 * were contributed by Neil A. Carson <neil (at) causality.com>. 145 */ 146 147 /* 148 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 149 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 150 * Systems, Inc. 151 * 152 * There are still a few things outstanding at this time: 153 * 154 * - There are some unresolved issues for MP systems: 155 * 156 * o The L1 metadata needs a lock, or more specifically, some places 157 * need to acquire an exclusive lock when modifying L1 translation 158 * table entries. 159 * 160 * o When one cpu modifies an L1 entry, and that L1 table is also 161 * being used by another cpu, then the latter will need to be told 162 * that a tlb invalidation may be necessary. (But only if the old 163 * domain number in the L1 entry being over-written is currently 164 * the active domain on that cpu). I guess there are lots more tlb 165 * shootdown issues too... 166 * 167 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 168 * MP systems will lose big-time because of the MMU domain hack. 169 * The only way this can be solved (apart from moving the vector 170 * page to 0xffff0000) is to reserve the first 1MB of user address 171 * space for kernel use only. This would require re-linking all 172 * applications so that the text section starts above this 1MB 173 * boundary. 174 * 175 * o Tracking which VM space is resident in the cache/tlb has not yet 176 * been implemented for MP systems. 177 * 178 * o Finally, there is a pathological condition where two cpus running 179 * two separate processes (not lwps) which happen to share an L1 180 * can get into a fight over one or more L1 entries. This will result 181 * in a significant slow-down if both processes are in tight loops. 182 */ 183 184 /* 185 * Special compilation symbols 186 * PMAP_DEBUG - Build in pmap_debug_level code 187 */ 188 189 /* Include header files */ 190 191 #include "opt_cpuoptions.h" 192 #include "opt_pmap_debug.h" 193 #include "opt_ddb.h" 194 #include "opt_lockdebug.h" 195 #include "opt_multiprocessor.h" 196 197 #include <sys/types.h> 198 #include <sys/param.h> 199 #include <sys/kernel.h> 200 #include <sys/systm.h> 201 #include <sys/proc.h> 202 #include <sys/malloc.h> 203 #include <sys/user.h> 204 #include <sys/pool.h> 205 #include <sys/cdefs.h> 206 207 #include <uvm/uvm.h> 208 209 #include <machine/bus.h> 210 #include <machine/pmap.h> 211 #include <machine/pcb.h> 212 #include <machine/param.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.154 2005/07/04 00:42:37 bsh Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 struct pmap kernel_pmap_store; 258 259 /* 260 * Which pmap is currently 'live' in the cache 261 * 262 * XXXSCW: Fix for SMP ... 263 */ 264 union pmap_cache_state *pmap_cache_state; 265 266 /* 267 * Pool and cache that pmap structures are allocated from. 268 * We use a cache to avoid clearing the pm_l2[] array (1KB) 269 * in pmap_create(). 270 */ 271 static struct pool pmap_pmap_pool; 272 static struct pool_cache pmap_pmap_cache; 273 static LIST_HEAD(, pmap) pmap_pmaps; 274 275 /* 276 * Pool of PV structures 277 */ 278 static struct pool pmap_pv_pool; 279 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 280 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 281 static struct pool_allocator pmap_bootstrap_pv_allocator = { 282 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 283 }; 284 285 /* 286 * Pool and cache of l2_dtable structures. 287 * We use a cache to avoid clearing the structures when they're 288 * allocated. (196 bytes) 289 */ 290 static struct pool pmap_l2dtable_pool; 291 static struct pool_cache pmap_l2dtable_cache; 292 static vaddr_t pmap_kernel_l2dtable_kva; 293 294 /* 295 * Pool and cache of L2 page descriptors. 296 * We use a cache to avoid clearing the descriptor table 297 * when they're allocated. (1KB) 298 */ 299 static struct pool pmap_l2ptp_pool; 300 static struct pool_cache pmap_l2ptp_cache; 301 static vaddr_t pmap_kernel_l2ptp_kva; 302 static paddr_t pmap_kernel_l2ptp_phys; 303 304 /* 305 * pmap copy/zero page, and mem(5) hook point 306 */ 307 static pt_entry_t *csrc_pte, *cdst_pte; 308 static vaddr_t csrcp, cdstp; 309 char *memhook; 310 extern caddr_t msgbufaddr; 311 312 /* 313 * Flag to indicate if pmap_init() has done its thing 314 */ 315 boolean_t pmap_initialized; 316 317 /* 318 * Misc. locking data structures 319 */ 320 321 #if defined(MULTIPROCESSOR) || defined(LOCKDEBUG) 322 static struct lock pmap_main_lock; 323 324 #define PMAP_MAP_TO_HEAD_LOCK() \ 325 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 326 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 327 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 328 #define PMAP_HEAD_TO_MAP_LOCK() \ 329 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 330 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 331 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 332 #else 333 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 334 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 335 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 336 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 337 #endif 338 339 #define pmap_acquire_pmap_lock(pm) \ 340 do { \ 341 if ((pm) != pmap_kernel()) \ 342 simple_lock(&(pm)->pm_lock); \ 343 } while (/*CONSTCOND*/0) 344 345 #define pmap_release_pmap_lock(pm) \ 346 do { \ 347 if ((pm) != pmap_kernel()) \ 348 simple_unlock(&(pm)->pm_lock); \ 349 } while (/*CONSTCOND*/0) 350 351 352 /* 353 * Metadata for L1 translation tables. 354 */ 355 struct l1_ttable { 356 /* Entry on the L1 Table list */ 357 SLIST_ENTRY(l1_ttable) l1_link; 358 359 /* Entry on the L1 Least Recently Used list */ 360 TAILQ_ENTRY(l1_ttable) l1_lru; 361 362 /* Track how many domains are allocated from this L1 */ 363 volatile u_int l1_domain_use_count; 364 365 /* 366 * A free-list of domain numbers for this L1. 367 * We avoid using ffs() and a bitmap to track domains since ffs() 368 * is slow on ARM. 369 */ 370 u_int8_t l1_domain_first; 371 u_int8_t l1_domain_free[PMAP_DOMAINS]; 372 373 /* Physical address of this L1 page table */ 374 paddr_t l1_physaddr; 375 376 /* KVA of this L1 page table */ 377 pd_entry_t *l1_kva; 378 }; 379 380 /* 381 * Convert a virtual address into its L1 table index. That is, the 382 * index used to locate the L2 descriptor table pointer in an L1 table. 383 * This is basically used to index l1->l1_kva[]. 384 * 385 * Each L2 descriptor table represents 1MB of VA space. 386 */ 387 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 388 389 /* 390 * L1 Page Tables are tracked using a Least Recently Used list. 391 * - New L1s are allocated from the HEAD. 392 * - Freed L1s are added to the TAIl. 393 * - Recently accessed L1s (where an 'access' is some change to one of 394 * the userland pmaps which owns this L1) are moved to the TAIL. 395 */ 396 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 397 static struct simplelock l1_lru_lock; 398 399 /* 400 * A list of all L1 tables 401 */ 402 static SLIST_HEAD(, l1_ttable) l1_list; 403 404 /* 405 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 406 * 407 * This is normally 16MB worth L2 page descriptors for any given pmap. 408 * Reference counts are maintained for L2 descriptors so they can be 409 * freed when empty. 410 */ 411 struct l2_dtable { 412 /* The number of L2 page descriptors allocated to this l2_dtable */ 413 u_int l2_occupancy; 414 415 /* List of L2 page descriptors */ 416 struct l2_bucket { 417 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 418 paddr_t l2b_phys; /* Physical address of same */ 419 u_short l2b_l1idx; /* This L2 table's L1 index */ 420 u_short l2b_occupancy; /* How many active descriptors */ 421 } l2_bucket[L2_BUCKET_SIZE]; 422 }; 423 424 /* 425 * Given an L1 table index, calculate the corresponding l2_dtable index 426 * and bucket index within the l2_dtable. 427 */ 428 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 429 (L2_SIZE - 1)) 430 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 431 432 /* 433 * Given a virtual address, this macro returns the 434 * virtual address required to drop into the next L2 bucket. 435 */ 436 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 437 438 /* 439 * L2 allocation. 440 */ 441 #define pmap_alloc_l2_dtable() \ 442 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 443 #define pmap_free_l2_dtable(l2) \ 444 pool_cache_put(&pmap_l2dtable_cache, (l2)) 445 #define pmap_alloc_l2_ptp(pap) \ 446 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 447 PR_NOWAIT, (pap))) 448 449 /* 450 * We try to map the page tables write-through, if possible. However, not 451 * all CPUs have a write-through cache mode, so on those we have to sync 452 * the cache when we frob page tables. 453 * 454 * We try to evaluate this at compile time, if possible. However, it's 455 * not always possible to do that, hence this run-time var. 456 */ 457 int pmap_needs_pte_sync; 458 459 /* 460 * Real definition of pv_entry. 461 */ 462 struct pv_entry { 463 struct pv_entry *pv_next; /* next pv_entry */ 464 pmap_t pv_pmap; /* pmap where mapping lies */ 465 vaddr_t pv_va; /* virtual address for mapping */ 466 u_int pv_flags; /* flags */ 467 }; 468 469 /* 470 * Macro to determine if a mapping might be resident in the 471 * instruction cache and/or TLB 472 */ 473 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 474 475 /* 476 * Macro to determine if a mapping might be resident in the 477 * data cache and/or TLB 478 */ 479 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 480 481 /* 482 * Local prototypes 483 */ 484 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 485 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 486 pt_entry_t **); 487 static boolean_t pmap_is_current(pmap_t); 488 static boolean_t pmap_is_cached(pmap_t); 489 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 490 pmap_t, vaddr_t, u_int); 491 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 492 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t); 493 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 494 u_int, u_int); 495 496 static void pmap_pinit(pmap_t); 497 static int pmap_pmap_ctor(void *, void *, int); 498 499 static void pmap_alloc_l1(pmap_t); 500 static void pmap_free_l1(pmap_t); 501 static void pmap_use_l1(pmap_t); 502 503 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 504 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 505 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 506 static int pmap_l2ptp_ctor(void *, void *, int); 507 static int pmap_l2dtable_ctor(void *, void *, int); 508 509 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 510 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 511 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 512 513 static void pmap_clearbit(struct vm_page *, u_int); 514 static int pmap_clean_page(struct pv_entry *, boolean_t); 515 static void pmap_page_remove(struct vm_page *); 516 517 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 518 static vaddr_t kernel_pt_lookup(paddr_t); 519 520 521 /* 522 * External function prototypes 523 */ 524 extern void bzero_page(vaddr_t); 525 extern void bcopy_page(vaddr_t, vaddr_t); 526 527 /* 528 * Misc variables 529 */ 530 vaddr_t virtual_avail; 531 vaddr_t virtual_end; 532 vaddr_t pmap_curmaxkvaddr; 533 534 vaddr_t avail_start; 535 vaddr_t avail_end; 536 537 extern pv_addr_t systempage; 538 539 /* Function to set the debug level of the pmap code */ 540 541 #ifdef PMAP_DEBUG 542 void 543 pmap_debug(int level) 544 { 545 pmap_debug_level = level; 546 printf("pmap_debug: level=%d\n", pmap_debug_level); 547 } 548 #endif /* PMAP_DEBUG */ 549 550 /* 551 * A bunch of routines to conditionally flush the caches/TLB depending 552 * on whether the specified pmap actually needs to be flushed at any 553 * given time. 554 */ 555 static __inline void 556 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 557 { 558 559 if (pm->pm_cstate.cs_tlb_id) 560 cpu_tlb_flushID_SE(va); 561 } 562 563 static __inline void 564 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 565 { 566 567 if (pm->pm_cstate.cs_tlb_d) 568 cpu_tlb_flushD_SE(va); 569 } 570 571 static __inline void 572 pmap_tlb_flushID(pmap_t pm) 573 { 574 575 if (pm->pm_cstate.cs_tlb_id) { 576 cpu_tlb_flushID(); 577 pm->pm_cstate.cs_tlb = 0; 578 } 579 } 580 581 static __inline void 582 pmap_tlb_flushD(pmap_t pm) 583 { 584 585 if (pm->pm_cstate.cs_tlb_d) { 586 cpu_tlb_flushD(); 587 pm->pm_cstate.cs_tlb_d = 0; 588 } 589 } 590 591 static __inline void 592 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 593 { 594 595 if (pm->pm_cstate.cs_cache_id) 596 cpu_idcache_wbinv_range(va, len); 597 } 598 599 static __inline void 600 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 601 boolean_t do_inv, boolean_t rd_only) 602 { 603 604 if (pm->pm_cstate.cs_cache_d) { 605 if (do_inv) { 606 if (rd_only) 607 cpu_dcache_inv_range(va, len); 608 else 609 cpu_dcache_wbinv_range(va, len); 610 } else 611 if (!rd_only) 612 cpu_dcache_wb_range(va, len); 613 } 614 } 615 616 static __inline void 617 pmap_idcache_wbinv_all(pmap_t pm) 618 { 619 620 if (pm->pm_cstate.cs_cache_id) { 621 cpu_idcache_wbinv_all(); 622 pm->pm_cstate.cs_cache = 0; 623 } 624 } 625 626 static __inline void 627 pmap_dcache_wbinv_all(pmap_t pm) 628 { 629 630 if (pm->pm_cstate.cs_cache_d) { 631 cpu_dcache_wbinv_all(); 632 pm->pm_cstate.cs_cache_d = 0; 633 } 634 } 635 636 static __inline boolean_t 637 pmap_is_current(pmap_t pm) 638 { 639 640 if (pm == pmap_kernel() || 641 (curproc && curproc->p_vmspace->vm_map.pmap == pm)) 642 return (TRUE); 643 644 return (FALSE); 645 } 646 647 static __inline boolean_t 648 pmap_is_cached(pmap_t pm) 649 { 650 651 if (pm == pmap_kernel() || pmap_cache_state == NULL || 652 pmap_cache_state == &pm->pm_cstate) 653 return (TRUE); 654 655 return (FALSE); 656 } 657 658 /* 659 * PTE_SYNC_CURRENT: 660 * 661 * Make sure the pte is written out to RAM. 662 * We need to do this for one of two cases: 663 * - We're dealing with the kernel pmap 664 * - There is no pmap active in the cache/tlb. 665 * - The specified pmap is 'active' in the cache/tlb. 666 */ 667 #ifdef PMAP_INCLUDE_PTE_SYNC 668 #define PTE_SYNC_CURRENT(pm, ptep) \ 669 do { \ 670 if (PMAP_NEEDS_PTE_SYNC && \ 671 pmap_is_cached(pm)) \ 672 PTE_SYNC(ptep); \ 673 } while (/*CONSTCOND*/0) 674 #else 675 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 676 #endif 677 678 /* 679 * main pv_entry manipulation functions: 680 * pmap_enter_pv: enter a mapping onto a vm_page list 681 * pmap_remove_pv: remove a mappiing from a vm_page list 682 * 683 * NOTE: pmap_enter_pv expects to lock the pvh itself 684 * pmap_remove_pv expects te caller to lock the pvh before calling 685 */ 686 687 /* 688 * pmap_enter_pv: enter a mapping onto a vm_page lst 689 * 690 * => caller should hold the proper lock on pmap_main_lock 691 * => caller should have pmap locked 692 * => we will gain the lock on the vm_page and allocate the new pv_entry 693 * => caller should adjust ptp's wire_count before calling 694 * => caller should not adjust pmap's wire_count 695 */ 696 static void 697 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 698 vaddr_t va, u_int flags) 699 { 700 701 NPDEBUG(PDB_PVDUMP, 702 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 703 704 pve->pv_pmap = pm; 705 pve->pv_va = va; 706 pve->pv_flags = flags; 707 708 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 709 pve->pv_next = pg->mdpage.pvh_list; /* add to ... */ 710 pg->mdpage.pvh_list = pve; /* ... locked list */ 711 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 712 if (pm == pmap_kernel()) { 713 if (flags & PVF_WRITE) 714 pg->mdpage.krw_mappings++; 715 else 716 pg->mdpage.kro_mappings++; 717 } else 718 if (flags & PVF_WRITE) 719 pg->mdpage.urw_mappings++; 720 else 721 pg->mdpage.uro_mappings++; 722 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 723 724 if (pve->pv_flags & PVF_WIRED) 725 ++pm->pm_stats.wired_count; 726 } 727 728 /* 729 * 730 * pmap_find_pv: Find a pv entry 731 * 732 * => caller should hold lock on vm_page 733 */ 734 static __inline struct pv_entry * 735 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 736 { 737 struct pv_entry *pv; 738 739 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 740 if (pm == pv->pv_pmap && va == pv->pv_va) 741 break; 742 } 743 744 return (pv); 745 } 746 747 /* 748 * pmap_remove_pv: try to remove a mapping from a pv_list 749 * 750 * => caller should hold proper lock on pmap_main_lock 751 * => pmap should be locked 752 * => caller should hold lock on vm_page [so that attrs can be adjusted] 753 * => caller should adjust ptp's wire_count and free PTP if needed 754 * => caller should NOT adjust pmap's wire_count 755 * => we return the removed pve 756 */ 757 static struct pv_entry * 758 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 759 { 760 struct pv_entry *pve, **prevptr; 761 762 NPDEBUG(PDB_PVDUMP, 763 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 764 765 prevptr = &pg->mdpage.pvh_list; /* previous pv_entry pointer */ 766 pve = *prevptr; 767 768 while (pve) { 769 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 770 NPDEBUG(PDB_PVDUMP, 771 printf("pmap_remove_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, pve->pv_flags)); 772 *prevptr = pve->pv_next; /* remove it! */ 773 if (pve->pv_flags & PVF_WIRED) 774 --pm->pm_stats.wired_count; 775 if (pm == pmap_kernel()) { 776 if (pve->pv_flags & PVF_WRITE) 777 pg->mdpage.krw_mappings--; 778 else 779 pg->mdpage.kro_mappings--; 780 } else 781 if (pve->pv_flags & PVF_WRITE) 782 pg->mdpage.urw_mappings--; 783 else 784 pg->mdpage.uro_mappings--; 785 break; 786 } 787 prevptr = &pve->pv_next; /* previous pointer */ 788 pve = pve->pv_next; /* advance */ 789 } 790 791 return(pve); /* return removed pve */ 792 } 793 794 /* 795 * 796 * pmap_modify_pv: Update pv flags 797 * 798 * => caller should hold lock on vm_page [so that attrs can be adjusted] 799 * => caller should NOT adjust pmap's wire_count 800 * => caller must call pmap_vac_me_harder() if writable status of a page 801 * may have changed. 802 * => we return the old flags 803 * 804 * Modify a physical-virtual mapping in the pv table 805 */ 806 static u_int 807 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 808 u_int clr_mask, u_int set_mask) 809 { 810 struct pv_entry *npv; 811 u_int flags, oflags; 812 813 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 814 return (0); 815 816 NPDEBUG(PDB_PVDUMP, 817 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 818 819 /* 820 * There is at least one VA mapping this page. 821 */ 822 823 if (clr_mask & (PVF_REF | PVF_MOD)) 824 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 825 826 oflags = npv->pv_flags; 827 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 828 829 if ((flags ^ oflags) & PVF_WIRED) { 830 if (flags & PVF_WIRED) 831 ++pm->pm_stats.wired_count; 832 else 833 --pm->pm_stats.wired_count; 834 } 835 836 if ((flags ^ oflags) & PVF_WRITE) { 837 if (pm == pmap_kernel()) { 838 if (flags & PVF_WRITE) { 839 pg->mdpage.krw_mappings++; 840 pg->mdpage.kro_mappings--; 841 } else { 842 pg->mdpage.kro_mappings++; 843 pg->mdpage.krw_mappings--; 844 } 845 } else 846 if (flags & PVF_WRITE) { 847 pg->mdpage.urw_mappings++; 848 pg->mdpage.uro_mappings--; 849 } else { 850 pg->mdpage.uro_mappings++; 851 pg->mdpage.urw_mappings--; 852 } 853 } 854 855 return (oflags); 856 } 857 858 static void 859 pmap_pinit(pmap_t pm) 860 { 861 862 if (vector_page < KERNEL_BASE) { 863 /* 864 * Map the vector page. 865 */ 866 pmap_enter(pm, vector_page, systempage.pv_pa, 867 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 868 pmap_update(pm); 869 } 870 } 871 872 /* 873 * Allocate an L1 translation table for the specified pmap. 874 * This is called at pmap creation time. 875 */ 876 static void 877 pmap_alloc_l1(pmap_t pm) 878 { 879 struct l1_ttable *l1; 880 u_int8_t domain; 881 882 /* 883 * Remove the L1 at the head of the LRU list 884 */ 885 simple_lock(&l1_lru_lock); 886 l1 = TAILQ_FIRST(&l1_lru_list); 887 KDASSERT(l1 != NULL); 888 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 889 890 /* 891 * Pick the first available domain number, and update 892 * the link to the next number. 893 */ 894 domain = l1->l1_domain_first; 895 l1->l1_domain_first = l1->l1_domain_free[domain]; 896 897 /* 898 * If there are still free domain numbers in this L1, 899 * put it back on the TAIL of the LRU list. 900 */ 901 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 902 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 903 904 simple_unlock(&l1_lru_lock); 905 906 /* 907 * Fix up the relevant bits in the pmap structure 908 */ 909 pm->pm_l1 = l1; 910 pm->pm_domain = domain; 911 } 912 913 /* 914 * Free an L1 translation table. 915 * This is called at pmap destruction time. 916 */ 917 static void 918 pmap_free_l1(pmap_t pm) 919 { 920 struct l1_ttable *l1 = pm->pm_l1; 921 922 simple_lock(&l1_lru_lock); 923 924 /* 925 * If this L1 is currently on the LRU list, remove it. 926 */ 927 if (l1->l1_domain_use_count < PMAP_DOMAINS) 928 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 929 930 /* 931 * Free up the domain number which was allocated to the pmap 932 */ 933 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 934 l1->l1_domain_first = pm->pm_domain; 935 l1->l1_domain_use_count--; 936 937 /* 938 * The L1 now must have at least 1 free domain, so add 939 * it back to the LRU list. If the use count is zero, 940 * put it at the head of the list, otherwise it goes 941 * to the tail. 942 */ 943 if (l1->l1_domain_use_count == 0) 944 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 945 else 946 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 947 948 simple_unlock(&l1_lru_lock); 949 } 950 951 static __inline void 952 pmap_use_l1(pmap_t pm) 953 { 954 struct l1_ttable *l1; 955 956 /* 957 * Do nothing if we're in interrupt context. 958 * Access to an L1 by the kernel pmap must not affect 959 * the LRU list. 960 */ 961 if (current_intr_depth || pm == pmap_kernel()) 962 return; 963 964 l1 = pm->pm_l1; 965 966 /* 967 * If the L1 is not currently on the LRU list, just return 968 */ 969 if (l1->l1_domain_use_count == PMAP_DOMAINS) 970 return; 971 972 simple_lock(&l1_lru_lock); 973 974 /* 975 * Check the use count again, now that we've acquired the lock 976 */ 977 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 978 simple_unlock(&l1_lru_lock); 979 return; 980 } 981 982 /* 983 * Move the L1 to the back of the LRU list 984 */ 985 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 986 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 987 988 simple_unlock(&l1_lru_lock); 989 } 990 991 /* 992 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 993 * 994 * Free an L2 descriptor table. 995 */ 996 static __inline void 997 #ifndef PMAP_INCLUDE_PTE_SYNC 998 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 999 #else 1000 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2, paddr_t pa) 1001 #endif 1002 { 1003 #ifdef PMAP_INCLUDE_PTE_SYNC 1004 /* 1005 * Note: With a write-back cache, we may need to sync this 1006 * L2 table before re-using it. 1007 * This is because it may have belonged to a non-current 1008 * pmap, in which case the cache syncs would have been 1009 * skipped when the pages were being unmapped. If the 1010 * L2 table were then to be immediately re-allocated to 1011 * the *current* pmap, it may well contain stale mappings 1012 * which have not yet been cleared by a cache write-back 1013 * and so would still be visible to the mmu. 1014 */ 1015 if (need_sync) 1016 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1017 #endif 1018 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1019 } 1020 1021 /* 1022 * Returns a pointer to the L2 bucket associated with the specified pmap 1023 * and VA, or NULL if no L2 bucket exists for the address. 1024 */ 1025 static __inline struct l2_bucket * 1026 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1027 { 1028 struct l2_dtable *l2; 1029 struct l2_bucket *l2b; 1030 u_short l1idx; 1031 1032 l1idx = L1_IDX(va); 1033 1034 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1035 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1036 return (NULL); 1037 1038 return (l2b); 1039 } 1040 1041 /* 1042 * Returns a pointer to the L2 bucket associated with the specified pmap 1043 * and VA. 1044 * 1045 * If no L2 bucket exists, perform the necessary allocations to put an L2 1046 * bucket/page table in place. 1047 * 1048 * Note that if a new L2 bucket/page was allocated, the caller *must* 1049 * increment the bucket occupancy counter appropriately *before* 1050 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1051 * the bucket/page in the meantime. 1052 */ 1053 static struct l2_bucket * 1054 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1055 { 1056 struct l2_dtable *l2; 1057 struct l2_bucket *l2b; 1058 u_short l1idx; 1059 1060 l1idx = L1_IDX(va); 1061 1062 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1063 /* 1064 * No mapping at this address, as there is 1065 * no entry in the L1 table. 1066 * Need to allocate a new l2_dtable. 1067 */ 1068 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1069 return (NULL); 1070 1071 /* 1072 * Link it into the parent pmap 1073 */ 1074 pm->pm_l2[L2_IDX(l1idx)] = l2; 1075 } 1076 1077 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1078 1079 /* 1080 * Fetch pointer to the L2 page table associated with the address. 1081 */ 1082 if (l2b->l2b_kva == NULL) { 1083 pt_entry_t *ptep; 1084 1085 /* 1086 * No L2 page table has been allocated. Chances are, this 1087 * is because we just allocated the l2_dtable, above. 1088 */ 1089 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1090 /* 1091 * Oops, no more L2 page tables available at this 1092 * time. We may need to deallocate the l2_dtable 1093 * if we allocated a new one above. 1094 */ 1095 if (l2->l2_occupancy == 0) { 1096 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1097 pmap_free_l2_dtable(l2); 1098 } 1099 return (NULL); 1100 } 1101 1102 l2->l2_occupancy++; 1103 l2b->l2b_kva = ptep; 1104 l2b->l2b_l1idx = l1idx; 1105 } 1106 1107 return (l2b); 1108 } 1109 1110 /* 1111 * One or more mappings in the specified L2 descriptor table have just been 1112 * invalidated. 1113 * 1114 * Garbage collect the metadata and descriptor table itself if necessary. 1115 * 1116 * The pmap lock must be acquired when this is called (not necessary 1117 * for the kernel pmap). 1118 */ 1119 static void 1120 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1121 { 1122 struct l2_dtable *l2; 1123 pd_entry_t *pl1pd, l1pd; 1124 pt_entry_t *ptep; 1125 u_short l1idx; 1126 1127 KDASSERT(count <= l2b->l2b_occupancy); 1128 1129 /* 1130 * Update the bucket's reference count according to how many 1131 * PTEs the caller has just invalidated. 1132 */ 1133 l2b->l2b_occupancy -= count; 1134 1135 /* 1136 * Note: 1137 * 1138 * Level 2 page tables allocated to the kernel pmap are never freed 1139 * as that would require checking all Level 1 page tables and 1140 * removing any references to the Level 2 page table. See also the 1141 * comment elsewhere about never freeing bootstrap L2 descriptors. 1142 * 1143 * We make do with just invalidating the mapping in the L2 table. 1144 * 1145 * This isn't really a big deal in practice and, in fact, leads 1146 * to a performance win over time as we don't need to continually 1147 * alloc/free. 1148 */ 1149 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1150 return; 1151 1152 /* 1153 * There are no more valid mappings in this level 2 page table. 1154 * Go ahead and NULL-out the pointer in the bucket, then 1155 * free the page table. 1156 */ 1157 l1idx = l2b->l2b_l1idx; 1158 ptep = l2b->l2b_kva; 1159 l2b->l2b_kva = NULL; 1160 1161 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1162 1163 /* 1164 * If the L1 slot matches the pmap's domain 1165 * number, then invalidate it. 1166 */ 1167 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1168 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1169 *pl1pd = 0; 1170 PTE_SYNC(pl1pd); 1171 } 1172 1173 /* 1174 * Release the L2 descriptor table back to the pool cache. 1175 */ 1176 #ifndef PMAP_INCLUDE_PTE_SYNC 1177 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1178 #else 1179 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1180 #endif 1181 1182 /* 1183 * Update the reference count in the associated l2_dtable 1184 */ 1185 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1186 if (--l2->l2_occupancy > 0) 1187 return; 1188 1189 /* 1190 * There are no more valid mappings in any of the Level 1 1191 * slots managed by this l2_dtable. Go ahead and NULL-out 1192 * the pointer in the parent pmap and free the l2_dtable. 1193 */ 1194 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1195 pmap_free_l2_dtable(l2); 1196 } 1197 1198 /* 1199 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1200 * structures. 1201 */ 1202 static int 1203 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1204 { 1205 #ifndef PMAP_INCLUDE_PTE_SYNC 1206 struct l2_bucket *l2b; 1207 pt_entry_t *ptep, pte; 1208 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1209 1210 /* 1211 * The mappings for these page tables were initially made using 1212 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1213 * mode will not be right for page table mappings. To avoid 1214 * polluting the pmap_kenter_pa() code with a special case for 1215 * page tables, we simply fix up the cache-mode here if it's not 1216 * correct. 1217 */ 1218 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1219 KDASSERT(l2b != NULL); 1220 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1221 pte = *ptep; 1222 1223 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1224 /* 1225 * Page tables must have the cache-mode set to Write-Thru. 1226 */ 1227 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1228 PTE_SYNC(ptep); 1229 cpu_tlb_flushD_SE(va); 1230 cpu_cpwait(); 1231 } 1232 #endif 1233 1234 memset(v, 0, L2_TABLE_SIZE_REAL); 1235 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1236 return (0); 1237 } 1238 1239 static int 1240 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1241 { 1242 1243 memset(v, 0, sizeof(struct l2_dtable)); 1244 return (0); 1245 } 1246 1247 static int 1248 pmap_pmap_ctor(void *arg, void *v, int flags) 1249 { 1250 1251 memset(v, 0, sizeof(struct pmap)); 1252 return (0); 1253 } 1254 1255 /* 1256 * Since we have a virtually indexed cache, we may need to inhibit caching if 1257 * there is more than one mapping and at least one of them is writable. 1258 * Since we purge the cache on every context switch, we only need to check for 1259 * other mappings within the same pmap, or kernel_pmap. 1260 * This function is also called when a page is unmapped, to possibly reenable 1261 * caching on any remaining mappings. 1262 * 1263 * The code implements the following logic, where: 1264 * 1265 * KW = # of kernel read/write pages 1266 * KR = # of kernel read only pages 1267 * UW = # of user read/write pages 1268 * UR = # of user read only pages 1269 * 1270 * KC = kernel mapping is cacheable 1271 * UC = user mapping is cacheable 1272 * 1273 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1274 * +--------------------------------------------- 1275 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1276 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1277 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1278 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1279 */ 1280 1281 static const int pmap_vac_flags[4][4] = { 1282 {-1, 0, 0, PVF_KNC}, 1283 {0, 0, PVF_NC, PVF_NC}, 1284 {0, PVF_NC, PVF_NC, PVF_NC}, 1285 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1286 }; 1287 1288 static __inline int 1289 pmap_get_vac_flags(const struct vm_page *pg) 1290 { 1291 int kidx, uidx; 1292 1293 kidx = 0; 1294 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1295 kidx |= 1; 1296 if (pg->mdpage.krw_mappings) 1297 kidx |= 2; 1298 1299 uidx = 0; 1300 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1301 uidx |= 1; 1302 if (pg->mdpage.urw_mappings) 1303 uidx |= 2; 1304 1305 return (pmap_vac_flags[uidx][kidx]); 1306 } 1307 1308 static __inline void 1309 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1310 { 1311 int nattr; 1312 1313 nattr = pmap_get_vac_flags(pg); 1314 1315 if (nattr < 0) { 1316 pg->mdpage.pvh_attrs &= ~PVF_NC; 1317 return; 1318 } 1319 1320 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1321 return; 1322 1323 if (pm == pmap_kernel()) 1324 pmap_vac_me_kpmap(pg, pm, va); 1325 else 1326 pmap_vac_me_user(pg, pm, va); 1327 1328 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1329 } 1330 1331 static void 1332 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1333 { 1334 u_int u_cacheable, u_entries; 1335 struct pv_entry *pv; 1336 pmap_t last_pmap = pm; 1337 1338 /* 1339 * Pass one, see if there are both kernel and user pmaps for 1340 * this page. Calculate whether there are user-writable or 1341 * kernel-writable pages. 1342 */ 1343 u_cacheable = 0; 1344 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1345 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1346 u_cacheable++; 1347 } 1348 1349 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1350 1351 /* 1352 * We know we have just been updating a kernel entry, so if 1353 * all user pages are already cacheable, then there is nothing 1354 * further to do. 1355 */ 1356 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1357 return; 1358 1359 if (u_entries) { 1360 /* 1361 * Scan over the list again, for each entry, if it 1362 * might not be set correctly, call pmap_vac_me_user 1363 * to recalculate the settings. 1364 */ 1365 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1366 /* 1367 * We know kernel mappings will get set 1368 * correctly in other calls. We also know 1369 * that if the pmap is the same as last_pmap 1370 * then we've just handled this entry. 1371 */ 1372 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1373 continue; 1374 1375 /* 1376 * If there are kernel entries and this page 1377 * is writable but non-cacheable, then we can 1378 * skip this entry also. 1379 */ 1380 if (pg->mdpage.k_mappings && 1381 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1382 (PVF_NC | PVF_WRITE)) 1383 continue; 1384 1385 /* 1386 * Similarly if there are no kernel-writable 1387 * entries and the page is already 1388 * read-only/cacheable. 1389 */ 1390 if (pg->mdpage.krw_mappings == 0 && 1391 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1392 continue; 1393 1394 /* 1395 * For some of the remaining cases, we know 1396 * that we must recalculate, but for others we 1397 * can't tell if they are correct or not, so 1398 * we recalculate anyway. 1399 */ 1400 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1401 } 1402 1403 if (pg->mdpage.k_mappings == 0) 1404 return; 1405 } 1406 1407 pmap_vac_me_user(pg, pm, va); 1408 } 1409 1410 static void 1411 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1412 { 1413 pmap_t kpmap = pmap_kernel(); 1414 struct pv_entry *pv, *npv; 1415 struct l2_bucket *l2b; 1416 pt_entry_t *ptep, pte; 1417 u_int entries = 0; 1418 u_int writable = 0; 1419 u_int cacheable_entries = 0; 1420 u_int kern_cacheable = 0; 1421 u_int other_writable = 0; 1422 1423 /* 1424 * Count mappings and writable mappings in this pmap. 1425 * Include kernel mappings as part of our own. 1426 * Keep a pointer to the first one. 1427 */ 1428 for (pv = npv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1429 /* Count mappings in the same pmap */ 1430 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1431 if (entries++ == 0) 1432 npv = pv; 1433 1434 /* Cacheable mappings */ 1435 if ((pv->pv_flags & PVF_NC) == 0) { 1436 cacheable_entries++; 1437 if (kpmap == pv->pv_pmap) 1438 kern_cacheable++; 1439 } 1440 1441 /* Writable mappings */ 1442 if (pv->pv_flags & PVF_WRITE) 1443 ++writable; 1444 } else 1445 if (pv->pv_flags & PVF_WRITE) 1446 other_writable = 1; 1447 } 1448 1449 /* 1450 * Enable or disable caching as necessary. 1451 * Note: the first entry might be part of the kernel pmap, 1452 * so we can't assume this is indicative of the state of the 1453 * other (maybe non-kpmap) entries. 1454 */ 1455 if ((entries > 1 && writable) || 1456 (entries > 0 && pm == kpmap && other_writable)) { 1457 if (cacheable_entries == 0) 1458 return; 1459 1460 for (pv = npv; pv; pv = pv->pv_next) { 1461 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1462 (pv->pv_flags & PVF_NC)) 1463 continue; 1464 1465 pv->pv_flags |= PVF_NC; 1466 1467 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1468 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1469 pte = *ptep & ~L2_S_CACHE_MASK; 1470 1471 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1472 l2pte_valid(pte)) { 1473 if (PV_BEEN_EXECD(pv->pv_flags)) { 1474 pmap_idcache_wbinv_range(pv->pv_pmap, 1475 pv->pv_va, PAGE_SIZE); 1476 pmap_tlb_flushID_SE(pv->pv_pmap, 1477 pv->pv_va); 1478 } else 1479 if (PV_BEEN_REFD(pv->pv_flags)) { 1480 pmap_dcache_wb_range(pv->pv_pmap, 1481 pv->pv_va, PAGE_SIZE, TRUE, 1482 (pv->pv_flags & PVF_WRITE) == 0); 1483 pmap_tlb_flushD_SE(pv->pv_pmap, 1484 pv->pv_va); 1485 } 1486 } 1487 1488 *ptep = pte; 1489 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1490 } 1491 cpu_cpwait(); 1492 } else 1493 if (entries > cacheable_entries) { 1494 /* 1495 * Turn cacheing back on for some pages. If it is a kernel 1496 * page, only do so if there are no other writable pages. 1497 */ 1498 for (pv = npv; pv; pv = pv->pv_next) { 1499 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1500 (kpmap != pv->pv_pmap || other_writable))) 1501 continue; 1502 1503 pv->pv_flags &= ~PVF_NC; 1504 1505 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1506 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1507 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1508 1509 if (l2pte_valid(pte)) { 1510 if (PV_BEEN_EXECD(pv->pv_flags)) { 1511 pmap_tlb_flushID_SE(pv->pv_pmap, 1512 pv->pv_va); 1513 } else 1514 if (PV_BEEN_REFD(pv->pv_flags)) { 1515 pmap_tlb_flushD_SE(pv->pv_pmap, 1516 pv->pv_va); 1517 } 1518 } 1519 1520 *ptep = pte; 1521 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1522 } 1523 } 1524 } 1525 1526 /* 1527 * Modify pte bits for all ptes corresponding to the given physical address. 1528 * We use `maskbits' rather than `clearbits' because we're always passing 1529 * constants and the latter would require an extra inversion at run-time. 1530 */ 1531 static void 1532 pmap_clearbit(struct vm_page *pg, u_int maskbits) 1533 { 1534 struct l2_bucket *l2b; 1535 struct pv_entry *pv; 1536 pt_entry_t *ptep, npte, opte; 1537 pmap_t pm; 1538 vaddr_t va; 1539 u_int oflags; 1540 1541 NPDEBUG(PDB_BITS, 1542 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 1543 pg, pg->phys_addr, maskbits)); 1544 1545 PMAP_HEAD_TO_MAP_LOCK(); 1546 simple_lock(&pg->mdpage.pvh_slock); 1547 1548 /* 1549 * Clear saved attributes (modify, reference) 1550 */ 1551 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1552 1553 if (pg->mdpage.pvh_list == NULL) { 1554 simple_unlock(&pg->mdpage.pvh_slock); 1555 PMAP_HEAD_TO_MAP_UNLOCK(); 1556 return; 1557 } 1558 1559 /* 1560 * Loop over all current mappings setting/clearing as appropos 1561 */ 1562 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1563 va = pv->pv_va; 1564 pm = pv->pv_pmap; 1565 oflags = pv->pv_flags; 1566 pv->pv_flags &= ~maskbits; 1567 1568 pmap_acquire_pmap_lock(pm); 1569 1570 l2b = pmap_get_l2_bucket(pm, va); 1571 KDASSERT(l2b != NULL); 1572 1573 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1574 npte = opte = *ptep; 1575 1576 NPDEBUG(PDB_BITS, 1577 printf( 1578 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 1579 pv, pv->pv_pmap, pv->pv_va, oflags)); 1580 1581 if (maskbits & (PVF_WRITE|PVF_MOD)) { 1582 if ((pv->pv_flags & PVF_NC)) { 1583 /* 1584 * Entry is not cacheable: 1585 * 1586 * Don't turn caching on again if this is a 1587 * modified emulation. This would be 1588 * inconsitent with the settings created by 1589 * pmap_vac_me_harder(). Otherwise, it's safe 1590 * to re-enable cacheing. 1591 * 1592 * There's no need to call pmap_vac_me_harder() 1593 * here: all pages are losing their write 1594 * permission. 1595 */ 1596 if (maskbits & PVF_WRITE) { 1597 npte |= pte_l2_s_cache_mode; 1598 pv->pv_flags &= ~PVF_NC; 1599 } 1600 } else 1601 if (opte & L2_S_PROT_W) { 1602 /* 1603 * Entry is writable/cacheable: check if pmap 1604 * is current if it is flush it, otherwise it 1605 * won't be in the cache 1606 */ 1607 if (PV_BEEN_EXECD(oflags)) 1608 pmap_idcache_wbinv_range(pm, pv->pv_va, 1609 PAGE_SIZE); 1610 else 1611 if (PV_BEEN_REFD(oflags)) 1612 pmap_dcache_wb_range(pm, pv->pv_va, 1613 PAGE_SIZE, 1614 (maskbits & PVF_REF) ? TRUE : FALSE, 1615 FALSE); 1616 } 1617 1618 /* make the pte read only */ 1619 npte &= ~L2_S_PROT_W; 1620 1621 if (maskbits & PVF_WRITE) { 1622 /* 1623 * Keep alias accounting up to date 1624 */ 1625 if (pv->pv_pmap == pmap_kernel()) { 1626 if (oflags & PVF_WRITE) { 1627 pg->mdpage.krw_mappings--; 1628 pg->mdpage.kro_mappings++; 1629 } 1630 } else 1631 if (oflags & PVF_WRITE) { 1632 pg->mdpage.urw_mappings--; 1633 pg->mdpage.uro_mappings++; 1634 } 1635 } 1636 } 1637 1638 if (maskbits & PVF_REF) { 1639 if ((pv->pv_flags & PVF_NC) == 0 && 1640 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1641 /* 1642 * Check npte here; we may have already 1643 * done the wbinv above, and the validity 1644 * of the PTE is the same for opte and 1645 * npte. 1646 */ 1647 if (npte & L2_S_PROT_W) { 1648 if (PV_BEEN_EXECD(oflags)) 1649 pmap_idcache_wbinv_range(pm, 1650 pv->pv_va, PAGE_SIZE); 1651 else 1652 if (PV_BEEN_REFD(oflags)) 1653 pmap_dcache_wb_range(pm, 1654 pv->pv_va, PAGE_SIZE, 1655 TRUE, FALSE); 1656 } else 1657 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1658 /* XXXJRT need idcache_inv_range */ 1659 if (PV_BEEN_EXECD(oflags)) 1660 pmap_idcache_wbinv_range(pm, 1661 pv->pv_va, PAGE_SIZE); 1662 else 1663 if (PV_BEEN_REFD(oflags)) 1664 pmap_dcache_wb_range(pm, 1665 pv->pv_va, PAGE_SIZE, 1666 TRUE, TRUE); 1667 } 1668 } 1669 1670 /* 1671 * Make the PTE invalid so that we will take a 1672 * page fault the next time the mapping is 1673 * referenced. 1674 */ 1675 npte &= ~L2_TYPE_MASK; 1676 npte |= L2_TYPE_INV; 1677 } 1678 1679 if (npte != opte) { 1680 *ptep = npte; 1681 PTE_SYNC(ptep); 1682 /* Flush the TLB entry if a current pmap. */ 1683 if (PV_BEEN_EXECD(oflags)) 1684 pmap_tlb_flushID_SE(pm, pv->pv_va); 1685 else 1686 if (PV_BEEN_REFD(oflags)) 1687 pmap_tlb_flushD_SE(pm, pv->pv_va); 1688 } 1689 1690 pmap_release_pmap_lock(pm); 1691 1692 NPDEBUG(PDB_BITS, 1693 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 1694 pm, va, opte, npte)); 1695 } 1696 1697 simple_unlock(&pg->mdpage.pvh_slock); 1698 PMAP_HEAD_TO_MAP_UNLOCK(); 1699 } 1700 1701 /* 1702 * pmap_clean_page() 1703 * 1704 * This is a local function used to work out the best strategy to clean 1705 * a single page referenced by its entry in the PV table. It's used by 1706 * pmap_copy_page, pmap_zero page and maybe some others later on. 1707 * 1708 * Its policy is effectively: 1709 * o If there are no mappings, we don't bother doing anything with the cache. 1710 * o If there is one mapping, we clean just that page. 1711 * o If there are multiple mappings, we clean the entire cache. 1712 * 1713 * So that some functions can be further optimised, it returns 0 if it didn't 1714 * clean the entire cache, or 1 if it did. 1715 * 1716 * XXX One bug in this routine is that if the pv_entry has a single page 1717 * mapped at 0x00000000 a whole cache clean will be performed rather than 1718 * just the 1 page. Since this should not occur in everyday use and if it does 1719 * it will just result in not the most efficient clean for the page. 1720 */ 1721 static int 1722 pmap_clean_page(struct pv_entry *pv, boolean_t is_src) 1723 { 1724 pmap_t pm, pm_to_clean = NULL; 1725 struct pv_entry *npv; 1726 u_int cache_needs_cleaning = 0; 1727 u_int flags = 0; 1728 vaddr_t page_to_clean = 0; 1729 1730 if (pv == NULL) { 1731 /* nothing mapped in so nothing to flush */ 1732 return (0); 1733 } 1734 1735 /* 1736 * Since we flush the cache each time we change to a different 1737 * user vmspace, we only need to flush the page if it is in the 1738 * current pmap. 1739 */ 1740 if (curproc) 1741 pm = curproc->p_vmspace->vm_map.pmap; 1742 else 1743 pm = pmap_kernel(); 1744 1745 for (npv = pv; npv; npv = npv->pv_next) { 1746 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 1747 flags |= npv->pv_flags; 1748 /* 1749 * The page is mapped non-cacheable in 1750 * this map. No need to flush the cache. 1751 */ 1752 if (npv->pv_flags & PVF_NC) { 1753 #ifdef DIAGNOSTIC 1754 if (cache_needs_cleaning) 1755 panic("pmap_clean_page: " 1756 "cache inconsistency"); 1757 #endif 1758 break; 1759 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 1760 continue; 1761 if (cache_needs_cleaning) { 1762 page_to_clean = 0; 1763 break; 1764 } else { 1765 page_to_clean = npv->pv_va; 1766 pm_to_clean = npv->pv_pmap; 1767 } 1768 cache_needs_cleaning = 1; 1769 } 1770 } 1771 1772 if (page_to_clean) { 1773 if (PV_BEEN_EXECD(flags)) 1774 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 1775 PAGE_SIZE); 1776 else 1777 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 1778 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 1779 } else if (cache_needs_cleaning) { 1780 if (PV_BEEN_EXECD(flags)) 1781 pmap_idcache_wbinv_all(pm); 1782 else 1783 pmap_dcache_wbinv_all(pm); 1784 return (1); 1785 } 1786 return (0); 1787 } 1788 1789 /* 1790 * Routine: pmap_page_remove 1791 * Function: 1792 * Removes this physical page from 1793 * all physical maps in which it resides. 1794 * Reflects back modify bits to the pager. 1795 */ 1796 static void 1797 pmap_page_remove(struct vm_page *pg) 1798 { 1799 struct l2_bucket *l2b; 1800 struct pv_entry *pv, *npv; 1801 pmap_t pm, curpm; 1802 pt_entry_t *ptep, pte; 1803 boolean_t flush; 1804 u_int flags; 1805 1806 NPDEBUG(PDB_FOLLOW, 1807 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, pg->phys_addr)); 1808 1809 PMAP_HEAD_TO_MAP_LOCK(); 1810 simple_lock(&pg->mdpage.pvh_slock); 1811 1812 pv = pg->mdpage.pvh_list; 1813 if (pv == NULL) { 1814 simple_unlock(&pg->mdpage.pvh_slock); 1815 PMAP_HEAD_TO_MAP_UNLOCK(); 1816 return; 1817 } 1818 1819 /* 1820 * Clear alias counts 1821 */ 1822 pg->mdpage.k_mappings = 0; 1823 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 1824 1825 flush = FALSE; 1826 flags = 0; 1827 if (curproc) 1828 curpm = curproc->p_vmspace->vm_map.pmap; 1829 else 1830 curpm = pmap_kernel(); 1831 1832 pmap_clean_page(pv, FALSE); 1833 1834 while (pv) { 1835 pm = pv->pv_pmap; 1836 if (flush == FALSE && (pm == curpm || pm == pmap_kernel())) 1837 flush = TRUE; 1838 1839 pmap_acquire_pmap_lock(pm); 1840 1841 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 1842 KDASSERT(l2b != NULL); 1843 1844 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1845 pte = *ptep; 1846 1847 /* 1848 * Update statistics 1849 */ 1850 --pm->pm_stats.resident_count; 1851 1852 /* Wired bit */ 1853 if (pv->pv_flags & PVF_WIRED) 1854 --pm->pm_stats.wired_count; 1855 1856 flags |= pv->pv_flags; 1857 1858 /* 1859 * Invalidate the PTEs. 1860 */ 1861 *ptep = 0; 1862 PTE_SYNC_CURRENT(pm, ptep); 1863 pmap_free_l2_bucket(pm, l2b, 1); 1864 1865 npv = pv->pv_next; 1866 pool_put(&pmap_pv_pool, pv); 1867 pv = npv; 1868 pmap_release_pmap_lock(pm); 1869 } 1870 pg->mdpage.pvh_list = NULL; 1871 simple_unlock(&pg->mdpage.pvh_slock); 1872 PMAP_HEAD_TO_MAP_UNLOCK(); 1873 1874 if (flush) { 1875 /* 1876 * Note: We can't use pmap_tlb_flush{I,}D() here since that 1877 * would need a subsequent call to pmap_update() to ensure 1878 * curpm->pm_cstate.cs_all is reset. Our callers are not 1879 * required to do that (see pmap(9)), so we can't modify 1880 * the current pmap's state. 1881 */ 1882 if (PV_BEEN_EXECD(flags)) 1883 cpu_tlb_flushID(); 1884 else 1885 cpu_tlb_flushD(); 1886 } 1887 cpu_cpwait(); 1888 } 1889 1890 /* 1891 * pmap_t pmap_create(void) 1892 * 1893 * Create a new pmap structure from scratch. 1894 */ 1895 pmap_t 1896 pmap_create(void) 1897 { 1898 pmap_t pm; 1899 1900 pm = pool_cache_get(&pmap_pmap_cache, PR_WAITOK); 1901 1902 simple_lock_init(&pm->pm_lock); 1903 pm->pm_obj.pgops = NULL; /* currently not a mappable object */ 1904 TAILQ_INIT(&pm->pm_obj.memq); 1905 pm->pm_obj.uo_npages = 0; 1906 pm->pm_obj.uo_refs = 1; 1907 pm->pm_stats.wired_count = 0; 1908 pm->pm_stats.resident_count = 1; 1909 pm->pm_cstate.cs_all = 0; 1910 pmap_alloc_l1(pm); 1911 1912 /* 1913 * Note: The pool cache ensures that the pm_l2[] array is already 1914 * initialised to zero. 1915 */ 1916 1917 pmap_pinit(pm); 1918 1919 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 1920 1921 return (pm); 1922 } 1923 1924 /* 1925 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 1926 * int flags) 1927 * 1928 * Insert the given physical page (p) at 1929 * the specified virtual address (v) in the 1930 * target physical map with the protection requested. 1931 * 1932 * NB: This is the only routine which MAY NOT lazy-evaluate 1933 * or lose information. That is, this routine must actually 1934 * insert this page into the given map NOW. 1935 */ 1936 int 1937 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 1938 { 1939 struct l2_bucket *l2b; 1940 struct vm_page *pg, *opg; 1941 struct pv_entry *pve; 1942 pt_entry_t *ptep, npte, opte; 1943 u_int nflags; 1944 u_int oflags; 1945 1946 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 1947 1948 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 1949 KDASSERT(((va | pa) & PGOFSET) == 0); 1950 1951 /* 1952 * Get a pointer to the page. Later on in this function, we 1953 * test for a managed page by checking pg != NULL. 1954 */ 1955 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 1956 1957 nflags = 0; 1958 if (prot & VM_PROT_WRITE) 1959 nflags |= PVF_WRITE; 1960 if (prot & VM_PROT_EXECUTE) 1961 nflags |= PVF_EXEC; 1962 if (flags & PMAP_WIRED) 1963 nflags |= PVF_WIRED; 1964 1965 PMAP_MAP_TO_HEAD_LOCK(); 1966 pmap_acquire_pmap_lock(pm); 1967 1968 /* 1969 * Fetch the L2 bucket which maps this page, allocating one if 1970 * necessary for user pmaps. 1971 */ 1972 if (pm == pmap_kernel()) 1973 l2b = pmap_get_l2_bucket(pm, va); 1974 else 1975 l2b = pmap_alloc_l2_bucket(pm, va); 1976 if (l2b == NULL) { 1977 if (flags & PMAP_CANFAIL) { 1978 pmap_release_pmap_lock(pm); 1979 PMAP_MAP_TO_HEAD_UNLOCK(); 1980 return (ENOMEM); 1981 } 1982 panic("pmap_enter: failed to allocate L2 bucket"); 1983 } 1984 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1985 opte = *ptep; 1986 npte = pa; 1987 oflags = 0; 1988 1989 if (opte) { 1990 /* 1991 * There is already a mapping at this address. 1992 * If the physical address is different, lookup the 1993 * vm_page. 1994 */ 1995 if (l2pte_pa(opte) != pa) 1996 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 1997 else 1998 opg = pg; 1999 } else 2000 opg = NULL; 2001 2002 if (pg) { 2003 /* 2004 * This is to be a managed mapping. 2005 */ 2006 if ((flags & VM_PROT_ALL) || 2007 (pg->mdpage.pvh_attrs & PVF_REF)) { 2008 /* 2009 * - The access type indicates that we don't need 2010 * to do referenced emulation. 2011 * OR 2012 * - The physical page has already been referenced 2013 * so no need to re-do referenced emulation here. 2014 */ 2015 npte |= L2_S_PROTO; 2016 2017 nflags |= PVF_REF; 2018 2019 if ((prot & VM_PROT_WRITE) != 0 && 2020 ((flags & VM_PROT_WRITE) != 0 || 2021 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2022 /* 2023 * This is a writable mapping, and the 2024 * page's mod state indicates it has 2025 * already been modified. Make it 2026 * writable from the outset. 2027 */ 2028 npte |= L2_S_PROT_W; 2029 nflags |= PVF_MOD; 2030 } 2031 } else { 2032 /* 2033 * Need to do page referenced emulation. 2034 */ 2035 npte |= L2_TYPE_INV; 2036 } 2037 2038 npte |= pte_l2_s_cache_mode; 2039 2040 if (pg == opg) { 2041 /* 2042 * We're changing the attrs of an existing mapping. 2043 */ 2044 simple_lock(&pg->mdpage.pvh_slock); 2045 oflags = pmap_modify_pv(pg, pm, va, 2046 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2047 PVF_MOD | PVF_REF, nflags); 2048 simple_unlock(&pg->mdpage.pvh_slock); 2049 2050 /* 2051 * We may need to flush the cache if we're 2052 * doing rw-ro... 2053 */ 2054 if (pm->pm_cstate.cs_cache_d && 2055 (oflags & PVF_NC) == 0 && 2056 (opte & L2_S_PROT_W) != 0 && 2057 (prot & VM_PROT_WRITE) == 0) 2058 cpu_dcache_wb_range(va, PAGE_SIZE); 2059 } else { 2060 /* 2061 * New mapping, or changing the backing page 2062 * of an existing mapping. 2063 */ 2064 if (opg) { 2065 /* 2066 * Replacing an existing mapping with a new one. 2067 * It is part of our managed memory so we 2068 * must remove it from the PV list 2069 */ 2070 simple_lock(&opg->mdpage.pvh_slock); 2071 pve = pmap_remove_pv(opg, pm, va); 2072 pmap_vac_me_harder(opg, pm, 0); 2073 simple_unlock(&opg->mdpage.pvh_slock); 2074 oflags = pve->pv_flags; 2075 2076 /* 2077 * If the old mapping was valid (ref/mod 2078 * emulation creates 'invalid' mappings 2079 * initially) then make sure to frob 2080 * the cache. 2081 */ 2082 if ((oflags & PVF_NC) == 0 && 2083 l2pte_valid(opte)) { 2084 if (PV_BEEN_EXECD(oflags)) { 2085 pmap_idcache_wbinv_range(pm, va, 2086 PAGE_SIZE); 2087 } else 2088 if (PV_BEEN_REFD(oflags)) { 2089 pmap_dcache_wb_range(pm, va, 2090 PAGE_SIZE, TRUE, 2091 (oflags & PVF_WRITE) == 0); 2092 } 2093 } 2094 } else 2095 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2096 if ((flags & PMAP_CANFAIL) == 0) 2097 panic("pmap_enter: no pv entries"); 2098 2099 if (pm != pmap_kernel()) 2100 pmap_free_l2_bucket(pm, l2b, 0); 2101 pmap_release_pmap_lock(pm); 2102 PMAP_MAP_TO_HEAD_UNLOCK(); 2103 NPDEBUG(PDB_ENTER, 2104 printf("pmap_enter: ENOMEM\n")); 2105 return (ENOMEM); 2106 } 2107 2108 pmap_enter_pv(pg, pve, pm, va, nflags); 2109 } 2110 } else { 2111 /* 2112 * We're mapping an unmanaged page. 2113 * These are always readable, and possibly writable, from 2114 * the get go as we don't need to track ref/mod status. 2115 */ 2116 npte |= L2_S_PROTO; 2117 if (prot & VM_PROT_WRITE) 2118 npte |= L2_S_PROT_W; 2119 2120 /* 2121 * Make sure the vector table is mapped cacheable 2122 */ 2123 if (pm != pmap_kernel() && va == vector_page) 2124 npte |= pte_l2_s_cache_mode; 2125 2126 if (opg) { 2127 /* 2128 * Looks like there's an existing 'managed' mapping 2129 * at this address. 2130 */ 2131 simple_lock(&opg->mdpage.pvh_slock); 2132 pve = pmap_remove_pv(opg, pm, va); 2133 pmap_vac_me_harder(opg, pm, 0); 2134 simple_unlock(&opg->mdpage.pvh_slock); 2135 oflags = pve->pv_flags; 2136 2137 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2138 if (PV_BEEN_EXECD(oflags)) 2139 pmap_idcache_wbinv_range(pm, va, 2140 PAGE_SIZE); 2141 else 2142 if (PV_BEEN_REFD(oflags)) 2143 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2144 TRUE, (oflags & PVF_WRITE) == 0); 2145 } 2146 pool_put(&pmap_pv_pool, pve); 2147 } 2148 } 2149 2150 /* 2151 * Make sure userland mappings get the right permissions 2152 */ 2153 if (pm != pmap_kernel() && va != vector_page) 2154 npte |= L2_S_PROT_U; 2155 2156 /* 2157 * Keep the stats up to date 2158 */ 2159 if (opte == 0) { 2160 l2b->l2b_occupancy++; 2161 pm->pm_stats.resident_count++; 2162 } 2163 2164 NPDEBUG(PDB_ENTER, 2165 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2166 2167 /* 2168 * If this is just a wiring change, the two PTEs will be 2169 * identical, so there's no need to update the page table. 2170 */ 2171 if (npte != opte) { 2172 boolean_t is_cached = pmap_is_cached(pm); 2173 2174 *ptep = npte; 2175 if (is_cached) { 2176 /* 2177 * We only need to frob the cache/tlb if this pmap 2178 * is current 2179 */ 2180 PTE_SYNC(ptep); 2181 if (va != vector_page && l2pte_valid(npte)) { 2182 /* 2183 * This mapping is likely to be accessed as 2184 * soon as we return to userland. Fix up the 2185 * L1 entry to avoid taking another 2186 * page/domain fault. 2187 */ 2188 pd_entry_t *pl1pd, l1pd; 2189 2190 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2191 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2192 L1_C_PROTO; 2193 if (*pl1pd != l1pd) { 2194 *pl1pd = l1pd; 2195 PTE_SYNC(pl1pd); 2196 } 2197 } 2198 } 2199 2200 if (PV_BEEN_EXECD(oflags)) 2201 pmap_tlb_flushID_SE(pm, va); 2202 else 2203 if (PV_BEEN_REFD(oflags)) 2204 pmap_tlb_flushD_SE(pm, va); 2205 2206 NPDEBUG(PDB_ENTER, 2207 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2208 is_cached, pm->pm_cstate.cs_all)); 2209 2210 if (pg != NULL) { 2211 simple_lock(&pg->mdpage.pvh_slock); 2212 pmap_vac_me_harder(pg, pm, va); 2213 simple_unlock(&pg->mdpage.pvh_slock); 2214 } 2215 } 2216 2217 pmap_release_pmap_lock(pm); 2218 PMAP_MAP_TO_HEAD_UNLOCK(); 2219 2220 return (0); 2221 } 2222 2223 /* 2224 * pmap_remove() 2225 * 2226 * pmap_remove is responsible for nuking a number of mappings for a range 2227 * of virtual address space in the current pmap. To do this efficiently 2228 * is interesting, because in a number of cases a wide virtual address 2229 * range may be supplied that contains few actual mappings. So, the 2230 * optimisations are: 2231 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 2232 * 2. Build up a list of pages we've hit, up to a maximum, so we can 2233 * maybe do just a partial cache clean. This path of execution is 2234 * complicated by the fact that the cache must be flushed _before_ 2235 * the PTE is nuked, being a VAC :-) 2236 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 2237 * all invalidations until pmap_update(), since pmap_remove_all() has 2238 * already flushed the cache. 2239 * 4. Maybe later fast-case a single page, but I don't think this is 2240 * going to make _that_ much difference overall. 2241 */ 2242 2243 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 2244 2245 void 2246 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 2247 { 2248 struct l2_bucket *l2b; 2249 vaddr_t next_bucket; 2250 pt_entry_t *ptep; 2251 u_int cleanlist_idx, total, cnt; 2252 struct { 2253 vaddr_t va; 2254 pt_entry_t *pte; 2255 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 2256 u_int mappings, is_exec, is_refd; 2257 2258 NPDEBUG(PDB_REMOVE, printf("pmap_remove: pmap=%p sva=%08lx eva=%08lx\n", 2259 pm, sva, eva)); 2260 2261 /* 2262 * we lock in the pmap => pv_head direction 2263 */ 2264 PMAP_MAP_TO_HEAD_LOCK(); 2265 pmap_acquire_pmap_lock(pm); 2266 2267 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 2268 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2269 if (pm->pm_cstate.cs_tlb == 0) 2270 pm->pm_remove_all = TRUE; 2271 } else 2272 cleanlist_idx = 0; 2273 2274 total = 0; 2275 2276 while (sva < eva) { 2277 /* 2278 * Do one L2 bucket's worth at a time. 2279 */ 2280 next_bucket = L2_NEXT_BUCKET(sva); 2281 if (next_bucket > eva) 2282 next_bucket = eva; 2283 2284 l2b = pmap_get_l2_bucket(pm, sva); 2285 if (l2b == NULL) { 2286 sva = next_bucket; 2287 continue; 2288 } 2289 2290 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2291 mappings = 0; 2292 2293 while (sva < next_bucket) { 2294 struct vm_page *pg; 2295 pt_entry_t pte; 2296 paddr_t pa; 2297 2298 pte = *ptep; 2299 2300 if (pte == 0) { 2301 /* 2302 * Nothing here, move along 2303 */ 2304 sva += PAGE_SIZE; 2305 ptep++; 2306 continue; 2307 } 2308 2309 pm->pm_stats.resident_count--; 2310 pa = l2pte_pa(pte); 2311 is_exec = 0; 2312 is_refd = 1; 2313 2314 /* 2315 * Update flags. In a number of circumstances, 2316 * we could cluster a lot of these and do a 2317 * number of sequential pages in one go. 2318 */ 2319 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 2320 struct pv_entry *pve; 2321 simple_lock(&pg->mdpage.pvh_slock); 2322 pve = pmap_remove_pv(pg, pm, sva); 2323 pmap_vac_me_harder(pg, pm, 0); 2324 simple_unlock(&pg->mdpage.pvh_slock); 2325 if (pve != NULL) { 2326 if (pm->pm_remove_all == FALSE) { 2327 is_exec = 2328 PV_BEEN_EXECD(pve->pv_flags); 2329 is_refd = 2330 PV_BEEN_REFD(pve->pv_flags); 2331 } 2332 pool_put(&pmap_pv_pool, pve); 2333 } 2334 } 2335 2336 if (!l2pte_valid(pte)) { 2337 *ptep = 0; 2338 PTE_SYNC_CURRENT(pm, ptep); 2339 sva += PAGE_SIZE; 2340 ptep++; 2341 mappings++; 2342 continue; 2343 } 2344 2345 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 2346 /* Add to the clean list. */ 2347 cleanlist[cleanlist_idx].pte = ptep; 2348 cleanlist[cleanlist_idx].va = 2349 sva | (is_exec & 1); 2350 cleanlist_idx++; 2351 } else 2352 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 2353 /* Nuke everything if needed. */ 2354 pmap_idcache_wbinv_all(pm); 2355 pmap_tlb_flushID(pm); 2356 2357 /* 2358 * Roll back the previous PTE list, 2359 * and zero out the current PTE. 2360 */ 2361 for (cnt = 0; 2362 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 2363 *cleanlist[cnt].pte = 0; 2364 } 2365 *ptep = 0; 2366 PTE_SYNC(ptep); 2367 cleanlist_idx++; 2368 pm->pm_remove_all = TRUE; 2369 } else { 2370 *ptep = 0; 2371 PTE_SYNC(ptep); 2372 if (pm->pm_remove_all == FALSE) { 2373 if (is_exec) 2374 pmap_tlb_flushID_SE(pm, sva); 2375 else 2376 if (is_refd) 2377 pmap_tlb_flushD_SE(pm, sva); 2378 } 2379 } 2380 2381 sva += PAGE_SIZE; 2382 ptep++; 2383 mappings++; 2384 } 2385 2386 /* 2387 * Deal with any left overs 2388 */ 2389 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 2390 total += cleanlist_idx; 2391 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 2392 if (pm->pm_cstate.cs_all != 0) { 2393 vaddr_t clva = cleanlist[cnt].va & ~1; 2394 if (cleanlist[cnt].va & 1) { 2395 pmap_idcache_wbinv_range(pm, 2396 clva, PAGE_SIZE); 2397 pmap_tlb_flushID_SE(pm, clva); 2398 } else { 2399 pmap_dcache_wb_range(pm, 2400 clva, PAGE_SIZE, TRUE, 2401 FALSE); 2402 pmap_tlb_flushD_SE(pm, clva); 2403 } 2404 } 2405 *cleanlist[cnt].pte = 0; 2406 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 2407 } 2408 2409 /* 2410 * If it looks like we're removing a whole bunch 2411 * of mappings, it's faster to just write-back 2412 * the whole cache now and defer TLB flushes until 2413 * pmap_update() is called. 2414 */ 2415 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 2416 cleanlist_idx = 0; 2417 else { 2418 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2419 pmap_idcache_wbinv_all(pm); 2420 pm->pm_remove_all = TRUE; 2421 } 2422 } 2423 2424 pmap_free_l2_bucket(pm, l2b, mappings); 2425 } 2426 2427 pmap_release_pmap_lock(pm); 2428 PMAP_MAP_TO_HEAD_UNLOCK(); 2429 } 2430 2431 /* 2432 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 2433 * 2434 * We assume there is already sufficient KVM space available 2435 * to do this, as we can't allocate L2 descriptor tables/metadata 2436 * from here. 2437 */ 2438 void 2439 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 2440 { 2441 struct l2_bucket *l2b; 2442 pt_entry_t *ptep, opte; 2443 2444 NPDEBUG(PDB_KENTER, 2445 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 2446 va, pa, prot)); 2447 2448 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2449 KDASSERT(l2b != NULL); 2450 2451 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2452 opte = *ptep; 2453 2454 if (l2pte_valid(opte)) { 2455 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2456 cpu_tlb_flushD_SE(va); 2457 cpu_cpwait(); 2458 } else 2459 if (opte == 0) 2460 l2b->l2b_occupancy++; 2461 2462 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 2463 pte_l2_s_cache_mode; 2464 PTE_SYNC(ptep); 2465 } 2466 2467 void 2468 pmap_kremove(vaddr_t va, vsize_t len) 2469 { 2470 struct l2_bucket *l2b; 2471 pt_entry_t *ptep, *sptep, opte; 2472 vaddr_t next_bucket, eva; 2473 u_int mappings; 2474 2475 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 2476 va, len)); 2477 2478 eva = va + len; 2479 2480 while (va < eva) { 2481 next_bucket = L2_NEXT_BUCKET(va); 2482 if (next_bucket > eva) 2483 next_bucket = eva; 2484 2485 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2486 KDASSERT(l2b != NULL); 2487 2488 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 2489 mappings = 0; 2490 2491 while (va < next_bucket) { 2492 opte = *ptep; 2493 if (l2pte_valid(opte)) { 2494 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2495 cpu_tlb_flushD_SE(va); 2496 } 2497 if (opte) { 2498 *ptep = 0; 2499 mappings++; 2500 } 2501 va += PAGE_SIZE; 2502 ptep++; 2503 } 2504 KDASSERT(mappings <= l2b->l2b_occupancy); 2505 l2b->l2b_occupancy -= mappings; 2506 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 2507 } 2508 cpu_cpwait(); 2509 } 2510 2511 boolean_t 2512 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 2513 { 2514 struct l2_dtable *l2; 2515 pd_entry_t *pl1pd, l1pd; 2516 pt_entry_t *ptep, pte; 2517 paddr_t pa; 2518 u_int l1idx; 2519 2520 pmap_acquire_pmap_lock(pm); 2521 2522 l1idx = L1_IDX(va); 2523 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2524 l1pd = *pl1pd; 2525 2526 if (l1pte_section_p(l1pd)) { 2527 /* 2528 * These should only happen for pmap_kernel() 2529 */ 2530 KDASSERT(pm == pmap_kernel()); 2531 pmap_release_pmap_lock(pm); 2532 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 2533 } else { 2534 /* 2535 * Note that we can't rely on the validity of the L1 2536 * descriptor as an indication that a mapping exists. 2537 * We have to look it up in the L2 dtable. 2538 */ 2539 l2 = pm->pm_l2[L2_IDX(l1idx)]; 2540 2541 if (l2 == NULL || 2542 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 2543 pmap_release_pmap_lock(pm); 2544 return (FALSE); 2545 } 2546 2547 ptep = &ptep[l2pte_index(va)]; 2548 pte = *ptep; 2549 pmap_release_pmap_lock(pm); 2550 2551 if (pte == 0) 2552 return (FALSE); 2553 2554 switch (pte & L2_TYPE_MASK) { 2555 case L2_TYPE_L: 2556 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 2557 break; 2558 2559 default: 2560 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 2561 break; 2562 } 2563 } 2564 2565 if (pap != NULL) 2566 *pap = pa; 2567 2568 return (TRUE); 2569 } 2570 2571 void 2572 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 2573 { 2574 struct l2_bucket *l2b; 2575 pt_entry_t *ptep, pte; 2576 vaddr_t next_bucket; 2577 u_int flags; 2578 int flush; 2579 2580 NPDEBUG(PDB_PROTECT, 2581 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 2582 pm, sva, eva, prot)); 2583 2584 if ((prot & VM_PROT_READ) == 0) { 2585 pmap_remove(pm, sva, eva); 2586 return; 2587 } 2588 2589 if (prot & VM_PROT_WRITE) { 2590 /* 2591 * If this is a read->write transition, just ignore it and let 2592 * uvm_fault() take care of it later. 2593 */ 2594 return; 2595 } 2596 2597 PMAP_MAP_TO_HEAD_LOCK(); 2598 pmap_acquire_pmap_lock(pm); 2599 2600 /* 2601 * OK, at this point, we know we're doing write-protect operation. 2602 * If the pmap is active, write-back the range. 2603 */ 2604 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 2605 2606 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 2607 flags = 0; 2608 2609 while (sva < eva) { 2610 next_bucket = L2_NEXT_BUCKET(sva); 2611 if (next_bucket > eva) 2612 next_bucket = eva; 2613 2614 l2b = pmap_get_l2_bucket(pm, sva); 2615 if (l2b == NULL) { 2616 sva = next_bucket; 2617 continue; 2618 } 2619 2620 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2621 2622 while (sva < next_bucket) { 2623 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 2624 struct vm_page *pg; 2625 u_int f; 2626 2627 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 2628 pte &= ~L2_S_PROT_W; 2629 *ptep = pte; 2630 PTE_SYNC(ptep); 2631 2632 if (pg != NULL) { 2633 simple_lock(&pg->mdpage.pvh_slock); 2634 f = pmap_modify_pv(pg, pm, sva, 2635 PVF_WRITE, 0); 2636 pmap_vac_me_harder(pg, pm, sva); 2637 simple_unlock(&pg->mdpage.pvh_slock); 2638 } else 2639 f = PVF_REF | PVF_EXEC; 2640 2641 if (flush >= 0) { 2642 flush++; 2643 flags |= f; 2644 } else 2645 if (PV_BEEN_EXECD(f)) 2646 pmap_tlb_flushID_SE(pm, sva); 2647 else 2648 if (PV_BEEN_REFD(f)) 2649 pmap_tlb_flushD_SE(pm, sva); 2650 } 2651 2652 sva += PAGE_SIZE; 2653 ptep++; 2654 } 2655 } 2656 2657 pmap_release_pmap_lock(pm); 2658 PMAP_MAP_TO_HEAD_UNLOCK(); 2659 2660 if (flush) { 2661 if (PV_BEEN_EXECD(flags)) 2662 pmap_tlb_flushID(pm); 2663 else 2664 if (PV_BEEN_REFD(flags)) 2665 pmap_tlb_flushD(pm); 2666 } 2667 } 2668 2669 void 2670 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 2671 { 2672 2673 NPDEBUG(PDB_PROTECT, 2674 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 2675 pg, pg->phys_addr, prot)); 2676 2677 switch(prot) { 2678 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 2679 case VM_PROT_READ|VM_PROT_WRITE: 2680 return; 2681 2682 case VM_PROT_READ: 2683 case VM_PROT_READ|VM_PROT_EXECUTE: 2684 pmap_clearbit(pg, PVF_WRITE); 2685 break; 2686 2687 default: 2688 pmap_page_remove(pg); 2689 break; 2690 } 2691 } 2692 2693 /* 2694 * pmap_clear_modify: 2695 * 2696 * Clear the "modified" attribute for a page. 2697 */ 2698 boolean_t 2699 pmap_clear_modify(struct vm_page *pg) 2700 { 2701 boolean_t rv; 2702 2703 if (pg->mdpage.pvh_attrs & PVF_MOD) { 2704 rv = TRUE; 2705 pmap_clearbit(pg, PVF_MOD); 2706 } else 2707 rv = FALSE; 2708 2709 return (rv); 2710 } 2711 2712 /* 2713 * pmap_clear_reference: 2714 * 2715 * Clear the "referenced" attribute for a page. 2716 */ 2717 boolean_t 2718 pmap_clear_reference(struct vm_page *pg) 2719 { 2720 boolean_t rv; 2721 2722 if (pg->mdpage.pvh_attrs & PVF_REF) { 2723 rv = TRUE; 2724 pmap_clearbit(pg, PVF_REF); 2725 } else 2726 rv = FALSE; 2727 2728 return (rv); 2729 } 2730 2731 /* 2732 * pmap_is_modified: 2733 * 2734 * Test if a page has the "modified" attribute. 2735 */ 2736 /* See <arm/arm32/pmap.h> */ 2737 2738 /* 2739 * pmap_is_referenced: 2740 * 2741 * Test if a page has the "referenced" attribute. 2742 */ 2743 /* See <arm/arm32/pmap.h> */ 2744 2745 int 2746 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 2747 { 2748 struct l2_dtable *l2; 2749 struct l2_bucket *l2b; 2750 pd_entry_t *pl1pd, l1pd; 2751 pt_entry_t *ptep, pte; 2752 paddr_t pa; 2753 u_int l1idx; 2754 int rv = 0; 2755 2756 PMAP_MAP_TO_HEAD_LOCK(); 2757 pmap_acquire_pmap_lock(pm); 2758 2759 l1idx = L1_IDX(va); 2760 2761 /* 2762 * If there is no l2_dtable for this address, then the process 2763 * has no business accessing it. 2764 * 2765 * Note: This will catch userland processes trying to access 2766 * kernel addresses. 2767 */ 2768 l2 = pm->pm_l2[L2_IDX(l1idx)]; 2769 if (l2 == NULL) 2770 goto out; 2771 2772 /* 2773 * Likewise if there is no L2 descriptor table 2774 */ 2775 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2776 if (l2b->l2b_kva == NULL) 2777 goto out; 2778 2779 /* 2780 * Check the PTE itself. 2781 */ 2782 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2783 pte = *ptep; 2784 if (pte == 0) 2785 goto out; 2786 2787 /* 2788 * Catch a userland access to the vector page mapped at 0x0 2789 */ 2790 if (user && (pte & L2_S_PROT_U) == 0) 2791 goto out; 2792 2793 pa = l2pte_pa(pte); 2794 2795 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 2796 /* 2797 * This looks like a good candidate for "page modified" 2798 * emulation... 2799 */ 2800 struct pv_entry *pv; 2801 struct vm_page *pg; 2802 2803 /* Extract the physical address of the page */ 2804 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2805 goto out; 2806 2807 /* Get the current flags for this page. */ 2808 simple_lock(&pg->mdpage.pvh_slock); 2809 2810 pv = pmap_find_pv(pg, pm, va); 2811 if (pv == NULL) { 2812 simple_unlock(&pg->mdpage.pvh_slock); 2813 goto out; 2814 } 2815 2816 /* 2817 * Do the flags say this page is writable? If not then it 2818 * is a genuine write fault. If yes then the write fault is 2819 * our fault as we did not reflect the write access in the 2820 * PTE. Now we know a write has occurred we can correct this 2821 * and also set the modified bit 2822 */ 2823 if ((pv->pv_flags & PVF_WRITE) == 0) { 2824 simple_unlock(&pg->mdpage.pvh_slock); 2825 goto out; 2826 } 2827 2828 NPDEBUG(PDB_FOLLOW, 2829 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 2830 pm, va, pg->phys_addr)); 2831 2832 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 2833 pv->pv_flags |= PVF_REF | PVF_MOD; 2834 simple_unlock(&pg->mdpage.pvh_slock); 2835 2836 /* 2837 * Re-enable write permissions for the page. No need to call 2838 * pmap_vac_me_harder(), since this is just a 2839 * modified-emulation fault, and the PVF_WRITE bit isn't 2840 * changing. We've already set the cacheable bits based on 2841 * the assumption that we can write to this page. 2842 */ 2843 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 2844 PTE_SYNC(ptep); 2845 rv = 1; 2846 } else 2847 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2848 /* 2849 * This looks like a good candidate for "page referenced" 2850 * emulation. 2851 */ 2852 struct pv_entry *pv; 2853 struct vm_page *pg; 2854 2855 /* Extract the physical address of the page */ 2856 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2857 goto out; 2858 2859 /* Get the current flags for this page. */ 2860 simple_lock(&pg->mdpage.pvh_slock); 2861 2862 pv = pmap_find_pv(pg, pm, va); 2863 if (pv == NULL) { 2864 simple_unlock(&pg->mdpage.pvh_slock); 2865 goto out; 2866 } 2867 2868 pg->mdpage.pvh_attrs |= PVF_REF; 2869 pv->pv_flags |= PVF_REF; 2870 simple_unlock(&pg->mdpage.pvh_slock); 2871 2872 NPDEBUG(PDB_FOLLOW, 2873 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 2874 pm, va, pg->phys_addr)); 2875 2876 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2877 PTE_SYNC(ptep); 2878 rv = 1; 2879 } 2880 2881 /* 2882 * We know there is a valid mapping here, so simply 2883 * fix up the L1 if necessary. 2884 */ 2885 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2886 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2887 if (*pl1pd != l1pd) { 2888 *pl1pd = l1pd; 2889 PTE_SYNC(pl1pd); 2890 rv = 1; 2891 } 2892 2893 #ifdef CPU_SA110 2894 /* 2895 * There are bugs in the rev K SA110. This is a check for one 2896 * of them. 2897 */ 2898 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2899 curcpu()->ci_arm_cpurev < 3) { 2900 /* Always current pmap */ 2901 if (l2pte_valid(pte)) { 2902 extern int kernel_debug; 2903 if (kernel_debug & 1) { 2904 struct proc *p = curlwp->l_proc; 2905 printf("prefetch_abort: page is already " 2906 "mapped - pte=%p *pte=%08x\n", ptep, pte); 2907 printf("prefetch_abort: pc=%08lx proc=%p " 2908 "process=%s\n", va, p, p->p_comm); 2909 printf("prefetch_abort: far=%08x fs=%x\n", 2910 cpu_faultaddress(), cpu_faultstatus()); 2911 } 2912 #ifdef DDB 2913 if (kernel_debug & 2) 2914 Debugger(); 2915 #endif 2916 rv = 1; 2917 } 2918 } 2919 #endif /* CPU_SA110 */ 2920 2921 #ifdef DEBUG 2922 /* 2923 * If 'rv == 0' at this point, it generally indicates that there is a 2924 * stale TLB entry for the faulting address. This happens when two or 2925 * more processes are sharing an L1. Since we don't flush the TLB on 2926 * a context switch between such processes, we can take domain faults 2927 * for mappings which exist at the same VA in both processes. EVEN IF 2928 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2929 * example. 2930 * 2931 * This is extremely likely to happen if pmap_enter() updated the L1 2932 * entry for a recently entered mapping. In this case, the TLB is 2933 * flushed for the new mapping, but there may still be TLB entries for 2934 * other mappings belonging to other processes in the 1MB range 2935 * covered by the L1 entry. 2936 * 2937 * Since 'rv == 0', we know that the L1 already contains the correct 2938 * value, so the fault must be due to a stale TLB entry. 2939 * 2940 * Since we always need to flush the TLB anyway in the case where we 2941 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2942 * stale TLB entries dynamically. 2943 * 2944 * However, the above condition can ONLY happen if the current L1 is 2945 * being shared. If it happens when the L1 is unshared, it indicates 2946 * that other parts of the pmap are not doing their job WRT managing 2947 * the TLB. 2948 */ 2949 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2950 extern int last_fault_code; 2951 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2952 pm, va, ftype); 2953 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2954 l2, l2b, ptep, pl1pd); 2955 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2956 pte, l1pd, last_fault_code); 2957 #ifdef DDB 2958 Debugger(); 2959 #endif 2960 } 2961 #endif 2962 2963 cpu_tlb_flushID_SE(va); 2964 cpu_cpwait(); 2965 2966 rv = 1; 2967 2968 out: 2969 pmap_release_pmap_lock(pm); 2970 PMAP_MAP_TO_HEAD_UNLOCK(); 2971 2972 return (rv); 2973 } 2974 2975 /* 2976 * pmap_collect: free resources held by a pmap 2977 * 2978 * => optional function. 2979 * => called when a process is swapped out to free memory. 2980 */ 2981 void 2982 pmap_collect(pmap_t pm) 2983 { 2984 /* 2985 * Nothing to do. 2986 * We don't even need to free-up the process' L1. 2987 */ 2988 } 2989 2990 /* 2991 * Routine: pmap_procwr 2992 * 2993 * Function: 2994 * Synchronize caches corresponding to [addr, addr+len) in p. 2995 * 2996 */ 2997 void 2998 pmap_procwr(struct proc *p, vaddr_t va, int len) 2999 { 3000 /* We only need to do anything if it is the current process. */ 3001 if (p == curproc) 3002 cpu_icache_sync_range(va, len); 3003 } 3004 3005 /* 3006 * Routine: pmap_unwire 3007 * Function: Clear the wired attribute for a map/virtual-address pair. 3008 * 3009 * In/out conditions: 3010 * The mapping must already exist in the pmap. 3011 */ 3012 void 3013 pmap_unwire(pmap_t pm, vaddr_t va) 3014 { 3015 struct l2_bucket *l2b; 3016 pt_entry_t *ptep, pte; 3017 struct vm_page *pg; 3018 paddr_t pa; 3019 3020 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 3021 3022 PMAP_MAP_TO_HEAD_LOCK(); 3023 pmap_acquire_pmap_lock(pm); 3024 3025 l2b = pmap_get_l2_bucket(pm, va); 3026 KDASSERT(l2b != NULL); 3027 3028 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3029 pte = *ptep; 3030 3031 /* Extract the physical address of the page */ 3032 pa = l2pte_pa(pte); 3033 3034 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3035 /* Update the wired bit in the pv entry for this page. */ 3036 simple_lock(&pg->mdpage.pvh_slock); 3037 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 3038 simple_unlock(&pg->mdpage.pvh_slock); 3039 } 3040 3041 pmap_release_pmap_lock(pm); 3042 PMAP_MAP_TO_HEAD_UNLOCK(); 3043 } 3044 3045 void 3046 pmap_activate(struct lwp *l) 3047 { 3048 pmap_t pm; 3049 struct pcb *pcb; 3050 int s; 3051 3052 pm = l->l_proc->p_vmspace->vm_map.pmap; 3053 pcb = &l->l_addr->u_pcb; 3054 3055 pmap_set_pcb_pagedir(pm, pcb); 3056 3057 if (l == curlwp) { 3058 u_int cur_dacr, cur_ttb; 3059 3060 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 3061 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 3062 3063 cur_ttb &= ~(L1_TABLE_SIZE - 1); 3064 3065 if (cur_ttb == (u_int)pcb->pcb_pagedir && 3066 cur_dacr == pcb->pcb_dacr) { 3067 /* 3068 * No need to switch address spaces. 3069 */ 3070 return; 3071 } 3072 3073 s = splhigh(); 3074 pmap_acquire_pmap_lock(pm); 3075 disable_interrupts(I32_bit | F32_bit); 3076 3077 /* 3078 * We MUST, I repeat, MUST fix up the L1 entry corresponding 3079 * to 'vector_page' in the incoming L1 table before switching 3080 * to it otherwise subsequent interrupts/exceptions (including 3081 * domain faults!) will jump into hyperspace. 3082 */ 3083 if (pcb->pcb_pl1vec) { 3084 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 3085 /* 3086 * Don't need to PTE_SYNC() at this point since 3087 * cpu_setttb() is about to flush both the cache 3088 * and the TLB. 3089 */ 3090 } 3091 3092 cpu_domains(pcb->pcb_dacr); 3093 cpu_setttb(pcb->pcb_pagedir); 3094 3095 enable_interrupts(I32_bit | F32_bit); 3096 3097 /* 3098 * Flag any previous userland pmap as being NOT 3099 * resident in the cache/tlb. 3100 */ 3101 if (pmap_cache_state && pmap_cache_state != &pm->pm_cstate) 3102 pmap_cache_state->cs_all = 0; 3103 3104 /* 3105 * The new pmap, however, IS resident. 3106 */ 3107 pmap_cache_state = &pm->pm_cstate; 3108 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3109 pmap_release_pmap_lock(pm); 3110 splx(s); 3111 } 3112 } 3113 3114 void 3115 pmap_deactivate(struct lwp *l) 3116 { 3117 } 3118 3119 void 3120 pmap_update(pmap_t pm) 3121 { 3122 3123 if (pm->pm_remove_all) { 3124 /* 3125 * Finish up the pmap_remove_all() optimisation by flushing 3126 * the TLB. 3127 */ 3128 pmap_tlb_flushID(pm); 3129 pm->pm_remove_all = FALSE; 3130 } 3131 3132 if (pmap_is_current(pm)) { 3133 /* 3134 * If we're dealing with a current userland pmap, move its L1 3135 * to the end of the LRU. 3136 */ 3137 if (pm != pmap_kernel()) 3138 pmap_use_l1(pm); 3139 3140 /* 3141 * We can assume we're done with frobbing the cache/tlb for 3142 * now. Make sure any future pmap ops don't skip cache/tlb 3143 * flushes. 3144 */ 3145 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3146 } 3147 3148 /* 3149 * make sure TLB/cache operations have completed. 3150 */ 3151 cpu_cpwait(); 3152 } 3153 3154 void 3155 pmap_remove_all(pmap_t pm) 3156 { 3157 3158 /* 3159 * The vmspace described by this pmap is about to be torn down. 3160 * Until pmap_update() is called, UVM will only make calls 3161 * to pmap_remove(). We can make life much simpler by flushing 3162 * the cache now, and deferring TLB invalidation to pmap_update(). 3163 */ 3164 pmap_idcache_wbinv_all(pm); 3165 pm->pm_remove_all = TRUE; 3166 } 3167 3168 /* 3169 * Retire the given physical map from service. 3170 * Should only be called if the map contains no valid mappings. 3171 */ 3172 void 3173 pmap_destroy(pmap_t pm) 3174 { 3175 u_int count; 3176 3177 if (pm == NULL) 3178 return; 3179 3180 if (pm->pm_remove_all) { 3181 pmap_tlb_flushID(pm); 3182 pm->pm_remove_all = FALSE; 3183 } 3184 3185 /* 3186 * Drop reference count 3187 */ 3188 simple_lock(&pm->pm_lock); 3189 count = --pm->pm_obj.uo_refs; 3190 simple_unlock(&pm->pm_lock); 3191 if (count > 0) { 3192 if (pmap_is_current(pm)) { 3193 if (pm != pmap_kernel()) 3194 pmap_use_l1(pm); 3195 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3196 } 3197 return; 3198 } 3199 3200 /* 3201 * reference count is zero, free pmap resources and then free pmap. 3202 */ 3203 3204 if (vector_page < KERNEL_BASE) { 3205 struct pcb *pcb = &lwp0.l_addr->u_pcb; 3206 3207 if (pmap_is_current(pm)) { 3208 /* 3209 * Frob the L1 entry corresponding to the vector 3210 * page so that it contains the kernel pmap's domain 3211 * number. This will ensure pmap_remove() does not 3212 * pull the current vector page out from under us. 3213 */ 3214 disable_interrupts(I32_bit | F32_bit); 3215 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 3216 cpu_domains(pcb->pcb_dacr); 3217 cpu_setttb(pcb->pcb_pagedir); 3218 enable_interrupts(I32_bit | F32_bit); 3219 } 3220 3221 /* Remove the vector page mapping */ 3222 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 3223 pmap_update(pm); 3224 3225 /* 3226 * Make sure cpu_switch(), et al, DTRT. This is safe to do 3227 * since this process has no remaining mappings of its own. 3228 */ 3229 curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 3230 curpcb->pcb_l1vec = pcb->pcb_l1vec; 3231 curpcb->pcb_dacr = pcb->pcb_dacr; 3232 curpcb->pcb_pagedir = pcb->pcb_pagedir; 3233 } 3234 3235 LIST_REMOVE(pm, pm_list); 3236 3237 pmap_free_l1(pm); 3238 3239 /* return the pmap to the pool */ 3240 pool_cache_put(&pmap_pmap_cache, pm); 3241 } 3242 3243 3244 /* 3245 * void pmap_reference(pmap_t pm) 3246 * 3247 * Add a reference to the specified pmap. 3248 */ 3249 void 3250 pmap_reference(pmap_t pm) 3251 { 3252 3253 if (pm == NULL) 3254 return; 3255 3256 pmap_use_l1(pm); 3257 3258 simple_lock(&pm->pm_lock); 3259 pm->pm_obj.uo_refs++; 3260 simple_unlock(&pm->pm_lock); 3261 } 3262 3263 /* 3264 * pmap_zero_page() 3265 * 3266 * Zero a given physical page by mapping it at a page hook point. 3267 * In doing the zero page op, the page we zero is mapped cachable, as with 3268 * StrongARM accesses to non-cached pages are non-burst making writing 3269 * _any_ bulk data very slow. 3270 */ 3271 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3272 void 3273 pmap_zero_page_generic(paddr_t phys) 3274 { 3275 #ifdef DEBUG 3276 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3277 3278 if (pg->mdpage.pvh_list != NULL) 3279 panic("pmap_zero_page: page has mappings"); 3280 #endif 3281 3282 KDASSERT((phys & PGOFSET) == 0); 3283 3284 /* 3285 * Hook in the page, zero it, and purge the cache for that 3286 * zeroed page. Invalidate the TLB as needed. 3287 */ 3288 *cdst_pte = L2_S_PROTO | phys | 3289 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3290 PTE_SYNC(cdst_pte); 3291 cpu_tlb_flushD_SE(cdstp); 3292 cpu_cpwait(); 3293 bzero_page(cdstp); 3294 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3295 } 3296 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3297 3298 #if ARM_MMU_XSCALE == 1 3299 void 3300 pmap_zero_page_xscale(paddr_t phys) 3301 { 3302 #ifdef DEBUG 3303 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3304 3305 if (pg->mdpage.pvh_list != NULL) 3306 panic("pmap_zero_page: page has mappings"); 3307 #endif 3308 3309 KDASSERT((phys & PGOFSET) == 0); 3310 3311 /* 3312 * Hook in the page, zero it, and purge the cache for that 3313 * zeroed page. Invalidate the TLB as needed. 3314 */ 3315 *cdst_pte = L2_S_PROTO | phys | 3316 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3317 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3318 PTE_SYNC(cdst_pte); 3319 cpu_tlb_flushD_SE(cdstp); 3320 cpu_cpwait(); 3321 bzero_page(cdstp); 3322 xscale_cache_clean_minidata(); 3323 } 3324 #endif /* ARM_MMU_XSCALE == 1 */ 3325 3326 /* pmap_pageidlezero() 3327 * 3328 * The same as above, except that we assume that the page is not 3329 * mapped. This means we never have to flush the cache first. Called 3330 * from the idle loop. 3331 */ 3332 boolean_t 3333 pmap_pageidlezero(paddr_t phys) 3334 { 3335 unsigned int i; 3336 int *ptr; 3337 boolean_t rv = TRUE; 3338 #ifdef DEBUG 3339 struct vm_page *pg; 3340 3341 pg = PHYS_TO_VM_PAGE(phys); 3342 if (pg->mdpage.pvh_list != NULL) 3343 panic("pmap_pageidlezero: page has mappings"); 3344 #endif 3345 3346 KDASSERT((phys & PGOFSET) == 0); 3347 3348 /* 3349 * Hook in the page, zero it, and purge the cache for that 3350 * zeroed page. Invalidate the TLB as needed. 3351 */ 3352 *cdst_pte = L2_S_PROTO | phys | 3353 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3354 PTE_SYNC(cdst_pte); 3355 cpu_tlb_flushD_SE(cdstp); 3356 cpu_cpwait(); 3357 3358 for (i = 0, ptr = (int *)cdstp; 3359 i < (PAGE_SIZE / sizeof(int)); i++) { 3360 if (sched_whichqs != 0) { 3361 /* 3362 * A process has become ready. Abort now, 3363 * so we don't keep it waiting while we 3364 * do slow memory access to finish this 3365 * page. 3366 */ 3367 rv = FALSE; 3368 break; 3369 } 3370 *ptr++ = 0; 3371 } 3372 3373 if (rv) 3374 /* 3375 * if we aborted we'll rezero this page again later so don't 3376 * purge it unless we finished it 3377 */ 3378 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3379 3380 return (rv); 3381 } 3382 3383 /* 3384 * pmap_copy_page() 3385 * 3386 * Copy one physical page into another, by mapping the pages into 3387 * hook points. The same comment regarding cachability as in 3388 * pmap_zero_page also applies here. 3389 */ 3390 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3391 void 3392 pmap_copy_page_generic(paddr_t src, paddr_t dst) 3393 { 3394 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 3395 #ifdef DEBUG 3396 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 3397 3398 if (dst_pg->mdpage.pvh_list != NULL) 3399 panic("pmap_copy_page: dst page has mappings"); 3400 #endif 3401 3402 KDASSERT((src & PGOFSET) == 0); 3403 KDASSERT((dst & PGOFSET) == 0); 3404 3405 /* 3406 * Clean the source page. Hold the source page's lock for 3407 * the duration of the copy so that no other mappings can 3408 * be created while we have a potentially aliased mapping. 3409 */ 3410 simple_lock(&src_pg->mdpage.pvh_slock); 3411 (void) pmap_clean_page(src_pg->mdpage.pvh_list, TRUE); 3412 3413 /* 3414 * Map the pages into the page hook points, copy them, and purge 3415 * the cache for the appropriate page. Invalidate the TLB 3416 * as required. 3417 */ 3418 *csrc_pte = L2_S_PROTO | src | 3419 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 3420 PTE_SYNC(csrc_pte); 3421 *cdst_pte = L2_S_PROTO | dst | 3422 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3423 PTE_SYNC(cdst_pte); 3424 cpu_tlb_flushD_SE(csrcp); 3425 cpu_tlb_flushD_SE(cdstp); 3426 cpu_cpwait(); 3427 bcopy_page(csrcp, cdstp); 3428 cpu_dcache_inv_range(csrcp, PAGE_SIZE); 3429 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 3430 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3431 } 3432 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3433 3434 #if ARM_MMU_XSCALE == 1 3435 void 3436 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 3437 { 3438 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 3439 #ifdef DEBUG 3440 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 3441 3442 if (dst_pg->mdpage.pvh_list != NULL) 3443 panic("pmap_copy_page: dst page has mappings"); 3444 #endif 3445 3446 KDASSERT((src & PGOFSET) == 0); 3447 KDASSERT((dst & PGOFSET) == 0); 3448 3449 /* 3450 * Clean the source page. Hold the source page's lock for 3451 * the duration of the copy so that no other mappings can 3452 * be created while we have a potentially aliased mapping. 3453 */ 3454 simple_lock(&src_pg->mdpage.pvh_slock); 3455 (void) pmap_clean_page(src_pg->mdpage.pvh_list, TRUE); 3456 3457 /* 3458 * Map the pages into the page hook points, copy them, and purge 3459 * the cache for the appropriate page. Invalidate the TLB 3460 * as required. 3461 */ 3462 *csrc_pte = L2_S_PROTO | src | 3463 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 3464 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3465 PTE_SYNC(csrc_pte); 3466 *cdst_pte = L2_S_PROTO | dst | 3467 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3468 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3469 PTE_SYNC(cdst_pte); 3470 cpu_tlb_flushD_SE(csrcp); 3471 cpu_tlb_flushD_SE(cdstp); 3472 cpu_cpwait(); 3473 bcopy_page(csrcp, cdstp); 3474 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 3475 xscale_cache_clean_minidata(); 3476 } 3477 #endif /* ARM_MMU_XSCALE == 1 */ 3478 3479 /* 3480 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 3481 * 3482 * Return the start and end addresses of the kernel's virtual space. 3483 * These values are setup in pmap_bootstrap and are updated as pages 3484 * are allocated. 3485 */ 3486 void 3487 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 3488 { 3489 *start = virtual_avail; 3490 *end = virtual_end; 3491 } 3492 3493 /* 3494 * Helper function for pmap_grow_l2_bucket() 3495 */ 3496 static __inline int 3497 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 3498 { 3499 struct l2_bucket *l2b; 3500 pt_entry_t *ptep; 3501 paddr_t pa; 3502 3503 if (uvm.page_init_done == FALSE) { 3504 if (uvm_page_physget(&pa) == FALSE) 3505 return (1); 3506 } else { 3507 struct vm_page *pg; 3508 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 3509 if (pg == NULL) 3510 return (1); 3511 pa = VM_PAGE_TO_PHYS(pg); 3512 } 3513 3514 if (pap) 3515 *pap = pa; 3516 3517 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3518 KDASSERT(l2b != NULL); 3519 3520 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3521 *ptep = L2_S_PROTO | pa | cache_mode | 3522 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 3523 PTE_SYNC(ptep); 3524 memset((void *)va, 0, PAGE_SIZE); 3525 return (0); 3526 } 3527 3528 /* 3529 * This is the same as pmap_alloc_l2_bucket(), except that it is only 3530 * used by pmap_growkernel(). 3531 */ 3532 static __inline struct l2_bucket * 3533 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 3534 { 3535 struct l2_dtable *l2; 3536 struct l2_bucket *l2b; 3537 u_short l1idx; 3538 vaddr_t nva; 3539 3540 l1idx = L1_IDX(va); 3541 3542 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 3543 /* 3544 * No mapping at this address, as there is 3545 * no entry in the L1 table. 3546 * Need to allocate a new l2_dtable. 3547 */ 3548 nva = pmap_kernel_l2dtable_kva; 3549 if ((nva & PGOFSET) == 0) { 3550 /* 3551 * Need to allocate a backing page 3552 */ 3553 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 3554 return (NULL); 3555 } 3556 3557 l2 = (struct l2_dtable *)nva; 3558 nva += sizeof(struct l2_dtable); 3559 3560 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 3561 /* 3562 * The new l2_dtable straddles a page boundary. 3563 * Map in another page to cover it. 3564 */ 3565 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 3566 return (NULL); 3567 } 3568 3569 pmap_kernel_l2dtable_kva = nva; 3570 3571 /* 3572 * Link it into the parent pmap 3573 */ 3574 pm->pm_l2[L2_IDX(l1idx)] = l2; 3575 } 3576 3577 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3578 3579 /* 3580 * Fetch pointer to the L2 page table associated with the address. 3581 */ 3582 if (l2b->l2b_kva == NULL) { 3583 pt_entry_t *ptep; 3584 3585 /* 3586 * No L2 page table has been allocated. Chances are, this 3587 * is because we just allocated the l2_dtable, above. 3588 */ 3589 nva = pmap_kernel_l2ptp_kva; 3590 ptep = (pt_entry_t *)nva; 3591 if ((nva & PGOFSET) == 0) { 3592 /* 3593 * Need to allocate a backing page 3594 */ 3595 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 3596 &pmap_kernel_l2ptp_phys)) 3597 return (NULL); 3598 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 3599 } 3600 3601 l2->l2_occupancy++; 3602 l2b->l2b_kva = ptep; 3603 l2b->l2b_l1idx = l1idx; 3604 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 3605 3606 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 3607 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 3608 } 3609 3610 return (l2b); 3611 } 3612 3613 vaddr_t 3614 pmap_growkernel(vaddr_t maxkvaddr) 3615 { 3616 pmap_t kpm = pmap_kernel(); 3617 struct l1_ttable *l1; 3618 struct l2_bucket *l2b; 3619 pd_entry_t *pl1pd; 3620 int s; 3621 3622 if (maxkvaddr <= pmap_curmaxkvaddr) 3623 goto out; /* we are OK */ 3624 3625 NPDEBUG(PDB_GROWKERN, 3626 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 3627 pmap_curmaxkvaddr, maxkvaddr)); 3628 3629 KDASSERT(maxkvaddr <= virtual_end); 3630 3631 /* 3632 * whoops! we need to add kernel PTPs 3633 */ 3634 3635 s = splhigh(); /* to be safe */ 3636 simple_lock(&kpm->pm_lock); 3637 3638 /* Map 1MB at a time */ 3639 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 3640 3641 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 3642 KDASSERT(l2b != NULL); 3643 3644 /* Distribute new L1 entry to all other L1s */ 3645 SLIST_FOREACH(l1, &l1_list, l1_link) { 3646 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 3647 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 3648 L1_C_PROTO; 3649 PTE_SYNC(pl1pd); 3650 } 3651 } 3652 3653 /* 3654 * flush out the cache, expensive but growkernel will happen so 3655 * rarely 3656 */ 3657 cpu_dcache_wbinv_all(); 3658 cpu_tlb_flushD(); 3659 cpu_cpwait(); 3660 3661 simple_unlock(&kpm->pm_lock); 3662 splx(s); 3663 3664 out: 3665 return (pmap_curmaxkvaddr); 3666 } 3667 3668 /************************ Utility routines ****************************/ 3669 3670 /* 3671 * vector_page_setprot: 3672 * 3673 * Manipulate the protection of the vector page. 3674 */ 3675 void 3676 vector_page_setprot(int prot) 3677 { 3678 struct l2_bucket *l2b; 3679 pt_entry_t *ptep; 3680 3681 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 3682 KDASSERT(l2b != NULL); 3683 3684 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 3685 3686 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 3687 PTE_SYNC(ptep); 3688 cpu_tlb_flushD_SE(vector_page); 3689 cpu_cpwait(); 3690 } 3691 3692 /* 3693 * This is used to stuff certain critical values into the PCB where they 3694 * can be accessed quickly from cpu_switch() et al. 3695 */ 3696 void 3697 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 3698 { 3699 struct l2_bucket *l2b; 3700 3701 KDASSERT(pm->pm_l1); 3702 3703 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 3704 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3705 (DOMAIN_CLIENT << (pm->pm_domain * 2)); 3706 pcb->pcb_cstate = (void *)&pm->pm_cstate; 3707 3708 if (vector_page < KERNEL_BASE) { 3709 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 3710 l2b = pmap_get_l2_bucket(pm, vector_page); 3711 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 3712 L1_C_DOM(pm->pm_domain); 3713 } else 3714 pcb->pcb_pl1vec = NULL; 3715 } 3716 3717 /* 3718 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3719 * Returns TRUE if the mapping exists, else FALSE. 3720 * 3721 * NOTE: This function is only used by a couple of arm-specific modules. 3722 * It is not safe to take any pmap locks here, since we could be right 3723 * in the middle of debugging the pmap anyway... 3724 * 3725 * It is possible for this routine to return FALSE even though a valid 3726 * mapping does exist. This is because we don't lock, so the metadata 3727 * state may be inconsistent. 3728 * 3729 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3730 * a "section" mapping. 3731 */ 3732 boolean_t 3733 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3734 { 3735 struct l2_dtable *l2; 3736 pd_entry_t *pl1pd, l1pd; 3737 pt_entry_t *ptep; 3738 u_short l1idx; 3739 3740 if (pm->pm_l1 == NULL) 3741 return (FALSE); 3742 3743 l1idx = L1_IDX(va); 3744 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3745 l1pd = *pl1pd; 3746 3747 if (l1pte_section_p(l1pd)) { 3748 *ptp = NULL; 3749 return (TRUE); 3750 } 3751 3752 if (pm->pm_l2 == NULL) 3753 return (FALSE); 3754 3755 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3756 3757 if (l2 == NULL || 3758 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3759 return (FALSE); 3760 } 3761 3762 *ptp = &ptep[l2pte_index(va)]; 3763 return (TRUE); 3764 } 3765 3766 boolean_t 3767 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 3768 { 3769 u_short l1idx; 3770 3771 if (pm->pm_l1 == NULL) 3772 return (FALSE); 3773 3774 l1idx = L1_IDX(va); 3775 *pdp = &pm->pm_l1->l1_kva[l1idx]; 3776 3777 return (TRUE); 3778 } 3779 3780 /************************ Bootstrapping routines ****************************/ 3781 3782 static void 3783 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 3784 { 3785 int i; 3786 3787 l1->l1_kva = l1pt; 3788 l1->l1_domain_use_count = 0; 3789 l1->l1_domain_first = 0; 3790 3791 for (i = 0; i < PMAP_DOMAINS; i++) 3792 l1->l1_domain_free[i] = i + 1; 3793 3794 /* 3795 * Copy the kernel's L1 entries to each new L1. 3796 */ 3797 if (pmap_initialized) 3798 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 3799 3800 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 3801 &l1->l1_physaddr) == FALSE) 3802 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 3803 3804 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 3805 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 3806 } 3807 3808 /* 3809 * pmap_bootstrap() is called from the board-specific initarm() routine 3810 * once the kernel L1/L2 descriptors tables have been set up. 3811 * 3812 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 3813 * spread over a number of disparate files/functions. 3814 * 3815 * We are passed the following parameters 3816 * - kernel_l1pt 3817 * This is a pointer to the base of the kernel's L1 translation table. 3818 * - vstart 3819 * 1MB-aligned start of managed kernel virtual memory. 3820 * - vend 3821 * 1MB-aligned end of managed kernel virtual memory. 3822 * 3823 * We use the first parameter to build the metadata (struct l1_ttable and 3824 * struct l2_dtable) necessary to track kernel mappings. 3825 */ 3826 #define PMAP_STATIC_L2_SIZE 16 3827 void 3828 pmap_bootstrap(pd_entry_t *kernel_l1pt, vaddr_t vstart, vaddr_t vend) 3829 { 3830 static struct l1_ttable static_l1; 3831 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 3832 struct l1_ttable *l1 = &static_l1; 3833 struct l2_dtable *l2; 3834 struct l2_bucket *l2b; 3835 pmap_t pm = pmap_kernel(); 3836 pd_entry_t pde; 3837 pt_entry_t *ptep; 3838 paddr_t pa; 3839 vaddr_t va; 3840 vsize_t size; 3841 int l1idx, l2idx, l2next = 0; 3842 3843 /* 3844 * Initialise the kernel pmap object 3845 */ 3846 pm->pm_l1 = l1; 3847 pm->pm_domain = PMAP_DOMAIN_KERNEL; 3848 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3849 simple_lock_init(&pm->pm_lock); 3850 pm->pm_obj.pgops = NULL; 3851 TAILQ_INIT(&pm->pm_obj.memq); 3852 pm->pm_obj.uo_npages = 0; 3853 pm->pm_obj.uo_refs = 1; 3854 3855 /* 3856 * Scan the L1 translation table created by initarm() and create 3857 * the required metadata for all valid mappings found in it. 3858 */ 3859 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 3860 pde = kernel_l1pt[l1idx]; 3861 3862 /* 3863 * We're only interested in Coarse mappings. 3864 * pmap_extract() can deal with section mappings without 3865 * recourse to checking L2 metadata. 3866 */ 3867 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 3868 continue; 3869 3870 /* 3871 * Lookup the KVA of this L2 descriptor table 3872 */ 3873 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 3874 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 3875 if (ptep == NULL) { 3876 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 3877 (u_int)l1idx << L1_S_SHIFT, pa); 3878 } 3879 3880 /* 3881 * Fetch the associated L2 metadata structure. 3882 * Allocate a new one if necessary. 3883 */ 3884 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 3885 if (l2next == PMAP_STATIC_L2_SIZE) 3886 panic("pmap_bootstrap: out of static L2s"); 3887 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 3888 } 3889 3890 /* 3891 * One more L1 slot tracked... 3892 */ 3893 l2->l2_occupancy++; 3894 3895 /* 3896 * Fill in the details of the L2 descriptor in the 3897 * appropriate bucket. 3898 */ 3899 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3900 l2b->l2b_kva = ptep; 3901 l2b->l2b_phys = pa; 3902 l2b->l2b_l1idx = l1idx; 3903 3904 /* 3905 * Establish an initial occupancy count for this descriptor 3906 */ 3907 for (l2idx = 0; 3908 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 3909 l2idx++) { 3910 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 3911 l2b->l2b_occupancy++; 3912 } 3913 } 3914 3915 /* 3916 * Make sure the descriptor itself has the correct cache mode. 3917 * If not, fix it, but whine about the problem. Port-meisters 3918 * should consider this a clue to fix up their initarm() 3919 * function. :) 3920 */ 3921 if (pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)ptep)) { 3922 printf("pmap_bootstrap: WARNING! wrong cache mode for " 3923 "L2 pte @ %p\n", ptep); 3924 } 3925 } 3926 3927 /* 3928 * Ensure the primary (kernel) L1 has the correct cache mode for 3929 * a page table. Bitch if it is not correctly set. 3930 */ 3931 for (va = (vaddr_t)kernel_l1pt; 3932 va < ((vaddr_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 3933 if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 3934 printf("pmap_bootstrap: WARNING! wrong cache mode for " 3935 "primary L1 @ 0x%lx\n", va); 3936 } 3937 3938 cpu_dcache_wbinv_all(); 3939 cpu_tlb_flushID(); 3940 cpu_cpwait(); 3941 3942 /* 3943 * now we allocate the "special" VAs which are used for tmp mappings 3944 * by the pmap (and other modules). we allocate the VAs by advancing 3945 * virtual_avail (note that there are no pages mapped at these VAs). 3946 * 3947 * Managed KVM space start from wherever initarm() tells us. 3948 */ 3949 virtual_avail = vstart; 3950 virtual_end = vend; 3951 3952 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 3953 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)csrc_pte); 3954 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 3955 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)cdst_pte); 3956 pmap_alloc_specials(&virtual_avail, 1, (void *)&memhook, NULL); 3957 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 3958 (void *)&msgbufaddr, NULL); 3959 3960 /* 3961 * Allocate a range of kernel virtual address space to be used 3962 * for L2 descriptor tables and metadata allocation in 3963 * pmap_growkernel(). 3964 */ 3965 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 3966 pmap_alloc_specials(&virtual_avail, 3967 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 3968 &pmap_kernel_l2ptp_kva, NULL); 3969 3970 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 3971 pmap_alloc_specials(&virtual_avail, 3972 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 3973 &pmap_kernel_l2dtable_kva, NULL); 3974 3975 /* 3976 * init the static-global locks and global pmap list. 3977 */ 3978 #if defined(MULTIPROCESSOR) || defined(LOCKDEBUG) 3979 spinlockinit(&pmap_main_lock, "pmaplk", 0); 3980 #endif 3981 3982 /* 3983 * We can now initialise the first L1's metadata. 3984 */ 3985 SLIST_INIT(&l1_list); 3986 TAILQ_INIT(&l1_lru_list); 3987 simple_lock_init(&l1_lru_lock); 3988 pmap_init_l1(l1, kernel_l1pt); 3989 3990 /* 3991 * Initialize the pmap pool and cache 3992 */ 3993 pool_init(&pmap_pmap_pool, sizeof(struct pmap), 0, 0, 0, "pmappl", 3994 &pool_allocator_nointr); 3995 pool_cache_init(&pmap_pmap_cache, &pmap_pmap_pool, 3996 pmap_pmap_ctor, NULL, NULL); 3997 LIST_INIT(&pmap_pmaps); 3998 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3999 4000 /* 4001 * Initialize the pv pool. 4002 */ 4003 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 4004 &pmap_bootstrap_pv_allocator); 4005 4006 /* 4007 * Initialize the L2 dtable pool and cache. 4008 */ 4009 pool_init(&pmap_l2dtable_pool, sizeof(struct l2_dtable), 0, 0, 0, 4010 "l2dtblpl", NULL); 4011 pool_cache_init(&pmap_l2dtable_cache, &pmap_l2dtable_pool, 4012 pmap_l2dtable_ctor, NULL, NULL); 4013 4014 /* 4015 * Initialise the L2 descriptor table pool and cache 4016 */ 4017 pool_init(&pmap_l2ptp_pool, L2_TABLE_SIZE_REAL, 0, L2_TABLE_SIZE_REAL, 4018 0, "l2ptppl", NULL); 4019 pool_cache_init(&pmap_l2ptp_cache, &pmap_l2ptp_pool, 4020 pmap_l2ptp_ctor, NULL, NULL); 4021 4022 cpu_dcache_wbinv_all(); 4023 } 4024 4025 static int 4026 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 4027 { 4028 pd_entry_t *pdep, pde; 4029 pt_entry_t *ptep, pte; 4030 vaddr_t pa; 4031 int rv = 0; 4032 4033 /* 4034 * Make sure the descriptor itself has the correct cache mode 4035 */ 4036 pdep = &kl1[L1_IDX(va)]; 4037 pde = *pdep; 4038 4039 if (l1pte_section_p(pde)) { 4040 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 4041 *pdep = (pde & ~L1_S_CACHE_MASK) | 4042 pte_l1_s_cache_mode_pt; 4043 PTE_SYNC(pdep); 4044 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 4045 rv = 1; 4046 } 4047 } else { 4048 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 4049 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 4050 if (ptep == NULL) 4051 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 4052 4053 ptep = &ptep[l2pte_index(va)]; 4054 pte = *ptep; 4055 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 4056 *ptep = (pte & ~L2_S_CACHE_MASK) | 4057 pte_l2_s_cache_mode_pt; 4058 PTE_SYNC(ptep); 4059 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 4060 rv = 1; 4061 } 4062 } 4063 4064 return (rv); 4065 } 4066 4067 static void 4068 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 4069 { 4070 vaddr_t va = *availp; 4071 struct l2_bucket *l2b; 4072 4073 if (ptep) { 4074 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4075 if (l2b == NULL) 4076 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 4077 4078 if (ptep) 4079 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 4080 } 4081 4082 *vap = va; 4083 *availp = va + (PAGE_SIZE * pages); 4084 } 4085 4086 void 4087 pmap_init(void) 4088 { 4089 extern int physmem; 4090 4091 /* 4092 * Set the available memory vars - These do not map to real memory 4093 * addresses and cannot as the physical memory is fragmented. 4094 * They are used by ps for %mem calculations. 4095 * One could argue whether this should be the entire memory or just 4096 * the memory that is useable in a user process. 4097 */ 4098 avail_start = 0; 4099 avail_end = physmem * PAGE_SIZE; 4100 4101 /* 4102 * Now we need to free enough pv_entry structures to allow us to get 4103 * the kmem_map/kmem_object allocated and inited (done after this 4104 * function is finished). to do this we allocate one bootstrap page out 4105 * of kernel_map and use it to provide an initial pool of pv_entry 4106 * structures. we never free this page. 4107 */ 4108 pool_setlowat(&pmap_pv_pool, 4109 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 4110 4111 pmap_initialized = TRUE; 4112 } 4113 4114 static vaddr_t last_bootstrap_page = 0; 4115 static void *free_bootstrap_pages = NULL; 4116 4117 static void * 4118 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 4119 { 4120 extern void *pool_page_alloc(struct pool *, int); 4121 vaddr_t new_page; 4122 void *rv; 4123 4124 if (pmap_initialized) 4125 return (pool_page_alloc(pp, flags)); 4126 4127 if (free_bootstrap_pages) { 4128 rv = free_bootstrap_pages; 4129 free_bootstrap_pages = *((void **)rv); 4130 return (rv); 4131 } 4132 4133 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 4134 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 4135 4136 KASSERT(new_page > last_bootstrap_page); 4137 last_bootstrap_page = new_page; 4138 return ((void *)new_page); 4139 } 4140 4141 static void 4142 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 4143 { 4144 extern void pool_page_free(struct pool *, void *); 4145 4146 if ((vaddr_t)v <= last_bootstrap_page) { 4147 *((void **)v) = free_bootstrap_pages; 4148 free_bootstrap_pages = v; 4149 return; 4150 } 4151 4152 if (pmap_initialized) { 4153 pool_page_free(pp, v); 4154 return; 4155 } 4156 } 4157 4158 /* 4159 * pmap_postinit() 4160 * 4161 * This routine is called after the vm and kmem subsystems have been 4162 * initialised. This allows the pmap code to perform any initialisation 4163 * that can only be done one the memory allocation is in place. 4164 */ 4165 void 4166 pmap_postinit(void) 4167 { 4168 extern paddr_t physical_start, physical_end; 4169 struct l2_bucket *l2b; 4170 struct l1_ttable *l1; 4171 struct pglist plist; 4172 struct vm_page *m; 4173 pd_entry_t *pl1pt; 4174 pt_entry_t *ptep, pte; 4175 vaddr_t va, eva; 4176 u_int loop, needed; 4177 int error; 4178 4179 pool_setlowat(&pmap_l2ptp_pool, 4180 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 4181 pool_setlowat(&pmap_l2dtable_pool, 4182 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 4183 4184 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 4185 needed -= 1; 4186 4187 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 4188 4189 for (loop = 0; loop < needed; loop++, l1++) { 4190 /* Allocate a L1 page table */ 4191 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 4192 if (va == 0) 4193 panic("Cannot allocate L1 KVM"); 4194 4195 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 4196 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 4197 if (error) 4198 panic("Cannot allocate L1 physical pages"); 4199 4200 m = TAILQ_FIRST(&plist); 4201 eva = va + L1_TABLE_SIZE; 4202 pl1pt = (pd_entry_t *)va; 4203 4204 while (m && va < eva) { 4205 paddr_t pa = VM_PAGE_TO_PHYS(m); 4206 4207 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 4208 4209 /* 4210 * Make sure the L1 descriptor table is mapped 4211 * with the cache-mode set to write-through. 4212 */ 4213 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4214 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4215 pte = *ptep; 4216 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 4217 *ptep = pte; 4218 PTE_SYNC(ptep); 4219 cpu_tlb_flushD_SE(va); 4220 4221 va += PAGE_SIZE; 4222 m = TAILQ_NEXT(m, pageq); 4223 } 4224 4225 #ifdef DIAGNOSTIC 4226 if (m) 4227 panic("pmap_alloc_l1pt: pglist not empty"); 4228 #endif /* DIAGNOSTIC */ 4229 4230 pmap_init_l1(l1, pl1pt); 4231 } 4232 4233 #ifdef DEBUG 4234 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 4235 needed); 4236 #endif 4237 } 4238 4239 /* 4240 * Note that the following routines are used by board-specific initialisation 4241 * code to configure the initial kernel page tables. 4242 * 4243 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 4244 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 4245 * behaviour of the old pmap, and provides an easy migration path for 4246 * initial bring-up of the new pmap on existing ports. Fortunately, 4247 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 4248 * will be deprecated. 4249 * 4250 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 4251 * tables. 4252 */ 4253 4254 /* 4255 * This list exists for the benefit of pmap_map_chunk(). It keeps track 4256 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 4257 * find them as necessary. 4258 * 4259 * Note that the data on this list MUST remain valid after initarm() returns, 4260 * as pmap_bootstrap() uses it to contruct L2 table metadata. 4261 */ 4262 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 4263 4264 static vaddr_t 4265 kernel_pt_lookup(paddr_t pa) 4266 { 4267 pv_addr_t *pv; 4268 4269 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 4270 #ifndef ARM32_NEW_VM_LAYOUT 4271 if (pv->pv_pa == (pa & ~PGOFSET)) 4272 return (pv->pv_va | (pa & PGOFSET)); 4273 #else 4274 if (pv->pv_pa == pa) 4275 return (pv->pv_va); 4276 #endif 4277 } 4278 return (0); 4279 } 4280 4281 /* 4282 * pmap_map_section: 4283 * 4284 * Create a single section mapping. 4285 */ 4286 void 4287 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 4288 { 4289 pd_entry_t *pde = (pd_entry_t *) l1pt; 4290 pd_entry_t fl; 4291 4292 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 4293 4294 switch (cache) { 4295 case PTE_NOCACHE: 4296 default: 4297 fl = 0; 4298 break; 4299 4300 case PTE_CACHE: 4301 fl = pte_l1_s_cache_mode; 4302 break; 4303 4304 case PTE_PAGETABLE: 4305 fl = pte_l1_s_cache_mode_pt; 4306 break; 4307 } 4308 4309 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4310 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4311 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4312 } 4313 4314 /* 4315 * pmap_map_entry: 4316 * 4317 * Create a single page mapping. 4318 */ 4319 void 4320 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 4321 { 4322 pd_entry_t *pde = (pd_entry_t *) l1pt; 4323 pt_entry_t fl; 4324 pt_entry_t *pte; 4325 4326 KASSERT(((va | pa) & PGOFSET) == 0); 4327 4328 switch (cache) { 4329 case PTE_NOCACHE: 4330 default: 4331 fl = 0; 4332 break; 4333 4334 case PTE_CACHE: 4335 fl = pte_l2_s_cache_mode; 4336 break; 4337 4338 case PTE_PAGETABLE: 4339 fl = pte_l2_s_cache_mode_pt; 4340 break; 4341 } 4342 4343 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4344 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 4345 4346 #ifndef ARM32_NEW_VM_LAYOUT 4347 pte = (pt_entry_t *) 4348 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4349 #else 4350 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4351 #endif 4352 if (pte == NULL) 4353 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 4354 4355 #ifndef ARM32_NEW_VM_LAYOUT 4356 pte[(va >> PGSHIFT) & 0x3ff] = 4357 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4358 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 4359 #else 4360 pte[l2pte_index(va)] = 4361 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4362 PTE_SYNC(&pte[l2pte_index(va)]); 4363 #endif 4364 } 4365 4366 /* 4367 * pmap_link_l2pt: 4368 * 4369 * Link the L2 page table specified by "l2pv" into the L1 4370 * page table at the slot for "va". 4371 */ 4372 void 4373 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 4374 { 4375 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4376 u_int slot = va >> L1_S_SHIFT; 4377 4378 #ifndef ARM32_NEW_VM_LAYOUT 4379 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 4380 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 4381 #endif 4382 4383 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4384 4385 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4386 #ifdef ARM32_NEW_VM_LAYOUT 4387 PTE_SYNC(&pde[slot]); 4388 #else 4389 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 4390 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 4391 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 4392 PTE_SYNC_RANGE(&pde[slot + 0], 4); 4393 #endif 4394 4395 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4396 } 4397 4398 /* 4399 * pmap_map_chunk: 4400 * 4401 * Map a chunk of memory using the most efficient mappings 4402 * possible (section, large page, small page) into the 4403 * provided L1 and L2 tables at the specified virtual address. 4404 */ 4405 vsize_t 4406 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 4407 int prot, int cache) 4408 { 4409 pd_entry_t *pde = (pd_entry_t *) l1pt; 4410 pt_entry_t *pte, f1, f2s, f2l; 4411 vsize_t resid; 4412 int i; 4413 4414 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4415 4416 if (l1pt == 0) 4417 panic("pmap_map_chunk: no L1 table provided"); 4418 4419 #ifdef VERBOSE_INIT_ARM 4420 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 4421 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4422 #endif 4423 4424 switch (cache) { 4425 case PTE_NOCACHE: 4426 default: 4427 f1 = 0; 4428 f2l = 0; 4429 f2s = 0; 4430 break; 4431 4432 case PTE_CACHE: 4433 f1 = pte_l1_s_cache_mode; 4434 f2l = pte_l2_l_cache_mode; 4435 f2s = pte_l2_s_cache_mode; 4436 break; 4437 4438 case PTE_PAGETABLE: 4439 f1 = pte_l1_s_cache_mode_pt; 4440 f2l = pte_l2_l_cache_mode_pt; 4441 f2s = pte_l2_s_cache_mode_pt; 4442 break; 4443 } 4444 4445 size = resid; 4446 4447 while (resid > 0) { 4448 /* See if we can use a section mapping. */ 4449 if (L1_S_MAPPABLE_P(va, pa, resid)) { 4450 #ifdef VERBOSE_INIT_ARM 4451 printf("S"); 4452 #endif 4453 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4454 L1_S_PROT(PTE_KERNEL, prot) | f1 | 4455 L1_S_DOM(PMAP_DOMAIN_KERNEL); 4456 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4457 va += L1_S_SIZE; 4458 pa += L1_S_SIZE; 4459 resid -= L1_S_SIZE; 4460 continue; 4461 } 4462 4463 /* 4464 * Ok, we're going to use an L2 table. Make sure 4465 * one is actually in the corresponding L1 slot 4466 * for the current VA. 4467 */ 4468 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4469 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 4470 4471 #ifndef ARM32_NEW_VM_LAYOUT 4472 pte = (pt_entry_t *) 4473 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4474 #else 4475 pte = (pt_entry_t *) kernel_pt_lookup( 4476 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4477 #endif 4478 if (pte == NULL) 4479 panic("pmap_map_chunk: can't find L2 table for VA" 4480 "0x%08lx", va); 4481 4482 /* See if we can use a L2 large page mapping. */ 4483 if (L2_L_MAPPABLE_P(va, pa, resid)) { 4484 #ifdef VERBOSE_INIT_ARM 4485 printf("L"); 4486 #endif 4487 for (i = 0; i < 16; i++) { 4488 #ifndef ARM32_NEW_VM_LAYOUT 4489 pte[((va >> PGSHIFT) & 0x3f0) + i] = 4490 L2_L_PROTO | pa | 4491 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4492 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 4493 #else 4494 pte[l2pte_index(va) + i] = 4495 L2_L_PROTO | pa | 4496 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4497 PTE_SYNC(&pte[l2pte_index(va) + i]); 4498 #endif 4499 } 4500 va += L2_L_SIZE; 4501 pa += L2_L_SIZE; 4502 resid -= L2_L_SIZE; 4503 continue; 4504 } 4505 4506 /* Use a small page mapping. */ 4507 #ifdef VERBOSE_INIT_ARM 4508 printf("P"); 4509 #endif 4510 #ifndef ARM32_NEW_VM_LAYOUT 4511 pte[(va >> PGSHIFT) & 0x3ff] = 4512 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4513 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 4514 #else 4515 pte[l2pte_index(va)] = 4516 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4517 PTE_SYNC(&pte[l2pte_index(va)]); 4518 #endif 4519 va += PAGE_SIZE; 4520 pa += PAGE_SIZE; 4521 resid -= PAGE_SIZE; 4522 } 4523 #ifdef VERBOSE_INIT_ARM 4524 printf("\n"); 4525 #endif 4526 return (size); 4527 } 4528 4529 /********************** Static device map routines ***************************/ 4530 4531 static const struct pmap_devmap *pmap_devmap_table; 4532 4533 /* 4534 * Register the devmap table. This is provided in case early console 4535 * initialization needs to register mappings created by bootstrap code 4536 * before pmap_devmap_bootstrap() is called. 4537 */ 4538 void 4539 pmap_devmap_register(const struct pmap_devmap *table) 4540 { 4541 4542 pmap_devmap_table = table; 4543 } 4544 4545 /* 4546 * Map all of the static regions in the devmap table, and remember 4547 * the devmap table so other parts of the kernel can look up entries 4548 * later. 4549 */ 4550 void 4551 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 4552 { 4553 int i; 4554 4555 pmap_devmap_table = table; 4556 4557 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4558 #ifdef VERBOSE_INIT_ARM 4559 printf("devmap: %08lx -> %08lx @ %08lx\n", 4560 pmap_devmap_table[i].pd_pa, 4561 pmap_devmap_table[i].pd_pa + 4562 pmap_devmap_table[i].pd_size - 1, 4563 pmap_devmap_table[i].pd_va); 4564 #endif 4565 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4566 pmap_devmap_table[i].pd_pa, 4567 pmap_devmap_table[i].pd_size, 4568 pmap_devmap_table[i].pd_prot, 4569 pmap_devmap_table[i].pd_cache); 4570 } 4571 } 4572 4573 const struct pmap_devmap * 4574 pmap_devmap_find_pa(paddr_t pa, psize_t size) 4575 { 4576 uint64_t endpa; 4577 int i; 4578 4579 if (pmap_devmap_table == NULL) 4580 return (NULL); 4581 4582 endpa = (uint64_t)pa + (uint64_t)size; 4583 4584 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4585 if (pa >= pmap_devmap_table[i].pd_pa && 4586 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 4587 (uint64_t)pmap_devmap_table[i].pd_size) 4588 return (&pmap_devmap_table[i]); 4589 } 4590 4591 return (NULL); 4592 } 4593 4594 const struct pmap_devmap * 4595 pmap_devmap_find_va(vaddr_t va, vsize_t size) 4596 { 4597 int i; 4598 4599 if (pmap_devmap_table == NULL) 4600 return (NULL); 4601 4602 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4603 if (va >= pmap_devmap_table[i].pd_va && 4604 va + size <= pmap_devmap_table[i].pd_va + 4605 pmap_devmap_table[i].pd_size) 4606 return (&pmap_devmap_table[i]); 4607 } 4608 4609 return (NULL); 4610 } 4611 4612 /********************** PTE initialization routines **************************/ 4613 4614 /* 4615 * These routines are called when the CPU type is identified to set up 4616 * the PTE prototypes, cache modes, etc. 4617 * 4618 * The variables are always here, just in case LKMs need to reference 4619 * them (though, they shouldn't). 4620 */ 4621 4622 pt_entry_t pte_l1_s_cache_mode; 4623 pt_entry_t pte_l1_s_cache_mode_pt; 4624 pt_entry_t pte_l1_s_cache_mask; 4625 4626 pt_entry_t pte_l2_l_cache_mode; 4627 pt_entry_t pte_l2_l_cache_mode_pt; 4628 pt_entry_t pte_l2_l_cache_mask; 4629 4630 pt_entry_t pte_l2_s_cache_mode; 4631 pt_entry_t pte_l2_s_cache_mode_pt; 4632 pt_entry_t pte_l2_s_cache_mask; 4633 4634 pt_entry_t pte_l2_s_prot_u; 4635 pt_entry_t pte_l2_s_prot_w; 4636 pt_entry_t pte_l2_s_prot_mask; 4637 4638 pt_entry_t pte_l1_s_proto; 4639 pt_entry_t pte_l1_c_proto; 4640 pt_entry_t pte_l2_s_proto; 4641 4642 void (*pmap_copy_page_func)(paddr_t, paddr_t); 4643 void (*pmap_zero_page_func)(paddr_t); 4644 4645 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 4646 void 4647 pmap_pte_init_generic(void) 4648 { 4649 4650 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 4651 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 4652 4653 pte_l2_l_cache_mode = L2_B|L2_C; 4654 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 4655 4656 pte_l2_s_cache_mode = L2_B|L2_C; 4657 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 4658 4659 /* 4660 * If we have a write-through cache, set B and C. If 4661 * we have a write-back cache, then we assume setting 4662 * only C will make those pages write-through. 4663 */ 4664 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 4665 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 4666 pte_l2_l_cache_mode_pt = L2_B|L2_C; 4667 pte_l2_s_cache_mode_pt = L2_B|L2_C; 4668 } else { 4669 pte_l1_s_cache_mode_pt = L1_S_C; 4670 pte_l2_l_cache_mode_pt = L2_C; 4671 pte_l2_s_cache_mode_pt = L2_C; 4672 } 4673 4674 pte_l2_s_prot_u = L2_S_PROT_U_generic; 4675 pte_l2_s_prot_w = L2_S_PROT_W_generic; 4676 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 4677 4678 pte_l1_s_proto = L1_S_PROTO_generic; 4679 pte_l1_c_proto = L1_C_PROTO_generic; 4680 pte_l2_s_proto = L2_S_PROTO_generic; 4681 4682 pmap_copy_page_func = pmap_copy_page_generic; 4683 pmap_zero_page_func = pmap_zero_page_generic; 4684 } 4685 4686 #if defined(CPU_ARM8) 4687 void 4688 pmap_pte_init_arm8(void) 4689 { 4690 4691 /* 4692 * ARM8 is compatible with generic, but we need to use 4693 * the page tables uncached. 4694 */ 4695 pmap_pte_init_generic(); 4696 4697 pte_l1_s_cache_mode_pt = 0; 4698 pte_l2_l_cache_mode_pt = 0; 4699 pte_l2_s_cache_mode_pt = 0; 4700 } 4701 #endif /* CPU_ARM8 */ 4702 4703 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 4704 void 4705 pmap_pte_init_arm9(void) 4706 { 4707 4708 /* 4709 * ARM9 is compatible with generic, but we want to use 4710 * write-through caching for now. 4711 */ 4712 pmap_pte_init_generic(); 4713 4714 pte_l1_s_cache_mode = L1_S_C; 4715 pte_l2_l_cache_mode = L2_C; 4716 pte_l2_s_cache_mode = L2_C; 4717 4718 pte_l1_s_cache_mode_pt = L1_S_C; 4719 pte_l2_l_cache_mode_pt = L2_C; 4720 pte_l2_s_cache_mode_pt = L2_C; 4721 } 4722 #endif /* CPU_ARM9 */ 4723 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4724 4725 #if defined(CPU_ARM10) 4726 void 4727 pmap_pte_init_arm10(void) 4728 { 4729 4730 /* 4731 * ARM10 is compatible with generic, but we want to use 4732 * write-through caching for now. 4733 */ 4734 pmap_pte_init_generic(); 4735 4736 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 4737 pte_l2_l_cache_mode = L2_B | L2_C; 4738 pte_l2_s_cache_mode = L2_B | L2_C; 4739 4740 pte_l1_s_cache_mode_pt = L1_S_C; 4741 pte_l2_l_cache_mode_pt = L2_C; 4742 pte_l2_s_cache_mode_pt = L2_C; 4743 4744 } 4745 #endif /* CPU_ARM10 */ 4746 4747 #if ARM_MMU_SA1 == 1 4748 void 4749 pmap_pte_init_sa1(void) 4750 { 4751 4752 /* 4753 * The StrongARM SA-1 cache does not have a write-through 4754 * mode. So, do the generic initialization, then reset 4755 * the page table cache mode to B=1,C=1, and note that 4756 * the PTEs need to be sync'd. 4757 */ 4758 pmap_pte_init_generic(); 4759 4760 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 4761 pte_l2_l_cache_mode_pt = L2_B|L2_C; 4762 pte_l2_s_cache_mode_pt = L2_B|L2_C; 4763 4764 pmap_needs_pte_sync = 1; 4765 } 4766 #endif /* ARM_MMU_SA1 == 1*/ 4767 4768 #if ARM_MMU_XSCALE == 1 4769 #if (ARM_NMMUS > 1) 4770 static u_int xscale_use_minidata; 4771 #endif 4772 4773 void 4774 pmap_pte_init_xscale(void) 4775 { 4776 uint32_t auxctl; 4777 int write_through = 0; 4778 4779 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 4780 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 4781 4782 pte_l2_l_cache_mode = L2_B|L2_C; 4783 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 4784 4785 pte_l2_s_cache_mode = L2_B|L2_C; 4786 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 4787 4788 pte_l1_s_cache_mode_pt = L1_S_C; 4789 pte_l2_l_cache_mode_pt = L2_C; 4790 pte_l2_s_cache_mode_pt = L2_C; 4791 4792 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 4793 /* 4794 * The XScale core has an enhanced mode where writes that 4795 * miss the cache cause a cache line to be allocated. This 4796 * is significantly faster than the traditional, write-through 4797 * behavior of this case. 4798 */ 4799 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 4800 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 4801 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 4802 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 4803 4804 #ifdef XSCALE_CACHE_WRITE_THROUGH 4805 /* 4806 * Some versions of the XScale core have various bugs in 4807 * their cache units, the work-around for which is to run 4808 * the cache in write-through mode. Unfortunately, this 4809 * has a major (negative) impact on performance. So, we 4810 * go ahead and run fast-and-loose, in the hopes that we 4811 * don't line up the planets in a way that will trip the 4812 * bugs. 4813 * 4814 * However, we give you the option to be slow-but-correct. 4815 */ 4816 write_through = 1; 4817 #elif defined(XSCALE_CACHE_WRITE_BACK) 4818 /* force write back cache mode */ 4819 write_through = 0; 4820 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 4821 /* 4822 * Intel PXA2[15]0 processors are known to have a bug in 4823 * write-back cache on revision 4 and earlier (stepping 4824 * A[01] and B[012]). Fixed for C0 and later. 4825 */ 4826 { 4827 uint32_t id, type; 4828 4829 id = cpufunc_id(); 4830 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 4831 4832 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 4833 if ((id & CPU_ID_REVISION_MASK) < 5) { 4834 /* write through for stepping A0-1 and B0-2 */ 4835 write_through = 1; 4836 } 4837 } 4838 } 4839 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 4840 4841 if (write_through) { 4842 pte_l1_s_cache_mode = L1_S_C; 4843 pte_l2_l_cache_mode = L2_C; 4844 pte_l2_s_cache_mode = L2_C; 4845 } 4846 4847 #if (ARM_NMMUS > 1) 4848 xscale_use_minidata = 1; 4849 #endif 4850 4851 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 4852 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 4853 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 4854 4855 pte_l1_s_proto = L1_S_PROTO_xscale; 4856 pte_l1_c_proto = L1_C_PROTO_xscale; 4857 pte_l2_s_proto = L2_S_PROTO_xscale; 4858 4859 pmap_copy_page_func = pmap_copy_page_xscale; 4860 pmap_zero_page_func = pmap_zero_page_xscale; 4861 4862 /* 4863 * Disable ECC protection of page table access, for now. 4864 */ 4865 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 4866 auxctl &= ~XSCALE_AUXCTL_P; 4867 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 4868 } 4869 4870 /* 4871 * xscale_setup_minidata: 4872 * 4873 * Set up the mini-data cache clean area. We require the 4874 * caller to allocate the right amount of physically and 4875 * virtually contiguous space. 4876 */ 4877 void 4878 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 4879 { 4880 extern vaddr_t xscale_minidata_clean_addr; 4881 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 4882 pd_entry_t *pde = (pd_entry_t *) l1pt; 4883 pt_entry_t *pte; 4884 vsize_t size; 4885 uint32_t auxctl; 4886 4887 xscale_minidata_clean_addr = va; 4888 4889 /* Round it to page size. */ 4890 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 4891 4892 for (; size != 0; 4893 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 4894 #ifndef ARM32_NEW_VM_LAYOUT 4895 pte = (pt_entry_t *) 4896 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4897 #else 4898 pte = (pt_entry_t *) kernel_pt_lookup( 4899 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4900 #endif 4901 if (pte == NULL) 4902 panic("xscale_setup_minidata: can't find L2 table for " 4903 "VA 0x%08lx", va); 4904 #ifndef ARM32_NEW_VM_LAYOUT 4905 pte[(va >> PGSHIFT) & 0x3ff] = 4906 #else 4907 pte[l2pte_index(va)] = 4908 #endif 4909 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4910 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4911 } 4912 4913 /* 4914 * Configure the mini-data cache for write-back with 4915 * read/write-allocate. 4916 * 4917 * NOTE: In order to reconfigure the mini-data cache, we must 4918 * make sure it contains no valid data! In order to do that, 4919 * we must issue a global data cache invalidate command! 4920 * 4921 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 4922 * THIS IS VERY IMPORTANT! 4923 */ 4924 4925 /* Invalidate data and mini-data. */ 4926 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 4927 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 4928 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 4929 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 4930 } 4931 4932 /* 4933 * Change the PTEs for the specified kernel mappings such that they 4934 * will use the mini data cache instead of the main data cache. 4935 */ 4936 void 4937 pmap_uarea(vaddr_t va) 4938 { 4939 struct l2_bucket *l2b; 4940 pt_entry_t *ptep, *sptep, pte; 4941 vaddr_t next_bucket, eva; 4942 4943 #if (ARM_NMMUS > 1) 4944 if (xscale_use_minidata == 0) 4945 return; 4946 #endif 4947 4948 eva = va + USPACE; 4949 4950 while (va < eva) { 4951 next_bucket = L2_NEXT_BUCKET(va); 4952 if (next_bucket > eva) 4953 next_bucket = eva; 4954 4955 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4956 KDASSERT(l2b != NULL); 4957 4958 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4959 4960 while (va < next_bucket) { 4961 pte = *ptep; 4962 if (!l2pte_minidata(pte)) { 4963 cpu_dcache_wbinv_range(va, PAGE_SIZE); 4964 cpu_tlb_flushD_SE(va); 4965 *ptep = pte & ~L2_B; 4966 } 4967 ptep++; 4968 va += PAGE_SIZE; 4969 } 4970 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4971 } 4972 cpu_cpwait(); 4973 } 4974 #endif /* ARM_MMU_XSCALE == 1 */ 4975 4976 #if defined(DDB) 4977 /* 4978 * A couple of ddb-callable functions for dumping pmaps 4979 */ 4980 void pmap_dump_all(void); 4981 void pmap_dump(pmap_t); 4982 4983 void 4984 pmap_dump_all(void) 4985 { 4986 pmap_t pm; 4987 4988 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 4989 if (pm == pmap_kernel()) 4990 continue; 4991 pmap_dump(pm); 4992 printf("\n"); 4993 } 4994 } 4995 4996 static pt_entry_t ncptes[64]; 4997 static void pmap_dump_ncpg(pmap_t); 4998 4999 void 5000 pmap_dump(pmap_t pm) 5001 { 5002 struct l2_dtable *l2; 5003 struct l2_bucket *l2b; 5004 pt_entry_t *ptep, pte; 5005 vaddr_t l2_va, l2b_va, va; 5006 int i, j, k, occ, rows = 0; 5007 5008 if (pm == pmap_kernel()) 5009 printf("pmap_kernel (%p): ", pm); 5010 else 5011 printf("user pmap (%p): ", pm); 5012 5013 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 5014 5015 l2_va = 0; 5016 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 5017 l2 = pm->pm_l2[i]; 5018 5019 if (l2 == NULL || l2->l2_occupancy == 0) 5020 continue; 5021 5022 l2b_va = l2_va; 5023 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 5024 l2b = &l2->l2_bucket[j]; 5025 5026 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 5027 continue; 5028 5029 ptep = l2b->l2b_kva; 5030 5031 for (k = 0; k < 256 && ptep[k] == 0; k++) 5032 ; 5033 5034 k &= ~63; 5035 occ = l2b->l2b_occupancy; 5036 va = l2b_va + (k * 4096); 5037 for (; k < 256; k++, va += 0x1000) { 5038 char ch = ' '; 5039 if ((k % 64) == 0) { 5040 if ((rows % 8) == 0) { 5041 printf( 5042 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 5043 } 5044 printf("%08lx: ", va); 5045 } 5046 5047 ncptes[k & 63] = 0; 5048 pte = ptep[k]; 5049 if (pte == 0) { 5050 ch = '.'; 5051 } else { 5052 occ--; 5053 switch (pte & 0x0c) { 5054 case 0x00: 5055 ch = 'D'; /* No cache No buff */ 5056 break; 5057 case 0x04: 5058 ch = 'B'; /* No cache buff */ 5059 break; 5060 case 0x08: 5061 if (pte & 0x40) 5062 ch = 'm'; 5063 else 5064 ch = 'C'; /* Cache No buff */ 5065 break; 5066 case 0x0c: 5067 ch = 'F'; /* Cache Buff */ 5068 break; 5069 } 5070 5071 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 5072 ch += 0x20; 5073 5074 if ((pte & 0xc) == 0) 5075 ncptes[k & 63] = pte; 5076 } 5077 5078 if ((k % 64) == 63) { 5079 rows++; 5080 printf("%c\n", ch); 5081 pmap_dump_ncpg(pm); 5082 if (occ == 0) 5083 break; 5084 } else 5085 printf("%c", ch); 5086 } 5087 } 5088 } 5089 } 5090 5091 static void 5092 pmap_dump_ncpg(pmap_t pm) 5093 { 5094 struct vm_page *pg; 5095 struct pv_entry *pv; 5096 int i; 5097 5098 for (i = 0; i < 63; i++) { 5099 if (ncptes[i] == 0) 5100 continue; 5101 5102 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 5103 if (pg == NULL) 5104 continue; 5105 5106 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 5107 pg->phys_addr, 5108 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 5109 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 5110 5111 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 5112 printf(" %c va 0x%08lx, flags 0x%x\n", 5113 (pm == pv->pv_pmap) ? '*' : ' ', 5114 pv->pv_va, pv->pv_flags); 5115 } 5116 } 5117 } 5118 #endif 5119
Indexes created Mon Sep 29 13:09:55 GMT 2025