pmap.c revision 1.157.24.1.4.2
1 /* $NetBSD: pmap.c,v 1.157.24.1.4.2 2007/11/10 04:00:01 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 3. All advertising materials mentioning features or use of this software 82 * must display the following acknowledgement: 83 * This product includes software developed by the NetBSD 84 * Foundation, Inc. and its contributors. 85 * 4. Neither the name of The NetBSD Foundation nor the names of its 86 * contributors may be used to endorse or promote products derived 87 * from this software without specific prior written permission. 88 * 89 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 90 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 91 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 92 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 93 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 94 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 95 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 96 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 97 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 98 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 99 * POSSIBILITY OF SUCH DAMAGE. 100 */ 101 102 /* 103 * Copyright (c) 1994-1998 Mark Brinicombe. 104 * Copyright (c) 1994 Brini. 105 * All rights reserved. 106 * 107 * This code is derived from software written for Brini by Mark Brinicombe 108 * 109 * Redistribution and use in source and binary forms, with or without 110 * modification, are permitted provided that the following conditions 111 * are met: 112 * 1. Redistributions of source code must retain the above copyright 113 * notice, this list of conditions and the following disclaimer. 114 * 2. Redistributions in binary form must reproduce the above copyright 115 * notice, this list of conditions and the following disclaimer in the 116 * documentation and/or other materials provided with the distribution. 117 * 3. All advertising materials mentioning features or use of this software 118 * must display the following acknowledgement: 119 * This product includes software developed by Mark Brinicombe. 120 * 4. The name of the author may not be used to endorse or promote products 121 * derived from this software without specific prior written permission. 122 * 123 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 124 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 125 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 126 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 127 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 128 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 129 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 130 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 131 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 132 * 133 * RiscBSD kernel project 134 * 135 * pmap.c 136 * 137 * Machine dependant vm stuff 138 * 139 * Created : 20/09/94 140 */ 141 142 /* 143 * armv6 and VIPT cache support by 3am Software Foundry, 144 * Copyright (c) 2007 Danger Inc 145 */ 146 147 /* 148 * Performance improvements, UVM changes, overhauls and part-rewrites 149 * were contributed by Neil A. Carson <neil (at) causality.com>. 150 */ 151 152 /* 153 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 154 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 155 * Systems, Inc. 156 * 157 * There are still a few things outstanding at this time: 158 * 159 * - There are some unresolved issues for MP systems: 160 * 161 * o The L1 metadata needs a lock, or more specifically, some places 162 * need to acquire an exclusive lock when modifying L1 translation 163 * table entries. 164 * 165 * o When one cpu modifies an L1 entry, and that L1 table is also 166 * being used by another cpu, then the latter will need to be told 167 * that a tlb invalidation may be necessary. (But only if the old 168 * domain number in the L1 entry being over-written is currently 169 * the active domain on that cpu). I guess there are lots more tlb 170 * shootdown issues too... 171 * 172 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 173 * MP systems will lose big-time because of the MMU domain hack. 174 * The only way this can be solved (apart from moving the vector 175 * page to 0xffff0000) is to reserve the first 1MB of user address 176 * space for kernel use only. This would require re-linking all 177 * applications so that the text section starts above this 1MB 178 * boundary. 179 * 180 * o Tracking which VM space is resident in the cache/tlb has not yet 181 * been implemented for MP systems. 182 * 183 * o Finally, there is a pathological condition where two cpus running 184 * two separate processes (not lwps) which happen to share an L1 185 * can get into a fight over one or more L1 entries. This will result 186 * in a significant slow-down if both processes are in tight loops. 187 */ 188 189 /* 190 * Special compilation symbols 191 * PMAP_DEBUG - Build in pmap_debug_level code 192 */ 193 194 /* Include header files */ 195 196 #include "opt_cpuoptions.h" 197 #include "opt_pmap_debug.h" 198 #include "opt_ddb.h" 199 #include "opt_lockdebug.h" 200 #include "opt_multiprocessor.h" 201 202 #include <sys/types.h> 203 #include <sys/param.h> 204 #include <sys/kernel.h> 205 #include <sys/systm.h> 206 #include <sys/proc.h> 207 #include <sys/malloc.h> 208 #include <sys/user.h> 209 #include <sys/pool.h> 210 #include <sys/cdefs.h> 211 212 #include <uvm/uvm.h> 213 214 #include <machine/bus.h> 215 #include <machine/pmap.h> 216 #include <machine/pcb.h> 217 #include <machine/param.h> 218 #include <arm/arm32/katelib.h> 219 220 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.157.24.1.4.2 2007/11/10 04:00:01 matt Exp $"); 221 222 #ifdef PMAP_DEBUG 223 224 /* XXX need to get rid of all refs to this */ 225 int pmap_debug_level = 0; 226 227 /* 228 * for switching to potentially finer grained debugging 229 */ 230 #define PDB_FOLLOW 0x0001 231 #define PDB_INIT 0x0002 232 #define PDB_ENTER 0x0004 233 #define PDB_REMOVE 0x0008 234 #define PDB_CREATE 0x0010 235 #define PDB_PTPAGE 0x0020 236 #define PDB_GROWKERN 0x0040 237 #define PDB_BITS 0x0080 238 #define PDB_COLLECT 0x0100 239 #define PDB_PROTECT 0x0200 240 #define PDB_MAP_L1 0x0400 241 #define PDB_BOOTSTRAP 0x1000 242 #define PDB_PARANOIA 0x2000 243 #define PDB_WIRING 0x4000 244 #define PDB_PVDUMP 0x8000 245 #define PDB_VAC 0x10000 246 #define PDB_KENTER 0x20000 247 #define PDB_KREMOVE 0x40000 248 #define PDB_EXEC 0x80000 249 250 int debugmap = 1; 251 int pmapdebug = 0; 252 #define NPDEBUG(_lev_,_stat_) \ 253 if (pmapdebug & (_lev_)) \ 254 ((_stat_)) 255 256 #else /* PMAP_DEBUG */ 257 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 258 #endif /* PMAP_DEBUG */ 259 260 /* 261 * pmap_kernel() points here 262 */ 263 struct pmap kernel_pmap_store; 264 265 /* 266 * Which pmap is currently 'live' in the cache 267 * 268 * XXXSCW: Fix for SMP ... 269 */ 270 union pmap_cache_state *pmap_cache_state; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool pmap_pmap_pool; 278 static struct pool_cache pmap_pmap_cache; 279 static LIST_HEAD(, pmap) pmap_pmaps; 280 281 /* 282 * Pool of PV structures 283 */ 284 static struct pool pmap_pv_pool; 285 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 286 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 287 static struct pool_allocator pmap_bootstrap_pv_allocator = { 288 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 289 }; 290 291 /* 292 * Pool and cache of l2_dtable structures. 293 * We use a cache to avoid clearing the structures when they're 294 * allocated. (196 bytes) 295 */ 296 static struct pool pmap_l2dtable_pool; 297 static struct pool_cache pmap_l2dtable_cache; 298 static vaddr_t pmap_kernel_l2dtable_kva; 299 300 /* 301 * Pool and cache of L2 page descriptors. 302 * We use a cache to avoid clearing the descriptor table 303 * when they're allocated. (1KB) 304 */ 305 static struct pool pmap_l2ptp_pool; 306 static struct pool_cache pmap_l2ptp_cache; 307 static vaddr_t pmap_kernel_l2ptp_kva; 308 static paddr_t pmap_kernel_l2ptp_phys; 309 310 #ifdef PMAPCOUNTERS 311 #define PMAP_EVCNT_INITIALIZER(name) \ 312 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 313 314 static struct evcnt pmap_ev_vac_color_new = 315 PMAP_EVCNT_INITIALIZER("new page color"); 316 static struct evcnt pmap_ev_vac_color_reuse = 317 PMAP_EVCNT_INITIALIZER("ok first page color"); 318 static struct evcnt pmap_ev_vac_color_ok = 319 PMAP_EVCNT_INITIALIZER("ok page color"); 320 static struct evcnt pmap_ev_vac_color_change = 321 PMAP_EVCNT_INITIALIZER("change page color"); 322 static struct evcnt pmap_ev_vac_color_erase = 323 PMAP_EVCNT_INITIALIZER("erase page color"); 324 static struct evcnt pmap_ev_vac_color_none = 325 PMAP_EVCNT_INITIALIZER("no page color"); 326 static struct evcnt pmap_ev_vac_color_restore = 327 PMAP_EVCNT_INITIALIZER("restore page color"); 328 329 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 330 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 331 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 332 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 333 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 334 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 335 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 336 337 static struct evcnt pmap_ev_mappings = 338 PMAP_EVCNT_INITIALIZER("pages mapped"); 339 static struct evcnt pmap_ev_unmappings = 340 PMAP_EVCNT_INITIALIZER("pages unmapped"); 341 static struct evcnt pmap_ev_remappings = 342 PMAP_EVCNT_INITIALIZER("pages remapped"); 343 344 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 345 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 346 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 347 348 static struct evcnt pmap_ev_kernel_mappings = 349 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 350 static struct evcnt pmap_ev_kernel_unmappings = 351 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 352 static struct evcnt pmap_ev_kernel_remappings = 353 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 354 355 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 356 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 357 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 358 359 static struct evcnt pmap_ev_kenter_mappings = 360 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 361 static struct evcnt pmap_ev_kenter_unmappings = 362 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 363 static struct evcnt pmap_ev_kenter_remappings = 364 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 365 static struct evcnt pmap_ev_pt_mappings = 366 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 367 368 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 369 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 370 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 372 373 static struct evcnt pmap_ev_exec_mappings = 374 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 375 static struct evcnt pmap_ev_exec_cached = 376 PMAP_EVCNT_INITIALIZER("exec pages cached"); 377 378 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 379 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 380 381 static struct evcnt pmap_ev_exec_synced = 382 PMAP_EVCNT_INITIALIZER("exec pages synced"); 383 static struct evcnt pmap_ev_exec_synced_map = 384 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 385 static struct evcnt pmap_ev_exec_synced_unmap = 386 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 387 static struct evcnt pmap_ev_exec_synced_remap = 388 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 389 static struct evcnt pmap_ev_exec_synced_clearbit = 390 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 391 static struct evcnt pmap_ev_exec_synced_kremove = 392 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 393 394 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 397 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 399 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 400 401 static struct evcnt pmap_ev_exec_discarded_unmap = 402 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 403 static struct evcnt pmap_ev_exec_discarded_zero = 404 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 405 static struct evcnt pmap_ev_exec_discarded_copy = 406 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 407 static struct evcnt pmap_ev_exec_discarded_page_protect = 408 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 409 static struct evcnt pmap_ev_exec_discarded_clearbit = 410 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 411 static struct evcnt pmap_ev_exec_discarded_kremove = 412 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 413 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 420 421 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 422 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 423 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 424 425 EVCNT_ATTACH_STATIC(pmap_ev_updates); 426 EVCNT_ATTACH_STATIC(pmap_ev_collects); 427 EVCNT_ATTACH_STATIC(pmap_ev_activations); 428 429 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 430 #else 431 #define PMAPCOUNT(x) ((void)0) 432 #endif 433 434 /* 435 * pmap copy/zero page, and mem(5) hook point 436 */ 437 static pt_entry_t *csrc_pte, *cdst_pte; 438 static vaddr_t csrcp, cdstp; 439 char *memhook; 440 extern caddr_t msgbufaddr; 441 442 /* 443 * Flag to indicate if pmap_init() has done its thing 444 */ 445 boolean_t pmap_initialized; 446 447 /* 448 * Misc. locking data structures 449 */ 450 451 #if defined(MULTIPROCESSOR) || defined(LOCKDEBUG) 452 static struct lock pmap_main_lock; 453 454 #define PMAP_MAP_TO_HEAD_LOCK() \ 455 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 456 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 457 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 458 #define PMAP_HEAD_TO_MAP_LOCK() \ 459 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 460 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 461 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 462 #else 463 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 464 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 465 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 466 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 467 #endif 468 469 #define pmap_acquire_pmap_lock(pm) \ 470 do { \ 471 if ((pm) != pmap_kernel()) \ 472 simple_lock(&(pm)->pm_lock); \ 473 } while (/*CONSTCOND*/0) 474 475 #define pmap_release_pmap_lock(pm) \ 476 do { \ 477 if ((pm) != pmap_kernel()) \ 478 simple_unlock(&(pm)->pm_lock); \ 479 } while (/*CONSTCOND*/0) 480 481 482 /* 483 * Metadata for L1 translation tables. 484 */ 485 struct l1_ttable { 486 /* Entry on the L1 Table list */ 487 SLIST_ENTRY(l1_ttable) l1_link; 488 489 /* Entry on the L1 Least Recently Used list */ 490 TAILQ_ENTRY(l1_ttable) l1_lru; 491 492 /* Track how many domains are allocated from this L1 */ 493 volatile u_int l1_domain_use_count; 494 495 /* 496 * A free-list of domain numbers for this L1. 497 * We avoid using ffs() and a bitmap to track domains since ffs() 498 * is slow on ARM. 499 */ 500 u_int8_t l1_domain_first; 501 u_int8_t l1_domain_free[PMAP_DOMAINS]; 502 503 /* Physical address of this L1 page table */ 504 paddr_t l1_physaddr; 505 506 /* KVA of this L1 page table */ 507 pd_entry_t *l1_kva; 508 }; 509 510 /* 511 * Convert a virtual address into its L1 table index. That is, the 512 * index used to locate the L2 descriptor table pointer in an L1 table. 513 * This is basically used to index l1->l1_kva[]. 514 * 515 * Each L2 descriptor table represents 1MB of VA space. 516 */ 517 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 518 519 /* 520 * L1 Page Tables are tracked using a Least Recently Used list. 521 * - New L1s are allocated from the HEAD. 522 * - Freed L1s are added to the TAIl. 523 * - Recently accessed L1s (where an 'access' is some change to one of 524 * the userland pmaps which owns this L1) are moved to the TAIL. 525 */ 526 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 527 static struct simplelock l1_lru_lock; 528 529 /* 530 * A list of all L1 tables 531 */ 532 static SLIST_HEAD(, l1_ttable) l1_list; 533 534 /* 535 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 536 * 537 * This is normally 16MB worth L2 page descriptors for any given pmap. 538 * Reference counts are maintained for L2 descriptors so they can be 539 * freed when empty. 540 */ 541 struct l2_dtable { 542 /* The number of L2 page descriptors allocated to this l2_dtable */ 543 u_int l2_occupancy; 544 545 /* List of L2 page descriptors */ 546 struct l2_bucket { 547 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 548 paddr_t l2b_phys; /* Physical address of same */ 549 u_short l2b_l1idx; /* This L2 table's L1 index */ 550 u_short l2b_occupancy; /* How many active descriptors */ 551 } l2_bucket[L2_BUCKET_SIZE]; 552 }; 553 554 /* 555 * Given an L1 table index, calculate the corresponding l2_dtable index 556 * and bucket index within the l2_dtable. 557 */ 558 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 559 (L2_SIZE - 1)) 560 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 561 562 /* 563 * Given a virtual address, this macro returns the 564 * virtual address required to drop into the next L2 bucket. 565 */ 566 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 567 568 /* 569 * L2 allocation. 570 */ 571 #define pmap_alloc_l2_dtable() \ 572 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 573 #define pmap_free_l2_dtable(l2) \ 574 pool_cache_put(&pmap_l2dtable_cache, (l2)) 575 #define pmap_alloc_l2_ptp(pap) \ 576 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 577 PR_NOWAIT, (pap))) 578 579 /* 580 * We try to map the page tables write-through, if possible. However, not 581 * all CPUs have a write-through cache mode, so on those we have to sync 582 * the cache when we frob page tables. 583 * 584 * We try to evaluate this at compile time, if possible. However, it's 585 * not always possible to do that, hence this run-time var. 586 */ 587 int pmap_needs_pte_sync; 588 589 /* 590 * Real definition of pv_entry. 591 */ 592 struct pv_entry { 593 struct pv_entry *pv_next; /* next pv_entry */ 594 pmap_t pv_pmap; /* pmap where mapping lies */ 595 vaddr_t pv_va; /* virtual address for mapping */ 596 u_int pv_flags; /* flags */ 597 }; 598 599 /* 600 * Macro to determine if a mapping might be resident in the 601 * instruction cache and/or TLB 602 */ 603 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 604 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 605 606 /* 607 * Macro to determine if a mapping might be resident in the 608 * data cache and/or TLB 609 */ 610 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 611 612 /* 613 * Local prototypes 614 */ 615 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 616 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 617 pt_entry_t **); 618 static boolean_t pmap_is_current(pmap_t); 619 static boolean_t pmap_is_cached(pmap_t); 620 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 621 pmap_t, vaddr_t, u_int); 622 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 623 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 624 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 625 u_int, u_int); 626 627 static void pmap_pinit(pmap_t); 628 static int pmap_pmap_ctor(void *, void *, int); 629 630 static void pmap_alloc_l1(pmap_t); 631 static void pmap_free_l1(pmap_t); 632 static void pmap_use_l1(pmap_t); 633 634 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 635 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 636 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 637 static int pmap_l2ptp_ctor(void *, void *, int); 638 static int pmap_l2dtable_ctor(void *, void *, int); 639 640 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 641 #ifdef PMAP_CACHE_VIVT 642 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 643 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 644 #endif 645 646 static void pmap_clearbit(struct vm_page *, u_int); 647 #ifdef PMAP_CACHE_VIVT 648 static int pmap_clean_page(struct pv_entry *, boolean_t); 649 #endif 650 #ifdef PMAP_CACHE_VIPT 651 static void pmap_syncicache_page(struct vm_page *); 652 static void pmap_flush_page(struct vm_page *); 653 #endif 654 static void pmap_page_remove(struct vm_page *); 655 656 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 657 static vaddr_t kernel_pt_lookup(paddr_t); 658 659 660 /* 661 * External function prototypes 662 */ 663 extern void bzero_page(vaddr_t); 664 extern void bcopy_page(vaddr_t, vaddr_t); 665 666 /* 667 * Misc variables 668 */ 669 vaddr_t virtual_avail; 670 vaddr_t virtual_end; 671 vaddr_t pmap_curmaxkvaddr; 672 673 vaddr_t avail_start; 674 vaddr_t avail_end; 675 676 extern pv_addr_t systempage; 677 678 /* Function to set the debug level of the pmap code */ 679 680 #ifdef PMAP_DEBUG 681 void 682 pmap_debug(int level) 683 { 684 pmap_debug_level = level; 685 printf("pmap_debug: level=%d\n", pmap_debug_level); 686 } 687 #endif /* PMAP_DEBUG */ 688 689 /* 690 * A bunch of routines to conditionally flush the caches/TLB depending 691 * on whether the specified pmap actually needs to be flushed at any 692 * given time. 693 */ 694 static inline void 695 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 696 { 697 698 if (pm->pm_cstate.cs_tlb_id) 699 cpu_tlb_flushID_SE(va); 700 } 701 702 static inline void 703 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 704 { 705 706 if (pm->pm_cstate.cs_tlb_d) 707 cpu_tlb_flushD_SE(va); 708 } 709 710 static inline void 711 pmap_tlb_flushID(pmap_t pm) 712 { 713 714 if (pm->pm_cstate.cs_tlb_id) { 715 cpu_tlb_flushID(); 716 pm->pm_cstate.cs_tlb = 0; 717 } 718 } 719 720 static inline void 721 pmap_tlb_flushD(pmap_t pm) 722 { 723 724 if (pm->pm_cstate.cs_tlb_d) { 725 cpu_tlb_flushD(); 726 pm->pm_cstate.cs_tlb_d = 0; 727 } 728 } 729 730 #ifdef PMAP_CACHE_VIVT 731 static inline void 732 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 733 { 734 if (pm->pm_cstate.cs_cache_id) { 735 cpu_idcache_wbinv_range(va, len); 736 } 737 } 738 739 static inline void 740 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 741 boolean_t do_inv, boolean_t rd_only) 742 { 743 744 if (pm->pm_cstate.cs_cache_d) { 745 if (do_inv) { 746 if (rd_only) 747 cpu_dcache_inv_range(va, len); 748 else 749 cpu_dcache_wbinv_range(va, len); 750 } else 751 if (!rd_only) 752 cpu_dcache_wb_range(va, len); 753 } 754 } 755 756 static inline void 757 pmap_idcache_wbinv_all(pmap_t pm) 758 { 759 if (pm->pm_cstate.cs_cache_id) { 760 cpu_idcache_wbinv_all(); 761 pm->pm_cstate.cs_cache = 0; 762 } 763 } 764 765 static inline void 766 pmap_dcache_wbinv_all(pmap_t pm) 767 { 768 if (pm->pm_cstate.cs_cache_d) { 769 cpu_dcache_wbinv_all(); 770 pm->pm_cstate.cs_cache_d = 0; 771 } 772 } 773 #endif /* PMAP_CACHE_VIVT */ 774 775 static inline boolean_t 776 pmap_is_current(pmap_t pm) 777 { 778 779 if (pm == pmap_kernel() || 780 (curproc && curproc->p_vmspace->vm_map.pmap == pm)) 781 return (TRUE); 782 783 return (FALSE); 784 } 785 786 static inline boolean_t 787 pmap_is_cached(pmap_t pm) 788 { 789 790 if (pm == pmap_kernel() || pmap_cache_state == NULL || 791 pmap_cache_state == &pm->pm_cstate) 792 return (TRUE); 793 794 return (FALSE); 795 } 796 797 /* 798 * PTE_SYNC_CURRENT: 799 * 800 * Make sure the pte is written out to RAM. 801 * We need to do this for one of two cases: 802 * - We're dealing with the kernel pmap 803 * - There is no pmap active in the cache/tlb. 804 * - The specified pmap is 'active' in the cache/tlb. 805 */ 806 #ifdef PMAP_INCLUDE_PTE_SYNC 807 #define PTE_SYNC_CURRENT(pm, ptep) \ 808 do { \ 809 if (PMAP_NEEDS_PTE_SYNC && \ 810 pmap_is_cached(pm)) \ 811 PTE_SYNC(ptep); \ 812 } while (/*CONSTCOND*/0) 813 #else 814 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 815 #endif 816 817 /* 818 * main pv_entry manipulation functions: 819 * pmap_enter_pv: enter a mapping onto a vm_page list 820 * pmap_remove_pv: remove a mappiing from a vm_page list 821 * 822 * NOTE: pmap_enter_pv expects to lock the pvh itself 823 * pmap_remove_pv expects te caller to lock the pvh before calling 824 */ 825 826 /* 827 * pmap_enter_pv: enter a mapping onto a vm_page lst 828 * 829 * => caller should hold the proper lock on pmap_main_lock 830 * => caller should have pmap locked 831 * => we will gain the lock on the vm_page and allocate the new pv_entry 832 * => caller should adjust ptp's wire_count before calling 833 * => caller should not adjust pmap's wire_count 834 */ 835 static void 836 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 837 vaddr_t va, u_int flags) 838 { 839 840 NPDEBUG(PDB_PVDUMP, 841 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 842 843 pve->pv_pmap = pm; 844 pve->pv_va = va; 845 pve->pv_flags = flags; 846 847 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 848 pve->pv_next = pg->mdpage.pvh_list; /* add to ... */ 849 pg->mdpage.pvh_list = pve; /* ... locked list */ 850 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 851 if (pm == pmap_kernel()) { 852 PMAPCOUNT(kernel_mappings); 853 if (flags & PVF_WRITE) 854 pg->mdpage.krw_mappings++; 855 else 856 pg->mdpage.kro_mappings++; 857 } else 858 if (flags & PVF_WRITE) 859 pg->mdpage.urw_mappings++; 860 else 861 pg->mdpage.uro_mappings++; 862 863 #ifdef PMAP_CACHE_VIPT 864 /* 865 * If this is an exec mapping and its the first exec mapping 866 * for this page, make sure to sync the I-cache. 867 */ 868 if (PV_IS_EXEC_P(flags)) { 869 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 870 pmap_syncicache_page(pg); 871 PMAPCOUNT(exec_synced_map); 872 } 873 PMAPCOUNT(exec_mappings); 874 } 875 #endif 876 877 PMAPCOUNT(mappings); 878 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 879 880 if (pve->pv_flags & PVF_WIRED) 881 ++pm->pm_stats.wired_count; 882 } 883 884 /* 885 * 886 * pmap_find_pv: Find a pv entry 887 * 888 * => caller should hold lock on vm_page 889 */ 890 static inline struct pv_entry * 891 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 892 { 893 struct pv_entry *pv; 894 895 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 896 if (pm == pv->pv_pmap && va == pv->pv_va) 897 break; 898 } 899 900 return (pv); 901 } 902 903 /* 904 * pmap_remove_pv: try to remove a mapping from a pv_list 905 * 906 * => caller should hold proper lock on pmap_main_lock 907 * => pmap should be locked 908 * => caller should hold lock on vm_page [so that attrs can be adjusted] 909 * => caller should adjust ptp's wire_count and free PTP if needed 910 * => caller should NOT adjust pmap's wire_count 911 * => we return the removed pve 912 */ 913 static struct pv_entry * 914 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 915 { 916 struct pv_entry *pve, **prevptr; 917 918 NPDEBUG(PDB_PVDUMP, 919 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 920 921 prevptr = &pg->mdpage.pvh_list; /* previous pv_entry pointer */ 922 pve = *prevptr; 923 924 while (pve) { 925 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 926 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 927 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 928 if (pve->pv_flags & PVF_WIRED) { 929 if (skip_wired) 930 return (NULL); 931 --pm->pm_stats.wired_count; 932 } 933 *prevptr = pve->pv_next; /* remove it! */ 934 if (pm == pmap_kernel()) { 935 PMAPCOUNT(kernel_unmappings); 936 if (pve->pv_flags & PVF_WRITE) 937 pg->mdpage.krw_mappings--; 938 else 939 pg->mdpage.kro_mappings--; 940 } else 941 if (pve->pv_flags & PVF_WRITE) 942 pg->mdpage.urw_mappings--; 943 else 944 pg->mdpage.uro_mappings--; 945 946 PMAPCOUNT(unmappings); 947 #ifdef PMAP_CACHE_VIPT 948 if (!(pve->pv_flags & PVF_WRITE)) 949 break; 950 /* 951 * If this page has had an exec mapping, then if 952 * this was the last mapping, discard the contents, 953 * otherwise sync the i-cache for this page. 954 */ 955 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 956 if (pg->mdpage.pvh_list == NULL) { 957 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 958 PMAPCOUNT(exec_discarded_unmap); 959 } else { 960 pmap_syncicache_page(pg); 961 PMAPCOUNT(exec_synced_unmap); 962 } 963 } 964 #endif 965 break; 966 } 967 prevptr = &pve->pv_next; /* previous pointer */ 968 pve = pve->pv_next; /* advance */ 969 } 970 971 return(pve); /* return removed pve */ 972 } 973 974 /* 975 * 976 * pmap_modify_pv: Update pv flags 977 * 978 * => caller should hold lock on vm_page [so that attrs can be adjusted] 979 * => caller should NOT adjust pmap's wire_count 980 * => caller must call pmap_vac_me_harder() if writable status of a page 981 * may have changed. 982 * => we return the old flags 983 * 984 * Modify a physical-virtual mapping in the pv table 985 */ 986 static u_int 987 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 988 u_int clr_mask, u_int set_mask) 989 { 990 struct pv_entry *npv; 991 u_int flags, oflags; 992 993 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 994 return (0); 995 996 NPDEBUG(PDB_PVDUMP, 997 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 998 999 /* 1000 * There is at least one VA mapping this page. 1001 */ 1002 1003 if (clr_mask & (PVF_REF | PVF_MOD)) 1004 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1005 1006 oflags = npv->pv_flags; 1007 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1008 1009 if ((flags ^ oflags) & PVF_WIRED) { 1010 if (flags & PVF_WIRED) 1011 ++pm->pm_stats.wired_count; 1012 else 1013 --pm->pm_stats.wired_count; 1014 } 1015 1016 if ((flags ^ oflags) & PVF_WRITE) { 1017 if (pm == pmap_kernel()) { 1018 if (flags & PVF_WRITE) { 1019 pg->mdpage.krw_mappings++; 1020 pg->mdpage.kro_mappings--; 1021 } else { 1022 pg->mdpage.kro_mappings++; 1023 pg->mdpage.krw_mappings--; 1024 } 1025 } else 1026 if (flags & PVF_WRITE) { 1027 pg->mdpage.urw_mappings++; 1028 pg->mdpage.uro_mappings--; 1029 } else { 1030 pg->mdpage.uro_mappings++; 1031 pg->mdpage.urw_mappings--; 1032 } 1033 } 1034 #ifdef PMAP_CACHE_VIPT 1035 /* 1036 * We have two cases here: the first is from enter_pv (new exec 1037 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1038 * Since in latter, pmap_enter_pv won't do anything, we just have 1039 * to do what pmap_remove_pv would do. 1040 */ 1041 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1042 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1043 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1044 pmap_syncicache_page(pg); 1045 PMAPCOUNT(exec_synced_remap); 1046 } 1047 #endif 1048 1049 PMAPCOUNT(remappings); 1050 1051 return (oflags); 1052 } 1053 1054 static void 1055 pmap_pinit(pmap_t pm) 1056 { 1057 1058 if (vector_page < KERNEL_BASE) { 1059 /* 1060 * Map the vector page. 1061 */ 1062 pmap_enter(pm, vector_page, systempage.pv_pa, 1063 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1064 pmap_update(pm); 1065 } 1066 } 1067 1068 /* 1069 * Allocate an L1 translation table for the specified pmap. 1070 * This is called at pmap creation time. 1071 */ 1072 static void 1073 pmap_alloc_l1(pmap_t pm) 1074 { 1075 struct l1_ttable *l1; 1076 u_int8_t domain; 1077 1078 /* 1079 * Remove the L1 at the head of the LRU list 1080 */ 1081 simple_lock(&l1_lru_lock); 1082 l1 = TAILQ_FIRST(&l1_lru_list); 1083 KDASSERT(l1 != NULL); 1084 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1085 1086 /* 1087 * Pick the first available domain number, and update 1088 * the link to the next number. 1089 */ 1090 domain = l1->l1_domain_first; 1091 l1->l1_domain_first = l1->l1_domain_free[domain]; 1092 1093 /* 1094 * If there are still free domain numbers in this L1, 1095 * put it back on the TAIL of the LRU list. 1096 */ 1097 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1098 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1099 1100 simple_unlock(&l1_lru_lock); 1101 1102 /* 1103 * Fix up the relevant bits in the pmap structure 1104 */ 1105 pm->pm_l1 = l1; 1106 pm->pm_domain = domain; 1107 } 1108 1109 /* 1110 * Free an L1 translation table. 1111 * This is called at pmap destruction time. 1112 */ 1113 static void 1114 pmap_free_l1(pmap_t pm) 1115 { 1116 struct l1_ttable *l1 = pm->pm_l1; 1117 1118 simple_lock(&l1_lru_lock); 1119 1120 /* 1121 * If this L1 is currently on the LRU list, remove it. 1122 */ 1123 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1124 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1125 1126 /* 1127 * Free up the domain number which was allocated to the pmap 1128 */ 1129 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1130 l1->l1_domain_first = pm->pm_domain; 1131 l1->l1_domain_use_count--; 1132 1133 /* 1134 * The L1 now must have at least 1 free domain, so add 1135 * it back to the LRU list. If the use count is zero, 1136 * put it at the head of the list, otherwise it goes 1137 * to the tail. 1138 */ 1139 if (l1->l1_domain_use_count == 0) 1140 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1141 else 1142 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1143 1144 simple_unlock(&l1_lru_lock); 1145 } 1146 1147 static inline void 1148 pmap_use_l1(pmap_t pm) 1149 { 1150 struct l1_ttable *l1; 1151 1152 /* 1153 * Do nothing if we're in interrupt context. 1154 * Access to an L1 by the kernel pmap must not affect 1155 * the LRU list. 1156 */ 1157 if (current_intr_depth || pm == pmap_kernel()) 1158 return; 1159 1160 l1 = pm->pm_l1; 1161 1162 /* 1163 * If the L1 is not currently on the LRU list, just return 1164 */ 1165 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1166 return; 1167 1168 simple_lock(&l1_lru_lock); 1169 1170 /* 1171 * Check the use count again, now that we've acquired the lock 1172 */ 1173 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1174 simple_unlock(&l1_lru_lock); 1175 return; 1176 } 1177 1178 /* 1179 * Move the L1 to the back of the LRU list 1180 */ 1181 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1182 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1183 1184 simple_unlock(&l1_lru_lock); 1185 } 1186 1187 /* 1188 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1189 * 1190 * Free an L2 descriptor table. 1191 */ 1192 static inline void 1193 #ifndef PMAP_INCLUDE_PTE_SYNC 1194 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1195 #else 1196 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2, paddr_t pa) 1197 #endif 1198 { 1199 #ifdef PMAP_INCLUDE_PTE_SYNC 1200 #ifdef PMAP_CACHE_VIVT 1201 /* 1202 * Note: With a write-back cache, we may need to sync this 1203 * L2 table before re-using it. 1204 * This is because it may have belonged to a non-current 1205 * pmap, in which case the cache syncs would have been 1206 * skipped for the pages that were being unmapped. If the 1207 * L2 table were then to be immediately re-allocated to 1208 * the *current* pmap, it may well contain stale mappings 1209 * which have not yet been cleared by a cache write-back 1210 * and so would still be visible to the mmu. 1211 */ 1212 if (need_sync) 1213 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1214 #endif /* PMAP_CACHE_VIVT */ 1215 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1216 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1217 } 1218 1219 /* 1220 * Returns a pointer to the L2 bucket associated with the specified pmap 1221 * and VA, or NULL if no L2 bucket exists for the address. 1222 */ 1223 static inline struct l2_bucket * 1224 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1225 { 1226 struct l2_dtable *l2; 1227 struct l2_bucket *l2b; 1228 u_short l1idx; 1229 1230 l1idx = L1_IDX(va); 1231 1232 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1233 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1234 return (NULL); 1235 1236 return (l2b); 1237 } 1238 1239 /* 1240 * Returns a pointer to the L2 bucket associated with the specified pmap 1241 * and VA. 1242 * 1243 * If no L2 bucket exists, perform the necessary allocations to put an L2 1244 * bucket/page table in place. 1245 * 1246 * Note that if a new L2 bucket/page was allocated, the caller *must* 1247 * increment the bucket occupancy counter appropriately *before* 1248 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1249 * the bucket/page in the meantime. 1250 */ 1251 static struct l2_bucket * 1252 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1253 { 1254 struct l2_dtable *l2; 1255 struct l2_bucket *l2b; 1256 u_short l1idx; 1257 1258 l1idx = L1_IDX(va); 1259 1260 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1261 /* 1262 * No mapping at this address, as there is 1263 * no entry in the L1 table. 1264 * Need to allocate a new l2_dtable. 1265 */ 1266 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1267 return (NULL); 1268 1269 /* 1270 * Link it into the parent pmap 1271 */ 1272 pm->pm_l2[L2_IDX(l1idx)] = l2; 1273 } 1274 1275 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1276 1277 /* 1278 * Fetch pointer to the L2 page table associated with the address. 1279 */ 1280 if (l2b->l2b_kva == NULL) { 1281 pt_entry_t *ptep; 1282 1283 /* 1284 * No L2 page table has been allocated. Chances are, this 1285 * is because we just allocated the l2_dtable, above. 1286 */ 1287 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1288 /* 1289 * Oops, no more L2 page tables available at this 1290 * time. We may need to deallocate the l2_dtable 1291 * if we allocated a new one above. 1292 */ 1293 if (l2->l2_occupancy == 0) { 1294 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1295 pmap_free_l2_dtable(l2); 1296 } 1297 return (NULL); 1298 } 1299 1300 l2->l2_occupancy++; 1301 l2b->l2b_kva = ptep; 1302 l2b->l2b_l1idx = l1idx; 1303 } 1304 1305 return (l2b); 1306 } 1307 1308 /* 1309 * One or more mappings in the specified L2 descriptor table have just been 1310 * invalidated. 1311 * 1312 * Garbage collect the metadata and descriptor table itself if necessary. 1313 * 1314 * The pmap lock must be acquired when this is called (not necessary 1315 * for the kernel pmap). 1316 */ 1317 static void 1318 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1319 { 1320 struct l2_dtable *l2; 1321 pd_entry_t *pl1pd, l1pd; 1322 pt_entry_t *ptep; 1323 u_short l1idx; 1324 1325 KDASSERT(count <= l2b->l2b_occupancy); 1326 1327 /* 1328 * Update the bucket's reference count according to how many 1329 * PTEs the caller has just invalidated. 1330 */ 1331 l2b->l2b_occupancy -= count; 1332 1333 /* 1334 * Note: 1335 * 1336 * Level 2 page tables allocated to the kernel pmap are never freed 1337 * as that would require checking all Level 1 page tables and 1338 * removing any references to the Level 2 page table. See also the 1339 * comment elsewhere about never freeing bootstrap L2 descriptors. 1340 * 1341 * We make do with just invalidating the mapping in the L2 table. 1342 * 1343 * This isn't really a big deal in practice and, in fact, leads 1344 * to a performance win over time as we don't need to continually 1345 * alloc/free. 1346 */ 1347 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1348 return; 1349 1350 /* 1351 * There are no more valid mappings in this level 2 page table. 1352 * Go ahead and NULL-out the pointer in the bucket, then 1353 * free the page table. 1354 */ 1355 l1idx = l2b->l2b_l1idx; 1356 ptep = l2b->l2b_kva; 1357 l2b->l2b_kva = NULL; 1358 1359 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1360 1361 /* 1362 * If the L1 slot matches the pmap's domain 1363 * number, then invalidate it. 1364 */ 1365 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1366 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1367 *pl1pd = 0; 1368 PTE_SYNC(pl1pd); 1369 } 1370 1371 /* 1372 * Release the L2 descriptor table back to the pool cache. 1373 */ 1374 #ifndef PMAP_INCLUDE_PTE_SYNC 1375 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1376 #else 1377 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1378 #endif 1379 1380 /* 1381 * Update the reference count in the associated l2_dtable 1382 */ 1383 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1384 if (--l2->l2_occupancy > 0) 1385 return; 1386 1387 /* 1388 * There are no more valid mappings in any of the Level 1 1389 * slots managed by this l2_dtable. Go ahead and NULL-out 1390 * the pointer in the parent pmap and free the l2_dtable. 1391 */ 1392 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1393 pmap_free_l2_dtable(l2); 1394 } 1395 1396 /* 1397 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1398 * structures. 1399 */ 1400 static int 1401 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1402 { 1403 #ifndef PMAP_INCLUDE_PTE_SYNC 1404 struct l2_bucket *l2b; 1405 pt_entry_t *ptep, pte; 1406 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1407 1408 /* 1409 * The mappings for these page tables were initially made using 1410 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1411 * mode will not be right for page table mappings. To avoid 1412 * polluting the pmap_kenter_pa() code with a special case for 1413 * page tables, we simply fix up the cache-mode here if it's not 1414 * correct. 1415 */ 1416 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1417 KDASSERT(l2b != NULL); 1418 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1419 pte = *ptep; 1420 1421 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1422 /* 1423 * Page tables must have the cache-mode set to Write-Thru. 1424 */ 1425 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1426 PTE_SYNC(ptep); 1427 cpu_tlb_flushD_SE(va); 1428 cpu_cpwait(); 1429 } 1430 #endif 1431 1432 memset(v, 0, L2_TABLE_SIZE_REAL); 1433 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1434 return (0); 1435 } 1436 1437 static int 1438 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1439 { 1440 1441 memset(v, 0, sizeof(struct l2_dtable)); 1442 return (0); 1443 } 1444 1445 static int 1446 pmap_pmap_ctor(void *arg, void *v, int flags) 1447 { 1448 1449 memset(v, 0, sizeof(struct pmap)); 1450 return (0); 1451 } 1452 1453 #ifdef PMAP_CACHE_VIVT 1454 /* 1455 * Since we have a virtually indexed cache, we may need to inhibit caching if 1456 * there is more than one mapping and at least one of them is writable. 1457 * Since we purge the cache on every context switch, we only need to check for 1458 * other mappings within the same pmap, or kernel_pmap. 1459 * This function is also called when a page is unmapped, to possibly reenable 1460 * caching on any remaining mappings. 1461 * 1462 * The code implements the following logic, where: 1463 * 1464 * KW = # of kernel read/write pages 1465 * KR = # of kernel read only pages 1466 * UW = # of user read/write pages 1467 * UR = # of user read only pages 1468 * 1469 * KC = kernel mapping is cacheable 1470 * UC = user mapping is cacheable 1471 * 1472 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1473 * +--------------------------------------------- 1474 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1475 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1476 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1477 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1478 */ 1479 1480 static const int pmap_vac_flags[4][4] = { 1481 {-1, 0, 0, PVF_KNC}, 1482 {0, 0, PVF_NC, PVF_NC}, 1483 {0, PVF_NC, PVF_NC, PVF_NC}, 1484 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1485 }; 1486 1487 static inline int 1488 pmap_get_vac_flags(const struct vm_page *pg) 1489 { 1490 int kidx, uidx; 1491 1492 kidx = 0; 1493 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1494 kidx |= 1; 1495 if (pg->mdpage.krw_mappings) 1496 kidx |= 2; 1497 1498 uidx = 0; 1499 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1500 uidx |= 1; 1501 if (pg->mdpage.urw_mappings) 1502 uidx |= 2; 1503 1504 return (pmap_vac_flags[uidx][kidx]); 1505 } 1506 1507 static inline void 1508 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1509 { 1510 int nattr; 1511 1512 nattr = pmap_get_vac_flags(pg); 1513 1514 if (nattr < 0) { 1515 pg->mdpage.pvh_attrs &= ~PVF_NC; 1516 return; 1517 } 1518 1519 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1520 return; 1521 1522 if (pm == pmap_kernel()) 1523 pmap_vac_me_kpmap(pg, pm, va); 1524 else 1525 pmap_vac_me_user(pg, pm, va); 1526 1527 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1528 } 1529 1530 static void 1531 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1532 { 1533 u_int u_cacheable, u_entries; 1534 struct pv_entry *pv; 1535 pmap_t last_pmap = pm; 1536 1537 /* 1538 * Pass one, see if there are both kernel and user pmaps for 1539 * this page. Calculate whether there are user-writable or 1540 * kernel-writable pages. 1541 */ 1542 u_cacheable = 0; 1543 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1544 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1545 u_cacheable++; 1546 } 1547 1548 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1549 1550 /* 1551 * We know we have just been updating a kernel entry, so if 1552 * all user pages are already cacheable, then there is nothing 1553 * further to do. 1554 */ 1555 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1556 return; 1557 1558 if (u_entries) { 1559 /* 1560 * Scan over the list again, for each entry, if it 1561 * might not be set correctly, call pmap_vac_me_user 1562 * to recalculate the settings. 1563 */ 1564 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1565 /* 1566 * We know kernel mappings will get set 1567 * correctly in other calls. We also know 1568 * that if the pmap is the same as last_pmap 1569 * then we've just handled this entry. 1570 */ 1571 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1572 continue; 1573 1574 /* 1575 * If there are kernel entries and this page 1576 * is writable but non-cacheable, then we can 1577 * skip this entry also. 1578 */ 1579 if (pg->mdpage.k_mappings && 1580 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1581 (PVF_NC | PVF_WRITE)) 1582 continue; 1583 1584 /* 1585 * Similarly if there are no kernel-writable 1586 * entries and the page is already 1587 * read-only/cacheable. 1588 */ 1589 if (pg->mdpage.krw_mappings == 0 && 1590 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1591 continue; 1592 1593 /* 1594 * For some of the remaining cases, we know 1595 * that we must recalculate, but for others we 1596 * can't tell if they are correct or not, so 1597 * we recalculate anyway. 1598 */ 1599 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1600 } 1601 1602 if (pg->mdpage.k_mappings == 0) 1603 return; 1604 } 1605 1606 pmap_vac_me_user(pg, pm, va); 1607 } 1608 1609 static void 1610 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1611 { 1612 pmap_t kpmap = pmap_kernel(); 1613 struct pv_entry *pv, *npv; 1614 struct l2_bucket *l2b; 1615 pt_entry_t *ptep, pte; 1616 u_int entries = 0; 1617 u_int writable = 0; 1618 u_int cacheable_entries = 0; 1619 u_int kern_cacheable = 0; 1620 u_int other_writable = 0; 1621 1622 /* 1623 * Count mappings and writable mappings in this pmap. 1624 * Include kernel mappings as part of our own. 1625 * Keep a pointer to the first one. 1626 */ 1627 for (pv = npv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1628 /* Count mappings in the same pmap */ 1629 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1630 if (entries++ == 0) 1631 npv = pv; 1632 1633 /* Cacheable mappings */ 1634 if ((pv->pv_flags & PVF_NC) == 0) { 1635 cacheable_entries++; 1636 if (kpmap == pv->pv_pmap) 1637 kern_cacheable++; 1638 } 1639 1640 /* Writable mappings */ 1641 if (pv->pv_flags & PVF_WRITE) 1642 ++writable; 1643 } else 1644 if (pv->pv_flags & PVF_WRITE) 1645 other_writable = 1; 1646 } 1647 1648 /* 1649 * Enable or disable caching as necessary. 1650 * Note: the first entry might be part of the kernel pmap, 1651 * so we can't assume this is indicative of the state of the 1652 * other (maybe non-kpmap) entries. 1653 */ 1654 if ((entries > 1 && writable) || 1655 (entries > 0 && pm == kpmap && other_writable)) { 1656 if (cacheable_entries == 0) 1657 return; 1658 1659 for (pv = npv; pv; pv = pv->pv_next) { 1660 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1661 (pv->pv_flags & PVF_NC)) 1662 continue; 1663 1664 pv->pv_flags |= PVF_NC; 1665 1666 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1667 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1668 pte = *ptep & ~L2_S_CACHE_MASK; 1669 1670 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1671 l2pte_valid(pte)) { 1672 if (PV_BEEN_EXECD(pv->pv_flags)) { 1673 #ifdef PMAP_CACHE_VIVT 1674 pmap_idcache_wbinv_range(pv->pv_pmap, 1675 pv->pv_va, PAGE_SIZE); 1676 #endif 1677 pmap_tlb_flushID_SE(pv->pv_pmap, 1678 pv->pv_va); 1679 } else 1680 if (PV_BEEN_REFD(pv->pv_flags)) { 1681 #ifdef PMAP_CACHE_VIVT 1682 pmap_dcache_wb_range(pv->pv_pmap, 1683 pv->pv_va, PAGE_SIZE, TRUE, 1684 (pv->pv_flags & PVF_WRITE) == 0); 1685 #endif 1686 pmap_tlb_flushD_SE(pv->pv_pmap, 1687 pv->pv_va); 1688 } 1689 } 1690 1691 *ptep = pte; 1692 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1693 } 1694 cpu_cpwait(); 1695 } else 1696 if (entries > cacheable_entries) { 1697 /* 1698 * Turn cacheing back on for some pages. If it is a kernel 1699 * page, only do so if there are no other writable pages. 1700 */ 1701 for (pv = npv; pv; pv = pv->pv_next) { 1702 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1703 (kpmap != pv->pv_pmap || other_writable))) 1704 continue; 1705 1706 pv->pv_flags &= ~PVF_NC; 1707 1708 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1709 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1710 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1711 1712 if (l2pte_valid(pte)) { 1713 if (PV_BEEN_EXECD(pv->pv_flags)) { 1714 pmap_tlb_flushID_SE(pv->pv_pmap, 1715 pv->pv_va); 1716 } else 1717 if (PV_BEEN_REFD(pv->pv_flags)) { 1718 pmap_tlb_flushD_SE(pv->pv_pmap, 1719 pv->pv_va); 1720 } 1721 } 1722 1723 *ptep = pte; 1724 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1725 } 1726 } 1727 } 1728 #endif 1729 1730 #ifdef PMAP_CACHE_VIPT 1731 /* 1732 * For virtually indexed / physically tagged caches, what we have to worry 1733 * about is illegal cache aliases. To prevent this, we must ensure that 1734 * virtual addresses that map the physical page use the same bits for those 1735 * bits masked by "arm_cache_prefer_mask" (bits 12+). If there is a conflict, 1736 * all mappings of the page must be non-cached. 1737 */ 1738 static void 1739 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1740 { 1741 struct pv_entry *pv, pv0; 1742 vaddr_t tst_mask; 1743 bool bad_alias; 1744 struct l2_bucket *l2b; 1745 pt_entry_t *ptep, pte, opte; 1746 1747 /* do we need to do anything? */ 1748 if (arm_cache_prefer_mask == 0) 1749 return; 1750 1751 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1752 pg, pm, va)); 1753 1754 #define popc4(x) \ 1755 (((0x94 >> ((x & 3) << 1)) & 3) + ((0x94 >> ((x & 12) >> 1)) & 3)) 1756 1757 KASSERT(!va || pm || (pg->mdpage.pvh_attrs & PVF_KENTRY)); 1758 1759 /* Already a conflict? */ 1760 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1761 /* just an add, things are already non-cached */ 1762 bad_alias = false; 1763 if (va) { 1764 PMAPCOUNT(vac_color_none); 1765 bad_alias = true; 1766 goto fixup; 1767 } 1768 pv = pg->mdpage.pvh_list; 1769 /* the list can't be empty because it would be cachable */ 1770 if (pg->mdpage.pvh_attrs & PVF_KENTRY) { 1771 tst_mask = pg->mdpage.pvh_attrs; 1772 } else { 1773 KASSERT(pv); 1774 tst_mask = pv->pv_va; 1775 pv = pv->pv_next; 1776 } 1777 tst_mask &= arm_cache_prefer_mask; 1778 for (; pv && !bad_alias; pv = pv->pv_next) { 1779 /* if there's a bad alias, stop checking. */ 1780 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1781 bad_alias = true; 1782 } 1783 /* If no conflicting colors, set everything back to cached */ 1784 if (!bad_alias) { 1785 PMAPCOUNT(vac_color_restore); 1786 pg->mdpage.pvh_attrs |= PVF_COLORED; 1787 if (!(pg->mdpage.pvh_attrs & PVF_KENTRY)) { 1788 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1789 pg->mdpage.pvh_attrs |= tst_mask; 1790 } 1791 pg->mdpage.pvh_attrs &= ~PVF_NC; 1792 } else { 1793 KASSERT(pg->mdpage.pvh_list != NULL); 1794 KASSERT((pg->mdpage.pvh_attrs & PVF_KENTRY) 1795 || pg->mdpage.pvh_list->pv_next != NULL); 1796 } 1797 } else if (!va) { 1798 KASSERT(pmap_is_page_colored_p(pg)); 1799 if (pm == NULL) 1800 pg->mdpage.pvh_attrs &= 1801 (PAGE_SIZE - 1) | arm_cache_prefer_mask; 1802 return; 1803 } else if (!pmap_is_page_colored_p(pg)) { 1804 /* not colored so we just use its color */ 1805 PMAPCOUNT(vac_color_new); 1806 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1807 if (pm == NULL) 1808 pg->mdpage.pvh_attrs |= PVF_COLORED | va; 1809 else 1810 pg->mdpage.pvh_attrs |= PVF_COLORED 1811 | (va & arm_cache_prefer_mask); 1812 return; 1813 } else if (!((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask)) { 1814 if (pm == NULL) { 1815 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1816 pg->mdpage.pvh_attrs |= va; 1817 } 1818 if (pg->mdpage.pvh_list) 1819 PMAPCOUNT(vac_color_reuse); 1820 else 1821 PMAPCOUNT(vac_color_ok); 1822 /* matching color, just return */ 1823 return; 1824 } else { 1825 /* color conflict. evict from cache. */ 1826 pmap_flush_page(pg); 1827 1828 /* the list can't be empty because this was a enter/modify */ 1829 pv = pg->mdpage.pvh_list; 1830 KASSERT((pg->mdpage.pvh_attrs & PVF_KENTRY) || pv); 1831 1832 /* 1833 * If there's only one mapped page, change color to the 1834 * page's new color and return. 1835 */ 1836 if (((pg->mdpage.pvh_attrs & PVF_KENTRY) 1837 ? pv : pv->pv_next) == NULL) { 1838 PMAPCOUNT(vac_color_change); 1839 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1840 if (pm == NULL) 1841 pg->mdpage.pvh_attrs |= va; 1842 else 1843 pg->mdpage.pvh_attrs |= 1844 (va & arm_cache_prefer_mask); 1845 return; 1846 } 1847 bad_alias = true; 1848 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 1849 pg->mdpage.pvh_attrs |= PVF_NC; 1850 PMAPCOUNT(vac_color_erase); 1851 } 1852 1853 fixup: 1854 /* 1855 * If the pmap is NULL, then we got called from pmap_kenter_pa 1856 * and we must save the kenter'ed va. And this changes the 1857 * color to match the kenter'ed page. if this is a remove clear 1858 * saved va bits which retaining the color bits. 1859 */ 1860 if (pm == NULL) { 1861 if (va) { 1862 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1); 1863 pg->mdpage.pvh_attrs |= va; 1864 } else { 1865 pg->mdpage.pvh_attrs &= 1866 ((PAGE_SIZE - 1) | arm_cache_prefer_mask); 1867 } 1868 } 1869 1870 pv = pg->mdpage.pvh_list; 1871 1872 /* 1873 * If this page has an kenter'ed mapping, fake up a pv entry. 1874 */ 1875 if (__predict_false(pg->mdpage.pvh_attrs & PVF_KENTRY)) { 1876 pv0.pv_pmap = pmap_kernel(); 1877 pv0.pv_va = pg->mdpage.pvh_attrs & ~(PAGE_SIZE - 1); 1878 pv0.pv_next = pv; 1879 pv0.pv_flags = PVF_REF; 1880 pv = &pv0; 1881 } 1882 1883 /* 1884 * Turn cacheing on/off for all pages. 1885 */ 1886 for (; pv; pv = pv->pv_next) { 1887 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1888 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1889 opte = *ptep; 1890 pte = opte & ~L2_S_CACHE_MASK; 1891 if (bad_alias) { 1892 pv->pv_flags |= PVF_NC; 1893 } else { 1894 pv->pv_flags &= ~PVF_NC; 1895 pte |= pte_l2_s_cache_mode; 1896 } 1897 if (opte == pte) /* only update is there's a change */ 1898 continue; 1899 1900 if (l2pte_valid(pte)) { 1901 if (PV_BEEN_EXECD(pv->pv_flags)) { 1902 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1903 } else if (PV_BEEN_REFD(pv->pv_flags)) { 1904 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 1905 } 1906 } 1907 1908 *ptep = pte; 1909 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1910 } 1911 } 1912 #endif /* PMAP_CACHE_VIPT */ 1913 1914 1915 /* 1916 * Modify pte bits for all ptes corresponding to the given physical address. 1917 * We use `maskbits' rather than `clearbits' because we're always passing 1918 * constants and the latter would require an extra inversion at run-time. 1919 */ 1920 static void 1921 pmap_clearbit(struct vm_page *pg, u_int maskbits) 1922 { 1923 struct l2_bucket *l2b; 1924 struct pv_entry *pv; 1925 pt_entry_t *ptep, npte, opte; 1926 pmap_t pm; 1927 vaddr_t va; 1928 u_int oflags; 1929 #ifdef PMAP_CACHE_VIPT 1930 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 1931 bool need_syncicache = false; 1932 bool did_syncicache = false; 1933 #endif 1934 1935 NPDEBUG(PDB_BITS, 1936 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 1937 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 1938 1939 PMAP_HEAD_TO_MAP_LOCK(); 1940 simple_lock(&pg->mdpage.pvh_slock); 1941 1942 #ifdef PMAP_CACHE_VIPT 1943 /* 1944 * If we might want to sync the I-cache and we've modified it, 1945 * then we know we definitely need to sync or discard it. 1946 */ 1947 if (want_syncicache) 1948 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 1949 #endif 1950 /* 1951 * Clear saved attributes (modify, reference) 1952 */ 1953 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1954 1955 if (pg->mdpage.pvh_list == NULL) { 1956 #ifdef PMAP_CACHE_VIPT 1957 if (need_syncicache) { 1958 /* 1959 * No one has it mapped, so just discard it. The next 1960 * exec remapping will cause it to be synced. 1961 */ 1962 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 1963 PMAPCOUNT(exec_discarded_clearbit); 1964 } 1965 #endif 1966 simple_unlock(&pg->mdpage.pvh_slock); 1967 PMAP_HEAD_TO_MAP_UNLOCK(); 1968 return; 1969 } 1970 1971 /* 1972 * Loop over all current mappings setting/clearing as appropos 1973 */ 1974 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1975 va = pv->pv_va; 1976 pm = pv->pv_pmap; 1977 oflags = pv->pv_flags; 1978 pv->pv_flags &= ~maskbits; 1979 1980 pmap_acquire_pmap_lock(pm); 1981 1982 l2b = pmap_get_l2_bucket(pm, va); 1983 KDASSERT(l2b != NULL); 1984 1985 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1986 npte = opte = *ptep; 1987 1988 NPDEBUG(PDB_BITS, 1989 printf( 1990 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 1991 pv, pv->pv_pmap, pv->pv_va, oflags)); 1992 1993 if (maskbits & (PVF_WRITE|PVF_MOD)) { 1994 #ifdef PMAP_CACHE_VIVT 1995 if ((pv->pv_flags & PVF_NC)) { 1996 /* 1997 * Entry is not cacheable: 1998 * 1999 * Don't turn caching on again if this is a 2000 * modified emulation. This would be 2001 * inconsitent with the settings created by 2002 * pmap_vac_me_harder(). Otherwise, it's safe 2003 * to re-enable cacheing. 2004 * 2005 * There's no need to call pmap_vac_me_harder() 2006 * here: all pages are losing their write 2007 * permission. 2008 */ 2009 if (maskbits & PVF_WRITE) { 2010 npte |= pte_l2_s_cache_mode; 2011 pv->pv_flags &= ~PVF_NC; 2012 } 2013 } else 2014 if (opte & L2_S_PROT_W) { 2015 /* 2016 * Entry is writable/cacheable: check if pmap 2017 * is current if it is flush it, otherwise it 2018 * won't be in the cache 2019 */ 2020 if (PV_BEEN_EXECD(oflags)) 2021 pmap_idcache_wbinv_range(pm, pv->pv_va, 2022 PAGE_SIZE); 2023 else 2024 if (PV_BEEN_REFD(oflags)) 2025 pmap_dcache_wb_range(pm, pv->pv_va, 2026 PAGE_SIZE, 2027 (maskbits & PVF_REF) ? TRUE : FALSE, 2028 FALSE); 2029 } 2030 #endif 2031 2032 /* make the pte read only */ 2033 npte &= ~L2_S_PROT_W; 2034 2035 if (maskbits & oflags & PVF_WRITE) { 2036 /* 2037 * Keep alias accounting up to date 2038 */ 2039 if (pv->pv_pmap == pmap_kernel()) { 2040 pg->mdpage.krw_mappings--; 2041 pg->mdpage.kro_mappings++; 2042 } else { 2043 pg->mdpage.urw_mappings--; 2044 pg->mdpage.uro_mappings++; 2045 } 2046 #ifdef PMAP_CACHE_VIPT 2047 if (want_syncicache) 2048 need_syncicache = true; 2049 #endif 2050 } 2051 } 2052 2053 if (maskbits & PVF_REF) { 2054 #ifdef PMAP_CACHE_VIVT 2055 if ((pv->pv_flags & PVF_NC) == 0 && 2056 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2057 l2pte_valid(npte)) { 2058 /* 2059 * Check npte here; we may have already 2060 * done the wbinv above, and the validity 2061 * of the PTE is the same for opte and 2062 * npte. 2063 */ 2064 /* XXXJRT need idcache_inv_range */ 2065 if (PV_BEEN_EXECD(oflags)) 2066 pmap_idcache_wbinv_range(pm, 2067 pv->pv_va, PAGE_SIZE); 2068 else 2069 if (PV_BEEN_REFD(oflags)) 2070 pmap_dcache_wb_range(pm, 2071 pv->pv_va, PAGE_SIZE, 2072 TRUE, TRUE); 2073 } 2074 #endif 2075 2076 /* 2077 * Make the PTE invalid so that we will take a 2078 * page fault the next time the mapping is 2079 * referenced. 2080 */ 2081 npte &= ~L2_TYPE_MASK; 2082 npte |= L2_TYPE_INV; 2083 } 2084 2085 if (npte != opte) { 2086 *ptep = npte; 2087 PTE_SYNC(ptep); 2088 /* Flush the TLB entry if a current pmap. */ 2089 if (PV_BEEN_EXECD(oflags)) 2090 pmap_tlb_flushID_SE(pm, pv->pv_va); 2091 else 2092 if (PV_BEEN_REFD(oflags)) 2093 pmap_tlb_flushD_SE(pm, pv->pv_va); 2094 } 2095 2096 pmap_release_pmap_lock(pm); 2097 2098 NPDEBUG(PDB_BITS, 2099 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2100 pm, va, opte, npte)); 2101 } 2102 2103 #ifdef PMAP_CACHE_VIPT 2104 /* 2105 * If we need to sync the I-cache and we haven't done it yet, do it. 2106 */ 2107 if (need_syncicache && !did_syncicache) { 2108 pmap_syncicache_page(pg); 2109 PMAPCOUNT(exec_synced_clearbit); 2110 } 2111 #endif 2112 2113 simple_unlock(&pg->mdpage.pvh_slock); 2114 PMAP_HEAD_TO_MAP_UNLOCK(); 2115 } 2116 2117 /* 2118 * pmap_clean_page() 2119 * 2120 * This is a local function used to work out the best strategy to clean 2121 * a single page referenced by its entry in the PV table. It's used by 2122 * pmap_copy_page, pmap_zero page and maybe some others later on. 2123 * 2124 * Its policy is effectively: 2125 * o If there are no mappings, we don't bother doing anything with the cache. 2126 * o If there is one mapping, we clean just that page. 2127 * o If there are multiple mappings, we clean the entire cache. 2128 * 2129 * So that some functions can be further optimised, it returns 0 if it didn't 2130 * clean the entire cache, or 1 if it did. 2131 * 2132 * XXX One bug in this routine is that if the pv_entry has a single page 2133 * mapped at 0x00000000 a whole cache clean will be performed rather than 2134 * just the 1 page. Since this should not occur in everyday use and if it does 2135 * it will just result in not the most efficient clean for the page. 2136 */ 2137 #ifdef PMAP_CACHE_VIVT 2138 static int 2139 pmap_clean_page(struct pv_entry *pv, boolean_t is_src) 2140 { 2141 pmap_t pm, pm_to_clean = NULL; 2142 struct pv_entry *npv; 2143 u_int cache_needs_cleaning = 0; 2144 u_int flags = 0; 2145 vaddr_t page_to_clean = 0; 2146 2147 if (pv == NULL) { 2148 /* nothing mapped in so nothing to flush */ 2149 return (0); 2150 } 2151 2152 /* 2153 * Since we flush the cache each time we change to a different 2154 * user vmspace, we only need to flush the page if it is in the 2155 * current pmap. 2156 */ 2157 if (curproc) 2158 pm = curproc->p_vmspace->vm_map.pmap; 2159 else 2160 pm = pmap_kernel(); 2161 2162 for (npv = pv; npv; npv = npv->pv_next) { 2163 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2164 flags |= npv->pv_flags; 2165 /* 2166 * The page is mapped non-cacheable in 2167 * this map. No need to flush the cache. 2168 */ 2169 if (npv->pv_flags & PVF_NC) { 2170 #ifdef DIAGNOSTIC 2171 if (cache_needs_cleaning) 2172 panic("pmap_clean_page: " 2173 "cache inconsistency"); 2174 #endif 2175 break; 2176 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2177 continue; 2178 if (cache_needs_cleaning) { 2179 page_to_clean = 0; 2180 break; 2181 } else { 2182 page_to_clean = npv->pv_va; 2183 pm_to_clean = npv->pv_pmap; 2184 } 2185 cache_needs_cleaning = 1; 2186 } 2187 } 2188 2189 if (page_to_clean) { 2190 if (PV_BEEN_EXECD(flags)) 2191 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2192 PAGE_SIZE); 2193 else 2194 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2195 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2196 } else if (cache_needs_cleaning) { 2197 if (PV_BEEN_EXECD(flags)) 2198 pmap_idcache_wbinv_all(pm); 2199 else 2200 pmap_dcache_wbinv_all(pm); 2201 return (1); 2202 } 2203 return (0); 2204 } 2205 #endif 2206 2207 #ifdef PMAP_CACHE_VIPT 2208 /* 2209 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2210 * right cache alias to make sure we flush the right stuff. 2211 */ 2212 void 2213 pmap_syncicache_page(struct vm_page *pg) 2214 { 2215 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2216 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2217 2218 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2219 pg, pg->mdpage.pvh_attrs)); 2220 /* 2221 * No need to clean the page if it's non-cached. 2222 */ 2223 if (pg->mdpage.pvh_attrs & PVF_NC) 2224 return; 2225 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2226 2227 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2228 /* 2229 * Set up a PTE with the right coloring to flush existing cache lines. 2230 */ 2231 *ptep = L2_S_PROTO | 2232 VM_PAGE_TO_PHYS(pg) 2233 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2234 | pte_l2_s_cache_mode; 2235 PTE_SYNC(ptep); 2236 2237 /* 2238 * Flush it. 2239 */ 2240 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2241 /* 2242 * Unmap the page. 2243 */ 2244 *ptep = 0; 2245 PTE_SYNC(ptep); 2246 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2247 2248 pg->mdpage.pvh_attrs |= PVF_EXEC; 2249 PMAPCOUNT(exec_synced); 2250 } 2251 2252 void 2253 pmap_flush_page(struct vm_page *pg) 2254 { 2255 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2256 const size_t pte_offset = va_offset >> PGSHIFT; 2257 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2258 2259 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2260 2261 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2262 pg, pg->mdpage.pvh_attrs)); 2263 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2264 /* 2265 * Set up a PTE with the right coloring to flush existing cache entries. 2266 */ 2267 *ptep = L2_S_PROTO 2268 | VM_PAGE_TO_PHYS(pg) 2269 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2270 | pte_l2_s_cache_mode; 2271 PTE_SYNC(ptep); 2272 2273 /* 2274 * Flush it. 2275 */ 2276 cpu_idcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 2277 2278 /* 2279 * Unmap the page. 2280 */ 2281 *ptep = 0; 2282 PTE_SYNC(ptep); 2283 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2284 } 2285 #endif /* PMAP_CACHE_VIPT */ 2286 2287 /* 2288 * Routine: pmap_page_remove 2289 * Function: 2290 * Removes this physical page from 2291 * all physical maps in which it resides. 2292 * Reflects back modify bits to the pager. 2293 */ 2294 static void 2295 pmap_page_remove(struct vm_page *pg) 2296 { 2297 struct l2_bucket *l2b; 2298 struct pv_entry *pv, *npv; 2299 pmap_t pm, curpm; 2300 pt_entry_t *ptep, pte; 2301 boolean_t flush; 2302 u_int flags; 2303 2304 NPDEBUG(PDB_FOLLOW, 2305 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2306 VM_PAGE_TO_PHYS(pg))); 2307 2308 PMAP_HEAD_TO_MAP_LOCK(); 2309 simple_lock(&pg->mdpage.pvh_slock); 2310 2311 pv = pg->mdpage.pvh_list; 2312 if (pv == NULL) { 2313 #ifdef PMAP_CACHE_VIPT 2314 /* 2315 * We *know* the page contents are about to be replaced. 2316 * Discard the exec contents 2317 */ 2318 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2319 PMAPCOUNT(exec_discarded_page_protect); 2320 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2321 #endif 2322 simple_unlock(&pg->mdpage.pvh_slock); 2323 PMAP_HEAD_TO_MAP_UNLOCK(); 2324 return; 2325 } 2326 #ifdef PMAP_CACHE_VIPT 2327 KASSERT(pmap_is_page_colored_p(pg)); 2328 #endif 2329 2330 /* 2331 * Clear alias counts 2332 */ 2333 pg->mdpage.k_mappings = 0; 2334 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2335 2336 flush = FALSE; 2337 flags = 0; 2338 if (curproc) 2339 curpm = curproc->p_vmspace->vm_map.pmap; 2340 else 2341 curpm = pmap_kernel(); 2342 2343 #ifdef PMAP_CACHE_VIVT 2344 pmap_clean_page(pv, FALSE); 2345 #endif 2346 2347 while (pv) { 2348 pm = pv->pv_pmap; 2349 if (flush == FALSE && (pm == curpm || pm == pmap_kernel())) 2350 flush = TRUE; 2351 2352 if (pm == pmap_kernel()) 2353 PMAPCOUNT(kernel_unmappings); 2354 PMAPCOUNT(unmappings); 2355 2356 pmap_acquire_pmap_lock(pm); 2357 2358 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2359 KDASSERT(l2b != NULL); 2360 2361 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2362 pte = *ptep; 2363 2364 /* 2365 * Update statistics 2366 */ 2367 --pm->pm_stats.resident_count; 2368 2369 /* Wired bit */ 2370 if (pv->pv_flags & PVF_WIRED) 2371 --pm->pm_stats.wired_count; 2372 2373 flags |= pv->pv_flags; 2374 2375 /* 2376 * Invalidate the PTEs. 2377 */ 2378 *ptep = 0; 2379 PTE_SYNC_CURRENT(pm, ptep); 2380 pmap_free_l2_bucket(pm, l2b, 1); 2381 2382 npv = pv->pv_next; 2383 pool_put(&pmap_pv_pool, pv); 2384 pv = npv; 2385 #ifdef PMAP_CACHE_VIPT 2386 /* 2387 * If this is the last pv entry and there is a kenter alias 2388 * we must call pmap_me_me_harder to restore its cacheability. 2389 * We need a pmap (to indicate we are removing a normal 2390 * mapping) so use this one. 2391 */ 2392 if (pv == NULL) { 2393 pg->mdpage.pvh_list = NULL; 2394 if (pg->mdpage.pvh_attrs & PVF_KENTRY) 2395 pmap_vac_me_harder(pg, pm, 0); 2396 } 2397 #endif 2398 pmap_release_pmap_lock(pm); 2399 } 2400 #ifdef PMAP_CACHE_VIPT 2401 /* 2402 * Since there are now no mappings, there isn't reason to mark it 2403 * as uncached. Its EXEC cache is also gone. 2404 */ 2405 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2406 PMAPCOUNT(exec_discarded_page_protect); 2407 pg->mdpage.pvh_attrs &= ~(PVF_NC|PVF_EXEC); 2408 #endif 2409 #ifdef PMAP_CACHE_VIVT 2410 pg->mdpage.pvh_list = NULL; 2411 #endif 2412 simple_unlock(&pg->mdpage.pvh_slock); 2413 PMAP_HEAD_TO_MAP_UNLOCK(); 2414 2415 if (flush) { 2416 /* 2417 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2418 * would need a subsequent call to pmap_update() to ensure 2419 * curpm->pm_cstate.cs_all is reset. Our callers are not 2420 * required to do that (see pmap(9)), so we can't modify 2421 * the current pmap's state. 2422 */ 2423 if (PV_BEEN_EXECD(flags)) 2424 cpu_tlb_flushID(); 2425 else 2426 cpu_tlb_flushD(); 2427 } 2428 cpu_cpwait(); 2429 } 2430 2431 /* 2432 * pmap_t pmap_create(void) 2433 * 2434 * Create a new pmap structure from scratch. 2435 */ 2436 pmap_t 2437 pmap_create(void) 2438 { 2439 pmap_t pm; 2440 2441 pm = pool_cache_get(&pmap_pmap_cache, PR_WAITOK); 2442 2443 simple_lock_init(&pm->pm_lock); 2444 pm->pm_obj.pgops = NULL; /* currently not a mappable object */ 2445 TAILQ_INIT(&pm->pm_obj.memq); 2446 pm->pm_obj.uo_npages = 0; 2447 pm->pm_obj.uo_refs = 1; 2448 pm->pm_stats.wired_count = 0; 2449 pm->pm_stats.resident_count = 1; 2450 pm->pm_cstate.cs_all = 0; 2451 pmap_alloc_l1(pm); 2452 2453 /* 2454 * Note: The pool cache ensures that the pm_l2[] array is already 2455 * initialised to zero. 2456 */ 2457 2458 pmap_pinit(pm); 2459 2460 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2461 2462 return (pm); 2463 } 2464 2465 /* 2466 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2467 * int flags) 2468 * 2469 * Insert the given physical page (p) at 2470 * the specified virtual address (v) in the 2471 * target physical map with the protection requested. 2472 * 2473 * NB: This is the only routine which MAY NOT lazy-evaluate 2474 * or lose information. That is, this routine must actually 2475 * insert this page into the given map NOW. 2476 */ 2477 int 2478 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 2479 { 2480 struct l2_bucket *l2b; 2481 struct vm_page *pg, *opg; 2482 struct pv_entry *pve; 2483 pt_entry_t *ptep, npte, opte; 2484 u_int nflags; 2485 u_int oflags; 2486 2487 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2488 2489 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2490 KDASSERT(((va | pa) & PGOFSET) == 0); 2491 2492 /* 2493 * Get a pointer to the page. Later on in this function, we 2494 * test for a managed page by checking pg != NULL. 2495 */ 2496 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2497 2498 nflags = 0; 2499 if (prot & VM_PROT_WRITE) 2500 nflags |= PVF_WRITE; 2501 if (prot & VM_PROT_EXECUTE) 2502 nflags |= PVF_EXEC; 2503 if (flags & PMAP_WIRED) 2504 nflags |= PVF_WIRED; 2505 2506 PMAP_MAP_TO_HEAD_LOCK(); 2507 pmap_acquire_pmap_lock(pm); 2508 2509 /* 2510 * Fetch the L2 bucket which maps this page, allocating one if 2511 * necessary for user pmaps. 2512 */ 2513 if (pm == pmap_kernel()) 2514 l2b = pmap_get_l2_bucket(pm, va); 2515 else 2516 l2b = pmap_alloc_l2_bucket(pm, va); 2517 if (l2b == NULL) { 2518 if (flags & PMAP_CANFAIL) { 2519 pmap_release_pmap_lock(pm); 2520 PMAP_MAP_TO_HEAD_UNLOCK(); 2521 return (ENOMEM); 2522 } 2523 panic("pmap_enter: failed to allocate L2 bucket"); 2524 } 2525 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2526 opte = *ptep; 2527 npte = pa; 2528 oflags = 0; 2529 2530 if (opte) { 2531 /* 2532 * There is already a mapping at this address. 2533 * If the physical address is different, lookup the 2534 * vm_page. 2535 */ 2536 if (l2pte_pa(opte) != pa) 2537 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2538 else 2539 opg = pg; 2540 } else 2541 opg = NULL; 2542 2543 if (pg) { 2544 /* 2545 * This is to be a managed mapping. 2546 */ 2547 if ((flags & VM_PROT_ALL) || 2548 (pg->mdpage.pvh_attrs & PVF_REF)) { 2549 /* 2550 * - The access type indicates that we don't need 2551 * to do referenced emulation. 2552 * OR 2553 * - The physical page has already been referenced 2554 * so no need to re-do referenced emulation here. 2555 */ 2556 npte |= L2_S_PROTO; 2557 2558 nflags |= PVF_REF; 2559 2560 if ((prot & VM_PROT_WRITE) != 0 && 2561 ((flags & VM_PROT_WRITE) != 0 || 2562 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2563 /* 2564 * This is a writable mapping, and the 2565 * page's mod state indicates it has 2566 * already been modified. Make it 2567 * writable from the outset. 2568 */ 2569 npte |= L2_S_PROT_W; 2570 nflags |= PVF_MOD; 2571 } 2572 } else { 2573 /* 2574 * Need to do page referenced emulation. 2575 */ 2576 npte |= L2_TYPE_INV; 2577 } 2578 2579 npte |= pte_l2_s_cache_mode; 2580 2581 if (pg == opg) { 2582 /* 2583 * We're changing the attrs of an existing mapping. 2584 */ 2585 simple_lock(&pg->mdpage.pvh_slock); 2586 oflags = pmap_modify_pv(pg, pm, va, 2587 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2588 PVF_MOD | PVF_REF, nflags); 2589 simple_unlock(&pg->mdpage.pvh_slock); 2590 2591 #ifdef PMAP_CACHE_VIVT 2592 /* 2593 * We may need to flush the cache if we're 2594 * doing rw-ro... 2595 */ 2596 if (pm->pm_cstate.cs_cache_d && 2597 (oflags & PVF_NC) == 0 && 2598 (opte & L2_S_PROT_W) != 0 && 2599 (prot & VM_PROT_WRITE) == 0) 2600 cpu_dcache_wb_range(va, PAGE_SIZE); 2601 #endif 2602 } else { 2603 /* 2604 * New mapping, or changing the backing page 2605 * of an existing mapping. 2606 */ 2607 if (opg) { 2608 /* 2609 * Replacing an existing mapping with a new one. 2610 * It is part of our managed memory so we 2611 * must remove it from the PV list 2612 */ 2613 simple_lock(&opg->mdpage.pvh_slock); 2614 pve = pmap_remove_pv(opg, pm, va, 0); 2615 pmap_vac_me_harder(opg, pm, 0); 2616 simple_unlock(&opg->mdpage.pvh_slock); 2617 oflags = pve->pv_flags; 2618 2619 #ifdef PMAP_CACHE_VIVT 2620 /* 2621 * If the old mapping was valid (ref/mod 2622 * emulation creates 'invalid' mappings 2623 * initially) then make sure to frob 2624 * the cache. 2625 */ 2626 if ((oflags & PVF_NC) == 0 && 2627 l2pte_valid(opte)) { 2628 if (PV_BEEN_EXECD(oflags)) { 2629 pmap_idcache_wbinv_range(pm, va, 2630 PAGE_SIZE); 2631 } else 2632 if (PV_BEEN_REFD(oflags)) { 2633 pmap_dcache_wb_range(pm, va, 2634 PAGE_SIZE, TRUE, 2635 (oflags & PVF_WRITE) == 0); 2636 } 2637 } 2638 #endif 2639 } else 2640 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2641 if ((flags & PMAP_CANFAIL) == 0) 2642 panic("pmap_enter: no pv entries"); 2643 2644 if (pm != pmap_kernel()) 2645 pmap_free_l2_bucket(pm, l2b, 0); 2646 pmap_release_pmap_lock(pm); 2647 PMAP_MAP_TO_HEAD_UNLOCK(); 2648 NPDEBUG(PDB_ENTER, 2649 printf("pmap_enter: ENOMEM\n")); 2650 return (ENOMEM); 2651 } 2652 2653 pmap_enter_pv(pg, pve, pm, va, nflags); 2654 } 2655 } else { 2656 /* 2657 * We're mapping an unmanaged page. 2658 * These are always readable, and possibly writable, from 2659 * the get go as we don't need to track ref/mod status. 2660 */ 2661 npte |= L2_S_PROTO; 2662 if (prot & VM_PROT_WRITE) 2663 npte |= L2_S_PROT_W; 2664 2665 /* 2666 * Make sure the vector table is mapped cacheable 2667 */ 2668 if (pm != pmap_kernel() && va == vector_page) 2669 npte |= pte_l2_s_cache_mode; 2670 2671 if (opg) { 2672 /* 2673 * Looks like there's an existing 'managed' mapping 2674 * at this address. 2675 */ 2676 simple_lock(&opg->mdpage.pvh_slock); 2677 pve = pmap_remove_pv(opg, pm, va, 0); 2678 pmap_vac_me_harder(opg, pm, 0); 2679 simple_unlock(&opg->mdpage.pvh_slock); 2680 oflags = pve->pv_flags; 2681 2682 #ifdef PMAP_CACHE_VIVT 2683 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2684 if (PV_BEEN_EXECD(oflags)) 2685 pmap_idcache_wbinv_range(pm, va, 2686 PAGE_SIZE); 2687 else 2688 if (PV_BEEN_REFD(oflags)) 2689 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2690 TRUE, (oflags & PVF_WRITE) == 0); 2691 } 2692 #endif 2693 pool_put(&pmap_pv_pool, pve); 2694 } 2695 } 2696 2697 /* 2698 * Make sure userland mappings get the right permissions 2699 */ 2700 if (pm != pmap_kernel() && va != vector_page) 2701 npte |= L2_S_PROT_U; 2702 2703 /* 2704 * Keep the stats up to date 2705 */ 2706 if (opte == 0) { 2707 l2b->l2b_occupancy++; 2708 pm->pm_stats.resident_count++; 2709 } 2710 2711 NPDEBUG(PDB_ENTER, 2712 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2713 2714 /* 2715 * If this is just a wiring change, the two PTEs will be 2716 * identical, so there's no need to update the page table. 2717 */ 2718 if (npte != opte) { 2719 boolean_t is_cached = pmap_is_cached(pm); 2720 2721 *ptep = npte; 2722 if (is_cached) { 2723 /* 2724 * We only need to frob the cache/tlb if this pmap 2725 * is current 2726 */ 2727 PTE_SYNC(ptep); 2728 if (va != vector_page && l2pte_valid(npte)) { 2729 /* 2730 * This mapping is likely to be accessed as 2731 * soon as we return to userland. Fix up the 2732 * L1 entry to avoid taking another 2733 * page/domain fault. 2734 */ 2735 pd_entry_t *pl1pd, l1pd; 2736 2737 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2738 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2739 L1_C_PROTO; 2740 if (*pl1pd != l1pd) { 2741 *pl1pd = l1pd; 2742 PTE_SYNC(pl1pd); 2743 } 2744 } 2745 } 2746 2747 if (PV_BEEN_EXECD(oflags)) 2748 pmap_tlb_flushID_SE(pm, va); 2749 else 2750 if (PV_BEEN_REFD(oflags)) 2751 pmap_tlb_flushD_SE(pm, va); 2752 2753 NPDEBUG(PDB_ENTER, 2754 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2755 is_cached, pm->pm_cstate.cs_all)); 2756 2757 if (pg != NULL) { 2758 simple_lock(&pg->mdpage.pvh_slock); 2759 pmap_vac_me_harder(pg, pm, va); 2760 simple_unlock(&pg->mdpage.pvh_slock); 2761 } 2762 } 2763 2764 pmap_release_pmap_lock(pm); 2765 PMAP_MAP_TO_HEAD_UNLOCK(); 2766 2767 return (0); 2768 } 2769 2770 /* 2771 * pmap_remove() 2772 * 2773 * pmap_remove is responsible for nuking a number of mappings for a range 2774 * of virtual address space in the current pmap. To do this efficiently 2775 * is interesting, because in a number of cases a wide virtual address 2776 * range may be supplied that contains few actual mappings. So, the 2777 * optimisations are: 2778 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 2779 * 2. Build up a list of pages we've hit, up to a maximum, so we can 2780 * maybe do just a partial cache clean. This path of execution is 2781 * complicated by the fact that the cache must be flushed _before_ 2782 * the PTE is nuked, being a VAC :-) 2783 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 2784 * all invalidations until pmap_update(), since pmap_remove_all() has 2785 * already flushed the cache. 2786 * 4. Maybe later fast-case a single page, but I don't think this is 2787 * going to make _that_ much difference overall. 2788 */ 2789 2790 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 2791 2792 void 2793 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 2794 { 2795 struct l2_bucket *l2b; 2796 vaddr_t next_bucket; 2797 pt_entry_t *ptep; 2798 u_int cleanlist_idx, total, cnt; 2799 struct { 2800 vaddr_t va; 2801 pt_entry_t *ptep; 2802 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 2803 u_int mappings, is_exec, is_refd; 2804 2805 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 2806 "eva=%08lx\n", pm, sva, eva)); 2807 2808 /* 2809 * we lock in the pmap => pv_head direction 2810 */ 2811 PMAP_MAP_TO_HEAD_LOCK(); 2812 pmap_acquire_pmap_lock(pm); 2813 2814 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 2815 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2816 if (pm->pm_cstate.cs_tlb == 0) 2817 pm->pm_remove_all = TRUE; 2818 } else 2819 cleanlist_idx = 0; 2820 2821 total = 0; 2822 2823 while (sva < eva) { 2824 /* 2825 * Do one L2 bucket's worth at a time. 2826 */ 2827 next_bucket = L2_NEXT_BUCKET(sva); 2828 if (next_bucket > eva) 2829 next_bucket = eva; 2830 2831 l2b = pmap_get_l2_bucket(pm, sva); 2832 if (l2b == NULL) { 2833 sva = next_bucket; 2834 continue; 2835 } 2836 2837 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2838 2839 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 2840 struct vm_page *pg; 2841 pt_entry_t pte; 2842 paddr_t pa; 2843 2844 pte = *ptep; 2845 2846 if (pte == 0) { 2847 /* Nothing here, move along */ 2848 continue; 2849 } 2850 2851 pa = l2pte_pa(pte); 2852 is_exec = 0; 2853 is_refd = 1; 2854 2855 /* 2856 * Update flags. In a number of circumstances, 2857 * we could cluster a lot of these and do a 2858 * number of sequential pages in one go. 2859 */ 2860 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 2861 struct pv_entry *pve; 2862 simple_lock(&pg->mdpage.pvh_slock); 2863 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 2864 pmap_vac_me_harder(pg, pm, 0); 2865 simple_unlock(&pg->mdpage.pvh_slock); 2866 if (pve != NULL) { 2867 if (pm->pm_remove_all == FALSE) { 2868 is_exec = 2869 PV_BEEN_EXECD(pve->pv_flags); 2870 is_refd = 2871 PV_BEEN_REFD(pve->pv_flags); 2872 } 2873 pool_put(&pmap_pv_pool, pve); 2874 } else 2875 if (skip_wired) { 2876 /* The mapping is wired. Skip it */ 2877 continue; 2878 } 2879 } else 2880 if (skip_wired) { 2881 /* Unmanaged pages are always wired. */ 2882 continue; 2883 } 2884 2885 mappings++; 2886 2887 if (!l2pte_valid(pte)) { 2888 /* 2889 * Ref/Mod emulation is still active for this 2890 * mapping, therefore it is has not yet been 2891 * accessed. No need to frob the cache/tlb. 2892 */ 2893 *ptep = 0; 2894 PTE_SYNC_CURRENT(pm, ptep); 2895 continue; 2896 } 2897 2898 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 2899 /* Add to the clean list. */ 2900 cleanlist[cleanlist_idx].ptep = ptep; 2901 cleanlist[cleanlist_idx].va = 2902 sva | (is_exec & 1); 2903 cleanlist_idx++; 2904 } else 2905 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 2906 /* Nuke everything if needed. */ 2907 #ifdef PMAP_CACHE_VIVT 2908 pmap_idcache_wbinv_all(pm); 2909 #endif 2910 pmap_tlb_flushID(pm); 2911 2912 /* 2913 * Roll back the previous PTE list, 2914 * and zero out the current PTE. 2915 */ 2916 for (cnt = 0; 2917 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 2918 *cleanlist[cnt].ptep = 0; 2919 } 2920 *ptep = 0; 2921 PTE_SYNC(ptep); 2922 cleanlist_idx++; 2923 pm->pm_remove_all = TRUE; 2924 } else { 2925 *ptep = 0; 2926 PTE_SYNC(ptep); 2927 if (pm->pm_remove_all == FALSE) { 2928 if (is_exec) 2929 pmap_tlb_flushID_SE(pm, sva); 2930 else 2931 if (is_refd) 2932 pmap_tlb_flushD_SE(pm, sva); 2933 } 2934 } 2935 } 2936 2937 /* 2938 * Deal with any left overs 2939 */ 2940 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 2941 total += cleanlist_idx; 2942 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 2943 if (pm->pm_cstate.cs_all != 0) { 2944 vaddr_t clva = cleanlist[cnt].va & ~1; 2945 if (cleanlist[cnt].va & 1) { 2946 #ifdef PMAP_CACHE_VIVT 2947 pmap_idcache_wbinv_range(pm, 2948 clva, PAGE_SIZE); 2949 #endif 2950 pmap_tlb_flushID_SE(pm, clva); 2951 } else { 2952 #ifdef PMAP_CACHE_VIVT 2953 pmap_dcache_wb_range(pm, 2954 clva, PAGE_SIZE, TRUE, 2955 FALSE); 2956 #endif 2957 pmap_tlb_flushD_SE(pm, clva); 2958 } 2959 } 2960 *cleanlist[cnt].ptep = 0; 2961 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 2962 } 2963 2964 /* 2965 * If it looks like we're removing a whole bunch 2966 * of mappings, it's faster to just write-back 2967 * the whole cache now and defer TLB flushes until 2968 * pmap_update() is called. 2969 */ 2970 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 2971 cleanlist_idx = 0; 2972 else { 2973 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2974 #ifdef PMAP_CACHE_VIVT 2975 pmap_idcache_wbinv_all(pm); 2976 #endif 2977 pm->pm_remove_all = TRUE; 2978 } 2979 } 2980 2981 pmap_free_l2_bucket(pm, l2b, mappings); 2982 pm->pm_stats.resident_count -= mappings; 2983 } 2984 2985 pmap_release_pmap_lock(pm); 2986 PMAP_MAP_TO_HEAD_UNLOCK(); 2987 } 2988 2989 /* 2990 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 2991 * 2992 * We assume there is already sufficient KVM space available 2993 * to do this, as we can't allocate L2 descriptor tables/metadata 2994 * from here. 2995 */ 2996 void 2997 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 2998 { 2999 struct l2_bucket *l2b; 3000 pt_entry_t *ptep, opte; 3001 #ifdef PMAP_CACHE_VIPT 3002 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3003 struct vm_page *opg; 3004 #endif 3005 3006 3007 NPDEBUG(PDB_KENTER, 3008 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3009 va, pa, prot)); 3010 3011 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3012 KDASSERT(l2b != NULL); 3013 3014 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3015 opte = *ptep; 3016 3017 if (opte == 0) { 3018 PMAPCOUNT(kenter_mappings); 3019 l2b->l2b_occupancy++; 3020 } else { 3021 PMAPCOUNT(kenter_remappings); 3022 #ifdef PMAP_CACHE_VIPT 3023 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3024 if (opg) { 3025 KASSERT(opg != pg); 3026 simple_lock(&opg->mdpage.pvh_slock); 3027 KASSERT(opg->mdpage.pvh_attrs & PVF_KENTRY); 3028 if (PV_IS_EXEC_P(opg->mdpage.pvh_attrs) 3029 && !(opg->mdpage.pvh_attrs & PVF_NC)) { 3030 if (opg->mdpage.pvh_list == NULL) { 3031 opg->mdpage.pvh_attrs &= ~PVF_EXEC; 3032 PMAPCOUNT(exec_discarded_kremove); 3033 } else { 3034 pmap_syncicache_page(opg); 3035 PMAPCOUNT(exec_synced_kremove); 3036 } 3037 } 3038 KASSERT(opg->mdpage.pvh_attrs | (PVF_COLORED|PVF_NC)); 3039 opg->mdpage.pvh_attrs &= ~PVF_KENTRY; 3040 pmap_vac_me_harder(opg, NULL, 0); 3041 simple_unlock(&opg->mdpage.pvh_slock); 3042 } 3043 #endif 3044 if (l2pte_valid(opte)) { 3045 #ifdef PMAP_CACHE_VIVT 3046 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3047 #endif 3048 cpu_tlb_flushD_SE(va); 3049 cpu_cpwait(); 3050 } 3051 } 3052 3053 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3054 pte_l2_s_cache_mode; 3055 PTE_SYNC(ptep); 3056 3057 #ifdef PMAP_CACHE_VIPT 3058 if (pg) { 3059 simple_lock(&pg->mdpage.pvh_slock); 3060 KASSERT((pg->mdpage.pvh_attrs & PVF_KENTRY) == 0); 3061 pg->mdpage.pvh_attrs |= PVF_KENTRY; 3062 pmap_vac_me_harder(pg, NULL, va); 3063 simple_unlock(&pg->mdpage.pvh_slock); 3064 } 3065 #endif 3066 } 3067 3068 void 3069 pmap_kremove(vaddr_t va, vsize_t len) 3070 { 3071 struct l2_bucket *l2b; 3072 pt_entry_t *ptep, *sptep, opte; 3073 vaddr_t next_bucket, eva; 3074 u_int mappings; 3075 #ifdef PMAP_CACHE_VIPT 3076 struct vm_page *opg; 3077 #endif 3078 3079 PMAPCOUNT(kenter_unmappings); 3080 3081 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3082 va, len)); 3083 3084 eva = va + len; 3085 3086 while (va < eva) { 3087 next_bucket = L2_NEXT_BUCKET(va); 3088 if (next_bucket > eva) 3089 next_bucket = eva; 3090 3091 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3092 KDASSERT(l2b != NULL); 3093 3094 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3095 mappings = 0; 3096 3097 while (va < next_bucket) { 3098 opte = *ptep; 3099 #ifdef PMAP_CACHE_VIPT 3100 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3101 if (opg) { 3102 simple_lock(&opg->mdpage.pvh_slock); 3103 KASSERT(opg->mdpage.pvh_attrs & PVF_KENTRY); 3104 if (PV_IS_EXEC_P(opg->mdpage.pvh_attrs) 3105 && !(opg->mdpage.pvh_attrs & PVF_NC)) { 3106 if (opg->mdpage.pvh_list == NULL) { 3107 opg->mdpage.pvh_attrs &= 3108 ~PVF_EXEC; 3109 PMAPCOUNT(exec_discarded_kremove); 3110 } else { 3111 pmap_syncicache_page(opg); 3112 PMAPCOUNT(exec_synced_kremove); 3113 } 3114 } 3115 KASSERT(opg->mdpage.pvh_attrs | (PVF_COLORED|PVF_NC)); 3116 opg->mdpage.pvh_attrs &= ~PVF_KENTRY; 3117 pmap_vac_me_harder(opg, NULL, 0); 3118 simple_unlock(&opg->mdpage.pvh_slock); 3119 } 3120 #endif 3121 if (l2pte_valid(opte)) { 3122 #ifdef PMAP_CACHE_VIVT 3123 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3124 #endif 3125 cpu_tlb_flushD_SE(va); 3126 } 3127 if (opte) { 3128 *ptep = 0; 3129 mappings++; 3130 } 3131 va += PAGE_SIZE; 3132 ptep++; 3133 } 3134 KDASSERT(mappings <= l2b->l2b_occupancy); 3135 l2b->l2b_occupancy -= mappings; 3136 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3137 } 3138 cpu_cpwait(); 3139 } 3140 3141 boolean_t 3142 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3143 { 3144 struct l2_dtable *l2; 3145 pd_entry_t *pl1pd, l1pd; 3146 pt_entry_t *ptep, pte; 3147 paddr_t pa; 3148 u_int l1idx; 3149 3150 pmap_acquire_pmap_lock(pm); 3151 3152 l1idx = L1_IDX(va); 3153 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3154 l1pd = *pl1pd; 3155 3156 if (l1pte_section_p(l1pd)) { 3157 /* 3158 * These should only happen for pmap_kernel() 3159 */ 3160 KDASSERT(pm == pmap_kernel()); 3161 pmap_release_pmap_lock(pm); 3162 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3163 } else { 3164 /* 3165 * Note that we can't rely on the validity of the L1 3166 * descriptor as an indication that a mapping exists. 3167 * We have to look it up in the L2 dtable. 3168 */ 3169 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3170 3171 if (l2 == NULL || 3172 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3173 pmap_release_pmap_lock(pm); 3174 return (FALSE); 3175 } 3176 3177 ptep = &ptep[l2pte_index(va)]; 3178 pte = *ptep; 3179 pmap_release_pmap_lock(pm); 3180 3181 if (pte == 0) 3182 return (FALSE); 3183 3184 switch (pte & L2_TYPE_MASK) { 3185 case L2_TYPE_L: 3186 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3187 break; 3188 3189 default: 3190 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3191 break; 3192 } 3193 } 3194 3195 if (pap != NULL) 3196 *pap = pa; 3197 3198 return (TRUE); 3199 } 3200 3201 void 3202 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3203 { 3204 struct l2_bucket *l2b; 3205 pt_entry_t *ptep, pte; 3206 vaddr_t next_bucket; 3207 u_int flags; 3208 u_int clr_mask; 3209 int flush; 3210 3211 NPDEBUG(PDB_PROTECT, 3212 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3213 pm, sva, eva, prot)); 3214 3215 if ((prot & VM_PROT_READ) == 0) { 3216 pmap_remove(pm, sva, eva); 3217 return; 3218 } 3219 3220 if (prot & VM_PROT_WRITE) { 3221 /* 3222 * If this is a read->write transition, just ignore it and let 3223 * uvm_fault() take care of it later. 3224 */ 3225 return; 3226 } 3227 3228 PMAP_MAP_TO_HEAD_LOCK(); 3229 pmap_acquire_pmap_lock(pm); 3230 3231 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3232 flags = 0; 3233 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3234 3235 while (sva < eva) { 3236 next_bucket = L2_NEXT_BUCKET(sva); 3237 if (next_bucket > eva) 3238 next_bucket = eva; 3239 3240 l2b = pmap_get_l2_bucket(pm, sva); 3241 if (l2b == NULL) { 3242 sva = next_bucket; 3243 continue; 3244 } 3245 3246 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3247 3248 while (sva < next_bucket) { 3249 pte = *ptep; 3250 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3251 struct vm_page *pg; 3252 u_int f; 3253 3254 #ifdef PMAP_CACHE_VIVT 3255 /* 3256 * OK, at this point, we know we're doing 3257 * write-protect operation. If the pmap is 3258 * active, write-back the page. 3259 */ 3260 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3261 FALSE, FALSE); 3262 #endif 3263 3264 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3265 pte &= ~L2_S_PROT_W; 3266 *ptep = pte; 3267 PTE_SYNC(ptep); 3268 3269 if (pg != NULL) { 3270 simple_lock(&pg->mdpage.pvh_slock); 3271 f = pmap_modify_pv(pg, pm, sva, 3272 clr_mask, 0); 3273 pmap_vac_me_harder(pg, pm, sva); 3274 simple_unlock(&pg->mdpage.pvh_slock); 3275 } else 3276 f = PVF_REF | PVF_EXEC; 3277 3278 if (flush >= 0) { 3279 flush++; 3280 flags |= f; 3281 } else 3282 if (PV_BEEN_EXECD(f)) 3283 pmap_tlb_flushID_SE(pm, sva); 3284 else 3285 if (PV_BEEN_REFD(f)) 3286 pmap_tlb_flushD_SE(pm, sva); 3287 } 3288 3289 sva += PAGE_SIZE; 3290 ptep++; 3291 } 3292 } 3293 3294 pmap_release_pmap_lock(pm); 3295 PMAP_MAP_TO_HEAD_UNLOCK(); 3296 3297 if (flush) { 3298 if (PV_BEEN_EXECD(flags)) 3299 pmap_tlb_flushID(pm); 3300 else 3301 if (PV_BEEN_REFD(flags)) 3302 pmap_tlb_flushD(pm); 3303 } 3304 } 3305 3306 void 3307 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3308 { 3309 struct l2_bucket *l2b; 3310 pt_entry_t *ptep; 3311 vaddr_t next_bucket; 3312 3313 NPDEBUG(PDB_EXEC, 3314 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3315 pm, sva, eva)); 3316 3317 PMAP_MAP_TO_HEAD_LOCK(); 3318 pmap_acquire_pmap_lock(pm); 3319 3320 while (sva < eva) { 3321 next_bucket = L2_NEXT_BUCKET(sva); 3322 if (next_bucket > eva) 3323 next_bucket = eva; 3324 3325 l2b = pmap_get_l2_bucket(pm, sva); 3326 if (l2b == NULL) { 3327 sva = next_bucket; 3328 continue; 3329 } 3330 3331 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3332 sva < next_bucket; 3333 sva += PAGE_SIZE, ptep++) { 3334 if (l2pte_valid(*ptep)) { 3335 cpu_icache_sync_range(sva, 3336 min(PAGE_SIZE, eva - sva)); 3337 } 3338 } 3339 } 3340 3341 pmap_release_pmap_lock(pm); 3342 PMAP_MAP_TO_HEAD_UNLOCK(); 3343 } 3344 3345 void 3346 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3347 { 3348 3349 NPDEBUG(PDB_PROTECT, 3350 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3351 pg, VM_PAGE_TO_PHYS(pg), prot)); 3352 3353 switch(prot) { 3354 return; 3355 case VM_PROT_READ|VM_PROT_WRITE: 3356 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3357 pmap_clearbit(pg, PVF_EXEC); 3358 break; 3359 #endif 3360 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3361 break; 3362 3363 case VM_PROT_READ: 3364 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3365 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3366 break; 3367 #endif 3368 case VM_PROT_READ|VM_PROT_EXECUTE: 3369 pmap_clearbit(pg, PVF_WRITE); 3370 break; 3371 3372 default: 3373 pmap_page_remove(pg); 3374 break; 3375 } 3376 } 3377 3378 /* 3379 * pmap_clear_modify: 3380 * 3381 * Clear the "modified" attribute for a page. 3382 */ 3383 boolean_t 3384 pmap_clear_modify(struct vm_page *pg) 3385 { 3386 boolean_t rv; 3387 3388 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3389 rv = TRUE; 3390 pmap_clearbit(pg, PVF_MOD); 3391 } else 3392 rv = FALSE; 3393 3394 return (rv); 3395 } 3396 3397 /* 3398 * pmap_clear_reference: 3399 * 3400 * Clear the "referenced" attribute for a page. 3401 */ 3402 boolean_t 3403 pmap_clear_reference(struct vm_page *pg) 3404 { 3405 boolean_t rv; 3406 3407 if (pg->mdpage.pvh_attrs & PVF_REF) { 3408 rv = TRUE; 3409 pmap_clearbit(pg, PVF_REF); 3410 } else 3411 rv = FALSE; 3412 3413 return (rv); 3414 } 3415 3416 /* 3417 * pmap_is_modified: 3418 * 3419 * Test if a page has the "modified" attribute. 3420 */ 3421 /* See <arm/arm32/pmap.h> */ 3422 3423 /* 3424 * pmap_is_referenced: 3425 * 3426 * Test if a page has the "referenced" attribute. 3427 */ 3428 /* See <arm/arm32/pmap.h> */ 3429 3430 int 3431 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3432 { 3433 struct l2_dtable *l2; 3434 struct l2_bucket *l2b; 3435 pd_entry_t *pl1pd, l1pd; 3436 pt_entry_t *ptep, pte; 3437 paddr_t pa; 3438 u_int l1idx; 3439 int rv = 0; 3440 3441 PMAP_MAP_TO_HEAD_LOCK(); 3442 pmap_acquire_pmap_lock(pm); 3443 3444 l1idx = L1_IDX(va); 3445 3446 /* 3447 * If there is no l2_dtable for this address, then the process 3448 * has no business accessing it. 3449 * 3450 * Note: This will catch userland processes trying to access 3451 * kernel addresses. 3452 */ 3453 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3454 if (l2 == NULL) 3455 goto out; 3456 3457 /* 3458 * Likewise if there is no L2 descriptor table 3459 */ 3460 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3461 if (l2b->l2b_kva == NULL) 3462 goto out; 3463 3464 /* 3465 * Check the PTE itself. 3466 */ 3467 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3468 pte = *ptep; 3469 if (pte == 0) 3470 goto out; 3471 3472 /* 3473 * Catch a userland access to the vector page mapped at 0x0 3474 */ 3475 if (user && (pte & L2_S_PROT_U) == 0) 3476 goto out; 3477 3478 pa = l2pte_pa(pte); 3479 3480 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3481 /* 3482 * This looks like a good candidate for "page modified" 3483 * emulation... 3484 */ 3485 struct pv_entry *pv; 3486 struct vm_page *pg; 3487 3488 /* Extract the physical address of the page */ 3489 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3490 goto out; 3491 3492 /* Get the current flags for this page. */ 3493 simple_lock(&pg->mdpage.pvh_slock); 3494 3495 pv = pmap_find_pv(pg, pm, va); 3496 if (pv == NULL) { 3497 simple_unlock(&pg->mdpage.pvh_slock); 3498 goto out; 3499 } 3500 3501 /* 3502 * Do the flags say this page is writable? If not then it 3503 * is a genuine write fault. If yes then the write fault is 3504 * our fault as we did not reflect the write access in the 3505 * PTE. Now we know a write has occurred we can correct this 3506 * and also set the modified bit 3507 */ 3508 if ((pv->pv_flags & PVF_WRITE) == 0) { 3509 simple_unlock(&pg->mdpage.pvh_slock); 3510 goto out; 3511 } 3512 3513 NPDEBUG(PDB_FOLLOW, 3514 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3515 pm, va, VM_PAGE_TO_PHYS(pg))); 3516 3517 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 3518 pv->pv_flags |= PVF_REF | PVF_MOD; 3519 simple_unlock(&pg->mdpage.pvh_slock); 3520 3521 /* 3522 * Re-enable write permissions for the page. No need to call 3523 * pmap_vac_me_harder(), since this is just a 3524 * modified-emulation fault, and the PVF_WRITE bit isn't 3525 * changing. We've already set the cacheable bits based on 3526 * the assumption that we can write to this page. 3527 */ 3528 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3529 PTE_SYNC(ptep); 3530 rv = 1; 3531 } else 3532 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3533 /* 3534 * This looks like a good candidate for "page referenced" 3535 * emulation. 3536 */ 3537 struct pv_entry *pv; 3538 struct vm_page *pg; 3539 3540 /* Extract the physical address of the page */ 3541 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3542 goto out; 3543 3544 /* Get the current flags for this page. */ 3545 simple_lock(&pg->mdpage.pvh_slock); 3546 3547 pv = pmap_find_pv(pg, pm, va); 3548 if (pv == NULL) { 3549 simple_unlock(&pg->mdpage.pvh_slock); 3550 goto out; 3551 } 3552 3553 pg->mdpage.pvh_attrs |= PVF_REF; 3554 pv->pv_flags |= PVF_REF; 3555 simple_unlock(&pg->mdpage.pvh_slock); 3556 3557 NPDEBUG(PDB_FOLLOW, 3558 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3559 pm, va, VM_PAGE_TO_PHYS(pg))); 3560 3561 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3562 PTE_SYNC(ptep); 3563 rv = 1; 3564 } 3565 3566 /* 3567 * We know there is a valid mapping here, so simply 3568 * fix up the L1 if necessary. 3569 */ 3570 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3571 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3572 if (*pl1pd != l1pd) { 3573 *pl1pd = l1pd; 3574 PTE_SYNC(pl1pd); 3575 rv = 1; 3576 } 3577 3578 #ifdef CPU_SA110 3579 /* 3580 * There are bugs in the rev K SA110. This is a check for one 3581 * of them. 3582 */ 3583 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3584 curcpu()->ci_arm_cpurev < 3) { 3585 /* Always current pmap */ 3586 if (l2pte_valid(pte)) { 3587 extern int kernel_debug; 3588 if (kernel_debug & 1) { 3589 struct proc *p = curlwp->l_proc; 3590 printf("prefetch_abort: page is already " 3591 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3592 printf("prefetch_abort: pc=%08lx proc=%p " 3593 "process=%s\n", va, p, p->p_comm); 3594 printf("prefetch_abort: far=%08x fs=%x\n", 3595 cpu_faultaddress(), cpu_faultstatus()); 3596 } 3597 #ifdef DDB 3598 if (kernel_debug & 2) 3599 Debugger(); 3600 #endif 3601 rv = 1; 3602 } 3603 } 3604 #endif /* CPU_SA110 */ 3605 3606 #ifdef DEBUG 3607 /* 3608 * If 'rv == 0' at this point, it generally indicates that there is a 3609 * stale TLB entry for the faulting address. This happens when two or 3610 * more processes are sharing an L1. Since we don't flush the TLB on 3611 * a context switch between such processes, we can take domain faults 3612 * for mappings which exist at the same VA in both processes. EVEN IF 3613 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3614 * example. 3615 * 3616 * This is extremely likely to happen if pmap_enter() updated the L1 3617 * entry for a recently entered mapping. In this case, the TLB is 3618 * flushed for the new mapping, but there may still be TLB entries for 3619 * other mappings belonging to other processes in the 1MB range 3620 * covered by the L1 entry. 3621 * 3622 * Since 'rv == 0', we know that the L1 already contains the correct 3623 * value, so the fault must be due to a stale TLB entry. 3624 * 3625 * Since we always need to flush the TLB anyway in the case where we 3626 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 3627 * stale TLB entries dynamically. 3628 * 3629 * However, the above condition can ONLY happen if the current L1 is 3630 * being shared. If it happens when the L1 is unshared, it indicates 3631 * that other parts of the pmap are not doing their job WRT managing 3632 * the TLB. 3633 */ 3634 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 3635 extern int last_fault_code; 3636 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 3637 pm, va, ftype); 3638 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 3639 l2, l2b, ptep, pl1pd); 3640 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 3641 pte, l1pd, last_fault_code); 3642 #ifdef DDB 3643 Debugger(); 3644 #endif 3645 } 3646 #endif 3647 3648 cpu_tlb_flushID_SE(va); 3649 cpu_cpwait(); 3650 3651 rv = 1; 3652 3653 out: 3654 pmap_release_pmap_lock(pm); 3655 PMAP_MAP_TO_HEAD_UNLOCK(); 3656 3657 return (rv); 3658 } 3659 3660 /* 3661 * pmap_collect: free resources held by a pmap 3662 * 3663 * => optional function. 3664 * => called when a process is swapped out to free memory. 3665 */ 3666 void 3667 pmap_collect(pmap_t pm) 3668 { 3669 3670 #ifdef PMAP_CACHE_VIVT 3671 pmap_idcache_wbinv_all(pm); 3672 #endif 3673 pm->pm_remove_all = TRUE; 3674 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 3675 pmap_update(pm); 3676 PMAPCOUNT(collects); 3677 } 3678 3679 /* 3680 * Routine: pmap_procwr 3681 * 3682 * Function: 3683 * Synchronize caches corresponding to [addr, addr+len) in p. 3684 * 3685 */ 3686 void 3687 pmap_procwr(struct proc *p, vaddr_t va, int len) 3688 { 3689 /* We only need to do anything if it is the current process. */ 3690 if (p == curproc) 3691 cpu_icache_sync_range(va, len); 3692 } 3693 3694 /* 3695 * Routine: pmap_unwire 3696 * Function: Clear the wired attribute for a map/virtual-address pair. 3697 * 3698 * In/out conditions: 3699 * The mapping must already exist in the pmap. 3700 */ 3701 void 3702 pmap_unwire(pmap_t pm, vaddr_t va) 3703 { 3704 struct l2_bucket *l2b; 3705 pt_entry_t *ptep, pte; 3706 struct vm_page *pg; 3707 paddr_t pa; 3708 3709 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 3710 3711 PMAP_MAP_TO_HEAD_LOCK(); 3712 pmap_acquire_pmap_lock(pm); 3713 3714 l2b = pmap_get_l2_bucket(pm, va); 3715 KDASSERT(l2b != NULL); 3716 3717 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3718 pte = *ptep; 3719 3720 /* Extract the physical address of the page */ 3721 pa = l2pte_pa(pte); 3722 3723 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3724 /* Update the wired bit in the pv entry for this page. */ 3725 simple_lock(&pg->mdpage.pvh_slock); 3726 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 3727 simple_unlock(&pg->mdpage.pvh_slock); 3728 } 3729 3730 pmap_release_pmap_lock(pm); 3731 PMAP_MAP_TO_HEAD_UNLOCK(); 3732 } 3733 3734 void 3735 pmap_activate(struct lwp *l) 3736 { 3737 pmap_t pm; 3738 struct pcb *pcb; 3739 int s; 3740 3741 pm = l->l_proc->p_vmspace->vm_map.pmap; 3742 pcb = &l->l_addr->u_pcb; 3743 3744 pmap_set_pcb_pagedir(pm, pcb); 3745 3746 PMAPCOUNT(activations); 3747 3748 if (l == curlwp) { 3749 u_int cur_dacr, cur_ttb; 3750 3751 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 3752 __asm volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 3753 3754 cur_ttb &= ~(L1_TABLE_SIZE - 1); 3755 3756 if (cur_ttb == (u_int)pcb->pcb_pagedir && 3757 cur_dacr == pcb->pcb_dacr) { 3758 /* 3759 * No need to switch address spaces. 3760 */ 3761 return; 3762 } 3763 3764 s = splhigh(); 3765 pmap_acquire_pmap_lock(pm); 3766 disable_interrupts(I32_bit | F32_bit); 3767 3768 /* 3769 * We MUST, I repeat, MUST fix up the L1 entry corresponding 3770 * to 'vector_page' in the incoming L1 table before switching 3771 * to it otherwise subsequent interrupts/exceptions (including 3772 * domain faults!) will jump into hyperspace. 3773 */ 3774 if (pcb->pcb_pl1vec) { 3775 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 3776 /* 3777 * Don't need to PTE_SYNC() at this point since 3778 * cpu_setttb() is about to flush both the cache 3779 * and the TLB. 3780 */ 3781 } 3782 3783 cpu_domains(pcb->pcb_dacr); 3784 cpu_setttb(pcb->pcb_pagedir); 3785 3786 enable_interrupts(I32_bit | F32_bit); 3787 3788 /* 3789 * Flag any previous userland pmap as being NOT 3790 * resident in the cache/tlb. 3791 */ 3792 if (pmap_cache_state && pmap_cache_state != &pm->pm_cstate) 3793 pmap_cache_state->cs_all = 0; 3794 3795 /* 3796 * The new pmap, however, IS resident. 3797 */ 3798 pmap_cache_state = &pm->pm_cstate; 3799 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3800 pmap_release_pmap_lock(pm); 3801 splx(s); 3802 } 3803 } 3804 3805 void 3806 pmap_deactivate(struct lwp *l) 3807 { 3808 } 3809 3810 void 3811 pmap_update(pmap_t pm) 3812 { 3813 3814 if (pm->pm_remove_all) { 3815 /* 3816 * Finish up the pmap_remove_all() optimisation by flushing 3817 * the TLB. 3818 */ 3819 pmap_tlb_flushID(pm); 3820 pm->pm_remove_all = FALSE; 3821 } 3822 3823 if (pmap_is_current(pm)) { 3824 /* 3825 * If we're dealing with a current userland pmap, move its L1 3826 * to the end of the LRU. 3827 */ 3828 if (pm != pmap_kernel()) 3829 pmap_use_l1(pm); 3830 3831 /* 3832 * We can assume we're done with frobbing the cache/tlb for 3833 * now. Make sure any future pmap ops don't skip cache/tlb 3834 * flushes. 3835 */ 3836 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3837 } 3838 3839 PMAPCOUNT(updates); 3840 3841 /* 3842 * make sure TLB/cache operations have completed. 3843 */ 3844 cpu_cpwait(); 3845 } 3846 3847 void 3848 pmap_remove_all(pmap_t pm) 3849 { 3850 3851 /* 3852 * The vmspace described by this pmap is about to be torn down. 3853 * Until pmap_update() is called, UVM will only make calls 3854 * to pmap_remove(). We can make life much simpler by flushing 3855 * the cache now, and deferring TLB invalidation to pmap_update(). 3856 */ 3857 #ifdef PMAP_CACHE_VIVT 3858 pmap_idcache_wbinv_all(pm); 3859 #endif 3860 pm->pm_remove_all = TRUE; 3861 } 3862 3863 /* 3864 * Retire the given physical map from service. 3865 * Should only be called if the map contains no valid mappings. 3866 */ 3867 void 3868 pmap_destroy(pmap_t pm) 3869 { 3870 u_int count; 3871 3872 if (pm == NULL) 3873 return; 3874 3875 if (pm->pm_remove_all) { 3876 pmap_tlb_flushID(pm); 3877 pm->pm_remove_all = FALSE; 3878 } 3879 3880 /* 3881 * Drop reference count 3882 */ 3883 simple_lock(&pm->pm_lock); 3884 count = --pm->pm_obj.uo_refs; 3885 simple_unlock(&pm->pm_lock); 3886 if (count > 0) { 3887 if (pmap_is_current(pm)) { 3888 if (pm != pmap_kernel()) 3889 pmap_use_l1(pm); 3890 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3891 } 3892 return; 3893 } 3894 3895 /* 3896 * reference count is zero, free pmap resources and then free pmap. 3897 */ 3898 3899 if (vector_page < KERNEL_BASE) { 3900 struct pcb *pcb = &lwp0.l_addr->u_pcb; 3901 3902 if (pmap_is_current(pm)) { 3903 /* 3904 * Frob the L1 entry corresponding to the vector 3905 * page so that it contains the kernel pmap's domain 3906 * number. This will ensure pmap_remove() does not 3907 * pull the current vector page out from under us. 3908 */ 3909 disable_interrupts(I32_bit | F32_bit); 3910 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 3911 cpu_domains(pcb->pcb_dacr); 3912 cpu_setttb(pcb->pcb_pagedir); 3913 enable_interrupts(I32_bit | F32_bit); 3914 } 3915 3916 /* Remove the vector page mapping */ 3917 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 3918 pmap_update(pm); 3919 3920 /* 3921 * Make sure cpu_switch(), et al, DTRT. This is safe to do 3922 * since this process has no remaining mappings of its own. 3923 */ 3924 curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 3925 curpcb->pcb_l1vec = pcb->pcb_l1vec; 3926 curpcb->pcb_dacr = pcb->pcb_dacr; 3927 curpcb->pcb_pagedir = pcb->pcb_pagedir; 3928 } 3929 3930 LIST_REMOVE(pm, pm_list); 3931 3932 pmap_free_l1(pm); 3933 3934 /* return the pmap to the pool */ 3935 pool_cache_put(&pmap_pmap_cache, pm); 3936 } 3937 3938 3939 /* 3940 * void pmap_reference(pmap_t pm) 3941 * 3942 * Add a reference to the specified pmap. 3943 */ 3944 void 3945 pmap_reference(pmap_t pm) 3946 { 3947 3948 if (pm == NULL) 3949 return; 3950 3951 pmap_use_l1(pm); 3952 3953 simple_lock(&pm->pm_lock); 3954 pm->pm_obj.uo_refs++; 3955 simple_unlock(&pm->pm_lock); 3956 } 3957 3958 #if ARM_MMU_V6 > 0 3959 3960 static struct evcnt pmap_prefer_nochange_ev = 3961 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 3962 static struct evcnt pmap_prefer_change_ev = 3963 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 3964 3965 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 3966 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 3967 3968 void 3969 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 3970 { 3971 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 3972 vaddr_t va = *vap; 3973 vaddr_t diff = (hint - va) & mask; 3974 if (diff == 0) { 3975 pmap_prefer_nochange_ev.ev_count++; 3976 } else { 3977 pmap_prefer_change_ev.ev_count++; 3978 if (__predict_false(td)) 3979 va -= mask + 1; 3980 *vap = va + diff; 3981 } 3982 } 3983 #endif /* ARM_MMU_V6 */ 3984 3985 /* 3986 * pmap_zero_page() 3987 * 3988 * Zero a given physical page by mapping it at a page hook point. 3989 * In doing the zero page op, the page we zero is mapped cachable, as with 3990 * StrongARM accesses to non-cached pages are non-burst making writing 3991 * _any_ bulk data very slow. 3992 */ 3993 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 3994 void 3995 pmap_zero_page_generic(paddr_t phys) 3996 { 3997 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 3998 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3999 #endif 4000 #ifdef PMAP_CACHE_VIPT 4001 /* Choose the last page color it had, if any */ 4002 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4003 #else 4004 const vsize_t va_offset = 0; 4005 #endif 4006 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4007 4008 #ifdef DEBUG 4009 if (pg->mdpage.pvh_list != NULL) 4010 panic("pmap_zero_page: page has mappings"); 4011 #endif 4012 4013 KDASSERT((phys & PGOFSET) == 0); 4014 4015 /* 4016 * Hook in the page, zero it, and purge the cache for that 4017 * zeroed page. Invalidate the TLB as needed. 4018 */ 4019 *ptep = L2_S_PROTO | phys | 4020 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4021 PTE_SYNC(ptep); 4022 cpu_tlb_flushD_SE(cdstp + va_offset); 4023 cpu_cpwait(); 4024 bzero_page(cdstp + va_offset); 4025 /* 4026 * Unmap the page. 4027 */ 4028 *ptep = 0; 4029 PTE_SYNC(ptep); 4030 cpu_tlb_flushD_SE(cdstp + va_offset); 4031 #ifdef PMAP_CACHE_VIVT 4032 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4033 #endif 4034 #ifdef PMAP_CACHE_VIPT 4035 /* 4036 * This page is now cache resident so it now has a page color. 4037 * Any contents have been obliterated so clear the EXEC flag. 4038 */ 4039 if (!pmap_is_page_colored_p(pg)) { 4040 PMAPCOUNT(vac_color_new); 4041 pg->mdpage.pvh_attrs |= PVF_COLORED; 4042 } 4043 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4044 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4045 PMAPCOUNT(exec_discarded_zero); 4046 } 4047 #endif 4048 } 4049 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4050 4051 #if ARM_MMU_XSCALE == 1 4052 void 4053 pmap_zero_page_xscale(paddr_t phys) 4054 { 4055 #ifdef DEBUG 4056 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4057 4058 if (pg->mdpage.pvh_list != NULL) 4059 panic("pmap_zero_page: page has mappings"); 4060 #endif 4061 4062 KDASSERT((phys & PGOFSET) == 0); 4063 4064 /* 4065 * Hook in the page, zero it, and purge the cache for that 4066 * zeroed page. Invalidate the TLB as needed. 4067 */ 4068 *cdst_pte = L2_S_PROTO | phys | 4069 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4070 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4071 PTE_SYNC(cdst_pte); 4072 cpu_tlb_flushD_SE(cdstp); 4073 cpu_cpwait(); 4074 bzero_page(cdstp); 4075 xscale_cache_clean_minidata(); 4076 } 4077 #endif /* ARM_MMU_XSCALE == 1 */ 4078 4079 /* pmap_pageidlezero() 4080 * 4081 * The same as above, except that we assume that the page is not 4082 * mapped. This means we never have to flush the cache first. Called 4083 * from the idle loop. 4084 */ 4085 boolean_t 4086 pmap_pageidlezero(paddr_t phys) 4087 { 4088 unsigned int i; 4089 int *ptr; 4090 boolean_t rv = TRUE; 4091 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4092 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4093 #endif 4094 #ifdef PMAP_CACHE_VIPT 4095 /* Choose the last page color it had, if any */ 4096 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4097 #else 4098 const vsize_t va_offset = 0; 4099 #endif 4100 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4101 4102 4103 #ifdef DEBUG 4104 if (pg->mdpage.pvh_list != NULL) 4105 panic("pmap_pageidlezero: page has mappings"); 4106 #endif 4107 4108 KDASSERT((phys & PGOFSET) == 0); 4109 4110 /* 4111 * Hook in the page, zero it, and purge the cache for that 4112 * zeroed page. Invalidate the TLB as needed. 4113 */ 4114 *ptep = L2_S_PROTO | phys | 4115 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4116 PTE_SYNC(ptep); 4117 cpu_tlb_flushD_SE(cdstp + va_offset); 4118 cpu_cpwait(); 4119 4120 for (i = 0, ptr = (int *)(cdstp + va_offset); 4121 i < (PAGE_SIZE / sizeof(int)); i++) { 4122 if (sched_whichqs != 0) { 4123 /* 4124 * A process has become ready. Abort now, 4125 * so we don't keep it waiting while we 4126 * do slow memory access to finish this 4127 * page. 4128 */ 4129 rv = FALSE; 4130 break; 4131 } 4132 *ptr++ = 0; 4133 } 4134 4135 #ifdef PMAP_CACHE_VIVT 4136 if (rv) 4137 /* 4138 * if we aborted we'll rezero this page again later so don't 4139 * purge it unless we finished it 4140 */ 4141 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4142 #elif defined(PMAP_CACHE_VIPT) 4143 /* 4144 * This page is now cache resident so it now has a page color. 4145 * Any contents have been obliterated so clear the EXEC flag. 4146 */ 4147 if (!pmap_is_page_colored_p(pg)) { 4148 PMAPCOUNT(vac_color_new); 4149 pg->mdpage.pvh_attrs |= PVF_COLORED; 4150 } 4151 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4152 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4153 PMAPCOUNT(exec_discarded_zero); 4154 } 4155 #endif 4156 /* 4157 * Unmap the page. 4158 */ 4159 *ptep = 0; 4160 PTE_SYNC(ptep); 4161 cpu_tlb_flushD_SE(cdstp + va_offset); 4162 4163 return (rv); 4164 } 4165 4166 /* 4167 * pmap_copy_page() 4168 * 4169 * Copy one physical page into another, by mapping the pages into 4170 * hook points. The same comment regarding cachability as in 4171 * pmap_zero_page also applies here. 4172 */ 4173 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4174 void 4175 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4176 { 4177 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4178 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4179 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4180 #endif 4181 #ifdef PMAP_CACHE_VIPT 4182 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4183 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4184 #else 4185 const vsize_t src_va_offset = 0; 4186 const vsize_t dst_va_offset = 0; 4187 #endif 4188 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4189 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4190 4191 #ifdef DEBUG 4192 if (dst_pg->mdpage.pvh_list != NULL) 4193 panic("pmap_copy_page: dst page has mappings"); 4194 #endif 4195 4196 #ifdef PMAP_CACHE_VIPT 4197 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4198 #endif 4199 KDASSERT((src & PGOFSET) == 0); 4200 KDASSERT((dst & PGOFSET) == 0); 4201 4202 /* 4203 * Clean the source page. Hold the source page's lock for 4204 * the duration of the copy so that no other mappings can 4205 * be created while we have a potentially aliased mapping. 4206 */ 4207 simple_lock(&src_pg->mdpage.pvh_slock); 4208 #ifdef PMAP_CACHE_VIVT 4209 (void) pmap_clean_page(src_pg->mdpage.pvh_list, TRUE); 4210 #endif 4211 4212 /* 4213 * Map the pages into the page hook points, copy them, and purge 4214 * the cache for the appropriate page. Invalidate the TLB 4215 * as required. 4216 */ 4217 *src_ptep = L2_S_PROTO 4218 | src 4219 #ifdef PMAP_CACHE_VIPT 4220 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4221 #endif 4222 #ifdef PMAP_CACHE_VIVT 4223 | pte_l2_s_cache_mode 4224 #endif 4225 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4226 *dst_ptep = L2_S_PROTO | dst | 4227 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4228 PTE_SYNC(src_ptep); 4229 PTE_SYNC(dst_ptep); 4230 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4231 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4232 cpu_cpwait(); 4233 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4234 #ifdef PMAP_CACHE_VIVT 4235 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4236 #endif 4237 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4238 #ifdef PMAP_CACHE_VIVT 4239 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4240 #endif 4241 /* 4242 * Unmap the pages. 4243 */ 4244 *src_ptep = 0; 4245 *dst_ptep = 0; 4246 PTE_SYNC(src_ptep); 4247 PTE_SYNC(dst_ptep); 4248 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4249 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4250 #ifdef PMAP_CACHE_VIPT 4251 /* 4252 * Now that the destination page is in the cache, mark it as colored. 4253 * If this was an exec page, discard it. 4254 */ 4255 if (!pmap_is_page_colored_p(dst_pg)) { 4256 PMAPCOUNT(vac_color_new); 4257 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4258 } 4259 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4260 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4261 PMAPCOUNT(exec_discarded_copy); 4262 } 4263 #endif 4264 } 4265 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4266 4267 #if ARM_MMU_XSCALE == 1 4268 void 4269 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4270 { 4271 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4272 #ifdef DEBUG 4273 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4274 4275 if (dst_pg->mdpage.pvh_list != NULL) 4276 panic("pmap_copy_page: dst page has mappings"); 4277 #endif 4278 4279 KDASSERT((src & PGOFSET) == 0); 4280 KDASSERT((dst & PGOFSET) == 0); 4281 4282 /* 4283 * Clean the source page. Hold the source page's lock for 4284 * the duration of the copy so that no other mappings can 4285 * be created while we have a potentially aliased mapping. 4286 */ 4287 simple_lock(&src_pg->mdpage.pvh_slock); 4288 #ifdef PMAP_CACHE_VIVT 4289 (void) pmap_clean_page(src_pg->mdpage.pvh_list, TRUE); 4290 #endif 4291 4292 /* 4293 * Map the pages into the page hook points, copy them, and purge 4294 * the cache for the appropriate page. Invalidate the TLB 4295 * as required. 4296 */ 4297 *csrc_pte = L2_S_PROTO | src | 4298 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4299 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4300 PTE_SYNC(csrc_pte); 4301 *cdst_pte = L2_S_PROTO | dst | 4302 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4303 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4304 PTE_SYNC(cdst_pte); 4305 cpu_tlb_flushD_SE(csrcp); 4306 cpu_tlb_flushD_SE(cdstp); 4307 cpu_cpwait(); 4308 bcopy_page(csrcp, cdstp); 4309 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4310 xscale_cache_clean_minidata(); 4311 } 4312 #endif /* ARM_MMU_XSCALE == 1 */ 4313 4314 /* 4315 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4316 * 4317 * Return the start and end addresses of the kernel's virtual space. 4318 * These values are setup in pmap_bootstrap and are updated as pages 4319 * are allocated. 4320 */ 4321 void 4322 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4323 { 4324 *start = virtual_avail; 4325 *end = virtual_end; 4326 } 4327 4328 /* 4329 * Helper function for pmap_grow_l2_bucket() 4330 */ 4331 static inline int 4332 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4333 { 4334 struct l2_bucket *l2b; 4335 pt_entry_t *ptep; 4336 paddr_t pa; 4337 4338 if (uvm.page_init_done == FALSE) { 4339 if (uvm_page_physget(&pa) == FALSE) 4340 return (1); 4341 } else { 4342 struct vm_page *pg; 4343 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4344 if (pg == NULL) 4345 return (1); 4346 pa = VM_PAGE_TO_PHYS(pg); 4347 #ifdef PMAP_CACHE_VIPT 4348 /* 4349 * This new page must not have any mappings. However, it might 4350 * have previously used and therefore present in the cache. If 4351 * it doesn't have the desired color, we have to flush it from 4352 * the cache. And while we are at it, make sure to clear its 4353 * EXEC status. 4354 */ 4355 KASSERT(!(pg->mdpage.pvh_attrs & PVF_KENTRY)); 4356 KASSERT(pg->mdpage.pvh_list == NULL); 4357 if (pmap_is_page_colored_p(pg)) { 4358 if ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask) { 4359 pmap_flush_page(pg); 4360 PMAPCOUNT(vac_color_change); 4361 } else { 4362 PMAPCOUNT(vac_color_reuse); 4363 } 4364 } else { 4365 PMAPCOUNT(vac_color_new); 4366 } 4367 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 4368 PMAPCOUNT(exec_discarded_kremove); 4369 /* 4370 * We'll pretend this page was entered by pmap_kenter_pa 4371 */ 4372 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_EXEC; 4373 pg->mdpage.pvh_attrs |= va | PVF_KENTRY | PVF_COLORED | PVF_REF | PVF_MOD; 4374 #endif 4375 } 4376 4377 if (pap) 4378 *pap = pa; 4379 4380 PMAPCOUNT(pt_mappings); 4381 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4382 KDASSERT(l2b != NULL); 4383 4384 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4385 *ptep = L2_S_PROTO | pa | cache_mode | 4386 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4387 PTE_SYNC(ptep); 4388 memset((void *)va, 0, PAGE_SIZE); 4389 return (0); 4390 } 4391 4392 /* 4393 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4394 * used by pmap_growkernel(). 4395 */ 4396 static inline struct l2_bucket * 4397 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4398 { 4399 struct l2_dtable *l2; 4400 struct l2_bucket *l2b; 4401 u_short l1idx; 4402 vaddr_t nva; 4403 4404 l1idx = L1_IDX(va); 4405 4406 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4407 /* 4408 * No mapping at this address, as there is 4409 * no entry in the L1 table. 4410 * Need to allocate a new l2_dtable. 4411 */ 4412 nva = pmap_kernel_l2dtable_kva; 4413 if ((nva & PGOFSET) == 0) { 4414 /* 4415 * Need to allocate a backing page 4416 */ 4417 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4418 return (NULL); 4419 } 4420 4421 l2 = (struct l2_dtable *)nva; 4422 nva += sizeof(struct l2_dtable); 4423 4424 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4425 /* 4426 * The new l2_dtable straddles a page boundary. 4427 * Map in another page to cover it. 4428 */ 4429 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4430 return (NULL); 4431 } 4432 4433 pmap_kernel_l2dtable_kva = nva; 4434 4435 /* 4436 * Link it into the parent pmap 4437 */ 4438 pm->pm_l2[L2_IDX(l1idx)] = l2; 4439 } 4440 4441 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4442 4443 /* 4444 * Fetch pointer to the L2 page table associated with the address. 4445 */ 4446 if (l2b->l2b_kva == NULL) { 4447 pt_entry_t *ptep; 4448 4449 /* 4450 * No L2 page table has been allocated. Chances are, this 4451 * is because we just allocated the l2_dtable, above. 4452 */ 4453 nva = pmap_kernel_l2ptp_kva; 4454 ptep = (pt_entry_t *)nva; 4455 if ((nva & PGOFSET) == 0) { 4456 /* 4457 * Need to allocate a backing page 4458 */ 4459 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4460 &pmap_kernel_l2ptp_phys)) 4461 return (NULL); 4462 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4463 } 4464 4465 l2->l2_occupancy++; 4466 l2b->l2b_kva = ptep; 4467 l2b->l2b_l1idx = l1idx; 4468 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4469 4470 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4471 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4472 } 4473 4474 return (l2b); 4475 } 4476 4477 vaddr_t 4478 pmap_growkernel(vaddr_t maxkvaddr) 4479 { 4480 pmap_t kpm = pmap_kernel(); 4481 struct l1_ttable *l1; 4482 struct l2_bucket *l2b; 4483 pd_entry_t *pl1pd; 4484 int s; 4485 4486 if (maxkvaddr <= pmap_curmaxkvaddr) 4487 goto out; /* we are OK */ 4488 4489 NPDEBUG(PDB_GROWKERN, 4490 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4491 pmap_curmaxkvaddr, maxkvaddr)); 4492 4493 KDASSERT(maxkvaddr <= virtual_end); 4494 4495 /* 4496 * whoops! we need to add kernel PTPs 4497 */ 4498 4499 s = splhigh(); /* to be safe */ 4500 simple_lock(&kpm->pm_lock); 4501 4502 /* Map 1MB at a time */ 4503 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4504 4505 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4506 KDASSERT(l2b != NULL); 4507 4508 /* Distribute new L1 entry to all other L1s */ 4509 SLIST_FOREACH(l1, &l1_list, l1_link) { 4510 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4511 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4512 L1_C_PROTO; 4513 PTE_SYNC(pl1pd); 4514 } 4515 } 4516 4517 /* 4518 * flush out the cache, expensive but growkernel will happen so 4519 * rarely 4520 */ 4521 cpu_dcache_wbinv_all(); 4522 cpu_tlb_flushD(); 4523 cpu_cpwait(); 4524 4525 simple_unlock(&kpm->pm_lock); 4526 splx(s); 4527 4528 out: 4529 return (pmap_curmaxkvaddr); 4530 } 4531 4532 /************************ Utility routines ****************************/ 4533 4534 /* 4535 * vector_page_setprot: 4536 * 4537 * Manipulate the protection of the vector page. 4538 */ 4539 void 4540 vector_page_setprot(int prot) 4541 { 4542 struct l2_bucket *l2b; 4543 pt_entry_t *ptep; 4544 4545 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4546 KDASSERT(l2b != NULL); 4547 4548 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4549 4550 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4551 PTE_SYNC(ptep); 4552 cpu_tlb_flushD_SE(vector_page); 4553 cpu_cpwait(); 4554 } 4555 4556 /* 4557 * This is used to stuff certain critical values into the PCB where they 4558 * can be accessed quickly from cpu_switch() et al. 4559 */ 4560 void 4561 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 4562 { 4563 struct l2_bucket *l2b; 4564 4565 KDASSERT(pm->pm_l1); 4566 4567 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 4568 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4569 (DOMAIN_CLIENT << (pm->pm_domain * 2)); 4570 pcb->pcb_cstate = (void *)&pm->pm_cstate; 4571 4572 if (vector_page < KERNEL_BASE) { 4573 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 4574 l2b = pmap_get_l2_bucket(pm, vector_page); 4575 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 4576 L1_C_DOM(pm->pm_domain); 4577 } else 4578 pcb->pcb_pl1vec = NULL; 4579 } 4580 4581 /* 4582 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4583 * Returns TRUE if the mapping exists, else FALSE. 4584 * 4585 * NOTE: This function is only used by a couple of arm-specific modules. 4586 * It is not safe to take any pmap locks here, since we could be right 4587 * in the middle of debugging the pmap anyway... 4588 * 4589 * It is possible for this routine to return FALSE even though a valid 4590 * mapping does exist. This is because we don't lock, so the metadata 4591 * state may be inconsistent. 4592 * 4593 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4594 * a "section" mapping. 4595 */ 4596 boolean_t 4597 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4598 { 4599 struct l2_dtable *l2; 4600 pd_entry_t *pl1pd, l1pd; 4601 pt_entry_t *ptep; 4602 u_short l1idx; 4603 4604 if (pm->pm_l1 == NULL) 4605 return (FALSE); 4606 4607 l1idx = L1_IDX(va); 4608 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4609 l1pd = *pl1pd; 4610 4611 if (l1pte_section_p(l1pd)) { 4612 *ptp = NULL; 4613 return (TRUE); 4614 } 4615 4616 if (pm->pm_l2 == NULL) 4617 return (FALSE); 4618 4619 l2 = pm->pm_l2[L2_IDX(l1idx)]; 4620 4621 if (l2 == NULL || 4622 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 4623 return (FALSE); 4624 } 4625 4626 *ptp = &ptep[l2pte_index(va)]; 4627 return (TRUE); 4628 } 4629 4630 boolean_t 4631 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 4632 { 4633 u_short l1idx; 4634 4635 if (pm->pm_l1 == NULL) 4636 return (FALSE); 4637 4638 l1idx = L1_IDX(va); 4639 *pdp = &pm->pm_l1->l1_kva[l1idx]; 4640 4641 return (TRUE); 4642 } 4643 4644 /************************ Bootstrapping routines ****************************/ 4645 4646 static void 4647 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 4648 { 4649 int i; 4650 4651 l1->l1_kva = l1pt; 4652 l1->l1_domain_use_count = 0; 4653 l1->l1_domain_first = 0; 4654 4655 for (i = 0; i < PMAP_DOMAINS; i++) 4656 l1->l1_domain_free[i] = i + 1; 4657 4658 /* 4659 * Copy the kernel's L1 entries to each new L1. 4660 */ 4661 if (pmap_initialized) 4662 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 4663 4664 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 4665 &l1->l1_physaddr) == FALSE) 4666 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 4667 4668 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 4669 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 4670 } 4671 4672 /* 4673 * pmap_bootstrap() is called from the board-specific initarm() routine 4674 * once the kernel L1/L2 descriptors tables have been set up. 4675 * 4676 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 4677 * spread over a number of disparate files/functions. 4678 * 4679 * We are passed the following parameters 4680 * - kernel_l1pt 4681 * This is a pointer to the base of the kernel's L1 translation table. 4682 * - vstart 4683 * 1MB-aligned start of managed kernel virtual memory. 4684 * - vend 4685 * 1MB-aligned end of managed kernel virtual memory. 4686 * 4687 * We use the first parameter to build the metadata (struct l1_ttable and 4688 * struct l2_dtable) necessary to track kernel mappings. 4689 */ 4690 #define PMAP_STATIC_L2_SIZE 16 4691 void 4692 pmap_bootstrap(pd_entry_t *kernel_l1pt, vaddr_t vstart, vaddr_t vend) 4693 { 4694 static struct l1_ttable static_l1; 4695 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 4696 struct l1_ttable *l1 = &static_l1; 4697 struct l2_dtable *l2; 4698 struct l2_bucket *l2b; 4699 pmap_t pm = pmap_kernel(); 4700 pd_entry_t pde; 4701 pt_entry_t *ptep; 4702 paddr_t pa; 4703 vaddr_t va; 4704 vsize_t size; 4705 int nptes, l1idx, l2idx, l2next = 0; 4706 4707 /* 4708 * Initialise the kernel pmap object 4709 */ 4710 pm->pm_l1 = l1; 4711 pm->pm_domain = PMAP_DOMAIN_KERNEL; 4712 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4713 simple_lock_init(&pm->pm_lock); 4714 pm->pm_obj.pgops = NULL; 4715 TAILQ_INIT(&pm->pm_obj.memq); 4716 pm->pm_obj.uo_npages = 0; 4717 pm->pm_obj.uo_refs = 1; 4718 4719 /* 4720 * Scan the L1 translation table created by initarm() and create 4721 * the required metadata for all valid mappings found in it. 4722 */ 4723 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 4724 pde = kernel_l1pt[l1idx]; 4725 4726 /* 4727 * We're only interested in Coarse mappings. 4728 * pmap_extract() can deal with section mappings without 4729 * recourse to checking L2 metadata. 4730 */ 4731 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 4732 continue; 4733 4734 /* 4735 * Lookup the KVA of this L2 descriptor table 4736 */ 4737 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 4738 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 4739 if (ptep == NULL) { 4740 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 4741 (u_int)l1idx << L1_S_SHIFT, pa); 4742 } 4743 4744 /* 4745 * Fetch the associated L2 metadata structure. 4746 * Allocate a new one if necessary. 4747 */ 4748 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4749 if (l2next == PMAP_STATIC_L2_SIZE) 4750 panic("pmap_bootstrap: out of static L2s"); 4751 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 4752 } 4753 4754 /* 4755 * One more L1 slot tracked... 4756 */ 4757 l2->l2_occupancy++; 4758 4759 /* 4760 * Fill in the details of the L2 descriptor in the 4761 * appropriate bucket. 4762 */ 4763 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4764 l2b->l2b_kva = ptep; 4765 l2b->l2b_phys = pa; 4766 l2b->l2b_l1idx = l1idx; 4767 4768 /* 4769 * Establish an initial occupancy count for this descriptor 4770 */ 4771 for (l2idx = 0; 4772 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 4773 l2idx++) { 4774 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 4775 l2b->l2b_occupancy++; 4776 } 4777 } 4778 4779 /* 4780 * Make sure the descriptor itself has the correct cache mode. 4781 * If not, fix it, but whine about the problem. Port-meisters 4782 * should consider this a clue to fix up their initarm() 4783 * function. :) 4784 */ 4785 if (pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)ptep)) { 4786 printf("pmap_bootstrap: WARNING! wrong cache mode for " 4787 "L2 pte @ %p\n", ptep); 4788 } 4789 } 4790 4791 /* 4792 * Ensure the primary (kernel) L1 has the correct cache mode for 4793 * a page table. Bitch if it is not correctly set. 4794 */ 4795 for (va = (vaddr_t)kernel_l1pt; 4796 va < ((vaddr_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 4797 if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 4798 printf("pmap_bootstrap: WARNING! wrong cache mode for " 4799 "primary L1 @ 0x%lx\n", va); 4800 } 4801 4802 cpu_dcache_wbinv_all(); 4803 cpu_tlb_flushID(); 4804 cpu_cpwait(); 4805 4806 /* 4807 * now we allocate the "special" VAs which are used for tmp mappings 4808 * by the pmap (and other modules). we allocate the VAs by advancing 4809 * virtual_avail (note that there are no pages mapped at these VAs). 4810 * 4811 * Managed KVM space start from wherever initarm() tells us. 4812 */ 4813 virtual_avail = vstart; 4814 virtual_end = vend; 4815 4816 #ifdef PMAP_CACHE_VIPT 4817 /* 4818 * If we have a VIPT cache, we need one page/pte per possible alias 4819 * page so we won't violate cache aliasing rules. 4820 */ 4821 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 4822 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 4823 #else 4824 nptes = 1; 4825 #endif 4826 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 4827 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)csrc_pte); 4828 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 4829 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)cdst_pte); 4830 pmap_alloc_specials(&virtual_avail, 1, (void *)&memhook, NULL); 4831 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 4832 (void *)&msgbufaddr, NULL); 4833 4834 /* 4835 * Allocate a range of kernel virtual address space to be used 4836 * for L2 descriptor tables and metadata allocation in 4837 * pmap_growkernel(). 4838 */ 4839 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 4840 pmap_alloc_specials(&virtual_avail, 4841 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 4842 &pmap_kernel_l2ptp_kva, NULL); 4843 4844 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 4845 pmap_alloc_specials(&virtual_avail, 4846 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 4847 &pmap_kernel_l2dtable_kva, NULL); 4848 4849 /* 4850 * init the static-global locks and global pmap list. 4851 */ 4852 #if defined(MULTIPROCESSOR) || defined(LOCKDEBUG) 4853 spinlockinit(&pmap_main_lock, "pmaplk", 0); 4854 #endif 4855 4856 /* 4857 * We can now initialise the first L1's metadata. 4858 */ 4859 SLIST_INIT(&l1_list); 4860 TAILQ_INIT(&l1_lru_list); 4861 simple_lock_init(&l1_lru_lock); 4862 pmap_init_l1(l1, kernel_l1pt); 4863 4864 /* 4865 * Initialize the pmap pool and cache 4866 */ 4867 pool_init(&pmap_pmap_pool, sizeof(struct pmap), 0, 0, 0, "pmappl", 4868 &pool_allocator_nointr); 4869 pool_cache_init(&pmap_pmap_cache, &pmap_pmap_pool, 4870 pmap_pmap_ctor, NULL, NULL); 4871 LIST_INIT(&pmap_pmaps); 4872 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 4873 4874 /* 4875 * Initialize the pv pool. 4876 */ 4877 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 4878 &pmap_bootstrap_pv_allocator); 4879 4880 /* 4881 * Initialize the L2 dtable pool and cache. 4882 */ 4883 pool_init(&pmap_l2dtable_pool, sizeof(struct l2_dtable), 0, 0, 0, 4884 "l2dtblpl", NULL); 4885 pool_cache_init(&pmap_l2dtable_cache, &pmap_l2dtable_pool, 4886 pmap_l2dtable_ctor, NULL, NULL); 4887 4888 /* 4889 * Initialise the L2 descriptor table pool and cache 4890 */ 4891 pool_init(&pmap_l2ptp_pool, L2_TABLE_SIZE_REAL, 0, L2_TABLE_SIZE_REAL, 4892 0, "l2ptppl", NULL); 4893 pool_cache_init(&pmap_l2ptp_cache, &pmap_l2ptp_pool, 4894 pmap_l2ptp_ctor, NULL, NULL); 4895 4896 cpu_dcache_wbinv_all(); 4897 } 4898 4899 static int 4900 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 4901 { 4902 pd_entry_t *pdep, pde; 4903 pt_entry_t *ptep, pte; 4904 vaddr_t pa; 4905 int rv = 0; 4906 4907 /* 4908 * Make sure the descriptor itself has the correct cache mode 4909 */ 4910 pdep = &kl1[L1_IDX(va)]; 4911 pde = *pdep; 4912 4913 if (l1pte_section_p(pde)) { 4914 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 4915 *pdep = (pde & ~L1_S_CACHE_MASK) | 4916 pte_l1_s_cache_mode_pt; 4917 PTE_SYNC(pdep); 4918 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 4919 rv = 1; 4920 } 4921 } else { 4922 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 4923 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 4924 if (ptep == NULL) 4925 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 4926 4927 ptep = &ptep[l2pte_index(va)]; 4928 pte = *ptep; 4929 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 4930 *ptep = (pte & ~L2_S_CACHE_MASK) | 4931 pte_l2_s_cache_mode_pt; 4932 PTE_SYNC(ptep); 4933 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 4934 rv = 1; 4935 } 4936 } 4937 4938 return (rv); 4939 } 4940 4941 static void 4942 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 4943 { 4944 vaddr_t va = *availp; 4945 struct l2_bucket *l2b; 4946 4947 if (ptep) { 4948 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4949 if (l2b == NULL) 4950 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 4951 4952 if (ptep) 4953 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 4954 } 4955 4956 *vap = va; 4957 *availp = va + (PAGE_SIZE * pages); 4958 } 4959 4960 void 4961 pmap_init(void) 4962 { 4963 extern int physmem; 4964 4965 /* 4966 * Set the available memory vars - These do not map to real memory 4967 * addresses and cannot as the physical memory is fragmented. 4968 * They are used by ps for %mem calculations. 4969 * One could argue whether this should be the entire memory or just 4970 * the memory that is useable in a user process. 4971 */ 4972 avail_start = 0; 4973 avail_end = physmem * PAGE_SIZE; 4974 4975 /* 4976 * Now we need to free enough pv_entry structures to allow us to get 4977 * the kmem_map/kmem_object allocated and inited (done after this 4978 * function is finished). to do this we allocate one bootstrap page out 4979 * of kernel_map and use it to provide an initial pool of pv_entry 4980 * structures. we never free this page. 4981 */ 4982 pool_setlowat(&pmap_pv_pool, 4983 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 4984 4985 pmap_initialized = TRUE; 4986 } 4987 4988 static vaddr_t last_bootstrap_page = 0; 4989 static void *free_bootstrap_pages = NULL; 4990 4991 static void * 4992 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 4993 { 4994 extern void *pool_page_alloc(struct pool *, int); 4995 vaddr_t new_page; 4996 void *rv; 4997 4998 if (pmap_initialized) 4999 return (pool_page_alloc(pp, flags)); 5000 5001 if (free_bootstrap_pages) { 5002 rv = free_bootstrap_pages; 5003 free_bootstrap_pages = *((void **)rv); 5004 return (rv); 5005 } 5006 5007 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5008 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5009 5010 KASSERT(new_page > last_bootstrap_page); 5011 last_bootstrap_page = new_page; 5012 return ((void *)new_page); 5013 } 5014 5015 static void 5016 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5017 { 5018 extern void pool_page_free(struct pool *, void *); 5019 5020 if ((vaddr_t)v <= last_bootstrap_page) { 5021 *((void **)v) = free_bootstrap_pages; 5022 free_bootstrap_pages = v; 5023 return; 5024 } 5025 5026 if (pmap_initialized) { 5027 pool_page_free(pp, v); 5028 return; 5029 } 5030 } 5031 5032 /* 5033 * pmap_postinit() 5034 * 5035 * This routine is called after the vm and kmem subsystems have been 5036 * initialised. This allows the pmap code to perform any initialisation 5037 * that can only be done one the memory allocation is in place. 5038 */ 5039 void 5040 pmap_postinit(void) 5041 { 5042 extern paddr_t physical_start, physical_end; 5043 struct l2_bucket *l2b; 5044 struct l1_ttable *l1; 5045 struct pglist plist; 5046 struct vm_page *m; 5047 pd_entry_t *pl1pt; 5048 pt_entry_t *ptep, pte; 5049 vaddr_t va, eva; 5050 u_int loop, needed; 5051 int error; 5052 5053 pool_setlowat(&pmap_l2ptp_pool, 5054 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5055 pool_setlowat(&pmap_l2dtable_pool, 5056 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5057 5058 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5059 needed -= 1; 5060 5061 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5062 5063 for (loop = 0; loop < needed; loop++, l1++) { 5064 /* Allocate a L1 page table */ 5065 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5066 if (va == 0) 5067 panic("Cannot allocate L1 KVM"); 5068 5069 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5070 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5071 if (error) 5072 panic("Cannot allocate L1 physical pages"); 5073 5074 m = TAILQ_FIRST(&plist); 5075 eva = va + L1_TABLE_SIZE; 5076 pl1pt = (pd_entry_t *)va; 5077 5078 while (m && va < eva) { 5079 paddr_t pa = VM_PAGE_TO_PHYS(m); 5080 5081 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 5082 5083 /* 5084 * Make sure the L1 descriptor table is mapped 5085 * with the cache-mode set to write-through. 5086 */ 5087 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5088 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5089 pte = *ptep; 5090 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5091 *ptep = pte; 5092 PTE_SYNC(ptep); 5093 cpu_tlb_flushD_SE(va); 5094 5095 va += PAGE_SIZE; 5096 m = TAILQ_NEXT(m, pageq); 5097 } 5098 5099 #ifdef DIAGNOSTIC 5100 if (m) 5101 panic("pmap_alloc_l1pt: pglist not empty"); 5102 #endif /* DIAGNOSTIC */ 5103 5104 pmap_init_l1(l1, pl1pt); 5105 } 5106 5107 #ifdef DEBUG 5108 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5109 needed); 5110 #endif 5111 } 5112 5113 /* 5114 * Note that the following routines are used by board-specific initialisation 5115 * code to configure the initial kernel page tables. 5116 * 5117 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5118 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5119 * behaviour of the old pmap, and provides an easy migration path for 5120 * initial bring-up of the new pmap on existing ports. Fortunately, 5121 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5122 * will be deprecated. 5123 * 5124 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5125 * tables. 5126 */ 5127 5128 /* 5129 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5130 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5131 * find them as necessary. 5132 * 5133 * Note that the data on this list MUST remain valid after initarm() returns, 5134 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5135 */ 5136 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5137 5138 static vaddr_t 5139 kernel_pt_lookup(paddr_t pa) 5140 { 5141 pv_addr_t *pv; 5142 5143 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5144 #ifndef ARM32_NEW_VM_LAYOUT 5145 if (pv->pv_pa == (pa & ~PGOFSET)) 5146 return (pv->pv_va | (pa & PGOFSET)); 5147 #else 5148 if (pv->pv_pa == pa) 5149 return (pv->pv_va); 5150 #endif 5151 } 5152 return (0); 5153 } 5154 5155 /* 5156 * pmap_map_section: 5157 * 5158 * Create a single section mapping. 5159 */ 5160 void 5161 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5162 { 5163 pd_entry_t *pde = (pd_entry_t *) l1pt; 5164 pd_entry_t fl; 5165 5166 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5167 5168 switch (cache) { 5169 case PTE_NOCACHE: 5170 default: 5171 fl = 0; 5172 break; 5173 5174 case PTE_CACHE: 5175 fl = pte_l1_s_cache_mode; 5176 break; 5177 5178 case PTE_PAGETABLE: 5179 fl = pte_l1_s_cache_mode_pt; 5180 break; 5181 } 5182 5183 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5184 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5185 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5186 } 5187 5188 /* 5189 * pmap_map_entry: 5190 * 5191 * Create a single page mapping. 5192 */ 5193 void 5194 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5195 { 5196 pd_entry_t *pde = (pd_entry_t *) l1pt; 5197 pt_entry_t fl; 5198 pt_entry_t *pte; 5199 5200 KASSERT(((va | pa) & PGOFSET) == 0); 5201 5202 switch (cache) { 5203 case PTE_NOCACHE: 5204 default: 5205 fl = 0; 5206 break; 5207 5208 case PTE_CACHE: 5209 fl = pte_l2_s_cache_mode; 5210 break; 5211 5212 case PTE_PAGETABLE: 5213 fl = pte_l2_s_cache_mode_pt; 5214 break; 5215 } 5216 5217 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5218 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5219 5220 #ifndef ARM32_NEW_VM_LAYOUT 5221 pte = (pt_entry_t *) 5222 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5223 #else 5224 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5225 #endif 5226 if (pte == NULL) 5227 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5228 5229 #ifndef ARM32_NEW_VM_LAYOUT 5230 pte[(va >> PGSHIFT) & 0x3ff] = 5231 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5232 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5233 #else 5234 pte[l2pte_index(va)] = 5235 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5236 PTE_SYNC(&pte[l2pte_index(va)]); 5237 #endif 5238 } 5239 5240 /* 5241 * pmap_link_l2pt: 5242 * 5243 * Link the L2 page table specified by "l2pv" into the L1 5244 * page table at the slot for "va". 5245 */ 5246 void 5247 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5248 { 5249 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5250 u_int slot = va >> L1_S_SHIFT; 5251 5252 #ifndef ARM32_NEW_VM_LAYOUT 5253 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5254 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5255 #endif 5256 5257 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5258 5259 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5260 #ifdef ARM32_NEW_VM_LAYOUT 5261 PTE_SYNC(&pde[slot]); 5262 #else 5263 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5264 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5265 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5266 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5267 #endif 5268 5269 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5270 } 5271 5272 /* 5273 * pmap_map_chunk: 5274 * 5275 * Map a chunk of memory using the most efficient mappings 5276 * possible (section, large page, small page) into the 5277 * provided L1 and L2 tables at the specified virtual address. 5278 */ 5279 vsize_t 5280 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5281 int prot, int cache) 5282 { 5283 pd_entry_t *pde = (pd_entry_t *) l1pt; 5284 pt_entry_t *pte, f1, f2s, f2l; 5285 vsize_t resid; 5286 int i; 5287 5288 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5289 5290 if (l1pt == 0) 5291 panic("pmap_map_chunk: no L1 table provided"); 5292 5293 #ifdef VERBOSE_INIT_ARM 5294 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5295 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5296 #endif 5297 5298 switch (cache) { 5299 case PTE_NOCACHE: 5300 default: 5301 f1 = 0; 5302 f2l = 0; 5303 f2s = 0; 5304 break; 5305 5306 case PTE_CACHE: 5307 f1 = pte_l1_s_cache_mode; 5308 f2l = pte_l2_l_cache_mode; 5309 f2s = pte_l2_s_cache_mode; 5310 break; 5311 5312 case PTE_PAGETABLE: 5313 f1 = pte_l1_s_cache_mode_pt; 5314 f2l = pte_l2_l_cache_mode_pt; 5315 f2s = pte_l2_s_cache_mode_pt; 5316 break; 5317 } 5318 5319 size = resid; 5320 5321 while (resid > 0) { 5322 /* See if we can use a section mapping. */ 5323 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5324 #ifdef VERBOSE_INIT_ARM 5325 printf("S"); 5326 #endif 5327 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5328 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5329 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5330 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5331 va += L1_S_SIZE; 5332 pa += L1_S_SIZE; 5333 resid -= L1_S_SIZE; 5334 continue; 5335 } 5336 5337 /* 5338 * Ok, we're going to use an L2 table. Make sure 5339 * one is actually in the corresponding L1 slot 5340 * for the current VA. 5341 */ 5342 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5343 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5344 5345 #ifndef ARM32_NEW_VM_LAYOUT 5346 pte = (pt_entry_t *) 5347 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5348 #else 5349 pte = (pt_entry_t *) kernel_pt_lookup( 5350 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5351 #endif 5352 if (pte == NULL) 5353 panic("pmap_map_chunk: can't find L2 table for VA" 5354 "0x%08lx", va); 5355 5356 /* See if we can use a L2 large page mapping. */ 5357 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5358 #ifdef VERBOSE_INIT_ARM 5359 printf("L"); 5360 #endif 5361 for (i = 0; i < 16; i++) { 5362 #ifndef ARM32_NEW_VM_LAYOUT 5363 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5364 L2_L_PROTO | pa | 5365 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5366 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5367 #else 5368 pte[l2pte_index(va) + i] = 5369 L2_L_PROTO | pa | 5370 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5371 PTE_SYNC(&pte[l2pte_index(va) + i]); 5372 #endif 5373 } 5374 va += L2_L_SIZE; 5375 pa += L2_L_SIZE; 5376 resid -= L2_L_SIZE; 5377 continue; 5378 } 5379 5380 /* Use a small page mapping. */ 5381 #ifdef VERBOSE_INIT_ARM 5382 printf("P"); 5383 #endif 5384 #ifndef ARM32_NEW_VM_LAYOUT 5385 pte[(va >> PGSHIFT) & 0x3ff] = 5386 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5387 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5388 #else 5389 pte[l2pte_index(va)] = 5390 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5391 PTE_SYNC(&pte[l2pte_index(va)]); 5392 #endif 5393 va += PAGE_SIZE; 5394 pa += PAGE_SIZE; 5395 resid -= PAGE_SIZE; 5396 } 5397 #ifdef VERBOSE_INIT_ARM 5398 printf("\n"); 5399 #endif 5400 return (size); 5401 } 5402 5403 /********************** Static device map routines ***************************/ 5404 5405 static const struct pmap_devmap *pmap_devmap_table; 5406 5407 /* 5408 * Register the devmap table. This is provided in case early console 5409 * initialization needs to register mappings created by bootstrap code 5410 * before pmap_devmap_bootstrap() is called. 5411 */ 5412 void 5413 pmap_devmap_register(const struct pmap_devmap *table) 5414 { 5415 5416 pmap_devmap_table = table; 5417 } 5418 5419 /* 5420 * Map all of the static regions in the devmap table, and remember 5421 * the devmap table so other parts of the kernel can look up entries 5422 * later. 5423 */ 5424 void 5425 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5426 { 5427 int i; 5428 5429 pmap_devmap_table = table; 5430 5431 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5432 #ifdef VERBOSE_INIT_ARM 5433 printf("devmap: %08lx -> %08lx @ %08lx\n", 5434 pmap_devmap_table[i].pd_pa, 5435 pmap_devmap_table[i].pd_pa + 5436 pmap_devmap_table[i].pd_size - 1, 5437 pmap_devmap_table[i].pd_va); 5438 #endif 5439 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5440 pmap_devmap_table[i].pd_pa, 5441 pmap_devmap_table[i].pd_size, 5442 pmap_devmap_table[i].pd_prot, 5443 pmap_devmap_table[i].pd_cache); 5444 } 5445 } 5446 5447 const struct pmap_devmap * 5448 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5449 { 5450 uint64_t endpa; 5451 int i; 5452 5453 if (pmap_devmap_table == NULL) 5454 return (NULL); 5455 5456 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5457 5458 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5459 if (pa >= pmap_devmap_table[i].pd_pa && 5460 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5461 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5462 return (&pmap_devmap_table[i]); 5463 } 5464 5465 return (NULL); 5466 } 5467 5468 const struct pmap_devmap * 5469 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5470 { 5471 int i; 5472 5473 if (pmap_devmap_table == NULL) 5474 return (NULL); 5475 5476 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5477 if (va >= pmap_devmap_table[i].pd_va && 5478 va + size - 1 <= pmap_devmap_table[i].pd_va + 5479 pmap_devmap_table[i].pd_size - 1) 5480 return (&pmap_devmap_table[i]); 5481 } 5482 5483 return (NULL); 5484 } 5485 5486 /********************** PTE initialization routines **************************/ 5487 5488 /* 5489 * These routines are called when the CPU type is identified to set up 5490 * the PTE prototypes, cache modes, etc. 5491 * 5492 * The variables are always here, just in case LKMs need to reference 5493 * them (though, they shouldn't). 5494 */ 5495 5496 pt_entry_t pte_l1_s_cache_mode; 5497 pt_entry_t pte_l1_s_cache_mode_pt; 5498 pt_entry_t pte_l1_s_cache_mask; 5499 5500 pt_entry_t pte_l2_l_cache_mode; 5501 pt_entry_t pte_l2_l_cache_mode_pt; 5502 pt_entry_t pte_l2_l_cache_mask; 5503 5504 pt_entry_t pte_l2_s_cache_mode; 5505 pt_entry_t pte_l2_s_cache_mode_pt; 5506 pt_entry_t pte_l2_s_cache_mask; 5507 5508 pt_entry_t pte_l2_s_prot_u; 5509 pt_entry_t pte_l2_s_prot_w; 5510 pt_entry_t pte_l2_s_prot_mask; 5511 5512 pt_entry_t pte_l1_s_proto; 5513 pt_entry_t pte_l1_c_proto; 5514 pt_entry_t pte_l2_s_proto; 5515 5516 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5517 void (*pmap_zero_page_func)(paddr_t); 5518 5519 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5520 void 5521 pmap_pte_init_generic(void) 5522 { 5523 5524 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5525 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5526 5527 pte_l2_l_cache_mode = L2_B|L2_C; 5528 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5529 5530 pte_l2_s_cache_mode = L2_B|L2_C; 5531 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5532 5533 /* 5534 * If we have a write-through cache, set B and C. If 5535 * we have a write-back cache, then we assume setting 5536 * only C will make those pages write-through. 5537 */ 5538 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5539 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5540 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5541 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5542 } else { 5543 #if ARM_MMU_V6 > 1 5544 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5545 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5546 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5547 #else 5548 pte_l1_s_cache_mode_pt = L1_S_C; 5549 pte_l2_l_cache_mode_pt = L2_C; 5550 pte_l2_s_cache_mode_pt = L2_C; 5551 #endif 5552 } 5553 5554 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5555 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5556 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5557 5558 pte_l1_s_proto = L1_S_PROTO_generic; 5559 pte_l1_c_proto = L1_C_PROTO_generic; 5560 pte_l2_s_proto = L2_S_PROTO_generic; 5561 5562 pmap_copy_page_func = pmap_copy_page_generic; 5563 pmap_zero_page_func = pmap_zero_page_generic; 5564 } 5565 5566 #if defined(CPU_ARM8) 5567 void 5568 pmap_pte_init_arm8(void) 5569 { 5570 5571 /* 5572 * ARM8 is compatible with generic, but we need to use 5573 * the page tables uncached. 5574 */ 5575 pmap_pte_init_generic(); 5576 5577 pte_l1_s_cache_mode_pt = 0; 5578 pte_l2_l_cache_mode_pt = 0; 5579 pte_l2_s_cache_mode_pt = 0; 5580 } 5581 #endif /* CPU_ARM8 */ 5582 5583 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5584 void 5585 pmap_pte_init_arm9(void) 5586 { 5587 5588 /* 5589 * ARM9 is compatible with generic, but we want to use 5590 * write-through caching for now. 5591 */ 5592 pmap_pte_init_generic(); 5593 5594 pte_l1_s_cache_mode = L1_S_C; 5595 pte_l2_l_cache_mode = L2_C; 5596 pte_l2_s_cache_mode = L2_C; 5597 5598 pte_l1_s_cache_mode_pt = L1_S_C; 5599 pte_l2_l_cache_mode_pt = L2_C; 5600 pte_l2_s_cache_mode_pt = L2_C; 5601 } 5602 #endif /* CPU_ARM9 */ 5603 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5604 5605 #if defined(CPU_ARM10) 5606 void 5607 pmap_pte_init_arm10(void) 5608 { 5609 5610 /* 5611 * ARM10 is compatible with generic, but we want to use 5612 * write-through caching for now. 5613 */ 5614 pmap_pte_init_generic(); 5615 5616 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 5617 pte_l2_l_cache_mode = L2_B | L2_C; 5618 pte_l2_s_cache_mode = L2_B | L2_C; 5619 5620 pte_l1_s_cache_mode_pt = L1_S_C; 5621 pte_l2_l_cache_mode_pt = L2_C; 5622 pte_l2_s_cache_mode_pt = L2_C; 5623 5624 } 5625 #endif /* CPU_ARM10 */ 5626 5627 #if ARM_MMU_SA1 == 1 5628 void 5629 pmap_pte_init_sa1(void) 5630 { 5631 5632 /* 5633 * The StrongARM SA-1 cache does not have a write-through 5634 * mode. So, do the generic initialization, then reset 5635 * the page table cache mode to B=1,C=1, and note that 5636 * the PTEs need to be sync'd. 5637 */ 5638 pmap_pte_init_generic(); 5639 5640 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5641 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5642 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5643 5644 pmap_needs_pte_sync = 1; 5645 } 5646 #endif /* ARM_MMU_SA1 == 1*/ 5647 5648 #if ARM_MMU_XSCALE == 1 5649 #if (ARM_NMMUS > 1) 5650 static u_int xscale_use_minidata; 5651 #endif 5652 5653 void 5654 pmap_pte_init_xscale(void) 5655 { 5656 uint32_t auxctl; 5657 int write_through = 0; 5658 5659 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5660 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 5661 5662 pte_l2_l_cache_mode = L2_B|L2_C; 5663 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 5664 5665 pte_l2_s_cache_mode = L2_B|L2_C; 5666 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 5667 5668 pte_l1_s_cache_mode_pt = L1_S_C; 5669 pte_l2_l_cache_mode_pt = L2_C; 5670 pte_l2_s_cache_mode_pt = L2_C; 5671 5672 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 5673 /* 5674 * The XScale core has an enhanced mode where writes that 5675 * miss the cache cause a cache line to be allocated. This 5676 * is significantly faster than the traditional, write-through 5677 * behavior of this case. 5678 */ 5679 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 5680 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 5681 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 5682 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 5683 5684 #ifdef XSCALE_CACHE_WRITE_THROUGH 5685 /* 5686 * Some versions of the XScale core have various bugs in 5687 * their cache units, the work-around for which is to run 5688 * the cache in write-through mode. Unfortunately, this 5689 * has a major (negative) impact on performance. So, we 5690 * go ahead and run fast-and-loose, in the hopes that we 5691 * don't line up the planets in a way that will trip the 5692 * bugs. 5693 * 5694 * However, we give you the option to be slow-but-correct. 5695 */ 5696 write_through = 1; 5697 #elif defined(XSCALE_CACHE_WRITE_BACK) 5698 /* force write back cache mode */ 5699 write_through = 0; 5700 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 5701 /* 5702 * Intel PXA2[15]0 processors are known to have a bug in 5703 * write-back cache on revision 4 and earlier (stepping 5704 * A[01] and B[012]). Fixed for C0 and later. 5705 */ 5706 { 5707 uint32_t id, type; 5708 5709 id = cpufunc_id(); 5710 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 5711 5712 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 5713 if ((id & CPU_ID_REVISION_MASK) < 5) { 5714 /* write through for stepping A0-1 and B0-2 */ 5715 write_through = 1; 5716 } 5717 } 5718 } 5719 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 5720 5721 if (write_through) { 5722 pte_l1_s_cache_mode = L1_S_C; 5723 pte_l2_l_cache_mode = L2_C; 5724 pte_l2_s_cache_mode = L2_C; 5725 } 5726 5727 #if (ARM_NMMUS > 1) 5728 xscale_use_minidata = 1; 5729 #endif 5730 5731 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 5732 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 5733 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 5734 5735 pte_l1_s_proto = L1_S_PROTO_xscale; 5736 pte_l1_c_proto = L1_C_PROTO_xscale; 5737 pte_l2_s_proto = L2_S_PROTO_xscale; 5738 5739 pmap_copy_page_func = pmap_copy_page_xscale; 5740 pmap_zero_page_func = pmap_zero_page_xscale; 5741 5742 /* 5743 * Disable ECC protection of page table access, for now. 5744 */ 5745 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 5746 auxctl &= ~XSCALE_AUXCTL_P; 5747 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 5748 } 5749 5750 /* 5751 * xscale_setup_minidata: 5752 * 5753 * Set up the mini-data cache clean area. We require the 5754 * caller to allocate the right amount of physically and 5755 * virtually contiguous space. 5756 */ 5757 void 5758 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 5759 { 5760 extern vaddr_t xscale_minidata_clean_addr; 5761 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 5762 pd_entry_t *pde = (pd_entry_t *) l1pt; 5763 pt_entry_t *pte; 5764 vsize_t size; 5765 uint32_t auxctl; 5766 5767 xscale_minidata_clean_addr = va; 5768 5769 /* Round it to page size. */ 5770 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 5771 5772 for (; size != 0; 5773 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 5774 #ifndef ARM32_NEW_VM_LAYOUT 5775 pte = (pt_entry_t *) 5776 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5777 #else 5778 pte = (pt_entry_t *) kernel_pt_lookup( 5779 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5780 #endif 5781 if (pte == NULL) 5782 panic("xscale_setup_minidata: can't find L2 table for " 5783 "VA 0x%08lx", va); 5784 #ifndef ARM32_NEW_VM_LAYOUT 5785 pte[(va >> PGSHIFT) & 0x3ff] = 5786 #else 5787 pte[l2pte_index(va)] = 5788 #endif 5789 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 5790 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 5791 } 5792 5793 /* 5794 * Configure the mini-data cache for write-back with 5795 * read/write-allocate. 5796 * 5797 * NOTE: In order to reconfigure the mini-data cache, we must 5798 * make sure it contains no valid data! In order to do that, 5799 * we must issue a global data cache invalidate command! 5800 * 5801 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 5802 * THIS IS VERY IMPORTANT! 5803 */ 5804 5805 /* Invalidate data and mini-data. */ 5806 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 5807 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 5808 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 5809 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 5810 } 5811 5812 /* 5813 * Change the PTEs for the specified kernel mappings such that they 5814 * will use the mini data cache instead of the main data cache. 5815 */ 5816 void 5817 pmap_uarea(vaddr_t va) 5818 { 5819 struct l2_bucket *l2b; 5820 pt_entry_t *ptep, *sptep, pte; 5821 vaddr_t next_bucket, eva; 5822 5823 #if (ARM_NMMUS > 1) 5824 if (xscale_use_minidata == 0) 5825 return; 5826 #endif 5827 5828 eva = va + USPACE; 5829 5830 while (va < eva) { 5831 next_bucket = L2_NEXT_BUCKET(va); 5832 if (next_bucket > eva) 5833 next_bucket = eva; 5834 5835 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5836 KDASSERT(l2b != NULL); 5837 5838 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 5839 5840 while (va < next_bucket) { 5841 pte = *ptep; 5842 if (!l2pte_minidata(pte)) { 5843 cpu_dcache_wbinv_range(va, PAGE_SIZE); 5844 cpu_tlb_flushD_SE(va); 5845 *ptep = pte & ~L2_B; 5846 } 5847 ptep++; 5848 va += PAGE_SIZE; 5849 } 5850 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 5851 } 5852 cpu_cpwait(); 5853 } 5854 #endif /* ARM_MMU_XSCALE == 1 */ 5855 5856 #if defined(DDB) 5857 /* 5858 * A couple of ddb-callable functions for dumping pmaps 5859 */ 5860 void pmap_dump_all(void); 5861 void pmap_dump(pmap_t); 5862 5863 void 5864 pmap_dump_all(void) 5865 { 5866 pmap_t pm; 5867 5868 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 5869 if (pm == pmap_kernel()) 5870 continue; 5871 pmap_dump(pm); 5872 printf("\n"); 5873 } 5874 } 5875 5876 static pt_entry_t ncptes[64]; 5877 static void pmap_dump_ncpg(pmap_t); 5878 5879 void 5880 pmap_dump(pmap_t pm) 5881 { 5882 struct l2_dtable *l2; 5883 struct l2_bucket *l2b; 5884 pt_entry_t *ptep, pte; 5885 vaddr_t l2_va, l2b_va, va; 5886 int i, j, k, occ, rows = 0; 5887 5888 if (pm == pmap_kernel()) 5889 printf("pmap_kernel (%p): ", pm); 5890 else 5891 printf("user pmap (%p): ", pm); 5892 5893 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 5894 5895 l2_va = 0; 5896 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 5897 l2 = pm->pm_l2[i]; 5898 5899 if (l2 == NULL || l2->l2_occupancy == 0) 5900 continue; 5901 5902 l2b_va = l2_va; 5903 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 5904 l2b = &l2->l2_bucket[j]; 5905 5906 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 5907 continue; 5908 5909 ptep = l2b->l2b_kva; 5910 5911 for (k = 0; k < 256 && ptep[k] == 0; k++) 5912 ; 5913 5914 k &= ~63; 5915 occ = l2b->l2b_occupancy; 5916 va = l2b_va + (k * 4096); 5917 for (; k < 256; k++, va += 0x1000) { 5918 char ch = ' '; 5919 if ((k % 64) == 0) { 5920 if ((rows % 8) == 0) { 5921 printf( 5922 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 5923 } 5924 printf("%08lx: ", va); 5925 } 5926 5927 ncptes[k & 63] = 0; 5928 pte = ptep[k]; 5929 if (pte == 0) { 5930 ch = '.'; 5931 } else { 5932 occ--; 5933 switch (pte & 0x0c) { 5934 case 0x00: 5935 ch = 'D'; /* No cache No buff */ 5936 break; 5937 case 0x04: 5938 ch = 'B'; /* No cache buff */ 5939 break; 5940 case 0x08: 5941 if (pte & 0x40) 5942 ch = 'm'; 5943 else 5944 ch = 'C'; /* Cache No buff */ 5945 break; 5946 case 0x0c: 5947 ch = 'F'; /* Cache Buff */ 5948 break; 5949 } 5950 5951 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 5952 ch += 0x20; 5953 5954 if ((pte & 0xc) == 0) 5955 ncptes[k & 63] = pte; 5956 } 5957 5958 if ((k % 64) == 63) { 5959 rows++; 5960 printf("%c\n", ch); 5961 pmap_dump_ncpg(pm); 5962 if (occ == 0) 5963 break; 5964 } else 5965 printf("%c", ch); 5966 } 5967 } 5968 } 5969 } 5970 5971 static void 5972 pmap_dump_ncpg(pmap_t pm) 5973 { 5974 struct vm_page *pg; 5975 struct pv_entry *pv; 5976 int i; 5977 5978 for (i = 0; i < 63; i++) { 5979 if (ncptes[i] == 0) 5980 continue; 5981 5982 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 5983 if (pg == NULL) 5984 continue; 5985 5986 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 5987 VM_PAGE_TO_PHYS(pg), 5988 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 5989 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 5990 5991 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 5992 printf(" %c va 0x%08lx, flags 0x%x\n", 5993 (pm == pv->pv_pmap) ? '*' : ' ', 5994 pv->pv_va, pv->pv_flags); 5995 } 5996 } 5997 } 5998 #endif 5999
Indexes created Sat Oct 25 16:10:12 GMT 2025