pmap.c revision 1.164.12.4
1 /* $NetBSD: pmap.c,v 1.164.12.4 2007/11/07 06:38:29 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 3. All advertising materials mentioning features or use of this software 82 * must display the following acknowledgement: 83 * This product includes software developed by the NetBSD 84 * Foundation, Inc. and its contributors. 85 * 4. Neither the name of The NetBSD Foundation nor the names of its 86 * contributors may be used to endorse or promote products derived 87 * from this software without specific prior written permission. 88 * 89 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 90 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 91 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 92 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 93 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 94 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 95 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 96 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 97 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 98 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 99 * POSSIBILITY OF SUCH DAMAGE. 100 */ 101 102 /* 103 * Copyright (c) 1994-1998 Mark Brinicombe. 104 * Copyright (c) 1994 Brini. 105 * All rights reserved. 106 * 107 * This code is derived from software written for Brini by Mark Brinicombe 108 * 109 * Redistribution and use in source and binary forms, with or without 110 * modification, are permitted provided that the following conditions 111 * are met: 112 * 1. Redistributions of source code must retain the above copyright 113 * notice, this list of conditions and the following disclaimer. 114 * 2. Redistributions in binary form must reproduce the above copyright 115 * notice, this list of conditions and the following disclaimer in the 116 * documentation and/or other materials provided with the distribution. 117 * 3. All advertising materials mentioning features or use of this software 118 * must display the following acknowledgement: 119 * This product includes software developed by Mark Brinicombe. 120 * 4. The name of the author may not be used to endorse or promote products 121 * derived from this software without specific prior written permission. 122 * 123 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 124 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 125 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 126 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 127 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 128 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 129 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 130 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 131 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 132 * 133 * RiscBSD kernel project 134 * 135 * pmap.c 136 * 137 * Machine dependant vm stuff 138 * 139 * Created : 20/09/94 140 */ 141 142 /* 143 * armv6 and VIPT cache support by 3am Software Foundry, 144 * Copyright (c) 2007 Danger Inc 145 */ 146 147 /* 148 * Performance improvements, UVM changes, overhauls and part-rewrites 149 * were contributed by Neil A. Carson <neil (at) causality.com>. 150 */ 151 152 /* 153 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 154 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 155 * Systems, Inc. 156 * 157 * There are still a few things outstanding at this time: 158 * 159 * - There are some unresolved issues for MP systems: 160 * 161 * o The L1 metadata needs a lock, or more specifically, some places 162 * need to acquire an exclusive lock when modifying L1 translation 163 * table entries. 164 * 165 * o When one cpu modifies an L1 entry, and that L1 table is also 166 * being used by another cpu, then the latter will need to be told 167 * that a tlb invalidation may be necessary. (But only if the old 168 * domain number in the L1 entry being over-written is currently 169 * the active domain on that cpu). I guess there are lots more tlb 170 * shootdown issues too... 171 * 172 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 173 * MP systems will lose big-time because of the MMU domain hack. 174 * The only way this can be solved (apart from moving the vector 175 * page to 0xffff0000) is to reserve the first 1MB of user address 176 * space for kernel use only. This would require re-linking all 177 * applications so that the text section starts above this 1MB 178 * boundary. 179 * 180 * o Tracking which VM space is resident in the cache/tlb has not yet 181 * been implemented for MP systems. 182 * 183 * o Finally, there is a pathological condition where two cpus running 184 * two separate processes (not lwps) which happen to share an L1 185 * can get into a fight over one or more L1 entries. This will result 186 * in a significant slow-down if both processes are in tight loops. 187 */ 188 189 /* 190 * Special compilation symbols 191 * PMAP_DEBUG - Build in pmap_debug_level code 192 */ 193 194 /* Include header files */ 195 196 #include "opt_cpuoptions.h" 197 #include "opt_pmap_debug.h" 198 #include "opt_ddb.h" 199 #include "opt_lockdebug.h" 200 #include "opt_multiprocessor.h" 201 202 #include <sys/types.h> 203 #include <sys/param.h> 204 #include <sys/kernel.h> 205 #include <sys/systm.h> 206 #include <sys/proc.h> 207 #include <sys/malloc.h> 208 #include <sys/user.h> 209 #include <sys/pool.h> 210 #include <sys/cdefs.h> 211 212 #include <uvm/uvm.h> 213 214 #include <machine/bus.h> 215 #include <machine/pmap.h> 216 #include <machine/pcb.h> 217 #include <machine/param.h> 218 #include <arm/arm32/katelib.h> 219 220 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.164.12.4 2007/11/07 06:38:29 matt Exp $"); 221 222 #ifdef PMAP_DEBUG 223 224 /* XXX need to get rid of all refs to this */ 225 int pmap_debug_level = 0; 226 227 /* 228 * for switching to potentially finer grained debugging 229 */ 230 #define PDB_FOLLOW 0x0001 231 #define PDB_INIT 0x0002 232 #define PDB_ENTER 0x0004 233 #define PDB_REMOVE 0x0008 234 #define PDB_CREATE 0x0010 235 #define PDB_PTPAGE 0x0020 236 #define PDB_GROWKERN 0x0040 237 #define PDB_BITS 0x0080 238 #define PDB_COLLECT 0x0100 239 #define PDB_PROTECT 0x0200 240 #define PDB_MAP_L1 0x0400 241 #define PDB_BOOTSTRAP 0x1000 242 #define PDB_PARANOIA 0x2000 243 #define PDB_WIRING 0x4000 244 #define PDB_PVDUMP 0x8000 245 #define PDB_VAC 0x10000 246 #define PDB_KENTER 0x20000 247 #define PDB_KREMOVE 0x40000 248 #define PDB_EXEC 0x80000 249 250 int debugmap = 1; 251 int pmapdebug = 0; 252 #define NPDEBUG(_lev_,_stat_) \ 253 if (pmapdebug & (_lev_)) \ 254 ((_stat_)) 255 256 #else /* PMAP_DEBUG */ 257 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 258 #endif /* PMAP_DEBUG */ 259 260 /* 261 * pmap_kernel() points here 262 */ 263 struct pmap kernel_pmap_store; 264 265 /* 266 * Which pmap is currently 'live' in the cache 267 * 268 * XXXSCW: Fix for SMP ... 269 */ 270 static pmap_t pmap_recent_user; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool pmap_pmap_pool; 278 static struct pool_cache pmap_pmap_cache; 279 static LIST_HEAD(, pmap) pmap_pmaps; 280 281 /* 282 * Pool of PV structures 283 */ 284 static struct pool pmap_pv_pool; 285 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 286 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 287 static struct pool_allocator pmap_bootstrap_pv_allocator = { 288 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 289 }; 290 291 /* 292 * Pool and cache of l2_dtable structures. 293 * We use a cache to avoid clearing the structures when they're 294 * allocated. (196 bytes) 295 */ 296 static struct pool pmap_l2dtable_pool; 297 static struct pool_cache pmap_l2dtable_cache; 298 static vaddr_t pmap_kernel_l2dtable_kva; 299 300 /* 301 * Pool and cache of L2 page descriptors. 302 * We use a cache to avoid clearing the descriptor table 303 * when they're allocated. (1KB) 304 */ 305 static struct pool pmap_l2ptp_pool; 306 static struct pool_cache pmap_l2ptp_cache; 307 static vaddr_t pmap_kernel_l2ptp_kva; 308 static paddr_t pmap_kernel_l2ptp_phys; 309 310 #ifdef PMAPCOUNT 311 #define PMAP_EVCNT_INITIALIZER(name) \ 312 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 313 314 #ifdef PMAP_CACHE_VIPT 315 static struct evcnt pmap_ev_vac_color_new = 316 PMAP_EVCNT_INITIALIZER("new page color"); 317 static struct evcnt pmap_ev_vac_color_reuse = 318 PMAP_EVCNT_INITIALIZER("ok first page color"); 319 static struct evcnt pmap_ev_vac_color_ok = 320 PMAP_EVCNT_INITIALIZER("ok page color"); 321 static struct evcnt pmap_ev_vac_color_change = 322 PMAP_EVCNT_INITIALIZER("change page color"); 323 static struct evcnt pmap_ev_vac_color_erase = 324 PMAP_EVCNT_INITIALIZER("erase page color"); 325 static struct evcnt pmap_ev_vac_color_none = 326 PMAP_EVCNT_INITIALIZER("no page color"); 327 static struct evcnt pmap_ev_vac_color_restore = 328 PMAP_EVCNT_INITIALIZER("restore page color"); 329 330 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 331 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 332 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 333 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 334 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 335 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 336 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 337 #endif 338 339 static struct evcnt pmap_ev_mappings = 340 PMAP_EVCNT_INITIALIZER("pages mapped"); 341 static struct evcnt pmap_ev_unmappings = 342 PMAP_EVCNT_INITIALIZER("pages unmapped"); 343 static struct evcnt pmap_ev_remappings = 344 PMAP_EVCNT_INITIALIZER("pages remapped"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 347 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 348 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 349 350 static struct evcnt pmap_ev_kernel_mappings = 351 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 352 static struct evcnt pmap_ev_kernel_unmappings = 353 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 354 static struct evcnt pmap_ev_kernel_remappings = 355 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 356 357 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 358 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 359 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 360 361 static struct evcnt pmap_ev_kenter_mappings = 362 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 363 static struct evcnt pmap_ev_kenter_unmappings = 364 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 365 static struct evcnt pmap_ev_kenter_remappings = 366 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 367 static struct evcnt pmap_ev_pt_mappings = 368 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 373 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 374 375 #ifdef PMAP_CACHE_VIPT 376 static struct evcnt pmap_ev_exec_mappings = 377 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 378 static struct evcnt pmap_ev_exec_cached = 379 PMAP_EVCNT_INITIALIZER("exec pages cached"); 380 381 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 382 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 383 384 static struct evcnt pmap_ev_exec_synced = 385 PMAP_EVCNT_INITIALIZER("exec pages synced"); 386 static struct evcnt pmap_ev_exec_synced_map = 387 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 388 static struct evcnt pmap_ev_exec_synced_unmap = 389 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 390 static struct evcnt pmap_ev_exec_synced_remap = 391 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 392 static struct evcnt pmap_ev_exec_synced_clearbit = 393 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 394 static struct evcnt pmap_ev_exec_synced_kremove = 395 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 396 397 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 399 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 400 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 401 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 402 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 403 404 static struct evcnt pmap_ev_exec_discarded_unmap = 405 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 406 static struct evcnt pmap_ev_exec_discarded_zero = 407 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 408 static struct evcnt pmap_ev_exec_discarded_copy = 409 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 410 static struct evcnt pmap_ev_exec_discarded_page_protect = 411 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 412 static struct evcnt pmap_ev_exec_discarded_clearbit = 413 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 414 static struct evcnt pmap_ev_exec_discarded_kremove = 415 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 416 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 422 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 423 #endif /* PMAP_CACHE_VIPT */ 424 425 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 426 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 427 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 428 429 EVCNT_ATTACH_STATIC(pmap_ev_updates); 430 EVCNT_ATTACH_STATIC(pmap_ev_collects); 431 EVCNT_ATTACH_STATIC(pmap_ev_activations); 432 433 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 434 #else 435 #define PMAPCOUNT(x) ((void)0) 436 #endif 437 438 /* 439 * pmap copy/zero page, and mem(5) hook point 440 */ 441 static pt_entry_t *csrc_pte, *cdst_pte; 442 static vaddr_t csrcp, cdstp; 443 char *memhook; 444 extern void *msgbufaddr; 445 446 /* 447 * Flag to indicate if pmap_init() has done its thing 448 */ 449 bool pmap_initialized; 450 451 /* 452 * Misc. locking data structures 453 */ 454 455 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 456 static struct lock pmap_main_lock; 457 458 #define PMAP_MAP_TO_HEAD_LOCK() \ 459 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 460 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 461 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 462 #define PMAP_HEAD_TO_MAP_LOCK() \ 463 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 464 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 465 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 466 #else 467 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 468 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 469 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 470 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 471 #endif 472 473 #define pmap_acquire_pmap_lock(pm) \ 474 do { \ 475 if ((pm) != pmap_kernel()) \ 476 simple_lock(&(pm)->pm_lock); \ 477 } while (/*CONSTCOND*/0) 478 479 #define pmap_release_pmap_lock(pm) \ 480 do { \ 481 if ((pm) != pmap_kernel()) \ 482 simple_unlock(&(pm)->pm_lock); \ 483 } while (/*CONSTCOND*/0) 484 485 486 /* 487 * Metadata for L1 translation tables. 488 */ 489 struct l1_ttable { 490 /* Entry on the L1 Table list */ 491 SLIST_ENTRY(l1_ttable) l1_link; 492 493 /* Entry on the L1 Least Recently Used list */ 494 TAILQ_ENTRY(l1_ttable) l1_lru; 495 496 /* Track how many domains are allocated from this L1 */ 497 volatile u_int l1_domain_use_count; 498 499 /* 500 * A free-list of domain numbers for this L1. 501 * We avoid using ffs() and a bitmap to track domains since ffs() 502 * is slow on ARM. 503 */ 504 u_int8_t l1_domain_first; 505 u_int8_t l1_domain_free[PMAP_DOMAINS]; 506 507 /* Physical address of this L1 page table */ 508 paddr_t l1_physaddr; 509 510 /* KVA of this L1 page table */ 511 pd_entry_t *l1_kva; 512 }; 513 514 /* 515 * Convert a virtual address into its L1 table index. That is, the 516 * index used to locate the L2 descriptor table pointer in an L1 table. 517 * This is basically used to index l1->l1_kva[]. 518 * 519 * Each L2 descriptor table represents 1MB of VA space. 520 */ 521 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 522 523 /* 524 * L1 Page Tables are tracked using a Least Recently Used list. 525 * - New L1s are allocated from the HEAD. 526 * - Freed L1s are added to the TAIl. 527 * - Recently accessed L1s (where an 'access' is some change to one of 528 * the userland pmaps which owns this L1) are moved to the TAIL. 529 */ 530 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 531 static struct simplelock l1_lru_lock; 532 533 /* 534 * A list of all L1 tables 535 */ 536 static SLIST_HEAD(, l1_ttable) l1_list; 537 538 /* 539 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 540 * 541 * This is normally 16MB worth L2 page descriptors for any given pmap. 542 * Reference counts are maintained for L2 descriptors so they can be 543 * freed when empty. 544 */ 545 struct l2_dtable { 546 /* The number of L2 page descriptors allocated to this l2_dtable */ 547 u_int l2_occupancy; 548 549 /* List of L2 page descriptors */ 550 struct l2_bucket { 551 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 552 paddr_t l2b_phys; /* Physical address of same */ 553 u_short l2b_l1idx; /* This L2 table's L1 index */ 554 u_short l2b_occupancy; /* How many active descriptors */ 555 } l2_bucket[L2_BUCKET_SIZE]; 556 }; 557 558 /* 559 * Given an L1 table index, calculate the corresponding l2_dtable index 560 * and bucket index within the l2_dtable. 561 */ 562 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 563 (L2_SIZE - 1)) 564 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 565 566 /* 567 * Given a virtual address, this macro returns the 568 * virtual address required to drop into the next L2 bucket. 569 */ 570 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 571 572 /* 573 * L2 allocation. 574 */ 575 #define pmap_alloc_l2_dtable() \ 576 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 577 #define pmap_free_l2_dtable(l2) \ 578 pool_cache_put(&pmap_l2dtable_cache, (l2)) 579 #define pmap_alloc_l2_ptp(pap) \ 580 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 581 PR_NOWAIT, (pap))) 582 583 /* 584 * We try to map the page tables write-through, if possible. However, not 585 * all CPUs have a write-through cache mode, so on those we have to sync 586 * the cache when we frob page tables. 587 * 588 * We try to evaluate this at compile time, if possible. However, it's 589 * not always possible to do that, hence this run-time var. 590 */ 591 int pmap_needs_pte_sync; 592 593 /* 594 * Real definition of pv_entry. 595 */ 596 struct pv_entry { 597 struct pv_entry *pv_next; /* next pv_entry */ 598 pmap_t pv_pmap; /* pmap where mapping lies */ 599 vaddr_t pv_va; /* virtual address for mapping */ 600 u_int pv_flags; /* flags */ 601 }; 602 603 /* 604 * Macro to determine if a mapping might be resident in the 605 * instruction cache and/or TLB 606 */ 607 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 608 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 609 610 /* 611 * Macro to determine if a mapping might be resident in the 612 * data cache and/or TLB 613 */ 614 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 615 616 /* 617 * Local prototypes 618 */ 619 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 620 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 621 pt_entry_t **); 622 static bool pmap_is_current(pmap_t); 623 static bool pmap_is_cached(pmap_t); 624 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 625 pmap_t, vaddr_t, u_int); 626 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 627 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 628 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 629 u_int, u_int); 630 631 static void pmap_pinit(pmap_t); 632 static int pmap_pmap_ctor(void *, void *, int); 633 634 static void pmap_alloc_l1(pmap_t); 635 static void pmap_free_l1(pmap_t); 636 static void pmap_use_l1(pmap_t); 637 638 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 639 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 640 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 641 static int pmap_l2ptp_ctor(void *, void *, int); 642 static int pmap_l2dtable_ctor(void *, void *, int); 643 644 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 645 #ifdef PMAP_CACHE_VIVT 646 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 647 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 648 #endif 649 650 static void pmap_clearbit(struct vm_page *, u_int); 651 #ifdef PMAP_CACHE_VIVT 652 static int pmap_clean_page(struct pv_entry *, bool); 653 #endif 654 #ifdef PMAP_CACHE_VIPT 655 static void pmap_syncicache_page(struct vm_page *); 656 static void pmap_flush_page(struct vm_page *); 657 #endif 658 static void pmap_page_remove(struct vm_page *); 659 660 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 661 static vaddr_t kernel_pt_lookup(paddr_t); 662 663 void pmap_switch(struct lwp *, struct lwp *); 664 665 666 /* 667 * External function prototypes 668 */ 669 extern void bzero_page(vaddr_t); 670 extern void bcopy_page(vaddr_t, vaddr_t); 671 672 /* 673 * Misc variables 674 */ 675 vaddr_t virtual_avail; 676 vaddr_t virtual_end; 677 vaddr_t pmap_curmaxkvaddr; 678 679 vaddr_t avail_start; 680 vaddr_t avail_end; 681 682 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 683 pv_addr_t kernelpages; 684 pv_addr_t kernel_l1pt; 685 pv_addr_t systempage; 686 687 /* Function to set the debug level of the pmap code */ 688 689 #ifdef PMAP_DEBUG 690 void 691 pmap_debug(int level) 692 { 693 pmap_debug_level = level; 694 printf("pmap_debug: level=%d\n", pmap_debug_level); 695 } 696 #endif /* PMAP_DEBUG */ 697 698 /* 699 * A bunch of routines to conditionally flush the caches/TLB depending 700 * on whether the specified pmap actually needs to be flushed at any 701 * given time. 702 */ 703 static inline void 704 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 705 { 706 707 if (pm->pm_cstate.cs_tlb_id) 708 cpu_tlb_flushID_SE(va); 709 } 710 711 static inline void 712 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 713 { 714 715 if (pm->pm_cstate.cs_tlb_d) 716 cpu_tlb_flushD_SE(va); 717 } 718 719 static inline void 720 pmap_tlb_flushID(pmap_t pm) 721 { 722 723 if (pm->pm_cstate.cs_tlb_id) { 724 cpu_tlb_flushID(); 725 pm->pm_cstate.cs_tlb = 0; 726 } 727 } 728 729 static inline void 730 pmap_tlb_flushD(pmap_t pm) 731 { 732 733 if (pm->pm_cstate.cs_tlb_d) { 734 cpu_tlb_flushD(); 735 pm->pm_cstate.cs_tlb_d = 0; 736 } 737 } 738 739 #ifdef PMAP_CACHE_VIVT 740 static inline void 741 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 742 { 743 if (pm->pm_cstate.cs_cache_id) { 744 cpu_idcache_wbinv_range(va, len); 745 } 746 } 747 748 static inline void 749 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 750 bool do_inv, bool rd_only) 751 { 752 753 if (pm->pm_cstate.cs_cache_d) { 754 if (do_inv) { 755 if (rd_only) 756 cpu_dcache_inv_range(va, len); 757 else 758 cpu_dcache_wbinv_range(va, len); 759 } else 760 if (!rd_only) 761 cpu_dcache_wb_range(va, len); 762 } 763 } 764 765 static inline void 766 pmap_idcache_wbinv_all(pmap_t pm) 767 { 768 if (pm->pm_cstate.cs_cache_id) { 769 cpu_idcache_wbinv_all(); 770 pm->pm_cstate.cs_cache = 0; 771 } 772 } 773 774 static inline void 775 pmap_dcache_wbinv_all(pmap_t pm) 776 { 777 if (pm->pm_cstate.cs_cache_d) { 778 cpu_dcache_wbinv_all(); 779 pm->pm_cstate.cs_cache_d = 0; 780 } 781 } 782 #endif /* PMAP_CACHE_VIVT */ 783 784 static inline bool 785 pmap_is_current(pmap_t pm) 786 { 787 788 if (pm == pmap_kernel() || 789 (curproc && curproc->p_vmspace->vm_map.pmap == pm)) 790 return true; 791 792 return false; 793 } 794 795 static inline bool 796 pmap_is_cached(pmap_t pm) 797 { 798 799 if (pm == pmap_kernel() || pmap_recent_user == NULL || 800 pmap_recent_user == pm) 801 return (true); 802 803 return false; 804 } 805 806 /* 807 * PTE_SYNC_CURRENT: 808 * 809 * Make sure the pte is written out to RAM. 810 * We need to do this for one of two cases: 811 * - We're dealing with the kernel pmap 812 * - There is no pmap active in the cache/tlb. 813 * - The specified pmap is 'active' in the cache/tlb. 814 */ 815 #ifdef PMAP_INCLUDE_PTE_SYNC 816 #define PTE_SYNC_CURRENT(pm, ptep) \ 817 do { \ 818 if (PMAP_NEEDS_PTE_SYNC && \ 819 pmap_is_cached(pm)) \ 820 PTE_SYNC(ptep); \ 821 } while (/*CONSTCOND*/0) 822 #else 823 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 824 #endif 825 826 /* 827 * main pv_entry manipulation functions: 828 * pmap_enter_pv: enter a mapping onto a vm_page list 829 * pmap_remove_pv: remove a mappiing from a vm_page list 830 * 831 * NOTE: pmap_enter_pv expects to lock the pvh itself 832 * pmap_remove_pv expects te caller to lock the pvh before calling 833 */ 834 835 /* 836 * pmap_enter_pv: enter a mapping onto a vm_page lst 837 * 838 * => caller should hold the proper lock on pmap_main_lock 839 * => caller should have pmap locked 840 * => we will gain the lock on the vm_page and allocate the new pv_entry 841 * => caller should adjust ptp's wire_count before calling 842 * => caller should not adjust pmap's wire_count 843 */ 844 static void 845 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 846 vaddr_t va, u_int flags) 847 { 848 849 NPDEBUG(PDB_PVDUMP, 850 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 851 852 pve->pv_pmap = pm; 853 pve->pv_va = va; 854 pve->pv_flags = flags; 855 856 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 857 pve->pv_next = pg->mdpage.pvh_list; /* add to ... */ 858 pg->mdpage.pvh_list = pve; /* ... locked list */ 859 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 860 if (pm == pmap_kernel()) { 861 PMAPCOUNT(kernel_mappings); 862 if (flags & PVF_WRITE) 863 pg->mdpage.krw_mappings++; 864 else 865 pg->mdpage.kro_mappings++; 866 } else 867 if (flags & PVF_WRITE) 868 pg->mdpage.urw_mappings++; 869 else 870 pg->mdpage.uro_mappings++; 871 872 #ifdef PMAP_CACHE_VIPT 873 /* 874 * If this is an exec mapping and its the first exec mapping 875 * for this page, make sure to sync the I-cache. 876 */ 877 if (PV_IS_EXEC_P(flags)) { 878 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 879 pmap_syncicache_page(pg); 880 PMAPCOUNT(exec_synced_map); 881 } 882 PMAPCOUNT(exec_mappings); 883 } 884 #endif 885 886 PMAPCOUNT(mappings); 887 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 888 889 if (pve->pv_flags & PVF_WIRED) 890 ++pm->pm_stats.wired_count; 891 } 892 893 /* 894 * 895 * pmap_find_pv: Find a pv entry 896 * 897 * => caller should hold lock on vm_page 898 */ 899 static inline struct pv_entry * 900 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 901 { 902 struct pv_entry *pv; 903 904 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 905 if (pm == pv->pv_pmap && va == pv->pv_va) 906 break; 907 } 908 909 return (pv); 910 } 911 912 /* 913 * pmap_remove_pv: try to remove a mapping from a pv_list 914 * 915 * => caller should hold proper lock on pmap_main_lock 916 * => pmap should be locked 917 * => caller should hold lock on vm_page [so that attrs can be adjusted] 918 * => caller should adjust ptp's wire_count and free PTP if needed 919 * => caller should NOT adjust pmap's wire_count 920 * => we return the removed pve 921 */ 922 static struct pv_entry * 923 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 924 { 925 struct pv_entry *pve, **prevptr; 926 927 NPDEBUG(PDB_PVDUMP, 928 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 929 930 prevptr = &pg->mdpage.pvh_list; /* previous pv_entry pointer */ 931 pve = *prevptr; 932 933 while (pve) { 934 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 935 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 936 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 937 if (pve->pv_flags & PVF_WIRED) { 938 if (skip_wired) 939 return (NULL); 940 --pm->pm_stats.wired_count; 941 } 942 *prevptr = pve->pv_next; /* remove it! */ 943 if (pm == pmap_kernel()) { 944 PMAPCOUNT(kernel_unmappings); 945 if (pve->pv_flags & PVF_WRITE) 946 pg->mdpage.krw_mappings--; 947 else 948 pg->mdpage.kro_mappings--; 949 } else 950 if (pve->pv_flags & PVF_WRITE) 951 pg->mdpage.urw_mappings--; 952 else 953 pg->mdpage.uro_mappings--; 954 955 PMAPCOUNT(unmappings); 956 #ifdef PMAP_CACHE_VIPT 957 if (!(pve->pv_flags & PVF_WRITE)) 958 break; 959 /* 960 * If this page has had an exec mapping, then if 961 * this was the last mapping, discard the contents, 962 * otherwise sync the i-cache for this page. 963 */ 964 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 965 if (pg->mdpage.pvh_list == NULL) { 966 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 967 PMAPCOUNT(exec_discarded_unmap); 968 } else { 969 pmap_syncicache_page(pg); 970 PMAPCOUNT(exec_synced_unmap); 971 } 972 } 973 #endif /* PMAP_CACHE_VIPT */ 974 break; 975 } 976 prevptr = &pve->pv_next; /* previous pointer */ 977 pve = pve->pv_next; /* advance */ 978 } 979 980 return(pve); /* return removed pve */ 981 } 982 983 /* 984 * 985 * pmap_modify_pv: Update pv flags 986 * 987 * => caller should hold lock on vm_page [so that attrs can be adjusted] 988 * => caller should NOT adjust pmap's wire_count 989 * => caller must call pmap_vac_me_harder() if writable status of a page 990 * may have changed. 991 * => we return the old flags 992 * 993 * Modify a physical-virtual mapping in the pv table 994 */ 995 static u_int 996 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 997 u_int clr_mask, u_int set_mask) 998 { 999 struct pv_entry *npv; 1000 u_int flags, oflags; 1001 1002 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1003 return (0); 1004 1005 NPDEBUG(PDB_PVDUMP, 1006 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 1007 1008 /* 1009 * There is at least one VA mapping this page. 1010 */ 1011 1012 if (clr_mask & (PVF_REF | PVF_MOD)) 1013 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1014 1015 oflags = npv->pv_flags; 1016 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1017 1018 if ((flags ^ oflags) & PVF_WIRED) { 1019 if (flags & PVF_WIRED) 1020 ++pm->pm_stats.wired_count; 1021 else 1022 --pm->pm_stats.wired_count; 1023 } 1024 1025 if ((flags ^ oflags) & PVF_WRITE) { 1026 if (pm == pmap_kernel()) { 1027 if (flags & PVF_WRITE) { 1028 pg->mdpage.krw_mappings++; 1029 pg->mdpage.kro_mappings--; 1030 } else { 1031 pg->mdpage.kro_mappings++; 1032 pg->mdpage.krw_mappings--; 1033 } 1034 } else 1035 if (flags & PVF_WRITE) { 1036 pg->mdpage.urw_mappings++; 1037 pg->mdpage.uro_mappings--; 1038 } else { 1039 pg->mdpage.uro_mappings++; 1040 pg->mdpage.urw_mappings--; 1041 } 1042 } 1043 #ifdef PMAP_CACHE_VIPT 1044 /* 1045 * We have two cases here: the first is from enter_pv (new exec 1046 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1047 * Since in latter, pmap_enter_pv won't do anything, we just have 1048 * to do what pmap_remove_pv would do. 1049 */ 1050 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1051 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1052 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1053 pmap_syncicache_page(pg); 1054 PMAPCOUNT(exec_synced_remap); 1055 } 1056 #endif 1057 1058 PMAPCOUNT(remappings); 1059 1060 return (oflags); 1061 } 1062 1063 /* 1064 * Allocate an L1 translation table for the specified pmap. 1065 * This is called at pmap creation time. 1066 */ 1067 static void 1068 pmap_alloc_l1(pmap_t pm) 1069 { 1070 struct l1_ttable *l1; 1071 u_int8_t domain; 1072 1073 /* 1074 * Remove the L1 at the head of the LRU list 1075 */ 1076 simple_lock(&l1_lru_lock); 1077 l1 = TAILQ_FIRST(&l1_lru_list); 1078 KDASSERT(l1 != NULL); 1079 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1080 1081 /* 1082 * Pick the first available domain number, and update 1083 * the link to the next number. 1084 */ 1085 domain = l1->l1_domain_first; 1086 l1->l1_domain_first = l1->l1_domain_free[domain]; 1087 1088 /* 1089 * If there are still free domain numbers in this L1, 1090 * put it back on the TAIL of the LRU list. 1091 */ 1092 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1093 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1094 1095 simple_unlock(&l1_lru_lock); 1096 1097 /* 1098 * Fix up the relevant bits in the pmap structure 1099 */ 1100 pm->pm_l1 = l1; 1101 pm->pm_domain = domain; 1102 } 1103 1104 /* 1105 * Free an L1 translation table. 1106 * This is called at pmap destruction time. 1107 */ 1108 static void 1109 pmap_free_l1(pmap_t pm) 1110 { 1111 struct l1_ttable *l1 = pm->pm_l1; 1112 1113 simple_lock(&l1_lru_lock); 1114 1115 /* 1116 * If this L1 is currently on the LRU list, remove it. 1117 */ 1118 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1119 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1120 1121 /* 1122 * Free up the domain number which was allocated to the pmap 1123 */ 1124 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1125 l1->l1_domain_first = pm->pm_domain; 1126 l1->l1_domain_use_count--; 1127 1128 /* 1129 * The L1 now must have at least 1 free domain, so add 1130 * it back to the LRU list. If the use count is zero, 1131 * put it at the head of the list, otherwise it goes 1132 * to the tail. 1133 */ 1134 if (l1->l1_domain_use_count == 0) 1135 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1136 else 1137 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1138 1139 simple_unlock(&l1_lru_lock); 1140 } 1141 1142 static inline void 1143 pmap_use_l1(pmap_t pm) 1144 { 1145 struct l1_ttable *l1; 1146 1147 /* 1148 * Do nothing if we're in interrupt context. 1149 * Access to an L1 by the kernel pmap must not affect 1150 * the LRU list. 1151 */ 1152 if (curcpu()->ci_intr_depth || pm == pmap_kernel()) 1153 return; 1154 1155 l1 = pm->pm_l1; 1156 1157 /* 1158 * If the L1 is not currently on the LRU list, just return 1159 */ 1160 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1161 return; 1162 1163 simple_lock(&l1_lru_lock); 1164 1165 /* 1166 * Check the use count again, now that we've acquired the lock 1167 */ 1168 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1169 simple_unlock(&l1_lru_lock); 1170 return; 1171 } 1172 1173 /* 1174 * Move the L1 to the back of the LRU list 1175 */ 1176 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1177 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1178 1179 simple_unlock(&l1_lru_lock); 1180 } 1181 1182 /* 1183 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1184 * 1185 * Free an L2 descriptor table. 1186 */ 1187 static inline void 1188 #ifndef PMAP_INCLUDE_PTE_SYNC 1189 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1190 #else 1191 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1192 #endif 1193 { 1194 #ifdef PMAP_INCLUDE_PTE_SYNC 1195 #ifdef PMAP_CACHE_VIVT 1196 /* 1197 * Note: With a write-back cache, we may need to sync this 1198 * L2 table before re-using it. 1199 * This is because it may have belonged to a non-current 1200 * pmap, in which case the cache syncs would have been 1201 * skipped for the pages that were being unmapped. If the 1202 * L2 table were then to be immediately re-allocated to 1203 * the *current* pmap, it may well contain stale mappings 1204 * which have not yet been cleared by a cache write-back 1205 * and so would still be visible to the mmu. 1206 */ 1207 if (need_sync) 1208 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1209 #endif /* PMAP_CACHE_VIVT */ 1210 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1211 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1212 } 1213 1214 /* 1215 * Returns a pointer to the L2 bucket associated with the specified pmap 1216 * and VA, or NULL if no L2 bucket exists for the address. 1217 */ 1218 static inline struct l2_bucket * 1219 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1220 { 1221 struct l2_dtable *l2; 1222 struct l2_bucket *l2b; 1223 u_short l1idx; 1224 1225 l1idx = L1_IDX(va); 1226 1227 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1228 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1229 return (NULL); 1230 1231 return (l2b); 1232 } 1233 1234 /* 1235 * Returns a pointer to the L2 bucket associated with the specified pmap 1236 * and VA. 1237 * 1238 * If no L2 bucket exists, perform the necessary allocations to put an L2 1239 * bucket/page table in place. 1240 * 1241 * Note that if a new L2 bucket/page was allocated, the caller *must* 1242 * increment the bucket occupancy counter appropriately *before* 1243 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1244 * the bucket/page in the meantime. 1245 */ 1246 static struct l2_bucket * 1247 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1248 { 1249 struct l2_dtable *l2; 1250 struct l2_bucket *l2b; 1251 u_short l1idx; 1252 1253 l1idx = L1_IDX(va); 1254 1255 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1256 /* 1257 * No mapping at this address, as there is 1258 * no entry in the L1 table. 1259 * Need to allocate a new l2_dtable. 1260 */ 1261 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1262 return (NULL); 1263 1264 /* 1265 * Link it into the parent pmap 1266 */ 1267 pm->pm_l2[L2_IDX(l1idx)] = l2; 1268 } 1269 1270 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1271 1272 /* 1273 * Fetch pointer to the L2 page table associated with the address. 1274 */ 1275 if (l2b->l2b_kva == NULL) { 1276 pt_entry_t *ptep; 1277 1278 /* 1279 * No L2 page table has been allocated. Chances are, this 1280 * is because we just allocated the l2_dtable, above. 1281 */ 1282 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1283 /* 1284 * Oops, no more L2 page tables available at this 1285 * time. We may need to deallocate the l2_dtable 1286 * if we allocated a new one above. 1287 */ 1288 if (l2->l2_occupancy == 0) { 1289 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1290 pmap_free_l2_dtable(l2); 1291 } 1292 return (NULL); 1293 } 1294 1295 l2->l2_occupancy++; 1296 l2b->l2b_kva = ptep; 1297 l2b->l2b_l1idx = l1idx; 1298 } 1299 1300 return (l2b); 1301 } 1302 1303 /* 1304 * One or more mappings in the specified L2 descriptor table have just been 1305 * invalidated. 1306 * 1307 * Garbage collect the metadata and descriptor table itself if necessary. 1308 * 1309 * The pmap lock must be acquired when this is called (not necessary 1310 * for the kernel pmap). 1311 */ 1312 static void 1313 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1314 { 1315 struct l2_dtable *l2; 1316 pd_entry_t *pl1pd, l1pd; 1317 pt_entry_t *ptep; 1318 u_short l1idx; 1319 1320 KDASSERT(count <= l2b->l2b_occupancy); 1321 1322 /* 1323 * Update the bucket's reference count according to how many 1324 * PTEs the caller has just invalidated. 1325 */ 1326 l2b->l2b_occupancy -= count; 1327 1328 /* 1329 * Note: 1330 * 1331 * Level 2 page tables allocated to the kernel pmap are never freed 1332 * as that would require checking all Level 1 page tables and 1333 * removing any references to the Level 2 page table. See also the 1334 * comment elsewhere about never freeing bootstrap L2 descriptors. 1335 * 1336 * We make do with just invalidating the mapping in the L2 table. 1337 * 1338 * This isn't really a big deal in practice and, in fact, leads 1339 * to a performance win over time as we don't need to continually 1340 * alloc/free. 1341 */ 1342 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1343 return; 1344 1345 /* 1346 * There are no more valid mappings in this level 2 page table. 1347 * Go ahead and NULL-out the pointer in the bucket, then 1348 * free the page table. 1349 */ 1350 l1idx = l2b->l2b_l1idx; 1351 ptep = l2b->l2b_kva; 1352 l2b->l2b_kva = NULL; 1353 1354 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1355 1356 /* 1357 * If the L1 slot matches the pmap's domain 1358 * number, then invalidate it. 1359 */ 1360 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1361 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1362 *pl1pd = 0; 1363 PTE_SYNC(pl1pd); 1364 } 1365 1366 /* 1367 * Release the L2 descriptor table back to the pool cache. 1368 */ 1369 #ifndef PMAP_INCLUDE_PTE_SYNC 1370 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1371 #else 1372 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1373 #endif 1374 1375 /* 1376 * Update the reference count in the associated l2_dtable 1377 */ 1378 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1379 if (--l2->l2_occupancy > 0) 1380 return; 1381 1382 /* 1383 * There are no more valid mappings in any of the Level 1 1384 * slots managed by this l2_dtable. Go ahead and NULL-out 1385 * the pointer in the parent pmap and free the l2_dtable. 1386 */ 1387 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1388 pmap_free_l2_dtable(l2); 1389 } 1390 1391 /* 1392 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1393 * structures. 1394 */ 1395 static int 1396 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1397 { 1398 #ifndef PMAP_INCLUDE_PTE_SYNC 1399 struct l2_bucket *l2b; 1400 pt_entry_t *ptep, pte; 1401 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1402 1403 /* 1404 * The mappings for these page tables were initially made using 1405 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1406 * mode will not be right for page table mappings. To avoid 1407 * polluting the pmap_kenter_pa() code with a special case for 1408 * page tables, we simply fix up the cache-mode here if it's not 1409 * correct. 1410 */ 1411 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1412 KDASSERT(l2b != NULL); 1413 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1414 pte = *ptep; 1415 1416 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1417 /* 1418 * Page tables must have the cache-mode set to Write-Thru. 1419 */ 1420 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1421 PTE_SYNC(ptep); 1422 cpu_tlb_flushD_SE(va); 1423 cpu_cpwait(); 1424 } 1425 #endif 1426 1427 memset(v, 0, L2_TABLE_SIZE_REAL); 1428 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1429 return (0); 1430 } 1431 1432 static int 1433 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1434 { 1435 1436 memset(v, 0, sizeof(struct l2_dtable)); 1437 return (0); 1438 } 1439 1440 static int 1441 pmap_pmap_ctor(void *arg, void *v, int flags) 1442 { 1443 1444 memset(v, 0, sizeof(struct pmap)); 1445 return (0); 1446 } 1447 1448 static void 1449 pmap_pinit(pmap_t pm) 1450 { 1451 struct l2_bucket *l2b; 1452 1453 if (vector_page < KERNEL_BASE) { 1454 /* 1455 * Map the vector page. 1456 */ 1457 pmap_enter(pm, vector_page, systempage.pv_pa, 1458 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1459 pmap_update(pm); 1460 1461 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1462 l2b = pmap_get_l2_bucket(pm, vector_page); 1463 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1464 L1_C_DOM(pm->pm_domain); 1465 } else 1466 pm->pm_pl1vec = NULL; 1467 } 1468 1469 #ifdef PMAP_CACHE_VIVT 1470 /* 1471 * Since we have a virtually indexed cache, we may need to inhibit caching if 1472 * there is more than one mapping and at least one of them is writable. 1473 * Since we purge the cache on every context switch, we only need to check for 1474 * other mappings within the same pmap, or kernel_pmap. 1475 * This function is also called when a page is unmapped, to possibly reenable 1476 * caching on any remaining mappings. 1477 * 1478 * The code implements the following logic, where: 1479 * 1480 * KW = # of kernel read/write pages 1481 * KR = # of kernel read only pages 1482 * UW = # of user read/write pages 1483 * UR = # of user read only pages 1484 * 1485 * KC = kernel mapping is cacheable 1486 * UC = user mapping is cacheable 1487 * 1488 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1489 * +--------------------------------------------- 1490 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1491 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1492 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1493 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1494 */ 1495 1496 static const int pmap_vac_flags[4][4] = { 1497 {-1, 0, 0, PVF_KNC}, 1498 {0, 0, PVF_NC, PVF_NC}, 1499 {0, PVF_NC, PVF_NC, PVF_NC}, 1500 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1501 }; 1502 1503 static inline int 1504 pmap_get_vac_flags(const struct vm_page *pg) 1505 { 1506 int kidx, uidx; 1507 1508 kidx = 0; 1509 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1510 kidx |= 1; 1511 if (pg->mdpage.krw_mappings) 1512 kidx |= 2; 1513 1514 uidx = 0; 1515 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1516 uidx |= 1; 1517 if (pg->mdpage.urw_mappings) 1518 uidx |= 2; 1519 1520 return (pmap_vac_flags[uidx][kidx]); 1521 } 1522 1523 static inline void 1524 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1525 { 1526 int nattr; 1527 1528 nattr = pmap_get_vac_flags(pg); 1529 1530 if (nattr < 0) { 1531 pg->mdpage.pvh_attrs &= ~PVF_NC; 1532 return; 1533 } 1534 1535 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1536 return; 1537 1538 if (pm == pmap_kernel()) 1539 pmap_vac_me_kpmap(pg, pm, va); 1540 else 1541 pmap_vac_me_user(pg, pm, va); 1542 1543 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1544 } 1545 1546 static void 1547 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1548 { 1549 u_int u_cacheable, u_entries; 1550 struct pv_entry *pv; 1551 pmap_t last_pmap = pm; 1552 1553 /* 1554 * Pass one, see if there are both kernel and user pmaps for 1555 * this page. Calculate whether there are user-writable or 1556 * kernel-writable pages. 1557 */ 1558 u_cacheable = 0; 1559 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1560 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1561 u_cacheable++; 1562 } 1563 1564 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1565 1566 /* 1567 * We know we have just been updating a kernel entry, so if 1568 * all user pages are already cacheable, then there is nothing 1569 * further to do. 1570 */ 1571 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1572 return; 1573 1574 if (u_entries) { 1575 /* 1576 * Scan over the list again, for each entry, if it 1577 * might not be set correctly, call pmap_vac_me_user 1578 * to recalculate the settings. 1579 */ 1580 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1581 /* 1582 * We know kernel mappings will get set 1583 * correctly in other calls. We also know 1584 * that if the pmap is the same as last_pmap 1585 * then we've just handled this entry. 1586 */ 1587 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1588 continue; 1589 1590 /* 1591 * If there are kernel entries and this page 1592 * is writable but non-cacheable, then we can 1593 * skip this entry also. 1594 */ 1595 if (pg->mdpage.k_mappings && 1596 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1597 (PVF_NC | PVF_WRITE)) 1598 continue; 1599 1600 /* 1601 * Similarly if there are no kernel-writable 1602 * entries and the page is already 1603 * read-only/cacheable. 1604 */ 1605 if (pg->mdpage.krw_mappings == 0 && 1606 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1607 continue; 1608 1609 /* 1610 * For some of the remaining cases, we know 1611 * that we must recalculate, but for others we 1612 * can't tell if they are correct or not, so 1613 * we recalculate anyway. 1614 */ 1615 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1616 } 1617 1618 if (pg->mdpage.k_mappings == 0) 1619 return; 1620 } 1621 1622 pmap_vac_me_user(pg, pm, va); 1623 } 1624 1625 static void 1626 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1627 { 1628 pmap_t kpmap = pmap_kernel(); 1629 struct pv_entry *pv, *npv; 1630 struct l2_bucket *l2b; 1631 pt_entry_t *ptep, pte; 1632 u_int entries = 0; 1633 u_int writable = 0; 1634 u_int cacheable_entries = 0; 1635 u_int kern_cacheable = 0; 1636 u_int other_writable = 0; 1637 1638 /* 1639 * Count mappings and writable mappings in this pmap. 1640 * Include kernel mappings as part of our own. 1641 * Keep a pointer to the first one. 1642 */ 1643 for (pv = npv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1644 /* Count mappings in the same pmap */ 1645 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1646 if (entries++ == 0) 1647 npv = pv; 1648 1649 /* Cacheable mappings */ 1650 if ((pv->pv_flags & PVF_NC) == 0) { 1651 cacheable_entries++; 1652 if (kpmap == pv->pv_pmap) 1653 kern_cacheable++; 1654 } 1655 1656 /* Writable mappings */ 1657 if (pv->pv_flags & PVF_WRITE) 1658 ++writable; 1659 } else 1660 if (pv->pv_flags & PVF_WRITE) 1661 other_writable = 1; 1662 } 1663 1664 /* 1665 * Enable or disable caching as necessary. 1666 * Note: the first entry might be part of the kernel pmap, 1667 * so we can't assume this is indicative of the state of the 1668 * other (maybe non-kpmap) entries. 1669 */ 1670 if ((entries > 1 && writable) || 1671 (entries > 0 && pm == kpmap && other_writable)) { 1672 if (cacheable_entries == 0) 1673 return; 1674 1675 for (pv = npv; pv; pv = pv->pv_next) { 1676 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1677 (pv->pv_flags & PVF_NC)) 1678 continue; 1679 1680 pv->pv_flags |= PVF_NC; 1681 1682 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1683 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1684 pte = *ptep & ~L2_S_CACHE_MASK; 1685 1686 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1687 l2pte_valid(pte)) { 1688 if (PV_BEEN_EXECD(pv->pv_flags)) { 1689 #ifdef PMAP_CACHE_VIVT 1690 pmap_idcache_wbinv_range(pv->pv_pmap, 1691 pv->pv_va, PAGE_SIZE); 1692 #endif 1693 pmap_tlb_flushID_SE(pv->pv_pmap, 1694 pv->pv_va); 1695 } else 1696 if (PV_BEEN_REFD(pv->pv_flags)) { 1697 #ifdef PMAP_CACHE_VIVT 1698 pmap_dcache_wb_range(pv->pv_pmap, 1699 pv->pv_va, PAGE_SIZE, true, 1700 (pv->pv_flags & PVF_WRITE) == 0); 1701 #endif 1702 pmap_tlb_flushD_SE(pv->pv_pmap, 1703 pv->pv_va); 1704 } 1705 } 1706 1707 *ptep = pte; 1708 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1709 } 1710 cpu_cpwait(); 1711 } else 1712 if (entries > cacheable_entries) { 1713 /* 1714 * Turn cacheing back on for some pages. If it is a kernel 1715 * page, only do so if there are no other writable pages. 1716 */ 1717 for (pv = npv; pv; pv = pv->pv_next) { 1718 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1719 (kpmap != pv->pv_pmap || other_writable))) 1720 continue; 1721 1722 pv->pv_flags &= ~PVF_NC; 1723 1724 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1725 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1726 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1727 1728 if (l2pte_valid(pte)) { 1729 if (PV_BEEN_EXECD(pv->pv_flags)) { 1730 pmap_tlb_flushID_SE(pv->pv_pmap, 1731 pv->pv_va); 1732 } else 1733 if (PV_BEEN_REFD(pv->pv_flags)) { 1734 pmap_tlb_flushD_SE(pv->pv_pmap, 1735 pv->pv_va); 1736 } 1737 } 1738 1739 *ptep = pte; 1740 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1741 } 1742 } 1743 } 1744 #endif 1745 1746 #ifdef PMAP_CACHE_VIPT 1747 /* 1748 * For virtually indexed / physically tagged caches, what we have to worry 1749 * about is illegal cache aliases. To prevent this, we must ensure that 1750 * virtual addresses that map the physical page use the same bits for those 1751 * bits masked by "arm_cache_prefer_mask" (bits 12+). If there is a conflict, 1752 * all mappings of the page must be non-cached. 1753 */ 1754 #if 0 1755 static inline vaddr_t 1756 pmap_check_sets(paddr_t pa) 1757 { 1758 extern int arm_dcache_l2_nsets; 1759 int set, way; 1760 vaddr_t mask = 0; 1761 int v; 1762 pa |= 1; 1763 for (set = 0; set < (1 << arm_dcache_l2_nsets); set++) { 1764 for (way = 0; way < 4; way++) { 1765 v = (way << 30) | (set << 5); 1766 asm("mcr p15, 3, %0, c15, c2, 0" :: "r"(v)); 1767 asm("mrc p15, 3, %0, c15, c0, 0" : "=r"(v)); 1768 1769 if ((v & (1 | ~(PAGE_SIZE-1))) == pa) { 1770 mask |= 1 << (set >> 7); 1771 } 1772 } 1773 } 1774 return mask; 1775 } 1776 #endif 1777 static void 1778 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1779 { 1780 struct pv_entry *pv, pv0; 1781 vaddr_t tst_mask; 1782 bool bad_alias; 1783 struct l2_bucket *l2b; 1784 pt_entry_t *ptep, pte, opte; 1785 1786 /* do we need to do anything? */ 1787 if (arm_cache_prefer_mask == 0) 1788 return; 1789 1790 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1791 pg, pm, va)); 1792 1793 #define popc4(x) \ 1794 (((0x94 >> ((x & 3) << 1)) & 3) + ((0x94 >> ((x & 12) >> 1)) & 3)) 1795 #if 0 1796 tst_mask = pmap_check_sets(pg->phys_addr); 1797 KASSERT(popc4(tst_mask) < 2); 1798 #endif 1799 1800 KASSERT(!va || pm || (pg->mdpage.pvh_attrs & PVF_KENTRY)); 1801 1802 /* Already a conflict? */ 1803 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1804 /* just an add, things are already non-cached */ 1805 bad_alias = false; 1806 if (va) { 1807 PMAPCOUNT(vac_color_none); 1808 bad_alias = true; 1809 goto fixup; 1810 } 1811 pv = pg->mdpage.pvh_list; 1812 /* the list can't be empty because it would be cachable */ 1813 if (pg->mdpage.pvh_attrs & PVF_KENTRY) { 1814 tst_mask = pg->mdpage.pvh_attrs; 1815 } else { 1816 KASSERT(pv); 1817 tst_mask = pv->pv_va; 1818 pv = pv->pv_next; 1819 } 1820 tst_mask &= arm_cache_prefer_mask; 1821 for (; pv && !bad_alias; pv = pv->pv_next) { 1822 /* if there's a bad alias, stop checking. */ 1823 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1824 bad_alias = true; 1825 } 1826 /* If no conflicting colors, set everything back to cached */ 1827 if (!bad_alias) { 1828 PMAPCOUNT(vac_color_restore); 1829 pg->mdpage.pvh_attrs |= PVF_COLORED; 1830 if (!(pg->mdpage.pvh_attrs & PVF_KENTRY)) { 1831 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1832 pg->mdpage.pvh_attrs |= tst_mask; 1833 } 1834 pg->mdpage.pvh_attrs &= ~PVF_NC; 1835 } else { 1836 KASSERT(pg->mdpage.pvh_list != NULL); 1837 KASSERT((pg->mdpage.pvh_attrs & PVF_KENTRY) 1838 || pg->mdpage.pvh_list->pv_next != NULL); 1839 } 1840 } else if (!va) { 1841 KASSERT(pmap_is_page_colored_p(pg)); 1842 if (pm == NULL) 1843 pg->mdpage.pvh_attrs &= 1844 (PAGE_SIZE - 1) | arm_cache_prefer_mask; 1845 return; 1846 } else if (!pmap_is_page_colored_p(pg)) { 1847 /* not colored so we just use its color */ 1848 PMAPCOUNT(vac_color_new); 1849 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1850 if (pm == NULL) 1851 pg->mdpage.pvh_attrs |= PVF_COLORED | va; 1852 else 1853 pg->mdpage.pvh_attrs |= PVF_COLORED 1854 | (va & arm_cache_prefer_mask); 1855 return; 1856 } else if (!((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask)) { 1857 if (pm == NULL) { 1858 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1859 pg->mdpage.pvh_attrs |= va; 1860 } 1861 if (pg->mdpage.pvh_list) 1862 PMAPCOUNT(vac_color_reuse); 1863 else 1864 PMAPCOUNT(vac_color_ok); 1865 /* matching color, just return */ 1866 return; 1867 } else { 1868 /* color conflict. evict from cache. */ 1869 pmap_flush_page(pg); 1870 1871 /* the list can't be empty because this was a enter/modify */ 1872 pv = pg->mdpage.pvh_list; 1873 KASSERT((pg->mdpage.pvh_attrs & PVF_KENTRY) || pv); 1874 1875 /* 1876 * If there's only one mapped page, change color to the 1877 * page's new color and return. 1878 */ 1879 if (((pg->mdpage.pvh_attrs & PVF_KENTRY) 1880 ? pv : pv->pv_next) == NULL) { 1881 PMAPCOUNT(vac_color_change); 1882 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1883 if (pm == NULL) 1884 pg->mdpage.pvh_attrs |= va; 1885 else 1886 pg->mdpage.pvh_attrs |= 1887 (va & arm_cache_prefer_mask); 1888 return; 1889 } 1890 bad_alias = true; 1891 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 1892 pg->mdpage.pvh_attrs |= PVF_NC; 1893 PMAPCOUNT(vac_color_erase); 1894 } 1895 1896 fixup: 1897 /* 1898 * If the pmap is NULL, then we got called from pmap_kenter_pa 1899 * and we must save the kenter'ed va. And this changes the 1900 * color to match the kenter'ed page. if this is a remove clear 1901 * saved va bits which retaining the color bits. 1902 */ 1903 if (pm == NULL) { 1904 if (va) { 1905 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1); 1906 pg->mdpage.pvh_attrs |= va; 1907 } else { 1908 pg->mdpage.pvh_attrs &= 1909 ((PAGE_SIZE - 1) | arm_cache_prefer_mask); 1910 } 1911 } 1912 1913 pv = pg->mdpage.pvh_list; 1914 1915 /* 1916 * If this page has an kenter'ed mapping, fake up a pv entry. 1917 */ 1918 if (__predict_false(pg->mdpage.pvh_attrs & PVF_KENTRY)) { 1919 pv0.pv_pmap = pmap_kernel(); 1920 pv0.pv_va = pg->mdpage.pvh_attrs & ~(PAGE_SIZE - 1); 1921 pv0.pv_next = pv; 1922 pv0.pv_flags = PVF_REF; 1923 pv = &pv0; 1924 } 1925 1926 /* 1927 * Turn cacheing on/off for all pages. 1928 */ 1929 for (; pv; pv = pv->pv_next) { 1930 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1931 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1932 opte = *ptep; 1933 pte = opte & ~L2_S_CACHE_MASK; 1934 if (bad_alias) { 1935 pv->pv_flags |= PVF_NC; 1936 } else { 1937 pv->pv_flags &= ~PVF_NC; 1938 pte |= pte_l2_s_cache_mode; 1939 } 1940 if (opte == pte) /* only update is there's a change */ 1941 continue; 1942 1943 if (l2pte_valid(pte)) { 1944 if (PV_BEEN_EXECD(pv->pv_flags)) { 1945 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1946 } else if (PV_BEEN_REFD(pv->pv_flags)) { 1947 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 1948 } 1949 } 1950 1951 *ptep = pte; 1952 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1953 } 1954 } 1955 #endif /* PMAP_CACHE_VIPT */ 1956 1957 1958 /* 1959 * Modify pte bits for all ptes corresponding to the given physical address. 1960 * We use `maskbits' rather than `clearbits' because we're always passing 1961 * constants and the latter would require an extra inversion at run-time. 1962 */ 1963 static void 1964 pmap_clearbit(struct vm_page *pg, u_int maskbits) 1965 { 1966 struct l2_bucket *l2b; 1967 struct pv_entry *pv; 1968 pt_entry_t *ptep, npte, opte; 1969 pmap_t pm; 1970 vaddr_t va; 1971 u_int oflags; 1972 #ifdef PMAP_CACHE_VIPT 1973 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 1974 bool need_syncicache = false; 1975 bool did_syncicache = false; 1976 #endif 1977 1978 NPDEBUG(PDB_BITS, 1979 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 1980 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 1981 1982 PMAP_HEAD_TO_MAP_LOCK(); 1983 simple_lock(&pg->mdpage.pvh_slock); 1984 1985 #ifdef PMAP_CACHE_VIPT 1986 /* 1987 * If we might want to sync the I-cache and we've modified it, 1988 * then we know we definitely need to sync or discard it. 1989 */ 1990 if (want_syncicache) 1991 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 1992 #endif 1993 /* 1994 * Clear saved attributes (modify, reference) 1995 */ 1996 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1997 1998 if (pg->mdpage.pvh_list == NULL) { 1999 #ifdef PMAP_CACHE_VIPT 2000 if (need_syncicache) { 2001 /* 2002 * No one has it mapped, so just discard it. The next 2003 * exec remapping will cause it to be synced. 2004 */ 2005 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2006 PMAPCOUNT(exec_discarded_clearbit); 2007 } 2008 #endif 2009 simple_unlock(&pg->mdpage.pvh_slock); 2010 PMAP_HEAD_TO_MAP_UNLOCK(); 2011 return; 2012 } 2013 2014 /* 2015 * Loop over all current mappings setting/clearing as appropos 2016 */ 2017 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 2018 va = pv->pv_va; 2019 pm = pv->pv_pmap; 2020 oflags = pv->pv_flags; 2021 pv->pv_flags &= ~maskbits; 2022 2023 pmap_acquire_pmap_lock(pm); 2024 2025 l2b = pmap_get_l2_bucket(pm, va); 2026 KDASSERT(l2b != NULL); 2027 2028 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2029 npte = opte = *ptep; 2030 2031 NPDEBUG(PDB_BITS, 2032 printf( 2033 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2034 pv, pv->pv_pmap, pv->pv_va, oflags)); 2035 2036 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2037 #ifdef PMAP_CACHE_VIVT 2038 if ((pv->pv_flags & PVF_NC)) { 2039 /* 2040 * Entry is not cacheable: 2041 * 2042 * Don't turn caching on again if this is a 2043 * modified emulation. This would be 2044 * inconsitent with the settings created by 2045 * pmap_vac_me_harder(). Otherwise, it's safe 2046 * to re-enable cacheing. 2047 * 2048 * There's no need to call pmap_vac_me_harder() 2049 * here: all pages are losing their write 2050 * permission. 2051 */ 2052 if (maskbits & PVF_WRITE) { 2053 npte |= pte_l2_s_cache_mode; 2054 pv->pv_flags &= ~PVF_NC; 2055 } 2056 } else 2057 if (opte & L2_S_PROT_W) { 2058 /* 2059 * Entry is writable/cacheable: check if pmap 2060 * is current if it is flush it, otherwise it 2061 * won't be in the cache 2062 */ 2063 if (PV_BEEN_EXECD(oflags)) 2064 pmap_idcache_wbinv_range(pm, pv->pv_va, 2065 PAGE_SIZE); 2066 else 2067 if (PV_BEEN_REFD(oflags)) 2068 pmap_dcache_wb_range(pm, pv->pv_va, 2069 PAGE_SIZE, 2070 (maskbits & PVF_REF) != 0, false); 2071 } 2072 #endif 2073 2074 /* make the pte read only */ 2075 npte &= ~L2_S_PROT_W; 2076 2077 if (maskbits & oflags & PVF_WRITE) { 2078 /* 2079 * Keep alias accounting up to date 2080 */ 2081 if (pv->pv_pmap == pmap_kernel()) { 2082 pg->mdpage.krw_mappings--; 2083 pg->mdpage.kro_mappings++; 2084 } else { 2085 pg->mdpage.urw_mappings--; 2086 pg->mdpage.uro_mappings++; 2087 } 2088 #ifdef PMAP_CACHE_VIPT 2089 if (want_syncicache) 2090 need_syncicache = true; 2091 #endif 2092 } 2093 } 2094 2095 if (maskbits & PVF_REF) { 2096 #ifdef PMAP_CACHE_VIVT 2097 if ((pv->pv_flags & PVF_NC) == 0 && 2098 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2099 l2pte_valid(npte)) { 2100 /* 2101 * Check npte here; we may have already 2102 * done the wbinv above, and the validity 2103 * of the PTE is the same for opte and 2104 * npte. 2105 */ 2106 /* XXXJRT need idcache_inv_range */ 2107 if (PV_BEEN_EXECD(oflags)) 2108 pmap_idcache_wbinv_range(pm, 2109 pv->pv_va, PAGE_SIZE); 2110 else 2111 if (PV_BEEN_REFD(oflags)) 2112 pmap_dcache_wb_range(pm, 2113 pv->pv_va, PAGE_SIZE, 2114 true, true); 2115 } 2116 #endif 2117 2118 /* 2119 * Make the PTE invalid so that we will take a 2120 * page fault the next time the mapping is 2121 * referenced. 2122 */ 2123 npte &= ~L2_TYPE_MASK; 2124 npte |= L2_TYPE_INV; 2125 } 2126 2127 if (npte != opte) { 2128 *ptep = npte; 2129 PTE_SYNC(ptep); 2130 /* Flush the TLB entry if a current pmap. */ 2131 if (PV_BEEN_EXECD(oflags)) 2132 pmap_tlb_flushID_SE(pm, pv->pv_va); 2133 else 2134 if (PV_BEEN_REFD(oflags)) 2135 pmap_tlb_flushD_SE(pm, pv->pv_va); 2136 } 2137 2138 pmap_release_pmap_lock(pm); 2139 2140 NPDEBUG(PDB_BITS, 2141 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2142 pm, va, opte, npte)); 2143 } 2144 2145 #ifdef PMAP_CACHE_VIPT 2146 /* 2147 * If we need to sync the I-cache and we haven't done it yet, do it. 2148 */ 2149 if (need_syncicache && !did_syncicache) { 2150 pmap_syncicache_page(pg); 2151 PMAPCOUNT(exec_synced_clearbit); 2152 } 2153 #endif 2154 2155 simple_unlock(&pg->mdpage.pvh_slock); 2156 PMAP_HEAD_TO_MAP_UNLOCK(); 2157 } 2158 2159 /* 2160 * pmap_clean_page() 2161 * 2162 * This is a local function used to work out the best strategy to clean 2163 * a single page referenced by its entry in the PV table. It's used by 2164 * pmap_copy_page, pmap_zero page and maybe some others later on. 2165 * 2166 * Its policy is effectively: 2167 * o If there are no mappings, we don't bother doing anything with the cache. 2168 * o If there is one mapping, we clean just that page. 2169 * o If there are multiple mappings, we clean the entire cache. 2170 * 2171 * So that some functions can be further optimised, it returns 0 if it didn't 2172 * clean the entire cache, or 1 if it did. 2173 * 2174 * XXX One bug in this routine is that if the pv_entry has a single page 2175 * mapped at 0x00000000 a whole cache clean will be performed rather than 2176 * just the 1 page. Since this should not occur in everyday use and if it does 2177 * it will just result in not the most efficient clean for the page. 2178 */ 2179 #ifdef PMAP_CACHE_VIVT 2180 static int 2181 pmap_clean_page(struct pv_entry *pv, bool is_src) 2182 { 2183 pmap_t pm, pm_to_clean = NULL; 2184 struct pv_entry *npv; 2185 u_int cache_needs_cleaning = 0; 2186 u_int flags = 0; 2187 vaddr_t page_to_clean = 0; 2188 2189 if (pv == NULL) { 2190 /* nothing mapped in so nothing to flush */ 2191 return (0); 2192 } 2193 2194 /* 2195 * Since we flush the cache each time we change to a different 2196 * user vmspace, we only need to flush the page if it is in the 2197 * current pmap. 2198 */ 2199 if (curproc) 2200 pm = curproc->p_vmspace->vm_map.pmap; 2201 else 2202 pm = pmap_kernel(); 2203 2204 for (npv = pv; npv; npv = npv->pv_next) { 2205 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2206 flags |= npv->pv_flags; 2207 /* 2208 * The page is mapped non-cacheable in 2209 * this map. No need to flush the cache. 2210 */ 2211 if (npv->pv_flags & PVF_NC) { 2212 #ifdef DIAGNOSTIC 2213 if (cache_needs_cleaning) 2214 panic("pmap_clean_page: " 2215 "cache inconsistency"); 2216 #endif 2217 break; 2218 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2219 continue; 2220 if (cache_needs_cleaning) { 2221 page_to_clean = 0; 2222 break; 2223 } else { 2224 page_to_clean = npv->pv_va; 2225 pm_to_clean = npv->pv_pmap; 2226 } 2227 cache_needs_cleaning = 1; 2228 } 2229 } 2230 2231 if (page_to_clean) { 2232 if (PV_BEEN_EXECD(flags)) 2233 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2234 PAGE_SIZE); 2235 else 2236 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2237 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2238 } else if (cache_needs_cleaning) { 2239 if (PV_BEEN_EXECD(flags)) 2240 pmap_idcache_wbinv_all(pm); 2241 else 2242 pmap_dcache_wbinv_all(pm); 2243 return (1); 2244 } 2245 return (0); 2246 } 2247 #endif 2248 2249 #ifdef PMAP_CACHE_VIPT 2250 /* 2251 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2252 * right cache alias to make sure we flush the right stuff. 2253 */ 2254 void 2255 pmap_syncicache_page(struct vm_page *pg) 2256 { 2257 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2258 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2259 2260 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2261 pg, pg->mdpage.pvh_attrs)); 2262 /* 2263 * No need to clean the page if it's non-cached. 2264 */ 2265 if (pg->mdpage.pvh_attrs & PVF_NC) 2266 return; 2267 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2268 2269 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2270 /* 2271 * Set up a PTE with the right coloring to flush existing cache lines. 2272 */ 2273 *ptep = L2_S_PROTO | 2274 VM_PAGE_TO_PHYS(pg) 2275 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2276 | pte_l2_s_cache_mode; 2277 PTE_SYNC(ptep); 2278 2279 /* 2280 * Flush it. 2281 */ 2282 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2283 /* 2284 * Unmap the page. 2285 */ 2286 *ptep = 0; 2287 PTE_SYNC(ptep); 2288 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2289 2290 pg->mdpage.pvh_attrs |= PVF_EXEC; 2291 PMAPCOUNT(exec_synced); 2292 } 2293 2294 void 2295 pmap_flush_page(struct vm_page *pg) 2296 { 2297 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2298 const size_t pte_offset = va_offset >> PGSHIFT; 2299 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2300 #if 0 2301 vaddr_t mask; 2302 #endif 2303 2304 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2305 #if 0 2306 mask = pmap_check_sets(pg->phys_addr); 2307 KASSERT(popc4(mask) < 2); 2308 #endif 2309 2310 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2311 pg, pg->mdpage.pvh_attrs)); 2312 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2313 /* 2314 * Set up a PTE with the right coloring to flush existing cache entries. 2315 */ 2316 *ptep = L2_S_PROTO 2317 | VM_PAGE_TO_PHYS(pg) 2318 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2319 | pte_l2_s_cache_mode; 2320 PTE_SYNC(ptep); 2321 2322 /* 2323 * Flush it. 2324 */ 2325 cpu_idcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 2326 2327 /* 2328 * Unmap the page. 2329 */ 2330 *ptep = 0; 2331 PTE_SYNC(ptep); 2332 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2333 #if 0 2334 mask = pmap_check_sets(pg->phys_addr); 2335 KASSERT(mask == 0); 2336 #endif 2337 } 2338 #endif /* PMAP_CACHE_VIPT */ 2339 2340 /* 2341 * Routine: pmap_page_remove 2342 * Function: 2343 * Removes this physical page from 2344 * all physical maps in which it resides. 2345 * Reflects back modify bits to the pager. 2346 */ 2347 static void 2348 pmap_page_remove(struct vm_page *pg) 2349 { 2350 struct l2_bucket *l2b; 2351 struct pv_entry *pv, *npv; 2352 pmap_t pm, curpm; 2353 pt_entry_t *ptep, pte; 2354 bool flush; 2355 u_int flags; 2356 2357 NPDEBUG(PDB_FOLLOW, 2358 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2359 VM_PAGE_TO_PHYS(pg))); 2360 2361 PMAP_HEAD_TO_MAP_LOCK(); 2362 simple_lock(&pg->mdpage.pvh_slock); 2363 2364 pv = pg->mdpage.pvh_list; 2365 if (pv == NULL) { 2366 #ifdef PMAP_CACHE_VIPT 2367 /* 2368 * We *know* the page contents are about to be replaced. 2369 * Discard the exec contents 2370 */ 2371 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2372 PMAPCOUNT(exec_discarded_page_protect); 2373 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2374 #endif 2375 simple_unlock(&pg->mdpage.pvh_slock); 2376 PMAP_HEAD_TO_MAP_UNLOCK(); 2377 return; 2378 } 2379 #ifdef PMAP_CACHE_VIPT 2380 KASSERT(pmap_is_page_colored_p(pg)); 2381 #endif 2382 2383 /* 2384 * Clear alias counts 2385 */ 2386 pg->mdpage.k_mappings = 0; 2387 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2388 2389 flush = false; 2390 flags = 0; 2391 if (curproc) 2392 curpm = curproc->p_vmspace->vm_map.pmap; 2393 else 2394 curpm = pmap_kernel(); 2395 2396 #ifdef PMAP_CACHE_VIVT 2397 pmap_clean_page(pv, false); 2398 #endif 2399 2400 while (pv) { 2401 pm = pv->pv_pmap; 2402 if (flush == false && (pm == curpm || pm == pmap_kernel())) 2403 flush = true; 2404 2405 if (pm == pmap_kernel()) 2406 PMAPCOUNT(kernel_unmappings); 2407 PMAPCOUNT(unmappings); 2408 2409 pmap_acquire_pmap_lock(pm); 2410 2411 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2412 KDASSERT(l2b != NULL); 2413 2414 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2415 pte = *ptep; 2416 2417 /* 2418 * Update statistics 2419 */ 2420 --pm->pm_stats.resident_count; 2421 2422 /* Wired bit */ 2423 if (pv->pv_flags & PVF_WIRED) 2424 --pm->pm_stats.wired_count; 2425 2426 flags |= pv->pv_flags; 2427 2428 /* 2429 * Invalidate the PTEs. 2430 */ 2431 *ptep = 0; 2432 PTE_SYNC_CURRENT(pm, ptep); 2433 pmap_free_l2_bucket(pm, l2b, 1); 2434 2435 npv = pv->pv_next; 2436 pool_put(&pmap_pv_pool, pv); 2437 pv = npv; 2438 if (pv == NULL) { 2439 pg->mdpage.pvh_list = NULL; 2440 if (pg->mdpage.pvh_attrs & PVF_KENTRY) 2441 pmap_vac_me_harder(pg, pm, 0); 2442 } 2443 pmap_release_pmap_lock(pm); 2444 } 2445 #ifdef PMAP_CACHE_VIPT 2446 /* 2447 * Since there are now no mappings, there isn't reason to mark it 2448 * as uncached. Its EXEC cache is also gone. 2449 */ 2450 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2451 PMAPCOUNT(exec_discarded_page_protect); 2452 pg->mdpage.pvh_attrs &= ~(PVF_NC|PVF_EXEC); 2453 #endif 2454 #ifdef PMAP_CACHE_VIVT 2455 pg->mdpage.pvh_list = NULL; 2456 #endif 2457 simple_unlock(&pg->mdpage.pvh_slock); 2458 PMAP_HEAD_TO_MAP_UNLOCK(); 2459 2460 if (flush) { 2461 /* 2462 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2463 * would need a subsequent call to pmap_update() to ensure 2464 * curpm->pm_cstate.cs_all is reset. Our callers are not 2465 * required to do that (see pmap(9)), so we can't modify 2466 * the current pmap's state. 2467 */ 2468 if (PV_BEEN_EXECD(flags)) 2469 cpu_tlb_flushID(); 2470 else 2471 cpu_tlb_flushD(); 2472 } 2473 cpu_cpwait(); 2474 } 2475 2476 /* 2477 * pmap_t pmap_create(void) 2478 * 2479 * Create a new pmap structure from scratch. 2480 */ 2481 pmap_t 2482 pmap_create(void) 2483 { 2484 pmap_t pm; 2485 2486 pm = pool_cache_get(&pmap_pmap_cache, PR_WAITOK); 2487 2488 simple_lock_init(&pm->pm_lock); 2489 pm->pm_obj.pgops = NULL; /* currently not a mappable object */ 2490 TAILQ_INIT(&pm->pm_obj.memq); 2491 pm->pm_obj.uo_npages = 0; 2492 pm->pm_obj.uo_refs = 1; 2493 pm->pm_stats.wired_count = 0; 2494 pm->pm_stats.resident_count = 1; 2495 pm->pm_cstate.cs_all = 0; 2496 pmap_alloc_l1(pm); 2497 2498 /* 2499 * Note: The pool cache ensures that the pm_l2[] array is already 2500 * initialised to zero. 2501 */ 2502 2503 pmap_pinit(pm); 2504 2505 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2506 2507 return (pm); 2508 } 2509 2510 /* 2511 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2512 * int flags) 2513 * 2514 * Insert the given physical page (p) at 2515 * the specified virtual address (v) in the 2516 * target physical map with the protection requested. 2517 * 2518 * NB: This is the only routine which MAY NOT lazy-evaluate 2519 * or lose information. That is, this routine must actually 2520 * insert this page into the given map NOW. 2521 */ 2522 int 2523 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 2524 { 2525 struct l2_bucket *l2b; 2526 struct vm_page *pg, *opg; 2527 struct pv_entry *pve; 2528 pt_entry_t *ptep, npte, opte; 2529 u_int nflags; 2530 u_int oflags; 2531 2532 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2533 2534 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2535 KDASSERT(((va | pa) & PGOFSET) == 0); 2536 2537 /* 2538 * Get a pointer to the page. Later on in this function, we 2539 * test for a managed page by checking pg != NULL. 2540 */ 2541 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2542 2543 nflags = 0; 2544 if (prot & VM_PROT_WRITE) 2545 nflags |= PVF_WRITE; 2546 if (prot & VM_PROT_EXECUTE) 2547 nflags |= PVF_EXEC; 2548 if (flags & PMAP_WIRED) 2549 nflags |= PVF_WIRED; 2550 2551 PMAP_MAP_TO_HEAD_LOCK(); 2552 pmap_acquire_pmap_lock(pm); 2553 2554 /* 2555 * Fetch the L2 bucket which maps this page, allocating one if 2556 * necessary for user pmaps. 2557 */ 2558 if (pm == pmap_kernel()) 2559 l2b = pmap_get_l2_bucket(pm, va); 2560 else 2561 l2b = pmap_alloc_l2_bucket(pm, va); 2562 if (l2b == NULL) { 2563 if (flags & PMAP_CANFAIL) { 2564 pmap_release_pmap_lock(pm); 2565 PMAP_MAP_TO_HEAD_UNLOCK(); 2566 return (ENOMEM); 2567 } 2568 panic("pmap_enter: failed to allocate L2 bucket"); 2569 } 2570 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2571 opte = *ptep; 2572 npte = pa; 2573 oflags = 0; 2574 2575 if (opte) { 2576 /* 2577 * There is already a mapping at this address. 2578 * If the physical address is different, lookup the 2579 * vm_page. 2580 */ 2581 if (l2pte_pa(opte) != pa) 2582 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2583 else 2584 opg = pg; 2585 } else 2586 opg = NULL; 2587 2588 if (pg) { 2589 /* 2590 * This is to be a managed mapping. 2591 */ 2592 if ((flags & VM_PROT_ALL) || 2593 (pg->mdpage.pvh_attrs & PVF_REF)) { 2594 /* 2595 * - The access type indicates that we don't need 2596 * to do referenced emulation. 2597 * OR 2598 * - The physical page has already been referenced 2599 * so no need to re-do referenced emulation here. 2600 */ 2601 npte |= L2_S_PROTO; 2602 2603 nflags |= PVF_REF; 2604 2605 if ((prot & VM_PROT_WRITE) != 0 && 2606 ((flags & VM_PROT_WRITE) != 0 || 2607 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2608 /* 2609 * This is a writable mapping, and the 2610 * page's mod state indicates it has 2611 * already been modified. Make it 2612 * writable from the outset. 2613 */ 2614 npte |= L2_S_PROT_W; 2615 nflags |= PVF_MOD; 2616 } 2617 } else { 2618 /* 2619 * Need to do page referenced emulation. 2620 */ 2621 npte |= L2_TYPE_INV; 2622 } 2623 2624 npte |= pte_l2_s_cache_mode; 2625 2626 if (pg == opg) { 2627 /* 2628 * We're changing the attrs of an existing mapping. 2629 */ 2630 simple_lock(&pg->mdpage.pvh_slock); 2631 oflags = pmap_modify_pv(pg, pm, va, 2632 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2633 PVF_MOD | PVF_REF, nflags); 2634 simple_unlock(&pg->mdpage.pvh_slock); 2635 2636 #ifdef PMAP_CACHE_VIVT 2637 /* 2638 * We may need to flush the cache if we're 2639 * doing rw-ro... 2640 */ 2641 if (pm->pm_cstate.cs_cache_d && 2642 (oflags & PVF_NC) == 0 && 2643 (opte & L2_S_PROT_W) != 0 && 2644 (prot & VM_PROT_WRITE) == 0) 2645 cpu_dcache_wb_range(va, PAGE_SIZE); 2646 #endif 2647 } else { 2648 /* 2649 * New mapping, or changing the backing page 2650 * of an existing mapping. 2651 */ 2652 if (opg) { 2653 /* 2654 * Replacing an existing mapping with a new one. 2655 * It is part of our managed memory so we 2656 * must remove it from the PV list 2657 */ 2658 simple_lock(&opg->mdpage.pvh_slock); 2659 pve = pmap_remove_pv(opg, pm, va, 0); 2660 pmap_vac_me_harder(opg, pm, 0); 2661 simple_unlock(&opg->mdpage.pvh_slock); 2662 oflags = pve->pv_flags; 2663 2664 #ifdef PMAP_CACHE_VIVT 2665 /* 2666 * If the old mapping was valid (ref/mod 2667 * emulation creates 'invalid' mappings 2668 * initially) then make sure to frob 2669 * the cache. 2670 */ 2671 if ((oflags & PVF_NC) == 0 && 2672 l2pte_valid(opte)) { 2673 if (PV_BEEN_EXECD(oflags)) { 2674 pmap_idcache_wbinv_range(pm, va, 2675 PAGE_SIZE); 2676 } else 2677 if (PV_BEEN_REFD(oflags)) { 2678 pmap_dcache_wb_range(pm, va, 2679 PAGE_SIZE, true, 2680 (oflags & PVF_WRITE) == 0); 2681 } 2682 } 2683 #endif 2684 } else 2685 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2686 if ((flags & PMAP_CANFAIL) == 0) 2687 panic("pmap_enter: no pv entries"); 2688 2689 if (pm != pmap_kernel()) 2690 pmap_free_l2_bucket(pm, l2b, 0); 2691 pmap_release_pmap_lock(pm); 2692 PMAP_MAP_TO_HEAD_UNLOCK(); 2693 NPDEBUG(PDB_ENTER, 2694 printf("pmap_enter: ENOMEM\n")); 2695 return (ENOMEM); 2696 } 2697 2698 pmap_enter_pv(pg, pve, pm, va, nflags); 2699 } 2700 } else { 2701 /* 2702 * We're mapping an unmanaged page. 2703 * These are always readable, and possibly writable, from 2704 * the get go as we don't need to track ref/mod status. 2705 */ 2706 npte |= L2_S_PROTO; 2707 if (prot & VM_PROT_WRITE) 2708 npte |= L2_S_PROT_W; 2709 2710 /* 2711 * Make sure the vector table is mapped cacheable 2712 */ 2713 if (pm != pmap_kernel() && va == vector_page) 2714 npte |= pte_l2_s_cache_mode; 2715 2716 if (opg) { 2717 /* 2718 * Looks like there's an existing 'managed' mapping 2719 * at this address. 2720 */ 2721 simple_lock(&opg->mdpage.pvh_slock); 2722 pve = pmap_remove_pv(opg, pm, va, 0); 2723 pmap_vac_me_harder(opg, pm, 0); 2724 simple_unlock(&opg->mdpage.pvh_slock); 2725 oflags = pve->pv_flags; 2726 2727 #ifdef PMAP_CACHE_VIVT 2728 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2729 if (PV_BEEN_EXECD(oflags)) 2730 pmap_idcache_wbinv_range(pm, va, 2731 PAGE_SIZE); 2732 else 2733 if (PV_BEEN_REFD(oflags)) 2734 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2735 true, (oflags & PVF_WRITE) == 0); 2736 } 2737 #endif 2738 pool_put(&pmap_pv_pool, pve); 2739 } 2740 } 2741 2742 /* 2743 * Make sure userland mappings get the right permissions 2744 */ 2745 if (pm != pmap_kernel() && va != vector_page) 2746 npte |= L2_S_PROT_U; 2747 2748 /* 2749 * Keep the stats up to date 2750 */ 2751 if (opte == 0) { 2752 l2b->l2b_occupancy++; 2753 pm->pm_stats.resident_count++; 2754 } 2755 2756 NPDEBUG(PDB_ENTER, 2757 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2758 2759 /* 2760 * If this is just a wiring change, the two PTEs will be 2761 * identical, so there's no need to update the page table. 2762 */ 2763 if (npte != opte) { 2764 bool is_cached = pmap_is_cached(pm); 2765 2766 *ptep = npte; 2767 if (is_cached) { 2768 /* 2769 * We only need to frob the cache/tlb if this pmap 2770 * is current 2771 */ 2772 PTE_SYNC(ptep); 2773 if (va != vector_page && l2pte_valid(npte)) { 2774 /* 2775 * This mapping is likely to be accessed as 2776 * soon as we return to userland. Fix up the 2777 * L1 entry to avoid taking another 2778 * page/domain fault. 2779 */ 2780 pd_entry_t *pl1pd, l1pd; 2781 2782 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2783 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2784 L1_C_PROTO; 2785 if (*pl1pd != l1pd) { 2786 *pl1pd = l1pd; 2787 PTE_SYNC(pl1pd); 2788 } 2789 } 2790 } 2791 2792 if (PV_BEEN_EXECD(oflags)) 2793 pmap_tlb_flushID_SE(pm, va); 2794 else 2795 if (PV_BEEN_REFD(oflags)) 2796 pmap_tlb_flushD_SE(pm, va); 2797 2798 NPDEBUG(PDB_ENTER, 2799 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2800 is_cached, pm->pm_cstate.cs_all)); 2801 2802 if (pg != NULL) { 2803 simple_lock(&pg->mdpage.pvh_slock); 2804 pmap_vac_me_harder(pg, pm, va); 2805 simple_unlock(&pg->mdpage.pvh_slock); 2806 } 2807 } 2808 2809 pmap_release_pmap_lock(pm); 2810 PMAP_MAP_TO_HEAD_UNLOCK(); 2811 2812 return (0); 2813 } 2814 2815 /* 2816 * pmap_remove() 2817 * 2818 * pmap_remove is responsible for nuking a number of mappings for a range 2819 * of virtual address space in the current pmap. To do this efficiently 2820 * is interesting, because in a number of cases a wide virtual address 2821 * range may be supplied that contains few actual mappings. So, the 2822 * optimisations are: 2823 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 2824 * 2. Build up a list of pages we've hit, up to a maximum, so we can 2825 * maybe do just a partial cache clean. This path of execution is 2826 * complicated by the fact that the cache must be flushed _before_ 2827 * the PTE is nuked, being a VAC :-) 2828 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 2829 * all invalidations until pmap_update(), since pmap_remove_all() has 2830 * already flushed the cache. 2831 * 4. Maybe later fast-case a single page, but I don't think this is 2832 * going to make _that_ much difference overall. 2833 */ 2834 2835 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 2836 2837 void 2838 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 2839 { 2840 struct l2_bucket *l2b; 2841 vaddr_t next_bucket; 2842 pt_entry_t *ptep; 2843 u_int cleanlist_idx, total, cnt; 2844 struct { 2845 vaddr_t va; 2846 pt_entry_t *ptep; 2847 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 2848 u_int mappings, is_exec, is_refd; 2849 2850 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 2851 "eva=%08lx\n", pm, sva, eva)); 2852 2853 /* 2854 * we lock in the pmap => pv_head direction 2855 */ 2856 PMAP_MAP_TO_HEAD_LOCK(); 2857 pmap_acquire_pmap_lock(pm); 2858 2859 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 2860 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2861 if (pm->pm_cstate.cs_tlb == 0) 2862 pm->pm_remove_all = true; 2863 } else 2864 cleanlist_idx = 0; 2865 2866 total = 0; 2867 2868 while (sva < eva) { 2869 /* 2870 * Do one L2 bucket's worth at a time. 2871 */ 2872 next_bucket = L2_NEXT_BUCKET(sva); 2873 if (next_bucket > eva) 2874 next_bucket = eva; 2875 2876 l2b = pmap_get_l2_bucket(pm, sva); 2877 if (l2b == NULL) { 2878 sva = next_bucket; 2879 continue; 2880 } 2881 2882 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2883 2884 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 2885 struct vm_page *pg; 2886 pt_entry_t pte; 2887 paddr_t pa; 2888 2889 pte = *ptep; 2890 2891 if (pte == 0) { 2892 /* Nothing here, move along */ 2893 continue; 2894 } 2895 2896 pa = l2pte_pa(pte); 2897 is_exec = 0; 2898 is_refd = 1; 2899 2900 /* 2901 * Update flags. In a number of circumstances, 2902 * we could cluster a lot of these and do a 2903 * number of sequential pages in one go. 2904 */ 2905 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 2906 struct pv_entry *pve; 2907 simple_lock(&pg->mdpage.pvh_slock); 2908 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 2909 pmap_vac_me_harder(pg, pm, 0); 2910 simple_unlock(&pg->mdpage.pvh_slock); 2911 if (pve != NULL) { 2912 if (pm->pm_remove_all == false) { 2913 is_exec = 2914 PV_BEEN_EXECD(pve->pv_flags); 2915 is_refd = 2916 PV_BEEN_REFD(pve->pv_flags); 2917 } 2918 pool_put(&pmap_pv_pool, pve); 2919 } else 2920 if (skip_wired) { 2921 /* The mapping is wired. Skip it */ 2922 continue; 2923 } 2924 } else 2925 if (skip_wired) { 2926 /* Unmanaged pages are always wired. */ 2927 continue; 2928 } 2929 2930 mappings++; 2931 2932 if (!l2pte_valid(pte)) { 2933 /* 2934 * Ref/Mod emulation is still active for this 2935 * mapping, therefore it is has not yet been 2936 * accessed. No need to frob the cache/tlb. 2937 */ 2938 *ptep = 0; 2939 PTE_SYNC_CURRENT(pm, ptep); 2940 continue; 2941 } 2942 2943 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 2944 /* Add to the clean list. */ 2945 cleanlist[cleanlist_idx].ptep = ptep; 2946 cleanlist[cleanlist_idx].va = 2947 sva | (is_exec & 1); 2948 cleanlist_idx++; 2949 } else 2950 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 2951 /* Nuke everything if needed. */ 2952 #ifdef PMAP_CACHE_VIVT 2953 pmap_idcache_wbinv_all(pm); 2954 #endif 2955 pmap_tlb_flushID(pm); 2956 2957 /* 2958 * Roll back the previous PTE list, 2959 * and zero out the current PTE. 2960 */ 2961 for (cnt = 0; 2962 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 2963 *cleanlist[cnt].ptep = 0; 2964 } 2965 *ptep = 0; 2966 PTE_SYNC(ptep); 2967 cleanlist_idx++; 2968 pm->pm_remove_all = true; 2969 } else { 2970 *ptep = 0; 2971 PTE_SYNC(ptep); 2972 if (pm->pm_remove_all == false) { 2973 if (is_exec) 2974 pmap_tlb_flushID_SE(pm, sva); 2975 else 2976 if (is_refd) 2977 pmap_tlb_flushD_SE(pm, sva); 2978 } 2979 } 2980 } 2981 2982 /* 2983 * Deal with any left overs 2984 */ 2985 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 2986 total += cleanlist_idx; 2987 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 2988 if (pm->pm_cstate.cs_all != 0) { 2989 vaddr_t clva = cleanlist[cnt].va & ~1; 2990 if (cleanlist[cnt].va & 1) { 2991 #ifdef PMAP_CACHE_VIVT 2992 pmap_idcache_wbinv_range(pm, 2993 clva, PAGE_SIZE); 2994 #endif 2995 pmap_tlb_flushID_SE(pm, clva); 2996 } else { 2997 #ifdef PMAP_CACHE_VIVT 2998 pmap_dcache_wb_range(pm, 2999 clva, PAGE_SIZE, true, 3000 false); 3001 #endif 3002 pmap_tlb_flushD_SE(pm, clva); 3003 } 3004 } 3005 *cleanlist[cnt].ptep = 0; 3006 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3007 } 3008 3009 /* 3010 * If it looks like we're removing a whole bunch 3011 * of mappings, it's faster to just write-back 3012 * the whole cache now and defer TLB flushes until 3013 * pmap_update() is called. 3014 */ 3015 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3016 cleanlist_idx = 0; 3017 else { 3018 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3019 #ifdef PMAP_CACHE_VIVT 3020 pmap_idcache_wbinv_all(pm); 3021 #endif 3022 pm->pm_remove_all = true; 3023 } 3024 } 3025 3026 pmap_free_l2_bucket(pm, l2b, mappings); 3027 pm->pm_stats.resident_count -= mappings; 3028 } 3029 3030 pmap_release_pmap_lock(pm); 3031 PMAP_MAP_TO_HEAD_UNLOCK(); 3032 } 3033 3034 /* 3035 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3036 * 3037 * We assume there is already sufficient KVM space available 3038 * to do this, as we can't allocate L2 descriptor tables/metadata 3039 * from here. 3040 */ 3041 void 3042 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 3043 { 3044 struct l2_bucket *l2b; 3045 pt_entry_t *ptep, opte; 3046 #ifdef PMAP_CACHE_VIPT 3047 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3048 struct vm_page *opg; 3049 #endif 3050 3051 3052 NPDEBUG(PDB_KENTER, 3053 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3054 va, pa, prot)); 3055 3056 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3057 KDASSERT(l2b != NULL); 3058 3059 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3060 opte = *ptep; 3061 3062 if (opte == 0) { 3063 PMAPCOUNT(kenter_mappings); 3064 l2b->l2b_occupancy++; 3065 } else { 3066 PMAPCOUNT(kenter_remappings); 3067 #ifdef PMAP_CACHE_VIPT 3068 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3069 if (opg) { 3070 KASSERT(opg != pg); 3071 simple_lock(&opg->mdpage.pvh_slock); 3072 KASSERT(opg->mdpage.pvh_attrs & PVF_KENTRY); 3073 if (PV_IS_EXEC_P(opg->mdpage.pvh_attrs) 3074 && !(opg->mdpage.pvh_attrs & PVF_NC)) { 3075 if (opg->mdpage.pvh_list == NULL) { 3076 opg->mdpage.pvh_attrs &= ~PVF_EXEC; 3077 PMAPCOUNT(exec_discarded_kremove); 3078 } else { 3079 pmap_syncicache_page(opg); 3080 PMAPCOUNT(exec_synced_kremove); 3081 } 3082 } 3083 KASSERT(opg->mdpage.pvh_attrs | (PVF_COLORED|PVF_NC)); 3084 opg->mdpage.pvh_attrs &= ~PVF_KENTRY; 3085 pmap_vac_me_harder(opg, NULL, 0); 3086 simple_unlock(&opg->mdpage.pvh_slock); 3087 } 3088 #endif 3089 if (l2pte_valid(opte)) { 3090 #ifdef PMAP_CACHE_VIVT 3091 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3092 #endif 3093 cpu_tlb_flushD_SE(va); 3094 cpu_cpwait(); 3095 } 3096 } 3097 3098 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3099 pte_l2_s_cache_mode; 3100 PTE_SYNC(ptep); 3101 3102 #ifdef PMAP_CACHE_VIPT 3103 if (pg) { 3104 simple_lock(&pg->mdpage.pvh_slock); 3105 KASSERT((pg->mdpage.pvh_attrs & PVF_KENTRY) == 0); 3106 pg->mdpage.pvh_attrs |= PVF_KENTRY; 3107 pmap_vac_me_harder(pg, NULL, va); 3108 simple_unlock(&pg->mdpage.pvh_slock); 3109 } 3110 #endif 3111 } 3112 3113 void 3114 pmap_kremove(vaddr_t va, vsize_t len) 3115 { 3116 struct l2_bucket *l2b; 3117 pt_entry_t *ptep, *sptep, opte; 3118 vaddr_t next_bucket, eva; 3119 u_int mappings; 3120 #ifdef PMAP_CACHE_VIPT 3121 struct vm_page *opg; 3122 #endif 3123 3124 PMAPCOUNT(kenter_unmappings); 3125 3126 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3127 va, len)); 3128 3129 eva = va + len; 3130 3131 while (va < eva) { 3132 next_bucket = L2_NEXT_BUCKET(va); 3133 if (next_bucket > eva) 3134 next_bucket = eva; 3135 3136 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3137 KDASSERT(l2b != NULL); 3138 3139 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3140 mappings = 0; 3141 3142 while (va < next_bucket) { 3143 opte = *ptep; 3144 #ifdef PMAP_CACHE_VIPT 3145 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3146 if (opg) { 3147 simple_lock(&opg->mdpage.pvh_slock); 3148 KASSERT(opg->mdpage.pvh_attrs & PVF_KENTRY); 3149 if (PV_IS_EXEC_P(opg->mdpage.pvh_attrs) 3150 && !(opg->mdpage.pvh_attrs & PVF_NC)) { 3151 if (opg->mdpage.pvh_list == NULL) { 3152 opg->mdpage.pvh_attrs &= 3153 ~PVF_EXEC; 3154 PMAPCOUNT(exec_discarded_kremove); 3155 } else { 3156 pmap_syncicache_page(opg); 3157 PMAPCOUNT(exec_synced_kremove); 3158 } 3159 } 3160 KASSERT(opg->mdpage.pvh_attrs | (PVF_COLORED|PVF_NC)); 3161 opg->mdpage.pvh_attrs &= ~PVF_KENTRY; 3162 pmap_vac_me_harder(opg, NULL, 0); 3163 simple_unlock(&opg->mdpage.pvh_slock); 3164 } 3165 #endif 3166 if (l2pte_valid(opte)) { 3167 #ifdef PMAP_CACHE_VIVT 3168 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3169 #endif 3170 cpu_tlb_flushD_SE(va); 3171 } 3172 if (opte) { 3173 *ptep = 0; 3174 mappings++; 3175 } 3176 va += PAGE_SIZE; 3177 ptep++; 3178 } 3179 KDASSERT(mappings <= l2b->l2b_occupancy); 3180 l2b->l2b_occupancy -= mappings; 3181 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3182 } 3183 cpu_cpwait(); 3184 } 3185 3186 bool 3187 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3188 { 3189 struct l2_dtable *l2; 3190 pd_entry_t *pl1pd, l1pd; 3191 pt_entry_t *ptep, pte; 3192 paddr_t pa; 3193 u_int l1idx; 3194 3195 pmap_acquire_pmap_lock(pm); 3196 3197 l1idx = L1_IDX(va); 3198 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3199 l1pd = *pl1pd; 3200 3201 if (l1pte_section_p(l1pd)) { 3202 /* 3203 * These should only happen for pmap_kernel() 3204 */ 3205 KDASSERT(pm == pmap_kernel()); 3206 pmap_release_pmap_lock(pm); 3207 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3208 } else { 3209 /* 3210 * Note that we can't rely on the validity of the L1 3211 * descriptor as an indication that a mapping exists. 3212 * We have to look it up in the L2 dtable. 3213 */ 3214 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3215 3216 if (l2 == NULL || 3217 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3218 pmap_release_pmap_lock(pm); 3219 return false; 3220 } 3221 3222 ptep = &ptep[l2pte_index(va)]; 3223 pte = *ptep; 3224 pmap_release_pmap_lock(pm); 3225 3226 if (pte == 0) 3227 return false; 3228 3229 switch (pte & L2_TYPE_MASK) { 3230 case L2_TYPE_L: 3231 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3232 break; 3233 3234 default: 3235 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3236 break; 3237 } 3238 } 3239 3240 if (pap != NULL) 3241 *pap = pa; 3242 3243 return true; 3244 } 3245 3246 void 3247 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3248 { 3249 struct l2_bucket *l2b; 3250 pt_entry_t *ptep, pte; 3251 vaddr_t next_bucket; 3252 u_int flags; 3253 u_int clr_mask; 3254 int flush; 3255 3256 NPDEBUG(PDB_PROTECT, 3257 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3258 pm, sva, eva, prot)); 3259 3260 if ((prot & VM_PROT_READ) == 0) { 3261 pmap_remove(pm, sva, eva); 3262 return; 3263 } 3264 3265 if (prot & VM_PROT_WRITE) { 3266 /* 3267 * If this is a read->write transition, just ignore it and let 3268 * uvm_fault() take care of it later. 3269 */ 3270 return; 3271 } 3272 3273 PMAP_MAP_TO_HEAD_LOCK(); 3274 pmap_acquire_pmap_lock(pm); 3275 3276 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3277 flags = 0; 3278 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3279 3280 while (sva < eva) { 3281 next_bucket = L2_NEXT_BUCKET(sva); 3282 if (next_bucket > eva) 3283 next_bucket = eva; 3284 3285 l2b = pmap_get_l2_bucket(pm, sva); 3286 if (l2b == NULL) { 3287 sva = next_bucket; 3288 continue; 3289 } 3290 3291 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3292 3293 while (sva < next_bucket) { 3294 pte = *ptep; 3295 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3296 struct vm_page *pg; 3297 u_int f; 3298 3299 #ifdef PMAP_CACHE_VIVT 3300 /* 3301 * OK, at this point, we know we're doing 3302 * write-protect operation. If the pmap is 3303 * active, write-back the page. 3304 */ 3305 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3306 false, false); 3307 #endif 3308 3309 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3310 pte &= ~L2_S_PROT_W; 3311 *ptep = pte; 3312 PTE_SYNC(ptep); 3313 3314 if (pg != NULL) { 3315 simple_lock(&pg->mdpage.pvh_slock); 3316 f = pmap_modify_pv(pg, pm, sva, 3317 clr_mask, 0); 3318 pmap_vac_me_harder(pg, pm, sva); 3319 simple_unlock(&pg->mdpage.pvh_slock); 3320 } else 3321 f = PVF_REF | PVF_EXEC; 3322 3323 if (flush >= 0) { 3324 flush++; 3325 flags |= f; 3326 } else 3327 if (PV_BEEN_EXECD(f)) 3328 pmap_tlb_flushID_SE(pm, sva); 3329 else 3330 if (PV_BEEN_REFD(f)) 3331 pmap_tlb_flushD_SE(pm, sva); 3332 } 3333 3334 sva += PAGE_SIZE; 3335 ptep++; 3336 } 3337 } 3338 3339 pmap_release_pmap_lock(pm); 3340 PMAP_MAP_TO_HEAD_UNLOCK(); 3341 3342 if (flush) { 3343 if (PV_BEEN_EXECD(flags)) 3344 pmap_tlb_flushID(pm); 3345 else 3346 if (PV_BEEN_REFD(flags)) 3347 pmap_tlb_flushD(pm); 3348 } 3349 } 3350 3351 void 3352 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3353 { 3354 3355 NPDEBUG(PDB_PROTECT, 3356 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3357 pg, VM_PAGE_TO_PHYS(pg), prot)); 3358 3359 switch(prot) { 3360 return; 3361 case VM_PROT_READ|VM_PROT_WRITE: 3362 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3363 pmap_clearbit(pg, PVF_EXEC); 3364 break; 3365 #endif 3366 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3367 break; 3368 3369 case VM_PROT_READ: 3370 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3371 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3372 break; 3373 #endif 3374 case VM_PROT_READ|VM_PROT_EXECUTE: 3375 pmap_clearbit(pg, PVF_WRITE); 3376 break; 3377 3378 default: 3379 pmap_page_remove(pg); 3380 break; 3381 } 3382 } 3383 3384 /* 3385 * pmap_clear_modify: 3386 * 3387 * Clear the "modified" attribute for a page. 3388 */ 3389 bool 3390 pmap_clear_modify(struct vm_page *pg) 3391 { 3392 bool rv; 3393 3394 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3395 rv = true; 3396 pmap_clearbit(pg, PVF_MOD); 3397 } else 3398 rv = false; 3399 3400 return (rv); 3401 } 3402 3403 /* 3404 * pmap_clear_reference: 3405 * 3406 * Clear the "referenced" attribute for a page. 3407 */ 3408 bool 3409 pmap_clear_reference(struct vm_page *pg) 3410 { 3411 bool rv; 3412 3413 if (pg->mdpage.pvh_attrs & PVF_REF) { 3414 rv = true; 3415 pmap_clearbit(pg, PVF_REF); 3416 } else 3417 rv = false; 3418 3419 return (rv); 3420 } 3421 3422 /* 3423 * pmap_is_modified: 3424 * 3425 * Test if a page has the "modified" attribute. 3426 */ 3427 /* See <arm/arm32/pmap.h> */ 3428 3429 /* 3430 * pmap_is_referenced: 3431 * 3432 * Test if a page has the "referenced" attribute. 3433 */ 3434 /* See <arm/arm32/pmap.h> */ 3435 3436 int 3437 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3438 { 3439 struct l2_dtable *l2; 3440 struct l2_bucket *l2b; 3441 pd_entry_t *pl1pd, l1pd; 3442 pt_entry_t *ptep, pte; 3443 paddr_t pa; 3444 u_int l1idx; 3445 int rv = 0; 3446 3447 PMAP_MAP_TO_HEAD_LOCK(); 3448 pmap_acquire_pmap_lock(pm); 3449 3450 l1idx = L1_IDX(va); 3451 3452 /* 3453 * If there is no l2_dtable for this address, then the process 3454 * has no business accessing it. 3455 * 3456 * Note: This will catch userland processes trying to access 3457 * kernel addresses. 3458 */ 3459 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3460 if (l2 == NULL) 3461 goto out; 3462 3463 /* 3464 * Likewise if there is no L2 descriptor table 3465 */ 3466 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3467 if (l2b->l2b_kva == NULL) 3468 goto out; 3469 3470 /* 3471 * Check the PTE itself. 3472 */ 3473 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3474 pte = *ptep; 3475 if (pte == 0) 3476 goto out; 3477 3478 /* 3479 * Catch a userland access to the vector page mapped at 0x0 3480 */ 3481 if (user && (pte & L2_S_PROT_U) == 0) 3482 goto out; 3483 3484 pa = l2pte_pa(pte); 3485 3486 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3487 /* 3488 * This looks like a good candidate for "page modified" 3489 * emulation... 3490 */ 3491 struct pv_entry *pv; 3492 struct vm_page *pg; 3493 3494 /* Extract the physical address of the page */ 3495 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3496 goto out; 3497 3498 /* Get the current flags for this page. */ 3499 simple_lock(&pg->mdpage.pvh_slock); 3500 3501 pv = pmap_find_pv(pg, pm, va); 3502 if (pv == NULL) { 3503 simple_unlock(&pg->mdpage.pvh_slock); 3504 goto out; 3505 } 3506 3507 /* 3508 * Do the flags say this page is writable? If not then it 3509 * is a genuine write fault. If yes then the write fault is 3510 * our fault as we did not reflect the write access in the 3511 * PTE. Now we know a write has occurred we can correct this 3512 * and also set the modified bit 3513 */ 3514 if ((pv->pv_flags & PVF_WRITE) == 0) { 3515 simple_unlock(&pg->mdpage.pvh_slock); 3516 goto out; 3517 } 3518 3519 NPDEBUG(PDB_FOLLOW, 3520 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3521 pm, va, VM_PAGE_TO_PHYS(pg))); 3522 3523 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 3524 pv->pv_flags |= PVF_REF | PVF_MOD; 3525 simple_unlock(&pg->mdpage.pvh_slock); 3526 3527 /* 3528 * Re-enable write permissions for the page. No need to call 3529 * pmap_vac_me_harder(), since this is just a 3530 * modified-emulation fault, and the PVF_WRITE bit isn't 3531 * changing. We've already set the cacheable bits based on 3532 * the assumption that we can write to this page. 3533 */ 3534 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3535 PTE_SYNC(ptep); 3536 rv = 1; 3537 } else 3538 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3539 /* 3540 * This looks like a good candidate for "page referenced" 3541 * emulation. 3542 */ 3543 struct pv_entry *pv; 3544 struct vm_page *pg; 3545 3546 /* Extract the physical address of the page */ 3547 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3548 goto out; 3549 3550 /* Get the current flags for this page. */ 3551 simple_lock(&pg->mdpage.pvh_slock); 3552 3553 pv = pmap_find_pv(pg, pm, va); 3554 if (pv == NULL) { 3555 simple_unlock(&pg->mdpage.pvh_slock); 3556 goto out; 3557 } 3558 3559 pg->mdpage.pvh_attrs |= PVF_REF; 3560 pv->pv_flags |= PVF_REF; 3561 simple_unlock(&pg->mdpage.pvh_slock); 3562 3563 NPDEBUG(PDB_FOLLOW, 3564 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3565 pm, va, VM_PAGE_TO_PHYS(pg))); 3566 3567 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3568 PTE_SYNC(ptep); 3569 rv = 1; 3570 } 3571 3572 /* 3573 * We know there is a valid mapping here, so simply 3574 * fix up the L1 if necessary. 3575 */ 3576 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3577 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3578 if (*pl1pd != l1pd) { 3579 *pl1pd = l1pd; 3580 PTE_SYNC(pl1pd); 3581 rv = 1; 3582 } 3583 3584 #ifdef CPU_SA110 3585 /* 3586 * There are bugs in the rev K SA110. This is a check for one 3587 * of them. 3588 */ 3589 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3590 curcpu()->ci_arm_cpurev < 3) { 3591 /* Always current pmap */ 3592 if (l2pte_valid(pte)) { 3593 extern int kernel_debug; 3594 if (kernel_debug & 1) { 3595 struct proc *p = curlwp->l_proc; 3596 printf("prefetch_abort: page is already " 3597 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3598 printf("prefetch_abort: pc=%08lx proc=%p " 3599 "process=%s\n", va, p, p->p_comm); 3600 printf("prefetch_abort: far=%08x fs=%x\n", 3601 cpu_faultaddress(), cpu_faultstatus()); 3602 } 3603 #ifdef DDB 3604 if (kernel_debug & 2) 3605 Debugger(); 3606 #endif 3607 rv = 1; 3608 } 3609 } 3610 #endif /* CPU_SA110 */ 3611 3612 #ifdef DEBUG 3613 /* 3614 * If 'rv == 0' at this point, it generally indicates that there is a 3615 * stale TLB entry for the faulting address. This happens when two or 3616 * more processes are sharing an L1. Since we don't flush the TLB on 3617 * a context switch between such processes, we can take domain faults 3618 * for mappings which exist at the same VA in both processes. EVEN IF 3619 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3620 * example. 3621 * 3622 * This is extremely likely to happen if pmap_enter() updated the L1 3623 * entry for a recently entered mapping. In this case, the TLB is 3624 * flushed for the new mapping, but there may still be TLB entries for 3625 * other mappings belonging to other processes in the 1MB range 3626 * covered by the L1 entry. 3627 * 3628 * Since 'rv == 0', we know that the L1 already contains the correct 3629 * value, so the fault must be due to a stale TLB entry. 3630 * 3631 * Since we always need to flush the TLB anyway in the case where we 3632 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 3633 * stale TLB entries dynamically. 3634 * 3635 * However, the above condition can ONLY happen if the current L1 is 3636 * being shared. If it happens when the L1 is unshared, it indicates 3637 * that other parts of the pmap are not doing their job WRT managing 3638 * the TLB. 3639 */ 3640 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 3641 extern int last_fault_code; 3642 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 3643 pm, va, ftype); 3644 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 3645 l2, l2b, ptep, pl1pd); 3646 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 3647 pte, l1pd, last_fault_code); 3648 #ifdef DDB 3649 Debugger(); 3650 #endif 3651 } 3652 #endif 3653 3654 cpu_tlb_flushID_SE(va); 3655 cpu_cpwait(); 3656 3657 rv = 1; 3658 3659 out: 3660 pmap_release_pmap_lock(pm); 3661 PMAP_MAP_TO_HEAD_UNLOCK(); 3662 3663 return (rv); 3664 } 3665 3666 /* 3667 * pmap_collect: free resources held by a pmap 3668 * 3669 * => optional function. 3670 * => called when a process is swapped out to free memory. 3671 */ 3672 void 3673 pmap_collect(pmap_t pm) 3674 { 3675 3676 #ifdef PMAP_CACHE_VIVT 3677 pmap_idcache_wbinv_all(pm); 3678 #endif 3679 pm->pm_remove_all = true; 3680 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 3681 pmap_update(pm); 3682 PMAPCOUNT(collects); 3683 } 3684 3685 /* 3686 * Routine: pmap_procwr 3687 * 3688 * Function: 3689 * Synchronize caches corresponding to [addr, addr+len) in p. 3690 * 3691 */ 3692 void 3693 pmap_procwr(struct proc *p, vaddr_t va, int len) 3694 { 3695 /* We only need to do anything if it is the current process. */ 3696 if (p == curproc) 3697 cpu_icache_sync_range(va, len); 3698 } 3699 3700 /* 3701 * Routine: pmap_unwire 3702 * Function: Clear the wired attribute for a map/virtual-address pair. 3703 * 3704 * In/out conditions: 3705 * The mapping must already exist in the pmap. 3706 */ 3707 void 3708 pmap_unwire(pmap_t pm, vaddr_t va) 3709 { 3710 struct l2_bucket *l2b; 3711 pt_entry_t *ptep, pte; 3712 struct vm_page *pg; 3713 paddr_t pa; 3714 3715 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 3716 3717 PMAP_MAP_TO_HEAD_LOCK(); 3718 pmap_acquire_pmap_lock(pm); 3719 3720 l2b = pmap_get_l2_bucket(pm, va); 3721 KDASSERT(l2b != NULL); 3722 3723 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3724 pte = *ptep; 3725 3726 /* Extract the physical address of the page */ 3727 pa = l2pte_pa(pte); 3728 3729 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3730 /* Update the wired bit in the pv entry for this page. */ 3731 simple_lock(&pg->mdpage.pvh_slock); 3732 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 3733 simple_unlock(&pg->mdpage.pvh_slock); 3734 } 3735 3736 pmap_release_pmap_lock(pm); 3737 PMAP_MAP_TO_HEAD_UNLOCK(); 3738 } 3739 3740 void 3741 pmap_switch(struct lwp *olwp, struct lwp *nlwp) 3742 { 3743 extern int block_userspace_access; 3744 pmap_t opm, npm, rpm; 3745 uint32_t odacr, ndacr; 3746 int oldirqstate; 3747 3748 npm = nlwp->l_proc->p_vmspace->vm_map.pmap; 3749 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3750 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 3751 3752 /* 3753 * If TTB and DACR are unchanged, short-circuit all the 3754 * TLB/cache management stuff. 3755 */ 3756 if (olwp != NULL) { 3757 opm = olwp->l_proc->p_vmspace->vm_map.pmap; 3758 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3759 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 3760 3761 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 3762 goto all_done; 3763 } else 3764 opm = NULL; 3765 3766 PMAPCOUNT(activations); 3767 block_userspace_access = 1; 3768 3769 /* 3770 * If switching to a user vmspace which is different to the 3771 * most recent one, and the most recent one is potentially 3772 * live in the cache, we must write-back and invalidate the 3773 * entire cache. 3774 */ 3775 rpm = pmap_recent_user; 3776 if (npm != pmap_kernel() && rpm && npm != rpm && 3777 rpm->pm_cstate.cs_cache) { 3778 rpm->pm_cstate.cs_cache = 0; 3779 #ifdef PMAP_CACHE_VIVT 3780 cpu_idcache_wbinv_all(); 3781 #endif 3782 } 3783 3784 /* No interrupts while we frob the TTB/DACR */ 3785 oldirqstate = disable_interrupts(I32_bit | F32_bit); 3786 3787 /* 3788 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 3789 * entry corresponding to 'vector_page' in the incoming L1 table 3790 * before switching to it otherwise subsequent interrupts/exceptions 3791 * (including domain faults!) will jump into hyperspace. 3792 */ 3793 if (npm->pm_pl1vec != NULL) { 3794 cpu_tlb_flushID_SE((u_int)vector_page); 3795 cpu_cpwait(); 3796 *npm->pm_pl1vec = npm->pm_l1vec; 3797 PTE_SYNC(npm->pm_pl1vec); 3798 } 3799 3800 cpu_domains(ndacr); 3801 3802 if (npm == pmap_kernel() || npm == rpm) { 3803 /* 3804 * Switching to a kernel thread, or back to the 3805 * same user vmspace as before... Simply update 3806 * the TTB (no TLB flush required) 3807 */ 3808 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 3809 "r"(npm->pm_l1->l1_physaddr)); 3810 cpu_cpwait(); 3811 } else { 3812 /* 3813 * Otherwise, update TTB and flush TLB 3814 */ 3815 cpu_context_switch(npm->pm_l1->l1_physaddr); 3816 if (rpm != NULL) 3817 rpm->pm_cstate.cs_tlb = 0; 3818 } 3819 3820 restore_interrupts(oldirqstate); 3821 3822 block_userspace_access = 0; 3823 3824 all_done: 3825 /* 3826 * The new pmap is resident. Make sure it's marked 3827 * as resident in the cache/TLB. 3828 */ 3829 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3830 if (npm != pmap_kernel()) 3831 pmap_recent_user = npm; 3832 3833 /* The old pmap is not longer active */ 3834 if (opm != NULL) 3835 opm->pm_activated = false; 3836 3837 /* But the new one is */ 3838 npm->pm_activated = true; 3839 } 3840 3841 void 3842 pmap_activate(struct lwp *l) 3843 { 3844 3845 if (l == curlwp && 3846 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == false) 3847 pmap_switch(NULL, l); 3848 } 3849 3850 void 3851 pmap_deactivate(struct lwp *l) 3852 { 3853 3854 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 3855 } 3856 3857 void 3858 pmap_update(pmap_t pm) 3859 { 3860 3861 if (pm->pm_remove_all) { 3862 /* 3863 * Finish up the pmap_remove_all() optimisation by flushing 3864 * the TLB. 3865 */ 3866 pmap_tlb_flushID(pm); 3867 pm->pm_remove_all = false; 3868 } 3869 3870 if (pmap_is_current(pm)) { 3871 /* 3872 * If we're dealing with a current userland pmap, move its L1 3873 * to the end of the LRU. 3874 */ 3875 if (pm != pmap_kernel()) 3876 pmap_use_l1(pm); 3877 3878 /* 3879 * We can assume we're done with frobbing the cache/tlb for 3880 * now. Make sure any future pmap ops don't skip cache/tlb 3881 * flushes. 3882 */ 3883 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3884 } 3885 3886 PMAPCOUNT(updates); 3887 3888 /* 3889 * make sure TLB/cache operations have completed. 3890 */ 3891 cpu_cpwait(); 3892 } 3893 3894 void 3895 pmap_remove_all(pmap_t pm) 3896 { 3897 3898 /* 3899 * The vmspace described by this pmap is about to be torn down. 3900 * Until pmap_update() is called, UVM will only make calls 3901 * to pmap_remove(). We can make life much simpler by flushing 3902 * the cache now, and deferring TLB invalidation to pmap_update(). 3903 */ 3904 #ifdef PMAP_CACHE_VIVT 3905 pmap_idcache_wbinv_all(pm); 3906 #endif 3907 pm->pm_remove_all = true; 3908 } 3909 3910 /* 3911 * Retire the given physical map from service. 3912 * Should only be called if the map contains no valid mappings. 3913 */ 3914 void 3915 pmap_destroy(pmap_t pm) 3916 { 3917 u_int count; 3918 3919 if (pm == NULL) 3920 return; 3921 3922 if (pm->pm_remove_all) { 3923 pmap_tlb_flushID(pm); 3924 pm->pm_remove_all = false; 3925 } 3926 3927 /* 3928 * Drop reference count 3929 */ 3930 simple_lock(&pm->pm_lock); 3931 count = --pm->pm_obj.uo_refs; 3932 simple_unlock(&pm->pm_lock); 3933 if (count > 0) { 3934 if (pmap_is_current(pm)) { 3935 if (pm != pmap_kernel()) 3936 pmap_use_l1(pm); 3937 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3938 } 3939 return; 3940 } 3941 3942 /* 3943 * reference count is zero, free pmap resources and then free pmap. 3944 */ 3945 3946 if (vector_page < KERNEL_BASE) { 3947 KDASSERT(!pmap_is_current(pm)); 3948 3949 /* Remove the vector page mapping */ 3950 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 3951 pmap_update(pm); 3952 } 3953 3954 LIST_REMOVE(pm, pm_list); 3955 3956 pmap_free_l1(pm); 3957 3958 if (pmap_recent_user == pm) 3959 pmap_recent_user = NULL; 3960 3961 /* return the pmap to the pool */ 3962 pool_cache_put(&pmap_pmap_cache, pm); 3963 } 3964 3965 3966 /* 3967 * void pmap_reference(pmap_t pm) 3968 * 3969 * Add a reference to the specified pmap. 3970 */ 3971 void 3972 pmap_reference(pmap_t pm) 3973 { 3974 3975 if (pm == NULL) 3976 return; 3977 3978 pmap_use_l1(pm); 3979 3980 simple_lock(&pm->pm_lock); 3981 pm->pm_obj.uo_refs++; 3982 simple_unlock(&pm->pm_lock); 3983 } 3984 3985 #if ARM_MMU_V6 > 0 3986 3987 static struct evcnt pmap_prefer_nochange_ev = 3988 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 3989 static struct evcnt pmap_prefer_change_ev = 3990 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 3991 3992 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 3993 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 3994 3995 void 3996 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 3997 { 3998 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 3999 vaddr_t va = *vap; 4000 vaddr_t diff = (hint - va) & mask; 4001 if (diff == 0) { 4002 pmap_prefer_nochange_ev.ev_count++; 4003 } else { 4004 pmap_prefer_change_ev.ev_count++; 4005 if (__predict_false(td)) 4006 va -= mask + 1; 4007 *vap = va + diff; 4008 } 4009 } 4010 #endif /* ARM_MMU_V6 */ 4011 4012 /* 4013 * pmap_zero_page() 4014 * 4015 * Zero a given physical page by mapping it at a page hook point. 4016 * In doing the zero page op, the page we zero is mapped cachable, as with 4017 * StrongARM accesses to non-cached pages are non-burst making writing 4018 * _any_ bulk data very slow. 4019 */ 4020 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4021 void 4022 pmap_zero_page_generic(paddr_t phys) 4023 { 4024 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4025 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4026 #endif 4027 #ifdef PMAP_CACHE_VIPT 4028 /* Choose the last page color it had, if any */ 4029 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4030 #else 4031 const vsize_t va_offset = 0; 4032 #endif 4033 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4034 4035 #ifdef DEBUG 4036 if (pg->mdpage.pvh_list != NULL) 4037 panic("pmap_zero_page: page has mappings"); 4038 #endif 4039 4040 KDASSERT((phys & PGOFSET) == 0); 4041 4042 /* 4043 * Hook in the page, zero it, and purge the cache for that 4044 * zeroed page. Invalidate the TLB as needed. 4045 */ 4046 *ptep = L2_S_PROTO | phys | 4047 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4048 PTE_SYNC(ptep); 4049 cpu_tlb_flushD_SE(cdstp + va_offset); 4050 cpu_cpwait(); 4051 bzero_page(cdstp + va_offset); 4052 /* 4053 * Unmap the page. 4054 */ 4055 *ptep = 0; 4056 PTE_SYNC(ptep); 4057 cpu_tlb_flushD_SE(cdstp + va_offset); 4058 #ifdef PMAP_CACHE_VIVT 4059 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4060 #endif 4061 #ifdef PMAP_CACHE_VIPT 4062 /* 4063 * This page is now cache resident so it now has a page color. 4064 * Any contents have been obliterated so clear the EXEC flag. 4065 */ 4066 if (!pmap_is_page_colored_p(pg)) { 4067 PMAPCOUNT(vac_color_new); 4068 pg->mdpage.pvh_attrs |= PVF_COLORED; 4069 } 4070 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4071 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4072 PMAPCOUNT(exec_discarded_zero); 4073 } 4074 #endif 4075 } 4076 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4077 4078 #if ARM_MMU_XSCALE == 1 4079 void 4080 pmap_zero_page_xscale(paddr_t phys) 4081 { 4082 #ifdef DEBUG 4083 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4084 4085 if (pg->mdpage.pvh_list != NULL) 4086 panic("pmap_zero_page: page has mappings"); 4087 #endif 4088 4089 KDASSERT((phys & PGOFSET) == 0); 4090 4091 /* 4092 * Hook in the page, zero it, and purge the cache for that 4093 * zeroed page. Invalidate the TLB as needed. 4094 */ 4095 *cdst_pte = L2_S_PROTO | phys | 4096 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4097 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4098 PTE_SYNC(cdst_pte); 4099 cpu_tlb_flushD_SE(cdstp); 4100 cpu_cpwait(); 4101 bzero_page(cdstp); 4102 xscale_cache_clean_minidata(); 4103 } 4104 #endif /* ARM_MMU_XSCALE == 1 */ 4105 4106 /* pmap_pageidlezero() 4107 * 4108 * The same as above, except that we assume that the page is not 4109 * mapped. This means we never have to flush the cache first. Called 4110 * from the idle loop. 4111 */ 4112 bool 4113 pmap_pageidlezero(paddr_t phys) 4114 { 4115 unsigned int i; 4116 int *ptr; 4117 bool rv = true; 4118 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4119 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4120 #endif 4121 #ifdef PMAP_CACHE_VIPT 4122 /* Choose the last page color it had, if any */ 4123 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4124 #else 4125 const vsize_t va_offset = 0; 4126 #endif 4127 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4128 4129 4130 #ifdef DEBUG 4131 if (pg->mdpage.pvh_list != NULL) 4132 panic("pmap_pageidlezero: page has mappings"); 4133 #endif 4134 4135 KDASSERT((phys & PGOFSET) == 0); 4136 4137 /* 4138 * Hook in the page, zero it, and purge the cache for that 4139 * zeroed page. Invalidate the TLB as needed. 4140 */ 4141 *ptep = L2_S_PROTO | phys | 4142 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4143 PTE_SYNC(ptep); 4144 cpu_tlb_flushD_SE(cdstp + va_offset); 4145 cpu_cpwait(); 4146 4147 for (i = 0, ptr = (int *)(cdstp + va_offset); 4148 i < (PAGE_SIZE / sizeof(int)); i++) { 4149 if (sched_curcpu_runnable_p() != 0) { 4150 /* 4151 * A process has become ready. Abort now, 4152 * so we don't keep it waiting while we 4153 * do slow memory access to finish this 4154 * page. 4155 */ 4156 rv = false; 4157 break; 4158 } 4159 *ptr++ = 0; 4160 } 4161 4162 #ifdef PMAP_CACHE_VIVT 4163 if (rv) 4164 /* 4165 * if we aborted we'll rezero this page again later so don't 4166 * purge it unless we finished it 4167 */ 4168 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4169 #elif defined(PMAP_CACHE_VIPT) 4170 /* 4171 * This page is now cache resident so it now has a page color. 4172 * Any contents have been obliterated so clear the EXEC flag. 4173 */ 4174 if (!pmap_is_page_colored_p(pg)) { 4175 PMAPCOUNT(vac_color_new); 4176 pg->mdpage.pvh_attrs |= PVF_COLORED; 4177 } 4178 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4179 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4180 PMAPCOUNT(exec_discarded_zero); 4181 } 4182 #endif 4183 /* 4184 * Unmap the page. 4185 */ 4186 *ptep = 0; 4187 PTE_SYNC(ptep); 4188 cpu_tlb_flushD_SE(cdstp + va_offset); 4189 4190 return (rv); 4191 } 4192 4193 /* 4194 * pmap_copy_page() 4195 * 4196 * Copy one physical page into another, by mapping the pages into 4197 * hook points. The same comment regarding cachability as in 4198 * pmap_zero_page also applies here. 4199 */ 4200 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4201 void 4202 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4203 { 4204 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4205 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4206 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4207 #endif 4208 #ifdef PMAP_CACHE_VIPT 4209 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4210 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4211 #else 4212 const vsize_t src_va_offset = 0; 4213 const vsize_t dst_va_offset = 0; 4214 #endif 4215 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4216 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4217 4218 #ifdef DEBUG 4219 if (dst_pg->mdpage.pvh_list != NULL) 4220 panic("pmap_copy_page: dst page has mappings"); 4221 #endif 4222 4223 #ifdef PMAP_CACHE_VIPT 4224 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4225 #endif 4226 KDASSERT((src & PGOFSET) == 0); 4227 KDASSERT((dst & PGOFSET) == 0); 4228 4229 /* 4230 * Clean the source page. Hold the source page's lock for 4231 * the duration of the copy so that no other mappings can 4232 * be created while we have a potentially aliased mapping. 4233 */ 4234 simple_lock(&src_pg->mdpage.pvh_slock); 4235 #ifdef PMAP_CACHE_VIVT 4236 (void) pmap_clean_page(src_pg->mdpage.pvh_list, true); 4237 #endif 4238 4239 /* 4240 * Map the pages into the page hook points, copy them, and purge 4241 * the cache for the appropriate page. Invalidate the TLB 4242 * as required. 4243 */ 4244 *src_ptep = L2_S_PROTO 4245 | src 4246 #ifdef PMAP_CACHE_VIPT 4247 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4248 #endif 4249 #ifdef PMAP_CACHE_VIVT 4250 | pte_l2_s_cache_mode 4251 #endif 4252 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4253 *dst_ptep = L2_S_PROTO | dst | 4254 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4255 PTE_SYNC(src_ptep); 4256 PTE_SYNC(dst_ptep); 4257 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4258 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4259 cpu_cpwait(); 4260 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4261 #ifdef PMAP_CACHE_VIVT 4262 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4263 #endif 4264 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4265 #ifdef PMAP_CACHE_VIVT 4266 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4267 #endif 4268 /* 4269 * Unmap the pages. 4270 */ 4271 *src_ptep = 0; 4272 *dst_ptep = 0; 4273 PTE_SYNC(src_ptep); 4274 PTE_SYNC(dst_ptep); 4275 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4276 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4277 #ifdef PMAP_CACHE_VIPT 4278 /* 4279 * Now that the destination page is in the cache, mark it as colored. 4280 * If this was an exec page, discard it. 4281 */ 4282 if (!pmap_is_page_colored_p(dst_pg)) { 4283 PMAPCOUNT(vac_color_new); 4284 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4285 } 4286 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4287 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4288 PMAPCOUNT(exec_discarded_copy); 4289 } 4290 #endif 4291 } 4292 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4293 4294 #if ARM_MMU_XSCALE == 1 4295 void 4296 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4297 { 4298 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4299 #ifdef DEBUG 4300 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4301 4302 if (dst_pg->mdpage.pvh_list != NULL) 4303 panic("pmap_copy_page: dst page has mappings"); 4304 #endif 4305 4306 KDASSERT((src & PGOFSET) == 0); 4307 KDASSERT((dst & PGOFSET) == 0); 4308 4309 /* 4310 * Clean the source page. Hold the source page's lock for 4311 * the duration of the copy so that no other mappings can 4312 * be created while we have a potentially aliased mapping. 4313 */ 4314 simple_lock(&src_pg->mdpage.pvh_slock); 4315 #ifdef PMAP_CACHE_VIVT 4316 (void) pmap_clean_page(src_pg->mdpage.pvh_list, true); 4317 #endif 4318 4319 /* 4320 * Map the pages into the page hook points, copy them, and purge 4321 * the cache for the appropriate page. Invalidate the TLB 4322 * as required. 4323 */ 4324 *csrc_pte = L2_S_PROTO | src | 4325 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4326 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4327 PTE_SYNC(csrc_pte); 4328 *cdst_pte = L2_S_PROTO | dst | 4329 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4330 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4331 PTE_SYNC(cdst_pte); 4332 cpu_tlb_flushD_SE(csrcp); 4333 cpu_tlb_flushD_SE(cdstp); 4334 cpu_cpwait(); 4335 bcopy_page(csrcp, cdstp); 4336 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4337 xscale_cache_clean_minidata(); 4338 } 4339 #endif /* ARM_MMU_XSCALE == 1 */ 4340 4341 /* 4342 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4343 * 4344 * Return the start and end addresses of the kernel's virtual space. 4345 * These values are setup in pmap_bootstrap and are updated as pages 4346 * are allocated. 4347 */ 4348 void 4349 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4350 { 4351 *start = virtual_avail; 4352 *end = virtual_end; 4353 } 4354 4355 /* 4356 * Helper function for pmap_grow_l2_bucket() 4357 */ 4358 static inline int 4359 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4360 { 4361 struct l2_bucket *l2b; 4362 pt_entry_t *ptep; 4363 paddr_t pa; 4364 4365 if (uvm.page_init_done == false) { 4366 #ifdef PMAP_STEAL_MEMORY 4367 pv_addr_t pv; 4368 pmap_boot_pagealloc(PAGE_SIZE, 4369 #ifdef PMAP_CACHE_VIPT 4370 arm_cache_prefer_mask, 4371 va & arm_cache_prefer_mask, 4372 #else 4373 0, 0, 4374 #endif 4375 &pv); 4376 pa = pv.pv_pa; 4377 #else 4378 if (uvm_page_physget(&pa) == false) 4379 return (1); 4380 #endif /* PMAP_STEAL_MEMORY */ 4381 } else { 4382 struct vm_page *pg; 4383 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4384 if (pg == NULL) 4385 return (1); 4386 pa = VM_PAGE_TO_PHYS(pg); 4387 #ifdef PMAP_CACHE_VIPT 4388 /* 4389 * This new page must not have any mappings. However, it might 4390 * have previously used and therefore present in the cache. If 4391 * it doesn't have the desired color, we have to flush it from 4392 * the cache. And while we are at it, make sure to clear its 4393 * EXEC status. 4394 */ 4395 KASSERT(!(pg->mdpage.pvh_attrs & PVF_KENTRY)); 4396 KASSERT(pg->mdpage.pvh_list == NULL); 4397 if (pmap_is_page_colored_p(pg)) { 4398 if ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask) { 4399 pmap_flush_page(pg); 4400 PMAPCOUNT(vac_color_change); 4401 } else { 4402 PMAPCOUNT(vac_color_reuse); 4403 } 4404 } else { 4405 PMAPCOUNT(vac_color_new); 4406 } 4407 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 4408 PMAPCOUNT(exec_discarded_kremove); 4409 /* 4410 * We'll pretend this page was entered by pmap_kenter_pa 4411 */ 4412 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_EXEC; 4413 pg->mdpage.pvh_attrs |= va | PVF_KENTRY | PVF_COLORED | PVF_REF | PVF_MOD; 4414 #endif 4415 } 4416 4417 if (pap) 4418 *pap = pa; 4419 4420 PMAPCOUNT(pt_mappings); 4421 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4422 KDASSERT(l2b != NULL); 4423 4424 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4425 *ptep = L2_S_PROTO | pa | cache_mode | 4426 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4427 PTE_SYNC(ptep); 4428 memset((void *)va, 0, PAGE_SIZE); 4429 return (0); 4430 } 4431 4432 /* 4433 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4434 * used by pmap_growkernel(). 4435 */ 4436 static inline struct l2_bucket * 4437 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4438 { 4439 struct l2_dtable *l2; 4440 struct l2_bucket *l2b; 4441 u_short l1idx; 4442 vaddr_t nva; 4443 4444 l1idx = L1_IDX(va); 4445 4446 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4447 /* 4448 * No mapping at this address, as there is 4449 * no entry in the L1 table. 4450 * Need to allocate a new l2_dtable. 4451 */ 4452 nva = pmap_kernel_l2dtable_kva; 4453 if ((nva & PGOFSET) == 0) { 4454 /* 4455 * Need to allocate a backing page 4456 */ 4457 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4458 return (NULL); 4459 } 4460 4461 l2 = (struct l2_dtable *)nva; 4462 nva += sizeof(struct l2_dtable); 4463 4464 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4465 /* 4466 * The new l2_dtable straddles a page boundary. 4467 * Map in another page to cover it. 4468 */ 4469 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4470 return (NULL); 4471 } 4472 4473 pmap_kernel_l2dtable_kva = nva; 4474 4475 /* 4476 * Link it into the parent pmap 4477 */ 4478 pm->pm_l2[L2_IDX(l1idx)] = l2; 4479 } 4480 4481 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4482 4483 /* 4484 * Fetch pointer to the L2 page table associated with the address. 4485 */ 4486 if (l2b->l2b_kva == NULL) { 4487 pt_entry_t *ptep; 4488 4489 /* 4490 * No L2 page table has been allocated. Chances are, this 4491 * is because we just allocated the l2_dtable, above. 4492 */ 4493 nva = pmap_kernel_l2ptp_kva; 4494 ptep = (pt_entry_t *)nva; 4495 if ((nva & PGOFSET) == 0) { 4496 /* 4497 * Need to allocate a backing page 4498 */ 4499 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4500 &pmap_kernel_l2ptp_phys)) 4501 return (NULL); 4502 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4503 } 4504 4505 l2->l2_occupancy++; 4506 l2b->l2b_kva = ptep; 4507 l2b->l2b_l1idx = l1idx; 4508 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4509 4510 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4511 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4512 } 4513 4514 return (l2b); 4515 } 4516 4517 vaddr_t 4518 pmap_growkernel(vaddr_t maxkvaddr) 4519 { 4520 pmap_t kpm = pmap_kernel(); 4521 struct l1_ttable *l1; 4522 struct l2_bucket *l2b; 4523 pd_entry_t *pl1pd; 4524 int s; 4525 4526 if (maxkvaddr <= pmap_curmaxkvaddr) 4527 goto out; /* we are OK */ 4528 4529 NPDEBUG(PDB_GROWKERN, 4530 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4531 pmap_curmaxkvaddr, maxkvaddr)); 4532 4533 KDASSERT(maxkvaddr <= virtual_end); 4534 4535 /* 4536 * whoops! we need to add kernel PTPs 4537 */ 4538 4539 s = splhigh(); /* to be safe */ 4540 simple_lock(&kpm->pm_lock); 4541 4542 /* Map 1MB at a time */ 4543 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4544 4545 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4546 KDASSERT(l2b != NULL); 4547 4548 /* Distribute new L1 entry to all other L1s */ 4549 SLIST_FOREACH(l1, &l1_list, l1_link) { 4550 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4551 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4552 L1_C_PROTO; 4553 PTE_SYNC(pl1pd); 4554 } 4555 } 4556 4557 /* 4558 * flush out the cache, expensive but growkernel will happen so 4559 * rarely 4560 */ 4561 cpu_dcache_wbinv_all(); 4562 cpu_tlb_flushD(); 4563 cpu_cpwait(); 4564 4565 simple_unlock(&kpm->pm_lock); 4566 splx(s); 4567 4568 out: 4569 return (pmap_curmaxkvaddr); 4570 } 4571 4572 /************************ Utility routines ****************************/ 4573 4574 /* 4575 * vector_page_setprot: 4576 * 4577 * Manipulate the protection of the vector page. 4578 */ 4579 void 4580 vector_page_setprot(int prot) 4581 { 4582 struct l2_bucket *l2b; 4583 pt_entry_t *ptep; 4584 4585 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4586 KDASSERT(l2b != NULL); 4587 4588 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4589 4590 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4591 PTE_SYNC(ptep); 4592 cpu_tlb_flushD_SE(vector_page); 4593 cpu_cpwait(); 4594 } 4595 4596 /* 4597 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4598 * Returns true if the mapping exists, else false. 4599 * 4600 * NOTE: This function is only used by a couple of arm-specific modules. 4601 * It is not safe to take any pmap locks here, since we could be right 4602 * in the middle of debugging the pmap anyway... 4603 * 4604 * It is possible for this routine to return false even though a valid 4605 * mapping does exist. This is because we don't lock, so the metadata 4606 * state may be inconsistent. 4607 * 4608 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4609 * a "section" mapping. 4610 */ 4611 bool 4612 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4613 { 4614 struct l2_dtable *l2; 4615 pd_entry_t *pl1pd, l1pd; 4616 pt_entry_t *ptep; 4617 u_short l1idx; 4618 4619 if (pm->pm_l1 == NULL) 4620 return false; 4621 4622 l1idx = L1_IDX(va); 4623 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4624 l1pd = *pl1pd; 4625 4626 if (l1pte_section_p(l1pd)) { 4627 *ptp = NULL; 4628 return true; 4629 } 4630 4631 if (pm->pm_l2 == NULL) 4632 return false; 4633 4634 l2 = pm->pm_l2[L2_IDX(l1idx)]; 4635 4636 if (l2 == NULL || 4637 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 4638 return false; 4639 } 4640 4641 *ptp = &ptep[l2pte_index(va)]; 4642 return true; 4643 } 4644 4645 bool 4646 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 4647 { 4648 u_short l1idx; 4649 4650 if (pm->pm_l1 == NULL) 4651 return false; 4652 4653 l1idx = L1_IDX(va); 4654 *pdp = &pm->pm_l1->l1_kva[l1idx]; 4655 4656 return true; 4657 } 4658 4659 /************************ Bootstrapping routines ****************************/ 4660 4661 static void 4662 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 4663 { 4664 int i; 4665 4666 l1->l1_kva = l1pt; 4667 l1->l1_domain_use_count = 0; 4668 l1->l1_domain_first = 0; 4669 4670 for (i = 0; i < PMAP_DOMAINS; i++) 4671 l1->l1_domain_free[i] = i + 1; 4672 4673 /* 4674 * Copy the kernel's L1 entries to each new L1. 4675 */ 4676 if (pmap_initialized) 4677 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 4678 4679 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 4680 &l1->l1_physaddr) == false) 4681 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 4682 4683 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 4684 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 4685 } 4686 4687 /* 4688 * pmap_bootstrap() is called from the board-specific initarm() routine 4689 * once the kernel L1/L2 descriptors tables have been set up. 4690 * 4691 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 4692 * spread over a number of disparate files/functions. 4693 * 4694 * We are passed the following parameters 4695 * - kernel_l1pt 4696 * This is a pointer to the base of the kernel's L1 translation table. 4697 * - vstart 4698 * 1MB-aligned start of managed kernel virtual memory. 4699 * - vend 4700 * 1MB-aligned end of managed kernel virtual memory. 4701 * 4702 * We use the first parameter to build the metadata (struct l1_ttable and 4703 * struct l2_dtable) necessary to track kernel mappings. 4704 */ 4705 #define PMAP_STATIC_L2_SIZE 16 4706 void 4707 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 4708 { 4709 static struct l1_ttable static_l1; 4710 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 4711 struct l1_ttable *l1 = &static_l1; 4712 struct l2_dtable *l2; 4713 struct l2_bucket *l2b; 4714 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 4715 pmap_t pm = pmap_kernel(); 4716 pd_entry_t pde; 4717 pt_entry_t *ptep; 4718 paddr_t pa; 4719 vaddr_t va; 4720 vsize_t size; 4721 int nptes, l1idx, l2idx, l2next = 0; 4722 4723 /* 4724 * Initialise the kernel pmap object 4725 */ 4726 pm->pm_l1 = l1; 4727 pm->pm_domain = PMAP_DOMAIN_KERNEL; 4728 pm->pm_activated = true; 4729 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4730 simple_lock_init(&pm->pm_lock); 4731 pm->pm_obj.pgops = NULL; 4732 TAILQ_INIT(&pm->pm_obj.memq); 4733 pm->pm_obj.uo_npages = 0; 4734 pm->pm_obj.uo_refs = 1; 4735 4736 /* 4737 * Scan the L1 translation table created by initarm() and create 4738 * the required metadata for all valid mappings found in it. 4739 */ 4740 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 4741 pde = l1pt[l1idx]; 4742 4743 /* 4744 * We're only interested in Coarse mappings. 4745 * pmap_extract() can deal with section mappings without 4746 * recourse to checking L2 metadata. 4747 */ 4748 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 4749 continue; 4750 4751 /* 4752 * Lookup the KVA of this L2 descriptor table 4753 */ 4754 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 4755 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 4756 if (ptep == NULL) { 4757 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 4758 (u_int)l1idx << L1_S_SHIFT, pa); 4759 } 4760 4761 /* 4762 * Fetch the associated L2 metadata structure. 4763 * Allocate a new one if necessary. 4764 */ 4765 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4766 if (l2next == PMAP_STATIC_L2_SIZE) 4767 panic("pmap_bootstrap: out of static L2s"); 4768 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 4769 } 4770 4771 /* 4772 * One more L1 slot tracked... 4773 */ 4774 l2->l2_occupancy++; 4775 4776 /* 4777 * Fill in the details of the L2 descriptor in the 4778 * appropriate bucket. 4779 */ 4780 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4781 l2b->l2b_kva = ptep; 4782 l2b->l2b_phys = pa; 4783 l2b->l2b_l1idx = l1idx; 4784 4785 /* 4786 * Establish an initial occupancy count for this descriptor 4787 */ 4788 for (l2idx = 0; 4789 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 4790 l2idx++) { 4791 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 4792 l2b->l2b_occupancy++; 4793 } 4794 } 4795 4796 /* 4797 * Make sure the descriptor itself has the correct cache mode. 4798 * If not, fix it, but whine about the problem. Port-meisters 4799 * should consider this a clue to fix up their initarm() 4800 * function. :) 4801 */ 4802 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 4803 printf("pmap_bootstrap: WARNING! wrong cache mode for " 4804 "L2 pte @ %p\n", ptep); 4805 } 4806 } 4807 4808 /* 4809 * Ensure the primary (kernel) L1 has the correct cache mode for 4810 * a page table. Bitch if it is not correctly set. 4811 */ 4812 for (va = (vaddr_t)l1pt; 4813 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 4814 if (pmap_set_pt_cache_mode(l1pt, va)) 4815 printf("pmap_bootstrap: WARNING! wrong cache mode for " 4816 "primary L1 @ 0x%lx\n", va); 4817 } 4818 4819 cpu_dcache_wbinv_all(); 4820 cpu_tlb_flushID(); 4821 cpu_cpwait(); 4822 4823 /* 4824 * now we allocate the "special" VAs which are used for tmp mappings 4825 * by the pmap (and other modules). we allocate the VAs by advancing 4826 * virtual_avail (note that there are no pages mapped at these VAs). 4827 * 4828 * Managed KVM space start from wherever initarm() tells us. 4829 */ 4830 virtual_avail = vstart; 4831 virtual_end = vend; 4832 4833 #ifdef PMAP_CACHE_VIPT 4834 /* 4835 * If we have a VIPT cache, we need one page/pte per possible alias 4836 * page so we won't violate cache aliasing rules. 4837 */ 4838 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 4839 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 4840 #else 4841 nptes = 1; 4842 #endif 4843 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 4844 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 4845 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 4846 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 4847 pmap_alloc_specials(&virtual_avail, 1, (void *)&memhook, NULL); 4848 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 4849 (void *)&msgbufaddr, NULL); 4850 4851 /* 4852 * Allocate a range of kernel virtual address space to be used 4853 * for L2 descriptor tables and metadata allocation in 4854 * pmap_growkernel(). 4855 */ 4856 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 4857 pmap_alloc_specials(&virtual_avail, 4858 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 4859 &pmap_kernel_l2ptp_kva, NULL); 4860 4861 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 4862 pmap_alloc_specials(&virtual_avail, 4863 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 4864 &pmap_kernel_l2dtable_kva, NULL); 4865 4866 /* 4867 * init the static-global locks and global pmap list. 4868 */ 4869 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 4870 4871 /* 4872 * We can now initialise the first L1's metadata. 4873 */ 4874 SLIST_INIT(&l1_list); 4875 TAILQ_INIT(&l1_lru_list); 4876 simple_lock_init(&l1_lru_lock); 4877 pmap_init_l1(l1, l1pt); 4878 4879 /* Set up vector page L1 details, if necessary */ 4880 if (vector_page < KERNEL_BASE) { 4881 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 4882 l2b = pmap_get_l2_bucket(pm, vector_page); 4883 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 4884 L1_C_DOM(pm->pm_domain); 4885 } else 4886 pm->pm_pl1vec = NULL; 4887 4888 /* 4889 * Initialize the pmap pool and cache 4890 */ 4891 pool_init(&pmap_pmap_pool, sizeof(struct pmap), 0, 0, 0, "pmappl", 4892 &pool_allocator_nointr, IPL_NONE); 4893 pool_cache_init(&pmap_pmap_cache, &pmap_pmap_pool, 4894 pmap_pmap_ctor, NULL, NULL); 4895 LIST_INIT(&pmap_pmaps); 4896 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 4897 4898 /* 4899 * Initialize the pv pool. 4900 */ 4901 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 4902 &pmap_bootstrap_pv_allocator, IPL_NONE); 4903 4904 /* 4905 * Initialize the L2 dtable pool and cache. 4906 */ 4907 pool_init(&pmap_l2dtable_pool, sizeof(struct l2_dtable), 0, 0, 0, 4908 "l2dtblpl", NULL, IPL_NONE); 4909 pool_cache_init(&pmap_l2dtable_cache, &pmap_l2dtable_pool, 4910 pmap_l2dtable_ctor, NULL, NULL); 4911 4912 /* 4913 * Initialise the L2 descriptor table pool and cache 4914 */ 4915 pool_init(&pmap_l2ptp_pool, L2_TABLE_SIZE_REAL, 0, L2_TABLE_SIZE_REAL, 4916 0, "l2ptppl", NULL, IPL_NONE); 4917 pool_cache_init(&pmap_l2ptp_cache, &pmap_l2ptp_pool, 4918 pmap_l2ptp_ctor, NULL, NULL); 4919 4920 cpu_dcache_wbinv_all(); 4921 } 4922 4923 static int 4924 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 4925 { 4926 pd_entry_t *pdep, pde; 4927 pt_entry_t *ptep, pte; 4928 vaddr_t pa; 4929 int rv = 0; 4930 4931 /* 4932 * Make sure the descriptor itself has the correct cache mode 4933 */ 4934 pdep = &kl1[L1_IDX(va)]; 4935 pde = *pdep; 4936 4937 if (l1pte_section_p(pde)) { 4938 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 4939 *pdep = (pde & ~L1_S_CACHE_MASK) | 4940 pte_l1_s_cache_mode_pt; 4941 PTE_SYNC(pdep); 4942 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 4943 rv = 1; 4944 } 4945 } else { 4946 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 4947 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 4948 if (ptep == NULL) 4949 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 4950 4951 ptep = &ptep[l2pte_index(va)]; 4952 pte = *ptep; 4953 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 4954 *ptep = (pte & ~L2_S_CACHE_MASK) | 4955 pte_l2_s_cache_mode_pt; 4956 PTE_SYNC(ptep); 4957 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 4958 rv = 1; 4959 } 4960 } 4961 4962 return (rv); 4963 } 4964 4965 static void 4966 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 4967 { 4968 vaddr_t va = *availp; 4969 struct l2_bucket *l2b; 4970 4971 if (ptep) { 4972 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4973 if (l2b == NULL) 4974 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 4975 4976 if (ptep) 4977 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 4978 } 4979 4980 *vap = va; 4981 *availp = va + (PAGE_SIZE * pages); 4982 } 4983 4984 void 4985 pmap_init(void) 4986 { 4987 extern int physmem; 4988 4989 /* 4990 * Set the available memory vars - These do not map to real memory 4991 * addresses and cannot as the physical memory is fragmented. 4992 * They are used by ps for %mem calculations. 4993 * One could argue whether this should be the entire memory or just 4994 * the memory that is useable in a user process. 4995 */ 4996 avail_start = 0; 4997 avail_end = physmem * PAGE_SIZE; 4998 4999 /* 5000 * Now we need to free enough pv_entry structures to allow us to get 5001 * the kmem_map/kmem_object allocated and inited (done after this 5002 * function is finished). to do this we allocate one bootstrap page out 5003 * of kernel_map and use it to provide an initial pool of pv_entry 5004 * structures. we never free this page. 5005 */ 5006 pool_setlowat(&pmap_pv_pool, 5007 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5008 5009 pmap_initialized = true; 5010 } 5011 5012 static vaddr_t last_bootstrap_page = 0; 5013 static void *free_bootstrap_pages = NULL; 5014 5015 static void * 5016 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5017 { 5018 extern void *pool_page_alloc(struct pool *, int); 5019 vaddr_t new_page; 5020 void *rv; 5021 5022 if (pmap_initialized) 5023 return (pool_page_alloc(pp, flags)); 5024 5025 if (free_bootstrap_pages) { 5026 rv = free_bootstrap_pages; 5027 free_bootstrap_pages = *((void **)rv); 5028 return (rv); 5029 } 5030 5031 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5032 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5033 5034 KASSERT(new_page > last_bootstrap_page); 5035 last_bootstrap_page = new_page; 5036 return ((void *)new_page); 5037 } 5038 5039 static void 5040 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5041 { 5042 extern void pool_page_free(struct pool *, void *); 5043 5044 if ((vaddr_t)v <= last_bootstrap_page) { 5045 *((void **)v) = free_bootstrap_pages; 5046 free_bootstrap_pages = v; 5047 return; 5048 } 5049 5050 if (pmap_initialized) { 5051 pool_page_free(pp, v); 5052 return; 5053 } 5054 } 5055 5056 /* 5057 * pmap_postinit() 5058 * 5059 * This routine is called after the vm and kmem subsystems have been 5060 * initialised. This allows the pmap code to perform any initialisation 5061 * that can only be done one the memory allocation is in place. 5062 */ 5063 void 5064 pmap_postinit(void) 5065 { 5066 extern paddr_t physical_start, physical_end; 5067 struct l2_bucket *l2b; 5068 struct l1_ttable *l1; 5069 struct pglist plist; 5070 struct vm_page *m; 5071 pd_entry_t *pl1pt; 5072 pt_entry_t *ptep, pte; 5073 vaddr_t va, eva; 5074 u_int loop, needed; 5075 int error; 5076 5077 pool_setlowat(&pmap_l2ptp_pool, 5078 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5079 pool_setlowat(&pmap_l2dtable_pool, 5080 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5081 5082 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5083 needed -= 1; 5084 5085 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5086 5087 for (loop = 0; loop < needed; loop++, l1++) { 5088 /* Allocate a L1 page table */ 5089 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5090 if (va == 0) 5091 panic("Cannot allocate L1 KVM"); 5092 5093 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5094 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5095 if (error) 5096 panic("Cannot allocate L1 physical pages"); 5097 5098 m = TAILQ_FIRST(&plist); 5099 eva = va + L1_TABLE_SIZE; 5100 pl1pt = (pd_entry_t *)va; 5101 5102 while (m && va < eva) { 5103 paddr_t pa = VM_PAGE_TO_PHYS(m); 5104 5105 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 5106 5107 /* 5108 * Make sure the L1 descriptor table is mapped 5109 * with the cache-mode set to write-through. 5110 */ 5111 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5112 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5113 pte = *ptep; 5114 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5115 *ptep = pte; 5116 PTE_SYNC(ptep); 5117 cpu_tlb_flushD_SE(va); 5118 5119 va += PAGE_SIZE; 5120 m = TAILQ_NEXT(m, pageq); 5121 } 5122 5123 #ifdef DIAGNOSTIC 5124 if (m) 5125 panic("pmap_alloc_l1pt: pglist not empty"); 5126 #endif /* DIAGNOSTIC */ 5127 5128 pmap_init_l1(l1, pl1pt); 5129 } 5130 5131 #ifdef DEBUG 5132 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5133 needed); 5134 #endif 5135 } 5136 5137 /* 5138 * Note that the following routines are used by board-specific initialisation 5139 * code to configure the initial kernel page tables. 5140 * 5141 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5142 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5143 * behaviour of the old pmap, and provides an easy migration path for 5144 * initial bring-up of the new pmap on existing ports. Fortunately, 5145 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5146 * will be deprecated. 5147 * 5148 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5149 * tables. 5150 */ 5151 5152 /* 5153 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5154 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5155 * find them as necessary. 5156 * 5157 * Note that the data on this list MUST remain valid after initarm() returns, 5158 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5159 */ 5160 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5161 5162 static vaddr_t 5163 kernel_pt_lookup(paddr_t pa) 5164 { 5165 pv_addr_t *pv; 5166 5167 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5168 #ifndef ARM32_NEW_VM_LAYOUT 5169 if (pv->pv_pa == (pa & ~PGOFSET)) 5170 return (pv->pv_va | (pa & PGOFSET)); 5171 #else 5172 if (pv->pv_pa == pa) 5173 return (pv->pv_va); 5174 #endif 5175 } 5176 return (0); 5177 } 5178 5179 /* 5180 * pmap_map_section: 5181 * 5182 * Create a single section mapping. 5183 */ 5184 void 5185 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5186 { 5187 pd_entry_t *pde = (pd_entry_t *) l1pt; 5188 pd_entry_t fl; 5189 5190 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5191 5192 switch (cache) { 5193 case PTE_NOCACHE: 5194 default: 5195 fl = 0; 5196 break; 5197 5198 case PTE_CACHE: 5199 fl = pte_l1_s_cache_mode; 5200 break; 5201 5202 case PTE_PAGETABLE: 5203 fl = pte_l1_s_cache_mode_pt; 5204 break; 5205 } 5206 5207 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5208 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5209 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5210 } 5211 5212 /* 5213 * pmap_map_entry: 5214 * 5215 * Create a single page mapping. 5216 */ 5217 void 5218 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5219 { 5220 pd_entry_t *pde = (pd_entry_t *) l1pt; 5221 pt_entry_t fl; 5222 pt_entry_t *pte; 5223 5224 KASSERT(((va | pa) & PGOFSET) == 0); 5225 5226 switch (cache) { 5227 case PTE_NOCACHE: 5228 default: 5229 fl = 0; 5230 break; 5231 5232 case PTE_CACHE: 5233 fl = pte_l2_s_cache_mode; 5234 break; 5235 5236 case PTE_PAGETABLE: 5237 fl = pte_l2_s_cache_mode_pt; 5238 break; 5239 } 5240 5241 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5242 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5243 5244 #ifndef ARM32_NEW_VM_LAYOUT 5245 pte = (pt_entry_t *) 5246 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5247 #else 5248 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5249 #endif 5250 if (pte == NULL) 5251 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5252 5253 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5254 #ifndef ARM32_NEW_VM_LAYOUT 5255 pte += (va >> PGSHIFT) & 0x3ff; 5256 #else 5257 pte += l2pte_index(va); 5258 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5259 #endif 5260 *pte = fl; 5261 PTE_SYNC(pte); 5262 } 5263 5264 /* 5265 * pmap_link_l2pt: 5266 * 5267 * Link the L2 page table specified by "l2pv" into the L1 5268 * page table at the slot for "va". 5269 */ 5270 void 5271 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5272 { 5273 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5274 u_int slot = va >> L1_S_SHIFT; 5275 5276 #ifndef ARM32_NEW_VM_LAYOUT 5277 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5278 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5279 #endif 5280 5281 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5282 5283 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5284 #ifdef ARM32_NEW_VM_LAYOUT 5285 PTE_SYNC(&pde[slot]); 5286 #else 5287 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5288 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5289 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5290 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5291 #endif 5292 5293 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5294 } 5295 5296 /* 5297 * pmap_map_chunk: 5298 * 5299 * Map a chunk of memory using the most efficient mappings 5300 * possible (section, large page, small page) into the 5301 * provided L1 and L2 tables at the specified virtual address. 5302 */ 5303 vsize_t 5304 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5305 int prot, int cache) 5306 { 5307 pd_entry_t *pde = (pd_entry_t *) l1pt; 5308 pt_entry_t *pte, f1, f2s, f2l; 5309 vsize_t resid; 5310 int i; 5311 5312 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5313 5314 if (l1pt == 0) 5315 panic("pmap_map_chunk: no L1 table provided"); 5316 5317 #ifdef VERBOSE_INIT_ARM 5318 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5319 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5320 #endif 5321 5322 switch (cache) { 5323 case PTE_NOCACHE: 5324 default: 5325 f1 = 0; 5326 f2l = 0; 5327 f2s = 0; 5328 break; 5329 5330 case PTE_CACHE: 5331 f1 = pte_l1_s_cache_mode; 5332 f2l = pte_l2_l_cache_mode; 5333 f2s = pte_l2_s_cache_mode; 5334 break; 5335 5336 case PTE_PAGETABLE: 5337 f1 = pte_l1_s_cache_mode_pt; 5338 f2l = pte_l2_l_cache_mode_pt; 5339 f2s = pte_l2_s_cache_mode_pt; 5340 break; 5341 } 5342 5343 size = resid; 5344 5345 while (resid > 0) { 5346 /* See if we can use a section mapping. */ 5347 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5348 #ifdef VERBOSE_INIT_ARM 5349 printf("S"); 5350 #endif 5351 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5352 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5353 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5354 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5355 va += L1_S_SIZE; 5356 pa += L1_S_SIZE; 5357 resid -= L1_S_SIZE; 5358 continue; 5359 } 5360 5361 /* 5362 * Ok, we're going to use an L2 table. Make sure 5363 * one is actually in the corresponding L1 slot 5364 * for the current VA. 5365 */ 5366 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5367 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5368 5369 #ifndef ARM32_NEW_VM_LAYOUT 5370 pte = (pt_entry_t *) 5371 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5372 #else 5373 pte = (pt_entry_t *) kernel_pt_lookup( 5374 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5375 #endif 5376 if (pte == NULL) 5377 panic("pmap_map_chunk: can't find L2 table for VA" 5378 "0x%08lx", va); 5379 5380 /* See if we can use a L2 large page mapping. */ 5381 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5382 #ifdef VERBOSE_INIT_ARM 5383 printf("L"); 5384 #endif 5385 for (i = 0; i < 16; i++) { 5386 #ifndef ARM32_NEW_VM_LAYOUT 5387 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5388 L2_L_PROTO | pa | 5389 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5390 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5391 #else 5392 pte[l2pte_index(va) + i] = 5393 L2_L_PROTO | pa | 5394 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5395 PTE_SYNC(&pte[l2pte_index(va) + i]); 5396 #endif 5397 } 5398 va += L2_L_SIZE; 5399 pa += L2_L_SIZE; 5400 resid -= L2_L_SIZE; 5401 continue; 5402 } 5403 5404 /* Use a small page mapping. */ 5405 #ifdef VERBOSE_INIT_ARM 5406 printf("P"); 5407 #endif 5408 #ifndef ARM32_NEW_VM_LAYOUT 5409 pte[(va >> PGSHIFT) & 0x3ff] = 5410 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5411 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5412 #else 5413 pte[l2pte_index(va)] = 5414 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5415 PTE_SYNC(&pte[l2pte_index(va)]); 5416 #endif 5417 va += PAGE_SIZE; 5418 pa += PAGE_SIZE; 5419 resid -= PAGE_SIZE; 5420 } 5421 #ifdef VERBOSE_INIT_ARM 5422 printf("\n"); 5423 #endif 5424 return (size); 5425 } 5426 5427 /********************** Static device map routines ***************************/ 5428 5429 static const struct pmap_devmap *pmap_devmap_table; 5430 5431 /* 5432 * Register the devmap table. This is provided in case early console 5433 * initialization needs to register mappings created by bootstrap code 5434 * before pmap_devmap_bootstrap() is called. 5435 */ 5436 void 5437 pmap_devmap_register(const struct pmap_devmap *table) 5438 { 5439 5440 pmap_devmap_table = table; 5441 } 5442 5443 /* 5444 * Map all of the static regions in the devmap table, and remember 5445 * the devmap table so other parts of the kernel can look up entries 5446 * later. 5447 */ 5448 void 5449 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5450 { 5451 int i; 5452 5453 pmap_devmap_table = table; 5454 5455 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5456 #ifdef VERBOSE_INIT_ARM 5457 printf("devmap: %08lx -> %08lx @ %08lx\n", 5458 pmap_devmap_table[i].pd_pa, 5459 pmap_devmap_table[i].pd_pa + 5460 pmap_devmap_table[i].pd_size - 1, 5461 pmap_devmap_table[i].pd_va); 5462 #endif 5463 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5464 pmap_devmap_table[i].pd_pa, 5465 pmap_devmap_table[i].pd_size, 5466 pmap_devmap_table[i].pd_prot, 5467 pmap_devmap_table[i].pd_cache); 5468 } 5469 } 5470 5471 const struct pmap_devmap * 5472 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5473 { 5474 uint64_t endpa; 5475 int i; 5476 5477 if (pmap_devmap_table == NULL) 5478 return (NULL); 5479 5480 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5481 5482 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5483 if (pa >= pmap_devmap_table[i].pd_pa && 5484 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5485 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5486 return (&pmap_devmap_table[i]); 5487 } 5488 5489 return (NULL); 5490 } 5491 5492 const struct pmap_devmap * 5493 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5494 { 5495 int i; 5496 5497 if (pmap_devmap_table == NULL) 5498 return (NULL); 5499 5500 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5501 if (va >= pmap_devmap_table[i].pd_va && 5502 va + size - 1 <= pmap_devmap_table[i].pd_va + 5503 pmap_devmap_table[i].pd_size - 1) 5504 return (&pmap_devmap_table[i]); 5505 } 5506 5507 return (NULL); 5508 } 5509 5510 /********************** PTE initialization routines **************************/ 5511 5512 /* 5513 * These routines are called when the CPU type is identified to set up 5514 * the PTE prototypes, cache modes, etc. 5515 * 5516 * The variables are always here, just in case LKMs need to reference 5517 * them (though, they shouldn't). 5518 */ 5519 5520 pt_entry_t pte_l1_s_cache_mode; 5521 pt_entry_t pte_l1_s_cache_mode_pt; 5522 pt_entry_t pte_l1_s_cache_mask; 5523 5524 pt_entry_t pte_l2_l_cache_mode; 5525 pt_entry_t pte_l2_l_cache_mode_pt; 5526 pt_entry_t pte_l2_l_cache_mask; 5527 5528 pt_entry_t pte_l2_s_cache_mode; 5529 pt_entry_t pte_l2_s_cache_mode_pt; 5530 pt_entry_t pte_l2_s_cache_mask; 5531 5532 pt_entry_t pte_l2_s_prot_u; 5533 pt_entry_t pte_l2_s_prot_w; 5534 pt_entry_t pte_l2_s_prot_mask; 5535 5536 pt_entry_t pte_l1_s_proto; 5537 pt_entry_t pte_l1_c_proto; 5538 pt_entry_t pte_l2_s_proto; 5539 5540 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5541 void (*pmap_zero_page_func)(paddr_t); 5542 5543 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5544 void 5545 pmap_pte_init_generic(void) 5546 { 5547 5548 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5549 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5550 5551 pte_l2_l_cache_mode = L2_B|L2_C; 5552 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5553 5554 pte_l2_s_cache_mode = L2_B|L2_C; 5555 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5556 5557 /* 5558 * If we have a write-through cache, set B and C. If 5559 * we have a write-back cache, then we assume setting 5560 * only C will make those pages write-through. 5561 */ 5562 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5563 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5564 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5565 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5566 } else { 5567 #if ARM_MMU_V6 > 1 5568 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5569 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5570 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5571 #else 5572 pte_l1_s_cache_mode_pt = L1_S_C; 5573 pte_l2_l_cache_mode_pt = L2_C; 5574 pte_l2_s_cache_mode_pt = L2_C; 5575 #endif 5576 } 5577 5578 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5579 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5580 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5581 5582 pte_l1_s_proto = L1_S_PROTO_generic; 5583 pte_l1_c_proto = L1_C_PROTO_generic; 5584 pte_l2_s_proto = L2_S_PROTO_generic; 5585 5586 pmap_copy_page_func = pmap_copy_page_generic; 5587 pmap_zero_page_func = pmap_zero_page_generic; 5588 } 5589 5590 #if defined(CPU_ARM8) 5591 void 5592 pmap_pte_init_arm8(void) 5593 { 5594 5595 /* 5596 * ARM8 is compatible with generic, but we need to use 5597 * the page tables uncached. 5598 */ 5599 pmap_pte_init_generic(); 5600 5601 pte_l1_s_cache_mode_pt = 0; 5602 pte_l2_l_cache_mode_pt = 0; 5603 pte_l2_s_cache_mode_pt = 0; 5604 } 5605 #endif /* CPU_ARM8 */ 5606 5607 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5608 void 5609 pmap_pte_init_arm9(void) 5610 { 5611 5612 /* 5613 * ARM9 is compatible with generic, but we want to use 5614 * write-through caching for now. 5615 */ 5616 pmap_pte_init_generic(); 5617 5618 pte_l1_s_cache_mode = L1_S_C; 5619 pte_l2_l_cache_mode = L2_C; 5620 pte_l2_s_cache_mode = L2_C; 5621 5622 pte_l1_s_cache_mode_pt = L1_S_C; 5623 pte_l2_l_cache_mode_pt = L2_C; 5624 pte_l2_s_cache_mode_pt = L2_C; 5625 } 5626 #endif /* CPU_ARM9 */ 5627 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5628 5629 #if defined(CPU_ARM10) 5630 void 5631 pmap_pte_init_arm10(void) 5632 { 5633 5634 /* 5635 * ARM10 is compatible with generic, but we want to use 5636 * write-through caching for now. 5637 */ 5638 pmap_pte_init_generic(); 5639 5640 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 5641 pte_l2_l_cache_mode = L2_B | L2_C; 5642 pte_l2_s_cache_mode = L2_B | L2_C; 5643 5644 pte_l1_s_cache_mode_pt = L1_S_C; 5645 pte_l2_l_cache_mode_pt = L2_C; 5646 pte_l2_s_cache_mode_pt = L2_C; 5647 5648 } 5649 #endif /* CPU_ARM10 */ 5650 5651 #if ARM_MMU_SA1 == 1 5652 void 5653 pmap_pte_init_sa1(void) 5654 { 5655 5656 /* 5657 * The StrongARM SA-1 cache does not have a write-through 5658 * mode. So, do the generic initialization, then reset 5659 * the page table cache mode to B=1,C=1, and note that 5660 * the PTEs need to be sync'd. 5661 */ 5662 pmap_pte_init_generic(); 5663 5664 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5665 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5666 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5667 5668 pmap_needs_pte_sync = 1; 5669 } 5670 #endif /* ARM_MMU_SA1 == 1*/ 5671 5672 #if ARM_MMU_XSCALE == 1 5673 #if (ARM_NMMUS > 1) 5674 static u_int xscale_use_minidata; 5675 #endif 5676 5677 void 5678 pmap_pte_init_xscale(void) 5679 { 5680 uint32_t auxctl; 5681 int write_through = 0; 5682 5683 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5684 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 5685 5686 pte_l2_l_cache_mode = L2_B|L2_C; 5687 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 5688 5689 pte_l2_s_cache_mode = L2_B|L2_C; 5690 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 5691 5692 pte_l1_s_cache_mode_pt = L1_S_C; 5693 pte_l2_l_cache_mode_pt = L2_C; 5694 pte_l2_s_cache_mode_pt = L2_C; 5695 5696 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 5697 /* 5698 * The XScale core has an enhanced mode where writes that 5699 * miss the cache cause a cache line to be allocated. This 5700 * is significantly faster than the traditional, write-through 5701 * behavior of this case. 5702 */ 5703 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 5704 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 5705 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 5706 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 5707 5708 #ifdef XSCALE_CACHE_WRITE_THROUGH 5709 /* 5710 * Some versions of the XScale core have various bugs in 5711 * their cache units, the work-around for which is to run 5712 * the cache in write-through mode. Unfortunately, this 5713 * has a major (negative) impact on performance. So, we 5714 * go ahead and run fast-and-loose, in the hopes that we 5715 * don't line up the planets in a way that will trip the 5716 * bugs. 5717 * 5718 * However, we give you the option to be slow-but-correct. 5719 */ 5720 write_through = 1; 5721 #elif defined(XSCALE_CACHE_WRITE_BACK) 5722 /* force write back cache mode */ 5723 write_through = 0; 5724 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 5725 /* 5726 * Intel PXA2[15]0 processors are known to have a bug in 5727 * write-back cache on revision 4 and earlier (stepping 5728 * A[01] and B[012]). Fixed for C0 and later. 5729 */ 5730 { 5731 uint32_t id, type; 5732 5733 id = cpufunc_id(); 5734 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 5735 5736 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 5737 if ((id & CPU_ID_REVISION_MASK) < 5) { 5738 /* write through for stepping A0-1 and B0-2 */ 5739 write_through = 1; 5740 } 5741 } 5742 } 5743 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 5744 5745 if (write_through) { 5746 pte_l1_s_cache_mode = L1_S_C; 5747 pte_l2_l_cache_mode = L2_C; 5748 pte_l2_s_cache_mode = L2_C; 5749 } 5750 5751 #if (ARM_NMMUS > 1) 5752 xscale_use_minidata = 1; 5753 #endif 5754 5755 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 5756 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 5757 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 5758 5759 pte_l1_s_proto = L1_S_PROTO_xscale; 5760 pte_l1_c_proto = L1_C_PROTO_xscale; 5761 pte_l2_s_proto = L2_S_PROTO_xscale; 5762 5763 pmap_copy_page_func = pmap_copy_page_xscale; 5764 pmap_zero_page_func = pmap_zero_page_xscale; 5765 5766 /* 5767 * Disable ECC protection of page table access, for now. 5768 */ 5769 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 5770 auxctl &= ~XSCALE_AUXCTL_P; 5771 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 5772 } 5773 5774 /* 5775 * xscale_setup_minidata: 5776 * 5777 * Set up the mini-data cache clean area. We require the 5778 * caller to allocate the right amount of physically and 5779 * virtually contiguous space. 5780 */ 5781 void 5782 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 5783 { 5784 extern vaddr_t xscale_minidata_clean_addr; 5785 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 5786 pd_entry_t *pde = (pd_entry_t *) l1pt; 5787 pt_entry_t *pte; 5788 vsize_t size; 5789 uint32_t auxctl; 5790 5791 xscale_minidata_clean_addr = va; 5792 5793 /* Round it to page size. */ 5794 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 5795 5796 for (; size != 0; 5797 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 5798 #ifndef ARM32_NEW_VM_LAYOUT 5799 pte = (pt_entry_t *) 5800 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5801 #else 5802 pte = (pt_entry_t *) kernel_pt_lookup( 5803 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5804 #endif 5805 if (pte == NULL) 5806 panic("xscale_setup_minidata: can't find L2 table for " 5807 "VA 0x%08lx", va); 5808 #ifndef ARM32_NEW_VM_LAYOUT 5809 pte[(va >> PGSHIFT) & 0x3ff] = 5810 #else 5811 pte[l2pte_index(va)] = 5812 #endif 5813 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 5814 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 5815 } 5816 5817 /* 5818 * Configure the mini-data cache for write-back with 5819 * read/write-allocate. 5820 * 5821 * NOTE: In order to reconfigure the mini-data cache, we must 5822 * make sure it contains no valid data! In order to do that, 5823 * we must issue a global data cache invalidate command! 5824 * 5825 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 5826 * THIS IS VERY IMPORTANT! 5827 */ 5828 5829 /* Invalidate data and mini-data. */ 5830 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 5831 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 5832 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 5833 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 5834 } 5835 5836 /* 5837 * Change the PTEs for the specified kernel mappings such that they 5838 * will use the mini data cache instead of the main data cache. 5839 */ 5840 void 5841 pmap_uarea(vaddr_t va) 5842 { 5843 struct l2_bucket *l2b; 5844 pt_entry_t *ptep, *sptep, pte; 5845 vaddr_t next_bucket, eva; 5846 5847 #if (ARM_NMMUS > 1) 5848 if (xscale_use_minidata == 0) 5849 return; 5850 #endif 5851 5852 eva = va + USPACE; 5853 5854 while (va < eva) { 5855 next_bucket = L2_NEXT_BUCKET(va); 5856 if (next_bucket > eva) 5857 next_bucket = eva; 5858 5859 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5860 KDASSERT(l2b != NULL); 5861 5862 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 5863 5864 while (va < next_bucket) { 5865 pte = *ptep; 5866 if (!l2pte_minidata(pte)) { 5867 cpu_dcache_wbinv_range(va, PAGE_SIZE); 5868 cpu_tlb_flushD_SE(va); 5869 *ptep = pte & ~L2_B; 5870 } 5871 ptep++; 5872 va += PAGE_SIZE; 5873 } 5874 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 5875 } 5876 cpu_cpwait(); 5877 } 5878 #endif /* ARM_MMU_XSCALE == 1 */ 5879 5880 #if defined(DDB) 5881 /* 5882 * A couple of ddb-callable functions for dumping pmaps 5883 */ 5884 void pmap_dump_all(void); 5885 void pmap_dump(pmap_t); 5886 5887 void 5888 pmap_dump_all(void) 5889 { 5890 pmap_t pm; 5891 5892 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 5893 if (pm == pmap_kernel()) 5894 continue; 5895 pmap_dump(pm); 5896 printf("\n"); 5897 } 5898 } 5899 5900 static pt_entry_t ncptes[64]; 5901 static void pmap_dump_ncpg(pmap_t); 5902 5903 void 5904 pmap_dump(pmap_t pm) 5905 { 5906 struct l2_dtable *l2; 5907 struct l2_bucket *l2b; 5908 pt_entry_t *ptep, pte; 5909 vaddr_t l2_va, l2b_va, va; 5910 int i, j, k, occ, rows = 0; 5911 5912 if (pm == pmap_kernel()) 5913 printf("pmap_kernel (%p): ", pm); 5914 else 5915 printf("user pmap (%p): ", pm); 5916 5917 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 5918 5919 l2_va = 0; 5920 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 5921 l2 = pm->pm_l2[i]; 5922 5923 if (l2 == NULL || l2->l2_occupancy == 0) 5924 continue; 5925 5926 l2b_va = l2_va; 5927 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 5928 l2b = &l2->l2_bucket[j]; 5929 5930 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 5931 continue; 5932 5933 ptep = l2b->l2b_kva; 5934 5935 for (k = 0; k < 256 && ptep[k] == 0; k++) 5936 ; 5937 5938 k &= ~63; 5939 occ = l2b->l2b_occupancy; 5940 va = l2b_va + (k * 4096); 5941 for (; k < 256; k++, va += 0x1000) { 5942 char ch = ' '; 5943 if ((k % 64) == 0) { 5944 if ((rows % 8) == 0) { 5945 printf( 5946 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 5947 } 5948 printf("%08lx: ", va); 5949 } 5950 5951 ncptes[k & 63] = 0; 5952 pte = ptep[k]; 5953 if (pte == 0) { 5954 ch = '.'; 5955 } else { 5956 occ--; 5957 switch (pte & 0x0c) { 5958 case 0x00: 5959 ch = 'D'; /* No cache No buff */ 5960 break; 5961 case 0x04: 5962 ch = 'B'; /* No cache buff */ 5963 break; 5964 case 0x08: 5965 if (pte & 0x40) 5966 ch = 'm'; 5967 else 5968 ch = 'C'; /* Cache No buff */ 5969 break; 5970 case 0x0c: 5971 ch = 'F'; /* Cache Buff */ 5972 break; 5973 } 5974 5975 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 5976 ch += 0x20; 5977 5978 if ((pte & 0xc) == 0) 5979 ncptes[k & 63] = pte; 5980 } 5981 5982 if ((k % 64) == 63) { 5983 rows++; 5984 printf("%c\n", ch); 5985 pmap_dump_ncpg(pm); 5986 if (occ == 0) 5987 break; 5988 } else 5989 printf("%c", ch); 5990 } 5991 } 5992 } 5993 } 5994 5995 static void 5996 pmap_dump_ncpg(pmap_t pm) 5997 { 5998 struct vm_page *pg; 5999 struct pv_entry *pv; 6000 int i; 6001 6002 for (i = 0; i < 63; i++) { 6003 if (ncptes[i] == 0) 6004 continue; 6005 6006 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6007 if (pg == NULL) 6008 continue; 6009 6010 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6011 VM_PAGE_TO_PHYS(pg), 6012 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 6013 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 6014 6015 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 6016 printf(" %c va 0x%08lx, flags 0x%x\n", 6017 (pm == pv->pv_pmap) ? '*' : ' ', 6018 pv->pv_va, pv->pv_flags); 6019 } 6020 } 6021 } 6022 #endif 6023 6024 #ifdef PMAP_STEAL_MEMORY 6025 void 6026 pmap_boot_pageadd(pv_addr_t *newpv) 6027 { 6028 pv_addr_t *pv, *npv; 6029 6030 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6031 if (newpv->pv_pa < pv->pv_va) { 6032 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6033 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6034 newpv->pv_size += pv->pv_size; 6035 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6036 } 6037 pv = NULL; 6038 } else { 6039 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6040 pv = npv) { 6041 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6042 KASSERT(pv->pv_pa < newpv->pv_pa); 6043 if (newpv->pv_pa > npv->pv_pa) 6044 continue; 6045 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6046 pv->pv_size += newpv->pv_size; 6047 return; 6048 } 6049 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6050 break; 6051 newpv->pv_size += npv->pv_size; 6052 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6053 SLIST_REMOVE_AFTER(newpv, pv_list); 6054 return; 6055 } 6056 } 6057 } 6058 6059 if (pv) { 6060 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6061 } else { 6062 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6063 } 6064 } 6065 6066 void 6067 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6068 pv_addr_t *rpv) 6069 { 6070 pv_addr_t *pv, **pvp; 6071 struct vm_physseg *ps; 6072 size_t i; 6073 6074 KASSERT(amount & PGOFSET); 6075 KASSERT((mask & PGOFSET) == 0); 6076 KASSERT((match & PGOFSET) == 0); 6077 KASSERT(amount != 0); 6078 6079 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6080 (pv = *pvp) != NULL; 6081 pvp = &SLIST_NEXT(pv, pv_list)) { 6082 pv_addr_t *newpv; 6083 psize_t off; 6084 /* 6085 * If this entry is too small to satify the request... 6086 */ 6087 KASSERT(pv->pv_size > 0); 6088 if (pv->pv_size < amount) 6089 continue; 6090 6091 for (off = 0; off <= mask; off += PAGE_SIZE) { 6092 if (((pv->pv_pa + off) & mask) == match 6093 && off + amount <= pv->pv_size) 6094 break; 6095 } 6096 if (off > mask) 6097 continue; 6098 6099 rpv->pv_va = pv->pv_va + off; 6100 rpv->pv_pa = pv->pv_pa + off; 6101 rpv->pv_size = amount; 6102 pv->pv_size -= amount; 6103 if (pv->pv_size == 0) { 6104 KASSERT(off == 0); 6105 KASSERT((vaddr_t) pv == rpv->pv_va); 6106 *pvp = SLIST_NEXT(pv, pv_list); 6107 } else if (off == 0) { 6108 KASSERT((vaddr_t) pv == rpv->pv_va); 6109 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6110 *newpv = *pv; 6111 newpv->pv_pa += amount; 6112 newpv->pv_va += amount; 6113 *pvp = newpv; 6114 } else if (off < pv->pv_size) { 6115 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6116 *newpv = *pv; 6117 newpv->pv_size -= off; 6118 newpv->pv_pa += off + amount; 6119 newpv->pv_va += off + amount; 6120 6121 SLIST_NEXT(pv, pv_list) = newpv; 6122 pv->pv_size = off; 6123 } else { 6124 KASSERT((vaddr_t) pv != rpv->pv_va); 6125 } 6126 memset((void *)rpv->pv_va, 0, amount); 6127 return; 6128 } 6129 6130 if (vm_nphysseg == 0) 6131 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6132 6133 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6134 (pv = *pvp) != NULL; 6135 pvp = &SLIST_NEXT(pv, pv_list)) { 6136 if (SLIST_NEXT(pv, pv_list) == NULL) 6137 break; 6138 } 6139 KASSERT(mask == 0); 6140 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6141 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6142 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6143 rpv->pv_va = pv->pv_va; 6144 rpv->pv_pa = pv->pv_pa; 6145 rpv->pv_size = amount; 6146 *pvp = NULL; 6147 pmap_map_chunk(kernel_l1pt.pv_va, 6148 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6149 ptoa(ps->avail_start), 6150 amount - pv->pv_size, 6151 VM_PROT_READ|VM_PROT_WRITE, 6152 PTE_CACHE); 6153 ps->avail_start += atop(amount - pv->pv_size); 6154 /* 6155 * If we consumed the entire physseg, remove it. 6156 */ 6157 if (ps->avail_start == ps->avail_end) { 6158 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6159 ps[0] = ps[1]; 6160 } 6161 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6162 return; 6163 } 6164 } 6165 6166 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6167 } 6168 6169 vaddr_t 6170 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6171 { 6172 pv_addr_t pv; 6173 6174 pmap_boot_pagealloc(size, 0, 0, &pv); 6175 6176 return pv.pv_va; 6177 } 6178 #endif /* PMAP_STEAL_MEMORY */ 6179
Indexes created Thu Oct 23 22:10:10 GMT 2025