pmap.c revision 1.169
1 /* $NetBSD: pmap.c,v 1.169 2007/11/08 11:10:28 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 3. All advertising materials mentioning features or use of this software 82 * must display the following acknowledgement: 83 * This product includes software developed by the NetBSD 84 * Foundation, Inc. and its contributors. 85 * 4. Neither the name of The NetBSD Foundation nor the names of its 86 * contributors may be used to endorse or promote products derived 87 * from this software without specific prior written permission. 88 * 89 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 90 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 91 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 92 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 93 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 94 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 95 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 96 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 97 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 98 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 99 * POSSIBILITY OF SUCH DAMAGE. 100 */ 101 102 /* 103 * Copyright (c) 1994-1998 Mark Brinicombe. 104 * Copyright (c) 1994 Brini. 105 * All rights reserved. 106 * 107 * This code is derived from software written for Brini by Mark Brinicombe 108 * 109 * Redistribution and use in source and binary forms, with or without 110 * modification, are permitted provided that the following conditions 111 * are met: 112 * 1. Redistributions of source code must retain the above copyright 113 * notice, this list of conditions and the following disclaimer. 114 * 2. Redistributions in binary form must reproduce the above copyright 115 * notice, this list of conditions and the following disclaimer in the 116 * documentation and/or other materials provided with the distribution. 117 * 3. All advertising materials mentioning features or use of this software 118 * must display the following acknowledgement: 119 * This product includes software developed by Mark Brinicombe. 120 * 4. The name of the author may not be used to endorse or promote products 121 * derived from this software without specific prior written permission. 122 * 123 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 124 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 125 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 126 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 127 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 128 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 129 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 130 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 131 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 132 * 133 * RiscBSD kernel project 134 * 135 * pmap.c 136 * 137 * Machine dependant vm stuff 138 * 139 * Created : 20/09/94 140 */ 141 142 /* 143 * Performance improvements, UVM changes, overhauls and part-rewrites 144 * were contributed by Neil A. Carson <neil (at) causality.com>. 145 */ 146 147 /* 148 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 149 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 150 * Systems, Inc. 151 * 152 * There are still a few things outstanding at this time: 153 * 154 * - There are some unresolved issues for MP systems: 155 * 156 * o The L1 metadata needs a lock, or more specifically, some places 157 * need to acquire an exclusive lock when modifying L1 translation 158 * table entries. 159 * 160 * o When one cpu modifies an L1 entry, and that L1 table is also 161 * being used by another cpu, then the latter will need to be told 162 * that a tlb invalidation may be necessary. (But only if the old 163 * domain number in the L1 entry being over-written is currently 164 * the active domain on that cpu). I guess there are lots more tlb 165 * shootdown issues too... 166 * 167 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 168 * MP systems will lose big-time because of the MMU domain hack. 169 * The only way this can be solved (apart from moving the vector 170 * page to 0xffff0000) is to reserve the first 1MB of user address 171 * space for kernel use only. This would require re-linking all 172 * applications so that the text section starts above this 1MB 173 * boundary. 174 * 175 * o Tracking which VM space is resident in the cache/tlb has not yet 176 * been implemented for MP systems. 177 * 178 * o Finally, there is a pathological condition where two cpus running 179 * two separate processes (not lwps) which happen to share an L1 180 * can get into a fight over one or more L1 entries. This will result 181 * in a significant slow-down if both processes are in tight loops. 182 */ 183 184 /* 185 * Special compilation symbols 186 * PMAP_DEBUG - Build in pmap_debug_level code 187 */ 188 189 /* Include header files */ 190 191 #include "opt_cpuoptions.h" 192 #include "opt_pmap_debug.h" 193 #include "opt_ddb.h" 194 #include "opt_lockdebug.h" 195 #include "opt_multiprocessor.h" 196 197 #include <sys/types.h> 198 #include <sys/param.h> 199 #include <sys/kernel.h> 200 #include <sys/systm.h> 201 #include <sys/proc.h> 202 #include <sys/malloc.h> 203 #include <sys/user.h> 204 #include <sys/pool.h> 205 #include <sys/cdefs.h> 206 207 #include <uvm/uvm.h> 208 209 #include <machine/bus.h> 210 #include <machine/pmap.h> 211 #include <machine/pcb.h> 212 #include <machine/param.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.169 2007/11/08 11:10:28 matt Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 struct pmap kernel_pmap_store; 258 259 /* 260 * Which pmap is currently 'live' in the cache 261 * 262 * XXXSCW: Fix for SMP ... 263 */ 264 static pmap_t pmap_recent_user; 265 266 /* 267 * Pool and cache that pmap structures are allocated from. 268 * We use a cache to avoid clearing the pm_l2[] array (1KB) 269 * in pmap_create(). 270 */ 271 static struct pool_cache pmap_cache; 272 static LIST_HEAD(, pmap) pmap_pmaps; 273 274 /* 275 * Pool of PV structures 276 */ 277 static struct pool pmap_pv_pool; 278 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 279 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 280 static struct pool_allocator pmap_bootstrap_pv_allocator = { 281 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 282 }; 283 284 /* 285 * Pool and cache of l2_dtable structures. 286 * We use a cache to avoid clearing the structures when they're 287 * allocated. (196 bytes) 288 */ 289 static struct pool_cache pmap_l2dtable_cache; 290 static vaddr_t pmap_kernel_l2dtable_kva; 291 292 /* 293 * Pool and cache of L2 page descriptors. 294 * We use a cache to avoid clearing the descriptor table 295 * when they're allocated. (1KB) 296 */ 297 static struct pool_cache pmap_l2ptp_cache; 298 static vaddr_t pmap_kernel_l2ptp_kva; 299 static paddr_t pmap_kernel_l2ptp_phys; 300 301 /* 302 * pmap copy/zero page, and mem(5) hook point 303 */ 304 static pt_entry_t *csrc_pte, *cdst_pte; 305 static vaddr_t csrcp, cdstp; 306 char *memhook; 307 extern void *msgbufaddr; 308 309 /* 310 * Flag to indicate if pmap_init() has done its thing 311 */ 312 bool pmap_initialized; 313 314 /* 315 * Misc. locking data structures 316 */ 317 318 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 319 static struct lock pmap_main_lock; 320 321 #define PMAP_MAP_TO_HEAD_LOCK() \ 322 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 323 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 324 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 325 #define PMAP_HEAD_TO_MAP_LOCK() \ 326 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 327 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 328 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 329 #else 330 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 331 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 332 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 333 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 334 #endif 335 336 #define pmap_acquire_pmap_lock(pm) \ 337 do { \ 338 if ((pm) != pmap_kernel()) \ 339 simple_lock(&(pm)->pm_lock); \ 340 } while (/*CONSTCOND*/0) 341 342 #define pmap_release_pmap_lock(pm) \ 343 do { \ 344 if ((pm) != pmap_kernel()) \ 345 simple_unlock(&(pm)->pm_lock); \ 346 } while (/*CONSTCOND*/0) 347 348 349 /* 350 * Metadata for L1 translation tables. 351 */ 352 struct l1_ttable { 353 /* Entry on the L1 Table list */ 354 SLIST_ENTRY(l1_ttable) l1_link; 355 356 /* Entry on the L1 Least Recently Used list */ 357 TAILQ_ENTRY(l1_ttable) l1_lru; 358 359 /* Track how many domains are allocated from this L1 */ 360 volatile u_int l1_domain_use_count; 361 362 /* 363 * A free-list of domain numbers for this L1. 364 * We avoid using ffs() and a bitmap to track domains since ffs() 365 * is slow on ARM. 366 */ 367 u_int8_t l1_domain_first; 368 u_int8_t l1_domain_free[PMAP_DOMAINS]; 369 370 /* Physical address of this L1 page table */ 371 paddr_t l1_physaddr; 372 373 /* KVA of this L1 page table */ 374 pd_entry_t *l1_kva; 375 }; 376 377 /* 378 * Convert a virtual address into its L1 table index. That is, the 379 * index used to locate the L2 descriptor table pointer in an L1 table. 380 * This is basically used to index l1->l1_kva[]. 381 * 382 * Each L2 descriptor table represents 1MB of VA space. 383 */ 384 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 385 386 /* 387 * L1 Page Tables are tracked using a Least Recently Used list. 388 * - New L1s are allocated from the HEAD. 389 * - Freed L1s are added to the TAIl. 390 * - Recently accessed L1s (where an 'access' is some change to one of 391 * the userland pmaps which owns this L1) are moved to the TAIL. 392 */ 393 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 394 static struct simplelock l1_lru_lock; 395 396 /* 397 * A list of all L1 tables 398 */ 399 static SLIST_HEAD(, l1_ttable) l1_list; 400 401 /* 402 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 403 * 404 * This is normally 16MB worth L2 page descriptors for any given pmap. 405 * Reference counts are maintained for L2 descriptors so they can be 406 * freed when empty. 407 */ 408 struct l2_dtable { 409 /* The number of L2 page descriptors allocated to this l2_dtable */ 410 u_int l2_occupancy; 411 412 /* List of L2 page descriptors */ 413 struct l2_bucket { 414 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 415 paddr_t l2b_phys; /* Physical address of same */ 416 u_short l2b_l1idx; /* This L2 table's L1 index */ 417 u_short l2b_occupancy; /* How many active descriptors */ 418 } l2_bucket[L2_BUCKET_SIZE]; 419 }; 420 421 /* 422 * Given an L1 table index, calculate the corresponding l2_dtable index 423 * and bucket index within the l2_dtable. 424 */ 425 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 426 (L2_SIZE - 1)) 427 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 428 429 /* 430 * Given a virtual address, this macro returns the 431 * virtual address required to drop into the next L2 bucket. 432 */ 433 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 434 435 /* 436 * L2 allocation. 437 */ 438 #define pmap_alloc_l2_dtable() \ 439 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 440 #define pmap_free_l2_dtable(l2) \ 441 pool_cache_put(&pmap_l2dtable_cache, (l2)) 442 #define pmap_alloc_l2_ptp(pap) \ 443 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 444 PR_NOWAIT, (pap))) 445 446 /* 447 * We try to map the page tables write-through, if possible. However, not 448 * all CPUs have a write-through cache mode, so on those we have to sync 449 * the cache when we frob page tables. 450 * 451 * We try to evaluate this at compile time, if possible. However, it's 452 * not always possible to do that, hence this run-time var. 453 */ 454 int pmap_needs_pte_sync; 455 456 /* 457 * Real definition of pv_entry. 458 */ 459 struct pv_entry { 460 struct pv_entry *pv_next; /* next pv_entry */ 461 pmap_t pv_pmap; /* pmap where mapping lies */ 462 vaddr_t pv_va; /* virtual address for mapping */ 463 u_int pv_flags; /* flags */ 464 }; 465 466 /* 467 * Macro to determine if a mapping might be resident in the 468 * instruction cache and/or TLB 469 */ 470 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 471 472 /* 473 * Macro to determine if a mapping might be resident in the 474 * data cache and/or TLB 475 */ 476 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 477 478 /* 479 * Local prototypes 480 */ 481 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 482 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 483 pt_entry_t **); 484 static bool pmap_is_current(pmap_t); 485 static bool pmap_is_cached(pmap_t); 486 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 487 pmap_t, vaddr_t, u_int); 488 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 489 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 490 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 491 u_int, u_int); 492 493 static void pmap_pinit(pmap_t); 494 static int pmap_pmap_ctor(void *, void *, int); 495 496 static void pmap_alloc_l1(pmap_t); 497 static void pmap_free_l1(pmap_t); 498 static void pmap_use_l1(pmap_t); 499 500 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 501 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 502 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 503 static int pmap_l2ptp_ctor(void *, void *, int); 504 static int pmap_l2dtable_ctor(void *, void *, int); 505 506 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 507 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 508 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 509 510 static void pmap_clearbit(struct vm_page *, u_int); 511 static int pmap_clean_page(struct pv_entry *, bool); 512 static void pmap_page_remove(struct vm_page *); 513 514 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 515 static vaddr_t kernel_pt_lookup(paddr_t); 516 517 void pmap_switch(struct lwp *, struct lwp *); 518 519 520 /* 521 * External function prototypes 522 */ 523 extern void bzero_page(vaddr_t); 524 extern void bcopy_page(vaddr_t, vaddr_t); 525 526 /* 527 * Misc variables 528 */ 529 vaddr_t virtual_avail; 530 vaddr_t virtual_end; 531 vaddr_t pmap_curmaxkvaddr; 532 533 vaddr_t avail_start; 534 vaddr_t avail_end; 535 536 extern pv_addr_t systempage; 537 538 /* Function to set the debug level of the pmap code */ 539 540 #ifdef PMAP_DEBUG 541 void 542 pmap_debug(int level) 543 { 544 pmap_debug_level = level; 545 printf("pmap_debug: level=%d\n", pmap_debug_level); 546 } 547 #endif /* PMAP_DEBUG */ 548 549 /* 550 * A bunch of routines to conditionally flush the caches/TLB depending 551 * on whether the specified pmap actually needs to be flushed at any 552 * given time. 553 */ 554 static inline void 555 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 556 { 557 558 if (pm->pm_cstate.cs_tlb_id) 559 cpu_tlb_flushID_SE(va); 560 } 561 562 static inline void 563 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 564 { 565 566 if (pm->pm_cstate.cs_tlb_d) 567 cpu_tlb_flushD_SE(va); 568 } 569 570 static inline void 571 pmap_tlb_flushID(pmap_t pm) 572 { 573 574 if (pm->pm_cstate.cs_tlb_id) { 575 cpu_tlb_flushID(); 576 pm->pm_cstate.cs_tlb = 0; 577 } 578 } 579 580 static inline void 581 pmap_tlb_flushD(pmap_t pm) 582 { 583 584 if (pm->pm_cstate.cs_tlb_d) { 585 cpu_tlb_flushD(); 586 pm->pm_cstate.cs_tlb_d = 0; 587 } 588 } 589 590 static inline void 591 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 592 { 593 594 if (pm->pm_cstate.cs_cache_id) 595 cpu_idcache_wbinv_range(va, len); 596 } 597 598 static inline void 599 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 600 bool do_inv, bool rd_only) 601 { 602 603 if (pm->pm_cstate.cs_cache_d) { 604 if (do_inv) { 605 if (rd_only) 606 cpu_dcache_inv_range(va, len); 607 else 608 cpu_dcache_wbinv_range(va, len); 609 } else 610 if (!rd_only) 611 cpu_dcache_wb_range(va, len); 612 } 613 } 614 615 static inline void 616 pmap_idcache_wbinv_all(pmap_t pm) 617 { 618 619 if (pm->pm_cstate.cs_cache_id) { 620 cpu_idcache_wbinv_all(); 621 pm->pm_cstate.cs_cache = 0; 622 } 623 } 624 625 static inline void 626 pmap_dcache_wbinv_all(pmap_t pm) 627 { 628 629 if (pm->pm_cstate.cs_cache_d) { 630 cpu_dcache_wbinv_all(); 631 pm->pm_cstate.cs_cache_d = 0; 632 } 633 } 634 635 static inline bool 636 pmap_is_current(pmap_t pm) 637 { 638 639 if (pm == pmap_kernel() || 640 (curproc && curproc->p_vmspace->vm_map.pmap == pm)) 641 return (true); 642 643 return (false); 644 } 645 646 static inline bool 647 pmap_is_cached(pmap_t pm) 648 { 649 650 if (pm == pmap_kernel() || pmap_recent_user == NULL || 651 pmap_recent_user == pm) 652 return (true); 653 654 return (false); 655 } 656 657 /* 658 * PTE_SYNC_CURRENT: 659 * 660 * Make sure the pte is written out to RAM. 661 * We need to do this for one of two cases: 662 * - We're dealing with the kernel pmap 663 * - There is no pmap active in the cache/tlb. 664 * - The specified pmap is 'active' in the cache/tlb. 665 */ 666 #ifdef PMAP_INCLUDE_PTE_SYNC 667 #define PTE_SYNC_CURRENT(pm, ptep) \ 668 do { \ 669 if (PMAP_NEEDS_PTE_SYNC && \ 670 pmap_is_cached(pm)) \ 671 PTE_SYNC(ptep); \ 672 } while (/*CONSTCOND*/0) 673 #else 674 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 675 #endif 676 677 /* 678 * main pv_entry manipulation functions: 679 * pmap_enter_pv: enter a mapping onto a vm_page list 680 * pmap_remove_pv: remove a mappiing from a vm_page list 681 * 682 * NOTE: pmap_enter_pv expects to lock the pvh itself 683 * pmap_remove_pv expects te caller to lock the pvh before calling 684 */ 685 686 /* 687 * pmap_enter_pv: enter a mapping onto a vm_page lst 688 * 689 * => caller should hold the proper lock on pmap_main_lock 690 * => caller should have pmap locked 691 * => we will gain the lock on the vm_page and allocate the new pv_entry 692 * => caller should adjust ptp's wire_count before calling 693 * => caller should not adjust pmap's wire_count 694 */ 695 static void 696 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 697 vaddr_t va, u_int flags) 698 { 699 700 NPDEBUG(PDB_PVDUMP, 701 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 702 703 pve->pv_pmap = pm; 704 pve->pv_va = va; 705 pve->pv_flags = flags; 706 707 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 708 pve->pv_next = pg->mdpage.pvh_list; /* add to ... */ 709 pg->mdpage.pvh_list = pve; /* ... locked list */ 710 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 711 if (pm == pmap_kernel()) { 712 if (flags & PVF_WRITE) 713 pg->mdpage.krw_mappings++; 714 else 715 pg->mdpage.kro_mappings++; 716 } else 717 if (flags & PVF_WRITE) 718 pg->mdpage.urw_mappings++; 719 else 720 pg->mdpage.uro_mappings++; 721 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 722 723 if (pve->pv_flags & PVF_WIRED) 724 ++pm->pm_stats.wired_count; 725 } 726 727 /* 728 * 729 * pmap_find_pv: Find a pv entry 730 * 731 * => caller should hold lock on vm_page 732 */ 733 static inline struct pv_entry * 734 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 735 { 736 struct pv_entry *pv; 737 738 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 739 if (pm == pv->pv_pmap && va == pv->pv_va) 740 break; 741 } 742 743 return (pv); 744 } 745 746 /* 747 * pmap_remove_pv: try to remove a mapping from a pv_list 748 * 749 * => caller should hold proper lock on pmap_main_lock 750 * => pmap should be locked 751 * => caller should hold lock on vm_page [so that attrs can be adjusted] 752 * => caller should adjust ptp's wire_count and free PTP if needed 753 * => caller should NOT adjust pmap's wire_count 754 * => we return the removed pve 755 */ 756 static struct pv_entry * 757 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 758 { 759 struct pv_entry *pve, **prevptr; 760 761 NPDEBUG(PDB_PVDUMP, 762 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 763 764 prevptr = &pg->mdpage.pvh_list; /* previous pv_entry pointer */ 765 pve = *prevptr; 766 767 while (pve) { 768 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 769 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 770 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 771 if (pve->pv_flags & PVF_WIRED) { 772 if (skip_wired) 773 return (NULL); 774 --pm->pm_stats.wired_count; 775 } 776 *prevptr = pve->pv_next; /* remove it! */ 777 if (pm == pmap_kernel()) { 778 if (pve->pv_flags & PVF_WRITE) 779 pg->mdpage.krw_mappings--; 780 else 781 pg->mdpage.kro_mappings--; 782 } else 783 if (pve->pv_flags & PVF_WRITE) 784 pg->mdpage.urw_mappings--; 785 else 786 pg->mdpage.uro_mappings--; 787 break; 788 } 789 prevptr = &pve->pv_next; /* previous pointer */ 790 pve = pve->pv_next; /* advance */ 791 } 792 793 return(pve); /* return removed pve */ 794 } 795 796 /* 797 * 798 * pmap_modify_pv: Update pv flags 799 * 800 * => caller should hold lock on vm_page [so that attrs can be adjusted] 801 * => caller should NOT adjust pmap's wire_count 802 * => caller must call pmap_vac_me_harder() if writable status of a page 803 * may have changed. 804 * => we return the old flags 805 * 806 * Modify a physical-virtual mapping in the pv table 807 */ 808 static u_int 809 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 810 u_int clr_mask, u_int set_mask) 811 { 812 struct pv_entry *npv; 813 u_int flags, oflags; 814 815 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 816 return (0); 817 818 NPDEBUG(PDB_PVDUMP, 819 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 820 821 /* 822 * There is at least one VA mapping this page. 823 */ 824 825 if (clr_mask & (PVF_REF | PVF_MOD)) 826 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 827 828 oflags = npv->pv_flags; 829 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 830 831 if ((flags ^ oflags) & PVF_WIRED) { 832 if (flags & PVF_WIRED) 833 ++pm->pm_stats.wired_count; 834 else 835 --pm->pm_stats.wired_count; 836 } 837 838 if ((flags ^ oflags) & PVF_WRITE) { 839 if (pm == pmap_kernel()) { 840 if (flags & PVF_WRITE) { 841 pg->mdpage.krw_mappings++; 842 pg->mdpage.kro_mappings--; 843 } else { 844 pg->mdpage.kro_mappings++; 845 pg->mdpage.krw_mappings--; 846 } 847 } else 848 if (flags & PVF_WRITE) { 849 pg->mdpage.urw_mappings++; 850 pg->mdpage.uro_mappings--; 851 } else { 852 pg->mdpage.uro_mappings++; 853 pg->mdpage.urw_mappings--; 854 } 855 } 856 857 return (oflags); 858 } 859 860 /* 861 * Allocate an L1 translation table for the specified pmap. 862 * This is called at pmap creation time. 863 */ 864 static void 865 pmap_alloc_l1(pmap_t pm) 866 { 867 struct l1_ttable *l1; 868 u_int8_t domain; 869 870 /* 871 * Remove the L1 at the head of the LRU list 872 */ 873 simple_lock(&l1_lru_lock); 874 l1 = TAILQ_FIRST(&l1_lru_list); 875 KDASSERT(l1 != NULL); 876 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 877 878 /* 879 * Pick the first available domain number, and update 880 * the link to the next number. 881 */ 882 domain = l1->l1_domain_first; 883 l1->l1_domain_first = l1->l1_domain_free[domain]; 884 885 /* 886 * If there are still free domain numbers in this L1, 887 * put it back on the TAIL of the LRU list. 888 */ 889 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 890 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 891 892 simple_unlock(&l1_lru_lock); 893 894 /* 895 * Fix up the relevant bits in the pmap structure 896 */ 897 pm->pm_l1 = l1; 898 pm->pm_domain = domain; 899 } 900 901 /* 902 * Free an L1 translation table. 903 * This is called at pmap destruction time. 904 */ 905 static void 906 pmap_free_l1(pmap_t pm) 907 { 908 struct l1_ttable *l1 = pm->pm_l1; 909 910 simple_lock(&l1_lru_lock); 911 912 /* 913 * If this L1 is currently on the LRU list, remove it. 914 */ 915 if (l1->l1_domain_use_count < PMAP_DOMAINS) 916 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 917 918 /* 919 * Free up the domain number which was allocated to the pmap 920 */ 921 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 922 l1->l1_domain_first = pm->pm_domain; 923 l1->l1_domain_use_count--; 924 925 /* 926 * The L1 now must have at least 1 free domain, so add 927 * it back to the LRU list. If the use count is zero, 928 * put it at the head of the list, otherwise it goes 929 * to the tail. 930 */ 931 if (l1->l1_domain_use_count == 0) 932 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 933 else 934 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 935 936 simple_unlock(&l1_lru_lock); 937 } 938 939 static inline void 940 pmap_use_l1(pmap_t pm) 941 { 942 struct l1_ttable *l1; 943 944 /* 945 * Do nothing if we're in interrupt context. 946 * Access to an L1 by the kernel pmap must not affect 947 * the LRU list. 948 */ 949 if (current_intr_depth || pm == pmap_kernel()) 950 return; 951 952 l1 = pm->pm_l1; 953 954 /* 955 * If the L1 is not currently on the LRU list, just return 956 */ 957 if (l1->l1_domain_use_count == PMAP_DOMAINS) 958 return; 959 960 simple_lock(&l1_lru_lock); 961 962 /* 963 * Check the use count again, now that we've acquired the lock 964 */ 965 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 966 simple_unlock(&l1_lru_lock); 967 return; 968 } 969 970 /* 971 * Move the L1 to the back of the LRU list 972 */ 973 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 974 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 975 976 simple_unlock(&l1_lru_lock); 977 } 978 979 /* 980 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 981 * 982 * Free an L2 descriptor table. 983 */ 984 static inline void 985 #ifndef PMAP_INCLUDE_PTE_SYNC 986 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 987 #else 988 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 989 #endif 990 { 991 #ifdef PMAP_INCLUDE_PTE_SYNC 992 /* 993 * Note: With a write-back cache, we may need to sync this 994 * L2 table before re-using it. 995 * This is because it may have belonged to a non-current 996 * pmap, in which case the cache syncs would have been 997 * skipped when the pages were being unmapped. If the 998 * L2 table were then to be immediately re-allocated to 999 * the *current* pmap, it may well contain stale mappings 1000 * which have not yet been cleared by a cache write-back 1001 * and so would still be visible to the mmu. 1002 */ 1003 if (need_sync) 1004 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1005 #endif 1006 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1007 } 1008 1009 /* 1010 * Returns a pointer to the L2 bucket associated with the specified pmap 1011 * and VA, or NULL if no L2 bucket exists for the address. 1012 */ 1013 static inline struct l2_bucket * 1014 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1015 { 1016 struct l2_dtable *l2; 1017 struct l2_bucket *l2b; 1018 u_short l1idx; 1019 1020 l1idx = L1_IDX(va); 1021 1022 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1023 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1024 return (NULL); 1025 1026 return (l2b); 1027 } 1028 1029 /* 1030 * Returns a pointer to the L2 bucket associated with the specified pmap 1031 * and VA. 1032 * 1033 * If no L2 bucket exists, perform the necessary allocations to put an L2 1034 * bucket/page table in place. 1035 * 1036 * Note that if a new L2 bucket/page was allocated, the caller *must* 1037 * increment the bucket occupancy counter appropriately *before* 1038 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1039 * the bucket/page in the meantime. 1040 */ 1041 static struct l2_bucket * 1042 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1043 { 1044 struct l2_dtable *l2; 1045 struct l2_bucket *l2b; 1046 u_short l1idx; 1047 1048 l1idx = L1_IDX(va); 1049 1050 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1051 /* 1052 * No mapping at this address, as there is 1053 * no entry in the L1 table. 1054 * Need to allocate a new l2_dtable. 1055 */ 1056 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1057 return (NULL); 1058 1059 /* 1060 * Link it into the parent pmap 1061 */ 1062 pm->pm_l2[L2_IDX(l1idx)] = l2; 1063 } 1064 1065 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1066 1067 /* 1068 * Fetch pointer to the L2 page table associated with the address. 1069 */ 1070 if (l2b->l2b_kva == NULL) { 1071 pt_entry_t *ptep; 1072 1073 /* 1074 * No L2 page table has been allocated. Chances are, this 1075 * is because we just allocated the l2_dtable, above. 1076 */ 1077 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1078 /* 1079 * Oops, no more L2 page tables available at this 1080 * time. We may need to deallocate the l2_dtable 1081 * if we allocated a new one above. 1082 */ 1083 if (l2->l2_occupancy == 0) { 1084 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1085 pmap_free_l2_dtable(l2); 1086 } 1087 return (NULL); 1088 } 1089 1090 l2->l2_occupancy++; 1091 l2b->l2b_kva = ptep; 1092 l2b->l2b_l1idx = l1idx; 1093 } 1094 1095 return (l2b); 1096 } 1097 1098 /* 1099 * One or more mappings in the specified L2 descriptor table have just been 1100 * invalidated. 1101 * 1102 * Garbage collect the metadata and descriptor table itself if necessary. 1103 * 1104 * The pmap lock must be acquired when this is called (not necessary 1105 * for the kernel pmap). 1106 */ 1107 static void 1108 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1109 { 1110 struct l2_dtable *l2; 1111 pd_entry_t *pl1pd, l1pd; 1112 pt_entry_t *ptep; 1113 u_short l1idx; 1114 1115 KDASSERT(count <= l2b->l2b_occupancy); 1116 1117 /* 1118 * Update the bucket's reference count according to how many 1119 * PTEs the caller has just invalidated. 1120 */ 1121 l2b->l2b_occupancy -= count; 1122 1123 /* 1124 * Note: 1125 * 1126 * Level 2 page tables allocated to the kernel pmap are never freed 1127 * as that would require checking all Level 1 page tables and 1128 * removing any references to the Level 2 page table. See also the 1129 * comment elsewhere about never freeing bootstrap L2 descriptors. 1130 * 1131 * We make do with just invalidating the mapping in the L2 table. 1132 * 1133 * This isn't really a big deal in practice and, in fact, leads 1134 * to a performance win over time as we don't need to continually 1135 * alloc/free. 1136 */ 1137 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1138 return; 1139 1140 /* 1141 * There are no more valid mappings in this level 2 page table. 1142 * Go ahead and NULL-out the pointer in the bucket, then 1143 * free the page table. 1144 */ 1145 l1idx = l2b->l2b_l1idx; 1146 ptep = l2b->l2b_kva; 1147 l2b->l2b_kva = NULL; 1148 1149 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1150 1151 /* 1152 * If the L1 slot matches the pmap's domain 1153 * number, then invalidate it. 1154 */ 1155 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1156 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1157 *pl1pd = 0; 1158 PTE_SYNC(pl1pd); 1159 } 1160 1161 /* 1162 * Release the L2 descriptor table back to the pool cache. 1163 */ 1164 #ifndef PMAP_INCLUDE_PTE_SYNC 1165 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1166 #else 1167 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1168 #endif 1169 1170 /* 1171 * Update the reference count in the associated l2_dtable 1172 */ 1173 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1174 if (--l2->l2_occupancy > 0) 1175 return; 1176 1177 /* 1178 * There are no more valid mappings in any of the Level 1 1179 * slots managed by this l2_dtable. Go ahead and NULL-out 1180 * the pointer in the parent pmap and free the l2_dtable. 1181 */ 1182 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1183 pmap_free_l2_dtable(l2); 1184 } 1185 1186 /* 1187 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1188 * structures. 1189 */ 1190 static int 1191 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1192 { 1193 #ifndef PMAP_INCLUDE_PTE_SYNC 1194 struct l2_bucket *l2b; 1195 pt_entry_t *ptep, pte; 1196 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1197 1198 /* 1199 * The mappings for these page tables were initially made using 1200 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1201 * mode will not be right for page table mappings. To avoid 1202 * polluting the pmap_kenter_pa() code with a special case for 1203 * page tables, we simply fix up the cache-mode here if it's not 1204 * correct. 1205 */ 1206 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1207 KDASSERT(l2b != NULL); 1208 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1209 pte = *ptep; 1210 1211 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1212 /* 1213 * Page tables must have the cache-mode set to Write-Thru. 1214 */ 1215 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1216 PTE_SYNC(ptep); 1217 cpu_tlb_flushD_SE(va); 1218 cpu_cpwait(); 1219 } 1220 #endif 1221 1222 memset(v, 0, L2_TABLE_SIZE_REAL); 1223 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1224 return (0); 1225 } 1226 1227 static int 1228 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1229 { 1230 1231 memset(v, 0, sizeof(struct l2_dtable)); 1232 return (0); 1233 } 1234 1235 static int 1236 pmap_pmap_ctor(void *arg, void *v, int flags) 1237 { 1238 1239 memset(v, 0, sizeof(struct pmap)); 1240 return (0); 1241 } 1242 1243 static void 1244 pmap_pinit(pmap_t pm) 1245 { 1246 struct l2_bucket *l2b; 1247 1248 if (vector_page < KERNEL_BASE) { 1249 /* 1250 * Map the vector page. 1251 */ 1252 pmap_enter(pm, vector_page, systempage.pv_pa, 1253 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1254 pmap_update(pm); 1255 1256 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1257 l2b = pmap_get_l2_bucket(pm, vector_page); 1258 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1259 L1_C_DOM(pm->pm_domain); 1260 } else 1261 pm->pm_pl1vec = NULL; 1262 } 1263 1264 /* 1265 * Since we have a virtually indexed cache, we may need to inhibit caching if 1266 * there is more than one mapping and at least one of them is writable. 1267 * Since we purge the cache on every context switch, we only need to check for 1268 * other mappings within the same pmap, or kernel_pmap. 1269 * This function is also called when a page is unmapped, to possibly reenable 1270 * caching on any remaining mappings. 1271 * 1272 * The code implements the following logic, where: 1273 * 1274 * KW = # of kernel read/write pages 1275 * KR = # of kernel read only pages 1276 * UW = # of user read/write pages 1277 * UR = # of user read only pages 1278 * 1279 * KC = kernel mapping is cacheable 1280 * UC = user mapping is cacheable 1281 * 1282 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1283 * +--------------------------------------------- 1284 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1285 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1286 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1287 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1288 */ 1289 1290 static const int pmap_vac_flags[4][4] = { 1291 {-1, 0, 0, PVF_KNC}, 1292 {0, 0, PVF_NC, PVF_NC}, 1293 {0, PVF_NC, PVF_NC, PVF_NC}, 1294 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1295 }; 1296 1297 static inline int 1298 pmap_get_vac_flags(const struct vm_page *pg) 1299 { 1300 int kidx, uidx; 1301 1302 kidx = 0; 1303 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1304 kidx |= 1; 1305 if (pg->mdpage.krw_mappings) 1306 kidx |= 2; 1307 1308 uidx = 0; 1309 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1310 uidx |= 1; 1311 if (pg->mdpage.urw_mappings) 1312 uidx |= 2; 1313 1314 return (pmap_vac_flags[uidx][kidx]); 1315 } 1316 1317 static inline void 1318 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1319 { 1320 int nattr; 1321 1322 nattr = pmap_get_vac_flags(pg); 1323 1324 if (nattr < 0) { 1325 pg->mdpage.pvh_attrs &= ~PVF_NC; 1326 return; 1327 } 1328 1329 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1330 return; 1331 1332 if (pm == pmap_kernel()) 1333 pmap_vac_me_kpmap(pg, pm, va); 1334 else 1335 pmap_vac_me_user(pg, pm, va); 1336 1337 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1338 } 1339 1340 static void 1341 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1342 { 1343 u_int u_cacheable, u_entries; 1344 struct pv_entry *pv; 1345 pmap_t last_pmap = pm; 1346 1347 /* 1348 * Pass one, see if there are both kernel and user pmaps for 1349 * this page. Calculate whether there are user-writable or 1350 * kernel-writable pages. 1351 */ 1352 u_cacheable = 0; 1353 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1354 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1355 u_cacheable++; 1356 } 1357 1358 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1359 1360 /* 1361 * We know we have just been updating a kernel entry, so if 1362 * all user pages are already cacheable, then there is nothing 1363 * further to do. 1364 */ 1365 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1366 return; 1367 1368 if (u_entries) { 1369 /* 1370 * Scan over the list again, for each entry, if it 1371 * might not be set correctly, call pmap_vac_me_user 1372 * to recalculate the settings. 1373 */ 1374 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1375 /* 1376 * We know kernel mappings will get set 1377 * correctly in other calls. We also know 1378 * that if the pmap is the same as last_pmap 1379 * then we've just handled this entry. 1380 */ 1381 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1382 continue; 1383 1384 /* 1385 * If there are kernel entries and this page 1386 * is writable but non-cacheable, then we can 1387 * skip this entry also. 1388 */ 1389 if (pg->mdpage.k_mappings && 1390 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1391 (PVF_NC | PVF_WRITE)) 1392 continue; 1393 1394 /* 1395 * Similarly if there are no kernel-writable 1396 * entries and the page is already 1397 * read-only/cacheable. 1398 */ 1399 if (pg->mdpage.krw_mappings == 0 && 1400 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1401 continue; 1402 1403 /* 1404 * For some of the remaining cases, we know 1405 * that we must recalculate, but for others we 1406 * can't tell if they are correct or not, so 1407 * we recalculate anyway. 1408 */ 1409 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1410 } 1411 1412 if (pg->mdpage.k_mappings == 0) 1413 return; 1414 } 1415 1416 pmap_vac_me_user(pg, pm, va); 1417 } 1418 1419 static void 1420 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1421 { 1422 pmap_t kpmap = pmap_kernel(); 1423 struct pv_entry *pv, *npv; 1424 struct l2_bucket *l2b; 1425 pt_entry_t *ptep, pte; 1426 u_int entries = 0; 1427 u_int writable = 0; 1428 u_int cacheable_entries = 0; 1429 u_int kern_cacheable = 0; 1430 u_int other_writable = 0; 1431 1432 /* 1433 * Count mappings and writable mappings in this pmap. 1434 * Include kernel mappings as part of our own. 1435 * Keep a pointer to the first one. 1436 */ 1437 for (pv = npv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1438 /* Count mappings in the same pmap */ 1439 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1440 if (entries++ == 0) 1441 npv = pv; 1442 1443 /* Cacheable mappings */ 1444 if ((pv->pv_flags & PVF_NC) == 0) { 1445 cacheable_entries++; 1446 if (kpmap == pv->pv_pmap) 1447 kern_cacheable++; 1448 } 1449 1450 /* Writable mappings */ 1451 if (pv->pv_flags & PVF_WRITE) 1452 ++writable; 1453 } else 1454 if (pv->pv_flags & PVF_WRITE) 1455 other_writable = 1; 1456 } 1457 1458 /* 1459 * Enable or disable caching as necessary. 1460 * Note: the first entry might be part of the kernel pmap, 1461 * so we can't assume this is indicative of the state of the 1462 * other (maybe non-kpmap) entries. 1463 */ 1464 if ((entries > 1 && writable) || 1465 (entries > 0 && pm == kpmap && other_writable)) { 1466 if (cacheable_entries == 0) 1467 return; 1468 1469 for (pv = npv; pv; pv = pv->pv_next) { 1470 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1471 (pv->pv_flags & PVF_NC)) 1472 continue; 1473 1474 pv->pv_flags |= PVF_NC; 1475 1476 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1477 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1478 pte = *ptep & ~L2_S_CACHE_MASK; 1479 1480 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1481 l2pte_valid(pte)) { 1482 if (PV_BEEN_EXECD(pv->pv_flags)) { 1483 pmap_idcache_wbinv_range(pv->pv_pmap, 1484 pv->pv_va, PAGE_SIZE); 1485 pmap_tlb_flushID_SE(pv->pv_pmap, 1486 pv->pv_va); 1487 } else 1488 if (PV_BEEN_REFD(pv->pv_flags)) { 1489 pmap_dcache_wb_range(pv->pv_pmap, 1490 pv->pv_va, PAGE_SIZE, true, 1491 (pv->pv_flags & PVF_WRITE) == 0); 1492 pmap_tlb_flushD_SE(pv->pv_pmap, 1493 pv->pv_va); 1494 } 1495 } 1496 1497 *ptep = pte; 1498 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1499 } 1500 cpu_cpwait(); 1501 } else 1502 if (entries > cacheable_entries) { 1503 /* 1504 * Turn cacheing back on for some pages. If it is a kernel 1505 * page, only do so if there are no other writable pages. 1506 */ 1507 for (pv = npv; pv; pv = pv->pv_next) { 1508 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1509 (kpmap != pv->pv_pmap || other_writable))) 1510 continue; 1511 1512 pv->pv_flags &= ~PVF_NC; 1513 1514 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1515 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1516 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1517 1518 if (l2pte_valid(pte)) { 1519 if (PV_BEEN_EXECD(pv->pv_flags)) { 1520 pmap_tlb_flushID_SE(pv->pv_pmap, 1521 pv->pv_va); 1522 } else 1523 if (PV_BEEN_REFD(pv->pv_flags)) { 1524 pmap_tlb_flushD_SE(pv->pv_pmap, 1525 pv->pv_va); 1526 } 1527 } 1528 1529 *ptep = pte; 1530 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1531 } 1532 } 1533 } 1534 1535 /* 1536 * Modify pte bits for all ptes corresponding to the given physical address. 1537 * We use `maskbits' rather than `clearbits' because we're always passing 1538 * constants and the latter would require an extra inversion at run-time. 1539 */ 1540 static void 1541 pmap_clearbit(struct vm_page *pg, u_int maskbits) 1542 { 1543 struct l2_bucket *l2b; 1544 struct pv_entry *pv; 1545 pt_entry_t *ptep, npte, opte; 1546 pmap_t pm; 1547 vaddr_t va; 1548 u_int oflags; 1549 1550 NPDEBUG(PDB_BITS, 1551 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 1552 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 1553 1554 PMAP_HEAD_TO_MAP_LOCK(); 1555 simple_lock(&pg->mdpage.pvh_slock); 1556 1557 /* 1558 * Clear saved attributes (modify, reference) 1559 */ 1560 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1561 1562 if (pg->mdpage.pvh_list == NULL) { 1563 simple_unlock(&pg->mdpage.pvh_slock); 1564 PMAP_HEAD_TO_MAP_UNLOCK(); 1565 return; 1566 } 1567 1568 /* 1569 * Loop over all current mappings setting/clearing as appropos 1570 */ 1571 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1572 va = pv->pv_va; 1573 pm = pv->pv_pmap; 1574 oflags = pv->pv_flags; 1575 pv->pv_flags &= ~maskbits; 1576 1577 pmap_acquire_pmap_lock(pm); 1578 1579 l2b = pmap_get_l2_bucket(pm, va); 1580 KDASSERT(l2b != NULL); 1581 1582 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1583 npte = opte = *ptep; 1584 1585 NPDEBUG(PDB_BITS, 1586 printf( 1587 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 1588 pv, pv->pv_pmap, pv->pv_va, oflags)); 1589 1590 if (maskbits & (PVF_WRITE|PVF_MOD)) { 1591 if ((pv->pv_flags & PVF_NC)) { 1592 /* 1593 * Entry is not cacheable: 1594 * 1595 * Don't turn caching on again if this is a 1596 * modified emulation. This would be 1597 * inconsitent with the settings created by 1598 * pmap_vac_me_harder(). Otherwise, it's safe 1599 * to re-enable cacheing. 1600 * 1601 * There's no need to call pmap_vac_me_harder() 1602 * here: all pages are losing their write 1603 * permission. 1604 */ 1605 if (maskbits & PVF_WRITE) { 1606 npte |= pte_l2_s_cache_mode; 1607 pv->pv_flags &= ~PVF_NC; 1608 } 1609 } else 1610 if (opte & L2_S_PROT_W) { 1611 /* 1612 * Entry is writable/cacheable: check if pmap 1613 * is current if it is flush it, otherwise it 1614 * won't be in the cache 1615 */ 1616 if (PV_BEEN_EXECD(oflags)) 1617 pmap_idcache_wbinv_range(pm, pv->pv_va, 1618 PAGE_SIZE); 1619 else 1620 if (PV_BEEN_REFD(oflags)) 1621 pmap_dcache_wb_range(pm, pv->pv_va, 1622 PAGE_SIZE, 1623 (maskbits & PVF_REF) ? true : false, 1624 false); 1625 } 1626 1627 /* make the pte read only */ 1628 npte &= ~L2_S_PROT_W; 1629 1630 if (maskbits & PVF_WRITE) { 1631 /* 1632 * Keep alias accounting up to date 1633 */ 1634 if (pv->pv_pmap == pmap_kernel()) { 1635 if (oflags & PVF_WRITE) { 1636 pg->mdpage.krw_mappings--; 1637 pg->mdpage.kro_mappings++; 1638 } 1639 } else 1640 if (oflags & PVF_WRITE) { 1641 pg->mdpage.urw_mappings--; 1642 pg->mdpage.uro_mappings++; 1643 } 1644 } 1645 } 1646 1647 if (maskbits & PVF_REF) { 1648 if ((pv->pv_flags & PVF_NC) == 0 && 1649 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1650 /* 1651 * Check npte here; we may have already 1652 * done the wbinv above, and the validity 1653 * of the PTE is the same for opte and 1654 * npte. 1655 */ 1656 if (npte & L2_S_PROT_W) { 1657 if (PV_BEEN_EXECD(oflags)) 1658 pmap_idcache_wbinv_range(pm, 1659 pv->pv_va, PAGE_SIZE); 1660 else 1661 if (PV_BEEN_REFD(oflags)) 1662 pmap_dcache_wb_range(pm, 1663 pv->pv_va, PAGE_SIZE, 1664 true, false); 1665 } else 1666 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1667 /* XXXJRT need idcache_inv_range */ 1668 if (PV_BEEN_EXECD(oflags)) 1669 pmap_idcache_wbinv_range(pm, 1670 pv->pv_va, PAGE_SIZE); 1671 else 1672 if (PV_BEEN_REFD(oflags)) 1673 pmap_dcache_wb_range(pm, 1674 pv->pv_va, PAGE_SIZE, 1675 true, true); 1676 } 1677 } 1678 1679 /* 1680 * Make the PTE invalid so that we will take a 1681 * page fault the next time the mapping is 1682 * referenced. 1683 */ 1684 npte &= ~L2_TYPE_MASK; 1685 npte |= L2_TYPE_INV; 1686 } 1687 1688 if (npte != opte) { 1689 *ptep = npte; 1690 PTE_SYNC(ptep); 1691 /* Flush the TLB entry if a current pmap. */ 1692 if (PV_BEEN_EXECD(oflags)) 1693 pmap_tlb_flushID_SE(pm, pv->pv_va); 1694 else 1695 if (PV_BEEN_REFD(oflags)) 1696 pmap_tlb_flushD_SE(pm, pv->pv_va); 1697 } 1698 1699 pmap_release_pmap_lock(pm); 1700 1701 NPDEBUG(PDB_BITS, 1702 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 1703 pm, va, opte, npte)); 1704 } 1705 1706 simple_unlock(&pg->mdpage.pvh_slock); 1707 PMAP_HEAD_TO_MAP_UNLOCK(); 1708 } 1709 1710 /* 1711 * pmap_clean_page() 1712 * 1713 * This is a local function used to work out the best strategy to clean 1714 * a single page referenced by its entry in the PV table. It's used by 1715 * pmap_copy_page, pmap_zero page and maybe some others later on. 1716 * 1717 * Its policy is effectively: 1718 * o If there are no mappings, we don't bother doing anything with the cache. 1719 * o If there is one mapping, we clean just that page. 1720 * o If there are multiple mappings, we clean the entire cache. 1721 * 1722 * So that some functions can be further optimised, it returns 0 if it didn't 1723 * clean the entire cache, or 1 if it did. 1724 * 1725 * XXX One bug in this routine is that if the pv_entry has a single page 1726 * mapped at 0x00000000 a whole cache clean will be performed rather than 1727 * just the 1 page. Since this should not occur in everyday use and if it does 1728 * it will just result in not the most efficient clean for the page. 1729 */ 1730 static int 1731 pmap_clean_page(struct pv_entry *pv, bool is_src) 1732 { 1733 pmap_t pm, pm_to_clean = NULL; 1734 struct pv_entry *npv; 1735 u_int cache_needs_cleaning = 0; 1736 u_int flags = 0; 1737 vaddr_t page_to_clean = 0; 1738 1739 if (pv == NULL) { 1740 /* nothing mapped in so nothing to flush */ 1741 return (0); 1742 } 1743 1744 /* 1745 * Since we flush the cache each time we change to a different 1746 * user vmspace, we only need to flush the page if it is in the 1747 * current pmap. 1748 */ 1749 if (curproc) 1750 pm = curproc->p_vmspace->vm_map.pmap; 1751 else 1752 pm = pmap_kernel(); 1753 1754 for (npv = pv; npv; npv = npv->pv_next) { 1755 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 1756 flags |= npv->pv_flags; 1757 /* 1758 * The page is mapped non-cacheable in 1759 * this map. No need to flush the cache. 1760 */ 1761 if (npv->pv_flags & PVF_NC) { 1762 #ifdef DIAGNOSTIC 1763 if (cache_needs_cleaning) 1764 panic("pmap_clean_page: " 1765 "cache inconsistency"); 1766 #endif 1767 break; 1768 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 1769 continue; 1770 if (cache_needs_cleaning) { 1771 page_to_clean = 0; 1772 break; 1773 } else { 1774 page_to_clean = npv->pv_va; 1775 pm_to_clean = npv->pv_pmap; 1776 } 1777 cache_needs_cleaning = 1; 1778 } 1779 } 1780 1781 if (page_to_clean) { 1782 if (PV_BEEN_EXECD(flags)) 1783 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 1784 PAGE_SIZE); 1785 else 1786 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 1787 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 1788 } else if (cache_needs_cleaning) { 1789 if (PV_BEEN_EXECD(flags)) 1790 pmap_idcache_wbinv_all(pm); 1791 else 1792 pmap_dcache_wbinv_all(pm); 1793 return (1); 1794 } 1795 return (0); 1796 } 1797 1798 /* 1799 * Routine: pmap_page_remove 1800 * Function: 1801 * Removes this physical page from 1802 * all physical maps in which it resides. 1803 * Reflects back modify bits to the pager. 1804 */ 1805 static void 1806 pmap_page_remove(struct vm_page *pg) 1807 { 1808 struct l2_bucket *l2b; 1809 struct pv_entry *pv, *npv; 1810 pmap_t pm, curpm; 1811 pt_entry_t *ptep, pte; 1812 bool flush; 1813 u_int flags; 1814 1815 NPDEBUG(PDB_FOLLOW, 1816 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 1817 VM_PAGE_TO_PHYS(pg))); 1818 1819 PMAP_HEAD_TO_MAP_LOCK(); 1820 simple_lock(&pg->mdpage.pvh_slock); 1821 1822 pv = pg->mdpage.pvh_list; 1823 if (pv == NULL) { 1824 simple_unlock(&pg->mdpage.pvh_slock); 1825 PMAP_HEAD_TO_MAP_UNLOCK(); 1826 return; 1827 } 1828 1829 /* 1830 * Clear alias counts 1831 */ 1832 pg->mdpage.k_mappings = 0; 1833 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 1834 1835 flush = false; 1836 flags = 0; 1837 if (curproc) 1838 curpm = curproc->p_vmspace->vm_map.pmap; 1839 else 1840 curpm = pmap_kernel(); 1841 1842 pmap_clean_page(pv, false); 1843 1844 while (pv) { 1845 pm = pv->pv_pmap; 1846 if (flush == false && (pm == curpm || pm == pmap_kernel())) 1847 flush = true; 1848 1849 pmap_acquire_pmap_lock(pm); 1850 1851 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 1852 KDASSERT(l2b != NULL); 1853 1854 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1855 pte = *ptep; 1856 1857 /* 1858 * Update statistics 1859 */ 1860 --pm->pm_stats.resident_count; 1861 1862 /* Wired bit */ 1863 if (pv->pv_flags & PVF_WIRED) 1864 --pm->pm_stats.wired_count; 1865 1866 flags |= pv->pv_flags; 1867 1868 /* 1869 * Invalidate the PTEs. 1870 */ 1871 *ptep = 0; 1872 PTE_SYNC_CURRENT(pm, ptep); 1873 pmap_free_l2_bucket(pm, l2b, 1); 1874 1875 npv = pv->pv_next; 1876 pool_put(&pmap_pv_pool, pv); 1877 pv = npv; 1878 pmap_release_pmap_lock(pm); 1879 } 1880 pg->mdpage.pvh_list = NULL; 1881 simple_unlock(&pg->mdpage.pvh_slock); 1882 PMAP_HEAD_TO_MAP_UNLOCK(); 1883 1884 if (flush) { 1885 /* 1886 * Note: We can't use pmap_tlb_flush{I,}D() here since that 1887 * would need a subsequent call to pmap_update() to ensure 1888 * curpm->pm_cstate.cs_all is reset. Our callers are not 1889 * required to do that (see pmap(9)), so we can't modify 1890 * the current pmap's state. 1891 */ 1892 if (PV_BEEN_EXECD(flags)) 1893 cpu_tlb_flushID(); 1894 else 1895 cpu_tlb_flushD(); 1896 } 1897 cpu_cpwait(); 1898 } 1899 1900 /* 1901 * pmap_t pmap_create(void) 1902 * 1903 * Create a new pmap structure from scratch. 1904 */ 1905 pmap_t 1906 pmap_create(void) 1907 { 1908 pmap_t pm; 1909 1910 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 1911 1912 simple_lock_init(&pm->pm_lock); 1913 pm->pm_obj.pgops = NULL; /* currently not a mappable object */ 1914 TAILQ_INIT(&pm->pm_obj.memq); 1915 pm->pm_obj.uo_npages = 0; 1916 pm->pm_obj.uo_refs = 1; 1917 pm->pm_stats.wired_count = 0; 1918 pm->pm_stats.resident_count = 1; 1919 pm->pm_cstate.cs_all = 0; 1920 pmap_alloc_l1(pm); 1921 1922 /* 1923 * Note: The pool cache ensures that the pm_l2[] array is already 1924 * initialised to zero. 1925 */ 1926 1927 pmap_pinit(pm); 1928 1929 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 1930 1931 return (pm); 1932 } 1933 1934 /* 1935 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 1936 * int flags) 1937 * 1938 * Insert the given physical page (p) at 1939 * the specified virtual address (v) in the 1940 * target physical map with the protection requested. 1941 * 1942 * NB: This is the only routine which MAY NOT lazy-evaluate 1943 * or lose information. That is, this routine must actually 1944 * insert this page into the given map NOW. 1945 */ 1946 int 1947 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 1948 { 1949 struct l2_bucket *l2b; 1950 struct vm_page *pg, *opg; 1951 struct pv_entry *pve; 1952 pt_entry_t *ptep, npte, opte; 1953 u_int nflags; 1954 u_int oflags; 1955 1956 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 1957 1958 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 1959 KDASSERT(((va | pa) & PGOFSET) == 0); 1960 1961 /* 1962 * Get a pointer to the page. Later on in this function, we 1963 * test for a managed page by checking pg != NULL. 1964 */ 1965 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 1966 1967 nflags = 0; 1968 if (prot & VM_PROT_WRITE) 1969 nflags |= PVF_WRITE; 1970 if (prot & VM_PROT_EXECUTE) 1971 nflags |= PVF_EXEC; 1972 if (flags & PMAP_WIRED) 1973 nflags |= PVF_WIRED; 1974 1975 PMAP_MAP_TO_HEAD_LOCK(); 1976 pmap_acquire_pmap_lock(pm); 1977 1978 /* 1979 * Fetch the L2 bucket which maps this page, allocating one if 1980 * necessary for user pmaps. 1981 */ 1982 if (pm == pmap_kernel()) 1983 l2b = pmap_get_l2_bucket(pm, va); 1984 else 1985 l2b = pmap_alloc_l2_bucket(pm, va); 1986 if (l2b == NULL) { 1987 if (flags & PMAP_CANFAIL) { 1988 pmap_release_pmap_lock(pm); 1989 PMAP_MAP_TO_HEAD_UNLOCK(); 1990 return (ENOMEM); 1991 } 1992 panic("pmap_enter: failed to allocate L2 bucket"); 1993 } 1994 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1995 opte = *ptep; 1996 npte = pa; 1997 oflags = 0; 1998 1999 if (opte) { 2000 /* 2001 * There is already a mapping at this address. 2002 * If the physical address is different, lookup the 2003 * vm_page. 2004 */ 2005 if (l2pte_pa(opte) != pa) 2006 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2007 else 2008 opg = pg; 2009 } else 2010 opg = NULL; 2011 2012 if (pg) { 2013 /* 2014 * This is to be a managed mapping. 2015 */ 2016 if ((flags & VM_PROT_ALL) || 2017 (pg->mdpage.pvh_attrs & PVF_REF)) { 2018 /* 2019 * - The access type indicates that we don't need 2020 * to do referenced emulation. 2021 * OR 2022 * - The physical page has already been referenced 2023 * so no need to re-do referenced emulation here. 2024 */ 2025 npte |= L2_S_PROTO; 2026 2027 nflags |= PVF_REF; 2028 2029 if ((prot & VM_PROT_WRITE) != 0 && 2030 ((flags & VM_PROT_WRITE) != 0 || 2031 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2032 /* 2033 * This is a writable mapping, and the 2034 * page's mod state indicates it has 2035 * already been modified. Make it 2036 * writable from the outset. 2037 */ 2038 npte |= L2_S_PROT_W; 2039 nflags |= PVF_MOD; 2040 } 2041 } else { 2042 /* 2043 * Need to do page referenced emulation. 2044 */ 2045 npte |= L2_TYPE_INV; 2046 } 2047 2048 npte |= pte_l2_s_cache_mode; 2049 2050 if (pg == opg) { 2051 /* 2052 * We're changing the attrs of an existing mapping. 2053 */ 2054 simple_lock(&pg->mdpage.pvh_slock); 2055 oflags = pmap_modify_pv(pg, pm, va, 2056 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2057 PVF_MOD | PVF_REF, nflags); 2058 simple_unlock(&pg->mdpage.pvh_slock); 2059 2060 /* 2061 * We may need to flush the cache if we're 2062 * doing rw-ro... 2063 */ 2064 if (pm->pm_cstate.cs_cache_d && 2065 (oflags & PVF_NC) == 0 && 2066 (opte & L2_S_PROT_W) != 0 && 2067 (prot & VM_PROT_WRITE) == 0) 2068 cpu_dcache_wb_range(va, PAGE_SIZE); 2069 } else { 2070 /* 2071 * New mapping, or changing the backing page 2072 * of an existing mapping. 2073 */ 2074 if (opg) { 2075 /* 2076 * Replacing an existing mapping with a new one. 2077 * It is part of our managed memory so we 2078 * must remove it from the PV list 2079 */ 2080 simple_lock(&opg->mdpage.pvh_slock); 2081 pve = pmap_remove_pv(opg, pm, va, 0); 2082 pmap_vac_me_harder(opg, pm, 0); 2083 simple_unlock(&opg->mdpage.pvh_slock); 2084 oflags = pve->pv_flags; 2085 2086 /* 2087 * If the old mapping was valid (ref/mod 2088 * emulation creates 'invalid' mappings 2089 * initially) then make sure to frob 2090 * the cache. 2091 */ 2092 if ((oflags & PVF_NC) == 0 && 2093 l2pte_valid(opte)) { 2094 if (PV_BEEN_EXECD(oflags)) { 2095 pmap_idcache_wbinv_range(pm, va, 2096 PAGE_SIZE); 2097 } else 2098 if (PV_BEEN_REFD(oflags)) { 2099 pmap_dcache_wb_range(pm, va, 2100 PAGE_SIZE, true, 2101 (oflags & PVF_WRITE) == 0); 2102 } 2103 } 2104 } else 2105 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2106 if ((flags & PMAP_CANFAIL) == 0) 2107 panic("pmap_enter: no pv entries"); 2108 2109 if (pm != pmap_kernel()) 2110 pmap_free_l2_bucket(pm, l2b, 0); 2111 pmap_release_pmap_lock(pm); 2112 PMAP_MAP_TO_HEAD_UNLOCK(); 2113 NPDEBUG(PDB_ENTER, 2114 printf("pmap_enter: ENOMEM\n")); 2115 return (ENOMEM); 2116 } 2117 2118 pmap_enter_pv(pg, pve, pm, va, nflags); 2119 } 2120 } else { 2121 /* 2122 * We're mapping an unmanaged page. 2123 * These are always readable, and possibly writable, from 2124 * the get go as we don't need to track ref/mod status. 2125 */ 2126 npte |= L2_S_PROTO; 2127 if (prot & VM_PROT_WRITE) 2128 npte |= L2_S_PROT_W; 2129 2130 /* 2131 * Make sure the vector table is mapped cacheable 2132 */ 2133 if (pm != pmap_kernel() && va == vector_page) 2134 npte |= pte_l2_s_cache_mode; 2135 2136 if (opg) { 2137 /* 2138 * Looks like there's an existing 'managed' mapping 2139 * at this address. 2140 */ 2141 simple_lock(&opg->mdpage.pvh_slock); 2142 pve = pmap_remove_pv(opg, pm, va, 0); 2143 pmap_vac_me_harder(opg, pm, 0); 2144 simple_unlock(&opg->mdpage.pvh_slock); 2145 oflags = pve->pv_flags; 2146 2147 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2148 if (PV_BEEN_EXECD(oflags)) 2149 pmap_idcache_wbinv_range(pm, va, 2150 PAGE_SIZE); 2151 else 2152 if (PV_BEEN_REFD(oflags)) 2153 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2154 true, (oflags & PVF_WRITE) == 0); 2155 } 2156 pool_put(&pmap_pv_pool, pve); 2157 } 2158 } 2159 2160 /* 2161 * Make sure userland mappings get the right permissions 2162 */ 2163 if (pm != pmap_kernel() && va != vector_page) 2164 npte |= L2_S_PROT_U; 2165 2166 /* 2167 * Keep the stats up to date 2168 */ 2169 if (opte == 0) { 2170 l2b->l2b_occupancy++; 2171 pm->pm_stats.resident_count++; 2172 } 2173 2174 NPDEBUG(PDB_ENTER, 2175 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2176 2177 /* 2178 * If this is just a wiring change, the two PTEs will be 2179 * identical, so there's no need to update the page table. 2180 */ 2181 if (npte != opte) { 2182 bool is_cached = pmap_is_cached(pm); 2183 2184 *ptep = npte; 2185 if (is_cached) { 2186 /* 2187 * We only need to frob the cache/tlb if this pmap 2188 * is current 2189 */ 2190 PTE_SYNC(ptep); 2191 if (va != vector_page && l2pte_valid(npte)) { 2192 /* 2193 * This mapping is likely to be accessed as 2194 * soon as we return to userland. Fix up the 2195 * L1 entry to avoid taking another 2196 * page/domain fault. 2197 */ 2198 pd_entry_t *pl1pd, l1pd; 2199 2200 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2201 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2202 L1_C_PROTO; 2203 if (*pl1pd != l1pd) { 2204 *pl1pd = l1pd; 2205 PTE_SYNC(pl1pd); 2206 } 2207 } 2208 } 2209 2210 if (PV_BEEN_EXECD(oflags)) 2211 pmap_tlb_flushID_SE(pm, va); 2212 else 2213 if (PV_BEEN_REFD(oflags)) 2214 pmap_tlb_flushD_SE(pm, va); 2215 2216 NPDEBUG(PDB_ENTER, 2217 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2218 is_cached, pm->pm_cstate.cs_all)); 2219 2220 if (pg != NULL) { 2221 simple_lock(&pg->mdpage.pvh_slock); 2222 pmap_vac_me_harder(pg, pm, va); 2223 simple_unlock(&pg->mdpage.pvh_slock); 2224 } 2225 } 2226 2227 pmap_release_pmap_lock(pm); 2228 PMAP_MAP_TO_HEAD_UNLOCK(); 2229 2230 return (0); 2231 } 2232 2233 /* 2234 * pmap_remove() 2235 * 2236 * pmap_remove is responsible for nuking a number of mappings for a range 2237 * of virtual address space in the current pmap. To do this efficiently 2238 * is interesting, because in a number of cases a wide virtual address 2239 * range may be supplied that contains few actual mappings. So, the 2240 * optimisations are: 2241 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 2242 * 2. Build up a list of pages we've hit, up to a maximum, so we can 2243 * maybe do just a partial cache clean. This path of execution is 2244 * complicated by the fact that the cache must be flushed _before_ 2245 * the PTE is nuked, being a VAC :-) 2246 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 2247 * all invalidations until pmap_update(), since pmap_remove_all() has 2248 * already flushed the cache. 2249 * 4. Maybe later fast-case a single page, but I don't think this is 2250 * going to make _that_ much difference overall. 2251 */ 2252 2253 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 2254 2255 void 2256 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 2257 { 2258 struct l2_bucket *l2b; 2259 vaddr_t next_bucket; 2260 pt_entry_t *ptep; 2261 u_int cleanlist_idx, total, cnt; 2262 struct { 2263 vaddr_t va; 2264 pt_entry_t *pte; 2265 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 2266 u_int mappings, is_exec, is_refd; 2267 2268 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 2269 "eva=%08lx\n", pm, sva, eva)); 2270 2271 /* 2272 * we lock in the pmap => pv_head direction 2273 */ 2274 PMAP_MAP_TO_HEAD_LOCK(); 2275 pmap_acquire_pmap_lock(pm); 2276 2277 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 2278 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2279 if (pm->pm_cstate.cs_tlb == 0) 2280 pm->pm_remove_all = true; 2281 } else 2282 cleanlist_idx = 0; 2283 2284 total = 0; 2285 2286 while (sva < eva) { 2287 /* 2288 * Do one L2 bucket's worth at a time. 2289 */ 2290 next_bucket = L2_NEXT_BUCKET(sva); 2291 if (next_bucket > eva) 2292 next_bucket = eva; 2293 2294 l2b = pmap_get_l2_bucket(pm, sva); 2295 if (l2b == NULL) { 2296 sva = next_bucket; 2297 continue; 2298 } 2299 2300 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2301 2302 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 2303 struct vm_page *pg; 2304 pt_entry_t pte; 2305 paddr_t pa; 2306 2307 pte = *ptep; 2308 2309 if (pte == 0) { 2310 /* Nothing here, move along */ 2311 continue; 2312 } 2313 2314 pa = l2pte_pa(pte); 2315 is_exec = 0; 2316 is_refd = 1; 2317 2318 /* 2319 * Update flags. In a number of circumstances, 2320 * we could cluster a lot of these and do a 2321 * number of sequential pages in one go. 2322 */ 2323 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 2324 struct pv_entry *pve; 2325 simple_lock(&pg->mdpage.pvh_slock); 2326 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 2327 pmap_vac_me_harder(pg, pm, 0); 2328 simple_unlock(&pg->mdpage.pvh_slock); 2329 if (pve != NULL) { 2330 if (pm->pm_remove_all == false) { 2331 is_exec = 2332 PV_BEEN_EXECD(pve->pv_flags); 2333 is_refd = 2334 PV_BEEN_REFD(pve->pv_flags); 2335 } 2336 pool_put(&pmap_pv_pool, pve); 2337 } else 2338 if (skip_wired) { 2339 /* The mapping is wired. Skip it */ 2340 continue; 2341 } 2342 } else 2343 if (skip_wired) { 2344 /* Unmanaged pages are always wired. */ 2345 continue; 2346 } 2347 2348 mappings++; 2349 2350 if (!l2pte_valid(pte)) { 2351 /* 2352 * Ref/Mod emulation is still active for this 2353 * mapping, therefore it is has not yet been 2354 * accessed. No need to frob the cache/tlb. 2355 */ 2356 *ptep = 0; 2357 PTE_SYNC_CURRENT(pm, ptep); 2358 continue; 2359 } 2360 2361 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 2362 /* Add to the clean list. */ 2363 cleanlist[cleanlist_idx].pte = ptep; 2364 cleanlist[cleanlist_idx].va = 2365 sva | (is_exec & 1); 2366 cleanlist_idx++; 2367 } else 2368 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 2369 /* Nuke everything if needed. */ 2370 pmap_idcache_wbinv_all(pm); 2371 pmap_tlb_flushID(pm); 2372 2373 /* 2374 * Roll back the previous PTE list, 2375 * and zero out the current PTE. 2376 */ 2377 for (cnt = 0; 2378 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 2379 *cleanlist[cnt].pte = 0; 2380 } 2381 *ptep = 0; 2382 PTE_SYNC(ptep); 2383 cleanlist_idx++; 2384 pm->pm_remove_all = true; 2385 } else { 2386 *ptep = 0; 2387 PTE_SYNC(ptep); 2388 if (pm->pm_remove_all == false) { 2389 if (is_exec) 2390 pmap_tlb_flushID_SE(pm, sva); 2391 else 2392 if (is_refd) 2393 pmap_tlb_flushD_SE(pm, sva); 2394 } 2395 } 2396 } 2397 2398 /* 2399 * Deal with any left overs 2400 */ 2401 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 2402 total += cleanlist_idx; 2403 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 2404 if (pm->pm_cstate.cs_all != 0) { 2405 vaddr_t clva = cleanlist[cnt].va & ~1; 2406 if (cleanlist[cnt].va & 1) { 2407 pmap_idcache_wbinv_range(pm, 2408 clva, PAGE_SIZE); 2409 pmap_tlb_flushID_SE(pm, clva); 2410 } else { 2411 pmap_dcache_wb_range(pm, 2412 clva, PAGE_SIZE, true, 2413 false); 2414 pmap_tlb_flushD_SE(pm, clva); 2415 } 2416 } 2417 *cleanlist[cnt].pte = 0; 2418 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 2419 } 2420 2421 /* 2422 * If it looks like we're removing a whole bunch 2423 * of mappings, it's faster to just write-back 2424 * the whole cache now and defer TLB flushes until 2425 * pmap_update() is called. 2426 */ 2427 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 2428 cleanlist_idx = 0; 2429 else { 2430 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2431 pmap_idcache_wbinv_all(pm); 2432 pm->pm_remove_all = true; 2433 } 2434 } 2435 2436 pmap_free_l2_bucket(pm, l2b, mappings); 2437 pm->pm_stats.resident_count -= mappings; 2438 } 2439 2440 pmap_release_pmap_lock(pm); 2441 PMAP_MAP_TO_HEAD_UNLOCK(); 2442 } 2443 2444 /* 2445 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 2446 * 2447 * We assume there is already sufficient KVM space available 2448 * to do this, as we can't allocate L2 descriptor tables/metadata 2449 * from here. 2450 */ 2451 void 2452 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 2453 { 2454 struct l2_bucket *l2b; 2455 pt_entry_t *ptep, opte; 2456 2457 NPDEBUG(PDB_KENTER, 2458 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 2459 va, pa, prot)); 2460 2461 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2462 KDASSERT(l2b != NULL); 2463 2464 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2465 opte = *ptep; 2466 2467 if (l2pte_valid(opte)) { 2468 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2469 cpu_tlb_flushD_SE(va); 2470 cpu_cpwait(); 2471 } else 2472 if (opte == 0) 2473 l2b->l2b_occupancy++; 2474 2475 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 2476 pte_l2_s_cache_mode; 2477 PTE_SYNC(ptep); 2478 } 2479 2480 void 2481 pmap_kremove(vaddr_t va, vsize_t len) 2482 { 2483 struct l2_bucket *l2b; 2484 pt_entry_t *ptep, *sptep, opte; 2485 vaddr_t next_bucket, eva; 2486 u_int mappings; 2487 2488 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 2489 va, len)); 2490 2491 eva = va + len; 2492 2493 while (va < eva) { 2494 next_bucket = L2_NEXT_BUCKET(va); 2495 if (next_bucket > eva) 2496 next_bucket = eva; 2497 2498 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2499 KDASSERT(l2b != NULL); 2500 2501 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 2502 mappings = 0; 2503 2504 while (va < next_bucket) { 2505 opte = *ptep; 2506 if (l2pte_valid(opte)) { 2507 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2508 cpu_tlb_flushD_SE(va); 2509 } 2510 if (opte) { 2511 *ptep = 0; 2512 mappings++; 2513 } 2514 va += PAGE_SIZE; 2515 ptep++; 2516 } 2517 KDASSERT(mappings <= l2b->l2b_occupancy); 2518 l2b->l2b_occupancy -= mappings; 2519 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 2520 } 2521 cpu_cpwait(); 2522 } 2523 2524 bool 2525 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 2526 { 2527 struct l2_dtable *l2; 2528 pd_entry_t *pl1pd, l1pd; 2529 pt_entry_t *ptep, pte; 2530 paddr_t pa; 2531 u_int l1idx; 2532 2533 pmap_acquire_pmap_lock(pm); 2534 2535 l1idx = L1_IDX(va); 2536 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2537 l1pd = *pl1pd; 2538 2539 if (l1pte_section_p(l1pd)) { 2540 /* 2541 * These should only happen for pmap_kernel() 2542 */ 2543 KDASSERT(pm == pmap_kernel()); 2544 pmap_release_pmap_lock(pm); 2545 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 2546 } else { 2547 /* 2548 * Note that we can't rely on the validity of the L1 2549 * descriptor as an indication that a mapping exists. 2550 * We have to look it up in the L2 dtable. 2551 */ 2552 l2 = pm->pm_l2[L2_IDX(l1idx)]; 2553 2554 if (l2 == NULL || 2555 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 2556 pmap_release_pmap_lock(pm); 2557 return (false); 2558 } 2559 2560 ptep = &ptep[l2pte_index(va)]; 2561 pte = *ptep; 2562 pmap_release_pmap_lock(pm); 2563 2564 if (pte == 0) 2565 return (false); 2566 2567 switch (pte & L2_TYPE_MASK) { 2568 case L2_TYPE_L: 2569 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 2570 break; 2571 2572 default: 2573 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 2574 break; 2575 } 2576 } 2577 2578 if (pap != NULL) 2579 *pap = pa; 2580 2581 return (true); 2582 } 2583 2584 void 2585 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 2586 { 2587 struct l2_bucket *l2b; 2588 pt_entry_t *ptep, pte; 2589 vaddr_t next_bucket; 2590 u_int flags; 2591 int flush; 2592 2593 NPDEBUG(PDB_PROTECT, 2594 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 2595 pm, sva, eva, prot)); 2596 2597 if ((prot & VM_PROT_READ) == 0) { 2598 pmap_remove(pm, sva, eva); 2599 return; 2600 } 2601 2602 if (prot & VM_PROT_WRITE) { 2603 /* 2604 * If this is a read->write transition, just ignore it and let 2605 * uvm_fault() take care of it later. 2606 */ 2607 return; 2608 } 2609 2610 PMAP_MAP_TO_HEAD_LOCK(); 2611 pmap_acquire_pmap_lock(pm); 2612 2613 /* 2614 * OK, at this point, we know we're doing write-protect operation. 2615 * If the pmap is active, write-back the range. 2616 */ 2617 pmap_dcache_wb_range(pm, sva, eva - sva, false, false); 2618 2619 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 2620 flags = 0; 2621 2622 while (sva < eva) { 2623 next_bucket = L2_NEXT_BUCKET(sva); 2624 if (next_bucket > eva) 2625 next_bucket = eva; 2626 2627 l2b = pmap_get_l2_bucket(pm, sva); 2628 if (l2b == NULL) { 2629 sva = next_bucket; 2630 continue; 2631 } 2632 2633 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2634 2635 while (sva < next_bucket) { 2636 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 2637 struct vm_page *pg; 2638 u_int f; 2639 2640 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 2641 pte &= ~L2_S_PROT_W; 2642 *ptep = pte; 2643 PTE_SYNC(ptep); 2644 2645 if (pg != NULL) { 2646 simple_lock(&pg->mdpage.pvh_slock); 2647 f = pmap_modify_pv(pg, pm, sva, 2648 PVF_WRITE, 0); 2649 pmap_vac_me_harder(pg, pm, sva); 2650 simple_unlock(&pg->mdpage.pvh_slock); 2651 } else 2652 f = PVF_REF | PVF_EXEC; 2653 2654 if (flush >= 0) { 2655 flush++; 2656 flags |= f; 2657 } else 2658 if (PV_BEEN_EXECD(f)) 2659 pmap_tlb_flushID_SE(pm, sva); 2660 else 2661 if (PV_BEEN_REFD(f)) 2662 pmap_tlb_flushD_SE(pm, sva); 2663 } 2664 2665 sva += PAGE_SIZE; 2666 ptep++; 2667 } 2668 } 2669 2670 pmap_release_pmap_lock(pm); 2671 PMAP_MAP_TO_HEAD_UNLOCK(); 2672 2673 if (flush) { 2674 if (PV_BEEN_EXECD(flags)) 2675 pmap_tlb_flushID(pm); 2676 else 2677 if (PV_BEEN_REFD(flags)) 2678 pmap_tlb_flushD(pm); 2679 } 2680 } 2681 2682 void 2683 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 2684 { 2685 2686 NPDEBUG(PDB_PROTECT, 2687 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 2688 pg, VM_PAGE_TO_PHYS(pg), prot)); 2689 2690 switch(prot) { 2691 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 2692 case VM_PROT_READ|VM_PROT_WRITE: 2693 return; 2694 2695 case VM_PROT_READ: 2696 case VM_PROT_READ|VM_PROT_EXECUTE: 2697 pmap_clearbit(pg, PVF_WRITE); 2698 break; 2699 2700 default: 2701 pmap_page_remove(pg); 2702 break; 2703 } 2704 } 2705 2706 /* 2707 * pmap_clear_modify: 2708 * 2709 * Clear the "modified" attribute for a page. 2710 */ 2711 bool 2712 pmap_clear_modify(struct vm_page *pg) 2713 { 2714 bool rv; 2715 2716 if (pg->mdpage.pvh_attrs & PVF_MOD) { 2717 rv = true; 2718 pmap_clearbit(pg, PVF_MOD); 2719 } else 2720 rv = false; 2721 2722 return (rv); 2723 } 2724 2725 /* 2726 * pmap_clear_reference: 2727 * 2728 * Clear the "referenced" attribute for a page. 2729 */ 2730 bool 2731 pmap_clear_reference(struct vm_page *pg) 2732 { 2733 bool rv; 2734 2735 if (pg->mdpage.pvh_attrs & PVF_REF) { 2736 rv = true; 2737 pmap_clearbit(pg, PVF_REF); 2738 } else 2739 rv = false; 2740 2741 return (rv); 2742 } 2743 2744 /* 2745 * pmap_is_modified: 2746 * 2747 * Test if a page has the "modified" attribute. 2748 */ 2749 /* See <arm/arm32/pmap.h> */ 2750 2751 /* 2752 * pmap_is_referenced: 2753 * 2754 * Test if a page has the "referenced" attribute. 2755 */ 2756 /* See <arm/arm32/pmap.h> */ 2757 2758 int 2759 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 2760 { 2761 struct l2_dtable *l2; 2762 struct l2_bucket *l2b; 2763 pd_entry_t *pl1pd, l1pd; 2764 pt_entry_t *ptep, pte; 2765 paddr_t pa; 2766 u_int l1idx; 2767 int rv = 0; 2768 2769 PMAP_MAP_TO_HEAD_LOCK(); 2770 pmap_acquire_pmap_lock(pm); 2771 2772 l1idx = L1_IDX(va); 2773 2774 /* 2775 * If there is no l2_dtable for this address, then the process 2776 * has no business accessing it. 2777 * 2778 * Note: This will catch userland processes trying to access 2779 * kernel addresses. 2780 */ 2781 l2 = pm->pm_l2[L2_IDX(l1idx)]; 2782 if (l2 == NULL) 2783 goto out; 2784 2785 /* 2786 * Likewise if there is no L2 descriptor table 2787 */ 2788 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2789 if (l2b->l2b_kva == NULL) 2790 goto out; 2791 2792 /* 2793 * Check the PTE itself. 2794 */ 2795 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2796 pte = *ptep; 2797 if (pte == 0) 2798 goto out; 2799 2800 /* 2801 * Catch a userland access to the vector page mapped at 0x0 2802 */ 2803 if (user && (pte & L2_S_PROT_U) == 0) 2804 goto out; 2805 2806 pa = l2pte_pa(pte); 2807 2808 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 2809 /* 2810 * This looks like a good candidate for "page modified" 2811 * emulation... 2812 */ 2813 struct pv_entry *pv; 2814 struct vm_page *pg; 2815 2816 /* Extract the physical address of the page */ 2817 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2818 goto out; 2819 2820 /* Get the current flags for this page. */ 2821 simple_lock(&pg->mdpage.pvh_slock); 2822 2823 pv = pmap_find_pv(pg, pm, va); 2824 if (pv == NULL) { 2825 simple_unlock(&pg->mdpage.pvh_slock); 2826 goto out; 2827 } 2828 2829 /* 2830 * Do the flags say this page is writable? If not then it 2831 * is a genuine write fault. If yes then the write fault is 2832 * our fault as we did not reflect the write access in the 2833 * PTE. Now we know a write has occurred we can correct this 2834 * and also set the modified bit 2835 */ 2836 if ((pv->pv_flags & PVF_WRITE) == 0) { 2837 simple_unlock(&pg->mdpage.pvh_slock); 2838 goto out; 2839 } 2840 2841 NPDEBUG(PDB_FOLLOW, 2842 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 2843 pm, va, VM_PAGE_TO_PHYS(pg))); 2844 2845 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 2846 pv->pv_flags |= PVF_REF | PVF_MOD; 2847 simple_unlock(&pg->mdpage.pvh_slock); 2848 2849 /* 2850 * Re-enable write permissions for the page. No need to call 2851 * pmap_vac_me_harder(), since this is just a 2852 * modified-emulation fault, and the PVF_WRITE bit isn't 2853 * changing. We've already set the cacheable bits based on 2854 * the assumption that we can write to this page. 2855 */ 2856 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 2857 PTE_SYNC(ptep); 2858 rv = 1; 2859 } else 2860 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2861 /* 2862 * This looks like a good candidate for "page referenced" 2863 * emulation. 2864 */ 2865 struct pv_entry *pv; 2866 struct vm_page *pg; 2867 2868 /* Extract the physical address of the page */ 2869 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2870 goto out; 2871 2872 /* Get the current flags for this page. */ 2873 simple_lock(&pg->mdpage.pvh_slock); 2874 2875 pv = pmap_find_pv(pg, pm, va); 2876 if (pv == NULL) { 2877 simple_unlock(&pg->mdpage.pvh_slock); 2878 goto out; 2879 } 2880 2881 pg->mdpage.pvh_attrs |= PVF_REF; 2882 pv->pv_flags |= PVF_REF; 2883 simple_unlock(&pg->mdpage.pvh_slock); 2884 2885 NPDEBUG(PDB_FOLLOW, 2886 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 2887 pm, va, VM_PAGE_TO_PHYS(pg))); 2888 2889 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2890 PTE_SYNC(ptep); 2891 rv = 1; 2892 } 2893 2894 /* 2895 * We know there is a valid mapping here, so simply 2896 * fix up the L1 if necessary. 2897 */ 2898 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2899 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2900 if (*pl1pd != l1pd) { 2901 *pl1pd = l1pd; 2902 PTE_SYNC(pl1pd); 2903 rv = 1; 2904 } 2905 2906 #ifdef CPU_SA110 2907 /* 2908 * There are bugs in the rev K SA110. This is a check for one 2909 * of them. 2910 */ 2911 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2912 curcpu()->ci_arm_cpurev < 3) { 2913 /* Always current pmap */ 2914 if (l2pte_valid(pte)) { 2915 extern int kernel_debug; 2916 if (kernel_debug & 1) { 2917 struct proc *p = curlwp->l_proc; 2918 printf("prefetch_abort: page is already " 2919 "mapped - pte=%p *pte=%08x\n", ptep, pte); 2920 printf("prefetch_abort: pc=%08lx proc=%p " 2921 "process=%s\n", va, p, p->p_comm); 2922 printf("prefetch_abort: far=%08x fs=%x\n", 2923 cpu_faultaddress(), cpu_faultstatus()); 2924 } 2925 #ifdef DDB 2926 if (kernel_debug & 2) 2927 Debugger(); 2928 #endif 2929 rv = 1; 2930 } 2931 } 2932 #endif /* CPU_SA110 */ 2933 2934 #ifdef DEBUG 2935 /* 2936 * If 'rv == 0' at this point, it generally indicates that there is a 2937 * stale TLB entry for the faulting address. This happens when two or 2938 * more processes are sharing an L1. Since we don't flush the TLB on 2939 * a context switch between such processes, we can take domain faults 2940 * for mappings which exist at the same VA in both processes. EVEN IF 2941 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2942 * example. 2943 * 2944 * This is extremely likely to happen if pmap_enter() updated the L1 2945 * entry for a recently entered mapping. In this case, the TLB is 2946 * flushed for the new mapping, but there may still be TLB entries for 2947 * other mappings belonging to other processes in the 1MB range 2948 * covered by the L1 entry. 2949 * 2950 * Since 'rv == 0', we know that the L1 already contains the correct 2951 * value, so the fault must be due to a stale TLB entry. 2952 * 2953 * Since we always need to flush the TLB anyway in the case where we 2954 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2955 * stale TLB entries dynamically. 2956 * 2957 * However, the above condition can ONLY happen if the current L1 is 2958 * being shared. If it happens when the L1 is unshared, it indicates 2959 * that other parts of the pmap are not doing their job WRT managing 2960 * the TLB. 2961 */ 2962 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2963 extern int last_fault_code; 2964 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2965 pm, va, ftype); 2966 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2967 l2, l2b, ptep, pl1pd); 2968 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2969 pte, l1pd, last_fault_code); 2970 #ifdef DDB 2971 Debugger(); 2972 #endif 2973 } 2974 #endif 2975 2976 cpu_tlb_flushID_SE(va); 2977 cpu_cpwait(); 2978 2979 rv = 1; 2980 2981 out: 2982 pmap_release_pmap_lock(pm); 2983 PMAP_MAP_TO_HEAD_UNLOCK(); 2984 2985 return (rv); 2986 } 2987 2988 /* 2989 * pmap_collect: free resources held by a pmap 2990 * 2991 * => optional function. 2992 * => called when a process is swapped out to free memory. 2993 */ 2994 void 2995 pmap_collect(pmap_t pm) 2996 { 2997 2998 pmap_idcache_wbinv_all(pm); 2999 pm->pm_remove_all = true; 3000 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 3001 pmap_update(pm); 3002 } 3003 3004 /* 3005 * Routine: pmap_procwr 3006 * 3007 * Function: 3008 * Synchronize caches corresponding to [addr, addr+len) in p. 3009 * 3010 */ 3011 void 3012 pmap_procwr(struct proc *p, vaddr_t va, int len) 3013 { 3014 /* We only need to do anything if it is the current process. */ 3015 if (p == curproc) 3016 cpu_icache_sync_range(va, len); 3017 } 3018 3019 /* 3020 * Routine: pmap_unwire 3021 * Function: Clear the wired attribute for a map/virtual-address pair. 3022 * 3023 * In/out conditions: 3024 * The mapping must already exist in the pmap. 3025 */ 3026 void 3027 pmap_unwire(pmap_t pm, vaddr_t va) 3028 { 3029 struct l2_bucket *l2b; 3030 pt_entry_t *ptep, pte; 3031 struct vm_page *pg; 3032 paddr_t pa; 3033 3034 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 3035 3036 PMAP_MAP_TO_HEAD_LOCK(); 3037 pmap_acquire_pmap_lock(pm); 3038 3039 l2b = pmap_get_l2_bucket(pm, va); 3040 KDASSERT(l2b != NULL); 3041 3042 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3043 pte = *ptep; 3044 3045 /* Extract the physical address of the page */ 3046 pa = l2pte_pa(pte); 3047 3048 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3049 /* Update the wired bit in the pv entry for this page. */ 3050 simple_lock(&pg->mdpage.pvh_slock); 3051 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 3052 simple_unlock(&pg->mdpage.pvh_slock); 3053 } 3054 3055 pmap_release_pmap_lock(pm); 3056 PMAP_MAP_TO_HEAD_UNLOCK(); 3057 } 3058 3059 void 3060 pmap_switch(struct lwp *olwp, struct lwp *nlwp) 3061 { 3062 extern int block_userspace_access; 3063 pmap_t opm, npm, rpm; 3064 uint32_t odacr, ndacr; 3065 int oldirqstate; 3066 3067 npm = nlwp->l_proc->p_vmspace->vm_map.pmap; 3068 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3069 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 3070 3071 /* 3072 * If TTB and DACR are unchanged, short-circuit all the 3073 * TLB/cache management stuff. 3074 */ 3075 if (olwp != NULL) { 3076 opm = olwp->l_proc->p_vmspace->vm_map.pmap; 3077 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3078 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 3079 3080 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 3081 goto all_done; 3082 } else 3083 opm = NULL; 3084 3085 block_userspace_access = 1; 3086 3087 /* 3088 * If switching to a user vmspace which is different to the 3089 * most recent one, and the most recent one is potentially 3090 * live in the cache, we must write-back and invalidate the 3091 * entire cache. 3092 */ 3093 rpm = pmap_recent_user; 3094 if (npm != pmap_kernel() && rpm && npm != rpm && 3095 rpm->pm_cstate.cs_cache) { 3096 rpm->pm_cstate.cs_cache = 0; 3097 cpu_idcache_wbinv_all(); 3098 } 3099 3100 /* No interrupts while we frob the TTB/DACR */ 3101 oldirqstate = disable_interrupts(I32_bit | F32_bit); 3102 3103 /* 3104 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 3105 * entry corresponding to 'vector_page' in the incoming L1 table 3106 * before switching to it otherwise subsequent interrupts/exceptions 3107 * (including domain faults!) will jump into hyperspace. 3108 */ 3109 if (npm->pm_pl1vec != NULL) { 3110 cpu_tlb_flushID_SE((u_int)vector_page); 3111 cpu_cpwait(); 3112 *npm->pm_pl1vec = npm->pm_l1vec; 3113 PTE_SYNC(npm->pm_pl1vec); 3114 } 3115 3116 cpu_domains(ndacr); 3117 3118 if (npm == pmap_kernel() || npm == rpm) { 3119 /* 3120 * Switching to a kernel thread, or back to the 3121 * same user vmspace as before... Simply update 3122 * the TTB (no TLB flush required) 3123 */ 3124 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 3125 "r"(npm->pm_l1->l1_physaddr)); 3126 cpu_cpwait(); 3127 } else { 3128 /* 3129 * Otherwise, update TTB and flush TLB 3130 */ 3131 cpu_context_switch(npm->pm_l1->l1_physaddr); 3132 if (rpm != NULL) 3133 rpm->pm_cstate.cs_tlb = 0; 3134 } 3135 3136 restore_interrupts(oldirqstate); 3137 3138 block_userspace_access = 0; 3139 3140 all_done: 3141 /* 3142 * The new pmap is resident. Make sure it's marked 3143 * as resident in the cache/TLB. 3144 */ 3145 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3146 if (npm != pmap_kernel()) 3147 pmap_recent_user = npm; 3148 3149 /* The old pmap is not longer active */ 3150 if (opm != NULL) 3151 opm->pm_activated = false; 3152 3153 /* But the new one is */ 3154 npm->pm_activated = true; 3155 } 3156 3157 void 3158 pmap_activate(struct lwp *l) 3159 { 3160 3161 if (l == curlwp && 3162 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == false) 3163 pmap_switch(NULL, l); 3164 } 3165 3166 void 3167 pmap_deactivate(struct lwp *l) 3168 { 3169 3170 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 3171 } 3172 3173 void 3174 pmap_update(pmap_t pm) 3175 { 3176 3177 if (pm->pm_remove_all) { 3178 /* 3179 * Finish up the pmap_remove_all() optimisation by flushing 3180 * the TLB. 3181 */ 3182 pmap_tlb_flushID(pm); 3183 pm->pm_remove_all = false; 3184 } 3185 3186 if (pmap_is_current(pm)) { 3187 /* 3188 * If we're dealing with a current userland pmap, move its L1 3189 * to the end of the LRU. 3190 */ 3191 if (pm != pmap_kernel()) 3192 pmap_use_l1(pm); 3193 3194 /* 3195 * We can assume we're done with frobbing the cache/tlb for 3196 * now. Make sure any future pmap ops don't skip cache/tlb 3197 * flushes. 3198 */ 3199 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3200 } 3201 3202 /* 3203 * make sure TLB/cache operations have completed. 3204 */ 3205 cpu_cpwait(); 3206 } 3207 3208 void 3209 pmap_remove_all(pmap_t pm) 3210 { 3211 3212 /* 3213 * The vmspace described by this pmap is about to be torn down. 3214 * Until pmap_update() is called, UVM will only make calls 3215 * to pmap_remove(). We can make life much simpler by flushing 3216 * the cache now, and deferring TLB invalidation to pmap_update(). 3217 */ 3218 pmap_idcache_wbinv_all(pm); 3219 pm->pm_remove_all = true; 3220 } 3221 3222 /* 3223 * Retire the given physical map from service. 3224 * Should only be called if the map contains no valid mappings. 3225 */ 3226 void 3227 pmap_destroy(pmap_t pm) 3228 { 3229 u_int count; 3230 3231 if (pm == NULL) 3232 return; 3233 3234 if (pm->pm_remove_all) { 3235 pmap_tlb_flushID(pm); 3236 pm->pm_remove_all = false; 3237 } 3238 3239 /* 3240 * Drop reference count 3241 */ 3242 simple_lock(&pm->pm_lock); 3243 count = --pm->pm_obj.uo_refs; 3244 simple_unlock(&pm->pm_lock); 3245 if (count > 0) { 3246 if (pmap_is_current(pm)) { 3247 if (pm != pmap_kernel()) 3248 pmap_use_l1(pm); 3249 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3250 } 3251 return; 3252 } 3253 3254 /* 3255 * reference count is zero, free pmap resources and then free pmap. 3256 */ 3257 3258 if (vector_page < KERNEL_BASE) { 3259 KDASSERT(!pmap_is_current(pm)); 3260 3261 /* Remove the vector page mapping */ 3262 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 3263 pmap_update(pm); 3264 } 3265 3266 LIST_REMOVE(pm, pm_list); 3267 3268 pmap_free_l1(pm); 3269 3270 if (pmap_recent_user == pm) 3271 pmap_recent_user = NULL; 3272 3273 /* return the pmap to the pool */ 3274 pool_cache_put(&pmap_cache, pm); 3275 } 3276 3277 3278 /* 3279 * void pmap_reference(pmap_t pm) 3280 * 3281 * Add a reference to the specified pmap. 3282 */ 3283 void 3284 pmap_reference(pmap_t pm) 3285 { 3286 3287 if (pm == NULL) 3288 return; 3289 3290 pmap_use_l1(pm); 3291 3292 simple_lock(&pm->pm_lock); 3293 pm->pm_obj.uo_refs++; 3294 simple_unlock(&pm->pm_lock); 3295 } 3296 3297 /* 3298 * pmap_zero_page() 3299 * 3300 * Zero a given physical page by mapping it at a page hook point. 3301 * In doing the zero page op, the page we zero is mapped cachable, as with 3302 * StrongARM accesses to non-cached pages are non-burst making writing 3303 * _any_ bulk data very slow. 3304 */ 3305 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3306 void 3307 pmap_zero_page_generic(paddr_t phys) 3308 { 3309 #ifdef DEBUG 3310 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3311 3312 if (pg->mdpage.pvh_list != NULL) 3313 panic("pmap_zero_page: page has mappings"); 3314 #endif 3315 3316 KDASSERT((phys & PGOFSET) == 0); 3317 3318 /* 3319 * Hook in the page, zero it, and purge the cache for that 3320 * zeroed page. Invalidate the TLB as needed. 3321 */ 3322 *cdst_pte = L2_S_PROTO | phys | 3323 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3324 PTE_SYNC(cdst_pte); 3325 cpu_tlb_flushD_SE(cdstp); 3326 cpu_cpwait(); 3327 bzero_page(cdstp); 3328 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3329 } 3330 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3331 3332 #if ARM_MMU_XSCALE == 1 3333 void 3334 pmap_zero_page_xscale(paddr_t phys) 3335 { 3336 #ifdef DEBUG 3337 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3338 3339 if (pg->mdpage.pvh_list != NULL) 3340 panic("pmap_zero_page: page has mappings"); 3341 #endif 3342 3343 KDASSERT((phys & PGOFSET) == 0); 3344 3345 /* 3346 * Hook in the page, zero it, and purge the cache for that 3347 * zeroed page. Invalidate the TLB as needed. 3348 */ 3349 *cdst_pte = L2_S_PROTO | phys | 3350 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3351 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3352 PTE_SYNC(cdst_pte); 3353 cpu_tlb_flushD_SE(cdstp); 3354 cpu_cpwait(); 3355 bzero_page(cdstp); 3356 xscale_cache_clean_minidata(); 3357 } 3358 #endif /* ARM_MMU_XSCALE == 1 */ 3359 3360 /* pmap_pageidlezero() 3361 * 3362 * The same as above, except that we assume that the page is not 3363 * mapped. This means we never have to flush the cache first. Called 3364 * from the idle loop. 3365 */ 3366 bool 3367 pmap_pageidlezero(paddr_t phys) 3368 { 3369 unsigned int i; 3370 int *ptr; 3371 bool rv = true; 3372 #ifdef DEBUG 3373 struct vm_page *pg; 3374 3375 pg = PHYS_TO_VM_PAGE(phys); 3376 if (pg->mdpage.pvh_list != NULL) 3377 panic("pmap_pageidlezero: page has mappings"); 3378 #endif 3379 3380 KDASSERT((phys & PGOFSET) == 0); 3381 3382 /* 3383 * Hook in the page, zero it, and purge the cache for that 3384 * zeroed page. Invalidate the TLB as needed. 3385 */ 3386 *cdst_pte = L2_S_PROTO | phys | 3387 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3388 PTE_SYNC(cdst_pte); 3389 cpu_tlb_flushD_SE(cdstp); 3390 cpu_cpwait(); 3391 3392 for (i = 0, ptr = (int *)cdstp; 3393 i < (PAGE_SIZE / sizeof(int)); i++) { 3394 if (sched_curcpu_runnable_p()) { 3395 /* 3396 * A process has become ready. Abort now, 3397 * so we don't keep it waiting while we 3398 * do slow memory access to finish this 3399 * page. 3400 */ 3401 rv = false; 3402 break; 3403 } 3404 *ptr++ = 0; 3405 } 3406 3407 if (rv) 3408 /* 3409 * if we aborted we'll rezero this page again later so don't 3410 * purge it unless we finished it 3411 */ 3412 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3413 3414 return (rv); 3415 } 3416 3417 /* 3418 * pmap_copy_page() 3419 * 3420 * Copy one physical page into another, by mapping the pages into 3421 * hook points. The same comment regarding cachability as in 3422 * pmap_zero_page also applies here. 3423 */ 3424 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3425 void 3426 pmap_copy_page_generic(paddr_t src, paddr_t dst) 3427 { 3428 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 3429 #ifdef DEBUG 3430 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 3431 3432 if (dst_pg->mdpage.pvh_list != NULL) 3433 panic("pmap_copy_page: dst page has mappings"); 3434 #endif 3435 3436 KDASSERT((src & PGOFSET) == 0); 3437 KDASSERT((dst & PGOFSET) == 0); 3438 3439 /* 3440 * Clean the source page. Hold the source page's lock for 3441 * the duration of the copy so that no other mappings can 3442 * be created while we have a potentially aliased mapping. 3443 */ 3444 simple_lock(&src_pg->mdpage.pvh_slock); 3445 (void) pmap_clean_page(src_pg->mdpage.pvh_list, true); 3446 3447 /* 3448 * Map the pages into the page hook points, copy them, and purge 3449 * the cache for the appropriate page. Invalidate the TLB 3450 * as required. 3451 */ 3452 *csrc_pte = L2_S_PROTO | src | 3453 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 3454 PTE_SYNC(csrc_pte); 3455 *cdst_pte = L2_S_PROTO | dst | 3456 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3457 PTE_SYNC(cdst_pte); 3458 cpu_tlb_flushD_SE(csrcp); 3459 cpu_tlb_flushD_SE(cdstp); 3460 cpu_cpwait(); 3461 bcopy_page(csrcp, cdstp); 3462 cpu_dcache_inv_range(csrcp, PAGE_SIZE); 3463 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 3464 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3465 } 3466 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3467 3468 #if ARM_MMU_XSCALE == 1 3469 void 3470 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 3471 { 3472 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 3473 #ifdef DEBUG 3474 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 3475 3476 if (dst_pg->mdpage.pvh_list != NULL) 3477 panic("pmap_copy_page: dst page has mappings"); 3478 #endif 3479 3480 KDASSERT((src & PGOFSET) == 0); 3481 KDASSERT((dst & PGOFSET) == 0); 3482 3483 /* 3484 * Clean the source page. Hold the source page's lock for 3485 * the duration of the copy so that no other mappings can 3486 * be created while we have a potentially aliased mapping. 3487 */ 3488 simple_lock(&src_pg->mdpage.pvh_slock); 3489 (void) pmap_clean_page(src_pg->mdpage.pvh_list, true); 3490 3491 /* 3492 * Map the pages into the page hook points, copy them, and purge 3493 * the cache for the appropriate page. Invalidate the TLB 3494 * as required. 3495 */ 3496 *csrc_pte = L2_S_PROTO | src | 3497 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 3498 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3499 PTE_SYNC(csrc_pte); 3500 *cdst_pte = L2_S_PROTO | dst | 3501 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3502 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3503 PTE_SYNC(cdst_pte); 3504 cpu_tlb_flushD_SE(csrcp); 3505 cpu_tlb_flushD_SE(cdstp); 3506 cpu_cpwait(); 3507 bcopy_page(csrcp, cdstp); 3508 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 3509 xscale_cache_clean_minidata(); 3510 } 3511 #endif /* ARM_MMU_XSCALE == 1 */ 3512 3513 /* 3514 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 3515 * 3516 * Return the start and end addresses of the kernel's virtual space. 3517 * These values are setup in pmap_bootstrap and are updated as pages 3518 * are allocated. 3519 */ 3520 void 3521 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 3522 { 3523 *start = virtual_avail; 3524 *end = virtual_end; 3525 } 3526 3527 /* 3528 * Helper function for pmap_grow_l2_bucket() 3529 */ 3530 static inline int 3531 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 3532 { 3533 struct l2_bucket *l2b; 3534 pt_entry_t *ptep; 3535 paddr_t pa; 3536 3537 if (uvm.page_init_done == false) { 3538 if (uvm_page_physget(&pa) == false) 3539 return (1); 3540 } else { 3541 struct vm_page *pg; 3542 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 3543 if (pg == NULL) 3544 return (1); 3545 pa = VM_PAGE_TO_PHYS(pg); 3546 } 3547 3548 if (pap) 3549 *pap = pa; 3550 3551 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3552 KDASSERT(l2b != NULL); 3553 3554 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3555 *ptep = L2_S_PROTO | pa | cache_mode | 3556 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 3557 PTE_SYNC(ptep); 3558 memset((void *)va, 0, PAGE_SIZE); 3559 return (0); 3560 } 3561 3562 /* 3563 * This is the same as pmap_alloc_l2_bucket(), except that it is only 3564 * used by pmap_growkernel(). 3565 */ 3566 static inline struct l2_bucket * 3567 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 3568 { 3569 struct l2_dtable *l2; 3570 struct l2_bucket *l2b; 3571 u_short l1idx; 3572 vaddr_t nva; 3573 3574 l1idx = L1_IDX(va); 3575 3576 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 3577 /* 3578 * No mapping at this address, as there is 3579 * no entry in the L1 table. 3580 * Need to allocate a new l2_dtable. 3581 */ 3582 nva = pmap_kernel_l2dtable_kva; 3583 if ((nva & PGOFSET) == 0) { 3584 /* 3585 * Need to allocate a backing page 3586 */ 3587 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 3588 return (NULL); 3589 } 3590 3591 l2 = (struct l2_dtable *)nva; 3592 nva += sizeof(struct l2_dtable); 3593 3594 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 3595 /* 3596 * The new l2_dtable straddles a page boundary. 3597 * Map in another page to cover it. 3598 */ 3599 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 3600 return (NULL); 3601 } 3602 3603 pmap_kernel_l2dtable_kva = nva; 3604 3605 /* 3606 * Link it into the parent pmap 3607 */ 3608 pm->pm_l2[L2_IDX(l1idx)] = l2; 3609 } 3610 3611 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3612 3613 /* 3614 * Fetch pointer to the L2 page table associated with the address. 3615 */ 3616 if (l2b->l2b_kva == NULL) { 3617 pt_entry_t *ptep; 3618 3619 /* 3620 * No L2 page table has been allocated. Chances are, this 3621 * is because we just allocated the l2_dtable, above. 3622 */ 3623 nva = pmap_kernel_l2ptp_kva; 3624 ptep = (pt_entry_t *)nva; 3625 if ((nva & PGOFSET) == 0) { 3626 /* 3627 * Need to allocate a backing page 3628 */ 3629 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 3630 &pmap_kernel_l2ptp_phys)) 3631 return (NULL); 3632 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 3633 } 3634 3635 l2->l2_occupancy++; 3636 l2b->l2b_kva = ptep; 3637 l2b->l2b_l1idx = l1idx; 3638 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 3639 3640 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 3641 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 3642 } 3643 3644 return (l2b); 3645 } 3646 3647 vaddr_t 3648 pmap_growkernel(vaddr_t maxkvaddr) 3649 { 3650 pmap_t kpm = pmap_kernel(); 3651 struct l1_ttable *l1; 3652 struct l2_bucket *l2b; 3653 pd_entry_t *pl1pd; 3654 int s; 3655 3656 if (maxkvaddr <= pmap_curmaxkvaddr) 3657 goto out; /* we are OK */ 3658 3659 NPDEBUG(PDB_GROWKERN, 3660 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 3661 pmap_curmaxkvaddr, maxkvaddr)); 3662 3663 KDASSERT(maxkvaddr <= virtual_end); 3664 3665 /* 3666 * whoops! we need to add kernel PTPs 3667 */ 3668 3669 s = splhigh(); /* to be safe */ 3670 simple_lock(&kpm->pm_lock); 3671 3672 /* Map 1MB at a time */ 3673 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 3674 3675 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 3676 KDASSERT(l2b != NULL); 3677 3678 /* Distribute new L1 entry to all other L1s */ 3679 SLIST_FOREACH(l1, &l1_list, l1_link) { 3680 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 3681 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 3682 L1_C_PROTO; 3683 PTE_SYNC(pl1pd); 3684 } 3685 } 3686 3687 /* 3688 * flush out the cache, expensive but growkernel will happen so 3689 * rarely 3690 */ 3691 cpu_dcache_wbinv_all(); 3692 cpu_tlb_flushD(); 3693 cpu_cpwait(); 3694 3695 simple_unlock(&kpm->pm_lock); 3696 splx(s); 3697 3698 out: 3699 return (pmap_curmaxkvaddr); 3700 } 3701 3702 /************************ Utility routines ****************************/ 3703 3704 /* 3705 * vector_page_setprot: 3706 * 3707 * Manipulate the protection of the vector page. 3708 */ 3709 void 3710 vector_page_setprot(int prot) 3711 { 3712 struct l2_bucket *l2b; 3713 pt_entry_t *ptep; 3714 3715 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 3716 KDASSERT(l2b != NULL); 3717 3718 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 3719 3720 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 3721 PTE_SYNC(ptep); 3722 cpu_tlb_flushD_SE(vector_page); 3723 cpu_cpwait(); 3724 } 3725 3726 /* 3727 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3728 * Returns true if the mapping exists, else false. 3729 * 3730 * NOTE: This function is only used by a couple of arm-specific modules. 3731 * It is not safe to take any pmap locks here, since we could be right 3732 * in the middle of debugging the pmap anyway... 3733 * 3734 * It is possible for this routine to return false even though a valid 3735 * mapping does exist. This is because we don't lock, so the metadata 3736 * state may be inconsistent. 3737 * 3738 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3739 * a "section" mapping. 3740 */ 3741 bool 3742 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3743 { 3744 struct l2_dtable *l2; 3745 pd_entry_t *pl1pd, l1pd; 3746 pt_entry_t *ptep; 3747 u_short l1idx; 3748 3749 if (pm->pm_l1 == NULL) 3750 return (false); 3751 3752 l1idx = L1_IDX(va); 3753 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3754 l1pd = *pl1pd; 3755 3756 if (l1pte_section_p(l1pd)) { 3757 *ptp = NULL; 3758 return (true); 3759 } 3760 3761 if (pm->pm_l2 == NULL) 3762 return (false); 3763 3764 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3765 3766 if (l2 == NULL || 3767 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3768 return (false); 3769 } 3770 3771 *ptp = &ptep[l2pte_index(va)]; 3772 return (true); 3773 } 3774 3775 bool 3776 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 3777 { 3778 u_short l1idx; 3779 3780 if (pm->pm_l1 == NULL) 3781 return (false); 3782 3783 l1idx = L1_IDX(va); 3784 *pdp = &pm->pm_l1->l1_kva[l1idx]; 3785 3786 return (true); 3787 } 3788 3789 /************************ Bootstrapping routines ****************************/ 3790 3791 static void 3792 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 3793 { 3794 int i; 3795 3796 l1->l1_kva = l1pt; 3797 l1->l1_domain_use_count = 0; 3798 l1->l1_domain_first = 0; 3799 3800 for (i = 0; i < PMAP_DOMAINS; i++) 3801 l1->l1_domain_free[i] = i + 1; 3802 3803 /* 3804 * Copy the kernel's L1 entries to each new L1. 3805 */ 3806 if (pmap_initialized) 3807 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 3808 3809 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 3810 &l1->l1_physaddr) == false) 3811 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 3812 3813 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 3814 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 3815 } 3816 3817 /* 3818 * pmap_bootstrap() is called from the board-specific initarm() routine 3819 * once the kernel L1/L2 descriptors tables have been set up. 3820 * 3821 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 3822 * spread over a number of disparate files/functions. 3823 * 3824 * We are passed the following parameters 3825 * - kernel_l1pt 3826 * This is a pointer to the base of the kernel's L1 translation table. 3827 * - vstart 3828 * 1MB-aligned start of managed kernel virtual memory. 3829 * - vend 3830 * 1MB-aligned end of managed kernel virtual memory. 3831 * 3832 * We use the first parameter to build the metadata (struct l1_ttable and 3833 * struct l2_dtable) necessary to track kernel mappings. 3834 */ 3835 #define PMAP_STATIC_L2_SIZE 16 3836 void 3837 pmap_bootstrap(pd_entry_t *kernel_l1pt, vaddr_t vstart, vaddr_t vend) 3838 { 3839 static struct l1_ttable static_l1; 3840 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 3841 struct l1_ttable *l1 = &static_l1; 3842 struct l2_dtable *l2; 3843 struct l2_bucket *l2b; 3844 pmap_t pm = pmap_kernel(); 3845 pd_entry_t pde; 3846 pt_entry_t *ptep; 3847 paddr_t pa; 3848 vaddr_t va; 3849 vsize_t size; 3850 int l1idx, l2idx, l2next = 0; 3851 3852 /* 3853 * Initialise the kernel pmap object 3854 */ 3855 pm->pm_l1 = l1; 3856 pm->pm_domain = PMAP_DOMAIN_KERNEL; 3857 pm->pm_activated = true; 3858 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3859 simple_lock_init(&pm->pm_lock); 3860 pm->pm_obj.pgops = NULL; 3861 TAILQ_INIT(&pm->pm_obj.memq); 3862 pm->pm_obj.uo_npages = 0; 3863 pm->pm_obj.uo_refs = 1; 3864 3865 /* 3866 * Scan the L1 translation table created by initarm() and create 3867 * the required metadata for all valid mappings found in it. 3868 */ 3869 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 3870 pde = kernel_l1pt[l1idx]; 3871 3872 /* 3873 * We're only interested in Coarse mappings. 3874 * pmap_extract() can deal with section mappings without 3875 * recourse to checking L2 metadata. 3876 */ 3877 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 3878 continue; 3879 3880 /* 3881 * Lookup the KVA of this L2 descriptor table 3882 */ 3883 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 3884 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 3885 if (ptep == NULL) { 3886 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 3887 (u_int)l1idx << L1_S_SHIFT, pa); 3888 } 3889 3890 /* 3891 * Fetch the associated L2 metadata structure. 3892 * Allocate a new one if necessary. 3893 */ 3894 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 3895 if (l2next == PMAP_STATIC_L2_SIZE) 3896 panic("pmap_bootstrap: out of static L2s"); 3897 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 3898 } 3899 3900 /* 3901 * One more L1 slot tracked... 3902 */ 3903 l2->l2_occupancy++; 3904 3905 /* 3906 * Fill in the details of the L2 descriptor in the 3907 * appropriate bucket. 3908 */ 3909 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3910 l2b->l2b_kva = ptep; 3911 l2b->l2b_phys = pa; 3912 l2b->l2b_l1idx = l1idx; 3913 3914 /* 3915 * Establish an initial occupancy count for this descriptor 3916 */ 3917 for (l2idx = 0; 3918 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 3919 l2idx++) { 3920 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 3921 l2b->l2b_occupancy++; 3922 } 3923 } 3924 3925 /* 3926 * Make sure the descriptor itself has the correct cache mode. 3927 * If not, fix it, but whine about the problem. Port-meisters 3928 * should consider this a clue to fix up their initarm() 3929 * function. :) 3930 */ 3931 if (pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)ptep)) { 3932 printf("pmap_bootstrap: WARNING! wrong cache mode for " 3933 "L2 pte @ %p\n", ptep); 3934 } 3935 } 3936 3937 /* 3938 * Ensure the primary (kernel) L1 has the correct cache mode for 3939 * a page table. Bitch if it is not correctly set. 3940 */ 3941 for (va = (vaddr_t)kernel_l1pt; 3942 va < ((vaddr_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 3943 if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 3944 printf("pmap_bootstrap: WARNING! wrong cache mode for " 3945 "primary L1 @ 0x%lx\n", va); 3946 } 3947 3948 cpu_dcache_wbinv_all(); 3949 cpu_tlb_flushID(); 3950 cpu_cpwait(); 3951 3952 /* 3953 * now we allocate the "special" VAs which are used for tmp mappings 3954 * by the pmap (and other modules). we allocate the VAs by advancing 3955 * virtual_avail (note that there are no pages mapped at these VAs). 3956 * 3957 * Managed KVM space start from wherever initarm() tells us. 3958 */ 3959 virtual_avail = vstart; 3960 virtual_end = vend; 3961 3962 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 3963 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)csrc_pte); 3964 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 3965 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)cdst_pte); 3966 pmap_alloc_specials(&virtual_avail, 1, (void *)&memhook, NULL); 3967 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 3968 (void *)&msgbufaddr, NULL); 3969 3970 /* 3971 * Allocate a range of kernel virtual address space to be used 3972 * for L2 descriptor tables and metadata allocation in 3973 * pmap_growkernel(). 3974 */ 3975 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 3976 pmap_alloc_specials(&virtual_avail, 3977 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 3978 &pmap_kernel_l2ptp_kva, NULL); 3979 3980 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 3981 pmap_alloc_specials(&virtual_avail, 3982 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 3983 &pmap_kernel_l2dtable_kva, NULL); 3984 3985 /* 3986 * init the static-global locks and global pmap list. 3987 */ 3988 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 3989 3990 /* 3991 * We can now initialise the first L1's metadata. 3992 */ 3993 SLIST_INIT(&l1_list); 3994 TAILQ_INIT(&l1_lru_list); 3995 simple_lock_init(&l1_lru_lock); 3996 pmap_init_l1(l1, kernel_l1pt); 3997 3998 /* Set up vector page L1 details, if necessary */ 3999 if (vector_page < KERNEL_BASE) { 4000 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 4001 l2b = pmap_get_l2_bucket(pm, vector_page); 4002 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 4003 L1_C_DOM(pm->pm_domain); 4004 } else 4005 pm->pm_pl1vec = NULL; 4006 4007 /* 4008 * Initialize the pmap cache 4009 */ 4010 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 4011 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 4012 LIST_INIT(&pmap_pmaps); 4013 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 4014 4015 /* 4016 * Initialize the pv pool. 4017 */ 4018 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 4019 &pmap_bootstrap_pv_allocator, IPL_NONE); 4020 4021 /* 4022 * Initialize the L2 dtable pool and cache. 4023 */ 4024 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 4025 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 4026 4027 /* 4028 * Initialise the L2 descriptor table pool and cache 4029 */ 4030 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 4031 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 4032 pmap_l2ptp_ctor, NULL, NULL); 4033 4034 cpu_dcache_wbinv_all(); 4035 } 4036 4037 static int 4038 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 4039 { 4040 pd_entry_t *pdep, pde; 4041 pt_entry_t *ptep, pte; 4042 vaddr_t pa; 4043 int rv = 0; 4044 4045 /* 4046 * Make sure the descriptor itself has the correct cache mode 4047 */ 4048 pdep = &kl1[L1_IDX(va)]; 4049 pde = *pdep; 4050 4051 if (l1pte_section_p(pde)) { 4052 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 4053 *pdep = (pde & ~L1_S_CACHE_MASK) | 4054 pte_l1_s_cache_mode_pt; 4055 PTE_SYNC(pdep); 4056 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 4057 rv = 1; 4058 } 4059 } else { 4060 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 4061 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 4062 if (ptep == NULL) 4063 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 4064 4065 ptep = &ptep[l2pte_index(va)]; 4066 pte = *ptep; 4067 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 4068 *ptep = (pte & ~L2_S_CACHE_MASK) | 4069 pte_l2_s_cache_mode_pt; 4070 PTE_SYNC(ptep); 4071 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 4072 rv = 1; 4073 } 4074 } 4075 4076 return (rv); 4077 } 4078 4079 static void 4080 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 4081 { 4082 vaddr_t va = *availp; 4083 struct l2_bucket *l2b; 4084 4085 if (ptep) { 4086 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4087 if (l2b == NULL) 4088 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 4089 4090 if (ptep) 4091 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 4092 } 4093 4094 *vap = va; 4095 *availp = va + (PAGE_SIZE * pages); 4096 } 4097 4098 void 4099 pmap_init(void) 4100 { 4101 extern int physmem; 4102 4103 /* 4104 * Set the available memory vars - These do not map to real memory 4105 * addresses and cannot as the physical memory is fragmented. 4106 * They are used by ps for %mem calculations. 4107 * One could argue whether this should be the entire memory or just 4108 * the memory that is useable in a user process. 4109 */ 4110 avail_start = 0; 4111 avail_end = physmem * PAGE_SIZE; 4112 4113 /* 4114 * Now we need to free enough pv_entry structures to allow us to get 4115 * the kmem_map/kmem_object allocated and inited (done after this 4116 * function is finished). to do this we allocate one bootstrap page out 4117 * of kernel_map and use it to provide an initial pool of pv_entry 4118 * structures. we never free this page. 4119 */ 4120 pool_setlowat(&pmap_pv_pool, 4121 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 4122 4123 pmap_initialized = true; 4124 } 4125 4126 static vaddr_t last_bootstrap_page = 0; 4127 static void *free_bootstrap_pages = NULL; 4128 4129 static void * 4130 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 4131 { 4132 extern void *pool_page_alloc(struct pool *, int); 4133 vaddr_t new_page; 4134 void *rv; 4135 4136 if (pmap_initialized) 4137 return (pool_page_alloc(pp, flags)); 4138 4139 if (free_bootstrap_pages) { 4140 rv = free_bootstrap_pages; 4141 free_bootstrap_pages = *((void **)rv); 4142 return (rv); 4143 } 4144 4145 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 4146 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 4147 4148 KASSERT(new_page > last_bootstrap_page); 4149 last_bootstrap_page = new_page; 4150 return ((void *)new_page); 4151 } 4152 4153 static void 4154 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 4155 { 4156 extern void pool_page_free(struct pool *, void *); 4157 4158 if ((vaddr_t)v <= last_bootstrap_page) { 4159 *((void **)v) = free_bootstrap_pages; 4160 free_bootstrap_pages = v; 4161 return; 4162 } 4163 4164 if (pmap_initialized) { 4165 pool_page_free(pp, v); 4166 return; 4167 } 4168 } 4169 4170 /* 4171 * pmap_postinit() 4172 * 4173 * This routine is called after the vm and kmem subsystems have been 4174 * initialised. This allows the pmap code to perform any initialisation 4175 * that can only be done one the memory allocation is in place. 4176 */ 4177 void 4178 pmap_postinit(void) 4179 { 4180 extern paddr_t physical_start, physical_end; 4181 struct l2_bucket *l2b; 4182 struct l1_ttable *l1; 4183 struct pglist plist; 4184 struct vm_page *m; 4185 pd_entry_t *pl1pt; 4186 pt_entry_t *ptep, pte; 4187 vaddr_t va, eva; 4188 u_int loop, needed; 4189 int error; 4190 4191 pool_cache_setlowat(&pmap_l2ptp_cache, 4192 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 4193 pool_cache_setlowat(&pmap_l2dtable_cache, 4194 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 4195 4196 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 4197 needed -= 1; 4198 4199 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 4200 4201 for (loop = 0; loop < needed; loop++, l1++) { 4202 /* Allocate a L1 page table */ 4203 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 4204 if (va == 0) 4205 panic("Cannot allocate L1 KVM"); 4206 4207 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 4208 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 4209 if (error) 4210 panic("Cannot allocate L1 physical pages"); 4211 4212 m = TAILQ_FIRST(&plist); 4213 eva = va + L1_TABLE_SIZE; 4214 pl1pt = (pd_entry_t *)va; 4215 4216 while (m && va < eva) { 4217 paddr_t pa = VM_PAGE_TO_PHYS(m); 4218 4219 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 4220 4221 /* 4222 * Make sure the L1 descriptor table is mapped 4223 * with the cache-mode set to write-through. 4224 */ 4225 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4226 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4227 pte = *ptep; 4228 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 4229 *ptep = pte; 4230 PTE_SYNC(ptep); 4231 cpu_tlb_flushD_SE(va); 4232 4233 va += PAGE_SIZE; 4234 m = TAILQ_NEXT(m, pageq); 4235 } 4236 4237 #ifdef DIAGNOSTIC 4238 if (m) 4239 panic("pmap_alloc_l1pt: pglist not empty"); 4240 #endif /* DIAGNOSTIC */ 4241 4242 pmap_init_l1(l1, pl1pt); 4243 } 4244 4245 #ifdef DEBUG 4246 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 4247 needed); 4248 #endif 4249 } 4250 4251 /* 4252 * Note that the following routines are used by board-specific initialisation 4253 * code to configure the initial kernel page tables. 4254 * 4255 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 4256 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 4257 * behaviour of the old pmap, and provides an easy migration path for 4258 * initial bring-up of the new pmap on existing ports. Fortunately, 4259 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 4260 * will be deprecated. 4261 * 4262 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 4263 * tables. 4264 */ 4265 4266 /* 4267 * This list exists for the benefit of pmap_map_chunk(). It keeps track 4268 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 4269 * find them as necessary. 4270 * 4271 * Note that the data on this list MUST remain valid after initarm() returns, 4272 * as pmap_bootstrap() uses it to contruct L2 table metadata. 4273 */ 4274 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 4275 4276 static vaddr_t 4277 kernel_pt_lookup(paddr_t pa) 4278 { 4279 pv_addr_t *pv; 4280 4281 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 4282 #ifndef ARM32_NEW_VM_LAYOUT 4283 if (pv->pv_pa == (pa & ~PGOFSET)) 4284 return (pv->pv_va | (pa & PGOFSET)); 4285 #else 4286 if (pv->pv_pa == pa) 4287 return (pv->pv_va); 4288 #endif 4289 } 4290 return (0); 4291 } 4292 4293 /* 4294 * pmap_map_section: 4295 * 4296 * Create a single section mapping. 4297 */ 4298 void 4299 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 4300 { 4301 pd_entry_t *pde = (pd_entry_t *) l1pt; 4302 pd_entry_t fl; 4303 4304 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 4305 4306 switch (cache) { 4307 case PTE_NOCACHE: 4308 default: 4309 fl = 0; 4310 break; 4311 4312 case PTE_CACHE: 4313 fl = pte_l1_s_cache_mode; 4314 break; 4315 4316 case PTE_PAGETABLE: 4317 fl = pte_l1_s_cache_mode_pt; 4318 break; 4319 } 4320 4321 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4322 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4323 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4324 } 4325 4326 /* 4327 * pmap_map_entry: 4328 * 4329 * Create a single page mapping. 4330 */ 4331 void 4332 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 4333 { 4334 pd_entry_t *pde = (pd_entry_t *) l1pt; 4335 pt_entry_t fl; 4336 pt_entry_t *pte; 4337 4338 KASSERT(((va | pa) & PGOFSET) == 0); 4339 4340 switch (cache) { 4341 case PTE_NOCACHE: 4342 default: 4343 fl = 0; 4344 break; 4345 4346 case PTE_CACHE: 4347 fl = pte_l2_s_cache_mode; 4348 break; 4349 4350 case PTE_PAGETABLE: 4351 fl = pte_l2_s_cache_mode_pt; 4352 break; 4353 } 4354 4355 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4356 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 4357 4358 #ifndef ARM32_NEW_VM_LAYOUT 4359 pte = (pt_entry_t *) 4360 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4361 #else 4362 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4363 #endif 4364 if (pte == NULL) 4365 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 4366 4367 #ifndef ARM32_NEW_VM_LAYOUT 4368 pte[(va >> PGSHIFT) & 0x3ff] = 4369 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4370 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 4371 #else 4372 pte[l2pte_index(va)] = 4373 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4374 PTE_SYNC(&pte[l2pte_index(va)]); 4375 #endif 4376 } 4377 4378 /* 4379 * pmap_link_l2pt: 4380 * 4381 * Link the L2 page table specified by "l2pv" into the L1 4382 * page table at the slot for "va". 4383 */ 4384 void 4385 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 4386 { 4387 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4388 u_int slot = va >> L1_S_SHIFT; 4389 4390 #ifndef ARM32_NEW_VM_LAYOUT 4391 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 4392 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 4393 #endif 4394 4395 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4396 4397 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4398 #ifdef ARM32_NEW_VM_LAYOUT 4399 PTE_SYNC(&pde[slot]); 4400 #else 4401 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 4402 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 4403 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 4404 PTE_SYNC_RANGE(&pde[slot + 0], 4); 4405 #endif 4406 4407 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4408 } 4409 4410 /* 4411 * pmap_map_chunk: 4412 * 4413 * Map a chunk of memory using the most efficient mappings 4414 * possible (section, large page, small page) into the 4415 * provided L1 and L2 tables at the specified virtual address. 4416 */ 4417 vsize_t 4418 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 4419 int prot, int cache) 4420 { 4421 pd_entry_t *pde = (pd_entry_t *) l1pt; 4422 pt_entry_t *pte, f1, f2s, f2l; 4423 vsize_t resid; 4424 int i; 4425 4426 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4427 4428 if (l1pt == 0) 4429 panic("pmap_map_chunk: no L1 table provided"); 4430 4431 #ifdef VERBOSE_INIT_ARM 4432 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 4433 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4434 #endif 4435 4436 switch (cache) { 4437 case PTE_NOCACHE: 4438 default: 4439 f1 = 0; 4440 f2l = 0; 4441 f2s = 0; 4442 break; 4443 4444 case PTE_CACHE: 4445 f1 = pte_l1_s_cache_mode; 4446 f2l = pte_l2_l_cache_mode; 4447 f2s = pte_l2_s_cache_mode; 4448 break; 4449 4450 case PTE_PAGETABLE: 4451 f1 = pte_l1_s_cache_mode_pt; 4452 f2l = pte_l2_l_cache_mode_pt; 4453 f2s = pte_l2_s_cache_mode_pt; 4454 break; 4455 } 4456 4457 size = resid; 4458 4459 while (resid > 0) { 4460 /* See if we can use a section mapping. */ 4461 if (L1_S_MAPPABLE_P(va, pa, resid)) { 4462 #ifdef VERBOSE_INIT_ARM 4463 printf("S"); 4464 #endif 4465 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4466 L1_S_PROT(PTE_KERNEL, prot) | f1 | 4467 L1_S_DOM(PMAP_DOMAIN_KERNEL); 4468 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4469 va += L1_S_SIZE; 4470 pa += L1_S_SIZE; 4471 resid -= L1_S_SIZE; 4472 continue; 4473 } 4474 4475 /* 4476 * Ok, we're going to use an L2 table. Make sure 4477 * one is actually in the corresponding L1 slot 4478 * for the current VA. 4479 */ 4480 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4481 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 4482 4483 #ifndef ARM32_NEW_VM_LAYOUT 4484 pte = (pt_entry_t *) 4485 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4486 #else 4487 pte = (pt_entry_t *) kernel_pt_lookup( 4488 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4489 #endif 4490 if (pte == NULL) 4491 panic("pmap_map_chunk: can't find L2 table for VA" 4492 "0x%08lx", va); 4493 4494 /* See if we can use a L2 large page mapping. */ 4495 if (L2_L_MAPPABLE_P(va, pa, resid)) { 4496 #ifdef VERBOSE_INIT_ARM 4497 printf("L"); 4498 #endif 4499 for (i = 0; i < 16; i++) { 4500 #ifndef ARM32_NEW_VM_LAYOUT 4501 pte[((va >> PGSHIFT) & 0x3f0) + i] = 4502 L2_L_PROTO | pa | 4503 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4504 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 4505 #else 4506 pte[l2pte_index(va) + i] = 4507 L2_L_PROTO | pa | 4508 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4509 PTE_SYNC(&pte[l2pte_index(va) + i]); 4510 #endif 4511 } 4512 va += L2_L_SIZE; 4513 pa += L2_L_SIZE; 4514 resid -= L2_L_SIZE; 4515 continue; 4516 } 4517 4518 /* Use a small page mapping. */ 4519 #ifdef VERBOSE_INIT_ARM 4520 printf("P"); 4521 #endif 4522 #ifndef ARM32_NEW_VM_LAYOUT 4523 pte[(va >> PGSHIFT) & 0x3ff] = 4524 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4525 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 4526 #else 4527 pte[l2pte_index(va)] = 4528 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4529 PTE_SYNC(&pte[l2pte_index(va)]); 4530 #endif 4531 va += PAGE_SIZE; 4532 pa += PAGE_SIZE; 4533 resid -= PAGE_SIZE; 4534 } 4535 #ifdef VERBOSE_INIT_ARM 4536 printf("\n"); 4537 #endif 4538 return (size); 4539 } 4540 4541 /********************** Static device map routines ***************************/ 4542 4543 static const struct pmap_devmap *pmap_devmap_table; 4544 4545 /* 4546 * Register the devmap table. This is provided in case early console 4547 * initialization needs to register mappings created by bootstrap code 4548 * before pmap_devmap_bootstrap() is called. 4549 */ 4550 void 4551 pmap_devmap_register(const struct pmap_devmap *table) 4552 { 4553 4554 pmap_devmap_table = table; 4555 } 4556 4557 /* 4558 * Map all of the static regions in the devmap table, and remember 4559 * the devmap table so other parts of the kernel can look up entries 4560 * later. 4561 */ 4562 void 4563 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 4564 { 4565 int i; 4566 4567 pmap_devmap_table = table; 4568 4569 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4570 #ifdef VERBOSE_INIT_ARM 4571 printf("devmap: %08lx -> %08lx @ %08lx\n", 4572 pmap_devmap_table[i].pd_pa, 4573 pmap_devmap_table[i].pd_pa + 4574 pmap_devmap_table[i].pd_size - 1, 4575 pmap_devmap_table[i].pd_va); 4576 #endif 4577 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4578 pmap_devmap_table[i].pd_pa, 4579 pmap_devmap_table[i].pd_size, 4580 pmap_devmap_table[i].pd_prot, 4581 pmap_devmap_table[i].pd_cache); 4582 } 4583 } 4584 4585 const struct pmap_devmap * 4586 pmap_devmap_find_pa(paddr_t pa, psize_t size) 4587 { 4588 uint64_t endpa; 4589 int i; 4590 4591 if (pmap_devmap_table == NULL) 4592 return (NULL); 4593 4594 endpa = (uint64_t)pa + (uint64_t)(size - 1); 4595 4596 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4597 if (pa >= pmap_devmap_table[i].pd_pa && 4598 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 4599 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 4600 return (&pmap_devmap_table[i]); 4601 } 4602 4603 return (NULL); 4604 } 4605 4606 const struct pmap_devmap * 4607 pmap_devmap_find_va(vaddr_t va, vsize_t size) 4608 { 4609 int i; 4610 4611 if (pmap_devmap_table == NULL) 4612 return (NULL); 4613 4614 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4615 if (va >= pmap_devmap_table[i].pd_va && 4616 va + size - 1 <= pmap_devmap_table[i].pd_va + 4617 pmap_devmap_table[i].pd_size - 1) 4618 return (&pmap_devmap_table[i]); 4619 } 4620 4621 return (NULL); 4622 } 4623 4624 /********************** PTE initialization routines **************************/ 4625 4626 /* 4627 * These routines are called when the CPU type is identified to set up 4628 * the PTE prototypes, cache modes, etc. 4629 * 4630 * The variables are always here, just in case LKMs need to reference 4631 * them (though, they shouldn't). 4632 */ 4633 4634 pt_entry_t pte_l1_s_cache_mode; 4635 pt_entry_t pte_l1_s_cache_mode_pt; 4636 pt_entry_t pte_l1_s_cache_mask; 4637 4638 pt_entry_t pte_l2_l_cache_mode; 4639 pt_entry_t pte_l2_l_cache_mode_pt; 4640 pt_entry_t pte_l2_l_cache_mask; 4641 4642 pt_entry_t pte_l2_s_cache_mode; 4643 pt_entry_t pte_l2_s_cache_mode_pt; 4644 pt_entry_t pte_l2_s_cache_mask; 4645 4646 pt_entry_t pte_l2_s_prot_u; 4647 pt_entry_t pte_l2_s_prot_w; 4648 pt_entry_t pte_l2_s_prot_mask; 4649 4650 pt_entry_t pte_l1_s_proto; 4651 pt_entry_t pte_l1_c_proto; 4652 pt_entry_t pte_l2_s_proto; 4653 4654 void (*pmap_copy_page_func)(paddr_t, paddr_t); 4655 void (*pmap_zero_page_func)(paddr_t); 4656 4657 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 4658 void 4659 pmap_pte_init_generic(void) 4660 { 4661 4662 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 4663 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 4664 4665 pte_l2_l_cache_mode = L2_B|L2_C; 4666 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 4667 4668 pte_l2_s_cache_mode = L2_B|L2_C; 4669 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 4670 4671 /* 4672 * If we have a write-through cache, set B and C. If 4673 * we have a write-back cache, then we assume setting 4674 * only C will make those pages write-through. 4675 */ 4676 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 4677 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 4678 pte_l2_l_cache_mode_pt = L2_B|L2_C; 4679 pte_l2_s_cache_mode_pt = L2_B|L2_C; 4680 } else { 4681 pte_l1_s_cache_mode_pt = L1_S_C; 4682 pte_l2_l_cache_mode_pt = L2_C; 4683 pte_l2_s_cache_mode_pt = L2_C; 4684 } 4685 4686 pte_l2_s_prot_u = L2_S_PROT_U_generic; 4687 pte_l2_s_prot_w = L2_S_PROT_W_generic; 4688 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 4689 4690 pte_l1_s_proto = L1_S_PROTO_generic; 4691 pte_l1_c_proto = L1_C_PROTO_generic; 4692 pte_l2_s_proto = L2_S_PROTO_generic; 4693 4694 pmap_copy_page_func = pmap_copy_page_generic; 4695 pmap_zero_page_func = pmap_zero_page_generic; 4696 } 4697 4698 #if defined(CPU_ARM8) 4699 void 4700 pmap_pte_init_arm8(void) 4701 { 4702 4703 /* 4704 * ARM8 is compatible with generic, but we need to use 4705 * the page tables uncached. 4706 */ 4707 pmap_pte_init_generic(); 4708 4709 pte_l1_s_cache_mode_pt = 0; 4710 pte_l2_l_cache_mode_pt = 0; 4711 pte_l2_s_cache_mode_pt = 0; 4712 } 4713 #endif /* CPU_ARM8 */ 4714 4715 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 4716 void 4717 pmap_pte_init_arm9(void) 4718 { 4719 4720 /* 4721 * ARM9 is compatible with generic, but we want to use 4722 * write-through caching for now. 4723 */ 4724 pmap_pte_init_generic(); 4725 4726 pte_l1_s_cache_mode = L1_S_C; 4727 pte_l2_l_cache_mode = L2_C; 4728 pte_l2_s_cache_mode = L2_C; 4729 4730 pte_l1_s_cache_mode_pt = L1_S_C; 4731 pte_l2_l_cache_mode_pt = L2_C; 4732 pte_l2_s_cache_mode_pt = L2_C; 4733 } 4734 #endif /* CPU_ARM9 */ 4735 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4736 4737 #if defined(CPU_ARM10) 4738 void 4739 pmap_pte_init_arm10(void) 4740 { 4741 4742 /* 4743 * ARM10 is compatible with generic, but we want to use 4744 * write-through caching for now. 4745 */ 4746 pmap_pte_init_generic(); 4747 4748 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 4749 pte_l2_l_cache_mode = L2_B | L2_C; 4750 pte_l2_s_cache_mode = L2_B | L2_C; 4751 4752 pte_l1_s_cache_mode_pt = L1_S_C; 4753 pte_l2_l_cache_mode_pt = L2_C; 4754 pte_l2_s_cache_mode_pt = L2_C; 4755 4756 } 4757 #endif /* CPU_ARM10 */ 4758 4759 #if ARM_MMU_SA1 == 1 4760 void 4761 pmap_pte_init_sa1(void) 4762 { 4763 4764 /* 4765 * The StrongARM SA-1 cache does not have a write-through 4766 * mode. So, do the generic initialization, then reset 4767 * the page table cache mode to B=1,C=1, and note that 4768 * the PTEs need to be sync'd. 4769 */ 4770 pmap_pte_init_generic(); 4771 4772 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 4773 pte_l2_l_cache_mode_pt = L2_B|L2_C; 4774 pte_l2_s_cache_mode_pt = L2_B|L2_C; 4775 4776 pmap_needs_pte_sync = 1; 4777 } 4778 #endif /* ARM_MMU_SA1 == 1*/ 4779 4780 #if ARM_MMU_XSCALE == 1 4781 #if (ARM_NMMUS > 1) 4782 static u_int xscale_use_minidata; 4783 #endif 4784 4785 void 4786 pmap_pte_init_xscale(void) 4787 { 4788 uint32_t auxctl; 4789 int write_through = 0; 4790 4791 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 4792 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 4793 4794 pte_l2_l_cache_mode = L2_B|L2_C; 4795 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 4796 4797 pte_l2_s_cache_mode = L2_B|L2_C; 4798 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 4799 4800 pte_l1_s_cache_mode_pt = L1_S_C; 4801 pte_l2_l_cache_mode_pt = L2_C; 4802 pte_l2_s_cache_mode_pt = L2_C; 4803 4804 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 4805 /* 4806 * The XScale core has an enhanced mode where writes that 4807 * miss the cache cause a cache line to be allocated. This 4808 * is significantly faster than the traditional, write-through 4809 * behavior of this case. 4810 */ 4811 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 4812 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 4813 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 4814 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 4815 4816 #ifdef XSCALE_CACHE_WRITE_THROUGH 4817 /* 4818 * Some versions of the XScale core have various bugs in 4819 * their cache units, the work-around for which is to run 4820 * the cache in write-through mode. Unfortunately, this 4821 * has a major (negative) impact on performance. So, we 4822 * go ahead and run fast-and-loose, in the hopes that we 4823 * don't line up the planets in a way that will trip the 4824 * bugs. 4825 * 4826 * However, we give you the option to be slow-but-correct. 4827 */ 4828 write_through = 1; 4829 #elif defined(XSCALE_CACHE_WRITE_BACK) 4830 /* force write back cache mode */ 4831 write_through = 0; 4832 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 4833 /* 4834 * Intel PXA2[15]0 processors are known to have a bug in 4835 * write-back cache on revision 4 and earlier (stepping 4836 * A[01] and B[012]). Fixed for C0 and later. 4837 */ 4838 { 4839 uint32_t id, type; 4840 4841 id = cpufunc_id(); 4842 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 4843 4844 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 4845 if ((id & CPU_ID_REVISION_MASK) < 5) { 4846 /* write through for stepping A0-1 and B0-2 */ 4847 write_through = 1; 4848 } 4849 } 4850 } 4851 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 4852 4853 if (write_through) { 4854 pte_l1_s_cache_mode = L1_S_C; 4855 pte_l2_l_cache_mode = L2_C; 4856 pte_l2_s_cache_mode = L2_C; 4857 } 4858 4859 #if (ARM_NMMUS > 1) 4860 xscale_use_minidata = 1; 4861 #endif 4862 4863 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 4864 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 4865 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 4866 4867 pte_l1_s_proto = L1_S_PROTO_xscale; 4868 pte_l1_c_proto = L1_C_PROTO_xscale; 4869 pte_l2_s_proto = L2_S_PROTO_xscale; 4870 4871 pmap_copy_page_func = pmap_copy_page_xscale; 4872 pmap_zero_page_func = pmap_zero_page_xscale; 4873 4874 /* 4875 * Disable ECC protection of page table access, for now. 4876 */ 4877 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 4878 auxctl &= ~XSCALE_AUXCTL_P; 4879 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 4880 } 4881 4882 /* 4883 * xscale_setup_minidata: 4884 * 4885 * Set up the mini-data cache clean area. We require the 4886 * caller to allocate the right amount of physically and 4887 * virtually contiguous space. 4888 */ 4889 void 4890 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 4891 { 4892 extern vaddr_t xscale_minidata_clean_addr; 4893 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 4894 pd_entry_t *pde = (pd_entry_t *) l1pt; 4895 pt_entry_t *pte; 4896 vsize_t size; 4897 uint32_t auxctl; 4898 4899 xscale_minidata_clean_addr = va; 4900 4901 /* Round it to page size. */ 4902 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 4903 4904 for (; size != 0; 4905 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 4906 #ifndef ARM32_NEW_VM_LAYOUT 4907 pte = (pt_entry_t *) 4908 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4909 #else 4910 pte = (pt_entry_t *) kernel_pt_lookup( 4911 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4912 #endif 4913 if (pte == NULL) 4914 panic("xscale_setup_minidata: can't find L2 table for " 4915 "VA 0x%08lx", va); 4916 #ifndef ARM32_NEW_VM_LAYOUT 4917 pte[(va >> PGSHIFT) & 0x3ff] = 4918 #else 4919 pte[l2pte_index(va)] = 4920 #endif 4921 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4922 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4923 } 4924 4925 /* 4926 * Configure the mini-data cache for write-back with 4927 * read/write-allocate. 4928 * 4929 * NOTE: In order to reconfigure the mini-data cache, we must 4930 * make sure it contains no valid data! In order to do that, 4931 * we must issue a global data cache invalidate command! 4932 * 4933 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 4934 * THIS IS VERY IMPORTANT! 4935 */ 4936 4937 /* Invalidate data and mini-data. */ 4938 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 4939 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 4940 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 4941 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 4942 } 4943 4944 /* 4945 * Change the PTEs for the specified kernel mappings such that they 4946 * will use the mini data cache instead of the main data cache. 4947 */ 4948 void 4949 pmap_uarea(vaddr_t va) 4950 { 4951 struct l2_bucket *l2b; 4952 pt_entry_t *ptep, *sptep, pte; 4953 vaddr_t next_bucket, eva; 4954 4955 #if (ARM_NMMUS > 1) 4956 if (xscale_use_minidata == 0) 4957 return; 4958 #endif 4959 4960 eva = va + USPACE; 4961 4962 while (va < eva) { 4963 next_bucket = L2_NEXT_BUCKET(va); 4964 if (next_bucket > eva) 4965 next_bucket = eva; 4966 4967 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4968 KDASSERT(l2b != NULL); 4969 4970 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4971 4972 while (va < next_bucket) { 4973 pte = *ptep; 4974 if (!l2pte_minidata(pte)) { 4975 cpu_dcache_wbinv_range(va, PAGE_SIZE); 4976 cpu_tlb_flushD_SE(va); 4977 *ptep = pte & ~L2_B; 4978 } 4979 ptep++; 4980 va += PAGE_SIZE; 4981 } 4982 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4983 } 4984 cpu_cpwait(); 4985 } 4986 #endif /* ARM_MMU_XSCALE == 1 */ 4987 4988 #if defined(DDB) 4989 /* 4990 * A couple of ddb-callable functions for dumping pmaps 4991 */ 4992 void pmap_dump_all(void); 4993 void pmap_dump(pmap_t); 4994 4995 void 4996 pmap_dump_all(void) 4997 { 4998 pmap_t pm; 4999 5000 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 5001 if (pm == pmap_kernel()) 5002 continue; 5003 pmap_dump(pm); 5004 printf("\n"); 5005 } 5006 } 5007 5008 static pt_entry_t ncptes[64]; 5009 static void pmap_dump_ncpg(pmap_t); 5010 5011 void 5012 pmap_dump(pmap_t pm) 5013 { 5014 struct l2_dtable *l2; 5015 struct l2_bucket *l2b; 5016 pt_entry_t *ptep, pte; 5017 vaddr_t l2_va, l2b_va, va; 5018 int i, j, k, occ, rows = 0; 5019 5020 if (pm == pmap_kernel()) 5021 printf("pmap_kernel (%p): ", pm); 5022 else 5023 printf("user pmap (%p): ", pm); 5024 5025 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 5026 5027 l2_va = 0; 5028 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 5029 l2 = pm->pm_l2[i]; 5030 5031 if (l2 == NULL || l2->l2_occupancy == 0) 5032 continue; 5033 5034 l2b_va = l2_va; 5035 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 5036 l2b = &l2->l2_bucket[j]; 5037 5038 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 5039 continue; 5040 5041 ptep = l2b->l2b_kva; 5042 5043 for (k = 0; k < 256 && ptep[k] == 0; k++) 5044 ; 5045 5046 k &= ~63; 5047 occ = l2b->l2b_occupancy; 5048 va = l2b_va + (k * 4096); 5049 for (; k < 256; k++, va += 0x1000) { 5050 char ch = ' '; 5051 if ((k % 64) == 0) { 5052 if ((rows % 8) == 0) { 5053 printf( 5054 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 5055 } 5056 printf("%08lx: ", va); 5057 } 5058 5059 ncptes[k & 63] = 0; 5060 pte = ptep[k]; 5061 if (pte == 0) { 5062 ch = '.'; 5063 } else { 5064 occ--; 5065 switch (pte & 0x0c) { 5066 case 0x00: 5067 ch = 'D'; /* No cache No buff */ 5068 break; 5069 case 0x04: 5070 ch = 'B'; /* No cache buff */ 5071 break; 5072 case 0x08: 5073 if (pte & 0x40) 5074 ch = 'm'; 5075 else 5076 ch = 'C'; /* Cache No buff */ 5077 break; 5078 case 0x0c: 5079 ch = 'F'; /* Cache Buff */ 5080 break; 5081 } 5082 5083 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 5084 ch += 0x20; 5085 5086 if ((pte & 0xc) == 0) 5087 ncptes[k & 63] = pte; 5088 } 5089 5090 if ((k % 64) == 63) { 5091 rows++; 5092 printf("%c\n", ch); 5093 pmap_dump_ncpg(pm); 5094 if (occ == 0) 5095 break; 5096 } else 5097 printf("%c", ch); 5098 } 5099 } 5100 } 5101 } 5102 5103 static void 5104 pmap_dump_ncpg(pmap_t pm) 5105 { 5106 struct vm_page *pg; 5107 struct pv_entry *pv; 5108 int i; 5109 5110 for (i = 0; i < 63; i++) { 5111 if (ncptes[i] == 0) 5112 continue; 5113 5114 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 5115 if (pg == NULL) 5116 continue; 5117 5118 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 5119 VM_PAGE_TO_PHYS(pg), 5120 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 5121 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 5122 5123 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 5124 printf(" %c va 0x%08lx, flags 0x%x\n", 5125 (pm == pv->pv_pmap) ? '*' : ' ', 5126 pv->pv_va, pv->pv_flags); 5127 } 5128 } 5129 } 5130 #endif 5131
Indexes created Tue Sep 23 07:09:52 GMT 2025