pmap.c revision 1.171
1 /* $NetBSD: pmap.c,v 1.171 2008/01/06 03:11:42 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 3. All advertising materials mentioning features or use of this software 82 * must display the following acknowledgement: 83 * This product includes software developed by the NetBSD 84 * Foundation, Inc. and its contributors. 85 * 4. Neither the name of The NetBSD Foundation nor the names of its 86 * contributors may be used to endorse or promote products derived 87 * from this software without specific prior written permission. 88 * 89 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 90 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 91 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 92 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 93 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 94 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 95 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 96 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 97 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 98 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 99 * POSSIBILITY OF SUCH DAMAGE. 100 */ 101 102 /* 103 * Copyright (c) 1994-1998 Mark Brinicombe. 104 * Copyright (c) 1994 Brini. 105 * All rights reserved. 106 * 107 * This code is derived from software written for Brini by Mark Brinicombe 108 * 109 * Redistribution and use in source and binary forms, with or without 110 * modification, are permitted provided that the following conditions 111 * are met: 112 * 1. Redistributions of source code must retain the above copyright 113 * notice, this list of conditions and the following disclaimer. 114 * 2. Redistributions in binary form must reproduce the above copyright 115 * notice, this list of conditions and the following disclaimer in the 116 * documentation and/or other materials provided with the distribution. 117 * 3. All advertising materials mentioning features or use of this software 118 * must display the following acknowledgement: 119 * This product includes software developed by Mark Brinicombe. 120 * 4. The name of the author may not be used to endorse or promote products 121 * derived from this software without specific prior written permission. 122 * 123 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 124 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 125 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 126 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 127 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 128 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 129 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 130 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 131 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 132 * 133 * RiscBSD kernel project 134 * 135 * pmap.c 136 * 137 * Machine dependant vm stuff 138 * 139 * Created : 20/09/94 140 */ 141 142 /* 143 * Performance improvements, UVM changes, overhauls and part-rewrites 144 * were contributed by Neil A. Carson <neil (at) causality.com>. 145 */ 146 147 /* 148 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 149 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 150 * Systems, Inc. 151 * 152 * There are still a few things outstanding at this time: 153 * 154 * - There are some unresolved issues for MP systems: 155 * 156 * o The L1 metadata needs a lock, or more specifically, some places 157 * need to acquire an exclusive lock when modifying L1 translation 158 * table entries. 159 * 160 * o When one cpu modifies an L1 entry, and that L1 table is also 161 * being used by another cpu, then the latter will need to be told 162 * that a tlb invalidation may be necessary. (But only if the old 163 * domain number in the L1 entry being over-written is currently 164 * the active domain on that cpu). I guess there are lots more tlb 165 * shootdown issues too... 166 * 167 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 168 * MP systems will lose big-time because of the MMU domain hack. 169 * The only way this can be solved (apart from moving the vector 170 * page to 0xffff0000) is to reserve the first 1MB of user address 171 * space for kernel use only. This would require re-linking all 172 * applications so that the text section starts above this 1MB 173 * boundary. 174 * 175 * o Tracking which VM space is resident in the cache/tlb has not yet 176 * been implemented for MP systems. 177 * 178 * o Finally, there is a pathological condition where two cpus running 179 * two separate processes (not lwps) which happen to share an L1 180 * can get into a fight over one or more L1 entries. This will result 181 * in a significant slow-down if both processes are in tight loops. 182 */ 183 184 /* 185 * Special compilation symbols 186 * PMAP_DEBUG - Build in pmap_debug_level code 187 */ 188 189 /* Include header files */ 190 191 #include "opt_cpuoptions.h" 192 #include "opt_pmap_debug.h" 193 #include "opt_ddb.h" 194 #include "opt_lockdebug.h" 195 #include "opt_multiprocessor.h" 196 197 #include <sys/param.h> 198 #include <sys/types.h> 199 #include <sys/kernel.h> 200 #include <sys/systm.h> 201 #include <sys/proc.h> 202 #include <sys/malloc.h> 203 #include <sys/user.h> 204 #include <sys/pool.h> 205 #include <sys/cdefs.h> 206 #include <sys/cpu.h> 207 208 #include <uvm/uvm.h> 209 210 #include <machine/bus.h> 211 #include <machine/pmap.h> 212 #include <machine/pcb.h> 213 #include <machine/param.h> 214 #include <arm/arm32/katelib.h> 215 216 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.171 2008/01/06 03:11:42 matt Exp $"); 217 218 #ifdef PMAP_DEBUG 219 220 /* XXX need to get rid of all refs to this */ 221 int pmap_debug_level = 0; 222 223 /* 224 * for switching to potentially finer grained debugging 225 */ 226 #define PDB_FOLLOW 0x0001 227 #define PDB_INIT 0x0002 228 #define PDB_ENTER 0x0004 229 #define PDB_REMOVE 0x0008 230 #define PDB_CREATE 0x0010 231 #define PDB_PTPAGE 0x0020 232 #define PDB_GROWKERN 0x0040 233 #define PDB_BITS 0x0080 234 #define PDB_COLLECT 0x0100 235 #define PDB_PROTECT 0x0200 236 #define PDB_MAP_L1 0x0400 237 #define PDB_BOOTSTRAP 0x1000 238 #define PDB_PARANOIA 0x2000 239 #define PDB_WIRING 0x4000 240 #define PDB_PVDUMP 0x8000 241 #define PDB_VAC 0x10000 242 #define PDB_KENTER 0x20000 243 #define PDB_KREMOVE 0x40000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 struct pmap kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pool and cache that pmap structures are allocated from. 269 * We use a cache to avoid clearing the pm_l2[] array (1KB) 270 * in pmap_create(). 271 */ 272 static struct pool_cache pmap_cache; 273 static LIST_HEAD(, pmap) pmap_pmaps; 274 275 /* 276 * Pool of PV structures 277 */ 278 static struct pool pmap_pv_pool; 279 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 280 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 281 static struct pool_allocator pmap_bootstrap_pv_allocator = { 282 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 283 }; 284 285 /* 286 * Pool and cache of l2_dtable structures. 287 * We use a cache to avoid clearing the structures when they're 288 * allocated. (196 bytes) 289 */ 290 static struct pool_cache pmap_l2dtable_cache; 291 static vaddr_t pmap_kernel_l2dtable_kva; 292 293 /* 294 * Pool and cache of L2 page descriptors. 295 * We use a cache to avoid clearing the descriptor table 296 * when they're allocated. (1KB) 297 */ 298 static struct pool_cache pmap_l2ptp_cache; 299 static vaddr_t pmap_kernel_l2ptp_kva; 300 static paddr_t pmap_kernel_l2ptp_phys; 301 302 /* 303 * pmap copy/zero page, and mem(5) hook point 304 */ 305 static pt_entry_t *csrc_pte, *cdst_pte; 306 static vaddr_t csrcp, cdstp; 307 vaddr_t memhook; 308 extern void *msgbufaddr; 309 310 /* 311 * Flag to indicate if pmap_init() has done its thing 312 */ 313 bool pmap_initialized; 314 315 /* 316 * Misc. locking data structures 317 */ 318 319 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 320 static struct lock pmap_main_lock; 321 322 #define PMAP_MAP_TO_HEAD_LOCK() \ 323 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 324 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 325 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 326 #define PMAP_HEAD_TO_MAP_LOCK() \ 327 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 328 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 329 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 330 #else 331 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 332 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 333 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 334 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 335 #endif 336 337 #define pmap_acquire_pmap_lock(pm) \ 338 do { \ 339 if ((pm) != pmap_kernel()) \ 340 simple_lock(&(pm)->pm_lock); \ 341 } while (/*CONSTCOND*/0) 342 343 #define pmap_release_pmap_lock(pm) \ 344 do { \ 345 if ((pm) != pmap_kernel()) \ 346 simple_unlock(&(pm)->pm_lock); \ 347 } while (/*CONSTCOND*/0) 348 349 350 /* 351 * Metadata for L1 translation tables. 352 */ 353 struct l1_ttable { 354 /* Entry on the L1 Table list */ 355 SLIST_ENTRY(l1_ttable) l1_link; 356 357 /* Entry on the L1 Least Recently Used list */ 358 TAILQ_ENTRY(l1_ttable) l1_lru; 359 360 /* Track how many domains are allocated from this L1 */ 361 volatile u_int l1_domain_use_count; 362 363 /* 364 * A free-list of domain numbers for this L1. 365 * We avoid using ffs() and a bitmap to track domains since ffs() 366 * is slow on ARM. 367 */ 368 u_int8_t l1_domain_first; 369 u_int8_t l1_domain_free[PMAP_DOMAINS]; 370 371 /* Physical address of this L1 page table */ 372 paddr_t l1_physaddr; 373 374 /* KVA of this L1 page table */ 375 pd_entry_t *l1_kva; 376 }; 377 378 /* 379 * Convert a virtual address into its L1 table index. That is, the 380 * index used to locate the L2 descriptor table pointer in an L1 table. 381 * This is basically used to index l1->l1_kva[]. 382 * 383 * Each L2 descriptor table represents 1MB of VA space. 384 */ 385 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 386 387 /* 388 * L1 Page Tables are tracked using a Least Recently Used list. 389 * - New L1s are allocated from the HEAD. 390 * - Freed L1s are added to the TAIl. 391 * - Recently accessed L1s (where an 'access' is some change to one of 392 * the userland pmaps which owns this L1) are moved to the TAIL. 393 */ 394 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 395 static struct simplelock l1_lru_lock; 396 397 /* 398 * A list of all L1 tables 399 */ 400 static SLIST_HEAD(, l1_ttable) l1_list; 401 402 /* 403 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 404 * 405 * This is normally 16MB worth L2 page descriptors for any given pmap. 406 * Reference counts are maintained for L2 descriptors so they can be 407 * freed when empty. 408 */ 409 struct l2_dtable { 410 /* The number of L2 page descriptors allocated to this l2_dtable */ 411 u_int l2_occupancy; 412 413 /* List of L2 page descriptors */ 414 struct l2_bucket { 415 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 416 paddr_t l2b_phys; /* Physical address of same */ 417 u_short l2b_l1idx; /* This L2 table's L1 index */ 418 u_short l2b_occupancy; /* How many active descriptors */ 419 } l2_bucket[L2_BUCKET_SIZE]; 420 }; 421 422 /* 423 * Given an L1 table index, calculate the corresponding l2_dtable index 424 * and bucket index within the l2_dtable. 425 */ 426 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 427 (L2_SIZE - 1)) 428 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 429 430 /* 431 * Given a virtual address, this macro returns the 432 * virtual address required to drop into the next L2 bucket. 433 */ 434 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 435 436 /* 437 * L2 allocation. 438 */ 439 #define pmap_alloc_l2_dtable() \ 440 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 441 #define pmap_free_l2_dtable(l2) \ 442 pool_cache_put(&pmap_l2dtable_cache, (l2)) 443 #define pmap_alloc_l2_ptp(pap) \ 444 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 445 PR_NOWAIT, (pap))) 446 447 /* 448 * We try to map the page tables write-through, if possible. However, not 449 * all CPUs have a write-through cache mode, so on those we have to sync 450 * the cache when we frob page tables. 451 * 452 * We try to evaluate this at compile time, if possible. However, it's 453 * not always possible to do that, hence this run-time var. 454 */ 455 int pmap_needs_pte_sync; 456 457 /* 458 * Real definition of pv_entry. 459 */ 460 struct pv_entry { 461 struct pv_entry *pv_next; /* next pv_entry */ 462 pmap_t pv_pmap; /* pmap where mapping lies */ 463 vaddr_t pv_va; /* virtual address for mapping */ 464 u_int pv_flags; /* flags */ 465 }; 466 467 /* 468 * Macro to determine if a mapping might be resident in the 469 * instruction cache and/or TLB 470 */ 471 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 472 473 /* 474 * Macro to determine if a mapping might be resident in the 475 * data cache and/or TLB 476 */ 477 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 478 479 /* 480 * Local prototypes 481 */ 482 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 483 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 484 pt_entry_t **); 485 static bool pmap_is_current(pmap_t); 486 static bool pmap_is_cached(pmap_t); 487 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 488 pmap_t, vaddr_t, u_int); 489 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 490 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 491 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 492 u_int, u_int); 493 494 static void pmap_pinit(pmap_t); 495 static int pmap_pmap_ctor(void *, void *, int); 496 497 static void pmap_alloc_l1(pmap_t); 498 static void pmap_free_l1(pmap_t); 499 static void pmap_use_l1(pmap_t); 500 501 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 502 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 503 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 504 static int pmap_l2ptp_ctor(void *, void *, int); 505 static int pmap_l2dtable_ctor(void *, void *, int); 506 507 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 508 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 509 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 510 511 static void pmap_clearbit(struct vm_page *, u_int); 512 static int pmap_clean_page(struct pv_entry *, bool); 513 static void pmap_page_remove(struct vm_page *); 514 515 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 516 static vaddr_t kernel_pt_lookup(paddr_t); 517 518 void pmap_switch(struct lwp *, struct lwp *); 519 520 521 /* 522 * External function prototypes 523 */ 524 extern void bzero_page(vaddr_t); 525 extern void bcopy_page(vaddr_t, vaddr_t); 526 527 /* 528 * Misc variables 529 */ 530 vaddr_t virtual_avail; 531 vaddr_t virtual_end; 532 vaddr_t pmap_curmaxkvaddr; 533 534 vaddr_t avail_start; 535 vaddr_t avail_end; 536 537 extern pv_addr_t systempage; 538 539 /* Function to set the debug level of the pmap code */ 540 541 #ifdef PMAP_DEBUG 542 void 543 pmap_debug(int level) 544 { 545 pmap_debug_level = level; 546 printf("pmap_debug: level=%d\n", pmap_debug_level); 547 } 548 #endif /* PMAP_DEBUG */ 549 550 /* 551 * A bunch of routines to conditionally flush the caches/TLB depending 552 * on whether the specified pmap actually needs to be flushed at any 553 * given time. 554 */ 555 static inline void 556 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 557 { 558 559 if (pm->pm_cstate.cs_tlb_id) 560 cpu_tlb_flushID_SE(va); 561 } 562 563 static inline void 564 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 565 { 566 567 if (pm->pm_cstate.cs_tlb_d) 568 cpu_tlb_flushD_SE(va); 569 } 570 571 static inline void 572 pmap_tlb_flushID(pmap_t pm) 573 { 574 575 if (pm->pm_cstate.cs_tlb_id) { 576 cpu_tlb_flushID(); 577 pm->pm_cstate.cs_tlb = 0; 578 } 579 } 580 581 static inline void 582 pmap_tlb_flushD(pmap_t pm) 583 { 584 585 if (pm->pm_cstate.cs_tlb_d) { 586 cpu_tlb_flushD(); 587 pm->pm_cstate.cs_tlb_d = 0; 588 } 589 } 590 591 static inline void 592 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 593 { 594 595 if (pm->pm_cstate.cs_cache_id) 596 cpu_idcache_wbinv_range(va, len); 597 } 598 599 static inline void 600 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 601 bool do_inv, bool rd_only) 602 { 603 604 if (pm->pm_cstate.cs_cache_d) { 605 if (do_inv) { 606 if (rd_only) 607 cpu_dcache_inv_range(va, len); 608 else 609 cpu_dcache_wbinv_range(va, len); 610 } else 611 if (!rd_only) 612 cpu_dcache_wb_range(va, len); 613 } 614 } 615 616 static inline void 617 pmap_idcache_wbinv_all(pmap_t pm) 618 { 619 620 if (pm->pm_cstate.cs_cache_id) { 621 cpu_idcache_wbinv_all(); 622 pm->pm_cstate.cs_cache = 0; 623 } 624 } 625 626 static inline void 627 pmap_dcache_wbinv_all(pmap_t pm) 628 { 629 630 if (pm->pm_cstate.cs_cache_d) { 631 cpu_dcache_wbinv_all(); 632 pm->pm_cstate.cs_cache_d = 0; 633 } 634 } 635 636 static inline bool 637 pmap_is_current(pmap_t pm) 638 { 639 640 if (pm == pmap_kernel() || 641 (curproc && curproc->p_vmspace->vm_map.pmap == pm)) 642 return (true); 643 644 return (false); 645 } 646 647 static inline bool 648 pmap_is_cached(pmap_t pm) 649 { 650 651 if (pm == pmap_kernel() || pmap_recent_user == NULL || 652 pmap_recent_user == pm) 653 return (true); 654 655 return (false); 656 } 657 658 /* 659 * PTE_SYNC_CURRENT: 660 * 661 * Make sure the pte is written out to RAM. 662 * We need to do this for one of two cases: 663 * - We're dealing with the kernel pmap 664 * - There is no pmap active in the cache/tlb. 665 * - The specified pmap is 'active' in the cache/tlb. 666 */ 667 #ifdef PMAP_INCLUDE_PTE_SYNC 668 #define PTE_SYNC_CURRENT(pm, ptep) \ 669 do { \ 670 if (PMAP_NEEDS_PTE_SYNC && \ 671 pmap_is_cached(pm)) \ 672 PTE_SYNC(ptep); \ 673 } while (/*CONSTCOND*/0) 674 #else 675 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 676 #endif 677 678 /* 679 * main pv_entry manipulation functions: 680 * pmap_enter_pv: enter a mapping onto a vm_page list 681 * pmap_remove_pv: remove a mappiing from a vm_page list 682 * 683 * NOTE: pmap_enter_pv expects to lock the pvh itself 684 * pmap_remove_pv expects te caller to lock the pvh before calling 685 */ 686 687 /* 688 * pmap_enter_pv: enter a mapping onto a vm_page lst 689 * 690 * => caller should hold the proper lock on pmap_main_lock 691 * => caller should have pmap locked 692 * => we will gain the lock on the vm_page and allocate the new pv_entry 693 * => caller should adjust ptp's wire_count before calling 694 * => caller should not adjust pmap's wire_count 695 */ 696 static void 697 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 698 vaddr_t va, u_int flags) 699 { 700 701 NPDEBUG(PDB_PVDUMP, 702 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 703 704 pve->pv_pmap = pm; 705 pve->pv_va = va; 706 pve->pv_flags = flags; 707 708 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 709 pve->pv_next = pg->mdpage.pvh_list; /* add to ... */ 710 pg->mdpage.pvh_list = pve; /* ... locked list */ 711 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 712 if (pm == pmap_kernel()) { 713 if (flags & PVF_WRITE) 714 pg->mdpage.krw_mappings++; 715 else 716 pg->mdpage.kro_mappings++; 717 } else 718 if (flags & PVF_WRITE) 719 pg->mdpage.urw_mappings++; 720 else 721 pg->mdpage.uro_mappings++; 722 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 723 724 if (pve->pv_flags & PVF_WIRED) 725 ++pm->pm_stats.wired_count; 726 } 727 728 /* 729 * 730 * pmap_find_pv: Find a pv entry 731 * 732 * => caller should hold lock on vm_page 733 */ 734 static inline struct pv_entry * 735 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 736 { 737 struct pv_entry *pv; 738 739 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 740 if (pm == pv->pv_pmap && va == pv->pv_va) 741 break; 742 } 743 744 return (pv); 745 } 746 747 /* 748 * pmap_remove_pv: try to remove a mapping from a pv_list 749 * 750 * => caller should hold proper lock on pmap_main_lock 751 * => pmap should be locked 752 * => caller should hold lock on vm_page [so that attrs can be adjusted] 753 * => caller should adjust ptp's wire_count and free PTP if needed 754 * => caller should NOT adjust pmap's wire_count 755 * => we return the removed pve 756 */ 757 static struct pv_entry * 758 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 759 { 760 struct pv_entry *pve, **prevptr; 761 762 NPDEBUG(PDB_PVDUMP, 763 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 764 765 prevptr = &pg->mdpage.pvh_list; /* previous pv_entry pointer */ 766 pve = *prevptr; 767 768 while (pve) { 769 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 770 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 771 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 772 if (pve->pv_flags & PVF_WIRED) { 773 if (skip_wired) 774 return (NULL); 775 --pm->pm_stats.wired_count; 776 } 777 *prevptr = pve->pv_next; /* remove it! */ 778 if (pm == pmap_kernel()) { 779 if (pve->pv_flags & PVF_WRITE) 780 pg->mdpage.krw_mappings--; 781 else 782 pg->mdpage.kro_mappings--; 783 } else 784 if (pve->pv_flags & PVF_WRITE) 785 pg->mdpage.urw_mappings--; 786 else 787 pg->mdpage.uro_mappings--; 788 break; 789 } 790 prevptr = &pve->pv_next; /* previous pointer */ 791 pve = pve->pv_next; /* advance */ 792 } 793 794 return(pve); /* return removed pve */ 795 } 796 797 /* 798 * 799 * pmap_modify_pv: Update pv flags 800 * 801 * => caller should hold lock on vm_page [so that attrs can be adjusted] 802 * => caller should NOT adjust pmap's wire_count 803 * => caller must call pmap_vac_me_harder() if writable status of a page 804 * may have changed. 805 * => we return the old flags 806 * 807 * Modify a physical-virtual mapping in the pv table 808 */ 809 static u_int 810 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 811 u_int clr_mask, u_int set_mask) 812 { 813 struct pv_entry *npv; 814 u_int flags, oflags; 815 816 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 817 return (0); 818 819 NPDEBUG(PDB_PVDUMP, 820 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 821 822 /* 823 * There is at least one VA mapping this page. 824 */ 825 826 if (clr_mask & (PVF_REF | PVF_MOD)) 827 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 828 829 oflags = npv->pv_flags; 830 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 831 832 if ((flags ^ oflags) & PVF_WIRED) { 833 if (flags & PVF_WIRED) 834 ++pm->pm_stats.wired_count; 835 else 836 --pm->pm_stats.wired_count; 837 } 838 839 if ((flags ^ oflags) & PVF_WRITE) { 840 if (pm == pmap_kernel()) { 841 if (flags & PVF_WRITE) { 842 pg->mdpage.krw_mappings++; 843 pg->mdpage.kro_mappings--; 844 } else { 845 pg->mdpage.kro_mappings++; 846 pg->mdpage.krw_mappings--; 847 } 848 } else 849 if (flags & PVF_WRITE) { 850 pg->mdpage.urw_mappings++; 851 pg->mdpage.uro_mappings--; 852 } else { 853 pg->mdpage.uro_mappings++; 854 pg->mdpage.urw_mappings--; 855 } 856 } 857 858 return (oflags); 859 } 860 861 /* 862 * Allocate an L1 translation table for the specified pmap. 863 * This is called at pmap creation time. 864 */ 865 static void 866 pmap_alloc_l1(pmap_t pm) 867 { 868 struct l1_ttable *l1; 869 u_int8_t domain; 870 871 /* 872 * Remove the L1 at the head of the LRU list 873 */ 874 simple_lock(&l1_lru_lock); 875 l1 = TAILQ_FIRST(&l1_lru_list); 876 KDASSERT(l1 != NULL); 877 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 878 879 /* 880 * Pick the first available domain number, and update 881 * the link to the next number. 882 */ 883 domain = l1->l1_domain_first; 884 l1->l1_domain_first = l1->l1_domain_free[domain]; 885 886 /* 887 * If there are still free domain numbers in this L1, 888 * put it back on the TAIL of the LRU list. 889 */ 890 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 891 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 892 893 simple_unlock(&l1_lru_lock); 894 895 /* 896 * Fix up the relevant bits in the pmap structure 897 */ 898 pm->pm_l1 = l1; 899 pm->pm_domain = domain; 900 } 901 902 /* 903 * Free an L1 translation table. 904 * This is called at pmap destruction time. 905 */ 906 static void 907 pmap_free_l1(pmap_t pm) 908 { 909 struct l1_ttable *l1 = pm->pm_l1; 910 911 simple_lock(&l1_lru_lock); 912 913 /* 914 * If this L1 is currently on the LRU list, remove it. 915 */ 916 if (l1->l1_domain_use_count < PMAP_DOMAINS) 917 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 918 919 /* 920 * Free up the domain number which was allocated to the pmap 921 */ 922 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 923 l1->l1_domain_first = pm->pm_domain; 924 l1->l1_domain_use_count--; 925 926 /* 927 * The L1 now must have at least 1 free domain, so add 928 * it back to the LRU list. If the use count is zero, 929 * put it at the head of the list, otherwise it goes 930 * to the tail. 931 */ 932 if (l1->l1_domain_use_count == 0) 933 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 934 else 935 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 936 937 simple_unlock(&l1_lru_lock); 938 } 939 940 static inline void 941 pmap_use_l1(pmap_t pm) 942 { 943 struct l1_ttable *l1; 944 945 /* 946 * Do nothing if we're in interrupt context. 947 * Access to an L1 by the kernel pmap must not affect 948 * the LRU list. 949 */ 950 if (cpu_intr_p() || pm == pmap_kernel()) 951 return; 952 953 l1 = pm->pm_l1; 954 955 /* 956 * If the L1 is not currently on the LRU list, just return 957 */ 958 if (l1->l1_domain_use_count == PMAP_DOMAINS) 959 return; 960 961 simple_lock(&l1_lru_lock); 962 963 /* 964 * Check the use count again, now that we've acquired the lock 965 */ 966 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 967 simple_unlock(&l1_lru_lock); 968 return; 969 } 970 971 /* 972 * Move the L1 to the back of the LRU list 973 */ 974 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 975 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 976 977 simple_unlock(&l1_lru_lock); 978 } 979 980 /* 981 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 982 * 983 * Free an L2 descriptor table. 984 */ 985 static inline void 986 #ifndef PMAP_INCLUDE_PTE_SYNC 987 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 988 #else 989 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 990 #endif 991 { 992 #ifdef PMAP_INCLUDE_PTE_SYNC 993 /* 994 * Note: With a write-back cache, we may need to sync this 995 * L2 table before re-using it. 996 * This is because it may have belonged to a non-current 997 * pmap, in which case the cache syncs would have been 998 * skipped when the pages were being unmapped. If the 999 * L2 table were then to be immediately re-allocated to 1000 * the *current* pmap, it may well contain stale mappings 1001 * which have not yet been cleared by a cache write-back 1002 * and so would still be visible to the mmu. 1003 */ 1004 if (need_sync) 1005 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1006 #endif 1007 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1008 } 1009 1010 /* 1011 * Returns a pointer to the L2 bucket associated with the specified pmap 1012 * and VA, or NULL if no L2 bucket exists for the address. 1013 */ 1014 static inline struct l2_bucket * 1015 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1016 { 1017 struct l2_dtable *l2; 1018 struct l2_bucket *l2b; 1019 u_short l1idx; 1020 1021 l1idx = L1_IDX(va); 1022 1023 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1024 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1025 return (NULL); 1026 1027 return (l2b); 1028 } 1029 1030 /* 1031 * Returns a pointer to the L2 bucket associated with the specified pmap 1032 * and VA. 1033 * 1034 * If no L2 bucket exists, perform the necessary allocations to put an L2 1035 * bucket/page table in place. 1036 * 1037 * Note that if a new L2 bucket/page was allocated, the caller *must* 1038 * increment the bucket occupancy counter appropriately *before* 1039 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1040 * the bucket/page in the meantime. 1041 */ 1042 static struct l2_bucket * 1043 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1044 { 1045 struct l2_dtable *l2; 1046 struct l2_bucket *l2b; 1047 u_short l1idx; 1048 1049 l1idx = L1_IDX(va); 1050 1051 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1052 /* 1053 * No mapping at this address, as there is 1054 * no entry in the L1 table. 1055 * Need to allocate a new l2_dtable. 1056 */ 1057 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1058 return (NULL); 1059 1060 /* 1061 * Link it into the parent pmap 1062 */ 1063 pm->pm_l2[L2_IDX(l1idx)] = l2; 1064 } 1065 1066 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1067 1068 /* 1069 * Fetch pointer to the L2 page table associated with the address. 1070 */ 1071 if (l2b->l2b_kva == NULL) { 1072 pt_entry_t *ptep; 1073 1074 /* 1075 * No L2 page table has been allocated. Chances are, this 1076 * is because we just allocated the l2_dtable, above. 1077 */ 1078 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1079 /* 1080 * Oops, no more L2 page tables available at this 1081 * time. We may need to deallocate the l2_dtable 1082 * if we allocated a new one above. 1083 */ 1084 if (l2->l2_occupancy == 0) { 1085 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1086 pmap_free_l2_dtable(l2); 1087 } 1088 return (NULL); 1089 } 1090 1091 l2->l2_occupancy++; 1092 l2b->l2b_kva = ptep; 1093 l2b->l2b_l1idx = l1idx; 1094 } 1095 1096 return (l2b); 1097 } 1098 1099 /* 1100 * One or more mappings in the specified L2 descriptor table have just been 1101 * invalidated. 1102 * 1103 * Garbage collect the metadata and descriptor table itself if necessary. 1104 * 1105 * The pmap lock must be acquired when this is called (not necessary 1106 * for the kernel pmap). 1107 */ 1108 static void 1109 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1110 { 1111 struct l2_dtable *l2; 1112 pd_entry_t *pl1pd, l1pd; 1113 pt_entry_t *ptep; 1114 u_short l1idx; 1115 1116 KDASSERT(count <= l2b->l2b_occupancy); 1117 1118 /* 1119 * Update the bucket's reference count according to how many 1120 * PTEs the caller has just invalidated. 1121 */ 1122 l2b->l2b_occupancy -= count; 1123 1124 /* 1125 * Note: 1126 * 1127 * Level 2 page tables allocated to the kernel pmap are never freed 1128 * as that would require checking all Level 1 page tables and 1129 * removing any references to the Level 2 page table. See also the 1130 * comment elsewhere about never freeing bootstrap L2 descriptors. 1131 * 1132 * We make do with just invalidating the mapping in the L2 table. 1133 * 1134 * This isn't really a big deal in practice and, in fact, leads 1135 * to a performance win over time as we don't need to continually 1136 * alloc/free. 1137 */ 1138 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1139 return; 1140 1141 /* 1142 * There are no more valid mappings in this level 2 page table. 1143 * Go ahead and NULL-out the pointer in the bucket, then 1144 * free the page table. 1145 */ 1146 l1idx = l2b->l2b_l1idx; 1147 ptep = l2b->l2b_kva; 1148 l2b->l2b_kva = NULL; 1149 1150 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1151 1152 /* 1153 * If the L1 slot matches the pmap's domain 1154 * number, then invalidate it. 1155 */ 1156 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1157 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1158 *pl1pd = 0; 1159 PTE_SYNC(pl1pd); 1160 } 1161 1162 /* 1163 * Release the L2 descriptor table back to the pool cache. 1164 */ 1165 #ifndef PMAP_INCLUDE_PTE_SYNC 1166 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1167 #else 1168 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1169 #endif 1170 1171 /* 1172 * Update the reference count in the associated l2_dtable 1173 */ 1174 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1175 if (--l2->l2_occupancy > 0) 1176 return; 1177 1178 /* 1179 * There are no more valid mappings in any of the Level 1 1180 * slots managed by this l2_dtable. Go ahead and NULL-out 1181 * the pointer in the parent pmap and free the l2_dtable. 1182 */ 1183 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1184 pmap_free_l2_dtable(l2); 1185 } 1186 1187 /* 1188 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1189 * structures. 1190 */ 1191 static int 1192 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1193 { 1194 #ifndef PMAP_INCLUDE_PTE_SYNC 1195 struct l2_bucket *l2b; 1196 pt_entry_t *ptep, pte; 1197 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1198 1199 /* 1200 * The mappings for these page tables were initially made using 1201 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1202 * mode will not be right for page table mappings. To avoid 1203 * polluting the pmap_kenter_pa() code with a special case for 1204 * page tables, we simply fix up the cache-mode here if it's not 1205 * correct. 1206 */ 1207 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1208 KDASSERT(l2b != NULL); 1209 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1210 pte = *ptep; 1211 1212 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1213 /* 1214 * Page tables must have the cache-mode set to Write-Thru. 1215 */ 1216 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1217 PTE_SYNC(ptep); 1218 cpu_tlb_flushD_SE(va); 1219 cpu_cpwait(); 1220 } 1221 #endif 1222 1223 memset(v, 0, L2_TABLE_SIZE_REAL); 1224 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1225 return (0); 1226 } 1227 1228 static int 1229 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1230 { 1231 1232 memset(v, 0, sizeof(struct l2_dtable)); 1233 return (0); 1234 } 1235 1236 static int 1237 pmap_pmap_ctor(void *arg, void *v, int flags) 1238 { 1239 1240 memset(v, 0, sizeof(struct pmap)); 1241 return (0); 1242 } 1243 1244 static void 1245 pmap_pinit(pmap_t pm) 1246 { 1247 struct l2_bucket *l2b; 1248 1249 if (vector_page < KERNEL_BASE) { 1250 /* 1251 * Map the vector page. 1252 */ 1253 pmap_enter(pm, vector_page, systempage.pv_pa, 1254 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1255 pmap_update(pm); 1256 1257 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1258 l2b = pmap_get_l2_bucket(pm, vector_page); 1259 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1260 L1_C_DOM(pm->pm_domain); 1261 } else 1262 pm->pm_pl1vec = NULL; 1263 } 1264 1265 /* 1266 * Since we have a virtually indexed cache, we may need to inhibit caching if 1267 * there is more than one mapping and at least one of them is writable. 1268 * Since we purge the cache on every context switch, we only need to check for 1269 * other mappings within the same pmap, or kernel_pmap. 1270 * This function is also called when a page is unmapped, to possibly reenable 1271 * caching on any remaining mappings. 1272 * 1273 * The code implements the following logic, where: 1274 * 1275 * KW = # of kernel read/write pages 1276 * KR = # of kernel read only pages 1277 * UW = # of user read/write pages 1278 * UR = # of user read only pages 1279 * 1280 * KC = kernel mapping is cacheable 1281 * UC = user mapping is cacheable 1282 * 1283 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1284 * +--------------------------------------------- 1285 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1286 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1287 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1288 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1289 */ 1290 1291 static const int pmap_vac_flags[4][4] = { 1292 {-1, 0, 0, PVF_KNC}, 1293 {0, 0, PVF_NC, PVF_NC}, 1294 {0, PVF_NC, PVF_NC, PVF_NC}, 1295 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1296 }; 1297 1298 static inline int 1299 pmap_get_vac_flags(const struct vm_page *pg) 1300 { 1301 int kidx, uidx; 1302 1303 kidx = 0; 1304 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1305 kidx |= 1; 1306 if (pg->mdpage.krw_mappings) 1307 kidx |= 2; 1308 1309 uidx = 0; 1310 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1311 uidx |= 1; 1312 if (pg->mdpage.urw_mappings) 1313 uidx |= 2; 1314 1315 return (pmap_vac_flags[uidx][kidx]); 1316 } 1317 1318 static inline void 1319 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1320 { 1321 int nattr; 1322 1323 nattr = pmap_get_vac_flags(pg); 1324 1325 if (nattr < 0) { 1326 pg->mdpage.pvh_attrs &= ~PVF_NC; 1327 return; 1328 } 1329 1330 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1331 return; 1332 1333 if (pm == pmap_kernel()) 1334 pmap_vac_me_kpmap(pg, pm, va); 1335 else 1336 pmap_vac_me_user(pg, pm, va); 1337 1338 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1339 } 1340 1341 static void 1342 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1343 { 1344 u_int u_cacheable, u_entries; 1345 struct pv_entry *pv; 1346 pmap_t last_pmap = pm; 1347 1348 /* 1349 * Pass one, see if there are both kernel and user pmaps for 1350 * this page. Calculate whether there are user-writable or 1351 * kernel-writable pages. 1352 */ 1353 u_cacheable = 0; 1354 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1355 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1356 u_cacheable++; 1357 } 1358 1359 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1360 1361 /* 1362 * We know we have just been updating a kernel entry, so if 1363 * all user pages are already cacheable, then there is nothing 1364 * further to do. 1365 */ 1366 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1367 return; 1368 1369 if (u_entries) { 1370 /* 1371 * Scan over the list again, for each entry, if it 1372 * might not be set correctly, call pmap_vac_me_user 1373 * to recalculate the settings. 1374 */ 1375 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1376 /* 1377 * We know kernel mappings will get set 1378 * correctly in other calls. We also know 1379 * that if the pmap is the same as last_pmap 1380 * then we've just handled this entry. 1381 */ 1382 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1383 continue; 1384 1385 /* 1386 * If there are kernel entries and this page 1387 * is writable but non-cacheable, then we can 1388 * skip this entry also. 1389 */ 1390 if (pg->mdpage.k_mappings && 1391 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1392 (PVF_NC | PVF_WRITE)) 1393 continue; 1394 1395 /* 1396 * Similarly if there are no kernel-writable 1397 * entries and the page is already 1398 * read-only/cacheable. 1399 */ 1400 if (pg->mdpage.krw_mappings == 0 && 1401 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1402 continue; 1403 1404 /* 1405 * For some of the remaining cases, we know 1406 * that we must recalculate, but for others we 1407 * can't tell if they are correct or not, so 1408 * we recalculate anyway. 1409 */ 1410 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1411 } 1412 1413 if (pg->mdpage.k_mappings == 0) 1414 return; 1415 } 1416 1417 pmap_vac_me_user(pg, pm, va); 1418 } 1419 1420 static void 1421 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1422 { 1423 pmap_t kpmap = pmap_kernel(); 1424 struct pv_entry *pv, *npv; 1425 struct l2_bucket *l2b; 1426 pt_entry_t *ptep, pte; 1427 u_int entries = 0; 1428 u_int writable = 0; 1429 u_int cacheable_entries = 0; 1430 u_int kern_cacheable = 0; 1431 u_int other_writable = 0; 1432 1433 /* 1434 * Count mappings and writable mappings in this pmap. 1435 * Include kernel mappings as part of our own. 1436 * Keep a pointer to the first one. 1437 */ 1438 for (pv = npv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1439 /* Count mappings in the same pmap */ 1440 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1441 if (entries++ == 0) 1442 npv = pv; 1443 1444 /* Cacheable mappings */ 1445 if ((pv->pv_flags & PVF_NC) == 0) { 1446 cacheable_entries++; 1447 if (kpmap == pv->pv_pmap) 1448 kern_cacheable++; 1449 } 1450 1451 /* Writable mappings */ 1452 if (pv->pv_flags & PVF_WRITE) 1453 ++writable; 1454 } else 1455 if (pv->pv_flags & PVF_WRITE) 1456 other_writable = 1; 1457 } 1458 1459 /* 1460 * Enable or disable caching as necessary. 1461 * Note: the first entry might be part of the kernel pmap, 1462 * so we can't assume this is indicative of the state of the 1463 * other (maybe non-kpmap) entries. 1464 */ 1465 if ((entries > 1 && writable) || 1466 (entries > 0 && pm == kpmap && other_writable)) { 1467 if (cacheable_entries == 0) 1468 return; 1469 1470 for (pv = npv; pv; pv = pv->pv_next) { 1471 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1472 (pv->pv_flags & PVF_NC)) 1473 continue; 1474 1475 pv->pv_flags |= PVF_NC; 1476 1477 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1478 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1479 pte = *ptep & ~L2_S_CACHE_MASK; 1480 1481 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1482 l2pte_valid(pte)) { 1483 if (PV_BEEN_EXECD(pv->pv_flags)) { 1484 pmap_idcache_wbinv_range(pv->pv_pmap, 1485 pv->pv_va, PAGE_SIZE); 1486 pmap_tlb_flushID_SE(pv->pv_pmap, 1487 pv->pv_va); 1488 } else 1489 if (PV_BEEN_REFD(pv->pv_flags)) { 1490 pmap_dcache_wb_range(pv->pv_pmap, 1491 pv->pv_va, PAGE_SIZE, true, 1492 (pv->pv_flags & PVF_WRITE) == 0); 1493 pmap_tlb_flushD_SE(pv->pv_pmap, 1494 pv->pv_va); 1495 } 1496 } 1497 1498 *ptep = pte; 1499 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1500 } 1501 cpu_cpwait(); 1502 } else 1503 if (entries > cacheable_entries) { 1504 /* 1505 * Turn cacheing back on for some pages. If it is a kernel 1506 * page, only do so if there are no other writable pages. 1507 */ 1508 for (pv = npv; pv; pv = pv->pv_next) { 1509 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1510 (kpmap != pv->pv_pmap || other_writable))) 1511 continue; 1512 1513 pv->pv_flags &= ~PVF_NC; 1514 1515 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1516 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1517 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1518 1519 if (l2pte_valid(pte)) { 1520 if (PV_BEEN_EXECD(pv->pv_flags)) { 1521 pmap_tlb_flushID_SE(pv->pv_pmap, 1522 pv->pv_va); 1523 } else 1524 if (PV_BEEN_REFD(pv->pv_flags)) { 1525 pmap_tlb_flushD_SE(pv->pv_pmap, 1526 pv->pv_va); 1527 } 1528 } 1529 1530 *ptep = pte; 1531 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1532 } 1533 } 1534 } 1535 1536 /* 1537 * Modify pte bits for all ptes corresponding to the given physical address. 1538 * We use `maskbits' rather than `clearbits' because we're always passing 1539 * constants and the latter would require an extra inversion at run-time. 1540 */ 1541 static void 1542 pmap_clearbit(struct vm_page *pg, u_int maskbits) 1543 { 1544 struct l2_bucket *l2b; 1545 struct pv_entry *pv; 1546 pt_entry_t *ptep, npte, opte; 1547 pmap_t pm; 1548 vaddr_t va; 1549 u_int oflags; 1550 1551 NPDEBUG(PDB_BITS, 1552 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 1553 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 1554 1555 PMAP_HEAD_TO_MAP_LOCK(); 1556 simple_lock(&pg->mdpage.pvh_slock); 1557 1558 /* 1559 * Clear saved attributes (modify, reference) 1560 */ 1561 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1562 1563 if (pg->mdpage.pvh_list == NULL) { 1564 simple_unlock(&pg->mdpage.pvh_slock); 1565 PMAP_HEAD_TO_MAP_UNLOCK(); 1566 return; 1567 } 1568 1569 /* 1570 * Loop over all current mappings setting/clearing as appropos 1571 */ 1572 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1573 va = pv->pv_va; 1574 pm = pv->pv_pmap; 1575 oflags = pv->pv_flags; 1576 pv->pv_flags &= ~maskbits; 1577 1578 pmap_acquire_pmap_lock(pm); 1579 1580 l2b = pmap_get_l2_bucket(pm, va); 1581 KDASSERT(l2b != NULL); 1582 1583 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1584 npte = opte = *ptep; 1585 1586 NPDEBUG(PDB_BITS, 1587 printf( 1588 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 1589 pv, pv->pv_pmap, pv->pv_va, oflags)); 1590 1591 if (maskbits & (PVF_WRITE|PVF_MOD)) { 1592 if ((pv->pv_flags & PVF_NC)) { 1593 /* 1594 * Entry is not cacheable: 1595 * 1596 * Don't turn caching on again if this is a 1597 * modified emulation. This would be 1598 * inconsitent with the settings created by 1599 * pmap_vac_me_harder(). Otherwise, it's safe 1600 * to re-enable cacheing. 1601 * 1602 * There's no need to call pmap_vac_me_harder() 1603 * here: all pages are losing their write 1604 * permission. 1605 */ 1606 if (maskbits & PVF_WRITE) { 1607 npte |= pte_l2_s_cache_mode; 1608 pv->pv_flags &= ~PVF_NC; 1609 } 1610 } else 1611 if (opte & L2_S_PROT_W) { 1612 /* 1613 * Entry is writable/cacheable: check if pmap 1614 * is current if it is flush it, otherwise it 1615 * won't be in the cache 1616 */ 1617 if (PV_BEEN_EXECD(oflags)) 1618 pmap_idcache_wbinv_range(pm, pv->pv_va, 1619 PAGE_SIZE); 1620 else 1621 if (PV_BEEN_REFD(oflags)) 1622 pmap_dcache_wb_range(pm, pv->pv_va, 1623 PAGE_SIZE, 1624 (maskbits & PVF_REF) ? true : false, 1625 false); 1626 } 1627 1628 /* make the pte read only */ 1629 npte &= ~L2_S_PROT_W; 1630 1631 if (maskbits & PVF_WRITE) { 1632 /* 1633 * Keep alias accounting up to date 1634 */ 1635 if (pv->pv_pmap == pmap_kernel()) { 1636 if (oflags & PVF_WRITE) { 1637 pg->mdpage.krw_mappings--; 1638 pg->mdpage.kro_mappings++; 1639 } 1640 } else 1641 if (oflags & PVF_WRITE) { 1642 pg->mdpage.urw_mappings--; 1643 pg->mdpage.uro_mappings++; 1644 } 1645 } 1646 } 1647 1648 if (maskbits & PVF_REF) { 1649 if ((pv->pv_flags & PVF_NC) == 0 && 1650 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1651 /* 1652 * Check npte here; we may have already 1653 * done the wbinv above, and the validity 1654 * of the PTE is the same for opte and 1655 * npte. 1656 */ 1657 if (npte & L2_S_PROT_W) { 1658 if (PV_BEEN_EXECD(oflags)) 1659 pmap_idcache_wbinv_range(pm, 1660 pv->pv_va, PAGE_SIZE); 1661 else 1662 if (PV_BEEN_REFD(oflags)) 1663 pmap_dcache_wb_range(pm, 1664 pv->pv_va, PAGE_SIZE, 1665 true, false); 1666 } else 1667 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1668 /* XXXJRT need idcache_inv_range */ 1669 if (PV_BEEN_EXECD(oflags)) 1670 pmap_idcache_wbinv_range(pm, 1671 pv->pv_va, PAGE_SIZE); 1672 else 1673 if (PV_BEEN_REFD(oflags)) 1674 pmap_dcache_wb_range(pm, 1675 pv->pv_va, PAGE_SIZE, 1676 true, true); 1677 } 1678 } 1679 1680 /* 1681 * Make the PTE invalid so that we will take a 1682 * page fault the next time the mapping is 1683 * referenced. 1684 */ 1685 npte &= ~L2_TYPE_MASK; 1686 npte |= L2_TYPE_INV; 1687 } 1688 1689 if (npte != opte) { 1690 *ptep = npte; 1691 PTE_SYNC(ptep); 1692 /* Flush the TLB entry if a current pmap. */ 1693 if (PV_BEEN_EXECD(oflags)) 1694 pmap_tlb_flushID_SE(pm, pv->pv_va); 1695 else 1696 if (PV_BEEN_REFD(oflags)) 1697 pmap_tlb_flushD_SE(pm, pv->pv_va); 1698 } 1699 1700 pmap_release_pmap_lock(pm); 1701 1702 NPDEBUG(PDB_BITS, 1703 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 1704 pm, va, opte, npte)); 1705 } 1706 1707 simple_unlock(&pg->mdpage.pvh_slock); 1708 PMAP_HEAD_TO_MAP_UNLOCK(); 1709 } 1710 1711 /* 1712 * pmap_clean_page() 1713 * 1714 * This is a local function used to work out the best strategy to clean 1715 * a single page referenced by its entry in the PV table. It's used by 1716 * pmap_copy_page, pmap_zero page and maybe some others later on. 1717 * 1718 * Its policy is effectively: 1719 * o If there are no mappings, we don't bother doing anything with the cache. 1720 * o If there is one mapping, we clean just that page. 1721 * o If there are multiple mappings, we clean the entire cache. 1722 * 1723 * So that some functions can be further optimised, it returns 0 if it didn't 1724 * clean the entire cache, or 1 if it did. 1725 * 1726 * XXX One bug in this routine is that if the pv_entry has a single page 1727 * mapped at 0x00000000 a whole cache clean will be performed rather than 1728 * just the 1 page. Since this should not occur in everyday use and if it does 1729 * it will just result in not the most efficient clean for the page. 1730 */ 1731 static int 1732 pmap_clean_page(struct pv_entry *pv, bool is_src) 1733 { 1734 pmap_t pm, pm_to_clean = NULL; 1735 struct pv_entry *npv; 1736 u_int cache_needs_cleaning = 0; 1737 u_int flags = 0; 1738 vaddr_t page_to_clean = 0; 1739 1740 if (pv == NULL) { 1741 /* nothing mapped in so nothing to flush */ 1742 return (0); 1743 } 1744 1745 /* 1746 * Since we flush the cache each time we change to a different 1747 * user vmspace, we only need to flush the page if it is in the 1748 * current pmap. 1749 */ 1750 if (curproc) 1751 pm = curproc->p_vmspace->vm_map.pmap; 1752 else 1753 pm = pmap_kernel(); 1754 1755 for (npv = pv; npv; npv = npv->pv_next) { 1756 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 1757 flags |= npv->pv_flags; 1758 /* 1759 * The page is mapped non-cacheable in 1760 * this map. No need to flush the cache. 1761 */ 1762 if (npv->pv_flags & PVF_NC) { 1763 #ifdef DIAGNOSTIC 1764 if (cache_needs_cleaning) 1765 panic("pmap_clean_page: " 1766 "cache inconsistency"); 1767 #endif 1768 break; 1769 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 1770 continue; 1771 if (cache_needs_cleaning) { 1772 page_to_clean = 0; 1773 break; 1774 } else { 1775 page_to_clean = npv->pv_va; 1776 pm_to_clean = npv->pv_pmap; 1777 } 1778 cache_needs_cleaning = 1; 1779 } 1780 } 1781 1782 if (page_to_clean) { 1783 if (PV_BEEN_EXECD(flags)) 1784 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 1785 PAGE_SIZE); 1786 else 1787 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 1788 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 1789 } else if (cache_needs_cleaning) { 1790 if (PV_BEEN_EXECD(flags)) 1791 pmap_idcache_wbinv_all(pm); 1792 else 1793 pmap_dcache_wbinv_all(pm); 1794 return (1); 1795 } 1796 return (0); 1797 } 1798 1799 /* 1800 * Routine: pmap_page_remove 1801 * Function: 1802 * Removes this physical page from 1803 * all physical maps in which it resides. 1804 * Reflects back modify bits to the pager. 1805 */ 1806 static void 1807 pmap_page_remove(struct vm_page *pg) 1808 { 1809 struct l2_bucket *l2b; 1810 struct pv_entry *pv, *npv; 1811 pmap_t pm, curpm; 1812 pt_entry_t *ptep, pte; 1813 bool flush; 1814 u_int flags; 1815 1816 NPDEBUG(PDB_FOLLOW, 1817 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 1818 VM_PAGE_TO_PHYS(pg))); 1819 1820 PMAP_HEAD_TO_MAP_LOCK(); 1821 simple_lock(&pg->mdpage.pvh_slock); 1822 1823 pv = pg->mdpage.pvh_list; 1824 if (pv == NULL) { 1825 simple_unlock(&pg->mdpage.pvh_slock); 1826 PMAP_HEAD_TO_MAP_UNLOCK(); 1827 return; 1828 } 1829 1830 /* 1831 * Clear alias counts 1832 */ 1833 pg->mdpage.k_mappings = 0; 1834 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 1835 1836 flush = false; 1837 flags = 0; 1838 if (curproc) 1839 curpm = curproc->p_vmspace->vm_map.pmap; 1840 else 1841 curpm = pmap_kernel(); 1842 1843 pmap_clean_page(pv, false); 1844 1845 while (pv) { 1846 pm = pv->pv_pmap; 1847 if (flush == false && (pm == curpm || pm == pmap_kernel())) 1848 flush = true; 1849 1850 pmap_acquire_pmap_lock(pm); 1851 1852 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 1853 KDASSERT(l2b != NULL); 1854 1855 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1856 pte = *ptep; 1857 1858 /* 1859 * Update statistics 1860 */ 1861 --pm->pm_stats.resident_count; 1862 1863 /* Wired bit */ 1864 if (pv->pv_flags & PVF_WIRED) 1865 --pm->pm_stats.wired_count; 1866 1867 flags |= pv->pv_flags; 1868 1869 /* 1870 * Invalidate the PTEs. 1871 */ 1872 *ptep = 0; 1873 PTE_SYNC_CURRENT(pm, ptep); 1874 pmap_free_l2_bucket(pm, l2b, 1); 1875 1876 npv = pv->pv_next; 1877 pool_put(&pmap_pv_pool, pv); 1878 pv = npv; 1879 pmap_release_pmap_lock(pm); 1880 } 1881 pg->mdpage.pvh_list = NULL; 1882 simple_unlock(&pg->mdpage.pvh_slock); 1883 PMAP_HEAD_TO_MAP_UNLOCK(); 1884 1885 if (flush) { 1886 /* 1887 * Note: We can't use pmap_tlb_flush{I,}D() here since that 1888 * would need a subsequent call to pmap_update() to ensure 1889 * curpm->pm_cstate.cs_all is reset. Our callers are not 1890 * required to do that (see pmap(9)), so we can't modify 1891 * the current pmap's state. 1892 */ 1893 if (PV_BEEN_EXECD(flags)) 1894 cpu_tlb_flushID(); 1895 else 1896 cpu_tlb_flushD(); 1897 } 1898 cpu_cpwait(); 1899 } 1900 1901 /* 1902 * pmap_t pmap_create(void) 1903 * 1904 * Create a new pmap structure from scratch. 1905 */ 1906 pmap_t 1907 pmap_create(void) 1908 { 1909 pmap_t pm; 1910 1911 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 1912 1913 simple_lock_init(&pm->pm_lock); 1914 pm->pm_obj.pgops = NULL; /* currently not a mappable object */ 1915 TAILQ_INIT(&pm->pm_obj.memq); 1916 pm->pm_obj.uo_npages = 0; 1917 pm->pm_obj.uo_refs = 1; 1918 pm->pm_stats.wired_count = 0; 1919 pm->pm_stats.resident_count = 1; 1920 pm->pm_cstate.cs_all = 0; 1921 pmap_alloc_l1(pm); 1922 1923 /* 1924 * Note: The pool cache ensures that the pm_l2[] array is already 1925 * initialised to zero. 1926 */ 1927 1928 pmap_pinit(pm); 1929 1930 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 1931 1932 return (pm); 1933 } 1934 1935 /* 1936 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 1937 * int flags) 1938 * 1939 * Insert the given physical page (p) at 1940 * the specified virtual address (v) in the 1941 * target physical map with the protection requested. 1942 * 1943 * NB: This is the only routine which MAY NOT lazy-evaluate 1944 * or lose information. That is, this routine must actually 1945 * insert this page into the given map NOW. 1946 */ 1947 int 1948 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 1949 { 1950 struct l2_bucket *l2b; 1951 struct vm_page *pg, *opg; 1952 struct pv_entry *pve; 1953 pt_entry_t *ptep, npte, opte; 1954 u_int nflags; 1955 u_int oflags; 1956 1957 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 1958 1959 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 1960 KDASSERT(((va | pa) & PGOFSET) == 0); 1961 1962 /* 1963 * Get a pointer to the page. Later on in this function, we 1964 * test for a managed page by checking pg != NULL. 1965 */ 1966 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 1967 1968 nflags = 0; 1969 if (prot & VM_PROT_WRITE) 1970 nflags |= PVF_WRITE; 1971 if (prot & VM_PROT_EXECUTE) 1972 nflags |= PVF_EXEC; 1973 if (flags & PMAP_WIRED) 1974 nflags |= PVF_WIRED; 1975 1976 PMAP_MAP_TO_HEAD_LOCK(); 1977 pmap_acquire_pmap_lock(pm); 1978 1979 /* 1980 * Fetch the L2 bucket which maps this page, allocating one if 1981 * necessary for user pmaps. 1982 */ 1983 if (pm == pmap_kernel()) 1984 l2b = pmap_get_l2_bucket(pm, va); 1985 else 1986 l2b = pmap_alloc_l2_bucket(pm, va); 1987 if (l2b == NULL) { 1988 if (flags & PMAP_CANFAIL) { 1989 pmap_release_pmap_lock(pm); 1990 PMAP_MAP_TO_HEAD_UNLOCK(); 1991 return (ENOMEM); 1992 } 1993 panic("pmap_enter: failed to allocate L2 bucket"); 1994 } 1995 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1996 opte = *ptep; 1997 npte = pa; 1998 oflags = 0; 1999 2000 if (opte) { 2001 /* 2002 * There is already a mapping at this address. 2003 * If the physical address is different, lookup the 2004 * vm_page. 2005 */ 2006 if (l2pte_pa(opte) != pa) 2007 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2008 else 2009 opg = pg; 2010 } else 2011 opg = NULL; 2012 2013 if (pg) { 2014 /* 2015 * This is to be a managed mapping. 2016 */ 2017 if ((flags & VM_PROT_ALL) || 2018 (pg->mdpage.pvh_attrs & PVF_REF)) { 2019 /* 2020 * - The access type indicates that we don't need 2021 * to do referenced emulation. 2022 * OR 2023 * - The physical page has already been referenced 2024 * so no need to re-do referenced emulation here. 2025 */ 2026 npte |= L2_S_PROTO; 2027 2028 nflags |= PVF_REF; 2029 2030 if ((prot & VM_PROT_WRITE) != 0 && 2031 ((flags & VM_PROT_WRITE) != 0 || 2032 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2033 /* 2034 * This is a writable mapping, and the 2035 * page's mod state indicates it has 2036 * already been modified. Make it 2037 * writable from the outset. 2038 */ 2039 npte |= L2_S_PROT_W; 2040 nflags |= PVF_MOD; 2041 } 2042 } else { 2043 /* 2044 * Need to do page referenced emulation. 2045 */ 2046 npte |= L2_TYPE_INV; 2047 } 2048 2049 npte |= pte_l2_s_cache_mode; 2050 2051 if (pg == opg) { 2052 /* 2053 * We're changing the attrs of an existing mapping. 2054 */ 2055 simple_lock(&pg->mdpage.pvh_slock); 2056 oflags = pmap_modify_pv(pg, pm, va, 2057 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2058 PVF_MOD | PVF_REF, nflags); 2059 simple_unlock(&pg->mdpage.pvh_slock); 2060 2061 /* 2062 * We may need to flush the cache if we're 2063 * doing rw-ro... 2064 */ 2065 if (pm->pm_cstate.cs_cache_d && 2066 (oflags & PVF_NC) == 0 && 2067 (opte & L2_S_PROT_W) != 0 && 2068 (prot & VM_PROT_WRITE) == 0) 2069 cpu_dcache_wb_range(va, PAGE_SIZE); 2070 } else { 2071 /* 2072 * New mapping, or changing the backing page 2073 * of an existing mapping. 2074 */ 2075 if (opg) { 2076 /* 2077 * Replacing an existing mapping with a new one. 2078 * It is part of our managed memory so we 2079 * must remove it from the PV list 2080 */ 2081 simple_lock(&opg->mdpage.pvh_slock); 2082 pve = pmap_remove_pv(opg, pm, va, 0); 2083 pmap_vac_me_harder(opg, pm, 0); 2084 simple_unlock(&opg->mdpage.pvh_slock); 2085 oflags = pve->pv_flags; 2086 2087 /* 2088 * If the old mapping was valid (ref/mod 2089 * emulation creates 'invalid' mappings 2090 * initially) then make sure to frob 2091 * the cache. 2092 */ 2093 if ((oflags & PVF_NC) == 0 && 2094 l2pte_valid(opte)) { 2095 if (PV_BEEN_EXECD(oflags)) { 2096 pmap_idcache_wbinv_range(pm, va, 2097 PAGE_SIZE); 2098 } else 2099 if (PV_BEEN_REFD(oflags)) { 2100 pmap_dcache_wb_range(pm, va, 2101 PAGE_SIZE, true, 2102 (oflags & PVF_WRITE) == 0); 2103 } 2104 } 2105 } else 2106 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2107 if ((flags & PMAP_CANFAIL) == 0) 2108 panic("pmap_enter: no pv entries"); 2109 2110 if (pm != pmap_kernel()) 2111 pmap_free_l2_bucket(pm, l2b, 0); 2112 pmap_release_pmap_lock(pm); 2113 PMAP_MAP_TO_HEAD_UNLOCK(); 2114 NPDEBUG(PDB_ENTER, 2115 printf("pmap_enter: ENOMEM\n")); 2116 return (ENOMEM); 2117 } 2118 2119 pmap_enter_pv(pg, pve, pm, va, nflags); 2120 } 2121 } else { 2122 /* 2123 * We're mapping an unmanaged page. 2124 * These are always readable, and possibly writable, from 2125 * the get go as we don't need to track ref/mod status. 2126 */ 2127 npte |= L2_S_PROTO; 2128 if (prot & VM_PROT_WRITE) 2129 npte |= L2_S_PROT_W; 2130 2131 /* 2132 * Make sure the vector table is mapped cacheable 2133 */ 2134 if (pm != pmap_kernel() && va == vector_page) 2135 npte |= pte_l2_s_cache_mode; 2136 2137 if (opg) { 2138 /* 2139 * Looks like there's an existing 'managed' mapping 2140 * at this address. 2141 */ 2142 simple_lock(&opg->mdpage.pvh_slock); 2143 pve = pmap_remove_pv(opg, pm, va, 0); 2144 pmap_vac_me_harder(opg, pm, 0); 2145 simple_unlock(&opg->mdpage.pvh_slock); 2146 oflags = pve->pv_flags; 2147 2148 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2149 if (PV_BEEN_EXECD(oflags)) 2150 pmap_idcache_wbinv_range(pm, va, 2151 PAGE_SIZE); 2152 else 2153 if (PV_BEEN_REFD(oflags)) 2154 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2155 true, (oflags & PVF_WRITE) == 0); 2156 } 2157 pool_put(&pmap_pv_pool, pve); 2158 } 2159 } 2160 2161 /* 2162 * Make sure userland mappings get the right permissions 2163 */ 2164 if (pm != pmap_kernel() && va != vector_page) 2165 npte |= L2_S_PROT_U; 2166 2167 /* 2168 * Keep the stats up to date 2169 */ 2170 if (opte == 0) { 2171 l2b->l2b_occupancy++; 2172 pm->pm_stats.resident_count++; 2173 } 2174 2175 NPDEBUG(PDB_ENTER, 2176 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2177 2178 /* 2179 * If this is just a wiring change, the two PTEs will be 2180 * identical, so there's no need to update the page table. 2181 */ 2182 if (npte != opte) { 2183 bool is_cached = pmap_is_cached(pm); 2184 2185 *ptep = npte; 2186 if (is_cached) { 2187 /* 2188 * We only need to frob the cache/tlb if this pmap 2189 * is current 2190 */ 2191 PTE_SYNC(ptep); 2192 if (va != vector_page && l2pte_valid(npte)) { 2193 /* 2194 * This mapping is likely to be accessed as 2195 * soon as we return to userland. Fix up the 2196 * L1 entry to avoid taking another 2197 * page/domain fault. 2198 */ 2199 pd_entry_t *pl1pd, l1pd; 2200 2201 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2202 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2203 L1_C_PROTO; 2204 if (*pl1pd != l1pd) { 2205 *pl1pd = l1pd; 2206 PTE_SYNC(pl1pd); 2207 } 2208 } 2209 } 2210 2211 if (PV_BEEN_EXECD(oflags)) 2212 pmap_tlb_flushID_SE(pm, va); 2213 else 2214 if (PV_BEEN_REFD(oflags)) 2215 pmap_tlb_flushD_SE(pm, va); 2216 2217 NPDEBUG(PDB_ENTER, 2218 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2219 is_cached, pm->pm_cstate.cs_all)); 2220 2221 if (pg != NULL) { 2222 simple_lock(&pg->mdpage.pvh_slock); 2223 pmap_vac_me_harder(pg, pm, va); 2224 simple_unlock(&pg->mdpage.pvh_slock); 2225 } 2226 } 2227 2228 pmap_release_pmap_lock(pm); 2229 PMAP_MAP_TO_HEAD_UNLOCK(); 2230 2231 return (0); 2232 } 2233 2234 /* 2235 * pmap_remove() 2236 * 2237 * pmap_remove is responsible for nuking a number of mappings for a range 2238 * of virtual address space in the current pmap. To do this efficiently 2239 * is interesting, because in a number of cases a wide virtual address 2240 * range may be supplied that contains few actual mappings. So, the 2241 * optimisations are: 2242 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 2243 * 2. Build up a list of pages we've hit, up to a maximum, so we can 2244 * maybe do just a partial cache clean. This path of execution is 2245 * complicated by the fact that the cache must be flushed _before_ 2246 * the PTE is nuked, being a VAC :-) 2247 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 2248 * all invalidations until pmap_update(), since pmap_remove_all() has 2249 * already flushed the cache. 2250 * 4. Maybe later fast-case a single page, but I don't think this is 2251 * going to make _that_ much difference overall. 2252 */ 2253 2254 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 2255 2256 void 2257 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 2258 { 2259 struct l2_bucket *l2b; 2260 vaddr_t next_bucket; 2261 pt_entry_t *ptep; 2262 u_int cleanlist_idx, total, cnt; 2263 struct { 2264 vaddr_t va; 2265 pt_entry_t *pte; 2266 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 2267 u_int mappings, is_exec, is_refd; 2268 2269 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 2270 "eva=%08lx\n", pm, sva, eva)); 2271 2272 /* 2273 * we lock in the pmap => pv_head direction 2274 */ 2275 PMAP_MAP_TO_HEAD_LOCK(); 2276 pmap_acquire_pmap_lock(pm); 2277 2278 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 2279 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2280 if (pm->pm_cstate.cs_tlb == 0) 2281 pm->pm_remove_all = true; 2282 } else 2283 cleanlist_idx = 0; 2284 2285 total = 0; 2286 2287 while (sva < eva) { 2288 /* 2289 * Do one L2 bucket's worth at a time. 2290 */ 2291 next_bucket = L2_NEXT_BUCKET(sva); 2292 if (next_bucket > eva) 2293 next_bucket = eva; 2294 2295 l2b = pmap_get_l2_bucket(pm, sva); 2296 if (l2b == NULL) { 2297 sva = next_bucket; 2298 continue; 2299 } 2300 2301 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2302 2303 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 2304 struct vm_page *pg; 2305 pt_entry_t pte; 2306 paddr_t pa; 2307 2308 pte = *ptep; 2309 2310 if (pte == 0) { 2311 /* Nothing here, move along */ 2312 continue; 2313 } 2314 2315 pa = l2pte_pa(pte); 2316 is_exec = 0; 2317 is_refd = 1; 2318 2319 /* 2320 * Update flags. In a number of circumstances, 2321 * we could cluster a lot of these and do a 2322 * number of sequential pages in one go. 2323 */ 2324 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 2325 struct pv_entry *pve; 2326 simple_lock(&pg->mdpage.pvh_slock); 2327 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 2328 pmap_vac_me_harder(pg, pm, 0); 2329 simple_unlock(&pg->mdpage.pvh_slock); 2330 if (pve != NULL) { 2331 if (pm->pm_remove_all == false) { 2332 is_exec = 2333 PV_BEEN_EXECD(pve->pv_flags); 2334 is_refd = 2335 PV_BEEN_REFD(pve->pv_flags); 2336 } 2337 pool_put(&pmap_pv_pool, pve); 2338 } else 2339 if (skip_wired) { 2340 /* The mapping is wired. Skip it */ 2341 continue; 2342 } 2343 } else 2344 if (skip_wired) { 2345 /* Unmanaged pages are always wired. */ 2346 continue; 2347 } 2348 2349 mappings++; 2350 2351 if (!l2pte_valid(pte)) { 2352 /* 2353 * Ref/Mod emulation is still active for this 2354 * mapping, therefore it is has not yet been 2355 * accessed. No need to frob the cache/tlb. 2356 */ 2357 *ptep = 0; 2358 PTE_SYNC_CURRENT(pm, ptep); 2359 continue; 2360 } 2361 2362 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 2363 /* Add to the clean list. */ 2364 cleanlist[cleanlist_idx].pte = ptep; 2365 cleanlist[cleanlist_idx].va = 2366 sva | (is_exec & 1); 2367 cleanlist_idx++; 2368 } else 2369 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 2370 /* Nuke everything if needed. */ 2371 pmap_idcache_wbinv_all(pm); 2372 pmap_tlb_flushID(pm); 2373 2374 /* 2375 * Roll back the previous PTE list, 2376 * and zero out the current PTE. 2377 */ 2378 for (cnt = 0; 2379 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 2380 *cleanlist[cnt].pte = 0; 2381 } 2382 *ptep = 0; 2383 PTE_SYNC(ptep); 2384 cleanlist_idx++; 2385 pm->pm_remove_all = true; 2386 } else { 2387 *ptep = 0; 2388 PTE_SYNC(ptep); 2389 if (pm->pm_remove_all == false) { 2390 if (is_exec) 2391 pmap_tlb_flushID_SE(pm, sva); 2392 else 2393 if (is_refd) 2394 pmap_tlb_flushD_SE(pm, sva); 2395 } 2396 } 2397 } 2398 2399 /* 2400 * Deal with any left overs 2401 */ 2402 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 2403 total += cleanlist_idx; 2404 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 2405 if (pm->pm_cstate.cs_all != 0) { 2406 vaddr_t clva = cleanlist[cnt].va & ~1; 2407 if (cleanlist[cnt].va & 1) { 2408 pmap_idcache_wbinv_range(pm, 2409 clva, PAGE_SIZE); 2410 pmap_tlb_flushID_SE(pm, clva); 2411 } else { 2412 pmap_dcache_wb_range(pm, 2413 clva, PAGE_SIZE, true, 2414 false); 2415 pmap_tlb_flushD_SE(pm, clva); 2416 } 2417 } 2418 *cleanlist[cnt].pte = 0; 2419 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 2420 } 2421 2422 /* 2423 * If it looks like we're removing a whole bunch 2424 * of mappings, it's faster to just write-back 2425 * the whole cache now and defer TLB flushes until 2426 * pmap_update() is called. 2427 */ 2428 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 2429 cleanlist_idx = 0; 2430 else { 2431 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2432 pmap_idcache_wbinv_all(pm); 2433 pm->pm_remove_all = true; 2434 } 2435 } 2436 2437 pmap_free_l2_bucket(pm, l2b, mappings); 2438 pm->pm_stats.resident_count -= mappings; 2439 } 2440 2441 pmap_release_pmap_lock(pm); 2442 PMAP_MAP_TO_HEAD_UNLOCK(); 2443 } 2444 2445 /* 2446 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 2447 * 2448 * We assume there is already sufficient KVM space available 2449 * to do this, as we can't allocate L2 descriptor tables/metadata 2450 * from here. 2451 */ 2452 void 2453 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 2454 { 2455 struct l2_bucket *l2b; 2456 pt_entry_t *ptep, opte; 2457 2458 NPDEBUG(PDB_KENTER, 2459 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 2460 va, pa, prot)); 2461 2462 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2463 KDASSERT(l2b != NULL); 2464 2465 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2466 opte = *ptep; 2467 2468 if (l2pte_valid(opte)) { 2469 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2470 cpu_tlb_flushD_SE(va); 2471 cpu_cpwait(); 2472 } else 2473 if (opte == 0) 2474 l2b->l2b_occupancy++; 2475 2476 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 2477 pte_l2_s_cache_mode; 2478 PTE_SYNC(ptep); 2479 } 2480 2481 void 2482 pmap_kremove(vaddr_t va, vsize_t len) 2483 { 2484 struct l2_bucket *l2b; 2485 pt_entry_t *ptep, *sptep, opte; 2486 vaddr_t next_bucket, eva; 2487 u_int mappings; 2488 2489 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 2490 va, len)); 2491 2492 eva = va + len; 2493 2494 while (va < eva) { 2495 next_bucket = L2_NEXT_BUCKET(va); 2496 if (next_bucket > eva) 2497 next_bucket = eva; 2498 2499 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2500 KDASSERT(l2b != NULL); 2501 2502 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 2503 mappings = 0; 2504 2505 while (va < next_bucket) { 2506 opte = *ptep; 2507 if (l2pte_valid(opte)) { 2508 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2509 cpu_tlb_flushD_SE(va); 2510 } 2511 if (opte) { 2512 *ptep = 0; 2513 mappings++; 2514 } 2515 va += PAGE_SIZE; 2516 ptep++; 2517 } 2518 KDASSERT(mappings <= l2b->l2b_occupancy); 2519 l2b->l2b_occupancy -= mappings; 2520 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 2521 } 2522 cpu_cpwait(); 2523 } 2524 2525 bool 2526 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 2527 { 2528 struct l2_dtable *l2; 2529 pd_entry_t *pl1pd, l1pd; 2530 pt_entry_t *ptep, pte; 2531 paddr_t pa; 2532 u_int l1idx; 2533 2534 pmap_acquire_pmap_lock(pm); 2535 2536 l1idx = L1_IDX(va); 2537 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2538 l1pd = *pl1pd; 2539 2540 if (l1pte_section_p(l1pd)) { 2541 /* 2542 * These should only happen for pmap_kernel() 2543 */ 2544 KDASSERT(pm == pmap_kernel()); 2545 pmap_release_pmap_lock(pm); 2546 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 2547 } else { 2548 /* 2549 * Note that we can't rely on the validity of the L1 2550 * descriptor as an indication that a mapping exists. 2551 * We have to look it up in the L2 dtable. 2552 */ 2553 l2 = pm->pm_l2[L2_IDX(l1idx)]; 2554 2555 if (l2 == NULL || 2556 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 2557 pmap_release_pmap_lock(pm); 2558 return (false); 2559 } 2560 2561 ptep = &ptep[l2pte_index(va)]; 2562 pte = *ptep; 2563 pmap_release_pmap_lock(pm); 2564 2565 if (pte == 0) 2566 return (false); 2567 2568 switch (pte & L2_TYPE_MASK) { 2569 case L2_TYPE_L: 2570 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 2571 break; 2572 2573 default: 2574 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 2575 break; 2576 } 2577 } 2578 2579 if (pap != NULL) 2580 *pap = pa; 2581 2582 return (true); 2583 } 2584 2585 void 2586 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 2587 { 2588 struct l2_bucket *l2b; 2589 pt_entry_t *ptep, pte; 2590 vaddr_t next_bucket; 2591 u_int flags; 2592 int flush; 2593 2594 NPDEBUG(PDB_PROTECT, 2595 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 2596 pm, sva, eva, prot)); 2597 2598 if ((prot & VM_PROT_READ) == 0) { 2599 pmap_remove(pm, sva, eva); 2600 return; 2601 } 2602 2603 if (prot & VM_PROT_WRITE) { 2604 /* 2605 * If this is a read->write transition, just ignore it and let 2606 * uvm_fault() take care of it later. 2607 */ 2608 return; 2609 } 2610 2611 PMAP_MAP_TO_HEAD_LOCK(); 2612 pmap_acquire_pmap_lock(pm); 2613 2614 /* 2615 * OK, at this point, we know we're doing write-protect operation. 2616 * If the pmap is active, write-back the range. 2617 */ 2618 pmap_dcache_wb_range(pm, sva, eva - sva, false, false); 2619 2620 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 2621 flags = 0; 2622 2623 while (sva < eva) { 2624 next_bucket = L2_NEXT_BUCKET(sva); 2625 if (next_bucket > eva) 2626 next_bucket = eva; 2627 2628 l2b = pmap_get_l2_bucket(pm, sva); 2629 if (l2b == NULL) { 2630 sva = next_bucket; 2631 continue; 2632 } 2633 2634 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2635 2636 while (sva < next_bucket) { 2637 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 2638 struct vm_page *pg; 2639 u_int f; 2640 2641 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 2642 pte &= ~L2_S_PROT_W; 2643 *ptep = pte; 2644 PTE_SYNC(ptep); 2645 2646 if (pg != NULL) { 2647 simple_lock(&pg->mdpage.pvh_slock); 2648 f = pmap_modify_pv(pg, pm, sva, 2649 PVF_WRITE, 0); 2650 pmap_vac_me_harder(pg, pm, sva); 2651 simple_unlock(&pg->mdpage.pvh_slock); 2652 } else 2653 f = PVF_REF | PVF_EXEC; 2654 2655 if (flush >= 0) { 2656 flush++; 2657 flags |= f; 2658 } else 2659 if (PV_BEEN_EXECD(f)) 2660 pmap_tlb_flushID_SE(pm, sva); 2661 else 2662 if (PV_BEEN_REFD(f)) 2663 pmap_tlb_flushD_SE(pm, sva); 2664 } 2665 2666 sva += PAGE_SIZE; 2667 ptep++; 2668 } 2669 } 2670 2671 pmap_release_pmap_lock(pm); 2672 PMAP_MAP_TO_HEAD_UNLOCK(); 2673 2674 if (flush) { 2675 if (PV_BEEN_EXECD(flags)) 2676 pmap_tlb_flushID(pm); 2677 else 2678 if (PV_BEEN_REFD(flags)) 2679 pmap_tlb_flushD(pm); 2680 } 2681 } 2682 2683 void 2684 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 2685 { 2686 2687 NPDEBUG(PDB_PROTECT, 2688 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 2689 pg, VM_PAGE_TO_PHYS(pg), prot)); 2690 2691 switch(prot) { 2692 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 2693 case VM_PROT_READ|VM_PROT_WRITE: 2694 return; 2695 2696 case VM_PROT_READ: 2697 case VM_PROT_READ|VM_PROT_EXECUTE: 2698 pmap_clearbit(pg, PVF_WRITE); 2699 break; 2700 2701 default: 2702 pmap_page_remove(pg); 2703 break; 2704 } 2705 } 2706 2707 /* 2708 * pmap_clear_modify: 2709 * 2710 * Clear the "modified" attribute for a page. 2711 */ 2712 bool 2713 pmap_clear_modify(struct vm_page *pg) 2714 { 2715 bool rv; 2716 2717 if (pg->mdpage.pvh_attrs & PVF_MOD) { 2718 rv = true; 2719 pmap_clearbit(pg, PVF_MOD); 2720 } else 2721 rv = false; 2722 2723 return (rv); 2724 } 2725 2726 /* 2727 * pmap_clear_reference: 2728 * 2729 * Clear the "referenced" attribute for a page. 2730 */ 2731 bool 2732 pmap_clear_reference(struct vm_page *pg) 2733 { 2734 bool rv; 2735 2736 if (pg->mdpage.pvh_attrs & PVF_REF) { 2737 rv = true; 2738 pmap_clearbit(pg, PVF_REF); 2739 } else 2740 rv = false; 2741 2742 return (rv); 2743 } 2744 2745 /* 2746 * pmap_is_modified: 2747 * 2748 * Test if a page has the "modified" attribute. 2749 */ 2750 /* See <arm/arm32/pmap.h> */ 2751 2752 /* 2753 * pmap_is_referenced: 2754 * 2755 * Test if a page has the "referenced" attribute. 2756 */ 2757 /* See <arm/arm32/pmap.h> */ 2758 2759 int 2760 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 2761 { 2762 struct l2_dtable *l2; 2763 struct l2_bucket *l2b; 2764 pd_entry_t *pl1pd, l1pd; 2765 pt_entry_t *ptep, pte; 2766 paddr_t pa; 2767 u_int l1idx; 2768 int rv = 0; 2769 2770 PMAP_MAP_TO_HEAD_LOCK(); 2771 pmap_acquire_pmap_lock(pm); 2772 2773 l1idx = L1_IDX(va); 2774 2775 /* 2776 * If there is no l2_dtable for this address, then the process 2777 * has no business accessing it. 2778 * 2779 * Note: This will catch userland processes trying to access 2780 * kernel addresses. 2781 */ 2782 l2 = pm->pm_l2[L2_IDX(l1idx)]; 2783 if (l2 == NULL) 2784 goto out; 2785 2786 /* 2787 * Likewise if there is no L2 descriptor table 2788 */ 2789 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2790 if (l2b->l2b_kva == NULL) 2791 goto out; 2792 2793 /* 2794 * Check the PTE itself. 2795 */ 2796 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2797 pte = *ptep; 2798 if (pte == 0) 2799 goto out; 2800 2801 /* 2802 * Catch a userland access to the vector page mapped at 0x0 2803 */ 2804 if (user && (pte & L2_S_PROT_U) == 0) 2805 goto out; 2806 2807 pa = l2pte_pa(pte); 2808 2809 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 2810 /* 2811 * This looks like a good candidate for "page modified" 2812 * emulation... 2813 */ 2814 struct pv_entry *pv; 2815 struct vm_page *pg; 2816 2817 /* Extract the physical address of the page */ 2818 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2819 goto out; 2820 2821 /* Get the current flags for this page. */ 2822 simple_lock(&pg->mdpage.pvh_slock); 2823 2824 pv = pmap_find_pv(pg, pm, va); 2825 if (pv == NULL) { 2826 simple_unlock(&pg->mdpage.pvh_slock); 2827 goto out; 2828 } 2829 2830 /* 2831 * Do the flags say this page is writable? If not then it 2832 * is a genuine write fault. If yes then the write fault is 2833 * our fault as we did not reflect the write access in the 2834 * PTE. Now we know a write has occurred we can correct this 2835 * and also set the modified bit 2836 */ 2837 if ((pv->pv_flags & PVF_WRITE) == 0) { 2838 simple_unlock(&pg->mdpage.pvh_slock); 2839 goto out; 2840 } 2841 2842 NPDEBUG(PDB_FOLLOW, 2843 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 2844 pm, va, VM_PAGE_TO_PHYS(pg))); 2845 2846 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 2847 pv->pv_flags |= PVF_REF | PVF_MOD; 2848 simple_unlock(&pg->mdpage.pvh_slock); 2849 2850 /* 2851 * Re-enable write permissions for the page. No need to call 2852 * pmap_vac_me_harder(), since this is just a 2853 * modified-emulation fault, and the PVF_WRITE bit isn't 2854 * changing. We've already set the cacheable bits based on 2855 * the assumption that we can write to this page. 2856 */ 2857 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 2858 PTE_SYNC(ptep); 2859 rv = 1; 2860 } else 2861 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2862 /* 2863 * This looks like a good candidate for "page referenced" 2864 * emulation. 2865 */ 2866 struct pv_entry *pv; 2867 struct vm_page *pg; 2868 2869 /* Extract the physical address of the page */ 2870 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2871 goto out; 2872 2873 /* Get the current flags for this page. */ 2874 simple_lock(&pg->mdpage.pvh_slock); 2875 2876 pv = pmap_find_pv(pg, pm, va); 2877 if (pv == NULL) { 2878 simple_unlock(&pg->mdpage.pvh_slock); 2879 goto out; 2880 } 2881 2882 pg->mdpage.pvh_attrs |= PVF_REF; 2883 pv->pv_flags |= PVF_REF; 2884 simple_unlock(&pg->mdpage.pvh_slock); 2885 2886 NPDEBUG(PDB_FOLLOW, 2887 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 2888 pm, va, VM_PAGE_TO_PHYS(pg))); 2889 2890 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2891 PTE_SYNC(ptep); 2892 rv = 1; 2893 } 2894 2895 /* 2896 * We know there is a valid mapping here, so simply 2897 * fix up the L1 if necessary. 2898 */ 2899 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2900 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2901 if (*pl1pd != l1pd) { 2902 *pl1pd = l1pd; 2903 PTE_SYNC(pl1pd); 2904 rv = 1; 2905 } 2906 2907 #ifdef CPU_SA110 2908 /* 2909 * There are bugs in the rev K SA110. This is a check for one 2910 * of them. 2911 */ 2912 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2913 curcpu()->ci_arm_cpurev < 3) { 2914 /* Always current pmap */ 2915 if (l2pte_valid(pte)) { 2916 extern int kernel_debug; 2917 if (kernel_debug & 1) { 2918 struct proc *p = curlwp->l_proc; 2919 printf("prefetch_abort: page is already " 2920 "mapped - pte=%p *pte=%08x\n", ptep, pte); 2921 printf("prefetch_abort: pc=%08lx proc=%p " 2922 "process=%s\n", va, p, p->p_comm); 2923 printf("prefetch_abort: far=%08x fs=%x\n", 2924 cpu_faultaddress(), cpu_faultstatus()); 2925 } 2926 #ifdef DDB 2927 if (kernel_debug & 2) 2928 Debugger(); 2929 #endif 2930 rv = 1; 2931 } 2932 } 2933 #endif /* CPU_SA110 */ 2934 2935 #ifdef DEBUG 2936 /* 2937 * If 'rv == 0' at this point, it generally indicates that there is a 2938 * stale TLB entry for the faulting address. This happens when two or 2939 * more processes are sharing an L1. Since we don't flush the TLB on 2940 * a context switch between such processes, we can take domain faults 2941 * for mappings which exist at the same VA in both processes. EVEN IF 2942 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2943 * example. 2944 * 2945 * This is extremely likely to happen if pmap_enter() updated the L1 2946 * entry for a recently entered mapping. In this case, the TLB is 2947 * flushed for the new mapping, but there may still be TLB entries for 2948 * other mappings belonging to other processes in the 1MB range 2949 * covered by the L1 entry. 2950 * 2951 * Since 'rv == 0', we know that the L1 already contains the correct 2952 * value, so the fault must be due to a stale TLB entry. 2953 * 2954 * Since we always need to flush the TLB anyway in the case where we 2955 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2956 * stale TLB entries dynamically. 2957 * 2958 * However, the above condition can ONLY happen if the current L1 is 2959 * being shared. If it happens when the L1 is unshared, it indicates 2960 * that other parts of the pmap are not doing their job WRT managing 2961 * the TLB. 2962 */ 2963 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2964 extern int last_fault_code; 2965 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2966 pm, va, ftype); 2967 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2968 l2, l2b, ptep, pl1pd); 2969 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2970 pte, l1pd, last_fault_code); 2971 #ifdef DDB 2972 Debugger(); 2973 #endif 2974 } 2975 #endif 2976 2977 cpu_tlb_flushID_SE(va); 2978 cpu_cpwait(); 2979 2980 rv = 1; 2981 2982 out: 2983 pmap_release_pmap_lock(pm); 2984 PMAP_MAP_TO_HEAD_UNLOCK(); 2985 2986 return (rv); 2987 } 2988 2989 /* 2990 * pmap_collect: free resources held by a pmap 2991 * 2992 * => optional function. 2993 * => called when a process is swapped out to free memory. 2994 */ 2995 void 2996 pmap_collect(pmap_t pm) 2997 { 2998 2999 pmap_idcache_wbinv_all(pm); 3000 pm->pm_remove_all = true; 3001 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 3002 pmap_update(pm); 3003 } 3004 3005 /* 3006 * Routine: pmap_procwr 3007 * 3008 * Function: 3009 * Synchronize caches corresponding to [addr, addr+len) in p. 3010 * 3011 */ 3012 void 3013 pmap_procwr(struct proc *p, vaddr_t va, int len) 3014 { 3015 /* We only need to do anything if it is the current process. */ 3016 if (p == curproc) 3017 cpu_icache_sync_range(va, len); 3018 } 3019 3020 /* 3021 * Routine: pmap_unwire 3022 * Function: Clear the wired attribute for a map/virtual-address pair. 3023 * 3024 * In/out conditions: 3025 * The mapping must already exist in the pmap. 3026 */ 3027 void 3028 pmap_unwire(pmap_t pm, vaddr_t va) 3029 { 3030 struct l2_bucket *l2b; 3031 pt_entry_t *ptep, pte; 3032 struct vm_page *pg; 3033 paddr_t pa; 3034 3035 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 3036 3037 PMAP_MAP_TO_HEAD_LOCK(); 3038 pmap_acquire_pmap_lock(pm); 3039 3040 l2b = pmap_get_l2_bucket(pm, va); 3041 KDASSERT(l2b != NULL); 3042 3043 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3044 pte = *ptep; 3045 3046 /* Extract the physical address of the page */ 3047 pa = l2pte_pa(pte); 3048 3049 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3050 /* Update the wired bit in the pv entry for this page. */ 3051 simple_lock(&pg->mdpage.pvh_slock); 3052 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 3053 simple_unlock(&pg->mdpage.pvh_slock); 3054 } 3055 3056 pmap_release_pmap_lock(pm); 3057 PMAP_MAP_TO_HEAD_UNLOCK(); 3058 } 3059 3060 void 3061 pmap_switch(struct lwp *olwp, struct lwp *nlwp) 3062 { 3063 extern int block_userspace_access; 3064 pmap_t opm, npm, rpm; 3065 uint32_t odacr, ndacr; 3066 int oldirqstate; 3067 3068 npm = nlwp->l_proc->p_vmspace->vm_map.pmap; 3069 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3070 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 3071 3072 /* 3073 * If TTB and DACR are unchanged, short-circuit all the 3074 * TLB/cache management stuff. 3075 */ 3076 if (olwp != NULL) { 3077 opm = olwp->l_proc->p_vmspace->vm_map.pmap; 3078 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3079 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 3080 3081 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 3082 goto all_done; 3083 } else 3084 opm = NULL; 3085 3086 block_userspace_access = 1; 3087 3088 /* 3089 * If switching to a user vmspace which is different to the 3090 * most recent one, and the most recent one is potentially 3091 * live in the cache, we must write-back and invalidate the 3092 * entire cache. 3093 */ 3094 rpm = pmap_recent_user; 3095 if (npm != pmap_kernel() && rpm && npm != rpm && 3096 rpm->pm_cstate.cs_cache) { 3097 rpm->pm_cstate.cs_cache = 0; 3098 cpu_idcache_wbinv_all(); 3099 } 3100 3101 /* No interrupts while we frob the TTB/DACR */ 3102 oldirqstate = disable_interrupts(I32_bit | F32_bit); 3103 3104 /* 3105 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 3106 * entry corresponding to 'vector_page' in the incoming L1 table 3107 * before switching to it otherwise subsequent interrupts/exceptions 3108 * (including domain faults!) will jump into hyperspace. 3109 */ 3110 if (npm->pm_pl1vec != NULL) { 3111 cpu_tlb_flushID_SE((u_int)vector_page); 3112 cpu_cpwait(); 3113 *npm->pm_pl1vec = npm->pm_l1vec; 3114 PTE_SYNC(npm->pm_pl1vec); 3115 } 3116 3117 cpu_domains(ndacr); 3118 3119 if (npm == pmap_kernel() || npm == rpm) { 3120 /* 3121 * Switching to a kernel thread, or back to the 3122 * same user vmspace as before... Simply update 3123 * the TTB (no TLB flush required) 3124 */ 3125 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 3126 "r"(npm->pm_l1->l1_physaddr)); 3127 cpu_cpwait(); 3128 } else { 3129 /* 3130 * Otherwise, update TTB and flush TLB 3131 */ 3132 cpu_context_switch(npm->pm_l1->l1_physaddr); 3133 if (rpm != NULL) 3134 rpm->pm_cstate.cs_tlb = 0; 3135 } 3136 3137 restore_interrupts(oldirqstate); 3138 3139 block_userspace_access = 0; 3140 3141 all_done: 3142 /* 3143 * The new pmap is resident. Make sure it's marked 3144 * as resident in the cache/TLB. 3145 */ 3146 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3147 if (npm != pmap_kernel()) 3148 pmap_recent_user = npm; 3149 3150 /* The old pmap is not longer active */ 3151 if (opm != NULL) 3152 opm->pm_activated = false; 3153 3154 /* But the new one is */ 3155 npm->pm_activated = true; 3156 } 3157 3158 void 3159 pmap_activate(struct lwp *l) 3160 { 3161 3162 if (l == curlwp && 3163 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == false) 3164 pmap_switch(NULL, l); 3165 } 3166 3167 void 3168 pmap_deactivate(struct lwp *l) 3169 { 3170 3171 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 3172 } 3173 3174 void 3175 pmap_update(pmap_t pm) 3176 { 3177 3178 if (pm->pm_remove_all) { 3179 /* 3180 * Finish up the pmap_remove_all() optimisation by flushing 3181 * the TLB. 3182 */ 3183 pmap_tlb_flushID(pm); 3184 pm->pm_remove_all = false; 3185 } 3186 3187 if (pmap_is_current(pm)) { 3188 /* 3189 * If we're dealing with a current userland pmap, move its L1 3190 * to the end of the LRU. 3191 */ 3192 if (pm != pmap_kernel()) 3193 pmap_use_l1(pm); 3194 3195 /* 3196 * We can assume we're done with frobbing the cache/tlb for 3197 * now. Make sure any future pmap ops don't skip cache/tlb 3198 * flushes. 3199 */ 3200 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3201 } 3202 3203 /* 3204 * make sure TLB/cache operations have completed. 3205 */ 3206 cpu_cpwait(); 3207 } 3208 3209 void 3210 pmap_remove_all(pmap_t pm) 3211 { 3212 3213 /* 3214 * The vmspace described by this pmap is about to be torn down. 3215 * Until pmap_update() is called, UVM will only make calls 3216 * to pmap_remove(). We can make life much simpler by flushing 3217 * the cache now, and deferring TLB invalidation to pmap_update(). 3218 */ 3219 pmap_idcache_wbinv_all(pm); 3220 pm->pm_remove_all = true; 3221 } 3222 3223 /* 3224 * Retire the given physical map from service. 3225 * Should only be called if the map contains no valid mappings. 3226 */ 3227 void 3228 pmap_destroy(pmap_t pm) 3229 { 3230 u_int count; 3231 3232 if (pm == NULL) 3233 return; 3234 3235 if (pm->pm_remove_all) { 3236 pmap_tlb_flushID(pm); 3237 pm->pm_remove_all = false; 3238 } 3239 3240 /* 3241 * Drop reference count 3242 */ 3243 simple_lock(&pm->pm_lock); 3244 count = --pm->pm_obj.uo_refs; 3245 simple_unlock(&pm->pm_lock); 3246 if (count > 0) { 3247 if (pmap_is_current(pm)) { 3248 if (pm != pmap_kernel()) 3249 pmap_use_l1(pm); 3250 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3251 } 3252 return; 3253 } 3254 3255 /* 3256 * reference count is zero, free pmap resources and then free pmap. 3257 */ 3258 3259 if (vector_page < KERNEL_BASE) { 3260 KDASSERT(!pmap_is_current(pm)); 3261 3262 /* Remove the vector page mapping */ 3263 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 3264 pmap_update(pm); 3265 } 3266 3267 LIST_REMOVE(pm, pm_list); 3268 3269 pmap_free_l1(pm); 3270 3271 if (pmap_recent_user == pm) 3272 pmap_recent_user = NULL; 3273 3274 /* return the pmap to the pool */ 3275 pool_cache_put(&pmap_cache, pm); 3276 } 3277 3278 3279 /* 3280 * void pmap_reference(pmap_t pm) 3281 * 3282 * Add a reference to the specified pmap. 3283 */ 3284 void 3285 pmap_reference(pmap_t pm) 3286 { 3287 3288 if (pm == NULL) 3289 return; 3290 3291 pmap_use_l1(pm); 3292 3293 simple_lock(&pm->pm_lock); 3294 pm->pm_obj.uo_refs++; 3295 simple_unlock(&pm->pm_lock); 3296 } 3297 3298 /* 3299 * pmap_zero_page() 3300 * 3301 * Zero a given physical page by mapping it at a page hook point. 3302 * In doing the zero page op, the page we zero is mapped cachable, as with 3303 * StrongARM accesses to non-cached pages are non-burst making writing 3304 * _any_ bulk data very slow. 3305 */ 3306 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3307 void 3308 pmap_zero_page_generic(paddr_t phys) 3309 { 3310 #ifdef DEBUG 3311 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3312 3313 if (pg->mdpage.pvh_list != NULL) 3314 panic("pmap_zero_page: page has mappings"); 3315 #endif 3316 3317 KDASSERT((phys & PGOFSET) == 0); 3318 3319 /* 3320 * Hook in the page, zero it, and purge the cache for that 3321 * zeroed page. Invalidate the TLB as needed. 3322 */ 3323 *cdst_pte = L2_S_PROTO | phys | 3324 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3325 PTE_SYNC(cdst_pte); 3326 cpu_tlb_flushD_SE(cdstp); 3327 cpu_cpwait(); 3328 bzero_page(cdstp); 3329 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3330 } 3331 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3332 3333 #if ARM_MMU_XSCALE == 1 3334 void 3335 pmap_zero_page_xscale(paddr_t phys) 3336 { 3337 #ifdef DEBUG 3338 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3339 3340 if (pg->mdpage.pvh_list != NULL) 3341 panic("pmap_zero_page: page has mappings"); 3342 #endif 3343 3344 KDASSERT((phys & PGOFSET) == 0); 3345 3346 /* 3347 * Hook in the page, zero it, and purge the cache for that 3348 * zeroed page. Invalidate the TLB as needed. 3349 */ 3350 *cdst_pte = L2_S_PROTO | phys | 3351 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3352 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3353 PTE_SYNC(cdst_pte); 3354 cpu_tlb_flushD_SE(cdstp); 3355 cpu_cpwait(); 3356 bzero_page(cdstp); 3357 xscale_cache_clean_minidata(); 3358 } 3359 #endif /* ARM_MMU_XSCALE == 1 */ 3360 3361 /* pmap_pageidlezero() 3362 * 3363 * The same as above, except that we assume that the page is not 3364 * mapped. This means we never have to flush the cache first. Called 3365 * from the idle loop. 3366 */ 3367 bool 3368 pmap_pageidlezero(paddr_t phys) 3369 { 3370 unsigned int i; 3371 int *ptr; 3372 bool rv = true; 3373 #ifdef DEBUG 3374 struct vm_page *pg; 3375 3376 pg = PHYS_TO_VM_PAGE(phys); 3377 if (pg->mdpage.pvh_list != NULL) 3378 panic("pmap_pageidlezero: page has mappings"); 3379 #endif 3380 3381 KDASSERT((phys & PGOFSET) == 0); 3382 3383 /* 3384 * Hook in the page, zero it, and purge the cache for that 3385 * zeroed page. Invalidate the TLB as needed. 3386 */ 3387 *cdst_pte = L2_S_PROTO | phys | 3388 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3389 PTE_SYNC(cdst_pte); 3390 cpu_tlb_flushD_SE(cdstp); 3391 cpu_cpwait(); 3392 3393 for (i = 0, ptr = (int *)cdstp; 3394 i < (PAGE_SIZE / sizeof(int)); i++) { 3395 if (sched_curcpu_runnable_p()) { 3396 /* 3397 * A process has become ready. Abort now, 3398 * so we don't keep it waiting while we 3399 * do slow memory access to finish this 3400 * page. 3401 */ 3402 rv = false; 3403 break; 3404 } 3405 *ptr++ = 0; 3406 } 3407 3408 if (rv) 3409 /* 3410 * if we aborted we'll rezero this page again later so don't 3411 * purge it unless we finished it 3412 */ 3413 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3414 3415 return (rv); 3416 } 3417 3418 /* 3419 * pmap_copy_page() 3420 * 3421 * Copy one physical page into another, by mapping the pages into 3422 * hook points. The same comment regarding cachability as in 3423 * pmap_zero_page also applies here. 3424 */ 3425 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3426 void 3427 pmap_copy_page_generic(paddr_t src, paddr_t dst) 3428 { 3429 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 3430 #ifdef DEBUG 3431 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 3432 3433 if (dst_pg->mdpage.pvh_list != NULL) 3434 panic("pmap_copy_page: dst page has mappings"); 3435 #endif 3436 3437 KDASSERT((src & PGOFSET) == 0); 3438 KDASSERT((dst & PGOFSET) == 0); 3439 3440 /* 3441 * Clean the source page. Hold the source page's lock for 3442 * the duration of the copy so that no other mappings can 3443 * be created while we have a potentially aliased mapping. 3444 */ 3445 simple_lock(&src_pg->mdpage.pvh_slock); 3446 (void) pmap_clean_page(src_pg->mdpage.pvh_list, true); 3447 3448 /* 3449 * Map the pages into the page hook points, copy them, and purge 3450 * the cache for the appropriate page. Invalidate the TLB 3451 * as required. 3452 */ 3453 *csrc_pte = L2_S_PROTO | src | 3454 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 3455 PTE_SYNC(csrc_pte); 3456 *cdst_pte = L2_S_PROTO | dst | 3457 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3458 PTE_SYNC(cdst_pte); 3459 cpu_tlb_flushD_SE(csrcp); 3460 cpu_tlb_flushD_SE(cdstp); 3461 cpu_cpwait(); 3462 bcopy_page(csrcp, cdstp); 3463 cpu_dcache_inv_range(csrcp, PAGE_SIZE); 3464 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 3465 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3466 } 3467 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3468 3469 #if ARM_MMU_XSCALE == 1 3470 void 3471 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 3472 { 3473 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 3474 #ifdef DEBUG 3475 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 3476 3477 if (dst_pg->mdpage.pvh_list != NULL) 3478 panic("pmap_copy_page: dst page has mappings"); 3479 #endif 3480 3481 KDASSERT((src & PGOFSET) == 0); 3482 KDASSERT((dst & PGOFSET) == 0); 3483 3484 /* 3485 * Clean the source page. Hold the source page's lock for 3486 * the duration of the copy so that no other mappings can 3487 * be created while we have a potentially aliased mapping. 3488 */ 3489 simple_lock(&src_pg->mdpage.pvh_slock); 3490 (void) pmap_clean_page(src_pg->mdpage.pvh_list, true); 3491 3492 /* 3493 * Map the pages into the page hook points, copy them, and purge 3494 * the cache for the appropriate page. Invalidate the TLB 3495 * as required. 3496 */ 3497 *csrc_pte = L2_S_PROTO | src | 3498 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 3499 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3500 PTE_SYNC(csrc_pte); 3501 *cdst_pte = L2_S_PROTO | dst | 3502 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3503 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3504 PTE_SYNC(cdst_pte); 3505 cpu_tlb_flushD_SE(csrcp); 3506 cpu_tlb_flushD_SE(cdstp); 3507 cpu_cpwait(); 3508 bcopy_page(csrcp, cdstp); 3509 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 3510 xscale_cache_clean_minidata(); 3511 } 3512 #endif /* ARM_MMU_XSCALE == 1 */ 3513 3514 /* 3515 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 3516 * 3517 * Return the start and end addresses of the kernel's virtual space. 3518 * These values are setup in pmap_bootstrap and are updated as pages 3519 * are allocated. 3520 */ 3521 void 3522 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 3523 { 3524 *start = virtual_avail; 3525 *end = virtual_end; 3526 } 3527 3528 /* 3529 * Helper function for pmap_grow_l2_bucket() 3530 */ 3531 static inline int 3532 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 3533 { 3534 struct l2_bucket *l2b; 3535 pt_entry_t *ptep; 3536 paddr_t pa; 3537 3538 if (uvm.page_init_done == false) { 3539 if (uvm_page_physget(&pa) == false) 3540 return (1); 3541 } else { 3542 struct vm_page *pg; 3543 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 3544 if (pg == NULL) 3545 return (1); 3546 pa = VM_PAGE_TO_PHYS(pg); 3547 } 3548 3549 if (pap) 3550 *pap = pa; 3551 3552 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3553 KDASSERT(l2b != NULL); 3554 3555 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3556 *ptep = L2_S_PROTO | pa | cache_mode | 3557 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 3558 PTE_SYNC(ptep); 3559 memset((void *)va, 0, PAGE_SIZE); 3560 return (0); 3561 } 3562 3563 /* 3564 * This is the same as pmap_alloc_l2_bucket(), except that it is only 3565 * used by pmap_growkernel(). 3566 */ 3567 static inline struct l2_bucket * 3568 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 3569 { 3570 struct l2_dtable *l2; 3571 struct l2_bucket *l2b; 3572 u_short l1idx; 3573 vaddr_t nva; 3574 3575 l1idx = L1_IDX(va); 3576 3577 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 3578 /* 3579 * No mapping at this address, as there is 3580 * no entry in the L1 table. 3581 * Need to allocate a new l2_dtable. 3582 */ 3583 nva = pmap_kernel_l2dtable_kva; 3584 if ((nva & PGOFSET) == 0) { 3585 /* 3586 * Need to allocate a backing page 3587 */ 3588 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 3589 return (NULL); 3590 } 3591 3592 l2 = (struct l2_dtable *)nva; 3593 nva += sizeof(struct l2_dtable); 3594 3595 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 3596 /* 3597 * The new l2_dtable straddles a page boundary. 3598 * Map in another page to cover it. 3599 */ 3600 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 3601 return (NULL); 3602 } 3603 3604 pmap_kernel_l2dtable_kva = nva; 3605 3606 /* 3607 * Link it into the parent pmap 3608 */ 3609 pm->pm_l2[L2_IDX(l1idx)] = l2; 3610 } 3611 3612 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3613 3614 /* 3615 * Fetch pointer to the L2 page table associated with the address. 3616 */ 3617 if (l2b->l2b_kva == NULL) { 3618 pt_entry_t *ptep; 3619 3620 /* 3621 * No L2 page table has been allocated. Chances are, this 3622 * is because we just allocated the l2_dtable, above. 3623 */ 3624 nva = pmap_kernel_l2ptp_kva; 3625 ptep = (pt_entry_t *)nva; 3626 if ((nva & PGOFSET) == 0) { 3627 /* 3628 * Need to allocate a backing page 3629 */ 3630 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 3631 &pmap_kernel_l2ptp_phys)) 3632 return (NULL); 3633 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 3634 } 3635 3636 l2->l2_occupancy++; 3637 l2b->l2b_kva = ptep; 3638 l2b->l2b_l1idx = l1idx; 3639 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 3640 3641 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 3642 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 3643 } 3644 3645 return (l2b); 3646 } 3647 3648 vaddr_t 3649 pmap_growkernel(vaddr_t maxkvaddr) 3650 { 3651 pmap_t kpm = pmap_kernel(); 3652 struct l1_ttable *l1; 3653 struct l2_bucket *l2b; 3654 pd_entry_t *pl1pd; 3655 int s; 3656 3657 if (maxkvaddr <= pmap_curmaxkvaddr) 3658 goto out; /* we are OK */ 3659 3660 NPDEBUG(PDB_GROWKERN, 3661 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 3662 pmap_curmaxkvaddr, maxkvaddr)); 3663 3664 KDASSERT(maxkvaddr <= virtual_end); 3665 3666 /* 3667 * whoops! we need to add kernel PTPs 3668 */ 3669 3670 s = splhigh(); /* to be safe */ 3671 simple_lock(&kpm->pm_lock); 3672 3673 /* Map 1MB at a time */ 3674 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 3675 3676 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 3677 KDASSERT(l2b != NULL); 3678 3679 /* Distribute new L1 entry to all other L1s */ 3680 SLIST_FOREACH(l1, &l1_list, l1_link) { 3681 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 3682 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 3683 L1_C_PROTO; 3684 PTE_SYNC(pl1pd); 3685 } 3686 } 3687 3688 /* 3689 * flush out the cache, expensive but growkernel will happen so 3690 * rarely 3691 */ 3692 cpu_dcache_wbinv_all(); 3693 cpu_tlb_flushD(); 3694 cpu_cpwait(); 3695 3696 simple_unlock(&kpm->pm_lock); 3697 splx(s); 3698 3699 out: 3700 return (pmap_curmaxkvaddr); 3701 } 3702 3703 /************************ Utility routines ****************************/ 3704 3705 /* 3706 * vector_page_setprot: 3707 * 3708 * Manipulate the protection of the vector page. 3709 */ 3710 void 3711 vector_page_setprot(int prot) 3712 { 3713 struct l2_bucket *l2b; 3714 pt_entry_t *ptep; 3715 3716 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 3717 KDASSERT(l2b != NULL); 3718 3719 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 3720 3721 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 3722 PTE_SYNC(ptep); 3723 cpu_tlb_flushD_SE(vector_page); 3724 cpu_cpwait(); 3725 } 3726 3727 /* 3728 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3729 * Returns true if the mapping exists, else false. 3730 * 3731 * NOTE: This function is only used by a couple of arm-specific modules. 3732 * It is not safe to take any pmap locks here, since we could be right 3733 * in the middle of debugging the pmap anyway... 3734 * 3735 * It is possible for this routine to return false even though a valid 3736 * mapping does exist. This is because we don't lock, so the metadata 3737 * state may be inconsistent. 3738 * 3739 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3740 * a "section" mapping. 3741 */ 3742 bool 3743 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3744 { 3745 struct l2_dtable *l2; 3746 pd_entry_t *pl1pd, l1pd; 3747 pt_entry_t *ptep; 3748 u_short l1idx; 3749 3750 if (pm->pm_l1 == NULL) 3751 return (false); 3752 3753 l1idx = L1_IDX(va); 3754 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3755 l1pd = *pl1pd; 3756 3757 if (l1pte_section_p(l1pd)) { 3758 *ptp = NULL; 3759 return (true); 3760 } 3761 3762 if (pm->pm_l2 == NULL) 3763 return (false); 3764 3765 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3766 3767 if (l2 == NULL || 3768 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3769 return (false); 3770 } 3771 3772 *ptp = &ptep[l2pte_index(va)]; 3773 return (true); 3774 } 3775 3776 bool 3777 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 3778 { 3779 u_short l1idx; 3780 3781 if (pm->pm_l1 == NULL) 3782 return (false); 3783 3784 l1idx = L1_IDX(va); 3785 *pdp = &pm->pm_l1->l1_kva[l1idx]; 3786 3787 return (true); 3788 } 3789 3790 /************************ Bootstrapping routines ****************************/ 3791 3792 static void 3793 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 3794 { 3795 int i; 3796 3797 l1->l1_kva = l1pt; 3798 l1->l1_domain_use_count = 0; 3799 l1->l1_domain_first = 0; 3800 3801 for (i = 0; i < PMAP_DOMAINS; i++) 3802 l1->l1_domain_free[i] = i + 1; 3803 3804 /* 3805 * Copy the kernel's L1 entries to each new L1. 3806 */ 3807 if (pmap_initialized) 3808 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 3809 3810 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 3811 &l1->l1_physaddr) == false) 3812 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 3813 3814 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 3815 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 3816 } 3817 3818 /* 3819 * pmap_bootstrap() is called from the board-specific initarm() routine 3820 * once the kernel L1/L2 descriptors tables have been set up. 3821 * 3822 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 3823 * spread over a number of disparate files/functions. 3824 * 3825 * We are passed the following parameters 3826 * - kernel_l1pt 3827 * This is a pointer to the base of the kernel's L1 translation table. 3828 * - vstart 3829 * 1MB-aligned start of managed kernel virtual memory. 3830 * - vend 3831 * 1MB-aligned end of managed kernel virtual memory. 3832 * 3833 * We use the first parameter to build the metadata (struct l1_ttable and 3834 * struct l2_dtable) necessary to track kernel mappings. 3835 */ 3836 #define PMAP_STATIC_L2_SIZE 16 3837 void 3838 pmap_bootstrap(pd_entry_t *kernel_l1pt, vaddr_t vstart, vaddr_t vend) 3839 { 3840 static struct l1_ttable static_l1; 3841 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 3842 struct l1_ttable *l1 = &static_l1; 3843 struct l2_dtable *l2; 3844 struct l2_bucket *l2b; 3845 pmap_t pm = pmap_kernel(); 3846 pd_entry_t pde; 3847 pt_entry_t *ptep; 3848 paddr_t pa; 3849 vaddr_t va; 3850 vsize_t size; 3851 int l1idx, l2idx, l2next = 0; 3852 3853 /* 3854 * Initialise the kernel pmap object 3855 */ 3856 pm->pm_l1 = l1; 3857 pm->pm_domain = PMAP_DOMAIN_KERNEL; 3858 pm->pm_activated = true; 3859 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3860 simple_lock_init(&pm->pm_lock); 3861 pm->pm_obj.pgops = NULL; 3862 TAILQ_INIT(&pm->pm_obj.memq); 3863 pm->pm_obj.uo_npages = 0; 3864 pm->pm_obj.uo_refs = 1; 3865 3866 /* 3867 * Scan the L1 translation table created by initarm() and create 3868 * the required metadata for all valid mappings found in it. 3869 */ 3870 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 3871 pde = kernel_l1pt[l1idx]; 3872 3873 /* 3874 * We're only interested in Coarse mappings. 3875 * pmap_extract() can deal with section mappings without 3876 * recourse to checking L2 metadata. 3877 */ 3878 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 3879 continue; 3880 3881 /* 3882 * Lookup the KVA of this L2 descriptor table 3883 */ 3884 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 3885 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 3886 if (ptep == NULL) { 3887 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 3888 (u_int)l1idx << L1_S_SHIFT, pa); 3889 } 3890 3891 /* 3892 * Fetch the associated L2 metadata structure. 3893 * Allocate a new one if necessary. 3894 */ 3895 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 3896 if (l2next == PMAP_STATIC_L2_SIZE) 3897 panic("pmap_bootstrap: out of static L2s"); 3898 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 3899 } 3900 3901 /* 3902 * One more L1 slot tracked... 3903 */ 3904 l2->l2_occupancy++; 3905 3906 /* 3907 * Fill in the details of the L2 descriptor in the 3908 * appropriate bucket. 3909 */ 3910 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3911 l2b->l2b_kva = ptep; 3912 l2b->l2b_phys = pa; 3913 l2b->l2b_l1idx = l1idx; 3914 3915 /* 3916 * Establish an initial occupancy count for this descriptor 3917 */ 3918 for (l2idx = 0; 3919 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 3920 l2idx++) { 3921 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 3922 l2b->l2b_occupancy++; 3923 } 3924 } 3925 3926 /* 3927 * Make sure the descriptor itself has the correct cache mode. 3928 * If not, fix it, but whine about the problem. Port-meisters 3929 * should consider this a clue to fix up their initarm() 3930 * function. :) 3931 */ 3932 if (pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)ptep)) { 3933 printf("pmap_bootstrap: WARNING! wrong cache mode for " 3934 "L2 pte @ %p\n", ptep); 3935 } 3936 } 3937 3938 /* 3939 * Ensure the primary (kernel) L1 has the correct cache mode for 3940 * a page table. Bitch if it is not correctly set. 3941 */ 3942 for (va = (vaddr_t)kernel_l1pt; 3943 va < ((vaddr_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 3944 if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 3945 printf("pmap_bootstrap: WARNING! wrong cache mode for " 3946 "primary L1 @ 0x%lx\n", va); 3947 } 3948 3949 cpu_dcache_wbinv_all(); 3950 cpu_tlb_flushID(); 3951 cpu_cpwait(); 3952 3953 /* 3954 * now we allocate the "special" VAs which are used for tmp mappings 3955 * by the pmap (and other modules). we allocate the VAs by advancing 3956 * virtual_avail (note that there are no pages mapped at these VAs). 3957 * 3958 * Managed KVM space start from wherever initarm() tells us. 3959 */ 3960 virtual_avail = vstart; 3961 virtual_end = vend; 3962 3963 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 3964 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)csrc_pte); 3965 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 3966 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)cdst_pte); 3967 pmap_alloc_specials(&virtual_avail, 1, &memhook, NULL); 3968 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 3969 (void *)&msgbufaddr, NULL); 3970 3971 /* 3972 * Allocate a range of kernel virtual address space to be used 3973 * for L2 descriptor tables and metadata allocation in 3974 * pmap_growkernel(). 3975 */ 3976 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 3977 pmap_alloc_specials(&virtual_avail, 3978 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 3979 &pmap_kernel_l2ptp_kva, NULL); 3980 3981 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 3982 pmap_alloc_specials(&virtual_avail, 3983 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 3984 &pmap_kernel_l2dtable_kva, NULL); 3985 3986 /* 3987 * init the static-global locks and global pmap list. 3988 */ 3989 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 3990 3991 /* 3992 * We can now initialise the first L1's metadata. 3993 */ 3994 SLIST_INIT(&l1_list); 3995 TAILQ_INIT(&l1_lru_list); 3996 simple_lock_init(&l1_lru_lock); 3997 pmap_init_l1(l1, kernel_l1pt); 3998 3999 /* Set up vector page L1 details, if necessary */ 4000 if (vector_page < KERNEL_BASE) { 4001 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 4002 l2b = pmap_get_l2_bucket(pm, vector_page); 4003 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 4004 L1_C_DOM(pm->pm_domain); 4005 } else 4006 pm->pm_pl1vec = NULL; 4007 4008 /* 4009 * Initialize the pmap cache 4010 */ 4011 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 4012 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 4013 LIST_INIT(&pmap_pmaps); 4014 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 4015 4016 /* 4017 * Initialize the pv pool. 4018 */ 4019 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 4020 &pmap_bootstrap_pv_allocator, IPL_NONE); 4021 4022 /* 4023 * Initialize the L2 dtable pool and cache. 4024 */ 4025 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 4026 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 4027 4028 /* 4029 * Initialise the L2 descriptor table pool and cache 4030 */ 4031 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 4032 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 4033 pmap_l2ptp_ctor, NULL, NULL); 4034 4035 cpu_dcache_wbinv_all(); 4036 } 4037 4038 static int 4039 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 4040 { 4041 pd_entry_t *pdep, pde; 4042 pt_entry_t *ptep, pte; 4043 vaddr_t pa; 4044 int rv = 0; 4045 4046 /* 4047 * Make sure the descriptor itself has the correct cache mode 4048 */ 4049 pdep = &kl1[L1_IDX(va)]; 4050 pde = *pdep; 4051 4052 if (l1pte_section_p(pde)) { 4053 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 4054 *pdep = (pde & ~L1_S_CACHE_MASK) | 4055 pte_l1_s_cache_mode_pt; 4056 PTE_SYNC(pdep); 4057 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 4058 rv = 1; 4059 } 4060 } else { 4061 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 4062 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 4063 if (ptep == NULL) 4064 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 4065 4066 ptep = &ptep[l2pte_index(va)]; 4067 pte = *ptep; 4068 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 4069 *ptep = (pte & ~L2_S_CACHE_MASK) | 4070 pte_l2_s_cache_mode_pt; 4071 PTE_SYNC(ptep); 4072 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 4073 rv = 1; 4074 } 4075 } 4076 4077 return (rv); 4078 } 4079 4080 static void 4081 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 4082 { 4083 vaddr_t va = *availp; 4084 struct l2_bucket *l2b; 4085 4086 if (ptep) { 4087 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4088 if (l2b == NULL) 4089 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 4090 4091 if (ptep) 4092 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 4093 } 4094 4095 *vap = va; 4096 *availp = va + (PAGE_SIZE * pages); 4097 } 4098 4099 void 4100 pmap_init(void) 4101 { 4102 extern int physmem; 4103 4104 /* 4105 * Set the available memory vars - These do not map to real memory 4106 * addresses and cannot as the physical memory is fragmented. 4107 * They are used by ps for %mem calculations. 4108 * One could argue whether this should be the entire memory or just 4109 * the memory that is useable in a user process. 4110 */ 4111 avail_start = 0; 4112 avail_end = physmem * PAGE_SIZE; 4113 4114 /* 4115 * Now we need to free enough pv_entry structures to allow us to get 4116 * the kmem_map/kmem_object allocated and inited (done after this 4117 * function is finished). to do this we allocate one bootstrap page out 4118 * of kernel_map and use it to provide an initial pool of pv_entry 4119 * structures. we never free this page. 4120 */ 4121 pool_setlowat(&pmap_pv_pool, 4122 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 4123 4124 pmap_initialized = true; 4125 } 4126 4127 static vaddr_t last_bootstrap_page = 0; 4128 static void *free_bootstrap_pages = NULL; 4129 4130 static void * 4131 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 4132 { 4133 extern void *pool_page_alloc(struct pool *, int); 4134 vaddr_t new_page; 4135 void *rv; 4136 4137 if (pmap_initialized) 4138 return (pool_page_alloc(pp, flags)); 4139 4140 if (free_bootstrap_pages) { 4141 rv = free_bootstrap_pages; 4142 free_bootstrap_pages = *((void **)rv); 4143 return (rv); 4144 } 4145 4146 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 4147 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 4148 4149 KASSERT(new_page > last_bootstrap_page); 4150 last_bootstrap_page = new_page; 4151 return ((void *)new_page); 4152 } 4153 4154 static void 4155 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 4156 { 4157 extern void pool_page_free(struct pool *, void *); 4158 4159 if ((vaddr_t)v <= last_bootstrap_page) { 4160 *((void **)v) = free_bootstrap_pages; 4161 free_bootstrap_pages = v; 4162 return; 4163 } 4164 4165 if (pmap_initialized) { 4166 pool_page_free(pp, v); 4167 return; 4168 } 4169 } 4170 4171 /* 4172 * pmap_postinit() 4173 * 4174 * This routine is called after the vm and kmem subsystems have been 4175 * initialised. This allows the pmap code to perform any initialisation 4176 * that can only be done one the memory allocation is in place. 4177 */ 4178 void 4179 pmap_postinit(void) 4180 { 4181 extern paddr_t physical_start, physical_end; 4182 struct l2_bucket *l2b; 4183 struct l1_ttable *l1; 4184 struct pglist plist; 4185 struct vm_page *m; 4186 pd_entry_t *pl1pt; 4187 pt_entry_t *ptep, pte; 4188 vaddr_t va, eva; 4189 u_int loop, needed; 4190 int error; 4191 4192 pool_cache_setlowat(&pmap_l2ptp_cache, 4193 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 4194 pool_cache_setlowat(&pmap_l2dtable_cache, 4195 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 4196 4197 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 4198 needed -= 1; 4199 4200 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 4201 4202 for (loop = 0; loop < needed; loop++, l1++) { 4203 /* Allocate a L1 page table */ 4204 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 4205 if (va == 0) 4206 panic("Cannot allocate L1 KVM"); 4207 4208 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 4209 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 4210 if (error) 4211 panic("Cannot allocate L1 physical pages"); 4212 4213 m = TAILQ_FIRST(&plist); 4214 eva = va + L1_TABLE_SIZE; 4215 pl1pt = (pd_entry_t *)va; 4216 4217 while (m && va < eva) { 4218 paddr_t pa = VM_PAGE_TO_PHYS(m); 4219 4220 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 4221 4222 /* 4223 * Make sure the L1 descriptor table is mapped 4224 * with the cache-mode set to write-through. 4225 */ 4226 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4227 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4228 pte = *ptep; 4229 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 4230 *ptep = pte; 4231 PTE_SYNC(ptep); 4232 cpu_tlb_flushD_SE(va); 4233 4234 va += PAGE_SIZE; 4235 m = TAILQ_NEXT(m, pageq); 4236 } 4237 4238 #ifdef DIAGNOSTIC 4239 if (m) 4240 panic("pmap_alloc_l1pt: pglist not empty"); 4241 #endif /* DIAGNOSTIC */ 4242 4243 pmap_init_l1(l1, pl1pt); 4244 } 4245 4246 #ifdef DEBUG 4247 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 4248 needed); 4249 #endif 4250 } 4251 4252 /* 4253 * Note that the following routines are used by board-specific initialisation 4254 * code to configure the initial kernel page tables. 4255 * 4256 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 4257 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 4258 * behaviour of the old pmap, and provides an easy migration path for 4259 * initial bring-up of the new pmap on existing ports. Fortunately, 4260 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 4261 * will be deprecated. 4262 * 4263 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 4264 * tables. 4265 */ 4266 4267 /* 4268 * This list exists for the benefit of pmap_map_chunk(). It keeps track 4269 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 4270 * find them as necessary. 4271 * 4272 * Note that the data on this list MUST remain valid after initarm() returns, 4273 * as pmap_bootstrap() uses it to contruct L2 table metadata. 4274 */ 4275 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 4276 4277 static vaddr_t 4278 kernel_pt_lookup(paddr_t pa) 4279 { 4280 pv_addr_t *pv; 4281 4282 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 4283 #ifndef ARM32_NEW_VM_LAYOUT 4284 if (pv->pv_pa == (pa & ~PGOFSET)) 4285 return (pv->pv_va | (pa & PGOFSET)); 4286 #else 4287 if (pv->pv_pa == pa) 4288 return (pv->pv_va); 4289 #endif 4290 } 4291 return (0); 4292 } 4293 4294 /* 4295 * pmap_map_section: 4296 * 4297 * Create a single section mapping. 4298 */ 4299 void 4300 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 4301 { 4302 pd_entry_t *pde = (pd_entry_t *) l1pt; 4303 pd_entry_t fl; 4304 4305 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 4306 4307 switch (cache) { 4308 case PTE_NOCACHE: 4309 default: 4310 fl = 0; 4311 break; 4312 4313 case PTE_CACHE: 4314 fl = pte_l1_s_cache_mode; 4315 break; 4316 4317 case PTE_PAGETABLE: 4318 fl = pte_l1_s_cache_mode_pt; 4319 break; 4320 } 4321 4322 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4323 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4324 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4325 } 4326 4327 /* 4328 * pmap_map_entry: 4329 * 4330 * Create a single page mapping. 4331 */ 4332 void 4333 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 4334 { 4335 pd_entry_t *pde = (pd_entry_t *) l1pt; 4336 pt_entry_t fl; 4337 pt_entry_t *pte; 4338 4339 KASSERT(((va | pa) & PGOFSET) == 0); 4340 4341 switch (cache) { 4342 case PTE_NOCACHE: 4343 default: 4344 fl = 0; 4345 break; 4346 4347 case PTE_CACHE: 4348 fl = pte_l2_s_cache_mode; 4349 break; 4350 4351 case PTE_PAGETABLE: 4352 fl = pte_l2_s_cache_mode_pt; 4353 break; 4354 } 4355 4356 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4357 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 4358 4359 #ifndef ARM32_NEW_VM_LAYOUT 4360 pte = (pt_entry_t *) 4361 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4362 #else 4363 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4364 #endif 4365 if (pte == NULL) 4366 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 4367 4368 #ifndef ARM32_NEW_VM_LAYOUT 4369 pte[(va >> PGSHIFT) & 0x3ff] = 4370 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4371 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 4372 #else 4373 pte[l2pte_index(va)] = 4374 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4375 PTE_SYNC(&pte[l2pte_index(va)]); 4376 #endif 4377 } 4378 4379 /* 4380 * pmap_link_l2pt: 4381 * 4382 * Link the L2 page table specified by "l2pv" into the L1 4383 * page table at the slot for "va". 4384 */ 4385 void 4386 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 4387 { 4388 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4389 u_int slot = va >> L1_S_SHIFT; 4390 4391 #ifndef ARM32_NEW_VM_LAYOUT 4392 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 4393 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 4394 #endif 4395 4396 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4397 4398 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4399 #ifdef ARM32_NEW_VM_LAYOUT 4400 PTE_SYNC(&pde[slot]); 4401 #else 4402 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 4403 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 4404 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 4405 PTE_SYNC_RANGE(&pde[slot + 0], 4); 4406 #endif 4407 4408 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4409 } 4410 4411 /* 4412 * pmap_map_chunk: 4413 * 4414 * Map a chunk of memory using the most efficient mappings 4415 * possible (section, large page, small page) into the 4416 * provided L1 and L2 tables at the specified virtual address. 4417 */ 4418 vsize_t 4419 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 4420 int prot, int cache) 4421 { 4422 pd_entry_t *pde = (pd_entry_t *) l1pt; 4423 pt_entry_t *pte, f1, f2s, f2l; 4424 vsize_t resid; 4425 int i; 4426 4427 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4428 4429 if (l1pt == 0) 4430 panic("pmap_map_chunk: no L1 table provided"); 4431 4432 #ifdef VERBOSE_INIT_ARM 4433 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 4434 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4435 #endif 4436 4437 switch (cache) { 4438 case PTE_NOCACHE: 4439 default: 4440 f1 = 0; 4441 f2l = 0; 4442 f2s = 0; 4443 break; 4444 4445 case PTE_CACHE: 4446 f1 = pte_l1_s_cache_mode; 4447 f2l = pte_l2_l_cache_mode; 4448 f2s = pte_l2_s_cache_mode; 4449 break; 4450 4451 case PTE_PAGETABLE: 4452 f1 = pte_l1_s_cache_mode_pt; 4453 f2l = pte_l2_l_cache_mode_pt; 4454 f2s = pte_l2_s_cache_mode_pt; 4455 break; 4456 } 4457 4458 size = resid; 4459 4460 while (resid > 0) { 4461 /* See if we can use a section mapping. */ 4462 if (L1_S_MAPPABLE_P(va, pa, resid)) { 4463 #ifdef VERBOSE_INIT_ARM 4464 printf("S"); 4465 #endif 4466 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4467 L1_S_PROT(PTE_KERNEL, prot) | f1 | 4468 L1_S_DOM(PMAP_DOMAIN_KERNEL); 4469 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4470 va += L1_S_SIZE; 4471 pa += L1_S_SIZE; 4472 resid -= L1_S_SIZE; 4473 continue; 4474 } 4475 4476 /* 4477 * Ok, we're going to use an L2 table. Make sure 4478 * one is actually in the corresponding L1 slot 4479 * for the current VA. 4480 */ 4481 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4482 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 4483 4484 #ifndef ARM32_NEW_VM_LAYOUT 4485 pte = (pt_entry_t *) 4486 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4487 #else 4488 pte = (pt_entry_t *) kernel_pt_lookup( 4489 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4490 #endif 4491 if (pte == NULL) 4492 panic("pmap_map_chunk: can't find L2 table for VA" 4493 "0x%08lx", va); 4494 4495 /* See if we can use a L2 large page mapping. */ 4496 if (L2_L_MAPPABLE_P(va, pa, resid)) { 4497 #ifdef VERBOSE_INIT_ARM 4498 printf("L"); 4499 #endif 4500 for (i = 0; i < 16; i++) { 4501 #ifndef ARM32_NEW_VM_LAYOUT 4502 pte[((va >> PGSHIFT) & 0x3f0) + i] = 4503 L2_L_PROTO | pa | 4504 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4505 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 4506 #else 4507 pte[l2pte_index(va) + i] = 4508 L2_L_PROTO | pa | 4509 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4510 PTE_SYNC(&pte[l2pte_index(va) + i]); 4511 #endif 4512 } 4513 va += L2_L_SIZE; 4514 pa += L2_L_SIZE; 4515 resid -= L2_L_SIZE; 4516 continue; 4517 } 4518 4519 /* Use a small page mapping. */ 4520 #ifdef VERBOSE_INIT_ARM 4521 printf("P"); 4522 #endif 4523 #ifndef ARM32_NEW_VM_LAYOUT 4524 pte[(va >> PGSHIFT) & 0x3ff] = 4525 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4526 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 4527 #else 4528 pte[l2pte_index(va)] = 4529 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4530 PTE_SYNC(&pte[l2pte_index(va)]); 4531 #endif 4532 va += PAGE_SIZE; 4533 pa += PAGE_SIZE; 4534 resid -= PAGE_SIZE; 4535 } 4536 #ifdef VERBOSE_INIT_ARM 4537 printf("\n"); 4538 #endif 4539 return (size); 4540 } 4541 4542 /********************** Static device map routines ***************************/ 4543 4544 static const struct pmap_devmap *pmap_devmap_table; 4545 4546 /* 4547 * Register the devmap table. This is provided in case early console 4548 * initialization needs to register mappings created by bootstrap code 4549 * before pmap_devmap_bootstrap() is called. 4550 */ 4551 void 4552 pmap_devmap_register(const struct pmap_devmap *table) 4553 { 4554 4555 pmap_devmap_table = table; 4556 } 4557 4558 /* 4559 * Map all of the static regions in the devmap table, and remember 4560 * the devmap table so other parts of the kernel can look up entries 4561 * later. 4562 */ 4563 void 4564 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 4565 { 4566 int i; 4567 4568 pmap_devmap_table = table; 4569 4570 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4571 #ifdef VERBOSE_INIT_ARM 4572 printf("devmap: %08lx -> %08lx @ %08lx\n", 4573 pmap_devmap_table[i].pd_pa, 4574 pmap_devmap_table[i].pd_pa + 4575 pmap_devmap_table[i].pd_size - 1, 4576 pmap_devmap_table[i].pd_va); 4577 #endif 4578 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4579 pmap_devmap_table[i].pd_pa, 4580 pmap_devmap_table[i].pd_size, 4581 pmap_devmap_table[i].pd_prot, 4582 pmap_devmap_table[i].pd_cache); 4583 } 4584 } 4585 4586 const struct pmap_devmap * 4587 pmap_devmap_find_pa(paddr_t pa, psize_t size) 4588 { 4589 uint64_t endpa; 4590 int i; 4591 4592 if (pmap_devmap_table == NULL) 4593 return (NULL); 4594 4595 endpa = (uint64_t)pa + (uint64_t)(size - 1); 4596 4597 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4598 if (pa >= pmap_devmap_table[i].pd_pa && 4599 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 4600 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 4601 return (&pmap_devmap_table[i]); 4602 } 4603 4604 return (NULL); 4605 } 4606 4607 const struct pmap_devmap * 4608 pmap_devmap_find_va(vaddr_t va, vsize_t size) 4609 { 4610 int i; 4611 4612 if (pmap_devmap_table == NULL) 4613 return (NULL); 4614 4615 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4616 if (va >= pmap_devmap_table[i].pd_va && 4617 va + size - 1 <= pmap_devmap_table[i].pd_va + 4618 pmap_devmap_table[i].pd_size - 1) 4619 return (&pmap_devmap_table[i]); 4620 } 4621 4622 return (NULL); 4623 } 4624 4625 /********************** PTE initialization routines **************************/ 4626 4627 /* 4628 * These routines are called when the CPU type is identified to set up 4629 * the PTE prototypes, cache modes, etc. 4630 * 4631 * The variables are always here, just in case LKMs need to reference 4632 * them (though, they shouldn't). 4633 */ 4634 4635 pt_entry_t pte_l1_s_cache_mode; 4636 pt_entry_t pte_l1_s_cache_mode_pt; 4637 pt_entry_t pte_l1_s_cache_mask; 4638 4639 pt_entry_t pte_l2_l_cache_mode; 4640 pt_entry_t pte_l2_l_cache_mode_pt; 4641 pt_entry_t pte_l2_l_cache_mask; 4642 4643 pt_entry_t pte_l2_s_cache_mode; 4644 pt_entry_t pte_l2_s_cache_mode_pt; 4645 pt_entry_t pte_l2_s_cache_mask; 4646 4647 pt_entry_t pte_l2_s_prot_u; 4648 pt_entry_t pte_l2_s_prot_w; 4649 pt_entry_t pte_l2_s_prot_mask; 4650 4651 pt_entry_t pte_l1_s_proto; 4652 pt_entry_t pte_l1_c_proto; 4653 pt_entry_t pte_l2_s_proto; 4654 4655 void (*pmap_copy_page_func)(paddr_t, paddr_t); 4656 void (*pmap_zero_page_func)(paddr_t); 4657 4658 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 4659 void 4660 pmap_pte_init_generic(void) 4661 { 4662 4663 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 4664 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 4665 4666 pte_l2_l_cache_mode = L2_B|L2_C; 4667 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 4668 4669 pte_l2_s_cache_mode = L2_B|L2_C; 4670 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 4671 4672 /* 4673 * If we have a write-through cache, set B and C. If 4674 * we have a write-back cache, then we assume setting 4675 * only C will make those pages write-through. 4676 */ 4677 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 4678 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 4679 pte_l2_l_cache_mode_pt = L2_B|L2_C; 4680 pte_l2_s_cache_mode_pt = L2_B|L2_C; 4681 } else { 4682 pte_l1_s_cache_mode_pt = L1_S_C; 4683 pte_l2_l_cache_mode_pt = L2_C; 4684 pte_l2_s_cache_mode_pt = L2_C; 4685 } 4686 4687 pte_l2_s_prot_u = L2_S_PROT_U_generic; 4688 pte_l2_s_prot_w = L2_S_PROT_W_generic; 4689 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 4690 4691 pte_l1_s_proto = L1_S_PROTO_generic; 4692 pte_l1_c_proto = L1_C_PROTO_generic; 4693 pte_l2_s_proto = L2_S_PROTO_generic; 4694 4695 pmap_copy_page_func = pmap_copy_page_generic; 4696 pmap_zero_page_func = pmap_zero_page_generic; 4697 } 4698 4699 #if defined(CPU_ARM8) 4700 void 4701 pmap_pte_init_arm8(void) 4702 { 4703 4704 /* 4705 * ARM8 is compatible with generic, but we need to use 4706 * the page tables uncached. 4707 */ 4708 pmap_pte_init_generic(); 4709 4710 pte_l1_s_cache_mode_pt = 0; 4711 pte_l2_l_cache_mode_pt = 0; 4712 pte_l2_s_cache_mode_pt = 0; 4713 } 4714 #endif /* CPU_ARM8 */ 4715 4716 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 4717 void 4718 pmap_pte_init_arm9(void) 4719 { 4720 4721 /* 4722 * ARM9 is compatible with generic, but we want to use 4723 * write-through caching for now. 4724 */ 4725 pmap_pte_init_generic(); 4726 4727 pte_l1_s_cache_mode = L1_S_C; 4728 pte_l2_l_cache_mode = L2_C; 4729 pte_l2_s_cache_mode = L2_C; 4730 4731 pte_l1_s_cache_mode_pt = L1_S_C; 4732 pte_l2_l_cache_mode_pt = L2_C; 4733 pte_l2_s_cache_mode_pt = L2_C; 4734 } 4735 #endif /* CPU_ARM9 */ 4736 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4737 4738 #if defined(CPU_ARM10) 4739 void 4740 pmap_pte_init_arm10(void) 4741 { 4742 4743 /* 4744 * ARM10 is compatible with generic, but we want to use 4745 * write-through caching for now. 4746 */ 4747 pmap_pte_init_generic(); 4748 4749 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 4750 pte_l2_l_cache_mode = L2_B | L2_C; 4751 pte_l2_s_cache_mode = L2_B | L2_C; 4752 4753 pte_l1_s_cache_mode_pt = L1_S_C; 4754 pte_l2_l_cache_mode_pt = L2_C; 4755 pte_l2_s_cache_mode_pt = L2_C; 4756 4757 } 4758 #endif /* CPU_ARM10 */ 4759 4760 #if ARM_MMU_SA1 == 1 4761 void 4762 pmap_pte_init_sa1(void) 4763 { 4764 4765 /* 4766 * The StrongARM SA-1 cache does not have a write-through 4767 * mode. So, do the generic initialization, then reset 4768 * the page table cache mode to B=1,C=1, and note that 4769 * the PTEs need to be sync'd. 4770 */ 4771 pmap_pte_init_generic(); 4772 4773 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 4774 pte_l2_l_cache_mode_pt = L2_B|L2_C; 4775 pte_l2_s_cache_mode_pt = L2_B|L2_C; 4776 4777 pmap_needs_pte_sync = 1; 4778 } 4779 #endif /* ARM_MMU_SA1 == 1*/ 4780 4781 #if ARM_MMU_XSCALE == 1 4782 #if (ARM_NMMUS > 1) 4783 static u_int xscale_use_minidata; 4784 #endif 4785 4786 void 4787 pmap_pte_init_xscale(void) 4788 { 4789 uint32_t auxctl; 4790 int write_through = 0; 4791 4792 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 4793 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 4794 4795 pte_l2_l_cache_mode = L2_B|L2_C; 4796 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 4797 4798 pte_l2_s_cache_mode = L2_B|L2_C; 4799 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 4800 4801 pte_l1_s_cache_mode_pt = L1_S_C; 4802 pte_l2_l_cache_mode_pt = L2_C; 4803 pte_l2_s_cache_mode_pt = L2_C; 4804 4805 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 4806 /* 4807 * The XScale core has an enhanced mode where writes that 4808 * miss the cache cause a cache line to be allocated. This 4809 * is significantly faster than the traditional, write-through 4810 * behavior of this case. 4811 */ 4812 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 4813 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 4814 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 4815 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 4816 4817 #ifdef XSCALE_CACHE_WRITE_THROUGH 4818 /* 4819 * Some versions of the XScale core have various bugs in 4820 * their cache units, the work-around for which is to run 4821 * the cache in write-through mode. Unfortunately, this 4822 * has a major (negative) impact on performance. So, we 4823 * go ahead and run fast-and-loose, in the hopes that we 4824 * don't line up the planets in a way that will trip the 4825 * bugs. 4826 * 4827 * However, we give you the option to be slow-but-correct. 4828 */ 4829 write_through = 1; 4830 #elif defined(XSCALE_CACHE_WRITE_BACK) 4831 /* force write back cache mode */ 4832 write_through = 0; 4833 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 4834 /* 4835 * Intel PXA2[15]0 processors are known to have a bug in 4836 * write-back cache on revision 4 and earlier (stepping 4837 * A[01] and B[012]). Fixed for C0 and later. 4838 */ 4839 { 4840 uint32_t id, type; 4841 4842 id = cpufunc_id(); 4843 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 4844 4845 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 4846 if ((id & CPU_ID_REVISION_MASK) < 5) { 4847 /* write through for stepping A0-1 and B0-2 */ 4848 write_through = 1; 4849 } 4850 } 4851 } 4852 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 4853 4854 if (write_through) { 4855 pte_l1_s_cache_mode = L1_S_C; 4856 pte_l2_l_cache_mode = L2_C; 4857 pte_l2_s_cache_mode = L2_C; 4858 } 4859 4860 #if (ARM_NMMUS > 1) 4861 xscale_use_minidata = 1; 4862 #endif 4863 4864 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 4865 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 4866 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 4867 4868 pte_l1_s_proto = L1_S_PROTO_xscale; 4869 pte_l1_c_proto = L1_C_PROTO_xscale; 4870 pte_l2_s_proto = L2_S_PROTO_xscale; 4871 4872 pmap_copy_page_func = pmap_copy_page_xscale; 4873 pmap_zero_page_func = pmap_zero_page_xscale; 4874 4875 /* 4876 * Disable ECC protection of page table access, for now. 4877 */ 4878 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 4879 auxctl &= ~XSCALE_AUXCTL_P; 4880 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 4881 } 4882 4883 /* 4884 * xscale_setup_minidata: 4885 * 4886 * Set up the mini-data cache clean area. We require the 4887 * caller to allocate the right amount of physically and 4888 * virtually contiguous space. 4889 */ 4890 void 4891 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 4892 { 4893 extern vaddr_t xscale_minidata_clean_addr; 4894 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 4895 pd_entry_t *pde = (pd_entry_t *) l1pt; 4896 pt_entry_t *pte; 4897 vsize_t size; 4898 uint32_t auxctl; 4899 4900 xscale_minidata_clean_addr = va; 4901 4902 /* Round it to page size. */ 4903 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 4904 4905 for (; size != 0; 4906 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 4907 #ifndef ARM32_NEW_VM_LAYOUT 4908 pte = (pt_entry_t *) 4909 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4910 #else 4911 pte = (pt_entry_t *) kernel_pt_lookup( 4912 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4913 #endif 4914 if (pte == NULL) 4915 panic("xscale_setup_minidata: can't find L2 table for " 4916 "VA 0x%08lx", va); 4917 #ifndef ARM32_NEW_VM_LAYOUT 4918 pte[(va >> PGSHIFT) & 0x3ff] = 4919 #else 4920 pte[l2pte_index(va)] = 4921 #endif 4922 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4923 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4924 } 4925 4926 /* 4927 * Configure the mini-data cache for write-back with 4928 * read/write-allocate. 4929 * 4930 * NOTE: In order to reconfigure the mini-data cache, we must 4931 * make sure it contains no valid data! In order to do that, 4932 * we must issue a global data cache invalidate command! 4933 * 4934 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 4935 * THIS IS VERY IMPORTANT! 4936 */ 4937 4938 /* Invalidate data and mini-data. */ 4939 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 4940 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 4941 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 4942 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 4943 } 4944 4945 /* 4946 * Change the PTEs for the specified kernel mappings such that they 4947 * will use the mini data cache instead of the main data cache. 4948 */ 4949 void 4950 pmap_uarea(vaddr_t va) 4951 { 4952 struct l2_bucket *l2b; 4953 pt_entry_t *ptep, *sptep, pte; 4954 vaddr_t next_bucket, eva; 4955 4956 #if (ARM_NMMUS > 1) 4957 if (xscale_use_minidata == 0) 4958 return; 4959 #endif 4960 4961 eva = va + USPACE; 4962 4963 while (va < eva) { 4964 next_bucket = L2_NEXT_BUCKET(va); 4965 if (next_bucket > eva) 4966 next_bucket = eva; 4967 4968 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4969 KDASSERT(l2b != NULL); 4970 4971 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4972 4973 while (va < next_bucket) { 4974 pte = *ptep; 4975 if (!l2pte_minidata(pte)) { 4976 cpu_dcache_wbinv_range(va, PAGE_SIZE); 4977 cpu_tlb_flushD_SE(va); 4978 *ptep = pte & ~L2_B; 4979 } 4980 ptep++; 4981 va += PAGE_SIZE; 4982 } 4983 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4984 } 4985 cpu_cpwait(); 4986 } 4987 #endif /* ARM_MMU_XSCALE == 1 */ 4988 4989 /* 4990 * return the PA of the current L1 table, for use when handling a crash dump 4991 */ 4992 uint32_t pmap_kernel_L1_addr() 4993 { 4994 return pmap_kernel()->pm_l1->l1_physaddr; 4995 } 4996 4997 #if defined(DDB) 4998 /* 4999 * A couple of ddb-callable functions for dumping pmaps 5000 */ 5001 void pmap_dump_all(void); 5002 void pmap_dump(pmap_t); 5003 5004 void 5005 pmap_dump_all(void) 5006 { 5007 pmap_t pm; 5008 5009 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 5010 if (pm == pmap_kernel()) 5011 continue; 5012 pmap_dump(pm); 5013 printf("\n"); 5014 } 5015 } 5016 5017 static pt_entry_t ncptes[64]; 5018 static void pmap_dump_ncpg(pmap_t); 5019 5020 void 5021 pmap_dump(pmap_t pm) 5022 { 5023 struct l2_dtable *l2; 5024 struct l2_bucket *l2b; 5025 pt_entry_t *ptep, pte; 5026 vaddr_t l2_va, l2b_va, va; 5027 int i, j, k, occ, rows = 0; 5028 5029 if (pm == pmap_kernel()) 5030 printf("pmap_kernel (%p): ", pm); 5031 else 5032 printf("user pmap (%p): ", pm); 5033 5034 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 5035 5036 l2_va = 0; 5037 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 5038 l2 = pm->pm_l2[i]; 5039 5040 if (l2 == NULL || l2->l2_occupancy == 0) 5041 continue; 5042 5043 l2b_va = l2_va; 5044 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 5045 l2b = &l2->l2_bucket[j]; 5046 5047 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 5048 continue; 5049 5050 ptep = l2b->l2b_kva; 5051 5052 for (k = 0; k < 256 && ptep[k] == 0; k++) 5053 ; 5054 5055 k &= ~63; 5056 occ = l2b->l2b_occupancy; 5057 va = l2b_va + (k * 4096); 5058 for (; k < 256; k++, va += 0x1000) { 5059 char ch = ' '; 5060 if ((k % 64) == 0) { 5061 if ((rows % 8) == 0) { 5062 printf( 5063 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 5064 } 5065 printf("%08lx: ", va); 5066 } 5067 5068 ncptes[k & 63] = 0; 5069 pte = ptep[k]; 5070 if (pte == 0) { 5071 ch = '.'; 5072 } else { 5073 occ--; 5074 switch (pte & 0x0c) { 5075 case 0x00: 5076 ch = 'D'; /* No cache No buff */ 5077 break; 5078 case 0x04: 5079 ch = 'B'; /* No cache buff */ 5080 break; 5081 case 0x08: 5082 if (pte & 0x40) 5083 ch = 'm'; 5084 else 5085 ch = 'C'; /* Cache No buff */ 5086 break; 5087 case 0x0c: 5088 ch = 'F'; /* Cache Buff */ 5089 break; 5090 } 5091 5092 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 5093 ch += 0x20; 5094 5095 if ((pte & 0xc) == 0) 5096 ncptes[k & 63] = pte; 5097 } 5098 5099 if ((k % 64) == 63) { 5100 rows++; 5101 printf("%c\n", ch); 5102 pmap_dump_ncpg(pm); 5103 if (occ == 0) 5104 break; 5105 } else 5106 printf("%c", ch); 5107 } 5108 } 5109 } 5110 } 5111 5112 static void 5113 pmap_dump_ncpg(pmap_t pm) 5114 { 5115 struct vm_page *pg; 5116 struct pv_entry *pv; 5117 int i; 5118 5119 for (i = 0; i < 63; i++) { 5120 if (ncptes[i] == 0) 5121 continue; 5122 5123 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 5124 if (pg == NULL) 5125 continue; 5126 5127 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 5128 VM_PAGE_TO_PHYS(pg), 5129 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 5130 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 5131 5132 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 5133 printf(" %c va 0x%08lx, flags 0x%x\n", 5134 (pm == pv->pv_pmap) ? '*' : ' ', 5135 pv->pv_va, pv->pv_flags); 5136 } 5137 } 5138 } 5139 #endif 5140
Indexes created Mon Sep 29 15:09:53 GMT 2025