pmap.c revision 1.173
1 /* $NetBSD: pmap.c,v 1.173 2008/04/20 15:42:19 scw Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 3. All advertising materials mentioning features or use of this software 82 * must display the following acknowledgement: 83 * This product includes software developed by the NetBSD 84 * Foundation, Inc. and its contributors. 85 * 4. Neither the name of The NetBSD Foundation nor the names of its 86 * contributors may be used to endorse or promote products derived 87 * from this software without specific prior written permission. 88 * 89 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 90 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 91 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 92 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 93 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 94 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 95 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 96 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 97 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 98 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 99 * POSSIBILITY OF SUCH DAMAGE. 100 */ 101 102 /* 103 * Copyright (c) 1994-1998 Mark Brinicombe. 104 * Copyright (c) 1994 Brini. 105 * All rights reserved. 106 * 107 * This code is derived from software written for Brini by Mark Brinicombe 108 * 109 * Redistribution and use in source and binary forms, with or without 110 * modification, are permitted provided that the following conditions 111 * are met: 112 * 1. Redistributions of source code must retain the above copyright 113 * notice, this list of conditions and the following disclaimer. 114 * 2. Redistributions in binary form must reproduce the above copyright 115 * notice, this list of conditions and the following disclaimer in the 116 * documentation and/or other materials provided with the distribution. 117 * 3. All advertising materials mentioning features or use of this software 118 * must display the following acknowledgement: 119 * This product includes software developed by Mark Brinicombe. 120 * 4. The name of the author may not be used to endorse or promote products 121 * derived from this software without specific prior written permission. 122 * 123 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 124 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 125 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 126 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 127 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 128 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 129 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 130 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 131 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 132 * 133 * RiscBSD kernel project 134 * 135 * pmap.c 136 * 137 * Machine dependant vm stuff 138 * 139 * Created : 20/09/94 140 */ 141 142 /* 143 * Performance improvements, UVM changes, overhauls and part-rewrites 144 * were contributed by Neil A. Carson <neil (at) causality.com>. 145 */ 146 147 /* 148 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 149 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 150 * Systems, Inc. 151 * 152 * There are still a few things outstanding at this time: 153 * 154 * - There are some unresolved issues for MP systems: 155 * 156 * o The L1 metadata needs a lock, or more specifically, some places 157 * need to acquire an exclusive lock when modifying L1 translation 158 * table entries. 159 * 160 * o When one cpu modifies an L1 entry, and that L1 table is also 161 * being used by another cpu, then the latter will need to be told 162 * that a tlb invalidation may be necessary. (But only if the old 163 * domain number in the L1 entry being over-written is currently 164 * the active domain on that cpu). I guess there are lots more tlb 165 * shootdown issues too... 166 * 167 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 168 * MP systems will lose big-time because of the MMU domain hack. 169 * The only way this can be solved (apart from moving the vector 170 * page to 0xffff0000) is to reserve the first 1MB of user address 171 * space for kernel use only. This would require re-linking all 172 * applications so that the text section starts above this 1MB 173 * boundary. 174 * 175 * o Tracking which VM space is resident in the cache/tlb has not yet 176 * been implemented for MP systems. 177 * 178 * o Finally, there is a pathological condition where two cpus running 179 * two separate processes (not lwps) which happen to share an L1 180 * can get into a fight over one or more L1 entries. This will result 181 * in a significant slow-down if both processes are in tight loops. 182 */ 183 184 /* 185 * Special compilation symbols 186 * PMAP_DEBUG - Build in pmap_debug_level code 187 */ 188 189 /* Include header files */ 190 191 #include "opt_cpuoptions.h" 192 #include "opt_pmap_debug.h" 193 #include "opt_ddb.h" 194 #include "opt_lockdebug.h" 195 #include "opt_multiprocessor.h" 196 197 #include <sys/param.h> 198 #include <sys/types.h> 199 #include <sys/kernel.h> 200 #include <sys/systm.h> 201 #include <sys/proc.h> 202 #include <sys/malloc.h> 203 #include <sys/user.h> 204 #include <sys/pool.h> 205 #include <sys/cdefs.h> 206 #include <sys/cpu.h> 207 208 #include <uvm/uvm.h> 209 210 #include <machine/bus.h> 211 #include <machine/pmap.h> 212 #include <machine/pcb.h> 213 #include <machine/param.h> 214 #include <arm/arm32/katelib.h> 215 216 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.173 2008/04/20 15:42:19 scw Exp $"); 217 218 #ifdef PMAP_DEBUG 219 220 /* XXX need to get rid of all refs to this */ 221 int pmap_debug_level = 0; 222 223 /* 224 * for switching to potentially finer grained debugging 225 */ 226 #define PDB_FOLLOW 0x0001 227 #define PDB_INIT 0x0002 228 #define PDB_ENTER 0x0004 229 #define PDB_REMOVE 0x0008 230 #define PDB_CREATE 0x0010 231 #define PDB_PTPAGE 0x0020 232 #define PDB_GROWKERN 0x0040 233 #define PDB_BITS 0x0080 234 #define PDB_COLLECT 0x0100 235 #define PDB_PROTECT 0x0200 236 #define PDB_MAP_L1 0x0400 237 #define PDB_BOOTSTRAP 0x1000 238 #define PDB_PARANOIA 0x2000 239 #define PDB_WIRING 0x4000 240 #define PDB_PVDUMP 0x8000 241 #define PDB_VAC 0x10000 242 #define PDB_KENTER 0x20000 243 #define PDB_KREMOVE 0x40000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 struct pmap kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 /* 308 * pmap copy/zero page, and mem(5) hook point 309 */ 310 static pt_entry_t *csrc_pte, *cdst_pte; 311 static vaddr_t csrcp, cdstp; 312 vaddr_t memhook; 313 extern void *msgbufaddr; 314 315 /* 316 * Flag to indicate if pmap_init() has done its thing 317 */ 318 bool pmap_initialized; 319 320 /* 321 * Misc. locking data structures 322 */ 323 324 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 325 static struct lock pmap_main_lock; 326 327 #define PMAP_MAP_TO_HEAD_LOCK() \ 328 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 329 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 330 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 331 #define PMAP_HEAD_TO_MAP_LOCK() \ 332 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 333 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 334 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 335 #else 336 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 337 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 338 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 339 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 340 #endif 341 342 #define pmap_acquire_pmap_lock(pm) \ 343 do { \ 344 if ((pm) != pmap_kernel()) \ 345 mutex_enter(&(pm)->pm_lock); \ 346 } while (/*CONSTCOND*/0) 347 348 #define pmap_release_pmap_lock(pm) \ 349 do { \ 350 if ((pm) != pmap_kernel()) \ 351 mutex_exit(&(pm)->pm_lock); \ 352 } while (/*CONSTCOND*/0) 353 354 355 /* 356 * Metadata for L1 translation tables. 357 */ 358 struct l1_ttable { 359 /* Entry on the L1 Table list */ 360 SLIST_ENTRY(l1_ttable) l1_link; 361 362 /* Entry on the L1 Least Recently Used list */ 363 TAILQ_ENTRY(l1_ttable) l1_lru; 364 365 /* Track how many domains are allocated from this L1 */ 366 volatile u_int l1_domain_use_count; 367 368 /* 369 * A free-list of domain numbers for this L1. 370 * We avoid using ffs() and a bitmap to track domains since ffs() 371 * is slow on ARM. 372 */ 373 u_int8_t l1_domain_first; 374 u_int8_t l1_domain_free[PMAP_DOMAINS]; 375 376 /* Physical address of this L1 page table */ 377 paddr_t l1_physaddr; 378 379 /* KVA of this L1 page table */ 380 pd_entry_t *l1_kva; 381 }; 382 383 /* 384 * Convert a virtual address into its L1 table index. That is, the 385 * index used to locate the L2 descriptor table pointer in an L1 table. 386 * This is basically used to index l1->l1_kva[]. 387 * 388 * Each L2 descriptor table represents 1MB of VA space. 389 */ 390 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 391 392 /* 393 * L1 Page Tables are tracked using a Least Recently Used list. 394 * - New L1s are allocated from the HEAD. 395 * - Freed L1s are added to the TAIl. 396 * - Recently accessed L1s (where an 'access' is some change to one of 397 * the userland pmaps which owns this L1) are moved to the TAIL. 398 */ 399 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 400 static struct simplelock l1_lru_lock; 401 402 /* 403 * A list of all L1 tables 404 */ 405 static SLIST_HEAD(, l1_ttable) l1_list; 406 407 /* 408 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 409 * 410 * This is normally 16MB worth L2 page descriptors for any given pmap. 411 * Reference counts are maintained for L2 descriptors so they can be 412 * freed when empty. 413 */ 414 struct l2_dtable { 415 /* The number of L2 page descriptors allocated to this l2_dtable */ 416 u_int l2_occupancy; 417 418 /* List of L2 page descriptors */ 419 struct l2_bucket { 420 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 421 paddr_t l2b_phys; /* Physical address of same */ 422 u_short l2b_l1idx; /* This L2 table's L1 index */ 423 u_short l2b_occupancy; /* How many active descriptors */ 424 } l2_bucket[L2_BUCKET_SIZE]; 425 }; 426 427 /* 428 * Given an L1 table index, calculate the corresponding l2_dtable index 429 * and bucket index within the l2_dtable. 430 */ 431 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 432 (L2_SIZE - 1)) 433 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 434 435 /* 436 * Given a virtual address, this macro returns the 437 * virtual address required to drop into the next L2 bucket. 438 */ 439 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 440 441 /* 442 * L2 allocation. 443 */ 444 #define pmap_alloc_l2_dtable() \ 445 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 446 #define pmap_free_l2_dtable(l2) \ 447 pool_cache_put(&pmap_l2dtable_cache, (l2)) 448 #define pmap_alloc_l2_ptp(pap) \ 449 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 450 PR_NOWAIT, (pap))) 451 452 /* 453 * We try to map the page tables write-through, if possible. However, not 454 * all CPUs have a write-through cache mode, so on those we have to sync 455 * the cache when we frob page tables. 456 * 457 * We try to evaluate this at compile time, if possible. However, it's 458 * not always possible to do that, hence this run-time var. 459 */ 460 int pmap_needs_pte_sync; 461 462 /* 463 * Real definition of pv_entry. 464 */ 465 struct pv_entry { 466 struct pv_entry *pv_next; /* next pv_entry */ 467 pmap_t pv_pmap; /* pmap where mapping lies */ 468 vaddr_t pv_va; /* virtual address for mapping */ 469 u_int pv_flags; /* flags */ 470 }; 471 472 /* 473 * Macro to determine if a mapping might be resident in the 474 * instruction cache and/or TLB 475 */ 476 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 477 478 /* 479 * Macro to determine if a mapping might be resident in the 480 * data cache and/or TLB 481 */ 482 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 483 484 /* 485 * Local prototypes 486 */ 487 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 488 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 489 pt_entry_t **); 490 static bool pmap_is_current(pmap_t); 491 static bool pmap_is_cached(pmap_t); 492 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 493 pmap_t, vaddr_t, u_int); 494 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 495 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 496 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 497 u_int, u_int); 498 499 static void pmap_pinit(pmap_t); 500 static int pmap_pmap_ctor(void *, void *, int); 501 502 static void pmap_alloc_l1(pmap_t); 503 static void pmap_free_l1(pmap_t); 504 static void pmap_use_l1(pmap_t); 505 506 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 507 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 508 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 509 static int pmap_l2ptp_ctor(void *, void *, int); 510 static int pmap_l2dtable_ctor(void *, void *, int); 511 512 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 513 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 514 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 515 516 static void pmap_clearbit(struct vm_page *, u_int); 517 static int pmap_clean_page(struct pv_entry *, bool); 518 static void pmap_page_remove(struct vm_page *); 519 520 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 521 static vaddr_t kernel_pt_lookup(paddr_t); 522 523 524 /* 525 * External function prototypes 526 */ 527 extern void bzero_page(vaddr_t); 528 extern void bcopy_page(vaddr_t, vaddr_t); 529 530 /* 531 * Misc variables 532 */ 533 vaddr_t virtual_avail; 534 vaddr_t virtual_end; 535 vaddr_t pmap_curmaxkvaddr; 536 537 vaddr_t avail_start; 538 vaddr_t avail_end; 539 540 extern pv_addr_t systempage; 541 542 /* Function to set the debug level of the pmap code */ 543 544 #ifdef PMAP_DEBUG 545 void 546 pmap_debug(int level) 547 { 548 pmap_debug_level = level; 549 printf("pmap_debug: level=%d\n", pmap_debug_level); 550 } 551 #endif /* PMAP_DEBUG */ 552 553 /* 554 * A bunch of routines to conditionally flush the caches/TLB depending 555 * on whether the specified pmap actually needs to be flushed at any 556 * given time. 557 */ 558 static inline void 559 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 560 { 561 562 if (pm->pm_cstate.cs_tlb_id) 563 cpu_tlb_flushID_SE(va); 564 } 565 566 static inline void 567 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 568 { 569 570 if (pm->pm_cstate.cs_tlb_d) 571 cpu_tlb_flushD_SE(va); 572 } 573 574 static inline void 575 pmap_tlb_flushID(pmap_t pm) 576 { 577 578 if (pm->pm_cstate.cs_tlb_id) { 579 cpu_tlb_flushID(); 580 pm->pm_cstate.cs_tlb = 0; 581 } 582 } 583 584 static inline void 585 pmap_tlb_flushD(pmap_t pm) 586 { 587 588 if (pm->pm_cstate.cs_tlb_d) { 589 cpu_tlb_flushD(); 590 pm->pm_cstate.cs_tlb_d = 0; 591 } 592 } 593 594 static inline void 595 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 596 { 597 598 if (pm->pm_cstate.cs_cache_id) 599 cpu_idcache_wbinv_range(va, len); 600 } 601 602 static inline void 603 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 604 bool do_inv, bool rd_only) 605 { 606 607 if (pm->pm_cstate.cs_cache_d) { 608 if (do_inv) { 609 if (rd_only) 610 cpu_dcache_inv_range(va, len); 611 else 612 cpu_dcache_wbinv_range(va, len); 613 } else 614 if (!rd_only) 615 cpu_dcache_wb_range(va, len); 616 } 617 } 618 619 static inline void 620 pmap_idcache_wbinv_all(pmap_t pm) 621 { 622 623 if (pm->pm_cstate.cs_cache_id) { 624 cpu_idcache_wbinv_all(); 625 pm->pm_cstate.cs_cache = 0; 626 } 627 } 628 629 static inline void 630 pmap_dcache_wbinv_all(pmap_t pm) 631 { 632 633 if (pm->pm_cstate.cs_cache_d) { 634 cpu_dcache_wbinv_all(); 635 pm->pm_cstate.cs_cache_d = 0; 636 } 637 } 638 639 static inline bool 640 pmap_is_current(pmap_t pm) 641 { 642 643 if (pm == pmap_kernel() || 644 (curproc && curproc->p_vmspace->vm_map.pmap == pm)) 645 return (true); 646 647 return (false); 648 } 649 650 static inline bool 651 pmap_is_cached(pmap_t pm) 652 { 653 654 if (pm == pmap_kernel() || pmap_recent_user == NULL || 655 pmap_recent_user == pm) 656 return (true); 657 658 return (false); 659 } 660 661 /* 662 * PTE_SYNC_CURRENT: 663 * 664 * Make sure the pte is written out to RAM. 665 * We need to do this for one of two cases: 666 * - We're dealing with the kernel pmap 667 * - There is no pmap active in the cache/tlb. 668 * - The specified pmap is 'active' in the cache/tlb. 669 */ 670 #ifdef PMAP_INCLUDE_PTE_SYNC 671 #define PTE_SYNC_CURRENT(pm, ptep) \ 672 do { \ 673 if (PMAP_NEEDS_PTE_SYNC && \ 674 pmap_is_cached(pm)) \ 675 PTE_SYNC(ptep); \ 676 } while (/*CONSTCOND*/0) 677 #else 678 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 679 #endif 680 681 /* 682 * main pv_entry manipulation functions: 683 * pmap_enter_pv: enter a mapping onto a vm_page list 684 * pmap_remove_pv: remove a mappiing from a vm_page list 685 * 686 * NOTE: pmap_enter_pv expects to lock the pvh itself 687 * pmap_remove_pv expects te caller to lock the pvh before calling 688 */ 689 690 /* 691 * pmap_enter_pv: enter a mapping onto a vm_page lst 692 * 693 * => caller should hold the proper lock on pmap_main_lock 694 * => caller should have pmap locked 695 * => we will gain the lock on the vm_page and allocate the new pv_entry 696 * => caller should adjust ptp's wire_count before calling 697 * => caller should not adjust pmap's wire_count 698 */ 699 static void 700 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 701 vaddr_t va, u_int flags) 702 { 703 704 NPDEBUG(PDB_PVDUMP, 705 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 706 707 pve->pv_pmap = pm; 708 pve->pv_va = va; 709 pve->pv_flags = flags; 710 711 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 712 pve->pv_next = pg->mdpage.pvh_list; /* add to ... */ 713 pg->mdpage.pvh_list = pve; /* ... locked list */ 714 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 715 if (pm == pmap_kernel()) { 716 if (flags & PVF_WRITE) 717 pg->mdpage.krw_mappings++; 718 else 719 pg->mdpage.kro_mappings++; 720 } else 721 if (flags & PVF_WRITE) 722 pg->mdpage.urw_mappings++; 723 else 724 pg->mdpage.uro_mappings++; 725 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 726 727 if (pve->pv_flags & PVF_WIRED) 728 ++pm->pm_stats.wired_count; 729 } 730 731 /* 732 * 733 * pmap_find_pv: Find a pv entry 734 * 735 * => caller should hold lock on vm_page 736 */ 737 static inline struct pv_entry * 738 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 739 { 740 struct pv_entry *pv; 741 742 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 743 if (pm == pv->pv_pmap && va == pv->pv_va) 744 break; 745 } 746 747 return (pv); 748 } 749 750 /* 751 * pmap_remove_pv: try to remove a mapping from a pv_list 752 * 753 * => caller should hold proper lock on pmap_main_lock 754 * => pmap should be locked 755 * => caller should hold lock on vm_page [so that attrs can be adjusted] 756 * => caller should adjust ptp's wire_count and free PTP if needed 757 * => caller should NOT adjust pmap's wire_count 758 * => we return the removed pve 759 */ 760 static struct pv_entry * 761 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 762 { 763 struct pv_entry *pve, **prevptr; 764 765 NPDEBUG(PDB_PVDUMP, 766 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 767 768 prevptr = &pg->mdpage.pvh_list; /* previous pv_entry pointer */ 769 pve = *prevptr; 770 771 while (pve) { 772 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 773 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 774 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 775 if (pve->pv_flags & PVF_WIRED) { 776 if (skip_wired) 777 return (NULL); 778 --pm->pm_stats.wired_count; 779 } 780 *prevptr = pve->pv_next; /* remove it! */ 781 if (pm == pmap_kernel()) { 782 if (pve->pv_flags & PVF_WRITE) 783 pg->mdpage.krw_mappings--; 784 else 785 pg->mdpage.kro_mappings--; 786 } else 787 if (pve->pv_flags & PVF_WRITE) 788 pg->mdpage.urw_mappings--; 789 else 790 pg->mdpage.uro_mappings--; 791 break; 792 } 793 prevptr = &pve->pv_next; /* previous pointer */ 794 pve = pve->pv_next; /* advance */ 795 } 796 797 return(pve); /* return removed pve */ 798 } 799 800 /* 801 * 802 * pmap_modify_pv: Update pv flags 803 * 804 * => caller should hold lock on vm_page [so that attrs can be adjusted] 805 * => caller should NOT adjust pmap's wire_count 806 * => caller must call pmap_vac_me_harder() if writable status of a page 807 * may have changed. 808 * => we return the old flags 809 * 810 * Modify a physical-virtual mapping in the pv table 811 */ 812 static u_int 813 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 814 u_int clr_mask, u_int set_mask) 815 { 816 struct pv_entry *npv; 817 u_int flags, oflags; 818 819 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 820 return (0); 821 822 NPDEBUG(PDB_PVDUMP, 823 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 824 825 /* 826 * There is at least one VA mapping this page. 827 */ 828 829 if (clr_mask & (PVF_REF | PVF_MOD)) 830 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 831 832 oflags = npv->pv_flags; 833 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 834 835 if ((flags ^ oflags) & PVF_WIRED) { 836 if (flags & PVF_WIRED) 837 ++pm->pm_stats.wired_count; 838 else 839 --pm->pm_stats.wired_count; 840 } 841 842 if ((flags ^ oflags) & PVF_WRITE) { 843 if (pm == pmap_kernel()) { 844 if (flags & PVF_WRITE) { 845 pg->mdpage.krw_mappings++; 846 pg->mdpage.kro_mappings--; 847 } else { 848 pg->mdpage.kro_mappings++; 849 pg->mdpage.krw_mappings--; 850 } 851 } else 852 if (flags & PVF_WRITE) { 853 pg->mdpage.urw_mappings++; 854 pg->mdpage.uro_mappings--; 855 } else { 856 pg->mdpage.uro_mappings++; 857 pg->mdpage.urw_mappings--; 858 } 859 } 860 861 return (oflags); 862 } 863 864 /* 865 * Allocate an L1 translation table for the specified pmap. 866 * This is called at pmap creation time. 867 */ 868 static void 869 pmap_alloc_l1(pmap_t pm) 870 { 871 struct l1_ttable *l1; 872 u_int8_t domain; 873 874 /* 875 * Remove the L1 at the head of the LRU list 876 */ 877 simple_lock(&l1_lru_lock); 878 l1 = TAILQ_FIRST(&l1_lru_list); 879 KDASSERT(l1 != NULL); 880 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 881 882 /* 883 * Pick the first available domain number, and update 884 * the link to the next number. 885 */ 886 domain = l1->l1_domain_first; 887 l1->l1_domain_first = l1->l1_domain_free[domain]; 888 889 /* 890 * If there are still free domain numbers in this L1, 891 * put it back on the TAIL of the LRU list. 892 */ 893 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 894 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 895 896 simple_unlock(&l1_lru_lock); 897 898 /* 899 * Fix up the relevant bits in the pmap structure 900 */ 901 pm->pm_l1 = l1; 902 pm->pm_domain = domain; 903 } 904 905 /* 906 * Free an L1 translation table. 907 * This is called at pmap destruction time. 908 */ 909 static void 910 pmap_free_l1(pmap_t pm) 911 { 912 struct l1_ttable *l1 = pm->pm_l1; 913 914 simple_lock(&l1_lru_lock); 915 916 /* 917 * If this L1 is currently on the LRU list, remove it. 918 */ 919 if (l1->l1_domain_use_count < PMAP_DOMAINS) 920 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 921 922 /* 923 * Free up the domain number which was allocated to the pmap 924 */ 925 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 926 l1->l1_domain_first = pm->pm_domain; 927 l1->l1_domain_use_count--; 928 929 /* 930 * The L1 now must have at least 1 free domain, so add 931 * it back to the LRU list. If the use count is zero, 932 * put it at the head of the list, otherwise it goes 933 * to the tail. 934 */ 935 if (l1->l1_domain_use_count == 0) 936 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 937 else 938 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 939 940 simple_unlock(&l1_lru_lock); 941 } 942 943 static inline void 944 pmap_use_l1(pmap_t pm) 945 { 946 struct l1_ttable *l1; 947 948 /* 949 * Do nothing if we're in interrupt context. 950 * Access to an L1 by the kernel pmap must not affect 951 * the LRU list. 952 */ 953 if (cpu_intr_p() || pm == pmap_kernel()) 954 return; 955 956 l1 = pm->pm_l1; 957 958 /* 959 * If the L1 is not currently on the LRU list, just return 960 */ 961 if (l1->l1_domain_use_count == PMAP_DOMAINS) 962 return; 963 964 simple_lock(&l1_lru_lock); 965 966 /* 967 * Check the use count again, now that we've acquired the lock 968 */ 969 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 970 simple_unlock(&l1_lru_lock); 971 return; 972 } 973 974 /* 975 * Move the L1 to the back of the LRU list 976 */ 977 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 978 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 979 980 simple_unlock(&l1_lru_lock); 981 } 982 983 /* 984 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 985 * 986 * Free an L2 descriptor table. 987 */ 988 static inline void 989 #ifndef PMAP_INCLUDE_PTE_SYNC 990 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 991 #else 992 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 993 #endif 994 { 995 #ifdef PMAP_INCLUDE_PTE_SYNC 996 /* 997 * Note: With a write-back cache, we may need to sync this 998 * L2 table before re-using it. 999 * This is because it may have belonged to a non-current 1000 * pmap, in which case the cache syncs would have been 1001 * skipped when the pages were being unmapped. If the 1002 * L2 table were then to be immediately re-allocated to 1003 * the *current* pmap, it may well contain stale mappings 1004 * which have not yet been cleared by a cache write-back 1005 * and so would still be visible to the mmu. 1006 */ 1007 if (need_sync) 1008 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1009 #endif 1010 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1011 } 1012 1013 /* 1014 * Returns a pointer to the L2 bucket associated with the specified pmap 1015 * and VA, or NULL if no L2 bucket exists for the address. 1016 */ 1017 static inline struct l2_bucket * 1018 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1019 { 1020 struct l2_dtable *l2; 1021 struct l2_bucket *l2b; 1022 u_short l1idx; 1023 1024 l1idx = L1_IDX(va); 1025 1026 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1027 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1028 return (NULL); 1029 1030 return (l2b); 1031 } 1032 1033 /* 1034 * Returns a pointer to the L2 bucket associated with the specified pmap 1035 * and VA. 1036 * 1037 * If no L2 bucket exists, perform the necessary allocations to put an L2 1038 * bucket/page table in place. 1039 * 1040 * Note that if a new L2 bucket/page was allocated, the caller *must* 1041 * increment the bucket occupancy counter appropriately *before* 1042 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1043 * the bucket/page in the meantime. 1044 */ 1045 static struct l2_bucket * 1046 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1047 { 1048 struct l2_dtable *l2; 1049 struct l2_bucket *l2b; 1050 u_short l1idx; 1051 1052 l1idx = L1_IDX(va); 1053 1054 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1055 /* 1056 * No mapping at this address, as there is 1057 * no entry in the L1 table. 1058 * Need to allocate a new l2_dtable. 1059 */ 1060 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1061 return (NULL); 1062 1063 /* 1064 * Link it into the parent pmap 1065 */ 1066 pm->pm_l2[L2_IDX(l1idx)] = l2; 1067 } 1068 1069 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1070 1071 /* 1072 * Fetch pointer to the L2 page table associated with the address. 1073 */ 1074 if (l2b->l2b_kva == NULL) { 1075 pt_entry_t *ptep; 1076 1077 /* 1078 * No L2 page table has been allocated. Chances are, this 1079 * is because we just allocated the l2_dtable, above. 1080 */ 1081 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1082 /* 1083 * Oops, no more L2 page tables available at this 1084 * time. We may need to deallocate the l2_dtable 1085 * if we allocated a new one above. 1086 */ 1087 if (l2->l2_occupancy == 0) { 1088 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1089 pmap_free_l2_dtable(l2); 1090 } 1091 return (NULL); 1092 } 1093 1094 l2->l2_occupancy++; 1095 l2b->l2b_kva = ptep; 1096 l2b->l2b_l1idx = l1idx; 1097 } 1098 1099 return (l2b); 1100 } 1101 1102 /* 1103 * One or more mappings in the specified L2 descriptor table have just been 1104 * invalidated. 1105 * 1106 * Garbage collect the metadata and descriptor table itself if necessary. 1107 * 1108 * The pmap lock must be acquired when this is called (not necessary 1109 * for the kernel pmap). 1110 */ 1111 static void 1112 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1113 { 1114 struct l2_dtable *l2; 1115 pd_entry_t *pl1pd, l1pd; 1116 pt_entry_t *ptep; 1117 u_short l1idx; 1118 1119 KDASSERT(count <= l2b->l2b_occupancy); 1120 1121 /* 1122 * Update the bucket's reference count according to how many 1123 * PTEs the caller has just invalidated. 1124 */ 1125 l2b->l2b_occupancy -= count; 1126 1127 /* 1128 * Note: 1129 * 1130 * Level 2 page tables allocated to the kernel pmap are never freed 1131 * as that would require checking all Level 1 page tables and 1132 * removing any references to the Level 2 page table. See also the 1133 * comment elsewhere about never freeing bootstrap L2 descriptors. 1134 * 1135 * We make do with just invalidating the mapping in the L2 table. 1136 * 1137 * This isn't really a big deal in practice and, in fact, leads 1138 * to a performance win over time as we don't need to continually 1139 * alloc/free. 1140 */ 1141 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1142 return; 1143 1144 /* 1145 * There are no more valid mappings in this level 2 page table. 1146 * Go ahead and NULL-out the pointer in the bucket, then 1147 * free the page table. 1148 */ 1149 l1idx = l2b->l2b_l1idx; 1150 ptep = l2b->l2b_kva; 1151 l2b->l2b_kva = NULL; 1152 1153 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1154 1155 /* 1156 * If the L1 slot matches the pmap's domain 1157 * number, then invalidate it. 1158 */ 1159 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1160 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1161 *pl1pd = 0; 1162 PTE_SYNC(pl1pd); 1163 } 1164 1165 /* 1166 * Release the L2 descriptor table back to the pool cache. 1167 */ 1168 #ifndef PMAP_INCLUDE_PTE_SYNC 1169 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1170 #else 1171 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1172 #endif 1173 1174 /* 1175 * Update the reference count in the associated l2_dtable 1176 */ 1177 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1178 if (--l2->l2_occupancy > 0) 1179 return; 1180 1181 /* 1182 * There are no more valid mappings in any of the Level 1 1183 * slots managed by this l2_dtable. Go ahead and NULL-out 1184 * the pointer in the parent pmap and free the l2_dtable. 1185 */ 1186 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1187 pmap_free_l2_dtable(l2); 1188 } 1189 1190 /* 1191 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1192 * structures. 1193 */ 1194 static int 1195 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1196 { 1197 #ifndef PMAP_INCLUDE_PTE_SYNC 1198 struct l2_bucket *l2b; 1199 pt_entry_t *ptep, pte; 1200 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1201 1202 /* 1203 * The mappings for these page tables were initially made using 1204 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1205 * mode will not be right for page table mappings. To avoid 1206 * polluting the pmap_kenter_pa() code with a special case for 1207 * page tables, we simply fix up the cache-mode here if it's not 1208 * correct. 1209 */ 1210 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1211 KDASSERT(l2b != NULL); 1212 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1213 pte = *ptep; 1214 1215 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1216 /* 1217 * Page tables must have the cache-mode set to Write-Thru. 1218 */ 1219 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1220 PTE_SYNC(ptep); 1221 cpu_tlb_flushD_SE(va); 1222 cpu_cpwait(); 1223 } 1224 #endif 1225 1226 memset(v, 0, L2_TABLE_SIZE_REAL); 1227 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1228 return (0); 1229 } 1230 1231 static int 1232 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1233 { 1234 1235 memset(v, 0, sizeof(struct l2_dtable)); 1236 return (0); 1237 } 1238 1239 static int 1240 pmap_pmap_ctor(void *arg, void *v, int flags) 1241 { 1242 1243 memset(v, 0, sizeof(struct pmap)); 1244 return (0); 1245 } 1246 1247 static void 1248 pmap_pinit(pmap_t pm) 1249 { 1250 struct l2_bucket *l2b; 1251 1252 if (vector_page < KERNEL_BASE) { 1253 /* 1254 * Map the vector page. 1255 */ 1256 pmap_enter(pm, vector_page, systempage.pv_pa, 1257 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1258 pmap_update(pm); 1259 1260 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1261 l2b = pmap_get_l2_bucket(pm, vector_page); 1262 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1263 L1_C_DOM(pm->pm_domain); 1264 } else 1265 pm->pm_pl1vec = NULL; 1266 } 1267 1268 /* 1269 * Since we have a virtually indexed cache, we may need to inhibit caching if 1270 * there is more than one mapping and at least one of them is writable. 1271 * Since we purge the cache on every context switch, we only need to check for 1272 * other mappings within the same pmap, or kernel_pmap. 1273 * This function is also called when a page is unmapped, to possibly reenable 1274 * caching on any remaining mappings. 1275 * 1276 * The code implements the following logic, where: 1277 * 1278 * KW = # of kernel read/write pages 1279 * KR = # of kernel read only pages 1280 * UW = # of user read/write pages 1281 * UR = # of user read only pages 1282 * 1283 * KC = kernel mapping is cacheable 1284 * UC = user mapping is cacheable 1285 * 1286 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1287 * +--------------------------------------------- 1288 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1289 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1290 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1291 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1292 */ 1293 1294 static const int pmap_vac_flags[4][4] = { 1295 {-1, 0, 0, PVF_KNC}, 1296 {0, 0, PVF_NC, PVF_NC}, 1297 {0, PVF_NC, PVF_NC, PVF_NC}, 1298 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1299 }; 1300 1301 static inline int 1302 pmap_get_vac_flags(const struct vm_page *pg) 1303 { 1304 int kidx, uidx; 1305 1306 kidx = 0; 1307 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1308 kidx |= 1; 1309 if (pg->mdpage.krw_mappings) 1310 kidx |= 2; 1311 1312 uidx = 0; 1313 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1314 uidx |= 1; 1315 if (pg->mdpage.urw_mappings) 1316 uidx |= 2; 1317 1318 return (pmap_vac_flags[uidx][kidx]); 1319 } 1320 1321 static inline void 1322 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1323 { 1324 int nattr; 1325 1326 nattr = pmap_get_vac_flags(pg); 1327 1328 if (nattr < 0) { 1329 pg->mdpage.pvh_attrs &= ~PVF_NC; 1330 return; 1331 } 1332 1333 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1334 return; 1335 1336 if (pm == pmap_kernel()) 1337 pmap_vac_me_kpmap(pg, pm, va); 1338 else 1339 pmap_vac_me_user(pg, pm, va); 1340 1341 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1342 } 1343 1344 static void 1345 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1346 { 1347 u_int u_cacheable, u_entries; 1348 struct pv_entry *pv; 1349 pmap_t last_pmap = pm; 1350 1351 /* 1352 * Pass one, see if there are both kernel and user pmaps for 1353 * this page. Calculate whether there are user-writable or 1354 * kernel-writable pages. 1355 */ 1356 u_cacheable = 0; 1357 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1358 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1359 u_cacheable++; 1360 } 1361 1362 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1363 1364 /* 1365 * We know we have just been updating a kernel entry, so if 1366 * all user pages are already cacheable, then there is nothing 1367 * further to do. 1368 */ 1369 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1370 return; 1371 1372 if (u_entries) { 1373 /* 1374 * Scan over the list again, for each entry, if it 1375 * might not be set correctly, call pmap_vac_me_user 1376 * to recalculate the settings. 1377 */ 1378 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1379 /* 1380 * We know kernel mappings will get set 1381 * correctly in other calls. We also know 1382 * that if the pmap is the same as last_pmap 1383 * then we've just handled this entry. 1384 */ 1385 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1386 continue; 1387 1388 /* 1389 * If there are kernel entries and this page 1390 * is writable but non-cacheable, then we can 1391 * skip this entry also. 1392 */ 1393 if (pg->mdpage.k_mappings && 1394 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1395 (PVF_NC | PVF_WRITE)) 1396 continue; 1397 1398 /* 1399 * Similarly if there are no kernel-writable 1400 * entries and the page is already 1401 * read-only/cacheable. 1402 */ 1403 if (pg->mdpage.krw_mappings == 0 && 1404 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1405 continue; 1406 1407 /* 1408 * For some of the remaining cases, we know 1409 * that we must recalculate, but for others we 1410 * can't tell if they are correct or not, so 1411 * we recalculate anyway. 1412 */ 1413 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1414 } 1415 1416 if (pg->mdpage.k_mappings == 0) 1417 return; 1418 } 1419 1420 pmap_vac_me_user(pg, pm, va); 1421 } 1422 1423 static void 1424 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1425 { 1426 pmap_t kpmap = pmap_kernel(); 1427 struct pv_entry *pv, *npv; 1428 struct l2_bucket *l2b; 1429 pt_entry_t *ptep, pte; 1430 u_int entries = 0; 1431 u_int writable = 0; 1432 u_int cacheable_entries = 0; 1433 u_int kern_cacheable = 0; 1434 u_int other_writable = 0; 1435 1436 /* 1437 * Count mappings and writable mappings in this pmap. 1438 * Include kernel mappings as part of our own. 1439 * Keep a pointer to the first one. 1440 */ 1441 for (pv = npv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1442 /* Count mappings in the same pmap */ 1443 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1444 if (entries++ == 0) 1445 npv = pv; 1446 1447 /* Cacheable mappings */ 1448 if ((pv->pv_flags & PVF_NC) == 0) { 1449 cacheable_entries++; 1450 if (kpmap == pv->pv_pmap) 1451 kern_cacheable++; 1452 } 1453 1454 /* Writable mappings */ 1455 if (pv->pv_flags & PVF_WRITE) 1456 ++writable; 1457 } else 1458 if (pv->pv_flags & PVF_WRITE) 1459 other_writable = 1; 1460 } 1461 1462 /* 1463 * Enable or disable caching as necessary. 1464 * Note: the first entry might be part of the kernel pmap, 1465 * so we can't assume this is indicative of the state of the 1466 * other (maybe non-kpmap) entries. 1467 */ 1468 if ((entries > 1 && writable) || 1469 (entries > 0 && pm == kpmap && other_writable)) { 1470 if (cacheable_entries == 0) 1471 return; 1472 1473 for (pv = npv; pv; pv = pv->pv_next) { 1474 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1475 (pv->pv_flags & PVF_NC)) 1476 continue; 1477 1478 pv->pv_flags |= PVF_NC; 1479 1480 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1481 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1482 pte = *ptep & ~L2_S_CACHE_MASK; 1483 1484 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1485 l2pte_valid(pte)) { 1486 if (PV_BEEN_EXECD(pv->pv_flags)) { 1487 pmap_idcache_wbinv_range(pv->pv_pmap, 1488 pv->pv_va, PAGE_SIZE); 1489 pmap_tlb_flushID_SE(pv->pv_pmap, 1490 pv->pv_va); 1491 } else 1492 if (PV_BEEN_REFD(pv->pv_flags)) { 1493 pmap_dcache_wb_range(pv->pv_pmap, 1494 pv->pv_va, PAGE_SIZE, true, 1495 (pv->pv_flags & PVF_WRITE) == 0); 1496 pmap_tlb_flushD_SE(pv->pv_pmap, 1497 pv->pv_va); 1498 } 1499 } 1500 1501 *ptep = pte; 1502 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1503 } 1504 cpu_cpwait(); 1505 } else 1506 if (entries > cacheable_entries) { 1507 /* 1508 * Turn cacheing back on for some pages. If it is a kernel 1509 * page, only do so if there are no other writable pages. 1510 */ 1511 for (pv = npv; pv; pv = pv->pv_next) { 1512 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1513 (kpmap != pv->pv_pmap || other_writable))) 1514 continue; 1515 1516 pv->pv_flags &= ~PVF_NC; 1517 1518 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1519 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1520 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1521 1522 if (l2pte_valid(pte)) { 1523 if (PV_BEEN_EXECD(pv->pv_flags)) { 1524 pmap_tlb_flushID_SE(pv->pv_pmap, 1525 pv->pv_va); 1526 } else 1527 if (PV_BEEN_REFD(pv->pv_flags)) { 1528 pmap_tlb_flushD_SE(pv->pv_pmap, 1529 pv->pv_va); 1530 } 1531 } 1532 1533 *ptep = pte; 1534 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1535 } 1536 } 1537 } 1538 1539 /* 1540 * Modify pte bits for all ptes corresponding to the given physical address. 1541 * We use `maskbits' rather than `clearbits' because we're always passing 1542 * constants and the latter would require an extra inversion at run-time. 1543 */ 1544 static void 1545 pmap_clearbit(struct vm_page *pg, u_int maskbits) 1546 { 1547 struct l2_bucket *l2b; 1548 struct pv_entry *pv; 1549 pt_entry_t *ptep, npte, opte; 1550 pmap_t pm; 1551 vaddr_t va; 1552 u_int oflags; 1553 1554 NPDEBUG(PDB_BITS, 1555 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 1556 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 1557 1558 PMAP_HEAD_TO_MAP_LOCK(); 1559 simple_lock(&pg->mdpage.pvh_slock); 1560 1561 /* 1562 * Clear saved attributes (modify, reference) 1563 */ 1564 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1565 1566 if (pg->mdpage.pvh_list == NULL) { 1567 simple_unlock(&pg->mdpage.pvh_slock); 1568 PMAP_HEAD_TO_MAP_UNLOCK(); 1569 return; 1570 } 1571 1572 /* 1573 * Loop over all current mappings setting/clearing as appropos 1574 */ 1575 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1576 va = pv->pv_va; 1577 pm = pv->pv_pmap; 1578 oflags = pv->pv_flags; 1579 pv->pv_flags &= ~maskbits; 1580 1581 pmap_acquire_pmap_lock(pm); 1582 1583 l2b = pmap_get_l2_bucket(pm, va); 1584 KDASSERT(l2b != NULL); 1585 1586 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1587 npte = opte = *ptep; 1588 1589 NPDEBUG(PDB_BITS, 1590 printf( 1591 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 1592 pv, pv->pv_pmap, pv->pv_va, oflags)); 1593 1594 if (maskbits & (PVF_WRITE|PVF_MOD)) { 1595 if ((pv->pv_flags & PVF_NC)) { 1596 /* 1597 * Entry is not cacheable: 1598 * 1599 * Don't turn caching on again if this is a 1600 * modified emulation. This would be 1601 * inconsitent with the settings created by 1602 * pmap_vac_me_harder(). Otherwise, it's safe 1603 * to re-enable cacheing. 1604 * 1605 * There's no need to call pmap_vac_me_harder() 1606 * here: all pages are losing their write 1607 * permission. 1608 */ 1609 if (maskbits & PVF_WRITE) { 1610 npte |= pte_l2_s_cache_mode; 1611 pv->pv_flags &= ~PVF_NC; 1612 } 1613 } else 1614 if (opte & L2_S_PROT_W) { 1615 /* 1616 * Entry is writable/cacheable: check if pmap 1617 * is current if it is flush it, otherwise it 1618 * won't be in the cache 1619 */ 1620 if (PV_BEEN_EXECD(oflags)) 1621 pmap_idcache_wbinv_range(pm, pv->pv_va, 1622 PAGE_SIZE); 1623 else 1624 if (PV_BEEN_REFD(oflags)) 1625 pmap_dcache_wb_range(pm, pv->pv_va, 1626 PAGE_SIZE, 1627 (maskbits & PVF_REF) ? true : false, 1628 false); 1629 } 1630 1631 /* make the pte read only */ 1632 npte &= ~L2_S_PROT_W; 1633 1634 if (maskbits & PVF_WRITE) { 1635 /* 1636 * Keep alias accounting up to date 1637 */ 1638 if (pv->pv_pmap == pmap_kernel()) { 1639 if (oflags & PVF_WRITE) { 1640 pg->mdpage.krw_mappings--; 1641 pg->mdpage.kro_mappings++; 1642 } 1643 } else 1644 if (oflags & PVF_WRITE) { 1645 pg->mdpage.urw_mappings--; 1646 pg->mdpage.uro_mappings++; 1647 } 1648 } 1649 } 1650 1651 if (maskbits & PVF_REF) { 1652 if ((pv->pv_flags & PVF_NC) == 0 && 1653 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1654 /* 1655 * Check npte here; we may have already 1656 * done the wbinv above, and the validity 1657 * of the PTE is the same for opte and 1658 * npte. 1659 */ 1660 if (npte & L2_S_PROT_W) { 1661 if (PV_BEEN_EXECD(oflags)) 1662 pmap_idcache_wbinv_range(pm, 1663 pv->pv_va, PAGE_SIZE); 1664 else 1665 if (PV_BEEN_REFD(oflags)) 1666 pmap_dcache_wb_range(pm, 1667 pv->pv_va, PAGE_SIZE, 1668 true, false); 1669 } else 1670 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1671 /* XXXJRT need idcache_inv_range */ 1672 if (PV_BEEN_EXECD(oflags)) 1673 pmap_idcache_wbinv_range(pm, 1674 pv->pv_va, PAGE_SIZE); 1675 else 1676 if (PV_BEEN_REFD(oflags)) 1677 pmap_dcache_wb_range(pm, 1678 pv->pv_va, PAGE_SIZE, 1679 true, true); 1680 } 1681 } 1682 1683 /* 1684 * Make the PTE invalid so that we will take a 1685 * page fault the next time the mapping is 1686 * referenced. 1687 */ 1688 npte &= ~L2_TYPE_MASK; 1689 npte |= L2_TYPE_INV; 1690 } 1691 1692 if (npte != opte) { 1693 *ptep = npte; 1694 PTE_SYNC(ptep); 1695 /* Flush the TLB entry if a current pmap. */ 1696 if (PV_BEEN_EXECD(oflags)) 1697 pmap_tlb_flushID_SE(pm, pv->pv_va); 1698 else 1699 if (PV_BEEN_REFD(oflags)) 1700 pmap_tlb_flushD_SE(pm, pv->pv_va); 1701 } 1702 1703 pmap_release_pmap_lock(pm); 1704 1705 NPDEBUG(PDB_BITS, 1706 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 1707 pm, va, opte, npte)); 1708 } 1709 1710 simple_unlock(&pg->mdpage.pvh_slock); 1711 PMAP_HEAD_TO_MAP_UNLOCK(); 1712 } 1713 1714 /* 1715 * pmap_clean_page() 1716 * 1717 * This is a local function used to work out the best strategy to clean 1718 * a single page referenced by its entry in the PV table. It's used by 1719 * pmap_copy_page, pmap_zero page and maybe some others later on. 1720 * 1721 * Its policy is effectively: 1722 * o If there are no mappings, we don't bother doing anything with the cache. 1723 * o If there is one mapping, we clean just that page. 1724 * o If there are multiple mappings, we clean the entire cache. 1725 * 1726 * So that some functions can be further optimised, it returns 0 if it didn't 1727 * clean the entire cache, or 1 if it did. 1728 * 1729 * XXX One bug in this routine is that if the pv_entry has a single page 1730 * mapped at 0x00000000 a whole cache clean will be performed rather than 1731 * just the 1 page. Since this should not occur in everyday use and if it does 1732 * it will just result in not the most efficient clean for the page. 1733 */ 1734 static int 1735 pmap_clean_page(struct pv_entry *pv, bool is_src) 1736 { 1737 pmap_t pm, pm_to_clean = NULL; 1738 struct pv_entry *npv; 1739 u_int cache_needs_cleaning = 0; 1740 u_int flags = 0; 1741 vaddr_t page_to_clean = 0; 1742 1743 if (pv == NULL) { 1744 /* nothing mapped in so nothing to flush */ 1745 return (0); 1746 } 1747 1748 /* 1749 * Since we flush the cache each time we change to a different 1750 * user vmspace, we only need to flush the page if it is in the 1751 * current pmap. 1752 */ 1753 if (curproc) 1754 pm = curproc->p_vmspace->vm_map.pmap; 1755 else 1756 pm = pmap_kernel(); 1757 1758 for (npv = pv; npv; npv = npv->pv_next) { 1759 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 1760 flags |= npv->pv_flags; 1761 /* 1762 * The page is mapped non-cacheable in 1763 * this map. No need to flush the cache. 1764 */ 1765 if (npv->pv_flags & PVF_NC) { 1766 #ifdef DIAGNOSTIC 1767 if (cache_needs_cleaning) 1768 panic("pmap_clean_page: " 1769 "cache inconsistency"); 1770 #endif 1771 break; 1772 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 1773 continue; 1774 if (cache_needs_cleaning) { 1775 page_to_clean = 0; 1776 break; 1777 } else { 1778 page_to_clean = npv->pv_va; 1779 pm_to_clean = npv->pv_pmap; 1780 } 1781 cache_needs_cleaning = 1; 1782 } 1783 } 1784 1785 if (page_to_clean) { 1786 if (PV_BEEN_EXECD(flags)) 1787 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 1788 PAGE_SIZE); 1789 else 1790 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 1791 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 1792 } else if (cache_needs_cleaning) { 1793 if (PV_BEEN_EXECD(flags)) 1794 pmap_idcache_wbinv_all(pm); 1795 else 1796 pmap_dcache_wbinv_all(pm); 1797 return (1); 1798 } 1799 return (0); 1800 } 1801 1802 /* 1803 * Routine: pmap_page_remove 1804 * Function: 1805 * Removes this physical page from 1806 * all physical maps in which it resides. 1807 * Reflects back modify bits to the pager. 1808 */ 1809 static void 1810 pmap_page_remove(struct vm_page *pg) 1811 { 1812 struct l2_bucket *l2b; 1813 struct pv_entry *pv, *npv; 1814 pmap_t pm, curpm; 1815 pt_entry_t *ptep, pte; 1816 bool flush; 1817 u_int flags; 1818 1819 NPDEBUG(PDB_FOLLOW, 1820 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 1821 VM_PAGE_TO_PHYS(pg))); 1822 1823 PMAP_HEAD_TO_MAP_LOCK(); 1824 simple_lock(&pg->mdpage.pvh_slock); 1825 1826 pv = pg->mdpage.pvh_list; 1827 if (pv == NULL) { 1828 simple_unlock(&pg->mdpage.pvh_slock); 1829 PMAP_HEAD_TO_MAP_UNLOCK(); 1830 return; 1831 } 1832 1833 /* 1834 * Clear alias counts 1835 */ 1836 pg->mdpage.k_mappings = 0; 1837 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 1838 1839 flush = false; 1840 flags = 0; 1841 if (curproc) 1842 curpm = curproc->p_vmspace->vm_map.pmap; 1843 else 1844 curpm = pmap_kernel(); 1845 1846 pmap_clean_page(pv, false); 1847 1848 while (pv) { 1849 pm = pv->pv_pmap; 1850 if (flush == false && (pm == curpm || pm == pmap_kernel())) 1851 flush = true; 1852 1853 pmap_acquire_pmap_lock(pm); 1854 1855 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 1856 KDASSERT(l2b != NULL); 1857 1858 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1859 pte = *ptep; 1860 1861 /* 1862 * Update statistics 1863 */ 1864 --pm->pm_stats.resident_count; 1865 1866 /* Wired bit */ 1867 if (pv->pv_flags & PVF_WIRED) 1868 --pm->pm_stats.wired_count; 1869 1870 flags |= pv->pv_flags; 1871 1872 /* 1873 * Invalidate the PTEs. 1874 */ 1875 *ptep = 0; 1876 PTE_SYNC_CURRENT(pm, ptep); 1877 pmap_free_l2_bucket(pm, l2b, 1); 1878 1879 npv = pv->pv_next; 1880 pool_put(&pmap_pv_pool, pv); 1881 pv = npv; 1882 pmap_release_pmap_lock(pm); 1883 } 1884 pg->mdpage.pvh_list = NULL; 1885 simple_unlock(&pg->mdpage.pvh_slock); 1886 PMAP_HEAD_TO_MAP_UNLOCK(); 1887 1888 if (flush) { 1889 /* 1890 * Note: We can't use pmap_tlb_flush{I,}D() here since that 1891 * would need a subsequent call to pmap_update() to ensure 1892 * curpm->pm_cstate.cs_all is reset. Our callers are not 1893 * required to do that (see pmap(9)), so we can't modify 1894 * the current pmap's state. 1895 */ 1896 if (PV_BEEN_EXECD(flags)) 1897 cpu_tlb_flushID(); 1898 else 1899 cpu_tlb_flushD(); 1900 } 1901 cpu_cpwait(); 1902 } 1903 1904 /* 1905 * pmap_t pmap_create(void) 1906 * 1907 * Create a new pmap structure from scratch. 1908 */ 1909 pmap_t 1910 pmap_create(void) 1911 { 1912 pmap_t pm; 1913 1914 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 1915 1916 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 1917 pm->pm_stats.wired_count = 0; 1918 pm->pm_stats.resident_count = 1; 1919 pm->pm_cstate.cs_all = 0; 1920 pmap_alloc_l1(pm); 1921 1922 /* 1923 * Note: The pool cache ensures that the pm_l2[] array is already 1924 * initialised to zero. 1925 */ 1926 1927 pmap_pinit(pm); 1928 1929 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 1930 1931 return (pm); 1932 } 1933 1934 /* 1935 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 1936 * int flags) 1937 * 1938 * Insert the given physical page (p) at 1939 * the specified virtual address (v) in the 1940 * target physical map with the protection requested. 1941 * 1942 * NB: This is the only routine which MAY NOT lazy-evaluate 1943 * or lose information. That is, this routine must actually 1944 * insert this page into the given map NOW. 1945 */ 1946 int 1947 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 1948 { 1949 struct l2_bucket *l2b; 1950 struct vm_page *pg, *opg; 1951 struct pv_entry *pve; 1952 pt_entry_t *ptep, npte, opte; 1953 u_int nflags; 1954 u_int oflags; 1955 1956 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 1957 1958 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 1959 KDASSERT(((va | pa) & PGOFSET) == 0); 1960 1961 /* 1962 * Get a pointer to the page. Later on in this function, we 1963 * test for a managed page by checking pg != NULL. 1964 */ 1965 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 1966 1967 nflags = 0; 1968 if (prot & VM_PROT_WRITE) 1969 nflags |= PVF_WRITE; 1970 if (prot & VM_PROT_EXECUTE) 1971 nflags |= PVF_EXEC; 1972 if (flags & PMAP_WIRED) 1973 nflags |= PVF_WIRED; 1974 1975 PMAP_MAP_TO_HEAD_LOCK(); 1976 pmap_acquire_pmap_lock(pm); 1977 1978 /* 1979 * Fetch the L2 bucket which maps this page, allocating one if 1980 * necessary for user pmaps. 1981 */ 1982 if (pm == pmap_kernel()) 1983 l2b = pmap_get_l2_bucket(pm, va); 1984 else 1985 l2b = pmap_alloc_l2_bucket(pm, va); 1986 if (l2b == NULL) { 1987 if (flags & PMAP_CANFAIL) { 1988 pmap_release_pmap_lock(pm); 1989 PMAP_MAP_TO_HEAD_UNLOCK(); 1990 return (ENOMEM); 1991 } 1992 panic("pmap_enter: failed to allocate L2 bucket"); 1993 } 1994 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1995 opte = *ptep; 1996 npte = pa; 1997 oflags = 0; 1998 1999 if (opte) { 2000 /* 2001 * There is already a mapping at this address. 2002 * If the physical address is different, lookup the 2003 * vm_page. 2004 */ 2005 if (l2pte_pa(opte) != pa) 2006 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2007 else 2008 opg = pg; 2009 } else 2010 opg = NULL; 2011 2012 if (pg) { 2013 /* 2014 * This is to be a managed mapping. 2015 */ 2016 if ((flags & VM_PROT_ALL) || 2017 (pg->mdpage.pvh_attrs & PVF_REF)) { 2018 /* 2019 * - The access type indicates that we don't need 2020 * to do referenced emulation. 2021 * OR 2022 * - The physical page has already been referenced 2023 * so no need to re-do referenced emulation here. 2024 */ 2025 npte |= L2_S_PROTO; 2026 2027 nflags |= PVF_REF; 2028 2029 if ((prot & VM_PROT_WRITE) != 0 && 2030 ((flags & VM_PROT_WRITE) != 0 || 2031 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2032 /* 2033 * This is a writable mapping, and the 2034 * page's mod state indicates it has 2035 * already been modified. Make it 2036 * writable from the outset. 2037 */ 2038 npte |= L2_S_PROT_W; 2039 nflags |= PVF_MOD; 2040 } 2041 } else { 2042 /* 2043 * Need to do page referenced emulation. 2044 */ 2045 npte |= L2_TYPE_INV; 2046 } 2047 2048 npte |= pte_l2_s_cache_mode; 2049 2050 if (pg == opg) { 2051 /* 2052 * We're changing the attrs of an existing mapping. 2053 */ 2054 simple_lock(&pg->mdpage.pvh_slock); 2055 oflags = pmap_modify_pv(pg, pm, va, 2056 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2057 PVF_MOD | PVF_REF, nflags); 2058 simple_unlock(&pg->mdpage.pvh_slock); 2059 2060 /* 2061 * We may need to flush the cache if we're 2062 * doing rw-ro... 2063 */ 2064 if (pm->pm_cstate.cs_cache_d && 2065 (oflags & PVF_NC) == 0 && 2066 (opte & L2_S_PROT_W) != 0 && 2067 (prot & VM_PROT_WRITE) == 0) 2068 cpu_dcache_wb_range(va, PAGE_SIZE); 2069 } else { 2070 /* 2071 * New mapping, or changing the backing page 2072 * of an existing mapping. 2073 */ 2074 if (opg) { 2075 /* 2076 * Replacing an existing mapping with a new one. 2077 * It is part of our managed memory so we 2078 * must remove it from the PV list 2079 */ 2080 simple_lock(&opg->mdpage.pvh_slock); 2081 pve = pmap_remove_pv(opg, pm, va, 0); 2082 pmap_vac_me_harder(opg, pm, 0); 2083 simple_unlock(&opg->mdpage.pvh_slock); 2084 oflags = pve->pv_flags; 2085 2086 /* 2087 * If the old mapping was valid (ref/mod 2088 * emulation creates 'invalid' mappings 2089 * initially) then make sure to frob 2090 * the cache. 2091 */ 2092 if ((oflags & PVF_NC) == 0 && 2093 l2pte_valid(opte)) { 2094 if (PV_BEEN_EXECD(oflags)) { 2095 pmap_idcache_wbinv_range(pm, va, 2096 PAGE_SIZE); 2097 } else 2098 if (PV_BEEN_REFD(oflags)) { 2099 pmap_dcache_wb_range(pm, va, 2100 PAGE_SIZE, true, 2101 (oflags & PVF_WRITE) == 0); 2102 } 2103 } 2104 } else 2105 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2106 if ((flags & PMAP_CANFAIL) == 0) 2107 panic("pmap_enter: no pv entries"); 2108 2109 if (pm != pmap_kernel()) 2110 pmap_free_l2_bucket(pm, l2b, 0); 2111 pmap_release_pmap_lock(pm); 2112 PMAP_MAP_TO_HEAD_UNLOCK(); 2113 NPDEBUG(PDB_ENTER, 2114 printf("pmap_enter: ENOMEM\n")); 2115 return (ENOMEM); 2116 } 2117 2118 pmap_enter_pv(pg, pve, pm, va, nflags); 2119 } 2120 } else { 2121 /* 2122 * We're mapping an unmanaged page. 2123 * These are always readable, and possibly writable, from 2124 * the get go as we don't need to track ref/mod status. 2125 */ 2126 npte |= L2_S_PROTO; 2127 if (prot & VM_PROT_WRITE) 2128 npte |= L2_S_PROT_W; 2129 2130 /* 2131 * Make sure the vector table is mapped cacheable 2132 */ 2133 if (pm != pmap_kernel() && va == vector_page) 2134 npte |= pte_l2_s_cache_mode; 2135 2136 if (opg) { 2137 /* 2138 * Looks like there's an existing 'managed' mapping 2139 * at this address. 2140 */ 2141 simple_lock(&opg->mdpage.pvh_slock); 2142 pve = pmap_remove_pv(opg, pm, va, 0); 2143 pmap_vac_me_harder(opg, pm, 0); 2144 simple_unlock(&opg->mdpage.pvh_slock); 2145 oflags = pve->pv_flags; 2146 2147 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2148 if (PV_BEEN_EXECD(oflags)) 2149 pmap_idcache_wbinv_range(pm, va, 2150 PAGE_SIZE); 2151 else 2152 if (PV_BEEN_REFD(oflags)) 2153 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2154 true, (oflags & PVF_WRITE) == 0); 2155 } 2156 pool_put(&pmap_pv_pool, pve); 2157 } 2158 } 2159 2160 /* 2161 * Make sure userland mappings get the right permissions 2162 */ 2163 if (pm != pmap_kernel() && va != vector_page) 2164 npte |= L2_S_PROT_U; 2165 2166 /* 2167 * Keep the stats up to date 2168 */ 2169 if (opte == 0) { 2170 l2b->l2b_occupancy++; 2171 pm->pm_stats.resident_count++; 2172 } 2173 2174 NPDEBUG(PDB_ENTER, 2175 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2176 2177 /* 2178 * If this is just a wiring change, the two PTEs will be 2179 * identical, so there's no need to update the page table. 2180 */ 2181 if (npte != opte) { 2182 bool is_cached = pmap_is_cached(pm); 2183 2184 *ptep = npte; 2185 if (is_cached) { 2186 /* 2187 * We only need to frob the cache/tlb if this pmap 2188 * is current 2189 */ 2190 PTE_SYNC(ptep); 2191 if (va != vector_page && l2pte_valid(npte)) { 2192 /* 2193 * This mapping is likely to be accessed as 2194 * soon as we return to userland. Fix up the 2195 * L1 entry to avoid taking another 2196 * page/domain fault. 2197 */ 2198 pd_entry_t *pl1pd, l1pd; 2199 2200 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2201 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2202 L1_C_PROTO; 2203 if (*pl1pd != l1pd) { 2204 *pl1pd = l1pd; 2205 PTE_SYNC(pl1pd); 2206 } 2207 } 2208 } 2209 2210 if (PV_BEEN_EXECD(oflags)) 2211 pmap_tlb_flushID_SE(pm, va); 2212 else 2213 if (PV_BEEN_REFD(oflags)) 2214 pmap_tlb_flushD_SE(pm, va); 2215 2216 NPDEBUG(PDB_ENTER, 2217 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2218 is_cached, pm->pm_cstate.cs_all)); 2219 2220 if (pg != NULL) { 2221 simple_lock(&pg->mdpage.pvh_slock); 2222 pmap_vac_me_harder(pg, pm, va); 2223 simple_unlock(&pg->mdpage.pvh_slock); 2224 } 2225 } 2226 2227 pmap_release_pmap_lock(pm); 2228 PMAP_MAP_TO_HEAD_UNLOCK(); 2229 2230 return (0); 2231 } 2232 2233 /* 2234 * pmap_remove() 2235 * 2236 * pmap_remove is responsible for nuking a number of mappings for a range 2237 * of virtual address space in the current pmap. To do this efficiently 2238 * is interesting, because in a number of cases a wide virtual address 2239 * range may be supplied that contains few actual mappings. So, the 2240 * optimisations are: 2241 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 2242 * 2. Build up a list of pages we've hit, up to a maximum, so we can 2243 * maybe do just a partial cache clean. This path of execution is 2244 * complicated by the fact that the cache must be flushed _before_ 2245 * the PTE is nuked, being a VAC :-) 2246 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 2247 * all invalidations until pmap_update(), since pmap_remove_all() has 2248 * already flushed the cache. 2249 * 4. Maybe later fast-case a single page, but I don't think this is 2250 * going to make _that_ much difference overall. 2251 */ 2252 2253 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 2254 2255 void 2256 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 2257 { 2258 struct l2_bucket *l2b; 2259 vaddr_t next_bucket; 2260 pt_entry_t *ptep; 2261 u_int cleanlist_idx, total, cnt; 2262 struct { 2263 vaddr_t va; 2264 pt_entry_t *pte; 2265 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 2266 u_int mappings, is_exec, is_refd; 2267 2268 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 2269 "eva=%08lx\n", pm, sva, eva)); 2270 2271 /* 2272 * we lock in the pmap => pv_head direction 2273 */ 2274 PMAP_MAP_TO_HEAD_LOCK(); 2275 pmap_acquire_pmap_lock(pm); 2276 2277 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 2278 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2279 if (pm->pm_cstate.cs_tlb == 0) 2280 pm->pm_remove_all = true; 2281 } else 2282 cleanlist_idx = 0; 2283 2284 total = 0; 2285 2286 while (sva < eva) { 2287 /* 2288 * Do one L2 bucket's worth at a time. 2289 */ 2290 next_bucket = L2_NEXT_BUCKET(sva); 2291 if (next_bucket > eva) 2292 next_bucket = eva; 2293 2294 l2b = pmap_get_l2_bucket(pm, sva); 2295 if (l2b == NULL) { 2296 sva = next_bucket; 2297 continue; 2298 } 2299 2300 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2301 2302 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 2303 struct vm_page *pg; 2304 pt_entry_t pte; 2305 paddr_t pa; 2306 2307 pte = *ptep; 2308 2309 if (pte == 0) { 2310 /* Nothing here, move along */ 2311 continue; 2312 } 2313 2314 pa = l2pte_pa(pte); 2315 is_exec = 0; 2316 is_refd = 1; 2317 2318 /* 2319 * Update flags. In a number of circumstances, 2320 * we could cluster a lot of these and do a 2321 * number of sequential pages in one go. 2322 */ 2323 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 2324 struct pv_entry *pve; 2325 simple_lock(&pg->mdpage.pvh_slock); 2326 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 2327 pmap_vac_me_harder(pg, pm, 0); 2328 simple_unlock(&pg->mdpage.pvh_slock); 2329 if (pve != NULL) { 2330 if (pm->pm_remove_all == false) { 2331 is_exec = 2332 PV_BEEN_EXECD(pve->pv_flags); 2333 is_refd = 2334 PV_BEEN_REFD(pve->pv_flags); 2335 } 2336 pool_put(&pmap_pv_pool, pve); 2337 } else 2338 if (skip_wired) { 2339 /* The mapping is wired. Skip it */ 2340 continue; 2341 } 2342 } else 2343 if (skip_wired) { 2344 /* Unmanaged pages are always wired. */ 2345 continue; 2346 } 2347 2348 mappings++; 2349 2350 if (!l2pte_valid(pte)) { 2351 /* 2352 * Ref/Mod emulation is still active for this 2353 * mapping, therefore it is has not yet been 2354 * accessed. No need to frob the cache/tlb. 2355 */ 2356 *ptep = 0; 2357 PTE_SYNC_CURRENT(pm, ptep); 2358 continue; 2359 } 2360 2361 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 2362 /* Add to the clean list. */ 2363 cleanlist[cleanlist_idx].pte = ptep; 2364 cleanlist[cleanlist_idx].va = 2365 sva | (is_exec & 1); 2366 cleanlist_idx++; 2367 } else 2368 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 2369 /* Nuke everything if needed. */ 2370 pmap_idcache_wbinv_all(pm); 2371 pmap_tlb_flushID(pm); 2372 2373 /* 2374 * Roll back the previous PTE list, 2375 * and zero out the current PTE. 2376 */ 2377 for (cnt = 0; 2378 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 2379 *cleanlist[cnt].pte = 0; 2380 } 2381 *ptep = 0; 2382 PTE_SYNC(ptep); 2383 cleanlist_idx++; 2384 pm->pm_remove_all = true; 2385 } else { 2386 *ptep = 0; 2387 PTE_SYNC(ptep); 2388 if (pm->pm_remove_all == false) { 2389 if (is_exec) 2390 pmap_tlb_flushID_SE(pm, sva); 2391 else 2392 if (is_refd) 2393 pmap_tlb_flushD_SE(pm, sva); 2394 } 2395 } 2396 } 2397 2398 /* 2399 * Deal with any left overs 2400 */ 2401 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 2402 total += cleanlist_idx; 2403 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 2404 if (pm->pm_cstate.cs_all != 0) { 2405 vaddr_t clva = cleanlist[cnt].va & ~1; 2406 if (cleanlist[cnt].va & 1) { 2407 pmap_idcache_wbinv_range(pm, 2408 clva, PAGE_SIZE); 2409 pmap_tlb_flushID_SE(pm, clva); 2410 } else { 2411 pmap_dcache_wb_range(pm, 2412 clva, PAGE_SIZE, true, 2413 false); 2414 pmap_tlb_flushD_SE(pm, clva); 2415 } 2416 } 2417 *cleanlist[cnt].pte = 0; 2418 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 2419 } 2420 2421 /* 2422 * If it looks like we're removing a whole bunch 2423 * of mappings, it's faster to just write-back 2424 * the whole cache now and defer TLB flushes until 2425 * pmap_update() is called. 2426 */ 2427 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 2428 cleanlist_idx = 0; 2429 else { 2430 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2431 pmap_idcache_wbinv_all(pm); 2432 pm->pm_remove_all = true; 2433 } 2434 } 2435 2436 pmap_free_l2_bucket(pm, l2b, mappings); 2437 pm->pm_stats.resident_count -= mappings; 2438 } 2439 2440 pmap_release_pmap_lock(pm); 2441 PMAP_MAP_TO_HEAD_UNLOCK(); 2442 } 2443 2444 /* 2445 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 2446 * 2447 * We assume there is already sufficient KVM space available 2448 * to do this, as we can't allocate L2 descriptor tables/metadata 2449 * from here. 2450 */ 2451 void 2452 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 2453 { 2454 struct l2_bucket *l2b; 2455 pt_entry_t *ptep, opte; 2456 2457 NPDEBUG(PDB_KENTER, 2458 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 2459 va, pa, prot)); 2460 2461 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2462 KDASSERT(l2b != NULL); 2463 2464 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2465 opte = *ptep; 2466 2467 if (l2pte_valid(opte)) { 2468 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2469 cpu_tlb_flushD_SE(va); 2470 cpu_cpwait(); 2471 } else 2472 if (opte == 0) 2473 l2b->l2b_occupancy++; 2474 2475 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 2476 pte_l2_s_cache_mode; 2477 PTE_SYNC(ptep); 2478 } 2479 2480 void 2481 pmap_kremove(vaddr_t va, vsize_t len) 2482 { 2483 struct l2_bucket *l2b; 2484 pt_entry_t *ptep, *sptep, opte; 2485 vaddr_t next_bucket, eva; 2486 u_int mappings; 2487 2488 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 2489 va, len)); 2490 2491 eva = va + len; 2492 2493 while (va < eva) { 2494 next_bucket = L2_NEXT_BUCKET(va); 2495 if (next_bucket > eva) 2496 next_bucket = eva; 2497 2498 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2499 KDASSERT(l2b != NULL); 2500 2501 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 2502 mappings = 0; 2503 2504 while (va < next_bucket) { 2505 opte = *ptep; 2506 if (l2pte_valid(opte)) { 2507 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2508 cpu_tlb_flushD_SE(va); 2509 } 2510 if (opte) { 2511 *ptep = 0; 2512 mappings++; 2513 } 2514 va += PAGE_SIZE; 2515 ptep++; 2516 } 2517 KDASSERT(mappings <= l2b->l2b_occupancy); 2518 l2b->l2b_occupancy -= mappings; 2519 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 2520 } 2521 cpu_cpwait(); 2522 } 2523 2524 bool 2525 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 2526 { 2527 struct l2_dtable *l2; 2528 pd_entry_t *pl1pd, l1pd; 2529 pt_entry_t *ptep, pte; 2530 paddr_t pa; 2531 u_int l1idx; 2532 2533 pmap_acquire_pmap_lock(pm); 2534 2535 l1idx = L1_IDX(va); 2536 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2537 l1pd = *pl1pd; 2538 2539 if (l1pte_section_p(l1pd)) { 2540 /* 2541 * These should only happen for pmap_kernel() 2542 */ 2543 KDASSERT(pm == pmap_kernel()); 2544 pmap_release_pmap_lock(pm); 2545 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 2546 } else { 2547 /* 2548 * Note that we can't rely on the validity of the L1 2549 * descriptor as an indication that a mapping exists. 2550 * We have to look it up in the L2 dtable. 2551 */ 2552 l2 = pm->pm_l2[L2_IDX(l1idx)]; 2553 2554 if (l2 == NULL || 2555 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 2556 pmap_release_pmap_lock(pm); 2557 return (false); 2558 } 2559 2560 ptep = &ptep[l2pte_index(va)]; 2561 pte = *ptep; 2562 pmap_release_pmap_lock(pm); 2563 2564 if (pte == 0) 2565 return (false); 2566 2567 switch (pte & L2_TYPE_MASK) { 2568 case L2_TYPE_L: 2569 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 2570 break; 2571 2572 default: 2573 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 2574 break; 2575 } 2576 } 2577 2578 if (pap != NULL) 2579 *pap = pa; 2580 2581 return (true); 2582 } 2583 2584 void 2585 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 2586 { 2587 struct l2_bucket *l2b; 2588 pt_entry_t *ptep, pte; 2589 vaddr_t next_bucket; 2590 u_int flags; 2591 int flush; 2592 2593 NPDEBUG(PDB_PROTECT, 2594 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 2595 pm, sva, eva, prot)); 2596 2597 if ((prot & VM_PROT_READ) == 0) { 2598 pmap_remove(pm, sva, eva); 2599 return; 2600 } 2601 2602 if (prot & VM_PROT_WRITE) { 2603 /* 2604 * If this is a read->write transition, just ignore it and let 2605 * uvm_fault() take care of it later. 2606 */ 2607 return; 2608 } 2609 2610 PMAP_MAP_TO_HEAD_LOCK(); 2611 pmap_acquire_pmap_lock(pm); 2612 2613 /* 2614 * OK, at this point, we know we're doing write-protect operation. 2615 * If the pmap is active, write-back the range. 2616 */ 2617 pmap_dcache_wb_range(pm, sva, eva - sva, false, false); 2618 2619 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 2620 flags = 0; 2621 2622 while (sva < eva) { 2623 next_bucket = L2_NEXT_BUCKET(sva); 2624 if (next_bucket > eva) 2625 next_bucket = eva; 2626 2627 l2b = pmap_get_l2_bucket(pm, sva); 2628 if (l2b == NULL) { 2629 sva = next_bucket; 2630 continue; 2631 } 2632 2633 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2634 2635 while (sva < next_bucket) { 2636 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 2637 struct vm_page *pg; 2638 u_int f; 2639 2640 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 2641 pte &= ~L2_S_PROT_W; 2642 *ptep = pte; 2643 PTE_SYNC(ptep); 2644 2645 if (pg != NULL) { 2646 simple_lock(&pg->mdpage.pvh_slock); 2647 f = pmap_modify_pv(pg, pm, sva, 2648 PVF_WRITE, 0); 2649 pmap_vac_me_harder(pg, pm, sva); 2650 simple_unlock(&pg->mdpage.pvh_slock); 2651 } else 2652 f = PVF_REF | PVF_EXEC; 2653 2654 if (flush >= 0) { 2655 flush++; 2656 flags |= f; 2657 } else 2658 if (PV_BEEN_EXECD(f)) 2659 pmap_tlb_flushID_SE(pm, sva); 2660 else 2661 if (PV_BEEN_REFD(f)) 2662 pmap_tlb_flushD_SE(pm, sva); 2663 } 2664 2665 sva += PAGE_SIZE; 2666 ptep++; 2667 } 2668 } 2669 2670 pmap_release_pmap_lock(pm); 2671 PMAP_MAP_TO_HEAD_UNLOCK(); 2672 2673 if (flush) { 2674 if (PV_BEEN_EXECD(flags)) 2675 pmap_tlb_flushID(pm); 2676 else 2677 if (PV_BEEN_REFD(flags)) 2678 pmap_tlb_flushD(pm); 2679 } 2680 } 2681 2682 void 2683 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 2684 { 2685 2686 NPDEBUG(PDB_PROTECT, 2687 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 2688 pg, VM_PAGE_TO_PHYS(pg), prot)); 2689 2690 switch(prot) { 2691 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 2692 case VM_PROT_READ|VM_PROT_WRITE: 2693 return; 2694 2695 case VM_PROT_READ: 2696 case VM_PROT_READ|VM_PROT_EXECUTE: 2697 pmap_clearbit(pg, PVF_WRITE); 2698 break; 2699 2700 default: 2701 pmap_page_remove(pg); 2702 break; 2703 } 2704 } 2705 2706 /* 2707 * pmap_clear_modify: 2708 * 2709 * Clear the "modified" attribute for a page. 2710 */ 2711 bool 2712 pmap_clear_modify(struct vm_page *pg) 2713 { 2714 bool rv; 2715 2716 if (pg->mdpage.pvh_attrs & PVF_MOD) { 2717 rv = true; 2718 pmap_clearbit(pg, PVF_MOD); 2719 } else 2720 rv = false; 2721 2722 return (rv); 2723 } 2724 2725 /* 2726 * pmap_clear_reference: 2727 * 2728 * Clear the "referenced" attribute for a page. 2729 */ 2730 bool 2731 pmap_clear_reference(struct vm_page *pg) 2732 { 2733 bool rv; 2734 2735 if (pg->mdpage.pvh_attrs & PVF_REF) { 2736 rv = true; 2737 pmap_clearbit(pg, PVF_REF); 2738 } else 2739 rv = false; 2740 2741 return (rv); 2742 } 2743 2744 /* 2745 * pmap_is_modified: 2746 * 2747 * Test if a page has the "modified" attribute. 2748 */ 2749 /* See <arm/arm32/pmap.h> */ 2750 2751 /* 2752 * pmap_is_referenced: 2753 * 2754 * Test if a page has the "referenced" attribute. 2755 */ 2756 /* See <arm/arm32/pmap.h> */ 2757 2758 int 2759 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 2760 { 2761 struct l2_dtable *l2; 2762 struct l2_bucket *l2b; 2763 pd_entry_t *pl1pd, l1pd; 2764 pt_entry_t *ptep, pte; 2765 paddr_t pa; 2766 u_int l1idx; 2767 int rv = 0; 2768 2769 PMAP_MAP_TO_HEAD_LOCK(); 2770 pmap_acquire_pmap_lock(pm); 2771 2772 l1idx = L1_IDX(va); 2773 2774 /* 2775 * If there is no l2_dtable for this address, then the process 2776 * has no business accessing it. 2777 * 2778 * Note: This will catch userland processes trying to access 2779 * kernel addresses. 2780 */ 2781 l2 = pm->pm_l2[L2_IDX(l1idx)]; 2782 if (l2 == NULL) 2783 goto out; 2784 2785 /* 2786 * Likewise if there is no L2 descriptor table 2787 */ 2788 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2789 if (l2b->l2b_kva == NULL) 2790 goto out; 2791 2792 /* 2793 * Check the PTE itself. 2794 */ 2795 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2796 pte = *ptep; 2797 if (pte == 0) 2798 goto out; 2799 2800 /* 2801 * Catch a userland access to the vector page mapped at 0x0 2802 */ 2803 if (user && (pte & L2_S_PROT_U) == 0) 2804 goto out; 2805 2806 pa = l2pte_pa(pte); 2807 2808 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 2809 /* 2810 * This looks like a good candidate for "page modified" 2811 * emulation... 2812 */ 2813 struct pv_entry *pv; 2814 struct vm_page *pg; 2815 2816 /* Extract the physical address of the page */ 2817 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2818 goto out; 2819 2820 /* Get the current flags for this page. */ 2821 simple_lock(&pg->mdpage.pvh_slock); 2822 2823 pv = pmap_find_pv(pg, pm, va); 2824 if (pv == NULL) { 2825 simple_unlock(&pg->mdpage.pvh_slock); 2826 goto out; 2827 } 2828 2829 /* 2830 * Do the flags say this page is writable? If not then it 2831 * is a genuine write fault. If yes then the write fault is 2832 * our fault as we did not reflect the write access in the 2833 * PTE. Now we know a write has occurred we can correct this 2834 * and also set the modified bit 2835 */ 2836 if ((pv->pv_flags & PVF_WRITE) == 0) { 2837 simple_unlock(&pg->mdpage.pvh_slock); 2838 goto out; 2839 } 2840 2841 NPDEBUG(PDB_FOLLOW, 2842 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 2843 pm, va, VM_PAGE_TO_PHYS(pg))); 2844 2845 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 2846 pv->pv_flags |= PVF_REF | PVF_MOD; 2847 simple_unlock(&pg->mdpage.pvh_slock); 2848 2849 /* 2850 * Re-enable write permissions for the page. No need to call 2851 * pmap_vac_me_harder(), since this is just a 2852 * modified-emulation fault, and the PVF_WRITE bit isn't 2853 * changing. We've already set the cacheable bits based on 2854 * the assumption that we can write to this page. 2855 */ 2856 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 2857 PTE_SYNC(ptep); 2858 rv = 1; 2859 } else 2860 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2861 /* 2862 * This looks like a good candidate for "page referenced" 2863 * emulation. 2864 */ 2865 struct pv_entry *pv; 2866 struct vm_page *pg; 2867 2868 /* Extract the physical address of the page */ 2869 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2870 goto out; 2871 2872 /* Get the current flags for this page. */ 2873 simple_lock(&pg->mdpage.pvh_slock); 2874 2875 pv = pmap_find_pv(pg, pm, va); 2876 if (pv == NULL) { 2877 simple_unlock(&pg->mdpage.pvh_slock); 2878 goto out; 2879 } 2880 2881 pg->mdpage.pvh_attrs |= PVF_REF; 2882 pv->pv_flags |= PVF_REF; 2883 simple_unlock(&pg->mdpage.pvh_slock); 2884 2885 NPDEBUG(PDB_FOLLOW, 2886 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 2887 pm, va, VM_PAGE_TO_PHYS(pg))); 2888 2889 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2890 PTE_SYNC(ptep); 2891 rv = 1; 2892 } 2893 2894 /* 2895 * We know there is a valid mapping here, so simply 2896 * fix up the L1 if necessary. 2897 */ 2898 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2899 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2900 if (*pl1pd != l1pd) { 2901 *pl1pd = l1pd; 2902 PTE_SYNC(pl1pd); 2903 rv = 1; 2904 } 2905 2906 #ifdef CPU_SA110 2907 /* 2908 * There are bugs in the rev K SA110. This is a check for one 2909 * of them. 2910 */ 2911 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2912 curcpu()->ci_arm_cpurev < 3) { 2913 /* Always current pmap */ 2914 if (l2pte_valid(pte)) { 2915 extern int kernel_debug; 2916 if (kernel_debug & 1) { 2917 struct proc *p = curlwp->l_proc; 2918 printf("prefetch_abort: page is already " 2919 "mapped - pte=%p *pte=%08x\n", ptep, pte); 2920 printf("prefetch_abort: pc=%08lx proc=%p " 2921 "process=%s\n", va, p, p->p_comm); 2922 printf("prefetch_abort: far=%08x fs=%x\n", 2923 cpu_faultaddress(), cpu_faultstatus()); 2924 } 2925 #ifdef DDB 2926 if (kernel_debug & 2) 2927 Debugger(); 2928 #endif 2929 rv = 1; 2930 } 2931 } 2932 #endif /* CPU_SA110 */ 2933 2934 #ifdef DEBUG 2935 /* 2936 * If 'rv == 0' at this point, it generally indicates that there is a 2937 * stale TLB entry for the faulting address. This happens when two or 2938 * more processes are sharing an L1. Since we don't flush the TLB on 2939 * a context switch between such processes, we can take domain faults 2940 * for mappings which exist at the same VA in both processes. EVEN IF 2941 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2942 * example. 2943 * 2944 * This is extremely likely to happen if pmap_enter() updated the L1 2945 * entry for a recently entered mapping. In this case, the TLB is 2946 * flushed for the new mapping, but there may still be TLB entries for 2947 * other mappings belonging to other processes in the 1MB range 2948 * covered by the L1 entry. 2949 * 2950 * Since 'rv == 0', we know that the L1 already contains the correct 2951 * value, so the fault must be due to a stale TLB entry. 2952 * 2953 * Since we always need to flush the TLB anyway in the case where we 2954 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2955 * stale TLB entries dynamically. 2956 * 2957 * However, the above condition can ONLY happen if the current L1 is 2958 * being shared. If it happens when the L1 is unshared, it indicates 2959 * that other parts of the pmap are not doing their job WRT managing 2960 * the TLB. 2961 */ 2962 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2963 extern int last_fault_code; 2964 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2965 pm, va, ftype); 2966 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2967 l2, l2b, ptep, pl1pd); 2968 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2969 pte, l1pd, last_fault_code); 2970 #ifdef DDB 2971 Debugger(); 2972 #endif 2973 } 2974 #endif 2975 2976 cpu_tlb_flushID_SE(va); 2977 cpu_cpwait(); 2978 2979 rv = 1; 2980 2981 out: 2982 pmap_release_pmap_lock(pm); 2983 PMAP_MAP_TO_HEAD_UNLOCK(); 2984 2985 return (rv); 2986 } 2987 2988 /* 2989 * pmap_collect: free resources held by a pmap 2990 * 2991 * => optional function. 2992 * => called when a process is swapped out to free memory. 2993 */ 2994 void 2995 pmap_collect(pmap_t pm) 2996 { 2997 2998 pmap_idcache_wbinv_all(pm); 2999 pm->pm_remove_all = true; 3000 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 3001 pmap_update(pm); 3002 } 3003 3004 /* 3005 * Routine: pmap_procwr 3006 * 3007 * Function: 3008 * Synchronize caches corresponding to [addr, addr+len) in p. 3009 * 3010 */ 3011 void 3012 pmap_procwr(struct proc *p, vaddr_t va, int len) 3013 { 3014 /* We only need to do anything if it is the current process. */ 3015 if (p == curproc) 3016 cpu_icache_sync_range(va, len); 3017 } 3018 3019 /* 3020 * Routine: pmap_unwire 3021 * Function: Clear the wired attribute for a map/virtual-address pair. 3022 * 3023 * In/out conditions: 3024 * The mapping must already exist in the pmap. 3025 */ 3026 void 3027 pmap_unwire(pmap_t pm, vaddr_t va) 3028 { 3029 struct l2_bucket *l2b; 3030 pt_entry_t *ptep, pte; 3031 struct vm_page *pg; 3032 paddr_t pa; 3033 3034 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 3035 3036 PMAP_MAP_TO_HEAD_LOCK(); 3037 pmap_acquire_pmap_lock(pm); 3038 3039 l2b = pmap_get_l2_bucket(pm, va); 3040 KDASSERT(l2b != NULL); 3041 3042 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3043 pte = *ptep; 3044 3045 /* Extract the physical address of the page */ 3046 pa = l2pte_pa(pte); 3047 3048 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3049 /* Update the wired bit in the pv entry for this page. */ 3050 simple_lock(&pg->mdpage.pvh_slock); 3051 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 3052 simple_unlock(&pg->mdpage.pvh_slock); 3053 } 3054 3055 pmap_release_pmap_lock(pm); 3056 PMAP_MAP_TO_HEAD_UNLOCK(); 3057 } 3058 3059 void 3060 pmap_activate(struct lwp *l) 3061 { 3062 extern int block_userspace_access; 3063 pmap_t opm, npm, rpm; 3064 uint32_t odacr, ndacr; 3065 int oldirqstate; 3066 3067 /* 3068 * If activating a non-current lwp or the current lwp is 3069 * already active, just return. 3070 */ 3071 if (l != curlwp || 3072 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 3073 return; 3074 3075 npm = l->l_proc->p_vmspace->vm_map.pmap; 3076 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3077 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 3078 3079 /* 3080 * If TTB and DACR are unchanged, short-circuit all the 3081 * TLB/cache management stuff. 3082 */ 3083 if (pmap_previous_active_lwp != NULL) { 3084 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 3085 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3086 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 3087 3088 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 3089 goto all_done; 3090 } else 3091 opm = NULL; 3092 3093 block_userspace_access = 1; 3094 3095 /* 3096 * If switching to a user vmspace which is different to the 3097 * most recent one, and the most recent one is potentially 3098 * live in the cache, we must write-back and invalidate the 3099 * entire cache. 3100 */ 3101 rpm = pmap_recent_user; 3102 if (npm != pmap_kernel() && rpm && npm != rpm && 3103 rpm->pm_cstate.cs_cache) { 3104 rpm->pm_cstate.cs_cache = 0; 3105 cpu_idcache_wbinv_all(); 3106 } 3107 3108 /* No interrupts while we frob the TTB/DACR */ 3109 oldirqstate = disable_interrupts(I32_bit | F32_bit); 3110 3111 /* 3112 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 3113 * entry corresponding to 'vector_page' in the incoming L1 table 3114 * before switching to it otherwise subsequent interrupts/exceptions 3115 * (including domain faults!) will jump into hyperspace. 3116 */ 3117 if (npm->pm_pl1vec != NULL) { 3118 cpu_tlb_flushID_SE((u_int)vector_page); 3119 cpu_cpwait(); 3120 *npm->pm_pl1vec = npm->pm_l1vec; 3121 PTE_SYNC(npm->pm_pl1vec); 3122 } 3123 3124 cpu_domains(ndacr); 3125 3126 if (npm == pmap_kernel() || npm == rpm) { 3127 /* 3128 * Switching to a kernel thread, or back to the 3129 * same user vmspace as before... Simply update 3130 * the TTB (no TLB flush required) 3131 */ 3132 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 3133 "r"(npm->pm_l1->l1_physaddr)); 3134 cpu_cpwait(); 3135 } else { 3136 /* 3137 * Otherwise, update TTB and flush TLB 3138 */ 3139 cpu_context_switch(npm->pm_l1->l1_physaddr); 3140 if (rpm != NULL) 3141 rpm->pm_cstate.cs_tlb = 0; 3142 } 3143 3144 restore_interrupts(oldirqstate); 3145 3146 block_userspace_access = 0; 3147 3148 all_done: 3149 /* 3150 * The new pmap is resident. Make sure it's marked 3151 * as resident in the cache/TLB. 3152 */ 3153 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3154 if (npm != pmap_kernel()) 3155 pmap_recent_user = npm; 3156 3157 /* The old pmap is not longer active */ 3158 if (opm != NULL) 3159 opm->pm_activated = false; 3160 3161 /* But the new one is */ 3162 npm->pm_activated = true; 3163 } 3164 3165 void 3166 pmap_deactivate(struct lwp *l) 3167 { 3168 3169 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 3170 } 3171 3172 void 3173 pmap_update(pmap_t pm) 3174 { 3175 3176 if (pm->pm_remove_all) { 3177 /* 3178 * Finish up the pmap_remove_all() optimisation by flushing 3179 * the TLB. 3180 */ 3181 pmap_tlb_flushID(pm); 3182 pm->pm_remove_all = false; 3183 } 3184 3185 if (pmap_is_current(pm)) { 3186 /* 3187 * If we're dealing with a current userland pmap, move its L1 3188 * to the end of the LRU. 3189 */ 3190 if (pm != pmap_kernel()) 3191 pmap_use_l1(pm); 3192 3193 /* 3194 * We can assume we're done with frobbing the cache/tlb for 3195 * now. Make sure any future pmap ops don't skip cache/tlb 3196 * flushes. 3197 */ 3198 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3199 } 3200 3201 /* 3202 * make sure TLB/cache operations have completed. 3203 */ 3204 cpu_cpwait(); 3205 } 3206 3207 void 3208 pmap_remove_all(pmap_t pm) 3209 { 3210 3211 /* 3212 * The vmspace described by this pmap is about to be torn down. 3213 * Until pmap_update() is called, UVM will only make calls 3214 * to pmap_remove(). We can make life much simpler by flushing 3215 * the cache now, and deferring TLB invalidation to pmap_update(). 3216 */ 3217 pmap_idcache_wbinv_all(pm); 3218 pm->pm_remove_all = true; 3219 } 3220 3221 /* 3222 * Retire the given physical map from service. 3223 * Should only be called if the map contains no valid mappings. 3224 */ 3225 void 3226 pmap_destroy(pmap_t pm) 3227 { 3228 u_int count; 3229 3230 if (pm == NULL) 3231 return; 3232 3233 if (pm->pm_remove_all) { 3234 pmap_tlb_flushID(pm); 3235 pm->pm_remove_all = false; 3236 } 3237 3238 /* 3239 * Drop reference count 3240 */ 3241 mutex_enter(&pm->pm_lock); 3242 count = --pm->pm_obj.uo_refs; 3243 mutex_exit(&pm->pm_lock); 3244 if (count > 0) { 3245 if (pmap_is_current(pm)) { 3246 if (pm != pmap_kernel()) 3247 pmap_use_l1(pm); 3248 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3249 } 3250 return; 3251 } 3252 3253 /* 3254 * reference count is zero, free pmap resources and then free pmap. 3255 */ 3256 3257 if (vector_page < KERNEL_BASE) { 3258 KDASSERT(!pmap_is_current(pm)); 3259 3260 /* Remove the vector page mapping */ 3261 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 3262 pmap_update(pm); 3263 } 3264 3265 LIST_REMOVE(pm, pm_list); 3266 3267 pmap_free_l1(pm); 3268 3269 if (pmap_recent_user == pm) 3270 pmap_recent_user = NULL; 3271 3272 UVM_OBJ_DESTROY(&pm->pm_obj); 3273 3274 /* return the pmap to the pool */ 3275 pool_cache_put(&pmap_cache, pm); 3276 } 3277 3278 3279 /* 3280 * void pmap_reference(pmap_t pm) 3281 * 3282 * Add a reference to the specified pmap. 3283 */ 3284 void 3285 pmap_reference(pmap_t pm) 3286 { 3287 3288 if (pm == NULL) 3289 return; 3290 3291 pmap_use_l1(pm); 3292 3293 mutex_enter(&pm->pm_lock); 3294 pm->pm_obj.uo_refs++; 3295 mutex_exit(&pm->pm_lock); 3296 } 3297 3298 /* 3299 * pmap_zero_page() 3300 * 3301 * Zero a given physical page by mapping it at a page hook point. 3302 * In doing the zero page op, the page we zero is mapped cachable, as with 3303 * StrongARM accesses to non-cached pages are non-burst making writing 3304 * _any_ bulk data very slow. 3305 */ 3306 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3307 void 3308 pmap_zero_page_generic(paddr_t phys) 3309 { 3310 #ifdef DEBUG 3311 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3312 3313 if (pg->mdpage.pvh_list != NULL) 3314 panic("pmap_zero_page: page has mappings"); 3315 #endif 3316 3317 KDASSERT((phys & PGOFSET) == 0); 3318 3319 /* 3320 * Hook in the page, zero it, and purge the cache for that 3321 * zeroed page. Invalidate the TLB as needed. 3322 */ 3323 *cdst_pte = L2_S_PROTO | phys | 3324 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3325 PTE_SYNC(cdst_pte); 3326 cpu_tlb_flushD_SE(cdstp); 3327 cpu_cpwait(); 3328 bzero_page(cdstp); 3329 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3330 } 3331 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3332 3333 #if ARM_MMU_XSCALE == 1 3334 void 3335 pmap_zero_page_xscale(paddr_t phys) 3336 { 3337 #ifdef DEBUG 3338 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3339 3340 if (pg->mdpage.pvh_list != NULL) 3341 panic("pmap_zero_page: page has mappings"); 3342 #endif 3343 3344 KDASSERT((phys & PGOFSET) == 0); 3345 3346 /* 3347 * Hook in the page, zero it, and purge the cache for that 3348 * zeroed page. Invalidate the TLB as needed. 3349 */ 3350 *cdst_pte = L2_S_PROTO | phys | 3351 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3352 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3353 PTE_SYNC(cdst_pte); 3354 cpu_tlb_flushD_SE(cdstp); 3355 cpu_cpwait(); 3356 bzero_page(cdstp); 3357 xscale_cache_clean_minidata(); 3358 } 3359 #endif /* ARM_MMU_XSCALE == 1 */ 3360 3361 /* pmap_pageidlezero() 3362 * 3363 * The same as above, except that we assume that the page is not 3364 * mapped. This means we never have to flush the cache first. Called 3365 * from the idle loop. 3366 */ 3367 bool 3368 pmap_pageidlezero(paddr_t phys) 3369 { 3370 unsigned int i; 3371 int *ptr; 3372 bool rv = true; 3373 #ifdef DEBUG 3374 struct vm_page *pg; 3375 3376 pg = PHYS_TO_VM_PAGE(phys); 3377 if (pg->mdpage.pvh_list != NULL) 3378 panic("pmap_pageidlezero: page has mappings"); 3379 #endif 3380 3381 KDASSERT((phys & PGOFSET) == 0); 3382 3383 /* 3384 * Hook in the page, zero it, and purge the cache for that 3385 * zeroed page. Invalidate the TLB as needed. 3386 */ 3387 *cdst_pte = L2_S_PROTO | phys | 3388 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3389 PTE_SYNC(cdst_pte); 3390 cpu_tlb_flushD_SE(cdstp); 3391 cpu_cpwait(); 3392 3393 for (i = 0, ptr = (int *)cdstp; 3394 i < (PAGE_SIZE / sizeof(int)); i++) { 3395 if (sched_curcpu_runnable_p()) { 3396 /* 3397 * A process has become ready. Abort now, 3398 * so we don't keep it waiting while we 3399 * do slow memory access to finish this 3400 * page. 3401 */ 3402 rv = false; 3403 break; 3404 } 3405 *ptr++ = 0; 3406 } 3407 3408 if (rv) 3409 /* 3410 * if we aborted we'll rezero this page again later so don't 3411 * purge it unless we finished it 3412 */ 3413 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3414 3415 return (rv); 3416 } 3417 3418 /* 3419 * pmap_copy_page() 3420 * 3421 * Copy one physical page into another, by mapping the pages into 3422 * hook points. The same comment regarding cachability as in 3423 * pmap_zero_page also applies here. 3424 */ 3425 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3426 void 3427 pmap_copy_page_generic(paddr_t src, paddr_t dst) 3428 { 3429 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 3430 #ifdef DEBUG 3431 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 3432 3433 if (dst_pg->mdpage.pvh_list != NULL) 3434 panic("pmap_copy_page: dst page has mappings"); 3435 #endif 3436 3437 KDASSERT((src & PGOFSET) == 0); 3438 KDASSERT((dst & PGOFSET) == 0); 3439 3440 /* 3441 * Clean the source page. Hold the source page's lock for 3442 * the duration of the copy so that no other mappings can 3443 * be created while we have a potentially aliased mapping. 3444 */ 3445 simple_lock(&src_pg->mdpage.pvh_slock); 3446 (void) pmap_clean_page(src_pg->mdpage.pvh_list, true); 3447 3448 /* 3449 * Map the pages into the page hook points, copy them, and purge 3450 * the cache for the appropriate page. Invalidate the TLB 3451 * as required. 3452 */ 3453 *csrc_pte = L2_S_PROTO | src | 3454 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 3455 PTE_SYNC(csrc_pte); 3456 *cdst_pte = L2_S_PROTO | dst | 3457 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3458 PTE_SYNC(cdst_pte); 3459 cpu_tlb_flushD_SE(csrcp); 3460 cpu_tlb_flushD_SE(cdstp); 3461 cpu_cpwait(); 3462 bcopy_page(csrcp, cdstp); 3463 cpu_dcache_inv_range(csrcp, PAGE_SIZE); 3464 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 3465 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3466 } 3467 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3468 3469 #if ARM_MMU_XSCALE == 1 3470 void 3471 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 3472 { 3473 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 3474 #ifdef DEBUG 3475 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 3476 3477 if (dst_pg->mdpage.pvh_list != NULL) 3478 panic("pmap_copy_page: dst page has mappings"); 3479 #endif 3480 3481 KDASSERT((src & PGOFSET) == 0); 3482 KDASSERT((dst & PGOFSET) == 0); 3483 3484 /* 3485 * Clean the source page. Hold the source page's lock for 3486 * the duration of the copy so that no other mappings can 3487 * be created while we have a potentially aliased mapping. 3488 */ 3489 simple_lock(&src_pg->mdpage.pvh_slock); 3490 (void) pmap_clean_page(src_pg->mdpage.pvh_list, true); 3491 3492 /* 3493 * Map the pages into the page hook points, copy them, and purge 3494 * the cache for the appropriate page. Invalidate the TLB 3495 * as required. 3496 */ 3497 *csrc_pte = L2_S_PROTO | src | 3498 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 3499 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3500 PTE_SYNC(csrc_pte); 3501 *cdst_pte = L2_S_PROTO | dst | 3502 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3503 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3504 PTE_SYNC(cdst_pte); 3505 cpu_tlb_flushD_SE(csrcp); 3506 cpu_tlb_flushD_SE(cdstp); 3507 cpu_cpwait(); 3508 bcopy_page(csrcp, cdstp); 3509 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 3510 xscale_cache_clean_minidata(); 3511 } 3512 #endif /* ARM_MMU_XSCALE == 1 */ 3513 3514 /* 3515 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 3516 * 3517 * Return the start and end addresses of the kernel's virtual space. 3518 * These values are setup in pmap_bootstrap and are updated as pages 3519 * are allocated. 3520 */ 3521 void 3522 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 3523 { 3524 *start = virtual_avail; 3525 *end = virtual_end; 3526 } 3527 3528 /* 3529 * Helper function for pmap_grow_l2_bucket() 3530 */ 3531 static inline int 3532 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 3533 { 3534 struct l2_bucket *l2b; 3535 pt_entry_t *ptep; 3536 paddr_t pa; 3537 3538 if (uvm.page_init_done == false) { 3539 if (uvm_page_physget(&pa) == false) 3540 return (1); 3541 } else { 3542 struct vm_page *pg; 3543 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 3544 if (pg == NULL) 3545 return (1); 3546 pa = VM_PAGE_TO_PHYS(pg); 3547 } 3548 3549 if (pap) 3550 *pap = pa; 3551 3552 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3553 KDASSERT(l2b != NULL); 3554 3555 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3556 *ptep = L2_S_PROTO | pa | cache_mode | 3557 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 3558 PTE_SYNC(ptep); 3559 memset((void *)va, 0, PAGE_SIZE); 3560 return (0); 3561 } 3562 3563 /* 3564 * This is the same as pmap_alloc_l2_bucket(), except that it is only 3565 * used by pmap_growkernel(). 3566 */ 3567 static inline struct l2_bucket * 3568 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 3569 { 3570 struct l2_dtable *l2; 3571 struct l2_bucket *l2b; 3572 u_short l1idx; 3573 vaddr_t nva; 3574 3575 l1idx = L1_IDX(va); 3576 3577 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 3578 /* 3579 * No mapping at this address, as there is 3580 * no entry in the L1 table. 3581 * Need to allocate a new l2_dtable. 3582 */ 3583 nva = pmap_kernel_l2dtable_kva; 3584 if ((nva & PGOFSET) == 0) { 3585 /* 3586 * Need to allocate a backing page 3587 */ 3588 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 3589 return (NULL); 3590 } 3591 3592 l2 = (struct l2_dtable *)nva; 3593 nva += sizeof(struct l2_dtable); 3594 3595 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 3596 /* 3597 * The new l2_dtable straddles a page boundary. 3598 * Map in another page to cover it. 3599 */ 3600 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 3601 return (NULL); 3602 } 3603 3604 pmap_kernel_l2dtable_kva = nva; 3605 3606 /* 3607 * Link it into the parent pmap 3608 */ 3609 pm->pm_l2[L2_IDX(l1idx)] = l2; 3610 } 3611 3612 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3613 3614 /* 3615 * Fetch pointer to the L2 page table associated with the address. 3616 */ 3617 if (l2b->l2b_kva == NULL) { 3618 pt_entry_t *ptep; 3619 3620 /* 3621 * No L2 page table has been allocated. Chances are, this 3622 * is because we just allocated the l2_dtable, above. 3623 */ 3624 nva = pmap_kernel_l2ptp_kva; 3625 ptep = (pt_entry_t *)nva; 3626 if ((nva & PGOFSET) == 0) { 3627 /* 3628 * Need to allocate a backing page 3629 */ 3630 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 3631 &pmap_kernel_l2ptp_phys)) 3632 return (NULL); 3633 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 3634 } 3635 3636 l2->l2_occupancy++; 3637 l2b->l2b_kva = ptep; 3638 l2b->l2b_l1idx = l1idx; 3639 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 3640 3641 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 3642 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 3643 } 3644 3645 return (l2b); 3646 } 3647 3648 vaddr_t 3649 pmap_growkernel(vaddr_t maxkvaddr) 3650 { 3651 pmap_t kpm = pmap_kernel(); 3652 struct l1_ttable *l1; 3653 struct l2_bucket *l2b; 3654 pd_entry_t *pl1pd; 3655 int s; 3656 3657 if (maxkvaddr <= pmap_curmaxkvaddr) 3658 goto out; /* we are OK */ 3659 3660 NPDEBUG(PDB_GROWKERN, 3661 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 3662 pmap_curmaxkvaddr, maxkvaddr)); 3663 3664 KDASSERT(maxkvaddr <= virtual_end); 3665 3666 /* 3667 * whoops! we need to add kernel PTPs 3668 */ 3669 3670 s = splhigh(); /* to be safe */ 3671 mutex_enter(&kpm->pm_lock); 3672 3673 /* Map 1MB at a time */ 3674 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 3675 3676 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 3677 KDASSERT(l2b != NULL); 3678 3679 /* Distribute new L1 entry to all other L1s */ 3680 SLIST_FOREACH(l1, &l1_list, l1_link) { 3681 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 3682 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 3683 L1_C_PROTO; 3684 PTE_SYNC(pl1pd); 3685 } 3686 } 3687 3688 /* 3689 * flush out the cache, expensive but growkernel will happen so 3690 * rarely 3691 */ 3692 cpu_dcache_wbinv_all(); 3693 cpu_tlb_flushD(); 3694 cpu_cpwait(); 3695 3696 mutex_exit(&kpm->pm_lock); 3697 splx(s); 3698 3699 out: 3700 return (pmap_curmaxkvaddr); 3701 } 3702 3703 /************************ Utility routines ****************************/ 3704 3705 /* 3706 * vector_page_setprot: 3707 * 3708 * Manipulate the protection of the vector page. 3709 */ 3710 void 3711 vector_page_setprot(int prot) 3712 { 3713 struct l2_bucket *l2b; 3714 pt_entry_t *ptep; 3715 3716 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 3717 KDASSERT(l2b != NULL); 3718 3719 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 3720 3721 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 3722 PTE_SYNC(ptep); 3723 cpu_tlb_flushD_SE(vector_page); 3724 cpu_cpwait(); 3725 } 3726 3727 /* 3728 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3729 * Returns true if the mapping exists, else false. 3730 * 3731 * NOTE: This function is only used by a couple of arm-specific modules. 3732 * It is not safe to take any pmap locks here, since we could be right 3733 * in the middle of debugging the pmap anyway... 3734 * 3735 * It is possible for this routine to return false even though a valid 3736 * mapping does exist. This is because we don't lock, so the metadata 3737 * state may be inconsistent. 3738 * 3739 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3740 * a "section" mapping. 3741 */ 3742 bool 3743 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3744 { 3745 struct l2_dtable *l2; 3746 pd_entry_t *pl1pd, l1pd; 3747 pt_entry_t *ptep; 3748 u_short l1idx; 3749 3750 if (pm->pm_l1 == NULL) 3751 return (false); 3752 3753 l1idx = L1_IDX(va); 3754 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3755 l1pd = *pl1pd; 3756 3757 if (l1pte_section_p(l1pd)) { 3758 *ptp = NULL; 3759 return (true); 3760 } 3761 3762 if (pm->pm_l2 == NULL) 3763 return (false); 3764 3765 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3766 3767 if (l2 == NULL || 3768 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3769 return (false); 3770 } 3771 3772 *ptp = &ptep[l2pte_index(va)]; 3773 return (true); 3774 } 3775 3776 bool 3777 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 3778 { 3779 u_short l1idx; 3780 3781 if (pm->pm_l1 == NULL) 3782 return (false); 3783 3784 l1idx = L1_IDX(va); 3785 *pdp = &pm->pm_l1->l1_kva[l1idx]; 3786 3787 return (true); 3788 } 3789 3790 /************************ Bootstrapping routines ****************************/ 3791 3792 static void 3793 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 3794 { 3795 int i; 3796 3797 l1->l1_kva = l1pt; 3798 l1->l1_domain_use_count = 0; 3799 l1->l1_domain_first = 0; 3800 3801 for (i = 0; i < PMAP_DOMAINS; i++) 3802 l1->l1_domain_free[i] = i + 1; 3803 3804 /* 3805 * Copy the kernel's L1 entries to each new L1. 3806 */ 3807 if (pmap_initialized) 3808 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 3809 3810 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 3811 &l1->l1_physaddr) == false) 3812 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 3813 3814 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 3815 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 3816 } 3817 3818 /* 3819 * pmap_bootstrap() is called from the board-specific initarm() routine 3820 * once the kernel L1/L2 descriptors tables have been set up. 3821 * 3822 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 3823 * spread over a number of disparate files/functions. 3824 * 3825 * We are passed the following parameters 3826 * - kernel_l1pt 3827 * This is a pointer to the base of the kernel's L1 translation table. 3828 * - vstart 3829 * 1MB-aligned start of managed kernel virtual memory. 3830 * - vend 3831 * 1MB-aligned end of managed kernel virtual memory. 3832 * 3833 * We use the first parameter to build the metadata (struct l1_ttable and 3834 * struct l2_dtable) necessary to track kernel mappings. 3835 */ 3836 #define PMAP_STATIC_L2_SIZE 16 3837 void 3838 pmap_bootstrap(pd_entry_t *kernel_l1pt, vaddr_t vstart, vaddr_t vend) 3839 { 3840 static struct l1_ttable static_l1; 3841 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 3842 struct l1_ttable *l1 = &static_l1; 3843 struct l2_dtable *l2; 3844 struct l2_bucket *l2b; 3845 pmap_t pm = pmap_kernel(); 3846 pd_entry_t pde; 3847 pt_entry_t *ptep; 3848 paddr_t pa; 3849 vaddr_t va; 3850 vsize_t size; 3851 int l1idx, l2idx, l2next = 0; 3852 3853 /* 3854 * Initialise the kernel pmap object 3855 */ 3856 pm->pm_l1 = l1; 3857 pm->pm_domain = PMAP_DOMAIN_KERNEL; 3858 pm->pm_activated = true; 3859 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3860 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 3861 3862 /* 3863 * Scan the L1 translation table created by initarm() and create 3864 * the required metadata for all valid mappings found in it. 3865 */ 3866 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 3867 pde = kernel_l1pt[l1idx]; 3868 3869 /* 3870 * We're only interested in Coarse mappings. 3871 * pmap_extract() can deal with section mappings without 3872 * recourse to checking L2 metadata. 3873 */ 3874 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 3875 continue; 3876 3877 /* 3878 * Lookup the KVA of this L2 descriptor table 3879 */ 3880 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 3881 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 3882 if (ptep == NULL) { 3883 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 3884 (u_int)l1idx << L1_S_SHIFT, pa); 3885 } 3886 3887 /* 3888 * Fetch the associated L2 metadata structure. 3889 * Allocate a new one if necessary. 3890 */ 3891 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 3892 if (l2next == PMAP_STATIC_L2_SIZE) 3893 panic("pmap_bootstrap: out of static L2s"); 3894 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 3895 } 3896 3897 /* 3898 * One more L1 slot tracked... 3899 */ 3900 l2->l2_occupancy++; 3901 3902 /* 3903 * Fill in the details of the L2 descriptor in the 3904 * appropriate bucket. 3905 */ 3906 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3907 l2b->l2b_kva = ptep; 3908 l2b->l2b_phys = pa; 3909 l2b->l2b_l1idx = l1idx; 3910 3911 /* 3912 * Establish an initial occupancy count for this descriptor 3913 */ 3914 for (l2idx = 0; 3915 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 3916 l2idx++) { 3917 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 3918 l2b->l2b_occupancy++; 3919 } 3920 } 3921 3922 /* 3923 * Make sure the descriptor itself has the correct cache mode. 3924 * If not, fix it, but whine about the problem. Port-meisters 3925 * should consider this a clue to fix up their initarm() 3926 * function. :) 3927 */ 3928 if (pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)ptep)) { 3929 printf("pmap_bootstrap: WARNING! wrong cache mode for " 3930 "L2 pte @ %p\n", ptep); 3931 } 3932 } 3933 3934 /* 3935 * Ensure the primary (kernel) L1 has the correct cache mode for 3936 * a page table. Bitch if it is not correctly set. 3937 */ 3938 for (va = (vaddr_t)kernel_l1pt; 3939 va < ((vaddr_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 3940 if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 3941 printf("pmap_bootstrap: WARNING! wrong cache mode for " 3942 "primary L1 @ 0x%lx\n", va); 3943 } 3944 3945 cpu_dcache_wbinv_all(); 3946 cpu_tlb_flushID(); 3947 cpu_cpwait(); 3948 3949 /* 3950 * now we allocate the "special" VAs which are used for tmp mappings 3951 * by the pmap (and other modules). we allocate the VAs by advancing 3952 * virtual_avail (note that there are no pages mapped at these VAs). 3953 * 3954 * Managed KVM space start from wherever initarm() tells us. 3955 */ 3956 virtual_avail = vstart; 3957 virtual_end = vend; 3958 3959 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 3960 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)csrc_pte); 3961 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 3962 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)cdst_pte); 3963 pmap_alloc_specials(&virtual_avail, 1, &memhook, NULL); 3964 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 3965 (void *)&msgbufaddr, NULL); 3966 3967 /* 3968 * Allocate a range of kernel virtual address space to be used 3969 * for L2 descriptor tables and metadata allocation in 3970 * pmap_growkernel(). 3971 */ 3972 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 3973 pmap_alloc_specials(&virtual_avail, 3974 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 3975 &pmap_kernel_l2ptp_kva, NULL); 3976 3977 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 3978 pmap_alloc_specials(&virtual_avail, 3979 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 3980 &pmap_kernel_l2dtable_kva, NULL); 3981 3982 /* 3983 * init the static-global locks and global pmap list. 3984 */ 3985 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 3986 3987 /* 3988 * We can now initialise the first L1's metadata. 3989 */ 3990 SLIST_INIT(&l1_list); 3991 TAILQ_INIT(&l1_lru_list); 3992 simple_lock_init(&l1_lru_lock); 3993 pmap_init_l1(l1, kernel_l1pt); 3994 3995 /* Set up vector page L1 details, if necessary */ 3996 if (vector_page < KERNEL_BASE) { 3997 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 3998 l2b = pmap_get_l2_bucket(pm, vector_page); 3999 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 4000 L1_C_DOM(pm->pm_domain); 4001 } else 4002 pm->pm_pl1vec = NULL; 4003 4004 /* 4005 * Initialize the pmap cache 4006 */ 4007 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 4008 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 4009 LIST_INIT(&pmap_pmaps); 4010 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 4011 4012 /* 4013 * Initialize the pv pool. 4014 */ 4015 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 4016 &pmap_bootstrap_pv_allocator, IPL_NONE); 4017 4018 /* 4019 * Initialize the L2 dtable pool and cache. 4020 */ 4021 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 4022 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 4023 4024 /* 4025 * Initialise the L2 descriptor table pool and cache 4026 */ 4027 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 4028 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 4029 pmap_l2ptp_ctor, NULL, NULL); 4030 4031 cpu_dcache_wbinv_all(); 4032 } 4033 4034 static int 4035 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 4036 { 4037 pd_entry_t *pdep, pde; 4038 pt_entry_t *ptep, pte; 4039 vaddr_t pa; 4040 int rv = 0; 4041 4042 /* 4043 * Make sure the descriptor itself has the correct cache mode 4044 */ 4045 pdep = &kl1[L1_IDX(va)]; 4046 pde = *pdep; 4047 4048 if (l1pte_section_p(pde)) { 4049 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 4050 *pdep = (pde & ~L1_S_CACHE_MASK) | 4051 pte_l1_s_cache_mode_pt; 4052 PTE_SYNC(pdep); 4053 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 4054 rv = 1; 4055 } 4056 } else { 4057 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 4058 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 4059 if (ptep == NULL) 4060 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 4061 4062 ptep = &ptep[l2pte_index(va)]; 4063 pte = *ptep; 4064 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 4065 *ptep = (pte & ~L2_S_CACHE_MASK) | 4066 pte_l2_s_cache_mode_pt; 4067 PTE_SYNC(ptep); 4068 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 4069 rv = 1; 4070 } 4071 } 4072 4073 return (rv); 4074 } 4075 4076 static void 4077 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 4078 { 4079 vaddr_t va = *availp; 4080 struct l2_bucket *l2b; 4081 4082 if (ptep) { 4083 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4084 if (l2b == NULL) 4085 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 4086 4087 if (ptep) 4088 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 4089 } 4090 4091 *vap = va; 4092 *availp = va + (PAGE_SIZE * pages); 4093 } 4094 4095 void 4096 pmap_init(void) 4097 { 4098 extern int physmem; 4099 4100 /* 4101 * Set the available memory vars - These do not map to real memory 4102 * addresses and cannot as the physical memory is fragmented. 4103 * They are used by ps for %mem calculations. 4104 * One could argue whether this should be the entire memory or just 4105 * the memory that is useable in a user process. 4106 */ 4107 avail_start = 0; 4108 avail_end = physmem * PAGE_SIZE; 4109 4110 /* 4111 * Now we need to free enough pv_entry structures to allow us to get 4112 * the kmem_map/kmem_object allocated and inited (done after this 4113 * function is finished). to do this we allocate one bootstrap page out 4114 * of kernel_map and use it to provide an initial pool of pv_entry 4115 * structures. we never free this page. 4116 */ 4117 pool_setlowat(&pmap_pv_pool, 4118 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 4119 4120 pmap_initialized = true; 4121 } 4122 4123 static vaddr_t last_bootstrap_page = 0; 4124 static void *free_bootstrap_pages = NULL; 4125 4126 static void * 4127 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 4128 { 4129 extern void *pool_page_alloc(struct pool *, int); 4130 vaddr_t new_page; 4131 void *rv; 4132 4133 if (pmap_initialized) 4134 return (pool_page_alloc(pp, flags)); 4135 4136 if (free_bootstrap_pages) { 4137 rv = free_bootstrap_pages; 4138 free_bootstrap_pages = *((void **)rv); 4139 return (rv); 4140 } 4141 4142 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 4143 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 4144 4145 KASSERT(new_page > last_bootstrap_page); 4146 last_bootstrap_page = new_page; 4147 return ((void *)new_page); 4148 } 4149 4150 static void 4151 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 4152 { 4153 extern void pool_page_free(struct pool *, void *); 4154 4155 if ((vaddr_t)v <= last_bootstrap_page) { 4156 *((void **)v) = free_bootstrap_pages; 4157 free_bootstrap_pages = v; 4158 return; 4159 } 4160 4161 if (pmap_initialized) { 4162 pool_page_free(pp, v); 4163 return; 4164 } 4165 } 4166 4167 /* 4168 * pmap_postinit() 4169 * 4170 * This routine is called after the vm and kmem subsystems have been 4171 * initialised. This allows the pmap code to perform any initialisation 4172 * that can only be done one the memory allocation is in place. 4173 */ 4174 void 4175 pmap_postinit(void) 4176 { 4177 extern paddr_t physical_start, physical_end; 4178 struct l2_bucket *l2b; 4179 struct l1_ttable *l1; 4180 struct pglist plist; 4181 struct vm_page *m; 4182 pd_entry_t *pl1pt; 4183 pt_entry_t *ptep, pte; 4184 vaddr_t va, eva; 4185 u_int loop, needed; 4186 int error; 4187 4188 pool_cache_setlowat(&pmap_l2ptp_cache, 4189 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 4190 pool_cache_setlowat(&pmap_l2dtable_cache, 4191 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 4192 4193 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 4194 needed -= 1; 4195 4196 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 4197 4198 for (loop = 0; loop < needed; loop++, l1++) { 4199 /* Allocate a L1 page table */ 4200 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 4201 if (va == 0) 4202 panic("Cannot allocate L1 KVM"); 4203 4204 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 4205 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 4206 if (error) 4207 panic("Cannot allocate L1 physical pages"); 4208 4209 m = TAILQ_FIRST(&plist); 4210 eva = va + L1_TABLE_SIZE; 4211 pl1pt = (pd_entry_t *)va; 4212 4213 while (m && va < eva) { 4214 paddr_t pa = VM_PAGE_TO_PHYS(m); 4215 4216 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 4217 4218 /* 4219 * Make sure the L1 descriptor table is mapped 4220 * with the cache-mode set to write-through. 4221 */ 4222 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4223 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4224 pte = *ptep; 4225 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 4226 *ptep = pte; 4227 PTE_SYNC(ptep); 4228 cpu_tlb_flushD_SE(va); 4229 4230 va += PAGE_SIZE; 4231 m = TAILQ_NEXT(m, pageq); 4232 } 4233 4234 #ifdef DIAGNOSTIC 4235 if (m) 4236 panic("pmap_alloc_l1pt: pglist not empty"); 4237 #endif /* DIAGNOSTIC */ 4238 4239 pmap_init_l1(l1, pl1pt); 4240 } 4241 4242 #ifdef DEBUG 4243 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 4244 needed); 4245 #endif 4246 } 4247 4248 /* 4249 * Note that the following routines are used by board-specific initialisation 4250 * code to configure the initial kernel page tables. 4251 * 4252 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 4253 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 4254 * behaviour of the old pmap, and provides an easy migration path for 4255 * initial bring-up of the new pmap on existing ports. Fortunately, 4256 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 4257 * will be deprecated. 4258 * 4259 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 4260 * tables. 4261 */ 4262 4263 /* 4264 * This list exists for the benefit of pmap_map_chunk(). It keeps track 4265 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 4266 * find them as necessary. 4267 * 4268 * Note that the data on this list MUST remain valid after initarm() returns, 4269 * as pmap_bootstrap() uses it to contruct L2 table metadata. 4270 */ 4271 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 4272 4273 static vaddr_t 4274 kernel_pt_lookup(paddr_t pa) 4275 { 4276 pv_addr_t *pv; 4277 4278 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 4279 #ifndef ARM32_NEW_VM_LAYOUT 4280 if (pv->pv_pa == (pa & ~PGOFSET)) 4281 return (pv->pv_va | (pa & PGOFSET)); 4282 #else 4283 if (pv->pv_pa == pa) 4284 return (pv->pv_va); 4285 #endif 4286 } 4287 return (0); 4288 } 4289 4290 /* 4291 * pmap_map_section: 4292 * 4293 * Create a single section mapping. 4294 */ 4295 void 4296 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 4297 { 4298 pd_entry_t *pde = (pd_entry_t *) l1pt; 4299 pd_entry_t fl; 4300 4301 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 4302 4303 switch (cache) { 4304 case PTE_NOCACHE: 4305 default: 4306 fl = 0; 4307 break; 4308 4309 case PTE_CACHE: 4310 fl = pte_l1_s_cache_mode; 4311 break; 4312 4313 case PTE_PAGETABLE: 4314 fl = pte_l1_s_cache_mode_pt; 4315 break; 4316 } 4317 4318 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4319 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4320 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4321 } 4322 4323 /* 4324 * pmap_map_entry: 4325 * 4326 * Create a single page mapping. 4327 */ 4328 void 4329 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 4330 { 4331 pd_entry_t *pde = (pd_entry_t *) l1pt; 4332 pt_entry_t fl; 4333 pt_entry_t *pte; 4334 4335 KASSERT(((va | pa) & PGOFSET) == 0); 4336 4337 switch (cache) { 4338 case PTE_NOCACHE: 4339 default: 4340 fl = 0; 4341 break; 4342 4343 case PTE_CACHE: 4344 fl = pte_l2_s_cache_mode; 4345 break; 4346 4347 case PTE_PAGETABLE: 4348 fl = pte_l2_s_cache_mode_pt; 4349 break; 4350 } 4351 4352 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4353 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 4354 4355 #ifndef ARM32_NEW_VM_LAYOUT 4356 pte = (pt_entry_t *) 4357 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4358 #else 4359 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4360 #endif 4361 if (pte == NULL) 4362 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 4363 4364 #ifndef ARM32_NEW_VM_LAYOUT 4365 pte[(va >> PGSHIFT) & 0x3ff] = 4366 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4367 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 4368 #else 4369 pte[l2pte_index(va)] = 4370 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4371 PTE_SYNC(&pte[l2pte_index(va)]); 4372 #endif 4373 } 4374 4375 /* 4376 * pmap_link_l2pt: 4377 * 4378 * Link the L2 page table specified by "l2pv" into the L1 4379 * page table at the slot for "va". 4380 */ 4381 void 4382 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 4383 { 4384 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4385 u_int slot = va >> L1_S_SHIFT; 4386 4387 #ifndef ARM32_NEW_VM_LAYOUT 4388 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 4389 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 4390 #endif 4391 4392 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4393 4394 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4395 #ifdef ARM32_NEW_VM_LAYOUT 4396 PTE_SYNC(&pde[slot]); 4397 #else 4398 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 4399 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 4400 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 4401 PTE_SYNC_RANGE(&pde[slot + 0], 4); 4402 #endif 4403 4404 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4405 } 4406 4407 /* 4408 * pmap_map_chunk: 4409 * 4410 * Map a chunk of memory using the most efficient mappings 4411 * possible (section, large page, small page) into the 4412 * provided L1 and L2 tables at the specified virtual address. 4413 */ 4414 vsize_t 4415 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 4416 int prot, int cache) 4417 { 4418 pd_entry_t *pde = (pd_entry_t *) l1pt; 4419 pt_entry_t *pte, f1, f2s, f2l; 4420 vsize_t resid; 4421 int i; 4422 4423 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4424 4425 if (l1pt == 0) 4426 panic("pmap_map_chunk: no L1 table provided"); 4427 4428 #ifdef VERBOSE_INIT_ARM 4429 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 4430 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4431 #endif 4432 4433 switch (cache) { 4434 case PTE_NOCACHE: 4435 default: 4436 f1 = 0; 4437 f2l = 0; 4438 f2s = 0; 4439 break; 4440 4441 case PTE_CACHE: 4442 f1 = pte_l1_s_cache_mode; 4443 f2l = pte_l2_l_cache_mode; 4444 f2s = pte_l2_s_cache_mode; 4445 break; 4446 4447 case PTE_PAGETABLE: 4448 f1 = pte_l1_s_cache_mode_pt; 4449 f2l = pte_l2_l_cache_mode_pt; 4450 f2s = pte_l2_s_cache_mode_pt; 4451 break; 4452 } 4453 4454 size = resid; 4455 4456 while (resid > 0) { 4457 /* See if we can use a section mapping. */ 4458 if (L1_S_MAPPABLE_P(va, pa, resid)) { 4459 #ifdef VERBOSE_INIT_ARM 4460 printf("S"); 4461 #endif 4462 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4463 L1_S_PROT(PTE_KERNEL, prot) | f1 | 4464 L1_S_DOM(PMAP_DOMAIN_KERNEL); 4465 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4466 va += L1_S_SIZE; 4467 pa += L1_S_SIZE; 4468 resid -= L1_S_SIZE; 4469 continue; 4470 } 4471 4472 /* 4473 * Ok, we're going to use an L2 table. Make sure 4474 * one is actually in the corresponding L1 slot 4475 * for the current VA. 4476 */ 4477 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4478 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 4479 4480 #ifndef ARM32_NEW_VM_LAYOUT 4481 pte = (pt_entry_t *) 4482 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4483 #else 4484 pte = (pt_entry_t *) kernel_pt_lookup( 4485 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4486 #endif 4487 if (pte == NULL) 4488 panic("pmap_map_chunk: can't find L2 table for VA" 4489 "0x%08lx", va); 4490 4491 /* See if we can use a L2 large page mapping. */ 4492 if (L2_L_MAPPABLE_P(va, pa, resid)) { 4493 #ifdef VERBOSE_INIT_ARM 4494 printf("L"); 4495 #endif 4496 for (i = 0; i < 16; i++) { 4497 #ifndef ARM32_NEW_VM_LAYOUT 4498 pte[((va >> PGSHIFT) & 0x3f0) + i] = 4499 L2_L_PROTO | pa | 4500 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4501 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 4502 #else 4503 pte[l2pte_index(va) + i] = 4504 L2_L_PROTO | pa | 4505 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4506 PTE_SYNC(&pte[l2pte_index(va) + i]); 4507 #endif 4508 } 4509 va += L2_L_SIZE; 4510 pa += L2_L_SIZE; 4511 resid -= L2_L_SIZE; 4512 continue; 4513 } 4514 4515 /* Use a small page mapping. */ 4516 #ifdef VERBOSE_INIT_ARM 4517 printf("P"); 4518 #endif 4519 #ifndef ARM32_NEW_VM_LAYOUT 4520 pte[(va >> PGSHIFT) & 0x3ff] = 4521 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4522 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 4523 #else 4524 pte[l2pte_index(va)] = 4525 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4526 PTE_SYNC(&pte[l2pte_index(va)]); 4527 #endif 4528 va += PAGE_SIZE; 4529 pa += PAGE_SIZE; 4530 resid -= PAGE_SIZE; 4531 } 4532 #ifdef VERBOSE_INIT_ARM 4533 printf("\n"); 4534 #endif 4535 return (size); 4536 } 4537 4538 /********************** Static device map routines ***************************/ 4539 4540 static const struct pmap_devmap *pmap_devmap_table; 4541 4542 /* 4543 * Register the devmap table. This is provided in case early console 4544 * initialization needs to register mappings created by bootstrap code 4545 * before pmap_devmap_bootstrap() is called. 4546 */ 4547 void 4548 pmap_devmap_register(const struct pmap_devmap *table) 4549 { 4550 4551 pmap_devmap_table = table; 4552 } 4553 4554 /* 4555 * Map all of the static regions in the devmap table, and remember 4556 * the devmap table so other parts of the kernel can look up entries 4557 * later. 4558 */ 4559 void 4560 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 4561 { 4562 int i; 4563 4564 pmap_devmap_table = table; 4565 4566 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4567 #ifdef VERBOSE_INIT_ARM 4568 printf("devmap: %08lx -> %08lx @ %08lx\n", 4569 pmap_devmap_table[i].pd_pa, 4570 pmap_devmap_table[i].pd_pa + 4571 pmap_devmap_table[i].pd_size - 1, 4572 pmap_devmap_table[i].pd_va); 4573 #endif 4574 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4575 pmap_devmap_table[i].pd_pa, 4576 pmap_devmap_table[i].pd_size, 4577 pmap_devmap_table[i].pd_prot, 4578 pmap_devmap_table[i].pd_cache); 4579 } 4580 } 4581 4582 const struct pmap_devmap * 4583 pmap_devmap_find_pa(paddr_t pa, psize_t size) 4584 { 4585 uint64_t endpa; 4586 int i; 4587 4588 if (pmap_devmap_table == NULL) 4589 return (NULL); 4590 4591 endpa = (uint64_t)pa + (uint64_t)(size - 1); 4592 4593 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4594 if (pa >= pmap_devmap_table[i].pd_pa && 4595 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 4596 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 4597 return (&pmap_devmap_table[i]); 4598 } 4599 4600 return (NULL); 4601 } 4602 4603 const struct pmap_devmap * 4604 pmap_devmap_find_va(vaddr_t va, vsize_t size) 4605 { 4606 int i; 4607 4608 if (pmap_devmap_table == NULL) 4609 return (NULL); 4610 4611 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4612 if (va >= pmap_devmap_table[i].pd_va && 4613 va + size - 1 <= pmap_devmap_table[i].pd_va + 4614 pmap_devmap_table[i].pd_size - 1) 4615 return (&pmap_devmap_table[i]); 4616 } 4617 4618 return (NULL); 4619 } 4620 4621 /********************** PTE initialization routines **************************/ 4622 4623 /* 4624 * These routines are called when the CPU type is identified to set up 4625 * the PTE prototypes, cache modes, etc. 4626 * 4627 * The variables are always here, just in case LKMs need to reference 4628 * them (though, they shouldn't). 4629 */ 4630 4631 pt_entry_t pte_l1_s_cache_mode; 4632 pt_entry_t pte_l1_s_cache_mode_pt; 4633 pt_entry_t pte_l1_s_cache_mask; 4634 4635 pt_entry_t pte_l2_l_cache_mode; 4636 pt_entry_t pte_l2_l_cache_mode_pt; 4637 pt_entry_t pte_l2_l_cache_mask; 4638 4639 pt_entry_t pte_l2_s_cache_mode; 4640 pt_entry_t pte_l2_s_cache_mode_pt; 4641 pt_entry_t pte_l2_s_cache_mask; 4642 4643 pt_entry_t pte_l2_s_prot_u; 4644 pt_entry_t pte_l2_s_prot_w; 4645 pt_entry_t pte_l2_s_prot_mask; 4646 4647 pt_entry_t pte_l1_s_proto; 4648 pt_entry_t pte_l1_c_proto; 4649 pt_entry_t pte_l2_s_proto; 4650 4651 void (*pmap_copy_page_func)(paddr_t, paddr_t); 4652 void (*pmap_zero_page_func)(paddr_t); 4653 4654 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 4655 void 4656 pmap_pte_init_generic(void) 4657 { 4658 4659 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 4660 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 4661 4662 pte_l2_l_cache_mode = L2_B|L2_C; 4663 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 4664 4665 pte_l2_s_cache_mode = L2_B|L2_C; 4666 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 4667 4668 /* 4669 * If we have a write-through cache, set B and C. If 4670 * we have a write-back cache, then we assume setting 4671 * only C will make those pages write-through. 4672 */ 4673 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 4674 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 4675 pte_l2_l_cache_mode_pt = L2_B|L2_C; 4676 pte_l2_s_cache_mode_pt = L2_B|L2_C; 4677 } else { 4678 pte_l1_s_cache_mode_pt = L1_S_C; 4679 pte_l2_l_cache_mode_pt = L2_C; 4680 pte_l2_s_cache_mode_pt = L2_C; 4681 } 4682 4683 pte_l2_s_prot_u = L2_S_PROT_U_generic; 4684 pte_l2_s_prot_w = L2_S_PROT_W_generic; 4685 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 4686 4687 pte_l1_s_proto = L1_S_PROTO_generic; 4688 pte_l1_c_proto = L1_C_PROTO_generic; 4689 pte_l2_s_proto = L2_S_PROTO_generic; 4690 4691 pmap_copy_page_func = pmap_copy_page_generic; 4692 pmap_zero_page_func = pmap_zero_page_generic; 4693 } 4694 4695 #if defined(CPU_ARM8) 4696 void 4697 pmap_pte_init_arm8(void) 4698 { 4699 4700 /* 4701 * ARM8 is compatible with generic, but we need to use 4702 * the page tables uncached. 4703 */ 4704 pmap_pte_init_generic(); 4705 4706 pte_l1_s_cache_mode_pt = 0; 4707 pte_l2_l_cache_mode_pt = 0; 4708 pte_l2_s_cache_mode_pt = 0; 4709 } 4710 #endif /* CPU_ARM8 */ 4711 4712 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 4713 void 4714 pmap_pte_init_arm9(void) 4715 { 4716 4717 /* 4718 * ARM9 is compatible with generic, but we want to use 4719 * write-through caching for now. 4720 */ 4721 pmap_pte_init_generic(); 4722 4723 pte_l1_s_cache_mode = L1_S_C; 4724 pte_l2_l_cache_mode = L2_C; 4725 pte_l2_s_cache_mode = L2_C; 4726 4727 pte_l1_s_cache_mode_pt = L1_S_C; 4728 pte_l2_l_cache_mode_pt = L2_C; 4729 pte_l2_s_cache_mode_pt = L2_C; 4730 } 4731 #endif /* CPU_ARM9 */ 4732 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4733 4734 #if defined(CPU_ARM10) 4735 void 4736 pmap_pte_init_arm10(void) 4737 { 4738 4739 /* 4740 * ARM10 is compatible with generic, but we want to use 4741 * write-through caching for now. 4742 */ 4743 pmap_pte_init_generic(); 4744 4745 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 4746 pte_l2_l_cache_mode = L2_B | L2_C; 4747 pte_l2_s_cache_mode = L2_B | L2_C; 4748 4749 pte_l1_s_cache_mode_pt = L1_S_C; 4750 pte_l2_l_cache_mode_pt = L2_C; 4751 pte_l2_s_cache_mode_pt = L2_C; 4752 4753 } 4754 #endif /* CPU_ARM10 */ 4755 4756 #if ARM_MMU_SA1 == 1 4757 void 4758 pmap_pte_init_sa1(void) 4759 { 4760 4761 /* 4762 * The StrongARM SA-1 cache does not have a write-through 4763 * mode. So, do the generic initialization, then reset 4764 * the page table cache mode to B=1,C=1, and note that 4765 * the PTEs need to be sync'd. 4766 */ 4767 pmap_pte_init_generic(); 4768 4769 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 4770 pte_l2_l_cache_mode_pt = L2_B|L2_C; 4771 pte_l2_s_cache_mode_pt = L2_B|L2_C; 4772 4773 pmap_needs_pte_sync = 1; 4774 } 4775 #endif /* ARM_MMU_SA1 == 1*/ 4776 4777 #if ARM_MMU_XSCALE == 1 4778 #if (ARM_NMMUS > 1) 4779 static u_int xscale_use_minidata; 4780 #endif 4781 4782 void 4783 pmap_pte_init_xscale(void) 4784 { 4785 uint32_t auxctl; 4786 int write_through = 0; 4787 4788 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 4789 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 4790 4791 pte_l2_l_cache_mode = L2_B|L2_C; 4792 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 4793 4794 pte_l2_s_cache_mode = L2_B|L2_C; 4795 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 4796 4797 pte_l1_s_cache_mode_pt = L1_S_C; 4798 pte_l2_l_cache_mode_pt = L2_C; 4799 pte_l2_s_cache_mode_pt = L2_C; 4800 4801 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 4802 /* 4803 * The XScale core has an enhanced mode where writes that 4804 * miss the cache cause a cache line to be allocated. This 4805 * is significantly faster than the traditional, write-through 4806 * behavior of this case. 4807 */ 4808 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 4809 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 4810 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 4811 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 4812 4813 #ifdef XSCALE_CACHE_WRITE_THROUGH 4814 /* 4815 * Some versions of the XScale core have various bugs in 4816 * their cache units, the work-around for which is to run 4817 * the cache in write-through mode. Unfortunately, this 4818 * has a major (negative) impact on performance. So, we 4819 * go ahead and run fast-and-loose, in the hopes that we 4820 * don't line up the planets in a way that will trip the 4821 * bugs. 4822 * 4823 * However, we give you the option to be slow-but-correct. 4824 */ 4825 write_through = 1; 4826 #elif defined(XSCALE_CACHE_WRITE_BACK) 4827 /* force write back cache mode */ 4828 write_through = 0; 4829 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 4830 /* 4831 * Intel PXA2[15]0 processors are known to have a bug in 4832 * write-back cache on revision 4 and earlier (stepping 4833 * A[01] and B[012]). Fixed for C0 and later. 4834 */ 4835 { 4836 uint32_t id, type; 4837 4838 id = cpufunc_id(); 4839 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 4840 4841 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 4842 if ((id & CPU_ID_REVISION_MASK) < 5) { 4843 /* write through for stepping A0-1 and B0-2 */ 4844 write_through = 1; 4845 } 4846 } 4847 } 4848 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 4849 4850 if (write_through) { 4851 pte_l1_s_cache_mode = L1_S_C; 4852 pte_l2_l_cache_mode = L2_C; 4853 pte_l2_s_cache_mode = L2_C; 4854 } 4855 4856 #if (ARM_NMMUS > 1) 4857 xscale_use_minidata = 1; 4858 #endif 4859 4860 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 4861 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 4862 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 4863 4864 pte_l1_s_proto = L1_S_PROTO_xscale; 4865 pte_l1_c_proto = L1_C_PROTO_xscale; 4866 pte_l2_s_proto = L2_S_PROTO_xscale; 4867 4868 pmap_copy_page_func = pmap_copy_page_xscale; 4869 pmap_zero_page_func = pmap_zero_page_xscale; 4870 4871 /* 4872 * Disable ECC protection of page table access, for now. 4873 */ 4874 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 4875 auxctl &= ~XSCALE_AUXCTL_P; 4876 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 4877 } 4878 4879 /* 4880 * xscale_setup_minidata: 4881 * 4882 * Set up the mini-data cache clean area. We require the 4883 * caller to allocate the right amount of physically and 4884 * virtually contiguous space. 4885 */ 4886 void 4887 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 4888 { 4889 extern vaddr_t xscale_minidata_clean_addr; 4890 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 4891 pd_entry_t *pde = (pd_entry_t *) l1pt; 4892 pt_entry_t *pte; 4893 vsize_t size; 4894 uint32_t auxctl; 4895 4896 xscale_minidata_clean_addr = va; 4897 4898 /* Round it to page size. */ 4899 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 4900 4901 for (; size != 0; 4902 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 4903 #ifndef ARM32_NEW_VM_LAYOUT 4904 pte = (pt_entry_t *) 4905 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4906 #else 4907 pte = (pt_entry_t *) kernel_pt_lookup( 4908 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4909 #endif 4910 if (pte == NULL) 4911 panic("xscale_setup_minidata: can't find L2 table for " 4912 "VA 0x%08lx", va); 4913 #ifndef ARM32_NEW_VM_LAYOUT 4914 pte[(va >> PGSHIFT) & 0x3ff] = 4915 #else 4916 pte[l2pte_index(va)] = 4917 #endif 4918 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4919 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4920 } 4921 4922 /* 4923 * Configure the mini-data cache for write-back with 4924 * read/write-allocate. 4925 * 4926 * NOTE: In order to reconfigure the mini-data cache, we must 4927 * make sure it contains no valid data! In order to do that, 4928 * we must issue a global data cache invalidate command! 4929 * 4930 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 4931 * THIS IS VERY IMPORTANT! 4932 */ 4933 4934 /* Invalidate data and mini-data. */ 4935 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 4936 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 4937 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 4938 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 4939 } 4940 4941 /* 4942 * Change the PTEs for the specified kernel mappings such that they 4943 * will use the mini data cache instead of the main data cache. 4944 */ 4945 void 4946 pmap_uarea(vaddr_t va) 4947 { 4948 struct l2_bucket *l2b; 4949 pt_entry_t *ptep, *sptep, pte; 4950 vaddr_t next_bucket, eva; 4951 4952 #if (ARM_NMMUS > 1) 4953 if (xscale_use_minidata == 0) 4954 return; 4955 #endif 4956 4957 eva = va + USPACE; 4958 4959 while (va < eva) { 4960 next_bucket = L2_NEXT_BUCKET(va); 4961 if (next_bucket > eva) 4962 next_bucket = eva; 4963 4964 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4965 KDASSERT(l2b != NULL); 4966 4967 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4968 4969 while (va < next_bucket) { 4970 pte = *ptep; 4971 if (!l2pte_minidata(pte)) { 4972 cpu_dcache_wbinv_range(va, PAGE_SIZE); 4973 cpu_tlb_flushD_SE(va); 4974 *ptep = pte & ~L2_B; 4975 } 4976 ptep++; 4977 va += PAGE_SIZE; 4978 } 4979 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4980 } 4981 cpu_cpwait(); 4982 } 4983 #endif /* ARM_MMU_XSCALE == 1 */ 4984 4985 /* 4986 * return the PA of the current L1 table, for use when handling a crash dump 4987 */ 4988 uint32_t pmap_kernel_L1_addr() 4989 { 4990 return pmap_kernel()->pm_l1->l1_physaddr; 4991 } 4992 4993 #if defined(DDB) 4994 /* 4995 * A couple of ddb-callable functions for dumping pmaps 4996 */ 4997 void pmap_dump_all(void); 4998 void pmap_dump(pmap_t); 4999 5000 void 5001 pmap_dump_all(void) 5002 { 5003 pmap_t pm; 5004 5005 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 5006 if (pm == pmap_kernel()) 5007 continue; 5008 pmap_dump(pm); 5009 printf("\n"); 5010 } 5011 } 5012 5013 static pt_entry_t ncptes[64]; 5014 static void pmap_dump_ncpg(pmap_t); 5015 5016 void 5017 pmap_dump(pmap_t pm) 5018 { 5019 struct l2_dtable *l2; 5020 struct l2_bucket *l2b; 5021 pt_entry_t *ptep, pte; 5022 vaddr_t l2_va, l2b_va, va; 5023 int i, j, k, occ, rows = 0; 5024 5025 if (pm == pmap_kernel()) 5026 printf("pmap_kernel (%p): ", pm); 5027 else 5028 printf("user pmap (%p): ", pm); 5029 5030 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 5031 5032 l2_va = 0; 5033 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 5034 l2 = pm->pm_l2[i]; 5035 5036 if (l2 == NULL || l2->l2_occupancy == 0) 5037 continue; 5038 5039 l2b_va = l2_va; 5040 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 5041 l2b = &l2->l2_bucket[j]; 5042 5043 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 5044 continue; 5045 5046 ptep = l2b->l2b_kva; 5047 5048 for (k = 0; k < 256 && ptep[k] == 0; k++) 5049 ; 5050 5051 k &= ~63; 5052 occ = l2b->l2b_occupancy; 5053 va = l2b_va + (k * 4096); 5054 for (; k < 256; k++, va += 0x1000) { 5055 char ch = ' '; 5056 if ((k % 64) == 0) { 5057 if ((rows % 8) == 0) { 5058 printf( 5059 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 5060 } 5061 printf("%08lx: ", va); 5062 } 5063 5064 ncptes[k & 63] = 0; 5065 pte = ptep[k]; 5066 if (pte == 0) { 5067 ch = '.'; 5068 } else { 5069 occ--; 5070 switch (pte & 0x0c) { 5071 case 0x00: 5072 ch = 'D'; /* No cache No buff */ 5073 break; 5074 case 0x04: 5075 ch = 'B'; /* No cache buff */ 5076 break; 5077 case 0x08: 5078 if (pte & 0x40) 5079 ch = 'm'; 5080 else 5081 ch = 'C'; /* Cache No buff */ 5082 break; 5083 case 0x0c: 5084 ch = 'F'; /* Cache Buff */ 5085 break; 5086 } 5087 5088 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 5089 ch += 0x20; 5090 5091 if ((pte & 0xc) == 0) 5092 ncptes[k & 63] = pte; 5093 } 5094 5095 if ((k % 64) == 63) { 5096 rows++; 5097 printf("%c\n", ch); 5098 pmap_dump_ncpg(pm); 5099 if (occ == 0) 5100 break; 5101 } else 5102 printf("%c", ch); 5103 } 5104 } 5105 } 5106 } 5107 5108 static void 5109 pmap_dump_ncpg(pmap_t pm) 5110 { 5111 struct vm_page *pg; 5112 struct pv_entry *pv; 5113 int i; 5114 5115 for (i = 0; i < 63; i++) { 5116 if (ncptes[i] == 0) 5117 continue; 5118 5119 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 5120 if (pg == NULL) 5121 continue; 5122 5123 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 5124 VM_PAGE_TO_PHYS(pg), 5125 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 5126 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 5127 5128 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 5129 printf(" %c va 0x%08lx, flags 0x%x\n", 5130 (pm == pv->pv_pmap) ? '*' : ' ', 5131 pv->pv_va, pv->pv_flags); 5132 } 5133 } 5134 } 5135 #endif 5136
Indexes created Fri Sep 26 20:09:58 GMT 2025