pmap.c revision 1.179
1 /* $NetBSD: pmap.c,v 1.179 2008/07/03 06:13:41 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/user.h> 202 #include <sys/pool.h> 203 #include <sys/cdefs.h> 204 #include <sys/cpu.h> 205 206 #include <uvm/uvm.h> 207 208 #include <machine/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.179 2008/07/03 06:13:41 matt Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 struct pmap kernel_pmap_store; 258 259 /* 260 * Which pmap is currently 'live' in the cache 261 * 262 * XXXSCW: Fix for SMP ... 263 */ 264 static pmap_t pmap_recent_user; 265 266 /* 267 * Pointer to last active lwp, or NULL if it exited. 268 */ 269 struct lwp *pmap_previous_active_lwp; 270 271 /* 272 * Pool and cache that pmap structures are allocated from. 273 * We use a cache to avoid clearing the pm_l2[] array (1KB) 274 * in pmap_create(). 275 */ 276 static struct pool_cache pmap_cache; 277 static LIST_HEAD(, pmap) pmap_pmaps; 278 279 /* 280 * Pool of PV structures 281 */ 282 static struct pool pmap_pv_pool; 283 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 284 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 285 static struct pool_allocator pmap_bootstrap_pv_allocator = { 286 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 287 }; 288 289 /* 290 * Pool and cache of l2_dtable structures. 291 * We use a cache to avoid clearing the structures when they're 292 * allocated. (196 bytes) 293 */ 294 static struct pool_cache pmap_l2dtable_cache; 295 static vaddr_t pmap_kernel_l2dtable_kva; 296 297 /* 298 * Pool and cache of L2 page descriptors. 299 * We use a cache to avoid clearing the descriptor table 300 * when they're allocated. (1KB) 301 */ 302 static struct pool_cache pmap_l2ptp_cache; 303 static vaddr_t pmap_kernel_l2ptp_kva; 304 static paddr_t pmap_kernel_l2ptp_phys; 305 306 #ifdef PMAPCOUNT 307 #define PMAP_EVCNT_INITIALIZER(name) \ 308 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 309 310 #ifdef PMAP_CACHE_VIPT 311 static struct evcnt pmap_ev_vac_color_new = 312 PMAP_EVCNT_INITIALIZER("new page color"); 313 static struct evcnt pmap_ev_vac_color_reuse = 314 PMAP_EVCNT_INITIALIZER("ok first page color"); 315 static struct evcnt pmap_ev_vac_color_ok = 316 PMAP_EVCNT_INITIALIZER("ok page color"); 317 static struct evcnt pmap_ev_vac_color_change = 318 PMAP_EVCNT_INITIALIZER("change page color"); 319 static struct evcnt pmap_ev_vac_color_erase = 320 PMAP_EVCNT_INITIALIZER("erase page color"); 321 static struct evcnt pmap_ev_vac_color_none = 322 PMAP_EVCNT_INITIALIZER("no page color"); 323 static struct evcnt pmap_ev_vac_color_restore = 324 PMAP_EVCNT_INITIALIZER("restore page color"); 325 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 329 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 330 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 331 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 332 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 333 #endif 334 335 static struct evcnt pmap_ev_mappings = 336 PMAP_EVCNT_INITIALIZER("pages mapped"); 337 static struct evcnt pmap_ev_unmappings = 338 PMAP_EVCNT_INITIALIZER("pages unmapped"); 339 static struct evcnt pmap_ev_remappings = 340 PMAP_EVCNT_INITIALIZER("pages remapped"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 343 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 344 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 345 346 static struct evcnt pmap_ev_kernel_mappings = 347 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 348 static struct evcnt pmap_ev_kernel_unmappings = 349 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 350 static struct evcnt pmap_ev_kernel_remappings = 351 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 352 353 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 354 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 355 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 356 357 static struct evcnt pmap_ev_kenter_mappings = 358 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 359 static struct evcnt pmap_ev_kenter_unmappings = 360 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 361 static struct evcnt pmap_ev_kenter_remappings = 362 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 363 static struct evcnt pmap_ev_pt_mappings = 364 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 365 366 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 367 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 368 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 369 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 370 371 #ifdef PMAP_CACHE_VIPT 372 static struct evcnt pmap_ev_exec_mappings = 373 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 374 static struct evcnt pmap_ev_exec_cached = 375 PMAP_EVCNT_INITIALIZER("exec pages cached"); 376 377 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 378 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 379 380 static struct evcnt pmap_ev_exec_synced = 381 PMAP_EVCNT_INITIALIZER("exec pages synced"); 382 static struct evcnt pmap_ev_exec_synced_map = 383 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 384 static struct evcnt pmap_ev_exec_synced_unmap = 385 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 386 static struct evcnt pmap_ev_exec_synced_remap = 387 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 388 static struct evcnt pmap_ev_exec_synced_clearbit = 389 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 390 static struct evcnt pmap_ev_exec_synced_kremove = 391 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 392 393 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 394 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 397 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 399 400 static struct evcnt pmap_ev_exec_discarded_unmap = 401 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 402 static struct evcnt pmap_ev_exec_discarded_zero = 403 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 404 static struct evcnt pmap_ev_exec_discarded_copy = 405 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 406 static struct evcnt pmap_ev_exec_discarded_page_protect = 407 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 408 static struct evcnt pmap_ev_exec_discarded_clearbit = 409 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 410 static struct evcnt pmap_ev_exec_discarded_kremove = 411 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 412 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 419 #endif /* PMAP_CACHE_VIPT */ 420 421 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 422 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 423 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 424 425 EVCNT_ATTACH_STATIC(pmap_ev_updates); 426 EVCNT_ATTACH_STATIC(pmap_ev_collects); 427 EVCNT_ATTACH_STATIC(pmap_ev_activations); 428 429 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 430 #else 431 #define PMAPCOUNT(x) ((void)0) 432 #endif 433 434 /* 435 * pmap copy/zero page, and mem(5) hook point 436 */ 437 static pt_entry_t *csrc_pte, *cdst_pte; 438 static vaddr_t csrcp, cdstp; 439 vaddr_t memhook; 440 extern void *msgbufaddr; 441 442 /* 443 * Flag to indicate if pmap_init() has done its thing 444 */ 445 bool pmap_initialized; 446 447 /* 448 * Misc. locking data structures 449 */ 450 451 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 452 static struct lock pmap_main_lock; 453 454 #define PMAP_MAP_TO_HEAD_LOCK() \ 455 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 456 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 457 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 458 #define PMAP_HEAD_TO_MAP_LOCK() \ 459 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 460 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 461 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 462 #else 463 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 464 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 465 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 466 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 467 #endif 468 469 #define pmap_acquire_pmap_lock(pm) \ 470 do { \ 471 if ((pm) != pmap_kernel()) \ 472 mutex_enter(&(pm)->pm_lock); \ 473 } while (/*CONSTCOND*/0) 474 475 #define pmap_release_pmap_lock(pm) \ 476 do { \ 477 if ((pm) != pmap_kernel()) \ 478 mutex_exit(&(pm)->pm_lock); \ 479 } while (/*CONSTCOND*/0) 480 481 482 /* 483 * Metadata for L1 translation tables. 484 */ 485 struct l1_ttable { 486 /* Entry on the L1 Table list */ 487 SLIST_ENTRY(l1_ttable) l1_link; 488 489 /* Entry on the L1 Least Recently Used list */ 490 TAILQ_ENTRY(l1_ttable) l1_lru; 491 492 /* Track how many domains are allocated from this L1 */ 493 volatile u_int l1_domain_use_count; 494 495 /* 496 * A free-list of domain numbers for this L1. 497 * We avoid using ffs() and a bitmap to track domains since ffs() 498 * is slow on ARM. 499 */ 500 u_int8_t l1_domain_first; 501 u_int8_t l1_domain_free[PMAP_DOMAINS]; 502 503 /* Physical address of this L1 page table */ 504 paddr_t l1_physaddr; 505 506 /* KVA of this L1 page table */ 507 pd_entry_t *l1_kva; 508 }; 509 510 /* 511 * Convert a virtual address into its L1 table index. That is, the 512 * index used to locate the L2 descriptor table pointer in an L1 table. 513 * This is basically used to index l1->l1_kva[]. 514 * 515 * Each L2 descriptor table represents 1MB of VA space. 516 */ 517 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 518 519 /* 520 * L1 Page Tables are tracked using a Least Recently Used list. 521 * - New L1s are allocated from the HEAD. 522 * - Freed L1s are added to the TAIl. 523 * - Recently accessed L1s (where an 'access' is some change to one of 524 * the userland pmaps which owns this L1) are moved to the TAIL. 525 */ 526 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 527 static struct simplelock l1_lru_lock; 528 529 /* 530 * A list of all L1 tables 531 */ 532 static SLIST_HEAD(, l1_ttable) l1_list; 533 534 /* 535 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 536 * 537 * This is normally 16MB worth L2 page descriptors for any given pmap. 538 * Reference counts are maintained for L2 descriptors so they can be 539 * freed when empty. 540 */ 541 struct l2_dtable { 542 /* The number of L2 page descriptors allocated to this l2_dtable */ 543 u_int l2_occupancy; 544 545 /* List of L2 page descriptors */ 546 struct l2_bucket { 547 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 548 paddr_t l2b_phys; /* Physical address of same */ 549 u_short l2b_l1idx; /* This L2 table's L1 index */ 550 u_short l2b_occupancy; /* How many active descriptors */ 551 } l2_bucket[L2_BUCKET_SIZE]; 552 }; 553 554 /* 555 * Given an L1 table index, calculate the corresponding l2_dtable index 556 * and bucket index within the l2_dtable. 557 */ 558 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 559 (L2_SIZE - 1)) 560 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 561 562 /* 563 * Given a virtual address, this macro returns the 564 * virtual address required to drop into the next L2 bucket. 565 */ 566 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 567 568 /* 569 * L2 allocation. 570 */ 571 #define pmap_alloc_l2_dtable() \ 572 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 573 #define pmap_free_l2_dtable(l2) \ 574 pool_cache_put(&pmap_l2dtable_cache, (l2)) 575 #define pmap_alloc_l2_ptp(pap) \ 576 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 577 PR_NOWAIT, (pap))) 578 579 /* 580 * We try to map the page tables write-through, if possible. However, not 581 * all CPUs have a write-through cache mode, so on those we have to sync 582 * the cache when we frob page tables. 583 * 584 * We try to evaluate this at compile time, if possible. However, it's 585 * not always possible to do that, hence this run-time var. 586 */ 587 int pmap_needs_pte_sync; 588 589 /* 590 * Real definition of pv_entry. 591 */ 592 struct pv_entry { 593 struct pv_entry *pv_next; /* next pv_entry */ 594 pmap_t pv_pmap; /* pmap where mapping lies */ 595 vaddr_t pv_va; /* virtual address for mapping */ 596 u_int pv_flags; /* flags */ 597 }; 598 599 /* 600 * Macro to determine if a mapping might be resident in the 601 * instruction cache and/or TLB 602 */ 603 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 604 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 605 606 /* 607 * Macro to determine if a mapping might be resident in the 608 * data cache and/or TLB 609 */ 610 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 611 612 /* 613 * Local prototypes 614 */ 615 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 616 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 617 pt_entry_t **); 618 static bool pmap_is_current(pmap_t); 619 static bool pmap_is_cached(pmap_t); 620 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 621 pmap_t, vaddr_t, u_int); 622 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 623 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 624 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 625 u_int, u_int); 626 627 static void pmap_pinit(pmap_t); 628 static int pmap_pmap_ctor(void *, void *, int); 629 630 static void pmap_alloc_l1(pmap_t); 631 static void pmap_free_l1(pmap_t); 632 static void pmap_use_l1(pmap_t); 633 634 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 635 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 636 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 637 static int pmap_l2ptp_ctor(void *, void *, int); 638 static int pmap_l2dtable_ctor(void *, void *, int); 639 640 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 641 #ifdef PMAP_CACHE_VIVT 642 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 643 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 644 #endif 645 646 static void pmap_clearbit(struct vm_page *, u_int); 647 #ifdef PMAP_CACHE_VIVT 648 static int pmap_clean_page(struct pv_entry *, bool); 649 #endif 650 #ifdef PMAP_CACHE_VIPT 651 static void pmap_syncicache_page(struct vm_page *); 652 static void pmap_flush_page(struct vm_page *); 653 #endif 654 static void pmap_page_remove(struct vm_page *); 655 656 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 657 static vaddr_t kernel_pt_lookup(paddr_t); 658 659 660 /* 661 * External function prototypes 662 */ 663 extern void bzero_page(vaddr_t); 664 extern void bcopy_page(vaddr_t, vaddr_t); 665 666 /* 667 * Misc variables 668 */ 669 vaddr_t virtual_avail; 670 vaddr_t virtual_end; 671 vaddr_t pmap_curmaxkvaddr; 672 673 vaddr_t avail_start; 674 vaddr_t avail_end; 675 676 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 677 pv_addr_t kernelpages; 678 pv_addr_t kernel_l1pt; 679 pv_addr_t systempage; 680 681 /* Function to set the debug level of the pmap code */ 682 683 #ifdef PMAP_DEBUG 684 void 685 pmap_debug(int level) 686 { 687 pmap_debug_level = level; 688 printf("pmap_debug: level=%d\n", pmap_debug_level); 689 } 690 #endif /* PMAP_DEBUG */ 691 692 /* 693 * A bunch of routines to conditionally flush the caches/TLB depending 694 * on whether the specified pmap actually needs to be flushed at any 695 * given time. 696 */ 697 static inline void 698 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 699 { 700 701 if (pm->pm_cstate.cs_tlb_id) 702 cpu_tlb_flushID_SE(va); 703 } 704 705 static inline void 706 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 707 { 708 709 if (pm->pm_cstate.cs_tlb_d) 710 cpu_tlb_flushD_SE(va); 711 } 712 713 static inline void 714 pmap_tlb_flushID(pmap_t pm) 715 { 716 717 if (pm->pm_cstate.cs_tlb_id) { 718 cpu_tlb_flushID(); 719 pm->pm_cstate.cs_tlb = 0; 720 } 721 } 722 723 static inline void 724 pmap_tlb_flushD(pmap_t pm) 725 { 726 727 if (pm->pm_cstate.cs_tlb_d) { 728 cpu_tlb_flushD(); 729 pm->pm_cstate.cs_tlb_d = 0; 730 } 731 } 732 733 #ifdef PMAP_CACHE_VIVT 734 static inline void 735 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 736 { 737 if (pm->pm_cstate.cs_cache_id) { 738 cpu_idcache_wbinv_range(va, len); 739 } 740 } 741 742 static inline void 743 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 744 bool do_inv, bool rd_only) 745 { 746 747 if (pm->pm_cstate.cs_cache_d) { 748 if (do_inv) { 749 if (rd_only) 750 cpu_dcache_inv_range(va, len); 751 else 752 cpu_dcache_wbinv_range(va, len); 753 } else 754 if (!rd_only) 755 cpu_dcache_wb_range(va, len); 756 } 757 } 758 759 static inline void 760 pmap_idcache_wbinv_all(pmap_t pm) 761 { 762 if (pm->pm_cstate.cs_cache_id) { 763 cpu_idcache_wbinv_all(); 764 pm->pm_cstate.cs_cache = 0; 765 } 766 } 767 768 static inline void 769 pmap_dcache_wbinv_all(pmap_t pm) 770 { 771 if (pm->pm_cstate.cs_cache_d) { 772 cpu_dcache_wbinv_all(); 773 pm->pm_cstate.cs_cache_d = 0; 774 } 775 } 776 #endif /* PMAP_CACHE_VIVT */ 777 778 static inline bool 779 pmap_is_current(pmap_t pm) 780 { 781 782 if (pm == pmap_kernel() || 783 (curproc && curproc->p_vmspace->vm_map.pmap == pm)) 784 return true; 785 786 return false; 787 } 788 789 static inline bool 790 pmap_is_cached(pmap_t pm) 791 { 792 793 if (pm == pmap_kernel() || pmap_recent_user == NULL || 794 pmap_recent_user == pm) 795 return (true); 796 797 return false; 798 } 799 800 /* 801 * PTE_SYNC_CURRENT: 802 * 803 * Make sure the pte is written out to RAM. 804 * We need to do this for one of two cases: 805 * - We're dealing with the kernel pmap 806 * - There is no pmap active in the cache/tlb. 807 * - The specified pmap is 'active' in the cache/tlb. 808 */ 809 #ifdef PMAP_INCLUDE_PTE_SYNC 810 #define PTE_SYNC_CURRENT(pm, ptep) \ 811 do { \ 812 if (PMAP_NEEDS_PTE_SYNC && \ 813 pmap_is_cached(pm)) \ 814 PTE_SYNC(ptep); \ 815 } while (/*CONSTCOND*/0) 816 #else 817 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 818 #endif 819 820 /* 821 * main pv_entry manipulation functions: 822 * pmap_enter_pv: enter a mapping onto a vm_page list 823 * pmap_remove_pv: remove a mappiing from a vm_page list 824 * 825 * NOTE: pmap_enter_pv expects to lock the pvh itself 826 * pmap_remove_pv expects te caller to lock the pvh before calling 827 */ 828 829 /* 830 * pmap_enter_pv: enter a mapping onto a vm_page lst 831 * 832 * => caller should hold the proper lock on pmap_main_lock 833 * => caller should have pmap locked 834 * => we will gain the lock on the vm_page and allocate the new pv_entry 835 * => caller should adjust ptp's wire_count before calling 836 * => caller should not adjust pmap's wire_count 837 */ 838 static void 839 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 840 vaddr_t va, u_int flags) 841 { 842 843 NPDEBUG(PDB_PVDUMP, 844 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 845 846 pve->pv_pmap = pm; 847 pve->pv_va = va; 848 pve->pv_flags = flags; 849 850 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 851 pve->pv_next = pg->mdpage.pvh_list; /* add to ... */ 852 pg->mdpage.pvh_list = pve; /* ... locked list */ 853 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 854 if (pm == pmap_kernel()) { 855 PMAPCOUNT(kernel_mappings); 856 if (flags & PVF_WRITE) 857 pg->mdpage.krw_mappings++; 858 else 859 pg->mdpage.kro_mappings++; 860 } else 861 if (flags & PVF_WRITE) 862 pg->mdpage.urw_mappings++; 863 else 864 pg->mdpage.uro_mappings++; 865 866 #ifdef PMAP_CACHE_VIPT 867 /* 868 * If this is an exec mapping and its the first exec mapping 869 * for this page, make sure to sync the I-cache. 870 */ 871 if (PV_IS_EXEC_P(flags)) { 872 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 873 pmap_syncicache_page(pg); 874 PMAPCOUNT(exec_synced_map); 875 } 876 PMAPCOUNT(exec_mappings); 877 } 878 #endif 879 880 PMAPCOUNT(mappings); 881 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 882 883 if (pve->pv_flags & PVF_WIRED) 884 ++pm->pm_stats.wired_count; 885 } 886 887 /* 888 * 889 * pmap_find_pv: Find a pv entry 890 * 891 * => caller should hold lock on vm_page 892 */ 893 static inline struct pv_entry * 894 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 895 { 896 struct pv_entry *pv; 897 898 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 899 if (pm == pv->pv_pmap && va == pv->pv_va) 900 break; 901 } 902 903 return (pv); 904 } 905 906 /* 907 * pmap_remove_pv: try to remove a mapping from a pv_list 908 * 909 * => caller should hold proper lock on pmap_main_lock 910 * => pmap should be locked 911 * => caller should hold lock on vm_page [so that attrs can be adjusted] 912 * => caller should adjust ptp's wire_count and free PTP if needed 913 * => caller should NOT adjust pmap's wire_count 914 * => we return the removed pve 915 */ 916 static struct pv_entry * 917 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 918 { 919 struct pv_entry *pve, **prevptr; 920 921 NPDEBUG(PDB_PVDUMP, 922 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 923 924 prevptr = &pg->mdpage.pvh_list; /* previous pv_entry pointer */ 925 pve = *prevptr; 926 927 while (pve) { 928 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 929 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 930 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 931 if (pve->pv_flags & PVF_WIRED) { 932 if (skip_wired) 933 return (NULL); 934 --pm->pm_stats.wired_count; 935 } 936 *prevptr = pve->pv_next; /* remove it! */ 937 if (pm == pmap_kernel()) { 938 PMAPCOUNT(kernel_unmappings); 939 if (pve->pv_flags & PVF_WRITE) 940 pg->mdpage.krw_mappings--; 941 else 942 pg->mdpage.kro_mappings--; 943 } else 944 if (pve->pv_flags & PVF_WRITE) 945 pg->mdpage.urw_mappings--; 946 else 947 pg->mdpage.uro_mappings--; 948 949 PMAPCOUNT(unmappings); 950 #ifdef PMAP_CACHE_VIPT 951 if (!(pve->pv_flags & PVF_WRITE)) 952 break; 953 /* 954 * If this page has had an exec mapping, then if 955 * this was the last mapping, discard the contents, 956 * otherwise sync the i-cache for this page. 957 */ 958 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 959 if (pg->mdpage.pvh_list == NULL) { 960 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 961 PMAPCOUNT(exec_discarded_unmap); 962 } else { 963 pmap_syncicache_page(pg); 964 PMAPCOUNT(exec_synced_unmap); 965 } 966 } 967 #endif /* PMAP_CACHE_VIPT */ 968 break; 969 } 970 prevptr = &pve->pv_next; /* previous pointer */ 971 pve = pve->pv_next; /* advance */ 972 } 973 974 return(pve); /* return removed pve */ 975 } 976 977 /* 978 * 979 * pmap_modify_pv: Update pv flags 980 * 981 * => caller should hold lock on vm_page [so that attrs can be adjusted] 982 * => caller should NOT adjust pmap's wire_count 983 * => caller must call pmap_vac_me_harder() if writable status of a page 984 * may have changed. 985 * => we return the old flags 986 * 987 * Modify a physical-virtual mapping in the pv table 988 */ 989 static u_int 990 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 991 u_int clr_mask, u_int set_mask) 992 { 993 struct pv_entry *npv; 994 u_int flags, oflags; 995 996 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 997 return (0); 998 999 NPDEBUG(PDB_PVDUMP, 1000 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 1001 1002 /* 1003 * There is at least one VA mapping this page. 1004 */ 1005 1006 if (clr_mask & (PVF_REF | PVF_MOD)) 1007 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1008 1009 oflags = npv->pv_flags; 1010 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1011 1012 if ((flags ^ oflags) & PVF_WIRED) { 1013 if (flags & PVF_WIRED) 1014 ++pm->pm_stats.wired_count; 1015 else 1016 --pm->pm_stats.wired_count; 1017 } 1018 1019 if ((flags ^ oflags) & PVF_WRITE) { 1020 if (pm == pmap_kernel()) { 1021 if (flags & PVF_WRITE) { 1022 pg->mdpage.krw_mappings++; 1023 pg->mdpage.kro_mappings--; 1024 } else { 1025 pg->mdpage.kro_mappings++; 1026 pg->mdpage.krw_mappings--; 1027 } 1028 } else 1029 if (flags & PVF_WRITE) { 1030 pg->mdpage.urw_mappings++; 1031 pg->mdpage.uro_mappings--; 1032 } else { 1033 pg->mdpage.uro_mappings++; 1034 pg->mdpage.urw_mappings--; 1035 } 1036 } 1037 #ifdef PMAP_CACHE_VIPT 1038 /* 1039 * We have two cases here: the first is from enter_pv (new exec 1040 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1041 * Since in latter, pmap_enter_pv won't do anything, we just have 1042 * to do what pmap_remove_pv would do. 1043 */ 1044 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1045 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1046 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1047 pmap_syncicache_page(pg); 1048 PMAPCOUNT(exec_synced_remap); 1049 } 1050 #endif 1051 1052 PMAPCOUNT(remappings); 1053 1054 return (oflags); 1055 } 1056 1057 /* 1058 * Allocate an L1 translation table for the specified pmap. 1059 * This is called at pmap creation time. 1060 */ 1061 static void 1062 pmap_alloc_l1(pmap_t pm) 1063 { 1064 struct l1_ttable *l1; 1065 u_int8_t domain; 1066 1067 /* 1068 * Remove the L1 at the head of the LRU list 1069 */ 1070 simple_lock(&l1_lru_lock); 1071 l1 = TAILQ_FIRST(&l1_lru_list); 1072 KDASSERT(l1 != NULL); 1073 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1074 1075 /* 1076 * Pick the first available domain number, and update 1077 * the link to the next number. 1078 */ 1079 domain = l1->l1_domain_first; 1080 l1->l1_domain_first = l1->l1_domain_free[domain]; 1081 1082 /* 1083 * If there are still free domain numbers in this L1, 1084 * put it back on the TAIL of the LRU list. 1085 */ 1086 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1087 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1088 1089 simple_unlock(&l1_lru_lock); 1090 1091 /* 1092 * Fix up the relevant bits in the pmap structure 1093 */ 1094 pm->pm_l1 = l1; 1095 pm->pm_domain = domain; 1096 } 1097 1098 /* 1099 * Free an L1 translation table. 1100 * This is called at pmap destruction time. 1101 */ 1102 static void 1103 pmap_free_l1(pmap_t pm) 1104 { 1105 struct l1_ttable *l1 = pm->pm_l1; 1106 1107 simple_lock(&l1_lru_lock); 1108 1109 /* 1110 * If this L1 is currently on the LRU list, remove it. 1111 */ 1112 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1113 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1114 1115 /* 1116 * Free up the domain number which was allocated to the pmap 1117 */ 1118 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1119 l1->l1_domain_first = pm->pm_domain; 1120 l1->l1_domain_use_count--; 1121 1122 /* 1123 * The L1 now must have at least 1 free domain, so add 1124 * it back to the LRU list. If the use count is zero, 1125 * put it at the head of the list, otherwise it goes 1126 * to the tail. 1127 */ 1128 if (l1->l1_domain_use_count == 0) 1129 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1130 else 1131 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1132 1133 simple_unlock(&l1_lru_lock); 1134 } 1135 1136 static inline void 1137 pmap_use_l1(pmap_t pm) 1138 { 1139 struct l1_ttable *l1; 1140 1141 /* 1142 * Do nothing if we're in interrupt context. 1143 * Access to an L1 by the kernel pmap must not affect 1144 * the LRU list. 1145 */ 1146 if (cpu_intr_p() || pm == pmap_kernel()) 1147 return; 1148 1149 l1 = pm->pm_l1; 1150 1151 /* 1152 * If the L1 is not currently on the LRU list, just return 1153 */ 1154 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1155 return; 1156 1157 simple_lock(&l1_lru_lock); 1158 1159 /* 1160 * Check the use count again, now that we've acquired the lock 1161 */ 1162 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1163 simple_unlock(&l1_lru_lock); 1164 return; 1165 } 1166 1167 /* 1168 * Move the L1 to the back of the LRU list 1169 */ 1170 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1171 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1172 1173 simple_unlock(&l1_lru_lock); 1174 } 1175 1176 /* 1177 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1178 * 1179 * Free an L2 descriptor table. 1180 */ 1181 static inline void 1182 #ifndef PMAP_INCLUDE_PTE_SYNC 1183 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1184 #else 1185 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1186 #endif 1187 { 1188 #ifdef PMAP_INCLUDE_PTE_SYNC 1189 #ifdef PMAP_CACHE_VIVT 1190 /* 1191 * Note: With a write-back cache, we may need to sync this 1192 * L2 table before re-using it. 1193 * This is because it may have belonged to a non-current 1194 * pmap, in which case the cache syncs would have been 1195 * skipped for the pages that were being unmapped. If the 1196 * L2 table were then to be immediately re-allocated to 1197 * the *current* pmap, it may well contain stale mappings 1198 * which have not yet been cleared by a cache write-back 1199 * and so would still be visible to the mmu. 1200 */ 1201 if (need_sync) 1202 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1203 #endif /* PMAP_CACHE_VIVT */ 1204 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1205 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1206 } 1207 1208 /* 1209 * Returns a pointer to the L2 bucket associated with the specified pmap 1210 * and VA, or NULL if no L2 bucket exists for the address. 1211 */ 1212 static inline struct l2_bucket * 1213 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1214 { 1215 struct l2_dtable *l2; 1216 struct l2_bucket *l2b; 1217 u_short l1idx; 1218 1219 l1idx = L1_IDX(va); 1220 1221 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1222 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1223 return (NULL); 1224 1225 return (l2b); 1226 } 1227 1228 /* 1229 * Returns a pointer to the L2 bucket associated with the specified pmap 1230 * and VA. 1231 * 1232 * If no L2 bucket exists, perform the necessary allocations to put an L2 1233 * bucket/page table in place. 1234 * 1235 * Note that if a new L2 bucket/page was allocated, the caller *must* 1236 * increment the bucket occupancy counter appropriately *before* 1237 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1238 * the bucket/page in the meantime. 1239 */ 1240 static struct l2_bucket * 1241 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1242 { 1243 struct l2_dtable *l2; 1244 struct l2_bucket *l2b; 1245 u_short l1idx; 1246 1247 l1idx = L1_IDX(va); 1248 1249 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1250 /* 1251 * No mapping at this address, as there is 1252 * no entry in the L1 table. 1253 * Need to allocate a new l2_dtable. 1254 */ 1255 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1256 return (NULL); 1257 1258 /* 1259 * Link it into the parent pmap 1260 */ 1261 pm->pm_l2[L2_IDX(l1idx)] = l2; 1262 } 1263 1264 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1265 1266 /* 1267 * Fetch pointer to the L2 page table associated with the address. 1268 */ 1269 if (l2b->l2b_kva == NULL) { 1270 pt_entry_t *ptep; 1271 1272 /* 1273 * No L2 page table has been allocated. Chances are, this 1274 * is because we just allocated the l2_dtable, above. 1275 */ 1276 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1277 /* 1278 * Oops, no more L2 page tables available at this 1279 * time. We may need to deallocate the l2_dtable 1280 * if we allocated a new one above. 1281 */ 1282 if (l2->l2_occupancy == 0) { 1283 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1284 pmap_free_l2_dtable(l2); 1285 } 1286 return (NULL); 1287 } 1288 1289 l2->l2_occupancy++; 1290 l2b->l2b_kva = ptep; 1291 l2b->l2b_l1idx = l1idx; 1292 } 1293 1294 return (l2b); 1295 } 1296 1297 /* 1298 * One or more mappings in the specified L2 descriptor table have just been 1299 * invalidated. 1300 * 1301 * Garbage collect the metadata and descriptor table itself if necessary. 1302 * 1303 * The pmap lock must be acquired when this is called (not necessary 1304 * for the kernel pmap). 1305 */ 1306 static void 1307 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1308 { 1309 struct l2_dtable *l2; 1310 pd_entry_t *pl1pd, l1pd; 1311 pt_entry_t *ptep; 1312 u_short l1idx; 1313 1314 KDASSERT(count <= l2b->l2b_occupancy); 1315 1316 /* 1317 * Update the bucket's reference count according to how many 1318 * PTEs the caller has just invalidated. 1319 */ 1320 l2b->l2b_occupancy -= count; 1321 1322 /* 1323 * Note: 1324 * 1325 * Level 2 page tables allocated to the kernel pmap are never freed 1326 * as that would require checking all Level 1 page tables and 1327 * removing any references to the Level 2 page table. See also the 1328 * comment elsewhere about never freeing bootstrap L2 descriptors. 1329 * 1330 * We make do with just invalidating the mapping in the L2 table. 1331 * 1332 * This isn't really a big deal in practice and, in fact, leads 1333 * to a performance win over time as we don't need to continually 1334 * alloc/free. 1335 */ 1336 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1337 return; 1338 1339 /* 1340 * There are no more valid mappings in this level 2 page table. 1341 * Go ahead and NULL-out the pointer in the bucket, then 1342 * free the page table. 1343 */ 1344 l1idx = l2b->l2b_l1idx; 1345 ptep = l2b->l2b_kva; 1346 l2b->l2b_kva = NULL; 1347 1348 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1349 1350 /* 1351 * If the L1 slot matches the pmap's domain 1352 * number, then invalidate it. 1353 */ 1354 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1355 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1356 *pl1pd = 0; 1357 PTE_SYNC(pl1pd); 1358 } 1359 1360 /* 1361 * Release the L2 descriptor table back to the pool cache. 1362 */ 1363 #ifndef PMAP_INCLUDE_PTE_SYNC 1364 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1365 #else 1366 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1367 #endif 1368 1369 /* 1370 * Update the reference count in the associated l2_dtable 1371 */ 1372 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1373 if (--l2->l2_occupancy > 0) 1374 return; 1375 1376 /* 1377 * There are no more valid mappings in any of the Level 1 1378 * slots managed by this l2_dtable. Go ahead and NULL-out 1379 * the pointer in the parent pmap and free the l2_dtable. 1380 */ 1381 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1382 pmap_free_l2_dtable(l2); 1383 } 1384 1385 /* 1386 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1387 * structures. 1388 */ 1389 static int 1390 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1391 { 1392 #ifndef PMAP_INCLUDE_PTE_SYNC 1393 struct l2_bucket *l2b; 1394 pt_entry_t *ptep, pte; 1395 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1396 1397 /* 1398 * The mappings for these page tables were initially made using 1399 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1400 * mode will not be right for page table mappings. To avoid 1401 * polluting the pmap_kenter_pa() code with a special case for 1402 * page tables, we simply fix up the cache-mode here if it's not 1403 * correct. 1404 */ 1405 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1406 KDASSERT(l2b != NULL); 1407 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1408 pte = *ptep; 1409 1410 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1411 /* 1412 * Page tables must have the cache-mode set to Write-Thru. 1413 */ 1414 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1415 PTE_SYNC(ptep); 1416 cpu_tlb_flushD_SE(va); 1417 cpu_cpwait(); 1418 } 1419 #endif 1420 1421 memset(v, 0, L2_TABLE_SIZE_REAL); 1422 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1423 return (0); 1424 } 1425 1426 static int 1427 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1428 { 1429 1430 memset(v, 0, sizeof(struct l2_dtable)); 1431 return (0); 1432 } 1433 1434 static int 1435 pmap_pmap_ctor(void *arg, void *v, int flags) 1436 { 1437 1438 memset(v, 0, sizeof(struct pmap)); 1439 return (0); 1440 } 1441 1442 static void 1443 pmap_pinit(pmap_t pm) 1444 { 1445 struct l2_bucket *l2b; 1446 1447 if (vector_page < KERNEL_BASE) { 1448 /* 1449 * Map the vector page. 1450 */ 1451 pmap_enter(pm, vector_page, systempage.pv_pa, 1452 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1453 pmap_update(pm); 1454 1455 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1456 l2b = pmap_get_l2_bucket(pm, vector_page); 1457 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1458 L1_C_DOM(pm->pm_domain); 1459 } else 1460 pm->pm_pl1vec = NULL; 1461 } 1462 1463 #ifdef PMAP_CACHE_VIVT 1464 /* 1465 * Since we have a virtually indexed cache, we may need to inhibit caching if 1466 * there is more than one mapping and at least one of them is writable. 1467 * Since we purge the cache on every context switch, we only need to check for 1468 * other mappings within the same pmap, or kernel_pmap. 1469 * This function is also called when a page is unmapped, to possibly reenable 1470 * caching on any remaining mappings. 1471 * 1472 * The code implements the following logic, where: 1473 * 1474 * KW = # of kernel read/write pages 1475 * KR = # of kernel read only pages 1476 * UW = # of user read/write pages 1477 * UR = # of user read only pages 1478 * 1479 * KC = kernel mapping is cacheable 1480 * UC = user mapping is cacheable 1481 * 1482 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1483 * +--------------------------------------------- 1484 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1485 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1486 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1487 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1488 */ 1489 1490 static const int pmap_vac_flags[4][4] = { 1491 {-1, 0, 0, PVF_KNC}, 1492 {0, 0, PVF_NC, PVF_NC}, 1493 {0, PVF_NC, PVF_NC, PVF_NC}, 1494 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1495 }; 1496 1497 static inline int 1498 pmap_get_vac_flags(const struct vm_page *pg) 1499 { 1500 int kidx, uidx; 1501 1502 kidx = 0; 1503 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1504 kidx |= 1; 1505 if (pg->mdpage.krw_mappings) 1506 kidx |= 2; 1507 1508 uidx = 0; 1509 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1510 uidx |= 1; 1511 if (pg->mdpage.urw_mappings) 1512 uidx |= 2; 1513 1514 return (pmap_vac_flags[uidx][kidx]); 1515 } 1516 1517 static inline void 1518 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1519 { 1520 int nattr; 1521 1522 nattr = pmap_get_vac_flags(pg); 1523 1524 if (nattr < 0) { 1525 pg->mdpage.pvh_attrs &= ~PVF_NC; 1526 return; 1527 } 1528 1529 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1530 return; 1531 1532 if (pm == pmap_kernel()) 1533 pmap_vac_me_kpmap(pg, pm, va); 1534 else 1535 pmap_vac_me_user(pg, pm, va); 1536 1537 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1538 } 1539 1540 static void 1541 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1542 { 1543 u_int u_cacheable, u_entries; 1544 struct pv_entry *pv; 1545 pmap_t last_pmap = pm; 1546 1547 /* 1548 * Pass one, see if there are both kernel and user pmaps for 1549 * this page. Calculate whether there are user-writable or 1550 * kernel-writable pages. 1551 */ 1552 u_cacheable = 0; 1553 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1554 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1555 u_cacheable++; 1556 } 1557 1558 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1559 1560 /* 1561 * We know we have just been updating a kernel entry, so if 1562 * all user pages are already cacheable, then there is nothing 1563 * further to do. 1564 */ 1565 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1566 return; 1567 1568 if (u_entries) { 1569 /* 1570 * Scan over the list again, for each entry, if it 1571 * might not be set correctly, call pmap_vac_me_user 1572 * to recalculate the settings. 1573 */ 1574 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1575 /* 1576 * We know kernel mappings will get set 1577 * correctly in other calls. We also know 1578 * that if the pmap is the same as last_pmap 1579 * then we've just handled this entry. 1580 */ 1581 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1582 continue; 1583 1584 /* 1585 * If there are kernel entries and this page 1586 * is writable but non-cacheable, then we can 1587 * skip this entry also. 1588 */ 1589 if (pg->mdpage.k_mappings && 1590 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1591 (PVF_NC | PVF_WRITE)) 1592 continue; 1593 1594 /* 1595 * Similarly if there are no kernel-writable 1596 * entries and the page is already 1597 * read-only/cacheable. 1598 */ 1599 if (pg->mdpage.krw_mappings == 0 && 1600 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1601 continue; 1602 1603 /* 1604 * For some of the remaining cases, we know 1605 * that we must recalculate, but for others we 1606 * can't tell if they are correct or not, so 1607 * we recalculate anyway. 1608 */ 1609 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1610 } 1611 1612 if (pg->mdpage.k_mappings == 0) 1613 return; 1614 } 1615 1616 pmap_vac_me_user(pg, pm, va); 1617 } 1618 1619 static void 1620 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1621 { 1622 pmap_t kpmap = pmap_kernel(); 1623 struct pv_entry *pv, *npv; 1624 struct l2_bucket *l2b; 1625 pt_entry_t *ptep, pte; 1626 u_int entries = 0; 1627 u_int writable = 0; 1628 u_int cacheable_entries = 0; 1629 u_int kern_cacheable = 0; 1630 u_int other_writable = 0; 1631 1632 /* 1633 * Count mappings and writable mappings in this pmap. 1634 * Include kernel mappings as part of our own. 1635 * Keep a pointer to the first one. 1636 */ 1637 for (pv = npv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1638 /* Count mappings in the same pmap */ 1639 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1640 if (entries++ == 0) 1641 npv = pv; 1642 1643 /* Cacheable mappings */ 1644 if ((pv->pv_flags & PVF_NC) == 0) { 1645 cacheable_entries++; 1646 if (kpmap == pv->pv_pmap) 1647 kern_cacheable++; 1648 } 1649 1650 /* Writable mappings */ 1651 if (pv->pv_flags & PVF_WRITE) 1652 ++writable; 1653 } else 1654 if (pv->pv_flags & PVF_WRITE) 1655 other_writable = 1; 1656 } 1657 1658 /* 1659 * Enable or disable caching as necessary. 1660 * Note: the first entry might be part of the kernel pmap, 1661 * so we can't assume this is indicative of the state of the 1662 * other (maybe non-kpmap) entries. 1663 */ 1664 if ((entries > 1 && writable) || 1665 (entries > 0 && pm == kpmap && other_writable)) { 1666 if (cacheable_entries == 0) 1667 return; 1668 1669 for (pv = npv; pv; pv = pv->pv_next) { 1670 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1671 (pv->pv_flags & PVF_NC)) 1672 continue; 1673 1674 pv->pv_flags |= PVF_NC; 1675 1676 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1677 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1678 pte = *ptep & ~L2_S_CACHE_MASK; 1679 1680 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1681 l2pte_valid(pte)) { 1682 if (PV_BEEN_EXECD(pv->pv_flags)) { 1683 #ifdef PMAP_CACHE_VIVT 1684 pmap_idcache_wbinv_range(pv->pv_pmap, 1685 pv->pv_va, PAGE_SIZE); 1686 #endif 1687 pmap_tlb_flushID_SE(pv->pv_pmap, 1688 pv->pv_va); 1689 } else 1690 if (PV_BEEN_REFD(pv->pv_flags)) { 1691 #ifdef PMAP_CACHE_VIVT 1692 pmap_dcache_wb_range(pv->pv_pmap, 1693 pv->pv_va, PAGE_SIZE, true, 1694 (pv->pv_flags & PVF_WRITE) == 0); 1695 #endif 1696 pmap_tlb_flushD_SE(pv->pv_pmap, 1697 pv->pv_va); 1698 } 1699 } 1700 1701 *ptep = pte; 1702 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1703 } 1704 cpu_cpwait(); 1705 } else 1706 if (entries > cacheable_entries) { 1707 /* 1708 * Turn cacheing back on for some pages. If it is a kernel 1709 * page, only do so if there are no other writable pages. 1710 */ 1711 for (pv = npv; pv; pv = pv->pv_next) { 1712 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1713 (kpmap != pv->pv_pmap || other_writable))) 1714 continue; 1715 1716 pv->pv_flags &= ~PVF_NC; 1717 1718 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1719 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1720 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1721 1722 if (l2pte_valid(pte)) { 1723 if (PV_BEEN_EXECD(pv->pv_flags)) { 1724 pmap_tlb_flushID_SE(pv->pv_pmap, 1725 pv->pv_va); 1726 } else 1727 if (PV_BEEN_REFD(pv->pv_flags)) { 1728 pmap_tlb_flushD_SE(pv->pv_pmap, 1729 pv->pv_va); 1730 } 1731 } 1732 1733 *ptep = pte; 1734 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1735 } 1736 } 1737 } 1738 #endif 1739 1740 #ifdef PMAP_CACHE_VIPT 1741 /* 1742 * For virtually indexed / physically tagged caches, what we have to worry 1743 * about is illegal cache aliases. To prevent this, we must ensure that 1744 * virtual addresses that map the physical page use the same bits for those 1745 * bits masked by "arm_cache_prefer_mask" (bits 12+). If there is a conflict, 1746 * all mappings of the page must be non-cached. 1747 */ 1748 #if 0 1749 static inline vaddr_t 1750 pmap_check_sets(paddr_t pa) 1751 { 1752 extern int arm_dcache_l2_nsets; 1753 int set, way; 1754 vaddr_t mask = 0; 1755 int v; 1756 pa |= 1; 1757 for (set = 0; set < (1 << arm_dcache_l2_nsets); set++) { 1758 for (way = 0; way < 4; way++) { 1759 v = (way << 30) | (set << 5); 1760 asm("mcr p15, 3, %0, c15, c2, 0" :: "r"(v)); 1761 asm("mrc p15, 3, %0, c15, c0, 0" : "=r"(v)); 1762 1763 if ((v & (1 | ~(PAGE_SIZE-1))) == pa) { 1764 mask |= 1 << (set >> 7); 1765 } 1766 } 1767 } 1768 return mask; 1769 } 1770 #endif 1771 static void 1772 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1773 { 1774 struct pv_entry *pv, pv0; 1775 vaddr_t tst_mask; 1776 bool bad_alias; 1777 struct l2_bucket *l2b; 1778 pt_entry_t *ptep, pte, opte; 1779 1780 /* do we need to do anything? */ 1781 if (arm_cache_prefer_mask == 0) 1782 return; 1783 1784 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1785 pg, pm, va)); 1786 1787 #define popc4(x) \ 1788 (((0x94 >> ((x & 3) << 1)) & 3) + ((0x94 >> ((x & 12) >> 1)) & 3)) 1789 #if 0 1790 tst_mask = pmap_check_sets(pg->phys_addr); 1791 KASSERT(popc4(tst_mask) < 2); 1792 #endif 1793 1794 KASSERT(!va || pm || (pg->mdpage.pvh_attrs & PVF_KENTRY)); 1795 1796 /* Already a conflict? */ 1797 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1798 /* just an add, things are already non-cached */ 1799 bad_alias = false; 1800 if (va) { 1801 PMAPCOUNT(vac_color_none); 1802 bad_alias = true; 1803 goto fixup; 1804 } 1805 pv = pg->mdpage.pvh_list; 1806 /* the list can't be empty because it would be cachable */ 1807 if (pg->mdpage.pvh_attrs & PVF_KENTRY) { 1808 tst_mask = pg->mdpage.pvh_attrs; 1809 } else { 1810 KASSERT(pv); 1811 tst_mask = pv->pv_va; 1812 pv = pv->pv_next; 1813 } 1814 /* 1815 * Only check for a bad alias if we have writable mappings. 1816 */ 1817 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings > 0 1818 || (pg->mdpage.pvh_attrs & PVF_KENTRY)) { 1819 tst_mask &= arm_cache_prefer_mask; 1820 for (; pv && !bad_alias; pv = pv->pv_next) { 1821 /* if there's a bad alias, stop checking. */ 1822 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1823 bad_alias = true; 1824 } 1825 } 1826 /* If no conflicting colors, set everything back to cached */ 1827 if (!bad_alias) { 1828 PMAPCOUNT(vac_color_restore); 1829 pg->mdpage.pvh_attrs |= PVF_COLORED; 1830 if (!(pg->mdpage.pvh_attrs & PVF_KENTRY)) { 1831 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1832 pg->mdpage.pvh_attrs |= tst_mask; 1833 } 1834 pg->mdpage.pvh_attrs &= ~PVF_NC; 1835 } else { 1836 KASSERT(pg->mdpage.pvh_list != NULL); 1837 KASSERT((pg->mdpage.pvh_attrs & PVF_KENTRY) 1838 || pg->mdpage.pvh_list->pv_next != NULL); 1839 } 1840 } else if (!va) { 1841 KASSERT(pmap_is_page_colored_p(pg)); 1842 if (pm == NULL) 1843 pg->mdpage.pvh_attrs &= 1844 (PAGE_SIZE - 1) | arm_cache_prefer_mask; 1845 return; 1846 } else if (!pmap_is_page_colored_p(pg)) { 1847 /* not colored so we just use its color */ 1848 PMAPCOUNT(vac_color_new); 1849 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1850 if (pm == NULL) 1851 pg->mdpage.pvh_attrs |= PVF_COLORED | va; 1852 else 1853 pg->mdpage.pvh_attrs |= PVF_COLORED 1854 | (va & arm_cache_prefer_mask); 1855 return; 1856 } else if (!((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) 1857 /* 1858 * If the VA matches the existing color or if all the mappings 1859 * are read-only, don't do anything. 1860 */ 1861 || (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0 1862 && (pg->mdpage.pvh_attrs & PVF_KENTRY) == 0)) { 1863 if (pm == NULL) { 1864 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1865 pg->mdpage.pvh_attrs |= va; 1866 } 1867 if (pg->mdpage.pvh_list) 1868 PMAPCOUNT(vac_color_reuse); 1869 else 1870 PMAPCOUNT(vac_color_ok); 1871 /* matching color, just return */ 1872 return; 1873 } else { 1874 /* color conflict. evict from cache. */ 1875 pmap_flush_page(pg); 1876 1877 /* the list can't be empty because this was a enter/modify */ 1878 pv = pg->mdpage.pvh_list; 1879 KASSERT((pg->mdpage.pvh_attrs & PVF_KENTRY) || pv); 1880 1881 /* 1882 * If there's only one mapped page, change color to the 1883 * page's new color and return. 1884 */ 1885 if (((pg->mdpage.pvh_attrs & PVF_KENTRY) 1886 ? pv : pv->pv_next) == NULL) { 1887 PMAPCOUNT(vac_color_change); 1888 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1889 if (pm == NULL) 1890 pg->mdpage.pvh_attrs |= va; 1891 else 1892 pg->mdpage.pvh_attrs |= 1893 (va & arm_cache_prefer_mask); 1894 return; 1895 } 1896 bad_alias = true; 1897 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 1898 pg->mdpage.pvh_attrs |= PVF_NC; 1899 PMAPCOUNT(vac_color_erase); 1900 } 1901 1902 fixup: 1903 /* 1904 * If the pmap is NULL, then we got called from pmap_kenter_pa 1905 * and we must save the kenter'ed va. And this changes the 1906 * color to match the kenter'ed page. if this is a remove clear 1907 * saved va bits which retaining the color bits. 1908 */ 1909 if (pm == NULL) { 1910 if (va) { 1911 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1); 1912 pg->mdpage.pvh_attrs |= va; 1913 } else { 1914 pg->mdpage.pvh_attrs &= 1915 ((PAGE_SIZE - 1) | arm_cache_prefer_mask); 1916 } 1917 } 1918 1919 pv = pg->mdpage.pvh_list; 1920 1921 /* 1922 * If this page has an kenter'ed mapping, fake up a pv entry. 1923 */ 1924 if (__predict_false(pg->mdpage.pvh_attrs & PVF_KENTRY)) { 1925 pv0.pv_pmap = pmap_kernel(); 1926 pv0.pv_va = pg->mdpage.pvh_attrs & ~(PAGE_SIZE - 1); 1927 pv0.pv_next = pv; 1928 pv0.pv_flags = PVF_REF; 1929 pv = &pv0; 1930 } 1931 1932 /* 1933 * Turn cacheing on/off for all pages. 1934 */ 1935 for (; pv; pv = pv->pv_next) { 1936 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1937 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1938 opte = *ptep; 1939 pte = opte & ~L2_S_CACHE_MASK; 1940 if (bad_alias) { 1941 pv->pv_flags |= PVF_NC; 1942 } else { 1943 pv->pv_flags &= ~PVF_NC; 1944 pte |= pte_l2_s_cache_mode; 1945 } 1946 if (opte == pte) /* only update is there's a change */ 1947 continue; 1948 1949 if (l2pte_valid(pte)) { 1950 if (PV_BEEN_EXECD(pv->pv_flags)) { 1951 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1952 } else if (PV_BEEN_REFD(pv->pv_flags)) { 1953 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 1954 } 1955 } 1956 1957 *ptep = pte; 1958 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1959 } 1960 } 1961 #endif /* PMAP_CACHE_VIPT */ 1962 1963 1964 /* 1965 * Modify pte bits for all ptes corresponding to the given physical address. 1966 * We use `maskbits' rather than `clearbits' because we're always passing 1967 * constants and the latter would require an extra inversion at run-time. 1968 */ 1969 static void 1970 pmap_clearbit(struct vm_page *pg, u_int maskbits) 1971 { 1972 struct l2_bucket *l2b; 1973 struct pv_entry *pv; 1974 pt_entry_t *ptep, npte, opte; 1975 pmap_t pm; 1976 vaddr_t va; 1977 u_int oflags; 1978 #ifdef PMAP_CACHE_VIPT 1979 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 1980 bool need_syncicache = false; 1981 bool did_syncicache = false; 1982 #endif 1983 1984 NPDEBUG(PDB_BITS, 1985 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 1986 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 1987 1988 PMAP_HEAD_TO_MAP_LOCK(); 1989 simple_lock(&pg->mdpage.pvh_slock); 1990 1991 #ifdef PMAP_CACHE_VIPT 1992 /* 1993 * If we might want to sync the I-cache and we've modified it, 1994 * then we know we definitely need to sync or discard it. 1995 */ 1996 if (want_syncicache) 1997 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 1998 #endif 1999 /* 2000 * Clear saved attributes (modify, reference) 2001 */ 2002 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2003 2004 if (pg->mdpage.pvh_list == NULL) { 2005 #ifdef PMAP_CACHE_VIPT 2006 if (need_syncicache) { 2007 /* 2008 * No one has it mapped, so just discard it. The next 2009 * exec remapping will cause it to be synced. 2010 */ 2011 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2012 PMAPCOUNT(exec_discarded_clearbit); 2013 } 2014 #endif 2015 simple_unlock(&pg->mdpage.pvh_slock); 2016 PMAP_HEAD_TO_MAP_UNLOCK(); 2017 return; 2018 } 2019 2020 /* 2021 * Loop over all current mappings setting/clearing as appropos 2022 */ 2023 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 2024 va = pv->pv_va; 2025 pm = pv->pv_pmap; 2026 oflags = pv->pv_flags; 2027 pv->pv_flags &= ~maskbits; 2028 2029 pmap_acquire_pmap_lock(pm); 2030 2031 l2b = pmap_get_l2_bucket(pm, va); 2032 KDASSERT(l2b != NULL); 2033 2034 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2035 npte = opte = *ptep; 2036 2037 NPDEBUG(PDB_BITS, 2038 printf( 2039 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2040 pv, pv->pv_pmap, pv->pv_va, oflags)); 2041 2042 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2043 #ifdef PMAP_CACHE_VIVT 2044 if ((pv->pv_flags & PVF_NC)) { 2045 /* 2046 * Entry is not cacheable: 2047 * 2048 * Don't turn caching on again if this is a 2049 * modified emulation. This would be 2050 * inconsitent with the settings created by 2051 * pmap_vac_me_harder(). Otherwise, it's safe 2052 * to re-enable cacheing. 2053 * 2054 * There's no need to call pmap_vac_me_harder() 2055 * here: all pages are losing their write 2056 * permission. 2057 */ 2058 if (maskbits & PVF_WRITE) { 2059 npte |= pte_l2_s_cache_mode; 2060 pv->pv_flags &= ~PVF_NC; 2061 } 2062 } else 2063 if (opte & L2_S_PROT_W) { 2064 /* 2065 * Entry is writable/cacheable: check if pmap 2066 * is current if it is flush it, otherwise it 2067 * won't be in the cache 2068 */ 2069 if (PV_BEEN_EXECD(oflags)) 2070 pmap_idcache_wbinv_range(pm, pv->pv_va, 2071 PAGE_SIZE); 2072 else 2073 if (PV_BEEN_REFD(oflags)) 2074 pmap_dcache_wb_range(pm, pv->pv_va, 2075 PAGE_SIZE, 2076 (maskbits & PVF_REF) != 0, false); 2077 } 2078 #endif 2079 2080 /* make the pte read only */ 2081 npte &= ~L2_S_PROT_W; 2082 2083 if (maskbits & oflags & PVF_WRITE) { 2084 /* 2085 * Keep alias accounting up to date 2086 */ 2087 if (pv->pv_pmap == pmap_kernel()) { 2088 pg->mdpage.krw_mappings--; 2089 pg->mdpage.kro_mappings++; 2090 } else { 2091 pg->mdpage.urw_mappings--; 2092 pg->mdpage.uro_mappings++; 2093 } 2094 #ifdef PMAP_CACHE_VIPT 2095 if (want_syncicache) 2096 need_syncicache = true; 2097 #endif 2098 } 2099 } 2100 2101 if (maskbits & PVF_REF) { 2102 #ifdef PMAP_CACHE_VIVT 2103 if ((pv->pv_flags & PVF_NC) == 0 && 2104 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2105 l2pte_valid(npte)) { 2106 /* 2107 * Check npte here; we may have already 2108 * done the wbinv above, and the validity 2109 * of the PTE is the same for opte and 2110 * npte. 2111 */ 2112 /* XXXJRT need idcache_inv_range */ 2113 if (PV_BEEN_EXECD(oflags)) 2114 pmap_idcache_wbinv_range(pm, 2115 pv->pv_va, PAGE_SIZE); 2116 else 2117 if (PV_BEEN_REFD(oflags)) 2118 pmap_dcache_wb_range(pm, 2119 pv->pv_va, PAGE_SIZE, 2120 true, true); 2121 } 2122 #endif 2123 2124 /* 2125 * Make the PTE invalid so that we will take a 2126 * page fault the next time the mapping is 2127 * referenced. 2128 */ 2129 npte &= ~L2_TYPE_MASK; 2130 npte |= L2_TYPE_INV; 2131 } 2132 2133 if (npte != opte) { 2134 *ptep = npte; 2135 PTE_SYNC(ptep); 2136 /* Flush the TLB entry if a current pmap. */ 2137 if (PV_BEEN_EXECD(oflags)) 2138 pmap_tlb_flushID_SE(pm, pv->pv_va); 2139 else 2140 if (PV_BEEN_REFD(oflags)) 2141 pmap_tlb_flushD_SE(pm, pv->pv_va); 2142 } 2143 2144 pmap_release_pmap_lock(pm); 2145 2146 NPDEBUG(PDB_BITS, 2147 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2148 pm, va, opte, npte)); 2149 } 2150 2151 #ifdef PMAP_CACHE_VIPT 2152 /* 2153 * If we need to sync the I-cache and we haven't done it yet, do it. 2154 */ 2155 if (need_syncicache && !did_syncicache) { 2156 pmap_syncicache_page(pg); 2157 PMAPCOUNT(exec_synced_clearbit); 2158 } 2159 #endif 2160 2161 simple_unlock(&pg->mdpage.pvh_slock); 2162 PMAP_HEAD_TO_MAP_UNLOCK(); 2163 } 2164 2165 /* 2166 * pmap_clean_page() 2167 * 2168 * This is a local function used to work out the best strategy to clean 2169 * a single page referenced by its entry in the PV table. It's used by 2170 * pmap_copy_page, pmap_zero page and maybe some others later on. 2171 * 2172 * Its policy is effectively: 2173 * o If there are no mappings, we don't bother doing anything with the cache. 2174 * o If there is one mapping, we clean just that page. 2175 * o If there are multiple mappings, we clean the entire cache. 2176 * 2177 * So that some functions can be further optimised, it returns 0 if it didn't 2178 * clean the entire cache, or 1 if it did. 2179 * 2180 * XXX One bug in this routine is that if the pv_entry has a single page 2181 * mapped at 0x00000000 a whole cache clean will be performed rather than 2182 * just the 1 page. Since this should not occur in everyday use and if it does 2183 * it will just result in not the most efficient clean for the page. 2184 */ 2185 #ifdef PMAP_CACHE_VIVT 2186 static int 2187 pmap_clean_page(struct pv_entry *pv, bool is_src) 2188 { 2189 pmap_t pm, pm_to_clean = NULL; 2190 struct pv_entry *npv; 2191 u_int cache_needs_cleaning = 0; 2192 u_int flags = 0; 2193 vaddr_t page_to_clean = 0; 2194 2195 if (pv == NULL) { 2196 /* nothing mapped in so nothing to flush */ 2197 return (0); 2198 } 2199 2200 /* 2201 * Since we flush the cache each time we change to a different 2202 * user vmspace, we only need to flush the page if it is in the 2203 * current pmap. 2204 */ 2205 if (curproc) 2206 pm = curproc->p_vmspace->vm_map.pmap; 2207 else 2208 pm = pmap_kernel(); 2209 2210 for (npv = pv; npv; npv = npv->pv_next) { 2211 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2212 flags |= npv->pv_flags; 2213 /* 2214 * The page is mapped non-cacheable in 2215 * this map. No need to flush the cache. 2216 */ 2217 if (npv->pv_flags & PVF_NC) { 2218 #ifdef DIAGNOSTIC 2219 if (cache_needs_cleaning) 2220 panic("pmap_clean_page: " 2221 "cache inconsistency"); 2222 #endif 2223 break; 2224 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2225 continue; 2226 if (cache_needs_cleaning) { 2227 page_to_clean = 0; 2228 break; 2229 } else { 2230 page_to_clean = npv->pv_va; 2231 pm_to_clean = npv->pv_pmap; 2232 } 2233 cache_needs_cleaning = 1; 2234 } 2235 } 2236 2237 if (page_to_clean) { 2238 if (PV_BEEN_EXECD(flags)) 2239 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2240 PAGE_SIZE); 2241 else 2242 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2243 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2244 } else if (cache_needs_cleaning) { 2245 if (PV_BEEN_EXECD(flags)) 2246 pmap_idcache_wbinv_all(pm); 2247 else 2248 pmap_dcache_wbinv_all(pm); 2249 return (1); 2250 } 2251 return (0); 2252 } 2253 #endif 2254 2255 #ifdef PMAP_CACHE_VIPT 2256 /* 2257 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2258 * right cache alias to make sure we flush the right stuff. 2259 */ 2260 void 2261 pmap_syncicache_page(struct vm_page *pg) 2262 { 2263 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2264 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2265 2266 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2267 pg, pg->mdpage.pvh_attrs)); 2268 /* 2269 * No need to clean the page if it's non-cached. 2270 */ 2271 if (pg->mdpage.pvh_attrs & PVF_NC) 2272 return; 2273 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2274 2275 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2276 /* 2277 * Set up a PTE with the right coloring to flush existing cache lines. 2278 */ 2279 *ptep = L2_S_PROTO | 2280 VM_PAGE_TO_PHYS(pg) 2281 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2282 | pte_l2_s_cache_mode; 2283 PTE_SYNC(ptep); 2284 2285 /* 2286 * Flush it. 2287 */ 2288 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2289 /* 2290 * Unmap the page. 2291 */ 2292 *ptep = 0; 2293 PTE_SYNC(ptep); 2294 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2295 2296 pg->mdpage.pvh_attrs |= PVF_EXEC; 2297 PMAPCOUNT(exec_synced); 2298 } 2299 2300 void 2301 pmap_flush_page(struct vm_page *pg) 2302 { 2303 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2304 const size_t pte_offset = va_offset >> PGSHIFT; 2305 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2306 const pt_entry_t oldpte = *ptep; 2307 #if 0 2308 vaddr_t mask; 2309 #endif 2310 2311 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2312 #if 0 2313 mask = pmap_check_sets(pg->phys_addr); 2314 KASSERT(popc4(mask) < 2); 2315 #endif 2316 2317 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2318 pg, pg->mdpage.pvh_attrs)); 2319 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2320 /* 2321 * Set up a PTE with the right coloring to flush existing cache entries. 2322 */ 2323 *ptep = L2_S_PROTO 2324 | VM_PAGE_TO_PHYS(pg) 2325 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2326 | pte_l2_s_cache_mode; 2327 PTE_SYNC(ptep); 2328 2329 /* 2330 * Flush it. 2331 */ 2332 cpu_idcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 2333 2334 /* 2335 * Restore the page table entry since we might have interrupted 2336 * pmap_zero_page or pmap_copy_page which was already using this pte. 2337 */ 2338 *ptep = oldpte; 2339 PTE_SYNC(ptep); 2340 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2341 #if 0 2342 mask = pmap_check_sets(pg->phys_addr); 2343 KASSERT(mask == 0); 2344 #endif 2345 } 2346 #endif /* PMAP_CACHE_VIPT */ 2347 2348 /* 2349 * Routine: pmap_page_remove 2350 * Function: 2351 * Removes this physical page from 2352 * all physical maps in which it resides. 2353 * Reflects back modify bits to the pager. 2354 */ 2355 static void 2356 pmap_page_remove(struct vm_page *pg) 2357 { 2358 struct l2_bucket *l2b; 2359 struct pv_entry *pv, *npv; 2360 pmap_t pm, curpm; 2361 pt_entry_t *ptep, pte; 2362 bool flush; 2363 u_int flags; 2364 2365 NPDEBUG(PDB_FOLLOW, 2366 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2367 VM_PAGE_TO_PHYS(pg))); 2368 2369 PMAP_HEAD_TO_MAP_LOCK(); 2370 simple_lock(&pg->mdpage.pvh_slock); 2371 2372 pv = pg->mdpage.pvh_list; 2373 if (pv == NULL) { 2374 #ifdef PMAP_CACHE_VIPT 2375 /* 2376 * We *know* the page contents are about to be replaced. 2377 * Discard the exec contents 2378 */ 2379 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2380 PMAPCOUNT(exec_discarded_page_protect); 2381 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2382 #endif 2383 simple_unlock(&pg->mdpage.pvh_slock); 2384 PMAP_HEAD_TO_MAP_UNLOCK(); 2385 return; 2386 } 2387 #ifdef PMAP_CACHE_VIPT 2388 KASSERT(pmap_is_page_colored_p(pg)); 2389 #endif 2390 2391 /* 2392 * Clear alias counts 2393 */ 2394 pg->mdpage.k_mappings = 0; 2395 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2396 2397 flush = false; 2398 flags = 0; 2399 if (curproc) 2400 curpm = curproc->p_vmspace->vm_map.pmap; 2401 else 2402 curpm = pmap_kernel(); 2403 2404 #ifdef PMAP_CACHE_VIVT 2405 pmap_clean_page(pv, false); 2406 #endif 2407 2408 while (pv) { 2409 pm = pv->pv_pmap; 2410 if (flush == false && (pm == curpm || pm == pmap_kernel())) 2411 flush = true; 2412 2413 if (pm == pmap_kernel()) 2414 PMAPCOUNT(kernel_unmappings); 2415 PMAPCOUNT(unmappings); 2416 2417 pmap_acquire_pmap_lock(pm); 2418 2419 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2420 KDASSERT(l2b != NULL); 2421 2422 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2423 pte = *ptep; 2424 2425 /* 2426 * Update statistics 2427 */ 2428 --pm->pm_stats.resident_count; 2429 2430 /* Wired bit */ 2431 if (pv->pv_flags & PVF_WIRED) 2432 --pm->pm_stats.wired_count; 2433 2434 flags |= pv->pv_flags; 2435 2436 /* 2437 * Invalidate the PTEs. 2438 */ 2439 *ptep = 0; 2440 PTE_SYNC_CURRENT(pm, ptep); 2441 pmap_free_l2_bucket(pm, l2b, 1); 2442 2443 npv = pv->pv_next; 2444 pool_put(&pmap_pv_pool, pv); 2445 pv = npv; 2446 if (pv == NULL) { 2447 pg->mdpage.pvh_list = NULL; 2448 if (pg->mdpage.pvh_attrs & PVF_KENTRY) 2449 pmap_vac_me_harder(pg, pm, 0); 2450 } 2451 pmap_release_pmap_lock(pm); 2452 } 2453 #ifdef PMAP_CACHE_VIPT 2454 /* 2455 * Since there are now no mappings, there isn't reason to mark it 2456 * as uncached. Its EXEC cache is also gone. 2457 */ 2458 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2459 PMAPCOUNT(exec_discarded_page_protect); 2460 pg->mdpage.pvh_attrs &= ~(PVF_NC|PVF_EXEC); 2461 #endif 2462 #ifdef PMAP_CACHE_VIVT 2463 pg->mdpage.pvh_list = NULL; 2464 #endif 2465 simple_unlock(&pg->mdpage.pvh_slock); 2466 PMAP_HEAD_TO_MAP_UNLOCK(); 2467 2468 if (flush) { 2469 /* 2470 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2471 * would need a subsequent call to pmap_update() to ensure 2472 * curpm->pm_cstate.cs_all is reset. Our callers are not 2473 * required to do that (see pmap(9)), so we can't modify 2474 * the current pmap's state. 2475 */ 2476 if (PV_BEEN_EXECD(flags)) 2477 cpu_tlb_flushID(); 2478 else 2479 cpu_tlb_flushD(); 2480 } 2481 cpu_cpwait(); 2482 } 2483 2484 /* 2485 * pmap_t pmap_create(void) 2486 * 2487 * Create a new pmap structure from scratch. 2488 */ 2489 pmap_t 2490 pmap_create(void) 2491 { 2492 pmap_t pm; 2493 2494 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2495 2496 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2497 pm->pm_stats.wired_count = 0; 2498 pm->pm_stats.resident_count = 1; 2499 pm->pm_cstate.cs_all = 0; 2500 pmap_alloc_l1(pm); 2501 2502 /* 2503 * Note: The pool cache ensures that the pm_l2[] array is already 2504 * initialised to zero. 2505 */ 2506 2507 pmap_pinit(pm); 2508 2509 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2510 2511 return (pm); 2512 } 2513 2514 /* 2515 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2516 * int flags) 2517 * 2518 * Insert the given physical page (p) at 2519 * the specified virtual address (v) in the 2520 * target physical map with the protection requested. 2521 * 2522 * NB: This is the only routine which MAY NOT lazy-evaluate 2523 * or lose information. That is, this routine must actually 2524 * insert this page into the given map NOW. 2525 */ 2526 int 2527 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 2528 { 2529 struct l2_bucket *l2b; 2530 struct vm_page *pg, *opg; 2531 struct pv_entry *pve; 2532 pt_entry_t *ptep, npte, opte; 2533 u_int nflags; 2534 u_int oflags; 2535 2536 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2537 2538 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2539 KDASSERT(((va | pa) & PGOFSET) == 0); 2540 2541 /* 2542 * Get a pointer to the page. Later on in this function, we 2543 * test for a managed page by checking pg != NULL. 2544 */ 2545 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2546 2547 nflags = 0; 2548 if (prot & VM_PROT_WRITE) 2549 nflags |= PVF_WRITE; 2550 if (prot & VM_PROT_EXECUTE) 2551 nflags |= PVF_EXEC; 2552 if (flags & PMAP_WIRED) 2553 nflags |= PVF_WIRED; 2554 2555 PMAP_MAP_TO_HEAD_LOCK(); 2556 pmap_acquire_pmap_lock(pm); 2557 2558 /* 2559 * Fetch the L2 bucket which maps this page, allocating one if 2560 * necessary for user pmaps. 2561 */ 2562 if (pm == pmap_kernel()) 2563 l2b = pmap_get_l2_bucket(pm, va); 2564 else 2565 l2b = pmap_alloc_l2_bucket(pm, va); 2566 if (l2b == NULL) { 2567 if (flags & PMAP_CANFAIL) { 2568 pmap_release_pmap_lock(pm); 2569 PMAP_MAP_TO_HEAD_UNLOCK(); 2570 return (ENOMEM); 2571 } 2572 panic("pmap_enter: failed to allocate L2 bucket"); 2573 } 2574 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2575 opte = *ptep; 2576 npte = pa; 2577 oflags = 0; 2578 2579 if (opte) { 2580 /* 2581 * There is already a mapping at this address. 2582 * If the physical address is different, lookup the 2583 * vm_page. 2584 */ 2585 if (l2pte_pa(opte) != pa) 2586 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2587 else 2588 opg = pg; 2589 } else 2590 opg = NULL; 2591 2592 if (pg) { 2593 /* 2594 * This is to be a managed mapping. 2595 */ 2596 if ((flags & VM_PROT_ALL) || 2597 (pg->mdpage.pvh_attrs & PVF_REF)) { 2598 /* 2599 * - The access type indicates that we don't need 2600 * to do referenced emulation. 2601 * OR 2602 * - The physical page has already been referenced 2603 * so no need to re-do referenced emulation here. 2604 */ 2605 npte |= L2_S_PROTO; 2606 2607 nflags |= PVF_REF; 2608 2609 if ((prot & VM_PROT_WRITE) != 0 && 2610 ((flags & VM_PROT_WRITE) != 0 || 2611 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2612 /* 2613 * This is a writable mapping, and the 2614 * page's mod state indicates it has 2615 * already been modified. Make it 2616 * writable from the outset. 2617 */ 2618 npte |= L2_S_PROT_W; 2619 nflags |= PVF_MOD; 2620 } 2621 } else { 2622 /* 2623 * Need to do page referenced emulation. 2624 */ 2625 npte |= L2_TYPE_INV; 2626 } 2627 2628 npte |= pte_l2_s_cache_mode; 2629 2630 if (pg == opg) { 2631 /* 2632 * We're changing the attrs of an existing mapping. 2633 */ 2634 simple_lock(&pg->mdpage.pvh_slock); 2635 oflags = pmap_modify_pv(pg, pm, va, 2636 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2637 PVF_MOD | PVF_REF, nflags); 2638 simple_unlock(&pg->mdpage.pvh_slock); 2639 2640 #ifdef PMAP_CACHE_VIVT 2641 /* 2642 * We may need to flush the cache if we're 2643 * doing rw-ro... 2644 */ 2645 if (pm->pm_cstate.cs_cache_d && 2646 (oflags & PVF_NC) == 0 && 2647 (opte & L2_S_PROT_W) != 0 && 2648 (prot & VM_PROT_WRITE) == 0) 2649 cpu_dcache_wb_range(va, PAGE_SIZE); 2650 #endif 2651 } else { 2652 /* 2653 * New mapping, or changing the backing page 2654 * of an existing mapping. 2655 */ 2656 if (opg) { 2657 /* 2658 * Replacing an existing mapping with a new one. 2659 * It is part of our managed memory so we 2660 * must remove it from the PV list 2661 */ 2662 simple_lock(&opg->mdpage.pvh_slock); 2663 pve = pmap_remove_pv(opg, pm, va, 0); 2664 pmap_vac_me_harder(opg, pm, 0); 2665 simple_unlock(&opg->mdpage.pvh_slock); 2666 oflags = pve->pv_flags; 2667 2668 #ifdef PMAP_CACHE_VIVT 2669 /* 2670 * If the old mapping was valid (ref/mod 2671 * emulation creates 'invalid' mappings 2672 * initially) then make sure to frob 2673 * the cache. 2674 */ 2675 if ((oflags & PVF_NC) == 0 && 2676 l2pte_valid(opte)) { 2677 if (PV_BEEN_EXECD(oflags)) { 2678 pmap_idcache_wbinv_range(pm, va, 2679 PAGE_SIZE); 2680 } else 2681 if (PV_BEEN_REFD(oflags)) { 2682 pmap_dcache_wb_range(pm, va, 2683 PAGE_SIZE, true, 2684 (oflags & PVF_WRITE) == 0); 2685 } 2686 } 2687 #endif 2688 } else 2689 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2690 if ((flags & PMAP_CANFAIL) == 0) 2691 panic("pmap_enter: no pv entries"); 2692 2693 if (pm != pmap_kernel()) 2694 pmap_free_l2_bucket(pm, l2b, 0); 2695 pmap_release_pmap_lock(pm); 2696 PMAP_MAP_TO_HEAD_UNLOCK(); 2697 NPDEBUG(PDB_ENTER, 2698 printf("pmap_enter: ENOMEM\n")); 2699 return (ENOMEM); 2700 } 2701 2702 pmap_enter_pv(pg, pve, pm, va, nflags); 2703 } 2704 } else { 2705 /* 2706 * We're mapping an unmanaged page. 2707 * These are always readable, and possibly writable, from 2708 * the get go as we don't need to track ref/mod status. 2709 */ 2710 npte |= L2_S_PROTO; 2711 if (prot & VM_PROT_WRITE) 2712 npte |= L2_S_PROT_W; 2713 2714 /* 2715 * Make sure the vector table is mapped cacheable 2716 */ 2717 if (pm != pmap_kernel() && va == vector_page) 2718 npte |= pte_l2_s_cache_mode; 2719 2720 if (opg) { 2721 /* 2722 * Looks like there's an existing 'managed' mapping 2723 * at this address. 2724 */ 2725 simple_lock(&opg->mdpage.pvh_slock); 2726 pve = pmap_remove_pv(opg, pm, va, 0); 2727 pmap_vac_me_harder(opg, pm, 0); 2728 simple_unlock(&opg->mdpage.pvh_slock); 2729 oflags = pve->pv_flags; 2730 2731 #ifdef PMAP_CACHE_VIVT 2732 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2733 if (PV_BEEN_EXECD(oflags)) 2734 pmap_idcache_wbinv_range(pm, va, 2735 PAGE_SIZE); 2736 else 2737 if (PV_BEEN_REFD(oflags)) 2738 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2739 true, (oflags & PVF_WRITE) == 0); 2740 } 2741 #endif 2742 pool_put(&pmap_pv_pool, pve); 2743 } 2744 } 2745 2746 /* 2747 * Make sure userland mappings get the right permissions 2748 */ 2749 if (pm != pmap_kernel() && va != vector_page) 2750 npte |= L2_S_PROT_U; 2751 2752 /* 2753 * Keep the stats up to date 2754 */ 2755 if (opte == 0) { 2756 l2b->l2b_occupancy++; 2757 pm->pm_stats.resident_count++; 2758 } 2759 2760 NPDEBUG(PDB_ENTER, 2761 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2762 2763 /* 2764 * If this is just a wiring change, the two PTEs will be 2765 * identical, so there's no need to update the page table. 2766 */ 2767 if (npte != opte) { 2768 bool is_cached = pmap_is_cached(pm); 2769 2770 *ptep = npte; 2771 if (is_cached) { 2772 /* 2773 * We only need to frob the cache/tlb if this pmap 2774 * is current 2775 */ 2776 PTE_SYNC(ptep); 2777 if (va != vector_page && l2pte_valid(npte)) { 2778 /* 2779 * This mapping is likely to be accessed as 2780 * soon as we return to userland. Fix up the 2781 * L1 entry to avoid taking another 2782 * page/domain fault. 2783 */ 2784 pd_entry_t *pl1pd, l1pd; 2785 2786 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2787 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2788 L1_C_PROTO; 2789 if (*pl1pd != l1pd) { 2790 *pl1pd = l1pd; 2791 PTE_SYNC(pl1pd); 2792 } 2793 } 2794 } 2795 2796 if (PV_BEEN_EXECD(oflags)) 2797 pmap_tlb_flushID_SE(pm, va); 2798 else 2799 if (PV_BEEN_REFD(oflags)) 2800 pmap_tlb_flushD_SE(pm, va); 2801 2802 NPDEBUG(PDB_ENTER, 2803 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2804 is_cached, pm->pm_cstate.cs_all)); 2805 2806 if (pg != NULL) { 2807 simple_lock(&pg->mdpage.pvh_slock); 2808 pmap_vac_me_harder(pg, pm, va); 2809 simple_unlock(&pg->mdpage.pvh_slock); 2810 } 2811 } 2812 2813 pmap_release_pmap_lock(pm); 2814 PMAP_MAP_TO_HEAD_UNLOCK(); 2815 2816 return (0); 2817 } 2818 2819 /* 2820 * pmap_remove() 2821 * 2822 * pmap_remove is responsible for nuking a number of mappings for a range 2823 * of virtual address space in the current pmap. To do this efficiently 2824 * is interesting, because in a number of cases a wide virtual address 2825 * range may be supplied that contains few actual mappings. So, the 2826 * optimisations are: 2827 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 2828 * 2. Build up a list of pages we've hit, up to a maximum, so we can 2829 * maybe do just a partial cache clean. This path of execution is 2830 * complicated by the fact that the cache must be flushed _before_ 2831 * the PTE is nuked, being a VAC :-) 2832 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 2833 * all invalidations until pmap_update(), since pmap_remove_all() has 2834 * already flushed the cache. 2835 * 4. Maybe later fast-case a single page, but I don't think this is 2836 * going to make _that_ much difference overall. 2837 */ 2838 2839 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 2840 2841 void 2842 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 2843 { 2844 struct l2_bucket *l2b; 2845 vaddr_t next_bucket; 2846 pt_entry_t *ptep; 2847 u_int cleanlist_idx, total, cnt; 2848 struct { 2849 vaddr_t va; 2850 pt_entry_t *ptep; 2851 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 2852 u_int mappings, is_exec, is_refd; 2853 2854 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 2855 "eva=%08lx\n", pm, sva, eva)); 2856 2857 /* 2858 * we lock in the pmap => pv_head direction 2859 */ 2860 PMAP_MAP_TO_HEAD_LOCK(); 2861 pmap_acquire_pmap_lock(pm); 2862 2863 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 2864 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2865 if (pm->pm_cstate.cs_tlb == 0) 2866 pm->pm_remove_all = true; 2867 } else 2868 cleanlist_idx = 0; 2869 2870 total = 0; 2871 2872 while (sva < eva) { 2873 /* 2874 * Do one L2 bucket's worth at a time. 2875 */ 2876 next_bucket = L2_NEXT_BUCKET(sva); 2877 if (next_bucket > eva) 2878 next_bucket = eva; 2879 2880 l2b = pmap_get_l2_bucket(pm, sva); 2881 if (l2b == NULL) { 2882 sva = next_bucket; 2883 continue; 2884 } 2885 2886 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2887 2888 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 2889 struct vm_page *pg; 2890 pt_entry_t pte; 2891 paddr_t pa; 2892 2893 pte = *ptep; 2894 2895 if (pte == 0) { 2896 /* Nothing here, move along */ 2897 continue; 2898 } 2899 2900 pa = l2pte_pa(pte); 2901 is_exec = 0; 2902 is_refd = 1; 2903 2904 /* 2905 * Update flags. In a number of circumstances, 2906 * we could cluster a lot of these and do a 2907 * number of sequential pages in one go. 2908 */ 2909 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 2910 struct pv_entry *pve; 2911 simple_lock(&pg->mdpage.pvh_slock); 2912 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 2913 pmap_vac_me_harder(pg, pm, 0); 2914 simple_unlock(&pg->mdpage.pvh_slock); 2915 if (pve != NULL) { 2916 if (pm->pm_remove_all == false) { 2917 is_exec = 2918 PV_BEEN_EXECD(pve->pv_flags); 2919 is_refd = 2920 PV_BEEN_REFD(pve->pv_flags); 2921 } 2922 pool_put(&pmap_pv_pool, pve); 2923 } else 2924 if (skip_wired) { 2925 /* The mapping is wired. Skip it */ 2926 continue; 2927 } 2928 } else 2929 if (skip_wired) { 2930 /* Unmanaged pages are always wired. */ 2931 continue; 2932 } 2933 2934 mappings++; 2935 2936 if (!l2pte_valid(pte)) { 2937 /* 2938 * Ref/Mod emulation is still active for this 2939 * mapping, therefore it is has not yet been 2940 * accessed. No need to frob the cache/tlb. 2941 */ 2942 *ptep = 0; 2943 PTE_SYNC_CURRENT(pm, ptep); 2944 continue; 2945 } 2946 2947 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 2948 /* Add to the clean list. */ 2949 cleanlist[cleanlist_idx].ptep = ptep; 2950 cleanlist[cleanlist_idx].va = 2951 sva | (is_exec & 1); 2952 cleanlist_idx++; 2953 } else 2954 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 2955 /* Nuke everything if needed. */ 2956 #ifdef PMAP_CACHE_VIVT 2957 pmap_idcache_wbinv_all(pm); 2958 #endif 2959 pmap_tlb_flushID(pm); 2960 2961 /* 2962 * Roll back the previous PTE list, 2963 * and zero out the current PTE. 2964 */ 2965 for (cnt = 0; 2966 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 2967 *cleanlist[cnt].ptep = 0; 2968 } 2969 *ptep = 0; 2970 PTE_SYNC(ptep); 2971 cleanlist_idx++; 2972 pm->pm_remove_all = true; 2973 } else { 2974 *ptep = 0; 2975 PTE_SYNC(ptep); 2976 if (pm->pm_remove_all == false) { 2977 if (is_exec) 2978 pmap_tlb_flushID_SE(pm, sva); 2979 else 2980 if (is_refd) 2981 pmap_tlb_flushD_SE(pm, sva); 2982 } 2983 } 2984 } 2985 2986 /* 2987 * Deal with any left overs 2988 */ 2989 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 2990 total += cleanlist_idx; 2991 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 2992 if (pm->pm_cstate.cs_all != 0) { 2993 vaddr_t clva = cleanlist[cnt].va & ~1; 2994 if (cleanlist[cnt].va & 1) { 2995 #ifdef PMAP_CACHE_VIVT 2996 pmap_idcache_wbinv_range(pm, 2997 clva, PAGE_SIZE); 2998 #endif 2999 pmap_tlb_flushID_SE(pm, clva); 3000 } else { 3001 #ifdef PMAP_CACHE_VIVT 3002 pmap_dcache_wb_range(pm, 3003 clva, PAGE_SIZE, true, 3004 false); 3005 #endif 3006 pmap_tlb_flushD_SE(pm, clva); 3007 } 3008 } 3009 *cleanlist[cnt].ptep = 0; 3010 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3011 } 3012 3013 /* 3014 * If it looks like we're removing a whole bunch 3015 * of mappings, it's faster to just write-back 3016 * the whole cache now and defer TLB flushes until 3017 * pmap_update() is called. 3018 */ 3019 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3020 cleanlist_idx = 0; 3021 else { 3022 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3023 #ifdef PMAP_CACHE_VIVT 3024 pmap_idcache_wbinv_all(pm); 3025 #endif 3026 pm->pm_remove_all = true; 3027 } 3028 } 3029 3030 pmap_free_l2_bucket(pm, l2b, mappings); 3031 pm->pm_stats.resident_count -= mappings; 3032 } 3033 3034 pmap_release_pmap_lock(pm); 3035 PMAP_MAP_TO_HEAD_UNLOCK(); 3036 } 3037 3038 /* 3039 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3040 * 3041 * We assume there is already sufficient KVM space available 3042 * to do this, as we can't allocate L2 descriptor tables/metadata 3043 * from here. 3044 */ 3045 void 3046 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 3047 { 3048 struct l2_bucket *l2b; 3049 pt_entry_t *ptep, opte; 3050 #ifdef PMAP_CACHE_VIPT 3051 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3052 struct vm_page *opg; 3053 #endif 3054 3055 3056 NPDEBUG(PDB_KENTER, 3057 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3058 va, pa, prot)); 3059 3060 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3061 KDASSERT(l2b != NULL); 3062 3063 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3064 opte = *ptep; 3065 3066 if (opte == 0) { 3067 PMAPCOUNT(kenter_mappings); 3068 l2b->l2b_occupancy++; 3069 } else { 3070 PMAPCOUNT(kenter_remappings); 3071 #ifdef PMAP_CACHE_VIPT 3072 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3073 if (opg) { 3074 KASSERT(opg != pg); 3075 simple_lock(&opg->mdpage.pvh_slock); 3076 KASSERT(opg->mdpage.pvh_attrs & PVF_KENTRY); 3077 if (PV_IS_EXEC_P(opg->mdpage.pvh_attrs) 3078 && !(opg->mdpage.pvh_attrs & PVF_NC)) { 3079 if (opg->mdpage.pvh_list == NULL) { 3080 opg->mdpage.pvh_attrs &= ~PVF_EXEC; 3081 PMAPCOUNT(exec_discarded_kremove); 3082 } else { 3083 pmap_syncicache_page(opg); 3084 PMAPCOUNT(exec_synced_kremove); 3085 } 3086 } 3087 KASSERT(opg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 3088 opg->mdpage.pvh_attrs &= ~PVF_KENTRY; 3089 pmap_vac_me_harder(opg, NULL, 0); 3090 simple_unlock(&opg->mdpage.pvh_slock); 3091 } 3092 #endif 3093 if (l2pte_valid(opte)) { 3094 #ifdef PMAP_CACHE_VIVT 3095 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3096 #endif 3097 cpu_tlb_flushD_SE(va); 3098 cpu_cpwait(); 3099 } 3100 } 3101 3102 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3103 pte_l2_s_cache_mode; 3104 PTE_SYNC(ptep); 3105 3106 #ifdef PMAP_CACHE_VIPT 3107 if (pg) { 3108 simple_lock(&pg->mdpage.pvh_slock); 3109 if (prot & VM_PROT_WRITE) { 3110 /* 3111 * If they want a writeable page, make sure it 3112 * isn't already mapped in the kernel. 3113 */ 3114 KASSERT((pg->mdpage.pvh_attrs & PVF_KENTRY) == 0); 3115 KASSERT(pg->mdpage.kro_mappings == 0); 3116 pg->mdpage.pvh_attrs |= PVF_KENTRY; 3117 pmap_vac_me_harder(pg, NULL, va); 3118 } else { 3119 KASSERT(pg->mdpage.krw_mappings == 0); 3120 KASSERT(pg->mdpage.urw_mappings == 0); 3121 KASSERT((pg->mdpage.pvh_attrs & PVF_NC) == 0); 3122 pg->mdpage.kro_mappings++; 3123 } 3124 simple_unlock(&pg->mdpage.pvh_slock); 3125 } 3126 #endif 3127 } 3128 3129 void 3130 pmap_kremove(vaddr_t va, vsize_t len) 3131 { 3132 struct l2_bucket *l2b; 3133 pt_entry_t *ptep, *sptep, opte; 3134 vaddr_t next_bucket, eva; 3135 u_int mappings; 3136 #ifdef PMAP_CACHE_VIPT 3137 struct vm_page *opg; 3138 #endif 3139 3140 PMAPCOUNT(kenter_unmappings); 3141 3142 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3143 va, len)); 3144 3145 eva = va + len; 3146 3147 while (va < eva) { 3148 next_bucket = L2_NEXT_BUCKET(va); 3149 if (next_bucket > eva) 3150 next_bucket = eva; 3151 3152 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3153 KDASSERT(l2b != NULL); 3154 3155 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3156 mappings = 0; 3157 3158 while (va < next_bucket) { 3159 opte = *ptep; 3160 #ifdef PMAP_CACHE_VIPT 3161 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3162 if (opg) { 3163 simple_lock(&opg->mdpage.pvh_slock); 3164 if (PV_IS_EXEC_P(opg->mdpage.pvh_attrs) 3165 && !(opg->mdpage.pvh_attrs & PVF_NC)) { 3166 if (opg->mdpage.pvh_list == NULL) { 3167 opg->mdpage.pvh_attrs &= 3168 ~PVF_EXEC; 3169 PMAPCOUNT(exec_discarded_kremove); 3170 } else { 3171 pmap_syncicache_page(opg); 3172 PMAPCOUNT(exec_synced_kremove); 3173 } 3174 } 3175 KASSERT(opg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 3176 if (L2_AP(AP_W) & opte) { 3177 KASSERT(opg->mdpage.pvh_attrs & PVF_KENTRY); 3178 opg->mdpage.pvh_attrs &= ~PVF_KENTRY; 3179 pmap_vac_me_harder(opg, NULL, 0); 3180 } else { 3181 KASSERT(opg->mdpage.kro_mappings > 0); 3182 opg->mdpage.kro_mappings--; 3183 } 3184 simple_unlock(&opg->mdpage.pvh_slock); 3185 } 3186 #endif 3187 if (l2pte_valid(opte)) { 3188 #ifdef PMAP_CACHE_VIVT 3189 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3190 #endif 3191 cpu_tlb_flushD_SE(va); 3192 } 3193 if (opte) { 3194 *ptep = 0; 3195 mappings++; 3196 } 3197 va += PAGE_SIZE; 3198 ptep++; 3199 } 3200 KDASSERT(mappings <= l2b->l2b_occupancy); 3201 l2b->l2b_occupancy -= mappings; 3202 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3203 } 3204 cpu_cpwait(); 3205 } 3206 3207 bool 3208 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3209 { 3210 struct l2_dtable *l2; 3211 pd_entry_t *pl1pd, l1pd; 3212 pt_entry_t *ptep, pte; 3213 paddr_t pa; 3214 u_int l1idx; 3215 3216 pmap_acquire_pmap_lock(pm); 3217 3218 l1idx = L1_IDX(va); 3219 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3220 l1pd = *pl1pd; 3221 3222 if (l1pte_section_p(l1pd)) { 3223 /* 3224 * These should only happen for pmap_kernel() 3225 */ 3226 KDASSERT(pm == pmap_kernel()); 3227 pmap_release_pmap_lock(pm); 3228 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3229 } else { 3230 /* 3231 * Note that we can't rely on the validity of the L1 3232 * descriptor as an indication that a mapping exists. 3233 * We have to look it up in the L2 dtable. 3234 */ 3235 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3236 3237 if (l2 == NULL || 3238 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3239 pmap_release_pmap_lock(pm); 3240 return false; 3241 } 3242 3243 ptep = &ptep[l2pte_index(va)]; 3244 pte = *ptep; 3245 pmap_release_pmap_lock(pm); 3246 3247 if (pte == 0) 3248 return false; 3249 3250 switch (pte & L2_TYPE_MASK) { 3251 case L2_TYPE_L: 3252 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3253 break; 3254 3255 default: 3256 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3257 break; 3258 } 3259 } 3260 3261 if (pap != NULL) 3262 *pap = pa; 3263 3264 return true; 3265 } 3266 3267 void 3268 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3269 { 3270 struct l2_bucket *l2b; 3271 pt_entry_t *ptep, pte; 3272 vaddr_t next_bucket; 3273 u_int flags; 3274 u_int clr_mask; 3275 int flush; 3276 3277 NPDEBUG(PDB_PROTECT, 3278 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3279 pm, sva, eva, prot)); 3280 3281 if ((prot & VM_PROT_READ) == 0) { 3282 pmap_remove(pm, sva, eva); 3283 return; 3284 } 3285 3286 if (prot & VM_PROT_WRITE) { 3287 /* 3288 * If this is a read->write transition, just ignore it and let 3289 * uvm_fault() take care of it later. 3290 */ 3291 return; 3292 } 3293 3294 PMAP_MAP_TO_HEAD_LOCK(); 3295 pmap_acquire_pmap_lock(pm); 3296 3297 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3298 flags = 0; 3299 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3300 3301 while (sva < eva) { 3302 next_bucket = L2_NEXT_BUCKET(sva); 3303 if (next_bucket > eva) 3304 next_bucket = eva; 3305 3306 l2b = pmap_get_l2_bucket(pm, sva); 3307 if (l2b == NULL) { 3308 sva = next_bucket; 3309 continue; 3310 } 3311 3312 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3313 3314 while (sva < next_bucket) { 3315 pte = *ptep; 3316 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3317 struct vm_page *pg; 3318 u_int f; 3319 3320 #ifdef PMAP_CACHE_VIVT 3321 /* 3322 * OK, at this point, we know we're doing 3323 * write-protect operation. If the pmap is 3324 * active, write-back the page. 3325 */ 3326 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3327 false, false); 3328 #endif 3329 3330 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3331 pte &= ~L2_S_PROT_W; 3332 *ptep = pte; 3333 PTE_SYNC(ptep); 3334 3335 if (pg != NULL) { 3336 simple_lock(&pg->mdpage.pvh_slock); 3337 f = pmap_modify_pv(pg, pm, sva, 3338 clr_mask, 0); 3339 pmap_vac_me_harder(pg, pm, sva); 3340 simple_unlock(&pg->mdpage.pvh_slock); 3341 } else 3342 f = PVF_REF | PVF_EXEC; 3343 3344 if (flush >= 0) { 3345 flush++; 3346 flags |= f; 3347 } else 3348 if (PV_BEEN_EXECD(f)) 3349 pmap_tlb_flushID_SE(pm, sva); 3350 else 3351 if (PV_BEEN_REFD(f)) 3352 pmap_tlb_flushD_SE(pm, sva); 3353 } 3354 3355 sva += PAGE_SIZE; 3356 ptep++; 3357 } 3358 } 3359 3360 pmap_release_pmap_lock(pm); 3361 PMAP_MAP_TO_HEAD_UNLOCK(); 3362 3363 if (flush) { 3364 if (PV_BEEN_EXECD(flags)) 3365 pmap_tlb_flushID(pm); 3366 else 3367 if (PV_BEEN_REFD(flags)) 3368 pmap_tlb_flushD(pm); 3369 } 3370 } 3371 3372 void 3373 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3374 { 3375 struct l2_bucket *l2b; 3376 pt_entry_t *ptep; 3377 vaddr_t next_bucket; 3378 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3379 3380 NPDEBUG(PDB_EXEC, 3381 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3382 pm, sva, eva)); 3383 3384 PMAP_MAP_TO_HEAD_LOCK(); 3385 pmap_acquire_pmap_lock(pm); 3386 3387 while (sva < eva) { 3388 next_bucket = L2_NEXT_BUCKET(sva); 3389 if (next_bucket > eva) 3390 next_bucket = eva; 3391 3392 l2b = pmap_get_l2_bucket(pm, sva); 3393 if (l2b == NULL) { 3394 sva = next_bucket; 3395 continue; 3396 } 3397 3398 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3399 sva < next_bucket; 3400 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3401 if (l2pte_valid(*ptep)) { 3402 cpu_icache_sync_range(sva, 3403 min(page_size, eva - sva)); 3404 } 3405 } 3406 } 3407 3408 pmap_release_pmap_lock(pm); 3409 PMAP_MAP_TO_HEAD_UNLOCK(); 3410 } 3411 3412 void 3413 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3414 { 3415 3416 NPDEBUG(PDB_PROTECT, 3417 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3418 pg, VM_PAGE_TO_PHYS(pg), prot)); 3419 3420 switch(prot) { 3421 return; 3422 case VM_PROT_READ|VM_PROT_WRITE: 3423 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3424 pmap_clearbit(pg, PVF_EXEC); 3425 break; 3426 #endif 3427 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3428 break; 3429 3430 case VM_PROT_READ: 3431 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3432 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3433 break; 3434 #endif 3435 case VM_PROT_READ|VM_PROT_EXECUTE: 3436 pmap_clearbit(pg, PVF_WRITE); 3437 break; 3438 3439 default: 3440 pmap_page_remove(pg); 3441 break; 3442 } 3443 } 3444 3445 /* 3446 * pmap_clear_modify: 3447 * 3448 * Clear the "modified" attribute for a page. 3449 */ 3450 bool 3451 pmap_clear_modify(struct vm_page *pg) 3452 { 3453 bool rv; 3454 3455 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3456 rv = true; 3457 pmap_clearbit(pg, PVF_MOD); 3458 } else 3459 rv = false; 3460 3461 return (rv); 3462 } 3463 3464 /* 3465 * pmap_clear_reference: 3466 * 3467 * Clear the "referenced" attribute for a page. 3468 */ 3469 bool 3470 pmap_clear_reference(struct vm_page *pg) 3471 { 3472 bool rv; 3473 3474 if (pg->mdpage.pvh_attrs & PVF_REF) { 3475 rv = true; 3476 pmap_clearbit(pg, PVF_REF); 3477 } else 3478 rv = false; 3479 3480 return (rv); 3481 } 3482 3483 /* 3484 * pmap_is_modified: 3485 * 3486 * Test if a page has the "modified" attribute. 3487 */ 3488 /* See <arm/arm32/pmap.h> */ 3489 3490 /* 3491 * pmap_is_referenced: 3492 * 3493 * Test if a page has the "referenced" attribute. 3494 */ 3495 /* See <arm/arm32/pmap.h> */ 3496 3497 int 3498 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3499 { 3500 struct l2_dtable *l2; 3501 struct l2_bucket *l2b; 3502 pd_entry_t *pl1pd, l1pd; 3503 pt_entry_t *ptep, pte; 3504 paddr_t pa; 3505 u_int l1idx; 3506 int rv = 0; 3507 3508 PMAP_MAP_TO_HEAD_LOCK(); 3509 pmap_acquire_pmap_lock(pm); 3510 3511 l1idx = L1_IDX(va); 3512 3513 /* 3514 * If there is no l2_dtable for this address, then the process 3515 * has no business accessing it. 3516 * 3517 * Note: This will catch userland processes trying to access 3518 * kernel addresses. 3519 */ 3520 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3521 if (l2 == NULL) 3522 goto out; 3523 3524 /* 3525 * Likewise if there is no L2 descriptor table 3526 */ 3527 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3528 if (l2b->l2b_kva == NULL) 3529 goto out; 3530 3531 /* 3532 * Check the PTE itself. 3533 */ 3534 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3535 pte = *ptep; 3536 if (pte == 0) 3537 goto out; 3538 3539 /* 3540 * Catch a userland access to the vector page mapped at 0x0 3541 */ 3542 if (user && (pte & L2_S_PROT_U) == 0) 3543 goto out; 3544 3545 pa = l2pte_pa(pte); 3546 3547 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3548 /* 3549 * This looks like a good candidate for "page modified" 3550 * emulation... 3551 */ 3552 struct pv_entry *pv; 3553 struct vm_page *pg; 3554 3555 /* Extract the physical address of the page */ 3556 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3557 goto out; 3558 3559 /* Get the current flags for this page. */ 3560 simple_lock(&pg->mdpage.pvh_slock); 3561 3562 pv = pmap_find_pv(pg, pm, va); 3563 if (pv == NULL) { 3564 simple_unlock(&pg->mdpage.pvh_slock); 3565 goto out; 3566 } 3567 3568 /* 3569 * Do the flags say this page is writable? If not then it 3570 * is a genuine write fault. If yes then the write fault is 3571 * our fault as we did not reflect the write access in the 3572 * PTE. Now we know a write has occurred we can correct this 3573 * and also set the modified bit 3574 */ 3575 if ((pv->pv_flags & PVF_WRITE) == 0) { 3576 simple_unlock(&pg->mdpage.pvh_slock); 3577 goto out; 3578 } 3579 3580 NPDEBUG(PDB_FOLLOW, 3581 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3582 pm, va, VM_PAGE_TO_PHYS(pg))); 3583 3584 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 3585 pv->pv_flags |= PVF_REF | PVF_MOD; 3586 simple_unlock(&pg->mdpage.pvh_slock); 3587 3588 /* 3589 * Re-enable write permissions for the page. No need to call 3590 * pmap_vac_me_harder(), since this is just a 3591 * modified-emulation fault, and the PVF_WRITE bit isn't 3592 * changing. We've already set the cacheable bits based on 3593 * the assumption that we can write to this page. 3594 */ 3595 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3596 PTE_SYNC(ptep); 3597 rv = 1; 3598 } else 3599 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3600 /* 3601 * This looks like a good candidate for "page referenced" 3602 * emulation. 3603 */ 3604 struct pv_entry *pv; 3605 struct vm_page *pg; 3606 3607 /* Extract the physical address of the page */ 3608 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3609 goto out; 3610 3611 /* Get the current flags for this page. */ 3612 simple_lock(&pg->mdpage.pvh_slock); 3613 3614 pv = pmap_find_pv(pg, pm, va); 3615 if (pv == NULL) { 3616 simple_unlock(&pg->mdpage.pvh_slock); 3617 goto out; 3618 } 3619 3620 pg->mdpage.pvh_attrs |= PVF_REF; 3621 pv->pv_flags |= PVF_REF; 3622 simple_unlock(&pg->mdpage.pvh_slock); 3623 3624 NPDEBUG(PDB_FOLLOW, 3625 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3626 pm, va, VM_PAGE_TO_PHYS(pg))); 3627 3628 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3629 PTE_SYNC(ptep); 3630 rv = 1; 3631 } 3632 3633 /* 3634 * We know there is a valid mapping here, so simply 3635 * fix up the L1 if necessary. 3636 */ 3637 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3638 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3639 if (*pl1pd != l1pd) { 3640 *pl1pd = l1pd; 3641 PTE_SYNC(pl1pd); 3642 rv = 1; 3643 } 3644 3645 #ifdef CPU_SA110 3646 /* 3647 * There are bugs in the rev K SA110. This is a check for one 3648 * of them. 3649 */ 3650 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3651 curcpu()->ci_arm_cpurev < 3) { 3652 /* Always current pmap */ 3653 if (l2pte_valid(pte)) { 3654 extern int kernel_debug; 3655 if (kernel_debug & 1) { 3656 struct proc *p = curlwp->l_proc; 3657 printf("prefetch_abort: page is already " 3658 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3659 printf("prefetch_abort: pc=%08lx proc=%p " 3660 "process=%s\n", va, p, p->p_comm); 3661 printf("prefetch_abort: far=%08x fs=%x\n", 3662 cpu_faultaddress(), cpu_faultstatus()); 3663 } 3664 #ifdef DDB 3665 if (kernel_debug & 2) 3666 Debugger(); 3667 #endif 3668 rv = 1; 3669 } 3670 } 3671 #endif /* CPU_SA110 */ 3672 3673 #ifdef DEBUG 3674 /* 3675 * If 'rv == 0' at this point, it generally indicates that there is a 3676 * stale TLB entry for the faulting address. This happens when two or 3677 * more processes are sharing an L1. Since we don't flush the TLB on 3678 * a context switch between such processes, we can take domain faults 3679 * for mappings which exist at the same VA in both processes. EVEN IF 3680 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3681 * example. 3682 * 3683 * This is extremely likely to happen if pmap_enter() updated the L1 3684 * entry for a recently entered mapping. In this case, the TLB is 3685 * flushed for the new mapping, but there may still be TLB entries for 3686 * other mappings belonging to other processes in the 1MB range 3687 * covered by the L1 entry. 3688 * 3689 * Since 'rv == 0', we know that the L1 already contains the correct 3690 * value, so the fault must be due to a stale TLB entry. 3691 * 3692 * Since we always need to flush the TLB anyway in the case where we 3693 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 3694 * stale TLB entries dynamically. 3695 * 3696 * However, the above condition can ONLY happen if the current L1 is 3697 * being shared. If it happens when the L1 is unshared, it indicates 3698 * that other parts of the pmap are not doing their job WRT managing 3699 * the TLB. 3700 */ 3701 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 3702 extern int last_fault_code; 3703 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 3704 pm, va, ftype); 3705 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 3706 l2, l2b, ptep, pl1pd); 3707 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 3708 pte, l1pd, last_fault_code); 3709 #ifdef DDB 3710 Debugger(); 3711 #endif 3712 } 3713 #endif 3714 3715 cpu_tlb_flushID_SE(va); 3716 cpu_cpwait(); 3717 3718 rv = 1; 3719 3720 out: 3721 pmap_release_pmap_lock(pm); 3722 PMAP_MAP_TO_HEAD_UNLOCK(); 3723 3724 return (rv); 3725 } 3726 3727 /* 3728 * pmap_collect: free resources held by a pmap 3729 * 3730 * => optional function. 3731 * => called when a process is swapped out to free memory. 3732 */ 3733 void 3734 pmap_collect(pmap_t pm) 3735 { 3736 3737 #ifdef PMAP_CACHE_VIVT 3738 pmap_idcache_wbinv_all(pm); 3739 #endif 3740 pm->pm_remove_all = true; 3741 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 3742 pmap_update(pm); 3743 PMAPCOUNT(collects); 3744 } 3745 3746 /* 3747 * Routine: pmap_procwr 3748 * 3749 * Function: 3750 * Synchronize caches corresponding to [addr, addr+len) in p. 3751 * 3752 */ 3753 void 3754 pmap_procwr(struct proc *p, vaddr_t va, int len) 3755 { 3756 /* We only need to do anything if it is the current process. */ 3757 if (p == curproc) 3758 cpu_icache_sync_range(va, len); 3759 } 3760 3761 /* 3762 * Routine: pmap_unwire 3763 * Function: Clear the wired attribute for a map/virtual-address pair. 3764 * 3765 * In/out conditions: 3766 * The mapping must already exist in the pmap. 3767 */ 3768 void 3769 pmap_unwire(pmap_t pm, vaddr_t va) 3770 { 3771 struct l2_bucket *l2b; 3772 pt_entry_t *ptep, pte; 3773 struct vm_page *pg; 3774 paddr_t pa; 3775 3776 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 3777 3778 PMAP_MAP_TO_HEAD_LOCK(); 3779 pmap_acquire_pmap_lock(pm); 3780 3781 l2b = pmap_get_l2_bucket(pm, va); 3782 KDASSERT(l2b != NULL); 3783 3784 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3785 pte = *ptep; 3786 3787 /* Extract the physical address of the page */ 3788 pa = l2pte_pa(pte); 3789 3790 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3791 /* Update the wired bit in the pv entry for this page. */ 3792 simple_lock(&pg->mdpage.pvh_slock); 3793 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 3794 simple_unlock(&pg->mdpage.pvh_slock); 3795 } 3796 3797 pmap_release_pmap_lock(pm); 3798 PMAP_MAP_TO_HEAD_UNLOCK(); 3799 } 3800 3801 void 3802 pmap_activate(struct lwp *l) 3803 { 3804 extern int block_userspace_access; 3805 pmap_t opm, npm, rpm; 3806 uint32_t odacr, ndacr; 3807 int oldirqstate; 3808 3809 /* 3810 * If activating a non-current lwp or the current lwp is 3811 * already active, just return. 3812 */ 3813 if (l != curlwp || 3814 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 3815 return; 3816 3817 npm = l->l_proc->p_vmspace->vm_map.pmap; 3818 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3819 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 3820 3821 /* 3822 * If TTB and DACR are unchanged, short-circuit all the 3823 * TLB/cache management stuff. 3824 */ 3825 if (pmap_previous_active_lwp != NULL) { 3826 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 3827 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3828 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 3829 3830 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 3831 goto all_done; 3832 } else 3833 opm = NULL; 3834 3835 PMAPCOUNT(activations); 3836 block_userspace_access = 1; 3837 3838 /* 3839 * If switching to a user vmspace which is different to the 3840 * most recent one, and the most recent one is potentially 3841 * live in the cache, we must write-back and invalidate the 3842 * entire cache. 3843 */ 3844 rpm = pmap_recent_user; 3845 if (npm != pmap_kernel() && rpm && npm != rpm && 3846 rpm->pm_cstate.cs_cache) { 3847 rpm->pm_cstate.cs_cache = 0; 3848 #ifdef PMAP_CACHE_VIVT 3849 cpu_idcache_wbinv_all(); 3850 #endif 3851 } 3852 3853 /* No interrupts while we frob the TTB/DACR */ 3854 oldirqstate = disable_interrupts(I32_bit | F32_bit); 3855 3856 /* 3857 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 3858 * entry corresponding to 'vector_page' in the incoming L1 table 3859 * before switching to it otherwise subsequent interrupts/exceptions 3860 * (including domain faults!) will jump into hyperspace. 3861 */ 3862 if (npm->pm_pl1vec != NULL) { 3863 cpu_tlb_flushID_SE((u_int)vector_page); 3864 cpu_cpwait(); 3865 *npm->pm_pl1vec = npm->pm_l1vec; 3866 PTE_SYNC(npm->pm_pl1vec); 3867 } 3868 3869 cpu_domains(ndacr); 3870 3871 if (npm == pmap_kernel() || npm == rpm) { 3872 /* 3873 * Switching to a kernel thread, or back to the 3874 * same user vmspace as before... Simply update 3875 * the TTB (no TLB flush required) 3876 */ 3877 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 3878 "r"(npm->pm_l1->l1_physaddr)); 3879 cpu_cpwait(); 3880 } else { 3881 /* 3882 * Otherwise, update TTB and flush TLB 3883 */ 3884 cpu_context_switch(npm->pm_l1->l1_physaddr); 3885 if (rpm != NULL) 3886 rpm->pm_cstate.cs_tlb = 0; 3887 } 3888 3889 restore_interrupts(oldirqstate); 3890 3891 block_userspace_access = 0; 3892 3893 all_done: 3894 /* 3895 * The new pmap is resident. Make sure it's marked 3896 * as resident in the cache/TLB. 3897 */ 3898 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3899 if (npm != pmap_kernel()) 3900 pmap_recent_user = npm; 3901 3902 /* The old pmap is not longer active */ 3903 if (opm != NULL) 3904 opm->pm_activated = false; 3905 3906 /* But the new one is */ 3907 npm->pm_activated = true; 3908 } 3909 3910 void 3911 pmap_deactivate(struct lwp *l) 3912 { 3913 3914 /* 3915 * If the process is exiting, make sure pmap_activate() does 3916 * a full MMU context-switch and cache flush, which we might 3917 * otherwise skip. See PR port-arm/38950. 3918 */ 3919 if (l->l_proc->p_sflag & PS_WEXIT) 3920 pmap_previous_active_lwp = NULL; 3921 3922 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 3923 } 3924 3925 void 3926 pmap_update(pmap_t pm) 3927 { 3928 3929 if (pm->pm_remove_all) { 3930 /* 3931 * Finish up the pmap_remove_all() optimisation by flushing 3932 * the TLB. 3933 */ 3934 pmap_tlb_flushID(pm); 3935 pm->pm_remove_all = false; 3936 } 3937 3938 if (pmap_is_current(pm)) { 3939 /* 3940 * If we're dealing with a current userland pmap, move its L1 3941 * to the end of the LRU. 3942 */ 3943 if (pm != pmap_kernel()) 3944 pmap_use_l1(pm); 3945 3946 /* 3947 * We can assume we're done with frobbing the cache/tlb for 3948 * now. Make sure any future pmap ops don't skip cache/tlb 3949 * flushes. 3950 */ 3951 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3952 } 3953 3954 PMAPCOUNT(updates); 3955 3956 /* 3957 * make sure TLB/cache operations have completed. 3958 */ 3959 cpu_cpwait(); 3960 } 3961 3962 void 3963 pmap_remove_all(pmap_t pm) 3964 { 3965 3966 /* 3967 * The vmspace described by this pmap is about to be torn down. 3968 * Until pmap_update() is called, UVM will only make calls 3969 * to pmap_remove(). We can make life much simpler by flushing 3970 * the cache now, and deferring TLB invalidation to pmap_update(). 3971 */ 3972 #ifdef PMAP_CACHE_VIVT 3973 pmap_idcache_wbinv_all(pm); 3974 #endif 3975 pm->pm_remove_all = true; 3976 } 3977 3978 /* 3979 * Retire the given physical map from service. 3980 * Should only be called if the map contains no valid mappings. 3981 */ 3982 void 3983 pmap_destroy(pmap_t pm) 3984 { 3985 u_int count; 3986 3987 if (pm == NULL) 3988 return; 3989 3990 if (pm->pm_remove_all) { 3991 pmap_tlb_flushID(pm); 3992 pm->pm_remove_all = false; 3993 } 3994 3995 /* 3996 * Drop reference count 3997 */ 3998 mutex_enter(&pm->pm_lock); 3999 count = --pm->pm_obj.uo_refs; 4000 mutex_exit(&pm->pm_lock); 4001 if (count > 0) { 4002 if (pmap_is_current(pm)) { 4003 if (pm != pmap_kernel()) 4004 pmap_use_l1(pm); 4005 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4006 } 4007 return; 4008 } 4009 4010 /* 4011 * reference count is zero, free pmap resources and then free pmap. 4012 */ 4013 4014 if (vector_page < KERNEL_BASE) { 4015 KDASSERT(!pmap_is_current(pm)); 4016 4017 /* Remove the vector page mapping */ 4018 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4019 pmap_update(pm); 4020 } 4021 4022 LIST_REMOVE(pm, pm_list); 4023 4024 pmap_free_l1(pm); 4025 4026 if (pmap_recent_user == pm) 4027 pmap_recent_user = NULL; 4028 4029 UVM_OBJ_DESTROY(&pm->pm_obj); 4030 4031 /* return the pmap to the pool */ 4032 pool_cache_put(&pmap_cache, pm); 4033 } 4034 4035 4036 /* 4037 * void pmap_reference(pmap_t pm) 4038 * 4039 * Add a reference to the specified pmap. 4040 */ 4041 void 4042 pmap_reference(pmap_t pm) 4043 { 4044 4045 if (pm == NULL) 4046 return; 4047 4048 pmap_use_l1(pm); 4049 4050 mutex_enter(&pm->pm_lock); 4051 pm->pm_obj.uo_refs++; 4052 mutex_exit(&pm->pm_lock); 4053 } 4054 4055 #if ARM_MMU_V6 > 0 4056 4057 static struct evcnt pmap_prefer_nochange_ev = 4058 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4059 static struct evcnt pmap_prefer_change_ev = 4060 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4061 4062 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4063 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4064 4065 void 4066 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4067 { 4068 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4069 vaddr_t va = *vap; 4070 vaddr_t diff = (hint - va) & mask; 4071 if (diff == 0) { 4072 pmap_prefer_nochange_ev.ev_count++; 4073 } else { 4074 pmap_prefer_change_ev.ev_count++; 4075 if (__predict_false(td)) 4076 va -= mask + 1; 4077 *vap = va + diff; 4078 } 4079 } 4080 #endif /* ARM_MMU_V6 */ 4081 4082 /* 4083 * pmap_zero_page() 4084 * 4085 * Zero a given physical page by mapping it at a page hook point. 4086 * In doing the zero page op, the page we zero is mapped cachable, as with 4087 * StrongARM accesses to non-cached pages are non-burst making writing 4088 * _any_ bulk data very slow. 4089 */ 4090 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4091 void 4092 pmap_zero_page_generic(paddr_t phys) 4093 { 4094 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4095 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4096 #endif 4097 #ifdef PMAP_CACHE_VIPT 4098 /* Choose the last page color it had, if any */ 4099 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4100 #else 4101 const vsize_t va_offset = 0; 4102 #endif 4103 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4104 4105 #ifdef DEBUG 4106 if (pg->mdpage.pvh_list != NULL) 4107 panic("pmap_zero_page: page has mappings"); 4108 #endif 4109 4110 KDASSERT((phys & PGOFSET) == 0); 4111 4112 /* 4113 * Hook in the page, zero it, and purge the cache for that 4114 * zeroed page. Invalidate the TLB as needed. 4115 */ 4116 *ptep = L2_S_PROTO | phys | 4117 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4118 PTE_SYNC(ptep); 4119 cpu_tlb_flushD_SE(cdstp + va_offset); 4120 cpu_cpwait(); 4121 bzero_page(cdstp + va_offset); 4122 /* 4123 * Unmap the page. 4124 */ 4125 *ptep = 0; 4126 PTE_SYNC(ptep); 4127 cpu_tlb_flushD_SE(cdstp + va_offset); 4128 #ifdef PMAP_CACHE_VIVT 4129 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4130 #endif 4131 #ifdef PMAP_CACHE_VIPT 4132 /* 4133 * This page is now cache resident so it now has a page color. 4134 * Any contents have been obliterated so clear the EXEC flag. 4135 */ 4136 if (!pmap_is_page_colored_p(pg)) { 4137 PMAPCOUNT(vac_color_new); 4138 pg->mdpage.pvh_attrs |= PVF_COLORED; 4139 } 4140 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4141 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4142 PMAPCOUNT(exec_discarded_zero); 4143 } 4144 #endif 4145 } 4146 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4147 4148 #if ARM_MMU_XSCALE == 1 4149 void 4150 pmap_zero_page_xscale(paddr_t phys) 4151 { 4152 #ifdef DEBUG 4153 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4154 4155 if (pg->mdpage.pvh_list != NULL) 4156 panic("pmap_zero_page: page has mappings"); 4157 #endif 4158 4159 KDASSERT((phys & PGOFSET) == 0); 4160 4161 /* 4162 * Hook in the page, zero it, and purge the cache for that 4163 * zeroed page. Invalidate the TLB as needed. 4164 */ 4165 *cdst_pte = L2_S_PROTO | phys | 4166 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4167 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4168 PTE_SYNC(cdst_pte); 4169 cpu_tlb_flushD_SE(cdstp); 4170 cpu_cpwait(); 4171 bzero_page(cdstp); 4172 xscale_cache_clean_minidata(); 4173 } 4174 #endif /* ARM_MMU_XSCALE == 1 */ 4175 4176 /* pmap_pageidlezero() 4177 * 4178 * The same as above, except that we assume that the page is not 4179 * mapped. This means we never have to flush the cache first. Called 4180 * from the idle loop. 4181 */ 4182 bool 4183 pmap_pageidlezero(paddr_t phys) 4184 { 4185 unsigned int i; 4186 int *ptr; 4187 bool rv = true; 4188 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4189 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4190 #endif 4191 #ifdef PMAP_CACHE_VIPT 4192 /* Choose the last page color it had, if any */ 4193 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4194 #else 4195 const vsize_t va_offset = 0; 4196 #endif 4197 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4198 4199 4200 #ifdef DEBUG 4201 if (pg->mdpage.pvh_list != NULL) 4202 panic("pmap_pageidlezero: page has mappings"); 4203 #endif 4204 4205 KDASSERT((phys & PGOFSET) == 0); 4206 4207 /* 4208 * Hook in the page, zero it, and purge the cache for that 4209 * zeroed page. Invalidate the TLB as needed. 4210 */ 4211 *ptep = L2_S_PROTO | phys | 4212 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4213 PTE_SYNC(ptep); 4214 cpu_tlb_flushD_SE(cdstp + va_offset); 4215 cpu_cpwait(); 4216 4217 for (i = 0, ptr = (int *)(cdstp + va_offset); 4218 i < (PAGE_SIZE / sizeof(int)); i++) { 4219 if (sched_curcpu_runnable_p() != 0) { 4220 /* 4221 * A process has become ready. Abort now, 4222 * so we don't keep it waiting while we 4223 * do slow memory access to finish this 4224 * page. 4225 */ 4226 rv = false; 4227 break; 4228 } 4229 *ptr++ = 0; 4230 } 4231 4232 #ifdef PMAP_CACHE_VIVT 4233 if (rv) 4234 /* 4235 * if we aborted we'll rezero this page again later so don't 4236 * purge it unless we finished it 4237 */ 4238 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4239 #elif defined(PMAP_CACHE_VIPT) 4240 /* 4241 * This page is now cache resident so it now has a page color. 4242 * Any contents have been obliterated so clear the EXEC flag. 4243 */ 4244 if (!pmap_is_page_colored_p(pg)) { 4245 PMAPCOUNT(vac_color_new); 4246 pg->mdpage.pvh_attrs |= PVF_COLORED; 4247 } 4248 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4249 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4250 PMAPCOUNT(exec_discarded_zero); 4251 } 4252 #endif 4253 /* 4254 * Unmap the page. 4255 */ 4256 *ptep = 0; 4257 PTE_SYNC(ptep); 4258 cpu_tlb_flushD_SE(cdstp + va_offset); 4259 4260 return (rv); 4261 } 4262 4263 /* 4264 * pmap_copy_page() 4265 * 4266 * Copy one physical page into another, by mapping the pages into 4267 * hook points. The same comment regarding cachability as in 4268 * pmap_zero_page also applies here. 4269 */ 4270 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4271 void 4272 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4273 { 4274 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4275 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4276 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4277 #endif 4278 #ifdef PMAP_CACHE_VIPT 4279 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4280 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4281 #else 4282 const vsize_t src_va_offset = 0; 4283 const vsize_t dst_va_offset = 0; 4284 #endif 4285 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4286 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4287 4288 #ifdef DEBUG 4289 if (dst_pg->mdpage.pvh_list != NULL) 4290 panic("pmap_copy_page: dst page has mappings"); 4291 #endif 4292 4293 #ifdef PMAP_CACHE_VIPT 4294 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4295 #endif 4296 KDASSERT((src & PGOFSET) == 0); 4297 KDASSERT((dst & PGOFSET) == 0); 4298 4299 /* 4300 * Clean the source page. Hold the source page's lock for 4301 * the duration of the copy so that no other mappings can 4302 * be created while we have a potentially aliased mapping. 4303 */ 4304 simple_lock(&src_pg->mdpage.pvh_slock); 4305 #ifdef PMAP_CACHE_VIVT 4306 (void) pmap_clean_page(src_pg->mdpage.pvh_list, true); 4307 #endif 4308 4309 /* 4310 * Map the pages into the page hook points, copy them, and purge 4311 * the cache for the appropriate page. Invalidate the TLB 4312 * as required. 4313 */ 4314 *src_ptep = L2_S_PROTO 4315 | src 4316 #ifdef PMAP_CACHE_VIPT 4317 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4318 #endif 4319 #ifdef PMAP_CACHE_VIVT 4320 | pte_l2_s_cache_mode 4321 #endif 4322 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4323 *dst_ptep = L2_S_PROTO | dst | 4324 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4325 PTE_SYNC(src_ptep); 4326 PTE_SYNC(dst_ptep); 4327 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4328 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4329 cpu_cpwait(); 4330 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4331 #ifdef PMAP_CACHE_VIVT 4332 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4333 #endif 4334 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4335 #ifdef PMAP_CACHE_VIVT 4336 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4337 #endif 4338 /* 4339 * Unmap the pages. 4340 */ 4341 *src_ptep = 0; 4342 *dst_ptep = 0; 4343 PTE_SYNC(src_ptep); 4344 PTE_SYNC(dst_ptep); 4345 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4346 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4347 #ifdef PMAP_CACHE_VIPT 4348 /* 4349 * Now that the destination page is in the cache, mark it as colored. 4350 * If this was an exec page, discard it. 4351 */ 4352 if (!pmap_is_page_colored_p(dst_pg)) { 4353 PMAPCOUNT(vac_color_new); 4354 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4355 } 4356 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4357 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4358 PMAPCOUNT(exec_discarded_copy); 4359 } 4360 #endif 4361 } 4362 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4363 4364 #if ARM_MMU_XSCALE == 1 4365 void 4366 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4367 { 4368 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4369 #ifdef DEBUG 4370 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4371 4372 if (dst_pg->mdpage.pvh_list != NULL) 4373 panic("pmap_copy_page: dst page has mappings"); 4374 #endif 4375 4376 KDASSERT((src & PGOFSET) == 0); 4377 KDASSERT((dst & PGOFSET) == 0); 4378 4379 /* 4380 * Clean the source page. Hold the source page's lock for 4381 * the duration of the copy so that no other mappings can 4382 * be created while we have a potentially aliased mapping. 4383 */ 4384 simple_lock(&src_pg->mdpage.pvh_slock); 4385 #ifdef PMAP_CACHE_VIVT 4386 (void) pmap_clean_page(src_pg->mdpage.pvh_list, true); 4387 #endif 4388 4389 /* 4390 * Map the pages into the page hook points, copy them, and purge 4391 * the cache for the appropriate page. Invalidate the TLB 4392 * as required. 4393 */ 4394 *csrc_pte = L2_S_PROTO | src | 4395 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4396 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4397 PTE_SYNC(csrc_pte); 4398 *cdst_pte = L2_S_PROTO | dst | 4399 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4400 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4401 PTE_SYNC(cdst_pte); 4402 cpu_tlb_flushD_SE(csrcp); 4403 cpu_tlb_flushD_SE(cdstp); 4404 cpu_cpwait(); 4405 bcopy_page(csrcp, cdstp); 4406 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4407 xscale_cache_clean_minidata(); 4408 } 4409 #endif /* ARM_MMU_XSCALE == 1 */ 4410 4411 /* 4412 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4413 * 4414 * Return the start and end addresses of the kernel's virtual space. 4415 * These values are setup in pmap_bootstrap and are updated as pages 4416 * are allocated. 4417 */ 4418 void 4419 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4420 { 4421 *start = virtual_avail; 4422 *end = virtual_end; 4423 } 4424 4425 /* 4426 * Helper function for pmap_grow_l2_bucket() 4427 */ 4428 static inline int 4429 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4430 { 4431 struct l2_bucket *l2b; 4432 pt_entry_t *ptep; 4433 paddr_t pa; 4434 4435 if (uvm.page_init_done == false) { 4436 #ifdef PMAP_STEAL_MEMORY 4437 pv_addr_t pv; 4438 pmap_boot_pagealloc(PAGE_SIZE, 4439 #ifdef PMAP_CACHE_VIPT 4440 arm_cache_prefer_mask, 4441 va & arm_cache_prefer_mask, 4442 #else 4443 0, 0, 4444 #endif 4445 &pv); 4446 pa = pv.pv_pa; 4447 #else 4448 if (uvm_page_physget(&pa) == false) 4449 return (1); 4450 #endif /* PMAP_STEAL_MEMORY */ 4451 } else { 4452 struct vm_page *pg; 4453 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4454 if (pg == NULL) 4455 return (1); 4456 pa = VM_PAGE_TO_PHYS(pg); 4457 #ifdef PMAP_CACHE_VIPT 4458 /* 4459 * This new page must not have any mappings. However, it might 4460 * have previously used and therefore present in the cache. If 4461 * it doesn't have the desired color, we have to flush it from 4462 * the cache. And while we are at it, make sure to clear its 4463 * EXEC status. 4464 */ 4465 KASSERT(!(pg->mdpage.pvh_attrs & PVF_KENTRY)); 4466 KASSERT(pg->mdpage.pvh_list == NULL); 4467 if (pmap_is_page_colored_p(pg)) { 4468 if ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask) { 4469 pmap_flush_page(pg); 4470 PMAPCOUNT(vac_color_change); 4471 } else { 4472 PMAPCOUNT(vac_color_reuse); 4473 } 4474 } else { 4475 PMAPCOUNT(vac_color_new); 4476 } 4477 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 4478 PMAPCOUNT(exec_discarded_kremove); 4479 /* 4480 * We'll pretend this page was entered by pmap_kenter_pa 4481 */ 4482 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_EXEC; 4483 pg->mdpage.pvh_attrs |= va | PVF_KENTRY | PVF_COLORED | PVF_REF | PVF_MOD; 4484 #endif 4485 } 4486 4487 if (pap) 4488 *pap = pa; 4489 4490 PMAPCOUNT(pt_mappings); 4491 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4492 KDASSERT(l2b != NULL); 4493 4494 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4495 *ptep = L2_S_PROTO | pa | cache_mode | 4496 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4497 PTE_SYNC(ptep); 4498 memset((void *)va, 0, PAGE_SIZE); 4499 return (0); 4500 } 4501 4502 /* 4503 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4504 * used by pmap_growkernel(). 4505 */ 4506 static inline struct l2_bucket * 4507 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4508 { 4509 struct l2_dtable *l2; 4510 struct l2_bucket *l2b; 4511 u_short l1idx; 4512 vaddr_t nva; 4513 4514 l1idx = L1_IDX(va); 4515 4516 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4517 /* 4518 * No mapping at this address, as there is 4519 * no entry in the L1 table. 4520 * Need to allocate a new l2_dtable. 4521 */ 4522 nva = pmap_kernel_l2dtable_kva; 4523 if ((nva & PGOFSET) == 0) { 4524 /* 4525 * Need to allocate a backing page 4526 */ 4527 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4528 return (NULL); 4529 } 4530 4531 l2 = (struct l2_dtable *)nva; 4532 nva += sizeof(struct l2_dtable); 4533 4534 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4535 /* 4536 * The new l2_dtable straddles a page boundary. 4537 * Map in another page to cover it. 4538 */ 4539 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4540 return (NULL); 4541 } 4542 4543 pmap_kernel_l2dtable_kva = nva; 4544 4545 /* 4546 * Link it into the parent pmap 4547 */ 4548 pm->pm_l2[L2_IDX(l1idx)] = l2; 4549 } 4550 4551 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4552 4553 /* 4554 * Fetch pointer to the L2 page table associated with the address. 4555 */ 4556 if (l2b->l2b_kva == NULL) { 4557 pt_entry_t *ptep; 4558 4559 /* 4560 * No L2 page table has been allocated. Chances are, this 4561 * is because we just allocated the l2_dtable, above. 4562 */ 4563 nva = pmap_kernel_l2ptp_kva; 4564 ptep = (pt_entry_t *)nva; 4565 if ((nva & PGOFSET) == 0) { 4566 /* 4567 * Need to allocate a backing page 4568 */ 4569 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4570 &pmap_kernel_l2ptp_phys)) 4571 return (NULL); 4572 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4573 } 4574 4575 l2->l2_occupancy++; 4576 l2b->l2b_kva = ptep; 4577 l2b->l2b_l1idx = l1idx; 4578 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4579 4580 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4581 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4582 } 4583 4584 return (l2b); 4585 } 4586 4587 vaddr_t 4588 pmap_growkernel(vaddr_t maxkvaddr) 4589 { 4590 pmap_t kpm = pmap_kernel(); 4591 struct l1_ttable *l1; 4592 struct l2_bucket *l2b; 4593 pd_entry_t *pl1pd; 4594 int s; 4595 4596 if (maxkvaddr <= pmap_curmaxkvaddr) 4597 goto out; /* we are OK */ 4598 4599 NPDEBUG(PDB_GROWKERN, 4600 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4601 pmap_curmaxkvaddr, maxkvaddr)); 4602 4603 KDASSERT(maxkvaddr <= virtual_end); 4604 4605 /* 4606 * whoops! we need to add kernel PTPs 4607 */ 4608 4609 s = splhigh(); /* to be safe */ 4610 mutex_enter(&kpm->pm_lock); 4611 4612 /* Map 1MB at a time */ 4613 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4614 4615 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4616 KDASSERT(l2b != NULL); 4617 4618 /* Distribute new L1 entry to all other L1s */ 4619 SLIST_FOREACH(l1, &l1_list, l1_link) { 4620 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4621 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4622 L1_C_PROTO; 4623 PTE_SYNC(pl1pd); 4624 } 4625 } 4626 4627 /* 4628 * flush out the cache, expensive but growkernel will happen so 4629 * rarely 4630 */ 4631 cpu_dcache_wbinv_all(); 4632 cpu_tlb_flushD(); 4633 cpu_cpwait(); 4634 4635 mutex_exit(&kpm->pm_lock); 4636 splx(s); 4637 4638 out: 4639 return (pmap_curmaxkvaddr); 4640 } 4641 4642 /************************ Utility routines ****************************/ 4643 4644 /* 4645 * vector_page_setprot: 4646 * 4647 * Manipulate the protection of the vector page. 4648 */ 4649 void 4650 vector_page_setprot(int prot) 4651 { 4652 struct l2_bucket *l2b; 4653 pt_entry_t *ptep; 4654 4655 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4656 KDASSERT(l2b != NULL); 4657 4658 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4659 4660 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4661 PTE_SYNC(ptep); 4662 cpu_tlb_flushD_SE(vector_page); 4663 cpu_cpwait(); 4664 } 4665 4666 /* 4667 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4668 * Returns true if the mapping exists, else false. 4669 * 4670 * NOTE: This function is only used by a couple of arm-specific modules. 4671 * It is not safe to take any pmap locks here, since we could be right 4672 * in the middle of debugging the pmap anyway... 4673 * 4674 * It is possible for this routine to return false even though a valid 4675 * mapping does exist. This is because we don't lock, so the metadata 4676 * state may be inconsistent. 4677 * 4678 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4679 * a "section" mapping. 4680 */ 4681 bool 4682 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4683 { 4684 struct l2_dtable *l2; 4685 pd_entry_t *pl1pd, l1pd; 4686 pt_entry_t *ptep; 4687 u_short l1idx; 4688 4689 if (pm->pm_l1 == NULL) 4690 return false; 4691 4692 l1idx = L1_IDX(va); 4693 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4694 l1pd = *pl1pd; 4695 4696 if (l1pte_section_p(l1pd)) { 4697 *ptp = NULL; 4698 return true; 4699 } 4700 4701 if (pm->pm_l2 == NULL) 4702 return false; 4703 4704 l2 = pm->pm_l2[L2_IDX(l1idx)]; 4705 4706 if (l2 == NULL || 4707 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 4708 return false; 4709 } 4710 4711 *ptp = &ptep[l2pte_index(va)]; 4712 return true; 4713 } 4714 4715 bool 4716 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 4717 { 4718 u_short l1idx; 4719 4720 if (pm->pm_l1 == NULL) 4721 return false; 4722 4723 l1idx = L1_IDX(va); 4724 *pdp = &pm->pm_l1->l1_kva[l1idx]; 4725 4726 return true; 4727 } 4728 4729 /************************ Bootstrapping routines ****************************/ 4730 4731 static void 4732 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 4733 { 4734 int i; 4735 4736 l1->l1_kva = l1pt; 4737 l1->l1_domain_use_count = 0; 4738 l1->l1_domain_first = 0; 4739 4740 for (i = 0; i < PMAP_DOMAINS; i++) 4741 l1->l1_domain_free[i] = i + 1; 4742 4743 /* 4744 * Copy the kernel's L1 entries to each new L1. 4745 */ 4746 if (pmap_initialized) 4747 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 4748 4749 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 4750 &l1->l1_physaddr) == false) 4751 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 4752 4753 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 4754 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 4755 } 4756 4757 /* 4758 * pmap_bootstrap() is called from the board-specific initarm() routine 4759 * once the kernel L1/L2 descriptors tables have been set up. 4760 * 4761 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 4762 * spread over a number of disparate files/functions. 4763 * 4764 * We are passed the following parameters 4765 * - kernel_l1pt 4766 * This is a pointer to the base of the kernel's L1 translation table. 4767 * - vstart 4768 * 1MB-aligned start of managed kernel virtual memory. 4769 * - vend 4770 * 1MB-aligned end of managed kernel virtual memory. 4771 * 4772 * We use the first parameter to build the metadata (struct l1_ttable and 4773 * struct l2_dtable) necessary to track kernel mappings. 4774 */ 4775 #define PMAP_STATIC_L2_SIZE 16 4776 void 4777 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 4778 { 4779 static struct l1_ttable static_l1; 4780 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 4781 struct l1_ttable *l1 = &static_l1; 4782 struct l2_dtable *l2; 4783 struct l2_bucket *l2b; 4784 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 4785 pmap_t pm = pmap_kernel(); 4786 pd_entry_t pde; 4787 pt_entry_t *ptep; 4788 paddr_t pa; 4789 vaddr_t va; 4790 vsize_t size; 4791 int nptes, l1idx, l2idx, l2next = 0; 4792 4793 /* 4794 * Initialise the kernel pmap object 4795 */ 4796 pm->pm_l1 = l1; 4797 pm->pm_domain = PMAP_DOMAIN_KERNEL; 4798 pm->pm_activated = true; 4799 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4800 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 4801 4802 /* 4803 * Scan the L1 translation table created by initarm() and create 4804 * the required metadata for all valid mappings found in it. 4805 */ 4806 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 4807 pde = l1pt[l1idx]; 4808 4809 /* 4810 * We're only interested in Coarse mappings. 4811 * pmap_extract() can deal with section mappings without 4812 * recourse to checking L2 metadata. 4813 */ 4814 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 4815 continue; 4816 4817 /* 4818 * Lookup the KVA of this L2 descriptor table 4819 */ 4820 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 4821 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 4822 if (ptep == NULL) { 4823 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 4824 (u_int)l1idx << L1_S_SHIFT, pa); 4825 } 4826 4827 /* 4828 * Fetch the associated L2 metadata structure. 4829 * Allocate a new one if necessary. 4830 */ 4831 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4832 if (l2next == PMAP_STATIC_L2_SIZE) 4833 panic("pmap_bootstrap: out of static L2s"); 4834 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 4835 } 4836 4837 /* 4838 * One more L1 slot tracked... 4839 */ 4840 l2->l2_occupancy++; 4841 4842 /* 4843 * Fill in the details of the L2 descriptor in the 4844 * appropriate bucket. 4845 */ 4846 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4847 l2b->l2b_kva = ptep; 4848 l2b->l2b_phys = pa; 4849 l2b->l2b_l1idx = l1idx; 4850 4851 /* 4852 * Establish an initial occupancy count for this descriptor 4853 */ 4854 for (l2idx = 0; 4855 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 4856 l2idx++) { 4857 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 4858 l2b->l2b_occupancy++; 4859 } 4860 } 4861 4862 /* 4863 * Make sure the descriptor itself has the correct cache mode. 4864 * If not, fix it, but whine about the problem. Port-meisters 4865 * should consider this a clue to fix up their initarm() 4866 * function. :) 4867 */ 4868 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 4869 printf("pmap_bootstrap: WARNING! wrong cache mode for " 4870 "L2 pte @ %p\n", ptep); 4871 } 4872 } 4873 4874 /* 4875 * Ensure the primary (kernel) L1 has the correct cache mode for 4876 * a page table. Bitch if it is not correctly set. 4877 */ 4878 for (va = (vaddr_t)l1pt; 4879 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 4880 if (pmap_set_pt_cache_mode(l1pt, va)) 4881 printf("pmap_bootstrap: WARNING! wrong cache mode for " 4882 "primary L1 @ 0x%lx\n", va); 4883 } 4884 4885 cpu_dcache_wbinv_all(); 4886 cpu_tlb_flushID(); 4887 cpu_cpwait(); 4888 4889 /* 4890 * now we allocate the "special" VAs which are used for tmp mappings 4891 * by the pmap (and other modules). we allocate the VAs by advancing 4892 * virtual_avail (note that there are no pages mapped at these VAs). 4893 * 4894 * Managed KVM space start from wherever initarm() tells us. 4895 */ 4896 virtual_avail = vstart; 4897 virtual_end = vend; 4898 4899 #ifdef PMAP_CACHE_VIPT 4900 /* 4901 * If we have a VIPT cache, we need one page/pte per possible alias 4902 * page so we won't violate cache aliasing rules. 4903 */ 4904 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 4905 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 4906 #else 4907 nptes = 1; 4908 #endif 4909 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 4910 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 4911 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 4912 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 4913 pmap_alloc_specials(&virtual_avail, 1, (void *)&memhook, NULL); 4914 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 4915 (void *)&msgbufaddr, NULL); 4916 4917 /* 4918 * Allocate a range of kernel virtual address space to be used 4919 * for L2 descriptor tables and metadata allocation in 4920 * pmap_growkernel(). 4921 */ 4922 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 4923 pmap_alloc_specials(&virtual_avail, 4924 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 4925 &pmap_kernel_l2ptp_kva, NULL); 4926 4927 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 4928 pmap_alloc_specials(&virtual_avail, 4929 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 4930 &pmap_kernel_l2dtable_kva, NULL); 4931 4932 /* 4933 * init the static-global locks and global pmap list. 4934 */ 4935 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 4936 4937 /* 4938 * We can now initialise the first L1's metadata. 4939 */ 4940 SLIST_INIT(&l1_list); 4941 TAILQ_INIT(&l1_lru_list); 4942 simple_lock_init(&l1_lru_lock); 4943 pmap_init_l1(l1, l1pt); 4944 4945 /* Set up vector page L1 details, if necessary */ 4946 if (vector_page < KERNEL_BASE) { 4947 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 4948 l2b = pmap_get_l2_bucket(pm, vector_page); 4949 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 4950 L1_C_DOM(pm->pm_domain); 4951 } else 4952 pm->pm_pl1vec = NULL; 4953 4954 /* 4955 * Initialize the pmap cache 4956 */ 4957 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 4958 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 4959 LIST_INIT(&pmap_pmaps); 4960 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 4961 4962 /* 4963 * Initialize the pv pool. 4964 */ 4965 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 4966 &pmap_bootstrap_pv_allocator, IPL_NONE); 4967 4968 /* 4969 * Initialize the L2 dtable pool and cache. 4970 */ 4971 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 4972 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 4973 4974 /* 4975 * Initialise the L2 descriptor table pool and cache 4976 */ 4977 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 4978 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 4979 pmap_l2ptp_ctor, NULL, NULL); 4980 4981 cpu_dcache_wbinv_all(); 4982 } 4983 4984 static int 4985 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 4986 { 4987 pd_entry_t *pdep, pde; 4988 pt_entry_t *ptep, pte; 4989 vaddr_t pa; 4990 int rv = 0; 4991 4992 /* 4993 * Make sure the descriptor itself has the correct cache mode 4994 */ 4995 pdep = &kl1[L1_IDX(va)]; 4996 pde = *pdep; 4997 4998 if (l1pte_section_p(pde)) { 4999 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5000 *pdep = (pde & ~L1_S_CACHE_MASK) | 5001 pte_l1_s_cache_mode_pt; 5002 PTE_SYNC(pdep); 5003 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5004 rv = 1; 5005 } 5006 } else { 5007 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5008 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5009 if (ptep == NULL) 5010 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5011 5012 ptep = &ptep[l2pte_index(va)]; 5013 pte = *ptep; 5014 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5015 *ptep = (pte & ~L2_S_CACHE_MASK) | 5016 pte_l2_s_cache_mode_pt; 5017 PTE_SYNC(ptep); 5018 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5019 rv = 1; 5020 } 5021 } 5022 5023 return (rv); 5024 } 5025 5026 static void 5027 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5028 { 5029 vaddr_t va = *availp; 5030 struct l2_bucket *l2b; 5031 5032 if (ptep) { 5033 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5034 if (l2b == NULL) 5035 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5036 5037 if (ptep) 5038 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5039 } 5040 5041 *vap = va; 5042 *availp = va + (PAGE_SIZE * pages); 5043 } 5044 5045 void 5046 pmap_init(void) 5047 { 5048 extern int physmem; 5049 5050 /* 5051 * Set the available memory vars - These do not map to real memory 5052 * addresses and cannot as the physical memory is fragmented. 5053 * They are used by ps for %mem calculations. 5054 * One could argue whether this should be the entire memory or just 5055 * the memory that is useable in a user process. 5056 */ 5057 avail_start = 0; 5058 avail_end = physmem * PAGE_SIZE; 5059 5060 /* 5061 * Now we need to free enough pv_entry structures to allow us to get 5062 * the kmem_map/kmem_object allocated and inited (done after this 5063 * function is finished). to do this we allocate one bootstrap page out 5064 * of kernel_map and use it to provide an initial pool of pv_entry 5065 * structures. we never free this page. 5066 */ 5067 pool_setlowat(&pmap_pv_pool, 5068 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5069 5070 pmap_initialized = true; 5071 } 5072 5073 static vaddr_t last_bootstrap_page = 0; 5074 static void *free_bootstrap_pages = NULL; 5075 5076 static void * 5077 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5078 { 5079 extern void *pool_page_alloc(struct pool *, int); 5080 vaddr_t new_page; 5081 void *rv; 5082 5083 if (pmap_initialized) 5084 return (pool_page_alloc(pp, flags)); 5085 5086 if (free_bootstrap_pages) { 5087 rv = free_bootstrap_pages; 5088 free_bootstrap_pages = *((void **)rv); 5089 return (rv); 5090 } 5091 5092 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5093 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5094 5095 KASSERT(new_page > last_bootstrap_page); 5096 last_bootstrap_page = new_page; 5097 return ((void *)new_page); 5098 } 5099 5100 static void 5101 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5102 { 5103 extern void pool_page_free(struct pool *, void *); 5104 5105 if ((vaddr_t)v <= last_bootstrap_page) { 5106 *((void **)v) = free_bootstrap_pages; 5107 free_bootstrap_pages = v; 5108 return; 5109 } 5110 5111 if (pmap_initialized) { 5112 pool_page_free(pp, v); 5113 return; 5114 } 5115 } 5116 5117 /* 5118 * pmap_postinit() 5119 * 5120 * This routine is called after the vm and kmem subsystems have been 5121 * initialised. This allows the pmap code to perform any initialisation 5122 * that can only be done one the memory allocation is in place. 5123 */ 5124 void 5125 pmap_postinit(void) 5126 { 5127 extern paddr_t physical_start, physical_end; 5128 struct l2_bucket *l2b; 5129 struct l1_ttable *l1; 5130 struct pglist plist; 5131 struct vm_page *m; 5132 pd_entry_t *pl1pt; 5133 pt_entry_t *ptep, pte; 5134 vaddr_t va, eva; 5135 u_int loop, needed; 5136 int error; 5137 5138 pool_cache_setlowat(&pmap_l2ptp_cache, 5139 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5140 pool_cache_setlowat(&pmap_l2dtable_cache, 5141 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5142 5143 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5144 needed -= 1; 5145 5146 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5147 5148 for (loop = 0; loop < needed; loop++, l1++) { 5149 /* Allocate a L1 page table */ 5150 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5151 if (va == 0) 5152 panic("Cannot allocate L1 KVM"); 5153 5154 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5155 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5156 if (error) 5157 panic("Cannot allocate L1 physical pages"); 5158 5159 m = TAILQ_FIRST(&plist); 5160 eva = va + L1_TABLE_SIZE; 5161 pl1pt = (pd_entry_t *)va; 5162 5163 while (m && va < eva) { 5164 paddr_t pa = VM_PAGE_TO_PHYS(m); 5165 5166 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 5167 5168 /* 5169 * Make sure the L1 descriptor table is mapped 5170 * with the cache-mode set to write-through. 5171 */ 5172 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5173 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5174 pte = *ptep; 5175 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5176 *ptep = pte; 5177 PTE_SYNC(ptep); 5178 cpu_tlb_flushD_SE(va); 5179 5180 va += PAGE_SIZE; 5181 m = TAILQ_NEXT(m, pageq.queue); 5182 } 5183 5184 #ifdef DIAGNOSTIC 5185 if (m) 5186 panic("pmap_alloc_l1pt: pglist not empty"); 5187 #endif /* DIAGNOSTIC */ 5188 5189 pmap_init_l1(l1, pl1pt); 5190 } 5191 5192 #ifdef DEBUG 5193 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5194 needed); 5195 #endif 5196 } 5197 5198 /* 5199 * Note that the following routines are used by board-specific initialisation 5200 * code to configure the initial kernel page tables. 5201 * 5202 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5203 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5204 * behaviour of the old pmap, and provides an easy migration path for 5205 * initial bring-up of the new pmap on existing ports. Fortunately, 5206 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5207 * will be deprecated. 5208 * 5209 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5210 * tables. 5211 */ 5212 5213 /* 5214 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5215 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5216 * find them as necessary. 5217 * 5218 * Note that the data on this list MUST remain valid after initarm() returns, 5219 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5220 */ 5221 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5222 5223 static vaddr_t 5224 kernel_pt_lookup(paddr_t pa) 5225 { 5226 pv_addr_t *pv; 5227 5228 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5229 #ifndef ARM32_NEW_VM_LAYOUT 5230 if (pv->pv_pa == (pa & ~PGOFSET)) 5231 return (pv->pv_va | (pa & PGOFSET)); 5232 #else 5233 if (pv->pv_pa == pa) 5234 return (pv->pv_va); 5235 #endif 5236 } 5237 return (0); 5238 } 5239 5240 /* 5241 * pmap_map_section: 5242 * 5243 * Create a single section mapping. 5244 */ 5245 void 5246 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5247 { 5248 pd_entry_t *pde = (pd_entry_t *) l1pt; 5249 pd_entry_t fl; 5250 5251 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5252 5253 switch (cache) { 5254 case PTE_NOCACHE: 5255 default: 5256 fl = 0; 5257 break; 5258 5259 case PTE_CACHE: 5260 fl = pte_l1_s_cache_mode; 5261 break; 5262 5263 case PTE_PAGETABLE: 5264 fl = pte_l1_s_cache_mode_pt; 5265 break; 5266 } 5267 5268 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5269 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5270 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5271 } 5272 5273 /* 5274 * pmap_map_entry: 5275 * 5276 * Create a single page mapping. 5277 */ 5278 void 5279 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5280 { 5281 pd_entry_t *pde = (pd_entry_t *) l1pt; 5282 pt_entry_t fl; 5283 pt_entry_t *pte; 5284 5285 KASSERT(((va | pa) & PGOFSET) == 0); 5286 5287 switch (cache) { 5288 case PTE_NOCACHE: 5289 default: 5290 fl = 0; 5291 break; 5292 5293 case PTE_CACHE: 5294 fl = pte_l2_s_cache_mode; 5295 break; 5296 5297 case PTE_PAGETABLE: 5298 fl = pte_l2_s_cache_mode_pt; 5299 break; 5300 } 5301 5302 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5303 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5304 5305 #ifndef ARM32_NEW_VM_LAYOUT 5306 pte = (pt_entry_t *) 5307 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5308 #else 5309 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5310 #endif 5311 if (pte == NULL) 5312 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5313 5314 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5315 #ifndef ARM32_NEW_VM_LAYOUT 5316 pte += (va >> PGSHIFT) & 0x3ff; 5317 #else 5318 pte += l2pte_index(va); 5319 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5320 #endif 5321 *pte = fl; 5322 PTE_SYNC(pte); 5323 } 5324 5325 /* 5326 * pmap_link_l2pt: 5327 * 5328 * Link the L2 page table specified by "l2pv" into the L1 5329 * page table at the slot for "va". 5330 */ 5331 void 5332 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5333 { 5334 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5335 u_int slot = va >> L1_S_SHIFT; 5336 5337 #ifndef ARM32_NEW_VM_LAYOUT 5338 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5339 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5340 #endif 5341 5342 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5343 5344 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5345 #ifdef ARM32_NEW_VM_LAYOUT 5346 PTE_SYNC(&pde[slot]); 5347 #else 5348 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5349 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5350 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5351 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5352 #endif 5353 5354 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5355 } 5356 5357 /* 5358 * pmap_map_chunk: 5359 * 5360 * Map a chunk of memory using the most efficient mappings 5361 * possible (section, large page, small page) into the 5362 * provided L1 and L2 tables at the specified virtual address. 5363 */ 5364 vsize_t 5365 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5366 int prot, int cache) 5367 { 5368 pd_entry_t *pde = (pd_entry_t *) l1pt; 5369 pt_entry_t *pte, f1, f2s, f2l; 5370 vsize_t resid; 5371 int i; 5372 5373 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5374 5375 if (l1pt == 0) 5376 panic("pmap_map_chunk: no L1 table provided"); 5377 5378 #ifdef VERBOSE_INIT_ARM 5379 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5380 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5381 #endif 5382 5383 switch (cache) { 5384 case PTE_NOCACHE: 5385 default: 5386 f1 = 0; 5387 f2l = 0; 5388 f2s = 0; 5389 break; 5390 5391 case PTE_CACHE: 5392 f1 = pte_l1_s_cache_mode; 5393 f2l = pte_l2_l_cache_mode; 5394 f2s = pte_l2_s_cache_mode; 5395 break; 5396 5397 case PTE_PAGETABLE: 5398 f1 = pte_l1_s_cache_mode_pt; 5399 f2l = pte_l2_l_cache_mode_pt; 5400 f2s = pte_l2_s_cache_mode_pt; 5401 break; 5402 } 5403 5404 size = resid; 5405 5406 while (resid > 0) { 5407 /* See if we can use a section mapping. */ 5408 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5409 #ifdef VERBOSE_INIT_ARM 5410 printf("S"); 5411 #endif 5412 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5413 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5414 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5415 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5416 va += L1_S_SIZE; 5417 pa += L1_S_SIZE; 5418 resid -= L1_S_SIZE; 5419 continue; 5420 } 5421 5422 /* 5423 * Ok, we're going to use an L2 table. Make sure 5424 * one is actually in the corresponding L1 slot 5425 * for the current VA. 5426 */ 5427 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5428 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5429 5430 #ifndef ARM32_NEW_VM_LAYOUT 5431 pte = (pt_entry_t *) 5432 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5433 #else 5434 pte = (pt_entry_t *) kernel_pt_lookup( 5435 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5436 #endif 5437 if (pte == NULL) 5438 panic("pmap_map_chunk: can't find L2 table for VA" 5439 "0x%08lx", va); 5440 5441 /* See if we can use a L2 large page mapping. */ 5442 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5443 #ifdef VERBOSE_INIT_ARM 5444 printf("L"); 5445 #endif 5446 for (i = 0; i < 16; i++) { 5447 #ifndef ARM32_NEW_VM_LAYOUT 5448 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5449 L2_L_PROTO | pa | 5450 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5451 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5452 #else 5453 pte[l2pte_index(va) + i] = 5454 L2_L_PROTO | pa | 5455 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5456 PTE_SYNC(&pte[l2pte_index(va) + i]); 5457 #endif 5458 } 5459 va += L2_L_SIZE; 5460 pa += L2_L_SIZE; 5461 resid -= L2_L_SIZE; 5462 continue; 5463 } 5464 5465 /* Use a small page mapping. */ 5466 #ifdef VERBOSE_INIT_ARM 5467 printf("P"); 5468 #endif 5469 #ifndef ARM32_NEW_VM_LAYOUT 5470 pte[(va >> PGSHIFT) & 0x3ff] = 5471 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5472 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5473 #else 5474 pte[l2pte_index(va)] = 5475 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5476 PTE_SYNC(&pte[l2pte_index(va)]); 5477 #endif 5478 va += PAGE_SIZE; 5479 pa += PAGE_SIZE; 5480 resid -= PAGE_SIZE; 5481 } 5482 #ifdef VERBOSE_INIT_ARM 5483 printf("\n"); 5484 #endif 5485 return (size); 5486 } 5487 5488 /********************** Static device map routines ***************************/ 5489 5490 static const struct pmap_devmap *pmap_devmap_table; 5491 5492 /* 5493 * Register the devmap table. This is provided in case early console 5494 * initialization needs to register mappings created by bootstrap code 5495 * before pmap_devmap_bootstrap() is called. 5496 */ 5497 void 5498 pmap_devmap_register(const struct pmap_devmap *table) 5499 { 5500 5501 pmap_devmap_table = table; 5502 } 5503 5504 /* 5505 * Map all of the static regions in the devmap table, and remember 5506 * the devmap table so other parts of the kernel can look up entries 5507 * later. 5508 */ 5509 void 5510 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5511 { 5512 int i; 5513 5514 pmap_devmap_table = table; 5515 5516 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5517 #ifdef VERBOSE_INIT_ARM 5518 printf("devmap: %08lx -> %08lx @ %08lx\n", 5519 pmap_devmap_table[i].pd_pa, 5520 pmap_devmap_table[i].pd_pa + 5521 pmap_devmap_table[i].pd_size - 1, 5522 pmap_devmap_table[i].pd_va); 5523 #endif 5524 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5525 pmap_devmap_table[i].pd_pa, 5526 pmap_devmap_table[i].pd_size, 5527 pmap_devmap_table[i].pd_prot, 5528 pmap_devmap_table[i].pd_cache); 5529 } 5530 } 5531 5532 const struct pmap_devmap * 5533 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5534 { 5535 uint64_t endpa; 5536 int i; 5537 5538 if (pmap_devmap_table == NULL) 5539 return (NULL); 5540 5541 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5542 5543 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5544 if (pa >= pmap_devmap_table[i].pd_pa && 5545 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5546 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5547 return (&pmap_devmap_table[i]); 5548 } 5549 5550 return (NULL); 5551 } 5552 5553 const struct pmap_devmap * 5554 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5555 { 5556 int i; 5557 5558 if (pmap_devmap_table == NULL) 5559 return (NULL); 5560 5561 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5562 if (va >= pmap_devmap_table[i].pd_va && 5563 va + size - 1 <= pmap_devmap_table[i].pd_va + 5564 pmap_devmap_table[i].pd_size - 1) 5565 return (&pmap_devmap_table[i]); 5566 } 5567 5568 return (NULL); 5569 } 5570 5571 /********************** PTE initialization routines **************************/ 5572 5573 /* 5574 * These routines are called when the CPU type is identified to set up 5575 * the PTE prototypes, cache modes, etc. 5576 * 5577 * The variables are always here, just in case LKMs need to reference 5578 * them (though, they shouldn't). 5579 */ 5580 5581 pt_entry_t pte_l1_s_cache_mode; 5582 pt_entry_t pte_l1_s_cache_mode_pt; 5583 pt_entry_t pte_l1_s_cache_mask; 5584 5585 pt_entry_t pte_l2_l_cache_mode; 5586 pt_entry_t pte_l2_l_cache_mode_pt; 5587 pt_entry_t pte_l2_l_cache_mask; 5588 5589 pt_entry_t pte_l2_s_cache_mode; 5590 pt_entry_t pte_l2_s_cache_mode_pt; 5591 pt_entry_t pte_l2_s_cache_mask; 5592 5593 pt_entry_t pte_l2_s_prot_u; 5594 pt_entry_t pte_l2_s_prot_w; 5595 pt_entry_t pte_l2_s_prot_mask; 5596 5597 pt_entry_t pte_l1_s_proto; 5598 pt_entry_t pte_l1_c_proto; 5599 pt_entry_t pte_l2_s_proto; 5600 5601 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5602 void (*pmap_zero_page_func)(paddr_t); 5603 5604 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5605 void 5606 pmap_pte_init_generic(void) 5607 { 5608 5609 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5610 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5611 5612 pte_l2_l_cache_mode = L2_B|L2_C; 5613 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5614 5615 pte_l2_s_cache_mode = L2_B|L2_C; 5616 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5617 5618 /* 5619 * If we have a write-through cache, set B and C. If 5620 * we have a write-back cache, then we assume setting 5621 * only C will make those pages write-through. 5622 */ 5623 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5624 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5625 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5626 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5627 } else { 5628 #if ARM_MMU_V6 > 1 5629 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5630 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5631 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5632 #else 5633 pte_l1_s_cache_mode_pt = L1_S_C; 5634 pte_l2_l_cache_mode_pt = L2_C; 5635 pte_l2_s_cache_mode_pt = L2_C; 5636 #endif 5637 } 5638 5639 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5640 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5641 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5642 5643 pte_l1_s_proto = L1_S_PROTO_generic; 5644 pte_l1_c_proto = L1_C_PROTO_generic; 5645 pte_l2_s_proto = L2_S_PROTO_generic; 5646 5647 pmap_copy_page_func = pmap_copy_page_generic; 5648 pmap_zero_page_func = pmap_zero_page_generic; 5649 } 5650 5651 #if defined(CPU_ARM8) 5652 void 5653 pmap_pte_init_arm8(void) 5654 { 5655 5656 /* 5657 * ARM8 is compatible with generic, but we need to use 5658 * the page tables uncached. 5659 */ 5660 pmap_pte_init_generic(); 5661 5662 pte_l1_s_cache_mode_pt = 0; 5663 pte_l2_l_cache_mode_pt = 0; 5664 pte_l2_s_cache_mode_pt = 0; 5665 } 5666 #endif /* CPU_ARM8 */ 5667 5668 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5669 void 5670 pmap_pte_init_arm9(void) 5671 { 5672 5673 /* 5674 * ARM9 is compatible with generic, but we want to use 5675 * write-through caching for now. 5676 */ 5677 pmap_pte_init_generic(); 5678 5679 pte_l1_s_cache_mode = L1_S_C; 5680 pte_l2_l_cache_mode = L2_C; 5681 pte_l2_s_cache_mode = L2_C; 5682 5683 pte_l1_s_cache_mode_pt = L1_S_C; 5684 pte_l2_l_cache_mode_pt = L2_C; 5685 pte_l2_s_cache_mode_pt = L2_C; 5686 } 5687 #endif /* CPU_ARM9 */ 5688 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5689 5690 #if defined(CPU_ARM10) 5691 void 5692 pmap_pte_init_arm10(void) 5693 { 5694 5695 /* 5696 * ARM10 is compatible with generic, but we want to use 5697 * write-through caching for now. 5698 */ 5699 pmap_pte_init_generic(); 5700 5701 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 5702 pte_l2_l_cache_mode = L2_B | L2_C; 5703 pte_l2_s_cache_mode = L2_B | L2_C; 5704 5705 pte_l1_s_cache_mode_pt = L1_S_C; 5706 pte_l2_l_cache_mode_pt = L2_C; 5707 pte_l2_s_cache_mode_pt = L2_C; 5708 5709 } 5710 #endif /* CPU_ARM10 */ 5711 5712 #if ARM_MMU_SA1 == 1 5713 void 5714 pmap_pte_init_sa1(void) 5715 { 5716 5717 /* 5718 * The StrongARM SA-1 cache does not have a write-through 5719 * mode. So, do the generic initialization, then reset 5720 * the page table cache mode to B=1,C=1, and note that 5721 * the PTEs need to be sync'd. 5722 */ 5723 pmap_pte_init_generic(); 5724 5725 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5726 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5727 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5728 5729 pmap_needs_pte_sync = 1; 5730 } 5731 #endif /* ARM_MMU_SA1 == 1*/ 5732 5733 #if ARM_MMU_XSCALE == 1 5734 #if (ARM_NMMUS > 1) 5735 static u_int xscale_use_minidata; 5736 #endif 5737 5738 void 5739 pmap_pte_init_xscale(void) 5740 { 5741 uint32_t auxctl; 5742 int write_through = 0; 5743 5744 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5745 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 5746 5747 pte_l2_l_cache_mode = L2_B|L2_C; 5748 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 5749 5750 pte_l2_s_cache_mode = L2_B|L2_C; 5751 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 5752 5753 pte_l1_s_cache_mode_pt = L1_S_C; 5754 pte_l2_l_cache_mode_pt = L2_C; 5755 pte_l2_s_cache_mode_pt = L2_C; 5756 5757 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 5758 /* 5759 * The XScale core has an enhanced mode where writes that 5760 * miss the cache cause a cache line to be allocated. This 5761 * is significantly faster than the traditional, write-through 5762 * behavior of this case. 5763 */ 5764 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 5765 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 5766 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 5767 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 5768 5769 #ifdef XSCALE_CACHE_WRITE_THROUGH 5770 /* 5771 * Some versions of the XScale core have various bugs in 5772 * their cache units, the work-around for which is to run 5773 * the cache in write-through mode. Unfortunately, this 5774 * has a major (negative) impact on performance. So, we 5775 * go ahead and run fast-and-loose, in the hopes that we 5776 * don't line up the planets in a way that will trip the 5777 * bugs. 5778 * 5779 * However, we give you the option to be slow-but-correct. 5780 */ 5781 write_through = 1; 5782 #elif defined(XSCALE_CACHE_WRITE_BACK) 5783 /* force write back cache mode */ 5784 write_through = 0; 5785 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 5786 /* 5787 * Intel PXA2[15]0 processors are known to have a bug in 5788 * write-back cache on revision 4 and earlier (stepping 5789 * A[01] and B[012]). Fixed for C0 and later. 5790 */ 5791 { 5792 uint32_t id, type; 5793 5794 id = cpufunc_id(); 5795 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 5796 5797 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 5798 if ((id & CPU_ID_REVISION_MASK) < 5) { 5799 /* write through for stepping A0-1 and B0-2 */ 5800 write_through = 1; 5801 } 5802 } 5803 } 5804 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 5805 5806 if (write_through) { 5807 pte_l1_s_cache_mode = L1_S_C; 5808 pte_l2_l_cache_mode = L2_C; 5809 pte_l2_s_cache_mode = L2_C; 5810 } 5811 5812 #if (ARM_NMMUS > 1) 5813 xscale_use_minidata = 1; 5814 #endif 5815 5816 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 5817 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 5818 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 5819 5820 pte_l1_s_proto = L1_S_PROTO_xscale; 5821 pte_l1_c_proto = L1_C_PROTO_xscale; 5822 pte_l2_s_proto = L2_S_PROTO_xscale; 5823 5824 pmap_copy_page_func = pmap_copy_page_xscale; 5825 pmap_zero_page_func = pmap_zero_page_xscale; 5826 5827 /* 5828 * Disable ECC protection of page table access, for now. 5829 */ 5830 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 5831 auxctl &= ~XSCALE_AUXCTL_P; 5832 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 5833 } 5834 5835 /* 5836 * xscale_setup_minidata: 5837 * 5838 * Set up the mini-data cache clean area. We require the 5839 * caller to allocate the right amount of physically and 5840 * virtually contiguous space. 5841 */ 5842 void 5843 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 5844 { 5845 extern vaddr_t xscale_minidata_clean_addr; 5846 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 5847 pd_entry_t *pde = (pd_entry_t *) l1pt; 5848 pt_entry_t *pte; 5849 vsize_t size; 5850 uint32_t auxctl; 5851 5852 xscale_minidata_clean_addr = va; 5853 5854 /* Round it to page size. */ 5855 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 5856 5857 for (; size != 0; 5858 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 5859 #ifndef ARM32_NEW_VM_LAYOUT 5860 pte = (pt_entry_t *) 5861 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5862 #else 5863 pte = (pt_entry_t *) kernel_pt_lookup( 5864 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5865 #endif 5866 if (pte == NULL) 5867 panic("xscale_setup_minidata: can't find L2 table for " 5868 "VA 0x%08lx", va); 5869 #ifndef ARM32_NEW_VM_LAYOUT 5870 pte[(va >> PGSHIFT) & 0x3ff] = 5871 #else 5872 pte[l2pte_index(va)] = 5873 #endif 5874 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 5875 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 5876 } 5877 5878 /* 5879 * Configure the mini-data cache for write-back with 5880 * read/write-allocate. 5881 * 5882 * NOTE: In order to reconfigure the mini-data cache, we must 5883 * make sure it contains no valid data! In order to do that, 5884 * we must issue a global data cache invalidate command! 5885 * 5886 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 5887 * THIS IS VERY IMPORTANT! 5888 */ 5889 5890 /* Invalidate data and mini-data. */ 5891 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 5892 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 5893 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 5894 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 5895 } 5896 5897 /* 5898 * Change the PTEs for the specified kernel mappings such that they 5899 * will use the mini data cache instead of the main data cache. 5900 */ 5901 void 5902 pmap_uarea(vaddr_t va) 5903 { 5904 struct l2_bucket *l2b; 5905 pt_entry_t *ptep, *sptep, pte; 5906 vaddr_t next_bucket, eva; 5907 5908 #if (ARM_NMMUS > 1) 5909 if (xscale_use_minidata == 0) 5910 return; 5911 #endif 5912 5913 eva = va + USPACE; 5914 5915 while (va < eva) { 5916 next_bucket = L2_NEXT_BUCKET(va); 5917 if (next_bucket > eva) 5918 next_bucket = eva; 5919 5920 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5921 KDASSERT(l2b != NULL); 5922 5923 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 5924 5925 while (va < next_bucket) { 5926 pte = *ptep; 5927 if (!l2pte_minidata(pte)) { 5928 cpu_dcache_wbinv_range(va, PAGE_SIZE); 5929 cpu_tlb_flushD_SE(va); 5930 *ptep = pte & ~L2_B; 5931 } 5932 ptep++; 5933 va += PAGE_SIZE; 5934 } 5935 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 5936 } 5937 cpu_cpwait(); 5938 } 5939 #endif /* ARM_MMU_XSCALE == 1 */ 5940 5941 /* 5942 * return the PA of the current L1 table, for use when handling a crash dump 5943 */ 5944 uint32_t pmap_kernel_L1_addr() 5945 { 5946 return pmap_kernel()->pm_l1->l1_physaddr; 5947 } 5948 5949 #if defined(DDB) 5950 /* 5951 * A couple of ddb-callable functions for dumping pmaps 5952 */ 5953 void pmap_dump_all(void); 5954 void pmap_dump(pmap_t); 5955 5956 void 5957 pmap_dump_all(void) 5958 { 5959 pmap_t pm; 5960 5961 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 5962 if (pm == pmap_kernel()) 5963 continue; 5964 pmap_dump(pm); 5965 printf("\n"); 5966 } 5967 } 5968 5969 static pt_entry_t ncptes[64]; 5970 static void pmap_dump_ncpg(pmap_t); 5971 5972 void 5973 pmap_dump(pmap_t pm) 5974 { 5975 struct l2_dtable *l2; 5976 struct l2_bucket *l2b; 5977 pt_entry_t *ptep, pte; 5978 vaddr_t l2_va, l2b_va, va; 5979 int i, j, k, occ, rows = 0; 5980 5981 if (pm == pmap_kernel()) 5982 printf("pmap_kernel (%p): ", pm); 5983 else 5984 printf("user pmap (%p): ", pm); 5985 5986 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 5987 5988 l2_va = 0; 5989 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 5990 l2 = pm->pm_l2[i]; 5991 5992 if (l2 == NULL || l2->l2_occupancy == 0) 5993 continue; 5994 5995 l2b_va = l2_va; 5996 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 5997 l2b = &l2->l2_bucket[j]; 5998 5999 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6000 continue; 6001 6002 ptep = l2b->l2b_kva; 6003 6004 for (k = 0; k < 256 && ptep[k] == 0; k++) 6005 ; 6006 6007 k &= ~63; 6008 occ = l2b->l2b_occupancy; 6009 va = l2b_va + (k * 4096); 6010 for (; k < 256; k++, va += 0x1000) { 6011 char ch = ' '; 6012 if ((k % 64) == 0) { 6013 if ((rows % 8) == 0) { 6014 printf( 6015 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6016 } 6017 printf("%08lx: ", va); 6018 } 6019 6020 ncptes[k & 63] = 0; 6021 pte = ptep[k]; 6022 if (pte == 0) { 6023 ch = '.'; 6024 } else { 6025 occ--; 6026 switch (pte & 0x0c) { 6027 case 0x00: 6028 ch = 'D'; /* No cache No buff */ 6029 break; 6030 case 0x04: 6031 ch = 'B'; /* No cache buff */ 6032 break; 6033 case 0x08: 6034 if (pte & 0x40) 6035 ch = 'm'; 6036 else 6037 ch = 'C'; /* Cache No buff */ 6038 break; 6039 case 0x0c: 6040 ch = 'F'; /* Cache Buff */ 6041 break; 6042 } 6043 6044 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6045 ch += 0x20; 6046 6047 if ((pte & 0xc) == 0) 6048 ncptes[k & 63] = pte; 6049 } 6050 6051 if ((k % 64) == 63) { 6052 rows++; 6053 printf("%c\n", ch); 6054 pmap_dump_ncpg(pm); 6055 if (occ == 0) 6056 break; 6057 } else 6058 printf("%c", ch); 6059 } 6060 } 6061 } 6062 } 6063 6064 static void 6065 pmap_dump_ncpg(pmap_t pm) 6066 { 6067 struct vm_page *pg; 6068 struct pv_entry *pv; 6069 int i; 6070 6071 for (i = 0; i < 63; i++) { 6072 if (ncptes[i] == 0) 6073 continue; 6074 6075 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6076 if (pg == NULL) 6077 continue; 6078 6079 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6080 VM_PAGE_TO_PHYS(pg), 6081 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 6082 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 6083 6084 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 6085 printf(" %c va 0x%08lx, flags 0x%x\n", 6086 (pm == pv->pv_pmap) ? '*' : ' ', 6087 pv->pv_va, pv->pv_flags); 6088 } 6089 } 6090 } 6091 #endif 6092 6093 #ifdef PMAP_STEAL_MEMORY 6094 void 6095 pmap_boot_pageadd(pv_addr_t *newpv) 6096 { 6097 pv_addr_t *pv, *npv; 6098 6099 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6100 if (newpv->pv_pa < pv->pv_va) { 6101 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6102 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6103 newpv->pv_size += pv->pv_size; 6104 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6105 } 6106 pv = NULL; 6107 } else { 6108 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6109 pv = npv) { 6110 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6111 KASSERT(pv->pv_pa < newpv->pv_pa); 6112 if (newpv->pv_pa > npv->pv_pa) 6113 continue; 6114 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6115 pv->pv_size += newpv->pv_size; 6116 return; 6117 } 6118 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6119 break; 6120 newpv->pv_size += npv->pv_size; 6121 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6122 SLIST_REMOVE_AFTER(newpv, pv_list); 6123 return; 6124 } 6125 } 6126 } 6127 6128 if (pv) { 6129 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6130 } else { 6131 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6132 } 6133 } 6134 6135 void 6136 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6137 pv_addr_t *rpv) 6138 { 6139 pv_addr_t *pv, **pvp; 6140 struct vm_physseg *ps; 6141 size_t i; 6142 6143 KASSERT(amount & PGOFSET); 6144 KASSERT((mask & PGOFSET) == 0); 6145 KASSERT((match & PGOFSET) == 0); 6146 KASSERT(amount != 0); 6147 6148 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6149 (pv = *pvp) != NULL; 6150 pvp = &SLIST_NEXT(pv, pv_list)) { 6151 pv_addr_t *newpv; 6152 psize_t off; 6153 /* 6154 * If this entry is too small to satify the request... 6155 */ 6156 KASSERT(pv->pv_size > 0); 6157 if (pv->pv_size < amount) 6158 continue; 6159 6160 for (off = 0; off <= mask; off += PAGE_SIZE) { 6161 if (((pv->pv_pa + off) & mask) == match 6162 && off + amount <= pv->pv_size) 6163 break; 6164 } 6165 if (off > mask) 6166 continue; 6167 6168 rpv->pv_va = pv->pv_va + off; 6169 rpv->pv_pa = pv->pv_pa + off; 6170 rpv->pv_size = amount; 6171 pv->pv_size -= amount; 6172 if (pv->pv_size == 0) { 6173 KASSERT(off == 0); 6174 KASSERT((vaddr_t) pv == rpv->pv_va); 6175 *pvp = SLIST_NEXT(pv, pv_list); 6176 } else if (off == 0) { 6177 KASSERT((vaddr_t) pv == rpv->pv_va); 6178 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6179 *newpv = *pv; 6180 newpv->pv_pa += amount; 6181 newpv->pv_va += amount; 6182 *pvp = newpv; 6183 } else if (off < pv->pv_size) { 6184 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6185 *newpv = *pv; 6186 newpv->pv_size -= off; 6187 newpv->pv_pa += off + amount; 6188 newpv->pv_va += off + amount; 6189 6190 SLIST_NEXT(pv, pv_list) = newpv; 6191 pv->pv_size = off; 6192 } else { 6193 KASSERT((vaddr_t) pv != rpv->pv_va); 6194 } 6195 memset((void *)rpv->pv_va, 0, amount); 6196 return; 6197 } 6198 6199 if (vm_nphysseg == 0) 6200 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6201 6202 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6203 (pv = *pvp) != NULL; 6204 pvp = &SLIST_NEXT(pv, pv_list)) { 6205 if (SLIST_NEXT(pv, pv_list) == NULL) 6206 break; 6207 } 6208 KASSERT(mask == 0); 6209 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6210 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6211 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6212 rpv->pv_va = pv->pv_va; 6213 rpv->pv_pa = pv->pv_pa; 6214 rpv->pv_size = amount; 6215 *pvp = NULL; 6216 pmap_map_chunk(kernel_l1pt.pv_va, 6217 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6218 ptoa(ps->avail_start), 6219 amount - pv->pv_size, 6220 VM_PROT_READ|VM_PROT_WRITE, 6221 PTE_CACHE); 6222 ps->avail_start += atop(amount - pv->pv_size); 6223 /* 6224 * If we consumed the entire physseg, remove it. 6225 */ 6226 if (ps->avail_start == ps->avail_end) { 6227 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6228 ps[0] = ps[1]; 6229 } 6230 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6231 return; 6232 } 6233 } 6234 6235 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6236 } 6237 6238 vaddr_t 6239 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6240 { 6241 pv_addr_t pv; 6242 6243 pmap_boot_pagealloc(size, 0, 0, &pv); 6244 6245 return pv.pv_va; 6246 } 6247 #endif /* PMAP_STEAL_MEMORY */ 6248
Indexes created Mon Sep 29 21:09:56 GMT 2025