pmap.c revision 1.183
1 /* $NetBSD: pmap.c,v 1.183 2008/08/06 19:13:45 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/user.h> 202 #include <sys/pool.h> 203 #include <sys/cdefs.h> 204 #include <sys/cpu.h> 205 206 #include <uvm/uvm.h> 207 208 #include <machine/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.183 2008/08/06 19:13:45 matt Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 struct pmap kernel_pmap_store; 258 259 /* 260 * Which pmap is currently 'live' in the cache 261 * 262 * XXXSCW: Fix for SMP ... 263 */ 264 static pmap_t pmap_recent_user; 265 266 /* 267 * Pointer to last active lwp, or NULL if it exited. 268 */ 269 struct lwp *pmap_previous_active_lwp; 270 271 /* 272 * Pool and cache that pmap structures are allocated from. 273 * We use a cache to avoid clearing the pm_l2[] array (1KB) 274 * in pmap_create(). 275 */ 276 static struct pool_cache pmap_cache; 277 static LIST_HEAD(, pmap) pmap_pmaps; 278 279 /* 280 * Pool of PV structures 281 */ 282 static struct pool pmap_pv_pool; 283 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 284 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 285 static struct pool_allocator pmap_bootstrap_pv_allocator = { 286 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 287 }; 288 289 /* 290 * Pool and cache of l2_dtable structures. 291 * We use a cache to avoid clearing the structures when they're 292 * allocated. (196 bytes) 293 */ 294 static struct pool_cache pmap_l2dtable_cache; 295 static vaddr_t pmap_kernel_l2dtable_kva; 296 297 /* 298 * Pool and cache of L2 page descriptors. 299 * We use a cache to avoid clearing the descriptor table 300 * when they're allocated. (1KB) 301 */ 302 static struct pool_cache pmap_l2ptp_cache; 303 static vaddr_t pmap_kernel_l2ptp_kva; 304 static paddr_t pmap_kernel_l2ptp_phys; 305 306 #ifdef PMAPCOUNTERS 307 #define PMAP_EVCNT_INITIALIZER(name) \ 308 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 309 310 #ifdef PMAP_CACHE_VIPT 311 static struct evcnt pmap_ev_vac_color_new = 312 PMAP_EVCNT_INITIALIZER("new page color"); 313 static struct evcnt pmap_ev_vac_color_reuse = 314 PMAP_EVCNT_INITIALIZER("ok first page color"); 315 static struct evcnt pmap_ev_vac_color_ok = 316 PMAP_EVCNT_INITIALIZER("ok page color"); 317 static struct evcnt pmap_ev_vac_color_blind = 318 PMAP_EVCNT_INITIALIZER("blind page color"); 319 static struct evcnt pmap_ev_vac_color_change = 320 PMAP_EVCNT_INITIALIZER("change page color"); 321 static struct evcnt pmap_ev_vac_color_erase = 322 PMAP_EVCNT_INITIALIZER("erase page color"); 323 static struct evcnt pmap_ev_vac_color_none = 324 PMAP_EVCNT_INITIALIZER("no page color"); 325 static struct evcnt pmap_ev_vac_color_restore = 326 PMAP_EVCNT_INITIALIZER("restore page color"); 327 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 329 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 330 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 331 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 332 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 333 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 334 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 335 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 336 #endif 337 338 static struct evcnt pmap_ev_mappings = 339 PMAP_EVCNT_INITIALIZER("pages mapped"); 340 static struct evcnt pmap_ev_unmappings = 341 PMAP_EVCNT_INITIALIZER("pages unmapped"); 342 static struct evcnt pmap_ev_remappings = 343 PMAP_EVCNT_INITIALIZER("pages remapped"); 344 345 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 346 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 347 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 348 349 static struct evcnt pmap_ev_kernel_mappings = 350 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 351 static struct evcnt pmap_ev_kernel_unmappings = 352 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 353 static struct evcnt pmap_ev_kernel_remappings = 354 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 355 356 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 357 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 358 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 359 360 static struct evcnt pmap_ev_kenter_mappings = 361 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 362 static struct evcnt pmap_ev_kenter_unmappings = 363 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 364 static struct evcnt pmap_ev_kenter_remappings = 365 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 366 static struct evcnt pmap_ev_pt_mappings = 367 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 368 369 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 370 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 373 374 #ifdef PMAP_CACHE_VIPT 375 static struct evcnt pmap_ev_exec_mappings = 376 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 377 static struct evcnt pmap_ev_exec_cached = 378 PMAP_EVCNT_INITIALIZER("exec pages cached"); 379 380 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 381 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 382 383 static struct evcnt pmap_ev_exec_synced = 384 PMAP_EVCNT_INITIALIZER("exec pages synced"); 385 static struct evcnt pmap_ev_exec_synced_map = 386 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 387 static struct evcnt pmap_ev_exec_synced_unmap = 388 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 389 static struct evcnt pmap_ev_exec_synced_remap = 390 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 391 static struct evcnt pmap_ev_exec_synced_clearbit = 392 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 393 static struct evcnt pmap_ev_exec_synced_kremove = 394 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 395 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 397 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 399 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 400 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 401 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 402 403 static struct evcnt pmap_ev_exec_discarded_unmap = 404 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 405 static struct evcnt pmap_ev_exec_discarded_zero = 406 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 407 static struct evcnt pmap_ev_exec_discarded_copy = 408 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 409 static struct evcnt pmap_ev_exec_discarded_page_protect = 410 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 411 static struct evcnt pmap_ev_exec_discarded_clearbit = 412 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 413 static struct evcnt pmap_ev_exec_discarded_kremove = 414 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 415 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 422 #endif /* PMAP_CACHE_VIPT */ 423 424 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 425 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 426 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 427 428 EVCNT_ATTACH_STATIC(pmap_ev_updates); 429 EVCNT_ATTACH_STATIC(pmap_ev_collects); 430 EVCNT_ATTACH_STATIC(pmap_ev_activations); 431 432 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 433 #else 434 #define PMAPCOUNT(x) ((void)0) 435 #endif 436 437 /* 438 * pmap copy/zero page, and mem(5) hook point 439 */ 440 static pt_entry_t *csrc_pte, *cdst_pte; 441 static vaddr_t csrcp, cdstp; 442 vaddr_t memhook; /* used by mem.c */ 443 extern void *msgbufaddr; 444 445 /* 446 * Flag to indicate if pmap_init() has done its thing 447 */ 448 bool pmap_initialized; 449 450 /* 451 * Misc. locking data structures 452 */ 453 454 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 455 static struct lock pmap_main_lock; 456 457 #define PMAP_MAP_TO_HEAD_LOCK() \ 458 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 459 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 460 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 461 #define PMAP_HEAD_TO_MAP_LOCK() \ 462 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 463 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 464 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 465 #else 466 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 467 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 468 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 469 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 470 #endif 471 472 #define pmap_acquire_pmap_lock(pm) \ 473 do { \ 474 if ((pm) != pmap_kernel()) \ 475 mutex_enter(&(pm)->pm_lock); \ 476 } while (/*CONSTCOND*/0) 477 478 #define pmap_release_pmap_lock(pm) \ 479 do { \ 480 if ((pm) != pmap_kernel()) \ 481 mutex_exit(&(pm)->pm_lock); \ 482 } while (/*CONSTCOND*/0) 483 484 485 /* 486 * Metadata for L1 translation tables. 487 */ 488 struct l1_ttable { 489 /* Entry on the L1 Table list */ 490 SLIST_ENTRY(l1_ttable) l1_link; 491 492 /* Entry on the L1 Least Recently Used list */ 493 TAILQ_ENTRY(l1_ttable) l1_lru; 494 495 /* Track how many domains are allocated from this L1 */ 496 volatile u_int l1_domain_use_count; 497 498 /* 499 * A free-list of domain numbers for this L1. 500 * We avoid using ffs() and a bitmap to track domains since ffs() 501 * is slow on ARM. 502 */ 503 u_int8_t l1_domain_first; 504 u_int8_t l1_domain_free[PMAP_DOMAINS]; 505 506 /* Physical address of this L1 page table */ 507 paddr_t l1_physaddr; 508 509 /* KVA of this L1 page table */ 510 pd_entry_t *l1_kva; 511 }; 512 513 /* 514 * Convert a virtual address into its L1 table index. That is, the 515 * index used to locate the L2 descriptor table pointer in an L1 table. 516 * This is basically used to index l1->l1_kva[]. 517 * 518 * Each L2 descriptor table represents 1MB of VA space. 519 */ 520 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 521 522 /* 523 * L1 Page Tables are tracked using a Least Recently Used list. 524 * - New L1s are allocated from the HEAD. 525 * - Freed L1s are added to the TAIl. 526 * - Recently accessed L1s (where an 'access' is some change to one of 527 * the userland pmaps which owns this L1) are moved to the TAIL. 528 */ 529 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 530 static struct simplelock l1_lru_lock; 531 532 /* 533 * A list of all L1 tables 534 */ 535 static SLIST_HEAD(, l1_ttable) l1_list; 536 537 /* 538 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 539 * 540 * This is normally 16MB worth L2 page descriptors for any given pmap. 541 * Reference counts are maintained for L2 descriptors so they can be 542 * freed when empty. 543 */ 544 struct l2_dtable { 545 /* The number of L2 page descriptors allocated to this l2_dtable */ 546 u_int l2_occupancy; 547 548 /* List of L2 page descriptors */ 549 struct l2_bucket { 550 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 551 paddr_t l2b_phys; /* Physical address of same */ 552 u_short l2b_l1idx; /* This L2 table's L1 index */ 553 u_short l2b_occupancy; /* How many active descriptors */ 554 } l2_bucket[L2_BUCKET_SIZE]; 555 }; 556 557 /* 558 * Given an L1 table index, calculate the corresponding l2_dtable index 559 * and bucket index within the l2_dtable. 560 */ 561 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 562 (L2_SIZE - 1)) 563 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 564 565 /* 566 * Given a virtual address, this macro returns the 567 * virtual address required to drop into the next L2 bucket. 568 */ 569 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 570 571 /* 572 * L2 allocation. 573 */ 574 #define pmap_alloc_l2_dtable() \ 575 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 576 #define pmap_free_l2_dtable(l2) \ 577 pool_cache_put(&pmap_l2dtable_cache, (l2)) 578 #define pmap_alloc_l2_ptp(pap) \ 579 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 580 PR_NOWAIT, (pap))) 581 582 /* 583 * We try to map the page tables write-through, if possible. However, not 584 * all CPUs have a write-through cache mode, so on those we have to sync 585 * the cache when we frob page tables. 586 * 587 * We try to evaluate this at compile time, if possible. However, it's 588 * not always possible to do that, hence this run-time var. 589 */ 590 int pmap_needs_pte_sync; 591 592 /* 593 * Real definition of pv_entry. 594 */ 595 struct pv_entry { 596 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 597 pmap_t pv_pmap; /* pmap where mapping lies */ 598 vaddr_t pv_va; /* virtual address for mapping */ 599 u_int pv_flags; /* flags */ 600 }; 601 602 /* 603 * Macro to determine if a mapping might be resident in the 604 * instruction cache and/or TLB 605 */ 606 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 607 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 608 609 /* 610 * Macro to determine if a mapping might be resident in the 611 * data cache and/or TLB 612 */ 613 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 614 615 /* 616 * Local prototypes 617 */ 618 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 619 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 620 pt_entry_t **); 621 static bool pmap_is_current(pmap_t); 622 static bool pmap_is_cached(pmap_t); 623 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 624 pmap_t, vaddr_t, u_int); 625 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 626 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 627 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 628 u_int, u_int); 629 630 static void pmap_pinit(pmap_t); 631 static int pmap_pmap_ctor(void *, void *, int); 632 633 static void pmap_alloc_l1(pmap_t); 634 static void pmap_free_l1(pmap_t); 635 static void pmap_use_l1(pmap_t); 636 637 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 638 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 639 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 640 static int pmap_l2ptp_ctor(void *, void *, int); 641 static int pmap_l2dtable_ctor(void *, void *, int); 642 643 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 644 #ifdef PMAP_CACHE_VIVT 645 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 646 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 647 #endif 648 649 static void pmap_clearbit(struct vm_page *, u_int); 650 #ifdef PMAP_CACHE_VIVT 651 static int pmap_clean_page(struct pv_entry *, bool); 652 #endif 653 #ifdef PMAP_CACHE_VIPT 654 static void pmap_syncicache_page(struct vm_page *); 655 static void pmap_flush_page(struct vm_page *, bool); 656 #endif 657 static void pmap_page_remove(struct vm_page *); 658 659 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 660 static vaddr_t kernel_pt_lookup(paddr_t); 661 662 663 /* 664 * External function prototypes 665 */ 666 extern void bzero_page(vaddr_t); 667 extern void bcopy_page(vaddr_t, vaddr_t); 668 669 /* 670 * Misc variables 671 */ 672 vaddr_t virtual_avail; 673 vaddr_t virtual_end; 674 vaddr_t pmap_curmaxkvaddr; 675 676 vaddr_t avail_start; 677 vaddr_t avail_end; 678 679 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 680 pv_addr_t kernelpages; 681 pv_addr_t kernel_l1pt; 682 pv_addr_t systempage; 683 684 /* Function to set the debug level of the pmap code */ 685 686 #ifdef PMAP_DEBUG 687 void 688 pmap_debug(int level) 689 { 690 pmap_debug_level = level; 691 printf("pmap_debug: level=%d\n", pmap_debug_level); 692 } 693 #endif /* PMAP_DEBUG */ 694 695 /* 696 * A bunch of routines to conditionally flush the caches/TLB depending 697 * on whether the specified pmap actually needs to be flushed at any 698 * given time. 699 */ 700 static inline void 701 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 702 { 703 704 if (pm->pm_cstate.cs_tlb_id) 705 cpu_tlb_flushID_SE(va); 706 } 707 708 static inline void 709 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 710 { 711 712 if (pm->pm_cstate.cs_tlb_d) 713 cpu_tlb_flushD_SE(va); 714 } 715 716 static inline void 717 pmap_tlb_flushID(pmap_t pm) 718 { 719 720 if (pm->pm_cstate.cs_tlb_id) { 721 cpu_tlb_flushID(); 722 pm->pm_cstate.cs_tlb = 0; 723 } 724 } 725 726 static inline void 727 pmap_tlb_flushD(pmap_t pm) 728 { 729 730 if (pm->pm_cstate.cs_tlb_d) { 731 cpu_tlb_flushD(); 732 pm->pm_cstate.cs_tlb_d = 0; 733 } 734 } 735 736 #ifdef PMAP_CACHE_VIVT 737 static inline void 738 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 739 { 740 if (pm->pm_cstate.cs_cache_id) { 741 cpu_idcache_wbinv_range(va, len); 742 } 743 } 744 745 static inline void 746 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 747 bool do_inv, bool rd_only) 748 { 749 750 if (pm->pm_cstate.cs_cache_d) { 751 if (do_inv) { 752 if (rd_only) 753 cpu_dcache_inv_range(va, len); 754 else 755 cpu_dcache_wbinv_range(va, len); 756 } else 757 if (!rd_only) 758 cpu_dcache_wb_range(va, len); 759 } 760 } 761 762 static inline void 763 pmap_idcache_wbinv_all(pmap_t pm) 764 { 765 if (pm->pm_cstate.cs_cache_id) { 766 cpu_idcache_wbinv_all(); 767 pm->pm_cstate.cs_cache = 0; 768 } 769 } 770 771 static inline void 772 pmap_dcache_wbinv_all(pmap_t pm) 773 { 774 if (pm->pm_cstate.cs_cache_d) { 775 cpu_dcache_wbinv_all(); 776 pm->pm_cstate.cs_cache_d = 0; 777 } 778 } 779 #endif /* PMAP_CACHE_VIVT */ 780 781 static inline bool 782 pmap_is_current(pmap_t pm) 783 { 784 785 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 786 return true; 787 788 return false; 789 } 790 791 static inline bool 792 pmap_is_cached(pmap_t pm) 793 { 794 795 if (pm == pmap_kernel() || pmap_recent_user == NULL || 796 pmap_recent_user == pm) 797 return (true); 798 799 return false; 800 } 801 802 /* 803 * PTE_SYNC_CURRENT: 804 * 805 * Make sure the pte is written out to RAM. 806 * We need to do this for one of two cases: 807 * - We're dealing with the kernel pmap 808 * - There is no pmap active in the cache/tlb. 809 * - The specified pmap is 'active' in the cache/tlb. 810 */ 811 #ifdef PMAP_INCLUDE_PTE_SYNC 812 #define PTE_SYNC_CURRENT(pm, ptep) \ 813 do { \ 814 if (PMAP_NEEDS_PTE_SYNC && \ 815 pmap_is_cached(pm)) \ 816 PTE_SYNC(ptep); \ 817 } while (/*CONSTCOND*/0) 818 #else 819 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 820 #endif 821 822 /* 823 * main pv_entry manipulation functions: 824 * pmap_enter_pv: enter a mapping onto a vm_page list 825 * pmap_remove_pv: remove a mappiing from a vm_page list 826 * 827 * NOTE: pmap_enter_pv expects to lock the pvh itself 828 * pmap_remove_pv expects te caller to lock the pvh before calling 829 */ 830 831 /* 832 * pmap_enter_pv: enter a mapping onto a vm_page lst 833 * 834 * => caller should hold the proper lock on pmap_main_lock 835 * => caller should have pmap locked 836 * => we will gain the lock on the vm_page and allocate the new pv_entry 837 * => caller should adjust ptp's wire_count before calling 838 * => caller should not adjust pmap's wire_count 839 */ 840 static void 841 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 842 vaddr_t va, u_int flags) 843 { 844 struct pv_entry **pvp; 845 846 NPDEBUG(PDB_PVDUMP, 847 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 848 849 pve->pv_pmap = pm; 850 pve->pv_va = va; 851 pve->pv_flags = flags; 852 853 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 854 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 855 #ifdef PMAP_CACHE_VIPT 856 /* 857 * Insert unmapped entries at the head of the pv list. 858 */ 859 if (__predict_true((flags & PVF_KENTRY) == 0)) { 860 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 861 pvp = &SLIST_NEXT(*pvp, pv_link); 862 } 863 #endif 864 SLIST_NEXT(pve, pv_link) = *pvp; /* add to ... */ 865 *pvp = pve; /* ... locked list */ 866 #ifdef PMAP_CACHE_VIPT 867 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD | PVF_KENTRY); 868 if ((flags & PVF_MOD) && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 869 pg->mdpage.pvh_attrs |= PVF_DIRTY; 870 KASSERT((pg->mdpage.pvh_attrs & PVF_MOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 871 #endif 872 if (pm == pmap_kernel()) { 873 PMAPCOUNT(kernel_mappings); 874 if (flags & PVF_WRITE) 875 pg->mdpage.krw_mappings++; 876 else 877 pg->mdpage.kro_mappings++; 878 } else 879 if (flags & PVF_WRITE) 880 pg->mdpage.urw_mappings++; 881 else 882 pg->mdpage.uro_mappings++; 883 884 #ifdef PMAP_CACHE_VIPT 885 /* 886 * If this is an exec mapping and its the first exec mapping 887 * for this page, make sure to sync the I-cache. 888 */ 889 if (PV_IS_EXEC_P(flags)) { 890 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 891 pmap_syncicache_page(pg); 892 PMAPCOUNT(exec_synced_map); 893 } 894 PMAPCOUNT(exec_mappings); 895 } 896 #endif 897 898 PMAPCOUNT(mappings); 899 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 900 901 if (pve->pv_flags & PVF_WIRED) 902 ++pm->pm_stats.wired_count; 903 } 904 905 /* 906 * 907 * pmap_find_pv: Find a pv entry 908 * 909 * => caller should hold lock on vm_page 910 */ 911 static inline struct pv_entry * 912 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 913 { 914 struct pv_entry *pv; 915 916 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 917 if (pm == pv->pv_pmap && va == pv->pv_va) 918 break; 919 } 920 921 return (pv); 922 } 923 924 /* 925 * pmap_remove_pv: try to remove a mapping from a pv_list 926 * 927 * => caller should hold proper lock on pmap_main_lock 928 * => pmap should be locked 929 * => caller should hold lock on vm_page [so that attrs can be adjusted] 930 * => caller should adjust ptp's wire_count and free PTP if needed 931 * => caller should NOT adjust pmap's wire_count 932 * => we return the removed pve 933 */ 934 static struct pv_entry * 935 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 936 { 937 struct pv_entry *pve, **prevptr; 938 939 NPDEBUG(PDB_PVDUMP, 940 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 941 942 prevptr = &SLIST_FIRST(&pg->mdpage.pvh_list); /* prev pv_entry ptr */ 943 pve = *prevptr; 944 945 while (pve) { 946 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 947 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 948 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 949 if (pve->pv_flags & PVF_WIRED) { 950 if (skip_wired) 951 return (NULL); 952 --pm->pm_stats.wired_count; 953 } 954 #ifdef PMAP_CACHE_VIPT 955 /* 956 * If we are removing the first pv entry and its 957 * a KENTRY, if the next one isn't also a KENTER, 958 * clear KENTRY from the page attributes. 959 */ 960 if (SLIST_FIRST(&pg->mdpage.pvh_list) == pve 961 && (pve->pv_flags & PVF_KENTRY) 962 && (SLIST_NEXT(pve, pv_link) == NULL 963 || (SLIST_NEXT(pve, pv_link)->pv_flags & PVF_KENTRY) == 0)) 964 pg->mdpage.pvh_attrs &= ~PVF_KENTRY; 965 #endif 966 *prevptr = SLIST_NEXT(pve, pv_link); /* remove it! */ 967 if (pm == pmap_kernel()) { 968 PMAPCOUNT(kernel_unmappings); 969 if (pve->pv_flags & PVF_WRITE) 970 pg->mdpage.krw_mappings--; 971 else 972 pg->mdpage.kro_mappings--; 973 } else 974 if (pve->pv_flags & PVF_WRITE) 975 pg->mdpage.urw_mappings--; 976 else 977 pg->mdpage.uro_mappings--; 978 979 PMAPCOUNT(unmappings); 980 #ifdef PMAP_CACHE_VIPT 981 if (!(pve->pv_flags & PVF_WRITE)) 982 break; 983 /* 984 * If this page has had an exec mapping, then if 985 * this was the last mapping, discard the contents, 986 * otherwise sync the i-cache for this page. 987 */ 988 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 989 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 990 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 991 PMAPCOUNT(exec_discarded_unmap); 992 } else { 993 pmap_syncicache_page(pg); 994 PMAPCOUNT(exec_synced_unmap); 995 } 996 } 997 #endif /* PMAP_CACHE_VIPT */ 998 break; 999 } 1000 prevptr = &SLIST_NEXT(pve, pv_link); /* previous pointer */ 1001 pve = *prevptr; /* advance */ 1002 } 1003 1004 #ifdef PMAP_CACHE_VIPT 1005 /* 1006 * If this was a writeable page and there are no more writeable 1007 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1008 * the contents to memory. 1009 */ 1010 if ((pg->mdpage.pvh_attrs & PVF_WRITE) 1011 && pg->mdpage.krw_mappings + pg->mdpage.urw_mappings == 0) { 1012 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1013 #if 0 /* XYY */ 1014 if ((pg->mdpage.pvh_attrs & PVF_NC) == 0) 1015 pmap_flush_page(pg, false); 1016 #endif 1017 } 1018 #endif /* PMAP_CACHE_VIPT */ 1019 1020 return(pve); /* return removed pve */ 1021 } 1022 1023 /* 1024 * 1025 * pmap_modify_pv: Update pv flags 1026 * 1027 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1028 * => caller should NOT adjust pmap's wire_count 1029 * => caller must call pmap_vac_me_harder() if writable status of a page 1030 * may have changed. 1031 * => we return the old flags 1032 * 1033 * Modify a physical-virtual mapping in the pv table 1034 */ 1035 static u_int 1036 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 1037 u_int clr_mask, u_int set_mask) 1038 { 1039 struct pv_entry *npv; 1040 u_int flags, oflags; 1041 1042 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1043 return (0); 1044 1045 NPDEBUG(PDB_PVDUMP, 1046 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 1047 1048 /* 1049 * There is at least one VA mapping this page. 1050 */ 1051 1052 if (clr_mask & (PVF_REF | PVF_MOD)) { 1053 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1054 #ifdef PMAP_CACHE_VIPT 1055 if ((set_mask & PVF_MOD) && !(pg->mdpage.pvh_attrs & PVF_NC)) 1056 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1057 KASSERT((pg->mdpage.pvh_attrs & PVF_MOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1058 #endif 1059 } 1060 1061 oflags = npv->pv_flags; 1062 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1063 1064 if ((flags ^ oflags) & PVF_WIRED) { 1065 if (flags & PVF_WIRED) 1066 ++pm->pm_stats.wired_count; 1067 else 1068 --pm->pm_stats.wired_count; 1069 } 1070 1071 if ((flags ^ oflags) & PVF_WRITE) { 1072 if (pm == pmap_kernel()) { 1073 if (flags & PVF_WRITE) { 1074 pg->mdpage.krw_mappings++; 1075 pg->mdpage.kro_mappings--; 1076 } else { 1077 pg->mdpage.kro_mappings++; 1078 pg->mdpage.krw_mappings--; 1079 } 1080 } else 1081 if (flags & PVF_WRITE) { 1082 pg->mdpage.urw_mappings++; 1083 pg->mdpage.uro_mappings--; 1084 } else { 1085 pg->mdpage.uro_mappings++; 1086 pg->mdpage.urw_mappings--; 1087 } 1088 } 1089 #ifdef PMAP_CACHE_VIPT 1090 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 1091 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1092 /* 1093 * We have two cases here: the first is from enter_pv (new exec 1094 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1095 * Since in latter, pmap_enter_pv won't do anything, we just have 1096 * to do what pmap_remove_pv would do. 1097 */ 1098 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1099 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1100 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1101 pmap_syncicache_page(pg); 1102 PMAPCOUNT(exec_synced_remap); 1103 } 1104 #endif 1105 1106 PMAPCOUNT(remappings); 1107 1108 return (oflags); 1109 } 1110 1111 /* 1112 * Allocate an L1 translation table for the specified pmap. 1113 * This is called at pmap creation time. 1114 */ 1115 static void 1116 pmap_alloc_l1(pmap_t pm) 1117 { 1118 struct l1_ttable *l1; 1119 u_int8_t domain; 1120 1121 /* 1122 * Remove the L1 at the head of the LRU list 1123 */ 1124 simple_lock(&l1_lru_lock); 1125 l1 = TAILQ_FIRST(&l1_lru_list); 1126 KDASSERT(l1 != NULL); 1127 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1128 1129 /* 1130 * Pick the first available domain number, and update 1131 * the link to the next number. 1132 */ 1133 domain = l1->l1_domain_first; 1134 l1->l1_domain_first = l1->l1_domain_free[domain]; 1135 1136 /* 1137 * If there are still free domain numbers in this L1, 1138 * put it back on the TAIL of the LRU list. 1139 */ 1140 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1141 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1142 1143 simple_unlock(&l1_lru_lock); 1144 1145 /* 1146 * Fix up the relevant bits in the pmap structure 1147 */ 1148 pm->pm_l1 = l1; 1149 pm->pm_domain = domain; 1150 } 1151 1152 /* 1153 * Free an L1 translation table. 1154 * This is called at pmap destruction time. 1155 */ 1156 static void 1157 pmap_free_l1(pmap_t pm) 1158 { 1159 struct l1_ttable *l1 = pm->pm_l1; 1160 1161 simple_lock(&l1_lru_lock); 1162 1163 /* 1164 * If this L1 is currently on the LRU list, remove it. 1165 */ 1166 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1167 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1168 1169 /* 1170 * Free up the domain number which was allocated to the pmap 1171 */ 1172 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1173 l1->l1_domain_first = pm->pm_domain; 1174 l1->l1_domain_use_count--; 1175 1176 /* 1177 * The L1 now must have at least 1 free domain, so add 1178 * it back to the LRU list. If the use count is zero, 1179 * put it at the head of the list, otherwise it goes 1180 * to the tail. 1181 */ 1182 if (l1->l1_domain_use_count == 0) 1183 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1184 else 1185 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1186 1187 simple_unlock(&l1_lru_lock); 1188 } 1189 1190 static inline void 1191 pmap_use_l1(pmap_t pm) 1192 { 1193 struct l1_ttable *l1; 1194 1195 /* 1196 * Do nothing if we're in interrupt context. 1197 * Access to an L1 by the kernel pmap must not affect 1198 * the LRU list. 1199 */ 1200 if (cpu_intr_p() || pm == pmap_kernel()) 1201 return; 1202 1203 l1 = pm->pm_l1; 1204 1205 /* 1206 * If the L1 is not currently on the LRU list, just return 1207 */ 1208 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1209 return; 1210 1211 simple_lock(&l1_lru_lock); 1212 1213 /* 1214 * Check the use count again, now that we've acquired the lock 1215 */ 1216 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1217 simple_unlock(&l1_lru_lock); 1218 return; 1219 } 1220 1221 /* 1222 * Move the L1 to the back of the LRU list 1223 */ 1224 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1225 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1226 1227 simple_unlock(&l1_lru_lock); 1228 } 1229 1230 /* 1231 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1232 * 1233 * Free an L2 descriptor table. 1234 */ 1235 static inline void 1236 #ifndef PMAP_INCLUDE_PTE_SYNC 1237 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1238 #else 1239 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1240 #endif 1241 { 1242 #ifdef PMAP_INCLUDE_PTE_SYNC 1243 #ifdef PMAP_CACHE_VIVT 1244 /* 1245 * Note: With a write-back cache, we may need to sync this 1246 * L2 table before re-using it. 1247 * This is because it may have belonged to a non-current 1248 * pmap, in which case the cache syncs would have been 1249 * skipped for the pages that were being unmapped. If the 1250 * L2 table were then to be immediately re-allocated to 1251 * the *current* pmap, it may well contain stale mappings 1252 * which have not yet been cleared by a cache write-back 1253 * and so would still be visible to the mmu. 1254 */ 1255 if (need_sync) 1256 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1257 #endif /* PMAP_CACHE_VIVT */ 1258 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1259 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1260 } 1261 1262 /* 1263 * Returns a pointer to the L2 bucket associated with the specified pmap 1264 * and VA, or NULL if no L2 bucket exists for the address. 1265 */ 1266 static inline struct l2_bucket * 1267 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1268 { 1269 struct l2_dtable *l2; 1270 struct l2_bucket *l2b; 1271 u_short l1idx; 1272 1273 l1idx = L1_IDX(va); 1274 1275 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1276 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1277 return (NULL); 1278 1279 return (l2b); 1280 } 1281 1282 /* 1283 * Returns a pointer to the L2 bucket associated with the specified pmap 1284 * and VA. 1285 * 1286 * If no L2 bucket exists, perform the necessary allocations to put an L2 1287 * bucket/page table in place. 1288 * 1289 * Note that if a new L2 bucket/page was allocated, the caller *must* 1290 * increment the bucket occupancy counter appropriately *before* 1291 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1292 * the bucket/page in the meantime. 1293 */ 1294 static struct l2_bucket * 1295 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1296 { 1297 struct l2_dtable *l2; 1298 struct l2_bucket *l2b; 1299 u_short l1idx; 1300 1301 l1idx = L1_IDX(va); 1302 1303 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1304 /* 1305 * No mapping at this address, as there is 1306 * no entry in the L1 table. 1307 * Need to allocate a new l2_dtable. 1308 */ 1309 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1310 return (NULL); 1311 1312 /* 1313 * Link it into the parent pmap 1314 */ 1315 pm->pm_l2[L2_IDX(l1idx)] = l2; 1316 } 1317 1318 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1319 1320 /* 1321 * Fetch pointer to the L2 page table associated with the address. 1322 */ 1323 if (l2b->l2b_kva == NULL) { 1324 pt_entry_t *ptep; 1325 1326 /* 1327 * No L2 page table has been allocated. Chances are, this 1328 * is because we just allocated the l2_dtable, above. 1329 */ 1330 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1331 /* 1332 * Oops, no more L2 page tables available at this 1333 * time. We may need to deallocate the l2_dtable 1334 * if we allocated a new one above. 1335 */ 1336 if (l2->l2_occupancy == 0) { 1337 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1338 pmap_free_l2_dtable(l2); 1339 } 1340 return (NULL); 1341 } 1342 1343 l2->l2_occupancy++; 1344 l2b->l2b_kva = ptep; 1345 l2b->l2b_l1idx = l1idx; 1346 } 1347 1348 return (l2b); 1349 } 1350 1351 /* 1352 * One or more mappings in the specified L2 descriptor table have just been 1353 * invalidated. 1354 * 1355 * Garbage collect the metadata and descriptor table itself if necessary. 1356 * 1357 * The pmap lock must be acquired when this is called (not necessary 1358 * for the kernel pmap). 1359 */ 1360 static void 1361 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1362 { 1363 struct l2_dtable *l2; 1364 pd_entry_t *pl1pd, l1pd; 1365 pt_entry_t *ptep; 1366 u_short l1idx; 1367 1368 KDASSERT(count <= l2b->l2b_occupancy); 1369 1370 /* 1371 * Update the bucket's reference count according to how many 1372 * PTEs the caller has just invalidated. 1373 */ 1374 l2b->l2b_occupancy -= count; 1375 1376 /* 1377 * Note: 1378 * 1379 * Level 2 page tables allocated to the kernel pmap are never freed 1380 * as that would require checking all Level 1 page tables and 1381 * removing any references to the Level 2 page table. See also the 1382 * comment elsewhere about never freeing bootstrap L2 descriptors. 1383 * 1384 * We make do with just invalidating the mapping in the L2 table. 1385 * 1386 * This isn't really a big deal in practice and, in fact, leads 1387 * to a performance win over time as we don't need to continually 1388 * alloc/free. 1389 */ 1390 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1391 return; 1392 1393 /* 1394 * There are no more valid mappings in this level 2 page table. 1395 * Go ahead and NULL-out the pointer in the bucket, then 1396 * free the page table. 1397 */ 1398 l1idx = l2b->l2b_l1idx; 1399 ptep = l2b->l2b_kva; 1400 l2b->l2b_kva = NULL; 1401 1402 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1403 1404 /* 1405 * If the L1 slot matches the pmap's domain 1406 * number, then invalidate it. 1407 */ 1408 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1409 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1410 *pl1pd = 0; 1411 PTE_SYNC(pl1pd); 1412 } 1413 1414 /* 1415 * Release the L2 descriptor table back to the pool cache. 1416 */ 1417 #ifndef PMAP_INCLUDE_PTE_SYNC 1418 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1419 #else 1420 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1421 #endif 1422 1423 /* 1424 * Update the reference count in the associated l2_dtable 1425 */ 1426 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1427 if (--l2->l2_occupancy > 0) 1428 return; 1429 1430 /* 1431 * There are no more valid mappings in any of the Level 1 1432 * slots managed by this l2_dtable. Go ahead and NULL-out 1433 * the pointer in the parent pmap and free the l2_dtable. 1434 */ 1435 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1436 pmap_free_l2_dtable(l2); 1437 } 1438 1439 /* 1440 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1441 * structures. 1442 */ 1443 static int 1444 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1445 { 1446 #ifndef PMAP_INCLUDE_PTE_SYNC 1447 struct l2_bucket *l2b; 1448 pt_entry_t *ptep, pte; 1449 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1450 1451 /* 1452 * The mappings for these page tables were initially made using 1453 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1454 * mode will not be right for page table mappings. To avoid 1455 * polluting the pmap_kenter_pa() code with a special case for 1456 * page tables, we simply fix up the cache-mode here if it's not 1457 * correct. 1458 */ 1459 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1460 KDASSERT(l2b != NULL); 1461 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1462 pte = *ptep; 1463 1464 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1465 /* 1466 * Page tables must have the cache-mode set to Write-Thru. 1467 */ 1468 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1469 PTE_SYNC(ptep); 1470 cpu_tlb_flushD_SE(va); 1471 cpu_cpwait(); 1472 } 1473 #endif 1474 1475 memset(v, 0, L2_TABLE_SIZE_REAL); 1476 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1477 return (0); 1478 } 1479 1480 static int 1481 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1482 { 1483 1484 memset(v, 0, sizeof(struct l2_dtable)); 1485 return (0); 1486 } 1487 1488 static int 1489 pmap_pmap_ctor(void *arg, void *v, int flags) 1490 { 1491 1492 memset(v, 0, sizeof(struct pmap)); 1493 return (0); 1494 } 1495 1496 static void 1497 pmap_pinit(pmap_t pm) 1498 { 1499 struct l2_bucket *l2b; 1500 1501 if (vector_page < KERNEL_BASE) { 1502 /* 1503 * Map the vector page. 1504 */ 1505 pmap_enter(pm, vector_page, systempage.pv_pa, 1506 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1507 pmap_update(pm); 1508 1509 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1510 l2b = pmap_get_l2_bucket(pm, vector_page); 1511 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1512 L1_C_DOM(pm->pm_domain); 1513 } else 1514 pm->pm_pl1vec = NULL; 1515 } 1516 1517 #ifdef PMAP_CACHE_VIVT 1518 /* 1519 * Since we have a virtually indexed cache, we may need to inhibit caching if 1520 * there is more than one mapping and at least one of them is writable. 1521 * Since we purge the cache on every context switch, we only need to check for 1522 * other mappings within the same pmap, or kernel_pmap. 1523 * This function is also called when a page is unmapped, to possibly reenable 1524 * caching on any remaining mappings. 1525 * 1526 * The code implements the following logic, where: 1527 * 1528 * KW = # of kernel read/write pages 1529 * KR = # of kernel read only pages 1530 * UW = # of user read/write pages 1531 * UR = # of user read only pages 1532 * 1533 * KC = kernel mapping is cacheable 1534 * UC = user mapping is cacheable 1535 * 1536 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1537 * +--------------------------------------------- 1538 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1539 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1540 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1541 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1542 */ 1543 1544 static const int pmap_vac_flags[4][4] = { 1545 {-1, 0, 0, PVF_KNC}, 1546 {0, 0, PVF_NC, PVF_NC}, 1547 {0, PVF_NC, PVF_NC, PVF_NC}, 1548 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1549 }; 1550 1551 static inline int 1552 pmap_get_vac_flags(const struct vm_page *pg) 1553 { 1554 int kidx, uidx; 1555 1556 kidx = 0; 1557 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1558 kidx |= 1; 1559 if (pg->mdpage.krw_mappings) 1560 kidx |= 2; 1561 1562 uidx = 0; 1563 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1564 uidx |= 1; 1565 if (pg->mdpage.urw_mappings) 1566 uidx |= 2; 1567 1568 return (pmap_vac_flags[uidx][kidx]); 1569 } 1570 1571 static inline void 1572 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1573 { 1574 int nattr; 1575 1576 nattr = pmap_get_vac_flags(pg); 1577 1578 if (nattr < 0) { 1579 pg->mdpage.pvh_attrs &= ~PVF_NC; 1580 return; 1581 } 1582 1583 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1584 return; 1585 1586 if (pm == pmap_kernel()) 1587 pmap_vac_me_kpmap(pg, pm, va); 1588 else 1589 pmap_vac_me_user(pg, pm, va); 1590 1591 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1592 } 1593 1594 static void 1595 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1596 { 1597 u_int u_cacheable, u_entries; 1598 struct pv_entry *pv; 1599 pmap_t last_pmap = pm; 1600 1601 /* 1602 * Pass one, see if there are both kernel and user pmaps for 1603 * this page. Calculate whether there are user-writable or 1604 * kernel-writable pages. 1605 */ 1606 u_cacheable = 0; 1607 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1608 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1609 u_cacheable++; 1610 } 1611 1612 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1613 1614 /* 1615 * We know we have just been updating a kernel entry, so if 1616 * all user pages are already cacheable, then there is nothing 1617 * further to do. 1618 */ 1619 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1620 return; 1621 1622 if (u_entries) { 1623 /* 1624 * Scan over the list again, for each entry, if it 1625 * might not be set correctly, call pmap_vac_me_user 1626 * to recalculate the settings. 1627 */ 1628 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1629 /* 1630 * We know kernel mappings will get set 1631 * correctly in other calls. We also know 1632 * that if the pmap is the same as last_pmap 1633 * then we've just handled this entry. 1634 */ 1635 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1636 continue; 1637 1638 /* 1639 * If there are kernel entries and this page 1640 * is writable but non-cacheable, then we can 1641 * skip this entry also. 1642 */ 1643 if (pg->mdpage.k_mappings && 1644 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1645 (PVF_NC | PVF_WRITE)) 1646 continue; 1647 1648 /* 1649 * Similarly if there are no kernel-writable 1650 * entries and the page is already 1651 * read-only/cacheable. 1652 */ 1653 if (pg->mdpage.krw_mappings == 0 && 1654 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1655 continue; 1656 1657 /* 1658 * For some of the remaining cases, we know 1659 * that we must recalculate, but for others we 1660 * can't tell if they are correct or not, so 1661 * we recalculate anyway. 1662 */ 1663 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1664 } 1665 1666 if (pg->mdpage.k_mappings == 0) 1667 return; 1668 } 1669 1670 pmap_vac_me_user(pg, pm, va); 1671 } 1672 1673 static void 1674 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1675 { 1676 pmap_t kpmap = pmap_kernel(); 1677 struct pv_entry *pv, *npv; 1678 struct l2_bucket *l2b; 1679 pt_entry_t *ptep, pte; 1680 u_int entries = 0; 1681 u_int writable = 0; 1682 u_int cacheable_entries = 0; 1683 u_int kern_cacheable = 0; 1684 u_int other_writable = 0; 1685 1686 /* 1687 * Count mappings and writable mappings in this pmap. 1688 * Include kernel mappings as part of our own. 1689 * Keep a pointer to the first one. 1690 */ 1691 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1692 /* Count mappings in the same pmap */ 1693 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1694 if (entries++ == 0) 1695 npv = pv; 1696 1697 /* Cacheable mappings */ 1698 if ((pv->pv_flags & PVF_NC) == 0) { 1699 cacheable_entries++; 1700 if (kpmap == pv->pv_pmap) 1701 kern_cacheable++; 1702 } 1703 1704 /* Writable mappings */ 1705 if (pv->pv_flags & PVF_WRITE) 1706 ++writable; 1707 } else 1708 if (pv->pv_flags & PVF_WRITE) 1709 other_writable = 1; 1710 } 1711 1712 /* 1713 * Enable or disable caching as necessary. 1714 * Note: the first entry might be part of the kernel pmap, 1715 * so we can't assume this is indicative of the state of the 1716 * other (maybe non-kpmap) entries. 1717 */ 1718 if ((entries > 1 && writable) || 1719 (entries > 0 && pm == kpmap && other_writable)) { 1720 if (cacheable_entries == 0) 1721 return; 1722 1723 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1724 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1725 (pv->pv_flags & PVF_NC)) 1726 continue; 1727 1728 pv->pv_flags |= PVF_NC; 1729 1730 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1731 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1732 pte = *ptep & ~L2_S_CACHE_MASK; 1733 1734 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1735 l2pte_valid(pte)) { 1736 if (PV_BEEN_EXECD(pv->pv_flags)) { 1737 #ifdef PMAP_CACHE_VIVT 1738 pmap_idcache_wbinv_range(pv->pv_pmap, 1739 pv->pv_va, PAGE_SIZE); 1740 #endif 1741 pmap_tlb_flushID_SE(pv->pv_pmap, 1742 pv->pv_va); 1743 } else 1744 if (PV_BEEN_REFD(pv->pv_flags)) { 1745 #ifdef PMAP_CACHE_VIVT 1746 pmap_dcache_wb_range(pv->pv_pmap, 1747 pv->pv_va, PAGE_SIZE, true, 1748 (pv->pv_flags & PVF_WRITE) == 0); 1749 #endif 1750 pmap_tlb_flushD_SE(pv->pv_pmap, 1751 pv->pv_va); 1752 } 1753 } 1754 1755 *ptep = pte; 1756 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1757 } 1758 cpu_cpwait(); 1759 } else 1760 if (entries > cacheable_entries) { 1761 /* 1762 * Turn cacheing back on for some pages. If it is a kernel 1763 * page, only do so if there are no other writable pages. 1764 */ 1765 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1766 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1767 (kpmap != pv->pv_pmap || other_writable))) 1768 continue; 1769 1770 pv->pv_flags &= ~PVF_NC; 1771 1772 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1773 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1774 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1775 1776 if (l2pte_valid(pte)) { 1777 if (PV_BEEN_EXECD(pv->pv_flags)) { 1778 pmap_tlb_flushID_SE(pv->pv_pmap, 1779 pv->pv_va); 1780 } else 1781 if (PV_BEEN_REFD(pv->pv_flags)) { 1782 pmap_tlb_flushD_SE(pv->pv_pmap, 1783 pv->pv_va); 1784 } 1785 } 1786 1787 *ptep = pte; 1788 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1789 } 1790 } 1791 } 1792 #endif 1793 1794 #ifdef PMAP_CACHE_VIPT 1795 /* 1796 * For virtually indexed / physically tagged caches, what we have to worry 1797 * about is illegal cache aliases. To prevent this, we must ensure that 1798 * virtual addresses that map the physical page use the same bits for those 1799 * bits masked by "arm_cache_prefer_mask" (bits 12+). If there is a conflict, 1800 * all mappings of the page must be non-cached. 1801 */ 1802 #if 0 1803 static inline vaddr_t 1804 pmap_check_sets(paddr_t pa) 1805 { 1806 extern int arm_dcache_l2_nsets; 1807 int set, way; 1808 vaddr_t mask = 0; 1809 int v; 1810 pa |= 1; 1811 for (set = 0; set < (1 << arm_dcache_l2_nsets); set++) { 1812 for (way = 0; way < 4; way++) { 1813 v = (way << 30) | (set << 5); 1814 asm("mcr p15, 3, %0, c15, c2, 0" :: "r"(v)); 1815 asm("mrc p15, 3, %0, c15, c0, 0" : "=r"(v)); 1816 1817 if ((v & (1 | ~(PAGE_SIZE-1))) == pa) { 1818 mask |= 1 << (set >> 7); 1819 } 1820 } 1821 } 1822 return mask; 1823 } 1824 #endif 1825 static void 1826 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1827 { 1828 struct pv_entry *pv; 1829 vaddr_t tst_mask; 1830 bool bad_alias; 1831 struct l2_bucket *l2b; 1832 pt_entry_t *ptep, pte, opte; 1833 const u_int 1834 rw_mappings = pg->mdpage.urw_mappings + pg->mdpage.krw_mappings, 1835 ro_mappings = pg->mdpage.uro_mappings + pg->mdpage.kro_mappings; 1836 1837 /* do we need to do anything? */ 1838 if (arm_cache_prefer_mask == 0) 1839 return; 1840 1841 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1842 pg, pm, va)); 1843 1844 #define popc4(x) \ 1845 (((0x94 >> ((x & 3) << 1)) & 3) + ((0x94 >> ((x & 12) >> 1)) & 3)) 1846 #if 0 1847 tst_mask = pmap_check_sets(pg->phys_addr); 1848 KASSERT(popc4(tst_mask) < 2); 1849 #endif 1850 1851 KASSERT(!va || pm); 1852 1853 /* Already a conflict? */ 1854 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1855 /* just an add, things are already non-cached */ 1856 KASSERT(!(pg->mdpage.pvh_attrs & PVF_DIRTY)); 1857 bad_alias = false; 1858 if (va) { 1859 PMAPCOUNT(vac_color_none); 1860 bad_alias = true; 1861 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1862 goto fixup; 1863 } 1864 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1865 /* the list can't be empty because it would be cachable */ 1866 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) { 1867 tst_mask = pg->mdpage.pvh_attrs; 1868 } else { 1869 KASSERT(pv); 1870 tst_mask = pv->pv_va; 1871 pv = SLIST_NEXT(pv, pv_link); 1872 } 1873 /* 1874 * Only check for a bad alias if we have writable mappings. 1875 */ 1876 tst_mask &= arm_cache_prefer_mask; 1877 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1878 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1879 /* if there's a bad alias, stop checking. */ 1880 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1881 bad_alias = true; 1882 } 1883 pg->mdpage.pvh_attrs |= PVF_WRITE; 1884 if (!bad_alias) 1885 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1886 } else { 1887 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1888 } 1889 /* If no conflicting colors, set everything back to cached */ 1890 if (!bad_alias) { 1891 #ifdef DEBUG 1892 if ((pg->mdpage.pvh_attrs & PVF_WRITE) 1893 || ro_mappings < 2) { 1894 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1895 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1896 } 1897 1898 #endif 1899 if (ro_mappings > 1 1900 && (pg->mdpage.pvh_attrs & PVF_DIRTY)) 1901 pmap_flush_page(pg, false); 1902 1903 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1904 pg->mdpage.pvh_attrs |= tst_mask | PVF_COLORED; 1905 PMAPCOUNT(vac_color_restore); 1906 } else { 1907 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1908 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1909 } 1910 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1911 } else if (!va) { 1912 KASSERT(pmap_is_page_colored_p(pg)); 1913 KASSERT(!(pg->mdpage.pvh_attrs & PVF_WRITE) 1914 || (pg->mdpage.pvh_attrs & PVF_DIRTY)); 1915 if (rw_mappings == 0) 1916 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1917 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1918 return; 1919 } else if (!pmap_is_page_colored_p(pg)) { 1920 /* not colored so we just use its color */ 1921 KASSERT(pg->mdpage.pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1922 PMAPCOUNT(vac_color_new); 1923 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1924 pg->mdpage.pvh_attrs |= PVF_COLORED 1925 | (va & arm_cache_prefer_mask) 1926 | (rw_mappings > 0 ? PVF_WRITE : 0); 1927 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1928 return; 1929 } else if (((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1930 bad_alias = false; 1931 if (rw_mappings > 0) { 1932 /* 1933 * We now have writeable mappings and more than one 1934 * readonly mapping, verify the colors don't clash 1935 * and mark the page as writeable. 1936 */ 1937 if (ro_mappings > 1 1938 && (pg->mdpage.pvh_attrs & PVF_WRITE) == 0 1939 && arm_cache_prefer_mask) { 1940 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1941 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1942 /* if there's a bad alias, stop checking. */ 1943 if (((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0) { 1944 bad_alias = true; 1945 break; 1946 } 1947 } 1948 } 1949 pg->mdpage.pvh_attrs |= PVF_WRITE; 1950 } 1951 /* If no conflicting colors, set everything back to cached */ 1952 if (!bad_alias) { 1953 #ifdef DEBUG 1954 if (rw_mappings > 0 1955 || (pg->mdpage.pvh_attrs & PMAP_KMPAGE)) { 1956 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1957 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1958 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1959 } 1960 #endif 1961 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) 1962 PMAPCOUNT(vac_color_reuse); 1963 else 1964 PMAPCOUNT(vac_color_ok); 1965 1966 /* matching color, just return */ 1967 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1968 return; 1969 } 1970 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1971 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1972 1973 /* color conflict. evict from cache. */ 1974 1975 pmap_flush_page(pg, true); 1976 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 1977 pg->mdpage.pvh_attrs |= PVF_NC; 1978 PMAPCOUNT(vac_color_erase); 1979 } else if (rw_mappings == 0 1980 && (pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 1981 KASSERT((pg->mdpage.pvh_attrs & PVF_WRITE) == 0); 1982 1983 /* 1984 * If the page has dirty cache lines, clean it. 1985 */ 1986 if (pg->mdpage.pvh_attrs & PVF_DIRTY) 1987 pmap_flush_page(pg, false); 1988 1989 /* 1990 * If this is the first remapping (we know that there are no 1991 * writeable mappings), then this is a simple color change. 1992 * Otherwise this is a seconary r/o mapping, which means 1993 * we don't have to do anything. 1994 */ 1995 if (ro_mappings == 1) { 1996 KASSERT(((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 1997 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1998 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 1999 PMAPCOUNT(vac_color_change); 2000 } else { 2001 PMAPCOUNT(vac_color_blind); 2002 } 2003 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2004 return; 2005 } else { 2006 if (rw_mappings > 0) 2007 pg->mdpage.pvh_attrs |= PVF_WRITE; 2008 2009 /* color conflict. evict from cache. */ 2010 pmap_flush_page(pg, true); 2011 2012 /* the list can't be empty because this was a enter/modify */ 2013 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2014 if ((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2015 KASSERT(pv); 2016 /* 2017 * If there's only one mapped page, change color to the 2018 * page's new color and return. 2019 */ 2020 if (SLIST_NEXT(pv, pv_link) == NULL) { 2021 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2022 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2023 PMAPCOUNT(vac_color_change); 2024 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2025 return; 2026 } 2027 } 2028 bad_alias = true; 2029 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2030 pg->mdpage.pvh_attrs |= PVF_NC; 2031 PMAPCOUNT(vac_color_erase); 2032 } 2033 2034 fixup: 2035 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2036 2037 /* 2038 * Turn cacheing on/off for all pages. 2039 */ 2040 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2041 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2042 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2043 opte = *ptep; 2044 pte = opte & ~L2_S_CACHE_MASK; 2045 if (bad_alias) { 2046 pv->pv_flags |= PVF_NC; 2047 } else { 2048 pv->pv_flags &= ~PVF_NC; 2049 pte |= pte_l2_s_cache_mode; 2050 } 2051 2052 if (opte == pte) /* only update is there's a change */ 2053 continue; 2054 2055 if (l2pte_valid(pte)) { 2056 if (PV_BEEN_EXECD(pv->pv_flags)) { 2057 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2058 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2059 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2060 } 2061 } 2062 2063 *ptep = pte; 2064 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2065 } 2066 } 2067 #endif /* PMAP_CACHE_VIPT */ 2068 2069 2070 /* 2071 * Modify pte bits for all ptes corresponding to the given physical address. 2072 * We use `maskbits' rather than `clearbits' because we're always passing 2073 * constants and the latter would require an extra inversion at run-time. 2074 */ 2075 static void 2076 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2077 { 2078 struct l2_bucket *l2b; 2079 struct pv_entry *pv; 2080 pt_entry_t *ptep, npte, opte; 2081 pmap_t pm; 2082 vaddr_t va; 2083 u_int oflags; 2084 #ifdef PMAP_CACHE_VIPT 2085 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 2086 bool need_syncicache = false; 2087 bool did_syncicache = false; 2088 bool need_vac_me_harder = false; 2089 #endif 2090 2091 NPDEBUG(PDB_BITS, 2092 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2093 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2094 2095 PMAP_HEAD_TO_MAP_LOCK(); 2096 simple_lock(&pg->mdpage.pvh_slock); 2097 2098 #ifdef PMAP_CACHE_VIPT 2099 /* 2100 * If we might want to sync the I-cache and we've modified it, 2101 * then we know we definitely need to sync or discard it. 2102 */ 2103 if (want_syncicache) 2104 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 2105 #endif 2106 /* 2107 * Clear saved attributes (modify, reference) 2108 */ 2109 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2110 2111 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 2112 #ifdef PMAP_CACHE_VIPT 2113 if (need_syncicache) { 2114 /* 2115 * No one has it mapped, so just discard it. The next 2116 * exec remapping will cause it to be synced. 2117 */ 2118 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2119 PMAPCOUNT(exec_discarded_clearbit); 2120 } 2121 #endif 2122 simple_unlock(&pg->mdpage.pvh_slock); 2123 PMAP_HEAD_TO_MAP_UNLOCK(); 2124 return; 2125 } 2126 2127 /* 2128 * Loop over all current mappings setting/clearing as appropos 2129 */ 2130 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2131 va = pv->pv_va; 2132 pm = pv->pv_pmap; 2133 oflags = pv->pv_flags; 2134 pv->pv_flags &= ~maskbits; 2135 2136 pmap_acquire_pmap_lock(pm); 2137 2138 l2b = pmap_get_l2_bucket(pm, va); 2139 KDASSERT(l2b != NULL); 2140 2141 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2142 npte = opte = *ptep; 2143 2144 NPDEBUG(PDB_BITS, 2145 printf( 2146 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2147 pv, pv->pv_pmap, pv->pv_va, oflags)); 2148 2149 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2150 #ifdef PMAP_CACHE_VIVT 2151 if ((pv->pv_flags & PVF_NC)) { 2152 /* 2153 * Entry is not cacheable: 2154 * 2155 * Don't turn caching on again if this is a 2156 * modified emulation. This would be 2157 * inconsitent with the settings created by 2158 * pmap_vac_me_harder(). Otherwise, it's safe 2159 * to re-enable cacheing. 2160 * 2161 * There's no need to call pmap_vac_me_harder() 2162 * here: all pages are losing their write 2163 * permission. 2164 */ 2165 if (maskbits & PVF_WRITE) { 2166 npte |= pte_l2_s_cache_mode; 2167 pv->pv_flags &= ~PVF_NC; 2168 } 2169 } else 2170 if (opte & L2_S_PROT_W) { 2171 /* 2172 * Entry is writable/cacheable: check if pmap 2173 * is current if it is flush it, otherwise it 2174 * won't be in the cache 2175 */ 2176 if (PV_BEEN_EXECD(oflags)) 2177 pmap_idcache_wbinv_range(pm, pv->pv_va, 2178 PAGE_SIZE); 2179 else 2180 if (PV_BEEN_REFD(oflags)) 2181 pmap_dcache_wb_range(pm, pv->pv_va, 2182 PAGE_SIZE, 2183 (maskbits & PVF_REF) != 0, false); 2184 } 2185 #endif 2186 2187 /* make the pte read only */ 2188 npte &= ~L2_S_PROT_W; 2189 2190 if (maskbits & oflags & PVF_WRITE) { 2191 /* 2192 * Keep alias accounting up to date 2193 */ 2194 if (pv->pv_pmap == pmap_kernel()) { 2195 pg->mdpage.krw_mappings--; 2196 pg->mdpage.kro_mappings++; 2197 } else { 2198 pg->mdpage.urw_mappings--; 2199 pg->mdpage.uro_mappings++; 2200 } 2201 #ifdef PMAP_CACHE_VIPT 2202 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 2203 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2204 if (want_syncicache) 2205 need_syncicache = true; 2206 need_vac_me_harder = true; 2207 #endif 2208 } 2209 } 2210 2211 if (maskbits & PVF_REF) { 2212 if ((pv->pv_flags & PVF_NC) == 0 && 2213 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2214 l2pte_valid(npte)) { 2215 #ifdef PMAP_CACHE_VIVT 2216 /* 2217 * Check npte here; we may have already 2218 * done the wbinv above, and the validity 2219 * of the PTE is the same for opte and 2220 * npte. 2221 */ 2222 /* XXXJRT need idcache_inv_range */ 2223 if (PV_BEEN_EXECD(oflags)) 2224 pmap_idcache_wbinv_range(pm, 2225 pv->pv_va, PAGE_SIZE); 2226 else 2227 if (PV_BEEN_REFD(oflags)) 2228 pmap_dcache_wb_range(pm, 2229 pv->pv_va, PAGE_SIZE, 2230 true, true); 2231 #endif 2232 } 2233 2234 /* 2235 * Make the PTE invalid so that we will take a 2236 * page fault the next time the mapping is 2237 * referenced. 2238 */ 2239 npte &= ~L2_TYPE_MASK; 2240 npte |= L2_TYPE_INV; 2241 } 2242 2243 if (npte != opte) { 2244 *ptep = npte; 2245 PTE_SYNC(ptep); 2246 /* Flush the TLB entry if a current pmap. */ 2247 if (PV_BEEN_EXECD(oflags)) 2248 pmap_tlb_flushID_SE(pm, pv->pv_va); 2249 else 2250 if (PV_BEEN_REFD(oflags)) 2251 pmap_tlb_flushD_SE(pm, pv->pv_va); 2252 } 2253 2254 pmap_release_pmap_lock(pm); 2255 2256 NPDEBUG(PDB_BITS, 2257 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2258 pm, va, opte, npte)); 2259 } 2260 2261 #ifdef PMAP_CACHE_VIPT 2262 /* 2263 * If we need to sync the I-cache and we haven't done it yet, do it. 2264 */ 2265 if (need_syncicache && !did_syncicache) { 2266 pmap_syncicache_page(pg); 2267 PMAPCOUNT(exec_synced_clearbit); 2268 } 2269 /* 2270 * If we are changing this to read-only, we ned to call vac_me_harder 2271 * so we can change all the read-only pages to cacheable. We pretend 2272 * this as a page deletion. 2273 */ 2274 if (need_vac_me_harder) { 2275 if (pg->mdpage.pvh_attrs & PVF_NC) 2276 pmap_vac_me_harder(pg, NULL, 0); 2277 #if 0 /* XYY */ 2278 else 2279 pmap_flush_page(pg, false); 2280 #endif 2281 } 2282 #endif 2283 2284 simple_unlock(&pg->mdpage.pvh_slock); 2285 PMAP_HEAD_TO_MAP_UNLOCK(); 2286 } 2287 2288 /* 2289 * pmap_clean_page() 2290 * 2291 * This is a local function used to work out the best strategy to clean 2292 * a single page referenced by its entry in the PV table. It's used by 2293 * pmap_copy_page, pmap_zero page and maybe some others later on. 2294 * 2295 * Its policy is effectively: 2296 * o If there are no mappings, we don't bother doing anything with the cache. 2297 * o If there is one mapping, we clean just that page. 2298 * o If there are multiple mappings, we clean the entire cache. 2299 * 2300 * So that some functions can be further optimised, it returns 0 if it didn't 2301 * clean the entire cache, or 1 if it did. 2302 * 2303 * XXX One bug in this routine is that if the pv_entry has a single page 2304 * mapped at 0x00000000 a whole cache clean will be performed rather than 2305 * just the 1 page. Since this should not occur in everyday use and if it does 2306 * it will just result in not the most efficient clean for the page. 2307 */ 2308 #ifdef PMAP_CACHE_VIVT 2309 static int 2310 pmap_clean_page(struct pv_entry *pv, bool is_src) 2311 { 2312 pmap_t pm, pm_to_clean = NULL; 2313 struct pv_entry *npv; 2314 u_int cache_needs_cleaning = 0; 2315 u_int flags = 0; 2316 vaddr_t page_to_clean = 0; 2317 2318 if (pv == NULL) { 2319 /* nothing mapped in so nothing to flush */ 2320 return (0); 2321 } 2322 2323 /* 2324 * Since we flush the cache each time we change to a different 2325 * user vmspace, we only need to flush the page if it is in the 2326 * current pmap. 2327 */ 2328 pm = curproc->p_vmspace->vm_map.pmap; 2329 2330 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2331 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2332 flags |= npv->pv_flags; 2333 /* 2334 * The page is mapped non-cacheable in 2335 * this map. No need to flush the cache. 2336 */ 2337 if (npv->pv_flags & PVF_NC) { 2338 #ifdef DIAGNOSTIC 2339 if (cache_needs_cleaning) 2340 panic("pmap_clean_page: " 2341 "cache inconsistency"); 2342 #endif 2343 break; 2344 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2345 continue; 2346 if (cache_needs_cleaning) { 2347 page_to_clean = 0; 2348 break; 2349 } else { 2350 page_to_clean = npv->pv_va; 2351 pm_to_clean = npv->pv_pmap; 2352 } 2353 cache_needs_cleaning = 1; 2354 } 2355 } 2356 2357 if (page_to_clean) { 2358 if (PV_BEEN_EXECD(flags)) 2359 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2360 PAGE_SIZE); 2361 else 2362 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2363 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2364 } else if (cache_needs_cleaning) { 2365 if (PV_BEEN_EXECD(flags)) 2366 pmap_idcache_wbinv_all(pm); 2367 else 2368 pmap_dcache_wbinv_all(pm); 2369 return (1); 2370 } 2371 return (0); 2372 } 2373 #endif 2374 2375 #ifdef PMAP_CACHE_VIPT 2376 /* 2377 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2378 * right cache alias to make sure we flush the right stuff. 2379 */ 2380 void 2381 pmap_syncicache_page(struct vm_page *pg) 2382 { 2383 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2384 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2385 2386 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2387 pg, pg->mdpage.pvh_attrs)); 2388 /* 2389 * No need to clean the page if it's non-cached. 2390 */ 2391 if (pg->mdpage.pvh_attrs & PVF_NC) 2392 return; 2393 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2394 2395 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2396 /* 2397 * Set up a PTE with the right coloring to flush existing cache lines. 2398 */ 2399 *ptep = L2_S_PROTO | 2400 VM_PAGE_TO_PHYS(pg) 2401 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2402 | pte_l2_s_cache_mode; 2403 PTE_SYNC(ptep); 2404 2405 /* 2406 * Flush it. 2407 */ 2408 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2409 /* 2410 * Unmap the page. 2411 */ 2412 *ptep = 0; 2413 PTE_SYNC(ptep); 2414 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2415 2416 pg->mdpage.pvh_attrs |= PVF_EXEC; 2417 PMAPCOUNT(exec_synced); 2418 } 2419 2420 void 2421 pmap_flush_page(struct vm_page *pg, bool flush) 2422 { 2423 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2424 const size_t pte_offset = va_offset >> PGSHIFT; 2425 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2426 const pt_entry_t oldpte = *ptep; 2427 #if 0 2428 vaddr_t mask; 2429 #endif 2430 2431 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2432 #if 0 2433 mask = pmap_check_sets(pg->phys_addr); 2434 KASSERT(popc4(mask) < 2); 2435 #endif 2436 2437 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2438 pg, pg->mdpage.pvh_attrs)); 2439 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2440 /* 2441 * Set up a PTE with the right coloring to flush existing cache entries. 2442 */ 2443 *ptep = L2_S_PROTO 2444 | VM_PAGE_TO_PHYS(pg) 2445 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2446 | pte_l2_s_cache_mode; 2447 PTE_SYNC(ptep); 2448 2449 /* 2450 * Flush it. 2451 */ 2452 if (flush) 2453 cpu_idcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 2454 else 2455 cpu_dcache_wb_range(cdstp + va_offset, PAGE_SIZE); 2456 2457 /* 2458 * Mark that the page is no longer dirty. 2459 */ 2460 if ((pg->mdpage.pvh_attrs & PVF_MOD) == 0) 2461 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2462 2463 /* 2464 * Restore the page table entry since we might have interrupted 2465 * pmap_zero_page or pmap_copy_page which was already using this pte. 2466 */ 2467 *ptep = oldpte; 2468 PTE_SYNC(ptep); 2469 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2470 #if 0 2471 mask = pmap_check_sets(pg->phys_addr); 2472 KASSERT(mask == 0); 2473 #endif 2474 } 2475 #endif /* PMAP_CACHE_VIPT */ 2476 2477 /* 2478 * Routine: pmap_page_remove 2479 * Function: 2480 * Removes this physical page from 2481 * all physical maps in which it resides. 2482 * Reflects back modify bits to the pager. 2483 */ 2484 static void 2485 pmap_page_remove(struct vm_page *pg) 2486 { 2487 struct l2_bucket *l2b; 2488 struct pv_entry *pv, *npv, **pvp; 2489 pmap_t pm, curpm; 2490 pt_entry_t *ptep, pte; 2491 bool flush; 2492 u_int flags; 2493 2494 NPDEBUG(PDB_FOLLOW, 2495 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2496 VM_PAGE_TO_PHYS(pg))); 2497 2498 PMAP_HEAD_TO_MAP_LOCK(); 2499 simple_lock(&pg->mdpage.pvh_slock); 2500 2501 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2502 if (pv == NULL) { 2503 #ifdef PMAP_CACHE_VIPT 2504 /* 2505 * We *know* the page contents are about to be replaced. 2506 * Discard the exec contents 2507 */ 2508 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2509 PMAPCOUNT(exec_discarded_page_protect); 2510 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2511 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2512 #if 0 /* XYY */ 2513 pmap_flush_page(pg, true); /* wbinv the contents */ 2514 #endif 2515 #endif 2516 simple_unlock(&pg->mdpage.pvh_slock); 2517 PMAP_HEAD_TO_MAP_UNLOCK(); 2518 return; 2519 } 2520 #ifdef PMAP_CACHE_VIPT 2521 KASSERT(pmap_is_page_colored_p(pg)); 2522 #endif 2523 2524 /* 2525 * Clear alias counts 2526 */ 2527 #ifdef PMAP_CACHE_VIVT 2528 pg->mdpage.k_mappings = 0; 2529 #endif 2530 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2531 2532 flush = false; 2533 flags = 0; 2534 curpm = curproc->p_vmspace->vm_map.pmap; 2535 2536 #ifdef PMAP_CACHE_VIVT 2537 pmap_clean_page(pv, false); 2538 #endif 2539 2540 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 2541 while (pv) { 2542 pm = pv->pv_pmap; 2543 npv = SLIST_NEXT(pv, pv_link); 2544 if (flush == false && (pm == curpm || pm == pmap_kernel())) 2545 flush = true; 2546 2547 if (pm == pmap_kernel()) { 2548 #ifdef PMAP_CACHE_VIPT 2549 /* 2550 * If this was unmanaged mapping, it must be preserved. 2551 * Move it back on the list and advance the end-of-list 2552 * pointer. 2553 */ 2554 if (pv->pv_flags & PVF_KENTRY) { 2555 *pvp = pv; 2556 pvp = &SLIST_NEXT(pv, pv_link); 2557 pv = npv; 2558 continue; 2559 } 2560 if (pv->pv_flags & PVF_WRITE) 2561 pg->mdpage.krw_mappings--; 2562 else 2563 pg->mdpage.kro_mappings--; 2564 #endif 2565 PMAPCOUNT(kernel_unmappings); 2566 } 2567 PMAPCOUNT(unmappings); 2568 2569 pmap_acquire_pmap_lock(pm); 2570 2571 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2572 KDASSERT(l2b != NULL); 2573 2574 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2575 pte = *ptep; 2576 2577 /* 2578 * Update statistics 2579 */ 2580 --pm->pm_stats.resident_count; 2581 2582 /* Wired bit */ 2583 if (pv->pv_flags & PVF_WIRED) 2584 --pm->pm_stats.wired_count; 2585 2586 flags |= pv->pv_flags; 2587 2588 /* 2589 * Invalidate the PTEs. 2590 */ 2591 *ptep = 0; 2592 PTE_SYNC_CURRENT(pm, ptep); 2593 pmap_free_l2_bucket(pm, l2b, 1); 2594 2595 pool_put(&pmap_pv_pool, pv); 2596 pv = npv; 2597 /* 2598 * if we reach the end of the list and there are still 2599 * mappings, they might be able to be cached now. 2600 */ 2601 if (pv == NULL) { 2602 *pvp = NULL; 2603 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 2604 pmap_vac_me_harder(pg, pm, 0); 2605 } 2606 pmap_release_pmap_lock(pm); 2607 } 2608 #ifdef PMAP_CACHE_VIPT 2609 /* 2610 * Its EXEC cache is now gone. 2611 */ 2612 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2613 PMAPCOUNT(exec_discarded_page_protect); 2614 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2615 KASSERT(pg->mdpage.urw_mappings == 0); 2616 KASSERT(pg->mdpage.uro_mappings == 0); 2617 #if 0 /* XYY */ 2618 if ((pg->mdpage.pvh_attrs & PMAP_KMPAGE) == 0) { 2619 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 2620 pmap_flush_page(pg, true); /* wbinv the contents */ 2621 } else if ((pg->mdpage.pvh_attrs & PVF_WRITE) 2622 && pg->mdpage.krw_mappings == 0) { 2623 pmap_flush_page(pg, false); /* wb the contents */ 2624 } 2625 } 2626 #endif 2627 if (pg->mdpage.krw_mappings == 0) 2628 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2629 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2630 #endif 2631 simple_unlock(&pg->mdpage.pvh_slock); 2632 PMAP_HEAD_TO_MAP_UNLOCK(); 2633 2634 if (flush) { 2635 /* 2636 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2637 * would need a subsequent call to pmap_update() to ensure 2638 * curpm->pm_cstate.cs_all is reset. Our callers are not 2639 * required to do that (see pmap(9)), so we can't modify 2640 * the current pmap's state. 2641 */ 2642 if (PV_BEEN_EXECD(flags)) 2643 cpu_tlb_flushID(); 2644 else 2645 cpu_tlb_flushD(); 2646 } 2647 cpu_cpwait(); 2648 } 2649 2650 /* 2651 * pmap_t pmap_create(void) 2652 * 2653 * Create a new pmap structure from scratch. 2654 */ 2655 pmap_t 2656 pmap_create(void) 2657 { 2658 pmap_t pm; 2659 2660 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2661 2662 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2663 pm->pm_stats.wired_count = 0; 2664 pm->pm_stats.resident_count = 1; 2665 pm->pm_cstate.cs_all = 0; 2666 pmap_alloc_l1(pm); 2667 2668 /* 2669 * Note: The pool cache ensures that the pm_l2[] array is already 2670 * initialised to zero. 2671 */ 2672 2673 pmap_pinit(pm); 2674 2675 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2676 2677 return (pm); 2678 } 2679 2680 /* 2681 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2682 * int flags) 2683 * 2684 * Insert the given physical page (p) at 2685 * the specified virtual address (v) in the 2686 * target physical map with the protection requested. 2687 * 2688 * NB: This is the only routine which MAY NOT lazy-evaluate 2689 * or lose information. That is, this routine must actually 2690 * insert this page into the given map NOW. 2691 */ 2692 int 2693 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 2694 { 2695 struct l2_bucket *l2b; 2696 struct vm_page *pg, *opg; 2697 struct pv_entry *pve; 2698 pt_entry_t *ptep, npte, opte; 2699 u_int nflags; 2700 u_int oflags; 2701 2702 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2703 2704 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2705 KDASSERT(((va | pa) & PGOFSET) == 0); 2706 2707 /* 2708 * Get a pointer to the page. Later on in this function, we 2709 * test for a managed page by checking pg != NULL. 2710 */ 2711 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2712 2713 nflags = 0; 2714 if (prot & VM_PROT_WRITE) 2715 nflags |= PVF_WRITE; 2716 if (prot & VM_PROT_EXECUTE) 2717 nflags |= PVF_EXEC; 2718 if (flags & PMAP_WIRED) 2719 nflags |= PVF_WIRED; 2720 2721 PMAP_MAP_TO_HEAD_LOCK(); 2722 pmap_acquire_pmap_lock(pm); 2723 2724 /* 2725 * Fetch the L2 bucket which maps this page, allocating one if 2726 * necessary for user pmaps. 2727 */ 2728 if (pm == pmap_kernel()) 2729 l2b = pmap_get_l2_bucket(pm, va); 2730 else 2731 l2b = pmap_alloc_l2_bucket(pm, va); 2732 if (l2b == NULL) { 2733 if (flags & PMAP_CANFAIL) { 2734 pmap_release_pmap_lock(pm); 2735 PMAP_MAP_TO_HEAD_UNLOCK(); 2736 return (ENOMEM); 2737 } 2738 panic("pmap_enter: failed to allocate L2 bucket"); 2739 } 2740 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2741 opte = *ptep; 2742 npte = pa; 2743 oflags = 0; 2744 2745 if (opte) { 2746 /* 2747 * There is already a mapping at this address. 2748 * If the physical address is different, lookup the 2749 * vm_page. 2750 */ 2751 if (l2pte_pa(opte) != pa) 2752 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2753 else 2754 opg = pg; 2755 } else 2756 opg = NULL; 2757 2758 if (pg) { 2759 /* 2760 * This is to be a managed mapping. 2761 */ 2762 if ((flags & VM_PROT_ALL) || 2763 (pg->mdpage.pvh_attrs & PVF_REF)) { 2764 /* 2765 * - The access type indicates that we don't need 2766 * to do referenced emulation. 2767 * OR 2768 * - The physical page has already been referenced 2769 * so no need to re-do referenced emulation here. 2770 */ 2771 npte |= L2_S_PROTO; 2772 2773 nflags |= PVF_REF; 2774 2775 if ((prot & VM_PROT_WRITE) != 0 && 2776 ((flags & VM_PROT_WRITE) != 0 || 2777 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2778 /* 2779 * This is a writable mapping, and the 2780 * page's mod state indicates it has 2781 * already been modified. Make it 2782 * writable from the outset. 2783 */ 2784 npte |= L2_S_PROT_W; 2785 nflags |= PVF_MOD; 2786 } 2787 } else { 2788 /* 2789 * Need to do page referenced emulation. 2790 */ 2791 npte |= L2_TYPE_INV; 2792 } 2793 2794 npte |= pte_l2_s_cache_mode; 2795 2796 if (pg == opg) { 2797 /* 2798 * We're changing the attrs of an existing mapping. 2799 */ 2800 simple_lock(&pg->mdpage.pvh_slock); 2801 oflags = pmap_modify_pv(pg, pm, va, 2802 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2803 PVF_MOD | PVF_REF, nflags); 2804 simple_unlock(&pg->mdpage.pvh_slock); 2805 2806 #ifdef PMAP_CACHE_VIVT 2807 /* 2808 * We may need to flush the cache if we're 2809 * doing rw-ro... 2810 */ 2811 if (pm->pm_cstate.cs_cache_d && 2812 (oflags & PVF_NC) == 0 && 2813 (opte & L2_S_PROT_W) != 0 && 2814 (prot & VM_PROT_WRITE) == 0) 2815 cpu_dcache_wb_range(va, PAGE_SIZE); 2816 #endif 2817 } else { 2818 /* 2819 * New mapping, or changing the backing page 2820 * of an existing mapping. 2821 */ 2822 if (opg) { 2823 /* 2824 * Replacing an existing mapping with a new one. 2825 * It is part of our managed memory so we 2826 * must remove it from the PV list 2827 */ 2828 simple_lock(&opg->mdpage.pvh_slock); 2829 pve = pmap_remove_pv(opg, pm, va, 0); 2830 pmap_vac_me_harder(opg, pm, 0); 2831 simple_unlock(&opg->mdpage.pvh_slock); 2832 oflags = pve->pv_flags; 2833 2834 #ifdef PMAP_CACHE_VIVT 2835 /* 2836 * If the old mapping was valid (ref/mod 2837 * emulation creates 'invalid' mappings 2838 * initially) then make sure to frob 2839 * the cache. 2840 */ 2841 if ((oflags & PVF_NC) == 0 && 2842 l2pte_valid(opte)) { 2843 if (PV_BEEN_EXECD(oflags)) { 2844 pmap_idcache_wbinv_range(pm, va, 2845 PAGE_SIZE); 2846 } else 2847 if (PV_BEEN_REFD(oflags)) { 2848 pmap_dcache_wb_range(pm, va, 2849 PAGE_SIZE, true, 2850 (oflags & PVF_WRITE) == 0); 2851 } 2852 } 2853 #endif 2854 } else 2855 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2856 if ((flags & PMAP_CANFAIL) == 0) 2857 panic("pmap_enter: no pv entries"); 2858 2859 if (pm != pmap_kernel()) 2860 pmap_free_l2_bucket(pm, l2b, 0); 2861 pmap_release_pmap_lock(pm); 2862 PMAP_MAP_TO_HEAD_UNLOCK(); 2863 NPDEBUG(PDB_ENTER, 2864 printf("pmap_enter: ENOMEM\n")); 2865 return (ENOMEM); 2866 } 2867 2868 pmap_enter_pv(pg, pve, pm, va, nflags); 2869 } 2870 } else { 2871 /* 2872 * We're mapping an unmanaged page. 2873 * These are always readable, and possibly writable, from 2874 * the get go as we don't need to track ref/mod status. 2875 */ 2876 npte |= L2_S_PROTO; 2877 if (prot & VM_PROT_WRITE) 2878 npte |= L2_S_PROT_W; 2879 2880 /* 2881 * Make sure the vector table is mapped cacheable 2882 */ 2883 if (pm != pmap_kernel() && va == vector_page) 2884 npte |= pte_l2_s_cache_mode; 2885 2886 if (opg) { 2887 /* 2888 * Looks like there's an existing 'managed' mapping 2889 * at this address. 2890 */ 2891 simple_lock(&opg->mdpage.pvh_slock); 2892 pve = pmap_remove_pv(opg, pm, va, 0); 2893 pmap_vac_me_harder(opg, pm, 0); 2894 simple_unlock(&opg->mdpage.pvh_slock); 2895 oflags = pve->pv_flags; 2896 2897 #ifdef PMAP_CACHE_VIVT 2898 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2899 if (PV_BEEN_EXECD(oflags)) 2900 pmap_idcache_wbinv_range(pm, va, 2901 PAGE_SIZE); 2902 else 2903 if (PV_BEEN_REFD(oflags)) 2904 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2905 true, (oflags & PVF_WRITE) == 0); 2906 } 2907 #endif 2908 pool_put(&pmap_pv_pool, pve); 2909 } 2910 } 2911 2912 /* 2913 * Make sure userland mappings get the right permissions 2914 */ 2915 if (pm != pmap_kernel() && va != vector_page) 2916 npte |= L2_S_PROT_U; 2917 2918 /* 2919 * Keep the stats up to date 2920 */ 2921 if (opte == 0) { 2922 l2b->l2b_occupancy++; 2923 pm->pm_stats.resident_count++; 2924 } 2925 2926 NPDEBUG(PDB_ENTER, 2927 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2928 2929 /* 2930 * If this is just a wiring change, the two PTEs will be 2931 * identical, so there's no need to update the page table. 2932 */ 2933 if (npte != opte) { 2934 bool is_cached = pmap_is_cached(pm); 2935 2936 *ptep = npte; 2937 if (is_cached) { 2938 /* 2939 * We only need to frob the cache/tlb if this pmap 2940 * is current 2941 */ 2942 PTE_SYNC(ptep); 2943 if (va != vector_page && l2pte_valid(npte)) { 2944 /* 2945 * This mapping is likely to be accessed as 2946 * soon as we return to userland. Fix up the 2947 * L1 entry to avoid taking another 2948 * page/domain fault. 2949 */ 2950 pd_entry_t *pl1pd, l1pd; 2951 2952 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2953 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2954 L1_C_PROTO; 2955 if (*pl1pd != l1pd) { 2956 *pl1pd = l1pd; 2957 PTE_SYNC(pl1pd); 2958 } 2959 } 2960 } 2961 2962 if (PV_BEEN_EXECD(oflags)) 2963 pmap_tlb_flushID_SE(pm, va); 2964 else 2965 if (PV_BEEN_REFD(oflags)) 2966 pmap_tlb_flushD_SE(pm, va); 2967 2968 NPDEBUG(PDB_ENTER, 2969 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2970 is_cached, pm->pm_cstate.cs_all)); 2971 2972 if (pg != NULL) { 2973 simple_lock(&pg->mdpage.pvh_slock); 2974 pmap_vac_me_harder(pg, pm, va); 2975 simple_unlock(&pg->mdpage.pvh_slock); 2976 } 2977 } 2978 #ifdef PMAP_CACHE_VIPT 2979 KASSERT((pg->mdpage.pvh_attrs & PVF_MOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2980 KASSERT(((pg->mdpage.pvh_attrs & PVF_WRITE) == 0) == (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0)); 2981 #endif 2982 2983 pmap_release_pmap_lock(pm); 2984 PMAP_MAP_TO_HEAD_UNLOCK(); 2985 2986 return (0); 2987 } 2988 2989 /* 2990 * pmap_remove() 2991 * 2992 * pmap_remove is responsible for nuking a number of mappings for a range 2993 * of virtual address space in the current pmap. To do this efficiently 2994 * is interesting, because in a number of cases a wide virtual address 2995 * range may be supplied that contains few actual mappings. So, the 2996 * optimisations are: 2997 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 2998 * 2. Build up a list of pages we've hit, up to a maximum, so we can 2999 * maybe do just a partial cache clean. This path of execution is 3000 * complicated by the fact that the cache must be flushed _before_ 3001 * the PTE is nuked, being a VAC :-) 3002 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3003 * all invalidations until pmap_update(), since pmap_remove_all() has 3004 * already flushed the cache. 3005 * 4. Maybe later fast-case a single page, but I don't think this is 3006 * going to make _that_ much difference overall. 3007 */ 3008 3009 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3010 3011 void 3012 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 3013 { 3014 struct l2_bucket *l2b; 3015 vaddr_t next_bucket; 3016 pt_entry_t *ptep; 3017 u_int cleanlist_idx, total, cnt; 3018 struct { 3019 vaddr_t va; 3020 pt_entry_t *ptep; 3021 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3022 u_int mappings, is_exec, is_refd; 3023 3024 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3025 "eva=%08lx\n", pm, sva, eva)); 3026 3027 /* 3028 * we lock in the pmap => pv_head direction 3029 */ 3030 PMAP_MAP_TO_HEAD_LOCK(); 3031 pmap_acquire_pmap_lock(pm); 3032 3033 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3034 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3035 if (pm->pm_cstate.cs_tlb == 0) 3036 pm->pm_remove_all = true; 3037 } else 3038 cleanlist_idx = 0; 3039 3040 total = 0; 3041 3042 while (sva < eva) { 3043 /* 3044 * Do one L2 bucket's worth at a time. 3045 */ 3046 next_bucket = L2_NEXT_BUCKET(sva); 3047 if (next_bucket > eva) 3048 next_bucket = eva; 3049 3050 l2b = pmap_get_l2_bucket(pm, sva); 3051 if (l2b == NULL) { 3052 sva = next_bucket; 3053 continue; 3054 } 3055 3056 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3057 3058 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3059 struct vm_page *pg; 3060 pt_entry_t pte; 3061 paddr_t pa; 3062 3063 pte = *ptep; 3064 3065 if (pte == 0) { 3066 /* Nothing here, move along */ 3067 continue; 3068 } 3069 3070 pa = l2pte_pa(pte); 3071 is_exec = 0; 3072 is_refd = 1; 3073 3074 /* 3075 * Update flags. In a number of circumstances, 3076 * we could cluster a lot of these and do a 3077 * number of sequential pages in one go. 3078 */ 3079 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3080 struct pv_entry *pve; 3081 simple_lock(&pg->mdpage.pvh_slock); 3082 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 3083 pmap_vac_me_harder(pg, pm, 0); 3084 simple_unlock(&pg->mdpage.pvh_slock); 3085 if (pve != NULL) { 3086 if (pm->pm_remove_all == false) { 3087 is_exec = 3088 PV_BEEN_EXECD(pve->pv_flags); 3089 is_refd = 3090 PV_BEEN_REFD(pve->pv_flags); 3091 } 3092 pool_put(&pmap_pv_pool, pve); 3093 } else 3094 if (skip_wired) { 3095 /* The mapping is wired. Skip it */ 3096 continue; 3097 } 3098 } else 3099 if (skip_wired) { 3100 /* Unmanaged pages are always wired. */ 3101 continue; 3102 } 3103 3104 mappings++; 3105 3106 if (!l2pte_valid(pte)) { 3107 /* 3108 * Ref/Mod emulation is still active for this 3109 * mapping, therefore it is has not yet been 3110 * accessed. No need to frob the cache/tlb. 3111 */ 3112 *ptep = 0; 3113 PTE_SYNC_CURRENT(pm, ptep); 3114 continue; 3115 } 3116 3117 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3118 /* Add to the clean list. */ 3119 cleanlist[cleanlist_idx].ptep = ptep; 3120 cleanlist[cleanlist_idx].va = 3121 sva | (is_exec & 1); 3122 cleanlist_idx++; 3123 } else 3124 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3125 /* Nuke everything if needed. */ 3126 #ifdef PMAP_CACHE_VIVT 3127 pmap_idcache_wbinv_all(pm); 3128 #endif 3129 pmap_tlb_flushID(pm); 3130 3131 /* 3132 * Roll back the previous PTE list, 3133 * and zero out the current PTE. 3134 */ 3135 for (cnt = 0; 3136 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3137 *cleanlist[cnt].ptep = 0; 3138 PTE_SYNC(cleanlist[cnt].ptep); 3139 } 3140 *ptep = 0; 3141 PTE_SYNC(ptep); 3142 cleanlist_idx++; 3143 pm->pm_remove_all = true; 3144 } else { 3145 *ptep = 0; 3146 PTE_SYNC(ptep); 3147 if (pm->pm_remove_all == false) { 3148 if (is_exec) 3149 pmap_tlb_flushID_SE(pm, sva); 3150 else 3151 if (is_refd) 3152 pmap_tlb_flushD_SE(pm, sva); 3153 } 3154 } 3155 } 3156 3157 /* 3158 * Deal with any left overs 3159 */ 3160 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3161 total += cleanlist_idx; 3162 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3163 if (pm->pm_cstate.cs_all != 0) { 3164 vaddr_t clva = cleanlist[cnt].va & ~1; 3165 if (cleanlist[cnt].va & 1) { 3166 #ifdef PMAP_CACHE_VIVT 3167 pmap_idcache_wbinv_range(pm, 3168 clva, PAGE_SIZE); 3169 #endif 3170 pmap_tlb_flushID_SE(pm, clva); 3171 } else { 3172 #ifdef PMAP_CACHE_VIVT 3173 pmap_dcache_wb_range(pm, 3174 clva, PAGE_SIZE, true, 3175 false); 3176 #endif 3177 pmap_tlb_flushD_SE(pm, clva); 3178 } 3179 } 3180 *cleanlist[cnt].ptep = 0; 3181 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3182 } 3183 3184 /* 3185 * If it looks like we're removing a whole bunch 3186 * of mappings, it's faster to just write-back 3187 * the whole cache now and defer TLB flushes until 3188 * pmap_update() is called. 3189 */ 3190 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3191 cleanlist_idx = 0; 3192 else { 3193 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3194 #ifdef PMAP_CACHE_VIVT 3195 pmap_idcache_wbinv_all(pm); 3196 #endif 3197 pm->pm_remove_all = true; 3198 } 3199 } 3200 3201 pmap_free_l2_bucket(pm, l2b, mappings); 3202 pm->pm_stats.resident_count -= mappings; 3203 } 3204 3205 pmap_release_pmap_lock(pm); 3206 PMAP_MAP_TO_HEAD_UNLOCK(); 3207 } 3208 3209 #ifdef PMAP_CACHE_VIPT 3210 static struct pv_entry * 3211 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3212 { 3213 struct pv_entry *pv; 3214 3215 simple_lock(&pg->mdpage.pvh_slock); 3216 KASSERT(pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 3217 KASSERT((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3218 3219 pv = pmap_remove_pv(pg, pmap_kernel(), va, false); 3220 KASSERT(pv); 3221 KASSERT(pv->pv_flags & PVF_KENTRY); 3222 3223 /* 3224 * If we are removing a writeable mapping to a cached exec page, 3225 * if it's the last mapping then clear it execness other sync 3226 * the page to the icache. 3227 */ 3228 if ((pg->mdpage.pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3229 && (pv->pv_flags & PVF_WRITE) != 0) { 3230 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 3231 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 3232 PMAPCOUNT(exec_discarded_kremove); 3233 } else { 3234 pmap_syncicache_page(pg); 3235 PMAPCOUNT(exec_synced_kremove); 3236 } 3237 } 3238 pmap_vac_me_harder(pg, pmap_kernel(), 0); 3239 simple_unlock(&pg->mdpage.pvh_slock); 3240 3241 return pv; 3242 } 3243 #endif /* PMAP_CACHE_VIPT */ 3244 3245 /* 3246 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3247 * 3248 * We assume there is already sufficient KVM space available 3249 * to do this, as we can't allocate L2 descriptor tables/metadata 3250 * from here. 3251 */ 3252 void 3253 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 3254 { 3255 struct l2_bucket *l2b; 3256 pt_entry_t *ptep, opte; 3257 #ifdef PMAP_CACHE_VIPT 3258 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3259 struct vm_page *opg; 3260 struct pv_entry *pv = NULL; 3261 #endif 3262 3263 NPDEBUG(PDB_KENTER, 3264 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3265 va, pa, prot)); 3266 3267 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3268 KDASSERT(l2b != NULL); 3269 3270 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3271 opte = *ptep; 3272 3273 if (opte == 0) { 3274 PMAPCOUNT(kenter_mappings); 3275 l2b->l2b_occupancy++; 3276 } else { 3277 PMAPCOUNT(kenter_remappings); 3278 #ifdef PMAP_CACHE_VIPT 3279 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3280 if (opg) { 3281 KASSERT(opg != pg); 3282 KASSERT((opg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3283 KASSERT((prot & PMAP_KMPAGE) == 0); 3284 simple_lock(&opg->mdpage.pvh_slock); 3285 pv = pmap_kremove_pg(opg, va); 3286 simple_unlock(&opg->mdpage.pvh_slock); 3287 } 3288 #endif 3289 if (l2pte_valid(opte)) { 3290 #ifdef PMAP_CACHE_VIVT 3291 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3292 #endif 3293 cpu_tlb_flushD_SE(va); 3294 cpu_cpwait(); 3295 } 3296 } 3297 3298 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3299 pte_l2_s_cache_mode; 3300 PTE_SYNC(ptep); 3301 3302 #ifdef PMAP_CACHE_VIPT 3303 if (pg) { 3304 if (prot & PMAP_KMPAGE) { 3305 KASSERT(pv == NULL); 3306 KASSERT((va & PVF_COLORED) == 0); 3307 simple_lock(&pg->mdpage.pvh_slock); 3308 KASSERT(pg->mdpage.urw_mappings == 0); 3309 KASSERT(pg->mdpage.uro_mappings == 0); 3310 KASSERT(pg->mdpage.krw_mappings == 0); 3311 KASSERT(pg->mdpage.kro_mappings == 0); 3312 KASSERT((pg->mdpage.pvh_attrs & PVF_NC) == 0); 3313 /* if there is a color conflict, evict from cache. */ 3314 if (pmap_is_page_colored_p(pg) 3315 && ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask)) { 3316 PMAPCOUNT(vac_color_change); 3317 pmap_flush_page(pg, true); 3318 } 3319 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 3320 pg->mdpage.pvh_attrs |= PVF_KMPAGE 3321 | PVF_COLORED | PVF_DIRTY 3322 | (va & arm_cache_prefer_mask); 3323 simple_unlock(&pg->mdpage.pvh_slock); 3324 } else { 3325 if (pv == NULL) { 3326 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3327 KASSERT(pv != NULL); 3328 } 3329 pmap_enter_pv(pg, pv, pmap_kernel(), va, 3330 PVF_WIRED | PVF_KENTRY 3331 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3332 if ((prot & VM_PROT_WRITE) 3333 && !(pg->mdpage.pvh_attrs & PVF_NC)) 3334 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3335 KASSERT((prot & VM_PROT_WRITE) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3336 simple_lock(&pg->mdpage.pvh_slock); 3337 pmap_vac_me_harder(pg, pmap_kernel(), va); 3338 simple_unlock(&pg->mdpage.pvh_slock); 3339 } 3340 } else { 3341 if (pv != NULL) 3342 pool_put(&pmap_pv_pool, pv); 3343 } 3344 #endif 3345 } 3346 3347 void 3348 pmap_kremove(vaddr_t va, vsize_t len) 3349 { 3350 struct l2_bucket *l2b; 3351 pt_entry_t *ptep, *sptep, opte; 3352 vaddr_t next_bucket, eva; 3353 u_int mappings; 3354 #ifdef PMAP_CACHE_VIPT 3355 struct vm_page *opg; 3356 #endif 3357 3358 PMAPCOUNT(kenter_unmappings); 3359 3360 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3361 va, len)); 3362 3363 eva = va + len; 3364 3365 while (va < eva) { 3366 next_bucket = L2_NEXT_BUCKET(va); 3367 if (next_bucket > eva) 3368 next_bucket = eva; 3369 3370 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3371 KDASSERT(l2b != NULL); 3372 3373 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3374 mappings = 0; 3375 3376 while (va < next_bucket) { 3377 opte = *ptep; 3378 #ifdef PMAP_CACHE_VIPT 3379 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3380 if (opg) { 3381 if (opg->mdpage.pvh_attrs & PVF_KMPAGE) { 3382 simple_lock(&opg->mdpage.pvh_slock); 3383 KASSERT(opg->mdpage.urw_mappings == 0); 3384 KASSERT(opg->mdpage.uro_mappings == 0); 3385 KASSERT(opg->mdpage.krw_mappings == 0); 3386 KASSERT(opg->mdpage.kro_mappings == 0); 3387 opg->mdpage.pvh_attrs &= 3388 ~(PVF_KMPAGE|PVF_WRITE); 3389 simple_unlock(&opg->mdpage.pvh_slock); 3390 } else { 3391 pool_put(&pmap_pv_pool, 3392 pmap_kremove_pg(opg, va)); 3393 } 3394 } 3395 #endif 3396 if (l2pte_valid(opte)) { 3397 #ifdef PMAP_CACHE_VIVT 3398 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3399 #endif 3400 cpu_tlb_flushD_SE(va); 3401 } 3402 if (opte) { 3403 *ptep = 0; 3404 mappings++; 3405 } 3406 va += PAGE_SIZE; 3407 ptep++; 3408 } 3409 KDASSERT(mappings <= l2b->l2b_occupancy); 3410 l2b->l2b_occupancy -= mappings; 3411 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3412 } 3413 cpu_cpwait(); 3414 } 3415 3416 bool 3417 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3418 { 3419 struct l2_dtable *l2; 3420 pd_entry_t *pl1pd, l1pd; 3421 pt_entry_t *ptep, pte; 3422 paddr_t pa; 3423 u_int l1idx; 3424 3425 pmap_acquire_pmap_lock(pm); 3426 3427 l1idx = L1_IDX(va); 3428 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3429 l1pd = *pl1pd; 3430 3431 if (l1pte_section_p(l1pd)) { 3432 /* 3433 * These should only happen for pmap_kernel() 3434 */ 3435 KDASSERT(pm == pmap_kernel()); 3436 pmap_release_pmap_lock(pm); 3437 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3438 } else { 3439 /* 3440 * Note that we can't rely on the validity of the L1 3441 * descriptor as an indication that a mapping exists. 3442 * We have to look it up in the L2 dtable. 3443 */ 3444 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3445 3446 if (l2 == NULL || 3447 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3448 pmap_release_pmap_lock(pm); 3449 return false; 3450 } 3451 3452 ptep = &ptep[l2pte_index(va)]; 3453 pte = *ptep; 3454 pmap_release_pmap_lock(pm); 3455 3456 if (pte == 0) 3457 return false; 3458 3459 switch (pte & L2_TYPE_MASK) { 3460 case L2_TYPE_L: 3461 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3462 break; 3463 3464 default: 3465 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3466 break; 3467 } 3468 } 3469 3470 if (pap != NULL) 3471 *pap = pa; 3472 3473 return true; 3474 } 3475 3476 void 3477 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3478 { 3479 struct l2_bucket *l2b; 3480 pt_entry_t *ptep, pte; 3481 vaddr_t next_bucket; 3482 u_int flags; 3483 u_int clr_mask; 3484 int flush; 3485 3486 NPDEBUG(PDB_PROTECT, 3487 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3488 pm, sva, eva, prot)); 3489 3490 if ((prot & VM_PROT_READ) == 0) { 3491 pmap_remove(pm, sva, eva); 3492 return; 3493 } 3494 3495 if (prot & VM_PROT_WRITE) { 3496 /* 3497 * If this is a read->write transition, just ignore it and let 3498 * uvm_fault() take care of it later. 3499 */ 3500 return; 3501 } 3502 3503 PMAP_MAP_TO_HEAD_LOCK(); 3504 pmap_acquire_pmap_lock(pm); 3505 3506 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3507 flags = 0; 3508 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3509 3510 while (sva < eva) { 3511 next_bucket = L2_NEXT_BUCKET(sva); 3512 if (next_bucket > eva) 3513 next_bucket = eva; 3514 3515 l2b = pmap_get_l2_bucket(pm, sva); 3516 if (l2b == NULL) { 3517 sva = next_bucket; 3518 continue; 3519 } 3520 3521 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3522 3523 while (sva < next_bucket) { 3524 pte = *ptep; 3525 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3526 struct vm_page *pg; 3527 u_int f; 3528 3529 #ifdef PMAP_CACHE_VIVT 3530 /* 3531 * OK, at this point, we know we're doing 3532 * write-protect operation. If the pmap is 3533 * active, write-back the page. 3534 */ 3535 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3536 false, false); 3537 #endif 3538 3539 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3540 pte &= ~L2_S_PROT_W; 3541 *ptep = pte; 3542 PTE_SYNC(ptep); 3543 3544 if (pg != NULL) { 3545 simple_lock(&pg->mdpage.pvh_slock); 3546 f = pmap_modify_pv(pg, pm, sva, 3547 clr_mask, 0); 3548 pmap_vac_me_harder(pg, pm, sva); 3549 simple_unlock(&pg->mdpage.pvh_slock); 3550 } else 3551 f = PVF_REF | PVF_EXEC; 3552 3553 if (flush >= 0) { 3554 flush++; 3555 flags |= f; 3556 } else 3557 if (PV_BEEN_EXECD(f)) 3558 pmap_tlb_flushID_SE(pm, sva); 3559 else 3560 if (PV_BEEN_REFD(f)) 3561 pmap_tlb_flushD_SE(pm, sva); 3562 } 3563 3564 sva += PAGE_SIZE; 3565 ptep++; 3566 } 3567 } 3568 3569 pmap_release_pmap_lock(pm); 3570 PMAP_MAP_TO_HEAD_UNLOCK(); 3571 3572 if (flush) { 3573 if (PV_BEEN_EXECD(flags)) 3574 pmap_tlb_flushID(pm); 3575 else 3576 if (PV_BEEN_REFD(flags)) 3577 pmap_tlb_flushD(pm); 3578 } 3579 } 3580 3581 void 3582 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3583 { 3584 struct l2_bucket *l2b; 3585 pt_entry_t *ptep; 3586 vaddr_t next_bucket; 3587 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3588 3589 NPDEBUG(PDB_EXEC, 3590 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3591 pm, sva, eva)); 3592 3593 PMAP_MAP_TO_HEAD_LOCK(); 3594 pmap_acquire_pmap_lock(pm); 3595 3596 while (sva < eva) { 3597 next_bucket = L2_NEXT_BUCKET(sva); 3598 if (next_bucket > eva) 3599 next_bucket = eva; 3600 3601 l2b = pmap_get_l2_bucket(pm, sva); 3602 if (l2b == NULL) { 3603 sva = next_bucket; 3604 continue; 3605 } 3606 3607 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3608 sva < next_bucket; 3609 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3610 if (l2pte_valid(*ptep)) { 3611 cpu_icache_sync_range(sva, 3612 min(page_size, eva - sva)); 3613 } 3614 } 3615 } 3616 3617 pmap_release_pmap_lock(pm); 3618 PMAP_MAP_TO_HEAD_UNLOCK(); 3619 } 3620 3621 void 3622 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3623 { 3624 3625 NPDEBUG(PDB_PROTECT, 3626 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3627 pg, VM_PAGE_TO_PHYS(pg), prot)); 3628 3629 switch(prot) { 3630 return; 3631 case VM_PROT_READ|VM_PROT_WRITE: 3632 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3633 pmap_clearbit(pg, PVF_EXEC); 3634 break; 3635 #endif 3636 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3637 break; 3638 3639 case VM_PROT_READ: 3640 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3641 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3642 break; 3643 #endif 3644 case VM_PROT_READ|VM_PROT_EXECUTE: 3645 pmap_clearbit(pg, PVF_WRITE); 3646 break; 3647 3648 default: 3649 pmap_page_remove(pg); 3650 break; 3651 } 3652 } 3653 3654 /* 3655 * pmap_clear_modify: 3656 * 3657 * Clear the "modified" attribute for a page. 3658 */ 3659 bool 3660 pmap_clear_modify(struct vm_page *pg) 3661 { 3662 bool rv; 3663 3664 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3665 rv = true; 3666 pmap_clearbit(pg, PVF_MOD); 3667 } else 3668 rv = false; 3669 3670 return (rv); 3671 } 3672 3673 /* 3674 * pmap_clear_reference: 3675 * 3676 * Clear the "referenced" attribute for a page. 3677 */ 3678 bool 3679 pmap_clear_reference(struct vm_page *pg) 3680 { 3681 bool rv; 3682 3683 if (pg->mdpage.pvh_attrs & PVF_REF) { 3684 rv = true; 3685 pmap_clearbit(pg, PVF_REF); 3686 } else 3687 rv = false; 3688 3689 return (rv); 3690 } 3691 3692 /* 3693 * pmap_is_modified: 3694 * 3695 * Test if a page has the "modified" attribute. 3696 */ 3697 /* See <arm/arm32/pmap.h> */ 3698 3699 /* 3700 * pmap_is_referenced: 3701 * 3702 * Test if a page has the "referenced" attribute. 3703 */ 3704 /* See <arm/arm32/pmap.h> */ 3705 3706 int 3707 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3708 { 3709 struct l2_dtable *l2; 3710 struct l2_bucket *l2b; 3711 pd_entry_t *pl1pd, l1pd; 3712 pt_entry_t *ptep, pte; 3713 paddr_t pa; 3714 u_int l1idx; 3715 int rv = 0; 3716 3717 PMAP_MAP_TO_HEAD_LOCK(); 3718 pmap_acquire_pmap_lock(pm); 3719 3720 l1idx = L1_IDX(va); 3721 3722 /* 3723 * If there is no l2_dtable for this address, then the process 3724 * has no business accessing it. 3725 * 3726 * Note: This will catch userland processes trying to access 3727 * kernel addresses. 3728 */ 3729 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3730 if (l2 == NULL) 3731 goto out; 3732 3733 /* 3734 * Likewise if there is no L2 descriptor table 3735 */ 3736 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3737 if (l2b->l2b_kva == NULL) 3738 goto out; 3739 3740 /* 3741 * Check the PTE itself. 3742 */ 3743 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3744 pte = *ptep; 3745 if (pte == 0) 3746 goto out; 3747 3748 /* 3749 * Catch a userland access to the vector page mapped at 0x0 3750 */ 3751 if (user && (pte & L2_S_PROT_U) == 0) 3752 goto out; 3753 3754 pa = l2pte_pa(pte); 3755 3756 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3757 /* 3758 * This looks like a good candidate for "page modified" 3759 * emulation... 3760 */ 3761 struct pv_entry *pv; 3762 struct vm_page *pg; 3763 3764 /* Extract the physical address of the page */ 3765 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3766 goto out; 3767 3768 /* Get the current flags for this page. */ 3769 simple_lock(&pg->mdpage.pvh_slock); 3770 3771 pv = pmap_find_pv(pg, pm, va); 3772 if (pv == NULL) { 3773 simple_unlock(&pg->mdpage.pvh_slock); 3774 goto out; 3775 } 3776 3777 /* 3778 * Do the flags say this page is writable? If not then it 3779 * is a genuine write fault. If yes then the write fault is 3780 * our fault as we did not reflect the write access in the 3781 * PTE. Now we know a write has occurred we can correct this 3782 * and also set the modified bit 3783 */ 3784 if ((pv->pv_flags & PVF_WRITE) == 0) { 3785 simple_unlock(&pg->mdpage.pvh_slock); 3786 goto out; 3787 } 3788 3789 NPDEBUG(PDB_FOLLOW, 3790 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3791 pm, va, VM_PAGE_TO_PHYS(pg))); 3792 3793 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD | PVF_DIRTY; 3794 pv->pv_flags |= PVF_REF | PVF_MOD; 3795 simple_unlock(&pg->mdpage.pvh_slock); 3796 3797 /* 3798 * Re-enable write permissions for the page. No need to call 3799 * pmap_vac_me_harder(), since this is just a 3800 * modified-emulation fault, and the PVF_WRITE bit isn't 3801 * changing. We've already set the cacheable bits based on 3802 * the assumption that we can write to this page. 3803 */ 3804 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3805 PTE_SYNC(ptep); 3806 rv = 1; 3807 } else 3808 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3809 /* 3810 * This looks like a good candidate for "page referenced" 3811 * emulation. 3812 */ 3813 struct pv_entry *pv; 3814 struct vm_page *pg; 3815 3816 /* Extract the physical address of the page */ 3817 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3818 goto out; 3819 3820 /* Get the current flags for this page. */ 3821 simple_lock(&pg->mdpage.pvh_slock); 3822 3823 pv = pmap_find_pv(pg, pm, va); 3824 if (pv == NULL) { 3825 simple_unlock(&pg->mdpage.pvh_slock); 3826 goto out; 3827 } 3828 3829 pg->mdpage.pvh_attrs |= PVF_REF; 3830 pv->pv_flags |= PVF_REF; 3831 simple_unlock(&pg->mdpage.pvh_slock); 3832 3833 NPDEBUG(PDB_FOLLOW, 3834 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3835 pm, va, VM_PAGE_TO_PHYS(pg))); 3836 3837 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3838 PTE_SYNC(ptep); 3839 rv = 1; 3840 } 3841 3842 /* 3843 * We know there is a valid mapping here, so simply 3844 * fix up the L1 if necessary. 3845 */ 3846 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3847 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3848 if (*pl1pd != l1pd) { 3849 *pl1pd = l1pd; 3850 PTE_SYNC(pl1pd); 3851 rv = 1; 3852 } 3853 3854 #ifdef CPU_SA110 3855 /* 3856 * There are bugs in the rev K SA110. This is a check for one 3857 * of them. 3858 */ 3859 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3860 curcpu()->ci_arm_cpurev < 3) { 3861 /* Always current pmap */ 3862 if (l2pte_valid(pte)) { 3863 extern int kernel_debug; 3864 if (kernel_debug & 1) { 3865 struct proc *p = curlwp->l_proc; 3866 printf("prefetch_abort: page is already " 3867 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3868 printf("prefetch_abort: pc=%08lx proc=%p " 3869 "process=%s\n", va, p, p->p_comm); 3870 printf("prefetch_abort: far=%08x fs=%x\n", 3871 cpu_faultaddress(), cpu_faultstatus()); 3872 } 3873 #ifdef DDB 3874 if (kernel_debug & 2) 3875 Debugger(); 3876 #endif 3877 rv = 1; 3878 } 3879 } 3880 #endif /* CPU_SA110 */ 3881 3882 #ifdef DEBUG 3883 /* 3884 * If 'rv == 0' at this point, it generally indicates that there is a 3885 * stale TLB entry for the faulting address. This happens when two or 3886 * more processes are sharing an L1. Since we don't flush the TLB on 3887 * a context switch between such processes, we can take domain faults 3888 * for mappings which exist at the same VA in both processes. EVEN IF 3889 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3890 * example. 3891 * 3892 * This is extremely likely to happen if pmap_enter() updated the L1 3893 * entry for a recently entered mapping. In this case, the TLB is 3894 * flushed for the new mapping, but there may still be TLB entries for 3895 * other mappings belonging to other processes in the 1MB range 3896 * covered by the L1 entry. 3897 * 3898 * Since 'rv == 0', we know that the L1 already contains the correct 3899 * value, so the fault must be due to a stale TLB entry. 3900 * 3901 * Since we always need to flush the TLB anyway in the case where we 3902 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 3903 * stale TLB entries dynamically. 3904 * 3905 * However, the above condition can ONLY happen if the current L1 is 3906 * being shared. If it happens when the L1 is unshared, it indicates 3907 * that other parts of the pmap are not doing their job WRT managing 3908 * the TLB. 3909 */ 3910 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 3911 extern int last_fault_code; 3912 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 3913 pm, va, ftype); 3914 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 3915 l2, l2b, ptep, pl1pd); 3916 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 3917 pte, l1pd, last_fault_code); 3918 #ifdef DDB 3919 Debugger(); 3920 #endif 3921 } 3922 #endif 3923 3924 cpu_tlb_flushID_SE(va); 3925 cpu_cpwait(); 3926 3927 rv = 1; 3928 3929 out: 3930 pmap_release_pmap_lock(pm); 3931 PMAP_MAP_TO_HEAD_UNLOCK(); 3932 3933 return (rv); 3934 } 3935 3936 /* 3937 * pmap_collect: free resources held by a pmap 3938 * 3939 * => optional function. 3940 * => called when a process is swapped out to free memory. 3941 */ 3942 void 3943 pmap_collect(pmap_t pm) 3944 { 3945 3946 #ifdef PMAP_CACHE_VIVT 3947 pmap_idcache_wbinv_all(pm); 3948 #endif 3949 pm->pm_remove_all = true; 3950 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 3951 pmap_update(pm); 3952 PMAPCOUNT(collects); 3953 } 3954 3955 /* 3956 * Routine: pmap_procwr 3957 * 3958 * Function: 3959 * Synchronize caches corresponding to [addr, addr+len) in p. 3960 * 3961 */ 3962 void 3963 pmap_procwr(struct proc *p, vaddr_t va, int len) 3964 { 3965 /* We only need to do anything if it is the current process. */ 3966 if (p == curproc) 3967 cpu_icache_sync_range(va, len); 3968 } 3969 3970 /* 3971 * Routine: pmap_unwire 3972 * Function: Clear the wired attribute for a map/virtual-address pair. 3973 * 3974 * In/out conditions: 3975 * The mapping must already exist in the pmap. 3976 */ 3977 void 3978 pmap_unwire(pmap_t pm, vaddr_t va) 3979 { 3980 struct l2_bucket *l2b; 3981 pt_entry_t *ptep, pte; 3982 struct vm_page *pg; 3983 paddr_t pa; 3984 3985 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 3986 3987 PMAP_MAP_TO_HEAD_LOCK(); 3988 pmap_acquire_pmap_lock(pm); 3989 3990 l2b = pmap_get_l2_bucket(pm, va); 3991 KDASSERT(l2b != NULL); 3992 3993 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3994 pte = *ptep; 3995 3996 /* Extract the physical address of the page */ 3997 pa = l2pte_pa(pte); 3998 3999 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4000 /* Update the wired bit in the pv entry for this page. */ 4001 simple_lock(&pg->mdpage.pvh_slock); 4002 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 4003 simple_unlock(&pg->mdpage.pvh_slock); 4004 } 4005 4006 pmap_release_pmap_lock(pm); 4007 PMAP_MAP_TO_HEAD_UNLOCK(); 4008 } 4009 4010 void 4011 pmap_activate(struct lwp *l) 4012 { 4013 extern int block_userspace_access; 4014 pmap_t opm, npm, rpm; 4015 uint32_t odacr, ndacr; 4016 int oldirqstate; 4017 4018 /* 4019 * If activating a non-current lwp or the current lwp is 4020 * already active, just return. 4021 */ 4022 if (l != curlwp || 4023 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4024 return; 4025 4026 npm = l->l_proc->p_vmspace->vm_map.pmap; 4027 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4028 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4029 4030 /* 4031 * If TTB and DACR are unchanged, short-circuit all the 4032 * TLB/cache management stuff. 4033 */ 4034 if (pmap_previous_active_lwp != NULL) { 4035 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4036 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4037 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4038 4039 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4040 goto all_done; 4041 } else 4042 opm = NULL; 4043 4044 PMAPCOUNT(activations); 4045 block_userspace_access = 1; 4046 4047 /* 4048 * If switching to a user vmspace which is different to the 4049 * most recent one, and the most recent one is potentially 4050 * live in the cache, we must write-back and invalidate the 4051 * entire cache. 4052 */ 4053 rpm = pmap_recent_user; 4054 if (npm != pmap_kernel() && rpm && npm != rpm && 4055 rpm->pm_cstate.cs_cache) { 4056 rpm->pm_cstate.cs_cache = 0; 4057 #ifdef PMAP_CACHE_VIVT 4058 cpu_idcache_wbinv_all(); 4059 #endif 4060 } 4061 4062 /* No interrupts while we frob the TTB/DACR */ 4063 oldirqstate = disable_interrupts(IF32_bits); 4064 4065 /* 4066 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4067 * entry corresponding to 'vector_page' in the incoming L1 table 4068 * before switching to it otherwise subsequent interrupts/exceptions 4069 * (including domain faults!) will jump into hyperspace. 4070 */ 4071 if (npm->pm_pl1vec != NULL) { 4072 cpu_tlb_flushID_SE((u_int)vector_page); 4073 cpu_cpwait(); 4074 *npm->pm_pl1vec = npm->pm_l1vec; 4075 PTE_SYNC(npm->pm_pl1vec); 4076 } 4077 4078 cpu_domains(ndacr); 4079 4080 if (npm == pmap_kernel() || npm == rpm) { 4081 /* 4082 * Switching to a kernel thread, or back to the 4083 * same user vmspace as before... Simply update 4084 * the TTB (no TLB flush required) 4085 */ 4086 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4087 "r"(npm->pm_l1->l1_physaddr)); 4088 cpu_cpwait(); 4089 } else { 4090 /* 4091 * Otherwise, update TTB and flush TLB 4092 */ 4093 cpu_context_switch(npm->pm_l1->l1_physaddr); 4094 if (rpm != NULL) 4095 rpm->pm_cstate.cs_tlb = 0; 4096 } 4097 4098 restore_interrupts(oldirqstate); 4099 4100 block_userspace_access = 0; 4101 4102 all_done: 4103 /* 4104 * The new pmap is resident. Make sure it's marked 4105 * as resident in the cache/TLB. 4106 */ 4107 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4108 if (npm != pmap_kernel()) 4109 pmap_recent_user = npm; 4110 4111 /* The old pmap is not longer active */ 4112 if (opm != NULL) 4113 opm->pm_activated = false; 4114 4115 /* But the new one is */ 4116 npm->pm_activated = true; 4117 } 4118 4119 void 4120 pmap_deactivate(struct lwp *l) 4121 { 4122 4123 /* 4124 * If the process is exiting, make sure pmap_activate() does 4125 * a full MMU context-switch and cache flush, which we might 4126 * otherwise skip. See PR port-arm/38950. 4127 */ 4128 if (l->l_proc->p_sflag & PS_WEXIT) 4129 pmap_previous_active_lwp = NULL; 4130 4131 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4132 } 4133 4134 void 4135 pmap_update(pmap_t pm) 4136 { 4137 4138 if (pm->pm_remove_all) { 4139 /* 4140 * Finish up the pmap_remove_all() optimisation by flushing 4141 * the TLB. 4142 */ 4143 pmap_tlb_flushID(pm); 4144 pm->pm_remove_all = false; 4145 } 4146 4147 if (pmap_is_current(pm)) { 4148 /* 4149 * If we're dealing with a current userland pmap, move its L1 4150 * to the end of the LRU. 4151 */ 4152 if (pm != pmap_kernel()) 4153 pmap_use_l1(pm); 4154 4155 /* 4156 * We can assume we're done with frobbing the cache/tlb for 4157 * now. Make sure any future pmap ops don't skip cache/tlb 4158 * flushes. 4159 */ 4160 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4161 } 4162 4163 PMAPCOUNT(updates); 4164 4165 /* 4166 * make sure TLB/cache operations have completed. 4167 */ 4168 cpu_cpwait(); 4169 } 4170 4171 void 4172 pmap_remove_all(pmap_t pm) 4173 { 4174 4175 /* 4176 * The vmspace described by this pmap is about to be torn down. 4177 * Until pmap_update() is called, UVM will only make calls 4178 * to pmap_remove(). We can make life much simpler by flushing 4179 * the cache now, and deferring TLB invalidation to pmap_update(). 4180 */ 4181 #ifdef PMAP_CACHE_VIVT 4182 pmap_idcache_wbinv_all(pm); 4183 #endif 4184 pm->pm_remove_all = true; 4185 } 4186 4187 /* 4188 * Retire the given physical map from service. 4189 * Should only be called if the map contains no valid mappings. 4190 */ 4191 void 4192 pmap_destroy(pmap_t pm) 4193 { 4194 u_int count; 4195 4196 if (pm == NULL) 4197 return; 4198 4199 if (pm->pm_remove_all) { 4200 pmap_tlb_flushID(pm); 4201 pm->pm_remove_all = false; 4202 } 4203 4204 /* 4205 * Drop reference count 4206 */ 4207 mutex_enter(&pm->pm_lock); 4208 count = --pm->pm_obj.uo_refs; 4209 mutex_exit(&pm->pm_lock); 4210 if (count > 0) { 4211 if (pmap_is_current(pm)) { 4212 if (pm != pmap_kernel()) 4213 pmap_use_l1(pm); 4214 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4215 } 4216 return; 4217 } 4218 4219 /* 4220 * reference count is zero, free pmap resources and then free pmap. 4221 */ 4222 4223 if (vector_page < KERNEL_BASE) { 4224 KDASSERT(!pmap_is_current(pm)); 4225 4226 /* Remove the vector page mapping */ 4227 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4228 pmap_update(pm); 4229 } 4230 4231 LIST_REMOVE(pm, pm_list); 4232 4233 pmap_free_l1(pm); 4234 4235 if (pmap_recent_user == pm) 4236 pmap_recent_user = NULL; 4237 4238 UVM_OBJ_DESTROY(&pm->pm_obj); 4239 4240 /* return the pmap to the pool */ 4241 pool_cache_put(&pmap_cache, pm); 4242 } 4243 4244 4245 /* 4246 * void pmap_reference(pmap_t pm) 4247 * 4248 * Add a reference to the specified pmap. 4249 */ 4250 void 4251 pmap_reference(pmap_t pm) 4252 { 4253 4254 if (pm == NULL) 4255 return; 4256 4257 pmap_use_l1(pm); 4258 4259 mutex_enter(&pm->pm_lock); 4260 pm->pm_obj.uo_refs++; 4261 mutex_exit(&pm->pm_lock); 4262 } 4263 4264 #if ARM_MMU_V6 > 0 4265 4266 static struct evcnt pmap_prefer_nochange_ev = 4267 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4268 static struct evcnt pmap_prefer_change_ev = 4269 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4270 4271 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4272 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4273 4274 void 4275 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4276 { 4277 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4278 vaddr_t va = *vap; 4279 vaddr_t diff = (hint - va) & mask; 4280 if (diff == 0) { 4281 pmap_prefer_nochange_ev.ev_count++; 4282 } else { 4283 pmap_prefer_change_ev.ev_count++; 4284 if (__predict_false(td)) 4285 va -= mask + 1; 4286 *vap = va + diff; 4287 } 4288 } 4289 #endif /* ARM_MMU_V6 */ 4290 4291 /* 4292 * pmap_zero_page() 4293 * 4294 * Zero a given physical page by mapping it at a page hook point. 4295 * In doing the zero page op, the page we zero is mapped cachable, as with 4296 * StrongARM accesses to non-cached pages are non-burst making writing 4297 * _any_ bulk data very slow. 4298 */ 4299 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4300 void 4301 pmap_zero_page_generic(paddr_t phys) 4302 { 4303 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4304 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4305 #endif 4306 #ifdef PMAP_CACHE_VIPT 4307 /* Choose the last page color it had, if any */ 4308 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4309 #else 4310 const vsize_t va_offset = 0; 4311 #endif 4312 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4313 4314 #ifdef DEBUG 4315 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4316 panic("pmap_zero_page: page has mappings"); 4317 #endif 4318 4319 KDASSERT((phys & PGOFSET) == 0); 4320 4321 /* 4322 * Hook in the page, zero it, and purge the cache for that 4323 * zeroed page. Invalidate the TLB as needed. 4324 */ 4325 *ptep = L2_S_PROTO | phys | 4326 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4327 PTE_SYNC(ptep); 4328 cpu_tlb_flushD_SE(cdstp + va_offset); 4329 cpu_cpwait(); 4330 bzero_page(cdstp + va_offset); 4331 /* 4332 * Unmap the page. 4333 */ 4334 *ptep = 0; 4335 PTE_SYNC(ptep); 4336 cpu_tlb_flushD_SE(cdstp + va_offset); 4337 #ifdef PMAP_CACHE_VIVT 4338 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4339 #endif 4340 #ifdef PMAP_CACHE_VIPT 4341 /* 4342 * This page is now cache resident so it now has a page color. 4343 * Any contents have been obliterated so clear the EXEC flag. 4344 */ 4345 if (!pmap_is_page_colored_p(pg)) { 4346 PMAPCOUNT(vac_color_new); 4347 pg->mdpage.pvh_attrs |= PVF_COLORED; 4348 } 4349 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4350 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4351 PMAPCOUNT(exec_discarded_zero); 4352 } 4353 pg->mdpage.pvh_attrs |= PVF_DIRTY; 4354 #endif 4355 } 4356 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4357 4358 #if ARM_MMU_XSCALE == 1 4359 void 4360 pmap_zero_page_xscale(paddr_t phys) 4361 { 4362 #ifdef DEBUG 4363 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4364 4365 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4366 panic("pmap_zero_page: page has mappings"); 4367 #endif 4368 4369 KDASSERT((phys & PGOFSET) == 0); 4370 4371 /* 4372 * Hook in the page, zero it, and purge the cache for that 4373 * zeroed page. Invalidate the TLB as needed. 4374 */ 4375 *cdst_pte = L2_S_PROTO | phys | 4376 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4377 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4378 PTE_SYNC(cdst_pte); 4379 cpu_tlb_flushD_SE(cdstp); 4380 cpu_cpwait(); 4381 bzero_page(cdstp); 4382 xscale_cache_clean_minidata(); 4383 } 4384 #endif /* ARM_MMU_XSCALE == 1 */ 4385 4386 /* pmap_pageidlezero() 4387 * 4388 * The same as above, except that we assume that the page is not 4389 * mapped. This means we never have to flush the cache first. Called 4390 * from the idle loop. 4391 */ 4392 bool 4393 pmap_pageidlezero(paddr_t phys) 4394 { 4395 unsigned int i; 4396 int *ptr; 4397 bool rv = true; 4398 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4399 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4400 #endif 4401 #ifdef PMAP_CACHE_VIPT 4402 /* Choose the last page color it had, if any */ 4403 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4404 #else 4405 const vsize_t va_offset = 0; 4406 #endif 4407 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4408 4409 4410 #ifdef DEBUG 4411 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4412 panic("pmap_pageidlezero: page has mappings"); 4413 #endif 4414 4415 KDASSERT((phys & PGOFSET) == 0); 4416 4417 /* 4418 * Hook in the page, zero it, and purge the cache for that 4419 * zeroed page. Invalidate the TLB as needed. 4420 */ 4421 *ptep = L2_S_PROTO | phys | 4422 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4423 PTE_SYNC(ptep); 4424 cpu_tlb_flushD_SE(cdstp + va_offset); 4425 cpu_cpwait(); 4426 4427 for (i = 0, ptr = (int *)(cdstp + va_offset); 4428 i < (PAGE_SIZE / sizeof(int)); i++) { 4429 if (sched_curcpu_runnable_p() != 0) { 4430 /* 4431 * A process has become ready. Abort now, 4432 * so we don't keep it waiting while we 4433 * do slow memory access to finish this 4434 * page. 4435 */ 4436 rv = false; 4437 break; 4438 } 4439 *ptr++ = 0; 4440 } 4441 4442 #ifdef PMAP_CACHE_VIVT 4443 if (rv) 4444 /* 4445 * if we aborted we'll rezero this page again later so don't 4446 * purge it unless we finished it 4447 */ 4448 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4449 #elif defined(PMAP_CACHE_VIPT) 4450 /* 4451 * This page is now cache resident so it now has a page color. 4452 * Any contents have been obliterated so clear the EXEC flag. 4453 */ 4454 if (!pmap_is_page_colored_p(pg)) { 4455 PMAPCOUNT(vac_color_new); 4456 pg->mdpage.pvh_attrs |= PVF_COLORED; 4457 } 4458 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4459 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4460 PMAPCOUNT(exec_discarded_zero); 4461 } 4462 #endif 4463 /* 4464 * Unmap the page. 4465 */ 4466 *ptep = 0; 4467 PTE_SYNC(ptep); 4468 cpu_tlb_flushD_SE(cdstp + va_offset); 4469 4470 return (rv); 4471 } 4472 4473 /* 4474 * pmap_copy_page() 4475 * 4476 * Copy one physical page into another, by mapping the pages into 4477 * hook points. The same comment regarding cachability as in 4478 * pmap_zero_page also applies here. 4479 */ 4480 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4481 void 4482 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4483 { 4484 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4485 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4486 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4487 #endif 4488 #ifdef PMAP_CACHE_VIPT 4489 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4490 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4491 #else 4492 const vsize_t src_va_offset = 0; 4493 const vsize_t dst_va_offset = 0; 4494 #endif 4495 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4496 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4497 4498 #ifdef DEBUG 4499 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4500 panic("pmap_copy_page: dst page has mappings"); 4501 #endif 4502 4503 #ifdef PMAP_CACHE_VIPT 4504 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4505 #endif 4506 KDASSERT((src & PGOFSET) == 0); 4507 KDASSERT((dst & PGOFSET) == 0); 4508 4509 /* 4510 * Clean the source page. Hold the source page's lock for 4511 * the duration of the copy so that no other mappings can 4512 * be created while we have a potentially aliased mapping. 4513 */ 4514 simple_lock(&src_pg->mdpage.pvh_slock); 4515 #ifdef PMAP_CACHE_VIVT 4516 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4517 #endif 4518 4519 /* 4520 * Map the pages into the page hook points, copy them, and purge 4521 * the cache for the appropriate page. Invalidate the TLB 4522 * as required. 4523 */ 4524 *src_ptep = L2_S_PROTO 4525 | src 4526 #ifdef PMAP_CACHE_VIPT 4527 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4528 #endif 4529 #ifdef PMAP_CACHE_VIVT 4530 | pte_l2_s_cache_mode 4531 #endif 4532 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4533 *dst_ptep = L2_S_PROTO | dst | 4534 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4535 PTE_SYNC(src_ptep); 4536 PTE_SYNC(dst_ptep); 4537 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4538 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4539 cpu_cpwait(); 4540 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4541 #ifdef PMAP_CACHE_VIVT 4542 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4543 #endif 4544 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4545 #ifdef PMAP_CACHE_VIVT 4546 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4547 #endif 4548 /* 4549 * Unmap the pages. 4550 */ 4551 *src_ptep = 0; 4552 *dst_ptep = 0; 4553 PTE_SYNC(src_ptep); 4554 PTE_SYNC(dst_ptep); 4555 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4556 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4557 #ifdef PMAP_CACHE_VIPT 4558 /* 4559 * Now that the destination page is in the cache, mark it as colored. 4560 * If this was an exec page, discard it. 4561 */ 4562 if (!pmap_is_page_colored_p(dst_pg)) { 4563 PMAPCOUNT(vac_color_new); 4564 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4565 } 4566 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4567 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4568 PMAPCOUNT(exec_discarded_copy); 4569 } 4570 dst_pg->mdpage.pvh_attrs |= PVF_DIRTY; 4571 #endif 4572 } 4573 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4574 4575 #if ARM_MMU_XSCALE == 1 4576 void 4577 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4578 { 4579 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4580 #ifdef DEBUG 4581 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4582 4583 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4584 panic("pmap_copy_page: dst page has mappings"); 4585 #endif 4586 4587 KDASSERT((src & PGOFSET) == 0); 4588 KDASSERT((dst & PGOFSET) == 0); 4589 4590 /* 4591 * Clean the source page. Hold the source page's lock for 4592 * the duration of the copy so that no other mappings can 4593 * be created while we have a potentially aliased mapping. 4594 */ 4595 simple_lock(&src_pg->mdpage.pvh_slock); 4596 #ifdef PMAP_CACHE_VIVT 4597 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4598 #endif 4599 4600 /* 4601 * Map the pages into the page hook points, copy them, and purge 4602 * the cache for the appropriate page. Invalidate the TLB 4603 * as required. 4604 */ 4605 *csrc_pte = L2_S_PROTO | src | 4606 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4607 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4608 PTE_SYNC(csrc_pte); 4609 *cdst_pte = L2_S_PROTO | dst | 4610 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4611 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4612 PTE_SYNC(cdst_pte); 4613 cpu_tlb_flushD_SE(csrcp); 4614 cpu_tlb_flushD_SE(cdstp); 4615 cpu_cpwait(); 4616 bcopy_page(csrcp, cdstp); 4617 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4618 xscale_cache_clean_minidata(); 4619 } 4620 #endif /* ARM_MMU_XSCALE == 1 */ 4621 4622 /* 4623 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4624 * 4625 * Return the start and end addresses of the kernel's virtual space. 4626 * These values are setup in pmap_bootstrap and are updated as pages 4627 * are allocated. 4628 */ 4629 void 4630 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4631 { 4632 *start = virtual_avail; 4633 *end = virtual_end; 4634 } 4635 4636 /* 4637 * Helper function for pmap_grow_l2_bucket() 4638 */ 4639 static inline int 4640 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4641 { 4642 struct l2_bucket *l2b; 4643 pt_entry_t *ptep; 4644 paddr_t pa; 4645 4646 if (uvm.page_init_done == false) { 4647 #ifdef PMAP_STEAL_MEMORY 4648 pv_addr_t pv; 4649 pmap_boot_pagealloc(PAGE_SIZE, 4650 #ifdef PMAP_CACHE_VIPT 4651 arm_cache_prefer_mask, 4652 va & arm_cache_prefer_mask, 4653 #else 4654 0, 0, 4655 #endif 4656 &pv); 4657 pa = pv.pv_pa; 4658 #else 4659 if (uvm_page_physget(&pa) == false) 4660 return (1); 4661 #endif /* PMAP_STEAL_MEMORY */ 4662 } else { 4663 struct vm_page *pg; 4664 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4665 if (pg == NULL) 4666 return (1); 4667 pa = VM_PAGE_TO_PHYS(pg); 4668 #ifdef PMAP_CACHE_VIPT 4669 /* 4670 * This new page must not have any mappings. Enter it via 4671 * pmap_kenter_pa and let that routine do the hard work. 4672 */ 4673 KASSERT(SLIST_EMPTY(&pg->mdpage.pvh_list)); 4674 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 4675 #endif 4676 } 4677 4678 if (pap) 4679 *pap = pa; 4680 4681 PMAPCOUNT(pt_mappings); 4682 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4683 KDASSERT(l2b != NULL); 4684 4685 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4686 *ptep = L2_S_PROTO | pa | cache_mode | 4687 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4688 PTE_SYNC(ptep); 4689 memset((void *)va, 0, PAGE_SIZE); 4690 return (0); 4691 } 4692 4693 /* 4694 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4695 * used by pmap_growkernel(). 4696 */ 4697 static inline struct l2_bucket * 4698 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4699 { 4700 struct l2_dtable *l2; 4701 struct l2_bucket *l2b; 4702 u_short l1idx; 4703 vaddr_t nva; 4704 4705 l1idx = L1_IDX(va); 4706 4707 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4708 /* 4709 * No mapping at this address, as there is 4710 * no entry in the L1 table. 4711 * Need to allocate a new l2_dtable. 4712 */ 4713 nva = pmap_kernel_l2dtable_kva; 4714 if ((nva & PGOFSET) == 0) { 4715 /* 4716 * Need to allocate a backing page 4717 */ 4718 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4719 return (NULL); 4720 } 4721 4722 l2 = (struct l2_dtable *)nva; 4723 nva += sizeof(struct l2_dtable); 4724 4725 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4726 /* 4727 * The new l2_dtable straddles a page boundary. 4728 * Map in another page to cover it. 4729 */ 4730 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4731 return (NULL); 4732 } 4733 4734 pmap_kernel_l2dtable_kva = nva; 4735 4736 /* 4737 * Link it into the parent pmap 4738 */ 4739 pm->pm_l2[L2_IDX(l1idx)] = l2; 4740 } 4741 4742 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4743 4744 /* 4745 * Fetch pointer to the L2 page table associated with the address. 4746 */ 4747 if (l2b->l2b_kva == NULL) { 4748 pt_entry_t *ptep; 4749 4750 /* 4751 * No L2 page table has been allocated. Chances are, this 4752 * is because we just allocated the l2_dtable, above. 4753 */ 4754 nva = pmap_kernel_l2ptp_kva; 4755 ptep = (pt_entry_t *)nva; 4756 if ((nva & PGOFSET) == 0) { 4757 /* 4758 * Need to allocate a backing page 4759 */ 4760 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4761 &pmap_kernel_l2ptp_phys)) 4762 return (NULL); 4763 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4764 } 4765 4766 l2->l2_occupancy++; 4767 l2b->l2b_kva = ptep; 4768 l2b->l2b_l1idx = l1idx; 4769 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4770 4771 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4772 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4773 } 4774 4775 return (l2b); 4776 } 4777 4778 vaddr_t 4779 pmap_growkernel(vaddr_t maxkvaddr) 4780 { 4781 pmap_t kpm = pmap_kernel(); 4782 struct l1_ttable *l1; 4783 struct l2_bucket *l2b; 4784 pd_entry_t *pl1pd; 4785 int s; 4786 4787 if (maxkvaddr <= pmap_curmaxkvaddr) 4788 goto out; /* we are OK */ 4789 4790 NPDEBUG(PDB_GROWKERN, 4791 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4792 pmap_curmaxkvaddr, maxkvaddr)); 4793 4794 KDASSERT(maxkvaddr <= virtual_end); 4795 4796 /* 4797 * whoops! we need to add kernel PTPs 4798 */ 4799 4800 s = splhigh(); /* to be safe */ 4801 mutex_enter(&kpm->pm_lock); 4802 4803 /* Map 1MB at a time */ 4804 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4805 4806 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4807 KDASSERT(l2b != NULL); 4808 4809 /* Distribute new L1 entry to all other L1s */ 4810 SLIST_FOREACH(l1, &l1_list, l1_link) { 4811 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4812 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4813 L1_C_PROTO; 4814 PTE_SYNC(pl1pd); 4815 } 4816 } 4817 4818 /* 4819 * flush out the cache, expensive but growkernel will happen so 4820 * rarely 4821 */ 4822 cpu_dcache_wbinv_all(); 4823 cpu_tlb_flushD(); 4824 cpu_cpwait(); 4825 4826 mutex_exit(&kpm->pm_lock); 4827 splx(s); 4828 4829 out: 4830 return (pmap_curmaxkvaddr); 4831 } 4832 4833 /************************ Utility routines ****************************/ 4834 4835 /* 4836 * vector_page_setprot: 4837 * 4838 * Manipulate the protection of the vector page. 4839 */ 4840 void 4841 vector_page_setprot(int prot) 4842 { 4843 struct l2_bucket *l2b; 4844 pt_entry_t *ptep; 4845 4846 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4847 KDASSERT(l2b != NULL); 4848 4849 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4850 4851 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4852 PTE_SYNC(ptep); 4853 cpu_tlb_flushD_SE(vector_page); 4854 cpu_cpwait(); 4855 } 4856 4857 /* 4858 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4859 * Returns true if the mapping exists, else false. 4860 * 4861 * NOTE: This function is only used by a couple of arm-specific modules. 4862 * It is not safe to take any pmap locks here, since we could be right 4863 * in the middle of debugging the pmap anyway... 4864 * 4865 * It is possible for this routine to return false even though a valid 4866 * mapping does exist. This is because we don't lock, so the metadata 4867 * state may be inconsistent. 4868 * 4869 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4870 * a "section" mapping. 4871 */ 4872 bool 4873 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4874 { 4875 struct l2_dtable *l2; 4876 pd_entry_t *pl1pd, l1pd; 4877 pt_entry_t *ptep; 4878 u_short l1idx; 4879 4880 if (pm->pm_l1 == NULL) 4881 return false; 4882 4883 l1idx = L1_IDX(va); 4884 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4885 l1pd = *pl1pd; 4886 4887 if (l1pte_section_p(l1pd)) { 4888 *ptp = NULL; 4889 return true; 4890 } 4891 4892 if (pm->pm_l2 == NULL) 4893 return false; 4894 4895 l2 = pm->pm_l2[L2_IDX(l1idx)]; 4896 4897 if (l2 == NULL || 4898 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 4899 return false; 4900 } 4901 4902 *ptp = &ptep[l2pte_index(va)]; 4903 return true; 4904 } 4905 4906 bool 4907 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 4908 { 4909 u_short l1idx; 4910 4911 if (pm->pm_l1 == NULL) 4912 return false; 4913 4914 l1idx = L1_IDX(va); 4915 *pdp = &pm->pm_l1->l1_kva[l1idx]; 4916 4917 return true; 4918 } 4919 4920 /************************ Bootstrapping routines ****************************/ 4921 4922 static void 4923 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 4924 { 4925 int i; 4926 4927 l1->l1_kva = l1pt; 4928 l1->l1_domain_use_count = 0; 4929 l1->l1_domain_first = 0; 4930 4931 for (i = 0; i < PMAP_DOMAINS; i++) 4932 l1->l1_domain_free[i] = i + 1; 4933 4934 /* 4935 * Copy the kernel's L1 entries to each new L1. 4936 */ 4937 if (pmap_initialized) 4938 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 4939 4940 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 4941 &l1->l1_physaddr) == false) 4942 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 4943 4944 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 4945 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 4946 } 4947 4948 /* 4949 * pmap_bootstrap() is called from the board-specific initarm() routine 4950 * once the kernel L1/L2 descriptors tables have been set up. 4951 * 4952 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 4953 * spread over a number of disparate files/functions. 4954 * 4955 * We are passed the following parameters 4956 * - kernel_l1pt 4957 * This is a pointer to the base of the kernel's L1 translation table. 4958 * - vstart 4959 * 1MB-aligned start of managed kernel virtual memory. 4960 * - vend 4961 * 1MB-aligned end of managed kernel virtual memory. 4962 * 4963 * We use the first parameter to build the metadata (struct l1_ttable and 4964 * struct l2_dtable) necessary to track kernel mappings. 4965 */ 4966 #define PMAP_STATIC_L2_SIZE 16 4967 void 4968 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 4969 { 4970 static struct l1_ttable static_l1; 4971 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 4972 struct l1_ttable *l1 = &static_l1; 4973 struct l2_dtable *l2; 4974 struct l2_bucket *l2b; 4975 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 4976 pmap_t pm = pmap_kernel(); 4977 pd_entry_t pde; 4978 pt_entry_t *ptep; 4979 paddr_t pa; 4980 vaddr_t va; 4981 vsize_t size; 4982 int nptes, l1idx, l2idx, l2next = 0; 4983 4984 /* 4985 * Initialise the kernel pmap object 4986 */ 4987 pm->pm_l1 = l1; 4988 pm->pm_domain = PMAP_DOMAIN_KERNEL; 4989 pm->pm_activated = true; 4990 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4991 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 4992 4993 /* 4994 * Scan the L1 translation table created by initarm() and create 4995 * the required metadata for all valid mappings found in it. 4996 */ 4997 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 4998 pde = l1pt[l1idx]; 4999 5000 /* 5001 * We're only interested in Coarse mappings. 5002 * pmap_extract() can deal with section mappings without 5003 * recourse to checking L2 metadata. 5004 */ 5005 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5006 continue; 5007 5008 /* 5009 * Lookup the KVA of this L2 descriptor table 5010 */ 5011 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5012 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5013 if (ptep == NULL) { 5014 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5015 (u_int)l1idx << L1_S_SHIFT, pa); 5016 } 5017 5018 /* 5019 * Fetch the associated L2 metadata structure. 5020 * Allocate a new one if necessary. 5021 */ 5022 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5023 if (l2next == PMAP_STATIC_L2_SIZE) 5024 panic("pmap_bootstrap: out of static L2s"); 5025 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5026 } 5027 5028 /* 5029 * One more L1 slot tracked... 5030 */ 5031 l2->l2_occupancy++; 5032 5033 /* 5034 * Fill in the details of the L2 descriptor in the 5035 * appropriate bucket. 5036 */ 5037 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5038 l2b->l2b_kva = ptep; 5039 l2b->l2b_phys = pa; 5040 l2b->l2b_l1idx = l1idx; 5041 5042 /* 5043 * Establish an initial occupancy count for this descriptor 5044 */ 5045 for (l2idx = 0; 5046 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5047 l2idx++) { 5048 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5049 l2b->l2b_occupancy++; 5050 } 5051 } 5052 5053 /* 5054 * Make sure the descriptor itself has the correct cache mode. 5055 * If not, fix it, but whine about the problem. Port-meisters 5056 * should consider this a clue to fix up their initarm() 5057 * function. :) 5058 */ 5059 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5060 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5061 "L2 pte @ %p\n", ptep); 5062 } 5063 } 5064 5065 /* 5066 * Ensure the primary (kernel) L1 has the correct cache mode for 5067 * a page table. Bitch if it is not correctly set. 5068 */ 5069 for (va = (vaddr_t)l1pt; 5070 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5071 if (pmap_set_pt_cache_mode(l1pt, va)) 5072 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5073 "primary L1 @ 0x%lx\n", va); 5074 } 5075 5076 cpu_dcache_wbinv_all(); 5077 cpu_tlb_flushID(); 5078 cpu_cpwait(); 5079 5080 /* 5081 * now we allocate the "special" VAs which are used for tmp mappings 5082 * by the pmap (and other modules). we allocate the VAs by advancing 5083 * virtual_avail (note that there are no pages mapped at these VAs). 5084 * 5085 * Managed KVM space start from wherever initarm() tells us. 5086 */ 5087 virtual_avail = vstart; 5088 virtual_end = vend; 5089 5090 #ifdef PMAP_CACHE_VIPT 5091 /* 5092 * If we have a VIPT cache, we need one page/pte per possible alias 5093 * page so we won't violate cache aliasing rules. 5094 */ 5095 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5096 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5097 #else 5098 nptes = 1; 5099 #endif 5100 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5101 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5102 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5103 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5104 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5105 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5106 (void *)&msgbufaddr, NULL); 5107 5108 /* 5109 * Allocate a range of kernel virtual address space to be used 5110 * for L2 descriptor tables and metadata allocation in 5111 * pmap_growkernel(). 5112 */ 5113 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5114 pmap_alloc_specials(&virtual_avail, 5115 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5116 &pmap_kernel_l2ptp_kva, NULL); 5117 5118 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5119 pmap_alloc_specials(&virtual_avail, 5120 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5121 &pmap_kernel_l2dtable_kva, NULL); 5122 5123 /* 5124 * init the static-global locks and global pmap list. 5125 */ 5126 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5127 5128 /* 5129 * We can now initialise the first L1's metadata. 5130 */ 5131 SLIST_INIT(&l1_list); 5132 TAILQ_INIT(&l1_lru_list); 5133 simple_lock_init(&l1_lru_lock); 5134 pmap_init_l1(l1, l1pt); 5135 5136 /* Set up vector page L1 details, if necessary */ 5137 if (vector_page < KERNEL_BASE) { 5138 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5139 l2b = pmap_get_l2_bucket(pm, vector_page); 5140 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5141 L1_C_DOM(pm->pm_domain); 5142 } else 5143 pm->pm_pl1vec = NULL; 5144 5145 /* 5146 * Initialize the pmap cache 5147 */ 5148 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5149 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5150 LIST_INIT(&pmap_pmaps); 5151 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5152 5153 /* 5154 * Initialize the pv pool. 5155 */ 5156 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5157 &pmap_bootstrap_pv_allocator, IPL_NONE); 5158 5159 /* 5160 * Initialize the L2 dtable pool and cache. 5161 */ 5162 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5163 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5164 5165 /* 5166 * Initialise the L2 descriptor table pool and cache 5167 */ 5168 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5169 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5170 pmap_l2ptp_ctor, NULL, NULL); 5171 5172 cpu_dcache_wbinv_all(); 5173 } 5174 5175 static int 5176 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5177 { 5178 pd_entry_t *pdep, pde; 5179 pt_entry_t *ptep, pte; 5180 vaddr_t pa; 5181 int rv = 0; 5182 5183 /* 5184 * Make sure the descriptor itself has the correct cache mode 5185 */ 5186 pdep = &kl1[L1_IDX(va)]; 5187 pde = *pdep; 5188 5189 if (l1pte_section_p(pde)) { 5190 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5191 *pdep = (pde & ~L1_S_CACHE_MASK) | 5192 pte_l1_s_cache_mode_pt; 5193 PTE_SYNC(pdep); 5194 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5195 rv = 1; 5196 } 5197 } else { 5198 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5199 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5200 if (ptep == NULL) 5201 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5202 5203 ptep = &ptep[l2pte_index(va)]; 5204 pte = *ptep; 5205 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5206 *ptep = (pte & ~L2_S_CACHE_MASK) | 5207 pte_l2_s_cache_mode_pt; 5208 PTE_SYNC(ptep); 5209 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5210 rv = 1; 5211 } 5212 } 5213 5214 return (rv); 5215 } 5216 5217 static void 5218 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5219 { 5220 vaddr_t va = *availp; 5221 struct l2_bucket *l2b; 5222 5223 if (ptep) { 5224 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5225 if (l2b == NULL) 5226 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5227 5228 if (ptep) 5229 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5230 } 5231 5232 *vap = va; 5233 *availp = va + (PAGE_SIZE * pages); 5234 } 5235 5236 void 5237 pmap_init(void) 5238 { 5239 extern int physmem; 5240 5241 /* 5242 * Set the available memory vars - These do not map to real memory 5243 * addresses and cannot as the physical memory is fragmented. 5244 * They are used by ps for %mem calculations. 5245 * One could argue whether this should be the entire memory or just 5246 * the memory that is useable in a user process. 5247 */ 5248 avail_start = 0; 5249 avail_end = physmem * PAGE_SIZE; 5250 5251 /* 5252 * Now we need to free enough pv_entry structures to allow us to get 5253 * the kmem_map/kmem_object allocated and inited (done after this 5254 * function is finished). to do this we allocate one bootstrap page out 5255 * of kernel_map and use it to provide an initial pool of pv_entry 5256 * structures. we never free this page. 5257 */ 5258 pool_setlowat(&pmap_pv_pool, 5259 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5260 5261 pmap_initialized = true; 5262 } 5263 5264 static vaddr_t last_bootstrap_page = 0; 5265 static void *free_bootstrap_pages = NULL; 5266 5267 static void * 5268 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5269 { 5270 extern void *pool_page_alloc(struct pool *, int); 5271 vaddr_t new_page; 5272 void *rv; 5273 5274 if (pmap_initialized) 5275 return (pool_page_alloc(pp, flags)); 5276 5277 if (free_bootstrap_pages) { 5278 rv = free_bootstrap_pages; 5279 free_bootstrap_pages = *((void **)rv); 5280 return (rv); 5281 } 5282 5283 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5284 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5285 5286 KASSERT(new_page > last_bootstrap_page); 5287 last_bootstrap_page = new_page; 5288 return ((void *)new_page); 5289 } 5290 5291 static void 5292 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5293 { 5294 extern void pool_page_free(struct pool *, void *); 5295 5296 if ((vaddr_t)v <= last_bootstrap_page) { 5297 *((void **)v) = free_bootstrap_pages; 5298 free_bootstrap_pages = v; 5299 return; 5300 } 5301 5302 if (pmap_initialized) { 5303 pool_page_free(pp, v); 5304 return; 5305 } 5306 } 5307 5308 /* 5309 * pmap_postinit() 5310 * 5311 * This routine is called after the vm and kmem subsystems have been 5312 * initialised. This allows the pmap code to perform any initialisation 5313 * that can only be done one the memory allocation is in place. 5314 */ 5315 void 5316 pmap_postinit(void) 5317 { 5318 extern paddr_t physical_start, physical_end; 5319 struct l2_bucket *l2b; 5320 struct l1_ttable *l1; 5321 struct pglist plist; 5322 struct vm_page *m; 5323 pd_entry_t *pl1pt; 5324 pt_entry_t *ptep, pte; 5325 vaddr_t va, eva; 5326 u_int loop, needed; 5327 int error; 5328 5329 pool_cache_setlowat(&pmap_l2ptp_cache, 5330 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5331 pool_cache_setlowat(&pmap_l2dtable_cache, 5332 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5333 5334 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5335 needed -= 1; 5336 5337 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5338 5339 for (loop = 0; loop < needed; loop++, l1++) { 5340 /* Allocate a L1 page table */ 5341 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5342 if (va == 0) 5343 panic("Cannot allocate L1 KVM"); 5344 5345 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5346 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5347 if (error) 5348 panic("Cannot allocate L1 physical pages"); 5349 5350 m = TAILQ_FIRST(&plist); 5351 eva = va + L1_TABLE_SIZE; 5352 pl1pt = (pd_entry_t *)va; 5353 5354 while (m && va < eva) { 5355 paddr_t pa = VM_PAGE_TO_PHYS(m); 5356 5357 pmap_kenter_pa(va, pa, 5358 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 5359 5360 /* 5361 * Make sure the L1 descriptor table is mapped 5362 * with the cache-mode set to write-through. 5363 */ 5364 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5365 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5366 pte = *ptep; 5367 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5368 *ptep = pte; 5369 PTE_SYNC(ptep); 5370 cpu_tlb_flushD_SE(va); 5371 5372 va += PAGE_SIZE; 5373 m = TAILQ_NEXT(m, pageq.queue); 5374 } 5375 5376 #ifdef DIAGNOSTIC 5377 if (m) 5378 panic("pmap_alloc_l1pt: pglist not empty"); 5379 #endif /* DIAGNOSTIC */ 5380 5381 pmap_init_l1(l1, pl1pt); 5382 } 5383 5384 #ifdef DEBUG 5385 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5386 needed); 5387 #endif 5388 } 5389 5390 /* 5391 * Note that the following routines are used by board-specific initialisation 5392 * code to configure the initial kernel page tables. 5393 * 5394 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5395 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5396 * behaviour of the old pmap, and provides an easy migration path for 5397 * initial bring-up of the new pmap on existing ports. Fortunately, 5398 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5399 * will be deprecated. 5400 * 5401 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5402 * tables. 5403 */ 5404 5405 /* 5406 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5407 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5408 * find them as necessary. 5409 * 5410 * Note that the data on this list MUST remain valid after initarm() returns, 5411 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5412 */ 5413 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5414 5415 static vaddr_t 5416 kernel_pt_lookup(paddr_t pa) 5417 { 5418 pv_addr_t *pv; 5419 5420 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5421 #ifndef ARM32_NEW_VM_LAYOUT 5422 if (pv->pv_pa == (pa & ~PGOFSET)) 5423 return (pv->pv_va | (pa & PGOFSET)); 5424 #else 5425 if (pv->pv_pa == pa) 5426 return (pv->pv_va); 5427 #endif 5428 } 5429 return (0); 5430 } 5431 5432 /* 5433 * pmap_map_section: 5434 * 5435 * Create a single section mapping. 5436 */ 5437 void 5438 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5439 { 5440 pd_entry_t *pde = (pd_entry_t *) l1pt; 5441 pd_entry_t fl; 5442 5443 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5444 5445 switch (cache) { 5446 case PTE_NOCACHE: 5447 default: 5448 fl = 0; 5449 break; 5450 5451 case PTE_CACHE: 5452 fl = pte_l1_s_cache_mode; 5453 break; 5454 5455 case PTE_PAGETABLE: 5456 fl = pte_l1_s_cache_mode_pt; 5457 break; 5458 } 5459 5460 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5461 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5462 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5463 } 5464 5465 /* 5466 * pmap_map_entry: 5467 * 5468 * Create a single page mapping. 5469 */ 5470 void 5471 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5472 { 5473 pd_entry_t *pde = (pd_entry_t *) l1pt; 5474 pt_entry_t fl; 5475 pt_entry_t *pte; 5476 5477 KASSERT(((va | pa) & PGOFSET) == 0); 5478 5479 switch (cache) { 5480 case PTE_NOCACHE: 5481 default: 5482 fl = 0; 5483 break; 5484 5485 case PTE_CACHE: 5486 fl = pte_l2_s_cache_mode; 5487 break; 5488 5489 case PTE_PAGETABLE: 5490 fl = pte_l2_s_cache_mode_pt; 5491 break; 5492 } 5493 5494 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5495 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5496 5497 #ifndef ARM32_NEW_VM_LAYOUT 5498 pte = (pt_entry_t *) 5499 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5500 #else 5501 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5502 #endif 5503 if (pte == NULL) 5504 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5505 5506 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5507 #ifndef ARM32_NEW_VM_LAYOUT 5508 pte += (va >> PGSHIFT) & 0x3ff; 5509 #else 5510 pte += l2pte_index(va); 5511 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5512 #endif 5513 *pte = fl; 5514 PTE_SYNC(pte); 5515 } 5516 5517 /* 5518 * pmap_link_l2pt: 5519 * 5520 * Link the L2 page table specified by "l2pv" into the L1 5521 * page table at the slot for "va". 5522 */ 5523 void 5524 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5525 { 5526 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5527 u_int slot = va >> L1_S_SHIFT; 5528 5529 #ifndef ARM32_NEW_VM_LAYOUT 5530 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5531 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5532 #endif 5533 5534 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5535 5536 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5537 #ifdef ARM32_NEW_VM_LAYOUT 5538 PTE_SYNC(&pde[slot]); 5539 #else 5540 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5541 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5542 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5543 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5544 #endif 5545 5546 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5547 } 5548 5549 /* 5550 * pmap_map_chunk: 5551 * 5552 * Map a chunk of memory using the most efficient mappings 5553 * possible (section, large page, small page) into the 5554 * provided L1 and L2 tables at the specified virtual address. 5555 */ 5556 vsize_t 5557 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5558 int prot, int cache) 5559 { 5560 pd_entry_t *pde = (pd_entry_t *) l1pt; 5561 pt_entry_t *pte, f1, f2s, f2l; 5562 vsize_t resid; 5563 int i; 5564 5565 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5566 5567 if (l1pt == 0) 5568 panic("pmap_map_chunk: no L1 table provided"); 5569 5570 #ifdef VERBOSE_INIT_ARM 5571 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5572 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5573 #endif 5574 5575 switch (cache) { 5576 case PTE_NOCACHE: 5577 default: 5578 f1 = 0; 5579 f2l = 0; 5580 f2s = 0; 5581 break; 5582 5583 case PTE_CACHE: 5584 f1 = pte_l1_s_cache_mode; 5585 f2l = pte_l2_l_cache_mode; 5586 f2s = pte_l2_s_cache_mode; 5587 break; 5588 5589 case PTE_PAGETABLE: 5590 f1 = pte_l1_s_cache_mode_pt; 5591 f2l = pte_l2_l_cache_mode_pt; 5592 f2s = pte_l2_s_cache_mode_pt; 5593 break; 5594 } 5595 5596 size = resid; 5597 5598 while (resid > 0) { 5599 /* See if we can use a section mapping. */ 5600 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5601 #ifdef VERBOSE_INIT_ARM 5602 printf("S"); 5603 #endif 5604 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5605 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5606 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5607 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5608 va += L1_S_SIZE; 5609 pa += L1_S_SIZE; 5610 resid -= L1_S_SIZE; 5611 continue; 5612 } 5613 5614 /* 5615 * Ok, we're going to use an L2 table. Make sure 5616 * one is actually in the corresponding L1 slot 5617 * for the current VA. 5618 */ 5619 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5620 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5621 5622 #ifndef ARM32_NEW_VM_LAYOUT 5623 pte = (pt_entry_t *) 5624 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5625 #else 5626 pte = (pt_entry_t *) kernel_pt_lookup( 5627 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5628 #endif 5629 if (pte == NULL) 5630 panic("pmap_map_chunk: can't find L2 table for VA" 5631 "0x%08lx", va); 5632 5633 /* See if we can use a L2 large page mapping. */ 5634 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5635 #ifdef VERBOSE_INIT_ARM 5636 printf("L"); 5637 #endif 5638 for (i = 0; i < 16; i++) { 5639 #ifndef ARM32_NEW_VM_LAYOUT 5640 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5641 L2_L_PROTO | pa | 5642 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5643 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5644 #else 5645 pte[l2pte_index(va) + i] = 5646 L2_L_PROTO | pa | 5647 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5648 PTE_SYNC(&pte[l2pte_index(va) + i]); 5649 #endif 5650 } 5651 va += L2_L_SIZE; 5652 pa += L2_L_SIZE; 5653 resid -= L2_L_SIZE; 5654 continue; 5655 } 5656 5657 /* Use a small page mapping. */ 5658 #ifdef VERBOSE_INIT_ARM 5659 printf("P"); 5660 #endif 5661 #ifndef ARM32_NEW_VM_LAYOUT 5662 pte[(va >> PGSHIFT) & 0x3ff] = 5663 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5664 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5665 #else 5666 pte[l2pte_index(va)] = 5667 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5668 PTE_SYNC(&pte[l2pte_index(va)]); 5669 #endif 5670 va += PAGE_SIZE; 5671 pa += PAGE_SIZE; 5672 resid -= PAGE_SIZE; 5673 } 5674 #ifdef VERBOSE_INIT_ARM 5675 printf("\n"); 5676 #endif 5677 return (size); 5678 } 5679 5680 /********************** Static device map routines ***************************/ 5681 5682 static const struct pmap_devmap *pmap_devmap_table; 5683 5684 /* 5685 * Register the devmap table. This is provided in case early console 5686 * initialization needs to register mappings created by bootstrap code 5687 * before pmap_devmap_bootstrap() is called. 5688 */ 5689 void 5690 pmap_devmap_register(const struct pmap_devmap *table) 5691 { 5692 5693 pmap_devmap_table = table; 5694 } 5695 5696 /* 5697 * Map all of the static regions in the devmap table, and remember 5698 * the devmap table so other parts of the kernel can look up entries 5699 * later. 5700 */ 5701 void 5702 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5703 { 5704 int i; 5705 5706 pmap_devmap_table = table; 5707 5708 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5709 #ifdef VERBOSE_INIT_ARM 5710 printf("devmap: %08lx -> %08lx @ %08lx\n", 5711 pmap_devmap_table[i].pd_pa, 5712 pmap_devmap_table[i].pd_pa + 5713 pmap_devmap_table[i].pd_size - 1, 5714 pmap_devmap_table[i].pd_va); 5715 #endif 5716 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5717 pmap_devmap_table[i].pd_pa, 5718 pmap_devmap_table[i].pd_size, 5719 pmap_devmap_table[i].pd_prot, 5720 pmap_devmap_table[i].pd_cache); 5721 } 5722 } 5723 5724 const struct pmap_devmap * 5725 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5726 { 5727 uint64_t endpa; 5728 int i; 5729 5730 if (pmap_devmap_table == NULL) 5731 return (NULL); 5732 5733 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5734 5735 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5736 if (pa >= pmap_devmap_table[i].pd_pa && 5737 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5738 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5739 return (&pmap_devmap_table[i]); 5740 } 5741 5742 return (NULL); 5743 } 5744 5745 const struct pmap_devmap * 5746 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5747 { 5748 int i; 5749 5750 if (pmap_devmap_table == NULL) 5751 return (NULL); 5752 5753 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5754 if (va >= pmap_devmap_table[i].pd_va && 5755 va + size - 1 <= pmap_devmap_table[i].pd_va + 5756 pmap_devmap_table[i].pd_size - 1) 5757 return (&pmap_devmap_table[i]); 5758 } 5759 5760 return (NULL); 5761 } 5762 5763 /********************** PTE initialization routines **************************/ 5764 5765 /* 5766 * These routines are called when the CPU type is identified to set up 5767 * the PTE prototypes, cache modes, etc. 5768 * 5769 * The variables are always here, just in case LKMs need to reference 5770 * them (though, they shouldn't). 5771 */ 5772 5773 pt_entry_t pte_l1_s_cache_mode; 5774 pt_entry_t pte_l1_s_cache_mode_pt; 5775 pt_entry_t pte_l1_s_cache_mask; 5776 5777 pt_entry_t pte_l2_l_cache_mode; 5778 pt_entry_t pte_l2_l_cache_mode_pt; 5779 pt_entry_t pte_l2_l_cache_mask; 5780 5781 pt_entry_t pte_l2_s_cache_mode; 5782 pt_entry_t pte_l2_s_cache_mode_pt; 5783 pt_entry_t pte_l2_s_cache_mask; 5784 5785 pt_entry_t pte_l2_s_prot_u; 5786 pt_entry_t pte_l2_s_prot_w; 5787 pt_entry_t pte_l2_s_prot_mask; 5788 5789 pt_entry_t pte_l1_s_proto; 5790 pt_entry_t pte_l1_c_proto; 5791 pt_entry_t pte_l2_s_proto; 5792 5793 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5794 void (*pmap_zero_page_func)(paddr_t); 5795 5796 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5797 void 5798 pmap_pte_init_generic(void) 5799 { 5800 5801 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5802 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5803 5804 pte_l2_l_cache_mode = L2_B|L2_C; 5805 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5806 5807 pte_l2_s_cache_mode = L2_B|L2_C; 5808 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5809 5810 /* 5811 * If we have a write-through cache, set B and C. If 5812 * we have a write-back cache, then we assume setting 5813 * only C will make those pages write-through. 5814 */ 5815 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5816 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5817 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5818 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5819 } else { 5820 #if ARM_MMU_V6 > 1 5821 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5822 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5823 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5824 #else 5825 pte_l1_s_cache_mode_pt = L1_S_C; 5826 pte_l2_l_cache_mode_pt = L2_C; 5827 pte_l2_s_cache_mode_pt = L2_C; 5828 #endif 5829 } 5830 5831 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5832 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5833 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5834 5835 pte_l1_s_proto = L1_S_PROTO_generic; 5836 pte_l1_c_proto = L1_C_PROTO_generic; 5837 pte_l2_s_proto = L2_S_PROTO_generic; 5838 5839 pmap_copy_page_func = pmap_copy_page_generic; 5840 pmap_zero_page_func = pmap_zero_page_generic; 5841 } 5842 5843 #if defined(CPU_ARM8) 5844 void 5845 pmap_pte_init_arm8(void) 5846 { 5847 5848 /* 5849 * ARM8 is compatible with generic, but we need to use 5850 * the page tables uncached. 5851 */ 5852 pmap_pte_init_generic(); 5853 5854 pte_l1_s_cache_mode_pt = 0; 5855 pte_l2_l_cache_mode_pt = 0; 5856 pte_l2_s_cache_mode_pt = 0; 5857 } 5858 #endif /* CPU_ARM8 */ 5859 5860 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5861 void 5862 pmap_pte_init_arm9(void) 5863 { 5864 5865 /* 5866 * ARM9 is compatible with generic, but we want to use 5867 * write-through caching for now. 5868 */ 5869 pmap_pte_init_generic(); 5870 5871 pte_l1_s_cache_mode = L1_S_C; 5872 pte_l2_l_cache_mode = L2_C; 5873 pte_l2_s_cache_mode = L2_C; 5874 5875 pte_l1_s_cache_mode_pt = L1_S_C; 5876 pte_l2_l_cache_mode_pt = L2_C; 5877 pte_l2_s_cache_mode_pt = L2_C; 5878 } 5879 #endif /* CPU_ARM9 */ 5880 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5881 5882 #if defined(CPU_ARM10) 5883 void 5884 pmap_pte_init_arm10(void) 5885 { 5886 5887 /* 5888 * ARM10 is compatible with generic, but we want to use 5889 * write-through caching for now. 5890 */ 5891 pmap_pte_init_generic(); 5892 5893 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 5894 pte_l2_l_cache_mode = L2_B | L2_C; 5895 pte_l2_s_cache_mode = L2_B | L2_C; 5896 5897 pte_l1_s_cache_mode_pt = L1_S_C; 5898 pte_l2_l_cache_mode_pt = L2_C; 5899 pte_l2_s_cache_mode_pt = L2_C; 5900 5901 } 5902 #endif /* CPU_ARM10 */ 5903 5904 #if ARM_MMU_SA1 == 1 5905 void 5906 pmap_pte_init_sa1(void) 5907 { 5908 5909 /* 5910 * The StrongARM SA-1 cache does not have a write-through 5911 * mode. So, do the generic initialization, then reset 5912 * the page table cache mode to B=1,C=1, and note that 5913 * the PTEs need to be sync'd. 5914 */ 5915 pmap_pte_init_generic(); 5916 5917 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5918 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5919 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5920 5921 pmap_needs_pte_sync = 1; 5922 } 5923 #endif /* ARM_MMU_SA1 == 1*/ 5924 5925 #if ARM_MMU_XSCALE == 1 5926 #if (ARM_NMMUS > 1) 5927 static u_int xscale_use_minidata; 5928 #endif 5929 5930 void 5931 pmap_pte_init_xscale(void) 5932 { 5933 uint32_t auxctl; 5934 int write_through = 0; 5935 5936 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5937 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 5938 5939 pte_l2_l_cache_mode = L2_B|L2_C; 5940 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 5941 5942 pte_l2_s_cache_mode = L2_B|L2_C; 5943 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 5944 5945 pte_l1_s_cache_mode_pt = L1_S_C; 5946 pte_l2_l_cache_mode_pt = L2_C; 5947 pte_l2_s_cache_mode_pt = L2_C; 5948 5949 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 5950 /* 5951 * The XScale core has an enhanced mode where writes that 5952 * miss the cache cause a cache line to be allocated. This 5953 * is significantly faster than the traditional, write-through 5954 * behavior of this case. 5955 */ 5956 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 5957 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 5958 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 5959 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 5960 5961 #ifdef XSCALE_CACHE_WRITE_THROUGH 5962 /* 5963 * Some versions of the XScale core have various bugs in 5964 * their cache units, the work-around for which is to run 5965 * the cache in write-through mode. Unfortunately, this 5966 * has a major (negative) impact on performance. So, we 5967 * go ahead and run fast-and-loose, in the hopes that we 5968 * don't line up the planets in a way that will trip the 5969 * bugs. 5970 * 5971 * However, we give you the option to be slow-but-correct. 5972 */ 5973 write_through = 1; 5974 #elif defined(XSCALE_CACHE_WRITE_BACK) 5975 /* force write back cache mode */ 5976 write_through = 0; 5977 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 5978 /* 5979 * Intel PXA2[15]0 processors are known to have a bug in 5980 * write-back cache on revision 4 and earlier (stepping 5981 * A[01] and B[012]). Fixed for C0 and later. 5982 */ 5983 { 5984 uint32_t id, type; 5985 5986 id = cpufunc_id(); 5987 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 5988 5989 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 5990 if ((id & CPU_ID_REVISION_MASK) < 5) { 5991 /* write through for stepping A0-1 and B0-2 */ 5992 write_through = 1; 5993 } 5994 } 5995 } 5996 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 5997 5998 if (write_through) { 5999 pte_l1_s_cache_mode = L1_S_C; 6000 pte_l2_l_cache_mode = L2_C; 6001 pte_l2_s_cache_mode = L2_C; 6002 } 6003 6004 #if (ARM_NMMUS > 1) 6005 xscale_use_minidata = 1; 6006 #endif 6007 6008 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6009 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6010 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6011 6012 pte_l1_s_proto = L1_S_PROTO_xscale; 6013 pte_l1_c_proto = L1_C_PROTO_xscale; 6014 pte_l2_s_proto = L2_S_PROTO_xscale; 6015 6016 pmap_copy_page_func = pmap_copy_page_xscale; 6017 pmap_zero_page_func = pmap_zero_page_xscale; 6018 6019 /* 6020 * Disable ECC protection of page table access, for now. 6021 */ 6022 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6023 auxctl &= ~XSCALE_AUXCTL_P; 6024 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6025 } 6026 6027 /* 6028 * xscale_setup_minidata: 6029 * 6030 * Set up the mini-data cache clean area. We require the 6031 * caller to allocate the right amount of physically and 6032 * virtually contiguous space. 6033 */ 6034 void 6035 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6036 { 6037 extern vaddr_t xscale_minidata_clean_addr; 6038 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6039 pd_entry_t *pde = (pd_entry_t *) l1pt; 6040 pt_entry_t *pte; 6041 vsize_t size; 6042 uint32_t auxctl; 6043 6044 xscale_minidata_clean_addr = va; 6045 6046 /* Round it to page size. */ 6047 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6048 6049 for (; size != 0; 6050 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6051 #ifndef ARM32_NEW_VM_LAYOUT 6052 pte = (pt_entry_t *) 6053 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6054 #else 6055 pte = (pt_entry_t *) kernel_pt_lookup( 6056 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6057 #endif 6058 if (pte == NULL) 6059 panic("xscale_setup_minidata: can't find L2 table for " 6060 "VA 0x%08lx", va); 6061 #ifndef ARM32_NEW_VM_LAYOUT 6062 pte[(va >> PGSHIFT) & 0x3ff] = 6063 #else 6064 pte[l2pte_index(va)] = 6065 #endif 6066 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6067 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6068 } 6069 6070 /* 6071 * Configure the mini-data cache for write-back with 6072 * read/write-allocate. 6073 * 6074 * NOTE: In order to reconfigure the mini-data cache, we must 6075 * make sure it contains no valid data! In order to do that, 6076 * we must issue a global data cache invalidate command! 6077 * 6078 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6079 * THIS IS VERY IMPORTANT! 6080 */ 6081 6082 /* Invalidate data and mini-data. */ 6083 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6084 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6085 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6086 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6087 } 6088 6089 /* 6090 * Change the PTEs for the specified kernel mappings such that they 6091 * will use the mini data cache instead of the main data cache. 6092 */ 6093 void 6094 pmap_uarea(vaddr_t va) 6095 { 6096 struct l2_bucket *l2b; 6097 pt_entry_t *ptep, *sptep, pte; 6098 vaddr_t next_bucket, eva; 6099 6100 #if (ARM_NMMUS > 1) 6101 if (xscale_use_minidata == 0) 6102 return; 6103 #endif 6104 6105 eva = va + USPACE; 6106 6107 while (va < eva) { 6108 next_bucket = L2_NEXT_BUCKET(va); 6109 if (next_bucket > eva) 6110 next_bucket = eva; 6111 6112 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6113 KDASSERT(l2b != NULL); 6114 6115 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6116 6117 while (va < next_bucket) { 6118 pte = *ptep; 6119 if (!l2pte_minidata(pte)) { 6120 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6121 cpu_tlb_flushD_SE(va); 6122 *ptep = pte & ~L2_B; 6123 } 6124 ptep++; 6125 va += PAGE_SIZE; 6126 } 6127 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6128 } 6129 cpu_cpwait(); 6130 } 6131 #endif /* ARM_MMU_XSCALE == 1 */ 6132 6133 /* 6134 * return the PA of the current L1 table, for use when handling a crash dump 6135 */ 6136 uint32_t pmap_kernel_L1_addr() 6137 { 6138 return pmap_kernel()->pm_l1->l1_physaddr; 6139 } 6140 6141 #if defined(DDB) 6142 /* 6143 * A couple of ddb-callable functions for dumping pmaps 6144 */ 6145 void pmap_dump_all(void); 6146 void pmap_dump(pmap_t); 6147 6148 void 6149 pmap_dump_all(void) 6150 { 6151 pmap_t pm; 6152 6153 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6154 if (pm == pmap_kernel()) 6155 continue; 6156 pmap_dump(pm); 6157 printf("\n"); 6158 } 6159 } 6160 6161 static pt_entry_t ncptes[64]; 6162 static void pmap_dump_ncpg(pmap_t); 6163 6164 void 6165 pmap_dump(pmap_t pm) 6166 { 6167 struct l2_dtable *l2; 6168 struct l2_bucket *l2b; 6169 pt_entry_t *ptep, pte; 6170 vaddr_t l2_va, l2b_va, va; 6171 int i, j, k, occ, rows = 0; 6172 6173 if (pm == pmap_kernel()) 6174 printf("pmap_kernel (%p): ", pm); 6175 else 6176 printf("user pmap (%p): ", pm); 6177 6178 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6179 6180 l2_va = 0; 6181 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6182 l2 = pm->pm_l2[i]; 6183 6184 if (l2 == NULL || l2->l2_occupancy == 0) 6185 continue; 6186 6187 l2b_va = l2_va; 6188 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6189 l2b = &l2->l2_bucket[j]; 6190 6191 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6192 continue; 6193 6194 ptep = l2b->l2b_kva; 6195 6196 for (k = 0; k < 256 && ptep[k] == 0; k++) 6197 ; 6198 6199 k &= ~63; 6200 occ = l2b->l2b_occupancy; 6201 va = l2b_va + (k * 4096); 6202 for (; k < 256; k++, va += 0x1000) { 6203 char ch = ' '; 6204 if ((k % 64) == 0) { 6205 if ((rows % 8) == 0) { 6206 printf( 6207 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6208 } 6209 printf("%08lx: ", va); 6210 } 6211 6212 ncptes[k & 63] = 0; 6213 pte = ptep[k]; 6214 if (pte == 0) { 6215 ch = '.'; 6216 } else { 6217 occ--; 6218 switch (pte & 0x0c) { 6219 case 0x00: 6220 ch = 'D'; /* No cache No buff */ 6221 break; 6222 case 0x04: 6223 ch = 'B'; /* No cache buff */ 6224 break; 6225 case 0x08: 6226 if (pte & 0x40) 6227 ch = 'm'; 6228 else 6229 ch = 'C'; /* Cache No buff */ 6230 break; 6231 case 0x0c: 6232 ch = 'F'; /* Cache Buff */ 6233 break; 6234 } 6235 6236 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6237 ch += 0x20; 6238 6239 if ((pte & 0xc) == 0) 6240 ncptes[k & 63] = pte; 6241 } 6242 6243 if ((k % 64) == 63) { 6244 rows++; 6245 printf("%c\n", ch); 6246 pmap_dump_ncpg(pm); 6247 if (occ == 0) 6248 break; 6249 } else 6250 printf("%c", ch); 6251 } 6252 } 6253 } 6254 } 6255 6256 static void 6257 pmap_dump_ncpg(pmap_t pm) 6258 { 6259 struct vm_page *pg; 6260 struct pv_entry *pv; 6261 int i; 6262 6263 for (i = 0; i < 63; i++) { 6264 if (ncptes[i] == 0) 6265 continue; 6266 6267 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6268 if (pg == NULL) 6269 continue; 6270 6271 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6272 VM_PAGE_TO_PHYS(pg), 6273 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 6274 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 6275 6276 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 6277 printf(" %c va 0x%08lx, flags 0x%x\n", 6278 (pm == pv->pv_pmap) ? '*' : ' ', 6279 pv->pv_va, pv->pv_flags); 6280 } 6281 } 6282 } 6283 #endif 6284 6285 #ifdef PMAP_STEAL_MEMORY 6286 void 6287 pmap_boot_pageadd(pv_addr_t *newpv) 6288 { 6289 pv_addr_t *pv, *npv; 6290 6291 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6292 if (newpv->pv_pa < pv->pv_va) { 6293 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6294 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6295 newpv->pv_size += pv->pv_size; 6296 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6297 } 6298 pv = NULL; 6299 } else { 6300 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6301 pv = npv) { 6302 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6303 KASSERT(pv->pv_pa < newpv->pv_pa); 6304 if (newpv->pv_pa > npv->pv_pa) 6305 continue; 6306 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6307 pv->pv_size += newpv->pv_size; 6308 return; 6309 } 6310 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6311 break; 6312 newpv->pv_size += npv->pv_size; 6313 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6314 SLIST_REMOVE_AFTER(newpv, pv_list); 6315 return; 6316 } 6317 } 6318 } 6319 6320 if (pv) { 6321 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6322 } else { 6323 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6324 } 6325 } 6326 6327 void 6328 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6329 pv_addr_t *rpv) 6330 { 6331 pv_addr_t *pv, **pvp; 6332 struct vm_physseg *ps; 6333 size_t i; 6334 6335 KASSERT(amount & PGOFSET); 6336 KASSERT((mask & PGOFSET) == 0); 6337 KASSERT((match & PGOFSET) == 0); 6338 KASSERT(amount != 0); 6339 6340 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6341 (pv = *pvp) != NULL; 6342 pvp = &SLIST_NEXT(pv, pv_list)) { 6343 pv_addr_t *newpv; 6344 psize_t off; 6345 /* 6346 * If this entry is too small to satify the request... 6347 */ 6348 KASSERT(pv->pv_size > 0); 6349 if (pv->pv_size < amount) 6350 continue; 6351 6352 for (off = 0; off <= mask; off += PAGE_SIZE) { 6353 if (((pv->pv_pa + off) & mask) == match 6354 && off + amount <= pv->pv_size) 6355 break; 6356 } 6357 if (off > mask) 6358 continue; 6359 6360 rpv->pv_va = pv->pv_va + off; 6361 rpv->pv_pa = pv->pv_pa + off; 6362 rpv->pv_size = amount; 6363 pv->pv_size -= amount; 6364 if (pv->pv_size == 0) { 6365 KASSERT(off == 0); 6366 KASSERT((vaddr_t) pv == rpv->pv_va); 6367 *pvp = SLIST_NEXT(pv, pv_list); 6368 } else if (off == 0) { 6369 KASSERT((vaddr_t) pv == rpv->pv_va); 6370 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6371 *newpv = *pv; 6372 newpv->pv_pa += amount; 6373 newpv->pv_va += amount; 6374 *pvp = newpv; 6375 } else if (off < pv->pv_size) { 6376 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6377 *newpv = *pv; 6378 newpv->pv_size -= off; 6379 newpv->pv_pa += off + amount; 6380 newpv->pv_va += off + amount; 6381 6382 SLIST_NEXT(pv, pv_list) = newpv; 6383 pv->pv_size = off; 6384 } else { 6385 KASSERT((vaddr_t) pv != rpv->pv_va); 6386 } 6387 memset((void *)rpv->pv_va, 0, amount); 6388 return; 6389 } 6390 6391 if (vm_nphysseg == 0) 6392 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6393 6394 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6395 (pv = *pvp) != NULL; 6396 pvp = &SLIST_NEXT(pv, pv_list)) { 6397 if (SLIST_NEXT(pv, pv_list) == NULL) 6398 break; 6399 } 6400 KASSERT(mask == 0); 6401 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6402 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6403 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6404 rpv->pv_va = pv->pv_va; 6405 rpv->pv_pa = pv->pv_pa; 6406 rpv->pv_size = amount; 6407 *pvp = NULL; 6408 pmap_map_chunk(kernel_l1pt.pv_va, 6409 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6410 ptoa(ps->avail_start), 6411 amount - pv->pv_size, 6412 VM_PROT_READ|VM_PROT_WRITE, 6413 PTE_CACHE); 6414 ps->avail_start += atop(amount - pv->pv_size); 6415 /* 6416 * If we consumed the entire physseg, remove it. 6417 */ 6418 if (ps->avail_start == ps->avail_end) { 6419 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6420 ps[0] = ps[1]; 6421 } 6422 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6423 return; 6424 } 6425 } 6426 6427 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6428 } 6429 6430 vaddr_t 6431 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6432 { 6433 pv_addr_t pv; 6434 6435 pmap_boot_pagealloc(size, 0, 0, &pv); 6436 6437 return pv.pv_va; 6438 } 6439 #endif /* PMAP_STEAL_MEMORY */ 6440
Indexes created Thu Sep 25 06:09:39 GMT 2025