pmap.c revision 1.185
1 /* $NetBSD: pmap.c,v 1.185 2008/08/13 06:05:54 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/user.h> 202 #include <sys/pool.h> 203 #include <sys/cdefs.h> 204 #include <sys/cpu.h> 205 206 #include <uvm/uvm.h> 207 208 #include <machine/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.185 2008/08/13 06:05:54 matt Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 struct pmap kernel_pmap_store; 258 259 /* 260 * Which pmap is currently 'live' in the cache 261 * 262 * XXXSCW: Fix for SMP ... 263 */ 264 static pmap_t pmap_recent_user; 265 266 /* 267 * Pointer to last active lwp, or NULL if it exited. 268 */ 269 struct lwp *pmap_previous_active_lwp; 270 271 /* 272 * Pool and cache that pmap structures are allocated from. 273 * We use a cache to avoid clearing the pm_l2[] array (1KB) 274 * in pmap_create(). 275 */ 276 static struct pool_cache pmap_cache; 277 static LIST_HEAD(, pmap) pmap_pmaps; 278 279 /* 280 * Pool of PV structures 281 */ 282 static struct pool pmap_pv_pool; 283 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 284 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 285 static struct pool_allocator pmap_bootstrap_pv_allocator = { 286 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 287 }; 288 289 /* 290 * Pool and cache of l2_dtable structures. 291 * We use a cache to avoid clearing the structures when they're 292 * allocated. (196 bytes) 293 */ 294 static struct pool_cache pmap_l2dtable_cache; 295 static vaddr_t pmap_kernel_l2dtable_kva; 296 297 /* 298 * Pool and cache of L2 page descriptors. 299 * We use a cache to avoid clearing the descriptor table 300 * when they're allocated. (1KB) 301 */ 302 static struct pool_cache pmap_l2ptp_cache; 303 static vaddr_t pmap_kernel_l2ptp_kva; 304 static paddr_t pmap_kernel_l2ptp_phys; 305 306 #ifdef PMAPCOUNTERS 307 #define PMAP_EVCNT_INITIALIZER(name) \ 308 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 309 310 #ifdef PMAP_CACHE_VIPT 311 static struct evcnt pmap_ev_vac_color_new = 312 PMAP_EVCNT_INITIALIZER("new page color"); 313 static struct evcnt pmap_ev_vac_color_reuse = 314 PMAP_EVCNT_INITIALIZER("ok first page color"); 315 static struct evcnt pmap_ev_vac_color_ok = 316 PMAP_EVCNT_INITIALIZER("ok page color"); 317 static struct evcnt pmap_ev_vac_color_blind = 318 PMAP_EVCNT_INITIALIZER("blind page color"); 319 static struct evcnt pmap_ev_vac_color_change = 320 PMAP_EVCNT_INITIALIZER("change page color"); 321 static struct evcnt pmap_ev_vac_color_erase = 322 PMAP_EVCNT_INITIALIZER("erase page color"); 323 static struct evcnt pmap_ev_vac_color_none = 324 PMAP_EVCNT_INITIALIZER("no page color"); 325 static struct evcnt pmap_ev_vac_color_restore = 326 PMAP_EVCNT_INITIALIZER("restore page color"); 327 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 329 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 330 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 331 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 332 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 333 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 334 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 335 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 336 #endif 337 338 static struct evcnt pmap_ev_mappings = 339 PMAP_EVCNT_INITIALIZER("pages mapped"); 340 static struct evcnt pmap_ev_unmappings = 341 PMAP_EVCNT_INITIALIZER("pages unmapped"); 342 static struct evcnt pmap_ev_remappings = 343 PMAP_EVCNT_INITIALIZER("pages remapped"); 344 345 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 346 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 347 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 348 349 static struct evcnt pmap_ev_kernel_mappings = 350 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 351 static struct evcnt pmap_ev_kernel_unmappings = 352 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 353 static struct evcnt pmap_ev_kernel_remappings = 354 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 355 356 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 357 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 358 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 359 360 static struct evcnt pmap_ev_kenter_mappings = 361 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 362 static struct evcnt pmap_ev_kenter_unmappings = 363 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 364 static struct evcnt pmap_ev_kenter_remappings = 365 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 366 static struct evcnt pmap_ev_pt_mappings = 367 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 368 369 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 370 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 373 374 #ifdef PMAP_CACHE_VIPT 375 static struct evcnt pmap_ev_exec_mappings = 376 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 377 static struct evcnt pmap_ev_exec_cached = 378 PMAP_EVCNT_INITIALIZER("exec pages cached"); 379 380 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 381 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 382 383 static struct evcnt pmap_ev_exec_synced = 384 PMAP_EVCNT_INITIALIZER("exec pages synced"); 385 static struct evcnt pmap_ev_exec_synced_map = 386 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 387 static struct evcnt pmap_ev_exec_synced_unmap = 388 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 389 static struct evcnt pmap_ev_exec_synced_remap = 390 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 391 static struct evcnt pmap_ev_exec_synced_clearbit = 392 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 393 static struct evcnt pmap_ev_exec_synced_kremove = 394 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 395 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 397 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 399 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 400 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 401 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 402 403 static struct evcnt pmap_ev_exec_discarded_unmap = 404 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 405 static struct evcnt pmap_ev_exec_discarded_zero = 406 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 407 static struct evcnt pmap_ev_exec_discarded_copy = 408 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 409 static struct evcnt pmap_ev_exec_discarded_page_protect = 410 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 411 static struct evcnt pmap_ev_exec_discarded_clearbit = 412 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 413 static struct evcnt pmap_ev_exec_discarded_kremove = 414 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 415 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 422 #endif /* PMAP_CACHE_VIPT */ 423 424 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 425 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 426 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 427 428 EVCNT_ATTACH_STATIC(pmap_ev_updates); 429 EVCNT_ATTACH_STATIC(pmap_ev_collects); 430 EVCNT_ATTACH_STATIC(pmap_ev_activations); 431 432 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 433 #else 434 #define PMAPCOUNT(x) ((void)0) 435 #endif 436 437 /* 438 * pmap copy/zero page, and mem(5) hook point 439 */ 440 static pt_entry_t *csrc_pte, *cdst_pte; 441 static vaddr_t csrcp, cdstp; 442 vaddr_t memhook; /* used by mem.c */ 443 extern void *msgbufaddr; 444 445 /* 446 * Flag to indicate if pmap_init() has done its thing 447 */ 448 bool pmap_initialized; 449 450 /* 451 * Misc. locking data structures 452 */ 453 454 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 455 static struct lock pmap_main_lock; 456 457 #define PMAP_MAP_TO_HEAD_LOCK() \ 458 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 459 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 460 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 461 #define PMAP_HEAD_TO_MAP_LOCK() \ 462 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 463 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 464 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 465 #else 466 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 467 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 468 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 469 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 470 #endif 471 472 #define pmap_acquire_pmap_lock(pm) \ 473 do { \ 474 if ((pm) != pmap_kernel()) \ 475 mutex_enter(&(pm)->pm_lock); \ 476 } while (/*CONSTCOND*/0) 477 478 #define pmap_release_pmap_lock(pm) \ 479 do { \ 480 if ((pm) != pmap_kernel()) \ 481 mutex_exit(&(pm)->pm_lock); \ 482 } while (/*CONSTCOND*/0) 483 484 485 /* 486 * Metadata for L1 translation tables. 487 */ 488 struct l1_ttable { 489 /* Entry on the L1 Table list */ 490 SLIST_ENTRY(l1_ttable) l1_link; 491 492 /* Entry on the L1 Least Recently Used list */ 493 TAILQ_ENTRY(l1_ttable) l1_lru; 494 495 /* Track how many domains are allocated from this L1 */ 496 volatile u_int l1_domain_use_count; 497 498 /* 499 * A free-list of domain numbers for this L1. 500 * We avoid using ffs() and a bitmap to track domains since ffs() 501 * is slow on ARM. 502 */ 503 u_int8_t l1_domain_first; 504 u_int8_t l1_domain_free[PMAP_DOMAINS]; 505 506 /* Physical address of this L1 page table */ 507 paddr_t l1_physaddr; 508 509 /* KVA of this L1 page table */ 510 pd_entry_t *l1_kva; 511 }; 512 513 /* 514 * Convert a virtual address into its L1 table index. That is, the 515 * index used to locate the L2 descriptor table pointer in an L1 table. 516 * This is basically used to index l1->l1_kva[]. 517 * 518 * Each L2 descriptor table represents 1MB of VA space. 519 */ 520 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 521 522 /* 523 * L1 Page Tables are tracked using a Least Recently Used list. 524 * - New L1s are allocated from the HEAD. 525 * - Freed L1s are added to the TAIl. 526 * - Recently accessed L1s (where an 'access' is some change to one of 527 * the userland pmaps which owns this L1) are moved to the TAIL. 528 */ 529 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 530 static struct simplelock l1_lru_lock; 531 532 /* 533 * A list of all L1 tables 534 */ 535 static SLIST_HEAD(, l1_ttable) l1_list; 536 537 /* 538 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 539 * 540 * This is normally 16MB worth L2 page descriptors for any given pmap. 541 * Reference counts are maintained for L2 descriptors so they can be 542 * freed when empty. 543 */ 544 struct l2_dtable { 545 /* The number of L2 page descriptors allocated to this l2_dtable */ 546 u_int l2_occupancy; 547 548 /* List of L2 page descriptors */ 549 struct l2_bucket { 550 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 551 paddr_t l2b_phys; /* Physical address of same */ 552 u_short l2b_l1idx; /* This L2 table's L1 index */ 553 u_short l2b_occupancy; /* How many active descriptors */ 554 } l2_bucket[L2_BUCKET_SIZE]; 555 }; 556 557 /* 558 * Given an L1 table index, calculate the corresponding l2_dtable index 559 * and bucket index within the l2_dtable. 560 */ 561 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 562 (L2_SIZE - 1)) 563 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 564 565 /* 566 * Given a virtual address, this macro returns the 567 * virtual address required to drop into the next L2 bucket. 568 */ 569 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 570 571 /* 572 * L2 allocation. 573 */ 574 #define pmap_alloc_l2_dtable() \ 575 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 576 #define pmap_free_l2_dtable(l2) \ 577 pool_cache_put(&pmap_l2dtable_cache, (l2)) 578 #define pmap_alloc_l2_ptp(pap) \ 579 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 580 PR_NOWAIT, (pap))) 581 582 /* 583 * We try to map the page tables write-through, if possible. However, not 584 * all CPUs have a write-through cache mode, so on those we have to sync 585 * the cache when we frob page tables. 586 * 587 * We try to evaluate this at compile time, if possible. However, it's 588 * not always possible to do that, hence this run-time var. 589 */ 590 int pmap_needs_pte_sync; 591 592 /* 593 * Real definition of pv_entry. 594 */ 595 struct pv_entry { 596 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 597 pmap_t pv_pmap; /* pmap where mapping lies */ 598 vaddr_t pv_va; /* virtual address for mapping */ 599 u_int pv_flags; /* flags */ 600 }; 601 602 /* 603 * Macro to determine if a mapping might be resident in the 604 * instruction cache and/or TLB 605 */ 606 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 607 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 608 609 /* 610 * Macro to determine if a mapping might be resident in the 611 * data cache and/or TLB 612 */ 613 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 614 615 /* 616 * Local prototypes 617 */ 618 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 619 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 620 pt_entry_t **); 621 static bool pmap_is_current(pmap_t); 622 static bool pmap_is_cached(pmap_t); 623 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 624 pmap_t, vaddr_t, u_int); 625 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 626 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 627 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 628 u_int, u_int); 629 630 static void pmap_pinit(pmap_t); 631 static int pmap_pmap_ctor(void *, void *, int); 632 633 static void pmap_alloc_l1(pmap_t); 634 static void pmap_free_l1(pmap_t); 635 static void pmap_use_l1(pmap_t); 636 637 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 638 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 639 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 640 static int pmap_l2ptp_ctor(void *, void *, int); 641 static int pmap_l2dtable_ctor(void *, void *, int); 642 643 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 644 #ifdef PMAP_CACHE_VIVT 645 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 646 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 647 #endif 648 649 static void pmap_clearbit(struct vm_page *, u_int); 650 #ifdef PMAP_CACHE_VIVT 651 static int pmap_clean_page(struct pv_entry *, bool); 652 #endif 653 #ifdef PMAP_CACHE_VIPT 654 static void pmap_syncicache_page(struct vm_page *); 655 static void pmap_flush_page(struct vm_page *, bool); 656 #endif 657 static void pmap_page_remove(struct vm_page *); 658 659 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 660 static vaddr_t kernel_pt_lookup(paddr_t); 661 662 663 /* 664 * External function prototypes 665 */ 666 extern void bzero_page(vaddr_t); 667 extern void bcopy_page(vaddr_t, vaddr_t); 668 669 /* 670 * Misc variables 671 */ 672 vaddr_t virtual_avail; 673 vaddr_t virtual_end; 674 vaddr_t pmap_curmaxkvaddr; 675 676 vaddr_t avail_start; 677 vaddr_t avail_end; 678 679 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 680 pv_addr_t kernelpages; 681 pv_addr_t kernel_l1pt; 682 pv_addr_t systempage; 683 684 /* Function to set the debug level of the pmap code */ 685 686 #ifdef PMAP_DEBUG 687 void 688 pmap_debug(int level) 689 { 690 pmap_debug_level = level; 691 printf("pmap_debug: level=%d\n", pmap_debug_level); 692 } 693 #endif /* PMAP_DEBUG */ 694 695 /* 696 * A bunch of routines to conditionally flush the caches/TLB depending 697 * on whether the specified pmap actually needs to be flushed at any 698 * given time. 699 */ 700 static inline void 701 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 702 { 703 704 if (pm->pm_cstate.cs_tlb_id) 705 cpu_tlb_flushID_SE(va); 706 } 707 708 static inline void 709 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 710 { 711 712 if (pm->pm_cstate.cs_tlb_d) 713 cpu_tlb_flushD_SE(va); 714 } 715 716 static inline void 717 pmap_tlb_flushID(pmap_t pm) 718 { 719 720 if (pm->pm_cstate.cs_tlb_id) { 721 cpu_tlb_flushID(); 722 pm->pm_cstate.cs_tlb = 0; 723 } 724 } 725 726 static inline void 727 pmap_tlb_flushD(pmap_t pm) 728 { 729 730 if (pm->pm_cstate.cs_tlb_d) { 731 cpu_tlb_flushD(); 732 pm->pm_cstate.cs_tlb_d = 0; 733 } 734 } 735 736 #ifdef PMAP_CACHE_VIVT 737 static inline void 738 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 739 { 740 if (pm->pm_cstate.cs_cache_id) { 741 cpu_idcache_wbinv_range(va, len); 742 } 743 } 744 745 static inline void 746 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 747 bool do_inv, bool rd_only) 748 { 749 750 if (pm->pm_cstate.cs_cache_d) { 751 if (do_inv) { 752 if (rd_only) 753 cpu_dcache_inv_range(va, len); 754 else 755 cpu_dcache_wbinv_range(va, len); 756 } else 757 if (!rd_only) 758 cpu_dcache_wb_range(va, len); 759 } 760 } 761 762 static inline void 763 pmap_idcache_wbinv_all(pmap_t pm) 764 { 765 if (pm->pm_cstate.cs_cache_id) { 766 cpu_idcache_wbinv_all(); 767 pm->pm_cstate.cs_cache = 0; 768 } 769 } 770 771 static inline void 772 pmap_dcache_wbinv_all(pmap_t pm) 773 { 774 if (pm->pm_cstate.cs_cache_d) { 775 cpu_dcache_wbinv_all(); 776 pm->pm_cstate.cs_cache_d = 0; 777 } 778 } 779 #endif /* PMAP_CACHE_VIVT */ 780 781 static inline bool 782 pmap_is_current(pmap_t pm) 783 { 784 785 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 786 return true; 787 788 return false; 789 } 790 791 static inline bool 792 pmap_is_cached(pmap_t pm) 793 { 794 795 if (pm == pmap_kernel() || pmap_recent_user == NULL || 796 pmap_recent_user == pm) 797 return (true); 798 799 return false; 800 } 801 802 /* 803 * PTE_SYNC_CURRENT: 804 * 805 * Make sure the pte is written out to RAM. 806 * We need to do this for one of two cases: 807 * - We're dealing with the kernel pmap 808 * - There is no pmap active in the cache/tlb. 809 * - The specified pmap is 'active' in the cache/tlb. 810 */ 811 #ifdef PMAP_INCLUDE_PTE_SYNC 812 #define PTE_SYNC_CURRENT(pm, ptep) \ 813 do { \ 814 if (PMAP_NEEDS_PTE_SYNC && \ 815 pmap_is_cached(pm)) \ 816 PTE_SYNC(ptep); \ 817 } while (/*CONSTCOND*/0) 818 #else 819 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 820 #endif 821 822 /* 823 * main pv_entry manipulation functions: 824 * pmap_enter_pv: enter a mapping onto a vm_page list 825 * pmap_remove_pv: remove a mappiing from a vm_page list 826 * 827 * NOTE: pmap_enter_pv expects to lock the pvh itself 828 * pmap_remove_pv expects te caller to lock the pvh before calling 829 */ 830 831 /* 832 * pmap_enter_pv: enter a mapping onto a vm_page lst 833 * 834 * => caller should hold the proper lock on pmap_main_lock 835 * => caller should have pmap locked 836 * => we will gain the lock on the vm_page and allocate the new pv_entry 837 * => caller should adjust ptp's wire_count before calling 838 * => caller should not adjust pmap's wire_count 839 */ 840 static void 841 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 842 vaddr_t va, u_int flags) 843 { 844 struct pv_entry **pvp; 845 846 NPDEBUG(PDB_PVDUMP, 847 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 848 849 pve->pv_pmap = pm; 850 pve->pv_va = va; 851 pve->pv_flags = flags; 852 853 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 854 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 855 #ifdef PMAP_CACHE_VIPT 856 /* 857 * Insert unmanaged entries, writeable first, at the head of 858 * the pv list. 859 */ 860 if (__predict_true((flags & PVF_KENTRY) == 0)) { 861 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 862 pvp = &SLIST_NEXT(*pvp, pv_link); 863 } else if ((flags & PVF_WRITE) == 0) { 864 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 865 pvp = &SLIST_NEXT(*pvp, pv_link); 866 } 867 #endif 868 SLIST_NEXT(pve, pv_link) = *pvp; /* add to ... */ 869 *pvp = pve; /* ... locked list */ 870 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 871 #ifdef PMAP_CACHE_VIPT 872 if ((pve->pv_flags & PVF_KWRITE) == PVF_KWRITE) 873 pg->mdpage.pvh_attrs |= PVF_KMOD; 874 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 875 pg->mdpage.pvh_attrs |= PVF_DIRTY; 876 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 877 #endif 878 if (pm == pmap_kernel()) { 879 PMAPCOUNT(kernel_mappings); 880 if (flags & PVF_WRITE) 881 pg->mdpage.krw_mappings++; 882 else 883 pg->mdpage.kro_mappings++; 884 } else 885 if (flags & PVF_WRITE) 886 pg->mdpage.urw_mappings++; 887 else 888 pg->mdpage.uro_mappings++; 889 890 #ifdef PMAP_CACHE_VIPT 891 /* 892 * If this is an exec mapping and its the first exec mapping 893 * for this page, make sure to sync the I-cache. 894 */ 895 if (PV_IS_EXEC_P(flags)) { 896 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 897 pmap_syncicache_page(pg); 898 PMAPCOUNT(exec_synced_map); 899 } 900 PMAPCOUNT(exec_mappings); 901 } 902 #endif 903 904 PMAPCOUNT(mappings); 905 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 906 907 if (pve->pv_flags & PVF_WIRED) 908 ++pm->pm_stats.wired_count; 909 } 910 911 /* 912 * 913 * pmap_find_pv: Find a pv entry 914 * 915 * => caller should hold lock on vm_page 916 */ 917 static inline struct pv_entry * 918 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 919 { 920 struct pv_entry *pv; 921 922 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 923 if (pm == pv->pv_pmap && va == pv->pv_va) 924 break; 925 } 926 927 return (pv); 928 } 929 930 /* 931 * pmap_remove_pv: try to remove a mapping from a pv_list 932 * 933 * => caller should hold proper lock on pmap_main_lock 934 * => pmap should be locked 935 * => caller should hold lock on vm_page [so that attrs can be adjusted] 936 * => caller should adjust ptp's wire_count and free PTP if needed 937 * => caller should NOT adjust pmap's wire_count 938 * => we return the removed pve 939 */ 940 static struct pv_entry * 941 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 942 { 943 struct pv_entry *pve, **prevptr; 944 945 NPDEBUG(PDB_PVDUMP, 946 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 947 948 prevptr = &SLIST_FIRST(&pg->mdpage.pvh_list); /* prev pv_entry ptr */ 949 pve = *prevptr; 950 951 while (pve) { 952 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 953 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 954 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 955 if (pve->pv_flags & PVF_WIRED) { 956 if (skip_wired) 957 return (NULL); 958 --pm->pm_stats.wired_count; 959 } 960 *prevptr = SLIST_NEXT(pve, pv_link); /* remove it! */ 961 if (pm == pmap_kernel()) { 962 PMAPCOUNT(kernel_unmappings); 963 if (pve->pv_flags & PVF_WRITE) 964 pg->mdpage.krw_mappings--; 965 else 966 pg->mdpage.kro_mappings--; 967 } else 968 if (pve->pv_flags & PVF_WRITE) 969 pg->mdpage.urw_mappings--; 970 else 971 pg->mdpage.uro_mappings--; 972 973 PMAPCOUNT(unmappings); 974 #ifdef PMAP_CACHE_VIPT 975 if (!(pve->pv_flags & PVF_WRITE)) 976 break; 977 /* 978 * If this page has had an exec mapping, then if 979 * this was the last mapping, discard the contents, 980 * otherwise sync the i-cache for this page. 981 */ 982 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 983 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 984 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 985 PMAPCOUNT(exec_discarded_unmap); 986 } else { 987 pmap_syncicache_page(pg); 988 PMAPCOUNT(exec_synced_unmap); 989 } 990 } 991 #endif /* PMAP_CACHE_VIPT */ 992 break; 993 } 994 prevptr = &SLIST_NEXT(pve, pv_link); /* previous pointer */ 995 pve = *prevptr; /* advance */ 996 } 997 998 #ifdef PMAP_CACHE_VIPT 999 /* 1000 * If we no longer have a WRITEABLE KENTRY at the head of list, 1001 * clear the KMOD attribute from the page. 1002 */ 1003 if (SLIST_FIRST(&pg->mdpage.pvh_list) == NULL 1004 || (SLIST_FIRST(&pg->mdpage.pvh_list)->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1005 pg->mdpage.pvh_attrs &= ~PVF_KMOD; 1006 1007 /* 1008 * If this was a writeable page and there are no more writeable 1009 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1010 * the contents to memory. 1011 */ 1012 if (pg->mdpage.krw_mappings + pg->mdpage.urw_mappings == 0) 1013 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1014 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1015 #endif /* PMAP_CACHE_VIPT */ 1016 1017 return(pve); /* return removed pve */ 1018 } 1019 1020 /* 1021 * 1022 * pmap_modify_pv: Update pv flags 1023 * 1024 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1025 * => caller should NOT adjust pmap's wire_count 1026 * => caller must call pmap_vac_me_harder() if writable status of a page 1027 * may have changed. 1028 * => we return the old flags 1029 * 1030 * Modify a physical-virtual mapping in the pv table 1031 */ 1032 static u_int 1033 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 1034 u_int clr_mask, u_int set_mask) 1035 { 1036 struct pv_entry *npv; 1037 u_int flags, oflags; 1038 1039 KASSERT((clr_mask & PVF_KENTRY) == 0); 1040 KASSERT((set_mask & PVF_KENTRY) == 0); 1041 1042 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1043 return (0); 1044 1045 NPDEBUG(PDB_PVDUMP, 1046 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 1047 1048 /* 1049 * There is at least one VA mapping this page. 1050 */ 1051 1052 if (clr_mask & (PVF_REF | PVF_MOD)) { 1053 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1054 #ifdef PMAP_CACHE_VIPT 1055 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1056 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1057 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1058 #endif 1059 } 1060 1061 oflags = npv->pv_flags; 1062 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1063 1064 if ((flags ^ oflags) & PVF_WIRED) { 1065 if (flags & PVF_WIRED) 1066 ++pm->pm_stats.wired_count; 1067 else 1068 --pm->pm_stats.wired_count; 1069 } 1070 1071 if ((flags ^ oflags) & PVF_WRITE) { 1072 if (pm == pmap_kernel()) { 1073 if (flags & PVF_WRITE) { 1074 pg->mdpage.krw_mappings++; 1075 pg->mdpage.kro_mappings--; 1076 } else { 1077 pg->mdpage.kro_mappings++; 1078 pg->mdpage.krw_mappings--; 1079 } 1080 } else 1081 if (flags & PVF_WRITE) { 1082 pg->mdpage.urw_mappings++; 1083 pg->mdpage.uro_mappings--; 1084 } else { 1085 pg->mdpage.uro_mappings++; 1086 pg->mdpage.urw_mappings--; 1087 } 1088 } 1089 #ifdef PMAP_CACHE_VIPT 1090 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 1091 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1092 /* 1093 * We have two cases here: the first is from enter_pv (new exec 1094 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1095 * Since in latter, pmap_enter_pv won't do anything, we just have 1096 * to do what pmap_remove_pv would do. 1097 */ 1098 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1099 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1100 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1101 pmap_syncicache_page(pg); 1102 PMAPCOUNT(exec_synced_remap); 1103 } 1104 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1105 #endif 1106 1107 PMAPCOUNT(remappings); 1108 1109 return (oflags); 1110 } 1111 1112 /* 1113 * Allocate an L1 translation table for the specified pmap. 1114 * This is called at pmap creation time. 1115 */ 1116 static void 1117 pmap_alloc_l1(pmap_t pm) 1118 { 1119 struct l1_ttable *l1; 1120 u_int8_t domain; 1121 1122 /* 1123 * Remove the L1 at the head of the LRU list 1124 */ 1125 simple_lock(&l1_lru_lock); 1126 l1 = TAILQ_FIRST(&l1_lru_list); 1127 KDASSERT(l1 != NULL); 1128 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1129 1130 /* 1131 * Pick the first available domain number, and update 1132 * the link to the next number. 1133 */ 1134 domain = l1->l1_domain_first; 1135 l1->l1_domain_first = l1->l1_domain_free[domain]; 1136 1137 /* 1138 * If there are still free domain numbers in this L1, 1139 * put it back on the TAIL of the LRU list. 1140 */ 1141 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1142 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1143 1144 simple_unlock(&l1_lru_lock); 1145 1146 /* 1147 * Fix up the relevant bits in the pmap structure 1148 */ 1149 pm->pm_l1 = l1; 1150 pm->pm_domain = domain; 1151 } 1152 1153 /* 1154 * Free an L1 translation table. 1155 * This is called at pmap destruction time. 1156 */ 1157 static void 1158 pmap_free_l1(pmap_t pm) 1159 { 1160 struct l1_ttable *l1 = pm->pm_l1; 1161 1162 simple_lock(&l1_lru_lock); 1163 1164 /* 1165 * If this L1 is currently on the LRU list, remove it. 1166 */ 1167 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1168 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1169 1170 /* 1171 * Free up the domain number which was allocated to the pmap 1172 */ 1173 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1174 l1->l1_domain_first = pm->pm_domain; 1175 l1->l1_domain_use_count--; 1176 1177 /* 1178 * The L1 now must have at least 1 free domain, so add 1179 * it back to the LRU list. If the use count is zero, 1180 * put it at the head of the list, otherwise it goes 1181 * to the tail. 1182 */ 1183 if (l1->l1_domain_use_count == 0) 1184 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1185 else 1186 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1187 1188 simple_unlock(&l1_lru_lock); 1189 } 1190 1191 static inline void 1192 pmap_use_l1(pmap_t pm) 1193 { 1194 struct l1_ttable *l1; 1195 1196 /* 1197 * Do nothing if we're in interrupt context. 1198 * Access to an L1 by the kernel pmap must not affect 1199 * the LRU list. 1200 */ 1201 if (cpu_intr_p() || pm == pmap_kernel()) 1202 return; 1203 1204 l1 = pm->pm_l1; 1205 1206 /* 1207 * If the L1 is not currently on the LRU list, just return 1208 */ 1209 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1210 return; 1211 1212 simple_lock(&l1_lru_lock); 1213 1214 /* 1215 * Check the use count again, now that we've acquired the lock 1216 */ 1217 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1218 simple_unlock(&l1_lru_lock); 1219 return; 1220 } 1221 1222 /* 1223 * Move the L1 to the back of the LRU list 1224 */ 1225 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1226 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1227 1228 simple_unlock(&l1_lru_lock); 1229 } 1230 1231 /* 1232 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1233 * 1234 * Free an L2 descriptor table. 1235 */ 1236 static inline void 1237 #ifndef PMAP_INCLUDE_PTE_SYNC 1238 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1239 #else 1240 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1241 #endif 1242 { 1243 #ifdef PMAP_INCLUDE_PTE_SYNC 1244 #ifdef PMAP_CACHE_VIVT 1245 /* 1246 * Note: With a write-back cache, we may need to sync this 1247 * L2 table before re-using it. 1248 * This is because it may have belonged to a non-current 1249 * pmap, in which case the cache syncs would have been 1250 * skipped for the pages that were being unmapped. If the 1251 * L2 table were then to be immediately re-allocated to 1252 * the *current* pmap, it may well contain stale mappings 1253 * which have not yet been cleared by a cache write-back 1254 * and so would still be visible to the mmu. 1255 */ 1256 if (need_sync) 1257 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1258 #endif /* PMAP_CACHE_VIVT */ 1259 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1260 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1261 } 1262 1263 /* 1264 * Returns a pointer to the L2 bucket associated with the specified pmap 1265 * and VA, or NULL if no L2 bucket exists for the address. 1266 */ 1267 static inline struct l2_bucket * 1268 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1269 { 1270 struct l2_dtable *l2; 1271 struct l2_bucket *l2b; 1272 u_short l1idx; 1273 1274 l1idx = L1_IDX(va); 1275 1276 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1277 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1278 return (NULL); 1279 1280 return (l2b); 1281 } 1282 1283 /* 1284 * Returns a pointer to the L2 bucket associated with the specified pmap 1285 * and VA. 1286 * 1287 * If no L2 bucket exists, perform the necessary allocations to put an L2 1288 * bucket/page table in place. 1289 * 1290 * Note that if a new L2 bucket/page was allocated, the caller *must* 1291 * increment the bucket occupancy counter appropriately *before* 1292 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1293 * the bucket/page in the meantime. 1294 */ 1295 static struct l2_bucket * 1296 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1297 { 1298 struct l2_dtable *l2; 1299 struct l2_bucket *l2b; 1300 u_short l1idx; 1301 1302 l1idx = L1_IDX(va); 1303 1304 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1305 /* 1306 * No mapping at this address, as there is 1307 * no entry in the L1 table. 1308 * Need to allocate a new l2_dtable. 1309 */ 1310 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1311 return (NULL); 1312 1313 /* 1314 * Link it into the parent pmap 1315 */ 1316 pm->pm_l2[L2_IDX(l1idx)] = l2; 1317 } 1318 1319 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1320 1321 /* 1322 * Fetch pointer to the L2 page table associated with the address. 1323 */ 1324 if (l2b->l2b_kva == NULL) { 1325 pt_entry_t *ptep; 1326 1327 /* 1328 * No L2 page table has been allocated. Chances are, this 1329 * is because we just allocated the l2_dtable, above. 1330 */ 1331 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1332 /* 1333 * Oops, no more L2 page tables available at this 1334 * time. We may need to deallocate the l2_dtable 1335 * if we allocated a new one above. 1336 */ 1337 if (l2->l2_occupancy == 0) { 1338 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1339 pmap_free_l2_dtable(l2); 1340 } 1341 return (NULL); 1342 } 1343 1344 l2->l2_occupancy++; 1345 l2b->l2b_kva = ptep; 1346 l2b->l2b_l1idx = l1idx; 1347 } 1348 1349 return (l2b); 1350 } 1351 1352 /* 1353 * One or more mappings in the specified L2 descriptor table have just been 1354 * invalidated. 1355 * 1356 * Garbage collect the metadata and descriptor table itself if necessary. 1357 * 1358 * The pmap lock must be acquired when this is called (not necessary 1359 * for the kernel pmap). 1360 */ 1361 static void 1362 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1363 { 1364 struct l2_dtable *l2; 1365 pd_entry_t *pl1pd, l1pd; 1366 pt_entry_t *ptep; 1367 u_short l1idx; 1368 1369 KDASSERT(count <= l2b->l2b_occupancy); 1370 1371 /* 1372 * Update the bucket's reference count according to how many 1373 * PTEs the caller has just invalidated. 1374 */ 1375 l2b->l2b_occupancy -= count; 1376 1377 /* 1378 * Note: 1379 * 1380 * Level 2 page tables allocated to the kernel pmap are never freed 1381 * as that would require checking all Level 1 page tables and 1382 * removing any references to the Level 2 page table. See also the 1383 * comment elsewhere about never freeing bootstrap L2 descriptors. 1384 * 1385 * We make do with just invalidating the mapping in the L2 table. 1386 * 1387 * This isn't really a big deal in practice and, in fact, leads 1388 * to a performance win over time as we don't need to continually 1389 * alloc/free. 1390 */ 1391 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1392 return; 1393 1394 /* 1395 * There are no more valid mappings in this level 2 page table. 1396 * Go ahead and NULL-out the pointer in the bucket, then 1397 * free the page table. 1398 */ 1399 l1idx = l2b->l2b_l1idx; 1400 ptep = l2b->l2b_kva; 1401 l2b->l2b_kva = NULL; 1402 1403 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1404 1405 /* 1406 * If the L1 slot matches the pmap's domain 1407 * number, then invalidate it. 1408 */ 1409 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1410 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1411 *pl1pd = 0; 1412 PTE_SYNC(pl1pd); 1413 } 1414 1415 /* 1416 * Release the L2 descriptor table back to the pool cache. 1417 */ 1418 #ifndef PMAP_INCLUDE_PTE_SYNC 1419 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1420 #else 1421 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1422 #endif 1423 1424 /* 1425 * Update the reference count in the associated l2_dtable 1426 */ 1427 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1428 if (--l2->l2_occupancy > 0) 1429 return; 1430 1431 /* 1432 * There are no more valid mappings in any of the Level 1 1433 * slots managed by this l2_dtable. Go ahead and NULL-out 1434 * the pointer in the parent pmap and free the l2_dtable. 1435 */ 1436 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1437 pmap_free_l2_dtable(l2); 1438 } 1439 1440 /* 1441 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1442 * structures. 1443 */ 1444 static int 1445 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1446 { 1447 #ifndef PMAP_INCLUDE_PTE_SYNC 1448 struct l2_bucket *l2b; 1449 pt_entry_t *ptep, pte; 1450 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1451 1452 /* 1453 * The mappings for these page tables were initially made using 1454 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1455 * mode will not be right for page table mappings. To avoid 1456 * polluting the pmap_kenter_pa() code with a special case for 1457 * page tables, we simply fix up the cache-mode here if it's not 1458 * correct. 1459 */ 1460 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1461 KDASSERT(l2b != NULL); 1462 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1463 pte = *ptep; 1464 1465 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1466 /* 1467 * Page tables must have the cache-mode set to Write-Thru. 1468 */ 1469 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1470 PTE_SYNC(ptep); 1471 cpu_tlb_flushD_SE(va); 1472 cpu_cpwait(); 1473 } 1474 #endif 1475 1476 memset(v, 0, L2_TABLE_SIZE_REAL); 1477 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1478 return (0); 1479 } 1480 1481 static int 1482 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1483 { 1484 1485 memset(v, 0, sizeof(struct l2_dtable)); 1486 return (0); 1487 } 1488 1489 static int 1490 pmap_pmap_ctor(void *arg, void *v, int flags) 1491 { 1492 1493 memset(v, 0, sizeof(struct pmap)); 1494 return (0); 1495 } 1496 1497 static void 1498 pmap_pinit(pmap_t pm) 1499 { 1500 struct l2_bucket *l2b; 1501 1502 if (vector_page < KERNEL_BASE) { 1503 /* 1504 * Map the vector page. 1505 */ 1506 pmap_enter(pm, vector_page, systempage.pv_pa, 1507 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1508 pmap_update(pm); 1509 1510 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1511 l2b = pmap_get_l2_bucket(pm, vector_page); 1512 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1513 L1_C_DOM(pm->pm_domain); 1514 } else 1515 pm->pm_pl1vec = NULL; 1516 } 1517 1518 #ifdef PMAP_CACHE_VIVT 1519 /* 1520 * Since we have a virtually indexed cache, we may need to inhibit caching if 1521 * there is more than one mapping and at least one of them is writable. 1522 * Since we purge the cache on every context switch, we only need to check for 1523 * other mappings within the same pmap, or kernel_pmap. 1524 * This function is also called when a page is unmapped, to possibly reenable 1525 * caching on any remaining mappings. 1526 * 1527 * The code implements the following logic, where: 1528 * 1529 * KW = # of kernel read/write pages 1530 * KR = # of kernel read only pages 1531 * UW = # of user read/write pages 1532 * UR = # of user read only pages 1533 * 1534 * KC = kernel mapping is cacheable 1535 * UC = user mapping is cacheable 1536 * 1537 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1538 * +--------------------------------------------- 1539 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1540 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1541 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1542 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1543 */ 1544 1545 static const int pmap_vac_flags[4][4] = { 1546 {-1, 0, 0, PVF_KNC}, 1547 {0, 0, PVF_NC, PVF_NC}, 1548 {0, PVF_NC, PVF_NC, PVF_NC}, 1549 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1550 }; 1551 1552 static inline int 1553 pmap_get_vac_flags(const struct vm_page *pg) 1554 { 1555 int kidx, uidx; 1556 1557 kidx = 0; 1558 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1559 kidx |= 1; 1560 if (pg->mdpage.krw_mappings) 1561 kidx |= 2; 1562 1563 uidx = 0; 1564 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1565 uidx |= 1; 1566 if (pg->mdpage.urw_mappings) 1567 uidx |= 2; 1568 1569 return (pmap_vac_flags[uidx][kidx]); 1570 } 1571 1572 static inline void 1573 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1574 { 1575 int nattr; 1576 1577 nattr = pmap_get_vac_flags(pg); 1578 1579 if (nattr < 0) { 1580 pg->mdpage.pvh_attrs &= ~PVF_NC; 1581 return; 1582 } 1583 1584 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1585 return; 1586 1587 if (pm == pmap_kernel()) 1588 pmap_vac_me_kpmap(pg, pm, va); 1589 else 1590 pmap_vac_me_user(pg, pm, va); 1591 1592 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1593 } 1594 1595 static void 1596 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1597 { 1598 u_int u_cacheable, u_entries; 1599 struct pv_entry *pv; 1600 pmap_t last_pmap = pm; 1601 1602 /* 1603 * Pass one, see if there are both kernel and user pmaps for 1604 * this page. Calculate whether there are user-writable or 1605 * kernel-writable pages. 1606 */ 1607 u_cacheable = 0; 1608 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1609 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1610 u_cacheable++; 1611 } 1612 1613 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1614 1615 /* 1616 * We know we have just been updating a kernel entry, so if 1617 * all user pages are already cacheable, then there is nothing 1618 * further to do. 1619 */ 1620 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1621 return; 1622 1623 if (u_entries) { 1624 /* 1625 * Scan over the list again, for each entry, if it 1626 * might not be set correctly, call pmap_vac_me_user 1627 * to recalculate the settings. 1628 */ 1629 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1630 /* 1631 * We know kernel mappings will get set 1632 * correctly in other calls. We also know 1633 * that if the pmap is the same as last_pmap 1634 * then we've just handled this entry. 1635 */ 1636 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1637 continue; 1638 1639 /* 1640 * If there are kernel entries and this page 1641 * is writable but non-cacheable, then we can 1642 * skip this entry also. 1643 */ 1644 if (pg->mdpage.k_mappings && 1645 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1646 (PVF_NC | PVF_WRITE)) 1647 continue; 1648 1649 /* 1650 * Similarly if there are no kernel-writable 1651 * entries and the page is already 1652 * read-only/cacheable. 1653 */ 1654 if (pg->mdpage.krw_mappings == 0 && 1655 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1656 continue; 1657 1658 /* 1659 * For some of the remaining cases, we know 1660 * that we must recalculate, but for others we 1661 * can't tell if they are correct or not, so 1662 * we recalculate anyway. 1663 */ 1664 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1665 } 1666 1667 if (pg->mdpage.k_mappings == 0) 1668 return; 1669 } 1670 1671 pmap_vac_me_user(pg, pm, va); 1672 } 1673 1674 static void 1675 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1676 { 1677 pmap_t kpmap = pmap_kernel(); 1678 struct pv_entry *pv, *npv = NULL; 1679 struct l2_bucket *l2b; 1680 pt_entry_t *ptep, pte; 1681 u_int entries = 0; 1682 u_int writable = 0; 1683 u_int cacheable_entries = 0; 1684 u_int kern_cacheable = 0; 1685 u_int other_writable = 0; 1686 1687 /* 1688 * Count mappings and writable mappings in this pmap. 1689 * Include kernel mappings as part of our own. 1690 * Keep a pointer to the first one. 1691 */ 1692 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1693 /* Count mappings in the same pmap */ 1694 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1695 if (entries++ == 0) 1696 npv = pv; 1697 1698 /* Cacheable mappings */ 1699 if ((pv->pv_flags & PVF_NC) == 0) { 1700 cacheable_entries++; 1701 if (kpmap == pv->pv_pmap) 1702 kern_cacheable++; 1703 } 1704 1705 /* Writable mappings */ 1706 if (pv->pv_flags & PVF_WRITE) 1707 ++writable; 1708 } else 1709 if (pv->pv_flags & PVF_WRITE) 1710 other_writable = 1; 1711 } 1712 1713 /* 1714 * Enable or disable caching as necessary. 1715 * Note: the first entry might be part of the kernel pmap, 1716 * so we can't assume this is indicative of the state of the 1717 * other (maybe non-kpmap) entries. 1718 */ 1719 if ((entries > 1 && writable) || 1720 (entries > 0 && pm == kpmap && other_writable)) { 1721 if (cacheable_entries == 0) 1722 return; 1723 1724 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1725 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1726 (pv->pv_flags & PVF_NC)) 1727 continue; 1728 1729 pv->pv_flags |= PVF_NC; 1730 1731 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1732 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1733 pte = *ptep & ~L2_S_CACHE_MASK; 1734 1735 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1736 l2pte_valid(pte)) { 1737 if (PV_BEEN_EXECD(pv->pv_flags)) { 1738 #ifdef PMAP_CACHE_VIVT 1739 pmap_idcache_wbinv_range(pv->pv_pmap, 1740 pv->pv_va, PAGE_SIZE); 1741 #endif 1742 pmap_tlb_flushID_SE(pv->pv_pmap, 1743 pv->pv_va); 1744 } else 1745 if (PV_BEEN_REFD(pv->pv_flags)) { 1746 #ifdef PMAP_CACHE_VIVT 1747 pmap_dcache_wb_range(pv->pv_pmap, 1748 pv->pv_va, PAGE_SIZE, true, 1749 (pv->pv_flags & PVF_WRITE) == 0); 1750 #endif 1751 pmap_tlb_flushD_SE(pv->pv_pmap, 1752 pv->pv_va); 1753 } 1754 } 1755 1756 *ptep = pte; 1757 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1758 } 1759 cpu_cpwait(); 1760 } else 1761 if (entries > cacheable_entries) { 1762 /* 1763 * Turn cacheing back on for some pages. If it is a kernel 1764 * page, only do so if there are no other writable pages. 1765 */ 1766 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1767 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1768 (kpmap != pv->pv_pmap || other_writable))) 1769 continue; 1770 1771 pv->pv_flags &= ~PVF_NC; 1772 1773 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1774 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1775 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1776 1777 if (l2pte_valid(pte)) { 1778 if (PV_BEEN_EXECD(pv->pv_flags)) { 1779 pmap_tlb_flushID_SE(pv->pv_pmap, 1780 pv->pv_va); 1781 } else 1782 if (PV_BEEN_REFD(pv->pv_flags)) { 1783 pmap_tlb_flushD_SE(pv->pv_pmap, 1784 pv->pv_va); 1785 } 1786 } 1787 1788 *ptep = pte; 1789 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1790 } 1791 } 1792 } 1793 #endif 1794 1795 #ifdef PMAP_CACHE_VIPT 1796 /* 1797 * For virtually indexed / physically tagged caches, what we have to worry 1798 * about is illegal cache aliases. To prevent this, we must ensure that 1799 * virtual addresses that map the physical page use the same bits for those 1800 * bits masked by "arm_cache_prefer_mask" (bits 12+). If there is a conflict, 1801 * all mappings of the page must be non-cached. 1802 */ 1803 #if 0 1804 static inline vaddr_t 1805 pmap_check_sets(paddr_t pa) 1806 { 1807 extern int arm_dcache_l2_nsets; 1808 int set, way; 1809 vaddr_t mask = 0; 1810 int v; 1811 pa |= 1; 1812 for (set = 0; set < (1 << arm_dcache_l2_nsets); set++) { 1813 for (way = 0; way < 4; way++) { 1814 v = (way << 30) | (set << 5); 1815 asm("mcr p15, 3, %0, c15, c2, 0" :: "r"(v)); 1816 asm("mrc p15, 3, %0, c15, c0, 0" : "=r"(v)); 1817 1818 if ((v & (1 | ~(PAGE_SIZE-1))) == pa) { 1819 mask |= 1 << (set >> 7); 1820 } 1821 } 1822 } 1823 return mask; 1824 } 1825 #endif 1826 static void 1827 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1828 { 1829 struct pv_entry *pv; 1830 vaddr_t tst_mask; 1831 bool bad_alias; 1832 struct l2_bucket *l2b; 1833 pt_entry_t *ptep, pte, opte; 1834 const u_int 1835 rw_mappings = pg->mdpage.urw_mappings + pg->mdpage.krw_mappings, 1836 ro_mappings = pg->mdpage.uro_mappings + pg->mdpage.kro_mappings; 1837 1838 /* do we need to do anything? */ 1839 if (arm_cache_prefer_mask == 0) 1840 return; 1841 1842 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1843 pg, pm, va)); 1844 1845 #define popc4(x) \ 1846 (((0x94 >> ((x & 3) << 1)) & 3) + ((0x94 >> ((x & 12) >> 1)) & 3)) 1847 #if 0 1848 tst_mask = pmap_check_sets(pg->phys_addr); 1849 KASSERT(popc4(tst_mask) < 2); 1850 #endif 1851 1852 KASSERT(!va || pm); 1853 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1854 1855 /* Already a conflict? */ 1856 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1857 /* just an add, things are already non-cached */ 1858 KASSERT(!(pg->mdpage.pvh_attrs & PVF_DIRTY)); 1859 bad_alias = false; 1860 if (va) { 1861 PMAPCOUNT(vac_color_none); 1862 bad_alias = true; 1863 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1864 goto fixup; 1865 } 1866 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1867 /* the list can't be empty because it would be cachable */ 1868 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) { 1869 tst_mask = pg->mdpage.pvh_attrs; 1870 } else { 1871 KASSERT(pv); 1872 tst_mask = pv->pv_va; 1873 pv = SLIST_NEXT(pv, pv_link); 1874 } 1875 /* 1876 * Only check for a bad alias if we have writable mappings. 1877 */ 1878 tst_mask &= arm_cache_prefer_mask; 1879 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1880 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1881 /* if there's a bad alias, stop checking. */ 1882 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1883 bad_alias = true; 1884 } 1885 pg->mdpage.pvh_attrs |= PVF_WRITE; 1886 if (!bad_alias) 1887 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1888 } else { 1889 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1890 } 1891 /* If no conflicting colors, set everything back to cached */ 1892 if (!bad_alias) { 1893 #ifdef DEBUG 1894 if ((pg->mdpage.pvh_attrs & PVF_WRITE) 1895 || ro_mappings < 2) { 1896 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1897 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1898 } 1899 1900 #endif 1901 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1902 pg->mdpage.pvh_attrs |= tst_mask | PVF_COLORED; 1903 /* 1904 * Restore DIRTY bit if page is modified 1905 */ 1906 if (pg->mdpage.pvh_attrs & PVF_DMOD) 1907 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1908 PMAPCOUNT(vac_color_restore); 1909 } else { 1910 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1911 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1912 } 1913 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1914 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1915 } else if (!va) { 1916 KASSERT(pmap_is_page_colored_p(pg)); 1917 KASSERT(!(pg->mdpage.pvh_attrs & PVF_WRITE) 1918 || (pg->mdpage.pvh_attrs & PVF_DIRTY)); 1919 if (rw_mappings == 0) 1920 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1921 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1922 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1923 return; 1924 } else if (!pmap_is_page_colored_p(pg)) { 1925 /* not colored so we just use its color */ 1926 KASSERT(pg->mdpage.pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1927 PMAPCOUNT(vac_color_new); 1928 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1929 pg->mdpage.pvh_attrs |= PVF_COLORED 1930 | (va & arm_cache_prefer_mask) 1931 | (rw_mappings > 0 ? PVF_WRITE : 0); 1932 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1933 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1934 return; 1935 } else if (((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1936 bad_alias = false; 1937 if (rw_mappings > 0) { 1938 /* 1939 * We now have writeable mappings and more than one 1940 * readonly mapping, verify the colors don't clash 1941 * and mark the page as writeable. 1942 */ 1943 if (ro_mappings > 1 1944 && (pg->mdpage.pvh_attrs & PVF_WRITE) == 0 1945 && arm_cache_prefer_mask) { 1946 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1947 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1948 /* if there's a bad alias, stop checking. */ 1949 if (((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0) { 1950 bad_alias = true; 1951 break; 1952 } 1953 } 1954 } 1955 pg->mdpage.pvh_attrs |= PVF_WRITE; 1956 } 1957 /* If no conflicting colors, set everything back to cached */ 1958 if (!bad_alias) { 1959 #ifdef DEBUG 1960 if (rw_mappings > 0 1961 || (pg->mdpage.pvh_attrs & PMAP_KMPAGE)) { 1962 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1963 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1964 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1965 } 1966 #endif 1967 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) 1968 PMAPCOUNT(vac_color_reuse); 1969 else 1970 PMAPCOUNT(vac_color_ok); 1971 1972 /* matching color, just return */ 1973 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1974 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1975 return; 1976 } 1977 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1978 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1979 1980 /* color conflict. evict from cache. */ 1981 1982 pmap_flush_page(pg, true); 1983 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 1984 pg->mdpage.pvh_attrs |= PVF_NC; 1985 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1986 PMAPCOUNT(vac_color_erase); 1987 } else if (rw_mappings == 0 1988 && (pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 1989 KASSERT((pg->mdpage.pvh_attrs & PVF_WRITE) == 0); 1990 1991 /* 1992 * If the page has dirty cache lines, clean it. 1993 */ 1994 if (pg->mdpage.pvh_attrs & PVF_DIRTY) 1995 pmap_flush_page(pg, false); 1996 1997 /* 1998 * If this is the first remapping (we know that there are no 1999 * writeable mappings), then this is a simple color change. 2000 * Otherwise this is a seconary r/o mapping, which means 2001 * we don't have to do anything. 2002 */ 2003 if (ro_mappings == 1) { 2004 KASSERT(((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2005 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2006 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2007 PMAPCOUNT(vac_color_change); 2008 } else { 2009 PMAPCOUNT(vac_color_blind); 2010 } 2011 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2012 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2013 return; 2014 } else { 2015 if (rw_mappings > 0) 2016 pg->mdpage.pvh_attrs |= PVF_WRITE; 2017 2018 /* color conflict. evict from cache. */ 2019 pmap_flush_page(pg, true); 2020 2021 /* the list can't be empty because this was a enter/modify */ 2022 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2023 if ((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2024 KASSERT(pv); 2025 /* 2026 * If there's only one mapped page, change color to the 2027 * page's new color and return. Restore the DIRTY bit 2028 * that was erased by pmap_flush_page. 2029 */ 2030 if (SLIST_NEXT(pv, pv_link) == NULL) { 2031 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2032 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2033 if (pg->mdpage.pvh_attrs & PVF_DMOD) 2034 pg->mdpage.pvh_attrs |= PVF_DIRTY; 2035 PMAPCOUNT(vac_color_change); 2036 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2037 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2038 return; 2039 } 2040 } 2041 bad_alias = true; 2042 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2043 pg->mdpage.pvh_attrs |= PVF_NC; 2044 PMAPCOUNT(vac_color_erase); 2045 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2046 } 2047 2048 fixup: 2049 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2050 2051 /* 2052 * Turn cacheing on/off for all pages. 2053 */ 2054 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2055 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2056 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2057 opte = *ptep; 2058 pte = opte & ~L2_S_CACHE_MASK; 2059 if (bad_alias) { 2060 pv->pv_flags |= PVF_NC; 2061 } else { 2062 pv->pv_flags &= ~PVF_NC; 2063 pte |= pte_l2_s_cache_mode; 2064 } 2065 2066 if (opte == pte) /* only update is there's a change */ 2067 continue; 2068 2069 if (l2pte_valid(pte)) { 2070 if (PV_BEEN_EXECD(pv->pv_flags)) { 2071 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2072 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2073 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2074 } 2075 } 2076 2077 *ptep = pte; 2078 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2079 } 2080 } 2081 #endif /* PMAP_CACHE_VIPT */ 2082 2083 2084 /* 2085 * Modify pte bits for all ptes corresponding to the given physical address. 2086 * We use `maskbits' rather than `clearbits' because we're always passing 2087 * constants and the latter would require an extra inversion at run-time. 2088 */ 2089 static void 2090 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2091 { 2092 struct l2_bucket *l2b; 2093 struct pv_entry *pv; 2094 pt_entry_t *ptep, npte, opte; 2095 pmap_t pm; 2096 vaddr_t va; 2097 u_int oflags; 2098 #ifdef PMAP_CACHE_VIPT 2099 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 2100 bool need_syncicache = false; 2101 bool did_syncicache = false; 2102 bool need_vac_me_harder = false; 2103 #endif 2104 2105 NPDEBUG(PDB_BITS, 2106 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2107 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2108 2109 PMAP_HEAD_TO_MAP_LOCK(); 2110 simple_lock(&pg->mdpage.pvh_slock); 2111 2112 #ifdef PMAP_CACHE_VIPT 2113 /* 2114 * If we might want to sync the I-cache and we've modified it, 2115 * then we know we definitely need to sync or discard it. 2116 */ 2117 if (want_syncicache) 2118 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 2119 #endif 2120 /* 2121 * Clear saved attributes (modify, reference) 2122 */ 2123 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2124 2125 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 2126 #ifdef PMAP_CACHE_VIPT 2127 if (need_syncicache) { 2128 /* 2129 * No one has it mapped, so just discard it. The next 2130 * exec remapping will cause it to be synced. 2131 */ 2132 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2133 PMAPCOUNT(exec_discarded_clearbit); 2134 } 2135 #endif 2136 simple_unlock(&pg->mdpage.pvh_slock); 2137 PMAP_HEAD_TO_MAP_UNLOCK(); 2138 return; 2139 } 2140 2141 /* 2142 * Loop over all current mappings setting/clearing as appropos 2143 */ 2144 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2145 va = pv->pv_va; 2146 pm = pv->pv_pmap; 2147 oflags = pv->pv_flags; 2148 /* 2149 * Kernel entries are unmanaged and as such not to be changed. 2150 */ 2151 if (oflags & PVF_KENTRY) 2152 continue; 2153 pv->pv_flags &= ~maskbits; 2154 2155 pmap_acquire_pmap_lock(pm); 2156 2157 l2b = pmap_get_l2_bucket(pm, va); 2158 KDASSERT(l2b != NULL); 2159 2160 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2161 npte = opte = *ptep; 2162 2163 NPDEBUG(PDB_BITS, 2164 printf( 2165 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2166 pv, pv->pv_pmap, pv->pv_va, oflags)); 2167 2168 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2169 #ifdef PMAP_CACHE_VIVT 2170 if ((pv->pv_flags & PVF_NC)) { 2171 /* 2172 * Entry is not cacheable: 2173 * 2174 * Don't turn caching on again if this is a 2175 * modified emulation. This would be 2176 * inconsitent with the settings created by 2177 * pmap_vac_me_harder(). Otherwise, it's safe 2178 * to re-enable cacheing. 2179 * 2180 * There's no need to call pmap_vac_me_harder() 2181 * here: all pages are losing their write 2182 * permission. 2183 */ 2184 if (maskbits & PVF_WRITE) { 2185 npte |= pte_l2_s_cache_mode; 2186 pv->pv_flags &= ~PVF_NC; 2187 } 2188 } else 2189 if (opte & L2_S_PROT_W) { 2190 /* 2191 * Entry is writable/cacheable: check if pmap 2192 * is current if it is flush it, otherwise it 2193 * won't be in the cache 2194 */ 2195 if (PV_BEEN_EXECD(oflags)) 2196 pmap_idcache_wbinv_range(pm, pv->pv_va, 2197 PAGE_SIZE); 2198 else 2199 if (PV_BEEN_REFD(oflags)) 2200 pmap_dcache_wb_range(pm, pv->pv_va, 2201 PAGE_SIZE, 2202 (maskbits & PVF_REF) != 0, false); 2203 } 2204 #endif 2205 2206 /* make the pte read only */ 2207 npte &= ~L2_S_PROT_W; 2208 2209 if (maskbits & oflags & PVF_WRITE) { 2210 /* 2211 * Keep alias accounting up to date 2212 */ 2213 if (pv->pv_pmap == pmap_kernel()) { 2214 pg->mdpage.krw_mappings--; 2215 pg->mdpage.kro_mappings++; 2216 } else { 2217 pg->mdpage.urw_mappings--; 2218 pg->mdpage.uro_mappings++; 2219 } 2220 #ifdef PMAP_CACHE_VIPT 2221 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 2222 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2223 if (want_syncicache) 2224 need_syncicache = true; 2225 need_vac_me_harder = true; 2226 #endif 2227 } 2228 } 2229 2230 if (maskbits & PVF_REF) { 2231 if ((pv->pv_flags & PVF_NC) == 0 && 2232 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2233 l2pte_valid(npte)) { 2234 #ifdef PMAP_CACHE_VIVT 2235 /* 2236 * Check npte here; we may have already 2237 * done the wbinv above, and the validity 2238 * of the PTE is the same for opte and 2239 * npte. 2240 */ 2241 /* XXXJRT need idcache_inv_range */ 2242 if (PV_BEEN_EXECD(oflags)) 2243 pmap_idcache_wbinv_range(pm, 2244 pv->pv_va, PAGE_SIZE); 2245 else 2246 if (PV_BEEN_REFD(oflags)) 2247 pmap_dcache_wb_range(pm, 2248 pv->pv_va, PAGE_SIZE, 2249 true, true); 2250 #endif 2251 } 2252 2253 /* 2254 * Make the PTE invalid so that we will take a 2255 * page fault the next time the mapping is 2256 * referenced. 2257 */ 2258 npte &= ~L2_TYPE_MASK; 2259 npte |= L2_TYPE_INV; 2260 } 2261 2262 if (npte != opte) { 2263 *ptep = npte; 2264 PTE_SYNC(ptep); 2265 /* Flush the TLB entry if a current pmap. */ 2266 if (PV_BEEN_EXECD(oflags)) 2267 pmap_tlb_flushID_SE(pm, pv->pv_va); 2268 else 2269 if (PV_BEEN_REFD(oflags)) 2270 pmap_tlb_flushD_SE(pm, pv->pv_va); 2271 } 2272 2273 pmap_release_pmap_lock(pm); 2274 2275 NPDEBUG(PDB_BITS, 2276 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2277 pm, va, opte, npte)); 2278 } 2279 2280 #ifdef PMAP_CACHE_VIPT 2281 /* 2282 * If we need to sync the I-cache and we haven't done it yet, do it. 2283 */ 2284 if (need_syncicache && !did_syncicache) { 2285 pmap_syncicache_page(pg); 2286 PMAPCOUNT(exec_synced_clearbit); 2287 } 2288 /* 2289 * If we are changing this to read-only, we ned to call vac_me_harder 2290 * so we can change all the read-only pages to cacheable. We pretend 2291 * this as a page deletion. 2292 */ 2293 if (need_vac_me_harder) { 2294 if (pg->mdpage.pvh_attrs & PVF_NC) 2295 pmap_vac_me_harder(pg, NULL, 0); 2296 } 2297 #endif 2298 2299 simple_unlock(&pg->mdpage.pvh_slock); 2300 PMAP_HEAD_TO_MAP_UNLOCK(); 2301 } 2302 2303 /* 2304 * pmap_clean_page() 2305 * 2306 * This is a local function used to work out the best strategy to clean 2307 * a single page referenced by its entry in the PV table. It's used by 2308 * pmap_copy_page, pmap_zero page and maybe some others later on. 2309 * 2310 * Its policy is effectively: 2311 * o If there are no mappings, we don't bother doing anything with the cache. 2312 * o If there is one mapping, we clean just that page. 2313 * o If there are multiple mappings, we clean the entire cache. 2314 * 2315 * So that some functions can be further optimised, it returns 0 if it didn't 2316 * clean the entire cache, or 1 if it did. 2317 * 2318 * XXX One bug in this routine is that if the pv_entry has a single page 2319 * mapped at 0x00000000 a whole cache clean will be performed rather than 2320 * just the 1 page. Since this should not occur in everyday use and if it does 2321 * it will just result in not the most efficient clean for the page. 2322 */ 2323 #ifdef PMAP_CACHE_VIVT 2324 static int 2325 pmap_clean_page(struct pv_entry *pv, bool is_src) 2326 { 2327 pmap_t pm, pm_to_clean = NULL; 2328 struct pv_entry *npv; 2329 u_int cache_needs_cleaning = 0; 2330 u_int flags = 0; 2331 vaddr_t page_to_clean = 0; 2332 2333 if (pv == NULL) { 2334 /* nothing mapped in so nothing to flush */ 2335 return (0); 2336 } 2337 2338 /* 2339 * Since we flush the cache each time we change to a different 2340 * user vmspace, we only need to flush the page if it is in the 2341 * current pmap. 2342 */ 2343 pm = curproc->p_vmspace->vm_map.pmap; 2344 2345 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2346 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2347 flags |= npv->pv_flags; 2348 /* 2349 * The page is mapped non-cacheable in 2350 * this map. No need to flush the cache. 2351 */ 2352 if (npv->pv_flags & PVF_NC) { 2353 #ifdef DIAGNOSTIC 2354 if (cache_needs_cleaning) 2355 panic("pmap_clean_page: " 2356 "cache inconsistency"); 2357 #endif 2358 break; 2359 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2360 continue; 2361 if (cache_needs_cleaning) { 2362 page_to_clean = 0; 2363 break; 2364 } else { 2365 page_to_clean = npv->pv_va; 2366 pm_to_clean = npv->pv_pmap; 2367 } 2368 cache_needs_cleaning = 1; 2369 } 2370 } 2371 2372 if (page_to_clean) { 2373 if (PV_BEEN_EXECD(flags)) 2374 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2375 PAGE_SIZE); 2376 else 2377 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2378 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2379 } else if (cache_needs_cleaning) { 2380 if (PV_BEEN_EXECD(flags)) 2381 pmap_idcache_wbinv_all(pm); 2382 else 2383 pmap_dcache_wbinv_all(pm); 2384 return (1); 2385 } 2386 return (0); 2387 } 2388 #endif 2389 2390 #ifdef PMAP_CACHE_VIPT 2391 /* 2392 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2393 * right cache alias to make sure we flush the right stuff. 2394 */ 2395 void 2396 pmap_syncicache_page(struct vm_page *pg) 2397 { 2398 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2399 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2400 2401 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2402 pg, pg->mdpage.pvh_attrs)); 2403 /* 2404 * No need to clean the page if it's non-cached. 2405 */ 2406 if (pg->mdpage.pvh_attrs & PVF_NC) 2407 return; 2408 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2409 2410 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2411 /* 2412 * Set up a PTE with the right coloring to flush existing cache lines. 2413 */ 2414 *ptep = L2_S_PROTO | 2415 VM_PAGE_TO_PHYS(pg) 2416 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2417 | pte_l2_s_cache_mode; 2418 PTE_SYNC(ptep); 2419 2420 /* 2421 * Flush it. 2422 */ 2423 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2424 /* 2425 * Unmap the page. 2426 */ 2427 *ptep = 0; 2428 PTE_SYNC(ptep); 2429 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2430 2431 pg->mdpage.pvh_attrs |= PVF_EXEC; 2432 PMAPCOUNT(exec_synced); 2433 } 2434 2435 void 2436 pmap_flush_page(struct vm_page *pg, bool flush) 2437 { 2438 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2439 const size_t pte_offset = va_offset >> PGSHIFT; 2440 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2441 const pt_entry_t oldpte = *ptep; 2442 #if 0 2443 vaddr_t mask; 2444 #endif 2445 2446 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2447 #if 0 2448 mask = pmap_check_sets(pg->phys_addr); 2449 KASSERT(popc4(mask) < 2); 2450 #endif 2451 2452 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2453 pg, pg->mdpage.pvh_attrs)); 2454 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2455 /* 2456 * Set up a PTE with the right coloring to flush existing cache entries. 2457 */ 2458 *ptep = L2_S_PROTO 2459 | VM_PAGE_TO_PHYS(pg) 2460 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2461 | pte_l2_s_cache_mode; 2462 PTE_SYNC(ptep); 2463 2464 /* 2465 * Flush it. 2466 */ 2467 if (flush) { 2468 cpu_idcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 2469 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2470 } else { 2471 cpu_dcache_wb_range(cdstp + va_offset, PAGE_SIZE); 2472 /* 2473 * Mark that the page is no longer dirty. 2474 */ 2475 if ((pg->mdpage.pvh_attrs & PVF_DMOD) == 0) 2476 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2477 } 2478 2479 /* 2480 * Restore the page table entry since we might have interrupted 2481 * pmap_zero_page or pmap_copy_page which was already using this pte. 2482 */ 2483 *ptep = oldpte; 2484 PTE_SYNC(ptep); 2485 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2486 #if 0 2487 mask = pmap_check_sets(pg->phys_addr); 2488 KASSERT(mask == 0); 2489 #endif 2490 } 2491 #endif /* PMAP_CACHE_VIPT */ 2492 2493 /* 2494 * Routine: pmap_page_remove 2495 * Function: 2496 * Removes this physical page from 2497 * all physical maps in which it resides. 2498 * Reflects back modify bits to the pager. 2499 */ 2500 static void 2501 pmap_page_remove(struct vm_page *pg) 2502 { 2503 struct l2_bucket *l2b; 2504 struct pv_entry *pv, *npv, **pvp; 2505 pmap_t pm, curpm; 2506 pt_entry_t *ptep, pte; 2507 bool flush; 2508 u_int flags; 2509 2510 NPDEBUG(PDB_FOLLOW, 2511 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2512 VM_PAGE_TO_PHYS(pg))); 2513 2514 PMAP_HEAD_TO_MAP_LOCK(); 2515 simple_lock(&pg->mdpage.pvh_slock); 2516 2517 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2518 if (pv == NULL) { 2519 #ifdef PMAP_CACHE_VIPT 2520 /* 2521 * We *know* the page contents are about to be replaced. 2522 * Discard the exec contents 2523 */ 2524 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2525 PMAPCOUNT(exec_discarded_page_protect); 2526 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2527 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2528 #endif 2529 simple_unlock(&pg->mdpage.pvh_slock); 2530 PMAP_HEAD_TO_MAP_UNLOCK(); 2531 return; 2532 } 2533 #ifdef PMAP_CACHE_VIPT 2534 KASSERT(pmap_is_page_colored_p(pg)); 2535 #endif 2536 2537 /* 2538 * Clear alias counts 2539 */ 2540 #ifdef PMAP_CACHE_VIVT 2541 pg->mdpage.k_mappings = 0; 2542 #endif 2543 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2544 2545 flush = false; 2546 flags = 0; 2547 curpm = curproc->p_vmspace->vm_map.pmap; 2548 2549 #ifdef PMAP_CACHE_VIVT 2550 pmap_clean_page(pv, false); 2551 #endif 2552 2553 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 2554 while (pv) { 2555 pm = pv->pv_pmap; 2556 npv = SLIST_NEXT(pv, pv_link); 2557 if (flush == false && (pm == curpm || pm == pmap_kernel())) 2558 flush = true; 2559 2560 if (pm == pmap_kernel()) { 2561 #ifdef PMAP_CACHE_VIPT 2562 /* 2563 * If this was unmanaged mapping, it must be preserved. 2564 * Move it back on the list and advance the end-of-list 2565 * pointer. 2566 */ 2567 if (pv->pv_flags & PVF_KENTRY) { 2568 *pvp = pv; 2569 pvp = &SLIST_NEXT(pv, pv_link); 2570 pv = npv; 2571 continue; 2572 } 2573 if (pv->pv_flags & PVF_WRITE) 2574 pg->mdpage.krw_mappings--; 2575 else 2576 pg->mdpage.kro_mappings--; 2577 #endif 2578 PMAPCOUNT(kernel_unmappings); 2579 } 2580 PMAPCOUNT(unmappings); 2581 2582 pmap_acquire_pmap_lock(pm); 2583 2584 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2585 KDASSERT(l2b != NULL); 2586 2587 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2588 pte = *ptep; 2589 2590 /* 2591 * Update statistics 2592 */ 2593 --pm->pm_stats.resident_count; 2594 2595 /* Wired bit */ 2596 if (pv->pv_flags & PVF_WIRED) 2597 --pm->pm_stats.wired_count; 2598 2599 flags |= pv->pv_flags; 2600 2601 /* 2602 * Invalidate the PTEs. 2603 */ 2604 *ptep = 0; 2605 PTE_SYNC_CURRENT(pm, ptep); 2606 pmap_free_l2_bucket(pm, l2b, 1); 2607 2608 pool_put(&pmap_pv_pool, pv); 2609 pv = npv; 2610 /* 2611 * if we reach the end of the list and there are still 2612 * mappings, they might be able to be cached now. 2613 */ 2614 if (pv == NULL) { 2615 *pvp = NULL; 2616 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 2617 pmap_vac_me_harder(pg, pm, 0); 2618 } 2619 pmap_release_pmap_lock(pm); 2620 } 2621 #ifdef PMAP_CACHE_VIPT 2622 /* 2623 * Its EXEC cache is now gone. 2624 */ 2625 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2626 PMAPCOUNT(exec_discarded_page_protect); 2627 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2628 KASSERT(pg->mdpage.urw_mappings == 0); 2629 KASSERT(pg->mdpage.uro_mappings == 0); 2630 if (pg->mdpage.krw_mappings == 0) 2631 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2632 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2633 #endif 2634 simple_unlock(&pg->mdpage.pvh_slock); 2635 PMAP_HEAD_TO_MAP_UNLOCK(); 2636 2637 if (flush) { 2638 /* 2639 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2640 * would need a subsequent call to pmap_update() to ensure 2641 * curpm->pm_cstate.cs_all is reset. Our callers are not 2642 * required to do that (see pmap(9)), so we can't modify 2643 * the current pmap's state. 2644 */ 2645 if (PV_BEEN_EXECD(flags)) 2646 cpu_tlb_flushID(); 2647 else 2648 cpu_tlb_flushD(); 2649 } 2650 cpu_cpwait(); 2651 } 2652 2653 /* 2654 * pmap_t pmap_create(void) 2655 * 2656 * Create a new pmap structure from scratch. 2657 */ 2658 pmap_t 2659 pmap_create(void) 2660 { 2661 pmap_t pm; 2662 2663 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2664 2665 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2666 pm->pm_stats.wired_count = 0; 2667 pm->pm_stats.resident_count = 1; 2668 pm->pm_cstate.cs_all = 0; 2669 pmap_alloc_l1(pm); 2670 2671 /* 2672 * Note: The pool cache ensures that the pm_l2[] array is already 2673 * initialised to zero. 2674 */ 2675 2676 pmap_pinit(pm); 2677 2678 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2679 2680 return (pm); 2681 } 2682 2683 /* 2684 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2685 * int flags) 2686 * 2687 * Insert the given physical page (p) at 2688 * the specified virtual address (v) in the 2689 * target physical map with the protection requested. 2690 * 2691 * NB: This is the only routine which MAY NOT lazy-evaluate 2692 * or lose information. That is, this routine must actually 2693 * insert this page into the given map NOW. 2694 */ 2695 int 2696 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 2697 { 2698 struct l2_bucket *l2b; 2699 struct vm_page *pg, *opg; 2700 struct pv_entry *pve; 2701 pt_entry_t *ptep, npte, opte; 2702 u_int nflags; 2703 u_int oflags; 2704 2705 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2706 2707 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2708 KDASSERT(((va | pa) & PGOFSET) == 0); 2709 2710 /* 2711 * Get a pointer to the page. Later on in this function, we 2712 * test for a managed page by checking pg != NULL. 2713 */ 2714 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2715 2716 nflags = 0; 2717 if (prot & VM_PROT_WRITE) 2718 nflags |= PVF_WRITE; 2719 if (prot & VM_PROT_EXECUTE) 2720 nflags |= PVF_EXEC; 2721 if (flags & PMAP_WIRED) 2722 nflags |= PVF_WIRED; 2723 2724 PMAP_MAP_TO_HEAD_LOCK(); 2725 pmap_acquire_pmap_lock(pm); 2726 2727 /* 2728 * Fetch the L2 bucket which maps this page, allocating one if 2729 * necessary for user pmaps. 2730 */ 2731 if (pm == pmap_kernel()) 2732 l2b = pmap_get_l2_bucket(pm, va); 2733 else 2734 l2b = pmap_alloc_l2_bucket(pm, va); 2735 if (l2b == NULL) { 2736 if (flags & PMAP_CANFAIL) { 2737 pmap_release_pmap_lock(pm); 2738 PMAP_MAP_TO_HEAD_UNLOCK(); 2739 return (ENOMEM); 2740 } 2741 panic("pmap_enter: failed to allocate L2 bucket"); 2742 } 2743 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2744 opte = *ptep; 2745 npte = pa; 2746 oflags = 0; 2747 2748 if (opte) { 2749 /* 2750 * There is already a mapping at this address. 2751 * If the physical address is different, lookup the 2752 * vm_page. 2753 */ 2754 if (l2pte_pa(opte) != pa) 2755 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2756 else 2757 opg = pg; 2758 } else 2759 opg = NULL; 2760 2761 if (pg) { 2762 /* 2763 * This is to be a managed mapping. 2764 */ 2765 if ((flags & VM_PROT_ALL) || 2766 (pg->mdpage.pvh_attrs & PVF_REF)) { 2767 /* 2768 * - The access type indicates that we don't need 2769 * to do referenced emulation. 2770 * OR 2771 * - The physical page has already been referenced 2772 * so no need to re-do referenced emulation here. 2773 */ 2774 npte |= L2_S_PROTO; 2775 2776 nflags |= PVF_REF; 2777 2778 if ((prot & VM_PROT_WRITE) != 0 && 2779 ((flags & VM_PROT_WRITE) != 0 || 2780 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2781 /* 2782 * This is a writable mapping, and the 2783 * page's mod state indicates it has 2784 * already been modified. Make it 2785 * writable from the outset. 2786 */ 2787 npte |= L2_S_PROT_W; 2788 nflags |= PVF_MOD; 2789 } 2790 } else { 2791 /* 2792 * Need to do page referenced emulation. 2793 */ 2794 npte |= L2_TYPE_INV; 2795 } 2796 2797 npte |= pte_l2_s_cache_mode; 2798 2799 if (pg == opg) { 2800 /* 2801 * We're changing the attrs of an existing mapping. 2802 */ 2803 simple_lock(&pg->mdpage.pvh_slock); 2804 oflags = pmap_modify_pv(pg, pm, va, 2805 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2806 PVF_MOD | PVF_REF, nflags); 2807 simple_unlock(&pg->mdpage.pvh_slock); 2808 2809 #ifdef PMAP_CACHE_VIVT 2810 /* 2811 * We may need to flush the cache if we're 2812 * doing rw-ro... 2813 */ 2814 if (pm->pm_cstate.cs_cache_d && 2815 (oflags & PVF_NC) == 0 && 2816 (opte & L2_S_PROT_W) != 0 && 2817 (prot & VM_PROT_WRITE) == 0) 2818 cpu_dcache_wb_range(va, PAGE_SIZE); 2819 #endif 2820 } else { 2821 /* 2822 * New mapping, or changing the backing page 2823 * of an existing mapping. 2824 */ 2825 if (opg) { 2826 /* 2827 * Replacing an existing mapping with a new one. 2828 * It is part of our managed memory so we 2829 * must remove it from the PV list 2830 */ 2831 simple_lock(&opg->mdpage.pvh_slock); 2832 pve = pmap_remove_pv(opg, pm, va, 0); 2833 pmap_vac_me_harder(opg, pm, 0); 2834 simple_unlock(&opg->mdpage.pvh_slock); 2835 oflags = pve->pv_flags; 2836 2837 #ifdef PMAP_CACHE_VIVT 2838 /* 2839 * If the old mapping was valid (ref/mod 2840 * emulation creates 'invalid' mappings 2841 * initially) then make sure to frob 2842 * the cache. 2843 */ 2844 if ((oflags & PVF_NC) == 0 && 2845 l2pte_valid(opte)) { 2846 if (PV_BEEN_EXECD(oflags)) { 2847 pmap_idcache_wbinv_range(pm, va, 2848 PAGE_SIZE); 2849 } else 2850 if (PV_BEEN_REFD(oflags)) { 2851 pmap_dcache_wb_range(pm, va, 2852 PAGE_SIZE, true, 2853 (oflags & PVF_WRITE) == 0); 2854 } 2855 } 2856 #endif 2857 } else 2858 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2859 if ((flags & PMAP_CANFAIL) == 0) 2860 panic("pmap_enter: no pv entries"); 2861 2862 if (pm != pmap_kernel()) 2863 pmap_free_l2_bucket(pm, l2b, 0); 2864 pmap_release_pmap_lock(pm); 2865 PMAP_MAP_TO_HEAD_UNLOCK(); 2866 NPDEBUG(PDB_ENTER, 2867 printf("pmap_enter: ENOMEM\n")); 2868 return (ENOMEM); 2869 } 2870 2871 pmap_enter_pv(pg, pve, pm, va, nflags); 2872 } 2873 } else { 2874 /* 2875 * We're mapping an unmanaged page. 2876 * These are always readable, and possibly writable, from 2877 * the get go as we don't need to track ref/mod status. 2878 */ 2879 npte |= L2_S_PROTO; 2880 if (prot & VM_PROT_WRITE) 2881 npte |= L2_S_PROT_W; 2882 2883 /* 2884 * Make sure the vector table is mapped cacheable 2885 */ 2886 if (pm != pmap_kernel() && va == vector_page) 2887 npte |= pte_l2_s_cache_mode; 2888 2889 if (opg) { 2890 /* 2891 * Looks like there's an existing 'managed' mapping 2892 * at this address. 2893 */ 2894 simple_lock(&opg->mdpage.pvh_slock); 2895 pve = pmap_remove_pv(opg, pm, va, 0); 2896 pmap_vac_me_harder(opg, pm, 0); 2897 simple_unlock(&opg->mdpage.pvh_slock); 2898 oflags = pve->pv_flags; 2899 2900 #ifdef PMAP_CACHE_VIVT 2901 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2902 if (PV_BEEN_EXECD(oflags)) 2903 pmap_idcache_wbinv_range(pm, va, 2904 PAGE_SIZE); 2905 else 2906 if (PV_BEEN_REFD(oflags)) 2907 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2908 true, (oflags & PVF_WRITE) == 0); 2909 } 2910 #endif 2911 pool_put(&pmap_pv_pool, pve); 2912 } 2913 } 2914 2915 /* 2916 * Make sure userland mappings get the right permissions 2917 */ 2918 if (pm != pmap_kernel() && va != vector_page) 2919 npte |= L2_S_PROT_U; 2920 2921 /* 2922 * Keep the stats up to date 2923 */ 2924 if (opte == 0) { 2925 l2b->l2b_occupancy++; 2926 pm->pm_stats.resident_count++; 2927 } 2928 2929 NPDEBUG(PDB_ENTER, 2930 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2931 2932 /* 2933 * If this is just a wiring change, the two PTEs will be 2934 * identical, so there's no need to update the page table. 2935 */ 2936 if (npte != opte) { 2937 bool is_cached = pmap_is_cached(pm); 2938 2939 *ptep = npte; 2940 if (is_cached) { 2941 /* 2942 * We only need to frob the cache/tlb if this pmap 2943 * is current 2944 */ 2945 PTE_SYNC(ptep); 2946 if (va != vector_page && l2pte_valid(npte)) { 2947 /* 2948 * This mapping is likely to be accessed as 2949 * soon as we return to userland. Fix up the 2950 * L1 entry to avoid taking another 2951 * page/domain fault. 2952 */ 2953 pd_entry_t *pl1pd, l1pd; 2954 2955 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2956 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2957 L1_C_PROTO; 2958 if (*pl1pd != l1pd) { 2959 *pl1pd = l1pd; 2960 PTE_SYNC(pl1pd); 2961 } 2962 } 2963 } 2964 2965 if (PV_BEEN_EXECD(oflags)) 2966 pmap_tlb_flushID_SE(pm, va); 2967 else 2968 if (PV_BEEN_REFD(oflags)) 2969 pmap_tlb_flushD_SE(pm, va); 2970 2971 NPDEBUG(PDB_ENTER, 2972 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2973 is_cached, pm->pm_cstate.cs_all)); 2974 2975 if (pg != NULL) { 2976 simple_lock(&pg->mdpage.pvh_slock); 2977 pmap_vac_me_harder(pg, pm, va); 2978 simple_unlock(&pg->mdpage.pvh_slock); 2979 } 2980 } 2981 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 2982 simple_lock(&pg->mdpage.pvh_slock); 2983 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2984 KASSERT(((pg->mdpage.pvh_attrs & PVF_WRITE) == 0) == (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0)); 2985 simple_unlock(&pg->mdpage.pvh_slock); 2986 #endif 2987 2988 pmap_release_pmap_lock(pm); 2989 PMAP_MAP_TO_HEAD_UNLOCK(); 2990 2991 return (0); 2992 } 2993 2994 /* 2995 * pmap_remove() 2996 * 2997 * pmap_remove is responsible for nuking a number of mappings for a range 2998 * of virtual address space in the current pmap. To do this efficiently 2999 * is interesting, because in a number of cases a wide virtual address 3000 * range may be supplied that contains few actual mappings. So, the 3001 * optimisations are: 3002 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3003 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3004 * maybe do just a partial cache clean. This path of execution is 3005 * complicated by the fact that the cache must be flushed _before_ 3006 * the PTE is nuked, being a VAC :-) 3007 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3008 * all invalidations until pmap_update(), since pmap_remove_all() has 3009 * already flushed the cache. 3010 * 4. Maybe later fast-case a single page, but I don't think this is 3011 * going to make _that_ much difference overall. 3012 */ 3013 3014 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3015 3016 void 3017 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 3018 { 3019 struct l2_bucket *l2b; 3020 vaddr_t next_bucket; 3021 pt_entry_t *ptep; 3022 u_int cleanlist_idx, total, cnt; 3023 struct { 3024 vaddr_t va; 3025 pt_entry_t *ptep; 3026 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3027 u_int mappings, is_exec, is_refd; 3028 3029 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3030 "eva=%08lx\n", pm, sva, eva)); 3031 3032 /* 3033 * we lock in the pmap => pv_head direction 3034 */ 3035 PMAP_MAP_TO_HEAD_LOCK(); 3036 pmap_acquire_pmap_lock(pm); 3037 3038 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3039 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3040 if (pm->pm_cstate.cs_tlb == 0) 3041 pm->pm_remove_all = true; 3042 } else 3043 cleanlist_idx = 0; 3044 3045 total = 0; 3046 3047 while (sva < eva) { 3048 /* 3049 * Do one L2 bucket's worth at a time. 3050 */ 3051 next_bucket = L2_NEXT_BUCKET(sva); 3052 if (next_bucket > eva) 3053 next_bucket = eva; 3054 3055 l2b = pmap_get_l2_bucket(pm, sva); 3056 if (l2b == NULL) { 3057 sva = next_bucket; 3058 continue; 3059 } 3060 3061 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3062 3063 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3064 struct vm_page *pg; 3065 pt_entry_t pte; 3066 paddr_t pa; 3067 3068 pte = *ptep; 3069 3070 if (pte == 0) { 3071 /* Nothing here, move along */ 3072 continue; 3073 } 3074 3075 pa = l2pte_pa(pte); 3076 is_exec = 0; 3077 is_refd = 1; 3078 3079 /* 3080 * Update flags. In a number of circumstances, 3081 * we could cluster a lot of these and do a 3082 * number of sequential pages in one go. 3083 */ 3084 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3085 struct pv_entry *pve; 3086 simple_lock(&pg->mdpage.pvh_slock); 3087 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 3088 pmap_vac_me_harder(pg, pm, 0); 3089 simple_unlock(&pg->mdpage.pvh_slock); 3090 if (pve != NULL) { 3091 if (pm->pm_remove_all == false) { 3092 is_exec = 3093 PV_BEEN_EXECD(pve->pv_flags); 3094 is_refd = 3095 PV_BEEN_REFD(pve->pv_flags); 3096 } 3097 pool_put(&pmap_pv_pool, pve); 3098 } else 3099 if (skip_wired) { 3100 /* The mapping is wired. Skip it */ 3101 continue; 3102 } 3103 } else 3104 if (skip_wired) { 3105 /* Unmanaged pages are always wired. */ 3106 continue; 3107 } 3108 3109 mappings++; 3110 3111 if (!l2pte_valid(pte)) { 3112 /* 3113 * Ref/Mod emulation is still active for this 3114 * mapping, therefore it is has not yet been 3115 * accessed. No need to frob the cache/tlb. 3116 */ 3117 *ptep = 0; 3118 PTE_SYNC_CURRENT(pm, ptep); 3119 continue; 3120 } 3121 3122 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3123 /* Add to the clean list. */ 3124 cleanlist[cleanlist_idx].ptep = ptep; 3125 cleanlist[cleanlist_idx].va = 3126 sva | (is_exec & 1); 3127 cleanlist_idx++; 3128 } else 3129 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3130 /* Nuke everything if needed. */ 3131 #ifdef PMAP_CACHE_VIVT 3132 pmap_idcache_wbinv_all(pm); 3133 #endif 3134 pmap_tlb_flushID(pm); 3135 3136 /* 3137 * Roll back the previous PTE list, 3138 * and zero out the current PTE. 3139 */ 3140 for (cnt = 0; 3141 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3142 *cleanlist[cnt].ptep = 0; 3143 PTE_SYNC(cleanlist[cnt].ptep); 3144 } 3145 *ptep = 0; 3146 PTE_SYNC(ptep); 3147 cleanlist_idx++; 3148 pm->pm_remove_all = true; 3149 } else { 3150 *ptep = 0; 3151 PTE_SYNC(ptep); 3152 if (pm->pm_remove_all == false) { 3153 if (is_exec) 3154 pmap_tlb_flushID_SE(pm, sva); 3155 else 3156 if (is_refd) 3157 pmap_tlb_flushD_SE(pm, sva); 3158 } 3159 } 3160 } 3161 3162 /* 3163 * Deal with any left overs 3164 */ 3165 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3166 total += cleanlist_idx; 3167 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3168 if (pm->pm_cstate.cs_all != 0) { 3169 vaddr_t clva = cleanlist[cnt].va & ~1; 3170 if (cleanlist[cnt].va & 1) { 3171 #ifdef PMAP_CACHE_VIVT 3172 pmap_idcache_wbinv_range(pm, 3173 clva, PAGE_SIZE); 3174 #endif 3175 pmap_tlb_flushID_SE(pm, clva); 3176 } else { 3177 #ifdef PMAP_CACHE_VIVT 3178 pmap_dcache_wb_range(pm, 3179 clva, PAGE_SIZE, true, 3180 false); 3181 #endif 3182 pmap_tlb_flushD_SE(pm, clva); 3183 } 3184 } 3185 *cleanlist[cnt].ptep = 0; 3186 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3187 } 3188 3189 /* 3190 * If it looks like we're removing a whole bunch 3191 * of mappings, it's faster to just write-back 3192 * the whole cache now and defer TLB flushes until 3193 * pmap_update() is called. 3194 */ 3195 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3196 cleanlist_idx = 0; 3197 else { 3198 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3199 #ifdef PMAP_CACHE_VIVT 3200 pmap_idcache_wbinv_all(pm); 3201 #endif 3202 pm->pm_remove_all = true; 3203 } 3204 } 3205 3206 pmap_free_l2_bucket(pm, l2b, mappings); 3207 pm->pm_stats.resident_count -= mappings; 3208 } 3209 3210 pmap_release_pmap_lock(pm); 3211 PMAP_MAP_TO_HEAD_UNLOCK(); 3212 } 3213 3214 #ifdef PMAP_CACHE_VIPT 3215 static struct pv_entry * 3216 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3217 { 3218 struct pv_entry *pv; 3219 3220 simple_lock(&pg->mdpage.pvh_slock); 3221 KASSERT(pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 3222 KASSERT((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3223 3224 pv = pmap_remove_pv(pg, pmap_kernel(), va, false); 3225 KASSERT(pv); 3226 KASSERT(pv->pv_flags & PVF_KENTRY); 3227 3228 /* 3229 * If we are removing a writeable mapping to a cached exec page, 3230 * if it's the last mapping then clear it execness other sync 3231 * the page to the icache. 3232 */ 3233 if ((pg->mdpage.pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3234 && (pv->pv_flags & PVF_WRITE) != 0) { 3235 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 3236 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 3237 PMAPCOUNT(exec_discarded_kremove); 3238 } else { 3239 pmap_syncicache_page(pg); 3240 PMAPCOUNT(exec_synced_kremove); 3241 } 3242 } 3243 pmap_vac_me_harder(pg, pmap_kernel(), 0); 3244 simple_unlock(&pg->mdpage.pvh_slock); 3245 3246 return pv; 3247 } 3248 #endif /* PMAP_CACHE_VIPT */ 3249 3250 /* 3251 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3252 * 3253 * We assume there is already sufficient KVM space available 3254 * to do this, as we can't allocate L2 descriptor tables/metadata 3255 * from here. 3256 */ 3257 void 3258 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 3259 { 3260 struct l2_bucket *l2b; 3261 pt_entry_t *ptep, opte; 3262 #ifdef PMAP_CACHE_VIPT 3263 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3264 struct vm_page *opg; 3265 struct pv_entry *pv = NULL; 3266 #endif 3267 3268 NPDEBUG(PDB_KENTER, 3269 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3270 va, pa, prot)); 3271 3272 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3273 KDASSERT(l2b != NULL); 3274 3275 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3276 opte = *ptep; 3277 3278 if (opte == 0) { 3279 PMAPCOUNT(kenter_mappings); 3280 l2b->l2b_occupancy++; 3281 } else { 3282 PMAPCOUNT(kenter_remappings); 3283 #ifdef PMAP_CACHE_VIPT 3284 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3285 if (opg) { 3286 KASSERT(opg != pg); 3287 KASSERT((opg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3288 KASSERT((prot & PMAP_KMPAGE) == 0); 3289 simple_lock(&opg->mdpage.pvh_slock); 3290 pv = pmap_kremove_pg(opg, va); 3291 simple_unlock(&opg->mdpage.pvh_slock); 3292 } 3293 #endif 3294 if (l2pte_valid(opte)) { 3295 #ifdef PMAP_CACHE_VIVT 3296 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3297 #endif 3298 cpu_tlb_flushD_SE(va); 3299 cpu_cpwait(); 3300 } 3301 } 3302 3303 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3304 pte_l2_s_cache_mode; 3305 PTE_SYNC(ptep); 3306 3307 #ifdef PMAP_CACHE_VIPT 3308 if (pg) { 3309 if (prot & PMAP_KMPAGE) { 3310 KASSERT(pv == NULL); 3311 KASSERT((va & PVF_COLORED) == 0); 3312 simple_lock(&pg->mdpage.pvh_slock); 3313 KASSERT(pg->mdpage.urw_mappings == 0); 3314 KASSERT(pg->mdpage.uro_mappings == 0); 3315 KASSERT(pg->mdpage.krw_mappings == 0); 3316 KASSERT(pg->mdpage.kro_mappings == 0); 3317 KASSERT((pg->mdpage.pvh_attrs & PVF_NC) == 0); 3318 /* if there is a color conflict, evict from cache. */ 3319 if (pmap_is_page_colored_p(pg) 3320 && ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask)) { 3321 PMAPCOUNT(vac_color_change); 3322 pmap_flush_page(pg, true); 3323 } 3324 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 3325 pg->mdpage.pvh_attrs |= PVF_KMPAGE 3326 | PVF_COLORED | PVF_DIRTY 3327 | (va & arm_cache_prefer_mask); 3328 simple_unlock(&pg->mdpage.pvh_slock); 3329 } else { 3330 if (pv == NULL) { 3331 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3332 KASSERT(pv != NULL); 3333 } 3334 pmap_enter_pv(pg, pv, pmap_kernel(), va, 3335 PVF_WIRED | PVF_KENTRY 3336 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3337 if ((prot & VM_PROT_WRITE) 3338 && !(pg->mdpage.pvh_attrs & PVF_NC)) 3339 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3340 KASSERT((prot & VM_PROT_WRITE) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3341 simple_lock(&pg->mdpage.pvh_slock); 3342 pmap_vac_me_harder(pg, pmap_kernel(), va); 3343 simple_unlock(&pg->mdpage.pvh_slock); 3344 } 3345 } else { 3346 if (pv != NULL) 3347 pool_put(&pmap_pv_pool, pv); 3348 } 3349 #endif 3350 } 3351 3352 void 3353 pmap_kremove(vaddr_t va, vsize_t len) 3354 { 3355 struct l2_bucket *l2b; 3356 pt_entry_t *ptep, *sptep, opte; 3357 vaddr_t next_bucket, eva; 3358 u_int mappings; 3359 #ifdef PMAP_CACHE_VIPT 3360 struct vm_page *opg; 3361 #endif 3362 3363 PMAPCOUNT(kenter_unmappings); 3364 3365 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3366 va, len)); 3367 3368 eva = va + len; 3369 3370 while (va < eva) { 3371 next_bucket = L2_NEXT_BUCKET(va); 3372 if (next_bucket > eva) 3373 next_bucket = eva; 3374 3375 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3376 KDASSERT(l2b != NULL); 3377 3378 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3379 mappings = 0; 3380 3381 while (va < next_bucket) { 3382 opte = *ptep; 3383 #ifdef PMAP_CACHE_VIPT 3384 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3385 if (opg) { 3386 if (opg->mdpage.pvh_attrs & PVF_KMPAGE) { 3387 simple_lock(&opg->mdpage.pvh_slock); 3388 KASSERT(opg->mdpage.urw_mappings == 0); 3389 KASSERT(opg->mdpage.uro_mappings == 0); 3390 KASSERT(opg->mdpage.krw_mappings == 0); 3391 KASSERT(opg->mdpage.kro_mappings == 0); 3392 opg->mdpage.pvh_attrs &= 3393 ~(PVF_KMPAGE|PVF_WRITE); 3394 simple_unlock(&opg->mdpage.pvh_slock); 3395 } else { 3396 pool_put(&pmap_pv_pool, 3397 pmap_kremove_pg(opg, va)); 3398 } 3399 } 3400 #endif 3401 if (l2pte_valid(opte)) { 3402 #ifdef PMAP_CACHE_VIVT 3403 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3404 #endif 3405 cpu_tlb_flushD_SE(va); 3406 } 3407 if (opte) { 3408 *ptep = 0; 3409 mappings++; 3410 } 3411 va += PAGE_SIZE; 3412 ptep++; 3413 } 3414 KDASSERT(mappings <= l2b->l2b_occupancy); 3415 l2b->l2b_occupancy -= mappings; 3416 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3417 } 3418 cpu_cpwait(); 3419 } 3420 3421 bool 3422 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3423 { 3424 struct l2_dtable *l2; 3425 pd_entry_t *pl1pd, l1pd; 3426 pt_entry_t *ptep, pte; 3427 paddr_t pa; 3428 u_int l1idx; 3429 3430 pmap_acquire_pmap_lock(pm); 3431 3432 l1idx = L1_IDX(va); 3433 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3434 l1pd = *pl1pd; 3435 3436 if (l1pte_section_p(l1pd)) { 3437 /* 3438 * These should only happen for pmap_kernel() 3439 */ 3440 KDASSERT(pm == pmap_kernel()); 3441 pmap_release_pmap_lock(pm); 3442 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3443 } else { 3444 /* 3445 * Note that we can't rely on the validity of the L1 3446 * descriptor as an indication that a mapping exists. 3447 * We have to look it up in the L2 dtable. 3448 */ 3449 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3450 3451 if (l2 == NULL || 3452 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3453 pmap_release_pmap_lock(pm); 3454 return false; 3455 } 3456 3457 ptep = &ptep[l2pte_index(va)]; 3458 pte = *ptep; 3459 pmap_release_pmap_lock(pm); 3460 3461 if (pte == 0) 3462 return false; 3463 3464 switch (pte & L2_TYPE_MASK) { 3465 case L2_TYPE_L: 3466 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3467 break; 3468 3469 default: 3470 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3471 break; 3472 } 3473 } 3474 3475 if (pap != NULL) 3476 *pap = pa; 3477 3478 return true; 3479 } 3480 3481 void 3482 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3483 { 3484 struct l2_bucket *l2b; 3485 pt_entry_t *ptep, pte; 3486 vaddr_t next_bucket; 3487 u_int flags; 3488 u_int clr_mask; 3489 int flush; 3490 3491 NPDEBUG(PDB_PROTECT, 3492 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3493 pm, sva, eva, prot)); 3494 3495 if ((prot & VM_PROT_READ) == 0) { 3496 pmap_remove(pm, sva, eva); 3497 return; 3498 } 3499 3500 if (prot & VM_PROT_WRITE) { 3501 /* 3502 * If this is a read->write transition, just ignore it and let 3503 * uvm_fault() take care of it later. 3504 */ 3505 return; 3506 } 3507 3508 PMAP_MAP_TO_HEAD_LOCK(); 3509 pmap_acquire_pmap_lock(pm); 3510 3511 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3512 flags = 0; 3513 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3514 3515 while (sva < eva) { 3516 next_bucket = L2_NEXT_BUCKET(sva); 3517 if (next_bucket > eva) 3518 next_bucket = eva; 3519 3520 l2b = pmap_get_l2_bucket(pm, sva); 3521 if (l2b == NULL) { 3522 sva = next_bucket; 3523 continue; 3524 } 3525 3526 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3527 3528 while (sva < next_bucket) { 3529 pte = *ptep; 3530 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3531 struct vm_page *pg; 3532 u_int f; 3533 3534 #ifdef PMAP_CACHE_VIVT 3535 /* 3536 * OK, at this point, we know we're doing 3537 * write-protect operation. If the pmap is 3538 * active, write-back the page. 3539 */ 3540 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3541 false, false); 3542 #endif 3543 3544 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3545 pte &= ~L2_S_PROT_W; 3546 *ptep = pte; 3547 PTE_SYNC(ptep); 3548 3549 if (pg != NULL) { 3550 simple_lock(&pg->mdpage.pvh_slock); 3551 f = pmap_modify_pv(pg, pm, sva, 3552 clr_mask, 0); 3553 pmap_vac_me_harder(pg, pm, sva); 3554 simple_unlock(&pg->mdpage.pvh_slock); 3555 } else 3556 f = PVF_REF | PVF_EXEC; 3557 3558 if (flush >= 0) { 3559 flush++; 3560 flags |= f; 3561 } else 3562 if (PV_BEEN_EXECD(f)) 3563 pmap_tlb_flushID_SE(pm, sva); 3564 else 3565 if (PV_BEEN_REFD(f)) 3566 pmap_tlb_flushD_SE(pm, sva); 3567 } 3568 3569 sva += PAGE_SIZE; 3570 ptep++; 3571 } 3572 } 3573 3574 pmap_release_pmap_lock(pm); 3575 PMAP_MAP_TO_HEAD_UNLOCK(); 3576 3577 if (flush) { 3578 if (PV_BEEN_EXECD(flags)) 3579 pmap_tlb_flushID(pm); 3580 else 3581 if (PV_BEEN_REFD(flags)) 3582 pmap_tlb_flushD(pm); 3583 } 3584 } 3585 3586 void 3587 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3588 { 3589 struct l2_bucket *l2b; 3590 pt_entry_t *ptep; 3591 vaddr_t next_bucket; 3592 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3593 3594 NPDEBUG(PDB_EXEC, 3595 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3596 pm, sva, eva)); 3597 3598 PMAP_MAP_TO_HEAD_LOCK(); 3599 pmap_acquire_pmap_lock(pm); 3600 3601 while (sva < eva) { 3602 next_bucket = L2_NEXT_BUCKET(sva); 3603 if (next_bucket > eva) 3604 next_bucket = eva; 3605 3606 l2b = pmap_get_l2_bucket(pm, sva); 3607 if (l2b == NULL) { 3608 sva = next_bucket; 3609 continue; 3610 } 3611 3612 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3613 sva < next_bucket; 3614 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3615 if (l2pte_valid(*ptep)) { 3616 cpu_icache_sync_range(sva, 3617 min(page_size, eva - sva)); 3618 } 3619 } 3620 } 3621 3622 pmap_release_pmap_lock(pm); 3623 PMAP_MAP_TO_HEAD_UNLOCK(); 3624 } 3625 3626 void 3627 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3628 { 3629 3630 NPDEBUG(PDB_PROTECT, 3631 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3632 pg, VM_PAGE_TO_PHYS(pg), prot)); 3633 3634 switch(prot) { 3635 return; 3636 case VM_PROT_READ|VM_PROT_WRITE: 3637 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3638 pmap_clearbit(pg, PVF_EXEC); 3639 break; 3640 #endif 3641 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3642 break; 3643 3644 case VM_PROT_READ: 3645 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3646 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3647 break; 3648 #endif 3649 case VM_PROT_READ|VM_PROT_EXECUTE: 3650 pmap_clearbit(pg, PVF_WRITE); 3651 break; 3652 3653 default: 3654 pmap_page_remove(pg); 3655 break; 3656 } 3657 } 3658 3659 /* 3660 * pmap_clear_modify: 3661 * 3662 * Clear the "modified" attribute for a page. 3663 */ 3664 bool 3665 pmap_clear_modify(struct vm_page *pg) 3666 { 3667 bool rv; 3668 3669 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3670 rv = true; 3671 pmap_clearbit(pg, PVF_MOD); 3672 } else 3673 rv = false; 3674 3675 return (rv); 3676 } 3677 3678 /* 3679 * pmap_clear_reference: 3680 * 3681 * Clear the "referenced" attribute for a page. 3682 */ 3683 bool 3684 pmap_clear_reference(struct vm_page *pg) 3685 { 3686 bool rv; 3687 3688 if (pg->mdpage.pvh_attrs & PVF_REF) { 3689 rv = true; 3690 pmap_clearbit(pg, PVF_REF); 3691 } else 3692 rv = false; 3693 3694 return (rv); 3695 } 3696 3697 /* 3698 * pmap_is_modified: 3699 * 3700 * Test if a page has the "modified" attribute. 3701 */ 3702 /* See <arm/arm32/pmap.h> */ 3703 3704 /* 3705 * pmap_is_referenced: 3706 * 3707 * Test if a page has the "referenced" attribute. 3708 */ 3709 /* See <arm/arm32/pmap.h> */ 3710 3711 int 3712 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3713 { 3714 struct l2_dtable *l2; 3715 struct l2_bucket *l2b; 3716 pd_entry_t *pl1pd, l1pd; 3717 pt_entry_t *ptep, pte; 3718 paddr_t pa; 3719 u_int l1idx; 3720 int rv = 0; 3721 3722 PMAP_MAP_TO_HEAD_LOCK(); 3723 pmap_acquire_pmap_lock(pm); 3724 3725 l1idx = L1_IDX(va); 3726 3727 /* 3728 * If there is no l2_dtable for this address, then the process 3729 * has no business accessing it. 3730 * 3731 * Note: This will catch userland processes trying to access 3732 * kernel addresses. 3733 */ 3734 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3735 if (l2 == NULL) 3736 goto out; 3737 3738 /* 3739 * Likewise if there is no L2 descriptor table 3740 */ 3741 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3742 if (l2b->l2b_kva == NULL) 3743 goto out; 3744 3745 /* 3746 * Check the PTE itself. 3747 */ 3748 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3749 pte = *ptep; 3750 if (pte == 0) 3751 goto out; 3752 3753 /* 3754 * Catch a userland access to the vector page mapped at 0x0 3755 */ 3756 if (user && (pte & L2_S_PROT_U) == 0) 3757 goto out; 3758 3759 pa = l2pte_pa(pte); 3760 3761 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3762 /* 3763 * This looks like a good candidate for "page modified" 3764 * emulation... 3765 */ 3766 struct pv_entry *pv; 3767 struct vm_page *pg; 3768 3769 /* Extract the physical address of the page */ 3770 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3771 goto out; 3772 3773 /* Get the current flags for this page. */ 3774 simple_lock(&pg->mdpage.pvh_slock); 3775 3776 pv = pmap_find_pv(pg, pm, va); 3777 if (pv == NULL) { 3778 simple_unlock(&pg->mdpage.pvh_slock); 3779 goto out; 3780 } 3781 3782 /* 3783 * Do the flags say this page is writable? If not then it 3784 * is a genuine write fault. If yes then the write fault is 3785 * our fault as we did not reflect the write access in the 3786 * PTE. Now we know a write has occurred we can correct this 3787 * and also set the modified bit 3788 */ 3789 if ((pv->pv_flags & PVF_WRITE) == 0) { 3790 simple_unlock(&pg->mdpage.pvh_slock); 3791 goto out; 3792 } 3793 3794 NPDEBUG(PDB_FOLLOW, 3795 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3796 pm, va, VM_PAGE_TO_PHYS(pg))); 3797 3798 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 3799 pv->pv_flags |= PVF_REF | PVF_MOD; 3800 #ifdef PMAP_CACHE_VIPT 3801 /* 3802 * If there are cacheable mappings for this page, mark it dirty. 3803 */ 3804 if ((pg->mdpage.pvh_attrs & PVF_NC) == 0) 3805 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3806 #endif 3807 simple_unlock(&pg->mdpage.pvh_slock); 3808 3809 /* 3810 * Re-enable write permissions for the page. No need to call 3811 * pmap_vac_me_harder(), since this is just a 3812 * modified-emulation fault, and the PVF_WRITE bit isn't 3813 * changing. We've already set the cacheable bits based on 3814 * the assumption that we can write to this page. 3815 */ 3816 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3817 PTE_SYNC(ptep); 3818 rv = 1; 3819 } else 3820 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3821 /* 3822 * This looks like a good candidate for "page referenced" 3823 * emulation. 3824 */ 3825 struct pv_entry *pv; 3826 struct vm_page *pg; 3827 3828 /* Extract the physical address of the page */ 3829 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3830 goto out; 3831 3832 /* Get the current flags for this page. */ 3833 simple_lock(&pg->mdpage.pvh_slock); 3834 3835 pv = pmap_find_pv(pg, pm, va); 3836 if (pv == NULL) { 3837 simple_unlock(&pg->mdpage.pvh_slock); 3838 goto out; 3839 } 3840 3841 pg->mdpage.pvh_attrs |= PVF_REF; 3842 pv->pv_flags |= PVF_REF; 3843 simple_unlock(&pg->mdpage.pvh_slock); 3844 3845 NPDEBUG(PDB_FOLLOW, 3846 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3847 pm, va, VM_PAGE_TO_PHYS(pg))); 3848 3849 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3850 PTE_SYNC(ptep); 3851 rv = 1; 3852 } 3853 3854 /* 3855 * We know there is a valid mapping here, so simply 3856 * fix up the L1 if necessary. 3857 */ 3858 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3859 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3860 if (*pl1pd != l1pd) { 3861 *pl1pd = l1pd; 3862 PTE_SYNC(pl1pd); 3863 rv = 1; 3864 } 3865 3866 #ifdef CPU_SA110 3867 /* 3868 * There are bugs in the rev K SA110. This is a check for one 3869 * of them. 3870 */ 3871 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3872 curcpu()->ci_arm_cpurev < 3) { 3873 /* Always current pmap */ 3874 if (l2pte_valid(pte)) { 3875 extern int kernel_debug; 3876 if (kernel_debug & 1) { 3877 struct proc *p = curlwp->l_proc; 3878 printf("prefetch_abort: page is already " 3879 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3880 printf("prefetch_abort: pc=%08lx proc=%p " 3881 "process=%s\n", va, p, p->p_comm); 3882 printf("prefetch_abort: far=%08x fs=%x\n", 3883 cpu_faultaddress(), cpu_faultstatus()); 3884 } 3885 #ifdef DDB 3886 if (kernel_debug & 2) 3887 Debugger(); 3888 #endif 3889 rv = 1; 3890 } 3891 } 3892 #endif /* CPU_SA110 */ 3893 3894 #ifdef DEBUG 3895 /* 3896 * If 'rv == 0' at this point, it generally indicates that there is a 3897 * stale TLB entry for the faulting address. This happens when two or 3898 * more processes are sharing an L1. Since we don't flush the TLB on 3899 * a context switch between such processes, we can take domain faults 3900 * for mappings which exist at the same VA in both processes. EVEN IF 3901 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3902 * example. 3903 * 3904 * This is extremely likely to happen if pmap_enter() updated the L1 3905 * entry for a recently entered mapping. In this case, the TLB is 3906 * flushed for the new mapping, but there may still be TLB entries for 3907 * other mappings belonging to other processes in the 1MB range 3908 * covered by the L1 entry. 3909 * 3910 * Since 'rv == 0', we know that the L1 already contains the correct 3911 * value, so the fault must be due to a stale TLB entry. 3912 * 3913 * Since we always need to flush the TLB anyway in the case where we 3914 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 3915 * stale TLB entries dynamically. 3916 * 3917 * However, the above condition can ONLY happen if the current L1 is 3918 * being shared. If it happens when the L1 is unshared, it indicates 3919 * that other parts of the pmap are not doing their job WRT managing 3920 * the TLB. 3921 */ 3922 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 3923 extern int last_fault_code; 3924 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 3925 pm, va, ftype); 3926 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 3927 l2, l2b, ptep, pl1pd); 3928 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 3929 pte, l1pd, last_fault_code); 3930 #ifdef DDB 3931 Debugger(); 3932 #endif 3933 } 3934 #endif 3935 3936 cpu_tlb_flushID_SE(va); 3937 cpu_cpwait(); 3938 3939 rv = 1; 3940 3941 out: 3942 pmap_release_pmap_lock(pm); 3943 PMAP_MAP_TO_HEAD_UNLOCK(); 3944 3945 return (rv); 3946 } 3947 3948 /* 3949 * pmap_collect: free resources held by a pmap 3950 * 3951 * => optional function. 3952 * => called when a process is swapped out to free memory. 3953 */ 3954 void 3955 pmap_collect(pmap_t pm) 3956 { 3957 3958 #ifdef PMAP_CACHE_VIVT 3959 pmap_idcache_wbinv_all(pm); 3960 #endif 3961 pm->pm_remove_all = true; 3962 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 3963 pmap_update(pm); 3964 PMAPCOUNT(collects); 3965 } 3966 3967 /* 3968 * Routine: pmap_procwr 3969 * 3970 * Function: 3971 * Synchronize caches corresponding to [addr, addr+len) in p. 3972 * 3973 */ 3974 void 3975 pmap_procwr(struct proc *p, vaddr_t va, int len) 3976 { 3977 /* We only need to do anything if it is the current process. */ 3978 if (p == curproc) 3979 cpu_icache_sync_range(va, len); 3980 } 3981 3982 /* 3983 * Routine: pmap_unwire 3984 * Function: Clear the wired attribute for a map/virtual-address pair. 3985 * 3986 * In/out conditions: 3987 * The mapping must already exist in the pmap. 3988 */ 3989 void 3990 pmap_unwire(pmap_t pm, vaddr_t va) 3991 { 3992 struct l2_bucket *l2b; 3993 pt_entry_t *ptep, pte; 3994 struct vm_page *pg; 3995 paddr_t pa; 3996 3997 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 3998 3999 PMAP_MAP_TO_HEAD_LOCK(); 4000 pmap_acquire_pmap_lock(pm); 4001 4002 l2b = pmap_get_l2_bucket(pm, va); 4003 KDASSERT(l2b != NULL); 4004 4005 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4006 pte = *ptep; 4007 4008 /* Extract the physical address of the page */ 4009 pa = l2pte_pa(pte); 4010 4011 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4012 /* Update the wired bit in the pv entry for this page. */ 4013 simple_lock(&pg->mdpage.pvh_slock); 4014 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 4015 simple_unlock(&pg->mdpage.pvh_slock); 4016 } 4017 4018 pmap_release_pmap_lock(pm); 4019 PMAP_MAP_TO_HEAD_UNLOCK(); 4020 } 4021 4022 void 4023 pmap_activate(struct lwp *l) 4024 { 4025 extern int block_userspace_access; 4026 pmap_t opm, npm, rpm; 4027 uint32_t odacr, ndacr; 4028 int oldirqstate; 4029 4030 /* 4031 * If activating a non-current lwp or the current lwp is 4032 * already active, just return. 4033 */ 4034 if (l != curlwp || 4035 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4036 return; 4037 4038 npm = l->l_proc->p_vmspace->vm_map.pmap; 4039 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4040 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4041 4042 /* 4043 * If TTB and DACR are unchanged, short-circuit all the 4044 * TLB/cache management stuff. 4045 */ 4046 if (pmap_previous_active_lwp != NULL) { 4047 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4048 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4049 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4050 4051 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4052 goto all_done; 4053 } else 4054 opm = NULL; 4055 4056 PMAPCOUNT(activations); 4057 block_userspace_access = 1; 4058 4059 /* 4060 * If switching to a user vmspace which is different to the 4061 * most recent one, and the most recent one is potentially 4062 * live in the cache, we must write-back and invalidate the 4063 * entire cache. 4064 */ 4065 rpm = pmap_recent_user; 4066 if (npm != pmap_kernel() && rpm && npm != rpm && 4067 rpm->pm_cstate.cs_cache) { 4068 rpm->pm_cstate.cs_cache = 0; 4069 #ifdef PMAP_CACHE_VIVT 4070 cpu_idcache_wbinv_all(); 4071 #endif 4072 } 4073 4074 /* No interrupts while we frob the TTB/DACR */ 4075 oldirqstate = disable_interrupts(IF32_bits); 4076 4077 /* 4078 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4079 * entry corresponding to 'vector_page' in the incoming L1 table 4080 * before switching to it otherwise subsequent interrupts/exceptions 4081 * (including domain faults!) will jump into hyperspace. 4082 */ 4083 if (npm->pm_pl1vec != NULL) { 4084 cpu_tlb_flushID_SE((u_int)vector_page); 4085 cpu_cpwait(); 4086 *npm->pm_pl1vec = npm->pm_l1vec; 4087 PTE_SYNC(npm->pm_pl1vec); 4088 } 4089 4090 cpu_domains(ndacr); 4091 4092 if (npm == pmap_kernel() || npm == rpm) { 4093 /* 4094 * Switching to a kernel thread, or back to the 4095 * same user vmspace as before... Simply update 4096 * the TTB (no TLB flush required) 4097 */ 4098 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4099 "r"(npm->pm_l1->l1_physaddr)); 4100 cpu_cpwait(); 4101 } else { 4102 /* 4103 * Otherwise, update TTB and flush TLB 4104 */ 4105 cpu_context_switch(npm->pm_l1->l1_physaddr); 4106 if (rpm != NULL) 4107 rpm->pm_cstate.cs_tlb = 0; 4108 } 4109 4110 restore_interrupts(oldirqstate); 4111 4112 block_userspace_access = 0; 4113 4114 all_done: 4115 /* 4116 * The new pmap is resident. Make sure it's marked 4117 * as resident in the cache/TLB. 4118 */ 4119 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4120 if (npm != pmap_kernel()) 4121 pmap_recent_user = npm; 4122 4123 /* The old pmap is not longer active */ 4124 if (opm != NULL) 4125 opm->pm_activated = false; 4126 4127 /* But the new one is */ 4128 npm->pm_activated = true; 4129 } 4130 4131 void 4132 pmap_deactivate(struct lwp *l) 4133 { 4134 4135 /* 4136 * If the process is exiting, make sure pmap_activate() does 4137 * a full MMU context-switch and cache flush, which we might 4138 * otherwise skip. See PR port-arm/38950. 4139 */ 4140 if (l->l_proc->p_sflag & PS_WEXIT) 4141 pmap_previous_active_lwp = NULL; 4142 4143 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4144 } 4145 4146 void 4147 pmap_update(pmap_t pm) 4148 { 4149 4150 if (pm->pm_remove_all) { 4151 /* 4152 * Finish up the pmap_remove_all() optimisation by flushing 4153 * the TLB. 4154 */ 4155 pmap_tlb_flushID(pm); 4156 pm->pm_remove_all = false; 4157 } 4158 4159 if (pmap_is_current(pm)) { 4160 /* 4161 * If we're dealing with a current userland pmap, move its L1 4162 * to the end of the LRU. 4163 */ 4164 if (pm != pmap_kernel()) 4165 pmap_use_l1(pm); 4166 4167 /* 4168 * We can assume we're done with frobbing the cache/tlb for 4169 * now. Make sure any future pmap ops don't skip cache/tlb 4170 * flushes. 4171 */ 4172 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4173 } 4174 4175 PMAPCOUNT(updates); 4176 4177 /* 4178 * make sure TLB/cache operations have completed. 4179 */ 4180 cpu_cpwait(); 4181 } 4182 4183 void 4184 pmap_remove_all(pmap_t pm) 4185 { 4186 4187 /* 4188 * The vmspace described by this pmap is about to be torn down. 4189 * Until pmap_update() is called, UVM will only make calls 4190 * to pmap_remove(). We can make life much simpler by flushing 4191 * the cache now, and deferring TLB invalidation to pmap_update(). 4192 */ 4193 #ifdef PMAP_CACHE_VIVT 4194 pmap_idcache_wbinv_all(pm); 4195 #endif 4196 pm->pm_remove_all = true; 4197 } 4198 4199 /* 4200 * Retire the given physical map from service. 4201 * Should only be called if the map contains no valid mappings. 4202 */ 4203 void 4204 pmap_destroy(pmap_t pm) 4205 { 4206 u_int count; 4207 4208 if (pm == NULL) 4209 return; 4210 4211 if (pm->pm_remove_all) { 4212 pmap_tlb_flushID(pm); 4213 pm->pm_remove_all = false; 4214 } 4215 4216 /* 4217 * Drop reference count 4218 */ 4219 mutex_enter(&pm->pm_lock); 4220 count = --pm->pm_obj.uo_refs; 4221 mutex_exit(&pm->pm_lock); 4222 if (count > 0) { 4223 if (pmap_is_current(pm)) { 4224 if (pm != pmap_kernel()) 4225 pmap_use_l1(pm); 4226 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4227 } 4228 return; 4229 } 4230 4231 /* 4232 * reference count is zero, free pmap resources and then free pmap. 4233 */ 4234 4235 if (vector_page < KERNEL_BASE) { 4236 KDASSERT(!pmap_is_current(pm)); 4237 4238 /* Remove the vector page mapping */ 4239 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4240 pmap_update(pm); 4241 } 4242 4243 LIST_REMOVE(pm, pm_list); 4244 4245 pmap_free_l1(pm); 4246 4247 if (pmap_recent_user == pm) 4248 pmap_recent_user = NULL; 4249 4250 UVM_OBJ_DESTROY(&pm->pm_obj); 4251 4252 /* return the pmap to the pool */ 4253 pool_cache_put(&pmap_cache, pm); 4254 } 4255 4256 4257 /* 4258 * void pmap_reference(pmap_t pm) 4259 * 4260 * Add a reference to the specified pmap. 4261 */ 4262 void 4263 pmap_reference(pmap_t pm) 4264 { 4265 4266 if (pm == NULL) 4267 return; 4268 4269 pmap_use_l1(pm); 4270 4271 mutex_enter(&pm->pm_lock); 4272 pm->pm_obj.uo_refs++; 4273 mutex_exit(&pm->pm_lock); 4274 } 4275 4276 #if ARM_MMU_V6 > 0 4277 4278 static struct evcnt pmap_prefer_nochange_ev = 4279 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4280 static struct evcnt pmap_prefer_change_ev = 4281 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4282 4283 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4284 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4285 4286 void 4287 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4288 { 4289 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4290 vaddr_t va = *vap; 4291 vaddr_t diff = (hint - va) & mask; 4292 if (diff == 0) { 4293 pmap_prefer_nochange_ev.ev_count++; 4294 } else { 4295 pmap_prefer_change_ev.ev_count++; 4296 if (__predict_false(td)) 4297 va -= mask + 1; 4298 *vap = va + diff; 4299 } 4300 } 4301 #endif /* ARM_MMU_V6 */ 4302 4303 /* 4304 * pmap_zero_page() 4305 * 4306 * Zero a given physical page by mapping it at a page hook point. 4307 * In doing the zero page op, the page we zero is mapped cachable, as with 4308 * StrongARM accesses to non-cached pages are non-burst making writing 4309 * _any_ bulk data very slow. 4310 */ 4311 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4312 void 4313 pmap_zero_page_generic(paddr_t phys) 4314 { 4315 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4316 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4317 #endif 4318 #ifdef PMAP_CACHE_VIPT 4319 /* Choose the last page color it had, if any */ 4320 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4321 #else 4322 const vsize_t va_offset = 0; 4323 #endif 4324 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4325 4326 #ifdef DEBUG 4327 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4328 panic("pmap_zero_page: page has mappings"); 4329 #endif 4330 4331 KDASSERT((phys & PGOFSET) == 0); 4332 4333 /* 4334 * Hook in the page, zero it, and purge the cache for that 4335 * zeroed page. Invalidate the TLB as needed. 4336 */ 4337 *ptep = L2_S_PROTO | phys | 4338 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4339 PTE_SYNC(ptep); 4340 cpu_tlb_flushD_SE(cdstp + va_offset); 4341 cpu_cpwait(); 4342 bzero_page(cdstp + va_offset); 4343 /* 4344 * Unmap the page. 4345 */ 4346 *ptep = 0; 4347 PTE_SYNC(ptep); 4348 cpu_tlb_flushD_SE(cdstp + va_offset); 4349 #ifdef PMAP_CACHE_VIVT 4350 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4351 #endif 4352 #ifdef PMAP_CACHE_VIPT 4353 /* 4354 * This page is now cache resident so it now has a page color. 4355 * Any contents have been obliterated so clear the EXEC flag. 4356 */ 4357 if (!pmap_is_page_colored_p(pg)) { 4358 PMAPCOUNT(vac_color_new); 4359 pg->mdpage.pvh_attrs |= PVF_COLORED; 4360 } 4361 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4362 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4363 PMAPCOUNT(exec_discarded_zero); 4364 } 4365 pg->mdpage.pvh_attrs |= PVF_DIRTY; 4366 #endif 4367 } 4368 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4369 4370 #if ARM_MMU_XSCALE == 1 4371 void 4372 pmap_zero_page_xscale(paddr_t phys) 4373 { 4374 #ifdef DEBUG 4375 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4376 4377 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4378 panic("pmap_zero_page: page has mappings"); 4379 #endif 4380 4381 KDASSERT((phys & PGOFSET) == 0); 4382 4383 /* 4384 * Hook in the page, zero it, and purge the cache for that 4385 * zeroed page. Invalidate the TLB as needed. 4386 */ 4387 *cdst_pte = L2_S_PROTO | phys | 4388 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4389 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4390 PTE_SYNC(cdst_pte); 4391 cpu_tlb_flushD_SE(cdstp); 4392 cpu_cpwait(); 4393 bzero_page(cdstp); 4394 xscale_cache_clean_minidata(); 4395 } 4396 #endif /* ARM_MMU_XSCALE == 1 */ 4397 4398 /* pmap_pageidlezero() 4399 * 4400 * The same as above, except that we assume that the page is not 4401 * mapped. This means we never have to flush the cache first. Called 4402 * from the idle loop. 4403 */ 4404 bool 4405 pmap_pageidlezero(paddr_t phys) 4406 { 4407 unsigned int i; 4408 int *ptr; 4409 bool rv = true; 4410 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4411 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4412 #endif 4413 #ifdef PMAP_CACHE_VIPT 4414 /* Choose the last page color it had, if any */ 4415 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4416 #else 4417 const vsize_t va_offset = 0; 4418 #endif 4419 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4420 4421 4422 #ifdef DEBUG 4423 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4424 panic("pmap_pageidlezero: page has mappings"); 4425 #endif 4426 4427 KDASSERT((phys & PGOFSET) == 0); 4428 4429 /* 4430 * Hook in the page, zero it, and purge the cache for that 4431 * zeroed page. Invalidate the TLB as needed. 4432 */ 4433 *ptep = L2_S_PROTO | phys | 4434 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4435 PTE_SYNC(ptep); 4436 cpu_tlb_flushD_SE(cdstp + va_offset); 4437 cpu_cpwait(); 4438 4439 for (i = 0, ptr = (int *)(cdstp + va_offset); 4440 i < (PAGE_SIZE / sizeof(int)); i++) { 4441 if (sched_curcpu_runnable_p() != 0) { 4442 /* 4443 * A process has become ready. Abort now, 4444 * so we don't keep it waiting while we 4445 * do slow memory access to finish this 4446 * page. 4447 */ 4448 rv = false; 4449 break; 4450 } 4451 *ptr++ = 0; 4452 } 4453 4454 #ifdef PMAP_CACHE_VIVT 4455 if (rv) 4456 /* 4457 * if we aborted we'll rezero this page again later so don't 4458 * purge it unless we finished it 4459 */ 4460 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4461 #elif defined(PMAP_CACHE_VIPT) 4462 /* 4463 * This page is now cache resident so it now has a page color. 4464 * Any contents have been obliterated so clear the EXEC flag. 4465 */ 4466 if (!pmap_is_page_colored_p(pg)) { 4467 PMAPCOUNT(vac_color_new); 4468 pg->mdpage.pvh_attrs |= PVF_COLORED; 4469 } 4470 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4471 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4472 PMAPCOUNT(exec_discarded_zero); 4473 } 4474 #endif 4475 /* 4476 * Unmap the page. 4477 */ 4478 *ptep = 0; 4479 PTE_SYNC(ptep); 4480 cpu_tlb_flushD_SE(cdstp + va_offset); 4481 4482 return (rv); 4483 } 4484 4485 /* 4486 * pmap_copy_page() 4487 * 4488 * Copy one physical page into another, by mapping the pages into 4489 * hook points. The same comment regarding cachability as in 4490 * pmap_zero_page also applies here. 4491 */ 4492 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4493 void 4494 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4495 { 4496 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4497 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4498 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4499 #endif 4500 #ifdef PMAP_CACHE_VIPT 4501 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4502 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4503 #else 4504 const vsize_t src_va_offset = 0; 4505 const vsize_t dst_va_offset = 0; 4506 #endif 4507 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4508 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4509 4510 #ifdef DEBUG 4511 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4512 panic("pmap_copy_page: dst page has mappings"); 4513 #endif 4514 4515 #ifdef PMAP_CACHE_VIPT 4516 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4517 #endif 4518 KDASSERT((src & PGOFSET) == 0); 4519 KDASSERT((dst & PGOFSET) == 0); 4520 4521 /* 4522 * Clean the source page. Hold the source page's lock for 4523 * the duration of the copy so that no other mappings can 4524 * be created while we have a potentially aliased mapping. 4525 */ 4526 simple_lock(&src_pg->mdpage.pvh_slock); 4527 #ifdef PMAP_CACHE_VIVT 4528 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4529 #endif 4530 4531 /* 4532 * Map the pages into the page hook points, copy them, and purge 4533 * the cache for the appropriate page. Invalidate the TLB 4534 * as required. 4535 */ 4536 *src_ptep = L2_S_PROTO 4537 | src 4538 #ifdef PMAP_CACHE_VIPT 4539 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4540 #endif 4541 #ifdef PMAP_CACHE_VIVT 4542 | pte_l2_s_cache_mode 4543 #endif 4544 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4545 *dst_ptep = L2_S_PROTO | dst | 4546 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4547 PTE_SYNC(src_ptep); 4548 PTE_SYNC(dst_ptep); 4549 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4550 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4551 cpu_cpwait(); 4552 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4553 #ifdef PMAP_CACHE_VIVT 4554 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4555 #endif 4556 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4557 #ifdef PMAP_CACHE_VIVT 4558 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4559 #endif 4560 /* 4561 * Unmap the pages. 4562 */ 4563 *src_ptep = 0; 4564 *dst_ptep = 0; 4565 PTE_SYNC(src_ptep); 4566 PTE_SYNC(dst_ptep); 4567 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4568 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4569 #ifdef PMAP_CACHE_VIPT 4570 /* 4571 * Now that the destination page is in the cache, mark it as colored. 4572 * If this was an exec page, discard it. 4573 */ 4574 if (!pmap_is_page_colored_p(dst_pg)) { 4575 PMAPCOUNT(vac_color_new); 4576 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4577 } 4578 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4579 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4580 PMAPCOUNT(exec_discarded_copy); 4581 } 4582 dst_pg->mdpage.pvh_attrs |= PVF_DIRTY; 4583 #endif 4584 } 4585 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4586 4587 #if ARM_MMU_XSCALE == 1 4588 void 4589 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4590 { 4591 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4592 #ifdef DEBUG 4593 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4594 4595 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4596 panic("pmap_copy_page: dst page has mappings"); 4597 #endif 4598 4599 KDASSERT((src & PGOFSET) == 0); 4600 KDASSERT((dst & PGOFSET) == 0); 4601 4602 /* 4603 * Clean the source page. Hold the source page's lock for 4604 * the duration of the copy so that no other mappings can 4605 * be created while we have a potentially aliased mapping. 4606 */ 4607 simple_lock(&src_pg->mdpage.pvh_slock); 4608 #ifdef PMAP_CACHE_VIVT 4609 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4610 #endif 4611 4612 /* 4613 * Map the pages into the page hook points, copy them, and purge 4614 * the cache for the appropriate page. Invalidate the TLB 4615 * as required. 4616 */ 4617 *csrc_pte = L2_S_PROTO | src | 4618 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4619 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4620 PTE_SYNC(csrc_pte); 4621 *cdst_pte = L2_S_PROTO | dst | 4622 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4623 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4624 PTE_SYNC(cdst_pte); 4625 cpu_tlb_flushD_SE(csrcp); 4626 cpu_tlb_flushD_SE(cdstp); 4627 cpu_cpwait(); 4628 bcopy_page(csrcp, cdstp); 4629 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4630 xscale_cache_clean_minidata(); 4631 } 4632 #endif /* ARM_MMU_XSCALE == 1 */ 4633 4634 /* 4635 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4636 * 4637 * Return the start and end addresses of the kernel's virtual space. 4638 * These values are setup in pmap_bootstrap and are updated as pages 4639 * are allocated. 4640 */ 4641 void 4642 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4643 { 4644 *start = virtual_avail; 4645 *end = virtual_end; 4646 } 4647 4648 /* 4649 * Helper function for pmap_grow_l2_bucket() 4650 */ 4651 static inline int 4652 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4653 { 4654 struct l2_bucket *l2b; 4655 pt_entry_t *ptep; 4656 paddr_t pa; 4657 4658 if (uvm.page_init_done == false) { 4659 #ifdef PMAP_STEAL_MEMORY 4660 pv_addr_t pv; 4661 pmap_boot_pagealloc(PAGE_SIZE, 4662 #ifdef PMAP_CACHE_VIPT 4663 arm_cache_prefer_mask, 4664 va & arm_cache_prefer_mask, 4665 #else 4666 0, 0, 4667 #endif 4668 &pv); 4669 pa = pv.pv_pa; 4670 #else 4671 if (uvm_page_physget(&pa) == false) 4672 return (1); 4673 #endif /* PMAP_STEAL_MEMORY */ 4674 } else { 4675 struct vm_page *pg; 4676 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4677 if (pg == NULL) 4678 return (1); 4679 pa = VM_PAGE_TO_PHYS(pg); 4680 #ifdef PMAP_CACHE_VIPT 4681 /* 4682 * This new page must not have any mappings. Enter it via 4683 * pmap_kenter_pa and let that routine do the hard work. 4684 */ 4685 KASSERT(SLIST_EMPTY(&pg->mdpage.pvh_list)); 4686 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 4687 #endif 4688 } 4689 4690 if (pap) 4691 *pap = pa; 4692 4693 PMAPCOUNT(pt_mappings); 4694 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4695 KDASSERT(l2b != NULL); 4696 4697 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4698 *ptep = L2_S_PROTO | pa | cache_mode | 4699 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4700 PTE_SYNC(ptep); 4701 memset((void *)va, 0, PAGE_SIZE); 4702 return (0); 4703 } 4704 4705 /* 4706 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4707 * used by pmap_growkernel(). 4708 */ 4709 static inline struct l2_bucket * 4710 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4711 { 4712 struct l2_dtable *l2; 4713 struct l2_bucket *l2b; 4714 u_short l1idx; 4715 vaddr_t nva; 4716 4717 l1idx = L1_IDX(va); 4718 4719 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4720 /* 4721 * No mapping at this address, as there is 4722 * no entry in the L1 table. 4723 * Need to allocate a new l2_dtable. 4724 */ 4725 nva = pmap_kernel_l2dtable_kva; 4726 if ((nva & PGOFSET) == 0) { 4727 /* 4728 * Need to allocate a backing page 4729 */ 4730 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4731 return (NULL); 4732 } 4733 4734 l2 = (struct l2_dtable *)nva; 4735 nva += sizeof(struct l2_dtable); 4736 4737 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4738 /* 4739 * The new l2_dtable straddles a page boundary. 4740 * Map in another page to cover it. 4741 */ 4742 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4743 return (NULL); 4744 } 4745 4746 pmap_kernel_l2dtable_kva = nva; 4747 4748 /* 4749 * Link it into the parent pmap 4750 */ 4751 pm->pm_l2[L2_IDX(l1idx)] = l2; 4752 } 4753 4754 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4755 4756 /* 4757 * Fetch pointer to the L2 page table associated with the address. 4758 */ 4759 if (l2b->l2b_kva == NULL) { 4760 pt_entry_t *ptep; 4761 4762 /* 4763 * No L2 page table has been allocated. Chances are, this 4764 * is because we just allocated the l2_dtable, above. 4765 */ 4766 nva = pmap_kernel_l2ptp_kva; 4767 ptep = (pt_entry_t *)nva; 4768 if ((nva & PGOFSET) == 0) { 4769 /* 4770 * Need to allocate a backing page 4771 */ 4772 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4773 &pmap_kernel_l2ptp_phys)) 4774 return (NULL); 4775 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4776 } 4777 4778 l2->l2_occupancy++; 4779 l2b->l2b_kva = ptep; 4780 l2b->l2b_l1idx = l1idx; 4781 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4782 4783 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4784 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4785 } 4786 4787 return (l2b); 4788 } 4789 4790 vaddr_t 4791 pmap_growkernel(vaddr_t maxkvaddr) 4792 { 4793 pmap_t kpm = pmap_kernel(); 4794 struct l1_ttable *l1; 4795 struct l2_bucket *l2b; 4796 pd_entry_t *pl1pd; 4797 int s; 4798 4799 if (maxkvaddr <= pmap_curmaxkvaddr) 4800 goto out; /* we are OK */ 4801 4802 NPDEBUG(PDB_GROWKERN, 4803 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4804 pmap_curmaxkvaddr, maxkvaddr)); 4805 4806 KDASSERT(maxkvaddr <= virtual_end); 4807 4808 /* 4809 * whoops! we need to add kernel PTPs 4810 */ 4811 4812 s = splhigh(); /* to be safe */ 4813 mutex_enter(&kpm->pm_lock); 4814 4815 /* Map 1MB at a time */ 4816 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4817 4818 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4819 KDASSERT(l2b != NULL); 4820 4821 /* Distribute new L1 entry to all other L1s */ 4822 SLIST_FOREACH(l1, &l1_list, l1_link) { 4823 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4824 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4825 L1_C_PROTO; 4826 PTE_SYNC(pl1pd); 4827 } 4828 } 4829 4830 /* 4831 * flush out the cache, expensive but growkernel will happen so 4832 * rarely 4833 */ 4834 cpu_dcache_wbinv_all(); 4835 cpu_tlb_flushD(); 4836 cpu_cpwait(); 4837 4838 mutex_exit(&kpm->pm_lock); 4839 splx(s); 4840 4841 out: 4842 return (pmap_curmaxkvaddr); 4843 } 4844 4845 /************************ Utility routines ****************************/ 4846 4847 /* 4848 * vector_page_setprot: 4849 * 4850 * Manipulate the protection of the vector page. 4851 */ 4852 void 4853 vector_page_setprot(int prot) 4854 { 4855 struct l2_bucket *l2b; 4856 pt_entry_t *ptep; 4857 4858 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4859 KDASSERT(l2b != NULL); 4860 4861 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4862 4863 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4864 PTE_SYNC(ptep); 4865 cpu_tlb_flushD_SE(vector_page); 4866 cpu_cpwait(); 4867 } 4868 4869 /* 4870 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4871 * Returns true if the mapping exists, else false. 4872 * 4873 * NOTE: This function is only used by a couple of arm-specific modules. 4874 * It is not safe to take any pmap locks here, since we could be right 4875 * in the middle of debugging the pmap anyway... 4876 * 4877 * It is possible for this routine to return false even though a valid 4878 * mapping does exist. This is because we don't lock, so the metadata 4879 * state may be inconsistent. 4880 * 4881 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4882 * a "section" mapping. 4883 */ 4884 bool 4885 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4886 { 4887 struct l2_dtable *l2; 4888 pd_entry_t *pl1pd, l1pd; 4889 pt_entry_t *ptep; 4890 u_short l1idx; 4891 4892 if (pm->pm_l1 == NULL) 4893 return false; 4894 4895 l1idx = L1_IDX(va); 4896 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4897 l1pd = *pl1pd; 4898 4899 if (l1pte_section_p(l1pd)) { 4900 *ptp = NULL; 4901 return true; 4902 } 4903 4904 if (pm->pm_l2 == NULL) 4905 return false; 4906 4907 l2 = pm->pm_l2[L2_IDX(l1idx)]; 4908 4909 if (l2 == NULL || 4910 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 4911 return false; 4912 } 4913 4914 *ptp = &ptep[l2pte_index(va)]; 4915 return true; 4916 } 4917 4918 bool 4919 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 4920 { 4921 u_short l1idx; 4922 4923 if (pm->pm_l1 == NULL) 4924 return false; 4925 4926 l1idx = L1_IDX(va); 4927 *pdp = &pm->pm_l1->l1_kva[l1idx]; 4928 4929 return true; 4930 } 4931 4932 /************************ Bootstrapping routines ****************************/ 4933 4934 static void 4935 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 4936 { 4937 int i; 4938 4939 l1->l1_kva = l1pt; 4940 l1->l1_domain_use_count = 0; 4941 l1->l1_domain_first = 0; 4942 4943 for (i = 0; i < PMAP_DOMAINS; i++) 4944 l1->l1_domain_free[i] = i + 1; 4945 4946 /* 4947 * Copy the kernel's L1 entries to each new L1. 4948 */ 4949 if (pmap_initialized) 4950 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 4951 4952 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 4953 &l1->l1_physaddr) == false) 4954 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 4955 4956 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 4957 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 4958 } 4959 4960 /* 4961 * pmap_bootstrap() is called from the board-specific initarm() routine 4962 * once the kernel L1/L2 descriptors tables have been set up. 4963 * 4964 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 4965 * spread over a number of disparate files/functions. 4966 * 4967 * We are passed the following parameters 4968 * - kernel_l1pt 4969 * This is a pointer to the base of the kernel's L1 translation table. 4970 * - vstart 4971 * 1MB-aligned start of managed kernel virtual memory. 4972 * - vend 4973 * 1MB-aligned end of managed kernel virtual memory. 4974 * 4975 * We use the first parameter to build the metadata (struct l1_ttable and 4976 * struct l2_dtable) necessary to track kernel mappings. 4977 */ 4978 #define PMAP_STATIC_L2_SIZE 16 4979 void 4980 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 4981 { 4982 static struct l1_ttable static_l1; 4983 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 4984 struct l1_ttable *l1 = &static_l1; 4985 struct l2_dtable *l2; 4986 struct l2_bucket *l2b; 4987 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 4988 pmap_t pm = pmap_kernel(); 4989 pd_entry_t pde; 4990 pt_entry_t *ptep; 4991 paddr_t pa; 4992 vaddr_t va; 4993 vsize_t size; 4994 int nptes, l1idx, l2idx, l2next = 0; 4995 4996 /* 4997 * Initialise the kernel pmap object 4998 */ 4999 pm->pm_l1 = l1; 5000 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5001 pm->pm_activated = true; 5002 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5003 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5004 5005 /* 5006 * Scan the L1 translation table created by initarm() and create 5007 * the required metadata for all valid mappings found in it. 5008 */ 5009 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5010 pde = l1pt[l1idx]; 5011 5012 /* 5013 * We're only interested in Coarse mappings. 5014 * pmap_extract() can deal with section mappings without 5015 * recourse to checking L2 metadata. 5016 */ 5017 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5018 continue; 5019 5020 /* 5021 * Lookup the KVA of this L2 descriptor table 5022 */ 5023 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5024 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5025 if (ptep == NULL) { 5026 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5027 (u_int)l1idx << L1_S_SHIFT, pa); 5028 } 5029 5030 /* 5031 * Fetch the associated L2 metadata structure. 5032 * Allocate a new one if necessary. 5033 */ 5034 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5035 if (l2next == PMAP_STATIC_L2_SIZE) 5036 panic("pmap_bootstrap: out of static L2s"); 5037 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5038 } 5039 5040 /* 5041 * One more L1 slot tracked... 5042 */ 5043 l2->l2_occupancy++; 5044 5045 /* 5046 * Fill in the details of the L2 descriptor in the 5047 * appropriate bucket. 5048 */ 5049 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5050 l2b->l2b_kva = ptep; 5051 l2b->l2b_phys = pa; 5052 l2b->l2b_l1idx = l1idx; 5053 5054 /* 5055 * Establish an initial occupancy count for this descriptor 5056 */ 5057 for (l2idx = 0; 5058 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5059 l2idx++) { 5060 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5061 l2b->l2b_occupancy++; 5062 } 5063 } 5064 5065 /* 5066 * Make sure the descriptor itself has the correct cache mode. 5067 * If not, fix it, but whine about the problem. Port-meisters 5068 * should consider this a clue to fix up their initarm() 5069 * function. :) 5070 */ 5071 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5072 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5073 "L2 pte @ %p\n", ptep); 5074 } 5075 } 5076 5077 /* 5078 * Ensure the primary (kernel) L1 has the correct cache mode for 5079 * a page table. Bitch if it is not correctly set. 5080 */ 5081 for (va = (vaddr_t)l1pt; 5082 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5083 if (pmap_set_pt_cache_mode(l1pt, va)) 5084 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5085 "primary L1 @ 0x%lx\n", va); 5086 } 5087 5088 cpu_dcache_wbinv_all(); 5089 cpu_tlb_flushID(); 5090 cpu_cpwait(); 5091 5092 /* 5093 * now we allocate the "special" VAs which are used for tmp mappings 5094 * by the pmap (and other modules). we allocate the VAs by advancing 5095 * virtual_avail (note that there are no pages mapped at these VAs). 5096 * 5097 * Managed KVM space start from wherever initarm() tells us. 5098 */ 5099 virtual_avail = vstart; 5100 virtual_end = vend; 5101 5102 #ifdef PMAP_CACHE_VIPT 5103 /* 5104 * If we have a VIPT cache, we need one page/pte per possible alias 5105 * page so we won't violate cache aliasing rules. 5106 */ 5107 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5108 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5109 #else 5110 nptes = 1; 5111 #endif 5112 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5113 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5114 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5115 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5116 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5117 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5118 (void *)&msgbufaddr, NULL); 5119 5120 /* 5121 * Allocate a range of kernel virtual address space to be used 5122 * for L2 descriptor tables and metadata allocation in 5123 * pmap_growkernel(). 5124 */ 5125 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5126 pmap_alloc_specials(&virtual_avail, 5127 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5128 &pmap_kernel_l2ptp_kva, NULL); 5129 5130 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5131 pmap_alloc_specials(&virtual_avail, 5132 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5133 &pmap_kernel_l2dtable_kva, NULL); 5134 5135 /* 5136 * init the static-global locks and global pmap list. 5137 */ 5138 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5139 5140 /* 5141 * We can now initialise the first L1's metadata. 5142 */ 5143 SLIST_INIT(&l1_list); 5144 TAILQ_INIT(&l1_lru_list); 5145 simple_lock_init(&l1_lru_lock); 5146 pmap_init_l1(l1, l1pt); 5147 5148 /* Set up vector page L1 details, if necessary */ 5149 if (vector_page < KERNEL_BASE) { 5150 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5151 l2b = pmap_get_l2_bucket(pm, vector_page); 5152 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5153 L1_C_DOM(pm->pm_domain); 5154 } else 5155 pm->pm_pl1vec = NULL; 5156 5157 /* 5158 * Initialize the pmap cache 5159 */ 5160 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5161 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5162 LIST_INIT(&pmap_pmaps); 5163 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5164 5165 /* 5166 * Initialize the pv pool. 5167 */ 5168 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5169 &pmap_bootstrap_pv_allocator, IPL_NONE); 5170 5171 /* 5172 * Initialize the L2 dtable pool and cache. 5173 */ 5174 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5175 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5176 5177 /* 5178 * Initialise the L2 descriptor table pool and cache 5179 */ 5180 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5181 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5182 pmap_l2ptp_ctor, NULL, NULL); 5183 5184 cpu_dcache_wbinv_all(); 5185 } 5186 5187 static int 5188 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5189 { 5190 pd_entry_t *pdep, pde; 5191 pt_entry_t *ptep, pte; 5192 vaddr_t pa; 5193 int rv = 0; 5194 5195 /* 5196 * Make sure the descriptor itself has the correct cache mode 5197 */ 5198 pdep = &kl1[L1_IDX(va)]; 5199 pde = *pdep; 5200 5201 if (l1pte_section_p(pde)) { 5202 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5203 *pdep = (pde & ~L1_S_CACHE_MASK) | 5204 pte_l1_s_cache_mode_pt; 5205 PTE_SYNC(pdep); 5206 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5207 rv = 1; 5208 } 5209 } else { 5210 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5211 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5212 if (ptep == NULL) 5213 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5214 5215 ptep = &ptep[l2pte_index(va)]; 5216 pte = *ptep; 5217 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5218 *ptep = (pte & ~L2_S_CACHE_MASK) | 5219 pte_l2_s_cache_mode_pt; 5220 PTE_SYNC(ptep); 5221 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5222 rv = 1; 5223 } 5224 } 5225 5226 return (rv); 5227 } 5228 5229 static void 5230 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5231 { 5232 vaddr_t va = *availp; 5233 struct l2_bucket *l2b; 5234 5235 if (ptep) { 5236 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5237 if (l2b == NULL) 5238 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5239 5240 if (ptep) 5241 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5242 } 5243 5244 *vap = va; 5245 *availp = va + (PAGE_SIZE * pages); 5246 } 5247 5248 void 5249 pmap_init(void) 5250 { 5251 extern int physmem; 5252 5253 /* 5254 * Set the available memory vars - These do not map to real memory 5255 * addresses and cannot as the physical memory is fragmented. 5256 * They are used by ps for %mem calculations. 5257 * One could argue whether this should be the entire memory or just 5258 * the memory that is useable in a user process. 5259 */ 5260 avail_start = 0; 5261 avail_end = physmem * PAGE_SIZE; 5262 5263 /* 5264 * Now we need to free enough pv_entry structures to allow us to get 5265 * the kmem_map/kmem_object allocated and inited (done after this 5266 * function is finished). to do this we allocate one bootstrap page out 5267 * of kernel_map and use it to provide an initial pool of pv_entry 5268 * structures. we never free this page. 5269 */ 5270 pool_setlowat(&pmap_pv_pool, 5271 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5272 5273 pmap_initialized = true; 5274 } 5275 5276 static vaddr_t last_bootstrap_page = 0; 5277 static void *free_bootstrap_pages = NULL; 5278 5279 static void * 5280 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5281 { 5282 extern void *pool_page_alloc(struct pool *, int); 5283 vaddr_t new_page; 5284 void *rv; 5285 5286 if (pmap_initialized) 5287 return (pool_page_alloc(pp, flags)); 5288 5289 if (free_bootstrap_pages) { 5290 rv = free_bootstrap_pages; 5291 free_bootstrap_pages = *((void **)rv); 5292 return (rv); 5293 } 5294 5295 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5296 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5297 5298 KASSERT(new_page > last_bootstrap_page); 5299 last_bootstrap_page = new_page; 5300 return ((void *)new_page); 5301 } 5302 5303 static void 5304 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5305 { 5306 extern void pool_page_free(struct pool *, void *); 5307 5308 if ((vaddr_t)v <= last_bootstrap_page) { 5309 *((void **)v) = free_bootstrap_pages; 5310 free_bootstrap_pages = v; 5311 return; 5312 } 5313 5314 if (pmap_initialized) { 5315 pool_page_free(pp, v); 5316 return; 5317 } 5318 } 5319 5320 /* 5321 * pmap_postinit() 5322 * 5323 * This routine is called after the vm and kmem subsystems have been 5324 * initialised. This allows the pmap code to perform any initialisation 5325 * that can only be done one the memory allocation is in place. 5326 */ 5327 void 5328 pmap_postinit(void) 5329 { 5330 extern paddr_t physical_start, physical_end; 5331 struct l2_bucket *l2b; 5332 struct l1_ttable *l1; 5333 struct pglist plist; 5334 struct vm_page *m; 5335 pd_entry_t *pl1pt; 5336 pt_entry_t *ptep, pte; 5337 vaddr_t va, eva; 5338 u_int loop, needed; 5339 int error; 5340 5341 pool_cache_setlowat(&pmap_l2ptp_cache, 5342 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5343 pool_cache_setlowat(&pmap_l2dtable_cache, 5344 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5345 5346 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5347 needed -= 1; 5348 5349 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5350 5351 for (loop = 0; loop < needed; loop++, l1++) { 5352 /* Allocate a L1 page table */ 5353 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5354 if (va == 0) 5355 panic("Cannot allocate L1 KVM"); 5356 5357 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5358 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5359 if (error) 5360 panic("Cannot allocate L1 physical pages"); 5361 5362 m = TAILQ_FIRST(&plist); 5363 eva = va + L1_TABLE_SIZE; 5364 pl1pt = (pd_entry_t *)va; 5365 5366 while (m && va < eva) { 5367 paddr_t pa = VM_PAGE_TO_PHYS(m); 5368 5369 pmap_kenter_pa(va, pa, 5370 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 5371 5372 /* 5373 * Make sure the L1 descriptor table is mapped 5374 * with the cache-mode set to write-through. 5375 */ 5376 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5377 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5378 pte = *ptep; 5379 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5380 *ptep = pte; 5381 PTE_SYNC(ptep); 5382 cpu_tlb_flushD_SE(va); 5383 5384 va += PAGE_SIZE; 5385 m = TAILQ_NEXT(m, pageq.queue); 5386 } 5387 5388 #ifdef DIAGNOSTIC 5389 if (m) 5390 panic("pmap_alloc_l1pt: pglist not empty"); 5391 #endif /* DIAGNOSTIC */ 5392 5393 pmap_init_l1(l1, pl1pt); 5394 } 5395 5396 #ifdef DEBUG 5397 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5398 needed); 5399 #endif 5400 } 5401 5402 /* 5403 * Note that the following routines are used by board-specific initialisation 5404 * code to configure the initial kernel page tables. 5405 * 5406 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5407 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5408 * behaviour of the old pmap, and provides an easy migration path for 5409 * initial bring-up of the new pmap on existing ports. Fortunately, 5410 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5411 * will be deprecated. 5412 * 5413 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5414 * tables. 5415 */ 5416 5417 /* 5418 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5419 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5420 * find them as necessary. 5421 * 5422 * Note that the data on this list MUST remain valid after initarm() returns, 5423 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5424 */ 5425 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5426 5427 static vaddr_t 5428 kernel_pt_lookup(paddr_t pa) 5429 { 5430 pv_addr_t *pv; 5431 5432 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5433 #ifndef ARM32_NEW_VM_LAYOUT 5434 if (pv->pv_pa == (pa & ~PGOFSET)) 5435 return (pv->pv_va | (pa & PGOFSET)); 5436 #else 5437 if (pv->pv_pa == pa) 5438 return (pv->pv_va); 5439 #endif 5440 } 5441 return (0); 5442 } 5443 5444 /* 5445 * pmap_map_section: 5446 * 5447 * Create a single section mapping. 5448 */ 5449 void 5450 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5451 { 5452 pd_entry_t *pde = (pd_entry_t *) l1pt; 5453 pd_entry_t fl; 5454 5455 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5456 5457 switch (cache) { 5458 case PTE_NOCACHE: 5459 default: 5460 fl = 0; 5461 break; 5462 5463 case PTE_CACHE: 5464 fl = pte_l1_s_cache_mode; 5465 break; 5466 5467 case PTE_PAGETABLE: 5468 fl = pte_l1_s_cache_mode_pt; 5469 break; 5470 } 5471 5472 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5473 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5474 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5475 } 5476 5477 /* 5478 * pmap_map_entry: 5479 * 5480 * Create a single page mapping. 5481 */ 5482 void 5483 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5484 { 5485 pd_entry_t *pde = (pd_entry_t *) l1pt; 5486 pt_entry_t fl; 5487 pt_entry_t *pte; 5488 5489 KASSERT(((va | pa) & PGOFSET) == 0); 5490 5491 switch (cache) { 5492 case PTE_NOCACHE: 5493 default: 5494 fl = 0; 5495 break; 5496 5497 case PTE_CACHE: 5498 fl = pte_l2_s_cache_mode; 5499 break; 5500 5501 case PTE_PAGETABLE: 5502 fl = pte_l2_s_cache_mode_pt; 5503 break; 5504 } 5505 5506 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5507 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5508 5509 #ifndef ARM32_NEW_VM_LAYOUT 5510 pte = (pt_entry_t *) 5511 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5512 #else 5513 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5514 #endif 5515 if (pte == NULL) 5516 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5517 5518 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5519 #ifndef ARM32_NEW_VM_LAYOUT 5520 pte += (va >> PGSHIFT) & 0x3ff; 5521 #else 5522 pte += l2pte_index(va); 5523 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5524 #endif 5525 *pte = fl; 5526 PTE_SYNC(pte); 5527 } 5528 5529 /* 5530 * pmap_link_l2pt: 5531 * 5532 * Link the L2 page table specified by "l2pv" into the L1 5533 * page table at the slot for "va". 5534 */ 5535 void 5536 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5537 { 5538 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5539 u_int slot = va >> L1_S_SHIFT; 5540 5541 #ifndef ARM32_NEW_VM_LAYOUT 5542 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5543 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5544 #endif 5545 5546 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5547 5548 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5549 #ifdef ARM32_NEW_VM_LAYOUT 5550 PTE_SYNC(&pde[slot]); 5551 #else 5552 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5553 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5554 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5555 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5556 #endif 5557 5558 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5559 } 5560 5561 /* 5562 * pmap_map_chunk: 5563 * 5564 * Map a chunk of memory using the most efficient mappings 5565 * possible (section, large page, small page) into the 5566 * provided L1 and L2 tables at the specified virtual address. 5567 */ 5568 vsize_t 5569 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5570 int prot, int cache) 5571 { 5572 pd_entry_t *pde = (pd_entry_t *) l1pt; 5573 pt_entry_t *pte, f1, f2s, f2l; 5574 vsize_t resid; 5575 int i; 5576 5577 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5578 5579 if (l1pt == 0) 5580 panic("pmap_map_chunk: no L1 table provided"); 5581 5582 #ifdef VERBOSE_INIT_ARM 5583 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5584 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5585 #endif 5586 5587 switch (cache) { 5588 case PTE_NOCACHE: 5589 default: 5590 f1 = 0; 5591 f2l = 0; 5592 f2s = 0; 5593 break; 5594 5595 case PTE_CACHE: 5596 f1 = pte_l1_s_cache_mode; 5597 f2l = pte_l2_l_cache_mode; 5598 f2s = pte_l2_s_cache_mode; 5599 break; 5600 5601 case PTE_PAGETABLE: 5602 f1 = pte_l1_s_cache_mode_pt; 5603 f2l = pte_l2_l_cache_mode_pt; 5604 f2s = pte_l2_s_cache_mode_pt; 5605 break; 5606 } 5607 5608 size = resid; 5609 5610 while (resid > 0) { 5611 /* See if we can use a section mapping. */ 5612 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5613 #ifdef VERBOSE_INIT_ARM 5614 printf("S"); 5615 #endif 5616 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5617 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5618 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5619 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5620 va += L1_S_SIZE; 5621 pa += L1_S_SIZE; 5622 resid -= L1_S_SIZE; 5623 continue; 5624 } 5625 5626 /* 5627 * Ok, we're going to use an L2 table. Make sure 5628 * one is actually in the corresponding L1 slot 5629 * for the current VA. 5630 */ 5631 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5632 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5633 5634 #ifndef ARM32_NEW_VM_LAYOUT 5635 pte = (pt_entry_t *) 5636 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5637 #else 5638 pte = (pt_entry_t *) kernel_pt_lookup( 5639 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5640 #endif 5641 if (pte == NULL) 5642 panic("pmap_map_chunk: can't find L2 table for VA" 5643 "0x%08lx", va); 5644 5645 /* See if we can use a L2 large page mapping. */ 5646 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5647 #ifdef VERBOSE_INIT_ARM 5648 printf("L"); 5649 #endif 5650 for (i = 0; i < 16; i++) { 5651 #ifndef ARM32_NEW_VM_LAYOUT 5652 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5653 L2_L_PROTO | pa | 5654 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5655 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5656 #else 5657 pte[l2pte_index(va) + i] = 5658 L2_L_PROTO | pa | 5659 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5660 PTE_SYNC(&pte[l2pte_index(va) + i]); 5661 #endif 5662 } 5663 va += L2_L_SIZE; 5664 pa += L2_L_SIZE; 5665 resid -= L2_L_SIZE; 5666 continue; 5667 } 5668 5669 /* Use a small page mapping. */ 5670 #ifdef VERBOSE_INIT_ARM 5671 printf("P"); 5672 #endif 5673 #ifndef ARM32_NEW_VM_LAYOUT 5674 pte[(va >> PGSHIFT) & 0x3ff] = 5675 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5676 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5677 #else 5678 pte[l2pte_index(va)] = 5679 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5680 PTE_SYNC(&pte[l2pte_index(va)]); 5681 #endif 5682 va += PAGE_SIZE; 5683 pa += PAGE_SIZE; 5684 resid -= PAGE_SIZE; 5685 } 5686 #ifdef VERBOSE_INIT_ARM 5687 printf("\n"); 5688 #endif 5689 return (size); 5690 } 5691 5692 /********************** Static device map routines ***************************/ 5693 5694 static const struct pmap_devmap *pmap_devmap_table; 5695 5696 /* 5697 * Register the devmap table. This is provided in case early console 5698 * initialization needs to register mappings created by bootstrap code 5699 * before pmap_devmap_bootstrap() is called. 5700 */ 5701 void 5702 pmap_devmap_register(const struct pmap_devmap *table) 5703 { 5704 5705 pmap_devmap_table = table; 5706 } 5707 5708 /* 5709 * Map all of the static regions in the devmap table, and remember 5710 * the devmap table so other parts of the kernel can look up entries 5711 * later. 5712 */ 5713 void 5714 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5715 { 5716 int i; 5717 5718 pmap_devmap_table = table; 5719 5720 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5721 #ifdef VERBOSE_INIT_ARM 5722 printf("devmap: %08lx -> %08lx @ %08lx\n", 5723 pmap_devmap_table[i].pd_pa, 5724 pmap_devmap_table[i].pd_pa + 5725 pmap_devmap_table[i].pd_size - 1, 5726 pmap_devmap_table[i].pd_va); 5727 #endif 5728 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5729 pmap_devmap_table[i].pd_pa, 5730 pmap_devmap_table[i].pd_size, 5731 pmap_devmap_table[i].pd_prot, 5732 pmap_devmap_table[i].pd_cache); 5733 } 5734 } 5735 5736 const struct pmap_devmap * 5737 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5738 { 5739 uint64_t endpa; 5740 int i; 5741 5742 if (pmap_devmap_table == NULL) 5743 return (NULL); 5744 5745 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5746 5747 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5748 if (pa >= pmap_devmap_table[i].pd_pa && 5749 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5750 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5751 return (&pmap_devmap_table[i]); 5752 } 5753 5754 return (NULL); 5755 } 5756 5757 const struct pmap_devmap * 5758 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5759 { 5760 int i; 5761 5762 if (pmap_devmap_table == NULL) 5763 return (NULL); 5764 5765 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5766 if (va >= pmap_devmap_table[i].pd_va && 5767 va + size - 1 <= pmap_devmap_table[i].pd_va + 5768 pmap_devmap_table[i].pd_size - 1) 5769 return (&pmap_devmap_table[i]); 5770 } 5771 5772 return (NULL); 5773 } 5774 5775 /********************** PTE initialization routines **************************/ 5776 5777 /* 5778 * These routines are called when the CPU type is identified to set up 5779 * the PTE prototypes, cache modes, etc. 5780 * 5781 * The variables are always here, just in case LKMs need to reference 5782 * them (though, they shouldn't). 5783 */ 5784 5785 pt_entry_t pte_l1_s_cache_mode; 5786 pt_entry_t pte_l1_s_cache_mode_pt; 5787 pt_entry_t pte_l1_s_cache_mask; 5788 5789 pt_entry_t pte_l2_l_cache_mode; 5790 pt_entry_t pte_l2_l_cache_mode_pt; 5791 pt_entry_t pte_l2_l_cache_mask; 5792 5793 pt_entry_t pte_l2_s_cache_mode; 5794 pt_entry_t pte_l2_s_cache_mode_pt; 5795 pt_entry_t pte_l2_s_cache_mask; 5796 5797 pt_entry_t pte_l2_s_prot_u; 5798 pt_entry_t pte_l2_s_prot_w; 5799 pt_entry_t pte_l2_s_prot_mask; 5800 5801 pt_entry_t pte_l1_s_proto; 5802 pt_entry_t pte_l1_c_proto; 5803 pt_entry_t pte_l2_s_proto; 5804 5805 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5806 void (*pmap_zero_page_func)(paddr_t); 5807 5808 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5809 void 5810 pmap_pte_init_generic(void) 5811 { 5812 5813 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5814 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5815 5816 pte_l2_l_cache_mode = L2_B|L2_C; 5817 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5818 5819 pte_l2_s_cache_mode = L2_B|L2_C; 5820 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5821 5822 /* 5823 * If we have a write-through cache, set B and C. If 5824 * we have a write-back cache, then we assume setting 5825 * only C will make those pages write-through. 5826 */ 5827 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5828 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5829 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5830 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5831 } else { 5832 #if ARM_MMU_V6 > 1 5833 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5834 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5835 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5836 #else 5837 pte_l1_s_cache_mode_pt = L1_S_C; 5838 pte_l2_l_cache_mode_pt = L2_C; 5839 pte_l2_s_cache_mode_pt = L2_C; 5840 #endif 5841 } 5842 5843 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5844 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5845 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5846 5847 pte_l1_s_proto = L1_S_PROTO_generic; 5848 pte_l1_c_proto = L1_C_PROTO_generic; 5849 pte_l2_s_proto = L2_S_PROTO_generic; 5850 5851 pmap_copy_page_func = pmap_copy_page_generic; 5852 pmap_zero_page_func = pmap_zero_page_generic; 5853 } 5854 5855 #if defined(CPU_ARM8) 5856 void 5857 pmap_pte_init_arm8(void) 5858 { 5859 5860 /* 5861 * ARM8 is compatible with generic, but we need to use 5862 * the page tables uncached. 5863 */ 5864 pmap_pte_init_generic(); 5865 5866 pte_l1_s_cache_mode_pt = 0; 5867 pte_l2_l_cache_mode_pt = 0; 5868 pte_l2_s_cache_mode_pt = 0; 5869 } 5870 #endif /* CPU_ARM8 */ 5871 5872 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5873 void 5874 pmap_pte_init_arm9(void) 5875 { 5876 5877 /* 5878 * ARM9 is compatible with generic, but we want to use 5879 * write-through caching for now. 5880 */ 5881 pmap_pte_init_generic(); 5882 5883 pte_l1_s_cache_mode = L1_S_C; 5884 pte_l2_l_cache_mode = L2_C; 5885 pte_l2_s_cache_mode = L2_C; 5886 5887 pte_l1_s_cache_mode_pt = L1_S_C; 5888 pte_l2_l_cache_mode_pt = L2_C; 5889 pte_l2_s_cache_mode_pt = L2_C; 5890 } 5891 #endif /* CPU_ARM9 */ 5892 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5893 5894 #if defined(CPU_ARM10) 5895 void 5896 pmap_pte_init_arm10(void) 5897 { 5898 5899 /* 5900 * ARM10 is compatible with generic, but we want to use 5901 * write-through caching for now. 5902 */ 5903 pmap_pte_init_generic(); 5904 5905 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 5906 pte_l2_l_cache_mode = L2_B | L2_C; 5907 pte_l2_s_cache_mode = L2_B | L2_C; 5908 5909 pte_l1_s_cache_mode_pt = L1_S_C; 5910 pte_l2_l_cache_mode_pt = L2_C; 5911 pte_l2_s_cache_mode_pt = L2_C; 5912 5913 } 5914 #endif /* CPU_ARM10 */ 5915 5916 #if ARM_MMU_SA1 == 1 5917 void 5918 pmap_pte_init_sa1(void) 5919 { 5920 5921 /* 5922 * The StrongARM SA-1 cache does not have a write-through 5923 * mode. So, do the generic initialization, then reset 5924 * the page table cache mode to B=1,C=1, and note that 5925 * the PTEs need to be sync'd. 5926 */ 5927 pmap_pte_init_generic(); 5928 5929 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5930 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5931 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5932 5933 pmap_needs_pte_sync = 1; 5934 } 5935 #endif /* ARM_MMU_SA1 == 1*/ 5936 5937 #if ARM_MMU_XSCALE == 1 5938 #if (ARM_NMMUS > 1) 5939 static u_int xscale_use_minidata; 5940 #endif 5941 5942 void 5943 pmap_pte_init_xscale(void) 5944 { 5945 uint32_t auxctl; 5946 int write_through = 0; 5947 5948 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5949 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 5950 5951 pte_l2_l_cache_mode = L2_B|L2_C; 5952 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 5953 5954 pte_l2_s_cache_mode = L2_B|L2_C; 5955 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 5956 5957 pte_l1_s_cache_mode_pt = L1_S_C; 5958 pte_l2_l_cache_mode_pt = L2_C; 5959 pte_l2_s_cache_mode_pt = L2_C; 5960 5961 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 5962 /* 5963 * The XScale core has an enhanced mode where writes that 5964 * miss the cache cause a cache line to be allocated. This 5965 * is significantly faster than the traditional, write-through 5966 * behavior of this case. 5967 */ 5968 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 5969 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 5970 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 5971 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 5972 5973 #ifdef XSCALE_CACHE_WRITE_THROUGH 5974 /* 5975 * Some versions of the XScale core have various bugs in 5976 * their cache units, the work-around for which is to run 5977 * the cache in write-through mode. Unfortunately, this 5978 * has a major (negative) impact on performance. So, we 5979 * go ahead and run fast-and-loose, in the hopes that we 5980 * don't line up the planets in a way that will trip the 5981 * bugs. 5982 * 5983 * However, we give you the option to be slow-but-correct. 5984 */ 5985 write_through = 1; 5986 #elif defined(XSCALE_CACHE_WRITE_BACK) 5987 /* force write back cache mode */ 5988 write_through = 0; 5989 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 5990 /* 5991 * Intel PXA2[15]0 processors are known to have a bug in 5992 * write-back cache on revision 4 and earlier (stepping 5993 * A[01] and B[012]). Fixed for C0 and later. 5994 */ 5995 { 5996 uint32_t id, type; 5997 5998 id = cpufunc_id(); 5999 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6000 6001 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6002 if ((id & CPU_ID_REVISION_MASK) < 5) { 6003 /* write through for stepping A0-1 and B0-2 */ 6004 write_through = 1; 6005 } 6006 } 6007 } 6008 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6009 6010 if (write_through) { 6011 pte_l1_s_cache_mode = L1_S_C; 6012 pte_l2_l_cache_mode = L2_C; 6013 pte_l2_s_cache_mode = L2_C; 6014 } 6015 6016 #if (ARM_NMMUS > 1) 6017 xscale_use_minidata = 1; 6018 #endif 6019 6020 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6021 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6022 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6023 6024 pte_l1_s_proto = L1_S_PROTO_xscale; 6025 pte_l1_c_proto = L1_C_PROTO_xscale; 6026 pte_l2_s_proto = L2_S_PROTO_xscale; 6027 6028 pmap_copy_page_func = pmap_copy_page_xscale; 6029 pmap_zero_page_func = pmap_zero_page_xscale; 6030 6031 /* 6032 * Disable ECC protection of page table access, for now. 6033 */ 6034 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6035 auxctl &= ~XSCALE_AUXCTL_P; 6036 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6037 } 6038 6039 /* 6040 * xscale_setup_minidata: 6041 * 6042 * Set up the mini-data cache clean area. We require the 6043 * caller to allocate the right amount of physically and 6044 * virtually contiguous space. 6045 */ 6046 void 6047 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6048 { 6049 extern vaddr_t xscale_minidata_clean_addr; 6050 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6051 pd_entry_t *pde = (pd_entry_t *) l1pt; 6052 pt_entry_t *pte; 6053 vsize_t size; 6054 uint32_t auxctl; 6055 6056 xscale_minidata_clean_addr = va; 6057 6058 /* Round it to page size. */ 6059 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6060 6061 for (; size != 0; 6062 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6063 #ifndef ARM32_NEW_VM_LAYOUT 6064 pte = (pt_entry_t *) 6065 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6066 #else 6067 pte = (pt_entry_t *) kernel_pt_lookup( 6068 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6069 #endif 6070 if (pte == NULL) 6071 panic("xscale_setup_minidata: can't find L2 table for " 6072 "VA 0x%08lx", va); 6073 #ifndef ARM32_NEW_VM_LAYOUT 6074 pte[(va >> PGSHIFT) & 0x3ff] = 6075 #else 6076 pte[l2pte_index(va)] = 6077 #endif 6078 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6079 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6080 } 6081 6082 /* 6083 * Configure the mini-data cache for write-back with 6084 * read/write-allocate. 6085 * 6086 * NOTE: In order to reconfigure the mini-data cache, we must 6087 * make sure it contains no valid data! In order to do that, 6088 * we must issue a global data cache invalidate command! 6089 * 6090 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6091 * THIS IS VERY IMPORTANT! 6092 */ 6093 6094 /* Invalidate data and mini-data. */ 6095 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6096 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6097 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6098 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6099 } 6100 6101 /* 6102 * Change the PTEs for the specified kernel mappings such that they 6103 * will use the mini data cache instead of the main data cache. 6104 */ 6105 void 6106 pmap_uarea(vaddr_t va) 6107 { 6108 struct l2_bucket *l2b; 6109 pt_entry_t *ptep, *sptep, pte; 6110 vaddr_t next_bucket, eva; 6111 6112 #if (ARM_NMMUS > 1) 6113 if (xscale_use_minidata == 0) 6114 return; 6115 #endif 6116 6117 eva = va + USPACE; 6118 6119 while (va < eva) { 6120 next_bucket = L2_NEXT_BUCKET(va); 6121 if (next_bucket > eva) 6122 next_bucket = eva; 6123 6124 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6125 KDASSERT(l2b != NULL); 6126 6127 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6128 6129 while (va < next_bucket) { 6130 pte = *ptep; 6131 if (!l2pte_minidata(pte)) { 6132 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6133 cpu_tlb_flushD_SE(va); 6134 *ptep = pte & ~L2_B; 6135 } 6136 ptep++; 6137 va += PAGE_SIZE; 6138 } 6139 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6140 } 6141 cpu_cpwait(); 6142 } 6143 #endif /* ARM_MMU_XSCALE == 1 */ 6144 6145 /* 6146 * return the PA of the current L1 table, for use when handling a crash dump 6147 */ 6148 uint32_t pmap_kernel_L1_addr() 6149 { 6150 return pmap_kernel()->pm_l1->l1_physaddr; 6151 } 6152 6153 #if defined(DDB) 6154 /* 6155 * A couple of ddb-callable functions for dumping pmaps 6156 */ 6157 void pmap_dump_all(void); 6158 void pmap_dump(pmap_t); 6159 6160 void 6161 pmap_dump_all(void) 6162 { 6163 pmap_t pm; 6164 6165 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6166 if (pm == pmap_kernel()) 6167 continue; 6168 pmap_dump(pm); 6169 printf("\n"); 6170 } 6171 } 6172 6173 static pt_entry_t ncptes[64]; 6174 static void pmap_dump_ncpg(pmap_t); 6175 6176 void 6177 pmap_dump(pmap_t pm) 6178 { 6179 struct l2_dtable *l2; 6180 struct l2_bucket *l2b; 6181 pt_entry_t *ptep, pte; 6182 vaddr_t l2_va, l2b_va, va; 6183 int i, j, k, occ, rows = 0; 6184 6185 if (pm == pmap_kernel()) 6186 printf("pmap_kernel (%p): ", pm); 6187 else 6188 printf("user pmap (%p): ", pm); 6189 6190 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6191 6192 l2_va = 0; 6193 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6194 l2 = pm->pm_l2[i]; 6195 6196 if (l2 == NULL || l2->l2_occupancy == 0) 6197 continue; 6198 6199 l2b_va = l2_va; 6200 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6201 l2b = &l2->l2_bucket[j]; 6202 6203 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6204 continue; 6205 6206 ptep = l2b->l2b_kva; 6207 6208 for (k = 0; k < 256 && ptep[k] == 0; k++) 6209 ; 6210 6211 k &= ~63; 6212 occ = l2b->l2b_occupancy; 6213 va = l2b_va + (k * 4096); 6214 for (; k < 256; k++, va += 0x1000) { 6215 char ch = ' '; 6216 if ((k % 64) == 0) { 6217 if ((rows % 8) == 0) { 6218 printf( 6219 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6220 } 6221 printf("%08lx: ", va); 6222 } 6223 6224 ncptes[k & 63] = 0; 6225 pte = ptep[k]; 6226 if (pte == 0) { 6227 ch = '.'; 6228 } else { 6229 occ--; 6230 switch (pte & 0x0c) { 6231 case 0x00: 6232 ch = 'D'; /* No cache No buff */ 6233 break; 6234 case 0x04: 6235 ch = 'B'; /* No cache buff */ 6236 break; 6237 case 0x08: 6238 if (pte & 0x40) 6239 ch = 'm'; 6240 else 6241 ch = 'C'; /* Cache No buff */ 6242 break; 6243 case 0x0c: 6244 ch = 'F'; /* Cache Buff */ 6245 break; 6246 } 6247 6248 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6249 ch += 0x20; 6250 6251 if ((pte & 0xc) == 0) 6252 ncptes[k & 63] = pte; 6253 } 6254 6255 if ((k % 64) == 63) { 6256 rows++; 6257 printf("%c\n", ch); 6258 pmap_dump_ncpg(pm); 6259 if (occ == 0) 6260 break; 6261 } else 6262 printf("%c", ch); 6263 } 6264 } 6265 } 6266 } 6267 6268 static void 6269 pmap_dump_ncpg(pmap_t pm) 6270 { 6271 struct vm_page *pg; 6272 struct pv_entry *pv; 6273 int i; 6274 6275 for (i = 0; i < 63; i++) { 6276 if (ncptes[i] == 0) 6277 continue; 6278 6279 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6280 if (pg == NULL) 6281 continue; 6282 6283 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6284 VM_PAGE_TO_PHYS(pg), 6285 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 6286 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 6287 6288 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 6289 printf(" %c va 0x%08lx, flags 0x%x\n", 6290 (pm == pv->pv_pmap) ? '*' : ' ', 6291 pv->pv_va, pv->pv_flags); 6292 } 6293 } 6294 } 6295 #endif 6296 6297 #ifdef PMAP_STEAL_MEMORY 6298 void 6299 pmap_boot_pageadd(pv_addr_t *newpv) 6300 { 6301 pv_addr_t *pv, *npv; 6302 6303 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6304 if (newpv->pv_pa < pv->pv_va) { 6305 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6306 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6307 newpv->pv_size += pv->pv_size; 6308 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6309 } 6310 pv = NULL; 6311 } else { 6312 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6313 pv = npv) { 6314 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6315 KASSERT(pv->pv_pa < newpv->pv_pa); 6316 if (newpv->pv_pa > npv->pv_pa) 6317 continue; 6318 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6319 pv->pv_size += newpv->pv_size; 6320 return; 6321 } 6322 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6323 break; 6324 newpv->pv_size += npv->pv_size; 6325 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6326 SLIST_REMOVE_AFTER(newpv, pv_list); 6327 return; 6328 } 6329 } 6330 } 6331 6332 if (pv) { 6333 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6334 } else { 6335 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6336 } 6337 } 6338 6339 void 6340 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6341 pv_addr_t *rpv) 6342 { 6343 pv_addr_t *pv, **pvp; 6344 struct vm_physseg *ps; 6345 size_t i; 6346 6347 KASSERT(amount & PGOFSET); 6348 KASSERT((mask & PGOFSET) == 0); 6349 KASSERT((match & PGOFSET) == 0); 6350 KASSERT(amount != 0); 6351 6352 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6353 (pv = *pvp) != NULL; 6354 pvp = &SLIST_NEXT(pv, pv_list)) { 6355 pv_addr_t *newpv; 6356 psize_t off; 6357 /* 6358 * If this entry is too small to satify the request... 6359 */ 6360 KASSERT(pv->pv_size > 0); 6361 if (pv->pv_size < amount) 6362 continue; 6363 6364 for (off = 0; off <= mask; off += PAGE_SIZE) { 6365 if (((pv->pv_pa + off) & mask) == match 6366 && off + amount <= pv->pv_size) 6367 break; 6368 } 6369 if (off > mask) 6370 continue; 6371 6372 rpv->pv_va = pv->pv_va + off; 6373 rpv->pv_pa = pv->pv_pa + off; 6374 rpv->pv_size = amount; 6375 pv->pv_size -= amount; 6376 if (pv->pv_size == 0) { 6377 KASSERT(off == 0); 6378 KASSERT((vaddr_t) pv == rpv->pv_va); 6379 *pvp = SLIST_NEXT(pv, pv_list); 6380 } else if (off == 0) { 6381 KASSERT((vaddr_t) pv == rpv->pv_va); 6382 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6383 *newpv = *pv; 6384 newpv->pv_pa += amount; 6385 newpv->pv_va += amount; 6386 *pvp = newpv; 6387 } else if (off < pv->pv_size) { 6388 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6389 *newpv = *pv; 6390 newpv->pv_size -= off; 6391 newpv->pv_pa += off + amount; 6392 newpv->pv_va += off + amount; 6393 6394 SLIST_NEXT(pv, pv_list) = newpv; 6395 pv->pv_size = off; 6396 } else { 6397 KASSERT((vaddr_t) pv != rpv->pv_va); 6398 } 6399 memset((void *)rpv->pv_va, 0, amount); 6400 return; 6401 } 6402 6403 if (vm_nphysseg == 0) 6404 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6405 6406 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6407 (pv = *pvp) != NULL; 6408 pvp = &SLIST_NEXT(pv, pv_list)) { 6409 if (SLIST_NEXT(pv, pv_list) == NULL) 6410 break; 6411 } 6412 KASSERT(mask == 0); 6413 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6414 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6415 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6416 rpv->pv_va = pv->pv_va; 6417 rpv->pv_pa = pv->pv_pa; 6418 rpv->pv_size = amount; 6419 *pvp = NULL; 6420 pmap_map_chunk(kernel_l1pt.pv_va, 6421 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6422 ptoa(ps->avail_start), 6423 amount - pv->pv_size, 6424 VM_PROT_READ|VM_PROT_WRITE, 6425 PTE_CACHE); 6426 ps->avail_start += atop(amount - pv->pv_size); 6427 /* 6428 * If we consumed the entire physseg, remove it. 6429 */ 6430 if (ps->avail_start == ps->avail_end) { 6431 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6432 ps[0] = ps[1]; 6433 } 6434 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6435 return; 6436 } 6437 } 6438 6439 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6440 } 6441 6442 vaddr_t 6443 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6444 { 6445 pv_addr_t pv; 6446 6447 pmap_boot_pagealloc(size, 0, 0, &pv); 6448 6449 return pv.pv_va; 6450 } 6451 #endif /* PMAP_STEAL_MEMORY */ 6452
Indexes created Fri Sep 26 20:09:58 GMT 2025