pmap.c revision 1.186
1 /* $NetBSD: pmap.c,v 1.186 2008/08/14 14:54:32 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/user.h> 202 #include <sys/pool.h> 203 #include <sys/cdefs.h> 204 #include <sys/cpu.h> 205 #include <sys/sysctl.h> 206 207 #include <uvm/uvm.h> 208 209 #include <machine/bus.h> 210 #include <machine/pmap.h> 211 #include <machine/pcb.h> 212 #include <machine/param.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.186 2008/08/14 14:54:32 matt Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 #define PDB_EXEC 0x80000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 struct pmap kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 #ifdef PMAPCOUNTERS 308 #define PMAP_EVCNT_INITIALIZER(name) \ 309 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 310 311 #ifdef PMAP_CACHE_VIPT 312 static struct evcnt pmap_ev_vac_color_new = 313 PMAP_EVCNT_INITIALIZER("new page color"); 314 static struct evcnt pmap_ev_vac_color_reuse = 315 PMAP_EVCNT_INITIALIZER("ok first page color"); 316 static struct evcnt pmap_ev_vac_color_ok = 317 PMAP_EVCNT_INITIALIZER("ok page color"); 318 static struct evcnt pmap_ev_vac_color_blind = 319 PMAP_EVCNT_INITIALIZER("blind page color"); 320 static struct evcnt pmap_ev_vac_color_change = 321 PMAP_EVCNT_INITIALIZER("change page color"); 322 static struct evcnt pmap_ev_vac_color_erase = 323 PMAP_EVCNT_INITIALIZER("erase page color"); 324 static struct evcnt pmap_ev_vac_color_none = 325 PMAP_EVCNT_INITIALIZER("no page color"); 326 static struct evcnt pmap_ev_vac_color_restore = 327 PMAP_EVCNT_INITIALIZER("restore page color"); 328 329 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 330 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 331 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 332 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 333 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 334 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 335 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 336 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 337 #endif 338 339 static struct evcnt pmap_ev_mappings = 340 PMAP_EVCNT_INITIALIZER("pages mapped"); 341 static struct evcnt pmap_ev_unmappings = 342 PMAP_EVCNT_INITIALIZER("pages unmapped"); 343 static struct evcnt pmap_ev_remappings = 344 PMAP_EVCNT_INITIALIZER("pages remapped"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 347 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 348 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 349 350 static struct evcnt pmap_ev_kernel_mappings = 351 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 352 static struct evcnt pmap_ev_kernel_unmappings = 353 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 354 static struct evcnt pmap_ev_kernel_remappings = 355 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 356 357 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 358 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 359 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 360 361 static struct evcnt pmap_ev_kenter_mappings = 362 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 363 static struct evcnt pmap_ev_kenter_unmappings = 364 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 365 static struct evcnt pmap_ev_kenter_remappings = 366 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 367 static struct evcnt pmap_ev_pt_mappings = 368 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 373 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 374 375 #ifdef PMAP_CACHE_VIPT 376 static struct evcnt pmap_ev_exec_mappings = 377 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 378 static struct evcnt pmap_ev_exec_cached = 379 PMAP_EVCNT_INITIALIZER("exec pages cached"); 380 381 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 382 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 383 384 static struct evcnt pmap_ev_exec_synced = 385 PMAP_EVCNT_INITIALIZER("exec pages synced"); 386 static struct evcnt pmap_ev_exec_synced_map = 387 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 388 static struct evcnt pmap_ev_exec_synced_unmap = 389 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 390 static struct evcnt pmap_ev_exec_synced_remap = 391 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 392 static struct evcnt pmap_ev_exec_synced_clearbit = 393 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 394 static struct evcnt pmap_ev_exec_synced_kremove = 395 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 396 397 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 399 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 400 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 401 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 402 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 403 404 static struct evcnt pmap_ev_exec_discarded_unmap = 405 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 406 static struct evcnt pmap_ev_exec_discarded_zero = 407 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 408 static struct evcnt pmap_ev_exec_discarded_copy = 409 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 410 static struct evcnt pmap_ev_exec_discarded_page_protect = 411 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 412 static struct evcnt pmap_ev_exec_discarded_clearbit = 413 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 414 static struct evcnt pmap_ev_exec_discarded_kremove = 415 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 416 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 422 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 423 #endif /* PMAP_CACHE_VIPT */ 424 425 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 426 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 427 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 428 429 EVCNT_ATTACH_STATIC(pmap_ev_updates); 430 EVCNT_ATTACH_STATIC(pmap_ev_collects); 431 EVCNT_ATTACH_STATIC(pmap_ev_activations); 432 433 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 434 #else 435 #define PMAPCOUNT(x) ((void)0) 436 #endif 437 438 /* 439 * pmap copy/zero page, and mem(5) hook point 440 */ 441 static pt_entry_t *csrc_pte, *cdst_pte; 442 static vaddr_t csrcp, cdstp; 443 vaddr_t memhook; /* used by mem.c */ 444 extern void *msgbufaddr; 445 int pmap_kmpages; 446 /* 447 * Flag to indicate if pmap_init() has done its thing 448 */ 449 bool pmap_initialized; 450 451 /* 452 * Misc. locking data structures 453 */ 454 455 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 456 static struct lock pmap_main_lock; 457 458 #define PMAP_MAP_TO_HEAD_LOCK() \ 459 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 460 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 461 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 462 #define PMAP_HEAD_TO_MAP_LOCK() \ 463 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 464 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 465 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 466 #else 467 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 468 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 469 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 470 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 471 #endif 472 473 #define pmap_acquire_pmap_lock(pm) \ 474 do { \ 475 if ((pm) != pmap_kernel()) \ 476 mutex_enter(&(pm)->pm_lock); \ 477 } while (/*CONSTCOND*/0) 478 479 #define pmap_release_pmap_lock(pm) \ 480 do { \ 481 if ((pm) != pmap_kernel()) \ 482 mutex_exit(&(pm)->pm_lock); \ 483 } while (/*CONSTCOND*/0) 484 485 486 /* 487 * Metadata for L1 translation tables. 488 */ 489 struct l1_ttable { 490 /* Entry on the L1 Table list */ 491 SLIST_ENTRY(l1_ttable) l1_link; 492 493 /* Entry on the L1 Least Recently Used list */ 494 TAILQ_ENTRY(l1_ttable) l1_lru; 495 496 /* Track how many domains are allocated from this L1 */ 497 volatile u_int l1_domain_use_count; 498 499 /* 500 * A free-list of domain numbers for this L1. 501 * We avoid using ffs() and a bitmap to track domains since ffs() 502 * is slow on ARM. 503 */ 504 u_int8_t l1_domain_first; 505 u_int8_t l1_domain_free[PMAP_DOMAINS]; 506 507 /* Physical address of this L1 page table */ 508 paddr_t l1_physaddr; 509 510 /* KVA of this L1 page table */ 511 pd_entry_t *l1_kva; 512 }; 513 514 /* 515 * Convert a virtual address into its L1 table index. That is, the 516 * index used to locate the L2 descriptor table pointer in an L1 table. 517 * This is basically used to index l1->l1_kva[]. 518 * 519 * Each L2 descriptor table represents 1MB of VA space. 520 */ 521 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 522 523 /* 524 * L1 Page Tables are tracked using a Least Recently Used list. 525 * - New L1s are allocated from the HEAD. 526 * - Freed L1s are added to the TAIl. 527 * - Recently accessed L1s (where an 'access' is some change to one of 528 * the userland pmaps which owns this L1) are moved to the TAIL. 529 */ 530 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 531 static struct simplelock l1_lru_lock; 532 533 /* 534 * A list of all L1 tables 535 */ 536 static SLIST_HEAD(, l1_ttable) l1_list; 537 538 /* 539 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 540 * 541 * This is normally 16MB worth L2 page descriptors for any given pmap. 542 * Reference counts are maintained for L2 descriptors so they can be 543 * freed when empty. 544 */ 545 struct l2_dtable { 546 /* The number of L2 page descriptors allocated to this l2_dtable */ 547 u_int l2_occupancy; 548 549 /* List of L2 page descriptors */ 550 struct l2_bucket { 551 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 552 paddr_t l2b_phys; /* Physical address of same */ 553 u_short l2b_l1idx; /* This L2 table's L1 index */ 554 u_short l2b_occupancy; /* How many active descriptors */ 555 } l2_bucket[L2_BUCKET_SIZE]; 556 }; 557 558 /* 559 * Given an L1 table index, calculate the corresponding l2_dtable index 560 * and bucket index within the l2_dtable. 561 */ 562 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 563 (L2_SIZE - 1)) 564 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 565 566 /* 567 * Given a virtual address, this macro returns the 568 * virtual address required to drop into the next L2 bucket. 569 */ 570 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 571 572 /* 573 * L2 allocation. 574 */ 575 #define pmap_alloc_l2_dtable() \ 576 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 577 #define pmap_free_l2_dtable(l2) \ 578 pool_cache_put(&pmap_l2dtable_cache, (l2)) 579 #define pmap_alloc_l2_ptp(pap) \ 580 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 581 PR_NOWAIT, (pap))) 582 583 /* 584 * We try to map the page tables write-through, if possible. However, not 585 * all CPUs have a write-through cache mode, so on those we have to sync 586 * the cache when we frob page tables. 587 * 588 * We try to evaluate this at compile time, if possible. However, it's 589 * not always possible to do that, hence this run-time var. 590 */ 591 int pmap_needs_pte_sync; 592 593 /* 594 * Real definition of pv_entry. 595 */ 596 struct pv_entry { 597 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 598 pmap_t pv_pmap; /* pmap where mapping lies */ 599 vaddr_t pv_va; /* virtual address for mapping */ 600 u_int pv_flags; /* flags */ 601 }; 602 603 /* 604 * Macro to determine if a mapping might be resident in the 605 * instruction cache and/or TLB 606 */ 607 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 608 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 609 610 /* 611 * Macro to determine if a mapping might be resident in the 612 * data cache and/or TLB 613 */ 614 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 615 616 /* 617 * Local prototypes 618 */ 619 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 620 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 621 pt_entry_t **); 622 static bool pmap_is_current(pmap_t); 623 static bool pmap_is_cached(pmap_t); 624 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 625 pmap_t, vaddr_t, u_int); 626 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 627 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 628 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 629 u_int, u_int); 630 631 static void pmap_pinit(pmap_t); 632 static int pmap_pmap_ctor(void *, void *, int); 633 634 static void pmap_alloc_l1(pmap_t); 635 static void pmap_free_l1(pmap_t); 636 static void pmap_use_l1(pmap_t); 637 638 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 639 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 640 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 641 static int pmap_l2ptp_ctor(void *, void *, int); 642 static int pmap_l2dtable_ctor(void *, void *, int); 643 644 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 645 #ifdef PMAP_CACHE_VIVT 646 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 647 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 648 #endif 649 650 static void pmap_clearbit(struct vm_page *, u_int); 651 #ifdef PMAP_CACHE_VIVT 652 static int pmap_clean_page(struct pv_entry *, bool); 653 #endif 654 #ifdef PMAP_CACHE_VIPT 655 static void pmap_syncicache_page(struct vm_page *); 656 static void pmap_flush_page(struct vm_page *, bool); 657 #endif 658 static void pmap_page_remove(struct vm_page *); 659 660 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 661 static vaddr_t kernel_pt_lookup(paddr_t); 662 663 664 /* 665 * External function prototypes 666 */ 667 extern void bzero_page(vaddr_t); 668 extern void bcopy_page(vaddr_t, vaddr_t); 669 670 /* 671 * Misc variables 672 */ 673 vaddr_t virtual_avail; 674 vaddr_t virtual_end; 675 vaddr_t pmap_curmaxkvaddr; 676 677 vaddr_t avail_start; 678 vaddr_t avail_end; 679 680 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 681 pv_addr_t kernelpages; 682 pv_addr_t kernel_l1pt; 683 pv_addr_t systempage; 684 685 /* Function to set the debug level of the pmap code */ 686 687 #ifdef PMAP_DEBUG 688 void 689 pmap_debug(int level) 690 { 691 pmap_debug_level = level; 692 printf("pmap_debug: level=%d\n", pmap_debug_level); 693 } 694 #endif /* PMAP_DEBUG */ 695 696 /* 697 * A bunch of routines to conditionally flush the caches/TLB depending 698 * on whether the specified pmap actually needs to be flushed at any 699 * given time. 700 */ 701 static inline void 702 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 703 { 704 705 if (pm->pm_cstate.cs_tlb_id) 706 cpu_tlb_flushID_SE(va); 707 } 708 709 static inline void 710 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 711 { 712 713 if (pm->pm_cstate.cs_tlb_d) 714 cpu_tlb_flushD_SE(va); 715 } 716 717 static inline void 718 pmap_tlb_flushID(pmap_t pm) 719 { 720 721 if (pm->pm_cstate.cs_tlb_id) { 722 cpu_tlb_flushID(); 723 pm->pm_cstate.cs_tlb = 0; 724 } 725 } 726 727 static inline void 728 pmap_tlb_flushD(pmap_t pm) 729 { 730 731 if (pm->pm_cstate.cs_tlb_d) { 732 cpu_tlb_flushD(); 733 pm->pm_cstate.cs_tlb_d = 0; 734 } 735 } 736 737 #ifdef PMAP_CACHE_VIVT 738 static inline void 739 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 740 { 741 if (pm->pm_cstate.cs_cache_id) { 742 cpu_idcache_wbinv_range(va, len); 743 } 744 } 745 746 static inline void 747 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 748 bool do_inv, bool rd_only) 749 { 750 751 if (pm->pm_cstate.cs_cache_d) { 752 if (do_inv) { 753 if (rd_only) 754 cpu_dcache_inv_range(va, len); 755 else 756 cpu_dcache_wbinv_range(va, len); 757 } else 758 if (!rd_only) 759 cpu_dcache_wb_range(va, len); 760 } 761 } 762 763 static inline void 764 pmap_idcache_wbinv_all(pmap_t pm) 765 { 766 if (pm->pm_cstate.cs_cache_id) { 767 cpu_idcache_wbinv_all(); 768 pm->pm_cstate.cs_cache = 0; 769 } 770 } 771 772 static inline void 773 pmap_dcache_wbinv_all(pmap_t pm) 774 { 775 if (pm->pm_cstate.cs_cache_d) { 776 cpu_dcache_wbinv_all(); 777 pm->pm_cstate.cs_cache_d = 0; 778 } 779 } 780 #endif /* PMAP_CACHE_VIVT */ 781 782 static inline bool 783 pmap_is_current(pmap_t pm) 784 { 785 786 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 787 return true; 788 789 return false; 790 } 791 792 static inline bool 793 pmap_is_cached(pmap_t pm) 794 { 795 796 if (pm == pmap_kernel() || pmap_recent_user == NULL || 797 pmap_recent_user == pm) 798 return (true); 799 800 return false; 801 } 802 803 /* 804 * PTE_SYNC_CURRENT: 805 * 806 * Make sure the pte is written out to RAM. 807 * We need to do this for one of two cases: 808 * - We're dealing with the kernel pmap 809 * - There is no pmap active in the cache/tlb. 810 * - The specified pmap is 'active' in the cache/tlb. 811 */ 812 #ifdef PMAP_INCLUDE_PTE_SYNC 813 #define PTE_SYNC_CURRENT(pm, ptep) \ 814 do { \ 815 if (PMAP_NEEDS_PTE_SYNC && \ 816 pmap_is_cached(pm)) \ 817 PTE_SYNC(ptep); \ 818 } while (/*CONSTCOND*/0) 819 #else 820 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 821 #endif 822 823 /* 824 * main pv_entry manipulation functions: 825 * pmap_enter_pv: enter a mapping onto a vm_page list 826 * pmap_remove_pv: remove a mappiing from a vm_page list 827 * 828 * NOTE: pmap_enter_pv expects to lock the pvh itself 829 * pmap_remove_pv expects te caller to lock the pvh before calling 830 */ 831 832 /* 833 * pmap_enter_pv: enter a mapping onto a vm_page lst 834 * 835 * => caller should hold the proper lock on pmap_main_lock 836 * => caller should have pmap locked 837 * => we will gain the lock on the vm_page and allocate the new pv_entry 838 * => caller should adjust ptp's wire_count before calling 839 * => caller should not adjust pmap's wire_count 840 */ 841 static void 842 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 843 vaddr_t va, u_int flags) 844 { 845 struct pv_entry **pvp; 846 847 NPDEBUG(PDB_PVDUMP, 848 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 849 850 pve->pv_pmap = pm; 851 pve->pv_va = va; 852 pve->pv_flags = flags; 853 854 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 855 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 856 #ifdef PMAP_CACHE_VIPT 857 /* 858 * Insert unmanaged entries, writeable first, at the head of 859 * the pv list. 860 */ 861 if (__predict_true((flags & PVF_KENTRY) == 0)) { 862 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 863 pvp = &SLIST_NEXT(*pvp, pv_link); 864 } else if ((flags & PVF_WRITE) == 0) { 865 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 866 pvp = &SLIST_NEXT(*pvp, pv_link); 867 } 868 #endif 869 SLIST_NEXT(pve, pv_link) = *pvp; /* add to ... */ 870 *pvp = pve; /* ... locked list */ 871 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 872 #ifdef PMAP_CACHE_VIPT 873 if ((pve->pv_flags & PVF_KWRITE) == PVF_KWRITE) 874 pg->mdpage.pvh_attrs |= PVF_KMOD; 875 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 876 pg->mdpage.pvh_attrs |= PVF_DIRTY; 877 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 878 #endif 879 if (pm == pmap_kernel()) { 880 PMAPCOUNT(kernel_mappings); 881 if (flags & PVF_WRITE) 882 pg->mdpage.krw_mappings++; 883 else 884 pg->mdpage.kro_mappings++; 885 } else 886 if (flags & PVF_WRITE) 887 pg->mdpage.urw_mappings++; 888 else 889 pg->mdpage.uro_mappings++; 890 891 #ifdef PMAP_CACHE_VIPT 892 /* 893 * If this is an exec mapping and its the first exec mapping 894 * for this page, make sure to sync the I-cache. 895 */ 896 if (PV_IS_EXEC_P(flags)) { 897 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 898 pmap_syncicache_page(pg); 899 PMAPCOUNT(exec_synced_map); 900 } 901 PMAPCOUNT(exec_mappings); 902 } 903 #endif 904 905 PMAPCOUNT(mappings); 906 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 907 908 if (pve->pv_flags & PVF_WIRED) 909 ++pm->pm_stats.wired_count; 910 } 911 912 /* 913 * 914 * pmap_find_pv: Find a pv entry 915 * 916 * => caller should hold lock on vm_page 917 */ 918 static inline struct pv_entry * 919 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 920 { 921 struct pv_entry *pv; 922 923 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 924 if (pm == pv->pv_pmap && va == pv->pv_va) 925 break; 926 } 927 928 return (pv); 929 } 930 931 /* 932 * pmap_remove_pv: try to remove a mapping from a pv_list 933 * 934 * => caller should hold proper lock on pmap_main_lock 935 * => pmap should be locked 936 * => caller should hold lock on vm_page [so that attrs can be adjusted] 937 * => caller should adjust ptp's wire_count and free PTP if needed 938 * => caller should NOT adjust pmap's wire_count 939 * => we return the removed pve 940 */ 941 static struct pv_entry * 942 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 943 { 944 struct pv_entry *pve, **prevptr; 945 946 NPDEBUG(PDB_PVDUMP, 947 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 948 949 prevptr = &SLIST_FIRST(&pg->mdpage.pvh_list); /* prev pv_entry ptr */ 950 pve = *prevptr; 951 952 while (pve) { 953 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 954 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 955 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 956 if (pve->pv_flags & PVF_WIRED) { 957 if (skip_wired) 958 return (NULL); 959 --pm->pm_stats.wired_count; 960 } 961 *prevptr = SLIST_NEXT(pve, pv_link); /* remove it! */ 962 if (pm == pmap_kernel()) { 963 PMAPCOUNT(kernel_unmappings); 964 if (pve->pv_flags & PVF_WRITE) 965 pg->mdpage.krw_mappings--; 966 else 967 pg->mdpage.kro_mappings--; 968 } else 969 if (pve->pv_flags & PVF_WRITE) 970 pg->mdpage.urw_mappings--; 971 else 972 pg->mdpage.uro_mappings--; 973 974 PMAPCOUNT(unmappings); 975 #ifdef PMAP_CACHE_VIPT 976 if (!(pve->pv_flags & PVF_WRITE)) 977 break; 978 /* 979 * If this page has had an exec mapping, then if 980 * this was the last mapping, discard the contents, 981 * otherwise sync the i-cache for this page. 982 */ 983 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 984 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 985 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 986 PMAPCOUNT(exec_discarded_unmap); 987 } else { 988 pmap_syncicache_page(pg); 989 PMAPCOUNT(exec_synced_unmap); 990 } 991 } 992 #endif /* PMAP_CACHE_VIPT */ 993 break; 994 } 995 prevptr = &SLIST_NEXT(pve, pv_link); /* previous pointer */ 996 pve = *prevptr; /* advance */ 997 } 998 999 #ifdef PMAP_CACHE_VIPT 1000 /* 1001 * If we no longer have a WRITEABLE KENTRY at the head of list, 1002 * clear the KMOD attribute from the page. 1003 */ 1004 if (SLIST_FIRST(&pg->mdpage.pvh_list) == NULL 1005 || (SLIST_FIRST(&pg->mdpage.pvh_list)->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1006 pg->mdpage.pvh_attrs &= ~PVF_KMOD; 1007 1008 /* 1009 * If this was a writeable page and there are no more writeable 1010 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1011 * the contents to memory. 1012 */ 1013 if (pg->mdpage.krw_mappings + pg->mdpage.urw_mappings == 0) 1014 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1015 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1016 #endif /* PMAP_CACHE_VIPT */ 1017 1018 return(pve); /* return removed pve */ 1019 } 1020 1021 /* 1022 * 1023 * pmap_modify_pv: Update pv flags 1024 * 1025 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1026 * => caller should NOT adjust pmap's wire_count 1027 * => caller must call pmap_vac_me_harder() if writable status of a page 1028 * may have changed. 1029 * => we return the old flags 1030 * 1031 * Modify a physical-virtual mapping in the pv table 1032 */ 1033 static u_int 1034 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 1035 u_int clr_mask, u_int set_mask) 1036 { 1037 struct pv_entry *npv; 1038 u_int flags, oflags; 1039 1040 KASSERT((clr_mask & PVF_KENTRY) == 0); 1041 KASSERT((set_mask & PVF_KENTRY) == 0); 1042 1043 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1044 return (0); 1045 1046 NPDEBUG(PDB_PVDUMP, 1047 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 1048 1049 /* 1050 * There is at least one VA mapping this page. 1051 */ 1052 1053 if (clr_mask & (PVF_REF | PVF_MOD)) { 1054 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1055 #ifdef PMAP_CACHE_VIPT 1056 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1057 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1058 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1059 #endif 1060 } 1061 1062 oflags = npv->pv_flags; 1063 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1064 1065 if ((flags ^ oflags) & PVF_WIRED) { 1066 if (flags & PVF_WIRED) 1067 ++pm->pm_stats.wired_count; 1068 else 1069 --pm->pm_stats.wired_count; 1070 } 1071 1072 if ((flags ^ oflags) & PVF_WRITE) { 1073 if (pm == pmap_kernel()) { 1074 if (flags & PVF_WRITE) { 1075 pg->mdpage.krw_mappings++; 1076 pg->mdpage.kro_mappings--; 1077 } else { 1078 pg->mdpage.kro_mappings++; 1079 pg->mdpage.krw_mappings--; 1080 } 1081 } else 1082 if (flags & PVF_WRITE) { 1083 pg->mdpage.urw_mappings++; 1084 pg->mdpage.uro_mappings--; 1085 } else { 1086 pg->mdpage.uro_mappings++; 1087 pg->mdpage.urw_mappings--; 1088 } 1089 } 1090 #ifdef PMAP_CACHE_VIPT 1091 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 1092 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1093 /* 1094 * We have two cases here: the first is from enter_pv (new exec 1095 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1096 * Since in latter, pmap_enter_pv won't do anything, we just have 1097 * to do what pmap_remove_pv would do. 1098 */ 1099 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1100 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1101 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1102 pmap_syncicache_page(pg); 1103 PMAPCOUNT(exec_synced_remap); 1104 } 1105 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1106 #endif 1107 1108 PMAPCOUNT(remappings); 1109 1110 return (oflags); 1111 } 1112 1113 /* 1114 * Allocate an L1 translation table for the specified pmap. 1115 * This is called at pmap creation time. 1116 */ 1117 static void 1118 pmap_alloc_l1(pmap_t pm) 1119 { 1120 struct l1_ttable *l1; 1121 u_int8_t domain; 1122 1123 /* 1124 * Remove the L1 at the head of the LRU list 1125 */ 1126 simple_lock(&l1_lru_lock); 1127 l1 = TAILQ_FIRST(&l1_lru_list); 1128 KDASSERT(l1 != NULL); 1129 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1130 1131 /* 1132 * Pick the first available domain number, and update 1133 * the link to the next number. 1134 */ 1135 domain = l1->l1_domain_first; 1136 l1->l1_domain_first = l1->l1_domain_free[domain]; 1137 1138 /* 1139 * If there are still free domain numbers in this L1, 1140 * put it back on the TAIL of the LRU list. 1141 */ 1142 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1143 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1144 1145 simple_unlock(&l1_lru_lock); 1146 1147 /* 1148 * Fix up the relevant bits in the pmap structure 1149 */ 1150 pm->pm_l1 = l1; 1151 pm->pm_domain = domain; 1152 } 1153 1154 /* 1155 * Free an L1 translation table. 1156 * This is called at pmap destruction time. 1157 */ 1158 static void 1159 pmap_free_l1(pmap_t pm) 1160 { 1161 struct l1_ttable *l1 = pm->pm_l1; 1162 1163 simple_lock(&l1_lru_lock); 1164 1165 /* 1166 * If this L1 is currently on the LRU list, remove it. 1167 */ 1168 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1169 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1170 1171 /* 1172 * Free up the domain number which was allocated to the pmap 1173 */ 1174 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1175 l1->l1_domain_first = pm->pm_domain; 1176 l1->l1_domain_use_count--; 1177 1178 /* 1179 * The L1 now must have at least 1 free domain, so add 1180 * it back to the LRU list. If the use count is zero, 1181 * put it at the head of the list, otherwise it goes 1182 * to the tail. 1183 */ 1184 if (l1->l1_domain_use_count == 0) 1185 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1186 else 1187 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1188 1189 simple_unlock(&l1_lru_lock); 1190 } 1191 1192 static inline void 1193 pmap_use_l1(pmap_t pm) 1194 { 1195 struct l1_ttable *l1; 1196 1197 /* 1198 * Do nothing if we're in interrupt context. 1199 * Access to an L1 by the kernel pmap must not affect 1200 * the LRU list. 1201 */ 1202 if (cpu_intr_p() || pm == pmap_kernel()) 1203 return; 1204 1205 l1 = pm->pm_l1; 1206 1207 /* 1208 * If the L1 is not currently on the LRU list, just return 1209 */ 1210 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1211 return; 1212 1213 simple_lock(&l1_lru_lock); 1214 1215 /* 1216 * Check the use count again, now that we've acquired the lock 1217 */ 1218 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1219 simple_unlock(&l1_lru_lock); 1220 return; 1221 } 1222 1223 /* 1224 * Move the L1 to the back of the LRU list 1225 */ 1226 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1227 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1228 1229 simple_unlock(&l1_lru_lock); 1230 } 1231 1232 /* 1233 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1234 * 1235 * Free an L2 descriptor table. 1236 */ 1237 static inline void 1238 #ifndef PMAP_INCLUDE_PTE_SYNC 1239 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1240 #else 1241 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1242 #endif 1243 { 1244 #ifdef PMAP_INCLUDE_PTE_SYNC 1245 #ifdef PMAP_CACHE_VIVT 1246 /* 1247 * Note: With a write-back cache, we may need to sync this 1248 * L2 table before re-using it. 1249 * This is because it may have belonged to a non-current 1250 * pmap, in which case the cache syncs would have been 1251 * skipped for the pages that were being unmapped. If the 1252 * L2 table were then to be immediately re-allocated to 1253 * the *current* pmap, it may well contain stale mappings 1254 * which have not yet been cleared by a cache write-back 1255 * and so would still be visible to the mmu. 1256 */ 1257 if (need_sync) 1258 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1259 #endif /* PMAP_CACHE_VIVT */ 1260 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1261 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1262 } 1263 1264 /* 1265 * Returns a pointer to the L2 bucket associated with the specified pmap 1266 * and VA, or NULL if no L2 bucket exists for the address. 1267 */ 1268 static inline struct l2_bucket * 1269 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1270 { 1271 struct l2_dtable *l2; 1272 struct l2_bucket *l2b; 1273 u_short l1idx; 1274 1275 l1idx = L1_IDX(va); 1276 1277 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1278 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1279 return (NULL); 1280 1281 return (l2b); 1282 } 1283 1284 /* 1285 * Returns a pointer to the L2 bucket associated with the specified pmap 1286 * and VA. 1287 * 1288 * If no L2 bucket exists, perform the necessary allocations to put an L2 1289 * bucket/page table in place. 1290 * 1291 * Note that if a new L2 bucket/page was allocated, the caller *must* 1292 * increment the bucket occupancy counter appropriately *before* 1293 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1294 * the bucket/page in the meantime. 1295 */ 1296 static struct l2_bucket * 1297 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1298 { 1299 struct l2_dtable *l2; 1300 struct l2_bucket *l2b; 1301 u_short l1idx; 1302 1303 l1idx = L1_IDX(va); 1304 1305 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1306 /* 1307 * No mapping at this address, as there is 1308 * no entry in the L1 table. 1309 * Need to allocate a new l2_dtable. 1310 */ 1311 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1312 return (NULL); 1313 1314 /* 1315 * Link it into the parent pmap 1316 */ 1317 pm->pm_l2[L2_IDX(l1idx)] = l2; 1318 } 1319 1320 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1321 1322 /* 1323 * Fetch pointer to the L2 page table associated with the address. 1324 */ 1325 if (l2b->l2b_kva == NULL) { 1326 pt_entry_t *ptep; 1327 1328 /* 1329 * No L2 page table has been allocated. Chances are, this 1330 * is because we just allocated the l2_dtable, above. 1331 */ 1332 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1333 /* 1334 * Oops, no more L2 page tables available at this 1335 * time. We may need to deallocate the l2_dtable 1336 * if we allocated a new one above. 1337 */ 1338 if (l2->l2_occupancy == 0) { 1339 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1340 pmap_free_l2_dtable(l2); 1341 } 1342 return (NULL); 1343 } 1344 1345 l2->l2_occupancy++; 1346 l2b->l2b_kva = ptep; 1347 l2b->l2b_l1idx = l1idx; 1348 } 1349 1350 return (l2b); 1351 } 1352 1353 /* 1354 * One or more mappings in the specified L2 descriptor table have just been 1355 * invalidated. 1356 * 1357 * Garbage collect the metadata and descriptor table itself if necessary. 1358 * 1359 * The pmap lock must be acquired when this is called (not necessary 1360 * for the kernel pmap). 1361 */ 1362 static void 1363 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1364 { 1365 struct l2_dtable *l2; 1366 pd_entry_t *pl1pd, l1pd; 1367 pt_entry_t *ptep; 1368 u_short l1idx; 1369 1370 KDASSERT(count <= l2b->l2b_occupancy); 1371 1372 /* 1373 * Update the bucket's reference count according to how many 1374 * PTEs the caller has just invalidated. 1375 */ 1376 l2b->l2b_occupancy -= count; 1377 1378 /* 1379 * Note: 1380 * 1381 * Level 2 page tables allocated to the kernel pmap are never freed 1382 * as that would require checking all Level 1 page tables and 1383 * removing any references to the Level 2 page table. See also the 1384 * comment elsewhere about never freeing bootstrap L2 descriptors. 1385 * 1386 * We make do with just invalidating the mapping in the L2 table. 1387 * 1388 * This isn't really a big deal in practice and, in fact, leads 1389 * to a performance win over time as we don't need to continually 1390 * alloc/free. 1391 */ 1392 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1393 return; 1394 1395 /* 1396 * There are no more valid mappings in this level 2 page table. 1397 * Go ahead and NULL-out the pointer in the bucket, then 1398 * free the page table. 1399 */ 1400 l1idx = l2b->l2b_l1idx; 1401 ptep = l2b->l2b_kva; 1402 l2b->l2b_kva = NULL; 1403 1404 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1405 1406 /* 1407 * If the L1 slot matches the pmap's domain 1408 * number, then invalidate it. 1409 */ 1410 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1411 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1412 *pl1pd = 0; 1413 PTE_SYNC(pl1pd); 1414 } 1415 1416 /* 1417 * Release the L2 descriptor table back to the pool cache. 1418 */ 1419 #ifndef PMAP_INCLUDE_PTE_SYNC 1420 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1421 #else 1422 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1423 #endif 1424 1425 /* 1426 * Update the reference count in the associated l2_dtable 1427 */ 1428 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1429 if (--l2->l2_occupancy > 0) 1430 return; 1431 1432 /* 1433 * There are no more valid mappings in any of the Level 1 1434 * slots managed by this l2_dtable. Go ahead and NULL-out 1435 * the pointer in the parent pmap and free the l2_dtable. 1436 */ 1437 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1438 pmap_free_l2_dtable(l2); 1439 } 1440 1441 /* 1442 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1443 * structures. 1444 */ 1445 static int 1446 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1447 { 1448 #ifndef PMAP_INCLUDE_PTE_SYNC 1449 struct l2_bucket *l2b; 1450 pt_entry_t *ptep, pte; 1451 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1452 1453 /* 1454 * The mappings for these page tables were initially made using 1455 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1456 * mode will not be right for page table mappings. To avoid 1457 * polluting the pmap_kenter_pa() code with a special case for 1458 * page tables, we simply fix up the cache-mode here if it's not 1459 * correct. 1460 */ 1461 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1462 KDASSERT(l2b != NULL); 1463 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1464 pte = *ptep; 1465 1466 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1467 /* 1468 * Page tables must have the cache-mode set to Write-Thru. 1469 */ 1470 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1471 PTE_SYNC(ptep); 1472 cpu_tlb_flushD_SE(va); 1473 cpu_cpwait(); 1474 } 1475 #endif 1476 1477 memset(v, 0, L2_TABLE_SIZE_REAL); 1478 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1479 return (0); 1480 } 1481 1482 static int 1483 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1484 { 1485 1486 memset(v, 0, sizeof(struct l2_dtable)); 1487 return (0); 1488 } 1489 1490 static int 1491 pmap_pmap_ctor(void *arg, void *v, int flags) 1492 { 1493 1494 memset(v, 0, sizeof(struct pmap)); 1495 return (0); 1496 } 1497 1498 static void 1499 pmap_pinit(pmap_t pm) 1500 { 1501 struct l2_bucket *l2b; 1502 1503 if (vector_page < KERNEL_BASE) { 1504 /* 1505 * Map the vector page. 1506 */ 1507 pmap_enter(pm, vector_page, systempage.pv_pa, 1508 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1509 pmap_update(pm); 1510 1511 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1512 l2b = pmap_get_l2_bucket(pm, vector_page); 1513 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1514 L1_C_DOM(pm->pm_domain); 1515 } else 1516 pm->pm_pl1vec = NULL; 1517 } 1518 1519 #ifdef PMAP_CACHE_VIVT 1520 /* 1521 * Since we have a virtually indexed cache, we may need to inhibit caching if 1522 * there is more than one mapping and at least one of them is writable. 1523 * Since we purge the cache on every context switch, we only need to check for 1524 * other mappings within the same pmap, or kernel_pmap. 1525 * This function is also called when a page is unmapped, to possibly reenable 1526 * caching on any remaining mappings. 1527 * 1528 * The code implements the following logic, where: 1529 * 1530 * KW = # of kernel read/write pages 1531 * KR = # of kernel read only pages 1532 * UW = # of user read/write pages 1533 * UR = # of user read only pages 1534 * 1535 * KC = kernel mapping is cacheable 1536 * UC = user mapping is cacheable 1537 * 1538 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1539 * +--------------------------------------------- 1540 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1541 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1542 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1543 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1544 */ 1545 1546 static const int pmap_vac_flags[4][4] = { 1547 {-1, 0, 0, PVF_KNC}, 1548 {0, 0, PVF_NC, PVF_NC}, 1549 {0, PVF_NC, PVF_NC, PVF_NC}, 1550 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1551 }; 1552 1553 static inline int 1554 pmap_get_vac_flags(const struct vm_page *pg) 1555 { 1556 int kidx, uidx; 1557 1558 kidx = 0; 1559 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1560 kidx |= 1; 1561 if (pg->mdpage.krw_mappings) 1562 kidx |= 2; 1563 1564 uidx = 0; 1565 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1566 uidx |= 1; 1567 if (pg->mdpage.urw_mappings) 1568 uidx |= 2; 1569 1570 return (pmap_vac_flags[uidx][kidx]); 1571 } 1572 1573 static inline void 1574 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1575 { 1576 int nattr; 1577 1578 nattr = pmap_get_vac_flags(pg); 1579 1580 if (nattr < 0) { 1581 pg->mdpage.pvh_attrs &= ~PVF_NC; 1582 return; 1583 } 1584 1585 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1586 return; 1587 1588 if (pm == pmap_kernel()) 1589 pmap_vac_me_kpmap(pg, pm, va); 1590 else 1591 pmap_vac_me_user(pg, pm, va); 1592 1593 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1594 } 1595 1596 static void 1597 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1598 { 1599 u_int u_cacheable, u_entries; 1600 struct pv_entry *pv; 1601 pmap_t last_pmap = pm; 1602 1603 /* 1604 * Pass one, see if there are both kernel and user pmaps for 1605 * this page. Calculate whether there are user-writable or 1606 * kernel-writable pages. 1607 */ 1608 u_cacheable = 0; 1609 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1610 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1611 u_cacheable++; 1612 } 1613 1614 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1615 1616 /* 1617 * We know we have just been updating a kernel entry, so if 1618 * all user pages are already cacheable, then there is nothing 1619 * further to do. 1620 */ 1621 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1622 return; 1623 1624 if (u_entries) { 1625 /* 1626 * Scan over the list again, for each entry, if it 1627 * might not be set correctly, call pmap_vac_me_user 1628 * to recalculate the settings. 1629 */ 1630 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1631 /* 1632 * We know kernel mappings will get set 1633 * correctly in other calls. We also know 1634 * that if the pmap is the same as last_pmap 1635 * then we've just handled this entry. 1636 */ 1637 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1638 continue; 1639 1640 /* 1641 * If there are kernel entries and this page 1642 * is writable but non-cacheable, then we can 1643 * skip this entry also. 1644 */ 1645 if (pg->mdpage.k_mappings && 1646 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1647 (PVF_NC | PVF_WRITE)) 1648 continue; 1649 1650 /* 1651 * Similarly if there are no kernel-writable 1652 * entries and the page is already 1653 * read-only/cacheable. 1654 */ 1655 if (pg->mdpage.krw_mappings == 0 && 1656 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1657 continue; 1658 1659 /* 1660 * For some of the remaining cases, we know 1661 * that we must recalculate, but for others we 1662 * can't tell if they are correct or not, so 1663 * we recalculate anyway. 1664 */ 1665 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1666 } 1667 1668 if (pg->mdpage.k_mappings == 0) 1669 return; 1670 } 1671 1672 pmap_vac_me_user(pg, pm, va); 1673 } 1674 1675 static void 1676 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1677 { 1678 pmap_t kpmap = pmap_kernel(); 1679 struct pv_entry *pv, *npv = NULL; 1680 struct l2_bucket *l2b; 1681 pt_entry_t *ptep, pte; 1682 u_int entries = 0; 1683 u_int writable = 0; 1684 u_int cacheable_entries = 0; 1685 u_int kern_cacheable = 0; 1686 u_int other_writable = 0; 1687 1688 /* 1689 * Count mappings and writable mappings in this pmap. 1690 * Include kernel mappings as part of our own. 1691 * Keep a pointer to the first one. 1692 */ 1693 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1694 /* Count mappings in the same pmap */ 1695 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1696 if (entries++ == 0) 1697 npv = pv; 1698 1699 /* Cacheable mappings */ 1700 if ((pv->pv_flags & PVF_NC) == 0) { 1701 cacheable_entries++; 1702 if (kpmap == pv->pv_pmap) 1703 kern_cacheable++; 1704 } 1705 1706 /* Writable mappings */ 1707 if (pv->pv_flags & PVF_WRITE) 1708 ++writable; 1709 } else 1710 if (pv->pv_flags & PVF_WRITE) 1711 other_writable = 1; 1712 } 1713 1714 /* 1715 * Enable or disable caching as necessary. 1716 * Note: the first entry might be part of the kernel pmap, 1717 * so we can't assume this is indicative of the state of the 1718 * other (maybe non-kpmap) entries. 1719 */ 1720 if ((entries > 1 && writable) || 1721 (entries > 0 && pm == kpmap && other_writable)) { 1722 if (cacheable_entries == 0) 1723 return; 1724 1725 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1726 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1727 (pv->pv_flags & PVF_NC)) 1728 continue; 1729 1730 pv->pv_flags |= PVF_NC; 1731 1732 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1733 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1734 pte = *ptep & ~L2_S_CACHE_MASK; 1735 1736 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1737 l2pte_valid(pte)) { 1738 if (PV_BEEN_EXECD(pv->pv_flags)) { 1739 #ifdef PMAP_CACHE_VIVT 1740 pmap_idcache_wbinv_range(pv->pv_pmap, 1741 pv->pv_va, PAGE_SIZE); 1742 #endif 1743 pmap_tlb_flushID_SE(pv->pv_pmap, 1744 pv->pv_va); 1745 } else 1746 if (PV_BEEN_REFD(pv->pv_flags)) { 1747 #ifdef PMAP_CACHE_VIVT 1748 pmap_dcache_wb_range(pv->pv_pmap, 1749 pv->pv_va, PAGE_SIZE, true, 1750 (pv->pv_flags & PVF_WRITE) == 0); 1751 #endif 1752 pmap_tlb_flushD_SE(pv->pv_pmap, 1753 pv->pv_va); 1754 } 1755 } 1756 1757 *ptep = pte; 1758 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1759 } 1760 cpu_cpwait(); 1761 } else 1762 if (entries > cacheable_entries) { 1763 /* 1764 * Turn cacheing back on for some pages. If it is a kernel 1765 * page, only do so if there are no other writable pages. 1766 */ 1767 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1768 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1769 (kpmap != pv->pv_pmap || other_writable))) 1770 continue; 1771 1772 pv->pv_flags &= ~PVF_NC; 1773 1774 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1775 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1776 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1777 1778 if (l2pte_valid(pte)) { 1779 if (PV_BEEN_EXECD(pv->pv_flags)) { 1780 pmap_tlb_flushID_SE(pv->pv_pmap, 1781 pv->pv_va); 1782 } else 1783 if (PV_BEEN_REFD(pv->pv_flags)) { 1784 pmap_tlb_flushD_SE(pv->pv_pmap, 1785 pv->pv_va); 1786 } 1787 } 1788 1789 *ptep = pte; 1790 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1791 } 1792 } 1793 } 1794 #endif 1795 1796 #ifdef PMAP_CACHE_VIPT 1797 /* 1798 * For virtually indexed / physically tagged caches, what we have to worry 1799 * about is illegal cache aliases. To prevent this, we must ensure that 1800 * virtual addresses that map the physical page use the same bits for those 1801 * bits masked by "arm_cache_prefer_mask" (bits 12+). If there is a conflict, 1802 * all mappings of the page must be non-cached. 1803 */ 1804 #if 0 1805 static inline vaddr_t 1806 pmap_check_sets(paddr_t pa) 1807 { 1808 extern int arm_dcache_l2_nsets; 1809 int set, way; 1810 vaddr_t mask = 0; 1811 int v; 1812 pa |= 1; 1813 for (set = 0; set < (1 << arm_dcache_l2_nsets); set++) { 1814 for (way = 0; way < 4; way++) { 1815 v = (way << 30) | (set << 5); 1816 asm("mcr p15, 3, %0, c15, c2, 0" :: "r"(v)); 1817 asm("mrc p15, 3, %0, c15, c0, 0" : "=r"(v)); 1818 1819 if ((v & (1 | ~(PAGE_SIZE-1))) == pa) { 1820 mask |= 1 << (set >> 7); 1821 } 1822 } 1823 } 1824 return mask; 1825 } 1826 #endif 1827 static void 1828 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1829 { 1830 struct pv_entry *pv; 1831 vaddr_t tst_mask; 1832 bool bad_alias; 1833 struct l2_bucket *l2b; 1834 pt_entry_t *ptep, pte, opte; 1835 const u_int 1836 rw_mappings = pg->mdpage.urw_mappings + pg->mdpage.krw_mappings, 1837 ro_mappings = pg->mdpage.uro_mappings + pg->mdpage.kro_mappings; 1838 1839 /* do we need to do anything? */ 1840 if (arm_cache_prefer_mask == 0) 1841 return; 1842 1843 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1844 pg, pm, va)); 1845 1846 #define popc4(x) \ 1847 (((0x94 >> ((x & 3) << 1)) & 3) + ((0x94 >> ((x & 12) >> 1)) & 3)) 1848 #if 0 1849 tst_mask = pmap_check_sets(pg->phys_addr); 1850 KASSERT(popc4(tst_mask) < 2); 1851 #endif 1852 1853 KASSERT(!va || pm); 1854 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1855 1856 /* Already a conflict? */ 1857 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1858 /* just an add, things are already non-cached */ 1859 KASSERT(!(pg->mdpage.pvh_attrs & PVF_DIRTY)); 1860 bad_alias = false; 1861 if (va) { 1862 PMAPCOUNT(vac_color_none); 1863 bad_alias = true; 1864 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1865 goto fixup; 1866 } 1867 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1868 /* the list can't be empty because it would be cachable */ 1869 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) { 1870 tst_mask = pg->mdpage.pvh_attrs; 1871 } else { 1872 KASSERT(pv); 1873 tst_mask = pv->pv_va; 1874 pv = SLIST_NEXT(pv, pv_link); 1875 } 1876 /* 1877 * Only check for a bad alias if we have writable mappings. 1878 */ 1879 tst_mask &= arm_cache_prefer_mask; 1880 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1881 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1882 /* if there's a bad alias, stop checking. */ 1883 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1884 bad_alias = true; 1885 } 1886 pg->mdpage.pvh_attrs |= PVF_WRITE; 1887 if (!bad_alias) 1888 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1889 } else { 1890 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1891 } 1892 /* If no conflicting colors, set everything back to cached */ 1893 if (!bad_alias) { 1894 #ifdef DEBUG 1895 if ((pg->mdpage.pvh_attrs & PVF_WRITE) 1896 || ro_mappings < 2) { 1897 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1898 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1899 } 1900 1901 #endif 1902 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1903 pg->mdpage.pvh_attrs |= tst_mask | PVF_COLORED; 1904 /* 1905 * Restore DIRTY bit if page is modified 1906 */ 1907 if (pg->mdpage.pvh_attrs & PVF_DMOD) 1908 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1909 PMAPCOUNT(vac_color_restore); 1910 } else { 1911 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1912 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1913 } 1914 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1915 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1916 } else if (!va) { 1917 KASSERT(pmap_is_page_colored_p(pg)); 1918 KASSERT(!(pg->mdpage.pvh_attrs & PVF_WRITE) 1919 || (pg->mdpage.pvh_attrs & PVF_DIRTY)); 1920 if (rw_mappings == 0) 1921 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1922 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1923 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1924 return; 1925 } else if (!pmap_is_page_colored_p(pg)) { 1926 /* not colored so we just use its color */ 1927 KASSERT(pg->mdpage.pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1928 PMAPCOUNT(vac_color_new); 1929 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1930 pg->mdpage.pvh_attrs |= PVF_COLORED 1931 | (va & arm_cache_prefer_mask) 1932 | (rw_mappings > 0 ? PVF_WRITE : 0); 1933 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1934 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1935 return; 1936 } else if (((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1937 bad_alias = false; 1938 if (rw_mappings > 0) { 1939 /* 1940 * We now have writeable mappings and more than one 1941 * readonly mapping, verify the colors don't clash 1942 * and mark the page as writeable. 1943 */ 1944 if (ro_mappings > 1 1945 && (pg->mdpage.pvh_attrs & PVF_WRITE) == 0 1946 && arm_cache_prefer_mask) { 1947 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1948 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1949 /* if there's a bad alias, stop checking. */ 1950 if (((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0) { 1951 bad_alias = true; 1952 break; 1953 } 1954 } 1955 } 1956 pg->mdpage.pvh_attrs |= PVF_WRITE; 1957 } 1958 /* If no conflicting colors, set everything back to cached */ 1959 if (!bad_alias) { 1960 #ifdef DEBUG 1961 if (rw_mappings > 0 1962 || (pg->mdpage.pvh_attrs & PMAP_KMPAGE)) { 1963 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1964 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1965 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1966 } 1967 #endif 1968 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) 1969 PMAPCOUNT(vac_color_reuse); 1970 else 1971 PMAPCOUNT(vac_color_ok); 1972 1973 /* matching color, just return */ 1974 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1975 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1976 return; 1977 } 1978 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1979 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1980 1981 /* color conflict. evict from cache. */ 1982 1983 pmap_flush_page(pg, true); 1984 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 1985 pg->mdpage.pvh_attrs |= PVF_NC; 1986 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1987 PMAPCOUNT(vac_color_erase); 1988 } else if (rw_mappings == 0 1989 && (pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 1990 KASSERT((pg->mdpage.pvh_attrs & PVF_WRITE) == 0); 1991 1992 /* 1993 * If the page has dirty cache lines, clean it. 1994 */ 1995 if (pg->mdpage.pvh_attrs & PVF_DIRTY) 1996 pmap_flush_page(pg, false); 1997 1998 /* 1999 * If this is the first remapping (we know that there are no 2000 * writeable mappings), then this is a simple color change. 2001 * Otherwise this is a seconary r/o mapping, which means 2002 * we don't have to do anything. 2003 */ 2004 if (ro_mappings == 1) { 2005 KASSERT(((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2006 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2007 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2008 PMAPCOUNT(vac_color_change); 2009 } else { 2010 PMAPCOUNT(vac_color_blind); 2011 } 2012 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2013 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2014 return; 2015 } else { 2016 if (rw_mappings > 0) 2017 pg->mdpage.pvh_attrs |= PVF_WRITE; 2018 2019 /* color conflict. evict from cache. */ 2020 pmap_flush_page(pg, true); 2021 2022 /* the list can't be empty because this was a enter/modify */ 2023 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2024 if ((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2025 KASSERT(pv); 2026 /* 2027 * If there's only one mapped page, change color to the 2028 * page's new color and return. Restore the DIRTY bit 2029 * that was erased by pmap_flush_page. 2030 */ 2031 if (SLIST_NEXT(pv, pv_link) == NULL) { 2032 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2033 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2034 if (pg->mdpage.pvh_attrs & PVF_DMOD) 2035 pg->mdpage.pvh_attrs |= PVF_DIRTY; 2036 PMAPCOUNT(vac_color_change); 2037 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2038 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2039 return; 2040 } 2041 } 2042 bad_alias = true; 2043 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2044 pg->mdpage.pvh_attrs |= PVF_NC; 2045 PMAPCOUNT(vac_color_erase); 2046 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2047 } 2048 2049 fixup: 2050 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2051 2052 /* 2053 * Turn cacheing on/off for all pages. 2054 */ 2055 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2056 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2057 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2058 opte = *ptep; 2059 pte = opte & ~L2_S_CACHE_MASK; 2060 if (bad_alias) { 2061 pv->pv_flags |= PVF_NC; 2062 } else { 2063 pv->pv_flags &= ~PVF_NC; 2064 pte |= pte_l2_s_cache_mode; 2065 } 2066 2067 if (opte == pte) /* only update is there's a change */ 2068 continue; 2069 2070 if (l2pte_valid(pte)) { 2071 if (PV_BEEN_EXECD(pv->pv_flags)) { 2072 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2073 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2074 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2075 } 2076 } 2077 2078 *ptep = pte; 2079 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2080 } 2081 } 2082 #endif /* PMAP_CACHE_VIPT */ 2083 2084 2085 /* 2086 * Modify pte bits for all ptes corresponding to the given physical address. 2087 * We use `maskbits' rather than `clearbits' because we're always passing 2088 * constants and the latter would require an extra inversion at run-time. 2089 */ 2090 static void 2091 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2092 { 2093 struct l2_bucket *l2b; 2094 struct pv_entry *pv; 2095 pt_entry_t *ptep, npte, opte; 2096 pmap_t pm; 2097 vaddr_t va; 2098 u_int oflags; 2099 #ifdef PMAP_CACHE_VIPT 2100 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 2101 bool need_syncicache = false; 2102 bool did_syncicache = false; 2103 bool need_vac_me_harder = false; 2104 #endif 2105 2106 NPDEBUG(PDB_BITS, 2107 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2108 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2109 2110 PMAP_HEAD_TO_MAP_LOCK(); 2111 simple_lock(&pg->mdpage.pvh_slock); 2112 2113 #ifdef PMAP_CACHE_VIPT 2114 /* 2115 * If we might want to sync the I-cache and we've modified it, 2116 * then we know we definitely need to sync or discard it. 2117 */ 2118 if (want_syncicache) 2119 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 2120 #endif 2121 /* 2122 * Clear saved attributes (modify, reference) 2123 */ 2124 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2125 2126 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 2127 #ifdef PMAP_CACHE_VIPT 2128 if (need_syncicache) { 2129 /* 2130 * No one has it mapped, so just discard it. The next 2131 * exec remapping will cause it to be synced. 2132 */ 2133 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2134 PMAPCOUNT(exec_discarded_clearbit); 2135 } 2136 #endif 2137 simple_unlock(&pg->mdpage.pvh_slock); 2138 PMAP_HEAD_TO_MAP_UNLOCK(); 2139 return; 2140 } 2141 2142 /* 2143 * Loop over all current mappings setting/clearing as appropos 2144 */ 2145 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2146 va = pv->pv_va; 2147 pm = pv->pv_pmap; 2148 oflags = pv->pv_flags; 2149 /* 2150 * Kernel entries are unmanaged and as such not to be changed. 2151 */ 2152 if (oflags & PVF_KENTRY) 2153 continue; 2154 pv->pv_flags &= ~maskbits; 2155 2156 pmap_acquire_pmap_lock(pm); 2157 2158 l2b = pmap_get_l2_bucket(pm, va); 2159 KDASSERT(l2b != NULL); 2160 2161 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2162 npte = opte = *ptep; 2163 2164 NPDEBUG(PDB_BITS, 2165 printf( 2166 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2167 pv, pv->pv_pmap, pv->pv_va, oflags)); 2168 2169 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2170 #ifdef PMAP_CACHE_VIVT 2171 if ((pv->pv_flags & PVF_NC)) { 2172 /* 2173 * Entry is not cacheable: 2174 * 2175 * Don't turn caching on again if this is a 2176 * modified emulation. This would be 2177 * inconsitent with the settings created by 2178 * pmap_vac_me_harder(). Otherwise, it's safe 2179 * to re-enable cacheing. 2180 * 2181 * There's no need to call pmap_vac_me_harder() 2182 * here: all pages are losing their write 2183 * permission. 2184 */ 2185 if (maskbits & PVF_WRITE) { 2186 npte |= pte_l2_s_cache_mode; 2187 pv->pv_flags &= ~PVF_NC; 2188 } 2189 } else 2190 if (opte & L2_S_PROT_W) { 2191 /* 2192 * Entry is writable/cacheable: check if pmap 2193 * is current if it is flush it, otherwise it 2194 * won't be in the cache 2195 */ 2196 if (PV_BEEN_EXECD(oflags)) 2197 pmap_idcache_wbinv_range(pm, pv->pv_va, 2198 PAGE_SIZE); 2199 else 2200 if (PV_BEEN_REFD(oflags)) 2201 pmap_dcache_wb_range(pm, pv->pv_va, 2202 PAGE_SIZE, 2203 (maskbits & PVF_REF) != 0, false); 2204 } 2205 #endif 2206 2207 /* make the pte read only */ 2208 npte &= ~L2_S_PROT_W; 2209 2210 if (maskbits & oflags & PVF_WRITE) { 2211 /* 2212 * Keep alias accounting up to date 2213 */ 2214 if (pv->pv_pmap == pmap_kernel()) { 2215 pg->mdpage.krw_mappings--; 2216 pg->mdpage.kro_mappings++; 2217 } else { 2218 pg->mdpage.urw_mappings--; 2219 pg->mdpage.uro_mappings++; 2220 } 2221 #ifdef PMAP_CACHE_VIPT 2222 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 2223 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2224 if (want_syncicache) 2225 need_syncicache = true; 2226 need_vac_me_harder = true; 2227 #endif 2228 } 2229 } 2230 2231 if (maskbits & PVF_REF) { 2232 if ((pv->pv_flags & PVF_NC) == 0 && 2233 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2234 l2pte_valid(npte)) { 2235 #ifdef PMAP_CACHE_VIVT 2236 /* 2237 * Check npte here; we may have already 2238 * done the wbinv above, and the validity 2239 * of the PTE is the same for opte and 2240 * npte. 2241 */ 2242 /* XXXJRT need idcache_inv_range */ 2243 if (PV_BEEN_EXECD(oflags)) 2244 pmap_idcache_wbinv_range(pm, 2245 pv->pv_va, PAGE_SIZE); 2246 else 2247 if (PV_BEEN_REFD(oflags)) 2248 pmap_dcache_wb_range(pm, 2249 pv->pv_va, PAGE_SIZE, 2250 true, true); 2251 #endif 2252 } 2253 2254 /* 2255 * Make the PTE invalid so that we will take a 2256 * page fault the next time the mapping is 2257 * referenced. 2258 */ 2259 npte &= ~L2_TYPE_MASK; 2260 npte |= L2_TYPE_INV; 2261 } 2262 2263 if (npte != opte) { 2264 *ptep = npte; 2265 PTE_SYNC(ptep); 2266 /* Flush the TLB entry if a current pmap. */ 2267 if (PV_BEEN_EXECD(oflags)) 2268 pmap_tlb_flushID_SE(pm, pv->pv_va); 2269 else 2270 if (PV_BEEN_REFD(oflags)) 2271 pmap_tlb_flushD_SE(pm, pv->pv_va); 2272 } 2273 2274 pmap_release_pmap_lock(pm); 2275 2276 NPDEBUG(PDB_BITS, 2277 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2278 pm, va, opte, npte)); 2279 } 2280 2281 #ifdef PMAP_CACHE_VIPT 2282 /* 2283 * If we need to sync the I-cache and we haven't done it yet, do it. 2284 */ 2285 if (need_syncicache && !did_syncicache) { 2286 pmap_syncicache_page(pg); 2287 PMAPCOUNT(exec_synced_clearbit); 2288 } 2289 /* 2290 * If we are changing this to read-only, we ned to call vac_me_harder 2291 * so we can change all the read-only pages to cacheable. We pretend 2292 * this as a page deletion. 2293 */ 2294 if (need_vac_me_harder) { 2295 if (pg->mdpage.pvh_attrs & PVF_NC) 2296 pmap_vac_me_harder(pg, NULL, 0); 2297 } 2298 #endif 2299 2300 simple_unlock(&pg->mdpage.pvh_slock); 2301 PMAP_HEAD_TO_MAP_UNLOCK(); 2302 } 2303 2304 /* 2305 * pmap_clean_page() 2306 * 2307 * This is a local function used to work out the best strategy to clean 2308 * a single page referenced by its entry in the PV table. It's used by 2309 * pmap_copy_page, pmap_zero page and maybe some others later on. 2310 * 2311 * Its policy is effectively: 2312 * o If there are no mappings, we don't bother doing anything with the cache. 2313 * o If there is one mapping, we clean just that page. 2314 * o If there are multiple mappings, we clean the entire cache. 2315 * 2316 * So that some functions can be further optimised, it returns 0 if it didn't 2317 * clean the entire cache, or 1 if it did. 2318 * 2319 * XXX One bug in this routine is that if the pv_entry has a single page 2320 * mapped at 0x00000000 a whole cache clean will be performed rather than 2321 * just the 1 page. Since this should not occur in everyday use and if it does 2322 * it will just result in not the most efficient clean for the page. 2323 */ 2324 #ifdef PMAP_CACHE_VIVT 2325 static int 2326 pmap_clean_page(struct pv_entry *pv, bool is_src) 2327 { 2328 pmap_t pm, pm_to_clean = NULL; 2329 struct pv_entry *npv; 2330 u_int cache_needs_cleaning = 0; 2331 u_int flags = 0; 2332 vaddr_t page_to_clean = 0; 2333 2334 if (pv == NULL) { 2335 /* nothing mapped in so nothing to flush */ 2336 return (0); 2337 } 2338 2339 /* 2340 * Since we flush the cache each time we change to a different 2341 * user vmspace, we only need to flush the page if it is in the 2342 * current pmap. 2343 */ 2344 pm = curproc->p_vmspace->vm_map.pmap; 2345 2346 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2347 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2348 flags |= npv->pv_flags; 2349 /* 2350 * The page is mapped non-cacheable in 2351 * this map. No need to flush the cache. 2352 */ 2353 if (npv->pv_flags & PVF_NC) { 2354 #ifdef DIAGNOSTIC 2355 if (cache_needs_cleaning) 2356 panic("pmap_clean_page: " 2357 "cache inconsistency"); 2358 #endif 2359 break; 2360 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2361 continue; 2362 if (cache_needs_cleaning) { 2363 page_to_clean = 0; 2364 break; 2365 } else { 2366 page_to_clean = npv->pv_va; 2367 pm_to_clean = npv->pv_pmap; 2368 } 2369 cache_needs_cleaning = 1; 2370 } 2371 } 2372 2373 if (page_to_clean) { 2374 if (PV_BEEN_EXECD(flags)) 2375 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2376 PAGE_SIZE); 2377 else 2378 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2379 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2380 } else if (cache_needs_cleaning) { 2381 if (PV_BEEN_EXECD(flags)) 2382 pmap_idcache_wbinv_all(pm); 2383 else 2384 pmap_dcache_wbinv_all(pm); 2385 return (1); 2386 } 2387 return (0); 2388 } 2389 #endif 2390 2391 #ifdef PMAP_CACHE_VIPT 2392 /* 2393 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2394 * right cache alias to make sure we flush the right stuff. 2395 */ 2396 void 2397 pmap_syncicache_page(struct vm_page *pg) 2398 { 2399 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2400 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2401 2402 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2403 pg, pg->mdpage.pvh_attrs)); 2404 /* 2405 * No need to clean the page if it's non-cached. 2406 */ 2407 if (pg->mdpage.pvh_attrs & PVF_NC) 2408 return; 2409 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2410 2411 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2412 /* 2413 * Set up a PTE with the right coloring to flush existing cache lines. 2414 */ 2415 *ptep = L2_S_PROTO | 2416 VM_PAGE_TO_PHYS(pg) 2417 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2418 | pte_l2_s_cache_mode; 2419 PTE_SYNC(ptep); 2420 2421 /* 2422 * Flush it. 2423 */ 2424 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2425 /* 2426 * Unmap the page. 2427 */ 2428 *ptep = 0; 2429 PTE_SYNC(ptep); 2430 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2431 2432 pg->mdpage.pvh_attrs |= PVF_EXEC; 2433 PMAPCOUNT(exec_synced); 2434 } 2435 2436 void 2437 pmap_flush_page(struct vm_page *pg, bool flush) 2438 { 2439 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2440 const size_t pte_offset = va_offset >> PGSHIFT; 2441 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2442 const pt_entry_t oldpte = *ptep; 2443 #if 0 2444 vaddr_t mask; 2445 #endif 2446 2447 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2448 #if 0 2449 mask = pmap_check_sets(pg->phys_addr); 2450 KASSERT(popc4(mask) < 2); 2451 #endif 2452 2453 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2454 pg, pg->mdpage.pvh_attrs)); 2455 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2456 /* 2457 * Set up a PTE with the right coloring to flush existing cache entries. 2458 */ 2459 *ptep = L2_S_PROTO 2460 | VM_PAGE_TO_PHYS(pg) 2461 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2462 | pte_l2_s_cache_mode; 2463 PTE_SYNC(ptep); 2464 2465 /* 2466 * Flush it. 2467 */ 2468 if (flush) { 2469 cpu_idcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 2470 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2471 } else { 2472 cpu_dcache_wb_range(cdstp + va_offset, PAGE_SIZE); 2473 /* 2474 * Mark that the page is no longer dirty. 2475 */ 2476 if ((pg->mdpage.pvh_attrs & PVF_DMOD) == 0) 2477 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2478 } 2479 2480 /* 2481 * Restore the page table entry since we might have interrupted 2482 * pmap_zero_page or pmap_copy_page which was already using this pte. 2483 */ 2484 *ptep = oldpte; 2485 PTE_SYNC(ptep); 2486 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2487 #if 0 2488 mask = pmap_check_sets(pg->phys_addr); 2489 KASSERT(mask == 0); 2490 #endif 2491 } 2492 #endif /* PMAP_CACHE_VIPT */ 2493 2494 /* 2495 * Routine: pmap_page_remove 2496 * Function: 2497 * Removes this physical page from 2498 * all physical maps in which it resides. 2499 * Reflects back modify bits to the pager. 2500 */ 2501 static void 2502 pmap_page_remove(struct vm_page *pg) 2503 { 2504 struct l2_bucket *l2b; 2505 struct pv_entry *pv, *npv, **pvp; 2506 pmap_t pm, curpm; 2507 pt_entry_t *ptep, pte; 2508 bool flush; 2509 u_int flags; 2510 2511 NPDEBUG(PDB_FOLLOW, 2512 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2513 VM_PAGE_TO_PHYS(pg))); 2514 2515 PMAP_HEAD_TO_MAP_LOCK(); 2516 simple_lock(&pg->mdpage.pvh_slock); 2517 2518 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2519 if (pv == NULL) { 2520 #ifdef PMAP_CACHE_VIPT 2521 /* 2522 * We *know* the page contents are about to be replaced. 2523 * Discard the exec contents 2524 */ 2525 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2526 PMAPCOUNT(exec_discarded_page_protect); 2527 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2528 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2529 #endif 2530 simple_unlock(&pg->mdpage.pvh_slock); 2531 PMAP_HEAD_TO_MAP_UNLOCK(); 2532 return; 2533 } 2534 #ifdef PMAP_CACHE_VIPT 2535 KASSERT(pmap_is_page_colored_p(pg)); 2536 #endif 2537 2538 /* 2539 * Clear alias counts 2540 */ 2541 #ifdef PMAP_CACHE_VIVT 2542 pg->mdpage.k_mappings = 0; 2543 #endif 2544 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2545 2546 flush = false; 2547 flags = 0; 2548 curpm = curproc->p_vmspace->vm_map.pmap; 2549 2550 #ifdef PMAP_CACHE_VIVT 2551 pmap_clean_page(pv, false); 2552 #endif 2553 2554 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 2555 while (pv) { 2556 pm = pv->pv_pmap; 2557 npv = SLIST_NEXT(pv, pv_link); 2558 if (flush == false && (pm == curpm || pm == pmap_kernel())) 2559 flush = true; 2560 2561 if (pm == pmap_kernel()) { 2562 #ifdef PMAP_CACHE_VIPT 2563 /* 2564 * If this was unmanaged mapping, it must be preserved. 2565 * Move it back on the list and advance the end-of-list 2566 * pointer. 2567 */ 2568 if (pv->pv_flags & PVF_KENTRY) { 2569 *pvp = pv; 2570 pvp = &SLIST_NEXT(pv, pv_link); 2571 pv = npv; 2572 continue; 2573 } 2574 if (pv->pv_flags & PVF_WRITE) 2575 pg->mdpage.krw_mappings--; 2576 else 2577 pg->mdpage.kro_mappings--; 2578 #endif 2579 PMAPCOUNT(kernel_unmappings); 2580 } 2581 PMAPCOUNT(unmappings); 2582 2583 pmap_acquire_pmap_lock(pm); 2584 2585 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2586 KDASSERT(l2b != NULL); 2587 2588 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2589 pte = *ptep; 2590 2591 /* 2592 * Update statistics 2593 */ 2594 --pm->pm_stats.resident_count; 2595 2596 /* Wired bit */ 2597 if (pv->pv_flags & PVF_WIRED) 2598 --pm->pm_stats.wired_count; 2599 2600 flags |= pv->pv_flags; 2601 2602 /* 2603 * Invalidate the PTEs. 2604 */ 2605 *ptep = 0; 2606 PTE_SYNC_CURRENT(pm, ptep); 2607 pmap_free_l2_bucket(pm, l2b, 1); 2608 2609 pool_put(&pmap_pv_pool, pv); 2610 pv = npv; 2611 /* 2612 * if we reach the end of the list and there are still 2613 * mappings, they might be able to be cached now. 2614 */ 2615 if (pv == NULL) { 2616 *pvp = NULL; 2617 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 2618 pmap_vac_me_harder(pg, pm, 0); 2619 } 2620 pmap_release_pmap_lock(pm); 2621 } 2622 #ifdef PMAP_CACHE_VIPT 2623 /* 2624 * Its EXEC cache is now gone. 2625 */ 2626 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2627 PMAPCOUNT(exec_discarded_page_protect); 2628 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2629 KASSERT(pg->mdpage.urw_mappings == 0); 2630 KASSERT(pg->mdpage.uro_mappings == 0); 2631 if (pg->mdpage.krw_mappings == 0) 2632 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2633 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2634 #endif 2635 simple_unlock(&pg->mdpage.pvh_slock); 2636 PMAP_HEAD_TO_MAP_UNLOCK(); 2637 2638 if (flush) { 2639 /* 2640 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2641 * would need a subsequent call to pmap_update() to ensure 2642 * curpm->pm_cstate.cs_all is reset. Our callers are not 2643 * required to do that (see pmap(9)), so we can't modify 2644 * the current pmap's state. 2645 */ 2646 if (PV_BEEN_EXECD(flags)) 2647 cpu_tlb_flushID(); 2648 else 2649 cpu_tlb_flushD(); 2650 } 2651 cpu_cpwait(); 2652 } 2653 2654 /* 2655 * pmap_t pmap_create(void) 2656 * 2657 * Create a new pmap structure from scratch. 2658 */ 2659 pmap_t 2660 pmap_create(void) 2661 { 2662 pmap_t pm; 2663 2664 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2665 2666 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2667 pm->pm_stats.wired_count = 0; 2668 pm->pm_stats.resident_count = 1; 2669 pm->pm_cstate.cs_all = 0; 2670 pmap_alloc_l1(pm); 2671 2672 /* 2673 * Note: The pool cache ensures that the pm_l2[] array is already 2674 * initialised to zero. 2675 */ 2676 2677 pmap_pinit(pm); 2678 2679 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2680 2681 return (pm); 2682 } 2683 2684 /* 2685 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2686 * int flags) 2687 * 2688 * Insert the given physical page (p) at 2689 * the specified virtual address (v) in the 2690 * target physical map with the protection requested. 2691 * 2692 * NB: This is the only routine which MAY NOT lazy-evaluate 2693 * or lose information. That is, this routine must actually 2694 * insert this page into the given map NOW. 2695 */ 2696 int 2697 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 2698 { 2699 struct l2_bucket *l2b; 2700 struct vm_page *pg, *opg; 2701 struct pv_entry *pve; 2702 pt_entry_t *ptep, npte, opte; 2703 u_int nflags; 2704 u_int oflags; 2705 2706 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2707 2708 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2709 KDASSERT(((va | pa) & PGOFSET) == 0); 2710 2711 /* 2712 * Get a pointer to the page. Later on in this function, we 2713 * test for a managed page by checking pg != NULL. 2714 */ 2715 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2716 2717 nflags = 0; 2718 if (prot & VM_PROT_WRITE) 2719 nflags |= PVF_WRITE; 2720 if (prot & VM_PROT_EXECUTE) 2721 nflags |= PVF_EXEC; 2722 if (flags & PMAP_WIRED) 2723 nflags |= PVF_WIRED; 2724 2725 PMAP_MAP_TO_HEAD_LOCK(); 2726 pmap_acquire_pmap_lock(pm); 2727 2728 /* 2729 * Fetch the L2 bucket which maps this page, allocating one if 2730 * necessary for user pmaps. 2731 */ 2732 if (pm == pmap_kernel()) 2733 l2b = pmap_get_l2_bucket(pm, va); 2734 else 2735 l2b = pmap_alloc_l2_bucket(pm, va); 2736 if (l2b == NULL) { 2737 if (flags & PMAP_CANFAIL) { 2738 pmap_release_pmap_lock(pm); 2739 PMAP_MAP_TO_HEAD_UNLOCK(); 2740 return (ENOMEM); 2741 } 2742 panic("pmap_enter: failed to allocate L2 bucket"); 2743 } 2744 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2745 opte = *ptep; 2746 npte = pa; 2747 oflags = 0; 2748 2749 if (opte) { 2750 /* 2751 * There is already a mapping at this address. 2752 * If the physical address is different, lookup the 2753 * vm_page. 2754 */ 2755 if (l2pte_pa(opte) != pa) 2756 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2757 else 2758 opg = pg; 2759 } else 2760 opg = NULL; 2761 2762 if (pg) { 2763 /* 2764 * This is to be a managed mapping. 2765 */ 2766 if ((flags & VM_PROT_ALL) || 2767 (pg->mdpage.pvh_attrs & PVF_REF)) { 2768 /* 2769 * - The access type indicates that we don't need 2770 * to do referenced emulation. 2771 * OR 2772 * - The physical page has already been referenced 2773 * so no need to re-do referenced emulation here. 2774 */ 2775 npte |= L2_S_PROTO; 2776 2777 nflags |= PVF_REF; 2778 2779 if ((prot & VM_PROT_WRITE) != 0 && 2780 ((flags & VM_PROT_WRITE) != 0 || 2781 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2782 /* 2783 * This is a writable mapping, and the 2784 * page's mod state indicates it has 2785 * already been modified. Make it 2786 * writable from the outset. 2787 */ 2788 npte |= L2_S_PROT_W; 2789 nflags |= PVF_MOD; 2790 } 2791 } else { 2792 /* 2793 * Need to do page referenced emulation. 2794 */ 2795 npte |= L2_TYPE_INV; 2796 } 2797 2798 npte |= pte_l2_s_cache_mode; 2799 2800 if (pg == opg) { 2801 /* 2802 * We're changing the attrs of an existing mapping. 2803 */ 2804 simple_lock(&pg->mdpage.pvh_slock); 2805 oflags = pmap_modify_pv(pg, pm, va, 2806 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2807 PVF_MOD | PVF_REF, nflags); 2808 simple_unlock(&pg->mdpage.pvh_slock); 2809 2810 #ifdef PMAP_CACHE_VIVT 2811 /* 2812 * We may need to flush the cache if we're 2813 * doing rw-ro... 2814 */ 2815 if (pm->pm_cstate.cs_cache_d && 2816 (oflags & PVF_NC) == 0 && 2817 (opte & L2_S_PROT_W) != 0 && 2818 (prot & VM_PROT_WRITE) == 0) 2819 cpu_dcache_wb_range(va, PAGE_SIZE); 2820 #endif 2821 } else { 2822 /* 2823 * New mapping, or changing the backing page 2824 * of an existing mapping. 2825 */ 2826 if (opg) { 2827 /* 2828 * Replacing an existing mapping with a new one. 2829 * It is part of our managed memory so we 2830 * must remove it from the PV list 2831 */ 2832 simple_lock(&opg->mdpage.pvh_slock); 2833 pve = pmap_remove_pv(opg, pm, va, 0); 2834 pmap_vac_me_harder(opg, pm, 0); 2835 simple_unlock(&opg->mdpage.pvh_slock); 2836 oflags = pve->pv_flags; 2837 2838 #ifdef PMAP_CACHE_VIVT 2839 /* 2840 * If the old mapping was valid (ref/mod 2841 * emulation creates 'invalid' mappings 2842 * initially) then make sure to frob 2843 * the cache. 2844 */ 2845 if ((oflags & PVF_NC) == 0 && 2846 l2pte_valid(opte)) { 2847 if (PV_BEEN_EXECD(oflags)) { 2848 pmap_idcache_wbinv_range(pm, va, 2849 PAGE_SIZE); 2850 } else 2851 if (PV_BEEN_REFD(oflags)) { 2852 pmap_dcache_wb_range(pm, va, 2853 PAGE_SIZE, true, 2854 (oflags & PVF_WRITE) == 0); 2855 } 2856 } 2857 #endif 2858 } else 2859 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2860 if ((flags & PMAP_CANFAIL) == 0) 2861 panic("pmap_enter: no pv entries"); 2862 2863 if (pm != pmap_kernel()) 2864 pmap_free_l2_bucket(pm, l2b, 0); 2865 pmap_release_pmap_lock(pm); 2866 PMAP_MAP_TO_HEAD_UNLOCK(); 2867 NPDEBUG(PDB_ENTER, 2868 printf("pmap_enter: ENOMEM\n")); 2869 return (ENOMEM); 2870 } 2871 2872 pmap_enter_pv(pg, pve, pm, va, nflags); 2873 } 2874 } else { 2875 /* 2876 * We're mapping an unmanaged page. 2877 * These are always readable, and possibly writable, from 2878 * the get go as we don't need to track ref/mod status. 2879 */ 2880 npte |= L2_S_PROTO; 2881 if (prot & VM_PROT_WRITE) 2882 npte |= L2_S_PROT_W; 2883 2884 /* 2885 * Make sure the vector table is mapped cacheable 2886 */ 2887 if (pm != pmap_kernel() && va == vector_page) 2888 npte |= pte_l2_s_cache_mode; 2889 2890 if (opg) { 2891 /* 2892 * Looks like there's an existing 'managed' mapping 2893 * at this address. 2894 */ 2895 simple_lock(&opg->mdpage.pvh_slock); 2896 pve = pmap_remove_pv(opg, pm, va, 0); 2897 pmap_vac_me_harder(opg, pm, 0); 2898 simple_unlock(&opg->mdpage.pvh_slock); 2899 oflags = pve->pv_flags; 2900 2901 #ifdef PMAP_CACHE_VIVT 2902 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2903 if (PV_BEEN_EXECD(oflags)) 2904 pmap_idcache_wbinv_range(pm, va, 2905 PAGE_SIZE); 2906 else 2907 if (PV_BEEN_REFD(oflags)) 2908 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2909 true, (oflags & PVF_WRITE) == 0); 2910 } 2911 #endif 2912 pool_put(&pmap_pv_pool, pve); 2913 } 2914 } 2915 2916 /* 2917 * Make sure userland mappings get the right permissions 2918 */ 2919 if (pm != pmap_kernel() && va != vector_page) 2920 npte |= L2_S_PROT_U; 2921 2922 /* 2923 * Keep the stats up to date 2924 */ 2925 if (opte == 0) { 2926 l2b->l2b_occupancy++; 2927 pm->pm_stats.resident_count++; 2928 } 2929 2930 NPDEBUG(PDB_ENTER, 2931 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2932 2933 /* 2934 * If this is just a wiring change, the two PTEs will be 2935 * identical, so there's no need to update the page table. 2936 */ 2937 if (npte != opte) { 2938 bool is_cached = pmap_is_cached(pm); 2939 2940 *ptep = npte; 2941 if (is_cached) { 2942 /* 2943 * We only need to frob the cache/tlb if this pmap 2944 * is current 2945 */ 2946 PTE_SYNC(ptep); 2947 if (va != vector_page && l2pte_valid(npte)) { 2948 /* 2949 * This mapping is likely to be accessed as 2950 * soon as we return to userland. Fix up the 2951 * L1 entry to avoid taking another 2952 * page/domain fault. 2953 */ 2954 pd_entry_t *pl1pd, l1pd; 2955 2956 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2957 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2958 L1_C_PROTO; 2959 if (*pl1pd != l1pd) { 2960 *pl1pd = l1pd; 2961 PTE_SYNC(pl1pd); 2962 } 2963 } 2964 } 2965 2966 if (PV_BEEN_EXECD(oflags)) 2967 pmap_tlb_flushID_SE(pm, va); 2968 else 2969 if (PV_BEEN_REFD(oflags)) 2970 pmap_tlb_flushD_SE(pm, va); 2971 2972 NPDEBUG(PDB_ENTER, 2973 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2974 is_cached, pm->pm_cstate.cs_all)); 2975 2976 if (pg != NULL) { 2977 simple_lock(&pg->mdpage.pvh_slock); 2978 pmap_vac_me_harder(pg, pm, va); 2979 simple_unlock(&pg->mdpage.pvh_slock); 2980 } 2981 } 2982 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 2983 simple_lock(&pg->mdpage.pvh_slock); 2984 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2985 KASSERT(((pg->mdpage.pvh_attrs & PVF_WRITE) == 0) == (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0)); 2986 simple_unlock(&pg->mdpage.pvh_slock); 2987 #endif 2988 2989 pmap_release_pmap_lock(pm); 2990 PMAP_MAP_TO_HEAD_UNLOCK(); 2991 2992 return (0); 2993 } 2994 2995 /* 2996 * pmap_remove() 2997 * 2998 * pmap_remove is responsible for nuking a number of mappings for a range 2999 * of virtual address space in the current pmap. To do this efficiently 3000 * is interesting, because in a number of cases a wide virtual address 3001 * range may be supplied that contains few actual mappings. So, the 3002 * optimisations are: 3003 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3004 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3005 * maybe do just a partial cache clean. This path of execution is 3006 * complicated by the fact that the cache must be flushed _before_ 3007 * the PTE is nuked, being a VAC :-) 3008 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3009 * all invalidations until pmap_update(), since pmap_remove_all() has 3010 * already flushed the cache. 3011 * 4. Maybe later fast-case a single page, but I don't think this is 3012 * going to make _that_ much difference overall. 3013 */ 3014 3015 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3016 3017 void 3018 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 3019 { 3020 struct l2_bucket *l2b; 3021 vaddr_t next_bucket; 3022 pt_entry_t *ptep; 3023 u_int cleanlist_idx, total, cnt; 3024 struct { 3025 vaddr_t va; 3026 pt_entry_t *ptep; 3027 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3028 u_int mappings, is_exec, is_refd; 3029 3030 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3031 "eva=%08lx\n", pm, sva, eva)); 3032 3033 /* 3034 * we lock in the pmap => pv_head direction 3035 */ 3036 PMAP_MAP_TO_HEAD_LOCK(); 3037 pmap_acquire_pmap_lock(pm); 3038 3039 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3040 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3041 if (pm->pm_cstate.cs_tlb == 0) 3042 pm->pm_remove_all = true; 3043 } else 3044 cleanlist_idx = 0; 3045 3046 total = 0; 3047 3048 while (sva < eva) { 3049 /* 3050 * Do one L2 bucket's worth at a time. 3051 */ 3052 next_bucket = L2_NEXT_BUCKET(sva); 3053 if (next_bucket > eva) 3054 next_bucket = eva; 3055 3056 l2b = pmap_get_l2_bucket(pm, sva); 3057 if (l2b == NULL) { 3058 sva = next_bucket; 3059 continue; 3060 } 3061 3062 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3063 3064 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3065 struct vm_page *pg; 3066 pt_entry_t pte; 3067 paddr_t pa; 3068 3069 pte = *ptep; 3070 3071 if (pte == 0) { 3072 /* Nothing here, move along */ 3073 continue; 3074 } 3075 3076 pa = l2pte_pa(pte); 3077 is_exec = 0; 3078 is_refd = 1; 3079 3080 /* 3081 * Update flags. In a number of circumstances, 3082 * we could cluster a lot of these and do a 3083 * number of sequential pages in one go. 3084 */ 3085 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3086 struct pv_entry *pve; 3087 simple_lock(&pg->mdpage.pvh_slock); 3088 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 3089 pmap_vac_me_harder(pg, pm, 0); 3090 simple_unlock(&pg->mdpage.pvh_slock); 3091 if (pve != NULL) { 3092 if (pm->pm_remove_all == false) { 3093 is_exec = 3094 PV_BEEN_EXECD(pve->pv_flags); 3095 is_refd = 3096 PV_BEEN_REFD(pve->pv_flags); 3097 } 3098 pool_put(&pmap_pv_pool, pve); 3099 } else 3100 if (skip_wired) { 3101 /* The mapping is wired. Skip it */ 3102 continue; 3103 } 3104 } else 3105 if (skip_wired) { 3106 /* Unmanaged pages are always wired. */ 3107 continue; 3108 } 3109 3110 mappings++; 3111 3112 if (!l2pte_valid(pte)) { 3113 /* 3114 * Ref/Mod emulation is still active for this 3115 * mapping, therefore it is has not yet been 3116 * accessed. No need to frob the cache/tlb. 3117 */ 3118 *ptep = 0; 3119 PTE_SYNC_CURRENT(pm, ptep); 3120 continue; 3121 } 3122 3123 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3124 /* Add to the clean list. */ 3125 cleanlist[cleanlist_idx].ptep = ptep; 3126 cleanlist[cleanlist_idx].va = 3127 sva | (is_exec & 1); 3128 cleanlist_idx++; 3129 } else 3130 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3131 /* Nuke everything if needed. */ 3132 #ifdef PMAP_CACHE_VIVT 3133 pmap_idcache_wbinv_all(pm); 3134 #endif 3135 pmap_tlb_flushID(pm); 3136 3137 /* 3138 * Roll back the previous PTE list, 3139 * and zero out the current PTE. 3140 */ 3141 for (cnt = 0; 3142 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3143 *cleanlist[cnt].ptep = 0; 3144 PTE_SYNC(cleanlist[cnt].ptep); 3145 } 3146 *ptep = 0; 3147 PTE_SYNC(ptep); 3148 cleanlist_idx++; 3149 pm->pm_remove_all = true; 3150 } else { 3151 *ptep = 0; 3152 PTE_SYNC(ptep); 3153 if (pm->pm_remove_all == false) { 3154 if (is_exec) 3155 pmap_tlb_flushID_SE(pm, sva); 3156 else 3157 if (is_refd) 3158 pmap_tlb_flushD_SE(pm, sva); 3159 } 3160 } 3161 } 3162 3163 /* 3164 * Deal with any left overs 3165 */ 3166 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3167 total += cleanlist_idx; 3168 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3169 if (pm->pm_cstate.cs_all != 0) { 3170 vaddr_t clva = cleanlist[cnt].va & ~1; 3171 if (cleanlist[cnt].va & 1) { 3172 #ifdef PMAP_CACHE_VIVT 3173 pmap_idcache_wbinv_range(pm, 3174 clva, PAGE_SIZE); 3175 #endif 3176 pmap_tlb_flushID_SE(pm, clva); 3177 } else { 3178 #ifdef PMAP_CACHE_VIVT 3179 pmap_dcache_wb_range(pm, 3180 clva, PAGE_SIZE, true, 3181 false); 3182 #endif 3183 pmap_tlb_flushD_SE(pm, clva); 3184 } 3185 } 3186 *cleanlist[cnt].ptep = 0; 3187 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3188 } 3189 3190 /* 3191 * If it looks like we're removing a whole bunch 3192 * of mappings, it's faster to just write-back 3193 * the whole cache now and defer TLB flushes until 3194 * pmap_update() is called. 3195 */ 3196 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3197 cleanlist_idx = 0; 3198 else { 3199 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3200 #ifdef PMAP_CACHE_VIVT 3201 pmap_idcache_wbinv_all(pm); 3202 #endif 3203 pm->pm_remove_all = true; 3204 } 3205 } 3206 3207 pmap_free_l2_bucket(pm, l2b, mappings); 3208 pm->pm_stats.resident_count -= mappings; 3209 } 3210 3211 pmap_release_pmap_lock(pm); 3212 PMAP_MAP_TO_HEAD_UNLOCK(); 3213 } 3214 3215 #ifdef PMAP_CACHE_VIPT 3216 static struct pv_entry * 3217 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3218 { 3219 struct pv_entry *pv; 3220 3221 simple_lock(&pg->mdpage.pvh_slock); 3222 KASSERT(pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 3223 KASSERT((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3224 3225 pv = pmap_remove_pv(pg, pmap_kernel(), va, false); 3226 KASSERT(pv); 3227 KASSERT(pv->pv_flags & PVF_KENTRY); 3228 3229 /* 3230 * If we are removing a writeable mapping to a cached exec page, 3231 * if it's the last mapping then clear it execness other sync 3232 * the page to the icache. 3233 */ 3234 if ((pg->mdpage.pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3235 && (pv->pv_flags & PVF_WRITE) != 0) { 3236 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 3237 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 3238 PMAPCOUNT(exec_discarded_kremove); 3239 } else { 3240 pmap_syncicache_page(pg); 3241 PMAPCOUNT(exec_synced_kremove); 3242 } 3243 } 3244 pmap_vac_me_harder(pg, pmap_kernel(), 0); 3245 simple_unlock(&pg->mdpage.pvh_slock); 3246 3247 return pv; 3248 } 3249 #endif /* PMAP_CACHE_VIPT */ 3250 3251 /* 3252 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3253 * 3254 * We assume there is already sufficient KVM space available 3255 * to do this, as we can't allocate L2 descriptor tables/metadata 3256 * from here. 3257 */ 3258 void 3259 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 3260 { 3261 struct l2_bucket *l2b; 3262 pt_entry_t *ptep, opte; 3263 #ifdef PMAP_CACHE_VIVT 3264 struct vm_page *pg = (prot & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3265 #endif 3266 #ifdef PMAP_CACHE_VIPT 3267 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3268 struct vm_page *opg; 3269 struct pv_entry *pv = NULL; 3270 #endif 3271 3272 NPDEBUG(PDB_KENTER, 3273 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3274 va, pa, prot)); 3275 3276 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3277 KDASSERT(l2b != NULL); 3278 3279 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3280 opte = *ptep; 3281 3282 if (opte == 0) { 3283 PMAPCOUNT(kenter_mappings); 3284 l2b->l2b_occupancy++; 3285 } else { 3286 PMAPCOUNT(kenter_remappings); 3287 #ifdef PMAP_CACHE_VIPT 3288 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3289 if (opg) { 3290 KASSERT(opg != pg); 3291 KASSERT((opg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3292 KASSERT((prot & PMAP_KMPAGE) == 0); 3293 simple_lock(&opg->mdpage.pvh_slock); 3294 pv = pmap_kremove_pg(opg, va); 3295 simple_unlock(&opg->mdpage.pvh_slock); 3296 } 3297 #endif 3298 if (l2pte_valid(opte)) { 3299 #ifdef PMAP_CACHE_VIVT 3300 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3301 #endif 3302 cpu_tlb_flushD_SE(va); 3303 cpu_cpwait(); 3304 } 3305 } 3306 3307 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3308 pte_l2_s_cache_mode; 3309 PTE_SYNC(ptep); 3310 3311 if (pg) { 3312 if (prot & PMAP_KMPAGE) { 3313 simple_lock(&pg->mdpage.pvh_slock); 3314 KASSERT(pg->mdpage.urw_mappings == 0); 3315 KASSERT(pg->mdpage.uro_mappings == 0); 3316 KASSERT(pg->mdpage.krw_mappings == 0); 3317 KASSERT(pg->mdpage.kro_mappings == 0); 3318 #ifdef PMAP_CACHE_VIPT 3319 KASSERT(pv == NULL); 3320 KASSERT((va & PVF_COLORED) == 0); 3321 KASSERT((pg->mdpage.pvh_attrs & PVF_NC) == 0); 3322 /* if there is a color conflict, evict from cache. */ 3323 if (pmap_is_page_colored_p(pg) 3324 && ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask)) { 3325 PMAPCOUNT(vac_color_change); 3326 pmap_flush_page(pg, true); 3327 } 3328 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 3329 pg->mdpage.pvh_attrs |= PVF_KMPAGE 3330 | PVF_COLORED | PVF_DIRTY 3331 | (va & arm_cache_prefer_mask); 3332 #endif 3333 #ifdef PMAP_CACHE_VIVT 3334 pg->mdpage.pvh_attrs |= PVF_KMPAGE; 3335 #endif 3336 pmap_kmpages++; 3337 simple_unlock(&pg->mdpage.pvh_slock); 3338 #ifdef PMAP_CACHE_VIPT 3339 } else { 3340 if (pv == NULL) { 3341 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3342 KASSERT(pv != NULL); 3343 } 3344 pmap_enter_pv(pg, pv, pmap_kernel(), va, 3345 PVF_WIRED | PVF_KENTRY 3346 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3347 if ((prot & VM_PROT_WRITE) 3348 && !(pg->mdpage.pvh_attrs & PVF_NC)) 3349 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3350 KASSERT((prot & VM_PROT_WRITE) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3351 simple_lock(&pg->mdpage.pvh_slock); 3352 pmap_vac_me_harder(pg, pmap_kernel(), va); 3353 simple_unlock(&pg->mdpage.pvh_slock); 3354 #endif 3355 } 3356 #ifdef PMAP_CACHE_VIPT 3357 } else { 3358 if (pv != NULL) 3359 pool_put(&pmap_pv_pool, pv); 3360 #endif 3361 } 3362 } 3363 3364 void 3365 pmap_kremove(vaddr_t va, vsize_t len) 3366 { 3367 struct l2_bucket *l2b; 3368 pt_entry_t *ptep, *sptep, opte; 3369 vaddr_t next_bucket, eva; 3370 u_int mappings; 3371 struct vm_page *opg; 3372 3373 PMAPCOUNT(kenter_unmappings); 3374 3375 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3376 va, len)); 3377 3378 eva = va + len; 3379 3380 while (va < eva) { 3381 next_bucket = L2_NEXT_BUCKET(va); 3382 if (next_bucket > eva) 3383 next_bucket = eva; 3384 3385 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3386 KDASSERT(l2b != NULL); 3387 3388 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3389 mappings = 0; 3390 3391 while (va < next_bucket) { 3392 opte = *ptep; 3393 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3394 if (opg) { 3395 if (opg->mdpage.pvh_attrs & PVF_KMPAGE) { 3396 simple_lock(&opg->mdpage.pvh_slock); 3397 KASSERT(opg->mdpage.urw_mappings == 0); 3398 KASSERT(opg->mdpage.uro_mappings == 0); 3399 KASSERT(opg->mdpage.krw_mappings == 0); 3400 KASSERT(opg->mdpage.kro_mappings == 0); 3401 opg->mdpage.pvh_attrs &= ~PVF_KMPAGE; 3402 #ifdef PMAP_CACHE_VIPT 3403 opg->mdpage.pvh_attrs &= ~PVF_WRITE; 3404 #endif 3405 pmap_kmpages--; 3406 simple_unlock(&opg->mdpage.pvh_slock); 3407 #ifdef PMAP_CACHE_VIPT 3408 } else { 3409 pool_put(&pmap_pv_pool, 3410 pmap_kremove_pg(opg, va)); 3411 #endif 3412 } 3413 } 3414 if (l2pte_valid(opte)) { 3415 #ifdef PMAP_CACHE_VIVT 3416 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3417 #endif 3418 cpu_tlb_flushD_SE(va); 3419 } 3420 if (opte) { 3421 *ptep = 0; 3422 mappings++; 3423 } 3424 va += PAGE_SIZE; 3425 ptep++; 3426 } 3427 KDASSERT(mappings <= l2b->l2b_occupancy); 3428 l2b->l2b_occupancy -= mappings; 3429 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3430 } 3431 cpu_cpwait(); 3432 } 3433 3434 bool 3435 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3436 { 3437 struct l2_dtable *l2; 3438 pd_entry_t *pl1pd, l1pd; 3439 pt_entry_t *ptep, pte; 3440 paddr_t pa; 3441 u_int l1idx; 3442 3443 pmap_acquire_pmap_lock(pm); 3444 3445 l1idx = L1_IDX(va); 3446 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3447 l1pd = *pl1pd; 3448 3449 if (l1pte_section_p(l1pd)) { 3450 /* 3451 * These should only happen for pmap_kernel() 3452 */ 3453 KDASSERT(pm == pmap_kernel()); 3454 pmap_release_pmap_lock(pm); 3455 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3456 } else { 3457 /* 3458 * Note that we can't rely on the validity of the L1 3459 * descriptor as an indication that a mapping exists. 3460 * We have to look it up in the L2 dtable. 3461 */ 3462 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3463 3464 if (l2 == NULL || 3465 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3466 pmap_release_pmap_lock(pm); 3467 return false; 3468 } 3469 3470 ptep = &ptep[l2pte_index(va)]; 3471 pte = *ptep; 3472 pmap_release_pmap_lock(pm); 3473 3474 if (pte == 0) 3475 return false; 3476 3477 switch (pte & L2_TYPE_MASK) { 3478 case L2_TYPE_L: 3479 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3480 break; 3481 3482 default: 3483 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3484 break; 3485 } 3486 } 3487 3488 if (pap != NULL) 3489 *pap = pa; 3490 3491 return true; 3492 } 3493 3494 void 3495 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3496 { 3497 struct l2_bucket *l2b; 3498 pt_entry_t *ptep, pte; 3499 vaddr_t next_bucket; 3500 u_int flags; 3501 u_int clr_mask; 3502 int flush; 3503 3504 NPDEBUG(PDB_PROTECT, 3505 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3506 pm, sva, eva, prot)); 3507 3508 if ((prot & VM_PROT_READ) == 0) { 3509 pmap_remove(pm, sva, eva); 3510 return; 3511 } 3512 3513 if (prot & VM_PROT_WRITE) { 3514 /* 3515 * If this is a read->write transition, just ignore it and let 3516 * uvm_fault() take care of it later. 3517 */ 3518 return; 3519 } 3520 3521 PMAP_MAP_TO_HEAD_LOCK(); 3522 pmap_acquire_pmap_lock(pm); 3523 3524 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3525 flags = 0; 3526 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3527 3528 while (sva < eva) { 3529 next_bucket = L2_NEXT_BUCKET(sva); 3530 if (next_bucket > eva) 3531 next_bucket = eva; 3532 3533 l2b = pmap_get_l2_bucket(pm, sva); 3534 if (l2b == NULL) { 3535 sva = next_bucket; 3536 continue; 3537 } 3538 3539 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3540 3541 while (sva < next_bucket) { 3542 pte = *ptep; 3543 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3544 struct vm_page *pg; 3545 u_int f; 3546 3547 #ifdef PMAP_CACHE_VIVT 3548 /* 3549 * OK, at this point, we know we're doing 3550 * write-protect operation. If the pmap is 3551 * active, write-back the page. 3552 */ 3553 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3554 false, false); 3555 #endif 3556 3557 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3558 pte &= ~L2_S_PROT_W; 3559 *ptep = pte; 3560 PTE_SYNC(ptep); 3561 3562 if (pg != NULL) { 3563 simple_lock(&pg->mdpage.pvh_slock); 3564 f = pmap_modify_pv(pg, pm, sva, 3565 clr_mask, 0); 3566 pmap_vac_me_harder(pg, pm, sva); 3567 simple_unlock(&pg->mdpage.pvh_slock); 3568 } else 3569 f = PVF_REF | PVF_EXEC; 3570 3571 if (flush >= 0) { 3572 flush++; 3573 flags |= f; 3574 } else 3575 if (PV_BEEN_EXECD(f)) 3576 pmap_tlb_flushID_SE(pm, sva); 3577 else 3578 if (PV_BEEN_REFD(f)) 3579 pmap_tlb_flushD_SE(pm, sva); 3580 } 3581 3582 sva += PAGE_SIZE; 3583 ptep++; 3584 } 3585 } 3586 3587 pmap_release_pmap_lock(pm); 3588 PMAP_MAP_TO_HEAD_UNLOCK(); 3589 3590 if (flush) { 3591 if (PV_BEEN_EXECD(flags)) 3592 pmap_tlb_flushID(pm); 3593 else 3594 if (PV_BEEN_REFD(flags)) 3595 pmap_tlb_flushD(pm); 3596 } 3597 } 3598 3599 void 3600 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3601 { 3602 struct l2_bucket *l2b; 3603 pt_entry_t *ptep; 3604 vaddr_t next_bucket; 3605 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3606 3607 NPDEBUG(PDB_EXEC, 3608 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3609 pm, sva, eva)); 3610 3611 PMAP_MAP_TO_HEAD_LOCK(); 3612 pmap_acquire_pmap_lock(pm); 3613 3614 while (sva < eva) { 3615 next_bucket = L2_NEXT_BUCKET(sva); 3616 if (next_bucket > eva) 3617 next_bucket = eva; 3618 3619 l2b = pmap_get_l2_bucket(pm, sva); 3620 if (l2b == NULL) { 3621 sva = next_bucket; 3622 continue; 3623 } 3624 3625 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3626 sva < next_bucket; 3627 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3628 if (l2pte_valid(*ptep)) { 3629 cpu_icache_sync_range(sva, 3630 min(page_size, eva - sva)); 3631 } 3632 } 3633 } 3634 3635 pmap_release_pmap_lock(pm); 3636 PMAP_MAP_TO_HEAD_UNLOCK(); 3637 } 3638 3639 void 3640 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3641 { 3642 3643 NPDEBUG(PDB_PROTECT, 3644 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3645 pg, VM_PAGE_TO_PHYS(pg), prot)); 3646 3647 switch(prot) { 3648 return; 3649 case VM_PROT_READ|VM_PROT_WRITE: 3650 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3651 pmap_clearbit(pg, PVF_EXEC); 3652 break; 3653 #endif 3654 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3655 break; 3656 3657 case VM_PROT_READ: 3658 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3659 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3660 break; 3661 #endif 3662 case VM_PROT_READ|VM_PROT_EXECUTE: 3663 pmap_clearbit(pg, PVF_WRITE); 3664 break; 3665 3666 default: 3667 pmap_page_remove(pg); 3668 break; 3669 } 3670 } 3671 3672 /* 3673 * pmap_clear_modify: 3674 * 3675 * Clear the "modified" attribute for a page. 3676 */ 3677 bool 3678 pmap_clear_modify(struct vm_page *pg) 3679 { 3680 bool rv; 3681 3682 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3683 rv = true; 3684 pmap_clearbit(pg, PVF_MOD); 3685 } else 3686 rv = false; 3687 3688 return (rv); 3689 } 3690 3691 /* 3692 * pmap_clear_reference: 3693 * 3694 * Clear the "referenced" attribute for a page. 3695 */ 3696 bool 3697 pmap_clear_reference(struct vm_page *pg) 3698 { 3699 bool rv; 3700 3701 if (pg->mdpage.pvh_attrs & PVF_REF) { 3702 rv = true; 3703 pmap_clearbit(pg, PVF_REF); 3704 } else 3705 rv = false; 3706 3707 return (rv); 3708 } 3709 3710 /* 3711 * pmap_is_modified: 3712 * 3713 * Test if a page has the "modified" attribute. 3714 */ 3715 /* See <arm/arm32/pmap.h> */ 3716 3717 /* 3718 * pmap_is_referenced: 3719 * 3720 * Test if a page has the "referenced" attribute. 3721 */ 3722 /* See <arm/arm32/pmap.h> */ 3723 3724 int 3725 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3726 { 3727 struct l2_dtable *l2; 3728 struct l2_bucket *l2b; 3729 pd_entry_t *pl1pd, l1pd; 3730 pt_entry_t *ptep, pte; 3731 paddr_t pa; 3732 u_int l1idx; 3733 int rv = 0; 3734 3735 PMAP_MAP_TO_HEAD_LOCK(); 3736 pmap_acquire_pmap_lock(pm); 3737 3738 l1idx = L1_IDX(va); 3739 3740 /* 3741 * If there is no l2_dtable for this address, then the process 3742 * has no business accessing it. 3743 * 3744 * Note: This will catch userland processes trying to access 3745 * kernel addresses. 3746 */ 3747 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3748 if (l2 == NULL) 3749 goto out; 3750 3751 /* 3752 * Likewise if there is no L2 descriptor table 3753 */ 3754 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3755 if (l2b->l2b_kva == NULL) 3756 goto out; 3757 3758 /* 3759 * Check the PTE itself. 3760 */ 3761 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3762 pte = *ptep; 3763 if (pte == 0) 3764 goto out; 3765 3766 /* 3767 * Catch a userland access to the vector page mapped at 0x0 3768 */ 3769 if (user && (pte & L2_S_PROT_U) == 0) 3770 goto out; 3771 3772 pa = l2pte_pa(pte); 3773 3774 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3775 /* 3776 * This looks like a good candidate for "page modified" 3777 * emulation... 3778 */ 3779 struct pv_entry *pv; 3780 struct vm_page *pg; 3781 3782 /* Extract the physical address of the page */ 3783 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3784 goto out; 3785 3786 /* Get the current flags for this page. */ 3787 simple_lock(&pg->mdpage.pvh_slock); 3788 3789 pv = pmap_find_pv(pg, pm, va); 3790 if (pv == NULL) { 3791 simple_unlock(&pg->mdpage.pvh_slock); 3792 goto out; 3793 } 3794 3795 /* 3796 * Do the flags say this page is writable? If not then it 3797 * is a genuine write fault. If yes then the write fault is 3798 * our fault as we did not reflect the write access in the 3799 * PTE. Now we know a write has occurred we can correct this 3800 * and also set the modified bit 3801 */ 3802 if ((pv->pv_flags & PVF_WRITE) == 0) { 3803 simple_unlock(&pg->mdpage.pvh_slock); 3804 goto out; 3805 } 3806 3807 NPDEBUG(PDB_FOLLOW, 3808 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3809 pm, va, VM_PAGE_TO_PHYS(pg))); 3810 3811 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 3812 pv->pv_flags |= PVF_REF | PVF_MOD; 3813 #ifdef PMAP_CACHE_VIPT 3814 /* 3815 * If there are cacheable mappings for this page, mark it dirty. 3816 */ 3817 if ((pg->mdpage.pvh_attrs & PVF_NC) == 0) 3818 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3819 #endif 3820 simple_unlock(&pg->mdpage.pvh_slock); 3821 3822 /* 3823 * Re-enable write permissions for the page. No need to call 3824 * pmap_vac_me_harder(), since this is just a 3825 * modified-emulation fault, and the PVF_WRITE bit isn't 3826 * changing. We've already set the cacheable bits based on 3827 * the assumption that we can write to this page. 3828 */ 3829 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3830 PTE_SYNC(ptep); 3831 rv = 1; 3832 } else 3833 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3834 /* 3835 * This looks like a good candidate for "page referenced" 3836 * emulation. 3837 */ 3838 struct pv_entry *pv; 3839 struct vm_page *pg; 3840 3841 /* Extract the physical address of the page */ 3842 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3843 goto out; 3844 3845 /* Get the current flags for this page. */ 3846 simple_lock(&pg->mdpage.pvh_slock); 3847 3848 pv = pmap_find_pv(pg, pm, va); 3849 if (pv == NULL) { 3850 simple_unlock(&pg->mdpage.pvh_slock); 3851 goto out; 3852 } 3853 3854 pg->mdpage.pvh_attrs |= PVF_REF; 3855 pv->pv_flags |= PVF_REF; 3856 simple_unlock(&pg->mdpage.pvh_slock); 3857 3858 NPDEBUG(PDB_FOLLOW, 3859 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3860 pm, va, VM_PAGE_TO_PHYS(pg))); 3861 3862 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3863 PTE_SYNC(ptep); 3864 rv = 1; 3865 } 3866 3867 /* 3868 * We know there is a valid mapping here, so simply 3869 * fix up the L1 if necessary. 3870 */ 3871 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3872 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3873 if (*pl1pd != l1pd) { 3874 *pl1pd = l1pd; 3875 PTE_SYNC(pl1pd); 3876 rv = 1; 3877 } 3878 3879 #ifdef CPU_SA110 3880 /* 3881 * There are bugs in the rev K SA110. This is a check for one 3882 * of them. 3883 */ 3884 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3885 curcpu()->ci_arm_cpurev < 3) { 3886 /* Always current pmap */ 3887 if (l2pte_valid(pte)) { 3888 extern int kernel_debug; 3889 if (kernel_debug & 1) { 3890 struct proc *p = curlwp->l_proc; 3891 printf("prefetch_abort: page is already " 3892 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3893 printf("prefetch_abort: pc=%08lx proc=%p " 3894 "process=%s\n", va, p, p->p_comm); 3895 printf("prefetch_abort: far=%08x fs=%x\n", 3896 cpu_faultaddress(), cpu_faultstatus()); 3897 } 3898 #ifdef DDB 3899 if (kernel_debug & 2) 3900 Debugger(); 3901 #endif 3902 rv = 1; 3903 } 3904 } 3905 #endif /* CPU_SA110 */ 3906 3907 #ifdef DEBUG 3908 /* 3909 * If 'rv == 0' at this point, it generally indicates that there is a 3910 * stale TLB entry for the faulting address. This happens when two or 3911 * more processes are sharing an L1. Since we don't flush the TLB on 3912 * a context switch between such processes, we can take domain faults 3913 * for mappings which exist at the same VA in both processes. EVEN IF 3914 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3915 * example. 3916 * 3917 * This is extremely likely to happen if pmap_enter() updated the L1 3918 * entry for a recently entered mapping. In this case, the TLB is 3919 * flushed for the new mapping, but there may still be TLB entries for 3920 * other mappings belonging to other processes in the 1MB range 3921 * covered by the L1 entry. 3922 * 3923 * Since 'rv == 0', we know that the L1 already contains the correct 3924 * value, so the fault must be due to a stale TLB entry. 3925 * 3926 * Since we always need to flush the TLB anyway in the case where we 3927 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 3928 * stale TLB entries dynamically. 3929 * 3930 * However, the above condition can ONLY happen if the current L1 is 3931 * being shared. If it happens when the L1 is unshared, it indicates 3932 * that other parts of the pmap are not doing their job WRT managing 3933 * the TLB. 3934 */ 3935 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 3936 extern int last_fault_code; 3937 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 3938 pm, va, ftype); 3939 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 3940 l2, l2b, ptep, pl1pd); 3941 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 3942 pte, l1pd, last_fault_code); 3943 #ifdef DDB 3944 Debugger(); 3945 #endif 3946 } 3947 #endif 3948 3949 cpu_tlb_flushID_SE(va); 3950 cpu_cpwait(); 3951 3952 rv = 1; 3953 3954 out: 3955 pmap_release_pmap_lock(pm); 3956 PMAP_MAP_TO_HEAD_UNLOCK(); 3957 3958 return (rv); 3959 } 3960 3961 /* 3962 * pmap_collect: free resources held by a pmap 3963 * 3964 * => optional function. 3965 * => called when a process is swapped out to free memory. 3966 */ 3967 void 3968 pmap_collect(pmap_t pm) 3969 { 3970 3971 #ifdef PMAP_CACHE_VIVT 3972 pmap_idcache_wbinv_all(pm); 3973 #endif 3974 pm->pm_remove_all = true; 3975 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 3976 pmap_update(pm); 3977 PMAPCOUNT(collects); 3978 } 3979 3980 /* 3981 * Routine: pmap_procwr 3982 * 3983 * Function: 3984 * Synchronize caches corresponding to [addr, addr+len) in p. 3985 * 3986 */ 3987 void 3988 pmap_procwr(struct proc *p, vaddr_t va, int len) 3989 { 3990 /* We only need to do anything if it is the current process. */ 3991 if (p == curproc) 3992 cpu_icache_sync_range(va, len); 3993 } 3994 3995 /* 3996 * Routine: pmap_unwire 3997 * Function: Clear the wired attribute for a map/virtual-address pair. 3998 * 3999 * In/out conditions: 4000 * The mapping must already exist in the pmap. 4001 */ 4002 void 4003 pmap_unwire(pmap_t pm, vaddr_t va) 4004 { 4005 struct l2_bucket *l2b; 4006 pt_entry_t *ptep, pte; 4007 struct vm_page *pg; 4008 paddr_t pa; 4009 4010 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4011 4012 PMAP_MAP_TO_HEAD_LOCK(); 4013 pmap_acquire_pmap_lock(pm); 4014 4015 l2b = pmap_get_l2_bucket(pm, va); 4016 KDASSERT(l2b != NULL); 4017 4018 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4019 pte = *ptep; 4020 4021 /* Extract the physical address of the page */ 4022 pa = l2pte_pa(pte); 4023 4024 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4025 /* Update the wired bit in the pv entry for this page. */ 4026 simple_lock(&pg->mdpage.pvh_slock); 4027 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 4028 simple_unlock(&pg->mdpage.pvh_slock); 4029 } 4030 4031 pmap_release_pmap_lock(pm); 4032 PMAP_MAP_TO_HEAD_UNLOCK(); 4033 } 4034 4035 void 4036 pmap_activate(struct lwp *l) 4037 { 4038 extern int block_userspace_access; 4039 pmap_t opm, npm, rpm; 4040 uint32_t odacr, ndacr; 4041 int oldirqstate; 4042 4043 /* 4044 * If activating a non-current lwp or the current lwp is 4045 * already active, just return. 4046 */ 4047 if (l != curlwp || 4048 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4049 return; 4050 4051 npm = l->l_proc->p_vmspace->vm_map.pmap; 4052 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4053 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4054 4055 /* 4056 * If TTB and DACR are unchanged, short-circuit all the 4057 * TLB/cache management stuff. 4058 */ 4059 if (pmap_previous_active_lwp != NULL) { 4060 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4061 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4062 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4063 4064 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4065 goto all_done; 4066 } else 4067 opm = NULL; 4068 4069 PMAPCOUNT(activations); 4070 block_userspace_access = 1; 4071 4072 /* 4073 * If switching to a user vmspace which is different to the 4074 * most recent one, and the most recent one is potentially 4075 * live in the cache, we must write-back and invalidate the 4076 * entire cache. 4077 */ 4078 rpm = pmap_recent_user; 4079 if (npm != pmap_kernel() && rpm && npm != rpm && 4080 rpm->pm_cstate.cs_cache) { 4081 rpm->pm_cstate.cs_cache = 0; 4082 #ifdef PMAP_CACHE_VIVT 4083 cpu_idcache_wbinv_all(); 4084 #endif 4085 } 4086 4087 /* No interrupts while we frob the TTB/DACR */ 4088 oldirqstate = disable_interrupts(IF32_bits); 4089 4090 /* 4091 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4092 * entry corresponding to 'vector_page' in the incoming L1 table 4093 * before switching to it otherwise subsequent interrupts/exceptions 4094 * (including domain faults!) will jump into hyperspace. 4095 */ 4096 if (npm->pm_pl1vec != NULL) { 4097 cpu_tlb_flushID_SE((u_int)vector_page); 4098 cpu_cpwait(); 4099 *npm->pm_pl1vec = npm->pm_l1vec; 4100 PTE_SYNC(npm->pm_pl1vec); 4101 } 4102 4103 cpu_domains(ndacr); 4104 4105 if (npm == pmap_kernel() || npm == rpm) { 4106 /* 4107 * Switching to a kernel thread, or back to the 4108 * same user vmspace as before... Simply update 4109 * the TTB (no TLB flush required) 4110 */ 4111 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4112 "r"(npm->pm_l1->l1_physaddr)); 4113 cpu_cpwait(); 4114 } else { 4115 /* 4116 * Otherwise, update TTB and flush TLB 4117 */ 4118 cpu_context_switch(npm->pm_l1->l1_physaddr); 4119 if (rpm != NULL) 4120 rpm->pm_cstate.cs_tlb = 0; 4121 } 4122 4123 restore_interrupts(oldirqstate); 4124 4125 block_userspace_access = 0; 4126 4127 all_done: 4128 /* 4129 * The new pmap is resident. Make sure it's marked 4130 * as resident in the cache/TLB. 4131 */ 4132 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4133 if (npm != pmap_kernel()) 4134 pmap_recent_user = npm; 4135 4136 /* The old pmap is not longer active */ 4137 if (opm != NULL) 4138 opm->pm_activated = false; 4139 4140 /* But the new one is */ 4141 npm->pm_activated = true; 4142 } 4143 4144 void 4145 pmap_deactivate(struct lwp *l) 4146 { 4147 4148 /* 4149 * If the process is exiting, make sure pmap_activate() does 4150 * a full MMU context-switch and cache flush, which we might 4151 * otherwise skip. See PR port-arm/38950. 4152 */ 4153 if (l->l_proc->p_sflag & PS_WEXIT) 4154 pmap_previous_active_lwp = NULL; 4155 4156 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4157 } 4158 4159 void 4160 pmap_update(pmap_t pm) 4161 { 4162 4163 if (pm->pm_remove_all) { 4164 /* 4165 * Finish up the pmap_remove_all() optimisation by flushing 4166 * the TLB. 4167 */ 4168 pmap_tlb_flushID(pm); 4169 pm->pm_remove_all = false; 4170 } 4171 4172 if (pmap_is_current(pm)) { 4173 /* 4174 * If we're dealing with a current userland pmap, move its L1 4175 * to the end of the LRU. 4176 */ 4177 if (pm != pmap_kernel()) 4178 pmap_use_l1(pm); 4179 4180 /* 4181 * We can assume we're done with frobbing the cache/tlb for 4182 * now. Make sure any future pmap ops don't skip cache/tlb 4183 * flushes. 4184 */ 4185 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4186 } 4187 4188 PMAPCOUNT(updates); 4189 4190 /* 4191 * make sure TLB/cache operations have completed. 4192 */ 4193 cpu_cpwait(); 4194 } 4195 4196 void 4197 pmap_remove_all(pmap_t pm) 4198 { 4199 4200 /* 4201 * The vmspace described by this pmap is about to be torn down. 4202 * Until pmap_update() is called, UVM will only make calls 4203 * to pmap_remove(). We can make life much simpler by flushing 4204 * the cache now, and deferring TLB invalidation to pmap_update(). 4205 */ 4206 #ifdef PMAP_CACHE_VIVT 4207 pmap_idcache_wbinv_all(pm); 4208 #endif 4209 pm->pm_remove_all = true; 4210 } 4211 4212 /* 4213 * Retire the given physical map from service. 4214 * Should only be called if the map contains no valid mappings. 4215 */ 4216 void 4217 pmap_destroy(pmap_t pm) 4218 { 4219 u_int count; 4220 4221 if (pm == NULL) 4222 return; 4223 4224 if (pm->pm_remove_all) { 4225 pmap_tlb_flushID(pm); 4226 pm->pm_remove_all = false; 4227 } 4228 4229 /* 4230 * Drop reference count 4231 */ 4232 mutex_enter(&pm->pm_lock); 4233 count = --pm->pm_obj.uo_refs; 4234 mutex_exit(&pm->pm_lock); 4235 if (count > 0) { 4236 if (pmap_is_current(pm)) { 4237 if (pm != pmap_kernel()) 4238 pmap_use_l1(pm); 4239 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4240 } 4241 return; 4242 } 4243 4244 /* 4245 * reference count is zero, free pmap resources and then free pmap. 4246 */ 4247 4248 if (vector_page < KERNEL_BASE) { 4249 KDASSERT(!pmap_is_current(pm)); 4250 4251 /* Remove the vector page mapping */ 4252 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4253 pmap_update(pm); 4254 } 4255 4256 LIST_REMOVE(pm, pm_list); 4257 4258 pmap_free_l1(pm); 4259 4260 if (pmap_recent_user == pm) 4261 pmap_recent_user = NULL; 4262 4263 UVM_OBJ_DESTROY(&pm->pm_obj); 4264 4265 /* return the pmap to the pool */ 4266 pool_cache_put(&pmap_cache, pm); 4267 } 4268 4269 4270 /* 4271 * void pmap_reference(pmap_t pm) 4272 * 4273 * Add a reference to the specified pmap. 4274 */ 4275 void 4276 pmap_reference(pmap_t pm) 4277 { 4278 4279 if (pm == NULL) 4280 return; 4281 4282 pmap_use_l1(pm); 4283 4284 mutex_enter(&pm->pm_lock); 4285 pm->pm_obj.uo_refs++; 4286 mutex_exit(&pm->pm_lock); 4287 } 4288 4289 #if ARM_MMU_V6 > 0 4290 4291 static struct evcnt pmap_prefer_nochange_ev = 4292 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4293 static struct evcnt pmap_prefer_change_ev = 4294 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4295 4296 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4297 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4298 4299 void 4300 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4301 { 4302 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4303 vaddr_t va = *vap; 4304 vaddr_t diff = (hint - va) & mask; 4305 if (diff == 0) { 4306 pmap_prefer_nochange_ev.ev_count++; 4307 } else { 4308 pmap_prefer_change_ev.ev_count++; 4309 if (__predict_false(td)) 4310 va -= mask + 1; 4311 *vap = va + diff; 4312 } 4313 } 4314 #endif /* ARM_MMU_V6 */ 4315 4316 /* 4317 * pmap_zero_page() 4318 * 4319 * Zero a given physical page by mapping it at a page hook point. 4320 * In doing the zero page op, the page we zero is mapped cachable, as with 4321 * StrongARM accesses to non-cached pages are non-burst making writing 4322 * _any_ bulk data very slow. 4323 */ 4324 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4325 void 4326 pmap_zero_page_generic(paddr_t phys) 4327 { 4328 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4329 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4330 #endif 4331 #ifdef PMAP_CACHE_VIPT 4332 /* Choose the last page color it had, if any */ 4333 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4334 #else 4335 const vsize_t va_offset = 0; 4336 #endif 4337 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4338 4339 #ifdef DEBUG 4340 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4341 panic("pmap_zero_page: page has mappings"); 4342 #endif 4343 4344 KDASSERT((phys & PGOFSET) == 0); 4345 4346 /* 4347 * Hook in the page, zero it, and purge the cache for that 4348 * zeroed page. Invalidate the TLB as needed. 4349 */ 4350 *ptep = L2_S_PROTO | phys | 4351 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4352 PTE_SYNC(ptep); 4353 cpu_tlb_flushD_SE(cdstp + va_offset); 4354 cpu_cpwait(); 4355 bzero_page(cdstp + va_offset); 4356 /* 4357 * Unmap the page. 4358 */ 4359 *ptep = 0; 4360 PTE_SYNC(ptep); 4361 cpu_tlb_flushD_SE(cdstp + va_offset); 4362 #ifdef PMAP_CACHE_VIVT 4363 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4364 #endif 4365 #ifdef PMAP_CACHE_VIPT 4366 /* 4367 * This page is now cache resident so it now has a page color. 4368 * Any contents have been obliterated so clear the EXEC flag. 4369 */ 4370 if (!pmap_is_page_colored_p(pg)) { 4371 PMAPCOUNT(vac_color_new); 4372 pg->mdpage.pvh_attrs |= PVF_COLORED; 4373 } 4374 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4375 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4376 PMAPCOUNT(exec_discarded_zero); 4377 } 4378 pg->mdpage.pvh_attrs |= PVF_DIRTY; 4379 #endif 4380 } 4381 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4382 4383 #if ARM_MMU_XSCALE == 1 4384 void 4385 pmap_zero_page_xscale(paddr_t phys) 4386 { 4387 #ifdef DEBUG 4388 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4389 4390 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4391 panic("pmap_zero_page: page has mappings"); 4392 #endif 4393 4394 KDASSERT((phys & PGOFSET) == 0); 4395 4396 /* 4397 * Hook in the page, zero it, and purge the cache for that 4398 * zeroed page. Invalidate the TLB as needed. 4399 */ 4400 *cdst_pte = L2_S_PROTO | phys | 4401 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4402 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4403 PTE_SYNC(cdst_pte); 4404 cpu_tlb_flushD_SE(cdstp); 4405 cpu_cpwait(); 4406 bzero_page(cdstp); 4407 xscale_cache_clean_minidata(); 4408 } 4409 #endif /* ARM_MMU_XSCALE == 1 */ 4410 4411 /* pmap_pageidlezero() 4412 * 4413 * The same as above, except that we assume that the page is not 4414 * mapped. This means we never have to flush the cache first. Called 4415 * from the idle loop. 4416 */ 4417 bool 4418 pmap_pageidlezero(paddr_t phys) 4419 { 4420 unsigned int i; 4421 int *ptr; 4422 bool rv = true; 4423 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4424 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4425 #endif 4426 #ifdef PMAP_CACHE_VIPT 4427 /* Choose the last page color it had, if any */ 4428 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4429 #else 4430 const vsize_t va_offset = 0; 4431 #endif 4432 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4433 4434 4435 #ifdef DEBUG 4436 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4437 panic("pmap_pageidlezero: page has mappings"); 4438 #endif 4439 4440 KDASSERT((phys & PGOFSET) == 0); 4441 4442 /* 4443 * Hook in the page, zero it, and purge the cache for that 4444 * zeroed page. Invalidate the TLB as needed. 4445 */ 4446 *ptep = L2_S_PROTO | phys | 4447 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4448 PTE_SYNC(ptep); 4449 cpu_tlb_flushD_SE(cdstp + va_offset); 4450 cpu_cpwait(); 4451 4452 for (i = 0, ptr = (int *)(cdstp + va_offset); 4453 i < (PAGE_SIZE / sizeof(int)); i++) { 4454 if (sched_curcpu_runnable_p() != 0) { 4455 /* 4456 * A process has become ready. Abort now, 4457 * so we don't keep it waiting while we 4458 * do slow memory access to finish this 4459 * page. 4460 */ 4461 rv = false; 4462 break; 4463 } 4464 *ptr++ = 0; 4465 } 4466 4467 #ifdef PMAP_CACHE_VIVT 4468 if (rv) 4469 /* 4470 * if we aborted we'll rezero this page again later so don't 4471 * purge it unless we finished it 4472 */ 4473 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4474 #elif defined(PMAP_CACHE_VIPT) 4475 /* 4476 * This page is now cache resident so it now has a page color. 4477 * Any contents have been obliterated so clear the EXEC flag. 4478 */ 4479 if (!pmap_is_page_colored_p(pg)) { 4480 PMAPCOUNT(vac_color_new); 4481 pg->mdpage.pvh_attrs |= PVF_COLORED; 4482 } 4483 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4484 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4485 PMAPCOUNT(exec_discarded_zero); 4486 } 4487 #endif 4488 /* 4489 * Unmap the page. 4490 */ 4491 *ptep = 0; 4492 PTE_SYNC(ptep); 4493 cpu_tlb_flushD_SE(cdstp + va_offset); 4494 4495 return (rv); 4496 } 4497 4498 /* 4499 * pmap_copy_page() 4500 * 4501 * Copy one physical page into another, by mapping the pages into 4502 * hook points. The same comment regarding cachability as in 4503 * pmap_zero_page also applies here. 4504 */ 4505 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4506 void 4507 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4508 { 4509 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4510 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4511 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4512 #endif 4513 #ifdef PMAP_CACHE_VIPT 4514 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4515 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4516 #else 4517 const vsize_t src_va_offset = 0; 4518 const vsize_t dst_va_offset = 0; 4519 #endif 4520 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4521 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4522 4523 #ifdef DEBUG 4524 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4525 panic("pmap_copy_page: dst page has mappings"); 4526 #endif 4527 4528 #ifdef PMAP_CACHE_VIPT 4529 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4530 #endif 4531 KDASSERT((src & PGOFSET) == 0); 4532 KDASSERT((dst & PGOFSET) == 0); 4533 4534 /* 4535 * Clean the source page. Hold the source page's lock for 4536 * the duration of the copy so that no other mappings can 4537 * be created while we have a potentially aliased mapping. 4538 */ 4539 simple_lock(&src_pg->mdpage.pvh_slock); 4540 #ifdef PMAP_CACHE_VIVT 4541 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4542 #endif 4543 4544 /* 4545 * Map the pages into the page hook points, copy them, and purge 4546 * the cache for the appropriate page. Invalidate the TLB 4547 * as required. 4548 */ 4549 *src_ptep = L2_S_PROTO 4550 | src 4551 #ifdef PMAP_CACHE_VIPT 4552 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4553 #endif 4554 #ifdef PMAP_CACHE_VIVT 4555 | pte_l2_s_cache_mode 4556 #endif 4557 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4558 *dst_ptep = L2_S_PROTO | dst | 4559 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4560 PTE_SYNC(src_ptep); 4561 PTE_SYNC(dst_ptep); 4562 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4563 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4564 cpu_cpwait(); 4565 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4566 #ifdef PMAP_CACHE_VIVT 4567 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4568 #endif 4569 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4570 #ifdef PMAP_CACHE_VIVT 4571 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4572 #endif 4573 /* 4574 * Unmap the pages. 4575 */ 4576 *src_ptep = 0; 4577 *dst_ptep = 0; 4578 PTE_SYNC(src_ptep); 4579 PTE_SYNC(dst_ptep); 4580 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4581 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4582 #ifdef PMAP_CACHE_VIPT 4583 /* 4584 * Now that the destination page is in the cache, mark it as colored. 4585 * If this was an exec page, discard it. 4586 */ 4587 if (!pmap_is_page_colored_p(dst_pg)) { 4588 PMAPCOUNT(vac_color_new); 4589 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4590 } 4591 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4592 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4593 PMAPCOUNT(exec_discarded_copy); 4594 } 4595 dst_pg->mdpage.pvh_attrs |= PVF_DIRTY; 4596 #endif 4597 } 4598 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4599 4600 #if ARM_MMU_XSCALE == 1 4601 void 4602 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4603 { 4604 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4605 #ifdef DEBUG 4606 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4607 4608 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4609 panic("pmap_copy_page: dst page has mappings"); 4610 #endif 4611 4612 KDASSERT((src & PGOFSET) == 0); 4613 KDASSERT((dst & PGOFSET) == 0); 4614 4615 /* 4616 * Clean the source page. Hold the source page's lock for 4617 * the duration of the copy so that no other mappings can 4618 * be created while we have a potentially aliased mapping. 4619 */ 4620 simple_lock(&src_pg->mdpage.pvh_slock); 4621 #ifdef PMAP_CACHE_VIVT 4622 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4623 #endif 4624 4625 /* 4626 * Map the pages into the page hook points, copy them, and purge 4627 * the cache for the appropriate page. Invalidate the TLB 4628 * as required. 4629 */ 4630 *csrc_pte = L2_S_PROTO | src | 4631 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4632 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4633 PTE_SYNC(csrc_pte); 4634 *cdst_pte = L2_S_PROTO | dst | 4635 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4636 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4637 PTE_SYNC(cdst_pte); 4638 cpu_tlb_flushD_SE(csrcp); 4639 cpu_tlb_flushD_SE(cdstp); 4640 cpu_cpwait(); 4641 bcopy_page(csrcp, cdstp); 4642 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4643 xscale_cache_clean_minidata(); 4644 } 4645 #endif /* ARM_MMU_XSCALE == 1 */ 4646 4647 /* 4648 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4649 * 4650 * Return the start and end addresses of the kernel's virtual space. 4651 * These values are setup in pmap_bootstrap and are updated as pages 4652 * are allocated. 4653 */ 4654 void 4655 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4656 { 4657 *start = virtual_avail; 4658 *end = virtual_end; 4659 } 4660 4661 /* 4662 * Helper function for pmap_grow_l2_bucket() 4663 */ 4664 static inline int 4665 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4666 { 4667 struct l2_bucket *l2b; 4668 pt_entry_t *ptep; 4669 paddr_t pa; 4670 4671 if (uvm.page_init_done == false) { 4672 #ifdef PMAP_STEAL_MEMORY 4673 pv_addr_t pv; 4674 pmap_boot_pagealloc(PAGE_SIZE, 4675 #ifdef PMAP_CACHE_VIPT 4676 arm_cache_prefer_mask, 4677 va & arm_cache_prefer_mask, 4678 #else 4679 0, 0, 4680 #endif 4681 &pv); 4682 pa = pv.pv_pa; 4683 #else 4684 if (uvm_page_physget(&pa) == false) 4685 return (1); 4686 #endif /* PMAP_STEAL_MEMORY */ 4687 } else { 4688 struct vm_page *pg; 4689 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4690 if (pg == NULL) 4691 return (1); 4692 pa = VM_PAGE_TO_PHYS(pg); 4693 #ifdef PMAP_CACHE_VIPT 4694 /* 4695 * This new page must not have any mappings. Enter it via 4696 * pmap_kenter_pa and let that routine do the hard work. 4697 */ 4698 KASSERT(SLIST_EMPTY(&pg->mdpage.pvh_list)); 4699 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 4700 #endif 4701 } 4702 4703 if (pap) 4704 *pap = pa; 4705 4706 PMAPCOUNT(pt_mappings); 4707 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4708 KDASSERT(l2b != NULL); 4709 4710 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4711 *ptep = L2_S_PROTO | pa | cache_mode | 4712 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4713 PTE_SYNC(ptep); 4714 memset((void *)va, 0, PAGE_SIZE); 4715 return (0); 4716 } 4717 4718 /* 4719 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4720 * used by pmap_growkernel(). 4721 */ 4722 static inline struct l2_bucket * 4723 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4724 { 4725 struct l2_dtable *l2; 4726 struct l2_bucket *l2b; 4727 u_short l1idx; 4728 vaddr_t nva; 4729 4730 l1idx = L1_IDX(va); 4731 4732 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4733 /* 4734 * No mapping at this address, as there is 4735 * no entry in the L1 table. 4736 * Need to allocate a new l2_dtable. 4737 */ 4738 nva = pmap_kernel_l2dtable_kva; 4739 if ((nva & PGOFSET) == 0) { 4740 /* 4741 * Need to allocate a backing page 4742 */ 4743 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4744 return (NULL); 4745 } 4746 4747 l2 = (struct l2_dtable *)nva; 4748 nva += sizeof(struct l2_dtable); 4749 4750 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4751 /* 4752 * The new l2_dtable straddles a page boundary. 4753 * Map in another page to cover it. 4754 */ 4755 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4756 return (NULL); 4757 } 4758 4759 pmap_kernel_l2dtable_kva = nva; 4760 4761 /* 4762 * Link it into the parent pmap 4763 */ 4764 pm->pm_l2[L2_IDX(l1idx)] = l2; 4765 } 4766 4767 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4768 4769 /* 4770 * Fetch pointer to the L2 page table associated with the address. 4771 */ 4772 if (l2b->l2b_kva == NULL) { 4773 pt_entry_t *ptep; 4774 4775 /* 4776 * No L2 page table has been allocated. Chances are, this 4777 * is because we just allocated the l2_dtable, above. 4778 */ 4779 nva = pmap_kernel_l2ptp_kva; 4780 ptep = (pt_entry_t *)nva; 4781 if ((nva & PGOFSET) == 0) { 4782 /* 4783 * Need to allocate a backing page 4784 */ 4785 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4786 &pmap_kernel_l2ptp_phys)) 4787 return (NULL); 4788 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4789 } 4790 4791 l2->l2_occupancy++; 4792 l2b->l2b_kva = ptep; 4793 l2b->l2b_l1idx = l1idx; 4794 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4795 4796 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4797 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4798 } 4799 4800 return (l2b); 4801 } 4802 4803 vaddr_t 4804 pmap_growkernel(vaddr_t maxkvaddr) 4805 { 4806 pmap_t kpm = pmap_kernel(); 4807 struct l1_ttable *l1; 4808 struct l2_bucket *l2b; 4809 pd_entry_t *pl1pd; 4810 int s; 4811 4812 if (maxkvaddr <= pmap_curmaxkvaddr) 4813 goto out; /* we are OK */ 4814 4815 NPDEBUG(PDB_GROWKERN, 4816 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4817 pmap_curmaxkvaddr, maxkvaddr)); 4818 4819 KDASSERT(maxkvaddr <= virtual_end); 4820 4821 /* 4822 * whoops! we need to add kernel PTPs 4823 */ 4824 4825 s = splhigh(); /* to be safe */ 4826 mutex_enter(&kpm->pm_lock); 4827 4828 /* Map 1MB at a time */ 4829 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4830 4831 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4832 KDASSERT(l2b != NULL); 4833 4834 /* Distribute new L1 entry to all other L1s */ 4835 SLIST_FOREACH(l1, &l1_list, l1_link) { 4836 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4837 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4838 L1_C_PROTO; 4839 PTE_SYNC(pl1pd); 4840 } 4841 } 4842 4843 /* 4844 * flush out the cache, expensive but growkernel will happen so 4845 * rarely 4846 */ 4847 cpu_dcache_wbinv_all(); 4848 cpu_tlb_flushD(); 4849 cpu_cpwait(); 4850 4851 mutex_exit(&kpm->pm_lock); 4852 splx(s); 4853 4854 out: 4855 return (pmap_curmaxkvaddr); 4856 } 4857 4858 /************************ Utility routines ****************************/ 4859 4860 /* 4861 * vector_page_setprot: 4862 * 4863 * Manipulate the protection of the vector page. 4864 */ 4865 void 4866 vector_page_setprot(int prot) 4867 { 4868 struct l2_bucket *l2b; 4869 pt_entry_t *ptep; 4870 4871 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4872 KDASSERT(l2b != NULL); 4873 4874 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4875 4876 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4877 PTE_SYNC(ptep); 4878 cpu_tlb_flushD_SE(vector_page); 4879 cpu_cpwait(); 4880 } 4881 4882 /* 4883 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4884 * Returns true if the mapping exists, else false. 4885 * 4886 * NOTE: This function is only used by a couple of arm-specific modules. 4887 * It is not safe to take any pmap locks here, since we could be right 4888 * in the middle of debugging the pmap anyway... 4889 * 4890 * It is possible for this routine to return false even though a valid 4891 * mapping does exist. This is because we don't lock, so the metadata 4892 * state may be inconsistent. 4893 * 4894 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4895 * a "section" mapping. 4896 */ 4897 bool 4898 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4899 { 4900 struct l2_dtable *l2; 4901 pd_entry_t *pl1pd, l1pd; 4902 pt_entry_t *ptep; 4903 u_short l1idx; 4904 4905 if (pm->pm_l1 == NULL) 4906 return false; 4907 4908 l1idx = L1_IDX(va); 4909 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4910 l1pd = *pl1pd; 4911 4912 if (l1pte_section_p(l1pd)) { 4913 *ptp = NULL; 4914 return true; 4915 } 4916 4917 if (pm->pm_l2 == NULL) 4918 return false; 4919 4920 l2 = pm->pm_l2[L2_IDX(l1idx)]; 4921 4922 if (l2 == NULL || 4923 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 4924 return false; 4925 } 4926 4927 *ptp = &ptep[l2pte_index(va)]; 4928 return true; 4929 } 4930 4931 bool 4932 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 4933 { 4934 u_short l1idx; 4935 4936 if (pm->pm_l1 == NULL) 4937 return false; 4938 4939 l1idx = L1_IDX(va); 4940 *pdp = &pm->pm_l1->l1_kva[l1idx]; 4941 4942 return true; 4943 } 4944 4945 /************************ Bootstrapping routines ****************************/ 4946 4947 static void 4948 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 4949 { 4950 int i; 4951 4952 l1->l1_kva = l1pt; 4953 l1->l1_domain_use_count = 0; 4954 l1->l1_domain_first = 0; 4955 4956 for (i = 0; i < PMAP_DOMAINS; i++) 4957 l1->l1_domain_free[i] = i + 1; 4958 4959 /* 4960 * Copy the kernel's L1 entries to each new L1. 4961 */ 4962 if (pmap_initialized) 4963 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 4964 4965 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 4966 &l1->l1_physaddr) == false) 4967 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 4968 4969 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 4970 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 4971 } 4972 4973 /* 4974 * pmap_bootstrap() is called from the board-specific initarm() routine 4975 * once the kernel L1/L2 descriptors tables have been set up. 4976 * 4977 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 4978 * spread over a number of disparate files/functions. 4979 * 4980 * We are passed the following parameters 4981 * - kernel_l1pt 4982 * This is a pointer to the base of the kernel's L1 translation table. 4983 * - vstart 4984 * 1MB-aligned start of managed kernel virtual memory. 4985 * - vend 4986 * 1MB-aligned end of managed kernel virtual memory. 4987 * 4988 * We use the first parameter to build the metadata (struct l1_ttable and 4989 * struct l2_dtable) necessary to track kernel mappings. 4990 */ 4991 #define PMAP_STATIC_L2_SIZE 16 4992 void 4993 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 4994 { 4995 static struct l1_ttable static_l1; 4996 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 4997 struct l1_ttable *l1 = &static_l1; 4998 struct l2_dtable *l2; 4999 struct l2_bucket *l2b; 5000 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5001 pmap_t pm = pmap_kernel(); 5002 pd_entry_t pde; 5003 pt_entry_t *ptep; 5004 paddr_t pa; 5005 vaddr_t va; 5006 vsize_t size; 5007 int nptes, l1idx, l2idx, l2next = 0; 5008 5009 /* 5010 * Initialise the kernel pmap object 5011 */ 5012 pm->pm_l1 = l1; 5013 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5014 pm->pm_activated = true; 5015 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5016 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5017 5018 /* 5019 * Scan the L1 translation table created by initarm() and create 5020 * the required metadata for all valid mappings found in it. 5021 */ 5022 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5023 pde = l1pt[l1idx]; 5024 5025 /* 5026 * We're only interested in Coarse mappings. 5027 * pmap_extract() can deal with section mappings without 5028 * recourse to checking L2 metadata. 5029 */ 5030 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5031 continue; 5032 5033 /* 5034 * Lookup the KVA of this L2 descriptor table 5035 */ 5036 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5037 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5038 if (ptep == NULL) { 5039 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5040 (u_int)l1idx << L1_S_SHIFT, pa); 5041 } 5042 5043 /* 5044 * Fetch the associated L2 metadata structure. 5045 * Allocate a new one if necessary. 5046 */ 5047 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5048 if (l2next == PMAP_STATIC_L2_SIZE) 5049 panic("pmap_bootstrap: out of static L2s"); 5050 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5051 } 5052 5053 /* 5054 * One more L1 slot tracked... 5055 */ 5056 l2->l2_occupancy++; 5057 5058 /* 5059 * Fill in the details of the L2 descriptor in the 5060 * appropriate bucket. 5061 */ 5062 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5063 l2b->l2b_kva = ptep; 5064 l2b->l2b_phys = pa; 5065 l2b->l2b_l1idx = l1idx; 5066 5067 /* 5068 * Establish an initial occupancy count for this descriptor 5069 */ 5070 for (l2idx = 0; 5071 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5072 l2idx++) { 5073 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5074 l2b->l2b_occupancy++; 5075 } 5076 } 5077 5078 /* 5079 * Make sure the descriptor itself has the correct cache mode. 5080 * If not, fix it, but whine about the problem. Port-meisters 5081 * should consider this a clue to fix up their initarm() 5082 * function. :) 5083 */ 5084 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5085 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5086 "L2 pte @ %p\n", ptep); 5087 } 5088 } 5089 5090 /* 5091 * Ensure the primary (kernel) L1 has the correct cache mode for 5092 * a page table. Bitch if it is not correctly set. 5093 */ 5094 for (va = (vaddr_t)l1pt; 5095 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5096 if (pmap_set_pt_cache_mode(l1pt, va)) 5097 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5098 "primary L1 @ 0x%lx\n", va); 5099 } 5100 5101 cpu_dcache_wbinv_all(); 5102 cpu_tlb_flushID(); 5103 cpu_cpwait(); 5104 5105 /* 5106 * now we allocate the "special" VAs which are used for tmp mappings 5107 * by the pmap (and other modules). we allocate the VAs by advancing 5108 * virtual_avail (note that there are no pages mapped at these VAs). 5109 * 5110 * Managed KVM space start from wherever initarm() tells us. 5111 */ 5112 virtual_avail = vstart; 5113 virtual_end = vend; 5114 5115 #ifdef PMAP_CACHE_VIPT 5116 /* 5117 * If we have a VIPT cache, we need one page/pte per possible alias 5118 * page so we won't violate cache aliasing rules. 5119 */ 5120 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5121 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5122 #else 5123 nptes = 1; 5124 #endif 5125 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5126 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5127 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5128 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5129 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5130 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5131 (void *)&msgbufaddr, NULL); 5132 5133 /* 5134 * Allocate a range of kernel virtual address space to be used 5135 * for L2 descriptor tables and metadata allocation in 5136 * pmap_growkernel(). 5137 */ 5138 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5139 pmap_alloc_specials(&virtual_avail, 5140 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5141 &pmap_kernel_l2ptp_kva, NULL); 5142 5143 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5144 pmap_alloc_specials(&virtual_avail, 5145 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5146 &pmap_kernel_l2dtable_kva, NULL); 5147 5148 /* 5149 * init the static-global locks and global pmap list. 5150 */ 5151 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5152 5153 /* 5154 * We can now initialise the first L1's metadata. 5155 */ 5156 SLIST_INIT(&l1_list); 5157 TAILQ_INIT(&l1_lru_list); 5158 simple_lock_init(&l1_lru_lock); 5159 pmap_init_l1(l1, l1pt); 5160 5161 /* Set up vector page L1 details, if necessary */ 5162 if (vector_page < KERNEL_BASE) { 5163 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5164 l2b = pmap_get_l2_bucket(pm, vector_page); 5165 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5166 L1_C_DOM(pm->pm_domain); 5167 } else 5168 pm->pm_pl1vec = NULL; 5169 5170 /* 5171 * Initialize the pmap cache 5172 */ 5173 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5174 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5175 LIST_INIT(&pmap_pmaps); 5176 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5177 5178 /* 5179 * Initialize the pv pool. 5180 */ 5181 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5182 &pmap_bootstrap_pv_allocator, IPL_NONE); 5183 5184 /* 5185 * Initialize the L2 dtable pool and cache. 5186 */ 5187 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5188 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5189 5190 /* 5191 * Initialise the L2 descriptor table pool and cache 5192 */ 5193 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5194 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5195 pmap_l2ptp_ctor, NULL, NULL); 5196 5197 cpu_dcache_wbinv_all(); 5198 } 5199 5200 static int 5201 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5202 { 5203 pd_entry_t *pdep, pde; 5204 pt_entry_t *ptep, pte; 5205 vaddr_t pa; 5206 int rv = 0; 5207 5208 /* 5209 * Make sure the descriptor itself has the correct cache mode 5210 */ 5211 pdep = &kl1[L1_IDX(va)]; 5212 pde = *pdep; 5213 5214 if (l1pte_section_p(pde)) { 5215 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5216 *pdep = (pde & ~L1_S_CACHE_MASK) | 5217 pte_l1_s_cache_mode_pt; 5218 PTE_SYNC(pdep); 5219 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5220 rv = 1; 5221 } 5222 } else { 5223 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5224 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5225 if (ptep == NULL) 5226 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5227 5228 ptep = &ptep[l2pte_index(va)]; 5229 pte = *ptep; 5230 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5231 *ptep = (pte & ~L2_S_CACHE_MASK) | 5232 pte_l2_s_cache_mode_pt; 5233 PTE_SYNC(ptep); 5234 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5235 rv = 1; 5236 } 5237 } 5238 5239 return (rv); 5240 } 5241 5242 static void 5243 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5244 { 5245 vaddr_t va = *availp; 5246 struct l2_bucket *l2b; 5247 5248 if (ptep) { 5249 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5250 if (l2b == NULL) 5251 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5252 5253 if (ptep) 5254 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5255 } 5256 5257 *vap = va; 5258 *availp = va + (PAGE_SIZE * pages); 5259 } 5260 5261 void 5262 pmap_init(void) 5263 { 5264 extern int physmem; 5265 5266 /* 5267 * Set the available memory vars - These do not map to real memory 5268 * addresses and cannot as the physical memory is fragmented. 5269 * They are used by ps for %mem calculations. 5270 * One could argue whether this should be the entire memory or just 5271 * the memory that is useable in a user process. 5272 */ 5273 avail_start = 0; 5274 avail_end = physmem * PAGE_SIZE; 5275 5276 /* 5277 * Now we need to free enough pv_entry structures to allow us to get 5278 * the kmem_map/kmem_object allocated and inited (done after this 5279 * function is finished). to do this we allocate one bootstrap page out 5280 * of kernel_map and use it to provide an initial pool of pv_entry 5281 * structures. we never free this page. 5282 */ 5283 pool_setlowat(&pmap_pv_pool, 5284 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5285 5286 pmap_initialized = true; 5287 } 5288 5289 static vaddr_t last_bootstrap_page = 0; 5290 static void *free_bootstrap_pages = NULL; 5291 5292 static void * 5293 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5294 { 5295 extern void *pool_page_alloc(struct pool *, int); 5296 vaddr_t new_page; 5297 void *rv; 5298 5299 if (pmap_initialized) 5300 return (pool_page_alloc(pp, flags)); 5301 5302 if (free_bootstrap_pages) { 5303 rv = free_bootstrap_pages; 5304 free_bootstrap_pages = *((void **)rv); 5305 return (rv); 5306 } 5307 5308 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5309 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5310 5311 KASSERT(new_page > last_bootstrap_page); 5312 last_bootstrap_page = new_page; 5313 return ((void *)new_page); 5314 } 5315 5316 static void 5317 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5318 { 5319 extern void pool_page_free(struct pool *, void *); 5320 5321 if ((vaddr_t)v <= last_bootstrap_page) { 5322 *((void **)v) = free_bootstrap_pages; 5323 free_bootstrap_pages = v; 5324 return; 5325 } 5326 5327 if (pmap_initialized) { 5328 pool_page_free(pp, v); 5329 return; 5330 } 5331 } 5332 5333 /* 5334 * pmap_postinit() 5335 * 5336 * This routine is called after the vm and kmem subsystems have been 5337 * initialised. This allows the pmap code to perform any initialisation 5338 * that can only be done one the memory allocation is in place. 5339 */ 5340 void 5341 pmap_postinit(void) 5342 { 5343 extern paddr_t physical_start, physical_end; 5344 struct l2_bucket *l2b; 5345 struct l1_ttable *l1; 5346 struct pglist plist; 5347 struct vm_page *m; 5348 pd_entry_t *pl1pt; 5349 pt_entry_t *ptep, pte; 5350 vaddr_t va, eva; 5351 u_int loop, needed; 5352 int error; 5353 5354 pool_cache_setlowat(&pmap_l2ptp_cache, 5355 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5356 pool_cache_setlowat(&pmap_l2dtable_cache, 5357 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5358 5359 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5360 needed -= 1; 5361 5362 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5363 5364 for (loop = 0; loop < needed; loop++, l1++) { 5365 /* Allocate a L1 page table */ 5366 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5367 if (va == 0) 5368 panic("Cannot allocate L1 KVM"); 5369 5370 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5371 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5372 if (error) 5373 panic("Cannot allocate L1 physical pages"); 5374 5375 m = TAILQ_FIRST(&plist); 5376 eva = va + L1_TABLE_SIZE; 5377 pl1pt = (pd_entry_t *)va; 5378 5379 while (m && va < eva) { 5380 paddr_t pa = VM_PAGE_TO_PHYS(m); 5381 5382 pmap_kenter_pa(va, pa, 5383 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 5384 5385 /* 5386 * Make sure the L1 descriptor table is mapped 5387 * with the cache-mode set to write-through. 5388 */ 5389 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5390 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5391 pte = *ptep; 5392 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5393 *ptep = pte; 5394 PTE_SYNC(ptep); 5395 cpu_tlb_flushD_SE(va); 5396 5397 va += PAGE_SIZE; 5398 m = TAILQ_NEXT(m, pageq.queue); 5399 } 5400 5401 #ifdef DIAGNOSTIC 5402 if (m) 5403 panic("pmap_alloc_l1pt: pglist not empty"); 5404 #endif /* DIAGNOSTIC */ 5405 5406 pmap_init_l1(l1, pl1pt); 5407 } 5408 5409 #ifdef DEBUG 5410 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5411 needed); 5412 #endif 5413 } 5414 5415 /* 5416 * Note that the following routines are used by board-specific initialisation 5417 * code to configure the initial kernel page tables. 5418 * 5419 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5420 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5421 * behaviour of the old pmap, and provides an easy migration path for 5422 * initial bring-up of the new pmap on existing ports. Fortunately, 5423 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5424 * will be deprecated. 5425 * 5426 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5427 * tables. 5428 */ 5429 5430 /* 5431 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5432 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5433 * find them as necessary. 5434 * 5435 * Note that the data on this list MUST remain valid after initarm() returns, 5436 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5437 */ 5438 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5439 5440 static vaddr_t 5441 kernel_pt_lookup(paddr_t pa) 5442 { 5443 pv_addr_t *pv; 5444 5445 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5446 #ifndef ARM32_NEW_VM_LAYOUT 5447 if (pv->pv_pa == (pa & ~PGOFSET)) 5448 return (pv->pv_va | (pa & PGOFSET)); 5449 #else 5450 if (pv->pv_pa == pa) 5451 return (pv->pv_va); 5452 #endif 5453 } 5454 return (0); 5455 } 5456 5457 /* 5458 * pmap_map_section: 5459 * 5460 * Create a single section mapping. 5461 */ 5462 void 5463 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5464 { 5465 pd_entry_t *pde = (pd_entry_t *) l1pt; 5466 pd_entry_t fl; 5467 5468 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5469 5470 switch (cache) { 5471 case PTE_NOCACHE: 5472 default: 5473 fl = 0; 5474 break; 5475 5476 case PTE_CACHE: 5477 fl = pte_l1_s_cache_mode; 5478 break; 5479 5480 case PTE_PAGETABLE: 5481 fl = pte_l1_s_cache_mode_pt; 5482 break; 5483 } 5484 5485 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5486 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5487 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5488 } 5489 5490 /* 5491 * pmap_map_entry: 5492 * 5493 * Create a single page mapping. 5494 */ 5495 void 5496 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5497 { 5498 pd_entry_t *pde = (pd_entry_t *) l1pt; 5499 pt_entry_t fl; 5500 pt_entry_t *pte; 5501 5502 KASSERT(((va | pa) & PGOFSET) == 0); 5503 5504 switch (cache) { 5505 case PTE_NOCACHE: 5506 default: 5507 fl = 0; 5508 break; 5509 5510 case PTE_CACHE: 5511 fl = pte_l2_s_cache_mode; 5512 break; 5513 5514 case PTE_PAGETABLE: 5515 fl = pte_l2_s_cache_mode_pt; 5516 break; 5517 } 5518 5519 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5520 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5521 5522 #ifndef ARM32_NEW_VM_LAYOUT 5523 pte = (pt_entry_t *) 5524 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5525 #else 5526 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5527 #endif 5528 if (pte == NULL) 5529 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5530 5531 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5532 #ifndef ARM32_NEW_VM_LAYOUT 5533 pte += (va >> PGSHIFT) & 0x3ff; 5534 #else 5535 pte += l2pte_index(va); 5536 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5537 #endif 5538 *pte = fl; 5539 PTE_SYNC(pte); 5540 } 5541 5542 /* 5543 * pmap_link_l2pt: 5544 * 5545 * Link the L2 page table specified by "l2pv" into the L1 5546 * page table at the slot for "va". 5547 */ 5548 void 5549 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5550 { 5551 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5552 u_int slot = va >> L1_S_SHIFT; 5553 5554 #ifndef ARM32_NEW_VM_LAYOUT 5555 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5556 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5557 #endif 5558 5559 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5560 5561 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5562 #ifdef ARM32_NEW_VM_LAYOUT 5563 PTE_SYNC(&pde[slot]); 5564 #else 5565 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5566 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5567 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5568 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5569 #endif 5570 5571 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5572 } 5573 5574 /* 5575 * pmap_map_chunk: 5576 * 5577 * Map a chunk of memory using the most efficient mappings 5578 * possible (section, large page, small page) into the 5579 * provided L1 and L2 tables at the specified virtual address. 5580 */ 5581 vsize_t 5582 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5583 int prot, int cache) 5584 { 5585 pd_entry_t *pde = (pd_entry_t *) l1pt; 5586 pt_entry_t *pte, f1, f2s, f2l; 5587 vsize_t resid; 5588 int i; 5589 5590 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5591 5592 if (l1pt == 0) 5593 panic("pmap_map_chunk: no L1 table provided"); 5594 5595 #ifdef VERBOSE_INIT_ARM 5596 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5597 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5598 #endif 5599 5600 switch (cache) { 5601 case PTE_NOCACHE: 5602 default: 5603 f1 = 0; 5604 f2l = 0; 5605 f2s = 0; 5606 break; 5607 5608 case PTE_CACHE: 5609 f1 = pte_l1_s_cache_mode; 5610 f2l = pte_l2_l_cache_mode; 5611 f2s = pte_l2_s_cache_mode; 5612 break; 5613 5614 case PTE_PAGETABLE: 5615 f1 = pte_l1_s_cache_mode_pt; 5616 f2l = pte_l2_l_cache_mode_pt; 5617 f2s = pte_l2_s_cache_mode_pt; 5618 break; 5619 } 5620 5621 size = resid; 5622 5623 while (resid > 0) { 5624 /* See if we can use a section mapping. */ 5625 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5626 #ifdef VERBOSE_INIT_ARM 5627 printf("S"); 5628 #endif 5629 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5630 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5631 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5632 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5633 va += L1_S_SIZE; 5634 pa += L1_S_SIZE; 5635 resid -= L1_S_SIZE; 5636 continue; 5637 } 5638 5639 /* 5640 * Ok, we're going to use an L2 table. Make sure 5641 * one is actually in the corresponding L1 slot 5642 * for the current VA. 5643 */ 5644 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5645 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5646 5647 #ifndef ARM32_NEW_VM_LAYOUT 5648 pte = (pt_entry_t *) 5649 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5650 #else 5651 pte = (pt_entry_t *) kernel_pt_lookup( 5652 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5653 #endif 5654 if (pte == NULL) 5655 panic("pmap_map_chunk: can't find L2 table for VA" 5656 "0x%08lx", va); 5657 5658 /* See if we can use a L2 large page mapping. */ 5659 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5660 #ifdef VERBOSE_INIT_ARM 5661 printf("L"); 5662 #endif 5663 for (i = 0; i < 16; i++) { 5664 #ifndef ARM32_NEW_VM_LAYOUT 5665 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5666 L2_L_PROTO | pa | 5667 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5668 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5669 #else 5670 pte[l2pte_index(va) + i] = 5671 L2_L_PROTO | pa | 5672 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5673 PTE_SYNC(&pte[l2pte_index(va) + i]); 5674 #endif 5675 } 5676 va += L2_L_SIZE; 5677 pa += L2_L_SIZE; 5678 resid -= L2_L_SIZE; 5679 continue; 5680 } 5681 5682 /* Use a small page mapping. */ 5683 #ifdef VERBOSE_INIT_ARM 5684 printf("P"); 5685 #endif 5686 #ifndef ARM32_NEW_VM_LAYOUT 5687 pte[(va >> PGSHIFT) & 0x3ff] = 5688 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5689 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5690 #else 5691 pte[l2pte_index(va)] = 5692 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5693 PTE_SYNC(&pte[l2pte_index(va)]); 5694 #endif 5695 va += PAGE_SIZE; 5696 pa += PAGE_SIZE; 5697 resid -= PAGE_SIZE; 5698 } 5699 #ifdef VERBOSE_INIT_ARM 5700 printf("\n"); 5701 #endif 5702 return (size); 5703 } 5704 5705 /********************** Static device map routines ***************************/ 5706 5707 static const struct pmap_devmap *pmap_devmap_table; 5708 5709 /* 5710 * Register the devmap table. This is provided in case early console 5711 * initialization needs to register mappings created by bootstrap code 5712 * before pmap_devmap_bootstrap() is called. 5713 */ 5714 void 5715 pmap_devmap_register(const struct pmap_devmap *table) 5716 { 5717 5718 pmap_devmap_table = table; 5719 } 5720 5721 /* 5722 * Map all of the static regions in the devmap table, and remember 5723 * the devmap table so other parts of the kernel can look up entries 5724 * later. 5725 */ 5726 void 5727 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5728 { 5729 int i; 5730 5731 pmap_devmap_table = table; 5732 5733 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5734 #ifdef VERBOSE_INIT_ARM 5735 printf("devmap: %08lx -> %08lx @ %08lx\n", 5736 pmap_devmap_table[i].pd_pa, 5737 pmap_devmap_table[i].pd_pa + 5738 pmap_devmap_table[i].pd_size - 1, 5739 pmap_devmap_table[i].pd_va); 5740 #endif 5741 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5742 pmap_devmap_table[i].pd_pa, 5743 pmap_devmap_table[i].pd_size, 5744 pmap_devmap_table[i].pd_prot, 5745 pmap_devmap_table[i].pd_cache); 5746 } 5747 } 5748 5749 const struct pmap_devmap * 5750 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5751 { 5752 uint64_t endpa; 5753 int i; 5754 5755 if (pmap_devmap_table == NULL) 5756 return (NULL); 5757 5758 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5759 5760 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5761 if (pa >= pmap_devmap_table[i].pd_pa && 5762 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5763 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5764 return (&pmap_devmap_table[i]); 5765 } 5766 5767 return (NULL); 5768 } 5769 5770 const struct pmap_devmap * 5771 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5772 { 5773 int i; 5774 5775 if (pmap_devmap_table == NULL) 5776 return (NULL); 5777 5778 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5779 if (va >= pmap_devmap_table[i].pd_va && 5780 va + size - 1 <= pmap_devmap_table[i].pd_va + 5781 pmap_devmap_table[i].pd_size - 1) 5782 return (&pmap_devmap_table[i]); 5783 } 5784 5785 return (NULL); 5786 } 5787 5788 /********************** PTE initialization routines **************************/ 5789 5790 /* 5791 * These routines are called when the CPU type is identified to set up 5792 * the PTE prototypes, cache modes, etc. 5793 * 5794 * The variables are always here, just in case LKMs need to reference 5795 * them (though, they shouldn't). 5796 */ 5797 5798 pt_entry_t pte_l1_s_cache_mode; 5799 pt_entry_t pte_l1_s_cache_mode_pt; 5800 pt_entry_t pte_l1_s_cache_mask; 5801 5802 pt_entry_t pte_l2_l_cache_mode; 5803 pt_entry_t pte_l2_l_cache_mode_pt; 5804 pt_entry_t pte_l2_l_cache_mask; 5805 5806 pt_entry_t pte_l2_s_cache_mode; 5807 pt_entry_t pte_l2_s_cache_mode_pt; 5808 pt_entry_t pte_l2_s_cache_mask; 5809 5810 pt_entry_t pte_l2_s_prot_u; 5811 pt_entry_t pte_l2_s_prot_w; 5812 pt_entry_t pte_l2_s_prot_mask; 5813 5814 pt_entry_t pte_l1_s_proto; 5815 pt_entry_t pte_l1_c_proto; 5816 pt_entry_t pte_l2_s_proto; 5817 5818 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5819 void (*pmap_zero_page_func)(paddr_t); 5820 5821 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5822 void 5823 pmap_pte_init_generic(void) 5824 { 5825 5826 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5827 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5828 5829 pte_l2_l_cache_mode = L2_B|L2_C; 5830 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5831 5832 pte_l2_s_cache_mode = L2_B|L2_C; 5833 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5834 5835 /* 5836 * If we have a write-through cache, set B and C. If 5837 * we have a write-back cache, then we assume setting 5838 * only C will make those pages write-through. 5839 */ 5840 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5841 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5842 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5843 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5844 } else { 5845 #if ARM_MMU_V6 > 1 5846 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5847 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5848 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5849 #else 5850 pte_l1_s_cache_mode_pt = L1_S_C; 5851 pte_l2_l_cache_mode_pt = L2_C; 5852 pte_l2_s_cache_mode_pt = L2_C; 5853 #endif 5854 } 5855 5856 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5857 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5858 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5859 5860 pte_l1_s_proto = L1_S_PROTO_generic; 5861 pte_l1_c_proto = L1_C_PROTO_generic; 5862 pte_l2_s_proto = L2_S_PROTO_generic; 5863 5864 pmap_copy_page_func = pmap_copy_page_generic; 5865 pmap_zero_page_func = pmap_zero_page_generic; 5866 } 5867 5868 #if defined(CPU_ARM8) 5869 void 5870 pmap_pte_init_arm8(void) 5871 { 5872 5873 /* 5874 * ARM8 is compatible with generic, but we need to use 5875 * the page tables uncached. 5876 */ 5877 pmap_pte_init_generic(); 5878 5879 pte_l1_s_cache_mode_pt = 0; 5880 pte_l2_l_cache_mode_pt = 0; 5881 pte_l2_s_cache_mode_pt = 0; 5882 } 5883 #endif /* CPU_ARM8 */ 5884 5885 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5886 void 5887 pmap_pte_init_arm9(void) 5888 { 5889 5890 /* 5891 * ARM9 is compatible with generic, but we want to use 5892 * write-through caching for now. 5893 */ 5894 pmap_pte_init_generic(); 5895 5896 pte_l1_s_cache_mode = L1_S_C; 5897 pte_l2_l_cache_mode = L2_C; 5898 pte_l2_s_cache_mode = L2_C; 5899 5900 pte_l1_s_cache_mode_pt = L1_S_C; 5901 pte_l2_l_cache_mode_pt = L2_C; 5902 pte_l2_s_cache_mode_pt = L2_C; 5903 } 5904 #endif /* CPU_ARM9 */ 5905 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5906 5907 #if defined(CPU_ARM10) 5908 void 5909 pmap_pte_init_arm10(void) 5910 { 5911 5912 /* 5913 * ARM10 is compatible with generic, but we want to use 5914 * write-through caching for now. 5915 */ 5916 pmap_pte_init_generic(); 5917 5918 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 5919 pte_l2_l_cache_mode = L2_B | L2_C; 5920 pte_l2_s_cache_mode = L2_B | L2_C; 5921 5922 pte_l1_s_cache_mode_pt = L1_S_C; 5923 pte_l2_l_cache_mode_pt = L2_C; 5924 pte_l2_s_cache_mode_pt = L2_C; 5925 5926 } 5927 #endif /* CPU_ARM10 */ 5928 5929 #if ARM_MMU_SA1 == 1 5930 void 5931 pmap_pte_init_sa1(void) 5932 { 5933 5934 /* 5935 * The StrongARM SA-1 cache does not have a write-through 5936 * mode. So, do the generic initialization, then reset 5937 * the page table cache mode to B=1,C=1, and note that 5938 * the PTEs need to be sync'd. 5939 */ 5940 pmap_pte_init_generic(); 5941 5942 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5943 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5944 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5945 5946 pmap_needs_pte_sync = 1; 5947 } 5948 #endif /* ARM_MMU_SA1 == 1*/ 5949 5950 #if ARM_MMU_XSCALE == 1 5951 #if (ARM_NMMUS > 1) 5952 static u_int xscale_use_minidata; 5953 #endif 5954 5955 void 5956 pmap_pte_init_xscale(void) 5957 { 5958 uint32_t auxctl; 5959 int write_through = 0; 5960 5961 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5962 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 5963 5964 pte_l2_l_cache_mode = L2_B|L2_C; 5965 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 5966 5967 pte_l2_s_cache_mode = L2_B|L2_C; 5968 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 5969 5970 pte_l1_s_cache_mode_pt = L1_S_C; 5971 pte_l2_l_cache_mode_pt = L2_C; 5972 pte_l2_s_cache_mode_pt = L2_C; 5973 5974 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 5975 /* 5976 * The XScale core has an enhanced mode where writes that 5977 * miss the cache cause a cache line to be allocated. This 5978 * is significantly faster than the traditional, write-through 5979 * behavior of this case. 5980 */ 5981 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 5982 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 5983 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 5984 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 5985 5986 #ifdef XSCALE_CACHE_WRITE_THROUGH 5987 /* 5988 * Some versions of the XScale core have various bugs in 5989 * their cache units, the work-around for which is to run 5990 * the cache in write-through mode. Unfortunately, this 5991 * has a major (negative) impact on performance. So, we 5992 * go ahead and run fast-and-loose, in the hopes that we 5993 * don't line up the planets in a way that will trip the 5994 * bugs. 5995 * 5996 * However, we give you the option to be slow-but-correct. 5997 */ 5998 write_through = 1; 5999 #elif defined(XSCALE_CACHE_WRITE_BACK) 6000 /* force write back cache mode */ 6001 write_through = 0; 6002 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6003 /* 6004 * Intel PXA2[15]0 processors are known to have a bug in 6005 * write-back cache on revision 4 and earlier (stepping 6006 * A[01] and B[012]). Fixed for C0 and later. 6007 */ 6008 { 6009 uint32_t id, type; 6010 6011 id = cpufunc_id(); 6012 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6013 6014 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6015 if ((id & CPU_ID_REVISION_MASK) < 5) { 6016 /* write through for stepping A0-1 and B0-2 */ 6017 write_through = 1; 6018 } 6019 } 6020 } 6021 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6022 6023 if (write_through) { 6024 pte_l1_s_cache_mode = L1_S_C; 6025 pte_l2_l_cache_mode = L2_C; 6026 pte_l2_s_cache_mode = L2_C; 6027 } 6028 6029 #if (ARM_NMMUS > 1) 6030 xscale_use_minidata = 1; 6031 #endif 6032 6033 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6034 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6035 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6036 6037 pte_l1_s_proto = L1_S_PROTO_xscale; 6038 pte_l1_c_proto = L1_C_PROTO_xscale; 6039 pte_l2_s_proto = L2_S_PROTO_xscale; 6040 6041 pmap_copy_page_func = pmap_copy_page_xscale; 6042 pmap_zero_page_func = pmap_zero_page_xscale; 6043 6044 /* 6045 * Disable ECC protection of page table access, for now. 6046 */ 6047 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6048 auxctl &= ~XSCALE_AUXCTL_P; 6049 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6050 } 6051 6052 /* 6053 * xscale_setup_minidata: 6054 * 6055 * Set up the mini-data cache clean area. We require the 6056 * caller to allocate the right amount of physically and 6057 * virtually contiguous space. 6058 */ 6059 void 6060 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6061 { 6062 extern vaddr_t xscale_minidata_clean_addr; 6063 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6064 pd_entry_t *pde = (pd_entry_t *) l1pt; 6065 pt_entry_t *pte; 6066 vsize_t size; 6067 uint32_t auxctl; 6068 6069 xscale_minidata_clean_addr = va; 6070 6071 /* Round it to page size. */ 6072 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6073 6074 for (; size != 0; 6075 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6076 #ifndef ARM32_NEW_VM_LAYOUT 6077 pte = (pt_entry_t *) 6078 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6079 #else 6080 pte = (pt_entry_t *) kernel_pt_lookup( 6081 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6082 #endif 6083 if (pte == NULL) 6084 panic("xscale_setup_minidata: can't find L2 table for " 6085 "VA 0x%08lx", va); 6086 #ifndef ARM32_NEW_VM_LAYOUT 6087 pte[(va >> PGSHIFT) & 0x3ff] = 6088 #else 6089 pte[l2pte_index(va)] = 6090 #endif 6091 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6092 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6093 } 6094 6095 /* 6096 * Configure the mini-data cache for write-back with 6097 * read/write-allocate. 6098 * 6099 * NOTE: In order to reconfigure the mini-data cache, we must 6100 * make sure it contains no valid data! In order to do that, 6101 * we must issue a global data cache invalidate command! 6102 * 6103 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6104 * THIS IS VERY IMPORTANT! 6105 */ 6106 6107 /* Invalidate data and mini-data. */ 6108 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6109 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6110 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6111 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6112 } 6113 6114 /* 6115 * Change the PTEs for the specified kernel mappings such that they 6116 * will use the mini data cache instead of the main data cache. 6117 */ 6118 void 6119 pmap_uarea(vaddr_t va) 6120 { 6121 struct l2_bucket *l2b; 6122 pt_entry_t *ptep, *sptep, pte; 6123 vaddr_t next_bucket, eva; 6124 6125 #if (ARM_NMMUS > 1) 6126 if (xscale_use_minidata == 0) 6127 return; 6128 #endif 6129 6130 eva = va + USPACE; 6131 6132 while (va < eva) { 6133 next_bucket = L2_NEXT_BUCKET(va); 6134 if (next_bucket > eva) 6135 next_bucket = eva; 6136 6137 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6138 KDASSERT(l2b != NULL); 6139 6140 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6141 6142 while (va < next_bucket) { 6143 pte = *ptep; 6144 if (!l2pte_minidata(pte)) { 6145 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6146 cpu_tlb_flushD_SE(va); 6147 *ptep = pte & ~L2_B; 6148 } 6149 ptep++; 6150 va += PAGE_SIZE; 6151 } 6152 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6153 } 6154 cpu_cpwait(); 6155 } 6156 #endif /* ARM_MMU_XSCALE == 1 */ 6157 6158 /* 6159 * return the PA of the current L1 table, for use when handling a crash dump 6160 */ 6161 uint32_t pmap_kernel_L1_addr() 6162 { 6163 return pmap_kernel()->pm_l1->l1_physaddr; 6164 } 6165 6166 #if defined(DDB) 6167 /* 6168 * A couple of ddb-callable functions for dumping pmaps 6169 */ 6170 void pmap_dump_all(void); 6171 void pmap_dump(pmap_t); 6172 6173 void 6174 pmap_dump_all(void) 6175 { 6176 pmap_t pm; 6177 6178 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6179 if (pm == pmap_kernel()) 6180 continue; 6181 pmap_dump(pm); 6182 printf("\n"); 6183 } 6184 } 6185 6186 static pt_entry_t ncptes[64]; 6187 static void pmap_dump_ncpg(pmap_t); 6188 6189 void 6190 pmap_dump(pmap_t pm) 6191 { 6192 struct l2_dtable *l2; 6193 struct l2_bucket *l2b; 6194 pt_entry_t *ptep, pte; 6195 vaddr_t l2_va, l2b_va, va; 6196 int i, j, k, occ, rows = 0; 6197 6198 if (pm == pmap_kernel()) 6199 printf("pmap_kernel (%p): ", pm); 6200 else 6201 printf("user pmap (%p): ", pm); 6202 6203 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6204 6205 l2_va = 0; 6206 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6207 l2 = pm->pm_l2[i]; 6208 6209 if (l2 == NULL || l2->l2_occupancy == 0) 6210 continue; 6211 6212 l2b_va = l2_va; 6213 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6214 l2b = &l2->l2_bucket[j]; 6215 6216 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6217 continue; 6218 6219 ptep = l2b->l2b_kva; 6220 6221 for (k = 0; k < 256 && ptep[k] == 0; k++) 6222 ; 6223 6224 k &= ~63; 6225 occ = l2b->l2b_occupancy; 6226 va = l2b_va + (k * 4096); 6227 for (; k < 256; k++, va += 0x1000) { 6228 char ch = ' '; 6229 if ((k % 64) == 0) { 6230 if ((rows % 8) == 0) { 6231 printf( 6232 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6233 } 6234 printf("%08lx: ", va); 6235 } 6236 6237 ncptes[k & 63] = 0; 6238 pte = ptep[k]; 6239 if (pte == 0) { 6240 ch = '.'; 6241 } else { 6242 occ--; 6243 switch (pte & 0x0c) { 6244 case 0x00: 6245 ch = 'D'; /* No cache No buff */ 6246 break; 6247 case 0x04: 6248 ch = 'B'; /* No cache buff */ 6249 break; 6250 case 0x08: 6251 if (pte & 0x40) 6252 ch = 'm'; 6253 else 6254 ch = 'C'; /* Cache No buff */ 6255 break; 6256 case 0x0c: 6257 ch = 'F'; /* Cache Buff */ 6258 break; 6259 } 6260 6261 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6262 ch += 0x20; 6263 6264 if ((pte & 0xc) == 0) 6265 ncptes[k & 63] = pte; 6266 } 6267 6268 if ((k % 64) == 63) { 6269 rows++; 6270 printf("%c\n", ch); 6271 pmap_dump_ncpg(pm); 6272 if (occ == 0) 6273 break; 6274 } else 6275 printf("%c", ch); 6276 } 6277 } 6278 } 6279 } 6280 6281 static void 6282 pmap_dump_ncpg(pmap_t pm) 6283 { 6284 struct vm_page *pg; 6285 struct pv_entry *pv; 6286 int i; 6287 6288 for (i = 0; i < 63; i++) { 6289 if (ncptes[i] == 0) 6290 continue; 6291 6292 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6293 if (pg == NULL) 6294 continue; 6295 6296 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6297 VM_PAGE_TO_PHYS(pg), 6298 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 6299 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 6300 6301 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 6302 printf(" %c va 0x%08lx, flags 0x%x\n", 6303 (pm == pv->pv_pmap) ? '*' : ' ', 6304 pv->pv_va, pv->pv_flags); 6305 } 6306 } 6307 } 6308 #endif 6309 6310 #ifdef PMAP_STEAL_MEMORY 6311 void 6312 pmap_boot_pageadd(pv_addr_t *newpv) 6313 { 6314 pv_addr_t *pv, *npv; 6315 6316 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6317 if (newpv->pv_pa < pv->pv_va) { 6318 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6319 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6320 newpv->pv_size += pv->pv_size; 6321 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6322 } 6323 pv = NULL; 6324 } else { 6325 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6326 pv = npv) { 6327 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6328 KASSERT(pv->pv_pa < newpv->pv_pa); 6329 if (newpv->pv_pa > npv->pv_pa) 6330 continue; 6331 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6332 pv->pv_size += newpv->pv_size; 6333 return; 6334 } 6335 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6336 break; 6337 newpv->pv_size += npv->pv_size; 6338 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6339 SLIST_REMOVE_AFTER(newpv, pv_list); 6340 return; 6341 } 6342 } 6343 } 6344 6345 if (pv) { 6346 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6347 } else { 6348 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6349 } 6350 } 6351 6352 void 6353 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6354 pv_addr_t *rpv) 6355 { 6356 pv_addr_t *pv, **pvp; 6357 struct vm_physseg *ps; 6358 size_t i; 6359 6360 KASSERT(amount & PGOFSET); 6361 KASSERT((mask & PGOFSET) == 0); 6362 KASSERT((match & PGOFSET) == 0); 6363 KASSERT(amount != 0); 6364 6365 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6366 (pv = *pvp) != NULL; 6367 pvp = &SLIST_NEXT(pv, pv_list)) { 6368 pv_addr_t *newpv; 6369 psize_t off; 6370 /* 6371 * If this entry is too small to satify the request... 6372 */ 6373 KASSERT(pv->pv_size > 0); 6374 if (pv->pv_size < amount) 6375 continue; 6376 6377 for (off = 0; off <= mask; off += PAGE_SIZE) { 6378 if (((pv->pv_pa + off) & mask) == match 6379 && off + amount <= pv->pv_size) 6380 break; 6381 } 6382 if (off > mask) 6383 continue; 6384 6385 rpv->pv_va = pv->pv_va + off; 6386 rpv->pv_pa = pv->pv_pa + off; 6387 rpv->pv_size = amount; 6388 pv->pv_size -= amount; 6389 if (pv->pv_size == 0) { 6390 KASSERT(off == 0); 6391 KASSERT((vaddr_t) pv == rpv->pv_va); 6392 *pvp = SLIST_NEXT(pv, pv_list); 6393 } else if (off == 0) { 6394 KASSERT((vaddr_t) pv == rpv->pv_va); 6395 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6396 *newpv = *pv; 6397 newpv->pv_pa += amount; 6398 newpv->pv_va += amount; 6399 *pvp = newpv; 6400 } else if (off < pv->pv_size) { 6401 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6402 *newpv = *pv; 6403 newpv->pv_size -= off; 6404 newpv->pv_pa += off + amount; 6405 newpv->pv_va += off + amount; 6406 6407 SLIST_NEXT(pv, pv_list) = newpv; 6408 pv->pv_size = off; 6409 } else { 6410 KASSERT((vaddr_t) pv != rpv->pv_va); 6411 } 6412 memset((void *)rpv->pv_va, 0, amount); 6413 return; 6414 } 6415 6416 if (vm_nphysseg == 0) 6417 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6418 6419 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6420 (pv = *pvp) != NULL; 6421 pvp = &SLIST_NEXT(pv, pv_list)) { 6422 if (SLIST_NEXT(pv, pv_list) == NULL) 6423 break; 6424 } 6425 KASSERT(mask == 0); 6426 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6427 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6428 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6429 rpv->pv_va = pv->pv_va; 6430 rpv->pv_pa = pv->pv_pa; 6431 rpv->pv_size = amount; 6432 *pvp = NULL; 6433 pmap_map_chunk(kernel_l1pt.pv_va, 6434 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6435 ptoa(ps->avail_start), 6436 amount - pv->pv_size, 6437 VM_PROT_READ|VM_PROT_WRITE, 6438 PTE_CACHE); 6439 ps->avail_start += atop(amount - pv->pv_size); 6440 /* 6441 * If we consumed the entire physseg, remove it. 6442 */ 6443 if (ps->avail_start == ps->avail_end) { 6444 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6445 ps[0] = ps[1]; 6446 } 6447 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6448 return; 6449 } 6450 } 6451 6452 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6453 } 6454 6455 vaddr_t 6456 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6457 { 6458 pv_addr_t pv; 6459 6460 pmap_boot_pagealloc(size, 0, 0, &pv); 6461 6462 return pv.pv_va; 6463 } 6464 #endif /* PMAP_STEAL_MEMORY */ 6465 6466 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6467 { 6468 sysctl_createv(clog, 0, NULL, NULL, 6469 CTLFLAG_PERMANENT, 6470 CTLTYPE_NODE, "machdep", NULL, 6471 NULL, 0, NULL, 0, 6472 CTL_MACHDEP, CTL_EOL); 6473 6474 sysctl_createv(clog, 0, NULL, NULL, 6475 CTLFLAG_PERMANENT, 6476 CTLTYPE_INT, "kmpages", 6477 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6478 NULL, 0, &pmap_kmpages, 0, 6479 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6480 } 6481
Indexes created Mon Sep 29 15:09:53 GMT 2025