pmap.c revision 1.189
1 /* $NetBSD: pmap.c,v 1.189 2008/11/04 07:21:24 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/user.h> 202 #include <sys/pool.h> 203 #include <sys/cdefs.h> 204 #include <sys/cpu.h> 205 #include <sys/sysctl.h> 206 207 #include <uvm/uvm.h> 208 209 #include <machine/bus.h> 210 #include <machine/pmap.h> 211 #include <machine/pcb.h> 212 #include <machine/param.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.189 2008/11/04 07:21:24 matt Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 #define PDB_EXEC 0x80000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 struct pmap kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 #ifdef PMAPCOUNTERS 308 #define PMAP_EVCNT_INITIALIZER(name) \ 309 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 310 311 #ifdef PMAP_CACHE_VIPT 312 static struct evcnt pmap_ev_vac_color_new = 313 PMAP_EVCNT_INITIALIZER("new page color"); 314 static struct evcnt pmap_ev_vac_color_reuse = 315 PMAP_EVCNT_INITIALIZER("ok first page color"); 316 static struct evcnt pmap_ev_vac_color_ok = 317 PMAP_EVCNT_INITIALIZER("ok page color"); 318 static struct evcnt pmap_ev_vac_color_blind = 319 PMAP_EVCNT_INITIALIZER("blind page color"); 320 static struct evcnt pmap_ev_vac_color_change = 321 PMAP_EVCNT_INITIALIZER("change page color"); 322 static struct evcnt pmap_ev_vac_color_erase = 323 PMAP_EVCNT_INITIALIZER("erase page color"); 324 static struct evcnt pmap_ev_vac_color_none = 325 PMAP_EVCNT_INITIALIZER("no page color"); 326 static struct evcnt pmap_ev_vac_color_restore = 327 PMAP_EVCNT_INITIALIZER("restore page color"); 328 329 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 330 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 331 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 332 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 333 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 334 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 335 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 336 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 337 #endif 338 339 static struct evcnt pmap_ev_mappings = 340 PMAP_EVCNT_INITIALIZER("pages mapped"); 341 static struct evcnt pmap_ev_unmappings = 342 PMAP_EVCNT_INITIALIZER("pages unmapped"); 343 static struct evcnt pmap_ev_remappings = 344 PMAP_EVCNT_INITIALIZER("pages remapped"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 347 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 348 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 349 350 static struct evcnt pmap_ev_kernel_mappings = 351 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 352 static struct evcnt pmap_ev_kernel_unmappings = 353 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 354 static struct evcnt pmap_ev_kernel_remappings = 355 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 356 357 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 358 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 359 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 360 361 static struct evcnt pmap_ev_kenter_mappings = 362 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 363 static struct evcnt pmap_ev_kenter_unmappings = 364 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 365 static struct evcnt pmap_ev_kenter_remappings = 366 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 367 static struct evcnt pmap_ev_pt_mappings = 368 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 373 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 374 375 #ifdef PMAP_CACHE_VIPT 376 static struct evcnt pmap_ev_exec_mappings = 377 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 378 static struct evcnt pmap_ev_exec_cached = 379 PMAP_EVCNT_INITIALIZER("exec pages cached"); 380 381 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 382 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 383 384 static struct evcnt pmap_ev_exec_synced = 385 PMAP_EVCNT_INITIALIZER("exec pages synced"); 386 static struct evcnt pmap_ev_exec_synced_map = 387 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 388 static struct evcnt pmap_ev_exec_synced_unmap = 389 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 390 static struct evcnt pmap_ev_exec_synced_remap = 391 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 392 static struct evcnt pmap_ev_exec_synced_clearbit = 393 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 394 static struct evcnt pmap_ev_exec_synced_kremove = 395 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 396 397 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 399 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 400 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 401 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 402 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 403 404 static struct evcnt pmap_ev_exec_discarded_unmap = 405 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 406 static struct evcnt pmap_ev_exec_discarded_zero = 407 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 408 static struct evcnt pmap_ev_exec_discarded_copy = 409 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 410 static struct evcnt pmap_ev_exec_discarded_page_protect = 411 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 412 static struct evcnt pmap_ev_exec_discarded_clearbit = 413 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 414 static struct evcnt pmap_ev_exec_discarded_kremove = 415 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 416 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 422 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 423 #endif /* PMAP_CACHE_VIPT */ 424 425 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 426 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 427 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 428 429 EVCNT_ATTACH_STATIC(pmap_ev_updates); 430 EVCNT_ATTACH_STATIC(pmap_ev_collects); 431 EVCNT_ATTACH_STATIC(pmap_ev_activations); 432 433 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 434 #else 435 #define PMAPCOUNT(x) ((void)0) 436 #endif 437 438 /* 439 * pmap copy/zero page, and mem(5) hook point 440 */ 441 static pt_entry_t *csrc_pte, *cdst_pte; 442 static vaddr_t csrcp, cdstp; 443 vaddr_t memhook; /* used by mem.c */ 444 kmutex_t memlock; /* used by mem.c */ 445 extern void *msgbufaddr; 446 int pmap_kmpages; 447 /* 448 * Flag to indicate if pmap_init() has done its thing 449 */ 450 bool pmap_initialized; 451 452 /* 453 * Misc. locking data structures 454 */ 455 456 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 457 static struct lock pmap_main_lock; 458 459 #define PMAP_MAP_TO_HEAD_LOCK() \ 460 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 461 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 462 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 463 #define PMAP_HEAD_TO_MAP_LOCK() \ 464 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 465 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 466 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 467 #else 468 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 469 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 470 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 471 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 472 #endif 473 474 #define pmap_acquire_pmap_lock(pm) \ 475 do { \ 476 if ((pm) != pmap_kernel()) \ 477 mutex_enter(&(pm)->pm_lock); \ 478 } while (/*CONSTCOND*/0) 479 480 #define pmap_release_pmap_lock(pm) \ 481 do { \ 482 if ((pm) != pmap_kernel()) \ 483 mutex_exit(&(pm)->pm_lock); \ 484 } while (/*CONSTCOND*/0) 485 486 487 /* 488 * Metadata for L1 translation tables. 489 */ 490 struct l1_ttable { 491 /* Entry on the L1 Table list */ 492 SLIST_ENTRY(l1_ttable) l1_link; 493 494 /* Entry on the L1 Least Recently Used list */ 495 TAILQ_ENTRY(l1_ttable) l1_lru; 496 497 /* Track how many domains are allocated from this L1 */ 498 volatile u_int l1_domain_use_count; 499 500 /* 501 * A free-list of domain numbers for this L1. 502 * We avoid using ffs() and a bitmap to track domains since ffs() 503 * is slow on ARM. 504 */ 505 u_int8_t l1_domain_first; 506 u_int8_t l1_domain_free[PMAP_DOMAINS]; 507 508 /* Physical address of this L1 page table */ 509 paddr_t l1_physaddr; 510 511 /* KVA of this L1 page table */ 512 pd_entry_t *l1_kva; 513 }; 514 515 /* 516 * Convert a virtual address into its L1 table index. That is, the 517 * index used to locate the L2 descriptor table pointer in an L1 table. 518 * This is basically used to index l1->l1_kva[]. 519 * 520 * Each L2 descriptor table represents 1MB of VA space. 521 */ 522 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 523 524 /* 525 * L1 Page Tables are tracked using a Least Recently Used list. 526 * - New L1s are allocated from the HEAD. 527 * - Freed L1s are added to the TAIl. 528 * - Recently accessed L1s (where an 'access' is some change to one of 529 * the userland pmaps which owns this L1) are moved to the TAIL. 530 */ 531 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 532 static struct simplelock l1_lru_lock; 533 534 /* 535 * A list of all L1 tables 536 */ 537 static SLIST_HEAD(, l1_ttable) l1_list; 538 539 /* 540 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 541 * 542 * This is normally 16MB worth L2 page descriptors for any given pmap. 543 * Reference counts are maintained for L2 descriptors so they can be 544 * freed when empty. 545 */ 546 struct l2_dtable { 547 /* The number of L2 page descriptors allocated to this l2_dtable */ 548 u_int l2_occupancy; 549 550 /* List of L2 page descriptors */ 551 struct l2_bucket { 552 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 553 paddr_t l2b_phys; /* Physical address of same */ 554 u_short l2b_l1idx; /* This L2 table's L1 index */ 555 u_short l2b_occupancy; /* How many active descriptors */ 556 } l2_bucket[L2_BUCKET_SIZE]; 557 }; 558 559 /* 560 * Given an L1 table index, calculate the corresponding l2_dtable index 561 * and bucket index within the l2_dtable. 562 */ 563 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 564 (L2_SIZE - 1)) 565 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 566 567 /* 568 * Given a virtual address, this macro returns the 569 * virtual address required to drop into the next L2 bucket. 570 */ 571 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 572 573 /* 574 * L2 allocation. 575 */ 576 #define pmap_alloc_l2_dtable() \ 577 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 578 #define pmap_free_l2_dtable(l2) \ 579 pool_cache_put(&pmap_l2dtable_cache, (l2)) 580 #define pmap_alloc_l2_ptp(pap) \ 581 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 582 PR_NOWAIT, (pap))) 583 584 /* 585 * We try to map the page tables write-through, if possible. However, not 586 * all CPUs have a write-through cache mode, so on those we have to sync 587 * the cache when we frob page tables. 588 * 589 * We try to evaluate this at compile time, if possible. However, it's 590 * not always possible to do that, hence this run-time var. 591 */ 592 int pmap_needs_pte_sync; 593 594 /* 595 * Real definition of pv_entry. 596 */ 597 struct pv_entry { 598 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 599 pmap_t pv_pmap; /* pmap where mapping lies */ 600 vaddr_t pv_va; /* virtual address for mapping */ 601 u_int pv_flags; /* flags */ 602 }; 603 604 /* 605 * Macro to determine if a mapping might be resident in the 606 * instruction cache and/or TLB 607 */ 608 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 609 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 610 611 /* 612 * Macro to determine if a mapping might be resident in the 613 * data cache and/or TLB 614 */ 615 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 616 617 /* 618 * Local prototypes 619 */ 620 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 621 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 622 pt_entry_t **); 623 static bool pmap_is_current(pmap_t); 624 static bool pmap_is_cached(pmap_t); 625 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 626 pmap_t, vaddr_t, u_int); 627 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 628 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 629 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 630 u_int, u_int); 631 632 static void pmap_pinit(pmap_t); 633 static int pmap_pmap_ctor(void *, void *, int); 634 635 static void pmap_alloc_l1(pmap_t); 636 static void pmap_free_l1(pmap_t); 637 static void pmap_use_l1(pmap_t); 638 639 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 640 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 641 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 642 static int pmap_l2ptp_ctor(void *, void *, int); 643 static int pmap_l2dtable_ctor(void *, void *, int); 644 645 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 646 #ifdef PMAP_CACHE_VIVT 647 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 648 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 649 #endif 650 651 static void pmap_clearbit(struct vm_page *, u_int); 652 #ifdef PMAP_CACHE_VIVT 653 static int pmap_clean_page(struct pv_entry *, bool); 654 #endif 655 #ifdef PMAP_CACHE_VIPT 656 static void pmap_syncicache_page(struct vm_page *); 657 static void pmap_flush_page(struct vm_page *, bool); 658 #endif 659 static void pmap_page_remove(struct vm_page *); 660 661 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 662 static vaddr_t kernel_pt_lookup(paddr_t); 663 664 665 /* 666 * External function prototypes 667 */ 668 extern void bzero_page(vaddr_t); 669 extern void bcopy_page(vaddr_t, vaddr_t); 670 671 /* 672 * Misc variables 673 */ 674 vaddr_t virtual_avail; 675 vaddr_t virtual_end; 676 vaddr_t pmap_curmaxkvaddr; 677 678 vaddr_t avail_start; 679 vaddr_t avail_end; 680 681 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 682 pv_addr_t kernelpages; 683 pv_addr_t kernel_l1pt; 684 pv_addr_t systempage; 685 686 /* Function to set the debug level of the pmap code */ 687 688 #ifdef PMAP_DEBUG 689 void 690 pmap_debug(int level) 691 { 692 pmap_debug_level = level; 693 printf("pmap_debug: level=%d\n", pmap_debug_level); 694 } 695 #endif /* PMAP_DEBUG */ 696 697 /* 698 * A bunch of routines to conditionally flush the caches/TLB depending 699 * on whether the specified pmap actually needs to be flushed at any 700 * given time. 701 */ 702 static inline void 703 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 704 { 705 706 if (pm->pm_cstate.cs_tlb_id) 707 cpu_tlb_flushID_SE(va); 708 } 709 710 static inline void 711 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 712 { 713 714 if (pm->pm_cstate.cs_tlb_d) 715 cpu_tlb_flushD_SE(va); 716 } 717 718 static inline void 719 pmap_tlb_flushID(pmap_t pm) 720 { 721 722 if (pm->pm_cstate.cs_tlb_id) { 723 cpu_tlb_flushID(); 724 pm->pm_cstate.cs_tlb = 0; 725 } 726 } 727 728 static inline void 729 pmap_tlb_flushD(pmap_t pm) 730 { 731 732 if (pm->pm_cstate.cs_tlb_d) { 733 cpu_tlb_flushD(); 734 pm->pm_cstate.cs_tlb_d = 0; 735 } 736 } 737 738 #ifdef PMAP_CACHE_VIVT 739 static inline void 740 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 741 { 742 if (pm->pm_cstate.cs_cache_id) { 743 cpu_idcache_wbinv_range(va, len); 744 } 745 } 746 747 static inline void 748 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 749 bool do_inv, bool rd_only) 750 { 751 752 if (pm->pm_cstate.cs_cache_d) { 753 if (do_inv) { 754 if (rd_only) 755 cpu_dcache_inv_range(va, len); 756 else 757 cpu_dcache_wbinv_range(va, len); 758 } else 759 if (!rd_only) 760 cpu_dcache_wb_range(va, len); 761 } 762 } 763 764 static inline void 765 pmap_idcache_wbinv_all(pmap_t pm) 766 { 767 if (pm->pm_cstate.cs_cache_id) { 768 cpu_idcache_wbinv_all(); 769 pm->pm_cstate.cs_cache = 0; 770 } 771 } 772 773 static inline void 774 pmap_dcache_wbinv_all(pmap_t pm) 775 { 776 if (pm->pm_cstate.cs_cache_d) { 777 cpu_dcache_wbinv_all(); 778 pm->pm_cstate.cs_cache_d = 0; 779 } 780 } 781 #endif /* PMAP_CACHE_VIVT */ 782 783 static inline bool 784 pmap_is_current(pmap_t pm) 785 { 786 787 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 788 return true; 789 790 return false; 791 } 792 793 static inline bool 794 pmap_is_cached(pmap_t pm) 795 { 796 797 if (pm == pmap_kernel() || pmap_recent_user == NULL || 798 pmap_recent_user == pm) 799 return (true); 800 801 return false; 802 } 803 804 /* 805 * PTE_SYNC_CURRENT: 806 * 807 * Make sure the pte is written out to RAM. 808 * We need to do this for one of two cases: 809 * - We're dealing with the kernel pmap 810 * - There is no pmap active in the cache/tlb. 811 * - The specified pmap is 'active' in the cache/tlb. 812 */ 813 #ifdef PMAP_INCLUDE_PTE_SYNC 814 #define PTE_SYNC_CURRENT(pm, ptep) \ 815 do { \ 816 if (PMAP_NEEDS_PTE_SYNC && \ 817 pmap_is_cached(pm)) \ 818 PTE_SYNC(ptep); \ 819 } while (/*CONSTCOND*/0) 820 #else 821 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 822 #endif 823 824 /* 825 * main pv_entry manipulation functions: 826 * pmap_enter_pv: enter a mapping onto a vm_page list 827 * pmap_remove_pv: remove a mappiing from a vm_page list 828 * 829 * NOTE: pmap_enter_pv expects to lock the pvh itself 830 * pmap_remove_pv expects te caller to lock the pvh before calling 831 */ 832 833 /* 834 * pmap_enter_pv: enter a mapping onto a vm_page lst 835 * 836 * => caller should hold the proper lock on pmap_main_lock 837 * => caller should have pmap locked 838 * => we will gain the lock on the vm_page and allocate the new pv_entry 839 * => caller should adjust ptp's wire_count before calling 840 * => caller should not adjust pmap's wire_count 841 */ 842 static void 843 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 844 vaddr_t va, u_int flags) 845 { 846 struct pv_entry **pvp; 847 848 NPDEBUG(PDB_PVDUMP, 849 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 850 851 pve->pv_pmap = pm; 852 pve->pv_va = va; 853 pve->pv_flags = flags; 854 855 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 856 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 857 #ifdef PMAP_CACHE_VIPT 858 /* 859 * Insert unmanaged entries, writeable first, at the head of 860 * the pv list. 861 */ 862 if (__predict_true((flags & PVF_KENTRY) == 0)) { 863 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 864 pvp = &SLIST_NEXT(*pvp, pv_link); 865 } else if ((flags & PVF_WRITE) == 0) { 866 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 867 pvp = &SLIST_NEXT(*pvp, pv_link); 868 } 869 #endif 870 SLIST_NEXT(pve, pv_link) = *pvp; /* add to ... */ 871 *pvp = pve; /* ... locked list */ 872 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 873 #ifdef PMAP_CACHE_VIPT 874 if ((pve->pv_flags & PVF_KWRITE) == PVF_KWRITE) 875 pg->mdpage.pvh_attrs |= PVF_KMOD; 876 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 877 pg->mdpage.pvh_attrs |= PVF_DIRTY; 878 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 879 #endif 880 if (pm == pmap_kernel()) { 881 PMAPCOUNT(kernel_mappings); 882 if (flags & PVF_WRITE) 883 pg->mdpage.krw_mappings++; 884 else 885 pg->mdpage.kro_mappings++; 886 } else 887 if (flags & PVF_WRITE) 888 pg->mdpage.urw_mappings++; 889 else 890 pg->mdpage.uro_mappings++; 891 892 #ifdef PMAP_CACHE_VIPT 893 /* 894 * If this is an exec mapping and its the first exec mapping 895 * for this page, make sure to sync the I-cache. 896 */ 897 if (PV_IS_EXEC_P(flags)) { 898 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 899 pmap_syncicache_page(pg); 900 PMAPCOUNT(exec_synced_map); 901 } 902 PMAPCOUNT(exec_mappings); 903 } 904 #endif 905 906 PMAPCOUNT(mappings); 907 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 908 909 if (pve->pv_flags & PVF_WIRED) 910 ++pm->pm_stats.wired_count; 911 } 912 913 /* 914 * 915 * pmap_find_pv: Find a pv entry 916 * 917 * => caller should hold lock on vm_page 918 */ 919 static inline struct pv_entry * 920 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 921 { 922 struct pv_entry *pv; 923 924 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 925 if (pm == pv->pv_pmap && va == pv->pv_va) 926 break; 927 } 928 929 return (pv); 930 } 931 932 /* 933 * pmap_remove_pv: try to remove a mapping from a pv_list 934 * 935 * => caller should hold proper lock on pmap_main_lock 936 * => pmap should be locked 937 * => caller should hold lock on vm_page [so that attrs can be adjusted] 938 * => caller should adjust ptp's wire_count and free PTP if needed 939 * => caller should NOT adjust pmap's wire_count 940 * => we return the removed pve 941 */ 942 static struct pv_entry * 943 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 944 { 945 struct pv_entry *pve, **prevptr; 946 947 NPDEBUG(PDB_PVDUMP, 948 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 949 950 prevptr = &SLIST_FIRST(&pg->mdpage.pvh_list); /* prev pv_entry ptr */ 951 pve = *prevptr; 952 953 while (pve) { 954 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 955 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 956 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 957 if (pve->pv_flags & PVF_WIRED) { 958 if (skip_wired) 959 return (NULL); 960 --pm->pm_stats.wired_count; 961 } 962 *prevptr = SLIST_NEXT(pve, pv_link); /* remove it! */ 963 if (pm == pmap_kernel()) { 964 PMAPCOUNT(kernel_unmappings); 965 if (pve->pv_flags & PVF_WRITE) 966 pg->mdpage.krw_mappings--; 967 else 968 pg->mdpage.kro_mappings--; 969 } else 970 if (pve->pv_flags & PVF_WRITE) 971 pg->mdpage.urw_mappings--; 972 else 973 pg->mdpage.uro_mappings--; 974 975 PMAPCOUNT(unmappings); 976 #ifdef PMAP_CACHE_VIPT 977 if (!(pve->pv_flags & PVF_WRITE)) 978 break; 979 /* 980 * If this page has had an exec mapping, then if 981 * this was the last mapping, discard the contents, 982 * otherwise sync the i-cache for this page. 983 */ 984 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 985 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 986 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 987 PMAPCOUNT(exec_discarded_unmap); 988 } else { 989 pmap_syncicache_page(pg); 990 PMAPCOUNT(exec_synced_unmap); 991 } 992 } 993 #endif /* PMAP_CACHE_VIPT */ 994 break; 995 } 996 prevptr = &SLIST_NEXT(pve, pv_link); /* previous pointer */ 997 pve = *prevptr; /* advance */ 998 } 999 1000 #ifdef PMAP_CACHE_VIPT 1001 /* 1002 * If we no longer have a WRITEABLE KENTRY at the head of list, 1003 * clear the KMOD attribute from the page. 1004 */ 1005 if (SLIST_FIRST(&pg->mdpage.pvh_list) == NULL 1006 || (SLIST_FIRST(&pg->mdpage.pvh_list)->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1007 pg->mdpage.pvh_attrs &= ~PVF_KMOD; 1008 1009 /* 1010 * If this was a writeable page and there are no more writeable 1011 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1012 * the contents to memory. 1013 */ 1014 if (pg->mdpage.krw_mappings + pg->mdpage.urw_mappings == 0) 1015 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1016 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1017 #endif /* PMAP_CACHE_VIPT */ 1018 1019 return(pve); /* return removed pve */ 1020 } 1021 1022 /* 1023 * 1024 * pmap_modify_pv: Update pv flags 1025 * 1026 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1027 * => caller should NOT adjust pmap's wire_count 1028 * => caller must call pmap_vac_me_harder() if writable status of a page 1029 * may have changed. 1030 * => we return the old flags 1031 * 1032 * Modify a physical-virtual mapping in the pv table 1033 */ 1034 static u_int 1035 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 1036 u_int clr_mask, u_int set_mask) 1037 { 1038 struct pv_entry *npv; 1039 u_int flags, oflags; 1040 1041 KASSERT((clr_mask & PVF_KENTRY) == 0); 1042 KASSERT((set_mask & PVF_KENTRY) == 0); 1043 1044 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1045 return (0); 1046 1047 NPDEBUG(PDB_PVDUMP, 1048 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 1049 1050 /* 1051 * There is at least one VA mapping this page. 1052 */ 1053 1054 if (clr_mask & (PVF_REF | PVF_MOD)) { 1055 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1056 #ifdef PMAP_CACHE_VIPT 1057 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1058 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1059 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1060 #endif 1061 } 1062 1063 oflags = npv->pv_flags; 1064 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1065 1066 if ((flags ^ oflags) & PVF_WIRED) { 1067 if (flags & PVF_WIRED) 1068 ++pm->pm_stats.wired_count; 1069 else 1070 --pm->pm_stats.wired_count; 1071 } 1072 1073 if ((flags ^ oflags) & PVF_WRITE) { 1074 if (pm == pmap_kernel()) { 1075 if (flags & PVF_WRITE) { 1076 pg->mdpage.krw_mappings++; 1077 pg->mdpage.kro_mappings--; 1078 } else { 1079 pg->mdpage.kro_mappings++; 1080 pg->mdpage.krw_mappings--; 1081 } 1082 } else 1083 if (flags & PVF_WRITE) { 1084 pg->mdpage.urw_mappings++; 1085 pg->mdpage.uro_mappings--; 1086 } else { 1087 pg->mdpage.uro_mappings++; 1088 pg->mdpage.urw_mappings--; 1089 } 1090 } 1091 #ifdef PMAP_CACHE_VIPT 1092 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 1093 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1094 /* 1095 * We have two cases here: the first is from enter_pv (new exec 1096 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1097 * Since in latter, pmap_enter_pv won't do anything, we just have 1098 * to do what pmap_remove_pv would do. 1099 */ 1100 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1101 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1102 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1103 pmap_syncicache_page(pg); 1104 PMAPCOUNT(exec_synced_remap); 1105 } 1106 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1107 #endif 1108 1109 PMAPCOUNT(remappings); 1110 1111 return (oflags); 1112 } 1113 1114 /* 1115 * Allocate an L1 translation table for the specified pmap. 1116 * This is called at pmap creation time. 1117 */ 1118 static void 1119 pmap_alloc_l1(pmap_t pm) 1120 { 1121 struct l1_ttable *l1; 1122 u_int8_t domain; 1123 1124 /* 1125 * Remove the L1 at the head of the LRU list 1126 */ 1127 simple_lock(&l1_lru_lock); 1128 l1 = TAILQ_FIRST(&l1_lru_list); 1129 KDASSERT(l1 != NULL); 1130 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1131 1132 /* 1133 * Pick the first available domain number, and update 1134 * the link to the next number. 1135 */ 1136 domain = l1->l1_domain_first; 1137 l1->l1_domain_first = l1->l1_domain_free[domain]; 1138 1139 /* 1140 * If there are still free domain numbers in this L1, 1141 * put it back on the TAIL of the LRU list. 1142 */ 1143 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1144 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1145 1146 simple_unlock(&l1_lru_lock); 1147 1148 /* 1149 * Fix up the relevant bits in the pmap structure 1150 */ 1151 pm->pm_l1 = l1; 1152 pm->pm_domain = domain; 1153 } 1154 1155 /* 1156 * Free an L1 translation table. 1157 * This is called at pmap destruction time. 1158 */ 1159 static void 1160 pmap_free_l1(pmap_t pm) 1161 { 1162 struct l1_ttable *l1 = pm->pm_l1; 1163 1164 simple_lock(&l1_lru_lock); 1165 1166 /* 1167 * If this L1 is currently on the LRU list, remove it. 1168 */ 1169 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1170 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1171 1172 /* 1173 * Free up the domain number which was allocated to the pmap 1174 */ 1175 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1176 l1->l1_domain_first = pm->pm_domain; 1177 l1->l1_domain_use_count--; 1178 1179 /* 1180 * The L1 now must have at least 1 free domain, so add 1181 * it back to the LRU list. If the use count is zero, 1182 * put it at the head of the list, otherwise it goes 1183 * to the tail. 1184 */ 1185 if (l1->l1_domain_use_count == 0) 1186 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1187 else 1188 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1189 1190 simple_unlock(&l1_lru_lock); 1191 } 1192 1193 static inline void 1194 pmap_use_l1(pmap_t pm) 1195 { 1196 struct l1_ttable *l1; 1197 1198 /* 1199 * Do nothing if we're in interrupt context. 1200 * Access to an L1 by the kernel pmap must not affect 1201 * the LRU list. 1202 */ 1203 if (cpu_intr_p() || pm == pmap_kernel()) 1204 return; 1205 1206 l1 = pm->pm_l1; 1207 1208 /* 1209 * If the L1 is not currently on the LRU list, just return 1210 */ 1211 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1212 return; 1213 1214 simple_lock(&l1_lru_lock); 1215 1216 /* 1217 * Check the use count again, now that we've acquired the lock 1218 */ 1219 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1220 simple_unlock(&l1_lru_lock); 1221 return; 1222 } 1223 1224 /* 1225 * Move the L1 to the back of the LRU list 1226 */ 1227 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1228 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1229 1230 simple_unlock(&l1_lru_lock); 1231 } 1232 1233 /* 1234 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1235 * 1236 * Free an L2 descriptor table. 1237 */ 1238 static inline void 1239 #ifndef PMAP_INCLUDE_PTE_SYNC 1240 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1241 #else 1242 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1243 #endif 1244 { 1245 #ifdef PMAP_INCLUDE_PTE_SYNC 1246 #ifdef PMAP_CACHE_VIVT 1247 /* 1248 * Note: With a write-back cache, we may need to sync this 1249 * L2 table before re-using it. 1250 * This is because it may have belonged to a non-current 1251 * pmap, in which case the cache syncs would have been 1252 * skipped for the pages that were being unmapped. If the 1253 * L2 table were then to be immediately re-allocated to 1254 * the *current* pmap, it may well contain stale mappings 1255 * which have not yet been cleared by a cache write-back 1256 * and so would still be visible to the mmu. 1257 */ 1258 if (need_sync) 1259 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1260 #endif /* PMAP_CACHE_VIVT */ 1261 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1262 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1263 } 1264 1265 /* 1266 * Returns a pointer to the L2 bucket associated with the specified pmap 1267 * and VA, or NULL if no L2 bucket exists for the address. 1268 */ 1269 static inline struct l2_bucket * 1270 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1271 { 1272 struct l2_dtable *l2; 1273 struct l2_bucket *l2b; 1274 u_short l1idx; 1275 1276 l1idx = L1_IDX(va); 1277 1278 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1279 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1280 return (NULL); 1281 1282 return (l2b); 1283 } 1284 1285 /* 1286 * Returns a pointer to the L2 bucket associated with the specified pmap 1287 * and VA. 1288 * 1289 * If no L2 bucket exists, perform the necessary allocations to put an L2 1290 * bucket/page table in place. 1291 * 1292 * Note that if a new L2 bucket/page was allocated, the caller *must* 1293 * increment the bucket occupancy counter appropriately *before* 1294 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1295 * the bucket/page in the meantime. 1296 */ 1297 static struct l2_bucket * 1298 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1299 { 1300 struct l2_dtable *l2; 1301 struct l2_bucket *l2b; 1302 u_short l1idx; 1303 1304 l1idx = L1_IDX(va); 1305 1306 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1307 /* 1308 * No mapping at this address, as there is 1309 * no entry in the L1 table. 1310 * Need to allocate a new l2_dtable. 1311 */ 1312 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1313 return (NULL); 1314 1315 /* 1316 * Link it into the parent pmap 1317 */ 1318 pm->pm_l2[L2_IDX(l1idx)] = l2; 1319 } 1320 1321 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1322 1323 /* 1324 * Fetch pointer to the L2 page table associated with the address. 1325 */ 1326 if (l2b->l2b_kva == NULL) { 1327 pt_entry_t *ptep; 1328 1329 /* 1330 * No L2 page table has been allocated. Chances are, this 1331 * is because we just allocated the l2_dtable, above. 1332 */ 1333 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1334 /* 1335 * Oops, no more L2 page tables available at this 1336 * time. We may need to deallocate the l2_dtable 1337 * if we allocated a new one above. 1338 */ 1339 if (l2->l2_occupancy == 0) { 1340 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1341 pmap_free_l2_dtable(l2); 1342 } 1343 return (NULL); 1344 } 1345 1346 l2->l2_occupancy++; 1347 l2b->l2b_kva = ptep; 1348 l2b->l2b_l1idx = l1idx; 1349 } 1350 1351 return (l2b); 1352 } 1353 1354 /* 1355 * One or more mappings in the specified L2 descriptor table have just been 1356 * invalidated. 1357 * 1358 * Garbage collect the metadata and descriptor table itself if necessary. 1359 * 1360 * The pmap lock must be acquired when this is called (not necessary 1361 * for the kernel pmap). 1362 */ 1363 static void 1364 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1365 { 1366 struct l2_dtable *l2; 1367 pd_entry_t *pl1pd, l1pd; 1368 pt_entry_t *ptep; 1369 u_short l1idx; 1370 1371 KDASSERT(count <= l2b->l2b_occupancy); 1372 1373 /* 1374 * Update the bucket's reference count according to how many 1375 * PTEs the caller has just invalidated. 1376 */ 1377 l2b->l2b_occupancy -= count; 1378 1379 /* 1380 * Note: 1381 * 1382 * Level 2 page tables allocated to the kernel pmap are never freed 1383 * as that would require checking all Level 1 page tables and 1384 * removing any references to the Level 2 page table. See also the 1385 * comment elsewhere about never freeing bootstrap L2 descriptors. 1386 * 1387 * We make do with just invalidating the mapping in the L2 table. 1388 * 1389 * This isn't really a big deal in practice and, in fact, leads 1390 * to a performance win over time as we don't need to continually 1391 * alloc/free. 1392 */ 1393 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1394 return; 1395 1396 /* 1397 * There are no more valid mappings in this level 2 page table. 1398 * Go ahead and NULL-out the pointer in the bucket, then 1399 * free the page table. 1400 */ 1401 l1idx = l2b->l2b_l1idx; 1402 ptep = l2b->l2b_kva; 1403 l2b->l2b_kva = NULL; 1404 1405 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1406 1407 /* 1408 * If the L1 slot matches the pmap's domain 1409 * number, then invalidate it. 1410 */ 1411 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1412 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1413 *pl1pd = 0; 1414 PTE_SYNC(pl1pd); 1415 } 1416 1417 /* 1418 * Release the L2 descriptor table back to the pool cache. 1419 */ 1420 #ifndef PMAP_INCLUDE_PTE_SYNC 1421 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1422 #else 1423 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1424 #endif 1425 1426 /* 1427 * Update the reference count in the associated l2_dtable 1428 */ 1429 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1430 if (--l2->l2_occupancy > 0) 1431 return; 1432 1433 /* 1434 * There are no more valid mappings in any of the Level 1 1435 * slots managed by this l2_dtable. Go ahead and NULL-out 1436 * the pointer in the parent pmap and free the l2_dtable. 1437 */ 1438 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1439 pmap_free_l2_dtable(l2); 1440 } 1441 1442 /* 1443 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1444 * structures. 1445 */ 1446 static int 1447 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1448 { 1449 #ifndef PMAP_INCLUDE_PTE_SYNC 1450 struct l2_bucket *l2b; 1451 pt_entry_t *ptep, pte; 1452 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1453 1454 /* 1455 * The mappings for these page tables were initially made using 1456 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1457 * mode will not be right for page table mappings. To avoid 1458 * polluting the pmap_kenter_pa() code with a special case for 1459 * page tables, we simply fix up the cache-mode here if it's not 1460 * correct. 1461 */ 1462 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1463 KDASSERT(l2b != NULL); 1464 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1465 pte = *ptep; 1466 1467 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1468 /* 1469 * Page tables must have the cache-mode set to Write-Thru. 1470 */ 1471 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1472 PTE_SYNC(ptep); 1473 cpu_tlb_flushD_SE(va); 1474 cpu_cpwait(); 1475 } 1476 #endif 1477 1478 memset(v, 0, L2_TABLE_SIZE_REAL); 1479 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1480 return (0); 1481 } 1482 1483 static int 1484 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1485 { 1486 1487 memset(v, 0, sizeof(struct l2_dtable)); 1488 return (0); 1489 } 1490 1491 static int 1492 pmap_pmap_ctor(void *arg, void *v, int flags) 1493 { 1494 1495 memset(v, 0, sizeof(struct pmap)); 1496 return (0); 1497 } 1498 1499 static void 1500 pmap_pinit(pmap_t pm) 1501 { 1502 struct l2_bucket *l2b; 1503 1504 if (vector_page < KERNEL_BASE) { 1505 /* 1506 * Map the vector page. 1507 */ 1508 pmap_enter(pm, vector_page, systempage.pv_pa, 1509 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1510 pmap_update(pm); 1511 1512 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1513 l2b = pmap_get_l2_bucket(pm, vector_page); 1514 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1515 L1_C_DOM(pm->pm_domain); 1516 } else 1517 pm->pm_pl1vec = NULL; 1518 } 1519 1520 #ifdef PMAP_CACHE_VIVT 1521 /* 1522 * Since we have a virtually indexed cache, we may need to inhibit caching if 1523 * there is more than one mapping and at least one of them is writable. 1524 * Since we purge the cache on every context switch, we only need to check for 1525 * other mappings within the same pmap, or kernel_pmap. 1526 * This function is also called when a page is unmapped, to possibly reenable 1527 * caching on any remaining mappings. 1528 * 1529 * The code implements the following logic, where: 1530 * 1531 * KW = # of kernel read/write pages 1532 * KR = # of kernel read only pages 1533 * UW = # of user read/write pages 1534 * UR = # of user read only pages 1535 * 1536 * KC = kernel mapping is cacheable 1537 * UC = user mapping is cacheable 1538 * 1539 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1540 * +--------------------------------------------- 1541 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1542 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1543 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1544 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1545 */ 1546 1547 static const int pmap_vac_flags[4][4] = { 1548 {-1, 0, 0, PVF_KNC}, 1549 {0, 0, PVF_NC, PVF_NC}, 1550 {0, PVF_NC, PVF_NC, PVF_NC}, 1551 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1552 }; 1553 1554 static inline int 1555 pmap_get_vac_flags(const struct vm_page *pg) 1556 { 1557 int kidx, uidx; 1558 1559 kidx = 0; 1560 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1561 kidx |= 1; 1562 if (pg->mdpage.krw_mappings) 1563 kidx |= 2; 1564 1565 uidx = 0; 1566 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1567 uidx |= 1; 1568 if (pg->mdpage.urw_mappings) 1569 uidx |= 2; 1570 1571 return (pmap_vac_flags[uidx][kidx]); 1572 } 1573 1574 static inline void 1575 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1576 { 1577 int nattr; 1578 1579 nattr = pmap_get_vac_flags(pg); 1580 1581 if (nattr < 0) { 1582 pg->mdpage.pvh_attrs &= ~PVF_NC; 1583 return; 1584 } 1585 1586 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1587 return; 1588 1589 if (pm == pmap_kernel()) 1590 pmap_vac_me_kpmap(pg, pm, va); 1591 else 1592 pmap_vac_me_user(pg, pm, va); 1593 1594 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1595 } 1596 1597 static void 1598 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1599 { 1600 u_int u_cacheable, u_entries; 1601 struct pv_entry *pv; 1602 pmap_t last_pmap = pm; 1603 1604 /* 1605 * Pass one, see if there are both kernel and user pmaps for 1606 * this page. Calculate whether there are user-writable or 1607 * kernel-writable pages. 1608 */ 1609 u_cacheable = 0; 1610 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1611 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1612 u_cacheable++; 1613 } 1614 1615 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1616 1617 /* 1618 * We know we have just been updating a kernel entry, so if 1619 * all user pages are already cacheable, then there is nothing 1620 * further to do. 1621 */ 1622 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1623 return; 1624 1625 if (u_entries) { 1626 /* 1627 * Scan over the list again, for each entry, if it 1628 * might not be set correctly, call pmap_vac_me_user 1629 * to recalculate the settings. 1630 */ 1631 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1632 /* 1633 * We know kernel mappings will get set 1634 * correctly in other calls. We also know 1635 * that if the pmap is the same as last_pmap 1636 * then we've just handled this entry. 1637 */ 1638 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1639 continue; 1640 1641 /* 1642 * If there are kernel entries and this page 1643 * is writable but non-cacheable, then we can 1644 * skip this entry also. 1645 */ 1646 if (pg->mdpage.k_mappings && 1647 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1648 (PVF_NC | PVF_WRITE)) 1649 continue; 1650 1651 /* 1652 * Similarly if there are no kernel-writable 1653 * entries and the page is already 1654 * read-only/cacheable. 1655 */ 1656 if (pg->mdpage.krw_mappings == 0 && 1657 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1658 continue; 1659 1660 /* 1661 * For some of the remaining cases, we know 1662 * that we must recalculate, but for others we 1663 * can't tell if they are correct or not, so 1664 * we recalculate anyway. 1665 */ 1666 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1667 } 1668 1669 if (pg->mdpage.k_mappings == 0) 1670 return; 1671 } 1672 1673 pmap_vac_me_user(pg, pm, va); 1674 } 1675 1676 static void 1677 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1678 { 1679 pmap_t kpmap = pmap_kernel(); 1680 struct pv_entry *pv, *npv = NULL; 1681 struct l2_bucket *l2b; 1682 pt_entry_t *ptep, pte; 1683 u_int entries = 0; 1684 u_int writable = 0; 1685 u_int cacheable_entries = 0; 1686 u_int kern_cacheable = 0; 1687 u_int other_writable = 0; 1688 1689 /* 1690 * Count mappings and writable mappings in this pmap. 1691 * Include kernel mappings as part of our own. 1692 * Keep a pointer to the first one. 1693 */ 1694 npv = NULL; 1695 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1696 /* Count mappings in the same pmap */ 1697 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1698 if (entries++ == 0) 1699 npv = pv; 1700 1701 /* Cacheable mappings */ 1702 if ((pv->pv_flags & PVF_NC) == 0) { 1703 cacheable_entries++; 1704 if (kpmap == pv->pv_pmap) 1705 kern_cacheable++; 1706 } 1707 1708 /* Writable mappings */ 1709 if (pv->pv_flags & PVF_WRITE) 1710 ++writable; 1711 } else 1712 if (pv->pv_flags & PVF_WRITE) 1713 other_writable = 1; 1714 } 1715 1716 /* 1717 * Enable or disable caching as necessary. 1718 * Note: the first entry might be part of the kernel pmap, 1719 * so we can't assume this is indicative of the state of the 1720 * other (maybe non-kpmap) entries. 1721 */ 1722 if ((entries > 1 && writable) || 1723 (entries > 0 && pm == kpmap && other_writable)) { 1724 if (cacheable_entries == 0) 1725 return; 1726 1727 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1728 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1729 (pv->pv_flags & PVF_NC)) 1730 continue; 1731 1732 pv->pv_flags |= PVF_NC; 1733 1734 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1735 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1736 pte = *ptep & ~L2_S_CACHE_MASK; 1737 1738 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1739 l2pte_valid(pte)) { 1740 if (PV_BEEN_EXECD(pv->pv_flags)) { 1741 #ifdef PMAP_CACHE_VIVT 1742 pmap_idcache_wbinv_range(pv->pv_pmap, 1743 pv->pv_va, PAGE_SIZE); 1744 #endif 1745 pmap_tlb_flushID_SE(pv->pv_pmap, 1746 pv->pv_va); 1747 } else 1748 if (PV_BEEN_REFD(pv->pv_flags)) { 1749 #ifdef PMAP_CACHE_VIVT 1750 pmap_dcache_wb_range(pv->pv_pmap, 1751 pv->pv_va, PAGE_SIZE, true, 1752 (pv->pv_flags & PVF_WRITE) == 0); 1753 #endif 1754 pmap_tlb_flushD_SE(pv->pv_pmap, 1755 pv->pv_va); 1756 } 1757 } 1758 1759 *ptep = pte; 1760 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1761 } 1762 cpu_cpwait(); 1763 } else 1764 if (entries > cacheable_entries) { 1765 /* 1766 * Turn cacheing back on for some pages. If it is a kernel 1767 * page, only do so if there are no other writable pages. 1768 */ 1769 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1770 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1771 (kpmap != pv->pv_pmap || other_writable))) 1772 continue; 1773 1774 pv->pv_flags &= ~PVF_NC; 1775 1776 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1777 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1778 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1779 1780 if (l2pte_valid(pte)) { 1781 if (PV_BEEN_EXECD(pv->pv_flags)) { 1782 pmap_tlb_flushID_SE(pv->pv_pmap, 1783 pv->pv_va); 1784 } else 1785 if (PV_BEEN_REFD(pv->pv_flags)) { 1786 pmap_tlb_flushD_SE(pv->pv_pmap, 1787 pv->pv_va); 1788 } 1789 } 1790 1791 *ptep = pte; 1792 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1793 } 1794 } 1795 } 1796 #endif 1797 1798 #ifdef PMAP_CACHE_VIPT 1799 /* 1800 * For virtually indexed / physically tagged caches, what we have to worry 1801 * about is illegal cache aliases. To prevent this, we must ensure that 1802 * virtual addresses that map the physical page use the same bits for those 1803 * bits masked by "arm_cache_prefer_mask" (bits 12+). If there is a conflict, 1804 * all mappings of the page must be non-cached. 1805 */ 1806 #if 0 1807 static inline vaddr_t 1808 pmap_check_sets(paddr_t pa) 1809 { 1810 extern int arm_dcache_l2_nsets; 1811 int set, way; 1812 vaddr_t mask = 0; 1813 int v; 1814 pa |= 1; 1815 for (set = 0; set < (1 << arm_dcache_l2_nsets); set++) { 1816 for (way = 0; way < 4; way++) { 1817 v = (way << 30) | (set << 5); 1818 asm("mcr p15, 3, %0, c15, c2, 0" :: "r"(v)); 1819 asm("mrc p15, 3, %0, c15, c0, 0" : "=r"(v)); 1820 1821 if ((v & (1 | ~(PAGE_SIZE-1))) == pa) { 1822 mask |= 1 << (set >> 7); 1823 } 1824 } 1825 } 1826 return mask; 1827 } 1828 #endif 1829 static void 1830 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1831 { 1832 struct pv_entry *pv; 1833 vaddr_t tst_mask; 1834 bool bad_alias; 1835 struct l2_bucket *l2b; 1836 pt_entry_t *ptep, pte, opte; 1837 const u_int 1838 rw_mappings = pg->mdpage.urw_mappings + pg->mdpage.krw_mappings, 1839 ro_mappings = pg->mdpage.uro_mappings + pg->mdpage.kro_mappings; 1840 1841 /* do we need to do anything? */ 1842 if (arm_cache_prefer_mask == 0) 1843 return; 1844 1845 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1846 pg, pm, va)); 1847 1848 #define popc4(x) \ 1849 (((0x94 >> ((x & 3) << 1)) & 3) + ((0x94 >> ((x & 12) >> 1)) & 3)) 1850 #if 0 1851 tst_mask = pmap_check_sets(pg->phys_addr); 1852 KASSERT(popc4(tst_mask) < 2); 1853 #endif 1854 1855 KASSERT(!va || pm); 1856 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1857 1858 /* Already a conflict? */ 1859 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1860 /* just an add, things are already non-cached */ 1861 KASSERT(!(pg->mdpage.pvh_attrs & PVF_DIRTY)); 1862 bad_alias = false; 1863 if (va) { 1864 PMAPCOUNT(vac_color_none); 1865 bad_alias = true; 1866 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1867 goto fixup; 1868 } 1869 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1870 /* the list can't be empty because it would be cachable */ 1871 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) { 1872 tst_mask = pg->mdpage.pvh_attrs; 1873 } else { 1874 KASSERT(pv); 1875 tst_mask = pv->pv_va; 1876 pv = SLIST_NEXT(pv, pv_link); 1877 } 1878 /* 1879 * Only check for a bad alias if we have writable mappings. 1880 */ 1881 tst_mask &= arm_cache_prefer_mask; 1882 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1883 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1884 /* if there's a bad alias, stop checking. */ 1885 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1886 bad_alias = true; 1887 } 1888 pg->mdpage.pvh_attrs |= PVF_WRITE; 1889 if (!bad_alias) 1890 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1891 } else { 1892 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1893 } 1894 /* If no conflicting colors, set everything back to cached */ 1895 if (!bad_alias) { 1896 #ifdef DEBUG 1897 if ((pg->mdpage.pvh_attrs & PVF_WRITE) 1898 || ro_mappings < 2) { 1899 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1900 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1901 } 1902 1903 #endif 1904 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1905 pg->mdpage.pvh_attrs |= tst_mask | PVF_COLORED; 1906 /* 1907 * Restore DIRTY bit if page is modified 1908 */ 1909 if (pg->mdpage.pvh_attrs & PVF_DMOD) 1910 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1911 PMAPCOUNT(vac_color_restore); 1912 } else { 1913 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1914 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1915 } 1916 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1917 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1918 } else if (!va) { 1919 KASSERT(pmap_is_page_colored_p(pg)); 1920 KASSERT(!(pg->mdpage.pvh_attrs & PVF_WRITE) 1921 || (pg->mdpage.pvh_attrs & PVF_DIRTY)); 1922 if (rw_mappings == 0) 1923 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1924 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1925 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1926 return; 1927 } else if (!pmap_is_page_colored_p(pg)) { 1928 /* not colored so we just use its color */ 1929 KASSERT(pg->mdpage.pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1930 PMAPCOUNT(vac_color_new); 1931 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1932 pg->mdpage.pvh_attrs |= PVF_COLORED 1933 | (va & arm_cache_prefer_mask) 1934 | (rw_mappings > 0 ? PVF_WRITE : 0); 1935 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1936 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1937 return; 1938 } else if (((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1939 bad_alias = false; 1940 if (rw_mappings > 0) { 1941 /* 1942 * We now have writeable mappings and more than one 1943 * readonly mapping, verify the colors don't clash 1944 * and mark the page as writeable. 1945 */ 1946 if (ro_mappings > 1 1947 && (pg->mdpage.pvh_attrs & PVF_WRITE) == 0 1948 && arm_cache_prefer_mask) { 1949 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1950 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1951 /* if there's a bad alias, stop checking. */ 1952 if (((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0) { 1953 bad_alias = true; 1954 break; 1955 } 1956 } 1957 } 1958 pg->mdpage.pvh_attrs |= PVF_WRITE; 1959 } 1960 /* If no conflicting colors, set everything back to cached */ 1961 if (!bad_alias) { 1962 #ifdef DEBUG 1963 if (rw_mappings > 0 1964 || (pg->mdpage.pvh_attrs & PMAP_KMPAGE)) { 1965 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1966 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1967 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1968 } 1969 #endif 1970 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) 1971 PMAPCOUNT(vac_color_reuse); 1972 else 1973 PMAPCOUNT(vac_color_ok); 1974 1975 /* matching color, just return */ 1976 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1977 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1978 return; 1979 } 1980 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1981 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1982 1983 /* color conflict. evict from cache. */ 1984 1985 pmap_flush_page(pg, true); 1986 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 1987 pg->mdpage.pvh_attrs |= PVF_NC; 1988 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1989 PMAPCOUNT(vac_color_erase); 1990 } else if (rw_mappings == 0 1991 && (pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 1992 KASSERT((pg->mdpage.pvh_attrs & PVF_WRITE) == 0); 1993 1994 /* 1995 * If the page has dirty cache lines, clean it. 1996 */ 1997 if (pg->mdpage.pvh_attrs & PVF_DIRTY) 1998 pmap_flush_page(pg, false); 1999 2000 /* 2001 * If this is the first remapping (we know that there are no 2002 * writeable mappings), then this is a simple color change. 2003 * Otherwise this is a seconary r/o mapping, which means 2004 * we don't have to do anything. 2005 */ 2006 if (ro_mappings == 1) { 2007 KASSERT(((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2008 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2009 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2010 PMAPCOUNT(vac_color_change); 2011 } else { 2012 PMAPCOUNT(vac_color_blind); 2013 } 2014 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2015 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2016 return; 2017 } else { 2018 if (rw_mappings > 0) 2019 pg->mdpage.pvh_attrs |= PVF_WRITE; 2020 2021 /* color conflict. evict from cache. */ 2022 pmap_flush_page(pg, true); 2023 2024 /* the list can't be empty because this was a enter/modify */ 2025 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2026 if ((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2027 KASSERT(pv); 2028 /* 2029 * If there's only one mapped page, change color to the 2030 * page's new color and return. Restore the DIRTY bit 2031 * that was erased by pmap_flush_page. 2032 */ 2033 if (SLIST_NEXT(pv, pv_link) == NULL) { 2034 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2035 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2036 if (pg->mdpage.pvh_attrs & PVF_DMOD) 2037 pg->mdpage.pvh_attrs |= PVF_DIRTY; 2038 PMAPCOUNT(vac_color_change); 2039 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2040 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2041 return; 2042 } 2043 } 2044 bad_alias = true; 2045 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2046 pg->mdpage.pvh_attrs |= PVF_NC; 2047 PMAPCOUNT(vac_color_erase); 2048 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2049 } 2050 2051 fixup: 2052 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2053 2054 /* 2055 * Turn cacheing on/off for all pages. 2056 */ 2057 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2058 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2059 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2060 opte = *ptep; 2061 pte = opte & ~L2_S_CACHE_MASK; 2062 if (bad_alias) { 2063 pv->pv_flags |= PVF_NC; 2064 } else { 2065 pv->pv_flags &= ~PVF_NC; 2066 pte |= pte_l2_s_cache_mode; 2067 } 2068 2069 if (opte == pte) /* only update is there's a change */ 2070 continue; 2071 2072 if (l2pte_valid(pte)) { 2073 if (PV_BEEN_EXECD(pv->pv_flags)) { 2074 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2075 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2076 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2077 } 2078 } 2079 2080 *ptep = pte; 2081 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2082 } 2083 } 2084 #endif /* PMAP_CACHE_VIPT */ 2085 2086 2087 /* 2088 * Modify pte bits for all ptes corresponding to the given physical address. 2089 * We use `maskbits' rather than `clearbits' because we're always passing 2090 * constants and the latter would require an extra inversion at run-time. 2091 */ 2092 static void 2093 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2094 { 2095 struct l2_bucket *l2b; 2096 struct pv_entry *pv; 2097 pt_entry_t *ptep, npte, opte; 2098 pmap_t pm; 2099 vaddr_t va; 2100 u_int oflags; 2101 #ifdef PMAP_CACHE_VIPT 2102 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 2103 bool need_syncicache = false; 2104 bool did_syncicache = false; 2105 bool need_vac_me_harder = false; 2106 #endif 2107 2108 NPDEBUG(PDB_BITS, 2109 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2110 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2111 2112 PMAP_HEAD_TO_MAP_LOCK(); 2113 simple_lock(&pg->mdpage.pvh_slock); 2114 2115 #ifdef PMAP_CACHE_VIPT 2116 /* 2117 * If we might want to sync the I-cache and we've modified it, 2118 * then we know we definitely need to sync or discard it. 2119 */ 2120 if (want_syncicache) 2121 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 2122 #endif 2123 /* 2124 * Clear saved attributes (modify, reference) 2125 */ 2126 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2127 2128 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 2129 #ifdef PMAP_CACHE_VIPT 2130 if (need_syncicache) { 2131 /* 2132 * No one has it mapped, so just discard it. The next 2133 * exec remapping will cause it to be synced. 2134 */ 2135 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2136 PMAPCOUNT(exec_discarded_clearbit); 2137 } 2138 #endif 2139 simple_unlock(&pg->mdpage.pvh_slock); 2140 PMAP_HEAD_TO_MAP_UNLOCK(); 2141 return; 2142 } 2143 2144 /* 2145 * Loop over all current mappings setting/clearing as appropos 2146 */ 2147 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2148 va = pv->pv_va; 2149 pm = pv->pv_pmap; 2150 oflags = pv->pv_flags; 2151 /* 2152 * Kernel entries are unmanaged and as such not to be changed. 2153 */ 2154 if (oflags & PVF_KENTRY) 2155 continue; 2156 pv->pv_flags &= ~maskbits; 2157 2158 pmap_acquire_pmap_lock(pm); 2159 2160 l2b = pmap_get_l2_bucket(pm, va); 2161 KDASSERT(l2b != NULL); 2162 2163 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2164 npte = opte = *ptep; 2165 2166 NPDEBUG(PDB_BITS, 2167 printf( 2168 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2169 pv, pv->pv_pmap, pv->pv_va, oflags)); 2170 2171 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2172 #ifdef PMAP_CACHE_VIVT 2173 if ((pv->pv_flags & PVF_NC)) { 2174 /* 2175 * Entry is not cacheable: 2176 * 2177 * Don't turn caching on again if this is a 2178 * modified emulation. This would be 2179 * inconsitent with the settings created by 2180 * pmap_vac_me_harder(). Otherwise, it's safe 2181 * to re-enable cacheing. 2182 * 2183 * There's no need to call pmap_vac_me_harder() 2184 * here: all pages are losing their write 2185 * permission. 2186 */ 2187 if (maskbits & PVF_WRITE) { 2188 npte |= pte_l2_s_cache_mode; 2189 pv->pv_flags &= ~PVF_NC; 2190 } 2191 } else 2192 if (opte & L2_S_PROT_W) { 2193 /* 2194 * Entry is writable/cacheable: check if pmap 2195 * is current if it is flush it, otherwise it 2196 * won't be in the cache 2197 */ 2198 if (PV_BEEN_EXECD(oflags)) 2199 pmap_idcache_wbinv_range(pm, pv->pv_va, 2200 PAGE_SIZE); 2201 else 2202 if (PV_BEEN_REFD(oflags)) 2203 pmap_dcache_wb_range(pm, pv->pv_va, 2204 PAGE_SIZE, 2205 (maskbits & PVF_REF) != 0, false); 2206 } 2207 #endif 2208 2209 /* make the pte read only */ 2210 npte &= ~L2_S_PROT_W; 2211 2212 if (maskbits & oflags & PVF_WRITE) { 2213 /* 2214 * Keep alias accounting up to date 2215 */ 2216 if (pv->pv_pmap == pmap_kernel()) { 2217 pg->mdpage.krw_mappings--; 2218 pg->mdpage.kro_mappings++; 2219 } else { 2220 pg->mdpage.urw_mappings--; 2221 pg->mdpage.uro_mappings++; 2222 } 2223 #ifdef PMAP_CACHE_VIPT 2224 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 2225 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2226 if (want_syncicache) 2227 need_syncicache = true; 2228 need_vac_me_harder = true; 2229 #endif 2230 } 2231 } 2232 2233 if (maskbits & PVF_REF) { 2234 if ((pv->pv_flags & PVF_NC) == 0 && 2235 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2236 l2pte_valid(npte)) { 2237 #ifdef PMAP_CACHE_VIVT 2238 /* 2239 * Check npte here; we may have already 2240 * done the wbinv above, and the validity 2241 * of the PTE is the same for opte and 2242 * npte. 2243 */ 2244 /* XXXJRT need idcache_inv_range */ 2245 if (PV_BEEN_EXECD(oflags)) 2246 pmap_idcache_wbinv_range(pm, 2247 pv->pv_va, PAGE_SIZE); 2248 else 2249 if (PV_BEEN_REFD(oflags)) 2250 pmap_dcache_wb_range(pm, 2251 pv->pv_va, PAGE_SIZE, 2252 true, true); 2253 #endif 2254 } 2255 2256 /* 2257 * Make the PTE invalid so that we will take a 2258 * page fault the next time the mapping is 2259 * referenced. 2260 */ 2261 npte &= ~L2_TYPE_MASK; 2262 npte |= L2_TYPE_INV; 2263 } 2264 2265 if (npte != opte) { 2266 *ptep = npte; 2267 PTE_SYNC(ptep); 2268 /* Flush the TLB entry if a current pmap. */ 2269 if (PV_BEEN_EXECD(oflags)) 2270 pmap_tlb_flushID_SE(pm, pv->pv_va); 2271 else 2272 if (PV_BEEN_REFD(oflags)) 2273 pmap_tlb_flushD_SE(pm, pv->pv_va); 2274 } 2275 2276 pmap_release_pmap_lock(pm); 2277 2278 NPDEBUG(PDB_BITS, 2279 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2280 pm, va, opte, npte)); 2281 } 2282 2283 #ifdef PMAP_CACHE_VIPT 2284 /* 2285 * If we need to sync the I-cache and we haven't done it yet, do it. 2286 */ 2287 if (need_syncicache && !did_syncicache) { 2288 pmap_syncicache_page(pg); 2289 PMAPCOUNT(exec_synced_clearbit); 2290 } 2291 /* 2292 * If we are changing this to read-only, we need to call vac_me_harder 2293 * so we can change all the read-only pages to cacheable. We pretend 2294 * this as a page deletion. 2295 */ 2296 if (need_vac_me_harder) { 2297 if (pg->mdpage.pvh_attrs & PVF_NC) 2298 pmap_vac_me_harder(pg, NULL, 0); 2299 } 2300 #endif 2301 2302 simple_unlock(&pg->mdpage.pvh_slock); 2303 PMAP_HEAD_TO_MAP_UNLOCK(); 2304 } 2305 2306 /* 2307 * pmap_clean_page() 2308 * 2309 * This is a local function used to work out the best strategy to clean 2310 * a single page referenced by its entry in the PV table. It's used by 2311 * pmap_copy_page, pmap_zero page and maybe some others later on. 2312 * 2313 * Its policy is effectively: 2314 * o If there are no mappings, we don't bother doing anything with the cache. 2315 * o If there is one mapping, we clean just that page. 2316 * o If there are multiple mappings, we clean the entire cache. 2317 * 2318 * So that some functions can be further optimised, it returns 0 if it didn't 2319 * clean the entire cache, or 1 if it did. 2320 * 2321 * XXX One bug in this routine is that if the pv_entry has a single page 2322 * mapped at 0x00000000 a whole cache clean will be performed rather than 2323 * just the 1 page. Since this should not occur in everyday use and if it does 2324 * it will just result in not the most efficient clean for the page. 2325 */ 2326 #ifdef PMAP_CACHE_VIVT 2327 static int 2328 pmap_clean_page(struct pv_entry *pv, bool is_src) 2329 { 2330 pmap_t pm, pm_to_clean = NULL; 2331 struct pv_entry *npv; 2332 u_int cache_needs_cleaning = 0; 2333 u_int flags = 0; 2334 vaddr_t page_to_clean = 0; 2335 2336 if (pv == NULL) { 2337 /* nothing mapped in so nothing to flush */ 2338 return (0); 2339 } 2340 2341 /* 2342 * Since we flush the cache each time we change to a different 2343 * user vmspace, we only need to flush the page if it is in the 2344 * current pmap. 2345 */ 2346 pm = curproc->p_vmspace->vm_map.pmap; 2347 2348 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2349 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2350 flags |= npv->pv_flags; 2351 /* 2352 * The page is mapped non-cacheable in 2353 * this map. No need to flush the cache. 2354 */ 2355 if (npv->pv_flags & PVF_NC) { 2356 #ifdef DIAGNOSTIC 2357 if (cache_needs_cleaning) 2358 panic("pmap_clean_page: " 2359 "cache inconsistency"); 2360 #endif 2361 break; 2362 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2363 continue; 2364 if (cache_needs_cleaning) { 2365 page_to_clean = 0; 2366 break; 2367 } else { 2368 page_to_clean = npv->pv_va; 2369 pm_to_clean = npv->pv_pmap; 2370 } 2371 cache_needs_cleaning = 1; 2372 } 2373 } 2374 2375 if (page_to_clean) { 2376 if (PV_BEEN_EXECD(flags)) 2377 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2378 PAGE_SIZE); 2379 else 2380 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2381 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2382 } else if (cache_needs_cleaning) { 2383 if (PV_BEEN_EXECD(flags)) 2384 pmap_idcache_wbinv_all(pm); 2385 else 2386 pmap_dcache_wbinv_all(pm); 2387 return (1); 2388 } 2389 return (0); 2390 } 2391 #endif 2392 2393 #ifdef PMAP_CACHE_VIPT 2394 /* 2395 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2396 * right cache alias to make sure we flush the right stuff. 2397 */ 2398 void 2399 pmap_syncicache_page(struct vm_page *pg) 2400 { 2401 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2402 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2403 2404 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2405 pg, pg->mdpage.pvh_attrs)); 2406 /* 2407 * No need to clean the page if it's non-cached. 2408 */ 2409 if (pg->mdpage.pvh_attrs & PVF_NC) 2410 return; 2411 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2412 2413 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2414 /* 2415 * Set up a PTE with the right coloring to flush existing cache lines. 2416 */ 2417 *ptep = L2_S_PROTO | 2418 VM_PAGE_TO_PHYS(pg) 2419 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2420 | pte_l2_s_cache_mode; 2421 PTE_SYNC(ptep); 2422 2423 /* 2424 * Flush it. 2425 */ 2426 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2427 /* 2428 * Unmap the page. 2429 */ 2430 *ptep = 0; 2431 PTE_SYNC(ptep); 2432 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2433 2434 pg->mdpage.pvh_attrs |= PVF_EXEC; 2435 PMAPCOUNT(exec_synced); 2436 } 2437 2438 void 2439 pmap_flush_page(struct vm_page *pg, bool flush) 2440 { 2441 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2442 const size_t pte_offset = va_offset >> PGSHIFT; 2443 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2444 const pt_entry_t oldpte = *ptep; 2445 #if 0 2446 vaddr_t mask; 2447 #endif 2448 2449 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2450 #if 0 2451 mask = pmap_check_sets(pg->phys_addr); 2452 KASSERT(popc4(mask) < 2); 2453 #endif 2454 2455 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2456 pg, pg->mdpage.pvh_attrs)); 2457 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2458 /* 2459 * Set up a PTE with the right coloring to flush existing cache entries. 2460 */ 2461 *ptep = L2_S_PROTO 2462 | VM_PAGE_TO_PHYS(pg) 2463 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2464 | pte_l2_s_cache_mode; 2465 PTE_SYNC(ptep); 2466 2467 /* 2468 * Flush it. 2469 */ 2470 if (flush) { 2471 cpu_idcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 2472 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2473 } else { 2474 cpu_dcache_wb_range(cdstp + va_offset, PAGE_SIZE); 2475 /* 2476 * Mark that the page is no longer dirty. 2477 */ 2478 if ((pg->mdpage.pvh_attrs & PVF_DMOD) == 0) 2479 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2480 } 2481 2482 /* 2483 * Restore the page table entry since we might have interrupted 2484 * pmap_zero_page or pmap_copy_page which was already using this pte. 2485 */ 2486 *ptep = oldpte; 2487 PTE_SYNC(ptep); 2488 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2489 #if 0 2490 mask = pmap_check_sets(pg->phys_addr); 2491 KASSERT(mask == 0); 2492 #endif 2493 } 2494 #endif /* PMAP_CACHE_VIPT */ 2495 2496 /* 2497 * Routine: pmap_page_remove 2498 * Function: 2499 * Removes this physical page from 2500 * all physical maps in which it resides. 2501 * Reflects back modify bits to the pager. 2502 */ 2503 static void 2504 pmap_page_remove(struct vm_page *pg) 2505 { 2506 struct l2_bucket *l2b; 2507 struct pv_entry *pv, *npv, **pvp; 2508 pmap_t pm, curpm; 2509 pt_entry_t *ptep, pte; 2510 bool flush; 2511 u_int flags; 2512 2513 NPDEBUG(PDB_FOLLOW, 2514 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2515 VM_PAGE_TO_PHYS(pg))); 2516 2517 PMAP_HEAD_TO_MAP_LOCK(); 2518 simple_lock(&pg->mdpage.pvh_slock); 2519 2520 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2521 if (pv == NULL) { 2522 #ifdef PMAP_CACHE_VIPT 2523 /* 2524 * We *know* the page contents are about to be replaced. 2525 * Discard the exec contents 2526 */ 2527 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2528 PMAPCOUNT(exec_discarded_page_protect); 2529 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2530 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2531 #endif 2532 simple_unlock(&pg->mdpage.pvh_slock); 2533 PMAP_HEAD_TO_MAP_UNLOCK(); 2534 return; 2535 } 2536 #ifdef PMAP_CACHE_VIPT 2537 KASSERT(pmap_is_page_colored_p(pg)); 2538 #endif 2539 2540 /* 2541 * Clear alias counts 2542 */ 2543 #ifdef PMAP_CACHE_VIVT 2544 pg->mdpage.k_mappings = 0; 2545 #endif 2546 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2547 2548 flush = false; 2549 flags = 0; 2550 curpm = curproc->p_vmspace->vm_map.pmap; 2551 2552 #ifdef PMAP_CACHE_VIVT 2553 pmap_clean_page(pv, false); 2554 #endif 2555 2556 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 2557 while (pv) { 2558 pm = pv->pv_pmap; 2559 npv = SLIST_NEXT(pv, pv_link); 2560 if (flush == false && (pm == curpm || pm == pmap_kernel())) 2561 flush = true; 2562 2563 if (pm == pmap_kernel()) { 2564 #ifdef PMAP_CACHE_VIPT 2565 /* 2566 * If this was unmanaged mapping, it must be preserved. 2567 * Move it back on the list and advance the end-of-list 2568 * pointer. 2569 */ 2570 if (pv->pv_flags & PVF_KENTRY) { 2571 *pvp = pv; 2572 pvp = &SLIST_NEXT(pv, pv_link); 2573 pv = npv; 2574 continue; 2575 } 2576 if (pv->pv_flags & PVF_WRITE) 2577 pg->mdpage.krw_mappings--; 2578 else 2579 pg->mdpage.kro_mappings--; 2580 #endif 2581 PMAPCOUNT(kernel_unmappings); 2582 } 2583 PMAPCOUNT(unmappings); 2584 2585 pmap_acquire_pmap_lock(pm); 2586 2587 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2588 KDASSERT(l2b != NULL); 2589 2590 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2591 pte = *ptep; 2592 2593 /* 2594 * Update statistics 2595 */ 2596 --pm->pm_stats.resident_count; 2597 2598 /* Wired bit */ 2599 if (pv->pv_flags & PVF_WIRED) 2600 --pm->pm_stats.wired_count; 2601 2602 flags |= pv->pv_flags; 2603 2604 /* 2605 * Invalidate the PTEs. 2606 */ 2607 *ptep = 0; 2608 PTE_SYNC_CURRENT(pm, ptep); 2609 pmap_free_l2_bucket(pm, l2b, 1); 2610 2611 pool_put(&pmap_pv_pool, pv); 2612 pv = npv; 2613 /* 2614 * if we reach the end of the list and there are still 2615 * mappings, they might be able to be cached now. 2616 */ 2617 if (pv == NULL) { 2618 *pvp = NULL; 2619 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 2620 pmap_vac_me_harder(pg, pm, 0); 2621 } 2622 pmap_release_pmap_lock(pm); 2623 } 2624 #ifdef PMAP_CACHE_VIPT 2625 /* 2626 * Its EXEC cache is now gone. 2627 */ 2628 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2629 PMAPCOUNT(exec_discarded_page_protect); 2630 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2631 KASSERT(pg->mdpage.urw_mappings == 0); 2632 KASSERT(pg->mdpage.uro_mappings == 0); 2633 if (pg->mdpage.krw_mappings == 0) 2634 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2635 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2636 #endif 2637 simple_unlock(&pg->mdpage.pvh_slock); 2638 PMAP_HEAD_TO_MAP_UNLOCK(); 2639 2640 if (flush) { 2641 /* 2642 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2643 * would need a subsequent call to pmap_update() to ensure 2644 * curpm->pm_cstate.cs_all is reset. Our callers are not 2645 * required to do that (see pmap(9)), so we can't modify 2646 * the current pmap's state. 2647 */ 2648 if (PV_BEEN_EXECD(flags)) 2649 cpu_tlb_flushID(); 2650 else 2651 cpu_tlb_flushD(); 2652 } 2653 cpu_cpwait(); 2654 } 2655 2656 /* 2657 * pmap_t pmap_create(void) 2658 * 2659 * Create a new pmap structure from scratch. 2660 */ 2661 pmap_t 2662 pmap_create(void) 2663 { 2664 pmap_t pm; 2665 2666 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2667 2668 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2669 pm->pm_stats.wired_count = 0; 2670 pm->pm_stats.resident_count = 1; 2671 pm->pm_cstate.cs_all = 0; 2672 pmap_alloc_l1(pm); 2673 2674 /* 2675 * Note: The pool cache ensures that the pm_l2[] array is already 2676 * initialised to zero. 2677 */ 2678 2679 pmap_pinit(pm); 2680 2681 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2682 2683 return (pm); 2684 } 2685 2686 /* 2687 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2688 * int flags) 2689 * 2690 * Insert the given physical page (p) at 2691 * the specified virtual address (v) in the 2692 * target physical map with the protection requested. 2693 * 2694 * NB: This is the only routine which MAY NOT lazy-evaluate 2695 * or lose information. That is, this routine must actually 2696 * insert this page into the given map NOW. 2697 */ 2698 int 2699 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 2700 { 2701 struct l2_bucket *l2b; 2702 struct vm_page *pg, *opg; 2703 struct pv_entry *pve; 2704 pt_entry_t *ptep, npte, opte; 2705 u_int nflags; 2706 u_int oflags; 2707 2708 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2709 2710 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2711 KDASSERT(((va | pa) & PGOFSET) == 0); 2712 2713 /* 2714 * Get a pointer to the page. Later on in this function, we 2715 * test for a managed page by checking pg != NULL. 2716 */ 2717 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2718 2719 nflags = 0; 2720 if (prot & VM_PROT_WRITE) 2721 nflags |= PVF_WRITE; 2722 if (prot & VM_PROT_EXECUTE) 2723 nflags |= PVF_EXEC; 2724 if (flags & PMAP_WIRED) 2725 nflags |= PVF_WIRED; 2726 2727 PMAP_MAP_TO_HEAD_LOCK(); 2728 pmap_acquire_pmap_lock(pm); 2729 2730 /* 2731 * Fetch the L2 bucket which maps this page, allocating one if 2732 * necessary for user pmaps. 2733 */ 2734 if (pm == pmap_kernel()) 2735 l2b = pmap_get_l2_bucket(pm, va); 2736 else 2737 l2b = pmap_alloc_l2_bucket(pm, va); 2738 if (l2b == NULL) { 2739 if (flags & PMAP_CANFAIL) { 2740 pmap_release_pmap_lock(pm); 2741 PMAP_MAP_TO_HEAD_UNLOCK(); 2742 return (ENOMEM); 2743 } 2744 panic("pmap_enter: failed to allocate L2 bucket"); 2745 } 2746 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2747 opte = *ptep; 2748 npte = pa; 2749 oflags = 0; 2750 2751 if (opte) { 2752 /* 2753 * There is already a mapping at this address. 2754 * If the physical address is different, lookup the 2755 * vm_page. 2756 */ 2757 if (l2pte_pa(opte) != pa) 2758 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2759 else 2760 opg = pg; 2761 } else 2762 opg = NULL; 2763 2764 if (pg) { 2765 /* 2766 * This is to be a managed mapping. 2767 */ 2768 if ((flags & VM_PROT_ALL) || 2769 (pg->mdpage.pvh_attrs & PVF_REF)) { 2770 /* 2771 * - The access type indicates that we don't need 2772 * to do referenced emulation. 2773 * OR 2774 * - The physical page has already been referenced 2775 * so no need to re-do referenced emulation here. 2776 */ 2777 npte |= L2_S_PROTO; 2778 2779 nflags |= PVF_REF; 2780 2781 if ((prot & VM_PROT_WRITE) != 0 && 2782 ((flags & VM_PROT_WRITE) != 0 || 2783 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2784 /* 2785 * This is a writable mapping, and the 2786 * page's mod state indicates it has 2787 * already been modified. Make it 2788 * writable from the outset. 2789 */ 2790 npte |= L2_S_PROT_W; 2791 nflags |= PVF_MOD; 2792 } 2793 } else { 2794 /* 2795 * Need to do page referenced emulation. 2796 */ 2797 npte |= L2_TYPE_INV; 2798 } 2799 2800 npte |= pte_l2_s_cache_mode; 2801 2802 if (pg == opg) { 2803 /* 2804 * We're changing the attrs of an existing mapping. 2805 */ 2806 simple_lock(&pg->mdpage.pvh_slock); 2807 oflags = pmap_modify_pv(pg, pm, va, 2808 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2809 PVF_MOD | PVF_REF, nflags); 2810 simple_unlock(&pg->mdpage.pvh_slock); 2811 2812 #ifdef PMAP_CACHE_VIVT 2813 /* 2814 * We may need to flush the cache if we're 2815 * doing rw-ro... 2816 */ 2817 if (pm->pm_cstate.cs_cache_d && 2818 (oflags & PVF_NC) == 0 && 2819 (opte & L2_S_PROT_W) != 0 && 2820 (prot & VM_PROT_WRITE) == 0) 2821 cpu_dcache_wb_range(va, PAGE_SIZE); 2822 #endif 2823 } else { 2824 /* 2825 * New mapping, or changing the backing page 2826 * of an existing mapping. 2827 */ 2828 if (opg) { 2829 /* 2830 * Replacing an existing mapping with a new one. 2831 * It is part of our managed memory so we 2832 * must remove it from the PV list 2833 */ 2834 simple_lock(&opg->mdpage.pvh_slock); 2835 pve = pmap_remove_pv(opg, pm, va, 0); 2836 pmap_vac_me_harder(opg, pm, 0); 2837 simple_unlock(&opg->mdpage.pvh_slock); 2838 oflags = pve->pv_flags; 2839 2840 #ifdef PMAP_CACHE_VIVT 2841 /* 2842 * If the old mapping was valid (ref/mod 2843 * emulation creates 'invalid' mappings 2844 * initially) then make sure to frob 2845 * the cache. 2846 */ 2847 if ((oflags & PVF_NC) == 0 && 2848 l2pte_valid(opte)) { 2849 if (PV_BEEN_EXECD(oflags)) { 2850 pmap_idcache_wbinv_range(pm, va, 2851 PAGE_SIZE); 2852 } else 2853 if (PV_BEEN_REFD(oflags)) { 2854 pmap_dcache_wb_range(pm, va, 2855 PAGE_SIZE, true, 2856 (oflags & PVF_WRITE) == 0); 2857 } 2858 } 2859 #endif 2860 } else 2861 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2862 if ((flags & PMAP_CANFAIL) == 0) 2863 panic("pmap_enter: no pv entries"); 2864 2865 if (pm != pmap_kernel()) 2866 pmap_free_l2_bucket(pm, l2b, 0); 2867 pmap_release_pmap_lock(pm); 2868 PMAP_MAP_TO_HEAD_UNLOCK(); 2869 NPDEBUG(PDB_ENTER, 2870 printf("pmap_enter: ENOMEM\n")); 2871 return (ENOMEM); 2872 } 2873 2874 pmap_enter_pv(pg, pve, pm, va, nflags); 2875 } 2876 } else { 2877 /* 2878 * We're mapping an unmanaged page. 2879 * These are always readable, and possibly writable, from 2880 * the get go as we don't need to track ref/mod status. 2881 */ 2882 npte |= L2_S_PROTO; 2883 if (prot & VM_PROT_WRITE) 2884 npte |= L2_S_PROT_W; 2885 2886 /* 2887 * Make sure the vector table is mapped cacheable 2888 */ 2889 if (pm != pmap_kernel() && va == vector_page) 2890 npte |= pte_l2_s_cache_mode; 2891 2892 if (opg) { 2893 /* 2894 * Looks like there's an existing 'managed' mapping 2895 * at this address. 2896 */ 2897 simple_lock(&opg->mdpage.pvh_slock); 2898 pve = pmap_remove_pv(opg, pm, va, 0); 2899 pmap_vac_me_harder(opg, pm, 0); 2900 simple_unlock(&opg->mdpage.pvh_slock); 2901 oflags = pve->pv_flags; 2902 2903 #ifdef PMAP_CACHE_VIVT 2904 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2905 if (PV_BEEN_EXECD(oflags)) 2906 pmap_idcache_wbinv_range(pm, va, 2907 PAGE_SIZE); 2908 else 2909 if (PV_BEEN_REFD(oflags)) 2910 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2911 true, (oflags & PVF_WRITE) == 0); 2912 } 2913 #endif 2914 pool_put(&pmap_pv_pool, pve); 2915 } 2916 } 2917 2918 /* 2919 * Make sure userland mappings get the right permissions 2920 */ 2921 if (pm != pmap_kernel() && va != vector_page) 2922 npte |= L2_S_PROT_U; 2923 2924 /* 2925 * Keep the stats up to date 2926 */ 2927 if (opte == 0) { 2928 l2b->l2b_occupancy++; 2929 pm->pm_stats.resident_count++; 2930 } 2931 2932 NPDEBUG(PDB_ENTER, 2933 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2934 2935 /* 2936 * If this is just a wiring change, the two PTEs will be 2937 * identical, so there's no need to update the page table. 2938 */ 2939 if (npte != opte) { 2940 bool is_cached = pmap_is_cached(pm); 2941 2942 *ptep = npte; 2943 if (is_cached) { 2944 /* 2945 * We only need to frob the cache/tlb if this pmap 2946 * is current 2947 */ 2948 PTE_SYNC(ptep); 2949 if (va != vector_page && l2pte_valid(npte)) { 2950 /* 2951 * This mapping is likely to be accessed as 2952 * soon as we return to userland. Fix up the 2953 * L1 entry to avoid taking another 2954 * page/domain fault. 2955 */ 2956 pd_entry_t *pl1pd, l1pd; 2957 2958 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2959 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2960 L1_C_PROTO; 2961 if (*pl1pd != l1pd) { 2962 *pl1pd = l1pd; 2963 PTE_SYNC(pl1pd); 2964 } 2965 } 2966 } 2967 2968 if (PV_BEEN_EXECD(oflags)) 2969 pmap_tlb_flushID_SE(pm, va); 2970 else 2971 if (PV_BEEN_REFD(oflags)) 2972 pmap_tlb_flushD_SE(pm, va); 2973 2974 NPDEBUG(PDB_ENTER, 2975 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2976 is_cached, pm->pm_cstate.cs_all)); 2977 2978 if (pg != NULL) { 2979 simple_lock(&pg->mdpage.pvh_slock); 2980 pmap_vac_me_harder(pg, pm, va); 2981 simple_unlock(&pg->mdpage.pvh_slock); 2982 } 2983 } 2984 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 2985 if (pg) { 2986 simple_lock(&pg->mdpage.pvh_slock); 2987 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2988 KASSERT(((pg->mdpage.pvh_attrs & PVF_WRITE) == 0) == (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0)); 2989 simple_unlock(&pg->mdpage.pvh_slock); 2990 } 2991 #endif 2992 2993 pmap_release_pmap_lock(pm); 2994 PMAP_MAP_TO_HEAD_UNLOCK(); 2995 2996 return (0); 2997 } 2998 2999 /* 3000 * pmap_remove() 3001 * 3002 * pmap_remove is responsible for nuking a number of mappings for a range 3003 * of virtual address space in the current pmap. To do this efficiently 3004 * is interesting, because in a number of cases a wide virtual address 3005 * range may be supplied that contains few actual mappings. So, the 3006 * optimisations are: 3007 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3008 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3009 * maybe do just a partial cache clean. This path of execution is 3010 * complicated by the fact that the cache must be flushed _before_ 3011 * the PTE is nuked, being a VAC :-) 3012 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3013 * all invalidations until pmap_update(), since pmap_remove_all() has 3014 * already flushed the cache. 3015 * 4. Maybe later fast-case a single page, but I don't think this is 3016 * going to make _that_ much difference overall. 3017 */ 3018 3019 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3020 3021 void 3022 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 3023 { 3024 struct l2_bucket *l2b; 3025 vaddr_t next_bucket; 3026 pt_entry_t *ptep; 3027 u_int cleanlist_idx, total, cnt; 3028 struct { 3029 vaddr_t va; 3030 pt_entry_t *ptep; 3031 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3032 u_int mappings, is_exec, is_refd; 3033 3034 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3035 "eva=%08lx\n", pm, sva, eva)); 3036 3037 /* 3038 * we lock in the pmap => pv_head direction 3039 */ 3040 PMAP_MAP_TO_HEAD_LOCK(); 3041 pmap_acquire_pmap_lock(pm); 3042 3043 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3044 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3045 if (pm->pm_cstate.cs_tlb == 0) 3046 pm->pm_remove_all = true; 3047 } else 3048 cleanlist_idx = 0; 3049 3050 total = 0; 3051 3052 while (sva < eva) { 3053 /* 3054 * Do one L2 bucket's worth at a time. 3055 */ 3056 next_bucket = L2_NEXT_BUCKET(sva); 3057 if (next_bucket > eva) 3058 next_bucket = eva; 3059 3060 l2b = pmap_get_l2_bucket(pm, sva); 3061 if (l2b == NULL) { 3062 sva = next_bucket; 3063 continue; 3064 } 3065 3066 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3067 3068 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3069 struct vm_page *pg; 3070 pt_entry_t pte; 3071 paddr_t pa; 3072 3073 pte = *ptep; 3074 3075 if (pte == 0) { 3076 /* Nothing here, move along */ 3077 continue; 3078 } 3079 3080 pa = l2pte_pa(pte); 3081 is_exec = 0; 3082 is_refd = 1; 3083 3084 /* 3085 * Update flags. In a number of circumstances, 3086 * we could cluster a lot of these and do a 3087 * number of sequential pages in one go. 3088 */ 3089 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3090 struct pv_entry *pve; 3091 simple_lock(&pg->mdpage.pvh_slock); 3092 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 3093 pmap_vac_me_harder(pg, pm, 0); 3094 simple_unlock(&pg->mdpage.pvh_slock); 3095 if (pve != NULL) { 3096 if (pm->pm_remove_all == false) { 3097 is_exec = 3098 PV_BEEN_EXECD(pve->pv_flags); 3099 is_refd = 3100 PV_BEEN_REFD(pve->pv_flags); 3101 } 3102 pool_put(&pmap_pv_pool, pve); 3103 } else 3104 if (skip_wired) { 3105 /* The mapping is wired. Skip it */ 3106 continue; 3107 } 3108 } else 3109 if (skip_wired) { 3110 /* Unmanaged pages are always wired. */ 3111 continue; 3112 } 3113 3114 mappings++; 3115 3116 if (!l2pte_valid(pte)) { 3117 /* 3118 * Ref/Mod emulation is still active for this 3119 * mapping, therefore it is has not yet been 3120 * accessed. No need to frob the cache/tlb. 3121 */ 3122 *ptep = 0; 3123 PTE_SYNC_CURRENT(pm, ptep); 3124 continue; 3125 } 3126 3127 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3128 /* Add to the clean list. */ 3129 cleanlist[cleanlist_idx].ptep = ptep; 3130 cleanlist[cleanlist_idx].va = 3131 sva | (is_exec & 1); 3132 cleanlist_idx++; 3133 } else 3134 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3135 /* Nuke everything if needed. */ 3136 #ifdef PMAP_CACHE_VIVT 3137 pmap_idcache_wbinv_all(pm); 3138 #endif 3139 pmap_tlb_flushID(pm); 3140 3141 /* 3142 * Roll back the previous PTE list, 3143 * and zero out the current PTE. 3144 */ 3145 for (cnt = 0; 3146 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3147 *cleanlist[cnt].ptep = 0; 3148 PTE_SYNC(cleanlist[cnt].ptep); 3149 } 3150 *ptep = 0; 3151 PTE_SYNC(ptep); 3152 cleanlist_idx++; 3153 pm->pm_remove_all = true; 3154 } else { 3155 *ptep = 0; 3156 PTE_SYNC(ptep); 3157 if (pm->pm_remove_all == false) { 3158 if (is_exec) 3159 pmap_tlb_flushID_SE(pm, sva); 3160 else 3161 if (is_refd) 3162 pmap_tlb_flushD_SE(pm, sva); 3163 } 3164 } 3165 } 3166 3167 /* 3168 * Deal with any left overs 3169 */ 3170 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3171 total += cleanlist_idx; 3172 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3173 if (pm->pm_cstate.cs_all != 0) { 3174 vaddr_t clva = cleanlist[cnt].va & ~1; 3175 if (cleanlist[cnt].va & 1) { 3176 #ifdef PMAP_CACHE_VIVT 3177 pmap_idcache_wbinv_range(pm, 3178 clva, PAGE_SIZE); 3179 #endif 3180 pmap_tlb_flushID_SE(pm, clva); 3181 } else { 3182 #ifdef PMAP_CACHE_VIVT 3183 pmap_dcache_wb_range(pm, 3184 clva, PAGE_SIZE, true, 3185 false); 3186 #endif 3187 pmap_tlb_flushD_SE(pm, clva); 3188 } 3189 } 3190 *cleanlist[cnt].ptep = 0; 3191 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3192 } 3193 3194 /* 3195 * If it looks like we're removing a whole bunch 3196 * of mappings, it's faster to just write-back 3197 * the whole cache now and defer TLB flushes until 3198 * pmap_update() is called. 3199 */ 3200 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3201 cleanlist_idx = 0; 3202 else { 3203 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3204 #ifdef PMAP_CACHE_VIVT 3205 pmap_idcache_wbinv_all(pm); 3206 #endif 3207 pm->pm_remove_all = true; 3208 } 3209 } 3210 3211 pmap_free_l2_bucket(pm, l2b, mappings); 3212 pm->pm_stats.resident_count -= mappings; 3213 } 3214 3215 pmap_release_pmap_lock(pm); 3216 PMAP_MAP_TO_HEAD_UNLOCK(); 3217 } 3218 3219 #ifdef PMAP_CACHE_VIPT 3220 static struct pv_entry * 3221 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3222 { 3223 struct pv_entry *pv; 3224 3225 simple_lock(&pg->mdpage.pvh_slock); 3226 KASSERT(pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 3227 KASSERT((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3228 3229 pv = pmap_remove_pv(pg, pmap_kernel(), va, false); 3230 KASSERT(pv); 3231 KASSERT(pv->pv_flags & PVF_KENTRY); 3232 3233 /* 3234 * If we are removing a writeable mapping to a cached exec page, 3235 * if it's the last mapping then clear it execness other sync 3236 * the page to the icache. 3237 */ 3238 if ((pg->mdpage.pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3239 && (pv->pv_flags & PVF_WRITE) != 0) { 3240 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 3241 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 3242 PMAPCOUNT(exec_discarded_kremove); 3243 } else { 3244 pmap_syncicache_page(pg); 3245 PMAPCOUNT(exec_synced_kremove); 3246 } 3247 } 3248 pmap_vac_me_harder(pg, pmap_kernel(), 0); 3249 simple_unlock(&pg->mdpage.pvh_slock); 3250 3251 return pv; 3252 } 3253 #endif /* PMAP_CACHE_VIPT */ 3254 3255 /* 3256 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3257 * 3258 * We assume there is already sufficient KVM space available 3259 * to do this, as we can't allocate L2 descriptor tables/metadata 3260 * from here. 3261 */ 3262 void 3263 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 3264 { 3265 struct l2_bucket *l2b; 3266 pt_entry_t *ptep, opte; 3267 #ifdef PMAP_CACHE_VIVT 3268 struct vm_page *pg = (prot & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3269 #endif 3270 #ifdef PMAP_CACHE_VIPT 3271 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3272 struct vm_page *opg; 3273 struct pv_entry *pv = NULL; 3274 #endif 3275 3276 NPDEBUG(PDB_KENTER, 3277 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3278 va, pa, prot)); 3279 3280 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3281 KDASSERT(l2b != NULL); 3282 3283 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3284 opte = *ptep; 3285 3286 if (opte == 0) { 3287 PMAPCOUNT(kenter_mappings); 3288 l2b->l2b_occupancy++; 3289 } else { 3290 PMAPCOUNT(kenter_remappings); 3291 #ifdef PMAP_CACHE_VIPT 3292 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3293 if (opg) { 3294 KASSERT(opg != pg); 3295 KASSERT((opg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3296 KASSERT((prot & PMAP_KMPAGE) == 0); 3297 simple_lock(&opg->mdpage.pvh_slock); 3298 pv = pmap_kremove_pg(opg, va); 3299 simple_unlock(&opg->mdpage.pvh_slock); 3300 } 3301 #endif 3302 if (l2pte_valid(opte)) { 3303 #ifdef PMAP_CACHE_VIVT 3304 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3305 #endif 3306 cpu_tlb_flushD_SE(va); 3307 cpu_cpwait(); 3308 } 3309 } 3310 3311 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3312 pte_l2_s_cache_mode; 3313 PTE_SYNC(ptep); 3314 3315 if (pg) { 3316 if (prot & PMAP_KMPAGE) { 3317 simple_lock(&pg->mdpage.pvh_slock); 3318 KASSERT(pg->mdpage.urw_mappings == 0); 3319 KASSERT(pg->mdpage.uro_mappings == 0); 3320 KASSERT(pg->mdpage.krw_mappings == 0); 3321 KASSERT(pg->mdpage.kro_mappings == 0); 3322 #ifdef PMAP_CACHE_VIPT 3323 KASSERT(pv == NULL); 3324 KASSERT((va & PVF_COLORED) == 0); 3325 KASSERT((pg->mdpage.pvh_attrs & PVF_NC) == 0); 3326 /* if there is a color conflict, evict from cache. */ 3327 if (pmap_is_page_colored_p(pg) 3328 && ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask)) { 3329 PMAPCOUNT(vac_color_change); 3330 pmap_flush_page(pg, true); 3331 } 3332 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 3333 pg->mdpage.pvh_attrs |= PVF_KMPAGE 3334 | PVF_COLORED | PVF_DIRTY 3335 | (va & arm_cache_prefer_mask); 3336 #endif 3337 #ifdef PMAP_CACHE_VIVT 3338 pg->mdpage.pvh_attrs |= PVF_KMPAGE; 3339 #endif 3340 pmap_kmpages++; 3341 simple_unlock(&pg->mdpage.pvh_slock); 3342 #ifdef PMAP_CACHE_VIPT 3343 } else { 3344 if (pv == NULL) { 3345 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3346 KASSERT(pv != NULL); 3347 } 3348 pmap_enter_pv(pg, pv, pmap_kernel(), va, 3349 PVF_WIRED | PVF_KENTRY 3350 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3351 if ((prot & VM_PROT_WRITE) 3352 && !(pg->mdpage.pvh_attrs & PVF_NC)) 3353 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3354 KASSERT((prot & VM_PROT_WRITE) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3355 simple_lock(&pg->mdpage.pvh_slock); 3356 pmap_vac_me_harder(pg, pmap_kernel(), va); 3357 simple_unlock(&pg->mdpage.pvh_slock); 3358 #endif 3359 } 3360 #ifdef PMAP_CACHE_VIPT 3361 } else { 3362 if (pv != NULL) 3363 pool_put(&pmap_pv_pool, pv); 3364 #endif 3365 } 3366 } 3367 3368 void 3369 pmap_kremove(vaddr_t va, vsize_t len) 3370 { 3371 struct l2_bucket *l2b; 3372 pt_entry_t *ptep, *sptep, opte; 3373 vaddr_t next_bucket, eva; 3374 u_int mappings; 3375 struct vm_page *opg; 3376 3377 PMAPCOUNT(kenter_unmappings); 3378 3379 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3380 va, len)); 3381 3382 eva = va + len; 3383 3384 while (va < eva) { 3385 next_bucket = L2_NEXT_BUCKET(va); 3386 if (next_bucket > eva) 3387 next_bucket = eva; 3388 3389 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3390 KDASSERT(l2b != NULL); 3391 3392 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3393 mappings = 0; 3394 3395 while (va < next_bucket) { 3396 opte = *ptep; 3397 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3398 if (opg) { 3399 if (opg->mdpage.pvh_attrs & PVF_KMPAGE) { 3400 simple_lock(&opg->mdpage.pvh_slock); 3401 KASSERT(opg->mdpage.urw_mappings == 0); 3402 KASSERT(opg->mdpage.uro_mappings == 0); 3403 KASSERT(opg->mdpage.krw_mappings == 0); 3404 KASSERT(opg->mdpage.kro_mappings == 0); 3405 opg->mdpage.pvh_attrs &= ~PVF_KMPAGE; 3406 #ifdef PMAP_CACHE_VIPT 3407 opg->mdpage.pvh_attrs &= ~PVF_WRITE; 3408 #endif 3409 pmap_kmpages--; 3410 simple_unlock(&opg->mdpage.pvh_slock); 3411 #ifdef PMAP_CACHE_VIPT 3412 } else { 3413 pool_put(&pmap_pv_pool, 3414 pmap_kremove_pg(opg, va)); 3415 #endif 3416 } 3417 } 3418 if (l2pte_valid(opte)) { 3419 #ifdef PMAP_CACHE_VIVT 3420 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3421 #endif 3422 cpu_tlb_flushD_SE(va); 3423 } 3424 if (opte) { 3425 *ptep = 0; 3426 mappings++; 3427 } 3428 va += PAGE_SIZE; 3429 ptep++; 3430 } 3431 KDASSERT(mappings <= l2b->l2b_occupancy); 3432 l2b->l2b_occupancy -= mappings; 3433 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3434 } 3435 cpu_cpwait(); 3436 } 3437 3438 bool 3439 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3440 { 3441 struct l2_dtable *l2; 3442 pd_entry_t *pl1pd, l1pd; 3443 pt_entry_t *ptep, pte; 3444 paddr_t pa; 3445 u_int l1idx; 3446 3447 pmap_acquire_pmap_lock(pm); 3448 3449 l1idx = L1_IDX(va); 3450 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3451 l1pd = *pl1pd; 3452 3453 if (l1pte_section_p(l1pd)) { 3454 /* 3455 * These should only happen for pmap_kernel() 3456 */ 3457 KDASSERT(pm == pmap_kernel()); 3458 pmap_release_pmap_lock(pm); 3459 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3460 } else { 3461 /* 3462 * Note that we can't rely on the validity of the L1 3463 * descriptor as an indication that a mapping exists. 3464 * We have to look it up in the L2 dtable. 3465 */ 3466 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3467 3468 if (l2 == NULL || 3469 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3470 pmap_release_pmap_lock(pm); 3471 return false; 3472 } 3473 3474 ptep = &ptep[l2pte_index(va)]; 3475 pte = *ptep; 3476 pmap_release_pmap_lock(pm); 3477 3478 if (pte == 0) 3479 return false; 3480 3481 switch (pte & L2_TYPE_MASK) { 3482 case L2_TYPE_L: 3483 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3484 break; 3485 3486 default: 3487 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3488 break; 3489 } 3490 } 3491 3492 if (pap != NULL) 3493 *pap = pa; 3494 3495 return true; 3496 } 3497 3498 void 3499 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3500 { 3501 struct l2_bucket *l2b; 3502 pt_entry_t *ptep, pte; 3503 vaddr_t next_bucket; 3504 u_int flags; 3505 u_int clr_mask; 3506 int flush; 3507 3508 NPDEBUG(PDB_PROTECT, 3509 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3510 pm, sva, eva, prot)); 3511 3512 if ((prot & VM_PROT_READ) == 0) { 3513 pmap_remove(pm, sva, eva); 3514 return; 3515 } 3516 3517 if (prot & VM_PROT_WRITE) { 3518 /* 3519 * If this is a read->write transition, just ignore it and let 3520 * uvm_fault() take care of it later. 3521 */ 3522 return; 3523 } 3524 3525 PMAP_MAP_TO_HEAD_LOCK(); 3526 pmap_acquire_pmap_lock(pm); 3527 3528 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3529 flags = 0; 3530 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3531 3532 while (sva < eva) { 3533 next_bucket = L2_NEXT_BUCKET(sva); 3534 if (next_bucket > eva) 3535 next_bucket = eva; 3536 3537 l2b = pmap_get_l2_bucket(pm, sva); 3538 if (l2b == NULL) { 3539 sva = next_bucket; 3540 continue; 3541 } 3542 3543 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3544 3545 while (sva < next_bucket) { 3546 pte = *ptep; 3547 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3548 struct vm_page *pg; 3549 u_int f; 3550 3551 #ifdef PMAP_CACHE_VIVT 3552 /* 3553 * OK, at this point, we know we're doing 3554 * write-protect operation. If the pmap is 3555 * active, write-back the page. 3556 */ 3557 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3558 false, false); 3559 #endif 3560 3561 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3562 pte &= ~L2_S_PROT_W; 3563 *ptep = pte; 3564 PTE_SYNC(ptep); 3565 3566 if (pg != NULL) { 3567 simple_lock(&pg->mdpage.pvh_slock); 3568 f = pmap_modify_pv(pg, pm, sva, 3569 clr_mask, 0); 3570 pmap_vac_me_harder(pg, pm, sva); 3571 simple_unlock(&pg->mdpage.pvh_slock); 3572 } else 3573 f = PVF_REF | PVF_EXEC; 3574 3575 if (flush >= 0) { 3576 flush++; 3577 flags |= f; 3578 } else 3579 if (PV_BEEN_EXECD(f)) 3580 pmap_tlb_flushID_SE(pm, sva); 3581 else 3582 if (PV_BEEN_REFD(f)) 3583 pmap_tlb_flushD_SE(pm, sva); 3584 } 3585 3586 sva += PAGE_SIZE; 3587 ptep++; 3588 } 3589 } 3590 3591 pmap_release_pmap_lock(pm); 3592 PMAP_MAP_TO_HEAD_UNLOCK(); 3593 3594 if (flush) { 3595 if (PV_BEEN_EXECD(flags)) 3596 pmap_tlb_flushID(pm); 3597 else 3598 if (PV_BEEN_REFD(flags)) 3599 pmap_tlb_flushD(pm); 3600 } 3601 } 3602 3603 void 3604 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3605 { 3606 struct l2_bucket *l2b; 3607 pt_entry_t *ptep; 3608 vaddr_t next_bucket; 3609 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3610 3611 NPDEBUG(PDB_EXEC, 3612 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3613 pm, sva, eva)); 3614 3615 PMAP_MAP_TO_HEAD_LOCK(); 3616 pmap_acquire_pmap_lock(pm); 3617 3618 while (sva < eva) { 3619 next_bucket = L2_NEXT_BUCKET(sva); 3620 if (next_bucket > eva) 3621 next_bucket = eva; 3622 3623 l2b = pmap_get_l2_bucket(pm, sva); 3624 if (l2b == NULL) { 3625 sva = next_bucket; 3626 continue; 3627 } 3628 3629 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3630 sva < next_bucket; 3631 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3632 if (l2pte_valid(*ptep)) { 3633 cpu_icache_sync_range(sva, 3634 min(page_size, eva - sva)); 3635 } 3636 } 3637 } 3638 3639 pmap_release_pmap_lock(pm); 3640 PMAP_MAP_TO_HEAD_UNLOCK(); 3641 } 3642 3643 void 3644 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3645 { 3646 3647 NPDEBUG(PDB_PROTECT, 3648 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3649 pg, VM_PAGE_TO_PHYS(pg), prot)); 3650 3651 switch(prot) { 3652 return; 3653 case VM_PROT_READ|VM_PROT_WRITE: 3654 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3655 pmap_clearbit(pg, PVF_EXEC); 3656 break; 3657 #endif 3658 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3659 break; 3660 3661 case VM_PROT_READ: 3662 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3663 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3664 break; 3665 #endif 3666 case VM_PROT_READ|VM_PROT_EXECUTE: 3667 pmap_clearbit(pg, PVF_WRITE); 3668 break; 3669 3670 default: 3671 pmap_page_remove(pg); 3672 break; 3673 } 3674 } 3675 3676 /* 3677 * pmap_clear_modify: 3678 * 3679 * Clear the "modified" attribute for a page. 3680 */ 3681 bool 3682 pmap_clear_modify(struct vm_page *pg) 3683 { 3684 bool rv; 3685 3686 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3687 rv = true; 3688 pmap_clearbit(pg, PVF_MOD); 3689 } else 3690 rv = false; 3691 3692 return (rv); 3693 } 3694 3695 /* 3696 * pmap_clear_reference: 3697 * 3698 * Clear the "referenced" attribute for a page. 3699 */ 3700 bool 3701 pmap_clear_reference(struct vm_page *pg) 3702 { 3703 bool rv; 3704 3705 if (pg->mdpage.pvh_attrs & PVF_REF) { 3706 rv = true; 3707 pmap_clearbit(pg, PVF_REF); 3708 } else 3709 rv = false; 3710 3711 return (rv); 3712 } 3713 3714 /* 3715 * pmap_is_modified: 3716 * 3717 * Test if a page has the "modified" attribute. 3718 */ 3719 /* See <arm/arm32/pmap.h> */ 3720 3721 /* 3722 * pmap_is_referenced: 3723 * 3724 * Test if a page has the "referenced" attribute. 3725 */ 3726 /* See <arm/arm32/pmap.h> */ 3727 3728 int 3729 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3730 { 3731 struct l2_dtable *l2; 3732 struct l2_bucket *l2b; 3733 pd_entry_t *pl1pd, l1pd; 3734 pt_entry_t *ptep, pte; 3735 paddr_t pa; 3736 u_int l1idx; 3737 int rv = 0; 3738 3739 PMAP_MAP_TO_HEAD_LOCK(); 3740 pmap_acquire_pmap_lock(pm); 3741 3742 l1idx = L1_IDX(va); 3743 3744 /* 3745 * If there is no l2_dtable for this address, then the process 3746 * has no business accessing it. 3747 * 3748 * Note: This will catch userland processes trying to access 3749 * kernel addresses. 3750 */ 3751 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3752 if (l2 == NULL) 3753 goto out; 3754 3755 /* 3756 * Likewise if there is no L2 descriptor table 3757 */ 3758 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3759 if (l2b->l2b_kva == NULL) 3760 goto out; 3761 3762 /* 3763 * Check the PTE itself. 3764 */ 3765 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3766 pte = *ptep; 3767 if (pte == 0) 3768 goto out; 3769 3770 /* 3771 * Catch a userland access to the vector page mapped at 0x0 3772 */ 3773 if (user && (pte & L2_S_PROT_U) == 0) 3774 goto out; 3775 3776 pa = l2pte_pa(pte); 3777 3778 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3779 /* 3780 * This looks like a good candidate for "page modified" 3781 * emulation... 3782 */ 3783 struct pv_entry *pv; 3784 struct vm_page *pg; 3785 3786 /* Extract the physical address of the page */ 3787 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3788 goto out; 3789 3790 /* Get the current flags for this page. */ 3791 simple_lock(&pg->mdpage.pvh_slock); 3792 3793 pv = pmap_find_pv(pg, pm, va); 3794 if (pv == NULL) { 3795 simple_unlock(&pg->mdpage.pvh_slock); 3796 goto out; 3797 } 3798 3799 /* 3800 * Do the flags say this page is writable? If not then it 3801 * is a genuine write fault. If yes then the write fault is 3802 * our fault as we did not reflect the write access in the 3803 * PTE. Now we know a write has occurred we can correct this 3804 * and also set the modified bit 3805 */ 3806 if ((pv->pv_flags & PVF_WRITE) == 0) { 3807 simple_unlock(&pg->mdpage.pvh_slock); 3808 goto out; 3809 } 3810 3811 NPDEBUG(PDB_FOLLOW, 3812 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3813 pm, va, VM_PAGE_TO_PHYS(pg))); 3814 3815 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 3816 pv->pv_flags |= PVF_REF | PVF_MOD; 3817 #ifdef PMAP_CACHE_VIPT 3818 /* 3819 * If there are cacheable mappings for this page, mark it dirty. 3820 */ 3821 if ((pg->mdpage.pvh_attrs & PVF_NC) == 0) 3822 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3823 #endif 3824 simple_unlock(&pg->mdpage.pvh_slock); 3825 3826 /* 3827 * Re-enable write permissions for the page. No need to call 3828 * pmap_vac_me_harder(), since this is just a 3829 * modified-emulation fault, and the PVF_WRITE bit isn't 3830 * changing. We've already set the cacheable bits based on 3831 * the assumption that we can write to this page. 3832 */ 3833 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3834 PTE_SYNC(ptep); 3835 rv = 1; 3836 } else 3837 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3838 /* 3839 * This looks like a good candidate for "page referenced" 3840 * emulation. 3841 */ 3842 struct pv_entry *pv; 3843 struct vm_page *pg; 3844 3845 /* Extract the physical address of the page */ 3846 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3847 goto out; 3848 3849 /* Get the current flags for this page. */ 3850 simple_lock(&pg->mdpage.pvh_slock); 3851 3852 pv = pmap_find_pv(pg, pm, va); 3853 if (pv == NULL) { 3854 simple_unlock(&pg->mdpage.pvh_slock); 3855 goto out; 3856 } 3857 3858 pg->mdpage.pvh_attrs |= PVF_REF; 3859 pv->pv_flags |= PVF_REF; 3860 simple_unlock(&pg->mdpage.pvh_slock); 3861 3862 NPDEBUG(PDB_FOLLOW, 3863 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3864 pm, va, VM_PAGE_TO_PHYS(pg))); 3865 3866 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3867 PTE_SYNC(ptep); 3868 rv = 1; 3869 } 3870 3871 /* 3872 * We know there is a valid mapping here, so simply 3873 * fix up the L1 if necessary. 3874 */ 3875 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3876 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3877 if (*pl1pd != l1pd) { 3878 *pl1pd = l1pd; 3879 PTE_SYNC(pl1pd); 3880 rv = 1; 3881 } 3882 3883 #ifdef CPU_SA110 3884 /* 3885 * There are bugs in the rev K SA110. This is a check for one 3886 * of them. 3887 */ 3888 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3889 curcpu()->ci_arm_cpurev < 3) { 3890 /* Always current pmap */ 3891 if (l2pte_valid(pte)) { 3892 extern int kernel_debug; 3893 if (kernel_debug & 1) { 3894 struct proc *p = curlwp->l_proc; 3895 printf("prefetch_abort: page is already " 3896 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3897 printf("prefetch_abort: pc=%08lx proc=%p " 3898 "process=%s\n", va, p, p->p_comm); 3899 printf("prefetch_abort: far=%08x fs=%x\n", 3900 cpu_faultaddress(), cpu_faultstatus()); 3901 } 3902 #ifdef DDB 3903 if (kernel_debug & 2) 3904 Debugger(); 3905 #endif 3906 rv = 1; 3907 } 3908 } 3909 #endif /* CPU_SA110 */ 3910 3911 #ifdef DEBUG 3912 /* 3913 * If 'rv == 0' at this point, it generally indicates that there is a 3914 * stale TLB entry for the faulting address. This happens when two or 3915 * more processes are sharing an L1. Since we don't flush the TLB on 3916 * a context switch between such processes, we can take domain faults 3917 * for mappings which exist at the same VA in both processes. EVEN IF 3918 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3919 * example. 3920 * 3921 * This is extremely likely to happen if pmap_enter() updated the L1 3922 * entry for a recently entered mapping. In this case, the TLB is 3923 * flushed for the new mapping, but there may still be TLB entries for 3924 * other mappings belonging to other processes in the 1MB range 3925 * covered by the L1 entry. 3926 * 3927 * Since 'rv == 0', we know that the L1 already contains the correct 3928 * value, so the fault must be due to a stale TLB entry. 3929 * 3930 * Since we always need to flush the TLB anyway in the case where we 3931 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 3932 * stale TLB entries dynamically. 3933 * 3934 * However, the above condition can ONLY happen if the current L1 is 3935 * being shared. If it happens when the L1 is unshared, it indicates 3936 * that other parts of the pmap are not doing their job WRT managing 3937 * the TLB. 3938 */ 3939 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 3940 extern int last_fault_code; 3941 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 3942 pm, va, ftype); 3943 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 3944 l2, l2b, ptep, pl1pd); 3945 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 3946 pte, l1pd, last_fault_code); 3947 #ifdef DDB 3948 Debugger(); 3949 #endif 3950 } 3951 #endif 3952 3953 cpu_tlb_flushID_SE(va); 3954 cpu_cpwait(); 3955 3956 rv = 1; 3957 3958 out: 3959 pmap_release_pmap_lock(pm); 3960 PMAP_MAP_TO_HEAD_UNLOCK(); 3961 3962 return (rv); 3963 } 3964 3965 /* 3966 * pmap_collect: free resources held by a pmap 3967 * 3968 * => optional function. 3969 * => called when a process is swapped out to free memory. 3970 */ 3971 void 3972 pmap_collect(pmap_t pm) 3973 { 3974 3975 #ifdef PMAP_CACHE_VIVT 3976 pmap_idcache_wbinv_all(pm); 3977 #endif 3978 pm->pm_remove_all = true; 3979 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 3980 pmap_update(pm); 3981 PMAPCOUNT(collects); 3982 } 3983 3984 /* 3985 * Routine: pmap_procwr 3986 * 3987 * Function: 3988 * Synchronize caches corresponding to [addr, addr+len) in p. 3989 * 3990 */ 3991 void 3992 pmap_procwr(struct proc *p, vaddr_t va, int len) 3993 { 3994 /* We only need to do anything if it is the current process. */ 3995 if (p == curproc) 3996 cpu_icache_sync_range(va, len); 3997 } 3998 3999 /* 4000 * Routine: pmap_unwire 4001 * Function: Clear the wired attribute for a map/virtual-address pair. 4002 * 4003 * In/out conditions: 4004 * The mapping must already exist in the pmap. 4005 */ 4006 void 4007 pmap_unwire(pmap_t pm, vaddr_t va) 4008 { 4009 struct l2_bucket *l2b; 4010 pt_entry_t *ptep, pte; 4011 struct vm_page *pg; 4012 paddr_t pa; 4013 4014 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4015 4016 PMAP_MAP_TO_HEAD_LOCK(); 4017 pmap_acquire_pmap_lock(pm); 4018 4019 l2b = pmap_get_l2_bucket(pm, va); 4020 KDASSERT(l2b != NULL); 4021 4022 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4023 pte = *ptep; 4024 4025 /* Extract the physical address of the page */ 4026 pa = l2pte_pa(pte); 4027 4028 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4029 /* Update the wired bit in the pv entry for this page. */ 4030 simple_lock(&pg->mdpage.pvh_slock); 4031 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 4032 simple_unlock(&pg->mdpage.pvh_slock); 4033 } 4034 4035 pmap_release_pmap_lock(pm); 4036 PMAP_MAP_TO_HEAD_UNLOCK(); 4037 } 4038 4039 void 4040 pmap_activate(struct lwp *l) 4041 { 4042 extern int block_userspace_access; 4043 pmap_t opm, npm, rpm; 4044 uint32_t odacr, ndacr; 4045 int oldirqstate; 4046 4047 /* 4048 * If activating a non-current lwp or the current lwp is 4049 * already active, just return. 4050 */ 4051 if (l != curlwp || 4052 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4053 return; 4054 4055 npm = l->l_proc->p_vmspace->vm_map.pmap; 4056 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4057 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4058 4059 /* 4060 * If TTB and DACR are unchanged, short-circuit all the 4061 * TLB/cache management stuff. 4062 */ 4063 if (pmap_previous_active_lwp != NULL) { 4064 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4065 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4066 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4067 4068 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4069 goto all_done; 4070 } else 4071 opm = NULL; 4072 4073 PMAPCOUNT(activations); 4074 block_userspace_access = 1; 4075 4076 /* 4077 * If switching to a user vmspace which is different to the 4078 * most recent one, and the most recent one is potentially 4079 * live in the cache, we must write-back and invalidate the 4080 * entire cache. 4081 */ 4082 rpm = pmap_recent_user; 4083 if (npm != pmap_kernel() && rpm && npm != rpm && 4084 rpm->pm_cstate.cs_cache) { 4085 rpm->pm_cstate.cs_cache = 0; 4086 #ifdef PMAP_CACHE_VIVT 4087 cpu_idcache_wbinv_all(); 4088 #endif 4089 } 4090 4091 /* No interrupts while we frob the TTB/DACR */ 4092 oldirqstate = disable_interrupts(IF32_bits); 4093 4094 /* 4095 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4096 * entry corresponding to 'vector_page' in the incoming L1 table 4097 * before switching to it otherwise subsequent interrupts/exceptions 4098 * (including domain faults!) will jump into hyperspace. 4099 */ 4100 if (npm->pm_pl1vec != NULL) { 4101 cpu_tlb_flushID_SE((u_int)vector_page); 4102 cpu_cpwait(); 4103 *npm->pm_pl1vec = npm->pm_l1vec; 4104 PTE_SYNC(npm->pm_pl1vec); 4105 } 4106 4107 cpu_domains(ndacr); 4108 4109 if (npm == pmap_kernel() || npm == rpm) { 4110 /* 4111 * Switching to a kernel thread, or back to the 4112 * same user vmspace as before... Simply update 4113 * the TTB (no TLB flush required) 4114 */ 4115 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4116 "r"(npm->pm_l1->l1_physaddr)); 4117 cpu_cpwait(); 4118 } else { 4119 /* 4120 * Otherwise, update TTB and flush TLB 4121 */ 4122 cpu_context_switch(npm->pm_l1->l1_physaddr); 4123 if (rpm != NULL) 4124 rpm->pm_cstate.cs_tlb = 0; 4125 } 4126 4127 restore_interrupts(oldirqstate); 4128 4129 block_userspace_access = 0; 4130 4131 all_done: 4132 /* 4133 * The new pmap is resident. Make sure it's marked 4134 * as resident in the cache/TLB. 4135 */ 4136 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4137 if (npm != pmap_kernel()) 4138 pmap_recent_user = npm; 4139 4140 /* The old pmap is not longer active */ 4141 if (opm != NULL) 4142 opm->pm_activated = false; 4143 4144 /* But the new one is */ 4145 npm->pm_activated = true; 4146 } 4147 4148 void 4149 pmap_deactivate(struct lwp *l) 4150 { 4151 4152 /* 4153 * If the process is exiting, make sure pmap_activate() does 4154 * a full MMU context-switch and cache flush, which we might 4155 * otherwise skip. See PR port-arm/38950. 4156 */ 4157 if (l->l_proc->p_sflag & PS_WEXIT) 4158 pmap_previous_active_lwp = NULL; 4159 4160 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4161 } 4162 4163 void 4164 pmap_update(pmap_t pm) 4165 { 4166 4167 if (pm->pm_remove_all) { 4168 /* 4169 * Finish up the pmap_remove_all() optimisation by flushing 4170 * the TLB. 4171 */ 4172 pmap_tlb_flushID(pm); 4173 pm->pm_remove_all = false; 4174 } 4175 4176 if (pmap_is_current(pm)) { 4177 /* 4178 * If we're dealing with a current userland pmap, move its L1 4179 * to the end of the LRU. 4180 */ 4181 if (pm != pmap_kernel()) 4182 pmap_use_l1(pm); 4183 4184 /* 4185 * We can assume we're done with frobbing the cache/tlb for 4186 * now. Make sure any future pmap ops don't skip cache/tlb 4187 * flushes. 4188 */ 4189 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4190 } 4191 4192 PMAPCOUNT(updates); 4193 4194 /* 4195 * make sure TLB/cache operations have completed. 4196 */ 4197 cpu_cpwait(); 4198 } 4199 4200 void 4201 pmap_remove_all(pmap_t pm) 4202 { 4203 4204 /* 4205 * The vmspace described by this pmap is about to be torn down. 4206 * Until pmap_update() is called, UVM will only make calls 4207 * to pmap_remove(). We can make life much simpler by flushing 4208 * the cache now, and deferring TLB invalidation to pmap_update(). 4209 */ 4210 #ifdef PMAP_CACHE_VIVT 4211 pmap_idcache_wbinv_all(pm); 4212 #endif 4213 pm->pm_remove_all = true; 4214 } 4215 4216 /* 4217 * Retire the given physical map from service. 4218 * Should only be called if the map contains no valid mappings. 4219 */ 4220 void 4221 pmap_destroy(pmap_t pm) 4222 { 4223 u_int count; 4224 4225 if (pm == NULL) 4226 return; 4227 4228 if (pm->pm_remove_all) { 4229 pmap_tlb_flushID(pm); 4230 pm->pm_remove_all = false; 4231 } 4232 4233 /* 4234 * Drop reference count 4235 */ 4236 mutex_enter(&pm->pm_lock); 4237 count = --pm->pm_obj.uo_refs; 4238 mutex_exit(&pm->pm_lock); 4239 if (count > 0) { 4240 if (pmap_is_current(pm)) { 4241 if (pm != pmap_kernel()) 4242 pmap_use_l1(pm); 4243 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4244 } 4245 return; 4246 } 4247 4248 /* 4249 * reference count is zero, free pmap resources and then free pmap. 4250 */ 4251 4252 if (vector_page < KERNEL_BASE) { 4253 KDASSERT(!pmap_is_current(pm)); 4254 4255 /* Remove the vector page mapping */ 4256 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4257 pmap_update(pm); 4258 } 4259 4260 LIST_REMOVE(pm, pm_list); 4261 4262 pmap_free_l1(pm); 4263 4264 if (pmap_recent_user == pm) 4265 pmap_recent_user = NULL; 4266 4267 UVM_OBJ_DESTROY(&pm->pm_obj); 4268 4269 /* return the pmap to the pool */ 4270 pool_cache_put(&pmap_cache, pm); 4271 } 4272 4273 4274 /* 4275 * void pmap_reference(pmap_t pm) 4276 * 4277 * Add a reference to the specified pmap. 4278 */ 4279 void 4280 pmap_reference(pmap_t pm) 4281 { 4282 4283 if (pm == NULL) 4284 return; 4285 4286 pmap_use_l1(pm); 4287 4288 mutex_enter(&pm->pm_lock); 4289 pm->pm_obj.uo_refs++; 4290 mutex_exit(&pm->pm_lock); 4291 } 4292 4293 #if ARM_MMU_V6 > 0 4294 4295 static struct evcnt pmap_prefer_nochange_ev = 4296 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4297 static struct evcnt pmap_prefer_change_ev = 4298 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4299 4300 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4301 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4302 4303 void 4304 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4305 { 4306 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4307 vaddr_t va = *vap; 4308 vaddr_t diff = (hint - va) & mask; 4309 if (diff == 0) { 4310 pmap_prefer_nochange_ev.ev_count++; 4311 } else { 4312 pmap_prefer_change_ev.ev_count++; 4313 if (__predict_false(td)) 4314 va -= mask + 1; 4315 *vap = va + diff; 4316 } 4317 } 4318 #endif /* ARM_MMU_V6 */ 4319 4320 /* 4321 * pmap_zero_page() 4322 * 4323 * Zero a given physical page by mapping it at a page hook point. 4324 * In doing the zero page op, the page we zero is mapped cachable, as with 4325 * StrongARM accesses to non-cached pages are non-burst making writing 4326 * _any_ bulk data very slow. 4327 */ 4328 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4329 void 4330 pmap_zero_page_generic(paddr_t phys) 4331 { 4332 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4333 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4334 #endif 4335 #ifdef PMAP_CACHE_VIPT 4336 /* Choose the last page color it had, if any */ 4337 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4338 #else 4339 const vsize_t va_offset = 0; 4340 #endif 4341 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4342 4343 #ifdef DEBUG 4344 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4345 panic("pmap_zero_page: page has mappings"); 4346 #endif 4347 4348 KDASSERT((phys & PGOFSET) == 0); 4349 4350 /* 4351 * Hook in the page, zero it, and purge the cache for that 4352 * zeroed page. Invalidate the TLB as needed. 4353 */ 4354 *ptep = L2_S_PROTO | phys | 4355 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4356 PTE_SYNC(ptep); 4357 cpu_tlb_flushD_SE(cdstp + va_offset); 4358 cpu_cpwait(); 4359 bzero_page(cdstp + va_offset); 4360 /* 4361 * Unmap the page. 4362 */ 4363 *ptep = 0; 4364 PTE_SYNC(ptep); 4365 cpu_tlb_flushD_SE(cdstp + va_offset); 4366 #ifdef PMAP_CACHE_VIVT 4367 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4368 #endif 4369 #ifdef PMAP_CACHE_VIPT 4370 /* 4371 * This page is now cache resident so it now has a page color. 4372 * Any contents have been obliterated so clear the EXEC flag. 4373 */ 4374 if (!pmap_is_page_colored_p(pg)) { 4375 PMAPCOUNT(vac_color_new); 4376 pg->mdpage.pvh_attrs |= PVF_COLORED; 4377 } 4378 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4379 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4380 PMAPCOUNT(exec_discarded_zero); 4381 } 4382 pg->mdpage.pvh_attrs |= PVF_DIRTY; 4383 #endif 4384 } 4385 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4386 4387 #if ARM_MMU_XSCALE == 1 4388 void 4389 pmap_zero_page_xscale(paddr_t phys) 4390 { 4391 #ifdef DEBUG 4392 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4393 4394 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4395 panic("pmap_zero_page: page has mappings"); 4396 #endif 4397 4398 KDASSERT((phys & PGOFSET) == 0); 4399 4400 /* 4401 * Hook in the page, zero it, and purge the cache for that 4402 * zeroed page. Invalidate the TLB as needed. 4403 */ 4404 *cdst_pte = L2_S_PROTO | phys | 4405 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4406 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4407 PTE_SYNC(cdst_pte); 4408 cpu_tlb_flushD_SE(cdstp); 4409 cpu_cpwait(); 4410 bzero_page(cdstp); 4411 xscale_cache_clean_minidata(); 4412 } 4413 #endif /* ARM_MMU_XSCALE == 1 */ 4414 4415 /* pmap_pageidlezero() 4416 * 4417 * The same as above, except that we assume that the page is not 4418 * mapped. This means we never have to flush the cache first. Called 4419 * from the idle loop. 4420 */ 4421 bool 4422 pmap_pageidlezero(paddr_t phys) 4423 { 4424 unsigned int i; 4425 int *ptr; 4426 bool rv = true; 4427 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4428 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4429 #endif 4430 #ifdef PMAP_CACHE_VIPT 4431 /* Choose the last page color it had, if any */ 4432 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4433 #else 4434 const vsize_t va_offset = 0; 4435 #endif 4436 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4437 4438 4439 #ifdef DEBUG 4440 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4441 panic("pmap_pageidlezero: page has mappings"); 4442 #endif 4443 4444 KDASSERT((phys & PGOFSET) == 0); 4445 4446 /* 4447 * Hook in the page, zero it, and purge the cache for that 4448 * zeroed page. Invalidate the TLB as needed. 4449 */ 4450 *ptep = L2_S_PROTO | phys | 4451 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4452 PTE_SYNC(ptep); 4453 cpu_tlb_flushD_SE(cdstp + va_offset); 4454 cpu_cpwait(); 4455 4456 for (i = 0, ptr = (int *)(cdstp + va_offset); 4457 i < (PAGE_SIZE / sizeof(int)); i++) { 4458 if (sched_curcpu_runnable_p() != 0) { 4459 /* 4460 * A process has become ready. Abort now, 4461 * so we don't keep it waiting while we 4462 * do slow memory access to finish this 4463 * page. 4464 */ 4465 rv = false; 4466 break; 4467 } 4468 *ptr++ = 0; 4469 } 4470 4471 #ifdef PMAP_CACHE_VIVT 4472 if (rv) 4473 /* 4474 * if we aborted we'll rezero this page again later so don't 4475 * purge it unless we finished it 4476 */ 4477 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4478 #elif defined(PMAP_CACHE_VIPT) 4479 /* 4480 * This page is now cache resident so it now has a page color. 4481 * Any contents have been obliterated so clear the EXEC flag. 4482 */ 4483 if (!pmap_is_page_colored_p(pg)) { 4484 PMAPCOUNT(vac_color_new); 4485 pg->mdpage.pvh_attrs |= PVF_COLORED; 4486 } 4487 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4488 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4489 PMAPCOUNT(exec_discarded_zero); 4490 } 4491 #endif 4492 /* 4493 * Unmap the page. 4494 */ 4495 *ptep = 0; 4496 PTE_SYNC(ptep); 4497 cpu_tlb_flushD_SE(cdstp + va_offset); 4498 4499 return (rv); 4500 } 4501 4502 /* 4503 * pmap_copy_page() 4504 * 4505 * Copy one physical page into another, by mapping the pages into 4506 * hook points. The same comment regarding cachability as in 4507 * pmap_zero_page also applies here. 4508 */ 4509 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4510 void 4511 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4512 { 4513 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4514 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4515 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4516 #endif 4517 #ifdef PMAP_CACHE_VIPT 4518 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4519 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4520 #else 4521 const vsize_t src_va_offset = 0; 4522 const vsize_t dst_va_offset = 0; 4523 #endif 4524 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4525 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4526 4527 #ifdef DEBUG 4528 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4529 panic("pmap_copy_page: dst page has mappings"); 4530 #endif 4531 4532 #ifdef PMAP_CACHE_VIPT 4533 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4534 #endif 4535 KDASSERT((src & PGOFSET) == 0); 4536 KDASSERT((dst & PGOFSET) == 0); 4537 4538 /* 4539 * Clean the source page. Hold the source page's lock for 4540 * the duration of the copy so that no other mappings can 4541 * be created while we have a potentially aliased mapping. 4542 */ 4543 simple_lock(&src_pg->mdpage.pvh_slock); 4544 #ifdef PMAP_CACHE_VIVT 4545 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4546 #endif 4547 4548 /* 4549 * Map the pages into the page hook points, copy them, and purge 4550 * the cache for the appropriate page. Invalidate the TLB 4551 * as required. 4552 */ 4553 *src_ptep = L2_S_PROTO 4554 | src 4555 #ifdef PMAP_CACHE_VIPT 4556 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4557 #endif 4558 #ifdef PMAP_CACHE_VIVT 4559 | pte_l2_s_cache_mode 4560 #endif 4561 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4562 *dst_ptep = L2_S_PROTO | dst | 4563 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4564 PTE_SYNC(src_ptep); 4565 PTE_SYNC(dst_ptep); 4566 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4567 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4568 cpu_cpwait(); 4569 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4570 #ifdef PMAP_CACHE_VIVT 4571 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4572 #endif 4573 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4574 #ifdef PMAP_CACHE_VIVT 4575 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4576 #endif 4577 /* 4578 * Unmap the pages. 4579 */ 4580 *src_ptep = 0; 4581 *dst_ptep = 0; 4582 PTE_SYNC(src_ptep); 4583 PTE_SYNC(dst_ptep); 4584 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4585 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4586 #ifdef PMAP_CACHE_VIPT 4587 /* 4588 * Now that the destination page is in the cache, mark it as colored. 4589 * If this was an exec page, discard it. 4590 */ 4591 if (!pmap_is_page_colored_p(dst_pg)) { 4592 PMAPCOUNT(vac_color_new); 4593 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4594 } 4595 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4596 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4597 PMAPCOUNT(exec_discarded_copy); 4598 } 4599 dst_pg->mdpage.pvh_attrs |= PVF_DIRTY; 4600 #endif 4601 } 4602 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4603 4604 #if ARM_MMU_XSCALE == 1 4605 void 4606 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4607 { 4608 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4609 #ifdef DEBUG 4610 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4611 4612 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4613 panic("pmap_copy_page: dst page has mappings"); 4614 #endif 4615 4616 KDASSERT((src & PGOFSET) == 0); 4617 KDASSERT((dst & PGOFSET) == 0); 4618 4619 /* 4620 * Clean the source page. Hold the source page's lock for 4621 * the duration of the copy so that no other mappings can 4622 * be created while we have a potentially aliased mapping. 4623 */ 4624 simple_lock(&src_pg->mdpage.pvh_slock); 4625 #ifdef PMAP_CACHE_VIVT 4626 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4627 #endif 4628 4629 /* 4630 * Map the pages into the page hook points, copy them, and purge 4631 * the cache for the appropriate page. Invalidate the TLB 4632 * as required. 4633 */ 4634 *csrc_pte = L2_S_PROTO | src | 4635 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4636 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4637 PTE_SYNC(csrc_pte); 4638 *cdst_pte = L2_S_PROTO | dst | 4639 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4640 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4641 PTE_SYNC(cdst_pte); 4642 cpu_tlb_flushD_SE(csrcp); 4643 cpu_tlb_flushD_SE(cdstp); 4644 cpu_cpwait(); 4645 bcopy_page(csrcp, cdstp); 4646 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4647 xscale_cache_clean_minidata(); 4648 } 4649 #endif /* ARM_MMU_XSCALE == 1 */ 4650 4651 /* 4652 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4653 * 4654 * Return the start and end addresses of the kernel's virtual space. 4655 * These values are setup in pmap_bootstrap and are updated as pages 4656 * are allocated. 4657 */ 4658 void 4659 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4660 { 4661 *start = virtual_avail; 4662 *end = virtual_end; 4663 } 4664 4665 /* 4666 * Helper function for pmap_grow_l2_bucket() 4667 */ 4668 static inline int 4669 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4670 { 4671 struct l2_bucket *l2b; 4672 pt_entry_t *ptep; 4673 paddr_t pa; 4674 4675 if (uvm.page_init_done == false) { 4676 #ifdef PMAP_STEAL_MEMORY 4677 pv_addr_t pv; 4678 pmap_boot_pagealloc(PAGE_SIZE, 4679 #ifdef PMAP_CACHE_VIPT 4680 arm_cache_prefer_mask, 4681 va & arm_cache_prefer_mask, 4682 #else 4683 0, 0, 4684 #endif 4685 &pv); 4686 pa = pv.pv_pa; 4687 #else 4688 if (uvm_page_physget(&pa) == false) 4689 return (1); 4690 #endif /* PMAP_STEAL_MEMORY */ 4691 } else { 4692 struct vm_page *pg; 4693 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4694 if (pg == NULL) 4695 return (1); 4696 pa = VM_PAGE_TO_PHYS(pg); 4697 #ifdef PMAP_CACHE_VIPT 4698 /* 4699 * This new page must not have any mappings. Enter it via 4700 * pmap_kenter_pa and let that routine do the hard work. 4701 */ 4702 KASSERT(SLIST_EMPTY(&pg->mdpage.pvh_list)); 4703 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 4704 #endif 4705 } 4706 4707 if (pap) 4708 *pap = pa; 4709 4710 PMAPCOUNT(pt_mappings); 4711 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4712 KDASSERT(l2b != NULL); 4713 4714 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4715 *ptep = L2_S_PROTO | pa | cache_mode | 4716 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4717 PTE_SYNC(ptep); 4718 memset((void *)va, 0, PAGE_SIZE); 4719 return (0); 4720 } 4721 4722 /* 4723 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4724 * used by pmap_growkernel(). 4725 */ 4726 static inline struct l2_bucket * 4727 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4728 { 4729 struct l2_dtable *l2; 4730 struct l2_bucket *l2b; 4731 u_short l1idx; 4732 vaddr_t nva; 4733 4734 l1idx = L1_IDX(va); 4735 4736 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4737 /* 4738 * No mapping at this address, as there is 4739 * no entry in the L1 table. 4740 * Need to allocate a new l2_dtable. 4741 */ 4742 nva = pmap_kernel_l2dtable_kva; 4743 if ((nva & PGOFSET) == 0) { 4744 /* 4745 * Need to allocate a backing page 4746 */ 4747 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4748 return (NULL); 4749 } 4750 4751 l2 = (struct l2_dtable *)nva; 4752 nva += sizeof(struct l2_dtable); 4753 4754 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4755 /* 4756 * The new l2_dtable straddles a page boundary. 4757 * Map in another page to cover it. 4758 */ 4759 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4760 return (NULL); 4761 } 4762 4763 pmap_kernel_l2dtable_kva = nva; 4764 4765 /* 4766 * Link it into the parent pmap 4767 */ 4768 pm->pm_l2[L2_IDX(l1idx)] = l2; 4769 } 4770 4771 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4772 4773 /* 4774 * Fetch pointer to the L2 page table associated with the address. 4775 */ 4776 if (l2b->l2b_kva == NULL) { 4777 pt_entry_t *ptep; 4778 4779 /* 4780 * No L2 page table has been allocated. Chances are, this 4781 * is because we just allocated the l2_dtable, above. 4782 */ 4783 nva = pmap_kernel_l2ptp_kva; 4784 ptep = (pt_entry_t *)nva; 4785 if ((nva & PGOFSET) == 0) { 4786 /* 4787 * Need to allocate a backing page 4788 */ 4789 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4790 &pmap_kernel_l2ptp_phys)) 4791 return (NULL); 4792 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4793 } 4794 4795 l2->l2_occupancy++; 4796 l2b->l2b_kva = ptep; 4797 l2b->l2b_l1idx = l1idx; 4798 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4799 4800 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4801 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4802 } 4803 4804 return (l2b); 4805 } 4806 4807 vaddr_t 4808 pmap_growkernel(vaddr_t maxkvaddr) 4809 { 4810 pmap_t kpm = pmap_kernel(); 4811 struct l1_ttable *l1; 4812 struct l2_bucket *l2b; 4813 pd_entry_t *pl1pd; 4814 int s; 4815 4816 if (maxkvaddr <= pmap_curmaxkvaddr) 4817 goto out; /* we are OK */ 4818 4819 NPDEBUG(PDB_GROWKERN, 4820 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4821 pmap_curmaxkvaddr, maxkvaddr)); 4822 4823 KDASSERT(maxkvaddr <= virtual_end); 4824 4825 /* 4826 * whoops! we need to add kernel PTPs 4827 */ 4828 4829 s = splhigh(); /* to be safe */ 4830 mutex_enter(&kpm->pm_lock); 4831 4832 /* Map 1MB at a time */ 4833 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4834 4835 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4836 KDASSERT(l2b != NULL); 4837 4838 /* Distribute new L1 entry to all other L1s */ 4839 SLIST_FOREACH(l1, &l1_list, l1_link) { 4840 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4841 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4842 L1_C_PROTO; 4843 PTE_SYNC(pl1pd); 4844 } 4845 } 4846 4847 /* 4848 * flush out the cache, expensive but growkernel will happen so 4849 * rarely 4850 */ 4851 cpu_dcache_wbinv_all(); 4852 cpu_tlb_flushD(); 4853 cpu_cpwait(); 4854 4855 mutex_exit(&kpm->pm_lock); 4856 splx(s); 4857 4858 out: 4859 return (pmap_curmaxkvaddr); 4860 } 4861 4862 /************************ Utility routines ****************************/ 4863 4864 /* 4865 * vector_page_setprot: 4866 * 4867 * Manipulate the protection of the vector page. 4868 */ 4869 void 4870 vector_page_setprot(int prot) 4871 { 4872 struct l2_bucket *l2b; 4873 pt_entry_t *ptep; 4874 4875 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4876 KDASSERT(l2b != NULL); 4877 4878 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4879 4880 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4881 PTE_SYNC(ptep); 4882 cpu_tlb_flushD_SE(vector_page); 4883 cpu_cpwait(); 4884 } 4885 4886 /* 4887 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4888 * Returns true if the mapping exists, else false. 4889 * 4890 * NOTE: This function is only used by a couple of arm-specific modules. 4891 * It is not safe to take any pmap locks here, since we could be right 4892 * in the middle of debugging the pmap anyway... 4893 * 4894 * It is possible for this routine to return false even though a valid 4895 * mapping does exist. This is because we don't lock, so the metadata 4896 * state may be inconsistent. 4897 * 4898 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4899 * a "section" mapping. 4900 */ 4901 bool 4902 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4903 { 4904 struct l2_dtable *l2; 4905 pd_entry_t *pl1pd, l1pd; 4906 pt_entry_t *ptep; 4907 u_short l1idx; 4908 4909 if (pm->pm_l1 == NULL) 4910 return false; 4911 4912 l1idx = L1_IDX(va); 4913 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4914 l1pd = *pl1pd; 4915 4916 if (l1pte_section_p(l1pd)) { 4917 *ptp = NULL; 4918 return true; 4919 } 4920 4921 if (pm->pm_l2 == NULL) 4922 return false; 4923 4924 l2 = pm->pm_l2[L2_IDX(l1idx)]; 4925 4926 if (l2 == NULL || 4927 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 4928 return false; 4929 } 4930 4931 *ptp = &ptep[l2pte_index(va)]; 4932 return true; 4933 } 4934 4935 bool 4936 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 4937 { 4938 u_short l1idx; 4939 4940 if (pm->pm_l1 == NULL) 4941 return false; 4942 4943 l1idx = L1_IDX(va); 4944 *pdp = &pm->pm_l1->l1_kva[l1idx]; 4945 4946 return true; 4947 } 4948 4949 /************************ Bootstrapping routines ****************************/ 4950 4951 static void 4952 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 4953 { 4954 int i; 4955 4956 l1->l1_kva = l1pt; 4957 l1->l1_domain_use_count = 0; 4958 l1->l1_domain_first = 0; 4959 4960 for (i = 0; i < PMAP_DOMAINS; i++) 4961 l1->l1_domain_free[i] = i + 1; 4962 4963 /* 4964 * Copy the kernel's L1 entries to each new L1. 4965 */ 4966 if (pmap_initialized) 4967 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 4968 4969 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 4970 &l1->l1_physaddr) == false) 4971 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 4972 4973 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 4974 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 4975 } 4976 4977 /* 4978 * pmap_bootstrap() is called from the board-specific initarm() routine 4979 * once the kernel L1/L2 descriptors tables have been set up. 4980 * 4981 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 4982 * spread over a number of disparate files/functions. 4983 * 4984 * We are passed the following parameters 4985 * - kernel_l1pt 4986 * This is a pointer to the base of the kernel's L1 translation table. 4987 * - vstart 4988 * 1MB-aligned start of managed kernel virtual memory. 4989 * - vend 4990 * 1MB-aligned end of managed kernel virtual memory. 4991 * 4992 * We use the first parameter to build the metadata (struct l1_ttable and 4993 * struct l2_dtable) necessary to track kernel mappings. 4994 */ 4995 #define PMAP_STATIC_L2_SIZE 16 4996 void 4997 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 4998 { 4999 static struct l1_ttable static_l1; 5000 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5001 struct l1_ttable *l1 = &static_l1; 5002 struct l2_dtable *l2; 5003 struct l2_bucket *l2b; 5004 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5005 pmap_t pm = pmap_kernel(); 5006 pd_entry_t pde; 5007 pt_entry_t *ptep; 5008 paddr_t pa; 5009 vaddr_t va; 5010 vsize_t size; 5011 int nptes, l1idx, l2idx, l2next = 0; 5012 5013 /* 5014 * Initialise the kernel pmap object 5015 */ 5016 pm->pm_l1 = l1; 5017 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5018 pm->pm_activated = true; 5019 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5020 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5021 5022 /* 5023 * Scan the L1 translation table created by initarm() and create 5024 * the required metadata for all valid mappings found in it. 5025 */ 5026 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5027 pde = l1pt[l1idx]; 5028 5029 /* 5030 * We're only interested in Coarse mappings. 5031 * pmap_extract() can deal with section mappings without 5032 * recourse to checking L2 metadata. 5033 */ 5034 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5035 continue; 5036 5037 /* 5038 * Lookup the KVA of this L2 descriptor table 5039 */ 5040 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5041 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5042 if (ptep == NULL) { 5043 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5044 (u_int)l1idx << L1_S_SHIFT, pa); 5045 } 5046 5047 /* 5048 * Fetch the associated L2 metadata structure. 5049 * Allocate a new one if necessary. 5050 */ 5051 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5052 if (l2next == PMAP_STATIC_L2_SIZE) 5053 panic("pmap_bootstrap: out of static L2s"); 5054 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5055 } 5056 5057 /* 5058 * One more L1 slot tracked... 5059 */ 5060 l2->l2_occupancy++; 5061 5062 /* 5063 * Fill in the details of the L2 descriptor in the 5064 * appropriate bucket. 5065 */ 5066 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5067 l2b->l2b_kva = ptep; 5068 l2b->l2b_phys = pa; 5069 l2b->l2b_l1idx = l1idx; 5070 5071 /* 5072 * Establish an initial occupancy count for this descriptor 5073 */ 5074 for (l2idx = 0; 5075 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5076 l2idx++) { 5077 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5078 l2b->l2b_occupancy++; 5079 } 5080 } 5081 5082 /* 5083 * Make sure the descriptor itself has the correct cache mode. 5084 * If not, fix it, but whine about the problem. Port-meisters 5085 * should consider this a clue to fix up their initarm() 5086 * function. :) 5087 */ 5088 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5089 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5090 "L2 pte @ %p\n", ptep); 5091 } 5092 } 5093 5094 /* 5095 * Ensure the primary (kernel) L1 has the correct cache mode for 5096 * a page table. Bitch if it is not correctly set. 5097 */ 5098 for (va = (vaddr_t)l1pt; 5099 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5100 if (pmap_set_pt_cache_mode(l1pt, va)) 5101 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5102 "primary L1 @ 0x%lx\n", va); 5103 } 5104 5105 cpu_dcache_wbinv_all(); 5106 cpu_tlb_flushID(); 5107 cpu_cpwait(); 5108 5109 /* 5110 * now we allocate the "special" VAs which are used for tmp mappings 5111 * by the pmap (and other modules). we allocate the VAs by advancing 5112 * virtual_avail (note that there are no pages mapped at these VAs). 5113 * 5114 * Managed KVM space start from wherever initarm() tells us. 5115 */ 5116 virtual_avail = vstart; 5117 virtual_end = vend; 5118 5119 #ifdef PMAP_CACHE_VIPT 5120 /* 5121 * If we have a VIPT cache, we need one page/pte per possible alias 5122 * page so we won't violate cache aliasing rules. 5123 */ 5124 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5125 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5126 #else 5127 nptes = 1; 5128 #endif 5129 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5130 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5131 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5132 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5133 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5134 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5135 (void *)&msgbufaddr, NULL); 5136 5137 /* 5138 * Allocate a range of kernel virtual address space to be used 5139 * for L2 descriptor tables and metadata allocation in 5140 * pmap_growkernel(). 5141 */ 5142 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5143 pmap_alloc_specials(&virtual_avail, 5144 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5145 &pmap_kernel_l2ptp_kva, NULL); 5146 5147 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5148 pmap_alloc_specials(&virtual_avail, 5149 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5150 &pmap_kernel_l2dtable_kva, NULL); 5151 5152 /* 5153 * init the static-global locks and global pmap list. 5154 */ 5155 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5156 5157 /* 5158 * We can now initialise the first L1's metadata. 5159 */ 5160 SLIST_INIT(&l1_list); 5161 TAILQ_INIT(&l1_lru_list); 5162 simple_lock_init(&l1_lru_lock); 5163 pmap_init_l1(l1, l1pt); 5164 5165 /* Set up vector page L1 details, if necessary */ 5166 if (vector_page < KERNEL_BASE) { 5167 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5168 l2b = pmap_get_l2_bucket(pm, vector_page); 5169 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5170 L1_C_DOM(pm->pm_domain); 5171 } else 5172 pm->pm_pl1vec = NULL; 5173 5174 /* 5175 * Initialize the pmap cache 5176 */ 5177 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5178 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5179 LIST_INIT(&pmap_pmaps); 5180 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5181 5182 /* 5183 * Initialize the pv pool. 5184 */ 5185 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5186 &pmap_bootstrap_pv_allocator, IPL_NONE); 5187 5188 /* 5189 * Initialize the L2 dtable pool and cache. 5190 */ 5191 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5192 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5193 5194 /* 5195 * Initialise the L2 descriptor table pool and cache 5196 */ 5197 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5198 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5199 pmap_l2ptp_ctor, NULL, NULL); 5200 5201 cpu_dcache_wbinv_all(); 5202 } 5203 5204 static int 5205 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5206 { 5207 pd_entry_t *pdep, pde; 5208 pt_entry_t *ptep, pte; 5209 vaddr_t pa; 5210 int rv = 0; 5211 5212 /* 5213 * Make sure the descriptor itself has the correct cache mode 5214 */ 5215 pdep = &kl1[L1_IDX(va)]; 5216 pde = *pdep; 5217 5218 if (l1pte_section_p(pde)) { 5219 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5220 *pdep = (pde & ~L1_S_CACHE_MASK) | 5221 pte_l1_s_cache_mode_pt; 5222 PTE_SYNC(pdep); 5223 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5224 rv = 1; 5225 } 5226 } else { 5227 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5228 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5229 if (ptep == NULL) 5230 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5231 5232 ptep = &ptep[l2pte_index(va)]; 5233 pte = *ptep; 5234 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5235 *ptep = (pte & ~L2_S_CACHE_MASK) | 5236 pte_l2_s_cache_mode_pt; 5237 PTE_SYNC(ptep); 5238 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5239 rv = 1; 5240 } 5241 } 5242 5243 return (rv); 5244 } 5245 5246 static void 5247 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5248 { 5249 vaddr_t va = *availp; 5250 struct l2_bucket *l2b; 5251 5252 if (ptep) { 5253 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5254 if (l2b == NULL) 5255 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5256 5257 if (ptep) 5258 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5259 } 5260 5261 *vap = va; 5262 *availp = va + (PAGE_SIZE * pages); 5263 } 5264 5265 void 5266 pmap_init(void) 5267 { 5268 extern int physmem; 5269 5270 /* 5271 * Set the available memory vars - These do not map to real memory 5272 * addresses and cannot as the physical memory is fragmented. 5273 * They are used by ps for %mem calculations. 5274 * One could argue whether this should be the entire memory or just 5275 * the memory that is useable in a user process. 5276 */ 5277 avail_start = 0; 5278 avail_end = physmem * PAGE_SIZE; 5279 5280 /* 5281 * Now we need to free enough pv_entry structures to allow us to get 5282 * the kmem_map/kmem_object allocated and inited (done after this 5283 * function is finished). to do this we allocate one bootstrap page out 5284 * of kernel_map and use it to provide an initial pool of pv_entry 5285 * structures. we never free this page. 5286 */ 5287 pool_setlowat(&pmap_pv_pool, 5288 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5289 5290 pmap_initialized = true; 5291 5292 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5293 } 5294 5295 static vaddr_t last_bootstrap_page = 0; 5296 static void *free_bootstrap_pages = NULL; 5297 5298 static void * 5299 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5300 { 5301 extern void *pool_page_alloc(struct pool *, int); 5302 vaddr_t new_page; 5303 void *rv; 5304 5305 if (pmap_initialized) 5306 return (pool_page_alloc(pp, flags)); 5307 5308 if (free_bootstrap_pages) { 5309 rv = free_bootstrap_pages; 5310 free_bootstrap_pages = *((void **)rv); 5311 return (rv); 5312 } 5313 5314 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5315 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5316 5317 KASSERT(new_page > last_bootstrap_page); 5318 last_bootstrap_page = new_page; 5319 return ((void *)new_page); 5320 } 5321 5322 static void 5323 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5324 { 5325 extern void pool_page_free(struct pool *, void *); 5326 5327 if ((vaddr_t)v <= last_bootstrap_page) { 5328 *((void **)v) = free_bootstrap_pages; 5329 free_bootstrap_pages = v; 5330 return; 5331 } 5332 5333 if (pmap_initialized) { 5334 pool_page_free(pp, v); 5335 return; 5336 } 5337 } 5338 5339 /* 5340 * pmap_postinit() 5341 * 5342 * This routine is called after the vm and kmem subsystems have been 5343 * initialised. This allows the pmap code to perform any initialisation 5344 * that can only be done one the memory allocation is in place. 5345 */ 5346 void 5347 pmap_postinit(void) 5348 { 5349 extern paddr_t physical_start, physical_end; 5350 struct l2_bucket *l2b; 5351 struct l1_ttable *l1; 5352 struct pglist plist; 5353 struct vm_page *m; 5354 pd_entry_t *pl1pt; 5355 pt_entry_t *ptep, pte; 5356 vaddr_t va, eva; 5357 u_int loop, needed; 5358 int error; 5359 5360 pool_cache_setlowat(&pmap_l2ptp_cache, 5361 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5362 pool_cache_setlowat(&pmap_l2dtable_cache, 5363 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5364 5365 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5366 needed -= 1; 5367 5368 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5369 5370 for (loop = 0; loop < needed; loop++, l1++) { 5371 /* Allocate a L1 page table */ 5372 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5373 if (va == 0) 5374 panic("Cannot allocate L1 KVM"); 5375 5376 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5377 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5378 if (error) 5379 panic("Cannot allocate L1 physical pages"); 5380 5381 m = TAILQ_FIRST(&plist); 5382 eva = va + L1_TABLE_SIZE; 5383 pl1pt = (pd_entry_t *)va; 5384 5385 while (m && va < eva) { 5386 paddr_t pa = VM_PAGE_TO_PHYS(m); 5387 5388 pmap_kenter_pa(va, pa, 5389 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 5390 5391 /* 5392 * Make sure the L1 descriptor table is mapped 5393 * with the cache-mode set to write-through. 5394 */ 5395 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5396 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5397 pte = *ptep; 5398 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5399 *ptep = pte; 5400 PTE_SYNC(ptep); 5401 cpu_tlb_flushD_SE(va); 5402 5403 va += PAGE_SIZE; 5404 m = TAILQ_NEXT(m, pageq.queue); 5405 } 5406 5407 #ifdef DIAGNOSTIC 5408 if (m) 5409 panic("pmap_alloc_l1pt: pglist not empty"); 5410 #endif /* DIAGNOSTIC */ 5411 5412 pmap_init_l1(l1, pl1pt); 5413 } 5414 5415 #ifdef DEBUG 5416 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5417 needed); 5418 #endif 5419 } 5420 5421 /* 5422 * Note that the following routines are used by board-specific initialisation 5423 * code to configure the initial kernel page tables. 5424 * 5425 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5426 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5427 * behaviour of the old pmap, and provides an easy migration path for 5428 * initial bring-up of the new pmap on existing ports. Fortunately, 5429 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5430 * will be deprecated. 5431 * 5432 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5433 * tables. 5434 */ 5435 5436 /* 5437 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5438 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5439 * find them as necessary. 5440 * 5441 * Note that the data on this list MUST remain valid after initarm() returns, 5442 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5443 */ 5444 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5445 5446 static vaddr_t 5447 kernel_pt_lookup(paddr_t pa) 5448 { 5449 pv_addr_t *pv; 5450 5451 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5452 #ifndef ARM32_NEW_VM_LAYOUT 5453 if (pv->pv_pa == (pa & ~PGOFSET)) 5454 return (pv->pv_va | (pa & PGOFSET)); 5455 #else 5456 if (pv->pv_pa == pa) 5457 return (pv->pv_va); 5458 #endif 5459 } 5460 return (0); 5461 } 5462 5463 /* 5464 * pmap_map_section: 5465 * 5466 * Create a single section mapping. 5467 */ 5468 void 5469 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5470 { 5471 pd_entry_t *pde = (pd_entry_t *) l1pt; 5472 pd_entry_t fl; 5473 5474 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5475 5476 switch (cache) { 5477 case PTE_NOCACHE: 5478 default: 5479 fl = 0; 5480 break; 5481 5482 case PTE_CACHE: 5483 fl = pte_l1_s_cache_mode; 5484 break; 5485 5486 case PTE_PAGETABLE: 5487 fl = pte_l1_s_cache_mode_pt; 5488 break; 5489 } 5490 5491 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5492 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5493 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5494 } 5495 5496 /* 5497 * pmap_map_entry: 5498 * 5499 * Create a single page mapping. 5500 */ 5501 void 5502 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5503 { 5504 pd_entry_t *pde = (pd_entry_t *) l1pt; 5505 pt_entry_t fl; 5506 pt_entry_t *pte; 5507 5508 KASSERT(((va | pa) & PGOFSET) == 0); 5509 5510 switch (cache) { 5511 case PTE_NOCACHE: 5512 default: 5513 fl = 0; 5514 break; 5515 5516 case PTE_CACHE: 5517 fl = pte_l2_s_cache_mode; 5518 break; 5519 5520 case PTE_PAGETABLE: 5521 fl = pte_l2_s_cache_mode_pt; 5522 break; 5523 } 5524 5525 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5526 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5527 5528 #ifndef ARM32_NEW_VM_LAYOUT 5529 pte = (pt_entry_t *) 5530 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5531 #else 5532 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5533 #endif 5534 if (pte == NULL) 5535 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5536 5537 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5538 #ifndef ARM32_NEW_VM_LAYOUT 5539 pte += (va >> PGSHIFT) & 0x3ff; 5540 #else 5541 pte += l2pte_index(va); 5542 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5543 #endif 5544 *pte = fl; 5545 PTE_SYNC(pte); 5546 } 5547 5548 /* 5549 * pmap_link_l2pt: 5550 * 5551 * Link the L2 page table specified by "l2pv" into the L1 5552 * page table at the slot for "va". 5553 */ 5554 void 5555 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5556 { 5557 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5558 u_int slot = va >> L1_S_SHIFT; 5559 5560 #ifndef ARM32_NEW_VM_LAYOUT 5561 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5562 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5563 #endif 5564 5565 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5566 5567 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5568 #ifdef ARM32_NEW_VM_LAYOUT 5569 PTE_SYNC(&pde[slot]); 5570 #else 5571 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5572 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5573 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5574 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5575 #endif 5576 5577 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5578 } 5579 5580 /* 5581 * pmap_map_chunk: 5582 * 5583 * Map a chunk of memory using the most efficient mappings 5584 * possible (section, large page, small page) into the 5585 * provided L1 and L2 tables at the specified virtual address. 5586 */ 5587 vsize_t 5588 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5589 int prot, int cache) 5590 { 5591 pd_entry_t *pde = (pd_entry_t *) l1pt; 5592 pt_entry_t *pte, f1, f2s, f2l; 5593 vsize_t resid; 5594 int i; 5595 5596 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5597 5598 if (l1pt == 0) 5599 panic("pmap_map_chunk: no L1 table provided"); 5600 5601 #ifdef VERBOSE_INIT_ARM 5602 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5603 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5604 #endif 5605 5606 switch (cache) { 5607 case PTE_NOCACHE: 5608 default: 5609 f1 = 0; 5610 f2l = 0; 5611 f2s = 0; 5612 break; 5613 5614 case PTE_CACHE: 5615 f1 = pte_l1_s_cache_mode; 5616 f2l = pte_l2_l_cache_mode; 5617 f2s = pte_l2_s_cache_mode; 5618 break; 5619 5620 case PTE_PAGETABLE: 5621 f1 = pte_l1_s_cache_mode_pt; 5622 f2l = pte_l2_l_cache_mode_pt; 5623 f2s = pte_l2_s_cache_mode_pt; 5624 break; 5625 } 5626 5627 size = resid; 5628 5629 while (resid > 0) { 5630 /* See if we can use a section mapping. */ 5631 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5632 #ifdef VERBOSE_INIT_ARM 5633 printf("S"); 5634 #endif 5635 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5636 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5637 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5638 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5639 va += L1_S_SIZE; 5640 pa += L1_S_SIZE; 5641 resid -= L1_S_SIZE; 5642 continue; 5643 } 5644 5645 /* 5646 * Ok, we're going to use an L2 table. Make sure 5647 * one is actually in the corresponding L1 slot 5648 * for the current VA. 5649 */ 5650 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5651 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5652 5653 #ifndef ARM32_NEW_VM_LAYOUT 5654 pte = (pt_entry_t *) 5655 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5656 #else 5657 pte = (pt_entry_t *) kernel_pt_lookup( 5658 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5659 #endif 5660 if (pte == NULL) 5661 panic("pmap_map_chunk: can't find L2 table for VA" 5662 "0x%08lx", va); 5663 5664 /* See if we can use a L2 large page mapping. */ 5665 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5666 #ifdef VERBOSE_INIT_ARM 5667 printf("L"); 5668 #endif 5669 for (i = 0; i < 16; i++) { 5670 #ifndef ARM32_NEW_VM_LAYOUT 5671 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5672 L2_L_PROTO | pa | 5673 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5674 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5675 #else 5676 pte[l2pte_index(va) + i] = 5677 L2_L_PROTO | pa | 5678 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5679 PTE_SYNC(&pte[l2pte_index(va) + i]); 5680 #endif 5681 } 5682 va += L2_L_SIZE; 5683 pa += L2_L_SIZE; 5684 resid -= L2_L_SIZE; 5685 continue; 5686 } 5687 5688 /* Use a small page mapping. */ 5689 #ifdef VERBOSE_INIT_ARM 5690 printf("P"); 5691 #endif 5692 #ifndef ARM32_NEW_VM_LAYOUT 5693 pte[(va >> PGSHIFT) & 0x3ff] = 5694 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5695 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5696 #else 5697 pte[l2pte_index(va)] = 5698 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5699 PTE_SYNC(&pte[l2pte_index(va)]); 5700 #endif 5701 va += PAGE_SIZE; 5702 pa += PAGE_SIZE; 5703 resid -= PAGE_SIZE; 5704 } 5705 #ifdef VERBOSE_INIT_ARM 5706 printf("\n"); 5707 #endif 5708 return (size); 5709 } 5710 5711 /********************** Static device map routines ***************************/ 5712 5713 static const struct pmap_devmap *pmap_devmap_table; 5714 5715 /* 5716 * Register the devmap table. This is provided in case early console 5717 * initialization needs to register mappings created by bootstrap code 5718 * before pmap_devmap_bootstrap() is called. 5719 */ 5720 void 5721 pmap_devmap_register(const struct pmap_devmap *table) 5722 { 5723 5724 pmap_devmap_table = table; 5725 } 5726 5727 /* 5728 * Map all of the static regions in the devmap table, and remember 5729 * the devmap table so other parts of the kernel can look up entries 5730 * later. 5731 */ 5732 void 5733 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5734 { 5735 int i; 5736 5737 pmap_devmap_table = table; 5738 5739 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5740 #ifdef VERBOSE_INIT_ARM 5741 printf("devmap: %08lx -> %08lx @ %08lx\n", 5742 pmap_devmap_table[i].pd_pa, 5743 pmap_devmap_table[i].pd_pa + 5744 pmap_devmap_table[i].pd_size - 1, 5745 pmap_devmap_table[i].pd_va); 5746 #endif 5747 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5748 pmap_devmap_table[i].pd_pa, 5749 pmap_devmap_table[i].pd_size, 5750 pmap_devmap_table[i].pd_prot, 5751 pmap_devmap_table[i].pd_cache); 5752 } 5753 } 5754 5755 const struct pmap_devmap * 5756 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5757 { 5758 uint64_t endpa; 5759 int i; 5760 5761 if (pmap_devmap_table == NULL) 5762 return (NULL); 5763 5764 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5765 5766 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5767 if (pa >= pmap_devmap_table[i].pd_pa && 5768 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5769 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5770 return (&pmap_devmap_table[i]); 5771 } 5772 5773 return (NULL); 5774 } 5775 5776 const struct pmap_devmap * 5777 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5778 { 5779 int i; 5780 5781 if (pmap_devmap_table == NULL) 5782 return (NULL); 5783 5784 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5785 if (va >= pmap_devmap_table[i].pd_va && 5786 va + size - 1 <= pmap_devmap_table[i].pd_va + 5787 pmap_devmap_table[i].pd_size - 1) 5788 return (&pmap_devmap_table[i]); 5789 } 5790 5791 return (NULL); 5792 } 5793 5794 /********************** PTE initialization routines **************************/ 5795 5796 /* 5797 * These routines are called when the CPU type is identified to set up 5798 * the PTE prototypes, cache modes, etc. 5799 * 5800 * The variables are always here, just in case LKMs need to reference 5801 * them (though, they shouldn't). 5802 */ 5803 5804 pt_entry_t pte_l1_s_cache_mode; 5805 pt_entry_t pte_l1_s_cache_mode_pt; 5806 pt_entry_t pte_l1_s_cache_mask; 5807 5808 pt_entry_t pte_l2_l_cache_mode; 5809 pt_entry_t pte_l2_l_cache_mode_pt; 5810 pt_entry_t pte_l2_l_cache_mask; 5811 5812 pt_entry_t pte_l2_s_cache_mode; 5813 pt_entry_t pte_l2_s_cache_mode_pt; 5814 pt_entry_t pte_l2_s_cache_mask; 5815 5816 pt_entry_t pte_l2_s_prot_u; 5817 pt_entry_t pte_l2_s_prot_w; 5818 pt_entry_t pte_l2_s_prot_mask; 5819 5820 pt_entry_t pte_l1_s_proto; 5821 pt_entry_t pte_l1_c_proto; 5822 pt_entry_t pte_l2_s_proto; 5823 5824 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5825 void (*pmap_zero_page_func)(paddr_t); 5826 5827 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5828 void 5829 pmap_pte_init_generic(void) 5830 { 5831 5832 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5833 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5834 5835 pte_l2_l_cache_mode = L2_B|L2_C; 5836 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5837 5838 pte_l2_s_cache_mode = L2_B|L2_C; 5839 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5840 5841 /* 5842 * If we have a write-through cache, set B and C. If 5843 * we have a write-back cache, then we assume setting 5844 * only C will make those pages write-through. 5845 */ 5846 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5847 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5848 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5849 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5850 } else { 5851 #if ARM_MMU_V6 > 1 5852 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5853 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5854 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5855 #else 5856 pte_l1_s_cache_mode_pt = L1_S_C; 5857 pte_l2_l_cache_mode_pt = L2_C; 5858 pte_l2_s_cache_mode_pt = L2_C; 5859 #endif 5860 } 5861 5862 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5863 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5864 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5865 5866 pte_l1_s_proto = L1_S_PROTO_generic; 5867 pte_l1_c_proto = L1_C_PROTO_generic; 5868 pte_l2_s_proto = L2_S_PROTO_generic; 5869 5870 pmap_copy_page_func = pmap_copy_page_generic; 5871 pmap_zero_page_func = pmap_zero_page_generic; 5872 } 5873 5874 #if defined(CPU_ARM8) 5875 void 5876 pmap_pte_init_arm8(void) 5877 { 5878 5879 /* 5880 * ARM8 is compatible with generic, but we need to use 5881 * the page tables uncached. 5882 */ 5883 pmap_pte_init_generic(); 5884 5885 pte_l1_s_cache_mode_pt = 0; 5886 pte_l2_l_cache_mode_pt = 0; 5887 pte_l2_s_cache_mode_pt = 0; 5888 } 5889 #endif /* CPU_ARM8 */ 5890 5891 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5892 void 5893 pmap_pte_init_arm9(void) 5894 { 5895 5896 /* 5897 * ARM9 is compatible with generic, but we want to use 5898 * write-through caching for now. 5899 */ 5900 pmap_pte_init_generic(); 5901 5902 pte_l1_s_cache_mode = L1_S_C; 5903 pte_l2_l_cache_mode = L2_C; 5904 pte_l2_s_cache_mode = L2_C; 5905 5906 pte_l1_s_cache_mode_pt = L1_S_C; 5907 pte_l2_l_cache_mode_pt = L2_C; 5908 pte_l2_s_cache_mode_pt = L2_C; 5909 } 5910 #endif /* CPU_ARM9 */ 5911 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5912 5913 #if defined(CPU_ARM10) 5914 void 5915 pmap_pte_init_arm10(void) 5916 { 5917 5918 /* 5919 * ARM10 is compatible with generic, but we want to use 5920 * write-through caching for now. 5921 */ 5922 pmap_pte_init_generic(); 5923 5924 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 5925 pte_l2_l_cache_mode = L2_B | L2_C; 5926 pte_l2_s_cache_mode = L2_B | L2_C; 5927 5928 pte_l1_s_cache_mode_pt = L1_S_C; 5929 pte_l2_l_cache_mode_pt = L2_C; 5930 pte_l2_s_cache_mode_pt = L2_C; 5931 5932 } 5933 #endif /* CPU_ARM10 */ 5934 5935 #if ARM_MMU_SA1 == 1 5936 void 5937 pmap_pte_init_sa1(void) 5938 { 5939 5940 /* 5941 * The StrongARM SA-1 cache does not have a write-through 5942 * mode. So, do the generic initialization, then reset 5943 * the page table cache mode to B=1,C=1, and note that 5944 * the PTEs need to be sync'd. 5945 */ 5946 pmap_pte_init_generic(); 5947 5948 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5949 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5950 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5951 5952 pmap_needs_pte_sync = 1; 5953 } 5954 #endif /* ARM_MMU_SA1 == 1*/ 5955 5956 #if ARM_MMU_XSCALE == 1 5957 #if (ARM_NMMUS > 1) 5958 static u_int xscale_use_minidata; 5959 #endif 5960 5961 void 5962 pmap_pte_init_xscale(void) 5963 { 5964 uint32_t auxctl; 5965 int write_through = 0; 5966 5967 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5968 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 5969 5970 pte_l2_l_cache_mode = L2_B|L2_C; 5971 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 5972 5973 pte_l2_s_cache_mode = L2_B|L2_C; 5974 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 5975 5976 pte_l1_s_cache_mode_pt = L1_S_C; 5977 pte_l2_l_cache_mode_pt = L2_C; 5978 pte_l2_s_cache_mode_pt = L2_C; 5979 5980 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 5981 /* 5982 * The XScale core has an enhanced mode where writes that 5983 * miss the cache cause a cache line to be allocated. This 5984 * is significantly faster than the traditional, write-through 5985 * behavior of this case. 5986 */ 5987 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 5988 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 5989 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 5990 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 5991 5992 #ifdef XSCALE_CACHE_WRITE_THROUGH 5993 /* 5994 * Some versions of the XScale core have various bugs in 5995 * their cache units, the work-around for which is to run 5996 * the cache in write-through mode. Unfortunately, this 5997 * has a major (negative) impact on performance. So, we 5998 * go ahead and run fast-and-loose, in the hopes that we 5999 * don't line up the planets in a way that will trip the 6000 * bugs. 6001 * 6002 * However, we give you the option to be slow-but-correct. 6003 */ 6004 write_through = 1; 6005 #elif defined(XSCALE_CACHE_WRITE_BACK) 6006 /* force write back cache mode */ 6007 write_through = 0; 6008 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6009 /* 6010 * Intel PXA2[15]0 processors are known to have a bug in 6011 * write-back cache on revision 4 and earlier (stepping 6012 * A[01] and B[012]). Fixed for C0 and later. 6013 */ 6014 { 6015 uint32_t id, type; 6016 6017 id = cpufunc_id(); 6018 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6019 6020 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6021 if ((id & CPU_ID_REVISION_MASK) < 5) { 6022 /* write through for stepping A0-1 and B0-2 */ 6023 write_through = 1; 6024 } 6025 } 6026 } 6027 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6028 6029 if (write_through) { 6030 pte_l1_s_cache_mode = L1_S_C; 6031 pte_l2_l_cache_mode = L2_C; 6032 pte_l2_s_cache_mode = L2_C; 6033 } 6034 6035 #if (ARM_NMMUS > 1) 6036 xscale_use_minidata = 1; 6037 #endif 6038 6039 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6040 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6041 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6042 6043 pte_l1_s_proto = L1_S_PROTO_xscale; 6044 pte_l1_c_proto = L1_C_PROTO_xscale; 6045 pte_l2_s_proto = L2_S_PROTO_xscale; 6046 6047 pmap_copy_page_func = pmap_copy_page_xscale; 6048 pmap_zero_page_func = pmap_zero_page_xscale; 6049 6050 /* 6051 * Disable ECC protection of page table access, for now. 6052 */ 6053 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6054 auxctl &= ~XSCALE_AUXCTL_P; 6055 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6056 } 6057 6058 /* 6059 * xscale_setup_minidata: 6060 * 6061 * Set up the mini-data cache clean area. We require the 6062 * caller to allocate the right amount of physically and 6063 * virtually contiguous space. 6064 */ 6065 void 6066 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6067 { 6068 extern vaddr_t xscale_minidata_clean_addr; 6069 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6070 pd_entry_t *pde = (pd_entry_t *) l1pt; 6071 pt_entry_t *pte; 6072 vsize_t size; 6073 uint32_t auxctl; 6074 6075 xscale_minidata_clean_addr = va; 6076 6077 /* Round it to page size. */ 6078 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6079 6080 for (; size != 0; 6081 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6082 #ifndef ARM32_NEW_VM_LAYOUT 6083 pte = (pt_entry_t *) 6084 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6085 #else 6086 pte = (pt_entry_t *) kernel_pt_lookup( 6087 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6088 #endif 6089 if (pte == NULL) 6090 panic("xscale_setup_minidata: can't find L2 table for " 6091 "VA 0x%08lx", va); 6092 #ifndef ARM32_NEW_VM_LAYOUT 6093 pte[(va >> PGSHIFT) & 0x3ff] = 6094 #else 6095 pte[l2pte_index(va)] = 6096 #endif 6097 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6098 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6099 } 6100 6101 /* 6102 * Configure the mini-data cache for write-back with 6103 * read/write-allocate. 6104 * 6105 * NOTE: In order to reconfigure the mini-data cache, we must 6106 * make sure it contains no valid data! In order to do that, 6107 * we must issue a global data cache invalidate command! 6108 * 6109 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6110 * THIS IS VERY IMPORTANT! 6111 */ 6112 6113 /* Invalidate data and mini-data. */ 6114 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6115 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6116 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6117 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6118 } 6119 6120 /* 6121 * Change the PTEs for the specified kernel mappings such that they 6122 * will use the mini data cache instead of the main data cache. 6123 */ 6124 void 6125 pmap_uarea(vaddr_t va) 6126 { 6127 struct l2_bucket *l2b; 6128 pt_entry_t *ptep, *sptep, pte; 6129 vaddr_t next_bucket, eva; 6130 6131 #if (ARM_NMMUS > 1) 6132 if (xscale_use_minidata == 0) 6133 return; 6134 #endif 6135 6136 eva = va + USPACE; 6137 6138 while (va < eva) { 6139 next_bucket = L2_NEXT_BUCKET(va); 6140 if (next_bucket > eva) 6141 next_bucket = eva; 6142 6143 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6144 KDASSERT(l2b != NULL); 6145 6146 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6147 6148 while (va < next_bucket) { 6149 pte = *ptep; 6150 if (!l2pte_minidata(pte)) { 6151 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6152 cpu_tlb_flushD_SE(va); 6153 *ptep = pte & ~L2_B; 6154 } 6155 ptep++; 6156 va += PAGE_SIZE; 6157 } 6158 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6159 } 6160 cpu_cpwait(); 6161 } 6162 #endif /* ARM_MMU_XSCALE == 1 */ 6163 6164 /* 6165 * return the PA of the current L1 table, for use when handling a crash dump 6166 */ 6167 uint32_t pmap_kernel_L1_addr() 6168 { 6169 return pmap_kernel()->pm_l1->l1_physaddr; 6170 } 6171 6172 #if defined(DDB) 6173 /* 6174 * A couple of ddb-callable functions for dumping pmaps 6175 */ 6176 void pmap_dump_all(void); 6177 void pmap_dump(pmap_t); 6178 6179 void 6180 pmap_dump_all(void) 6181 { 6182 pmap_t pm; 6183 6184 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6185 if (pm == pmap_kernel()) 6186 continue; 6187 pmap_dump(pm); 6188 printf("\n"); 6189 } 6190 } 6191 6192 static pt_entry_t ncptes[64]; 6193 static void pmap_dump_ncpg(pmap_t); 6194 6195 void 6196 pmap_dump(pmap_t pm) 6197 { 6198 struct l2_dtable *l2; 6199 struct l2_bucket *l2b; 6200 pt_entry_t *ptep, pte; 6201 vaddr_t l2_va, l2b_va, va; 6202 int i, j, k, occ, rows = 0; 6203 6204 if (pm == pmap_kernel()) 6205 printf("pmap_kernel (%p): ", pm); 6206 else 6207 printf("user pmap (%p): ", pm); 6208 6209 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6210 6211 l2_va = 0; 6212 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6213 l2 = pm->pm_l2[i]; 6214 6215 if (l2 == NULL || l2->l2_occupancy == 0) 6216 continue; 6217 6218 l2b_va = l2_va; 6219 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6220 l2b = &l2->l2_bucket[j]; 6221 6222 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6223 continue; 6224 6225 ptep = l2b->l2b_kva; 6226 6227 for (k = 0; k < 256 && ptep[k] == 0; k++) 6228 ; 6229 6230 k &= ~63; 6231 occ = l2b->l2b_occupancy; 6232 va = l2b_va + (k * 4096); 6233 for (; k < 256; k++, va += 0x1000) { 6234 char ch = ' '; 6235 if ((k % 64) == 0) { 6236 if ((rows % 8) == 0) { 6237 printf( 6238 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6239 } 6240 printf("%08lx: ", va); 6241 } 6242 6243 ncptes[k & 63] = 0; 6244 pte = ptep[k]; 6245 if (pte == 0) { 6246 ch = '.'; 6247 } else { 6248 occ--; 6249 switch (pte & 0x0c) { 6250 case 0x00: 6251 ch = 'D'; /* No cache No buff */ 6252 break; 6253 case 0x04: 6254 ch = 'B'; /* No cache buff */ 6255 break; 6256 case 0x08: 6257 if (pte & 0x40) 6258 ch = 'm'; 6259 else 6260 ch = 'C'; /* Cache No buff */ 6261 break; 6262 case 0x0c: 6263 ch = 'F'; /* Cache Buff */ 6264 break; 6265 } 6266 6267 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6268 ch += 0x20; 6269 6270 if ((pte & 0xc) == 0) 6271 ncptes[k & 63] = pte; 6272 } 6273 6274 if ((k % 64) == 63) { 6275 rows++; 6276 printf("%c\n", ch); 6277 pmap_dump_ncpg(pm); 6278 if (occ == 0) 6279 break; 6280 } else 6281 printf("%c", ch); 6282 } 6283 } 6284 } 6285 } 6286 6287 static void 6288 pmap_dump_ncpg(pmap_t pm) 6289 { 6290 struct vm_page *pg; 6291 struct pv_entry *pv; 6292 int i; 6293 6294 for (i = 0; i < 63; i++) { 6295 if (ncptes[i] == 0) 6296 continue; 6297 6298 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6299 if (pg == NULL) 6300 continue; 6301 6302 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6303 VM_PAGE_TO_PHYS(pg), 6304 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 6305 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 6306 6307 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 6308 printf(" %c va 0x%08lx, flags 0x%x\n", 6309 (pm == pv->pv_pmap) ? '*' : ' ', 6310 pv->pv_va, pv->pv_flags); 6311 } 6312 } 6313 } 6314 #endif 6315 6316 #ifdef PMAP_STEAL_MEMORY 6317 void 6318 pmap_boot_pageadd(pv_addr_t *newpv) 6319 { 6320 pv_addr_t *pv, *npv; 6321 6322 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6323 if (newpv->pv_pa < pv->pv_va) { 6324 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6325 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6326 newpv->pv_size += pv->pv_size; 6327 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6328 } 6329 pv = NULL; 6330 } else { 6331 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6332 pv = npv) { 6333 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6334 KASSERT(pv->pv_pa < newpv->pv_pa); 6335 if (newpv->pv_pa > npv->pv_pa) 6336 continue; 6337 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6338 pv->pv_size += newpv->pv_size; 6339 return; 6340 } 6341 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6342 break; 6343 newpv->pv_size += npv->pv_size; 6344 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6345 SLIST_REMOVE_AFTER(newpv, pv_list); 6346 return; 6347 } 6348 } 6349 } 6350 6351 if (pv) { 6352 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6353 } else { 6354 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6355 } 6356 } 6357 6358 void 6359 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6360 pv_addr_t *rpv) 6361 { 6362 pv_addr_t *pv, **pvp; 6363 struct vm_physseg *ps; 6364 size_t i; 6365 6366 KASSERT(amount & PGOFSET); 6367 KASSERT((mask & PGOFSET) == 0); 6368 KASSERT((match & PGOFSET) == 0); 6369 KASSERT(amount != 0); 6370 6371 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6372 (pv = *pvp) != NULL; 6373 pvp = &SLIST_NEXT(pv, pv_list)) { 6374 pv_addr_t *newpv; 6375 psize_t off; 6376 /* 6377 * If this entry is too small to satify the request... 6378 */ 6379 KASSERT(pv->pv_size > 0); 6380 if (pv->pv_size < amount) 6381 continue; 6382 6383 for (off = 0; off <= mask; off += PAGE_SIZE) { 6384 if (((pv->pv_pa + off) & mask) == match 6385 && off + amount <= pv->pv_size) 6386 break; 6387 } 6388 if (off > mask) 6389 continue; 6390 6391 rpv->pv_va = pv->pv_va + off; 6392 rpv->pv_pa = pv->pv_pa + off; 6393 rpv->pv_size = amount; 6394 pv->pv_size -= amount; 6395 if (pv->pv_size == 0) { 6396 KASSERT(off == 0); 6397 KASSERT((vaddr_t) pv == rpv->pv_va); 6398 *pvp = SLIST_NEXT(pv, pv_list); 6399 } else if (off == 0) { 6400 KASSERT((vaddr_t) pv == rpv->pv_va); 6401 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6402 *newpv = *pv; 6403 newpv->pv_pa += amount; 6404 newpv->pv_va += amount; 6405 *pvp = newpv; 6406 } else if (off < pv->pv_size) { 6407 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6408 *newpv = *pv; 6409 newpv->pv_size -= off; 6410 newpv->pv_pa += off + amount; 6411 newpv->pv_va += off + amount; 6412 6413 SLIST_NEXT(pv, pv_list) = newpv; 6414 pv->pv_size = off; 6415 } else { 6416 KASSERT((vaddr_t) pv != rpv->pv_va); 6417 } 6418 memset((void *)rpv->pv_va, 0, amount); 6419 return; 6420 } 6421 6422 if (vm_nphysseg == 0) 6423 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6424 6425 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6426 (pv = *pvp) != NULL; 6427 pvp = &SLIST_NEXT(pv, pv_list)) { 6428 if (SLIST_NEXT(pv, pv_list) == NULL) 6429 break; 6430 } 6431 KASSERT(mask == 0); 6432 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6433 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6434 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6435 rpv->pv_va = pv->pv_va; 6436 rpv->pv_pa = pv->pv_pa; 6437 rpv->pv_size = amount; 6438 *pvp = NULL; 6439 pmap_map_chunk(kernel_l1pt.pv_va, 6440 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6441 ptoa(ps->avail_start), 6442 amount - pv->pv_size, 6443 VM_PROT_READ|VM_PROT_WRITE, 6444 PTE_CACHE); 6445 ps->avail_start += atop(amount - pv->pv_size); 6446 /* 6447 * If we consumed the entire physseg, remove it. 6448 */ 6449 if (ps->avail_start == ps->avail_end) { 6450 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6451 ps[0] = ps[1]; 6452 } 6453 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6454 return; 6455 } 6456 } 6457 6458 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6459 } 6460 6461 vaddr_t 6462 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6463 { 6464 pv_addr_t pv; 6465 6466 pmap_boot_pagealloc(size, 0, 0, &pv); 6467 6468 return pv.pv_va; 6469 } 6470 #endif /* PMAP_STEAL_MEMORY */ 6471 6472 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6473 { 6474 sysctl_createv(clog, 0, NULL, NULL, 6475 CTLFLAG_PERMANENT, 6476 CTLTYPE_NODE, "machdep", NULL, 6477 NULL, 0, NULL, 0, 6478 CTL_MACHDEP, CTL_EOL); 6479 6480 sysctl_createv(clog, 0, NULL, NULL, 6481 CTLFLAG_PERMANENT, 6482 CTLTYPE_INT, "kmpages", 6483 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6484 NULL, 0, &pmap_kmpages, 0, 6485 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6486 } 6487
Indexes created Sun Sep 28 16:09:52 GMT 2025