pmap.c revision 1.194
1 /* $NetBSD: pmap.c,v 1.194 2008/12/30 05:51:19 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/user.h> 202 #include <sys/pool.h> 203 #include <sys/cdefs.h> 204 #include <sys/cpu.h> 205 #include <sys/sysctl.h> 206 207 #include <uvm/uvm.h> 208 209 #include <machine/bus.h> 210 #include <machine/pmap.h> 211 #include <machine/pcb.h> 212 #include <machine/param.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.194 2008/12/30 05:51:19 matt Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 #define PDB_EXEC 0x80000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 static struct pmap kernel_pmap_store; 259 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 260 261 /* 262 * Which pmap is currently 'live' in the cache 263 * 264 * XXXSCW: Fix for SMP ... 265 */ 266 static pmap_t pmap_recent_user; 267 268 /* 269 * Pointer to last active lwp, or NULL if it exited. 270 */ 271 struct lwp *pmap_previous_active_lwp; 272 273 /* 274 * Pool and cache that pmap structures are allocated from. 275 * We use a cache to avoid clearing the pm_l2[] array (1KB) 276 * in pmap_create(). 277 */ 278 static struct pool_cache pmap_cache; 279 static LIST_HEAD(, pmap) pmap_pmaps; 280 281 /* 282 * Pool of PV structures 283 */ 284 static struct pool pmap_pv_pool; 285 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 286 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 287 static struct pool_allocator pmap_bootstrap_pv_allocator = { 288 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 289 }; 290 291 /* 292 * Pool and cache of l2_dtable structures. 293 * We use a cache to avoid clearing the structures when they're 294 * allocated. (196 bytes) 295 */ 296 static struct pool_cache pmap_l2dtable_cache; 297 static vaddr_t pmap_kernel_l2dtable_kva; 298 299 /* 300 * Pool and cache of L2 page descriptors. 301 * We use a cache to avoid clearing the descriptor table 302 * when they're allocated. (1KB) 303 */ 304 static struct pool_cache pmap_l2ptp_cache; 305 static vaddr_t pmap_kernel_l2ptp_kva; 306 static paddr_t pmap_kernel_l2ptp_phys; 307 308 #ifdef PMAPCOUNTERS 309 #define PMAP_EVCNT_INITIALIZER(name) \ 310 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 311 312 #ifdef PMAP_CACHE_VIPT 313 static struct evcnt pmap_ev_vac_clean_one = 314 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 315 static struct evcnt pmap_ev_vac_flush_one = 316 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 317 static struct evcnt pmap_ev_vac_flush_lots = 318 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 319 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 322 323 static struct evcnt pmap_ev_vac_color_new = 324 PMAP_EVCNT_INITIALIZER("new page color"); 325 static struct evcnt pmap_ev_vac_color_reuse = 326 PMAP_EVCNT_INITIALIZER("ok first page color"); 327 static struct evcnt pmap_ev_vac_color_ok = 328 PMAP_EVCNT_INITIALIZER("ok page color"); 329 static struct evcnt pmap_ev_vac_color_blind = 330 PMAP_EVCNT_INITIALIZER("blind page color"); 331 static struct evcnt pmap_ev_vac_color_change = 332 PMAP_EVCNT_INITIALIZER("change page color"); 333 static struct evcnt pmap_ev_vac_color_erase = 334 PMAP_EVCNT_INITIALIZER("erase page color"); 335 static struct evcnt pmap_ev_vac_color_none = 336 PMAP_EVCNT_INITIALIZER("no page color"); 337 static struct evcnt pmap_ev_vac_color_restore = 338 PMAP_EVCNT_INITIALIZER("restore page color"); 339 340 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 341 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 342 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 348 #endif 349 350 static struct evcnt pmap_ev_mappings = 351 PMAP_EVCNT_INITIALIZER("pages mapped"); 352 static struct evcnt pmap_ev_unmappings = 353 PMAP_EVCNT_INITIALIZER("pages unmapped"); 354 static struct evcnt pmap_ev_remappings = 355 PMAP_EVCNT_INITIALIZER("pages remapped"); 356 357 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 358 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 359 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 360 361 static struct evcnt pmap_ev_kernel_mappings = 362 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 363 static struct evcnt pmap_ev_kernel_unmappings = 364 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 365 static struct evcnt pmap_ev_kernel_remappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 367 368 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 369 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 370 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 371 372 static struct evcnt pmap_ev_kenter_mappings = 373 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 374 static struct evcnt pmap_ev_kenter_unmappings = 375 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 376 static struct evcnt pmap_ev_kenter_remappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 378 static struct evcnt pmap_ev_pt_mappings = 379 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 380 381 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 382 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 383 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 384 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 385 386 #ifdef PMAP_CACHE_VIPT 387 static struct evcnt pmap_ev_exec_mappings = 388 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 389 static struct evcnt pmap_ev_exec_cached = 390 PMAP_EVCNT_INITIALIZER("exec pages cached"); 391 392 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 393 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 394 395 static struct evcnt pmap_ev_exec_synced = 396 PMAP_EVCNT_INITIALIZER("exec pages synced"); 397 static struct evcnt pmap_ev_exec_synced_map = 398 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 399 static struct evcnt pmap_ev_exec_synced_unmap = 400 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 401 static struct evcnt pmap_ev_exec_synced_remap = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 403 static struct evcnt pmap_ev_exec_synced_clearbit = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 405 static struct evcnt pmap_ev_exec_synced_kremove = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 407 408 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 409 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 414 415 static struct evcnt pmap_ev_exec_discarded_unmap = 416 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 417 static struct evcnt pmap_ev_exec_discarded_zero = 418 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 419 static struct evcnt pmap_ev_exec_discarded_copy = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 421 static struct evcnt pmap_ev_exec_discarded_page_protect = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 423 static struct evcnt pmap_ev_exec_discarded_clearbit = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 425 static struct evcnt pmap_ev_exec_discarded_kremove = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 427 428 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 429 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 430 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 434 #endif /* PMAP_CACHE_VIPT */ 435 436 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 437 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 438 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 439 440 EVCNT_ATTACH_STATIC(pmap_ev_updates); 441 EVCNT_ATTACH_STATIC(pmap_ev_collects); 442 EVCNT_ATTACH_STATIC(pmap_ev_activations); 443 444 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 445 #else 446 #define PMAPCOUNT(x) ((void)0) 447 #endif 448 449 /* 450 * pmap copy/zero page, and mem(5) hook point 451 */ 452 static pt_entry_t *csrc_pte, *cdst_pte; 453 static vaddr_t csrcp, cdstp; 454 vaddr_t memhook; /* used by mem.c */ 455 kmutex_t memlock; /* used by mem.c */ 456 void *zeropage; /* used by mem.c */ 457 extern void *msgbufaddr; 458 int pmap_kmpages; 459 /* 460 * Flag to indicate if pmap_init() has done its thing 461 */ 462 bool pmap_initialized; 463 464 /* 465 * Misc. locking data structures 466 */ 467 468 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 469 static struct lock pmap_main_lock; 470 471 #define PMAP_MAP_TO_HEAD_LOCK() \ 472 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 473 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 474 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 475 #define PMAP_HEAD_TO_MAP_LOCK() \ 476 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 477 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 478 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 479 #else 480 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 481 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 482 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 483 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 484 #endif 485 486 #define pmap_acquire_pmap_lock(pm) \ 487 do { \ 488 if ((pm) != pmap_kernel()) \ 489 mutex_enter(&(pm)->pm_lock); \ 490 } while (/*CONSTCOND*/0) 491 492 #define pmap_release_pmap_lock(pm) \ 493 do { \ 494 if ((pm) != pmap_kernel()) \ 495 mutex_exit(&(pm)->pm_lock); \ 496 } while (/*CONSTCOND*/0) 497 498 499 /* 500 * Metadata for L1 translation tables. 501 */ 502 struct l1_ttable { 503 /* Entry on the L1 Table list */ 504 SLIST_ENTRY(l1_ttable) l1_link; 505 506 /* Entry on the L1 Least Recently Used list */ 507 TAILQ_ENTRY(l1_ttable) l1_lru; 508 509 /* Track how many domains are allocated from this L1 */ 510 volatile u_int l1_domain_use_count; 511 512 /* 513 * A free-list of domain numbers for this L1. 514 * We avoid using ffs() and a bitmap to track domains since ffs() 515 * is slow on ARM. 516 */ 517 u_int8_t l1_domain_first; 518 u_int8_t l1_domain_free[PMAP_DOMAINS]; 519 520 /* Physical address of this L1 page table */ 521 paddr_t l1_physaddr; 522 523 /* KVA of this L1 page table */ 524 pd_entry_t *l1_kva; 525 }; 526 527 /* 528 * Convert a virtual address into its L1 table index. That is, the 529 * index used to locate the L2 descriptor table pointer in an L1 table. 530 * This is basically used to index l1->l1_kva[]. 531 * 532 * Each L2 descriptor table represents 1MB of VA space. 533 */ 534 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 535 536 /* 537 * L1 Page Tables are tracked using a Least Recently Used list. 538 * - New L1s are allocated from the HEAD. 539 * - Freed L1s are added to the TAIl. 540 * - Recently accessed L1s (where an 'access' is some change to one of 541 * the userland pmaps which owns this L1) are moved to the TAIL. 542 */ 543 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 544 static struct simplelock l1_lru_lock; 545 546 /* 547 * A list of all L1 tables 548 */ 549 static SLIST_HEAD(, l1_ttable) l1_list; 550 551 /* 552 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 553 * 554 * This is normally 16MB worth L2 page descriptors for any given pmap. 555 * Reference counts are maintained for L2 descriptors so they can be 556 * freed when empty. 557 */ 558 struct l2_dtable { 559 /* The number of L2 page descriptors allocated to this l2_dtable */ 560 u_int l2_occupancy; 561 562 /* List of L2 page descriptors */ 563 struct l2_bucket { 564 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 565 paddr_t l2b_phys; /* Physical address of same */ 566 u_short l2b_l1idx; /* This L2 table's L1 index */ 567 u_short l2b_occupancy; /* How many active descriptors */ 568 } l2_bucket[L2_BUCKET_SIZE]; 569 }; 570 571 /* 572 * Given an L1 table index, calculate the corresponding l2_dtable index 573 * and bucket index within the l2_dtable. 574 */ 575 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 576 (L2_SIZE - 1)) 577 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 578 579 /* 580 * Given a virtual address, this macro returns the 581 * virtual address required to drop into the next L2 bucket. 582 */ 583 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 584 585 /* 586 * L2 allocation. 587 */ 588 #define pmap_alloc_l2_dtable() \ 589 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 590 #define pmap_free_l2_dtable(l2) \ 591 pool_cache_put(&pmap_l2dtable_cache, (l2)) 592 #define pmap_alloc_l2_ptp(pap) \ 593 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 594 PR_NOWAIT, (pap))) 595 596 /* 597 * We try to map the page tables write-through, if possible. However, not 598 * all CPUs have a write-through cache mode, so on those we have to sync 599 * the cache when we frob page tables. 600 * 601 * We try to evaluate this at compile time, if possible. However, it's 602 * not always possible to do that, hence this run-time var. 603 */ 604 int pmap_needs_pte_sync; 605 606 /* 607 * Real definition of pv_entry. 608 */ 609 struct pv_entry { 610 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 611 pmap_t pv_pmap; /* pmap where mapping lies */ 612 vaddr_t pv_va; /* virtual address for mapping */ 613 u_int pv_flags; /* flags */ 614 }; 615 616 /* 617 * Macro to determine if a mapping might be resident in the 618 * instruction cache and/or TLB 619 */ 620 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 621 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 622 623 /* 624 * Macro to determine if a mapping might be resident in the 625 * data cache and/or TLB 626 */ 627 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 628 629 /* 630 * Local prototypes 631 */ 632 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 633 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 634 pt_entry_t **); 635 static bool pmap_is_current(pmap_t); 636 static bool pmap_is_cached(pmap_t); 637 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 638 pmap_t, vaddr_t, u_int); 639 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 640 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 641 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 642 u_int, u_int); 643 644 static void pmap_pinit(pmap_t); 645 static int pmap_pmap_ctor(void *, void *, int); 646 647 static void pmap_alloc_l1(pmap_t); 648 static void pmap_free_l1(pmap_t); 649 static void pmap_use_l1(pmap_t); 650 651 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 652 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 653 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 654 static int pmap_l2ptp_ctor(void *, void *, int); 655 static int pmap_l2dtable_ctor(void *, void *, int); 656 657 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 658 #ifdef PMAP_CACHE_VIVT 659 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 660 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 661 #endif 662 663 static void pmap_clearbit(struct vm_page *, u_int); 664 #ifdef PMAP_CACHE_VIVT 665 static int pmap_clean_page(struct pv_entry *, bool); 666 #endif 667 #ifdef PMAP_CACHE_VIPT 668 static void pmap_syncicache_page(struct vm_page *); 669 enum pmap_flush_op { 670 PMAP_FLUSH_PRIMARY, 671 PMAP_FLUSH_SECONDARY, 672 PMAP_CLEAN_PRIMARY 673 }; 674 static void pmap_flush_page(struct vm_page *, enum pmap_flush_op); 675 #endif 676 static void pmap_page_remove(struct vm_page *); 677 678 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 679 static vaddr_t kernel_pt_lookup(paddr_t); 680 681 682 /* 683 * External function prototypes 684 */ 685 extern void bzero_page(vaddr_t); 686 extern void bcopy_page(vaddr_t, vaddr_t); 687 688 /* 689 * Misc variables 690 */ 691 vaddr_t virtual_avail; 692 vaddr_t virtual_end; 693 vaddr_t pmap_curmaxkvaddr; 694 695 vaddr_t avail_start; 696 vaddr_t avail_end; 697 698 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 699 pv_addr_t kernelpages; 700 pv_addr_t kernel_l1pt; 701 pv_addr_t systempage; 702 703 /* Function to set the debug level of the pmap code */ 704 705 #ifdef PMAP_DEBUG 706 void 707 pmap_debug(int level) 708 { 709 pmap_debug_level = level; 710 printf("pmap_debug: level=%d\n", pmap_debug_level); 711 } 712 #endif /* PMAP_DEBUG */ 713 714 /* 715 * A bunch of routines to conditionally flush the caches/TLB depending 716 * on whether the specified pmap actually needs to be flushed at any 717 * given time. 718 */ 719 static inline void 720 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 721 { 722 723 if (pm->pm_cstate.cs_tlb_id) 724 cpu_tlb_flushID_SE(va); 725 } 726 727 static inline void 728 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 729 { 730 731 if (pm->pm_cstate.cs_tlb_d) 732 cpu_tlb_flushD_SE(va); 733 } 734 735 static inline void 736 pmap_tlb_flushID(pmap_t pm) 737 { 738 739 if (pm->pm_cstate.cs_tlb_id) { 740 cpu_tlb_flushID(); 741 pm->pm_cstate.cs_tlb = 0; 742 } 743 } 744 745 static inline void 746 pmap_tlb_flushD(pmap_t pm) 747 { 748 749 if (pm->pm_cstate.cs_tlb_d) { 750 cpu_tlb_flushD(); 751 pm->pm_cstate.cs_tlb_d = 0; 752 } 753 } 754 755 #ifdef PMAP_CACHE_VIVT 756 static inline void 757 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 758 { 759 if (pm->pm_cstate.cs_cache_id) { 760 cpu_idcache_wbinv_range(va, len); 761 } 762 } 763 764 static inline void 765 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 766 bool do_inv, bool rd_only) 767 { 768 769 if (pm->pm_cstate.cs_cache_d) { 770 if (do_inv) { 771 if (rd_only) 772 cpu_dcache_inv_range(va, len); 773 else 774 cpu_dcache_wbinv_range(va, len); 775 } else 776 if (!rd_only) 777 cpu_dcache_wb_range(va, len); 778 } 779 } 780 781 static inline void 782 pmap_idcache_wbinv_all(pmap_t pm) 783 { 784 if (pm->pm_cstate.cs_cache_id) { 785 cpu_idcache_wbinv_all(); 786 pm->pm_cstate.cs_cache = 0; 787 } 788 } 789 790 static inline void 791 pmap_dcache_wbinv_all(pmap_t pm) 792 { 793 if (pm->pm_cstate.cs_cache_d) { 794 cpu_dcache_wbinv_all(); 795 pm->pm_cstate.cs_cache_d = 0; 796 } 797 } 798 #endif /* PMAP_CACHE_VIVT */ 799 800 static inline bool 801 pmap_is_current(pmap_t pm) 802 { 803 804 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 805 return true; 806 807 return false; 808 } 809 810 static inline bool 811 pmap_is_cached(pmap_t pm) 812 { 813 814 if (pm == pmap_kernel() || pmap_recent_user == NULL || 815 pmap_recent_user == pm) 816 return (true); 817 818 return false; 819 } 820 821 /* 822 * PTE_SYNC_CURRENT: 823 * 824 * Make sure the pte is written out to RAM. 825 * We need to do this for one of two cases: 826 * - We're dealing with the kernel pmap 827 * - There is no pmap active in the cache/tlb. 828 * - The specified pmap is 'active' in the cache/tlb. 829 */ 830 #ifdef PMAP_INCLUDE_PTE_SYNC 831 #define PTE_SYNC_CURRENT(pm, ptep) \ 832 do { \ 833 if (PMAP_NEEDS_PTE_SYNC && \ 834 pmap_is_cached(pm)) \ 835 PTE_SYNC(ptep); \ 836 } while (/*CONSTCOND*/0) 837 #else 838 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 839 #endif 840 841 /* 842 * main pv_entry manipulation functions: 843 * pmap_enter_pv: enter a mapping onto a vm_page list 844 * pmap_remove_pv: remove a mappiing from a vm_page list 845 * 846 * NOTE: pmap_enter_pv expects to lock the pvh itself 847 * pmap_remove_pv expects te caller to lock the pvh before calling 848 */ 849 850 /* 851 * pmap_enter_pv: enter a mapping onto a vm_page lst 852 * 853 * => caller should hold the proper lock on pmap_main_lock 854 * => caller should have pmap locked 855 * => we will gain the lock on the vm_page and allocate the new pv_entry 856 * => caller should adjust ptp's wire_count before calling 857 * => caller should not adjust pmap's wire_count 858 */ 859 static void 860 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 861 vaddr_t va, u_int flags) 862 { 863 struct pv_entry **pvp; 864 865 NPDEBUG(PDB_PVDUMP, 866 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 867 868 pve->pv_pmap = pm; 869 pve->pv_va = va; 870 pve->pv_flags = flags; 871 872 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 873 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 874 #ifdef PMAP_CACHE_VIPT 875 /* 876 * Insert unmanaged entries, writeable first, at the head of 877 * the pv list. 878 */ 879 if (__predict_true((flags & PVF_KENTRY) == 0)) { 880 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 881 pvp = &SLIST_NEXT(*pvp, pv_link); 882 } else if ((flags & PVF_WRITE) == 0) { 883 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 884 pvp = &SLIST_NEXT(*pvp, pv_link); 885 } 886 #endif 887 SLIST_NEXT(pve, pv_link) = *pvp; /* add to ... */ 888 *pvp = pve; /* ... locked list */ 889 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 890 #ifdef PMAP_CACHE_VIPT 891 if ((pve->pv_flags & PVF_KWRITE) == PVF_KWRITE) 892 pg->mdpage.pvh_attrs |= PVF_KMOD; 893 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 894 pg->mdpage.pvh_attrs |= PVF_DIRTY; 895 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 896 #endif 897 if (pm == pmap_kernel()) { 898 PMAPCOUNT(kernel_mappings); 899 if (flags & PVF_WRITE) 900 pg->mdpage.krw_mappings++; 901 else 902 pg->mdpage.kro_mappings++; 903 } else 904 if (flags & PVF_WRITE) 905 pg->mdpage.urw_mappings++; 906 else 907 pg->mdpage.uro_mappings++; 908 909 #ifdef PMAP_CACHE_VIPT 910 /* 911 * If this is an exec mapping and its the first exec mapping 912 * for this page, make sure to sync the I-cache. 913 */ 914 if (PV_IS_EXEC_P(flags)) { 915 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 916 pmap_syncicache_page(pg); 917 PMAPCOUNT(exec_synced_map); 918 } 919 PMAPCOUNT(exec_mappings); 920 } 921 #endif 922 923 PMAPCOUNT(mappings); 924 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 925 926 if (pve->pv_flags & PVF_WIRED) 927 ++pm->pm_stats.wired_count; 928 } 929 930 /* 931 * 932 * pmap_find_pv: Find a pv entry 933 * 934 * => caller should hold lock on vm_page 935 */ 936 static inline struct pv_entry * 937 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 938 { 939 struct pv_entry *pv; 940 941 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 942 if (pm == pv->pv_pmap && va == pv->pv_va) 943 break; 944 } 945 946 return (pv); 947 } 948 949 /* 950 * pmap_remove_pv: try to remove a mapping from a pv_list 951 * 952 * => caller should hold proper lock on pmap_main_lock 953 * => pmap should be locked 954 * => caller should hold lock on vm_page [so that attrs can be adjusted] 955 * => caller should adjust ptp's wire_count and free PTP if needed 956 * => caller should NOT adjust pmap's wire_count 957 * => we return the removed pve 958 */ 959 static struct pv_entry * 960 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 961 { 962 struct pv_entry *pve, **prevptr; 963 964 NPDEBUG(PDB_PVDUMP, 965 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 966 967 prevptr = &SLIST_FIRST(&pg->mdpage.pvh_list); /* prev pv_entry ptr */ 968 pve = *prevptr; 969 970 while (pve) { 971 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 972 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 973 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 974 if (pve->pv_flags & PVF_WIRED) { 975 if (skip_wired) 976 return (NULL); 977 --pm->pm_stats.wired_count; 978 } 979 *prevptr = SLIST_NEXT(pve, pv_link); /* remove it! */ 980 if (pm == pmap_kernel()) { 981 PMAPCOUNT(kernel_unmappings); 982 if (pve->pv_flags & PVF_WRITE) 983 pg->mdpage.krw_mappings--; 984 else 985 pg->mdpage.kro_mappings--; 986 } else 987 if (pve->pv_flags & PVF_WRITE) 988 pg->mdpage.urw_mappings--; 989 else 990 pg->mdpage.uro_mappings--; 991 992 PMAPCOUNT(unmappings); 993 #ifdef PMAP_CACHE_VIPT 994 if (!(pve->pv_flags & PVF_WRITE)) 995 break; 996 /* 997 * If this page has had an exec mapping, then if 998 * this was the last mapping, discard the contents, 999 * otherwise sync the i-cache for this page. 1000 */ 1001 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 1002 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 1003 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 1004 PMAPCOUNT(exec_discarded_unmap); 1005 } else { 1006 pmap_syncicache_page(pg); 1007 PMAPCOUNT(exec_synced_unmap); 1008 } 1009 } 1010 #endif /* PMAP_CACHE_VIPT */ 1011 break; 1012 } 1013 prevptr = &SLIST_NEXT(pve, pv_link); /* previous pointer */ 1014 pve = *prevptr; /* advance */ 1015 } 1016 1017 #ifdef PMAP_CACHE_VIPT 1018 /* 1019 * If we no longer have a WRITEABLE KENTRY at the head of list, 1020 * clear the KMOD attribute from the page. 1021 */ 1022 if (SLIST_FIRST(&pg->mdpage.pvh_list) == NULL 1023 || (SLIST_FIRST(&pg->mdpage.pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1024 pg->mdpage.pvh_attrs &= ~PVF_KMOD; 1025 1026 /* 1027 * If this was a writeable page and there are no more writeable 1028 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1029 * the contents to memory. 1030 */ 1031 if (pg->mdpage.krw_mappings + pg->mdpage.urw_mappings == 0) 1032 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1033 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1034 #endif /* PMAP_CACHE_VIPT */ 1035 1036 return(pve); /* return removed pve */ 1037 } 1038 1039 /* 1040 * 1041 * pmap_modify_pv: Update pv flags 1042 * 1043 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1044 * => caller should NOT adjust pmap's wire_count 1045 * => caller must call pmap_vac_me_harder() if writable status of a page 1046 * may have changed. 1047 * => we return the old flags 1048 * 1049 * Modify a physical-virtual mapping in the pv table 1050 */ 1051 static u_int 1052 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 1053 u_int clr_mask, u_int set_mask) 1054 { 1055 struct pv_entry *npv; 1056 u_int flags, oflags; 1057 1058 KASSERT((clr_mask & PVF_KENTRY) == 0); 1059 KASSERT((set_mask & PVF_KENTRY) == 0); 1060 1061 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1062 return (0); 1063 1064 NPDEBUG(PDB_PVDUMP, 1065 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 1066 1067 /* 1068 * There is at least one VA mapping this page. 1069 */ 1070 1071 if (clr_mask & (PVF_REF | PVF_MOD)) { 1072 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1073 #ifdef PMAP_CACHE_VIPT 1074 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1075 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1076 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1077 #endif 1078 } 1079 1080 oflags = npv->pv_flags; 1081 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1082 1083 if ((flags ^ oflags) & PVF_WIRED) { 1084 if (flags & PVF_WIRED) 1085 ++pm->pm_stats.wired_count; 1086 else 1087 --pm->pm_stats.wired_count; 1088 } 1089 1090 if ((flags ^ oflags) & PVF_WRITE) { 1091 if (pm == pmap_kernel()) { 1092 if (flags & PVF_WRITE) { 1093 pg->mdpage.krw_mappings++; 1094 pg->mdpage.kro_mappings--; 1095 } else { 1096 pg->mdpage.kro_mappings++; 1097 pg->mdpage.krw_mappings--; 1098 } 1099 } else 1100 if (flags & PVF_WRITE) { 1101 pg->mdpage.urw_mappings++; 1102 pg->mdpage.uro_mappings--; 1103 } else { 1104 pg->mdpage.uro_mappings++; 1105 pg->mdpage.urw_mappings--; 1106 } 1107 } 1108 #ifdef PMAP_CACHE_VIPT 1109 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 1110 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1111 /* 1112 * We have two cases here: the first is from enter_pv (new exec 1113 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1114 * Since in latter, pmap_enter_pv won't do anything, we just have 1115 * to do what pmap_remove_pv would do. 1116 */ 1117 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1118 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1119 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1120 pmap_syncicache_page(pg); 1121 PMAPCOUNT(exec_synced_remap); 1122 } 1123 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1124 #endif 1125 1126 PMAPCOUNT(remappings); 1127 1128 return (oflags); 1129 } 1130 1131 /* 1132 * Allocate an L1 translation table for the specified pmap. 1133 * This is called at pmap creation time. 1134 */ 1135 static void 1136 pmap_alloc_l1(pmap_t pm) 1137 { 1138 struct l1_ttable *l1; 1139 u_int8_t domain; 1140 1141 /* 1142 * Remove the L1 at the head of the LRU list 1143 */ 1144 simple_lock(&l1_lru_lock); 1145 l1 = TAILQ_FIRST(&l1_lru_list); 1146 KDASSERT(l1 != NULL); 1147 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1148 1149 /* 1150 * Pick the first available domain number, and update 1151 * the link to the next number. 1152 */ 1153 domain = l1->l1_domain_first; 1154 l1->l1_domain_first = l1->l1_domain_free[domain]; 1155 1156 /* 1157 * If there are still free domain numbers in this L1, 1158 * put it back on the TAIL of the LRU list. 1159 */ 1160 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1161 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1162 1163 simple_unlock(&l1_lru_lock); 1164 1165 /* 1166 * Fix up the relevant bits in the pmap structure 1167 */ 1168 pm->pm_l1 = l1; 1169 pm->pm_domain = domain; 1170 } 1171 1172 /* 1173 * Free an L1 translation table. 1174 * This is called at pmap destruction time. 1175 */ 1176 static void 1177 pmap_free_l1(pmap_t pm) 1178 { 1179 struct l1_ttable *l1 = pm->pm_l1; 1180 1181 simple_lock(&l1_lru_lock); 1182 1183 /* 1184 * If this L1 is currently on the LRU list, remove it. 1185 */ 1186 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1187 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1188 1189 /* 1190 * Free up the domain number which was allocated to the pmap 1191 */ 1192 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1193 l1->l1_domain_first = pm->pm_domain; 1194 l1->l1_domain_use_count--; 1195 1196 /* 1197 * The L1 now must have at least 1 free domain, so add 1198 * it back to the LRU list. If the use count is zero, 1199 * put it at the head of the list, otherwise it goes 1200 * to the tail. 1201 */ 1202 if (l1->l1_domain_use_count == 0) 1203 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1204 else 1205 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1206 1207 simple_unlock(&l1_lru_lock); 1208 } 1209 1210 static inline void 1211 pmap_use_l1(pmap_t pm) 1212 { 1213 struct l1_ttable *l1; 1214 1215 /* 1216 * Do nothing if we're in interrupt context. 1217 * Access to an L1 by the kernel pmap must not affect 1218 * the LRU list. 1219 */ 1220 if (cpu_intr_p() || pm == pmap_kernel()) 1221 return; 1222 1223 l1 = pm->pm_l1; 1224 1225 /* 1226 * If the L1 is not currently on the LRU list, just return 1227 */ 1228 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1229 return; 1230 1231 simple_lock(&l1_lru_lock); 1232 1233 /* 1234 * Check the use count again, now that we've acquired the lock 1235 */ 1236 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1237 simple_unlock(&l1_lru_lock); 1238 return; 1239 } 1240 1241 /* 1242 * Move the L1 to the back of the LRU list 1243 */ 1244 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1245 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1246 1247 simple_unlock(&l1_lru_lock); 1248 } 1249 1250 /* 1251 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1252 * 1253 * Free an L2 descriptor table. 1254 */ 1255 static inline void 1256 #ifndef PMAP_INCLUDE_PTE_SYNC 1257 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1258 #else 1259 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1260 #endif 1261 { 1262 #ifdef PMAP_INCLUDE_PTE_SYNC 1263 #ifdef PMAP_CACHE_VIVT 1264 /* 1265 * Note: With a write-back cache, we may need to sync this 1266 * L2 table before re-using it. 1267 * This is because it may have belonged to a non-current 1268 * pmap, in which case the cache syncs would have been 1269 * skipped for the pages that were being unmapped. If the 1270 * L2 table were then to be immediately re-allocated to 1271 * the *current* pmap, it may well contain stale mappings 1272 * which have not yet been cleared by a cache write-back 1273 * and so would still be visible to the mmu. 1274 */ 1275 if (need_sync) 1276 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1277 #endif /* PMAP_CACHE_VIVT */ 1278 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1279 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1280 } 1281 1282 /* 1283 * Returns a pointer to the L2 bucket associated with the specified pmap 1284 * and VA, or NULL if no L2 bucket exists for the address. 1285 */ 1286 static inline struct l2_bucket * 1287 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1288 { 1289 struct l2_dtable *l2; 1290 struct l2_bucket *l2b; 1291 u_short l1idx; 1292 1293 l1idx = L1_IDX(va); 1294 1295 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1296 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1297 return (NULL); 1298 1299 return (l2b); 1300 } 1301 1302 /* 1303 * Returns a pointer to the L2 bucket associated with the specified pmap 1304 * and VA. 1305 * 1306 * If no L2 bucket exists, perform the necessary allocations to put an L2 1307 * bucket/page table in place. 1308 * 1309 * Note that if a new L2 bucket/page was allocated, the caller *must* 1310 * increment the bucket occupancy counter appropriately *before* 1311 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1312 * the bucket/page in the meantime. 1313 */ 1314 static struct l2_bucket * 1315 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1316 { 1317 struct l2_dtable *l2; 1318 struct l2_bucket *l2b; 1319 u_short l1idx; 1320 1321 l1idx = L1_IDX(va); 1322 1323 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1324 /* 1325 * No mapping at this address, as there is 1326 * no entry in the L1 table. 1327 * Need to allocate a new l2_dtable. 1328 */ 1329 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1330 return (NULL); 1331 1332 /* 1333 * Link it into the parent pmap 1334 */ 1335 pm->pm_l2[L2_IDX(l1idx)] = l2; 1336 } 1337 1338 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1339 1340 /* 1341 * Fetch pointer to the L2 page table associated with the address. 1342 */ 1343 if (l2b->l2b_kva == NULL) { 1344 pt_entry_t *ptep; 1345 1346 /* 1347 * No L2 page table has been allocated. Chances are, this 1348 * is because we just allocated the l2_dtable, above. 1349 */ 1350 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1351 /* 1352 * Oops, no more L2 page tables available at this 1353 * time. We may need to deallocate the l2_dtable 1354 * if we allocated a new one above. 1355 */ 1356 if (l2->l2_occupancy == 0) { 1357 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1358 pmap_free_l2_dtable(l2); 1359 } 1360 return (NULL); 1361 } 1362 1363 l2->l2_occupancy++; 1364 l2b->l2b_kva = ptep; 1365 l2b->l2b_l1idx = l1idx; 1366 } 1367 1368 return (l2b); 1369 } 1370 1371 /* 1372 * One or more mappings in the specified L2 descriptor table have just been 1373 * invalidated. 1374 * 1375 * Garbage collect the metadata and descriptor table itself if necessary. 1376 * 1377 * The pmap lock must be acquired when this is called (not necessary 1378 * for the kernel pmap). 1379 */ 1380 static void 1381 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1382 { 1383 struct l2_dtable *l2; 1384 pd_entry_t *pl1pd, l1pd; 1385 pt_entry_t *ptep; 1386 u_short l1idx; 1387 1388 KDASSERT(count <= l2b->l2b_occupancy); 1389 1390 /* 1391 * Update the bucket's reference count according to how many 1392 * PTEs the caller has just invalidated. 1393 */ 1394 l2b->l2b_occupancy -= count; 1395 1396 /* 1397 * Note: 1398 * 1399 * Level 2 page tables allocated to the kernel pmap are never freed 1400 * as that would require checking all Level 1 page tables and 1401 * removing any references to the Level 2 page table. See also the 1402 * comment elsewhere about never freeing bootstrap L2 descriptors. 1403 * 1404 * We make do with just invalidating the mapping in the L2 table. 1405 * 1406 * This isn't really a big deal in practice and, in fact, leads 1407 * to a performance win over time as we don't need to continually 1408 * alloc/free. 1409 */ 1410 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1411 return; 1412 1413 /* 1414 * There are no more valid mappings in this level 2 page table. 1415 * Go ahead and NULL-out the pointer in the bucket, then 1416 * free the page table. 1417 */ 1418 l1idx = l2b->l2b_l1idx; 1419 ptep = l2b->l2b_kva; 1420 l2b->l2b_kva = NULL; 1421 1422 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1423 1424 /* 1425 * If the L1 slot matches the pmap's domain 1426 * number, then invalidate it. 1427 */ 1428 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1429 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1430 *pl1pd = 0; 1431 PTE_SYNC(pl1pd); 1432 } 1433 1434 /* 1435 * Release the L2 descriptor table back to the pool cache. 1436 */ 1437 #ifndef PMAP_INCLUDE_PTE_SYNC 1438 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1439 #else 1440 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1441 #endif 1442 1443 /* 1444 * Update the reference count in the associated l2_dtable 1445 */ 1446 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1447 if (--l2->l2_occupancy > 0) 1448 return; 1449 1450 /* 1451 * There are no more valid mappings in any of the Level 1 1452 * slots managed by this l2_dtable. Go ahead and NULL-out 1453 * the pointer in the parent pmap and free the l2_dtable. 1454 */ 1455 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1456 pmap_free_l2_dtable(l2); 1457 } 1458 1459 /* 1460 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1461 * structures. 1462 */ 1463 static int 1464 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1465 { 1466 #ifndef PMAP_INCLUDE_PTE_SYNC 1467 struct l2_bucket *l2b; 1468 pt_entry_t *ptep, pte; 1469 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1470 1471 /* 1472 * The mappings for these page tables were initially made using 1473 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1474 * mode will not be right for page table mappings. To avoid 1475 * polluting the pmap_kenter_pa() code with a special case for 1476 * page tables, we simply fix up the cache-mode here if it's not 1477 * correct. 1478 */ 1479 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1480 KDASSERT(l2b != NULL); 1481 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1482 pte = *ptep; 1483 1484 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1485 /* 1486 * Page tables must have the cache-mode set to Write-Thru. 1487 */ 1488 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1489 PTE_SYNC(ptep); 1490 cpu_tlb_flushD_SE(va); 1491 cpu_cpwait(); 1492 } 1493 #endif 1494 1495 memset(v, 0, L2_TABLE_SIZE_REAL); 1496 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1497 return (0); 1498 } 1499 1500 static int 1501 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1502 { 1503 1504 memset(v, 0, sizeof(struct l2_dtable)); 1505 return (0); 1506 } 1507 1508 static int 1509 pmap_pmap_ctor(void *arg, void *v, int flags) 1510 { 1511 1512 memset(v, 0, sizeof(struct pmap)); 1513 return (0); 1514 } 1515 1516 static void 1517 pmap_pinit(pmap_t pm) 1518 { 1519 struct l2_bucket *l2b; 1520 1521 if (vector_page < KERNEL_BASE) { 1522 /* 1523 * Map the vector page. 1524 */ 1525 pmap_enter(pm, vector_page, systempage.pv_pa, 1526 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1527 pmap_update(pm); 1528 1529 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1530 l2b = pmap_get_l2_bucket(pm, vector_page); 1531 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1532 L1_C_DOM(pm->pm_domain); 1533 } else 1534 pm->pm_pl1vec = NULL; 1535 } 1536 1537 #ifdef PMAP_CACHE_VIVT 1538 /* 1539 * Since we have a virtually indexed cache, we may need to inhibit caching if 1540 * there is more than one mapping and at least one of them is writable. 1541 * Since we purge the cache on every context switch, we only need to check for 1542 * other mappings within the same pmap, or kernel_pmap. 1543 * This function is also called when a page is unmapped, to possibly reenable 1544 * caching on any remaining mappings. 1545 * 1546 * The code implements the following logic, where: 1547 * 1548 * KW = # of kernel read/write pages 1549 * KR = # of kernel read only pages 1550 * UW = # of user read/write pages 1551 * UR = # of user read only pages 1552 * 1553 * KC = kernel mapping is cacheable 1554 * UC = user mapping is cacheable 1555 * 1556 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1557 * +--------------------------------------------- 1558 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1559 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1560 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1561 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1562 */ 1563 1564 static const int pmap_vac_flags[4][4] = { 1565 {-1, 0, 0, PVF_KNC}, 1566 {0, 0, PVF_NC, PVF_NC}, 1567 {0, PVF_NC, PVF_NC, PVF_NC}, 1568 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1569 }; 1570 1571 static inline int 1572 pmap_get_vac_flags(const struct vm_page *pg) 1573 { 1574 int kidx, uidx; 1575 1576 kidx = 0; 1577 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1578 kidx |= 1; 1579 if (pg->mdpage.krw_mappings) 1580 kidx |= 2; 1581 1582 uidx = 0; 1583 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1584 uidx |= 1; 1585 if (pg->mdpage.urw_mappings) 1586 uidx |= 2; 1587 1588 return (pmap_vac_flags[uidx][kidx]); 1589 } 1590 1591 static inline void 1592 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1593 { 1594 int nattr; 1595 1596 nattr = pmap_get_vac_flags(pg); 1597 1598 if (nattr < 0) { 1599 pg->mdpage.pvh_attrs &= ~PVF_NC; 1600 return; 1601 } 1602 1603 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1604 return; 1605 1606 if (pm == pmap_kernel()) 1607 pmap_vac_me_kpmap(pg, pm, va); 1608 else 1609 pmap_vac_me_user(pg, pm, va); 1610 1611 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1612 } 1613 1614 static void 1615 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1616 { 1617 u_int u_cacheable, u_entries; 1618 struct pv_entry *pv; 1619 pmap_t last_pmap = pm; 1620 1621 /* 1622 * Pass one, see if there are both kernel and user pmaps for 1623 * this page. Calculate whether there are user-writable or 1624 * kernel-writable pages. 1625 */ 1626 u_cacheable = 0; 1627 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1628 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1629 u_cacheable++; 1630 } 1631 1632 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1633 1634 /* 1635 * We know we have just been updating a kernel entry, so if 1636 * all user pages are already cacheable, then there is nothing 1637 * further to do. 1638 */ 1639 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1640 return; 1641 1642 if (u_entries) { 1643 /* 1644 * Scan over the list again, for each entry, if it 1645 * might not be set correctly, call pmap_vac_me_user 1646 * to recalculate the settings. 1647 */ 1648 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1649 /* 1650 * We know kernel mappings will get set 1651 * correctly in other calls. We also know 1652 * that if the pmap is the same as last_pmap 1653 * then we've just handled this entry. 1654 */ 1655 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1656 continue; 1657 1658 /* 1659 * If there are kernel entries and this page 1660 * is writable but non-cacheable, then we can 1661 * skip this entry also. 1662 */ 1663 if (pg->mdpage.k_mappings && 1664 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1665 (PVF_NC | PVF_WRITE)) 1666 continue; 1667 1668 /* 1669 * Similarly if there are no kernel-writable 1670 * entries and the page is already 1671 * read-only/cacheable. 1672 */ 1673 if (pg->mdpage.krw_mappings == 0 && 1674 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1675 continue; 1676 1677 /* 1678 * For some of the remaining cases, we know 1679 * that we must recalculate, but for others we 1680 * can't tell if they are correct or not, so 1681 * we recalculate anyway. 1682 */ 1683 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1684 } 1685 1686 if (pg->mdpage.k_mappings == 0) 1687 return; 1688 } 1689 1690 pmap_vac_me_user(pg, pm, va); 1691 } 1692 1693 static void 1694 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1695 { 1696 pmap_t kpmap = pmap_kernel(); 1697 struct pv_entry *pv, *npv = NULL; 1698 struct l2_bucket *l2b; 1699 pt_entry_t *ptep, pte; 1700 u_int entries = 0; 1701 u_int writable = 0; 1702 u_int cacheable_entries = 0; 1703 u_int kern_cacheable = 0; 1704 u_int other_writable = 0; 1705 1706 /* 1707 * Count mappings and writable mappings in this pmap. 1708 * Include kernel mappings as part of our own. 1709 * Keep a pointer to the first one. 1710 */ 1711 npv = NULL; 1712 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1713 /* Count mappings in the same pmap */ 1714 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1715 if (entries++ == 0) 1716 npv = pv; 1717 1718 /* Cacheable mappings */ 1719 if ((pv->pv_flags & PVF_NC) == 0) { 1720 cacheable_entries++; 1721 if (kpmap == pv->pv_pmap) 1722 kern_cacheable++; 1723 } 1724 1725 /* Writable mappings */ 1726 if (pv->pv_flags & PVF_WRITE) 1727 ++writable; 1728 } else 1729 if (pv->pv_flags & PVF_WRITE) 1730 other_writable = 1; 1731 } 1732 1733 /* 1734 * Enable or disable caching as necessary. 1735 * Note: the first entry might be part of the kernel pmap, 1736 * so we can't assume this is indicative of the state of the 1737 * other (maybe non-kpmap) entries. 1738 */ 1739 if ((entries > 1 && writable) || 1740 (entries > 0 && pm == kpmap && other_writable)) { 1741 if (cacheable_entries == 0) 1742 return; 1743 1744 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1745 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1746 (pv->pv_flags & PVF_NC)) 1747 continue; 1748 1749 pv->pv_flags |= PVF_NC; 1750 1751 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1752 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1753 pte = *ptep & ~L2_S_CACHE_MASK; 1754 1755 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1756 l2pte_valid(pte)) { 1757 if (PV_BEEN_EXECD(pv->pv_flags)) { 1758 #ifdef PMAP_CACHE_VIVT 1759 pmap_idcache_wbinv_range(pv->pv_pmap, 1760 pv->pv_va, PAGE_SIZE); 1761 #endif 1762 pmap_tlb_flushID_SE(pv->pv_pmap, 1763 pv->pv_va); 1764 } else 1765 if (PV_BEEN_REFD(pv->pv_flags)) { 1766 #ifdef PMAP_CACHE_VIVT 1767 pmap_dcache_wb_range(pv->pv_pmap, 1768 pv->pv_va, PAGE_SIZE, true, 1769 (pv->pv_flags & PVF_WRITE) == 0); 1770 #endif 1771 pmap_tlb_flushD_SE(pv->pv_pmap, 1772 pv->pv_va); 1773 } 1774 } 1775 1776 *ptep = pte; 1777 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1778 } 1779 cpu_cpwait(); 1780 } else 1781 if (entries > cacheable_entries) { 1782 /* 1783 * Turn cacheing back on for some pages. If it is a kernel 1784 * page, only do so if there are no other writable pages. 1785 */ 1786 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1787 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1788 (kpmap != pv->pv_pmap || other_writable))) 1789 continue; 1790 1791 pv->pv_flags &= ~PVF_NC; 1792 1793 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1794 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1795 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1796 1797 if (l2pte_valid(pte)) { 1798 if (PV_BEEN_EXECD(pv->pv_flags)) { 1799 pmap_tlb_flushID_SE(pv->pv_pmap, 1800 pv->pv_va); 1801 } else 1802 if (PV_BEEN_REFD(pv->pv_flags)) { 1803 pmap_tlb_flushD_SE(pv->pv_pmap, 1804 pv->pv_va); 1805 } 1806 } 1807 1808 *ptep = pte; 1809 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1810 } 1811 } 1812 } 1813 #endif 1814 1815 #ifdef PMAP_CACHE_VIPT 1816 static void 1817 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1818 { 1819 struct pv_entry *pv; 1820 vaddr_t tst_mask; 1821 bool bad_alias; 1822 struct l2_bucket *l2b; 1823 pt_entry_t *ptep, pte, opte; 1824 const u_int 1825 rw_mappings = pg->mdpage.urw_mappings + pg->mdpage.krw_mappings, 1826 ro_mappings = pg->mdpage.uro_mappings + pg->mdpage.kro_mappings; 1827 1828 /* do we need to do anything? */ 1829 if (arm_cache_prefer_mask == 0) 1830 return; 1831 1832 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1833 pg, pm, va)); 1834 1835 KASSERT(!va || pm); 1836 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1837 1838 /* Already a conflict? */ 1839 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1840 /* just an add, things are already non-cached */ 1841 KASSERT(!(pg->mdpage.pvh_attrs & PVF_DIRTY)); 1842 bad_alias = false; 1843 if (va) { 1844 PMAPCOUNT(vac_color_none); 1845 bad_alias = true; 1846 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1847 goto fixup; 1848 } 1849 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1850 /* the list can't be empty because it would be cachable */ 1851 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) { 1852 tst_mask = pg->mdpage.pvh_attrs; 1853 } else { 1854 KASSERT(pv); 1855 tst_mask = pv->pv_va; 1856 pv = SLIST_NEXT(pv, pv_link); 1857 } 1858 /* 1859 * Only check for a bad alias if we have writable mappings. 1860 */ 1861 tst_mask &= arm_cache_prefer_mask; 1862 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1863 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1864 /* if there's a bad alias, stop checking. */ 1865 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1866 bad_alias = true; 1867 } 1868 pg->mdpage.pvh_attrs |= PVF_WRITE; 1869 if (!bad_alias) 1870 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1871 } else { 1872 /* 1873 * We have only read-only mappings. Let's see if there 1874 * are multiple colors in use or if we mapped a KMPAGE. 1875 * If the latter, we have a bad alias. If the former, 1876 * we need to remember that. 1877 */ 1878 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1879 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1880 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) 1881 bad_alias = true; 1882 break; 1883 } 1884 } 1885 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1886 /* 1887 * No KMPAGE and we exited early, so we must have 1888 * multiple color mappings. 1889 */ 1890 if (!bad_alias && pv != NULL) 1891 pg->mdpage.pvh_attrs |= PVF_MULTCLR; 1892 } 1893 1894 /* If no conflicting colors, set everything back to cached */ 1895 if (!bad_alias) { 1896 #ifdef DEBUG 1897 if ((pg->mdpage.pvh_attrs & PVF_WRITE) 1898 || ro_mappings < 2) { 1899 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1900 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1901 } 1902 #endif 1903 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1904 pg->mdpage.pvh_attrs |= tst_mask | PVF_COLORED; 1905 /* 1906 * Restore DIRTY bit if page is modified 1907 */ 1908 if (pg->mdpage.pvh_attrs & PVF_DMOD) 1909 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1910 PMAPCOUNT(vac_color_restore); 1911 } else { 1912 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1913 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1914 } 1915 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1916 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1917 } else if (!va) { 1918 KASSERT(pmap_is_page_colored_p(pg)); 1919 KASSERT(!(pg->mdpage.pvh_attrs & PVF_WRITE) 1920 || (pg->mdpage.pvh_attrs & PVF_DIRTY)); 1921 if (rw_mappings == 0) { 1922 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1923 if (ro_mappings == 1 1924 && (pg->mdpage.pvh_attrs & PVF_MULTCLR)) { 1925 /* 1926 * If this is the last readonly mapping 1927 * but it doesn't match the current color 1928 * for the page, change the current color 1929 * to match this last readonly mapping. 1930 */ 1931 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1932 tst_mask = (pg->mdpage.pvh_attrs ^ pv->pv_va) 1933 & arm_cache_prefer_mask; 1934 if (tst_mask) { 1935 pg->mdpage.pvh_attrs ^= tst_mask; 1936 PMAPCOUNT(vac_color_change); 1937 } 1938 } 1939 } 1940 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1941 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1942 return; 1943 } else if (!pmap_is_page_colored_p(pg)) { 1944 /* not colored so we just use its color */ 1945 KASSERT(pg->mdpage.pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1946 PMAPCOUNT(vac_color_new); 1947 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1948 pg->mdpage.pvh_attrs |= PVF_COLORED 1949 | (va & arm_cache_prefer_mask) 1950 | (rw_mappings > 0 ? PVF_WRITE : 0); 1951 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1952 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1953 return; 1954 } else if (((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1955 bad_alias = false; 1956 if (rw_mappings > 0) { 1957 /* 1958 * We now have writeable mappings and if we have 1959 * readonly mappings in more than once color, we have 1960 * an aliasing problem. Regardless mark the page as 1961 * writeable. 1962 */ 1963 if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 1964 if (ro_mappings < 2) { 1965 /* 1966 * If we only have less than two 1967 * read-only mappings, just flush the 1968 * non-primary colors from the cache. 1969 */ 1970 pmap_flush_page(pg, 1971 PMAP_FLUSH_SECONDARY); 1972 } else { 1973 bad_alias = true; 1974 } 1975 } 1976 pg->mdpage.pvh_attrs |= PVF_WRITE; 1977 } 1978 /* If no conflicting colors, set everything back to cached */ 1979 if (!bad_alias) { 1980 #ifdef DEBUG 1981 if (rw_mappings > 0 1982 || (pg->mdpage.pvh_attrs & PMAP_KMPAGE)) { 1983 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1984 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1985 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1986 } 1987 #endif 1988 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) 1989 PMAPCOUNT(vac_color_reuse); 1990 else 1991 PMAPCOUNT(vac_color_ok); 1992 1993 /* matching color, just return */ 1994 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1995 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1996 return; 1997 } 1998 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1999 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 2000 2001 /* color conflict. evict from cache. */ 2002 2003 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 2004 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2005 pg->mdpage.pvh_attrs |= PVF_NC; 2006 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2007 PMAPCOUNT(vac_color_erase); 2008 } else if (rw_mappings == 0 2009 && (pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2010 KASSERT((pg->mdpage.pvh_attrs & PVF_WRITE) == 0); 2011 2012 /* 2013 * If the page has dirty cache lines, clean it. 2014 */ 2015 if (pg->mdpage.pvh_attrs & PVF_DIRTY) 2016 pmap_flush_page(pg, PMAP_CLEAN_PRIMARY); 2017 2018 /* 2019 * If this is the first remapping (we know that there are no 2020 * writeable mappings), then this is a simple color change. 2021 * Otherwise this is a seconary r/o mapping, which means 2022 * we don't have to do anything. 2023 */ 2024 if (ro_mappings == 1) { 2025 KASSERT(((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2026 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2027 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2028 PMAPCOUNT(vac_color_change); 2029 } else { 2030 PMAPCOUNT(vac_color_blind); 2031 } 2032 pg->mdpage.pvh_attrs |= PVF_MULTCLR; 2033 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2034 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2035 return; 2036 } else { 2037 if (rw_mappings > 0) 2038 pg->mdpage.pvh_attrs |= PVF_WRITE; 2039 2040 /* color conflict. evict from cache. */ 2041 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 2042 2043 /* the list can't be empty because this was a enter/modify */ 2044 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2045 if ((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2046 KASSERT(pv); 2047 /* 2048 * If there's only one mapped page, change color to the 2049 * page's new color and return. Restore the DIRTY bit 2050 * that was erased by pmap_flush_page. 2051 */ 2052 if (SLIST_NEXT(pv, pv_link) == NULL) { 2053 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2054 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2055 if (pg->mdpage.pvh_attrs & PVF_DMOD) 2056 pg->mdpage.pvh_attrs |= PVF_DIRTY; 2057 PMAPCOUNT(vac_color_change); 2058 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2059 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2060 return; 2061 } 2062 } 2063 bad_alias = true; 2064 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2065 pg->mdpage.pvh_attrs |= PVF_NC; 2066 PMAPCOUNT(vac_color_erase); 2067 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2068 } 2069 2070 fixup: 2071 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2072 2073 /* 2074 * Turn cacheing on/off for all pages. 2075 */ 2076 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2077 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2078 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2079 opte = *ptep; 2080 pte = opte & ~L2_S_CACHE_MASK; 2081 if (bad_alias) { 2082 pv->pv_flags |= PVF_NC; 2083 } else { 2084 pv->pv_flags &= ~PVF_NC; 2085 pte |= pte_l2_s_cache_mode; 2086 } 2087 2088 if (opte == pte) /* only update is there's a change */ 2089 continue; 2090 2091 if (l2pte_valid(pte)) { 2092 if (PV_BEEN_EXECD(pv->pv_flags)) { 2093 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2094 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2095 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2096 } 2097 } 2098 2099 *ptep = pte; 2100 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2101 } 2102 } 2103 #endif /* PMAP_CACHE_VIPT */ 2104 2105 2106 /* 2107 * Modify pte bits for all ptes corresponding to the given physical address. 2108 * We use `maskbits' rather than `clearbits' because we're always passing 2109 * constants and the latter would require an extra inversion at run-time. 2110 */ 2111 static void 2112 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2113 { 2114 struct l2_bucket *l2b; 2115 struct pv_entry *pv; 2116 pt_entry_t *ptep, npte, opte; 2117 pmap_t pm; 2118 vaddr_t va; 2119 u_int oflags; 2120 #ifdef PMAP_CACHE_VIPT 2121 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 2122 bool need_syncicache = false; 2123 bool did_syncicache = false; 2124 bool need_vac_me_harder = false; 2125 #endif 2126 2127 NPDEBUG(PDB_BITS, 2128 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2129 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2130 2131 PMAP_HEAD_TO_MAP_LOCK(); 2132 simple_lock(&pg->mdpage.pvh_slock); 2133 2134 #ifdef PMAP_CACHE_VIPT 2135 /* 2136 * If we might want to sync the I-cache and we've modified it, 2137 * then we know we definitely need to sync or discard it. 2138 */ 2139 if (want_syncicache) 2140 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 2141 #endif 2142 /* 2143 * Clear saved attributes (modify, reference) 2144 */ 2145 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2146 2147 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 2148 #ifdef PMAP_CACHE_VIPT 2149 if (need_syncicache) { 2150 /* 2151 * No one has it mapped, so just discard it. The next 2152 * exec remapping will cause it to be synced. 2153 */ 2154 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2155 PMAPCOUNT(exec_discarded_clearbit); 2156 } 2157 #endif 2158 simple_unlock(&pg->mdpage.pvh_slock); 2159 PMAP_HEAD_TO_MAP_UNLOCK(); 2160 return; 2161 } 2162 2163 /* 2164 * Loop over all current mappings setting/clearing as appropos 2165 */ 2166 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2167 va = pv->pv_va; 2168 pm = pv->pv_pmap; 2169 oflags = pv->pv_flags; 2170 /* 2171 * Kernel entries are unmanaged and as such not to be changed. 2172 */ 2173 if (oflags & PVF_KENTRY) 2174 continue; 2175 pv->pv_flags &= ~maskbits; 2176 2177 pmap_acquire_pmap_lock(pm); 2178 2179 l2b = pmap_get_l2_bucket(pm, va); 2180 KDASSERT(l2b != NULL); 2181 2182 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2183 npte = opte = *ptep; 2184 2185 NPDEBUG(PDB_BITS, 2186 printf( 2187 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2188 pv, pv->pv_pmap, pv->pv_va, oflags)); 2189 2190 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2191 #ifdef PMAP_CACHE_VIVT 2192 if ((pv->pv_flags & PVF_NC)) { 2193 /* 2194 * Entry is not cacheable: 2195 * 2196 * Don't turn caching on again if this is a 2197 * modified emulation. This would be 2198 * inconsitent with the settings created by 2199 * pmap_vac_me_harder(). Otherwise, it's safe 2200 * to re-enable cacheing. 2201 * 2202 * There's no need to call pmap_vac_me_harder() 2203 * here: all pages are losing their write 2204 * permission. 2205 */ 2206 if (maskbits & PVF_WRITE) { 2207 npte |= pte_l2_s_cache_mode; 2208 pv->pv_flags &= ~PVF_NC; 2209 } 2210 } else 2211 if (opte & L2_S_PROT_W) { 2212 /* 2213 * Entry is writable/cacheable: check if pmap 2214 * is current if it is flush it, otherwise it 2215 * won't be in the cache 2216 */ 2217 if (PV_BEEN_EXECD(oflags)) 2218 pmap_idcache_wbinv_range(pm, pv->pv_va, 2219 PAGE_SIZE); 2220 else 2221 if (PV_BEEN_REFD(oflags)) 2222 pmap_dcache_wb_range(pm, pv->pv_va, 2223 PAGE_SIZE, 2224 (maskbits & PVF_REF) != 0, false); 2225 } 2226 #endif 2227 2228 /* make the pte read only */ 2229 npte &= ~L2_S_PROT_W; 2230 2231 if (maskbits & oflags & PVF_WRITE) { 2232 /* 2233 * Keep alias accounting up to date 2234 */ 2235 if (pv->pv_pmap == pmap_kernel()) { 2236 pg->mdpage.krw_mappings--; 2237 pg->mdpage.kro_mappings++; 2238 } else { 2239 pg->mdpage.urw_mappings--; 2240 pg->mdpage.uro_mappings++; 2241 } 2242 #ifdef PMAP_CACHE_VIPT 2243 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 2244 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2245 if (want_syncicache) 2246 need_syncicache = true; 2247 need_vac_me_harder = true; 2248 #endif 2249 } 2250 } 2251 2252 if (maskbits & PVF_REF) { 2253 if ((pv->pv_flags & PVF_NC) == 0 && 2254 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2255 l2pte_valid(npte)) { 2256 #ifdef PMAP_CACHE_VIVT 2257 /* 2258 * Check npte here; we may have already 2259 * done the wbinv above, and the validity 2260 * of the PTE is the same for opte and 2261 * npte. 2262 */ 2263 /* XXXJRT need idcache_inv_range */ 2264 if (PV_BEEN_EXECD(oflags)) 2265 pmap_idcache_wbinv_range(pm, 2266 pv->pv_va, PAGE_SIZE); 2267 else 2268 if (PV_BEEN_REFD(oflags)) 2269 pmap_dcache_wb_range(pm, 2270 pv->pv_va, PAGE_SIZE, 2271 true, true); 2272 #endif 2273 } 2274 2275 /* 2276 * Make the PTE invalid so that we will take a 2277 * page fault the next time the mapping is 2278 * referenced. 2279 */ 2280 npte &= ~L2_TYPE_MASK; 2281 npte |= L2_TYPE_INV; 2282 } 2283 2284 if (npte != opte) { 2285 *ptep = npte; 2286 PTE_SYNC(ptep); 2287 /* Flush the TLB entry if a current pmap. */ 2288 if (PV_BEEN_EXECD(oflags)) 2289 pmap_tlb_flushID_SE(pm, pv->pv_va); 2290 else 2291 if (PV_BEEN_REFD(oflags)) 2292 pmap_tlb_flushD_SE(pm, pv->pv_va); 2293 } 2294 2295 pmap_release_pmap_lock(pm); 2296 2297 NPDEBUG(PDB_BITS, 2298 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2299 pm, va, opte, npte)); 2300 } 2301 2302 #ifdef PMAP_CACHE_VIPT 2303 /* 2304 * If we need to sync the I-cache and we haven't done it yet, do it. 2305 */ 2306 if (need_syncicache && !did_syncicache) { 2307 pmap_syncicache_page(pg); 2308 PMAPCOUNT(exec_synced_clearbit); 2309 } 2310 /* 2311 * If we are changing this to read-only, we need to call vac_me_harder 2312 * so we can change all the read-only pages to cacheable. We pretend 2313 * this as a page deletion. 2314 */ 2315 if (need_vac_me_harder) { 2316 if (pg->mdpage.pvh_attrs & PVF_NC) 2317 pmap_vac_me_harder(pg, NULL, 0); 2318 } 2319 #endif 2320 2321 simple_unlock(&pg->mdpage.pvh_slock); 2322 PMAP_HEAD_TO_MAP_UNLOCK(); 2323 } 2324 2325 /* 2326 * pmap_clean_page() 2327 * 2328 * This is a local function used to work out the best strategy to clean 2329 * a single page referenced by its entry in the PV table. It's used by 2330 * pmap_copy_page, pmap_zero page and maybe some others later on. 2331 * 2332 * Its policy is effectively: 2333 * o If there are no mappings, we don't bother doing anything with the cache. 2334 * o If there is one mapping, we clean just that page. 2335 * o If there are multiple mappings, we clean the entire cache. 2336 * 2337 * So that some functions can be further optimised, it returns 0 if it didn't 2338 * clean the entire cache, or 1 if it did. 2339 * 2340 * XXX One bug in this routine is that if the pv_entry has a single page 2341 * mapped at 0x00000000 a whole cache clean will be performed rather than 2342 * just the 1 page. Since this should not occur in everyday use and if it does 2343 * it will just result in not the most efficient clean for the page. 2344 */ 2345 #ifdef PMAP_CACHE_VIVT 2346 static int 2347 pmap_clean_page(struct pv_entry *pv, bool is_src) 2348 { 2349 pmap_t pm, pm_to_clean = NULL; 2350 struct pv_entry *npv; 2351 u_int cache_needs_cleaning = 0; 2352 u_int flags = 0; 2353 vaddr_t page_to_clean = 0; 2354 2355 if (pv == NULL) { 2356 /* nothing mapped in so nothing to flush */ 2357 return (0); 2358 } 2359 2360 /* 2361 * Since we flush the cache each time we change to a different 2362 * user vmspace, we only need to flush the page if it is in the 2363 * current pmap. 2364 */ 2365 pm = curproc->p_vmspace->vm_map.pmap; 2366 2367 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2368 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2369 flags |= npv->pv_flags; 2370 /* 2371 * The page is mapped non-cacheable in 2372 * this map. No need to flush the cache. 2373 */ 2374 if (npv->pv_flags & PVF_NC) { 2375 #ifdef DIAGNOSTIC 2376 if (cache_needs_cleaning) 2377 panic("pmap_clean_page: " 2378 "cache inconsistency"); 2379 #endif 2380 break; 2381 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2382 continue; 2383 if (cache_needs_cleaning) { 2384 page_to_clean = 0; 2385 break; 2386 } else { 2387 page_to_clean = npv->pv_va; 2388 pm_to_clean = npv->pv_pmap; 2389 } 2390 cache_needs_cleaning = 1; 2391 } 2392 } 2393 2394 if (page_to_clean) { 2395 if (PV_BEEN_EXECD(flags)) 2396 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2397 PAGE_SIZE); 2398 else 2399 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2400 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2401 } else if (cache_needs_cleaning) { 2402 if (PV_BEEN_EXECD(flags)) 2403 pmap_idcache_wbinv_all(pm); 2404 else 2405 pmap_dcache_wbinv_all(pm); 2406 return (1); 2407 } 2408 return (0); 2409 } 2410 #endif 2411 2412 #ifdef PMAP_CACHE_VIPT 2413 /* 2414 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2415 * right cache alias to make sure we flush the right stuff. 2416 */ 2417 void 2418 pmap_syncicache_page(struct vm_page *pg) 2419 { 2420 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2421 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2422 2423 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2424 pg, pg->mdpage.pvh_attrs)); 2425 /* 2426 * No need to clean the page if it's non-cached. 2427 */ 2428 if (pg->mdpage.pvh_attrs & PVF_NC) 2429 return; 2430 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2431 2432 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2433 /* 2434 * Set up a PTE with the right coloring to flush existing cache lines. 2435 */ 2436 *ptep = L2_S_PROTO | 2437 VM_PAGE_TO_PHYS(pg) 2438 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2439 | pte_l2_s_cache_mode; 2440 PTE_SYNC(ptep); 2441 2442 /* 2443 * Flush it. 2444 */ 2445 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2446 /* 2447 * Unmap the page. 2448 */ 2449 *ptep = 0; 2450 PTE_SYNC(ptep); 2451 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2452 2453 pg->mdpage.pvh_attrs |= PVF_EXEC; 2454 PMAPCOUNT(exec_synced); 2455 } 2456 2457 void 2458 pmap_flush_page(struct vm_page *pg, enum pmap_flush_op flush) 2459 { 2460 vsize_t va_offset, end_va; 2461 void (*cf)(vaddr_t, vsize_t); 2462 2463 if (arm_cache_prefer_mask == 0) 2464 return; 2465 2466 switch (flush) { 2467 case PMAP_FLUSH_PRIMARY: 2468 if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 2469 va_offset = 0; 2470 end_va = arm_cache_prefer_mask; 2471 pg->mdpage.pvh_attrs &= ~PVF_MULTCLR; 2472 PMAPCOUNT(vac_flush_lots); 2473 } else { 2474 va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2475 end_va = va_offset; 2476 PMAPCOUNT(vac_flush_one); 2477 } 2478 /* 2479 * Mark that the page is no longer dirty. 2480 */ 2481 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2482 cf = cpufuncs.cf_idcache_wbinv_range; 2483 break; 2484 case PMAP_FLUSH_SECONDARY: 2485 va_offset = 0; 2486 end_va = arm_cache_prefer_mask; 2487 cf = cpufuncs.cf_idcache_wbinv_range; 2488 pg->mdpage.pvh_attrs &= ~PVF_MULTCLR; 2489 PMAPCOUNT(vac_flush_lots); 2490 break; 2491 case PMAP_CLEAN_PRIMARY: 2492 va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2493 end_va = va_offset; 2494 cf = cpufuncs.cf_dcache_wb_range; 2495 /* 2496 * Mark that the page is no longer dirty. 2497 */ 2498 if ((pg->mdpage.pvh_attrs & PVF_DMOD) == 0) 2499 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2500 PMAPCOUNT(vac_clean_one); 2501 break; 2502 default: 2503 return; 2504 } 2505 2506 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2507 2508 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2509 pg, pg->mdpage.pvh_attrs)); 2510 2511 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2512 const size_t pte_offset = va_offset >> PGSHIFT; 2513 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2514 const pt_entry_t oldpte = *ptep; 2515 2516 if (flush == PMAP_FLUSH_SECONDARY 2517 && va_offset == (pg->mdpage.pvh_attrs & arm_cache_prefer_mask)) 2518 continue; 2519 2520 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2521 /* 2522 * Set up a PTE with the right coloring to flush 2523 * existing cache entries. 2524 */ 2525 *ptep = L2_S_PROTO 2526 | VM_PAGE_TO_PHYS(pg) 2527 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2528 | pte_l2_s_cache_mode; 2529 PTE_SYNC(ptep); 2530 2531 /* 2532 * Flush it. 2533 */ 2534 (*cf)(cdstp + va_offset, PAGE_SIZE); 2535 2536 /* 2537 * Restore the page table entry since we might have interrupted 2538 * pmap_zero_page or pmap_copy_page which was already using 2539 * this pte. 2540 */ 2541 *ptep = oldpte; 2542 PTE_SYNC(ptep); 2543 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2544 } 2545 } 2546 #endif /* PMAP_CACHE_VIPT */ 2547 2548 /* 2549 * Routine: pmap_page_remove 2550 * Function: 2551 * Removes this physical page from 2552 * all physical maps in which it resides. 2553 * Reflects back modify bits to the pager. 2554 */ 2555 static void 2556 pmap_page_remove(struct vm_page *pg) 2557 { 2558 struct l2_bucket *l2b; 2559 struct pv_entry *pv, *npv, **pvp; 2560 pmap_t pm, curpm; 2561 pt_entry_t *ptep, pte; 2562 bool flush; 2563 u_int flags; 2564 2565 NPDEBUG(PDB_FOLLOW, 2566 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2567 VM_PAGE_TO_PHYS(pg))); 2568 2569 PMAP_HEAD_TO_MAP_LOCK(); 2570 simple_lock(&pg->mdpage.pvh_slock); 2571 2572 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2573 if (pv == NULL) { 2574 #ifdef PMAP_CACHE_VIPT 2575 /* 2576 * We *know* the page contents are about to be replaced. 2577 * Discard the exec contents 2578 */ 2579 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2580 PMAPCOUNT(exec_discarded_page_protect); 2581 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2582 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2583 #endif 2584 simple_unlock(&pg->mdpage.pvh_slock); 2585 PMAP_HEAD_TO_MAP_UNLOCK(); 2586 return; 2587 } 2588 #ifdef PMAP_CACHE_VIPT 2589 KASSERT(pmap_is_page_colored_p(pg)); 2590 #endif 2591 2592 /* 2593 * Clear alias counts 2594 */ 2595 #ifdef PMAP_CACHE_VIVT 2596 pg->mdpage.k_mappings = 0; 2597 #endif 2598 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2599 2600 flush = false; 2601 flags = 0; 2602 curpm = curproc->p_vmspace->vm_map.pmap; 2603 2604 #ifdef PMAP_CACHE_VIVT 2605 pmap_clean_page(pv, false); 2606 #endif 2607 2608 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 2609 while (pv) { 2610 pm = pv->pv_pmap; 2611 npv = SLIST_NEXT(pv, pv_link); 2612 if (flush == false && (pm == curpm || pm == pmap_kernel())) 2613 flush = true; 2614 2615 if (pm == pmap_kernel()) { 2616 #ifdef PMAP_CACHE_VIPT 2617 /* 2618 * If this was unmanaged mapping, it must be preserved. 2619 * Move it back on the list and advance the end-of-list 2620 * pointer. 2621 */ 2622 if (pv->pv_flags & PVF_KENTRY) { 2623 *pvp = pv; 2624 pvp = &SLIST_NEXT(pv, pv_link); 2625 pv = npv; 2626 continue; 2627 } 2628 if (pv->pv_flags & PVF_WRITE) 2629 pg->mdpage.krw_mappings--; 2630 else 2631 pg->mdpage.kro_mappings--; 2632 #endif 2633 PMAPCOUNT(kernel_unmappings); 2634 } 2635 PMAPCOUNT(unmappings); 2636 2637 pmap_acquire_pmap_lock(pm); 2638 2639 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2640 KDASSERT(l2b != NULL); 2641 2642 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2643 pte = *ptep; 2644 2645 /* 2646 * Update statistics 2647 */ 2648 --pm->pm_stats.resident_count; 2649 2650 /* Wired bit */ 2651 if (pv->pv_flags & PVF_WIRED) 2652 --pm->pm_stats.wired_count; 2653 2654 flags |= pv->pv_flags; 2655 2656 /* 2657 * Invalidate the PTEs. 2658 */ 2659 *ptep = 0; 2660 PTE_SYNC_CURRENT(pm, ptep); 2661 pmap_free_l2_bucket(pm, l2b, 1); 2662 2663 pool_put(&pmap_pv_pool, pv); 2664 pv = npv; 2665 /* 2666 * if we reach the end of the list and there are still 2667 * mappings, they might be able to be cached now. 2668 */ 2669 if (pv == NULL) { 2670 *pvp = NULL; 2671 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 2672 pmap_vac_me_harder(pg, pm, 0); 2673 } 2674 pmap_release_pmap_lock(pm); 2675 } 2676 #ifdef PMAP_CACHE_VIPT 2677 /* 2678 * Its EXEC cache is now gone. 2679 */ 2680 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2681 PMAPCOUNT(exec_discarded_page_protect); 2682 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2683 KASSERT(pg->mdpage.urw_mappings == 0); 2684 KASSERT(pg->mdpage.uro_mappings == 0); 2685 if (pg->mdpage.krw_mappings == 0) 2686 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2687 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2688 #endif 2689 simple_unlock(&pg->mdpage.pvh_slock); 2690 PMAP_HEAD_TO_MAP_UNLOCK(); 2691 2692 if (flush) { 2693 /* 2694 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2695 * would need a subsequent call to pmap_update() to ensure 2696 * curpm->pm_cstate.cs_all is reset. Our callers are not 2697 * required to do that (see pmap(9)), so we can't modify 2698 * the current pmap's state. 2699 */ 2700 if (PV_BEEN_EXECD(flags)) 2701 cpu_tlb_flushID(); 2702 else 2703 cpu_tlb_flushD(); 2704 } 2705 cpu_cpwait(); 2706 } 2707 2708 /* 2709 * pmap_t pmap_create(void) 2710 * 2711 * Create a new pmap structure from scratch. 2712 */ 2713 pmap_t 2714 pmap_create(void) 2715 { 2716 pmap_t pm; 2717 2718 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2719 2720 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2721 pm->pm_stats.wired_count = 0; 2722 pm->pm_stats.resident_count = 1; 2723 pm->pm_cstate.cs_all = 0; 2724 pmap_alloc_l1(pm); 2725 2726 /* 2727 * Note: The pool cache ensures that the pm_l2[] array is already 2728 * initialised to zero. 2729 */ 2730 2731 pmap_pinit(pm); 2732 2733 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2734 2735 return (pm); 2736 } 2737 2738 /* 2739 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2740 * int flags) 2741 * 2742 * Insert the given physical page (p) at 2743 * the specified virtual address (v) in the 2744 * target physical map with the protection requested. 2745 * 2746 * NB: This is the only routine which MAY NOT lazy-evaluate 2747 * or lose information. That is, this routine must actually 2748 * insert this page into the given map NOW. 2749 */ 2750 int 2751 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 2752 { 2753 struct l2_bucket *l2b; 2754 struct vm_page *pg, *opg; 2755 struct pv_entry *pve; 2756 pt_entry_t *ptep, npte, opte; 2757 u_int nflags; 2758 u_int oflags; 2759 2760 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2761 2762 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2763 KDASSERT(((va | pa) & PGOFSET) == 0); 2764 2765 /* 2766 * Get a pointer to the page. Later on in this function, we 2767 * test for a managed page by checking pg != NULL. 2768 */ 2769 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2770 2771 nflags = 0; 2772 if (prot & VM_PROT_WRITE) 2773 nflags |= PVF_WRITE; 2774 if (prot & VM_PROT_EXECUTE) 2775 nflags |= PVF_EXEC; 2776 if (flags & PMAP_WIRED) 2777 nflags |= PVF_WIRED; 2778 2779 PMAP_MAP_TO_HEAD_LOCK(); 2780 pmap_acquire_pmap_lock(pm); 2781 2782 /* 2783 * Fetch the L2 bucket which maps this page, allocating one if 2784 * necessary for user pmaps. 2785 */ 2786 if (pm == pmap_kernel()) 2787 l2b = pmap_get_l2_bucket(pm, va); 2788 else 2789 l2b = pmap_alloc_l2_bucket(pm, va); 2790 if (l2b == NULL) { 2791 if (flags & PMAP_CANFAIL) { 2792 pmap_release_pmap_lock(pm); 2793 PMAP_MAP_TO_HEAD_UNLOCK(); 2794 return (ENOMEM); 2795 } 2796 panic("pmap_enter: failed to allocate L2 bucket"); 2797 } 2798 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2799 opte = *ptep; 2800 npte = pa; 2801 oflags = 0; 2802 2803 if (opte) { 2804 /* 2805 * There is already a mapping at this address. 2806 * If the physical address is different, lookup the 2807 * vm_page. 2808 */ 2809 if (l2pte_pa(opte) != pa) 2810 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2811 else 2812 opg = pg; 2813 } else 2814 opg = NULL; 2815 2816 if (pg) { 2817 /* 2818 * This is to be a managed mapping. 2819 */ 2820 if ((flags & VM_PROT_ALL) || 2821 (pg->mdpage.pvh_attrs & PVF_REF)) { 2822 /* 2823 * - The access type indicates that we don't need 2824 * to do referenced emulation. 2825 * OR 2826 * - The physical page has already been referenced 2827 * so no need to re-do referenced emulation here. 2828 */ 2829 npte |= L2_S_PROTO; 2830 2831 nflags |= PVF_REF; 2832 2833 if ((prot & VM_PROT_WRITE) != 0 && 2834 ((flags & VM_PROT_WRITE) != 0 || 2835 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2836 /* 2837 * This is a writable mapping, and the 2838 * page's mod state indicates it has 2839 * already been modified. Make it 2840 * writable from the outset. 2841 */ 2842 npte |= L2_S_PROT_W; 2843 nflags |= PVF_MOD; 2844 } 2845 } else { 2846 /* 2847 * Need to do page referenced emulation. 2848 */ 2849 npte |= L2_TYPE_INV; 2850 } 2851 2852 npte |= pte_l2_s_cache_mode; 2853 2854 if (pg == opg) { 2855 /* 2856 * We're changing the attrs of an existing mapping. 2857 */ 2858 simple_lock(&pg->mdpage.pvh_slock); 2859 oflags = pmap_modify_pv(pg, pm, va, 2860 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2861 PVF_MOD | PVF_REF, nflags); 2862 simple_unlock(&pg->mdpage.pvh_slock); 2863 2864 #ifdef PMAP_CACHE_VIVT 2865 /* 2866 * We may need to flush the cache if we're 2867 * doing rw-ro... 2868 */ 2869 if (pm->pm_cstate.cs_cache_d && 2870 (oflags & PVF_NC) == 0 && 2871 (opte & L2_S_PROT_W) != 0 && 2872 (prot & VM_PROT_WRITE) == 0) 2873 cpu_dcache_wb_range(va, PAGE_SIZE); 2874 #endif 2875 } else { 2876 /* 2877 * New mapping, or changing the backing page 2878 * of an existing mapping. 2879 */ 2880 if (opg) { 2881 /* 2882 * Replacing an existing mapping with a new one. 2883 * It is part of our managed memory so we 2884 * must remove it from the PV list 2885 */ 2886 simple_lock(&opg->mdpage.pvh_slock); 2887 pve = pmap_remove_pv(opg, pm, va, 0); 2888 pmap_vac_me_harder(opg, pm, 0); 2889 simple_unlock(&opg->mdpage.pvh_slock); 2890 oflags = pve->pv_flags; 2891 2892 #ifdef PMAP_CACHE_VIVT 2893 /* 2894 * If the old mapping was valid (ref/mod 2895 * emulation creates 'invalid' mappings 2896 * initially) then make sure to frob 2897 * the cache. 2898 */ 2899 if ((oflags & PVF_NC) == 0 && 2900 l2pte_valid(opte)) { 2901 if (PV_BEEN_EXECD(oflags)) { 2902 pmap_idcache_wbinv_range(pm, va, 2903 PAGE_SIZE); 2904 } else 2905 if (PV_BEEN_REFD(oflags)) { 2906 pmap_dcache_wb_range(pm, va, 2907 PAGE_SIZE, true, 2908 (oflags & PVF_WRITE) == 0); 2909 } 2910 } 2911 #endif 2912 } else 2913 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2914 if ((flags & PMAP_CANFAIL) == 0) 2915 panic("pmap_enter: no pv entries"); 2916 2917 if (pm != pmap_kernel()) 2918 pmap_free_l2_bucket(pm, l2b, 0); 2919 pmap_release_pmap_lock(pm); 2920 PMAP_MAP_TO_HEAD_UNLOCK(); 2921 NPDEBUG(PDB_ENTER, 2922 printf("pmap_enter: ENOMEM\n")); 2923 return (ENOMEM); 2924 } 2925 2926 pmap_enter_pv(pg, pve, pm, va, nflags); 2927 } 2928 } else { 2929 /* 2930 * We're mapping an unmanaged page. 2931 * These are always readable, and possibly writable, from 2932 * the get go as we don't need to track ref/mod status. 2933 */ 2934 npte |= L2_S_PROTO; 2935 if (prot & VM_PROT_WRITE) 2936 npte |= L2_S_PROT_W; 2937 2938 /* 2939 * Make sure the vector table is mapped cacheable 2940 */ 2941 if (pm != pmap_kernel() && va == vector_page) 2942 npte |= pte_l2_s_cache_mode; 2943 2944 if (opg) { 2945 /* 2946 * Looks like there's an existing 'managed' mapping 2947 * at this address. 2948 */ 2949 simple_lock(&opg->mdpage.pvh_slock); 2950 pve = pmap_remove_pv(opg, pm, va, 0); 2951 pmap_vac_me_harder(opg, pm, 0); 2952 simple_unlock(&opg->mdpage.pvh_slock); 2953 oflags = pve->pv_flags; 2954 2955 #ifdef PMAP_CACHE_VIVT 2956 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2957 if (PV_BEEN_EXECD(oflags)) 2958 pmap_idcache_wbinv_range(pm, va, 2959 PAGE_SIZE); 2960 else 2961 if (PV_BEEN_REFD(oflags)) 2962 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2963 true, (oflags & PVF_WRITE) == 0); 2964 } 2965 #endif 2966 pool_put(&pmap_pv_pool, pve); 2967 } 2968 } 2969 2970 /* 2971 * Make sure userland mappings get the right permissions 2972 */ 2973 if (pm != pmap_kernel() && va != vector_page) 2974 npte |= L2_S_PROT_U; 2975 2976 /* 2977 * Keep the stats up to date 2978 */ 2979 if (opte == 0) { 2980 l2b->l2b_occupancy++; 2981 pm->pm_stats.resident_count++; 2982 } 2983 2984 NPDEBUG(PDB_ENTER, 2985 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2986 2987 /* 2988 * If this is just a wiring change, the two PTEs will be 2989 * identical, so there's no need to update the page table. 2990 */ 2991 if (npte != opte) { 2992 bool is_cached = pmap_is_cached(pm); 2993 2994 *ptep = npte; 2995 if (is_cached) { 2996 /* 2997 * We only need to frob the cache/tlb if this pmap 2998 * is current 2999 */ 3000 PTE_SYNC(ptep); 3001 if (va != vector_page && l2pte_valid(npte)) { 3002 /* 3003 * This mapping is likely to be accessed as 3004 * soon as we return to userland. Fix up the 3005 * L1 entry to avoid taking another 3006 * page/domain fault. 3007 */ 3008 pd_entry_t *pl1pd, l1pd; 3009 3010 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3011 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3012 L1_C_PROTO; 3013 if (*pl1pd != l1pd) { 3014 *pl1pd = l1pd; 3015 PTE_SYNC(pl1pd); 3016 } 3017 } 3018 } 3019 3020 if (PV_BEEN_EXECD(oflags)) 3021 pmap_tlb_flushID_SE(pm, va); 3022 else 3023 if (PV_BEEN_REFD(oflags)) 3024 pmap_tlb_flushD_SE(pm, va); 3025 3026 NPDEBUG(PDB_ENTER, 3027 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3028 is_cached, pm->pm_cstate.cs_all)); 3029 3030 if (pg != NULL) { 3031 simple_lock(&pg->mdpage.pvh_slock); 3032 pmap_vac_me_harder(pg, pm, va); 3033 simple_unlock(&pg->mdpage.pvh_slock); 3034 } 3035 } 3036 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3037 if (pg) { 3038 simple_lock(&pg->mdpage.pvh_slock); 3039 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3040 KASSERT(((pg->mdpage.pvh_attrs & PVF_WRITE) == 0) == (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0)); 3041 simple_unlock(&pg->mdpage.pvh_slock); 3042 } 3043 #endif 3044 3045 pmap_release_pmap_lock(pm); 3046 PMAP_MAP_TO_HEAD_UNLOCK(); 3047 3048 return (0); 3049 } 3050 3051 /* 3052 * pmap_remove() 3053 * 3054 * pmap_remove is responsible for nuking a number of mappings for a range 3055 * of virtual address space in the current pmap. To do this efficiently 3056 * is interesting, because in a number of cases a wide virtual address 3057 * range may be supplied that contains few actual mappings. So, the 3058 * optimisations are: 3059 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3060 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3061 * maybe do just a partial cache clean. This path of execution is 3062 * complicated by the fact that the cache must be flushed _before_ 3063 * the PTE is nuked, being a VAC :-) 3064 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3065 * all invalidations until pmap_update(), since pmap_remove_all() has 3066 * already flushed the cache. 3067 * 4. Maybe later fast-case a single page, but I don't think this is 3068 * going to make _that_ much difference overall. 3069 */ 3070 3071 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3072 3073 void 3074 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 3075 { 3076 struct l2_bucket *l2b; 3077 vaddr_t next_bucket; 3078 pt_entry_t *ptep; 3079 u_int cleanlist_idx, total, cnt; 3080 struct { 3081 vaddr_t va; 3082 pt_entry_t *ptep; 3083 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3084 u_int mappings, is_exec, is_refd; 3085 3086 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3087 "eva=%08lx\n", pm, sva, eva)); 3088 3089 /* 3090 * we lock in the pmap => pv_head direction 3091 */ 3092 PMAP_MAP_TO_HEAD_LOCK(); 3093 pmap_acquire_pmap_lock(pm); 3094 3095 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3096 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3097 if (pm->pm_cstate.cs_tlb == 0) 3098 pm->pm_remove_all = true; 3099 } else 3100 cleanlist_idx = 0; 3101 3102 total = 0; 3103 3104 while (sva < eva) { 3105 /* 3106 * Do one L2 bucket's worth at a time. 3107 */ 3108 next_bucket = L2_NEXT_BUCKET(sva); 3109 if (next_bucket > eva) 3110 next_bucket = eva; 3111 3112 l2b = pmap_get_l2_bucket(pm, sva); 3113 if (l2b == NULL) { 3114 sva = next_bucket; 3115 continue; 3116 } 3117 3118 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3119 3120 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3121 struct vm_page *pg; 3122 pt_entry_t pte; 3123 paddr_t pa; 3124 3125 pte = *ptep; 3126 3127 if (pte == 0) { 3128 /* Nothing here, move along */ 3129 continue; 3130 } 3131 3132 pa = l2pte_pa(pte); 3133 is_exec = 0; 3134 is_refd = 1; 3135 3136 /* 3137 * Update flags. In a number of circumstances, 3138 * we could cluster a lot of these and do a 3139 * number of sequential pages in one go. 3140 */ 3141 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3142 struct pv_entry *pve; 3143 simple_lock(&pg->mdpage.pvh_slock); 3144 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 3145 pmap_vac_me_harder(pg, pm, 0); 3146 simple_unlock(&pg->mdpage.pvh_slock); 3147 if (pve != NULL) { 3148 if (pm->pm_remove_all == false) { 3149 is_exec = 3150 PV_BEEN_EXECD(pve->pv_flags); 3151 is_refd = 3152 PV_BEEN_REFD(pve->pv_flags); 3153 } 3154 pool_put(&pmap_pv_pool, pve); 3155 } else 3156 if (skip_wired) { 3157 /* The mapping is wired. Skip it */ 3158 continue; 3159 } 3160 } else 3161 if (skip_wired) { 3162 /* Unmanaged pages are always wired. */ 3163 continue; 3164 } 3165 3166 mappings++; 3167 3168 if (!l2pte_valid(pte)) { 3169 /* 3170 * Ref/Mod emulation is still active for this 3171 * mapping, therefore it is has not yet been 3172 * accessed. No need to frob the cache/tlb. 3173 */ 3174 *ptep = 0; 3175 PTE_SYNC_CURRENT(pm, ptep); 3176 continue; 3177 } 3178 3179 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3180 /* Add to the clean list. */ 3181 cleanlist[cleanlist_idx].ptep = ptep; 3182 cleanlist[cleanlist_idx].va = 3183 sva | (is_exec & 1); 3184 cleanlist_idx++; 3185 } else 3186 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3187 /* Nuke everything if needed. */ 3188 #ifdef PMAP_CACHE_VIVT 3189 pmap_idcache_wbinv_all(pm); 3190 #endif 3191 pmap_tlb_flushID(pm); 3192 3193 /* 3194 * Roll back the previous PTE list, 3195 * and zero out the current PTE. 3196 */ 3197 for (cnt = 0; 3198 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3199 *cleanlist[cnt].ptep = 0; 3200 PTE_SYNC(cleanlist[cnt].ptep); 3201 } 3202 *ptep = 0; 3203 PTE_SYNC(ptep); 3204 cleanlist_idx++; 3205 pm->pm_remove_all = true; 3206 } else { 3207 *ptep = 0; 3208 PTE_SYNC(ptep); 3209 if (pm->pm_remove_all == false) { 3210 if (is_exec) 3211 pmap_tlb_flushID_SE(pm, sva); 3212 else 3213 if (is_refd) 3214 pmap_tlb_flushD_SE(pm, sva); 3215 } 3216 } 3217 } 3218 3219 /* 3220 * Deal with any left overs 3221 */ 3222 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3223 total += cleanlist_idx; 3224 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3225 if (pm->pm_cstate.cs_all != 0) { 3226 vaddr_t clva = cleanlist[cnt].va & ~1; 3227 if (cleanlist[cnt].va & 1) { 3228 #ifdef PMAP_CACHE_VIVT 3229 pmap_idcache_wbinv_range(pm, 3230 clva, PAGE_SIZE); 3231 #endif 3232 pmap_tlb_flushID_SE(pm, clva); 3233 } else { 3234 #ifdef PMAP_CACHE_VIVT 3235 pmap_dcache_wb_range(pm, 3236 clva, PAGE_SIZE, true, 3237 false); 3238 #endif 3239 pmap_tlb_flushD_SE(pm, clva); 3240 } 3241 } 3242 *cleanlist[cnt].ptep = 0; 3243 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3244 } 3245 3246 /* 3247 * If it looks like we're removing a whole bunch 3248 * of mappings, it's faster to just write-back 3249 * the whole cache now and defer TLB flushes until 3250 * pmap_update() is called. 3251 */ 3252 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3253 cleanlist_idx = 0; 3254 else { 3255 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3256 #ifdef PMAP_CACHE_VIVT 3257 pmap_idcache_wbinv_all(pm); 3258 #endif 3259 pm->pm_remove_all = true; 3260 } 3261 } 3262 3263 pmap_free_l2_bucket(pm, l2b, mappings); 3264 pm->pm_stats.resident_count -= mappings; 3265 } 3266 3267 pmap_release_pmap_lock(pm); 3268 PMAP_MAP_TO_HEAD_UNLOCK(); 3269 } 3270 3271 #ifdef PMAP_CACHE_VIPT 3272 static struct pv_entry * 3273 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3274 { 3275 struct pv_entry *pv; 3276 3277 simple_lock(&pg->mdpage.pvh_slock); 3278 KASSERT(pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 3279 KASSERT((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3280 3281 pv = pmap_remove_pv(pg, pmap_kernel(), va, false); 3282 KASSERT(pv); 3283 KASSERT(pv->pv_flags & PVF_KENTRY); 3284 3285 /* 3286 * If we are removing a writeable mapping to a cached exec page, 3287 * if it's the last mapping then clear it execness other sync 3288 * the page to the icache. 3289 */ 3290 if ((pg->mdpage.pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3291 && (pv->pv_flags & PVF_WRITE) != 0) { 3292 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 3293 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 3294 PMAPCOUNT(exec_discarded_kremove); 3295 } else { 3296 pmap_syncicache_page(pg); 3297 PMAPCOUNT(exec_synced_kremove); 3298 } 3299 } 3300 pmap_vac_me_harder(pg, pmap_kernel(), 0); 3301 simple_unlock(&pg->mdpage.pvh_slock); 3302 3303 return pv; 3304 } 3305 #endif /* PMAP_CACHE_VIPT */ 3306 3307 /* 3308 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3309 * 3310 * We assume there is already sufficient KVM space available 3311 * to do this, as we can't allocate L2 descriptor tables/metadata 3312 * from here. 3313 */ 3314 void 3315 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 3316 { 3317 struct l2_bucket *l2b; 3318 pt_entry_t *ptep, opte; 3319 #ifdef PMAP_CACHE_VIVT 3320 struct vm_page *pg = (prot & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3321 #endif 3322 #ifdef PMAP_CACHE_VIPT 3323 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3324 struct vm_page *opg; 3325 struct pv_entry *pv = NULL; 3326 #endif 3327 3328 NPDEBUG(PDB_KENTER, 3329 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3330 va, pa, prot)); 3331 3332 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3333 KDASSERT(l2b != NULL); 3334 3335 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3336 opte = *ptep; 3337 3338 if (opte == 0) { 3339 PMAPCOUNT(kenter_mappings); 3340 l2b->l2b_occupancy++; 3341 } else { 3342 PMAPCOUNT(kenter_remappings); 3343 #ifdef PMAP_CACHE_VIPT 3344 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3345 if (opg) { 3346 KASSERT(opg != pg); 3347 KASSERT((opg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3348 KASSERT((prot & PMAP_KMPAGE) == 0); 3349 simple_lock(&opg->mdpage.pvh_slock); 3350 pv = pmap_kremove_pg(opg, va); 3351 simple_unlock(&opg->mdpage.pvh_slock); 3352 } 3353 #endif 3354 if (l2pte_valid(opte)) { 3355 #ifdef PMAP_CACHE_VIVT 3356 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3357 #endif 3358 cpu_tlb_flushD_SE(va); 3359 cpu_cpwait(); 3360 } 3361 } 3362 3363 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3364 pte_l2_s_cache_mode; 3365 PTE_SYNC(ptep); 3366 3367 if (pg) { 3368 if (prot & PMAP_KMPAGE) { 3369 simple_lock(&pg->mdpage.pvh_slock); 3370 KASSERT(pg->mdpage.urw_mappings == 0); 3371 KASSERT(pg->mdpage.uro_mappings == 0); 3372 KASSERT(pg->mdpage.krw_mappings == 0); 3373 KASSERT(pg->mdpage.kro_mappings == 0); 3374 #ifdef PMAP_CACHE_VIPT 3375 KASSERT(pv == NULL); 3376 KASSERT((va & PVF_COLORED) == 0); 3377 KASSERT((pg->mdpage.pvh_attrs & PVF_NC) == 0); 3378 /* if there is a color conflict, evict from cache. */ 3379 if (pmap_is_page_colored_p(pg) 3380 && ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask)) { 3381 PMAPCOUNT(vac_color_change); 3382 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 3383 } 3384 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 3385 pg->mdpage.pvh_attrs |= PVF_KMPAGE 3386 | PVF_COLORED | PVF_DIRTY 3387 | (va & arm_cache_prefer_mask); 3388 #endif 3389 #ifdef PMAP_CACHE_VIVT 3390 pg->mdpage.pvh_attrs |= PVF_KMPAGE; 3391 #endif 3392 pmap_kmpages++; 3393 simple_unlock(&pg->mdpage.pvh_slock); 3394 #ifdef PMAP_CACHE_VIPT 3395 } else { 3396 if (pv == NULL) { 3397 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3398 KASSERT(pv != NULL); 3399 } 3400 pmap_enter_pv(pg, pv, pmap_kernel(), va, 3401 PVF_WIRED | PVF_KENTRY 3402 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3403 if ((prot & VM_PROT_WRITE) 3404 && !(pg->mdpage.pvh_attrs & PVF_NC)) 3405 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3406 KASSERT((prot & VM_PROT_WRITE) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3407 simple_lock(&pg->mdpage.pvh_slock); 3408 pmap_vac_me_harder(pg, pmap_kernel(), va); 3409 simple_unlock(&pg->mdpage.pvh_slock); 3410 #endif 3411 } 3412 #ifdef PMAP_CACHE_VIPT 3413 } else { 3414 if (pv != NULL) 3415 pool_put(&pmap_pv_pool, pv); 3416 #endif 3417 } 3418 } 3419 3420 void 3421 pmap_kremove(vaddr_t va, vsize_t len) 3422 { 3423 struct l2_bucket *l2b; 3424 pt_entry_t *ptep, *sptep, opte; 3425 vaddr_t next_bucket, eva; 3426 u_int mappings; 3427 struct vm_page *opg; 3428 3429 PMAPCOUNT(kenter_unmappings); 3430 3431 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3432 va, len)); 3433 3434 eva = va + len; 3435 3436 while (va < eva) { 3437 next_bucket = L2_NEXT_BUCKET(va); 3438 if (next_bucket > eva) 3439 next_bucket = eva; 3440 3441 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3442 KDASSERT(l2b != NULL); 3443 3444 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3445 mappings = 0; 3446 3447 while (va < next_bucket) { 3448 opte = *ptep; 3449 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3450 if (opg) { 3451 if (opg->mdpage.pvh_attrs & PVF_KMPAGE) { 3452 simple_lock(&opg->mdpage.pvh_slock); 3453 KASSERT(opg->mdpage.urw_mappings == 0); 3454 KASSERT(opg->mdpage.uro_mappings == 0); 3455 KASSERT(opg->mdpage.krw_mappings == 0); 3456 KASSERT(opg->mdpage.kro_mappings == 0); 3457 opg->mdpage.pvh_attrs &= ~PVF_KMPAGE; 3458 #ifdef PMAP_CACHE_VIPT 3459 opg->mdpage.pvh_attrs &= ~PVF_WRITE; 3460 #endif 3461 pmap_kmpages--; 3462 simple_unlock(&opg->mdpage.pvh_slock); 3463 #ifdef PMAP_CACHE_VIPT 3464 } else { 3465 pool_put(&pmap_pv_pool, 3466 pmap_kremove_pg(opg, va)); 3467 #endif 3468 } 3469 } 3470 if (l2pte_valid(opte)) { 3471 #ifdef PMAP_CACHE_VIVT 3472 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3473 #endif 3474 cpu_tlb_flushD_SE(va); 3475 } 3476 if (opte) { 3477 *ptep = 0; 3478 mappings++; 3479 } 3480 va += PAGE_SIZE; 3481 ptep++; 3482 } 3483 KDASSERT(mappings <= l2b->l2b_occupancy); 3484 l2b->l2b_occupancy -= mappings; 3485 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3486 } 3487 cpu_cpwait(); 3488 } 3489 3490 bool 3491 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3492 { 3493 struct l2_dtable *l2; 3494 pd_entry_t *pl1pd, l1pd; 3495 pt_entry_t *ptep, pte; 3496 paddr_t pa; 3497 u_int l1idx; 3498 3499 pmap_acquire_pmap_lock(pm); 3500 3501 l1idx = L1_IDX(va); 3502 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3503 l1pd = *pl1pd; 3504 3505 if (l1pte_section_p(l1pd)) { 3506 /* 3507 * These should only happen for pmap_kernel() 3508 */ 3509 KDASSERT(pm == pmap_kernel()); 3510 pmap_release_pmap_lock(pm); 3511 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3512 } else { 3513 /* 3514 * Note that we can't rely on the validity of the L1 3515 * descriptor as an indication that a mapping exists. 3516 * We have to look it up in the L2 dtable. 3517 */ 3518 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3519 3520 if (l2 == NULL || 3521 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3522 pmap_release_pmap_lock(pm); 3523 return false; 3524 } 3525 3526 ptep = &ptep[l2pte_index(va)]; 3527 pte = *ptep; 3528 pmap_release_pmap_lock(pm); 3529 3530 if (pte == 0) 3531 return false; 3532 3533 switch (pte & L2_TYPE_MASK) { 3534 case L2_TYPE_L: 3535 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3536 break; 3537 3538 default: 3539 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3540 break; 3541 } 3542 } 3543 3544 if (pap != NULL) 3545 *pap = pa; 3546 3547 return true; 3548 } 3549 3550 void 3551 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3552 { 3553 struct l2_bucket *l2b; 3554 pt_entry_t *ptep, pte; 3555 vaddr_t next_bucket; 3556 u_int flags; 3557 u_int clr_mask; 3558 int flush; 3559 3560 NPDEBUG(PDB_PROTECT, 3561 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3562 pm, sva, eva, prot)); 3563 3564 if ((prot & VM_PROT_READ) == 0) { 3565 pmap_remove(pm, sva, eva); 3566 return; 3567 } 3568 3569 if (prot & VM_PROT_WRITE) { 3570 /* 3571 * If this is a read->write transition, just ignore it and let 3572 * uvm_fault() take care of it later. 3573 */ 3574 return; 3575 } 3576 3577 PMAP_MAP_TO_HEAD_LOCK(); 3578 pmap_acquire_pmap_lock(pm); 3579 3580 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3581 flags = 0; 3582 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3583 3584 while (sva < eva) { 3585 next_bucket = L2_NEXT_BUCKET(sva); 3586 if (next_bucket > eva) 3587 next_bucket = eva; 3588 3589 l2b = pmap_get_l2_bucket(pm, sva); 3590 if (l2b == NULL) { 3591 sva = next_bucket; 3592 continue; 3593 } 3594 3595 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3596 3597 while (sva < next_bucket) { 3598 pte = *ptep; 3599 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3600 struct vm_page *pg; 3601 u_int f; 3602 3603 #ifdef PMAP_CACHE_VIVT 3604 /* 3605 * OK, at this point, we know we're doing 3606 * write-protect operation. If the pmap is 3607 * active, write-back the page. 3608 */ 3609 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3610 false, false); 3611 #endif 3612 3613 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3614 pte &= ~L2_S_PROT_W; 3615 *ptep = pte; 3616 PTE_SYNC(ptep); 3617 3618 if (pg != NULL) { 3619 simple_lock(&pg->mdpage.pvh_slock); 3620 f = pmap_modify_pv(pg, pm, sva, 3621 clr_mask, 0); 3622 pmap_vac_me_harder(pg, pm, sva); 3623 simple_unlock(&pg->mdpage.pvh_slock); 3624 } else 3625 f = PVF_REF | PVF_EXEC; 3626 3627 if (flush >= 0) { 3628 flush++; 3629 flags |= f; 3630 } else 3631 if (PV_BEEN_EXECD(f)) 3632 pmap_tlb_flushID_SE(pm, sva); 3633 else 3634 if (PV_BEEN_REFD(f)) 3635 pmap_tlb_flushD_SE(pm, sva); 3636 } 3637 3638 sva += PAGE_SIZE; 3639 ptep++; 3640 } 3641 } 3642 3643 pmap_release_pmap_lock(pm); 3644 PMAP_MAP_TO_HEAD_UNLOCK(); 3645 3646 if (flush) { 3647 if (PV_BEEN_EXECD(flags)) 3648 pmap_tlb_flushID(pm); 3649 else 3650 if (PV_BEEN_REFD(flags)) 3651 pmap_tlb_flushD(pm); 3652 } 3653 } 3654 3655 void 3656 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3657 { 3658 struct l2_bucket *l2b; 3659 pt_entry_t *ptep; 3660 vaddr_t next_bucket; 3661 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3662 3663 NPDEBUG(PDB_EXEC, 3664 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3665 pm, sva, eva)); 3666 3667 PMAP_MAP_TO_HEAD_LOCK(); 3668 pmap_acquire_pmap_lock(pm); 3669 3670 while (sva < eva) { 3671 next_bucket = L2_NEXT_BUCKET(sva); 3672 if (next_bucket > eva) 3673 next_bucket = eva; 3674 3675 l2b = pmap_get_l2_bucket(pm, sva); 3676 if (l2b == NULL) { 3677 sva = next_bucket; 3678 continue; 3679 } 3680 3681 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3682 sva < next_bucket; 3683 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3684 if (l2pte_valid(*ptep)) { 3685 cpu_icache_sync_range(sva, 3686 min(page_size, eva - sva)); 3687 } 3688 } 3689 } 3690 3691 pmap_release_pmap_lock(pm); 3692 PMAP_MAP_TO_HEAD_UNLOCK(); 3693 } 3694 3695 void 3696 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3697 { 3698 3699 NPDEBUG(PDB_PROTECT, 3700 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3701 pg, VM_PAGE_TO_PHYS(pg), prot)); 3702 3703 switch(prot) { 3704 return; 3705 case VM_PROT_READ|VM_PROT_WRITE: 3706 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3707 pmap_clearbit(pg, PVF_EXEC); 3708 break; 3709 #endif 3710 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3711 break; 3712 3713 case VM_PROT_READ: 3714 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3715 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3716 break; 3717 #endif 3718 case VM_PROT_READ|VM_PROT_EXECUTE: 3719 pmap_clearbit(pg, PVF_WRITE); 3720 break; 3721 3722 default: 3723 pmap_page_remove(pg); 3724 break; 3725 } 3726 } 3727 3728 /* 3729 * pmap_clear_modify: 3730 * 3731 * Clear the "modified" attribute for a page. 3732 */ 3733 bool 3734 pmap_clear_modify(struct vm_page *pg) 3735 { 3736 bool rv; 3737 3738 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3739 rv = true; 3740 #ifdef PMAP_CACHE_VIPT 3741 /* 3742 * If we are going to clear the modified bit and there are 3743 * no other modified bits set, flush the page to memory and 3744 * mark it clean. 3745 */ 3746 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3747 pmap_flush_page(pg, PMAP_CLEAN_PRIMARY); 3748 #endif 3749 pmap_clearbit(pg, PVF_MOD); 3750 } else 3751 rv = false; 3752 3753 return (rv); 3754 } 3755 3756 /* 3757 * pmap_clear_reference: 3758 * 3759 * Clear the "referenced" attribute for a page. 3760 */ 3761 bool 3762 pmap_clear_reference(struct vm_page *pg) 3763 { 3764 bool rv; 3765 3766 if (pg->mdpage.pvh_attrs & PVF_REF) { 3767 rv = true; 3768 pmap_clearbit(pg, PVF_REF); 3769 } else 3770 rv = false; 3771 3772 return (rv); 3773 } 3774 3775 /* 3776 * pmap_is_modified: 3777 * 3778 * Test if a page has the "modified" attribute. 3779 */ 3780 /* See <arm/arm32/pmap.h> */ 3781 3782 /* 3783 * pmap_is_referenced: 3784 * 3785 * Test if a page has the "referenced" attribute. 3786 */ 3787 /* See <arm/arm32/pmap.h> */ 3788 3789 int 3790 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3791 { 3792 struct l2_dtable *l2; 3793 struct l2_bucket *l2b; 3794 pd_entry_t *pl1pd, l1pd; 3795 pt_entry_t *ptep, pte; 3796 paddr_t pa; 3797 u_int l1idx; 3798 int rv = 0; 3799 3800 PMAP_MAP_TO_HEAD_LOCK(); 3801 pmap_acquire_pmap_lock(pm); 3802 3803 l1idx = L1_IDX(va); 3804 3805 /* 3806 * If there is no l2_dtable for this address, then the process 3807 * has no business accessing it. 3808 * 3809 * Note: This will catch userland processes trying to access 3810 * kernel addresses. 3811 */ 3812 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3813 if (l2 == NULL) 3814 goto out; 3815 3816 /* 3817 * Likewise if there is no L2 descriptor table 3818 */ 3819 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3820 if (l2b->l2b_kva == NULL) 3821 goto out; 3822 3823 /* 3824 * Check the PTE itself. 3825 */ 3826 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3827 pte = *ptep; 3828 if (pte == 0) 3829 goto out; 3830 3831 /* 3832 * Catch a userland access to the vector page mapped at 0x0 3833 */ 3834 if (user && (pte & L2_S_PROT_U) == 0) 3835 goto out; 3836 3837 pa = l2pte_pa(pte); 3838 3839 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3840 /* 3841 * This looks like a good candidate for "page modified" 3842 * emulation... 3843 */ 3844 struct pv_entry *pv; 3845 struct vm_page *pg; 3846 3847 /* Extract the physical address of the page */ 3848 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3849 goto out; 3850 3851 /* Get the current flags for this page. */ 3852 simple_lock(&pg->mdpage.pvh_slock); 3853 3854 pv = pmap_find_pv(pg, pm, va); 3855 if (pv == NULL) { 3856 simple_unlock(&pg->mdpage.pvh_slock); 3857 goto out; 3858 } 3859 3860 /* 3861 * Do the flags say this page is writable? If not then it 3862 * is a genuine write fault. If yes then the write fault is 3863 * our fault as we did not reflect the write access in the 3864 * PTE. Now we know a write has occurred we can correct this 3865 * and also set the modified bit 3866 */ 3867 if ((pv->pv_flags & PVF_WRITE) == 0) { 3868 simple_unlock(&pg->mdpage.pvh_slock); 3869 goto out; 3870 } 3871 3872 NPDEBUG(PDB_FOLLOW, 3873 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3874 pm, va, VM_PAGE_TO_PHYS(pg))); 3875 3876 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 3877 pv->pv_flags |= PVF_REF | PVF_MOD; 3878 #ifdef PMAP_CACHE_VIPT 3879 /* 3880 * If there are cacheable mappings for this page, mark it dirty. 3881 */ 3882 if ((pg->mdpage.pvh_attrs & PVF_NC) == 0) 3883 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3884 #endif 3885 simple_unlock(&pg->mdpage.pvh_slock); 3886 3887 /* 3888 * Re-enable write permissions for the page. No need to call 3889 * pmap_vac_me_harder(), since this is just a 3890 * modified-emulation fault, and the PVF_WRITE bit isn't 3891 * changing. We've already set the cacheable bits based on 3892 * the assumption that we can write to this page. 3893 */ 3894 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3895 PTE_SYNC(ptep); 3896 rv = 1; 3897 } else 3898 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3899 /* 3900 * This looks like a good candidate for "page referenced" 3901 * emulation. 3902 */ 3903 struct pv_entry *pv; 3904 struct vm_page *pg; 3905 3906 /* Extract the physical address of the page */ 3907 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3908 goto out; 3909 3910 /* Get the current flags for this page. */ 3911 simple_lock(&pg->mdpage.pvh_slock); 3912 3913 pv = pmap_find_pv(pg, pm, va); 3914 if (pv == NULL) { 3915 simple_unlock(&pg->mdpage.pvh_slock); 3916 goto out; 3917 } 3918 3919 pg->mdpage.pvh_attrs |= PVF_REF; 3920 pv->pv_flags |= PVF_REF; 3921 simple_unlock(&pg->mdpage.pvh_slock); 3922 3923 NPDEBUG(PDB_FOLLOW, 3924 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3925 pm, va, VM_PAGE_TO_PHYS(pg))); 3926 3927 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3928 PTE_SYNC(ptep); 3929 rv = 1; 3930 } 3931 3932 /* 3933 * We know there is a valid mapping here, so simply 3934 * fix up the L1 if necessary. 3935 */ 3936 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3937 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3938 if (*pl1pd != l1pd) { 3939 *pl1pd = l1pd; 3940 PTE_SYNC(pl1pd); 3941 rv = 1; 3942 } 3943 3944 #ifdef CPU_SA110 3945 /* 3946 * There are bugs in the rev K SA110. This is a check for one 3947 * of them. 3948 */ 3949 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3950 curcpu()->ci_arm_cpurev < 3) { 3951 /* Always current pmap */ 3952 if (l2pte_valid(pte)) { 3953 extern int kernel_debug; 3954 if (kernel_debug & 1) { 3955 struct proc *p = curlwp->l_proc; 3956 printf("prefetch_abort: page is already " 3957 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3958 printf("prefetch_abort: pc=%08lx proc=%p " 3959 "process=%s\n", va, p, p->p_comm); 3960 printf("prefetch_abort: far=%08x fs=%x\n", 3961 cpu_faultaddress(), cpu_faultstatus()); 3962 } 3963 #ifdef DDB 3964 if (kernel_debug & 2) 3965 Debugger(); 3966 #endif 3967 rv = 1; 3968 } 3969 } 3970 #endif /* CPU_SA110 */ 3971 3972 #ifdef DEBUG 3973 /* 3974 * If 'rv == 0' at this point, it generally indicates that there is a 3975 * stale TLB entry for the faulting address. This happens when two or 3976 * more processes are sharing an L1. Since we don't flush the TLB on 3977 * a context switch between such processes, we can take domain faults 3978 * for mappings which exist at the same VA in both processes. EVEN IF 3979 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3980 * example. 3981 * 3982 * This is extremely likely to happen if pmap_enter() updated the L1 3983 * entry for a recently entered mapping. In this case, the TLB is 3984 * flushed for the new mapping, but there may still be TLB entries for 3985 * other mappings belonging to other processes in the 1MB range 3986 * covered by the L1 entry. 3987 * 3988 * Since 'rv == 0', we know that the L1 already contains the correct 3989 * value, so the fault must be due to a stale TLB entry. 3990 * 3991 * Since we always need to flush the TLB anyway in the case where we 3992 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 3993 * stale TLB entries dynamically. 3994 * 3995 * However, the above condition can ONLY happen if the current L1 is 3996 * being shared. If it happens when the L1 is unshared, it indicates 3997 * that other parts of the pmap are not doing their job WRT managing 3998 * the TLB. 3999 */ 4000 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4001 extern int last_fault_code; 4002 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4003 pm, va, ftype); 4004 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4005 l2, l2b, ptep, pl1pd); 4006 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4007 pte, l1pd, last_fault_code); 4008 #ifdef DDB 4009 Debugger(); 4010 #endif 4011 } 4012 #endif 4013 4014 cpu_tlb_flushID_SE(va); 4015 cpu_cpwait(); 4016 4017 rv = 1; 4018 4019 out: 4020 pmap_release_pmap_lock(pm); 4021 PMAP_MAP_TO_HEAD_UNLOCK(); 4022 4023 return (rv); 4024 } 4025 4026 /* 4027 * pmap_collect: free resources held by a pmap 4028 * 4029 * => optional function. 4030 * => called when a process is swapped out to free memory. 4031 */ 4032 void 4033 pmap_collect(pmap_t pm) 4034 { 4035 4036 #ifdef PMAP_CACHE_VIVT 4037 pmap_idcache_wbinv_all(pm); 4038 #endif 4039 pm->pm_remove_all = true; 4040 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 4041 pmap_update(pm); 4042 PMAPCOUNT(collects); 4043 } 4044 4045 /* 4046 * Routine: pmap_procwr 4047 * 4048 * Function: 4049 * Synchronize caches corresponding to [addr, addr+len) in p. 4050 * 4051 */ 4052 void 4053 pmap_procwr(struct proc *p, vaddr_t va, int len) 4054 { 4055 /* We only need to do anything if it is the current process. */ 4056 if (p == curproc) 4057 cpu_icache_sync_range(va, len); 4058 } 4059 4060 /* 4061 * Routine: pmap_unwire 4062 * Function: Clear the wired attribute for a map/virtual-address pair. 4063 * 4064 * In/out conditions: 4065 * The mapping must already exist in the pmap. 4066 */ 4067 void 4068 pmap_unwire(pmap_t pm, vaddr_t va) 4069 { 4070 struct l2_bucket *l2b; 4071 pt_entry_t *ptep, pte; 4072 struct vm_page *pg; 4073 paddr_t pa; 4074 4075 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4076 4077 PMAP_MAP_TO_HEAD_LOCK(); 4078 pmap_acquire_pmap_lock(pm); 4079 4080 l2b = pmap_get_l2_bucket(pm, va); 4081 KDASSERT(l2b != NULL); 4082 4083 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4084 pte = *ptep; 4085 4086 /* Extract the physical address of the page */ 4087 pa = l2pte_pa(pte); 4088 4089 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4090 /* Update the wired bit in the pv entry for this page. */ 4091 simple_lock(&pg->mdpage.pvh_slock); 4092 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 4093 simple_unlock(&pg->mdpage.pvh_slock); 4094 } 4095 4096 pmap_release_pmap_lock(pm); 4097 PMAP_MAP_TO_HEAD_UNLOCK(); 4098 } 4099 4100 void 4101 pmap_activate(struct lwp *l) 4102 { 4103 extern int block_userspace_access; 4104 pmap_t opm, npm, rpm; 4105 uint32_t odacr, ndacr; 4106 int oldirqstate; 4107 4108 /* 4109 * If activating a non-current lwp or the current lwp is 4110 * already active, just return. 4111 */ 4112 if (l != curlwp || 4113 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4114 return; 4115 4116 npm = l->l_proc->p_vmspace->vm_map.pmap; 4117 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4118 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4119 4120 /* 4121 * If TTB and DACR are unchanged, short-circuit all the 4122 * TLB/cache management stuff. 4123 */ 4124 if (pmap_previous_active_lwp != NULL) { 4125 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4126 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4127 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4128 4129 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4130 goto all_done; 4131 } else 4132 opm = NULL; 4133 4134 PMAPCOUNT(activations); 4135 block_userspace_access = 1; 4136 4137 /* 4138 * If switching to a user vmspace which is different to the 4139 * most recent one, and the most recent one is potentially 4140 * live in the cache, we must write-back and invalidate the 4141 * entire cache. 4142 */ 4143 rpm = pmap_recent_user; 4144 if (npm != pmap_kernel() && rpm && npm != rpm && 4145 rpm->pm_cstate.cs_cache) { 4146 rpm->pm_cstate.cs_cache = 0; 4147 #ifdef PMAP_CACHE_VIVT 4148 cpu_idcache_wbinv_all(); 4149 #endif 4150 } 4151 4152 /* No interrupts while we frob the TTB/DACR */ 4153 oldirqstate = disable_interrupts(IF32_bits); 4154 4155 /* 4156 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4157 * entry corresponding to 'vector_page' in the incoming L1 table 4158 * before switching to it otherwise subsequent interrupts/exceptions 4159 * (including domain faults!) will jump into hyperspace. 4160 */ 4161 if (npm->pm_pl1vec != NULL) { 4162 cpu_tlb_flushID_SE((u_int)vector_page); 4163 cpu_cpwait(); 4164 *npm->pm_pl1vec = npm->pm_l1vec; 4165 PTE_SYNC(npm->pm_pl1vec); 4166 } 4167 4168 cpu_domains(ndacr); 4169 4170 if (npm == pmap_kernel() || npm == rpm) { 4171 /* 4172 * Switching to a kernel thread, or back to the 4173 * same user vmspace as before... Simply update 4174 * the TTB (no TLB flush required) 4175 */ 4176 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4177 "r"(npm->pm_l1->l1_physaddr)); 4178 cpu_cpwait(); 4179 } else { 4180 /* 4181 * Otherwise, update TTB and flush TLB 4182 */ 4183 cpu_context_switch(npm->pm_l1->l1_physaddr); 4184 if (rpm != NULL) 4185 rpm->pm_cstate.cs_tlb = 0; 4186 } 4187 4188 restore_interrupts(oldirqstate); 4189 4190 block_userspace_access = 0; 4191 4192 all_done: 4193 /* 4194 * The new pmap is resident. Make sure it's marked 4195 * as resident in the cache/TLB. 4196 */ 4197 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4198 if (npm != pmap_kernel()) 4199 pmap_recent_user = npm; 4200 4201 /* The old pmap is not longer active */ 4202 if (opm != NULL) 4203 opm->pm_activated = false; 4204 4205 /* But the new one is */ 4206 npm->pm_activated = true; 4207 } 4208 4209 void 4210 pmap_deactivate(struct lwp *l) 4211 { 4212 4213 /* 4214 * If the process is exiting, make sure pmap_activate() does 4215 * a full MMU context-switch and cache flush, which we might 4216 * otherwise skip. See PR port-arm/38950. 4217 */ 4218 if (l->l_proc->p_sflag & PS_WEXIT) 4219 pmap_previous_active_lwp = NULL; 4220 4221 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4222 } 4223 4224 void 4225 pmap_update(pmap_t pm) 4226 { 4227 4228 if (pm->pm_remove_all) { 4229 /* 4230 * Finish up the pmap_remove_all() optimisation by flushing 4231 * the TLB. 4232 */ 4233 pmap_tlb_flushID(pm); 4234 pm->pm_remove_all = false; 4235 } 4236 4237 if (pmap_is_current(pm)) { 4238 /* 4239 * If we're dealing with a current userland pmap, move its L1 4240 * to the end of the LRU. 4241 */ 4242 if (pm != pmap_kernel()) 4243 pmap_use_l1(pm); 4244 4245 /* 4246 * We can assume we're done with frobbing the cache/tlb for 4247 * now. Make sure any future pmap ops don't skip cache/tlb 4248 * flushes. 4249 */ 4250 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4251 } 4252 4253 PMAPCOUNT(updates); 4254 4255 /* 4256 * make sure TLB/cache operations have completed. 4257 */ 4258 cpu_cpwait(); 4259 } 4260 4261 void 4262 pmap_remove_all(pmap_t pm) 4263 { 4264 4265 /* 4266 * The vmspace described by this pmap is about to be torn down. 4267 * Until pmap_update() is called, UVM will only make calls 4268 * to pmap_remove(). We can make life much simpler by flushing 4269 * the cache now, and deferring TLB invalidation to pmap_update(). 4270 */ 4271 #ifdef PMAP_CACHE_VIVT 4272 pmap_idcache_wbinv_all(pm); 4273 #endif 4274 pm->pm_remove_all = true; 4275 } 4276 4277 /* 4278 * Retire the given physical map from service. 4279 * Should only be called if the map contains no valid mappings. 4280 */ 4281 void 4282 pmap_destroy(pmap_t pm) 4283 { 4284 u_int count; 4285 4286 if (pm == NULL) 4287 return; 4288 4289 if (pm->pm_remove_all) { 4290 pmap_tlb_flushID(pm); 4291 pm->pm_remove_all = false; 4292 } 4293 4294 /* 4295 * Drop reference count 4296 */ 4297 mutex_enter(&pm->pm_lock); 4298 count = --pm->pm_obj.uo_refs; 4299 mutex_exit(&pm->pm_lock); 4300 if (count > 0) { 4301 if (pmap_is_current(pm)) { 4302 if (pm != pmap_kernel()) 4303 pmap_use_l1(pm); 4304 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4305 } 4306 return; 4307 } 4308 4309 /* 4310 * reference count is zero, free pmap resources and then free pmap. 4311 */ 4312 4313 if (vector_page < KERNEL_BASE) { 4314 KDASSERT(!pmap_is_current(pm)); 4315 4316 /* Remove the vector page mapping */ 4317 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4318 pmap_update(pm); 4319 } 4320 4321 LIST_REMOVE(pm, pm_list); 4322 4323 pmap_free_l1(pm); 4324 4325 if (pmap_recent_user == pm) 4326 pmap_recent_user = NULL; 4327 4328 UVM_OBJ_DESTROY(&pm->pm_obj); 4329 4330 /* return the pmap to the pool */ 4331 pool_cache_put(&pmap_cache, pm); 4332 } 4333 4334 4335 /* 4336 * void pmap_reference(pmap_t pm) 4337 * 4338 * Add a reference to the specified pmap. 4339 */ 4340 void 4341 pmap_reference(pmap_t pm) 4342 { 4343 4344 if (pm == NULL) 4345 return; 4346 4347 pmap_use_l1(pm); 4348 4349 mutex_enter(&pm->pm_lock); 4350 pm->pm_obj.uo_refs++; 4351 mutex_exit(&pm->pm_lock); 4352 } 4353 4354 #if ARM_MMU_V6 > 0 4355 4356 static struct evcnt pmap_prefer_nochange_ev = 4357 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4358 static struct evcnt pmap_prefer_change_ev = 4359 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4360 4361 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4362 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4363 4364 void 4365 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4366 { 4367 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4368 vaddr_t va = *vap; 4369 vaddr_t diff = (hint - va) & mask; 4370 if (diff == 0) { 4371 pmap_prefer_nochange_ev.ev_count++; 4372 } else { 4373 pmap_prefer_change_ev.ev_count++; 4374 if (__predict_false(td)) 4375 va -= mask + 1; 4376 *vap = va + diff; 4377 } 4378 } 4379 #endif /* ARM_MMU_V6 */ 4380 4381 /* 4382 * pmap_zero_page() 4383 * 4384 * Zero a given physical page by mapping it at a page hook point. 4385 * In doing the zero page op, the page we zero is mapped cachable, as with 4386 * StrongARM accesses to non-cached pages are non-burst making writing 4387 * _any_ bulk data very slow. 4388 */ 4389 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4390 void 4391 pmap_zero_page_generic(paddr_t phys) 4392 { 4393 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4394 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4395 #endif 4396 #ifdef PMAP_CACHE_VIPT 4397 /* Choose the last page color it had, if any */ 4398 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4399 #else 4400 const vsize_t va_offset = 0; 4401 #endif 4402 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4403 4404 #ifdef DEBUG 4405 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4406 panic("pmap_zero_page: page has mappings"); 4407 #endif 4408 4409 KDASSERT((phys & PGOFSET) == 0); 4410 4411 /* 4412 * Hook in the page, zero it, and purge the cache for that 4413 * zeroed page. Invalidate the TLB as needed. 4414 */ 4415 *ptep = L2_S_PROTO | phys | 4416 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4417 PTE_SYNC(ptep); 4418 cpu_tlb_flushD_SE(cdstp + va_offset); 4419 cpu_cpwait(); 4420 bzero_page(cdstp + va_offset); 4421 /* 4422 * Unmap the page. 4423 */ 4424 *ptep = 0; 4425 PTE_SYNC(ptep); 4426 cpu_tlb_flushD_SE(cdstp + va_offset); 4427 #ifdef PMAP_CACHE_VIVT 4428 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4429 #endif 4430 #ifdef PMAP_CACHE_VIPT 4431 /* 4432 * This page is now cache resident so it now has a page color. 4433 * Any contents have been obliterated so clear the EXEC flag. 4434 */ 4435 if (!pmap_is_page_colored_p(pg)) { 4436 PMAPCOUNT(vac_color_new); 4437 pg->mdpage.pvh_attrs |= PVF_COLORED; 4438 } 4439 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4440 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4441 PMAPCOUNT(exec_discarded_zero); 4442 } 4443 pg->mdpage.pvh_attrs |= PVF_DIRTY; 4444 #endif 4445 } 4446 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4447 4448 #if ARM_MMU_XSCALE == 1 4449 void 4450 pmap_zero_page_xscale(paddr_t phys) 4451 { 4452 #ifdef DEBUG 4453 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4454 4455 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4456 panic("pmap_zero_page: page has mappings"); 4457 #endif 4458 4459 KDASSERT((phys & PGOFSET) == 0); 4460 4461 /* 4462 * Hook in the page, zero it, and purge the cache for that 4463 * zeroed page. Invalidate the TLB as needed. 4464 */ 4465 *cdst_pte = L2_S_PROTO | phys | 4466 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4467 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4468 PTE_SYNC(cdst_pte); 4469 cpu_tlb_flushD_SE(cdstp); 4470 cpu_cpwait(); 4471 bzero_page(cdstp); 4472 xscale_cache_clean_minidata(); 4473 } 4474 #endif /* ARM_MMU_XSCALE == 1 */ 4475 4476 /* pmap_pageidlezero() 4477 * 4478 * The same as above, except that we assume that the page is not 4479 * mapped. This means we never have to flush the cache first. Called 4480 * from the idle loop. 4481 */ 4482 bool 4483 pmap_pageidlezero(paddr_t phys) 4484 { 4485 unsigned int i; 4486 int *ptr; 4487 bool rv = true; 4488 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4489 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4490 #endif 4491 #ifdef PMAP_CACHE_VIPT 4492 /* Choose the last page color it had, if any */ 4493 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4494 #else 4495 const vsize_t va_offset = 0; 4496 #endif 4497 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4498 4499 4500 #ifdef DEBUG 4501 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4502 panic("pmap_pageidlezero: page has mappings"); 4503 #endif 4504 4505 KDASSERT((phys & PGOFSET) == 0); 4506 4507 /* 4508 * Hook in the page, zero it, and purge the cache for that 4509 * zeroed page. Invalidate the TLB as needed. 4510 */ 4511 *ptep = L2_S_PROTO | phys | 4512 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4513 PTE_SYNC(ptep); 4514 cpu_tlb_flushD_SE(cdstp + va_offset); 4515 cpu_cpwait(); 4516 4517 for (i = 0, ptr = (int *)(cdstp + va_offset); 4518 i < (PAGE_SIZE / sizeof(int)); i++) { 4519 if (sched_curcpu_runnable_p() != 0) { 4520 /* 4521 * A process has become ready. Abort now, 4522 * so we don't keep it waiting while we 4523 * do slow memory access to finish this 4524 * page. 4525 */ 4526 rv = false; 4527 break; 4528 } 4529 *ptr++ = 0; 4530 } 4531 4532 #ifdef PMAP_CACHE_VIVT 4533 if (rv) 4534 /* 4535 * if we aborted we'll rezero this page again later so don't 4536 * purge it unless we finished it 4537 */ 4538 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4539 #elif defined(PMAP_CACHE_VIPT) 4540 /* 4541 * This page is now cache resident so it now has a page color. 4542 * Any contents have been obliterated so clear the EXEC flag. 4543 */ 4544 if (!pmap_is_page_colored_p(pg)) { 4545 PMAPCOUNT(vac_color_new); 4546 pg->mdpage.pvh_attrs |= PVF_COLORED; 4547 } 4548 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4549 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4550 PMAPCOUNT(exec_discarded_zero); 4551 } 4552 #endif 4553 /* 4554 * Unmap the page. 4555 */ 4556 *ptep = 0; 4557 PTE_SYNC(ptep); 4558 cpu_tlb_flushD_SE(cdstp + va_offset); 4559 4560 return (rv); 4561 } 4562 4563 /* 4564 * pmap_copy_page() 4565 * 4566 * Copy one physical page into another, by mapping the pages into 4567 * hook points. The same comment regarding cachability as in 4568 * pmap_zero_page also applies here. 4569 */ 4570 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4571 void 4572 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4573 { 4574 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4575 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4576 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4577 #endif 4578 #ifdef PMAP_CACHE_VIPT 4579 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4580 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4581 #else 4582 const vsize_t src_va_offset = 0; 4583 const vsize_t dst_va_offset = 0; 4584 #endif 4585 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4586 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4587 4588 #ifdef DEBUG 4589 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4590 panic("pmap_copy_page: dst page has mappings"); 4591 #endif 4592 4593 #ifdef PMAP_CACHE_VIPT 4594 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4595 #endif 4596 KDASSERT((src & PGOFSET) == 0); 4597 KDASSERT((dst & PGOFSET) == 0); 4598 4599 /* 4600 * Clean the source page. Hold the source page's lock for 4601 * the duration of the copy so that no other mappings can 4602 * be created while we have a potentially aliased mapping. 4603 */ 4604 simple_lock(&src_pg->mdpage.pvh_slock); 4605 #ifdef PMAP_CACHE_VIVT 4606 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4607 #endif 4608 4609 /* 4610 * Map the pages into the page hook points, copy them, and purge 4611 * the cache for the appropriate page. Invalidate the TLB 4612 * as required. 4613 */ 4614 *src_ptep = L2_S_PROTO 4615 | src 4616 #ifdef PMAP_CACHE_VIPT 4617 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4618 #endif 4619 #ifdef PMAP_CACHE_VIVT 4620 | pte_l2_s_cache_mode 4621 #endif 4622 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4623 *dst_ptep = L2_S_PROTO | dst | 4624 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4625 PTE_SYNC(src_ptep); 4626 PTE_SYNC(dst_ptep); 4627 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4628 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4629 cpu_cpwait(); 4630 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4631 #ifdef PMAP_CACHE_VIVT 4632 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4633 #endif 4634 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4635 #ifdef PMAP_CACHE_VIVT 4636 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4637 #endif 4638 /* 4639 * Unmap the pages. 4640 */ 4641 *src_ptep = 0; 4642 *dst_ptep = 0; 4643 PTE_SYNC(src_ptep); 4644 PTE_SYNC(dst_ptep); 4645 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4646 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4647 #ifdef PMAP_CACHE_VIPT 4648 /* 4649 * Now that the destination page is in the cache, mark it as colored. 4650 * If this was an exec page, discard it. 4651 */ 4652 if (!pmap_is_page_colored_p(dst_pg)) { 4653 PMAPCOUNT(vac_color_new); 4654 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4655 } 4656 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4657 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4658 PMAPCOUNT(exec_discarded_copy); 4659 } 4660 dst_pg->mdpage.pvh_attrs |= PVF_DIRTY; 4661 #endif 4662 } 4663 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4664 4665 #if ARM_MMU_XSCALE == 1 4666 void 4667 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4668 { 4669 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4670 #ifdef DEBUG 4671 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4672 4673 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4674 panic("pmap_copy_page: dst page has mappings"); 4675 #endif 4676 4677 KDASSERT((src & PGOFSET) == 0); 4678 KDASSERT((dst & PGOFSET) == 0); 4679 4680 /* 4681 * Clean the source page. Hold the source page's lock for 4682 * the duration of the copy so that no other mappings can 4683 * be created while we have a potentially aliased mapping. 4684 */ 4685 simple_lock(&src_pg->mdpage.pvh_slock); 4686 #ifdef PMAP_CACHE_VIVT 4687 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4688 #endif 4689 4690 /* 4691 * Map the pages into the page hook points, copy them, and purge 4692 * the cache for the appropriate page. Invalidate the TLB 4693 * as required. 4694 */ 4695 *csrc_pte = L2_S_PROTO | src | 4696 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4697 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4698 PTE_SYNC(csrc_pte); 4699 *cdst_pte = L2_S_PROTO | dst | 4700 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4701 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4702 PTE_SYNC(cdst_pte); 4703 cpu_tlb_flushD_SE(csrcp); 4704 cpu_tlb_flushD_SE(cdstp); 4705 cpu_cpwait(); 4706 bcopy_page(csrcp, cdstp); 4707 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4708 xscale_cache_clean_minidata(); 4709 } 4710 #endif /* ARM_MMU_XSCALE == 1 */ 4711 4712 /* 4713 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4714 * 4715 * Return the start and end addresses of the kernel's virtual space. 4716 * These values are setup in pmap_bootstrap and are updated as pages 4717 * are allocated. 4718 */ 4719 void 4720 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4721 { 4722 *start = virtual_avail; 4723 *end = virtual_end; 4724 } 4725 4726 /* 4727 * Helper function for pmap_grow_l2_bucket() 4728 */ 4729 static inline int 4730 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4731 { 4732 struct l2_bucket *l2b; 4733 pt_entry_t *ptep; 4734 paddr_t pa; 4735 4736 if (uvm.page_init_done == false) { 4737 #ifdef PMAP_STEAL_MEMORY 4738 pv_addr_t pv; 4739 pmap_boot_pagealloc(PAGE_SIZE, 4740 #ifdef PMAP_CACHE_VIPT 4741 arm_cache_prefer_mask, 4742 va & arm_cache_prefer_mask, 4743 #else 4744 0, 0, 4745 #endif 4746 &pv); 4747 pa = pv.pv_pa; 4748 #else 4749 if (uvm_page_physget(&pa) == false) 4750 return (1); 4751 #endif /* PMAP_STEAL_MEMORY */ 4752 } else { 4753 struct vm_page *pg; 4754 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4755 if (pg == NULL) 4756 return (1); 4757 pa = VM_PAGE_TO_PHYS(pg); 4758 #ifdef PMAP_CACHE_VIPT 4759 /* 4760 * This new page must not have any mappings. Enter it via 4761 * pmap_kenter_pa and let that routine do the hard work. 4762 */ 4763 KASSERT(SLIST_EMPTY(&pg->mdpage.pvh_list)); 4764 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 4765 #endif 4766 } 4767 4768 if (pap) 4769 *pap = pa; 4770 4771 PMAPCOUNT(pt_mappings); 4772 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4773 KDASSERT(l2b != NULL); 4774 4775 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4776 *ptep = L2_S_PROTO | pa | cache_mode | 4777 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4778 PTE_SYNC(ptep); 4779 memset((void *)va, 0, PAGE_SIZE); 4780 return (0); 4781 } 4782 4783 /* 4784 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4785 * used by pmap_growkernel(). 4786 */ 4787 static inline struct l2_bucket * 4788 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4789 { 4790 struct l2_dtable *l2; 4791 struct l2_bucket *l2b; 4792 u_short l1idx; 4793 vaddr_t nva; 4794 4795 l1idx = L1_IDX(va); 4796 4797 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4798 /* 4799 * No mapping at this address, as there is 4800 * no entry in the L1 table. 4801 * Need to allocate a new l2_dtable. 4802 */ 4803 nva = pmap_kernel_l2dtable_kva; 4804 if ((nva & PGOFSET) == 0) { 4805 /* 4806 * Need to allocate a backing page 4807 */ 4808 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4809 return (NULL); 4810 } 4811 4812 l2 = (struct l2_dtable *)nva; 4813 nva += sizeof(struct l2_dtable); 4814 4815 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4816 /* 4817 * The new l2_dtable straddles a page boundary. 4818 * Map in another page to cover it. 4819 */ 4820 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4821 return (NULL); 4822 } 4823 4824 pmap_kernel_l2dtable_kva = nva; 4825 4826 /* 4827 * Link it into the parent pmap 4828 */ 4829 pm->pm_l2[L2_IDX(l1idx)] = l2; 4830 } 4831 4832 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4833 4834 /* 4835 * Fetch pointer to the L2 page table associated with the address. 4836 */ 4837 if (l2b->l2b_kva == NULL) { 4838 pt_entry_t *ptep; 4839 4840 /* 4841 * No L2 page table has been allocated. Chances are, this 4842 * is because we just allocated the l2_dtable, above. 4843 */ 4844 nva = pmap_kernel_l2ptp_kva; 4845 ptep = (pt_entry_t *)nva; 4846 if ((nva & PGOFSET) == 0) { 4847 /* 4848 * Need to allocate a backing page 4849 */ 4850 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4851 &pmap_kernel_l2ptp_phys)) 4852 return (NULL); 4853 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4854 } 4855 4856 l2->l2_occupancy++; 4857 l2b->l2b_kva = ptep; 4858 l2b->l2b_l1idx = l1idx; 4859 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4860 4861 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4862 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4863 } 4864 4865 return (l2b); 4866 } 4867 4868 vaddr_t 4869 pmap_growkernel(vaddr_t maxkvaddr) 4870 { 4871 pmap_t kpm = pmap_kernel(); 4872 struct l1_ttable *l1; 4873 struct l2_bucket *l2b; 4874 pd_entry_t *pl1pd; 4875 int s; 4876 4877 if (maxkvaddr <= pmap_curmaxkvaddr) 4878 goto out; /* we are OK */ 4879 4880 NPDEBUG(PDB_GROWKERN, 4881 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4882 pmap_curmaxkvaddr, maxkvaddr)); 4883 4884 KDASSERT(maxkvaddr <= virtual_end); 4885 4886 /* 4887 * whoops! we need to add kernel PTPs 4888 */ 4889 4890 s = splhigh(); /* to be safe */ 4891 mutex_enter(&kpm->pm_lock); 4892 4893 /* Map 1MB at a time */ 4894 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4895 4896 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4897 KDASSERT(l2b != NULL); 4898 4899 /* Distribute new L1 entry to all other L1s */ 4900 SLIST_FOREACH(l1, &l1_list, l1_link) { 4901 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4902 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4903 L1_C_PROTO; 4904 PTE_SYNC(pl1pd); 4905 } 4906 } 4907 4908 /* 4909 * flush out the cache, expensive but growkernel will happen so 4910 * rarely 4911 */ 4912 cpu_dcache_wbinv_all(); 4913 cpu_tlb_flushD(); 4914 cpu_cpwait(); 4915 4916 mutex_exit(&kpm->pm_lock); 4917 splx(s); 4918 4919 out: 4920 return (pmap_curmaxkvaddr); 4921 } 4922 4923 /************************ Utility routines ****************************/ 4924 4925 /* 4926 * vector_page_setprot: 4927 * 4928 * Manipulate the protection of the vector page. 4929 */ 4930 void 4931 vector_page_setprot(int prot) 4932 { 4933 struct l2_bucket *l2b; 4934 pt_entry_t *ptep; 4935 4936 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4937 KDASSERT(l2b != NULL); 4938 4939 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4940 4941 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4942 PTE_SYNC(ptep); 4943 cpu_tlb_flushD_SE(vector_page); 4944 cpu_cpwait(); 4945 } 4946 4947 /* 4948 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4949 * Returns true if the mapping exists, else false. 4950 * 4951 * NOTE: This function is only used by a couple of arm-specific modules. 4952 * It is not safe to take any pmap locks here, since we could be right 4953 * in the middle of debugging the pmap anyway... 4954 * 4955 * It is possible for this routine to return false even though a valid 4956 * mapping does exist. This is because we don't lock, so the metadata 4957 * state may be inconsistent. 4958 * 4959 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4960 * a "section" mapping. 4961 */ 4962 bool 4963 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4964 { 4965 struct l2_dtable *l2; 4966 pd_entry_t *pl1pd, l1pd; 4967 pt_entry_t *ptep; 4968 u_short l1idx; 4969 4970 if (pm->pm_l1 == NULL) 4971 return false; 4972 4973 l1idx = L1_IDX(va); 4974 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4975 l1pd = *pl1pd; 4976 4977 if (l1pte_section_p(l1pd)) { 4978 *ptp = NULL; 4979 return true; 4980 } 4981 4982 if (pm->pm_l2 == NULL) 4983 return false; 4984 4985 l2 = pm->pm_l2[L2_IDX(l1idx)]; 4986 4987 if (l2 == NULL || 4988 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 4989 return false; 4990 } 4991 4992 *ptp = &ptep[l2pte_index(va)]; 4993 return true; 4994 } 4995 4996 bool 4997 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 4998 { 4999 u_short l1idx; 5000 5001 if (pm->pm_l1 == NULL) 5002 return false; 5003 5004 l1idx = L1_IDX(va); 5005 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5006 5007 return true; 5008 } 5009 5010 /************************ Bootstrapping routines ****************************/ 5011 5012 static void 5013 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5014 { 5015 int i; 5016 5017 l1->l1_kva = l1pt; 5018 l1->l1_domain_use_count = 0; 5019 l1->l1_domain_first = 0; 5020 5021 for (i = 0; i < PMAP_DOMAINS; i++) 5022 l1->l1_domain_free[i] = i + 1; 5023 5024 /* 5025 * Copy the kernel's L1 entries to each new L1. 5026 */ 5027 if (pmap_initialized) 5028 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5029 5030 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5031 &l1->l1_physaddr) == false) 5032 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5033 5034 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5035 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5036 } 5037 5038 /* 5039 * pmap_bootstrap() is called from the board-specific initarm() routine 5040 * once the kernel L1/L2 descriptors tables have been set up. 5041 * 5042 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5043 * spread over a number of disparate files/functions. 5044 * 5045 * We are passed the following parameters 5046 * - kernel_l1pt 5047 * This is a pointer to the base of the kernel's L1 translation table. 5048 * - vstart 5049 * 1MB-aligned start of managed kernel virtual memory. 5050 * - vend 5051 * 1MB-aligned end of managed kernel virtual memory. 5052 * 5053 * We use the first parameter to build the metadata (struct l1_ttable and 5054 * struct l2_dtable) necessary to track kernel mappings. 5055 */ 5056 #define PMAP_STATIC_L2_SIZE 16 5057 void 5058 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5059 { 5060 static struct l1_ttable static_l1; 5061 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5062 struct l1_ttable *l1 = &static_l1; 5063 struct l2_dtable *l2; 5064 struct l2_bucket *l2b; 5065 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5066 pmap_t pm = pmap_kernel(); 5067 pd_entry_t pde; 5068 pt_entry_t *ptep; 5069 paddr_t pa; 5070 vaddr_t va; 5071 vsize_t size; 5072 int nptes, l1idx, l2idx, l2next = 0; 5073 5074 /* 5075 * Initialise the kernel pmap object 5076 */ 5077 pm->pm_l1 = l1; 5078 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5079 pm->pm_activated = true; 5080 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5081 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5082 5083 /* 5084 * Scan the L1 translation table created by initarm() and create 5085 * the required metadata for all valid mappings found in it. 5086 */ 5087 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5088 pde = l1pt[l1idx]; 5089 5090 /* 5091 * We're only interested in Coarse mappings. 5092 * pmap_extract() can deal with section mappings without 5093 * recourse to checking L2 metadata. 5094 */ 5095 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5096 continue; 5097 5098 /* 5099 * Lookup the KVA of this L2 descriptor table 5100 */ 5101 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5102 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5103 if (ptep == NULL) { 5104 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5105 (u_int)l1idx << L1_S_SHIFT, pa); 5106 } 5107 5108 /* 5109 * Fetch the associated L2 metadata structure. 5110 * Allocate a new one if necessary. 5111 */ 5112 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5113 if (l2next == PMAP_STATIC_L2_SIZE) 5114 panic("pmap_bootstrap: out of static L2s"); 5115 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5116 } 5117 5118 /* 5119 * One more L1 slot tracked... 5120 */ 5121 l2->l2_occupancy++; 5122 5123 /* 5124 * Fill in the details of the L2 descriptor in the 5125 * appropriate bucket. 5126 */ 5127 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5128 l2b->l2b_kva = ptep; 5129 l2b->l2b_phys = pa; 5130 l2b->l2b_l1idx = l1idx; 5131 5132 /* 5133 * Establish an initial occupancy count for this descriptor 5134 */ 5135 for (l2idx = 0; 5136 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5137 l2idx++) { 5138 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5139 l2b->l2b_occupancy++; 5140 } 5141 } 5142 5143 /* 5144 * Make sure the descriptor itself has the correct cache mode. 5145 * If not, fix it, but whine about the problem. Port-meisters 5146 * should consider this a clue to fix up their initarm() 5147 * function. :) 5148 */ 5149 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5150 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5151 "L2 pte @ %p\n", ptep); 5152 } 5153 } 5154 5155 /* 5156 * Ensure the primary (kernel) L1 has the correct cache mode for 5157 * a page table. Bitch if it is not correctly set. 5158 */ 5159 for (va = (vaddr_t)l1pt; 5160 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5161 if (pmap_set_pt_cache_mode(l1pt, va)) 5162 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5163 "primary L1 @ 0x%lx\n", va); 5164 } 5165 5166 cpu_dcache_wbinv_all(); 5167 cpu_tlb_flushID(); 5168 cpu_cpwait(); 5169 5170 /* 5171 * now we allocate the "special" VAs which are used for tmp mappings 5172 * by the pmap (and other modules). we allocate the VAs by advancing 5173 * virtual_avail (note that there are no pages mapped at these VAs). 5174 * 5175 * Managed KVM space start from wherever initarm() tells us. 5176 */ 5177 virtual_avail = vstart; 5178 virtual_end = vend; 5179 5180 #ifdef PMAP_CACHE_VIPT 5181 /* 5182 * If we have a VIPT cache, we need one page/pte per possible alias 5183 * page so we won't violate cache aliasing rules. 5184 */ 5185 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5186 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5187 #else 5188 nptes = 1; 5189 #endif 5190 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5191 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5192 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5193 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5194 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5195 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5196 (void *)&msgbufaddr, NULL); 5197 5198 /* 5199 * Allocate a range of kernel virtual address space to be used 5200 * for L2 descriptor tables and metadata allocation in 5201 * pmap_growkernel(). 5202 */ 5203 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5204 pmap_alloc_specials(&virtual_avail, 5205 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5206 &pmap_kernel_l2ptp_kva, NULL); 5207 5208 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5209 pmap_alloc_specials(&virtual_avail, 5210 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5211 &pmap_kernel_l2dtable_kva, NULL); 5212 5213 /* 5214 * init the static-global locks and global pmap list. 5215 */ 5216 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5217 5218 /* 5219 * We can now initialise the first L1's metadata. 5220 */ 5221 SLIST_INIT(&l1_list); 5222 TAILQ_INIT(&l1_lru_list); 5223 simple_lock_init(&l1_lru_lock); 5224 pmap_init_l1(l1, l1pt); 5225 5226 /* Set up vector page L1 details, if necessary */ 5227 if (vector_page < KERNEL_BASE) { 5228 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5229 l2b = pmap_get_l2_bucket(pm, vector_page); 5230 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5231 L1_C_DOM(pm->pm_domain); 5232 } else 5233 pm->pm_pl1vec = NULL; 5234 5235 /* 5236 * Initialize the pmap cache 5237 */ 5238 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5239 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5240 LIST_INIT(&pmap_pmaps); 5241 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5242 5243 /* 5244 * Initialize the pv pool. 5245 */ 5246 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5247 &pmap_bootstrap_pv_allocator, IPL_NONE); 5248 5249 /* 5250 * Initialize the L2 dtable pool and cache. 5251 */ 5252 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5253 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5254 5255 /* 5256 * Initialise the L2 descriptor table pool and cache 5257 */ 5258 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5259 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5260 pmap_l2ptp_ctor, NULL, NULL); 5261 5262 cpu_dcache_wbinv_all(); 5263 } 5264 5265 static int 5266 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5267 { 5268 pd_entry_t *pdep, pde; 5269 pt_entry_t *ptep, pte; 5270 vaddr_t pa; 5271 int rv = 0; 5272 5273 /* 5274 * Make sure the descriptor itself has the correct cache mode 5275 */ 5276 pdep = &kl1[L1_IDX(va)]; 5277 pde = *pdep; 5278 5279 if (l1pte_section_p(pde)) { 5280 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5281 *pdep = (pde & ~L1_S_CACHE_MASK) | 5282 pte_l1_s_cache_mode_pt; 5283 PTE_SYNC(pdep); 5284 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5285 rv = 1; 5286 } 5287 } else { 5288 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5289 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5290 if (ptep == NULL) 5291 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5292 5293 ptep = &ptep[l2pte_index(va)]; 5294 pte = *ptep; 5295 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5296 *ptep = (pte & ~L2_S_CACHE_MASK) | 5297 pte_l2_s_cache_mode_pt; 5298 PTE_SYNC(ptep); 5299 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5300 rv = 1; 5301 } 5302 } 5303 5304 return (rv); 5305 } 5306 5307 static void 5308 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5309 { 5310 vaddr_t va = *availp; 5311 struct l2_bucket *l2b; 5312 5313 if (ptep) { 5314 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5315 if (l2b == NULL) 5316 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5317 5318 if (ptep) 5319 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5320 } 5321 5322 *vap = va; 5323 *availp = va + (PAGE_SIZE * pages); 5324 } 5325 5326 void 5327 pmap_init(void) 5328 { 5329 extern int physmem; 5330 5331 /* 5332 * Set the available memory vars - These do not map to real memory 5333 * addresses and cannot as the physical memory is fragmented. 5334 * They are used by ps for %mem calculations. 5335 * One could argue whether this should be the entire memory or just 5336 * the memory that is useable in a user process. 5337 */ 5338 avail_start = 0; 5339 avail_end = physmem * PAGE_SIZE; 5340 5341 /* 5342 * Now we need to free enough pv_entry structures to allow us to get 5343 * the kmem_map/kmem_object allocated and inited (done after this 5344 * function is finished). to do this we allocate one bootstrap page out 5345 * of kernel_map and use it to provide an initial pool of pv_entry 5346 * structures. we never free this page. 5347 */ 5348 pool_setlowat(&pmap_pv_pool, 5349 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5350 5351 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5352 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5353 UVM_KMF_WIRED|UVM_KMF_ZERO); 5354 5355 pmap_initialized = true; 5356 } 5357 5358 static vaddr_t last_bootstrap_page = 0; 5359 static void *free_bootstrap_pages = NULL; 5360 5361 static void * 5362 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5363 { 5364 extern void *pool_page_alloc(struct pool *, int); 5365 vaddr_t new_page; 5366 void *rv; 5367 5368 if (pmap_initialized) 5369 return (pool_page_alloc(pp, flags)); 5370 5371 if (free_bootstrap_pages) { 5372 rv = free_bootstrap_pages; 5373 free_bootstrap_pages = *((void **)rv); 5374 return (rv); 5375 } 5376 5377 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5378 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5379 5380 KASSERT(new_page > last_bootstrap_page); 5381 last_bootstrap_page = new_page; 5382 return ((void *)new_page); 5383 } 5384 5385 static void 5386 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5387 { 5388 extern void pool_page_free(struct pool *, void *); 5389 5390 if ((vaddr_t)v <= last_bootstrap_page) { 5391 *((void **)v) = free_bootstrap_pages; 5392 free_bootstrap_pages = v; 5393 return; 5394 } 5395 5396 if (pmap_initialized) { 5397 pool_page_free(pp, v); 5398 return; 5399 } 5400 } 5401 5402 /* 5403 * pmap_postinit() 5404 * 5405 * This routine is called after the vm and kmem subsystems have been 5406 * initialised. This allows the pmap code to perform any initialisation 5407 * that can only be done one the memory allocation is in place. 5408 */ 5409 void 5410 pmap_postinit(void) 5411 { 5412 extern paddr_t physical_start, physical_end; 5413 struct l2_bucket *l2b; 5414 struct l1_ttable *l1; 5415 struct pglist plist; 5416 struct vm_page *m; 5417 pd_entry_t *pl1pt; 5418 pt_entry_t *ptep, pte; 5419 vaddr_t va, eva; 5420 u_int loop, needed; 5421 int error; 5422 5423 pool_cache_setlowat(&pmap_l2ptp_cache, 5424 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5425 pool_cache_setlowat(&pmap_l2dtable_cache, 5426 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5427 5428 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5429 needed -= 1; 5430 5431 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5432 5433 for (loop = 0; loop < needed; loop++, l1++) { 5434 /* Allocate a L1 page table */ 5435 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5436 if (va == 0) 5437 panic("Cannot allocate L1 KVM"); 5438 5439 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5440 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5441 if (error) 5442 panic("Cannot allocate L1 physical pages"); 5443 5444 m = TAILQ_FIRST(&plist); 5445 eva = va + L1_TABLE_SIZE; 5446 pl1pt = (pd_entry_t *)va; 5447 5448 while (m && va < eva) { 5449 paddr_t pa = VM_PAGE_TO_PHYS(m); 5450 5451 pmap_kenter_pa(va, pa, 5452 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 5453 5454 /* 5455 * Make sure the L1 descriptor table is mapped 5456 * with the cache-mode set to write-through. 5457 */ 5458 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5459 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5460 pte = *ptep; 5461 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5462 *ptep = pte; 5463 PTE_SYNC(ptep); 5464 cpu_tlb_flushD_SE(va); 5465 5466 va += PAGE_SIZE; 5467 m = TAILQ_NEXT(m, pageq.queue); 5468 } 5469 5470 #ifdef DIAGNOSTIC 5471 if (m) 5472 panic("pmap_alloc_l1pt: pglist not empty"); 5473 #endif /* DIAGNOSTIC */ 5474 5475 pmap_init_l1(l1, pl1pt); 5476 } 5477 5478 #ifdef DEBUG 5479 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5480 needed); 5481 #endif 5482 } 5483 5484 /* 5485 * Note that the following routines are used by board-specific initialisation 5486 * code to configure the initial kernel page tables. 5487 * 5488 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5489 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5490 * behaviour of the old pmap, and provides an easy migration path for 5491 * initial bring-up of the new pmap on existing ports. Fortunately, 5492 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5493 * will be deprecated. 5494 * 5495 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5496 * tables. 5497 */ 5498 5499 /* 5500 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5501 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5502 * find them as necessary. 5503 * 5504 * Note that the data on this list MUST remain valid after initarm() returns, 5505 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5506 */ 5507 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5508 5509 static vaddr_t 5510 kernel_pt_lookup(paddr_t pa) 5511 { 5512 pv_addr_t *pv; 5513 5514 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5515 #ifndef ARM32_NEW_VM_LAYOUT 5516 if (pv->pv_pa == (pa & ~PGOFSET)) 5517 return (pv->pv_va | (pa & PGOFSET)); 5518 #else 5519 if (pv->pv_pa == pa) 5520 return (pv->pv_va); 5521 #endif 5522 } 5523 return (0); 5524 } 5525 5526 /* 5527 * pmap_map_section: 5528 * 5529 * Create a single section mapping. 5530 */ 5531 void 5532 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5533 { 5534 pd_entry_t *pde = (pd_entry_t *) l1pt; 5535 pd_entry_t fl; 5536 5537 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5538 5539 switch (cache) { 5540 case PTE_NOCACHE: 5541 default: 5542 fl = 0; 5543 break; 5544 5545 case PTE_CACHE: 5546 fl = pte_l1_s_cache_mode; 5547 break; 5548 5549 case PTE_PAGETABLE: 5550 fl = pte_l1_s_cache_mode_pt; 5551 break; 5552 } 5553 5554 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5555 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5556 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5557 } 5558 5559 /* 5560 * pmap_map_entry: 5561 * 5562 * Create a single page mapping. 5563 */ 5564 void 5565 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5566 { 5567 pd_entry_t *pde = (pd_entry_t *) l1pt; 5568 pt_entry_t fl; 5569 pt_entry_t *pte; 5570 5571 KASSERT(((va | pa) & PGOFSET) == 0); 5572 5573 switch (cache) { 5574 case PTE_NOCACHE: 5575 default: 5576 fl = 0; 5577 break; 5578 5579 case PTE_CACHE: 5580 fl = pte_l2_s_cache_mode; 5581 break; 5582 5583 case PTE_PAGETABLE: 5584 fl = pte_l2_s_cache_mode_pt; 5585 break; 5586 } 5587 5588 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5589 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5590 5591 #ifndef ARM32_NEW_VM_LAYOUT 5592 pte = (pt_entry_t *) 5593 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5594 #else 5595 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5596 #endif 5597 if (pte == NULL) 5598 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5599 5600 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5601 #ifndef ARM32_NEW_VM_LAYOUT 5602 pte += (va >> PGSHIFT) & 0x3ff; 5603 #else 5604 pte += l2pte_index(va); 5605 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5606 #endif 5607 *pte = fl; 5608 PTE_SYNC(pte); 5609 } 5610 5611 /* 5612 * pmap_link_l2pt: 5613 * 5614 * Link the L2 page table specified by "l2pv" into the L1 5615 * page table at the slot for "va". 5616 */ 5617 void 5618 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5619 { 5620 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5621 u_int slot = va >> L1_S_SHIFT; 5622 5623 #ifndef ARM32_NEW_VM_LAYOUT 5624 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5625 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5626 #endif 5627 5628 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5629 5630 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5631 #ifdef ARM32_NEW_VM_LAYOUT 5632 PTE_SYNC(&pde[slot]); 5633 #else 5634 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5635 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5636 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5637 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5638 #endif 5639 5640 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5641 } 5642 5643 /* 5644 * pmap_map_chunk: 5645 * 5646 * Map a chunk of memory using the most efficient mappings 5647 * possible (section, large page, small page) into the 5648 * provided L1 and L2 tables at the specified virtual address. 5649 */ 5650 vsize_t 5651 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5652 int prot, int cache) 5653 { 5654 pd_entry_t *pde = (pd_entry_t *) l1pt; 5655 pt_entry_t *pte, f1, f2s, f2l; 5656 vsize_t resid; 5657 int i; 5658 5659 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5660 5661 if (l1pt == 0) 5662 panic("pmap_map_chunk: no L1 table provided"); 5663 5664 #ifdef VERBOSE_INIT_ARM 5665 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5666 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5667 #endif 5668 5669 switch (cache) { 5670 case PTE_NOCACHE: 5671 default: 5672 f1 = 0; 5673 f2l = 0; 5674 f2s = 0; 5675 break; 5676 5677 case PTE_CACHE: 5678 f1 = pte_l1_s_cache_mode; 5679 f2l = pte_l2_l_cache_mode; 5680 f2s = pte_l2_s_cache_mode; 5681 break; 5682 5683 case PTE_PAGETABLE: 5684 f1 = pte_l1_s_cache_mode_pt; 5685 f2l = pte_l2_l_cache_mode_pt; 5686 f2s = pte_l2_s_cache_mode_pt; 5687 break; 5688 } 5689 5690 size = resid; 5691 5692 while (resid > 0) { 5693 /* See if we can use a section mapping. */ 5694 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5695 #ifdef VERBOSE_INIT_ARM 5696 printf("S"); 5697 #endif 5698 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5699 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5700 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5701 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5702 va += L1_S_SIZE; 5703 pa += L1_S_SIZE; 5704 resid -= L1_S_SIZE; 5705 continue; 5706 } 5707 5708 /* 5709 * Ok, we're going to use an L2 table. Make sure 5710 * one is actually in the corresponding L1 slot 5711 * for the current VA. 5712 */ 5713 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5714 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5715 5716 #ifndef ARM32_NEW_VM_LAYOUT 5717 pte = (pt_entry_t *) 5718 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5719 #else 5720 pte = (pt_entry_t *) kernel_pt_lookup( 5721 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5722 #endif 5723 if (pte == NULL) 5724 panic("pmap_map_chunk: can't find L2 table for VA" 5725 "0x%08lx", va); 5726 5727 /* See if we can use a L2 large page mapping. */ 5728 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5729 #ifdef VERBOSE_INIT_ARM 5730 printf("L"); 5731 #endif 5732 for (i = 0; i < 16; i++) { 5733 #ifndef ARM32_NEW_VM_LAYOUT 5734 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5735 L2_L_PROTO | pa | 5736 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5737 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5738 #else 5739 pte[l2pte_index(va) + i] = 5740 L2_L_PROTO | pa | 5741 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5742 PTE_SYNC(&pte[l2pte_index(va) + i]); 5743 #endif 5744 } 5745 va += L2_L_SIZE; 5746 pa += L2_L_SIZE; 5747 resid -= L2_L_SIZE; 5748 continue; 5749 } 5750 5751 /* Use a small page mapping. */ 5752 #ifdef VERBOSE_INIT_ARM 5753 printf("P"); 5754 #endif 5755 #ifndef ARM32_NEW_VM_LAYOUT 5756 pte[(va >> PGSHIFT) & 0x3ff] = 5757 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5758 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5759 #else 5760 pte[l2pte_index(va)] = 5761 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5762 PTE_SYNC(&pte[l2pte_index(va)]); 5763 #endif 5764 va += PAGE_SIZE; 5765 pa += PAGE_SIZE; 5766 resid -= PAGE_SIZE; 5767 } 5768 #ifdef VERBOSE_INIT_ARM 5769 printf("\n"); 5770 #endif 5771 return (size); 5772 } 5773 5774 /********************** Static device map routines ***************************/ 5775 5776 static const struct pmap_devmap *pmap_devmap_table; 5777 5778 /* 5779 * Register the devmap table. This is provided in case early console 5780 * initialization needs to register mappings created by bootstrap code 5781 * before pmap_devmap_bootstrap() is called. 5782 */ 5783 void 5784 pmap_devmap_register(const struct pmap_devmap *table) 5785 { 5786 5787 pmap_devmap_table = table; 5788 } 5789 5790 /* 5791 * Map all of the static regions in the devmap table, and remember 5792 * the devmap table so other parts of the kernel can look up entries 5793 * later. 5794 */ 5795 void 5796 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5797 { 5798 int i; 5799 5800 pmap_devmap_table = table; 5801 5802 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5803 #ifdef VERBOSE_INIT_ARM 5804 printf("devmap: %08lx -> %08lx @ %08lx\n", 5805 pmap_devmap_table[i].pd_pa, 5806 pmap_devmap_table[i].pd_pa + 5807 pmap_devmap_table[i].pd_size - 1, 5808 pmap_devmap_table[i].pd_va); 5809 #endif 5810 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5811 pmap_devmap_table[i].pd_pa, 5812 pmap_devmap_table[i].pd_size, 5813 pmap_devmap_table[i].pd_prot, 5814 pmap_devmap_table[i].pd_cache); 5815 } 5816 } 5817 5818 const struct pmap_devmap * 5819 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5820 { 5821 uint64_t endpa; 5822 int i; 5823 5824 if (pmap_devmap_table == NULL) 5825 return (NULL); 5826 5827 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5828 5829 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5830 if (pa >= pmap_devmap_table[i].pd_pa && 5831 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5832 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5833 return (&pmap_devmap_table[i]); 5834 } 5835 5836 return (NULL); 5837 } 5838 5839 const struct pmap_devmap * 5840 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5841 { 5842 int i; 5843 5844 if (pmap_devmap_table == NULL) 5845 return (NULL); 5846 5847 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5848 if (va >= pmap_devmap_table[i].pd_va && 5849 va + size - 1 <= pmap_devmap_table[i].pd_va + 5850 pmap_devmap_table[i].pd_size - 1) 5851 return (&pmap_devmap_table[i]); 5852 } 5853 5854 return (NULL); 5855 } 5856 5857 /********************** PTE initialization routines **************************/ 5858 5859 /* 5860 * These routines are called when the CPU type is identified to set up 5861 * the PTE prototypes, cache modes, etc. 5862 * 5863 * The variables are always here, just in case modules need to reference 5864 * them (though, they shouldn't). 5865 */ 5866 5867 pt_entry_t pte_l1_s_cache_mode; 5868 pt_entry_t pte_l1_s_cache_mode_pt; 5869 pt_entry_t pte_l1_s_cache_mask; 5870 5871 pt_entry_t pte_l2_l_cache_mode; 5872 pt_entry_t pte_l2_l_cache_mode_pt; 5873 pt_entry_t pte_l2_l_cache_mask; 5874 5875 pt_entry_t pte_l2_s_cache_mode; 5876 pt_entry_t pte_l2_s_cache_mode_pt; 5877 pt_entry_t pte_l2_s_cache_mask; 5878 5879 pt_entry_t pte_l2_s_prot_u; 5880 pt_entry_t pte_l2_s_prot_w; 5881 pt_entry_t pte_l2_s_prot_mask; 5882 5883 pt_entry_t pte_l1_s_proto; 5884 pt_entry_t pte_l1_c_proto; 5885 pt_entry_t pte_l2_s_proto; 5886 5887 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5888 void (*pmap_zero_page_func)(paddr_t); 5889 5890 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5891 void 5892 pmap_pte_init_generic(void) 5893 { 5894 5895 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5896 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5897 5898 pte_l2_l_cache_mode = L2_B|L2_C; 5899 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5900 5901 pte_l2_s_cache_mode = L2_B|L2_C; 5902 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5903 5904 /* 5905 * If we have a write-through cache, set B and C. If 5906 * we have a write-back cache, then we assume setting 5907 * only C will make those pages write-through. 5908 */ 5909 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5910 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5911 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5912 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5913 } else { 5914 #if ARM_MMU_V6 > 1 5915 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5916 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5917 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5918 #else 5919 pte_l1_s_cache_mode_pt = L1_S_C; 5920 pte_l2_l_cache_mode_pt = L2_C; 5921 pte_l2_s_cache_mode_pt = L2_C; 5922 #endif 5923 } 5924 5925 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5926 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5927 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5928 5929 pte_l1_s_proto = L1_S_PROTO_generic; 5930 pte_l1_c_proto = L1_C_PROTO_generic; 5931 pte_l2_s_proto = L2_S_PROTO_generic; 5932 5933 pmap_copy_page_func = pmap_copy_page_generic; 5934 pmap_zero_page_func = pmap_zero_page_generic; 5935 } 5936 5937 #if defined(CPU_ARM8) 5938 void 5939 pmap_pte_init_arm8(void) 5940 { 5941 5942 /* 5943 * ARM8 is compatible with generic, but we need to use 5944 * the page tables uncached. 5945 */ 5946 pmap_pte_init_generic(); 5947 5948 pte_l1_s_cache_mode_pt = 0; 5949 pte_l2_l_cache_mode_pt = 0; 5950 pte_l2_s_cache_mode_pt = 0; 5951 } 5952 #endif /* CPU_ARM8 */ 5953 5954 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5955 void 5956 pmap_pte_init_arm9(void) 5957 { 5958 5959 /* 5960 * ARM9 is compatible with generic, but we want to use 5961 * write-through caching for now. 5962 */ 5963 pmap_pte_init_generic(); 5964 5965 pte_l1_s_cache_mode = L1_S_C; 5966 pte_l2_l_cache_mode = L2_C; 5967 pte_l2_s_cache_mode = L2_C; 5968 5969 pte_l1_s_cache_mode_pt = L1_S_C; 5970 pte_l2_l_cache_mode_pt = L2_C; 5971 pte_l2_s_cache_mode_pt = L2_C; 5972 } 5973 #endif /* CPU_ARM9 */ 5974 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5975 5976 #if defined(CPU_ARM10) 5977 void 5978 pmap_pte_init_arm10(void) 5979 { 5980 5981 /* 5982 * ARM10 is compatible with generic, but we want to use 5983 * write-through caching for now. 5984 */ 5985 pmap_pte_init_generic(); 5986 5987 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 5988 pte_l2_l_cache_mode = L2_B | L2_C; 5989 pte_l2_s_cache_mode = L2_B | L2_C; 5990 5991 pte_l1_s_cache_mode_pt = L1_S_C; 5992 pte_l2_l_cache_mode_pt = L2_C; 5993 pte_l2_s_cache_mode_pt = L2_C; 5994 5995 } 5996 #endif /* CPU_ARM10 */ 5997 5998 #if ARM_MMU_SA1 == 1 5999 void 6000 pmap_pte_init_sa1(void) 6001 { 6002 6003 /* 6004 * The StrongARM SA-1 cache does not have a write-through 6005 * mode. So, do the generic initialization, then reset 6006 * the page table cache mode to B=1,C=1, and note that 6007 * the PTEs need to be sync'd. 6008 */ 6009 pmap_pte_init_generic(); 6010 6011 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6012 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6013 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6014 6015 pmap_needs_pte_sync = 1; 6016 } 6017 #endif /* ARM_MMU_SA1 == 1*/ 6018 6019 #if ARM_MMU_XSCALE == 1 6020 #if (ARM_NMMUS > 1) 6021 static u_int xscale_use_minidata; 6022 #endif 6023 6024 void 6025 pmap_pte_init_xscale(void) 6026 { 6027 uint32_t auxctl; 6028 int write_through = 0; 6029 6030 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6031 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6032 6033 pte_l2_l_cache_mode = L2_B|L2_C; 6034 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6035 6036 pte_l2_s_cache_mode = L2_B|L2_C; 6037 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6038 6039 pte_l1_s_cache_mode_pt = L1_S_C; 6040 pte_l2_l_cache_mode_pt = L2_C; 6041 pte_l2_s_cache_mode_pt = L2_C; 6042 6043 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6044 /* 6045 * The XScale core has an enhanced mode where writes that 6046 * miss the cache cause a cache line to be allocated. This 6047 * is significantly faster than the traditional, write-through 6048 * behavior of this case. 6049 */ 6050 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6051 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6052 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6053 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6054 6055 #ifdef XSCALE_CACHE_WRITE_THROUGH 6056 /* 6057 * Some versions of the XScale core have various bugs in 6058 * their cache units, the work-around for which is to run 6059 * the cache in write-through mode. Unfortunately, this 6060 * has a major (negative) impact on performance. So, we 6061 * go ahead and run fast-and-loose, in the hopes that we 6062 * don't line up the planets in a way that will trip the 6063 * bugs. 6064 * 6065 * However, we give you the option to be slow-but-correct. 6066 */ 6067 write_through = 1; 6068 #elif defined(XSCALE_CACHE_WRITE_BACK) 6069 /* force write back cache mode */ 6070 write_through = 0; 6071 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6072 /* 6073 * Intel PXA2[15]0 processors are known to have a bug in 6074 * write-back cache on revision 4 and earlier (stepping 6075 * A[01] and B[012]). Fixed for C0 and later. 6076 */ 6077 { 6078 uint32_t id, type; 6079 6080 id = cpufunc_id(); 6081 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6082 6083 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6084 if ((id & CPU_ID_REVISION_MASK) < 5) { 6085 /* write through for stepping A0-1 and B0-2 */ 6086 write_through = 1; 6087 } 6088 } 6089 } 6090 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6091 6092 if (write_through) { 6093 pte_l1_s_cache_mode = L1_S_C; 6094 pte_l2_l_cache_mode = L2_C; 6095 pte_l2_s_cache_mode = L2_C; 6096 } 6097 6098 #if (ARM_NMMUS > 1) 6099 xscale_use_minidata = 1; 6100 #endif 6101 6102 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6103 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6104 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6105 6106 pte_l1_s_proto = L1_S_PROTO_xscale; 6107 pte_l1_c_proto = L1_C_PROTO_xscale; 6108 pte_l2_s_proto = L2_S_PROTO_xscale; 6109 6110 pmap_copy_page_func = pmap_copy_page_xscale; 6111 pmap_zero_page_func = pmap_zero_page_xscale; 6112 6113 /* 6114 * Disable ECC protection of page table access, for now. 6115 */ 6116 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6117 auxctl &= ~XSCALE_AUXCTL_P; 6118 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6119 } 6120 6121 /* 6122 * xscale_setup_minidata: 6123 * 6124 * Set up the mini-data cache clean area. We require the 6125 * caller to allocate the right amount of physically and 6126 * virtually contiguous space. 6127 */ 6128 void 6129 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6130 { 6131 extern vaddr_t xscale_minidata_clean_addr; 6132 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6133 pd_entry_t *pde = (pd_entry_t *) l1pt; 6134 pt_entry_t *pte; 6135 vsize_t size; 6136 uint32_t auxctl; 6137 6138 xscale_minidata_clean_addr = va; 6139 6140 /* Round it to page size. */ 6141 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6142 6143 for (; size != 0; 6144 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6145 #ifndef ARM32_NEW_VM_LAYOUT 6146 pte = (pt_entry_t *) 6147 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6148 #else 6149 pte = (pt_entry_t *) kernel_pt_lookup( 6150 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6151 #endif 6152 if (pte == NULL) 6153 panic("xscale_setup_minidata: can't find L2 table for " 6154 "VA 0x%08lx", va); 6155 #ifndef ARM32_NEW_VM_LAYOUT 6156 pte[(va >> PGSHIFT) & 0x3ff] = 6157 #else 6158 pte[l2pte_index(va)] = 6159 #endif 6160 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6161 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6162 } 6163 6164 /* 6165 * Configure the mini-data cache for write-back with 6166 * read/write-allocate. 6167 * 6168 * NOTE: In order to reconfigure the mini-data cache, we must 6169 * make sure it contains no valid data! In order to do that, 6170 * we must issue a global data cache invalidate command! 6171 * 6172 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6173 * THIS IS VERY IMPORTANT! 6174 */ 6175 6176 /* Invalidate data and mini-data. */ 6177 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6178 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6179 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6180 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6181 } 6182 6183 /* 6184 * Change the PTEs for the specified kernel mappings such that they 6185 * will use the mini data cache instead of the main data cache. 6186 */ 6187 void 6188 pmap_uarea(vaddr_t va) 6189 { 6190 struct l2_bucket *l2b; 6191 pt_entry_t *ptep, *sptep, pte; 6192 vaddr_t next_bucket, eva; 6193 6194 #if (ARM_NMMUS > 1) 6195 if (xscale_use_minidata == 0) 6196 return; 6197 #endif 6198 6199 eva = va + USPACE; 6200 6201 while (va < eva) { 6202 next_bucket = L2_NEXT_BUCKET(va); 6203 if (next_bucket > eva) 6204 next_bucket = eva; 6205 6206 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6207 KDASSERT(l2b != NULL); 6208 6209 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6210 6211 while (va < next_bucket) { 6212 pte = *ptep; 6213 if (!l2pte_minidata(pte)) { 6214 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6215 cpu_tlb_flushD_SE(va); 6216 *ptep = pte & ~L2_B; 6217 } 6218 ptep++; 6219 va += PAGE_SIZE; 6220 } 6221 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6222 } 6223 cpu_cpwait(); 6224 } 6225 #endif /* ARM_MMU_XSCALE == 1 */ 6226 6227 /* 6228 * return the PA of the current L1 table, for use when handling a crash dump 6229 */ 6230 uint32_t pmap_kernel_L1_addr() 6231 { 6232 return pmap_kernel()->pm_l1->l1_physaddr; 6233 } 6234 6235 #if defined(DDB) 6236 /* 6237 * A couple of ddb-callable functions for dumping pmaps 6238 */ 6239 void pmap_dump_all(void); 6240 void pmap_dump(pmap_t); 6241 6242 void 6243 pmap_dump_all(void) 6244 { 6245 pmap_t pm; 6246 6247 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6248 if (pm == pmap_kernel()) 6249 continue; 6250 pmap_dump(pm); 6251 printf("\n"); 6252 } 6253 } 6254 6255 static pt_entry_t ncptes[64]; 6256 static void pmap_dump_ncpg(pmap_t); 6257 6258 void 6259 pmap_dump(pmap_t pm) 6260 { 6261 struct l2_dtable *l2; 6262 struct l2_bucket *l2b; 6263 pt_entry_t *ptep, pte; 6264 vaddr_t l2_va, l2b_va, va; 6265 int i, j, k, occ, rows = 0; 6266 6267 if (pm == pmap_kernel()) 6268 printf("pmap_kernel (%p): ", pm); 6269 else 6270 printf("user pmap (%p): ", pm); 6271 6272 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6273 6274 l2_va = 0; 6275 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6276 l2 = pm->pm_l2[i]; 6277 6278 if (l2 == NULL || l2->l2_occupancy == 0) 6279 continue; 6280 6281 l2b_va = l2_va; 6282 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6283 l2b = &l2->l2_bucket[j]; 6284 6285 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6286 continue; 6287 6288 ptep = l2b->l2b_kva; 6289 6290 for (k = 0; k < 256 && ptep[k] == 0; k++) 6291 ; 6292 6293 k &= ~63; 6294 occ = l2b->l2b_occupancy; 6295 va = l2b_va + (k * 4096); 6296 for (; k < 256; k++, va += 0x1000) { 6297 char ch = ' '; 6298 if ((k % 64) == 0) { 6299 if ((rows % 8) == 0) { 6300 printf( 6301 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6302 } 6303 printf("%08lx: ", va); 6304 } 6305 6306 ncptes[k & 63] = 0; 6307 pte = ptep[k]; 6308 if (pte == 0) { 6309 ch = '.'; 6310 } else { 6311 occ--; 6312 switch (pte & 0x0c) { 6313 case 0x00: 6314 ch = 'D'; /* No cache No buff */ 6315 break; 6316 case 0x04: 6317 ch = 'B'; /* No cache buff */ 6318 break; 6319 case 0x08: 6320 if (pte & 0x40) 6321 ch = 'm'; 6322 else 6323 ch = 'C'; /* Cache No buff */ 6324 break; 6325 case 0x0c: 6326 ch = 'F'; /* Cache Buff */ 6327 break; 6328 } 6329 6330 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6331 ch += 0x20; 6332 6333 if ((pte & 0xc) == 0) 6334 ncptes[k & 63] = pte; 6335 } 6336 6337 if ((k % 64) == 63) { 6338 rows++; 6339 printf("%c\n", ch); 6340 pmap_dump_ncpg(pm); 6341 if (occ == 0) 6342 break; 6343 } else 6344 printf("%c", ch); 6345 } 6346 } 6347 } 6348 } 6349 6350 static void 6351 pmap_dump_ncpg(pmap_t pm) 6352 { 6353 struct vm_page *pg; 6354 struct pv_entry *pv; 6355 int i; 6356 6357 for (i = 0; i < 63; i++) { 6358 if (ncptes[i] == 0) 6359 continue; 6360 6361 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6362 if (pg == NULL) 6363 continue; 6364 6365 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6366 VM_PAGE_TO_PHYS(pg), 6367 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 6368 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 6369 6370 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 6371 printf(" %c va 0x%08lx, flags 0x%x\n", 6372 (pm == pv->pv_pmap) ? '*' : ' ', 6373 pv->pv_va, pv->pv_flags); 6374 } 6375 } 6376 } 6377 #endif 6378 6379 #ifdef PMAP_STEAL_MEMORY 6380 void 6381 pmap_boot_pageadd(pv_addr_t *newpv) 6382 { 6383 pv_addr_t *pv, *npv; 6384 6385 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6386 if (newpv->pv_pa < pv->pv_va) { 6387 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6388 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6389 newpv->pv_size += pv->pv_size; 6390 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6391 } 6392 pv = NULL; 6393 } else { 6394 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6395 pv = npv) { 6396 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6397 KASSERT(pv->pv_pa < newpv->pv_pa); 6398 if (newpv->pv_pa > npv->pv_pa) 6399 continue; 6400 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6401 pv->pv_size += newpv->pv_size; 6402 return; 6403 } 6404 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6405 break; 6406 newpv->pv_size += npv->pv_size; 6407 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6408 SLIST_REMOVE_AFTER(newpv, pv_list); 6409 return; 6410 } 6411 } 6412 } 6413 6414 if (pv) { 6415 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6416 } else { 6417 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6418 } 6419 } 6420 6421 void 6422 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6423 pv_addr_t *rpv) 6424 { 6425 pv_addr_t *pv, **pvp; 6426 struct vm_physseg *ps; 6427 size_t i; 6428 6429 KASSERT(amount & PGOFSET); 6430 KASSERT((mask & PGOFSET) == 0); 6431 KASSERT((match & PGOFSET) == 0); 6432 KASSERT(amount != 0); 6433 6434 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6435 (pv = *pvp) != NULL; 6436 pvp = &SLIST_NEXT(pv, pv_list)) { 6437 pv_addr_t *newpv; 6438 psize_t off; 6439 /* 6440 * If this entry is too small to satify the request... 6441 */ 6442 KASSERT(pv->pv_size > 0); 6443 if (pv->pv_size < amount) 6444 continue; 6445 6446 for (off = 0; off <= mask; off += PAGE_SIZE) { 6447 if (((pv->pv_pa + off) & mask) == match 6448 && off + amount <= pv->pv_size) 6449 break; 6450 } 6451 if (off > mask) 6452 continue; 6453 6454 rpv->pv_va = pv->pv_va + off; 6455 rpv->pv_pa = pv->pv_pa + off; 6456 rpv->pv_size = amount; 6457 pv->pv_size -= amount; 6458 if (pv->pv_size == 0) { 6459 KASSERT(off == 0); 6460 KASSERT((vaddr_t) pv == rpv->pv_va); 6461 *pvp = SLIST_NEXT(pv, pv_list); 6462 } else if (off == 0) { 6463 KASSERT((vaddr_t) pv == rpv->pv_va); 6464 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6465 *newpv = *pv; 6466 newpv->pv_pa += amount; 6467 newpv->pv_va += amount; 6468 *pvp = newpv; 6469 } else if (off < pv->pv_size) { 6470 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6471 *newpv = *pv; 6472 newpv->pv_size -= off; 6473 newpv->pv_pa += off + amount; 6474 newpv->pv_va += off + amount; 6475 6476 SLIST_NEXT(pv, pv_list) = newpv; 6477 pv->pv_size = off; 6478 } else { 6479 KASSERT((vaddr_t) pv != rpv->pv_va); 6480 } 6481 memset((void *)rpv->pv_va, 0, amount); 6482 return; 6483 } 6484 6485 if (vm_nphysseg == 0) 6486 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6487 6488 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6489 (pv = *pvp) != NULL; 6490 pvp = &SLIST_NEXT(pv, pv_list)) { 6491 if (SLIST_NEXT(pv, pv_list) == NULL) 6492 break; 6493 } 6494 KASSERT(mask == 0); 6495 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6496 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6497 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6498 rpv->pv_va = pv->pv_va; 6499 rpv->pv_pa = pv->pv_pa; 6500 rpv->pv_size = amount; 6501 *pvp = NULL; 6502 pmap_map_chunk(kernel_l1pt.pv_va, 6503 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6504 ptoa(ps->avail_start), 6505 amount - pv->pv_size, 6506 VM_PROT_READ|VM_PROT_WRITE, 6507 PTE_CACHE); 6508 ps->avail_start += atop(amount - pv->pv_size); 6509 /* 6510 * If we consumed the entire physseg, remove it. 6511 */ 6512 if (ps->avail_start == ps->avail_end) { 6513 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6514 ps[0] = ps[1]; 6515 } 6516 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6517 return; 6518 } 6519 } 6520 6521 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6522 } 6523 6524 vaddr_t 6525 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6526 { 6527 pv_addr_t pv; 6528 6529 pmap_boot_pagealloc(size, 0, 0, &pv); 6530 6531 return pv.pv_va; 6532 } 6533 #endif /* PMAP_STEAL_MEMORY */ 6534 6535 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6536 { 6537 sysctl_createv(clog, 0, NULL, NULL, 6538 CTLFLAG_PERMANENT, 6539 CTLTYPE_NODE, "machdep", NULL, 6540 NULL, 0, NULL, 0, 6541 CTL_MACHDEP, CTL_EOL); 6542 6543 sysctl_createv(clog, 0, NULL, NULL, 6544 CTLFLAG_PERMANENT, 6545 CTLTYPE_INT, "kmpages", 6546 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6547 NULL, 0, &pmap_kmpages, 0, 6548 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6549 } 6550
Indexes created Sat Sep 27 22:09:54 GMT 2025