pmap.c revision 1.196
1 /* $NetBSD: pmap.c,v 1.196 2009/03/09 08:42:36 nonaka Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/user.h> 202 #include <sys/pool.h> 203 #include <sys/cdefs.h> 204 #include <sys/cpu.h> 205 #include <sys/sysctl.h> 206 207 #include <uvm/uvm.h> 208 209 #include <machine/bus.h> 210 #include <machine/pmap.h> 211 #include <machine/pcb.h> 212 #include <machine/param.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.196 2009/03/09 08:42:36 nonaka Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 #define PDB_EXEC 0x80000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 static struct pmap kernel_pmap_store; 259 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 260 261 /* 262 * Which pmap is currently 'live' in the cache 263 * 264 * XXXSCW: Fix for SMP ... 265 */ 266 static pmap_t pmap_recent_user; 267 268 /* 269 * Pointer to last active lwp, or NULL if it exited. 270 */ 271 struct lwp *pmap_previous_active_lwp; 272 273 /* 274 * Pool and cache that pmap structures are allocated from. 275 * We use a cache to avoid clearing the pm_l2[] array (1KB) 276 * in pmap_create(). 277 */ 278 static struct pool_cache pmap_cache; 279 static LIST_HEAD(, pmap) pmap_pmaps; 280 281 /* 282 * Pool of PV structures 283 */ 284 static struct pool pmap_pv_pool; 285 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 286 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 287 static struct pool_allocator pmap_bootstrap_pv_allocator = { 288 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 289 }; 290 291 /* 292 * Pool and cache of l2_dtable structures. 293 * We use a cache to avoid clearing the structures when they're 294 * allocated. (196 bytes) 295 */ 296 static struct pool_cache pmap_l2dtable_cache; 297 static vaddr_t pmap_kernel_l2dtable_kva; 298 299 /* 300 * Pool and cache of L2 page descriptors. 301 * We use a cache to avoid clearing the descriptor table 302 * when they're allocated. (1KB) 303 */ 304 static struct pool_cache pmap_l2ptp_cache; 305 static vaddr_t pmap_kernel_l2ptp_kva; 306 static paddr_t pmap_kernel_l2ptp_phys; 307 308 #ifdef PMAPCOUNTERS 309 #define PMAP_EVCNT_INITIALIZER(name) \ 310 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 311 312 #ifdef PMAP_CACHE_VIPT 313 static struct evcnt pmap_ev_vac_clean_one = 314 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 315 static struct evcnt pmap_ev_vac_flush_one = 316 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 317 static struct evcnt pmap_ev_vac_flush_lots = 318 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 319 static struct evcnt pmap_ev_vac_flush_lots2 = 320 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 325 326 static struct evcnt pmap_ev_vac_color_new = 327 PMAP_EVCNT_INITIALIZER("new page color"); 328 static struct evcnt pmap_ev_vac_color_reuse = 329 PMAP_EVCNT_INITIALIZER("ok first page color"); 330 static struct evcnt pmap_ev_vac_color_ok = 331 PMAP_EVCNT_INITIALIZER("ok page color"); 332 static struct evcnt pmap_ev_vac_color_blind = 333 PMAP_EVCNT_INITIALIZER("blind page color"); 334 static struct evcnt pmap_ev_vac_color_change = 335 PMAP_EVCNT_INITIALIZER("change page color"); 336 static struct evcnt pmap_ev_vac_color_erase = 337 PMAP_EVCNT_INITIALIZER("erase page color"); 338 static struct evcnt pmap_ev_vac_color_none = 339 PMAP_EVCNT_INITIALIZER("no page color"); 340 static struct evcnt pmap_ev_vac_color_restore = 341 PMAP_EVCNT_INITIALIZER("restore page color"); 342 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 351 #endif 352 353 static struct evcnt pmap_ev_mappings = 354 PMAP_EVCNT_INITIALIZER("pages mapped"); 355 static struct evcnt pmap_ev_unmappings = 356 PMAP_EVCNT_INITIALIZER("pages unmapped"); 357 static struct evcnt pmap_ev_remappings = 358 PMAP_EVCNT_INITIALIZER("pages remapped"); 359 360 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 362 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 363 364 static struct evcnt pmap_ev_kernel_mappings = 365 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 366 static struct evcnt pmap_ev_kernel_unmappings = 367 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 368 static struct evcnt pmap_ev_kernel_remappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 370 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 373 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 374 375 static struct evcnt pmap_ev_kenter_mappings = 376 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 377 static struct evcnt pmap_ev_kenter_unmappings = 378 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 379 static struct evcnt pmap_ev_kenter_remappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 381 static struct evcnt pmap_ev_pt_mappings = 382 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 383 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 387 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 388 389 #ifdef PMAP_CACHE_VIPT 390 static struct evcnt pmap_ev_exec_mappings = 391 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 392 static struct evcnt pmap_ev_exec_cached = 393 PMAP_EVCNT_INITIALIZER("exec pages cached"); 394 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 397 398 static struct evcnt pmap_ev_exec_synced = 399 PMAP_EVCNT_INITIALIZER("exec pages synced"); 400 static struct evcnt pmap_ev_exec_synced_map = 401 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 402 static struct evcnt pmap_ev_exec_synced_unmap = 403 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 404 static struct evcnt pmap_ev_exec_synced_remap = 405 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 406 static struct evcnt pmap_ev_exec_synced_clearbit = 407 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 408 static struct evcnt pmap_ev_exec_synced_kremove = 409 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 410 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 417 418 static struct evcnt pmap_ev_exec_discarded_unmap = 419 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 420 static struct evcnt pmap_ev_exec_discarded_zero = 421 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 422 static struct evcnt pmap_ev_exec_discarded_copy = 423 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 424 static struct evcnt pmap_ev_exec_discarded_page_protect = 425 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 426 static struct evcnt pmap_ev_exec_discarded_clearbit = 427 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 428 static struct evcnt pmap_ev_exec_discarded_kremove = 429 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 430 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 437 #endif /* PMAP_CACHE_VIPT */ 438 439 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 440 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 441 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 442 443 EVCNT_ATTACH_STATIC(pmap_ev_updates); 444 EVCNT_ATTACH_STATIC(pmap_ev_collects); 445 EVCNT_ATTACH_STATIC(pmap_ev_activations); 446 447 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 448 #else 449 #define PMAPCOUNT(x) ((void)0) 450 #endif 451 452 /* 453 * pmap copy/zero page, and mem(5) hook point 454 */ 455 static pt_entry_t *csrc_pte, *cdst_pte; 456 static vaddr_t csrcp, cdstp; 457 vaddr_t memhook; /* used by mem.c */ 458 kmutex_t memlock; /* used by mem.c */ 459 void *zeropage; /* used by mem.c */ 460 extern void *msgbufaddr; 461 int pmap_kmpages; 462 /* 463 * Flag to indicate if pmap_init() has done its thing 464 */ 465 bool pmap_initialized; 466 467 /* 468 * Misc. locking data structures 469 */ 470 471 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 472 static struct lock pmap_main_lock; 473 474 #define PMAP_MAP_TO_HEAD_LOCK() \ 475 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 476 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 477 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 478 #define PMAP_HEAD_TO_MAP_LOCK() \ 479 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 480 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 481 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 482 #else 483 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 484 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 485 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 486 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 487 #endif 488 489 #define pmap_acquire_pmap_lock(pm) \ 490 do { \ 491 if ((pm) != pmap_kernel()) \ 492 mutex_enter(&(pm)->pm_lock); \ 493 } while (/*CONSTCOND*/0) 494 495 #define pmap_release_pmap_lock(pm) \ 496 do { \ 497 if ((pm) != pmap_kernel()) \ 498 mutex_exit(&(pm)->pm_lock); \ 499 } while (/*CONSTCOND*/0) 500 501 502 /* 503 * Metadata for L1 translation tables. 504 */ 505 struct l1_ttable { 506 /* Entry on the L1 Table list */ 507 SLIST_ENTRY(l1_ttable) l1_link; 508 509 /* Entry on the L1 Least Recently Used list */ 510 TAILQ_ENTRY(l1_ttable) l1_lru; 511 512 /* Track how many domains are allocated from this L1 */ 513 volatile u_int l1_domain_use_count; 514 515 /* 516 * A free-list of domain numbers for this L1. 517 * We avoid using ffs() and a bitmap to track domains since ffs() 518 * is slow on ARM. 519 */ 520 u_int8_t l1_domain_first; 521 u_int8_t l1_domain_free[PMAP_DOMAINS]; 522 523 /* Physical address of this L1 page table */ 524 paddr_t l1_physaddr; 525 526 /* KVA of this L1 page table */ 527 pd_entry_t *l1_kva; 528 }; 529 530 /* 531 * Convert a virtual address into its L1 table index. That is, the 532 * index used to locate the L2 descriptor table pointer in an L1 table. 533 * This is basically used to index l1->l1_kva[]. 534 * 535 * Each L2 descriptor table represents 1MB of VA space. 536 */ 537 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 538 539 /* 540 * L1 Page Tables are tracked using a Least Recently Used list. 541 * - New L1s are allocated from the HEAD. 542 * - Freed L1s are added to the TAIl. 543 * - Recently accessed L1s (where an 'access' is some change to one of 544 * the userland pmaps which owns this L1) are moved to the TAIL. 545 */ 546 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 547 static struct simplelock l1_lru_lock; 548 549 /* 550 * A list of all L1 tables 551 */ 552 static SLIST_HEAD(, l1_ttable) l1_list; 553 554 /* 555 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 556 * 557 * This is normally 16MB worth L2 page descriptors for any given pmap. 558 * Reference counts are maintained for L2 descriptors so they can be 559 * freed when empty. 560 */ 561 struct l2_dtable { 562 /* The number of L2 page descriptors allocated to this l2_dtable */ 563 u_int l2_occupancy; 564 565 /* List of L2 page descriptors */ 566 struct l2_bucket { 567 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 568 paddr_t l2b_phys; /* Physical address of same */ 569 u_short l2b_l1idx; /* This L2 table's L1 index */ 570 u_short l2b_occupancy; /* How many active descriptors */ 571 } l2_bucket[L2_BUCKET_SIZE]; 572 }; 573 574 /* 575 * Given an L1 table index, calculate the corresponding l2_dtable index 576 * and bucket index within the l2_dtable. 577 */ 578 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 579 (L2_SIZE - 1)) 580 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 581 582 /* 583 * Given a virtual address, this macro returns the 584 * virtual address required to drop into the next L2 bucket. 585 */ 586 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 587 588 /* 589 * L2 allocation. 590 */ 591 #define pmap_alloc_l2_dtable() \ 592 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 593 #define pmap_free_l2_dtable(l2) \ 594 pool_cache_put(&pmap_l2dtable_cache, (l2)) 595 #define pmap_alloc_l2_ptp(pap) \ 596 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 597 PR_NOWAIT, (pap))) 598 599 /* 600 * We try to map the page tables write-through, if possible. However, not 601 * all CPUs have a write-through cache mode, so on those we have to sync 602 * the cache when we frob page tables. 603 * 604 * We try to evaluate this at compile time, if possible. However, it's 605 * not always possible to do that, hence this run-time var. 606 */ 607 int pmap_needs_pte_sync; 608 609 /* 610 * Real definition of pv_entry. 611 */ 612 struct pv_entry { 613 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 614 pmap_t pv_pmap; /* pmap where mapping lies */ 615 vaddr_t pv_va; /* virtual address for mapping */ 616 u_int pv_flags; /* flags */ 617 }; 618 619 /* 620 * Macro to determine if a mapping might be resident in the 621 * instruction cache and/or TLB 622 */ 623 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 624 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 625 626 /* 627 * Macro to determine if a mapping might be resident in the 628 * data cache and/or TLB 629 */ 630 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 631 632 /* 633 * Local prototypes 634 */ 635 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 636 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 637 pt_entry_t **); 638 static bool pmap_is_current(pmap_t); 639 static bool pmap_is_cached(pmap_t); 640 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 641 pmap_t, vaddr_t, u_int); 642 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 643 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t, int); 644 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 645 u_int, u_int); 646 647 static void pmap_pinit(pmap_t); 648 static int pmap_pmap_ctor(void *, void *, int); 649 650 static void pmap_alloc_l1(pmap_t); 651 static void pmap_free_l1(pmap_t); 652 static void pmap_use_l1(pmap_t); 653 654 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 655 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 656 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 657 static int pmap_l2ptp_ctor(void *, void *, int); 658 static int pmap_l2dtable_ctor(void *, void *, int); 659 660 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 661 #ifdef PMAP_CACHE_VIVT 662 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 663 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 664 #endif 665 666 static void pmap_clearbit(struct vm_page *, u_int); 667 #ifdef PMAP_CACHE_VIVT 668 static int pmap_clean_page(struct pv_entry *, bool); 669 #endif 670 #ifdef PMAP_CACHE_VIPT 671 static void pmap_syncicache_page(struct vm_page *); 672 enum pmap_flush_op { 673 PMAP_FLUSH_PRIMARY, 674 PMAP_FLUSH_SECONDARY, 675 PMAP_CLEAN_PRIMARY 676 }; 677 static void pmap_flush_page(struct vm_page *, enum pmap_flush_op); 678 #endif 679 static void pmap_page_remove(struct vm_page *); 680 681 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 682 static vaddr_t kernel_pt_lookup(paddr_t); 683 684 685 /* 686 * External function prototypes 687 */ 688 extern void bzero_page(vaddr_t); 689 extern void bcopy_page(vaddr_t, vaddr_t); 690 691 /* 692 * Misc variables 693 */ 694 vaddr_t virtual_avail; 695 vaddr_t virtual_end; 696 vaddr_t pmap_curmaxkvaddr; 697 698 paddr_t avail_start; 699 paddr_t avail_end; 700 701 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 702 pv_addr_t kernelpages; 703 pv_addr_t kernel_l1pt; 704 pv_addr_t systempage; 705 706 /* Function to set the debug level of the pmap code */ 707 708 #ifdef PMAP_DEBUG 709 void 710 pmap_debug(int level) 711 { 712 pmap_debug_level = level; 713 printf("pmap_debug: level=%d\n", pmap_debug_level); 714 } 715 #endif /* PMAP_DEBUG */ 716 717 /* 718 * A bunch of routines to conditionally flush the caches/TLB depending 719 * on whether the specified pmap actually needs to be flushed at any 720 * given time. 721 */ 722 static inline void 723 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 724 { 725 726 if (pm->pm_cstate.cs_tlb_id) 727 cpu_tlb_flushID_SE(va); 728 } 729 730 static inline void 731 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 732 { 733 734 if (pm->pm_cstate.cs_tlb_d) 735 cpu_tlb_flushD_SE(va); 736 } 737 738 static inline void 739 pmap_tlb_flushID(pmap_t pm) 740 { 741 742 if (pm->pm_cstate.cs_tlb_id) { 743 cpu_tlb_flushID(); 744 pm->pm_cstate.cs_tlb = 0; 745 } 746 } 747 748 static inline void 749 pmap_tlb_flushD(pmap_t pm) 750 { 751 752 if (pm->pm_cstate.cs_tlb_d) { 753 cpu_tlb_flushD(); 754 pm->pm_cstate.cs_tlb_d = 0; 755 } 756 } 757 758 #ifdef PMAP_CACHE_VIVT 759 static inline void 760 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 761 { 762 if (pm->pm_cstate.cs_cache_id) { 763 cpu_idcache_wbinv_range(va, len); 764 } 765 } 766 767 static inline void 768 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 769 bool do_inv, bool rd_only) 770 { 771 772 if (pm->pm_cstate.cs_cache_d) { 773 if (do_inv) { 774 if (rd_only) 775 cpu_dcache_inv_range(va, len); 776 else 777 cpu_dcache_wbinv_range(va, len); 778 } else 779 if (!rd_only) 780 cpu_dcache_wb_range(va, len); 781 } 782 } 783 784 static inline void 785 pmap_idcache_wbinv_all(pmap_t pm) 786 { 787 if (pm->pm_cstate.cs_cache_id) { 788 cpu_idcache_wbinv_all(); 789 pm->pm_cstate.cs_cache = 0; 790 } 791 } 792 793 static inline void 794 pmap_dcache_wbinv_all(pmap_t pm) 795 { 796 if (pm->pm_cstate.cs_cache_d) { 797 cpu_dcache_wbinv_all(); 798 pm->pm_cstate.cs_cache_d = 0; 799 } 800 } 801 #endif /* PMAP_CACHE_VIVT */ 802 803 static inline bool 804 pmap_is_current(pmap_t pm) 805 { 806 807 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 808 return true; 809 810 return false; 811 } 812 813 static inline bool 814 pmap_is_cached(pmap_t pm) 815 { 816 817 if (pm == pmap_kernel() || pmap_recent_user == NULL || 818 pmap_recent_user == pm) 819 return (true); 820 821 return false; 822 } 823 824 /* 825 * PTE_SYNC_CURRENT: 826 * 827 * Make sure the pte is written out to RAM. 828 * We need to do this for one of two cases: 829 * - We're dealing with the kernel pmap 830 * - There is no pmap active in the cache/tlb. 831 * - The specified pmap is 'active' in the cache/tlb. 832 */ 833 #ifdef PMAP_INCLUDE_PTE_SYNC 834 #define PTE_SYNC_CURRENT(pm, ptep) \ 835 do { \ 836 if (PMAP_NEEDS_PTE_SYNC && \ 837 pmap_is_cached(pm)) \ 838 PTE_SYNC(ptep); \ 839 } while (/*CONSTCOND*/0) 840 #else 841 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 842 #endif 843 844 /* 845 * main pv_entry manipulation functions: 846 * pmap_enter_pv: enter a mapping onto a vm_page list 847 * pmap_remove_pv: remove a mappiing from a vm_page list 848 * 849 * NOTE: pmap_enter_pv expects to lock the pvh itself 850 * pmap_remove_pv expects te caller to lock the pvh before calling 851 */ 852 853 /* 854 * pmap_enter_pv: enter a mapping onto a vm_page lst 855 * 856 * => caller should hold the proper lock on pmap_main_lock 857 * => caller should have pmap locked 858 * => we will gain the lock on the vm_page and allocate the new pv_entry 859 * => caller should adjust ptp's wire_count before calling 860 * => caller should not adjust pmap's wire_count 861 */ 862 static void 863 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 864 vaddr_t va, u_int flags) 865 { 866 struct pv_entry **pvp; 867 868 NPDEBUG(PDB_PVDUMP, 869 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 870 871 pve->pv_pmap = pm; 872 pve->pv_va = va; 873 pve->pv_flags = flags; 874 875 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 876 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 877 #ifdef PMAP_CACHE_VIPT 878 /* 879 * Insert unmanaged entries, writeable first, at the head of 880 * the pv list. 881 */ 882 if (__predict_true((flags & PVF_KENTRY) == 0)) { 883 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 884 pvp = &SLIST_NEXT(*pvp, pv_link); 885 } else if ((flags & PVF_WRITE) == 0) { 886 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 887 pvp = &SLIST_NEXT(*pvp, pv_link); 888 } 889 #endif 890 SLIST_NEXT(pve, pv_link) = *pvp; /* add to ... */ 891 *pvp = pve; /* ... locked list */ 892 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 893 #ifdef PMAP_CACHE_VIPT 894 if ((pve->pv_flags & PVF_KWRITE) == PVF_KWRITE) 895 pg->mdpage.pvh_attrs |= PVF_KMOD; 896 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 897 pg->mdpage.pvh_attrs |= PVF_DIRTY; 898 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 899 #endif 900 if (pm == pmap_kernel()) { 901 PMAPCOUNT(kernel_mappings); 902 if (flags & PVF_WRITE) 903 pg->mdpage.krw_mappings++; 904 else 905 pg->mdpage.kro_mappings++; 906 } else 907 if (flags & PVF_WRITE) 908 pg->mdpage.urw_mappings++; 909 else 910 pg->mdpage.uro_mappings++; 911 912 #ifdef PMAP_CACHE_VIPT 913 /* 914 * If this is an exec mapping and its the first exec mapping 915 * for this page, make sure to sync the I-cache. 916 */ 917 if (PV_IS_EXEC_P(flags)) { 918 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 919 pmap_syncicache_page(pg); 920 PMAPCOUNT(exec_synced_map); 921 } 922 PMAPCOUNT(exec_mappings); 923 } 924 #endif 925 926 PMAPCOUNT(mappings); 927 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 928 929 if (pve->pv_flags & PVF_WIRED) 930 ++pm->pm_stats.wired_count; 931 } 932 933 /* 934 * 935 * pmap_find_pv: Find a pv entry 936 * 937 * => caller should hold lock on vm_page 938 */ 939 static inline struct pv_entry * 940 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 941 { 942 struct pv_entry *pv; 943 944 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 945 if (pm == pv->pv_pmap && va == pv->pv_va) 946 break; 947 } 948 949 return (pv); 950 } 951 952 /* 953 * pmap_remove_pv: try to remove a mapping from a pv_list 954 * 955 * => caller should hold proper lock on pmap_main_lock 956 * => pmap should be locked 957 * => caller should hold lock on vm_page [so that attrs can be adjusted] 958 * => caller should adjust ptp's wire_count and free PTP if needed 959 * => caller should NOT adjust pmap's wire_count 960 * => we return the removed pve 961 */ 962 static struct pv_entry * 963 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired) 964 { 965 struct pv_entry *pve, **prevptr; 966 967 NPDEBUG(PDB_PVDUMP, 968 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 969 970 prevptr = &SLIST_FIRST(&pg->mdpage.pvh_list); /* prev pv_entry ptr */ 971 pve = *prevptr; 972 973 while (pve) { 974 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 975 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 976 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 977 if (pve->pv_flags & PVF_WIRED) { 978 if (skip_wired) 979 return (NULL); 980 --pm->pm_stats.wired_count; 981 } 982 *prevptr = SLIST_NEXT(pve, pv_link); /* remove it! */ 983 if (pm == pmap_kernel()) { 984 PMAPCOUNT(kernel_unmappings); 985 if (pve->pv_flags & PVF_WRITE) 986 pg->mdpage.krw_mappings--; 987 else 988 pg->mdpage.kro_mappings--; 989 } else 990 if (pve->pv_flags & PVF_WRITE) 991 pg->mdpage.urw_mappings--; 992 else 993 pg->mdpage.uro_mappings--; 994 995 PMAPCOUNT(unmappings); 996 #ifdef PMAP_CACHE_VIPT 997 if (!(pve->pv_flags & PVF_WRITE)) 998 break; 999 /* 1000 * If this page has had an exec mapping, then if 1001 * this was the last mapping, discard the contents, 1002 * otherwise sync the i-cache for this page. 1003 */ 1004 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 1005 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 1006 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 1007 PMAPCOUNT(exec_discarded_unmap); 1008 } else { 1009 pmap_syncicache_page(pg); 1010 PMAPCOUNT(exec_synced_unmap); 1011 } 1012 } 1013 #endif /* PMAP_CACHE_VIPT */ 1014 break; 1015 } 1016 prevptr = &SLIST_NEXT(pve, pv_link); /* previous pointer */ 1017 pve = *prevptr; /* advance */ 1018 } 1019 1020 #ifdef PMAP_CACHE_VIPT 1021 /* 1022 * If we no longer have a WRITEABLE KENTRY at the head of list, 1023 * clear the KMOD attribute from the page. 1024 */ 1025 if (SLIST_FIRST(&pg->mdpage.pvh_list) == NULL 1026 || (SLIST_FIRST(&pg->mdpage.pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1027 pg->mdpage.pvh_attrs &= ~PVF_KMOD; 1028 1029 /* 1030 * If this was a writeable page and there are no more writeable 1031 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1032 * the contents to memory. 1033 */ 1034 if (pg->mdpage.krw_mappings + pg->mdpage.urw_mappings == 0) 1035 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1036 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1037 #endif /* PMAP_CACHE_VIPT */ 1038 1039 return(pve); /* return removed pve */ 1040 } 1041 1042 /* 1043 * 1044 * pmap_modify_pv: Update pv flags 1045 * 1046 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1047 * => caller should NOT adjust pmap's wire_count 1048 * => caller must call pmap_vac_me_harder() if writable status of a page 1049 * may have changed. 1050 * => we return the old flags 1051 * 1052 * Modify a physical-virtual mapping in the pv table 1053 */ 1054 static u_int 1055 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 1056 u_int clr_mask, u_int set_mask) 1057 { 1058 struct pv_entry *npv; 1059 u_int flags, oflags; 1060 1061 KASSERT((clr_mask & PVF_KENTRY) == 0); 1062 KASSERT((set_mask & PVF_KENTRY) == 0); 1063 1064 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1065 return (0); 1066 1067 NPDEBUG(PDB_PVDUMP, 1068 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 1069 1070 /* 1071 * There is at least one VA mapping this page. 1072 */ 1073 1074 if (clr_mask & (PVF_REF | PVF_MOD)) { 1075 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1076 #ifdef PMAP_CACHE_VIPT 1077 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1078 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1079 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1080 #endif 1081 } 1082 1083 oflags = npv->pv_flags; 1084 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1085 1086 if ((flags ^ oflags) & PVF_WIRED) { 1087 if (flags & PVF_WIRED) 1088 ++pm->pm_stats.wired_count; 1089 else 1090 --pm->pm_stats.wired_count; 1091 } 1092 1093 if ((flags ^ oflags) & PVF_WRITE) { 1094 if (pm == pmap_kernel()) { 1095 if (flags & PVF_WRITE) { 1096 pg->mdpage.krw_mappings++; 1097 pg->mdpage.kro_mappings--; 1098 } else { 1099 pg->mdpage.kro_mappings++; 1100 pg->mdpage.krw_mappings--; 1101 } 1102 } else 1103 if (flags & PVF_WRITE) { 1104 pg->mdpage.urw_mappings++; 1105 pg->mdpage.uro_mappings--; 1106 } else { 1107 pg->mdpage.uro_mappings++; 1108 pg->mdpage.urw_mappings--; 1109 } 1110 } 1111 #ifdef PMAP_CACHE_VIPT 1112 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 1113 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1114 /* 1115 * We have two cases here: the first is from enter_pv (new exec 1116 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1117 * Since in latter, pmap_enter_pv won't do anything, we just have 1118 * to do what pmap_remove_pv would do. 1119 */ 1120 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1121 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1122 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1123 pmap_syncicache_page(pg); 1124 PMAPCOUNT(exec_synced_remap); 1125 } 1126 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1127 #endif 1128 1129 PMAPCOUNT(remappings); 1130 1131 return (oflags); 1132 } 1133 1134 /* 1135 * Allocate an L1 translation table for the specified pmap. 1136 * This is called at pmap creation time. 1137 */ 1138 static void 1139 pmap_alloc_l1(pmap_t pm) 1140 { 1141 struct l1_ttable *l1; 1142 u_int8_t domain; 1143 1144 /* 1145 * Remove the L1 at the head of the LRU list 1146 */ 1147 simple_lock(&l1_lru_lock); 1148 l1 = TAILQ_FIRST(&l1_lru_list); 1149 KDASSERT(l1 != NULL); 1150 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1151 1152 /* 1153 * Pick the first available domain number, and update 1154 * the link to the next number. 1155 */ 1156 domain = l1->l1_domain_first; 1157 l1->l1_domain_first = l1->l1_domain_free[domain]; 1158 1159 /* 1160 * If there are still free domain numbers in this L1, 1161 * put it back on the TAIL of the LRU list. 1162 */ 1163 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1164 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1165 1166 simple_unlock(&l1_lru_lock); 1167 1168 /* 1169 * Fix up the relevant bits in the pmap structure 1170 */ 1171 pm->pm_l1 = l1; 1172 pm->pm_domain = domain; 1173 } 1174 1175 /* 1176 * Free an L1 translation table. 1177 * This is called at pmap destruction time. 1178 */ 1179 static void 1180 pmap_free_l1(pmap_t pm) 1181 { 1182 struct l1_ttable *l1 = pm->pm_l1; 1183 1184 simple_lock(&l1_lru_lock); 1185 1186 /* 1187 * If this L1 is currently on the LRU list, remove it. 1188 */ 1189 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1190 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1191 1192 /* 1193 * Free up the domain number which was allocated to the pmap 1194 */ 1195 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1196 l1->l1_domain_first = pm->pm_domain; 1197 l1->l1_domain_use_count--; 1198 1199 /* 1200 * The L1 now must have at least 1 free domain, so add 1201 * it back to the LRU list. If the use count is zero, 1202 * put it at the head of the list, otherwise it goes 1203 * to the tail. 1204 */ 1205 if (l1->l1_domain_use_count == 0) 1206 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1207 else 1208 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1209 1210 simple_unlock(&l1_lru_lock); 1211 } 1212 1213 static inline void 1214 pmap_use_l1(pmap_t pm) 1215 { 1216 struct l1_ttable *l1; 1217 1218 /* 1219 * Do nothing if we're in interrupt context. 1220 * Access to an L1 by the kernel pmap must not affect 1221 * the LRU list. 1222 */ 1223 if (cpu_intr_p() || pm == pmap_kernel()) 1224 return; 1225 1226 l1 = pm->pm_l1; 1227 1228 /* 1229 * If the L1 is not currently on the LRU list, just return 1230 */ 1231 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1232 return; 1233 1234 simple_lock(&l1_lru_lock); 1235 1236 /* 1237 * Check the use count again, now that we've acquired the lock 1238 */ 1239 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1240 simple_unlock(&l1_lru_lock); 1241 return; 1242 } 1243 1244 /* 1245 * Move the L1 to the back of the LRU list 1246 */ 1247 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1248 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1249 1250 simple_unlock(&l1_lru_lock); 1251 } 1252 1253 /* 1254 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1255 * 1256 * Free an L2 descriptor table. 1257 */ 1258 static inline void 1259 #ifndef PMAP_INCLUDE_PTE_SYNC 1260 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1261 #else 1262 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1263 #endif 1264 { 1265 #ifdef PMAP_INCLUDE_PTE_SYNC 1266 #ifdef PMAP_CACHE_VIVT 1267 /* 1268 * Note: With a write-back cache, we may need to sync this 1269 * L2 table before re-using it. 1270 * This is because it may have belonged to a non-current 1271 * pmap, in which case the cache syncs would have been 1272 * skipped for the pages that were being unmapped. If the 1273 * L2 table were then to be immediately re-allocated to 1274 * the *current* pmap, it may well contain stale mappings 1275 * which have not yet been cleared by a cache write-back 1276 * and so would still be visible to the mmu. 1277 */ 1278 if (need_sync) 1279 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1280 #endif /* PMAP_CACHE_VIVT */ 1281 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1282 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1283 } 1284 1285 /* 1286 * Returns a pointer to the L2 bucket associated with the specified pmap 1287 * and VA, or NULL if no L2 bucket exists for the address. 1288 */ 1289 static inline struct l2_bucket * 1290 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1291 { 1292 struct l2_dtable *l2; 1293 struct l2_bucket *l2b; 1294 u_short l1idx; 1295 1296 l1idx = L1_IDX(va); 1297 1298 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1299 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1300 return (NULL); 1301 1302 return (l2b); 1303 } 1304 1305 /* 1306 * Returns a pointer to the L2 bucket associated with the specified pmap 1307 * and VA. 1308 * 1309 * If no L2 bucket exists, perform the necessary allocations to put an L2 1310 * bucket/page table in place. 1311 * 1312 * Note that if a new L2 bucket/page was allocated, the caller *must* 1313 * increment the bucket occupancy counter appropriately *before* 1314 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1315 * the bucket/page in the meantime. 1316 */ 1317 static struct l2_bucket * 1318 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1319 { 1320 struct l2_dtable *l2; 1321 struct l2_bucket *l2b; 1322 u_short l1idx; 1323 1324 l1idx = L1_IDX(va); 1325 1326 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1327 /* 1328 * No mapping at this address, as there is 1329 * no entry in the L1 table. 1330 * Need to allocate a new l2_dtable. 1331 */ 1332 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1333 return (NULL); 1334 1335 /* 1336 * Link it into the parent pmap 1337 */ 1338 pm->pm_l2[L2_IDX(l1idx)] = l2; 1339 } 1340 1341 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1342 1343 /* 1344 * Fetch pointer to the L2 page table associated with the address. 1345 */ 1346 if (l2b->l2b_kva == NULL) { 1347 pt_entry_t *ptep; 1348 1349 /* 1350 * No L2 page table has been allocated. Chances are, this 1351 * is because we just allocated the l2_dtable, above. 1352 */ 1353 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1354 /* 1355 * Oops, no more L2 page tables available at this 1356 * time. We may need to deallocate the l2_dtable 1357 * if we allocated a new one above. 1358 */ 1359 if (l2->l2_occupancy == 0) { 1360 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1361 pmap_free_l2_dtable(l2); 1362 } 1363 return (NULL); 1364 } 1365 1366 l2->l2_occupancy++; 1367 l2b->l2b_kva = ptep; 1368 l2b->l2b_l1idx = l1idx; 1369 } 1370 1371 return (l2b); 1372 } 1373 1374 /* 1375 * One or more mappings in the specified L2 descriptor table have just been 1376 * invalidated. 1377 * 1378 * Garbage collect the metadata and descriptor table itself if necessary. 1379 * 1380 * The pmap lock must be acquired when this is called (not necessary 1381 * for the kernel pmap). 1382 */ 1383 static void 1384 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1385 { 1386 struct l2_dtable *l2; 1387 pd_entry_t *pl1pd, l1pd; 1388 pt_entry_t *ptep; 1389 u_short l1idx; 1390 1391 KDASSERT(count <= l2b->l2b_occupancy); 1392 1393 /* 1394 * Update the bucket's reference count according to how many 1395 * PTEs the caller has just invalidated. 1396 */ 1397 l2b->l2b_occupancy -= count; 1398 1399 /* 1400 * Note: 1401 * 1402 * Level 2 page tables allocated to the kernel pmap are never freed 1403 * as that would require checking all Level 1 page tables and 1404 * removing any references to the Level 2 page table. See also the 1405 * comment elsewhere about never freeing bootstrap L2 descriptors. 1406 * 1407 * We make do with just invalidating the mapping in the L2 table. 1408 * 1409 * This isn't really a big deal in practice and, in fact, leads 1410 * to a performance win over time as we don't need to continually 1411 * alloc/free. 1412 */ 1413 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1414 return; 1415 1416 /* 1417 * There are no more valid mappings in this level 2 page table. 1418 * Go ahead and NULL-out the pointer in the bucket, then 1419 * free the page table. 1420 */ 1421 l1idx = l2b->l2b_l1idx; 1422 ptep = l2b->l2b_kva; 1423 l2b->l2b_kva = NULL; 1424 1425 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1426 1427 /* 1428 * If the L1 slot matches the pmap's domain 1429 * number, then invalidate it. 1430 */ 1431 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1432 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1433 *pl1pd = 0; 1434 PTE_SYNC(pl1pd); 1435 } 1436 1437 /* 1438 * Release the L2 descriptor table back to the pool cache. 1439 */ 1440 #ifndef PMAP_INCLUDE_PTE_SYNC 1441 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1442 #else 1443 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1444 #endif 1445 1446 /* 1447 * Update the reference count in the associated l2_dtable 1448 */ 1449 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1450 if (--l2->l2_occupancy > 0) 1451 return; 1452 1453 /* 1454 * There are no more valid mappings in any of the Level 1 1455 * slots managed by this l2_dtable. Go ahead and NULL-out 1456 * the pointer in the parent pmap and free the l2_dtable. 1457 */ 1458 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1459 pmap_free_l2_dtable(l2); 1460 } 1461 1462 /* 1463 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1464 * structures. 1465 */ 1466 static int 1467 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1468 { 1469 #ifndef PMAP_INCLUDE_PTE_SYNC 1470 struct l2_bucket *l2b; 1471 pt_entry_t *ptep, pte; 1472 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1473 1474 /* 1475 * The mappings for these page tables were initially made using 1476 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1477 * mode will not be right for page table mappings. To avoid 1478 * polluting the pmap_kenter_pa() code with a special case for 1479 * page tables, we simply fix up the cache-mode here if it's not 1480 * correct. 1481 */ 1482 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1483 KDASSERT(l2b != NULL); 1484 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1485 pte = *ptep; 1486 1487 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1488 /* 1489 * Page tables must have the cache-mode set to Write-Thru. 1490 */ 1491 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1492 PTE_SYNC(ptep); 1493 cpu_tlb_flushD_SE(va); 1494 cpu_cpwait(); 1495 } 1496 #endif 1497 1498 memset(v, 0, L2_TABLE_SIZE_REAL); 1499 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1500 return (0); 1501 } 1502 1503 static int 1504 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1505 { 1506 1507 memset(v, 0, sizeof(struct l2_dtable)); 1508 return (0); 1509 } 1510 1511 static int 1512 pmap_pmap_ctor(void *arg, void *v, int flags) 1513 { 1514 1515 memset(v, 0, sizeof(struct pmap)); 1516 return (0); 1517 } 1518 1519 static void 1520 pmap_pinit(pmap_t pm) 1521 { 1522 struct l2_bucket *l2b; 1523 1524 if (vector_page < KERNEL_BASE) { 1525 /* 1526 * Map the vector page. 1527 */ 1528 pmap_enter(pm, vector_page, systempage.pv_pa, 1529 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1530 pmap_update(pm); 1531 1532 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1533 l2b = pmap_get_l2_bucket(pm, vector_page); 1534 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1535 L1_C_DOM(pm->pm_domain); 1536 } else 1537 pm->pm_pl1vec = NULL; 1538 } 1539 1540 #ifdef PMAP_CACHE_VIVT 1541 /* 1542 * Since we have a virtually indexed cache, we may need to inhibit caching if 1543 * there is more than one mapping and at least one of them is writable. 1544 * Since we purge the cache on every context switch, we only need to check for 1545 * other mappings within the same pmap, or kernel_pmap. 1546 * This function is also called when a page is unmapped, to possibly reenable 1547 * caching on any remaining mappings. 1548 * 1549 * The code implements the following logic, where: 1550 * 1551 * KW = # of kernel read/write pages 1552 * KR = # of kernel read only pages 1553 * UW = # of user read/write pages 1554 * UR = # of user read only pages 1555 * 1556 * KC = kernel mapping is cacheable 1557 * UC = user mapping is cacheable 1558 * 1559 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1560 * +--------------------------------------------- 1561 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1562 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1563 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1564 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1565 */ 1566 1567 static const int pmap_vac_flags[4][4] = { 1568 {-1, 0, 0, PVF_KNC}, 1569 {0, 0, PVF_NC, PVF_NC}, 1570 {0, PVF_NC, PVF_NC, PVF_NC}, 1571 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1572 }; 1573 1574 static inline int 1575 pmap_get_vac_flags(const struct vm_page *pg) 1576 { 1577 int kidx, uidx; 1578 1579 kidx = 0; 1580 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1581 kidx |= 1; 1582 if (pg->mdpage.krw_mappings) 1583 kidx |= 2; 1584 1585 uidx = 0; 1586 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1587 uidx |= 1; 1588 if (pg->mdpage.urw_mappings) 1589 uidx |= 2; 1590 1591 return (pmap_vac_flags[uidx][kidx]); 1592 } 1593 1594 static inline void 1595 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1596 { 1597 int nattr; 1598 1599 nattr = pmap_get_vac_flags(pg); 1600 1601 if (nattr < 0) { 1602 pg->mdpage.pvh_attrs &= ~PVF_NC; 1603 return; 1604 } 1605 1606 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1607 return; 1608 1609 if (pm == pmap_kernel()) 1610 pmap_vac_me_kpmap(pg, pm, va); 1611 else 1612 pmap_vac_me_user(pg, pm, va); 1613 1614 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1615 } 1616 1617 static void 1618 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1619 { 1620 u_int u_cacheable, u_entries; 1621 struct pv_entry *pv; 1622 pmap_t last_pmap = pm; 1623 1624 /* 1625 * Pass one, see if there are both kernel and user pmaps for 1626 * this page. Calculate whether there are user-writable or 1627 * kernel-writable pages. 1628 */ 1629 u_cacheable = 0; 1630 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1631 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1632 u_cacheable++; 1633 } 1634 1635 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1636 1637 /* 1638 * We know we have just been updating a kernel entry, so if 1639 * all user pages are already cacheable, then there is nothing 1640 * further to do. 1641 */ 1642 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1643 return; 1644 1645 if (u_entries) { 1646 /* 1647 * Scan over the list again, for each entry, if it 1648 * might not be set correctly, call pmap_vac_me_user 1649 * to recalculate the settings. 1650 */ 1651 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1652 /* 1653 * We know kernel mappings will get set 1654 * correctly in other calls. We also know 1655 * that if the pmap is the same as last_pmap 1656 * then we've just handled this entry. 1657 */ 1658 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1659 continue; 1660 1661 /* 1662 * If there are kernel entries and this page 1663 * is writable but non-cacheable, then we can 1664 * skip this entry also. 1665 */ 1666 if (pg->mdpage.k_mappings && 1667 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1668 (PVF_NC | PVF_WRITE)) 1669 continue; 1670 1671 /* 1672 * Similarly if there are no kernel-writable 1673 * entries and the page is already 1674 * read-only/cacheable. 1675 */ 1676 if (pg->mdpage.krw_mappings == 0 && 1677 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1678 continue; 1679 1680 /* 1681 * For some of the remaining cases, we know 1682 * that we must recalculate, but for others we 1683 * can't tell if they are correct or not, so 1684 * we recalculate anyway. 1685 */ 1686 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1687 } 1688 1689 if (pg->mdpage.k_mappings == 0) 1690 return; 1691 } 1692 1693 pmap_vac_me_user(pg, pm, va); 1694 } 1695 1696 static void 1697 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1698 { 1699 pmap_t kpmap = pmap_kernel(); 1700 struct pv_entry *pv, *npv = NULL; 1701 struct l2_bucket *l2b; 1702 pt_entry_t *ptep, pte; 1703 u_int entries = 0; 1704 u_int writable = 0; 1705 u_int cacheable_entries = 0; 1706 u_int kern_cacheable = 0; 1707 u_int other_writable = 0; 1708 1709 /* 1710 * Count mappings and writable mappings in this pmap. 1711 * Include kernel mappings as part of our own. 1712 * Keep a pointer to the first one. 1713 */ 1714 npv = NULL; 1715 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1716 /* Count mappings in the same pmap */ 1717 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1718 if (entries++ == 0) 1719 npv = pv; 1720 1721 /* Cacheable mappings */ 1722 if ((pv->pv_flags & PVF_NC) == 0) { 1723 cacheable_entries++; 1724 if (kpmap == pv->pv_pmap) 1725 kern_cacheable++; 1726 } 1727 1728 /* Writable mappings */ 1729 if (pv->pv_flags & PVF_WRITE) 1730 ++writable; 1731 } else 1732 if (pv->pv_flags & PVF_WRITE) 1733 other_writable = 1; 1734 } 1735 1736 /* 1737 * Enable or disable caching as necessary. 1738 * Note: the first entry might be part of the kernel pmap, 1739 * so we can't assume this is indicative of the state of the 1740 * other (maybe non-kpmap) entries. 1741 */ 1742 if ((entries > 1 && writable) || 1743 (entries > 0 && pm == kpmap && other_writable)) { 1744 if (cacheable_entries == 0) 1745 return; 1746 1747 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1748 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1749 (pv->pv_flags & PVF_NC)) 1750 continue; 1751 1752 pv->pv_flags |= PVF_NC; 1753 1754 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1755 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1756 pte = *ptep & ~L2_S_CACHE_MASK; 1757 1758 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1759 l2pte_valid(pte)) { 1760 if (PV_BEEN_EXECD(pv->pv_flags)) { 1761 #ifdef PMAP_CACHE_VIVT 1762 pmap_idcache_wbinv_range(pv->pv_pmap, 1763 pv->pv_va, PAGE_SIZE); 1764 #endif 1765 pmap_tlb_flushID_SE(pv->pv_pmap, 1766 pv->pv_va); 1767 } else 1768 if (PV_BEEN_REFD(pv->pv_flags)) { 1769 #ifdef PMAP_CACHE_VIVT 1770 pmap_dcache_wb_range(pv->pv_pmap, 1771 pv->pv_va, PAGE_SIZE, true, 1772 (pv->pv_flags & PVF_WRITE) == 0); 1773 #endif 1774 pmap_tlb_flushD_SE(pv->pv_pmap, 1775 pv->pv_va); 1776 } 1777 } 1778 1779 *ptep = pte; 1780 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1781 } 1782 cpu_cpwait(); 1783 } else 1784 if (entries > cacheable_entries) { 1785 /* 1786 * Turn cacheing back on for some pages. If it is a kernel 1787 * page, only do so if there are no other writable pages. 1788 */ 1789 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1790 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1791 (kpmap != pv->pv_pmap || other_writable))) 1792 continue; 1793 1794 pv->pv_flags &= ~PVF_NC; 1795 1796 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1797 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1798 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1799 1800 if (l2pte_valid(pte)) { 1801 if (PV_BEEN_EXECD(pv->pv_flags)) { 1802 pmap_tlb_flushID_SE(pv->pv_pmap, 1803 pv->pv_va); 1804 } else 1805 if (PV_BEEN_REFD(pv->pv_flags)) { 1806 pmap_tlb_flushD_SE(pv->pv_pmap, 1807 pv->pv_va); 1808 } 1809 } 1810 1811 *ptep = pte; 1812 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1813 } 1814 } 1815 } 1816 #endif 1817 1818 #ifdef PMAP_CACHE_VIPT 1819 static void 1820 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1821 { 1822 struct pv_entry *pv; 1823 vaddr_t tst_mask; 1824 bool bad_alias; 1825 struct l2_bucket *l2b; 1826 pt_entry_t *ptep, pte, opte; 1827 const u_int 1828 rw_mappings = pg->mdpage.urw_mappings + pg->mdpage.krw_mappings, 1829 ro_mappings = pg->mdpage.uro_mappings + pg->mdpage.kro_mappings; 1830 1831 /* do we need to do anything? */ 1832 if (arm_cache_prefer_mask == 0) 1833 return; 1834 1835 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1836 pg, pm, va)); 1837 1838 KASSERT(!va || pm); 1839 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1840 1841 /* Already a conflict? */ 1842 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1843 /* just an add, things are already non-cached */ 1844 KASSERT(!(pg->mdpage.pvh_attrs & PVF_DIRTY)); 1845 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 1846 bad_alias = false; 1847 if (va) { 1848 PMAPCOUNT(vac_color_none); 1849 bad_alias = true; 1850 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1851 goto fixup; 1852 } 1853 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1854 /* the list can't be empty because it would be cachable */ 1855 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) { 1856 tst_mask = pg->mdpage.pvh_attrs; 1857 } else { 1858 KASSERT(pv); 1859 tst_mask = pv->pv_va; 1860 pv = SLIST_NEXT(pv, pv_link); 1861 } 1862 /* 1863 * Only check for a bad alias if we have writable mappings. 1864 */ 1865 tst_mask &= arm_cache_prefer_mask; 1866 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1867 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1868 /* if there's a bad alias, stop checking. */ 1869 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1870 bad_alias = true; 1871 } 1872 pg->mdpage.pvh_attrs |= PVF_WRITE; 1873 if (!bad_alias) 1874 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1875 } else { 1876 /* 1877 * We have only read-only mappings. Let's see if there 1878 * are multiple colors in use or if we mapped a KMPAGE. 1879 * If the latter, we have a bad alias. If the former, 1880 * we need to remember that. 1881 */ 1882 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1883 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1884 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) 1885 bad_alias = true; 1886 break; 1887 } 1888 } 1889 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1890 /* 1891 * No KMPAGE and we exited early, so we must have 1892 * multiple color mappings. 1893 */ 1894 if (!bad_alias && pv != NULL) 1895 pg->mdpage.pvh_attrs |= PVF_MULTCLR; 1896 } 1897 1898 /* If no conflicting colors, set everything back to cached */ 1899 if (!bad_alias) { 1900 #ifdef DEBUG 1901 if ((pg->mdpage.pvh_attrs & PVF_WRITE) 1902 || ro_mappings < 2) { 1903 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1904 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1905 } 1906 #endif 1907 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1908 pg->mdpage.pvh_attrs |= tst_mask | PVF_COLORED; 1909 /* 1910 * Restore DIRTY bit if page is modified 1911 */ 1912 if (pg->mdpage.pvh_attrs & PVF_DMOD) 1913 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1914 PMAPCOUNT(vac_color_restore); 1915 } else { 1916 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1917 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1918 } 1919 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1920 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1921 } else if (!va) { 1922 KASSERT(pmap_is_page_colored_p(pg)); 1923 KASSERT(!(pg->mdpage.pvh_attrs & PVF_WRITE) 1924 || (pg->mdpage.pvh_attrs & PVF_DIRTY)); 1925 if (rw_mappings == 0) { 1926 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1927 if (ro_mappings == 1 1928 && (pg->mdpage.pvh_attrs & PVF_MULTCLR)) { 1929 /* 1930 * If this is the last readonly mapping 1931 * but it doesn't match the current color 1932 * for the page, change the current color 1933 * to match this last readonly mapping. 1934 */ 1935 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1936 tst_mask = (pg->mdpage.pvh_attrs ^ pv->pv_va) 1937 & arm_cache_prefer_mask; 1938 if (tst_mask) { 1939 pg->mdpage.pvh_attrs ^= tst_mask; 1940 PMAPCOUNT(vac_color_change); 1941 } 1942 } 1943 } 1944 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1945 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1946 return; 1947 } else if (!pmap_is_page_colored_p(pg)) { 1948 /* not colored so we just use its color */ 1949 KASSERT(pg->mdpage.pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1950 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 1951 PMAPCOUNT(vac_color_new); 1952 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1953 pg->mdpage.pvh_attrs |= PVF_COLORED 1954 | (va & arm_cache_prefer_mask) 1955 | (rw_mappings > 0 ? PVF_WRITE : 0); 1956 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1957 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1958 return; 1959 } else if (((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1960 bad_alias = false; 1961 if (rw_mappings > 0) { 1962 /* 1963 * We now have writeable mappings and if we have 1964 * readonly mappings in more than once color, we have 1965 * an aliasing problem. Regardless mark the page as 1966 * writeable. 1967 */ 1968 if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 1969 if (ro_mappings < 2) { 1970 /* 1971 * If we only have less than two 1972 * read-only mappings, just flush the 1973 * non-primary colors from the cache. 1974 */ 1975 pmap_flush_page(pg, 1976 PMAP_FLUSH_SECONDARY); 1977 } else { 1978 bad_alias = true; 1979 } 1980 } 1981 pg->mdpage.pvh_attrs |= PVF_WRITE; 1982 } 1983 /* If no conflicting colors, set everything back to cached */ 1984 if (!bad_alias) { 1985 #ifdef DEBUG 1986 if (rw_mappings > 0 1987 || (pg->mdpage.pvh_attrs & PMAP_KMPAGE)) { 1988 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1989 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1990 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1991 } 1992 #endif 1993 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) 1994 PMAPCOUNT(vac_color_reuse); 1995 else 1996 PMAPCOUNT(vac_color_ok); 1997 1998 /* matching color, just return */ 1999 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2000 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2001 return; 2002 } 2003 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 2004 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 2005 2006 /* color conflict. evict from cache. */ 2007 2008 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 2009 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2010 pg->mdpage.pvh_attrs |= PVF_NC; 2011 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2012 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 2013 PMAPCOUNT(vac_color_erase); 2014 } else if (rw_mappings == 0 2015 && (pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2016 KASSERT((pg->mdpage.pvh_attrs & PVF_WRITE) == 0); 2017 2018 /* 2019 * If the page has dirty cache lines, clean it. 2020 */ 2021 if (pg->mdpage.pvh_attrs & PVF_DIRTY) 2022 pmap_flush_page(pg, PMAP_CLEAN_PRIMARY); 2023 2024 /* 2025 * If this is the first remapping (we know that there are no 2026 * writeable mappings), then this is a simple color change. 2027 * Otherwise this is a seconary r/o mapping, which means 2028 * we don't have to do anything. 2029 */ 2030 if (ro_mappings == 1) { 2031 KASSERT(((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2032 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2033 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2034 PMAPCOUNT(vac_color_change); 2035 } else { 2036 PMAPCOUNT(vac_color_blind); 2037 } 2038 pg->mdpage.pvh_attrs |= PVF_MULTCLR; 2039 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2040 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2041 return; 2042 } else { 2043 if (rw_mappings > 0) 2044 pg->mdpage.pvh_attrs |= PVF_WRITE; 2045 2046 /* color conflict. evict from cache. */ 2047 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 2048 2049 /* the list can't be empty because this was a enter/modify */ 2050 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2051 if ((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2052 KASSERT(pv); 2053 /* 2054 * If there's only one mapped page, change color to the 2055 * page's new color and return. Restore the DIRTY bit 2056 * that was erased by pmap_flush_page. 2057 */ 2058 if (SLIST_NEXT(pv, pv_link) == NULL) { 2059 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2060 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2061 if (pg->mdpage.pvh_attrs & PVF_DMOD) 2062 pg->mdpage.pvh_attrs |= PVF_DIRTY; 2063 PMAPCOUNT(vac_color_change); 2064 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2065 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2066 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 2067 return; 2068 } 2069 } 2070 bad_alias = true; 2071 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2072 pg->mdpage.pvh_attrs |= PVF_NC; 2073 PMAPCOUNT(vac_color_erase); 2074 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2075 } 2076 2077 fixup: 2078 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2079 2080 /* 2081 * Turn cacheing on/off for all pages. 2082 */ 2083 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2084 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2085 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2086 opte = *ptep; 2087 pte = opte & ~L2_S_CACHE_MASK; 2088 if (bad_alias) { 2089 pv->pv_flags |= PVF_NC; 2090 } else { 2091 pv->pv_flags &= ~PVF_NC; 2092 pte |= pte_l2_s_cache_mode; 2093 } 2094 2095 if (opte == pte) /* only update is there's a change */ 2096 continue; 2097 2098 if (l2pte_valid(pte)) { 2099 if (PV_BEEN_EXECD(pv->pv_flags)) { 2100 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2101 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2102 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2103 } 2104 } 2105 2106 *ptep = pte; 2107 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2108 } 2109 } 2110 #endif /* PMAP_CACHE_VIPT */ 2111 2112 2113 /* 2114 * Modify pte bits for all ptes corresponding to the given physical address. 2115 * We use `maskbits' rather than `clearbits' because we're always passing 2116 * constants and the latter would require an extra inversion at run-time. 2117 */ 2118 static void 2119 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2120 { 2121 struct l2_bucket *l2b; 2122 struct pv_entry *pv; 2123 pt_entry_t *ptep, npte, opte; 2124 pmap_t pm; 2125 vaddr_t va; 2126 u_int oflags; 2127 #ifdef PMAP_CACHE_VIPT 2128 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 2129 bool need_syncicache = false; 2130 bool did_syncicache = false; 2131 bool need_vac_me_harder = false; 2132 #endif 2133 2134 NPDEBUG(PDB_BITS, 2135 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2136 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2137 2138 PMAP_HEAD_TO_MAP_LOCK(); 2139 simple_lock(&pg->mdpage.pvh_slock); 2140 2141 #ifdef PMAP_CACHE_VIPT 2142 /* 2143 * If we might want to sync the I-cache and we've modified it, 2144 * then we know we definitely need to sync or discard it. 2145 */ 2146 if (want_syncicache) 2147 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 2148 #endif 2149 /* 2150 * Clear saved attributes (modify, reference) 2151 */ 2152 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2153 2154 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 2155 #ifdef PMAP_CACHE_VIPT 2156 if (need_syncicache) { 2157 /* 2158 * No one has it mapped, so just discard it. The next 2159 * exec remapping will cause it to be synced. 2160 */ 2161 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2162 PMAPCOUNT(exec_discarded_clearbit); 2163 } 2164 #endif 2165 simple_unlock(&pg->mdpage.pvh_slock); 2166 PMAP_HEAD_TO_MAP_UNLOCK(); 2167 return; 2168 } 2169 2170 /* 2171 * Loop over all current mappings setting/clearing as appropos 2172 */ 2173 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2174 va = pv->pv_va; 2175 pm = pv->pv_pmap; 2176 oflags = pv->pv_flags; 2177 /* 2178 * Kernel entries are unmanaged and as such not to be changed. 2179 */ 2180 if (oflags & PVF_KENTRY) 2181 continue; 2182 pv->pv_flags &= ~maskbits; 2183 2184 pmap_acquire_pmap_lock(pm); 2185 2186 l2b = pmap_get_l2_bucket(pm, va); 2187 KDASSERT(l2b != NULL); 2188 2189 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2190 npte = opte = *ptep; 2191 2192 NPDEBUG(PDB_BITS, 2193 printf( 2194 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2195 pv, pv->pv_pmap, pv->pv_va, oflags)); 2196 2197 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2198 #ifdef PMAP_CACHE_VIVT 2199 if ((pv->pv_flags & PVF_NC)) { 2200 /* 2201 * Entry is not cacheable: 2202 * 2203 * Don't turn caching on again if this is a 2204 * modified emulation. This would be 2205 * inconsitent with the settings created by 2206 * pmap_vac_me_harder(). Otherwise, it's safe 2207 * to re-enable cacheing. 2208 * 2209 * There's no need to call pmap_vac_me_harder() 2210 * here: all pages are losing their write 2211 * permission. 2212 */ 2213 if (maskbits & PVF_WRITE) { 2214 npte |= pte_l2_s_cache_mode; 2215 pv->pv_flags &= ~PVF_NC; 2216 } 2217 } else 2218 if (opte & L2_S_PROT_W) { 2219 /* 2220 * Entry is writable/cacheable: check if pmap 2221 * is current if it is flush it, otherwise it 2222 * won't be in the cache 2223 */ 2224 if (PV_BEEN_EXECD(oflags)) 2225 pmap_idcache_wbinv_range(pm, pv->pv_va, 2226 PAGE_SIZE); 2227 else 2228 if (PV_BEEN_REFD(oflags)) 2229 pmap_dcache_wb_range(pm, pv->pv_va, 2230 PAGE_SIZE, 2231 (maskbits & PVF_REF) != 0, false); 2232 } 2233 #endif 2234 2235 /* make the pte read only */ 2236 npte &= ~L2_S_PROT_W; 2237 2238 if (maskbits & oflags & PVF_WRITE) { 2239 /* 2240 * Keep alias accounting up to date 2241 */ 2242 if (pv->pv_pmap == pmap_kernel()) { 2243 pg->mdpage.krw_mappings--; 2244 pg->mdpage.kro_mappings++; 2245 } else { 2246 pg->mdpage.urw_mappings--; 2247 pg->mdpage.uro_mappings++; 2248 } 2249 #ifdef PMAP_CACHE_VIPT 2250 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 2251 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2252 if (want_syncicache) 2253 need_syncicache = true; 2254 need_vac_me_harder = true; 2255 #endif 2256 } 2257 } 2258 2259 if (maskbits & PVF_REF) { 2260 if ((pv->pv_flags & PVF_NC) == 0 && 2261 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2262 l2pte_valid(npte)) { 2263 #ifdef PMAP_CACHE_VIVT 2264 /* 2265 * Check npte here; we may have already 2266 * done the wbinv above, and the validity 2267 * of the PTE is the same for opte and 2268 * npte. 2269 */ 2270 /* XXXJRT need idcache_inv_range */ 2271 if (PV_BEEN_EXECD(oflags)) 2272 pmap_idcache_wbinv_range(pm, 2273 pv->pv_va, PAGE_SIZE); 2274 else 2275 if (PV_BEEN_REFD(oflags)) 2276 pmap_dcache_wb_range(pm, 2277 pv->pv_va, PAGE_SIZE, 2278 true, true); 2279 #endif 2280 } 2281 2282 /* 2283 * Make the PTE invalid so that we will take a 2284 * page fault the next time the mapping is 2285 * referenced. 2286 */ 2287 npte &= ~L2_TYPE_MASK; 2288 npte |= L2_TYPE_INV; 2289 } 2290 2291 if (npte != opte) { 2292 *ptep = npte; 2293 PTE_SYNC(ptep); 2294 /* Flush the TLB entry if a current pmap. */ 2295 if (PV_BEEN_EXECD(oflags)) 2296 pmap_tlb_flushID_SE(pm, pv->pv_va); 2297 else 2298 if (PV_BEEN_REFD(oflags)) 2299 pmap_tlb_flushD_SE(pm, pv->pv_va); 2300 } 2301 2302 pmap_release_pmap_lock(pm); 2303 2304 NPDEBUG(PDB_BITS, 2305 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2306 pm, va, opte, npte)); 2307 } 2308 2309 #ifdef PMAP_CACHE_VIPT 2310 /* 2311 * If we need to sync the I-cache and we haven't done it yet, do it. 2312 */ 2313 if (need_syncicache && !did_syncicache) { 2314 pmap_syncicache_page(pg); 2315 PMAPCOUNT(exec_synced_clearbit); 2316 } 2317 /* 2318 * If we are changing this to read-only, we need to call vac_me_harder 2319 * so we can change all the read-only pages to cacheable. We pretend 2320 * this as a page deletion. 2321 */ 2322 if (need_vac_me_harder) { 2323 if (pg->mdpage.pvh_attrs & PVF_NC) 2324 pmap_vac_me_harder(pg, NULL, 0); 2325 } 2326 #endif 2327 2328 simple_unlock(&pg->mdpage.pvh_slock); 2329 PMAP_HEAD_TO_MAP_UNLOCK(); 2330 } 2331 2332 /* 2333 * pmap_clean_page() 2334 * 2335 * This is a local function used to work out the best strategy to clean 2336 * a single page referenced by its entry in the PV table. It's used by 2337 * pmap_copy_page, pmap_zero page and maybe some others later on. 2338 * 2339 * Its policy is effectively: 2340 * o If there are no mappings, we don't bother doing anything with the cache. 2341 * o If there is one mapping, we clean just that page. 2342 * o If there are multiple mappings, we clean the entire cache. 2343 * 2344 * So that some functions can be further optimised, it returns 0 if it didn't 2345 * clean the entire cache, or 1 if it did. 2346 * 2347 * XXX One bug in this routine is that if the pv_entry has a single page 2348 * mapped at 0x00000000 a whole cache clean will be performed rather than 2349 * just the 1 page. Since this should not occur in everyday use and if it does 2350 * it will just result in not the most efficient clean for the page. 2351 */ 2352 #ifdef PMAP_CACHE_VIVT 2353 static int 2354 pmap_clean_page(struct pv_entry *pv, bool is_src) 2355 { 2356 pmap_t pm, pm_to_clean = NULL; 2357 struct pv_entry *npv; 2358 u_int cache_needs_cleaning = 0; 2359 u_int flags = 0; 2360 vaddr_t page_to_clean = 0; 2361 2362 if (pv == NULL) { 2363 /* nothing mapped in so nothing to flush */ 2364 return (0); 2365 } 2366 2367 /* 2368 * Since we flush the cache each time we change to a different 2369 * user vmspace, we only need to flush the page if it is in the 2370 * current pmap. 2371 */ 2372 pm = curproc->p_vmspace->vm_map.pmap; 2373 2374 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2375 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2376 flags |= npv->pv_flags; 2377 /* 2378 * The page is mapped non-cacheable in 2379 * this map. No need to flush the cache. 2380 */ 2381 if (npv->pv_flags & PVF_NC) { 2382 #ifdef DIAGNOSTIC 2383 if (cache_needs_cleaning) 2384 panic("pmap_clean_page: " 2385 "cache inconsistency"); 2386 #endif 2387 break; 2388 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2389 continue; 2390 if (cache_needs_cleaning) { 2391 page_to_clean = 0; 2392 break; 2393 } else { 2394 page_to_clean = npv->pv_va; 2395 pm_to_clean = npv->pv_pmap; 2396 } 2397 cache_needs_cleaning = 1; 2398 } 2399 } 2400 2401 if (page_to_clean) { 2402 if (PV_BEEN_EXECD(flags)) 2403 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2404 PAGE_SIZE); 2405 else 2406 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2407 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2408 } else if (cache_needs_cleaning) { 2409 if (PV_BEEN_EXECD(flags)) 2410 pmap_idcache_wbinv_all(pm); 2411 else 2412 pmap_dcache_wbinv_all(pm); 2413 return (1); 2414 } 2415 return (0); 2416 } 2417 #endif 2418 2419 #ifdef PMAP_CACHE_VIPT 2420 /* 2421 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2422 * right cache alias to make sure we flush the right stuff. 2423 */ 2424 void 2425 pmap_syncicache_page(struct vm_page *pg) 2426 { 2427 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2428 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2429 2430 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2431 pg, pg->mdpage.pvh_attrs)); 2432 /* 2433 * No need to clean the page if it's non-cached. 2434 */ 2435 if (pg->mdpage.pvh_attrs & PVF_NC) 2436 return; 2437 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2438 2439 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2440 /* 2441 * Set up a PTE with the right coloring to flush existing cache lines. 2442 */ 2443 *ptep = L2_S_PROTO | 2444 VM_PAGE_TO_PHYS(pg) 2445 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2446 | pte_l2_s_cache_mode; 2447 PTE_SYNC(ptep); 2448 2449 /* 2450 * Flush it. 2451 */ 2452 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2453 /* 2454 * Unmap the page. 2455 */ 2456 *ptep = 0; 2457 PTE_SYNC(ptep); 2458 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2459 2460 pg->mdpage.pvh_attrs |= PVF_EXEC; 2461 PMAPCOUNT(exec_synced); 2462 } 2463 2464 void 2465 pmap_flush_page(struct vm_page *pg, enum pmap_flush_op flush) 2466 { 2467 vsize_t va_offset, end_va; 2468 void (*cf)(vaddr_t, vsize_t); 2469 2470 if (arm_cache_prefer_mask == 0) 2471 return; 2472 2473 switch (flush) { 2474 case PMAP_FLUSH_PRIMARY: 2475 if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 2476 va_offset = 0; 2477 end_va = arm_cache_prefer_mask; 2478 pg->mdpage.pvh_attrs &= ~PVF_MULTCLR; 2479 PMAPCOUNT(vac_flush_lots); 2480 } else { 2481 va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2482 end_va = va_offset; 2483 PMAPCOUNT(vac_flush_one); 2484 } 2485 /* 2486 * Mark that the page is no longer dirty. 2487 */ 2488 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2489 cf = cpufuncs.cf_idcache_wbinv_range; 2490 break; 2491 case PMAP_FLUSH_SECONDARY: 2492 va_offset = 0; 2493 end_va = arm_cache_prefer_mask; 2494 cf = cpufuncs.cf_idcache_wbinv_range; 2495 pg->mdpage.pvh_attrs &= ~PVF_MULTCLR; 2496 PMAPCOUNT(vac_flush_lots); 2497 break; 2498 case PMAP_CLEAN_PRIMARY: 2499 va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2500 end_va = va_offset; 2501 cf = cpufuncs.cf_dcache_wb_range; 2502 /* 2503 * Mark that the page is no longer dirty. 2504 */ 2505 if ((pg->mdpage.pvh_attrs & PVF_DMOD) == 0) 2506 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2507 PMAPCOUNT(vac_clean_one); 2508 break; 2509 default: 2510 return; 2511 } 2512 2513 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2514 2515 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2516 pg, pg->mdpage.pvh_attrs)); 2517 2518 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2519 const size_t pte_offset = va_offset >> PGSHIFT; 2520 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2521 const pt_entry_t oldpte = *ptep; 2522 2523 if (flush == PMAP_FLUSH_SECONDARY 2524 && va_offset == (pg->mdpage.pvh_attrs & arm_cache_prefer_mask)) 2525 continue; 2526 2527 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2528 /* 2529 * Set up a PTE with the right coloring to flush 2530 * existing cache entries. 2531 */ 2532 *ptep = L2_S_PROTO 2533 | VM_PAGE_TO_PHYS(pg) 2534 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2535 | pte_l2_s_cache_mode; 2536 PTE_SYNC(ptep); 2537 2538 /* 2539 * Flush it. 2540 */ 2541 (*cf)(cdstp + va_offset, PAGE_SIZE); 2542 2543 /* 2544 * Restore the page table entry since we might have interrupted 2545 * pmap_zero_page or pmap_copy_page which was already using 2546 * this pte. 2547 */ 2548 *ptep = oldpte; 2549 PTE_SYNC(ptep); 2550 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2551 } 2552 } 2553 #endif /* PMAP_CACHE_VIPT */ 2554 2555 /* 2556 * Routine: pmap_page_remove 2557 * Function: 2558 * Removes this physical page from 2559 * all physical maps in which it resides. 2560 * Reflects back modify bits to the pager. 2561 */ 2562 static void 2563 pmap_page_remove(struct vm_page *pg) 2564 { 2565 struct l2_bucket *l2b; 2566 struct pv_entry *pv, *npv, **pvp; 2567 pmap_t pm, curpm; 2568 pt_entry_t *ptep, pte; 2569 bool flush; 2570 u_int flags; 2571 2572 NPDEBUG(PDB_FOLLOW, 2573 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2574 VM_PAGE_TO_PHYS(pg))); 2575 2576 PMAP_HEAD_TO_MAP_LOCK(); 2577 simple_lock(&pg->mdpage.pvh_slock); 2578 2579 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2580 if (pv == NULL) { 2581 #ifdef PMAP_CACHE_VIPT 2582 /* 2583 * We *know* the page contents are about to be replaced. 2584 * Discard the exec contents 2585 */ 2586 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2587 PMAPCOUNT(exec_discarded_page_protect); 2588 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2589 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2590 #endif 2591 simple_unlock(&pg->mdpage.pvh_slock); 2592 PMAP_HEAD_TO_MAP_UNLOCK(); 2593 return; 2594 } 2595 #ifdef PMAP_CACHE_VIPT 2596 KASSERT(pmap_is_page_colored_p(pg)); 2597 #endif 2598 2599 /* 2600 * Clear alias counts 2601 */ 2602 #ifdef PMAP_CACHE_VIVT 2603 pg->mdpage.k_mappings = 0; 2604 #endif 2605 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2606 2607 flush = false; 2608 flags = 0; 2609 curpm = curproc->p_vmspace->vm_map.pmap; 2610 2611 #ifdef PMAP_CACHE_VIVT 2612 pmap_clean_page(pv, false); 2613 #endif 2614 2615 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 2616 while (pv) { 2617 pm = pv->pv_pmap; 2618 npv = SLIST_NEXT(pv, pv_link); 2619 if (flush == false && (pm == curpm || pm == pmap_kernel())) 2620 flush = true; 2621 2622 if (pm == pmap_kernel()) { 2623 #ifdef PMAP_CACHE_VIPT 2624 /* 2625 * If this was unmanaged mapping, it must be preserved. 2626 * Move it back on the list and advance the end-of-list 2627 * pointer. 2628 */ 2629 if (pv->pv_flags & PVF_KENTRY) { 2630 *pvp = pv; 2631 pvp = &SLIST_NEXT(pv, pv_link); 2632 pv = npv; 2633 continue; 2634 } 2635 if (pv->pv_flags & PVF_WRITE) 2636 pg->mdpage.krw_mappings--; 2637 else 2638 pg->mdpage.kro_mappings--; 2639 #endif 2640 PMAPCOUNT(kernel_unmappings); 2641 } 2642 PMAPCOUNT(unmappings); 2643 2644 pmap_acquire_pmap_lock(pm); 2645 2646 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2647 KDASSERT(l2b != NULL); 2648 2649 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2650 pte = *ptep; 2651 2652 /* 2653 * Update statistics 2654 */ 2655 --pm->pm_stats.resident_count; 2656 2657 /* Wired bit */ 2658 if (pv->pv_flags & PVF_WIRED) 2659 --pm->pm_stats.wired_count; 2660 2661 flags |= pv->pv_flags; 2662 2663 /* 2664 * Invalidate the PTEs. 2665 */ 2666 *ptep = 0; 2667 PTE_SYNC_CURRENT(pm, ptep); 2668 pmap_free_l2_bucket(pm, l2b, 1); 2669 2670 pool_put(&pmap_pv_pool, pv); 2671 pv = npv; 2672 /* 2673 * if we reach the end of the list and there are still 2674 * mappings, they might be able to be cached now. 2675 */ 2676 if (pv == NULL) { 2677 *pvp = NULL; 2678 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 2679 pmap_vac_me_harder(pg, pm, 0); 2680 } 2681 pmap_release_pmap_lock(pm); 2682 } 2683 #ifdef PMAP_CACHE_VIPT 2684 /* 2685 * Its EXEC cache is now gone. 2686 */ 2687 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2688 PMAPCOUNT(exec_discarded_page_protect); 2689 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2690 KASSERT(pg->mdpage.urw_mappings == 0); 2691 KASSERT(pg->mdpage.uro_mappings == 0); 2692 if (pg->mdpage.krw_mappings == 0) 2693 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2694 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2695 #endif 2696 simple_unlock(&pg->mdpage.pvh_slock); 2697 PMAP_HEAD_TO_MAP_UNLOCK(); 2698 2699 if (flush) { 2700 /* 2701 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2702 * would need a subsequent call to pmap_update() to ensure 2703 * curpm->pm_cstate.cs_all is reset. Our callers are not 2704 * required to do that (see pmap(9)), so we can't modify 2705 * the current pmap's state. 2706 */ 2707 if (PV_BEEN_EXECD(flags)) 2708 cpu_tlb_flushID(); 2709 else 2710 cpu_tlb_flushD(); 2711 } 2712 cpu_cpwait(); 2713 } 2714 2715 /* 2716 * pmap_t pmap_create(void) 2717 * 2718 * Create a new pmap structure from scratch. 2719 */ 2720 pmap_t 2721 pmap_create(void) 2722 { 2723 pmap_t pm; 2724 2725 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2726 2727 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2728 pm->pm_stats.wired_count = 0; 2729 pm->pm_stats.resident_count = 1; 2730 pm->pm_cstate.cs_all = 0; 2731 pmap_alloc_l1(pm); 2732 2733 /* 2734 * Note: The pool cache ensures that the pm_l2[] array is already 2735 * initialised to zero. 2736 */ 2737 2738 pmap_pinit(pm); 2739 2740 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2741 2742 return (pm); 2743 } 2744 2745 /* 2746 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2747 * int flags) 2748 * 2749 * Insert the given physical page (p) at 2750 * the specified virtual address (v) in the 2751 * target physical map with the protection requested. 2752 * 2753 * NB: This is the only routine which MAY NOT lazy-evaluate 2754 * or lose information. That is, this routine must actually 2755 * insert this page into the given map NOW. 2756 */ 2757 int 2758 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 2759 { 2760 struct l2_bucket *l2b; 2761 struct vm_page *pg, *opg; 2762 struct pv_entry *pve; 2763 pt_entry_t *ptep, npte, opte; 2764 u_int nflags; 2765 u_int oflags; 2766 2767 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2768 2769 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2770 KDASSERT(((va | pa) & PGOFSET) == 0); 2771 2772 /* 2773 * Get a pointer to the page. Later on in this function, we 2774 * test for a managed page by checking pg != NULL. 2775 */ 2776 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2777 2778 nflags = 0; 2779 if (prot & VM_PROT_WRITE) 2780 nflags |= PVF_WRITE; 2781 if (prot & VM_PROT_EXECUTE) 2782 nflags |= PVF_EXEC; 2783 if (flags & PMAP_WIRED) 2784 nflags |= PVF_WIRED; 2785 2786 PMAP_MAP_TO_HEAD_LOCK(); 2787 pmap_acquire_pmap_lock(pm); 2788 2789 /* 2790 * Fetch the L2 bucket which maps this page, allocating one if 2791 * necessary for user pmaps. 2792 */ 2793 if (pm == pmap_kernel()) 2794 l2b = pmap_get_l2_bucket(pm, va); 2795 else 2796 l2b = pmap_alloc_l2_bucket(pm, va); 2797 if (l2b == NULL) { 2798 if (flags & PMAP_CANFAIL) { 2799 pmap_release_pmap_lock(pm); 2800 PMAP_MAP_TO_HEAD_UNLOCK(); 2801 return (ENOMEM); 2802 } 2803 panic("pmap_enter: failed to allocate L2 bucket"); 2804 } 2805 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2806 opte = *ptep; 2807 npte = pa; 2808 oflags = 0; 2809 2810 if (opte) { 2811 /* 2812 * There is already a mapping at this address. 2813 * If the physical address is different, lookup the 2814 * vm_page. 2815 */ 2816 if (l2pte_pa(opte) != pa) 2817 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2818 else 2819 opg = pg; 2820 } else 2821 opg = NULL; 2822 2823 if (pg) { 2824 /* 2825 * This is to be a managed mapping. 2826 */ 2827 if ((flags & VM_PROT_ALL) || 2828 (pg->mdpage.pvh_attrs & PVF_REF)) { 2829 /* 2830 * - The access type indicates that we don't need 2831 * to do referenced emulation. 2832 * OR 2833 * - The physical page has already been referenced 2834 * so no need to re-do referenced emulation here. 2835 */ 2836 npte |= L2_S_PROTO; 2837 2838 nflags |= PVF_REF; 2839 2840 if ((prot & VM_PROT_WRITE) != 0 && 2841 ((flags & VM_PROT_WRITE) != 0 || 2842 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2843 /* 2844 * This is a writable mapping, and the 2845 * page's mod state indicates it has 2846 * already been modified. Make it 2847 * writable from the outset. 2848 */ 2849 npte |= L2_S_PROT_W; 2850 nflags |= PVF_MOD; 2851 } 2852 } else { 2853 /* 2854 * Need to do page referenced emulation. 2855 */ 2856 npte |= L2_TYPE_INV; 2857 } 2858 2859 npte |= pte_l2_s_cache_mode; 2860 2861 if (pg == opg) { 2862 /* 2863 * We're changing the attrs of an existing mapping. 2864 */ 2865 simple_lock(&pg->mdpage.pvh_slock); 2866 oflags = pmap_modify_pv(pg, pm, va, 2867 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2868 PVF_MOD | PVF_REF, nflags); 2869 simple_unlock(&pg->mdpage.pvh_slock); 2870 2871 #ifdef PMAP_CACHE_VIVT 2872 /* 2873 * We may need to flush the cache if we're 2874 * doing rw-ro... 2875 */ 2876 if (pm->pm_cstate.cs_cache_d && 2877 (oflags & PVF_NC) == 0 && 2878 (opte & L2_S_PROT_W) != 0 && 2879 (prot & VM_PROT_WRITE) == 0) 2880 cpu_dcache_wb_range(va, PAGE_SIZE); 2881 #endif 2882 } else { 2883 /* 2884 * New mapping, or changing the backing page 2885 * of an existing mapping. 2886 */ 2887 if (opg) { 2888 /* 2889 * Replacing an existing mapping with a new one. 2890 * It is part of our managed memory so we 2891 * must remove it from the PV list 2892 */ 2893 simple_lock(&opg->mdpage.pvh_slock); 2894 pve = pmap_remove_pv(opg, pm, va, 0); 2895 pmap_vac_me_harder(opg, pm, 0); 2896 simple_unlock(&opg->mdpage.pvh_slock); 2897 oflags = pve->pv_flags; 2898 2899 #ifdef PMAP_CACHE_VIVT 2900 /* 2901 * If the old mapping was valid (ref/mod 2902 * emulation creates 'invalid' mappings 2903 * initially) then make sure to frob 2904 * the cache. 2905 */ 2906 if ((oflags & PVF_NC) == 0 && 2907 l2pte_valid(opte)) { 2908 if (PV_BEEN_EXECD(oflags)) { 2909 pmap_idcache_wbinv_range(pm, va, 2910 PAGE_SIZE); 2911 } else 2912 if (PV_BEEN_REFD(oflags)) { 2913 pmap_dcache_wb_range(pm, va, 2914 PAGE_SIZE, true, 2915 (oflags & PVF_WRITE) == 0); 2916 } 2917 } 2918 #endif 2919 } else 2920 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2921 if ((flags & PMAP_CANFAIL) == 0) 2922 panic("pmap_enter: no pv entries"); 2923 2924 if (pm != pmap_kernel()) 2925 pmap_free_l2_bucket(pm, l2b, 0); 2926 pmap_release_pmap_lock(pm); 2927 PMAP_MAP_TO_HEAD_UNLOCK(); 2928 NPDEBUG(PDB_ENTER, 2929 printf("pmap_enter: ENOMEM\n")); 2930 return (ENOMEM); 2931 } 2932 2933 pmap_enter_pv(pg, pve, pm, va, nflags); 2934 } 2935 } else { 2936 /* 2937 * We're mapping an unmanaged page. 2938 * These are always readable, and possibly writable, from 2939 * the get go as we don't need to track ref/mod status. 2940 */ 2941 npte |= L2_S_PROTO; 2942 if (prot & VM_PROT_WRITE) 2943 npte |= L2_S_PROT_W; 2944 2945 /* 2946 * Make sure the vector table is mapped cacheable 2947 */ 2948 if (pm != pmap_kernel() && va == vector_page) 2949 npte |= pte_l2_s_cache_mode; 2950 2951 if (opg) { 2952 /* 2953 * Looks like there's an existing 'managed' mapping 2954 * at this address. 2955 */ 2956 simple_lock(&opg->mdpage.pvh_slock); 2957 pve = pmap_remove_pv(opg, pm, va, 0); 2958 pmap_vac_me_harder(opg, pm, 0); 2959 simple_unlock(&opg->mdpage.pvh_slock); 2960 oflags = pve->pv_flags; 2961 2962 #ifdef PMAP_CACHE_VIVT 2963 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2964 if (PV_BEEN_EXECD(oflags)) 2965 pmap_idcache_wbinv_range(pm, va, 2966 PAGE_SIZE); 2967 else 2968 if (PV_BEEN_REFD(oflags)) 2969 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2970 true, (oflags & PVF_WRITE) == 0); 2971 } 2972 #endif 2973 pool_put(&pmap_pv_pool, pve); 2974 } 2975 } 2976 2977 /* 2978 * Make sure userland mappings get the right permissions 2979 */ 2980 if (pm != pmap_kernel() && va != vector_page) 2981 npte |= L2_S_PROT_U; 2982 2983 /* 2984 * Keep the stats up to date 2985 */ 2986 if (opte == 0) { 2987 l2b->l2b_occupancy++; 2988 pm->pm_stats.resident_count++; 2989 } 2990 2991 NPDEBUG(PDB_ENTER, 2992 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2993 2994 /* 2995 * If this is just a wiring change, the two PTEs will be 2996 * identical, so there's no need to update the page table. 2997 */ 2998 if (npte != opte) { 2999 bool is_cached = pmap_is_cached(pm); 3000 3001 *ptep = npte; 3002 if (is_cached) { 3003 /* 3004 * We only need to frob the cache/tlb if this pmap 3005 * is current 3006 */ 3007 PTE_SYNC(ptep); 3008 if (va != vector_page && l2pte_valid(npte)) { 3009 /* 3010 * This mapping is likely to be accessed as 3011 * soon as we return to userland. Fix up the 3012 * L1 entry to avoid taking another 3013 * page/domain fault. 3014 */ 3015 pd_entry_t *pl1pd, l1pd; 3016 3017 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3018 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3019 L1_C_PROTO; 3020 if (*pl1pd != l1pd) { 3021 *pl1pd = l1pd; 3022 PTE_SYNC(pl1pd); 3023 } 3024 } 3025 } 3026 3027 if (PV_BEEN_EXECD(oflags)) 3028 pmap_tlb_flushID_SE(pm, va); 3029 else 3030 if (PV_BEEN_REFD(oflags)) 3031 pmap_tlb_flushD_SE(pm, va); 3032 3033 NPDEBUG(PDB_ENTER, 3034 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3035 is_cached, pm->pm_cstate.cs_all)); 3036 3037 if (pg != NULL) { 3038 simple_lock(&pg->mdpage.pvh_slock); 3039 pmap_vac_me_harder(pg, pm, va); 3040 simple_unlock(&pg->mdpage.pvh_slock); 3041 } 3042 } 3043 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3044 if (pg) { 3045 simple_lock(&pg->mdpage.pvh_slock); 3046 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3047 KASSERT(((pg->mdpage.pvh_attrs & PVF_WRITE) == 0) == (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0)); 3048 simple_unlock(&pg->mdpage.pvh_slock); 3049 } 3050 #endif 3051 3052 pmap_release_pmap_lock(pm); 3053 PMAP_MAP_TO_HEAD_UNLOCK(); 3054 3055 return (0); 3056 } 3057 3058 /* 3059 * pmap_remove() 3060 * 3061 * pmap_remove is responsible for nuking a number of mappings for a range 3062 * of virtual address space in the current pmap. To do this efficiently 3063 * is interesting, because in a number of cases a wide virtual address 3064 * range may be supplied that contains few actual mappings. So, the 3065 * optimisations are: 3066 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3067 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3068 * maybe do just a partial cache clean. This path of execution is 3069 * complicated by the fact that the cache must be flushed _before_ 3070 * the PTE is nuked, being a VAC :-) 3071 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3072 * all invalidations until pmap_update(), since pmap_remove_all() has 3073 * already flushed the cache. 3074 * 4. Maybe later fast-case a single page, but I don't think this is 3075 * going to make _that_ much difference overall. 3076 */ 3077 3078 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3079 3080 void 3081 pmap_do_remove(pmap_t pm, vaddr_t sva, vaddr_t eva, int skip_wired) 3082 { 3083 struct l2_bucket *l2b; 3084 vaddr_t next_bucket; 3085 pt_entry_t *ptep; 3086 u_int cleanlist_idx, total, cnt; 3087 struct { 3088 vaddr_t va; 3089 pt_entry_t *ptep; 3090 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3091 u_int mappings, is_exec, is_refd; 3092 3093 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3094 "eva=%08lx\n", pm, sva, eva)); 3095 3096 /* 3097 * we lock in the pmap => pv_head direction 3098 */ 3099 PMAP_MAP_TO_HEAD_LOCK(); 3100 pmap_acquire_pmap_lock(pm); 3101 3102 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3103 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3104 if (pm->pm_cstate.cs_tlb == 0) 3105 pm->pm_remove_all = true; 3106 } else 3107 cleanlist_idx = 0; 3108 3109 total = 0; 3110 3111 while (sva < eva) { 3112 /* 3113 * Do one L2 bucket's worth at a time. 3114 */ 3115 next_bucket = L2_NEXT_BUCKET(sva); 3116 if (next_bucket > eva) 3117 next_bucket = eva; 3118 3119 l2b = pmap_get_l2_bucket(pm, sva); 3120 if (l2b == NULL) { 3121 sva = next_bucket; 3122 continue; 3123 } 3124 3125 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3126 3127 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3128 struct vm_page *pg; 3129 pt_entry_t pte; 3130 paddr_t pa; 3131 3132 pte = *ptep; 3133 3134 if (pte == 0) { 3135 /* Nothing here, move along */ 3136 continue; 3137 } 3138 3139 pa = l2pte_pa(pte); 3140 is_exec = 0; 3141 is_refd = 1; 3142 3143 /* 3144 * Update flags. In a number of circumstances, 3145 * we could cluster a lot of these and do a 3146 * number of sequential pages in one go. 3147 */ 3148 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3149 struct pv_entry *pve; 3150 simple_lock(&pg->mdpage.pvh_slock); 3151 pve = pmap_remove_pv(pg, pm, sva, skip_wired); 3152 pmap_vac_me_harder(pg, pm, 0); 3153 simple_unlock(&pg->mdpage.pvh_slock); 3154 if (pve != NULL) { 3155 if (pm->pm_remove_all == false) { 3156 is_exec = 3157 PV_BEEN_EXECD(pve->pv_flags); 3158 is_refd = 3159 PV_BEEN_REFD(pve->pv_flags); 3160 } 3161 pool_put(&pmap_pv_pool, pve); 3162 } else 3163 if (skip_wired) { 3164 /* The mapping is wired. Skip it */ 3165 continue; 3166 } 3167 } else 3168 if (skip_wired) { 3169 /* Unmanaged pages are always wired. */ 3170 continue; 3171 } 3172 3173 mappings++; 3174 3175 if (!l2pte_valid(pte)) { 3176 /* 3177 * Ref/Mod emulation is still active for this 3178 * mapping, therefore it is has not yet been 3179 * accessed. No need to frob the cache/tlb. 3180 */ 3181 *ptep = 0; 3182 PTE_SYNC_CURRENT(pm, ptep); 3183 continue; 3184 } 3185 3186 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3187 /* Add to the clean list. */ 3188 cleanlist[cleanlist_idx].ptep = ptep; 3189 cleanlist[cleanlist_idx].va = 3190 sva | (is_exec & 1); 3191 cleanlist_idx++; 3192 } else 3193 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3194 /* Nuke everything if needed. */ 3195 #ifdef PMAP_CACHE_VIVT 3196 pmap_idcache_wbinv_all(pm); 3197 #endif 3198 pmap_tlb_flushID(pm); 3199 3200 /* 3201 * Roll back the previous PTE list, 3202 * and zero out the current PTE. 3203 */ 3204 for (cnt = 0; 3205 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3206 *cleanlist[cnt].ptep = 0; 3207 PTE_SYNC(cleanlist[cnt].ptep); 3208 } 3209 *ptep = 0; 3210 PTE_SYNC(ptep); 3211 cleanlist_idx++; 3212 pm->pm_remove_all = true; 3213 } else { 3214 *ptep = 0; 3215 PTE_SYNC(ptep); 3216 if (pm->pm_remove_all == false) { 3217 if (is_exec) 3218 pmap_tlb_flushID_SE(pm, sva); 3219 else 3220 if (is_refd) 3221 pmap_tlb_flushD_SE(pm, sva); 3222 } 3223 } 3224 } 3225 3226 /* 3227 * Deal with any left overs 3228 */ 3229 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3230 total += cleanlist_idx; 3231 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3232 if (pm->pm_cstate.cs_all != 0) { 3233 vaddr_t clva = cleanlist[cnt].va & ~1; 3234 if (cleanlist[cnt].va & 1) { 3235 #ifdef PMAP_CACHE_VIVT 3236 pmap_idcache_wbinv_range(pm, 3237 clva, PAGE_SIZE); 3238 #endif 3239 pmap_tlb_flushID_SE(pm, clva); 3240 } else { 3241 #ifdef PMAP_CACHE_VIVT 3242 pmap_dcache_wb_range(pm, 3243 clva, PAGE_SIZE, true, 3244 false); 3245 #endif 3246 pmap_tlb_flushD_SE(pm, clva); 3247 } 3248 } 3249 *cleanlist[cnt].ptep = 0; 3250 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3251 } 3252 3253 /* 3254 * If it looks like we're removing a whole bunch 3255 * of mappings, it's faster to just write-back 3256 * the whole cache now and defer TLB flushes until 3257 * pmap_update() is called. 3258 */ 3259 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3260 cleanlist_idx = 0; 3261 else { 3262 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3263 #ifdef PMAP_CACHE_VIVT 3264 pmap_idcache_wbinv_all(pm); 3265 #endif 3266 pm->pm_remove_all = true; 3267 } 3268 } 3269 3270 pmap_free_l2_bucket(pm, l2b, mappings); 3271 pm->pm_stats.resident_count -= mappings; 3272 } 3273 3274 pmap_release_pmap_lock(pm); 3275 PMAP_MAP_TO_HEAD_UNLOCK(); 3276 } 3277 3278 #ifdef PMAP_CACHE_VIPT 3279 static struct pv_entry * 3280 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3281 { 3282 struct pv_entry *pv; 3283 3284 simple_lock(&pg->mdpage.pvh_slock); 3285 KASSERT(pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 3286 KASSERT((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3287 3288 pv = pmap_remove_pv(pg, pmap_kernel(), va, false); 3289 KASSERT(pv); 3290 KASSERT(pv->pv_flags & PVF_KENTRY); 3291 3292 /* 3293 * If we are removing a writeable mapping to a cached exec page, 3294 * if it's the last mapping then clear it execness other sync 3295 * the page to the icache. 3296 */ 3297 if ((pg->mdpage.pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3298 && (pv->pv_flags & PVF_WRITE) != 0) { 3299 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 3300 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 3301 PMAPCOUNT(exec_discarded_kremove); 3302 } else { 3303 pmap_syncicache_page(pg); 3304 PMAPCOUNT(exec_synced_kremove); 3305 } 3306 } 3307 pmap_vac_me_harder(pg, pmap_kernel(), 0); 3308 simple_unlock(&pg->mdpage.pvh_slock); 3309 3310 return pv; 3311 } 3312 #endif /* PMAP_CACHE_VIPT */ 3313 3314 /* 3315 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3316 * 3317 * We assume there is already sufficient KVM space available 3318 * to do this, as we can't allocate L2 descriptor tables/metadata 3319 * from here. 3320 */ 3321 void 3322 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 3323 { 3324 struct l2_bucket *l2b; 3325 pt_entry_t *ptep, opte; 3326 #ifdef PMAP_CACHE_VIVT 3327 struct vm_page *pg = (prot & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3328 #endif 3329 #ifdef PMAP_CACHE_VIPT 3330 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3331 struct vm_page *opg; 3332 struct pv_entry *pv = NULL; 3333 #endif 3334 3335 NPDEBUG(PDB_KENTER, 3336 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3337 va, pa, prot)); 3338 3339 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3340 KDASSERT(l2b != NULL); 3341 3342 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3343 opte = *ptep; 3344 3345 if (opte == 0) { 3346 PMAPCOUNT(kenter_mappings); 3347 l2b->l2b_occupancy++; 3348 } else { 3349 PMAPCOUNT(kenter_remappings); 3350 #ifdef PMAP_CACHE_VIPT 3351 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3352 if (opg) { 3353 KASSERT(opg != pg); 3354 KASSERT((opg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3355 KASSERT((prot & PMAP_KMPAGE) == 0); 3356 simple_lock(&opg->mdpage.pvh_slock); 3357 pv = pmap_kremove_pg(opg, va); 3358 simple_unlock(&opg->mdpage.pvh_slock); 3359 } 3360 #endif 3361 if (l2pte_valid(opte)) { 3362 #ifdef PMAP_CACHE_VIVT 3363 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3364 #endif 3365 cpu_tlb_flushD_SE(va); 3366 cpu_cpwait(); 3367 } 3368 } 3369 3370 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3371 pte_l2_s_cache_mode; 3372 PTE_SYNC(ptep); 3373 3374 if (pg) { 3375 if (prot & PMAP_KMPAGE) { 3376 simple_lock(&pg->mdpage.pvh_slock); 3377 KASSERT(pg->mdpage.urw_mappings == 0); 3378 KASSERT(pg->mdpage.uro_mappings == 0); 3379 KASSERT(pg->mdpage.krw_mappings == 0); 3380 KASSERT(pg->mdpage.kro_mappings == 0); 3381 #ifdef PMAP_CACHE_VIPT 3382 KASSERT(pv == NULL); 3383 KASSERT((va & PVF_COLORED) == 0); 3384 KASSERT((pg->mdpage.pvh_attrs & PVF_NC) == 0); 3385 /* if there is a color conflict, evict from cache. */ 3386 if (pmap_is_page_colored_p(pg) 3387 && ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask)) { 3388 PMAPCOUNT(vac_color_change); 3389 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 3390 } else if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 3391 /* 3392 * If this page has multiple colors, expunge 3393 * them. 3394 */ 3395 PMAPCOUNT(vac_flush_lots2); 3396 pmap_flush_page(pg, PMAP_FLUSH_SECONDARY); 3397 } 3398 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 3399 pg->mdpage.pvh_attrs |= PVF_KMPAGE 3400 | PVF_COLORED | PVF_DIRTY 3401 | (va & arm_cache_prefer_mask); 3402 #endif 3403 #ifdef PMAP_CACHE_VIVT 3404 pg->mdpage.pvh_attrs |= PVF_KMPAGE; 3405 #endif 3406 pmap_kmpages++; 3407 simple_unlock(&pg->mdpage.pvh_slock); 3408 #ifdef PMAP_CACHE_VIPT 3409 } else { 3410 if (pv == NULL) { 3411 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3412 KASSERT(pv != NULL); 3413 } 3414 pmap_enter_pv(pg, pv, pmap_kernel(), va, 3415 PVF_WIRED | PVF_KENTRY 3416 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3417 if ((prot & VM_PROT_WRITE) 3418 && !(pg->mdpage.pvh_attrs & PVF_NC)) 3419 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3420 KASSERT((prot & VM_PROT_WRITE) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3421 simple_lock(&pg->mdpage.pvh_slock); 3422 pmap_vac_me_harder(pg, pmap_kernel(), va); 3423 simple_unlock(&pg->mdpage.pvh_slock); 3424 #endif 3425 } 3426 #ifdef PMAP_CACHE_VIPT 3427 } else { 3428 if (pv != NULL) 3429 pool_put(&pmap_pv_pool, pv); 3430 #endif 3431 } 3432 } 3433 3434 void 3435 pmap_kremove(vaddr_t va, vsize_t len) 3436 { 3437 struct l2_bucket *l2b; 3438 pt_entry_t *ptep, *sptep, opte; 3439 vaddr_t next_bucket, eva; 3440 u_int mappings; 3441 struct vm_page *opg; 3442 3443 PMAPCOUNT(kenter_unmappings); 3444 3445 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3446 va, len)); 3447 3448 eva = va + len; 3449 3450 while (va < eva) { 3451 next_bucket = L2_NEXT_BUCKET(va); 3452 if (next_bucket > eva) 3453 next_bucket = eva; 3454 3455 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3456 KDASSERT(l2b != NULL); 3457 3458 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3459 mappings = 0; 3460 3461 while (va < next_bucket) { 3462 opte = *ptep; 3463 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3464 if (opg) { 3465 if (opg->mdpage.pvh_attrs & PVF_KMPAGE) { 3466 simple_lock(&opg->mdpage.pvh_slock); 3467 KASSERT(opg->mdpage.urw_mappings == 0); 3468 KASSERT(opg->mdpage.uro_mappings == 0); 3469 KASSERT(opg->mdpage.krw_mappings == 0); 3470 KASSERT(opg->mdpage.kro_mappings == 0); 3471 opg->mdpage.pvh_attrs &= ~PVF_KMPAGE; 3472 #ifdef PMAP_CACHE_VIPT 3473 opg->mdpage.pvh_attrs &= ~PVF_WRITE; 3474 #endif 3475 pmap_kmpages--; 3476 simple_unlock(&opg->mdpage.pvh_slock); 3477 #ifdef PMAP_CACHE_VIPT 3478 } else { 3479 pool_put(&pmap_pv_pool, 3480 pmap_kremove_pg(opg, va)); 3481 #endif 3482 } 3483 } 3484 if (l2pte_valid(opte)) { 3485 #ifdef PMAP_CACHE_VIVT 3486 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3487 #endif 3488 cpu_tlb_flushD_SE(va); 3489 } 3490 if (opte) { 3491 *ptep = 0; 3492 mappings++; 3493 } 3494 va += PAGE_SIZE; 3495 ptep++; 3496 } 3497 KDASSERT(mappings <= l2b->l2b_occupancy); 3498 l2b->l2b_occupancy -= mappings; 3499 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3500 } 3501 cpu_cpwait(); 3502 } 3503 3504 bool 3505 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3506 { 3507 struct l2_dtable *l2; 3508 pd_entry_t *pl1pd, l1pd; 3509 pt_entry_t *ptep, pte; 3510 paddr_t pa; 3511 u_int l1idx; 3512 3513 pmap_acquire_pmap_lock(pm); 3514 3515 l1idx = L1_IDX(va); 3516 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3517 l1pd = *pl1pd; 3518 3519 if (l1pte_section_p(l1pd)) { 3520 /* 3521 * These should only happen for pmap_kernel() 3522 */ 3523 KDASSERT(pm == pmap_kernel()); 3524 pmap_release_pmap_lock(pm); 3525 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3526 } else { 3527 /* 3528 * Note that we can't rely on the validity of the L1 3529 * descriptor as an indication that a mapping exists. 3530 * We have to look it up in the L2 dtable. 3531 */ 3532 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3533 3534 if (l2 == NULL || 3535 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3536 pmap_release_pmap_lock(pm); 3537 return false; 3538 } 3539 3540 ptep = &ptep[l2pte_index(va)]; 3541 pte = *ptep; 3542 pmap_release_pmap_lock(pm); 3543 3544 if (pte == 0) 3545 return false; 3546 3547 switch (pte & L2_TYPE_MASK) { 3548 case L2_TYPE_L: 3549 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3550 break; 3551 3552 default: 3553 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3554 break; 3555 } 3556 } 3557 3558 if (pap != NULL) 3559 *pap = pa; 3560 3561 return true; 3562 } 3563 3564 void 3565 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3566 { 3567 struct l2_bucket *l2b; 3568 pt_entry_t *ptep, pte; 3569 vaddr_t next_bucket; 3570 u_int flags; 3571 u_int clr_mask; 3572 int flush; 3573 3574 NPDEBUG(PDB_PROTECT, 3575 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3576 pm, sva, eva, prot)); 3577 3578 if ((prot & VM_PROT_READ) == 0) { 3579 pmap_remove(pm, sva, eva); 3580 return; 3581 } 3582 3583 if (prot & VM_PROT_WRITE) { 3584 /* 3585 * If this is a read->write transition, just ignore it and let 3586 * uvm_fault() take care of it later. 3587 */ 3588 return; 3589 } 3590 3591 PMAP_MAP_TO_HEAD_LOCK(); 3592 pmap_acquire_pmap_lock(pm); 3593 3594 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3595 flags = 0; 3596 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3597 3598 while (sva < eva) { 3599 next_bucket = L2_NEXT_BUCKET(sva); 3600 if (next_bucket > eva) 3601 next_bucket = eva; 3602 3603 l2b = pmap_get_l2_bucket(pm, sva); 3604 if (l2b == NULL) { 3605 sva = next_bucket; 3606 continue; 3607 } 3608 3609 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3610 3611 while (sva < next_bucket) { 3612 pte = *ptep; 3613 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3614 struct vm_page *pg; 3615 u_int f; 3616 3617 #ifdef PMAP_CACHE_VIVT 3618 /* 3619 * OK, at this point, we know we're doing 3620 * write-protect operation. If the pmap is 3621 * active, write-back the page. 3622 */ 3623 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3624 false, false); 3625 #endif 3626 3627 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3628 pte &= ~L2_S_PROT_W; 3629 *ptep = pte; 3630 PTE_SYNC(ptep); 3631 3632 if (pg != NULL) { 3633 simple_lock(&pg->mdpage.pvh_slock); 3634 f = pmap_modify_pv(pg, pm, sva, 3635 clr_mask, 0); 3636 pmap_vac_me_harder(pg, pm, sva); 3637 simple_unlock(&pg->mdpage.pvh_slock); 3638 } else 3639 f = PVF_REF | PVF_EXEC; 3640 3641 if (flush >= 0) { 3642 flush++; 3643 flags |= f; 3644 } else 3645 if (PV_BEEN_EXECD(f)) 3646 pmap_tlb_flushID_SE(pm, sva); 3647 else 3648 if (PV_BEEN_REFD(f)) 3649 pmap_tlb_flushD_SE(pm, sva); 3650 } 3651 3652 sva += PAGE_SIZE; 3653 ptep++; 3654 } 3655 } 3656 3657 pmap_release_pmap_lock(pm); 3658 PMAP_MAP_TO_HEAD_UNLOCK(); 3659 3660 if (flush) { 3661 if (PV_BEEN_EXECD(flags)) 3662 pmap_tlb_flushID(pm); 3663 else 3664 if (PV_BEEN_REFD(flags)) 3665 pmap_tlb_flushD(pm); 3666 } 3667 } 3668 3669 void 3670 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3671 { 3672 struct l2_bucket *l2b; 3673 pt_entry_t *ptep; 3674 vaddr_t next_bucket; 3675 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3676 3677 NPDEBUG(PDB_EXEC, 3678 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3679 pm, sva, eva)); 3680 3681 PMAP_MAP_TO_HEAD_LOCK(); 3682 pmap_acquire_pmap_lock(pm); 3683 3684 while (sva < eva) { 3685 next_bucket = L2_NEXT_BUCKET(sva); 3686 if (next_bucket > eva) 3687 next_bucket = eva; 3688 3689 l2b = pmap_get_l2_bucket(pm, sva); 3690 if (l2b == NULL) { 3691 sva = next_bucket; 3692 continue; 3693 } 3694 3695 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3696 sva < next_bucket; 3697 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3698 if (l2pte_valid(*ptep)) { 3699 cpu_icache_sync_range(sva, 3700 min(page_size, eva - sva)); 3701 } 3702 } 3703 } 3704 3705 pmap_release_pmap_lock(pm); 3706 PMAP_MAP_TO_HEAD_UNLOCK(); 3707 } 3708 3709 void 3710 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3711 { 3712 3713 NPDEBUG(PDB_PROTECT, 3714 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3715 pg, VM_PAGE_TO_PHYS(pg), prot)); 3716 3717 switch(prot) { 3718 return; 3719 case VM_PROT_READ|VM_PROT_WRITE: 3720 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3721 pmap_clearbit(pg, PVF_EXEC); 3722 break; 3723 #endif 3724 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3725 break; 3726 3727 case VM_PROT_READ: 3728 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3729 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3730 break; 3731 #endif 3732 case VM_PROT_READ|VM_PROT_EXECUTE: 3733 pmap_clearbit(pg, PVF_WRITE); 3734 break; 3735 3736 default: 3737 pmap_page_remove(pg); 3738 break; 3739 } 3740 } 3741 3742 /* 3743 * pmap_clear_modify: 3744 * 3745 * Clear the "modified" attribute for a page. 3746 */ 3747 bool 3748 pmap_clear_modify(struct vm_page *pg) 3749 { 3750 bool rv; 3751 3752 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3753 rv = true; 3754 #ifdef PMAP_CACHE_VIPT 3755 /* 3756 * If we are going to clear the modified bit and there are 3757 * no other modified bits set, flush the page to memory and 3758 * mark it clean. 3759 */ 3760 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3761 pmap_flush_page(pg, PMAP_CLEAN_PRIMARY); 3762 #endif 3763 pmap_clearbit(pg, PVF_MOD); 3764 } else 3765 rv = false; 3766 3767 return (rv); 3768 } 3769 3770 /* 3771 * pmap_clear_reference: 3772 * 3773 * Clear the "referenced" attribute for a page. 3774 */ 3775 bool 3776 pmap_clear_reference(struct vm_page *pg) 3777 { 3778 bool rv; 3779 3780 if (pg->mdpage.pvh_attrs & PVF_REF) { 3781 rv = true; 3782 pmap_clearbit(pg, PVF_REF); 3783 } else 3784 rv = false; 3785 3786 return (rv); 3787 } 3788 3789 /* 3790 * pmap_is_modified: 3791 * 3792 * Test if a page has the "modified" attribute. 3793 */ 3794 /* See <arm/arm32/pmap.h> */ 3795 3796 /* 3797 * pmap_is_referenced: 3798 * 3799 * Test if a page has the "referenced" attribute. 3800 */ 3801 /* See <arm/arm32/pmap.h> */ 3802 3803 int 3804 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3805 { 3806 struct l2_dtable *l2; 3807 struct l2_bucket *l2b; 3808 pd_entry_t *pl1pd, l1pd; 3809 pt_entry_t *ptep, pte; 3810 paddr_t pa; 3811 u_int l1idx; 3812 int rv = 0; 3813 3814 PMAP_MAP_TO_HEAD_LOCK(); 3815 pmap_acquire_pmap_lock(pm); 3816 3817 l1idx = L1_IDX(va); 3818 3819 /* 3820 * If there is no l2_dtable for this address, then the process 3821 * has no business accessing it. 3822 * 3823 * Note: This will catch userland processes trying to access 3824 * kernel addresses. 3825 */ 3826 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3827 if (l2 == NULL) 3828 goto out; 3829 3830 /* 3831 * Likewise if there is no L2 descriptor table 3832 */ 3833 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3834 if (l2b->l2b_kva == NULL) 3835 goto out; 3836 3837 /* 3838 * Check the PTE itself. 3839 */ 3840 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3841 pte = *ptep; 3842 if (pte == 0) 3843 goto out; 3844 3845 /* 3846 * Catch a userland access to the vector page mapped at 0x0 3847 */ 3848 if (user && (pte & L2_S_PROT_U) == 0) 3849 goto out; 3850 3851 pa = l2pte_pa(pte); 3852 3853 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3854 /* 3855 * This looks like a good candidate for "page modified" 3856 * emulation... 3857 */ 3858 struct pv_entry *pv; 3859 struct vm_page *pg; 3860 3861 /* Extract the physical address of the page */ 3862 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3863 goto out; 3864 3865 /* Get the current flags for this page. */ 3866 simple_lock(&pg->mdpage.pvh_slock); 3867 3868 pv = pmap_find_pv(pg, pm, va); 3869 if (pv == NULL) { 3870 simple_unlock(&pg->mdpage.pvh_slock); 3871 goto out; 3872 } 3873 3874 /* 3875 * Do the flags say this page is writable? If not then it 3876 * is a genuine write fault. If yes then the write fault is 3877 * our fault as we did not reflect the write access in the 3878 * PTE. Now we know a write has occurred we can correct this 3879 * and also set the modified bit 3880 */ 3881 if ((pv->pv_flags & PVF_WRITE) == 0) { 3882 simple_unlock(&pg->mdpage.pvh_slock); 3883 goto out; 3884 } 3885 3886 NPDEBUG(PDB_FOLLOW, 3887 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3888 pm, va, VM_PAGE_TO_PHYS(pg))); 3889 3890 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 3891 pv->pv_flags |= PVF_REF | PVF_MOD; 3892 #ifdef PMAP_CACHE_VIPT 3893 /* 3894 * If there are cacheable mappings for this page, mark it dirty. 3895 */ 3896 if ((pg->mdpage.pvh_attrs & PVF_NC) == 0) 3897 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3898 #endif 3899 simple_unlock(&pg->mdpage.pvh_slock); 3900 3901 /* 3902 * Re-enable write permissions for the page. No need to call 3903 * pmap_vac_me_harder(), since this is just a 3904 * modified-emulation fault, and the PVF_WRITE bit isn't 3905 * changing. We've already set the cacheable bits based on 3906 * the assumption that we can write to this page. 3907 */ 3908 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3909 PTE_SYNC(ptep); 3910 rv = 1; 3911 } else 3912 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3913 /* 3914 * This looks like a good candidate for "page referenced" 3915 * emulation. 3916 */ 3917 struct pv_entry *pv; 3918 struct vm_page *pg; 3919 3920 /* Extract the physical address of the page */ 3921 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3922 goto out; 3923 3924 /* Get the current flags for this page. */ 3925 simple_lock(&pg->mdpage.pvh_slock); 3926 3927 pv = pmap_find_pv(pg, pm, va); 3928 if (pv == NULL) { 3929 simple_unlock(&pg->mdpage.pvh_slock); 3930 goto out; 3931 } 3932 3933 pg->mdpage.pvh_attrs |= PVF_REF; 3934 pv->pv_flags |= PVF_REF; 3935 simple_unlock(&pg->mdpage.pvh_slock); 3936 3937 NPDEBUG(PDB_FOLLOW, 3938 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3939 pm, va, VM_PAGE_TO_PHYS(pg))); 3940 3941 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3942 PTE_SYNC(ptep); 3943 rv = 1; 3944 } 3945 3946 /* 3947 * We know there is a valid mapping here, so simply 3948 * fix up the L1 if necessary. 3949 */ 3950 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3951 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3952 if (*pl1pd != l1pd) { 3953 *pl1pd = l1pd; 3954 PTE_SYNC(pl1pd); 3955 rv = 1; 3956 } 3957 3958 #ifdef CPU_SA110 3959 /* 3960 * There are bugs in the rev K SA110. This is a check for one 3961 * of them. 3962 */ 3963 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3964 curcpu()->ci_arm_cpurev < 3) { 3965 /* Always current pmap */ 3966 if (l2pte_valid(pte)) { 3967 extern int kernel_debug; 3968 if (kernel_debug & 1) { 3969 struct proc *p = curlwp->l_proc; 3970 printf("prefetch_abort: page is already " 3971 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3972 printf("prefetch_abort: pc=%08lx proc=%p " 3973 "process=%s\n", va, p, p->p_comm); 3974 printf("prefetch_abort: far=%08x fs=%x\n", 3975 cpu_faultaddress(), cpu_faultstatus()); 3976 } 3977 #ifdef DDB 3978 if (kernel_debug & 2) 3979 Debugger(); 3980 #endif 3981 rv = 1; 3982 } 3983 } 3984 #endif /* CPU_SA110 */ 3985 3986 #ifdef DEBUG 3987 /* 3988 * If 'rv == 0' at this point, it generally indicates that there is a 3989 * stale TLB entry for the faulting address. This happens when two or 3990 * more processes are sharing an L1. Since we don't flush the TLB on 3991 * a context switch between such processes, we can take domain faults 3992 * for mappings which exist at the same VA in both processes. EVEN IF 3993 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3994 * example. 3995 * 3996 * This is extremely likely to happen if pmap_enter() updated the L1 3997 * entry for a recently entered mapping. In this case, the TLB is 3998 * flushed for the new mapping, but there may still be TLB entries for 3999 * other mappings belonging to other processes in the 1MB range 4000 * covered by the L1 entry. 4001 * 4002 * Since 'rv == 0', we know that the L1 already contains the correct 4003 * value, so the fault must be due to a stale TLB entry. 4004 * 4005 * Since we always need to flush the TLB anyway in the case where we 4006 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4007 * stale TLB entries dynamically. 4008 * 4009 * However, the above condition can ONLY happen if the current L1 is 4010 * being shared. If it happens when the L1 is unshared, it indicates 4011 * that other parts of the pmap are not doing their job WRT managing 4012 * the TLB. 4013 */ 4014 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4015 extern int last_fault_code; 4016 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4017 pm, va, ftype); 4018 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4019 l2, l2b, ptep, pl1pd); 4020 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4021 pte, l1pd, last_fault_code); 4022 #ifdef DDB 4023 Debugger(); 4024 #endif 4025 } 4026 #endif 4027 4028 cpu_tlb_flushID_SE(va); 4029 cpu_cpwait(); 4030 4031 rv = 1; 4032 4033 out: 4034 pmap_release_pmap_lock(pm); 4035 PMAP_MAP_TO_HEAD_UNLOCK(); 4036 4037 return (rv); 4038 } 4039 4040 /* 4041 * pmap_collect: free resources held by a pmap 4042 * 4043 * => optional function. 4044 * => called when a process is swapped out to free memory. 4045 */ 4046 void 4047 pmap_collect(pmap_t pm) 4048 { 4049 4050 #ifdef PMAP_CACHE_VIVT 4051 pmap_idcache_wbinv_all(pm); 4052 #endif 4053 pm->pm_remove_all = true; 4054 pmap_do_remove(pm, VM_MIN_ADDRESS, VM_MAX_ADDRESS, 1); 4055 pmap_update(pm); 4056 PMAPCOUNT(collects); 4057 } 4058 4059 /* 4060 * Routine: pmap_procwr 4061 * 4062 * Function: 4063 * Synchronize caches corresponding to [addr, addr+len) in p. 4064 * 4065 */ 4066 void 4067 pmap_procwr(struct proc *p, vaddr_t va, int len) 4068 { 4069 /* We only need to do anything if it is the current process. */ 4070 if (p == curproc) 4071 cpu_icache_sync_range(va, len); 4072 } 4073 4074 /* 4075 * Routine: pmap_unwire 4076 * Function: Clear the wired attribute for a map/virtual-address pair. 4077 * 4078 * In/out conditions: 4079 * The mapping must already exist in the pmap. 4080 */ 4081 void 4082 pmap_unwire(pmap_t pm, vaddr_t va) 4083 { 4084 struct l2_bucket *l2b; 4085 pt_entry_t *ptep, pte; 4086 struct vm_page *pg; 4087 paddr_t pa; 4088 4089 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4090 4091 PMAP_MAP_TO_HEAD_LOCK(); 4092 pmap_acquire_pmap_lock(pm); 4093 4094 l2b = pmap_get_l2_bucket(pm, va); 4095 KDASSERT(l2b != NULL); 4096 4097 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4098 pte = *ptep; 4099 4100 /* Extract the physical address of the page */ 4101 pa = l2pte_pa(pte); 4102 4103 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4104 /* Update the wired bit in the pv entry for this page. */ 4105 simple_lock(&pg->mdpage.pvh_slock); 4106 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 4107 simple_unlock(&pg->mdpage.pvh_slock); 4108 } 4109 4110 pmap_release_pmap_lock(pm); 4111 PMAP_MAP_TO_HEAD_UNLOCK(); 4112 } 4113 4114 void 4115 pmap_activate(struct lwp *l) 4116 { 4117 extern int block_userspace_access; 4118 pmap_t opm, npm, rpm; 4119 uint32_t odacr, ndacr; 4120 int oldirqstate; 4121 4122 /* 4123 * If activating a non-current lwp or the current lwp is 4124 * already active, just return. 4125 */ 4126 if (l != curlwp || 4127 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4128 return; 4129 4130 npm = l->l_proc->p_vmspace->vm_map.pmap; 4131 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4132 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4133 4134 /* 4135 * If TTB and DACR are unchanged, short-circuit all the 4136 * TLB/cache management stuff. 4137 */ 4138 if (pmap_previous_active_lwp != NULL) { 4139 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4140 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4141 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4142 4143 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4144 goto all_done; 4145 } else 4146 opm = NULL; 4147 4148 PMAPCOUNT(activations); 4149 block_userspace_access = 1; 4150 4151 /* 4152 * If switching to a user vmspace which is different to the 4153 * most recent one, and the most recent one is potentially 4154 * live in the cache, we must write-back and invalidate the 4155 * entire cache. 4156 */ 4157 rpm = pmap_recent_user; 4158 if (npm != pmap_kernel() && rpm && npm != rpm && 4159 rpm->pm_cstate.cs_cache) { 4160 rpm->pm_cstate.cs_cache = 0; 4161 #ifdef PMAP_CACHE_VIVT 4162 cpu_idcache_wbinv_all(); 4163 #endif 4164 } 4165 4166 /* No interrupts while we frob the TTB/DACR */ 4167 oldirqstate = disable_interrupts(IF32_bits); 4168 4169 /* 4170 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4171 * entry corresponding to 'vector_page' in the incoming L1 table 4172 * before switching to it otherwise subsequent interrupts/exceptions 4173 * (including domain faults!) will jump into hyperspace. 4174 */ 4175 if (npm->pm_pl1vec != NULL) { 4176 cpu_tlb_flushID_SE((u_int)vector_page); 4177 cpu_cpwait(); 4178 *npm->pm_pl1vec = npm->pm_l1vec; 4179 PTE_SYNC(npm->pm_pl1vec); 4180 } 4181 4182 cpu_domains(ndacr); 4183 4184 if (npm == pmap_kernel() || npm == rpm) { 4185 /* 4186 * Switching to a kernel thread, or back to the 4187 * same user vmspace as before... Simply update 4188 * the TTB (no TLB flush required) 4189 */ 4190 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4191 "r"(npm->pm_l1->l1_physaddr)); 4192 cpu_cpwait(); 4193 } else { 4194 /* 4195 * Otherwise, update TTB and flush TLB 4196 */ 4197 cpu_context_switch(npm->pm_l1->l1_physaddr); 4198 if (rpm != NULL) 4199 rpm->pm_cstate.cs_tlb = 0; 4200 } 4201 4202 restore_interrupts(oldirqstate); 4203 4204 block_userspace_access = 0; 4205 4206 all_done: 4207 /* 4208 * The new pmap is resident. Make sure it's marked 4209 * as resident in the cache/TLB. 4210 */ 4211 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4212 if (npm != pmap_kernel()) 4213 pmap_recent_user = npm; 4214 4215 /* The old pmap is not longer active */ 4216 if (opm != NULL) 4217 opm->pm_activated = false; 4218 4219 /* But the new one is */ 4220 npm->pm_activated = true; 4221 } 4222 4223 void 4224 pmap_deactivate(struct lwp *l) 4225 { 4226 4227 /* 4228 * If the process is exiting, make sure pmap_activate() does 4229 * a full MMU context-switch and cache flush, which we might 4230 * otherwise skip. See PR port-arm/38950. 4231 */ 4232 if (l->l_proc->p_sflag & PS_WEXIT) 4233 pmap_previous_active_lwp = NULL; 4234 4235 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4236 } 4237 4238 void 4239 pmap_update(pmap_t pm) 4240 { 4241 4242 if (pm->pm_remove_all) { 4243 /* 4244 * Finish up the pmap_remove_all() optimisation by flushing 4245 * the TLB. 4246 */ 4247 pmap_tlb_flushID(pm); 4248 pm->pm_remove_all = false; 4249 } 4250 4251 if (pmap_is_current(pm)) { 4252 /* 4253 * If we're dealing with a current userland pmap, move its L1 4254 * to the end of the LRU. 4255 */ 4256 if (pm != pmap_kernel()) 4257 pmap_use_l1(pm); 4258 4259 /* 4260 * We can assume we're done with frobbing the cache/tlb for 4261 * now. Make sure any future pmap ops don't skip cache/tlb 4262 * flushes. 4263 */ 4264 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4265 } 4266 4267 PMAPCOUNT(updates); 4268 4269 /* 4270 * make sure TLB/cache operations have completed. 4271 */ 4272 cpu_cpwait(); 4273 } 4274 4275 void 4276 pmap_remove_all(pmap_t pm) 4277 { 4278 4279 /* 4280 * The vmspace described by this pmap is about to be torn down. 4281 * Until pmap_update() is called, UVM will only make calls 4282 * to pmap_remove(). We can make life much simpler by flushing 4283 * the cache now, and deferring TLB invalidation to pmap_update(). 4284 */ 4285 #ifdef PMAP_CACHE_VIVT 4286 pmap_idcache_wbinv_all(pm); 4287 #endif 4288 pm->pm_remove_all = true; 4289 } 4290 4291 /* 4292 * Retire the given physical map from service. 4293 * Should only be called if the map contains no valid mappings. 4294 */ 4295 void 4296 pmap_destroy(pmap_t pm) 4297 { 4298 u_int count; 4299 4300 if (pm == NULL) 4301 return; 4302 4303 if (pm->pm_remove_all) { 4304 pmap_tlb_flushID(pm); 4305 pm->pm_remove_all = false; 4306 } 4307 4308 /* 4309 * Drop reference count 4310 */ 4311 mutex_enter(&pm->pm_lock); 4312 count = --pm->pm_obj.uo_refs; 4313 mutex_exit(&pm->pm_lock); 4314 if (count > 0) { 4315 if (pmap_is_current(pm)) { 4316 if (pm != pmap_kernel()) 4317 pmap_use_l1(pm); 4318 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4319 } 4320 return; 4321 } 4322 4323 /* 4324 * reference count is zero, free pmap resources and then free pmap. 4325 */ 4326 4327 if (vector_page < KERNEL_BASE) { 4328 KDASSERT(!pmap_is_current(pm)); 4329 4330 /* Remove the vector page mapping */ 4331 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4332 pmap_update(pm); 4333 } 4334 4335 LIST_REMOVE(pm, pm_list); 4336 4337 pmap_free_l1(pm); 4338 4339 if (pmap_recent_user == pm) 4340 pmap_recent_user = NULL; 4341 4342 UVM_OBJ_DESTROY(&pm->pm_obj); 4343 4344 /* return the pmap to the pool */ 4345 pool_cache_put(&pmap_cache, pm); 4346 } 4347 4348 4349 /* 4350 * void pmap_reference(pmap_t pm) 4351 * 4352 * Add a reference to the specified pmap. 4353 */ 4354 void 4355 pmap_reference(pmap_t pm) 4356 { 4357 4358 if (pm == NULL) 4359 return; 4360 4361 pmap_use_l1(pm); 4362 4363 mutex_enter(&pm->pm_lock); 4364 pm->pm_obj.uo_refs++; 4365 mutex_exit(&pm->pm_lock); 4366 } 4367 4368 #if ARM_MMU_V6 > 0 4369 4370 static struct evcnt pmap_prefer_nochange_ev = 4371 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4372 static struct evcnt pmap_prefer_change_ev = 4373 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4374 4375 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4376 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4377 4378 void 4379 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4380 { 4381 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4382 vaddr_t va = *vap; 4383 vaddr_t diff = (hint - va) & mask; 4384 if (diff == 0) { 4385 pmap_prefer_nochange_ev.ev_count++; 4386 } else { 4387 pmap_prefer_change_ev.ev_count++; 4388 if (__predict_false(td)) 4389 va -= mask + 1; 4390 *vap = va + diff; 4391 } 4392 } 4393 #endif /* ARM_MMU_V6 */ 4394 4395 /* 4396 * pmap_zero_page() 4397 * 4398 * Zero a given physical page by mapping it at a page hook point. 4399 * In doing the zero page op, the page we zero is mapped cachable, as with 4400 * StrongARM accesses to non-cached pages are non-burst making writing 4401 * _any_ bulk data very slow. 4402 */ 4403 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4404 void 4405 pmap_zero_page_generic(paddr_t phys) 4406 { 4407 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4408 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4409 #endif 4410 #ifdef PMAP_CACHE_VIPT 4411 /* Choose the last page color it had, if any */ 4412 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4413 #else 4414 const vsize_t va_offset = 0; 4415 #endif 4416 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4417 4418 #ifdef DEBUG 4419 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4420 panic("pmap_zero_page: page has mappings"); 4421 #endif 4422 4423 KDASSERT((phys & PGOFSET) == 0); 4424 4425 /* 4426 * Hook in the page, zero it, and purge the cache for that 4427 * zeroed page. Invalidate the TLB as needed. 4428 */ 4429 *ptep = L2_S_PROTO | phys | 4430 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4431 PTE_SYNC(ptep); 4432 cpu_tlb_flushD_SE(cdstp + va_offset); 4433 cpu_cpwait(); 4434 bzero_page(cdstp + va_offset); 4435 /* 4436 * Unmap the page. 4437 */ 4438 *ptep = 0; 4439 PTE_SYNC(ptep); 4440 cpu_tlb_flushD_SE(cdstp + va_offset); 4441 #ifdef PMAP_CACHE_VIVT 4442 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4443 #endif 4444 #ifdef PMAP_CACHE_VIPT 4445 /* 4446 * This page is now cache resident so it now has a page color. 4447 * Any contents have been obliterated so clear the EXEC flag. 4448 */ 4449 if (!pmap_is_page_colored_p(pg)) { 4450 PMAPCOUNT(vac_color_new); 4451 pg->mdpage.pvh_attrs |= PVF_COLORED; 4452 } 4453 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4454 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4455 PMAPCOUNT(exec_discarded_zero); 4456 } 4457 pg->mdpage.pvh_attrs |= PVF_DIRTY; 4458 #endif 4459 } 4460 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4461 4462 #if ARM_MMU_XSCALE == 1 4463 void 4464 pmap_zero_page_xscale(paddr_t phys) 4465 { 4466 #ifdef DEBUG 4467 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4468 4469 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4470 panic("pmap_zero_page: page has mappings"); 4471 #endif 4472 4473 KDASSERT((phys & PGOFSET) == 0); 4474 4475 /* 4476 * Hook in the page, zero it, and purge the cache for that 4477 * zeroed page. Invalidate the TLB as needed. 4478 */ 4479 *cdst_pte = L2_S_PROTO | phys | 4480 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4481 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4482 PTE_SYNC(cdst_pte); 4483 cpu_tlb_flushD_SE(cdstp); 4484 cpu_cpwait(); 4485 bzero_page(cdstp); 4486 xscale_cache_clean_minidata(); 4487 } 4488 #endif /* ARM_MMU_XSCALE == 1 */ 4489 4490 /* pmap_pageidlezero() 4491 * 4492 * The same as above, except that we assume that the page is not 4493 * mapped. This means we never have to flush the cache first. Called 4494 * from the idle loop. 4495 */ 4496 bool 4497 pmap_pageidlezero(paddr_t phys) 4498 { 4499 unsigned int i; 4500 int *ptr; 4501 bool rv = true; 4502 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4503 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4504 #endif 4505 #ifdef PMAP_CACHE_VIPT 4506 /* Choose the last page color it had, if any */ 4507 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4508 #else 4509 const vsize_t va_offset = 0; 4510 #endif 4511 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4512 4513 4514 #ifdef DEBUG 4515 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4516 panic("pmap_pageidlezero: page has mappings"); 4517 #endif 4518 4519 KDASSERT((phys & PGOFSET) == 0); 4520 4521 /* 4522 * Hook in the page, zero it, and purge the cache for that 4523 * zeroed page. Invalidate the TLB as needed. 4524 */ 4525 *ptep = L2_S_PROTO | phys | 4526 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4527 PTE_SYNC(ptep); 4528 cpu_tlb_flushD_SE(cdstp + va_offset); 4529 cpu_cpwait(); 4530 4531 for (i = 0, ptr = (int *)(cdstp + va_offset); 4532 i < (PAGE_SIZE / sizeof(int)); i++) { 4533 if (sched_curcpu_runnable_p() != 0) { 4534 /* 4535 * A process has become ready. Abort now, 4536 * so we don't keep it waiting while we 4537 * do slow memory access to finish this 4538 * page. 4539 */ 4540 rv = false; 4541 break; 4542 } 4543 *ptr++ = 0; 4544 } 4545 4546 #ifdef PMAP_CACHE_VIVT 4547 if (rv) 4548 /* 4549 * if we aborted we'll rezero this page again later so don't 4550 * purge it unless we finished it 4551 */ 4552 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4553 #elif defined(PMAP_CACHE_VIPT) 4554 /* 4555 * This page is now cache resident so it now has a page color. 4556 * Any contents have been obliterated so clear the EXEC flag. 4557 */ 4558 if (!pmap_is_page_colored_p(pg)) { 4559 PMAPCOUNT(vac_color_new); 4560 pg->mdpage.pvh_attrs |= PVF_COLORED; 4561 } 4562 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4563 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4564 PMAPCOUNT(exec_discarded_zero); 4565 } 4566 #endif 4567 /* 4568 * Unmap the page. 4569 */ 4570 *ptep = 0; 4571 PTE_SYNC(ptep); 4572 cpu_tlb_flushD_SE(cdstp + va_offset); 4573 4574 return (rv); 4575 } 4576 4577 /* 4578 * pmap_copy_page() 4579 * 4580 * Copy one physical page into another, by mapping the pages into 4581 * hook points. The same comment regarding cachability as in 4582 * pmap_zero_page also applies here. 4583 */ 4584 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4585 void 4586 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4587 { 4588 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4589 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4590 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4591 #endif 4592 #ifdef PMAP_CACHE_VIPT 4593 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4594 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4595 #else 4596 const vsize_t src_va_offset = 0; 4597 const vsize_t dst_va_offset = 0; 4598 #endif 4599 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4600 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4601 4602 #ifdef DEBUG 4603 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4604 panic("pmap_copy_page: dst page has mappings"); 4605 #endif 4606 4607 #ifdef PMAP_CACHE_VIPT 4608 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4609 #endif 4610 KDASSERT((src & PGOFSET) == 0); 4611 KDASSERT((dst & PGOFSET) == 0); 4612 4613 /* 4614 * Clean the source page. Hold the source page's lock for 4615 * the duration of the copy so that no other mappings can 4616 * be created while we have a potentially aliased mapping. 4617 */ 4618 simple_lock(&src_pg->mdpage.pvh_slock); 4619 #ifdef PMAP_CACHE_VIVT 4620 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4621 #endif 4622 4623 /* 4624 * Map the pages into the page hook points, copy them, and purge 4625 * the cache for the appropriate page. Invalidate the TLB 4626 * as required. 4627 */ 4628 *src_ptep = L2_S_PROTO 4629 | src 4630 #ifdef PMAP_CACHE_VIPT 4631 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4632 #endif 4633 #ifdef PMAP_CACHE_VIVT 4634 | pte_l2_s_cache_mode 4635 #endif 4636 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4637 *dst_ptep = L2_S_PROTO | dst | 4638 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4639 PTE_SYNC(src_ptep); 4640 PTE_SYNC(dst_ptep); 4641 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4642 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4643 cpu_cpwait(); 4644 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4645 #ifdef PMAP_CACHE_VIVT 4646 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4647 #endif 4648 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4649 #ifdef PMAP_CACHE_VIVT 4650 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4651 #endif 4652 /* 4653 * Unmap the pages. 4654 */ 4655 *src_ptep = 0; 4656 *dst_ptep = 0; 4657 PTE_SYNC(src_ptep); 4658 PTE_SYNC(dst_ptep); 4659 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4660 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4661 #ifdef PMAP_CACHE_VIPT 4662 /* 4663 * Now that the destination page is in the cache, mark it as colored. 4664 * If this was an exec page, discard it. 4665 */ 4666 if (!pmap_is_page_colored_p(dst_pg)) { 4667 PMAPCOUNT(vac_color_new); 4668 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4669 } 4670 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4671 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4672 PMAPCOUNT(exec_discarded_copy); 4673 } 4674 dst_pg->mdpage.pvh_attrs |= PVF_DIRTY; 4675 #endif 4676 } 4677 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4678 4679 #if ARM_MMU_XSCALE == 1 4680 void 4681 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4682 { 4683 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4684 #ifdef DEBUG 4685 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4686 4687 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4688 panic("pmap_copy_page: dst page has mappings"); 4689 #endif 4690 4691 KDASSERT((src & PGOFSET) == 0); 4692 KDASSERT((dst & PGOFSET) == 0); 4693 4694 /* 4695 * Clean the source page. Hold the source page's lock for 4696 * the duration of the copy so that no other mappings can 4697 * be created while we have a potentially aliased mapping. 4698 */ 4699 simple_lock(&src_pg->mdpage.pvh_slock); 4700 #ifdef PMAP_CACHE_VIVT 4701 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4702 #endif 4703 4704 /* 4705 * Map the pages into the page hook points, copy them, and purge 4706 * the cache for the appropriate page. Invalidate the TLB 4707 * as required. 4708 */ 4709 *csrc_pte = L2_S_PROTO | src | 4710 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4711 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4712 PTE_SYNC(csrc_pte); 4713 *cdst_pte = L2_S_PROTO | dst | 4714 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4715 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4716 PTE_SYNC(cdst_pte); 4717 cpu_tlb_flushD_SE(csrcp); 4718 cpu_tlb_flushD_SE(cdstp); 4719 cpu_cpwait(); 4720 bcopy_page(csrcp, cdstp); 4721 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4722 xscale_cache_clean_minidata(); 4723 } 4724 #endif /* ARM_MMU_XSCALE == 1 */ 4725 4726 /* 4727 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4728 * 4729 * Return the start and end addresses of the kernel's virtual space. 4730 * These values are setup in pmap_bootstrap and are updated as pages 4731 * are allocated. 4732 */ 4733 void 4734 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4735 { 4736 *start = virtual_avail; 4737 *end = virtual_end; 4738 } 4739 4740 /* 4741 * Helper function for pmap_grow_l2_bucket() 4742 */ 4743 static inline int 4744 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4745 { 4746 struct l2_bucket *l2b; 4747 pt_entry_t *ptep; 4748 paddr_t pa; 4749 4750 if (uvm.page_init_done == false) { 4751 #ifdef PMAP_STEAL_MEMORY 4752 pv_addr_t pv; 4753 pmap_boot_pagealloc(PAGE_SIZE, 4754 #ifdef PMAP_CACHE_VIPT 4755 arm_cache_prefer_mask, 4756 va & arm_cache_prefer_mask, 4757 #else 4758 0, 0, 4759 #endif 4760 &pv); 4761 pa = pv.pv_pa; 4762 #else 4763 if (uvm_page_physget(&pa) == false) 4764 return (1); 4765 #endif /* PMAP_STEAL_MEMORY */ 4766 } else { 4767 struct vm_page *pg; 4768 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4769 if (pg == NULL) 4770 return (1); 4771 pa = VM_PAGE_TO_PHYS(pg); 4772 #ifdef PMAP_CACHE_VIPT 4773 /* 4774 * This new page must not have any mappings. Enter it via 4775 * pmap_kenter_pa and let that routine do the hard work. 4776 */ 4777 KASSERT(SLIST_EMPTY(&pg->mdpage.pvh_list)); 4778 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 4779 #endif 4780 } 4781 4782 if (pap) 4783 *pap = pa; 4784 4785 PMAPCOUNT(pt_mappings); 4786 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4787 KDASSERT(l2b != NULL); 4788 4789 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4790 *ptep = L2_S_PROTO | pa | cache_mode | 4791 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4792 PTE_SYNC(ptep); 4793 memset((void *)va, 0, PAGE_SIZE); 4794 return (0); 4795 } 4796 4797 /* 4798 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4799 * used by pmap_growkernel(). 4800 */ 4801 static inline struct l2_bucket * 4802 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4803 { 4804 struct l2_dtable *l2; 4805 struct l2_bucket *l2b; 4806 u_short l1idx; 4807 vaddr_t nva; 4808 4809 l1idx = L1_IDX(va); 4810 4811 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4812 /* 4813 * No mapping at this address, as there is 4814 * no entry in the L1 table. 4815 * Need to allocate a new l2_dtable. 4816 */ 4817 nva = pmap_kernel_l2dtable_kva; 4818 if ((nva & PGOFSET) == 0) { 4819 /* 4820 * Need to allocate a backing page 4821 */ 4822 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4823 return (NULL); 4824 } 4825 4826 l2 = (struct l2_dtable *)nva; 4827 nva += sizeof(struct l2_dtable); 4828 4829 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4830 /* 4831 * The new l2_dtable straddles a page boundary. 4832 * Map in another page to cover it. 4833 */ 4834 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4835 return (NULL); 4836 } 4837 4838 pmap_kernel_l2dtable_kva = nva; 4839 4840 /* 4841 * Link it into the parent pmap 4842 */ 4843 pm->pm_l2[L2_IDX(l1idx)] = l2; 4844 } 4845 4846 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4847 4848 /* 4849 * Fetch pointer to the L2 page table associated with the address. 4850 */ 4851 if (l2b->l2b_kva == NULL) { 4852 pt_entry_t *ptep; 4853 4854 /* 4855 * No L2 page table has been allocated. Chances are, this 4856 * is because we just allocated the l2_dtable, above. 4857 */ 4858 nva = pmap_kernel_l2ptp_kva; 4859 ptep = (pt_entry_t *)nva; 4860 if ((nva & PGOFSET) == 0) { 4861 /* 4862 * Need to allocate a backing page 4863 */ 4864 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4865 &pmap_kernel_l2ptp_phys)) 4866 return (NULL); 4867 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4868 } 4869 4870 l2->l2_occupancy++; 4871 l2b->l2b_kva = ptep; 4872 l2b->l2b_l1idx = l1idx; 4873 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4874 4875 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4876 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4877 } 4878 4879 return (l2b); 4880 } 4881 4882 vaddr_t 4883 pmap_growkernel(vaddr_t maxkvaddr) 4884 { 4885 pmap_t kpm = pmap_kernel(); 4886 struct l1_ttable *l1; 4887 struct l2_bucket *l2b; 4888 pd_entry_t *pl1pd; 4889 int s; 4890 4891 if (maxkvaddr <= pmap_curmaxkvaddr) 4892 goto out; /* we are OK */ 4893 4894 NPDEBUG(PDB_GROWKERN, 4895 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4896 pmap_curmaxkvaddr, maxkvaddr)); 4897 4898 KDASSERT(maxkvaddr <= virtual_end); 4899 4900 /* 4901 * whoops! we need to add kernel PTPs 4902 */ 4903 4904 s = splhigh(); /* to be safe */ 4905 mutex_enter(&kpm->pm_lock); 4906 4907 /* Map 1MB at a time */ 4908 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4909 4910 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4911 KDASSERT(l2b != NULL); 4912 4913 /* Distribute new L1 entry to all other L1s */ 4914 SLIST_FOREACH(l1, &l1_list, l1_link) { 4915 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4916 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4917 L1_C_PROTO; 4918 PTE_SYNC(pl1pd); 4919 } 4920 } 4921 4922 /* 4923 * flush out the cache, expensive but growkernel will happen so 4924 * rarely 4925 */ 4926 cpu_dcache_wbinv_all(); 4927 cpu_tlb_flushD(); 4928 cpu_cpwait(); 4929 4930 mutex_exit(&kpm->pm_lock); 4931 splx(s); 4932 4933 out: 4934 return (pmap_curmaxkvaddr); 4935 } 4936 4937 /************************ Utility routines ****************************/ 4938 4939 /* 4940 * vector_page_setprot: 4941 * 4942 * Manipulate the protection of the vector page. 4943 */ 4944 void 4945 vector_page_setprot(int prot) 4946 { 4947 struct l2_bucket *l2b; 4948 pt_entry_t *ptep; 4949 4950 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4951 KDASSERT(l2b != NULL); 4952 4953 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4954 4955 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4956 PTE_SYNC(ptep); 4957 cpu_tlb_flushD_SE(vector_page); 4958 cpu_cpwait(); 4959 } 4960 4961 /* 4962 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4963 * Returns true if the mapping exists, else false. 4964 * 4965 * NOTE: This function is only used by a couple of arm-specific modules. 4966 * It is not safe to take any pmap locks here, since we could be right 4967 * in the middle of debugging the pmap anyway... 4968 * 4969 * It is possible for this routine to return false even though a valid 4970 * mapping does exist. This is because we don't lock, so the metadata 4971 * state may be inconsistent. 4972 * 4973 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4974 * a "section" mapping. 4975 */ 4976 bool 4977 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4978 { 4979 struct l2_dtable *l2; 4980 pd_entry_t *pl1pd, l1pd; 4981 pt_entry_t *ptep; 4982 u_short l1idx; 4983 4984 if (pm->pm_l1 == NULL) 4985 return false; 4986 4987 l1idx = L1_IDX(va); 4988 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4989 l1pd = *pl1pd; 4990 4991 if (l1pte_section_p(l1pd)) { 4992 *ptp = NULL; 4993 return true; 4994 } 4995 4996 if (pm->pm_l2 == NULL) 4997 return false; 4998 4999 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5000 5001 if (l2 == NULL || 5002 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5003 return false; 5004 } 5005 5006 *ptp = &ptep[l2pte_index(va)]; 5007 return true; 5008 } 5009 5010 bool 5011 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5012 { 5013 u_short l1idx; 5014 5015 if (pm->pm_l1 == NULL) 5016 return false; 5017 5018 l1idx = L1_IDX(va); 5019 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5020 5021 return true; 5022 } 5023 5024 /************************ Bootstrapping routines ****************************/ 5025 5026 static void 5027 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5028 { 5029 int i; 5030 5031 l1->l1_kva = l1pt; 5032 l1->l1_domain_use_count = 0; 5033 l1->l1_domain_first = 0; 5034 5035 for (i = 0; i < PMAP_DOMAINS; i++) 5036 l1->l1_domain_free[i] = i + 1; 5037 5038 /* 5039 * Copy the kernel's L1 entries to each new L1. 5040 */ 5041 if (pmap_initialized) 5042 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5043 5044 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5045 &l1->l1_physaddr) == false) 5046 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5047 5048 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5049 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5050 } 5051 5052 /* 5053 * pmap_bootstrap() is called from the board-specific initarm() routine 5054 * once the kernel L1/L2 descriptors tables have been set up. 5055 * 5056 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5057 * spread over a number of disparate files/functions. 5058 * 5059 * We are passed the following parameters 5060 * - kernel_l1pt 5061 * This is a pointer to the base of the kernel's L1 translation table. 5062 * - vstart 5063 * 1MB-aligned start of managed kernel virtual memory. 5064 * - vend 5065 * 1MB-aligned end of managed kernel virtual memory. 5066 * 5067 * We use the first parameter to build the metadata (struct l1_ttable and 5068 * struct l2_dtable) necessary to track kernel mappings. 5069 */ 5070 #define PMAP_STATIC_L2_SIZE 16 5071 void 5072 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5073 { 5074 static struct l1_ttable static_l1; 5075 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5076 struct l1_ttable *l1 = &static_l1; 5077 struct l2_dtable *l2; 5078 struct l2_bucket *l2b; 5079 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5080 pmap_t pm = pmap_kernel(); 5081 pd_entry_t pde; 5082 pt_entry_t *ptep; 5083 paddr_t pa; 5084 vaddr_t va; 5085 vsize_t size; 5086 int nptes, l1idx, l2idx, l2next = 0; 5087 5088 /* 5089 * Initialise the kernel pmap object 5090 */ 5091 pm->pm_l1 = l1; 5092 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5093 pm->pm_activated = true; 5094 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5095 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5096 5097 /* 5098 * Scan the L1 translation table created by initarm() and create 5099 * the required metadata for all valid mappings found in it. 5100 */ 5101 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5102 pde = l1pt[l1idx]; 5103 5104 /* 5105 * We're only interested in Coarse mappings. 5106 * pmap_extract() can deal with section mappings without 5107 * recourse to checking L2 metadata. 5108 */ 5109 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5110 continue; 5111 5112 /* 5113 * Lookup the KVA of this L2 descriptor table 5114 */ 5115 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5116 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5117 if (ptep == NULL) { 5118 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5119 (u_int)l1idx << L1_S_SHIFT, pa); 5120 } 5121 5122 /* 5123 * Fetch the associated L2 metadata structure. 5124 * Allocate a new one if necessary. 5125 */ 5126 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5127 if (l2next == PMAP_STATIC_L2_SIZE) 5128 panic("pmap_bootstrap: out of static L2s"); 5129 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5130 } 5131 5132 /* 5133 * One more L1 slot tracked... 5134 */ 5135 l2->l2_occupancy++; 5136 5137 /* 5138 * Fill in the details of the L2 descriptor in the 5139 * appropriate bucket. 5140 */ 5141 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5142 l2b->l2b_kva = ptep; 5143 l2b->l2b_phys = pa; 5144 l2b->l2b_l1idx = l1idx; 5145 5146 /* 5147 * Establish an initial occupancy count for this descriptor 5148 */ 5149 for (l2idx = 0; 5150 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5151 l2idx++) { 5152 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5153 l2b->l2b_occupancy++; 5154 } 5155 } 5156 5157 /* 5158 * Make sure the descriptor itself has the correct cache mode. 5159 * If not, fix it, but whine about the problem. Port-meisters 5160 * should consider this a clue to fix up their initarm() 5161 * function. :) 5162 */ 5163 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5164 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5165 "L2 pte @ %p\n", ptep); 5166 } 5167 } 5168 5169 /* 5170 * Ensure the primary (kernel) L1 has the correct cache mode for 5171 * a page table. Bitch if it is not correctly set. 5172 */ 5173 for (va = (vaddr_t)l1pt; 5174 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5175 if (pmap_set_pt_cache_mode(l1pt, va)) 5176 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5177 "primary L1 @ 0x%lx\n", va); 5178 } 5179 5180 cpu_dcache_wbinv_all(); 5181 cpu_tlb_flushID(); 5182 cpu_cpwait(); 5183 5184 /* 5185 * now we allocate the "special" VAs which are used for tmp mappings 5186 * by the pmap (and other modules). we allocate the VAs by advancing 5187 * virtual_avail (note that there are no pages mapped at these VAs). 5188 * 5189 * Managed KVM space start from wherever initarm() tells us. 5190 */ 5191 virtual_avail = vstart; 5192 virtual_end = vend; 5193 5194 #ifdef PMAP_CACHE_VIPT 5195 /* 5196 * If we have a VIPT cache, we need one page/pte per possible alias 5197 * page so we won't violate cache aliasing rules. 5198 */ 5199 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5200 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5201 #else 5202 nptes = 1; 5203 #endif 5204 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5205 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5206 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5207 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5208 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5209 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5210 (void *)&msgbufaddr, NULL); 5211 5212 /* 5213 * Allocate a range of kernel virtual address space to be used 5214 * for L2 descriptor tables and metadata allocation in 5215 * pmap_growkernel(). 5216 */ 5217 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5218 pmap_alloc_specials(&virtual_avail, 5219 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5220 &pmap_kernel_l2ptp_kva, NULL); 5221 5222 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5223 pmap_alloc_specials(&virtual_avail, 5224 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5225 &pmap_kernel_l2dtable_kva, NULL); 5226 5227 /* 5228 * init the static-global locks and global pmap list. 5229 */ 5230 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5231 5232 /* 5233 * We can now initialise the first L1's metadata. 5234 */ 5235 SLIST_INIT(&l1_list); 5236 TAILQ_INIT(&l1_lru_list); 5237 simple_lock_init(&l1_lru_lock); 5238 pmap_init_l1(l1, l1pt); 5239 5240 /* Set up vector page L1 details, if necessary */ 5241 if (vector_page < KERNEL_BASE) { 5242 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5243 l2b = pmap_get_l2_bucket(pm, vector_page); 5244 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5245 L1_C_DOM(pm->pm_domain); 5246 } else 5247 pm->pm_pl1vec = NULL; 5248 5249 /* 5250 * Initialize the pmap cache 5251 */ 5252 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5253 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5254 LIST_INIT(&pmap_pmaps); 5255 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5256 5257 /* 5258 * Initialize the pv pool. 5259 */ 5260 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5261 &pmap_bootstrap_pv_allocator, IPL_NONE); 5262 5263 /* 5264 * Initialize the L2 dtable pool and cache. 5265 */ 5266 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5267 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5268 5269 /* 5270 * Initialise the L2 descriptor table pool and cache 5271 */ 5272 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5273 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5274 pmap_l2ptp_ctor, NULL, NULL); 5275 5276 cpu_dcache_wbinv_all(); 5277 } 5278 5279 static int 5280 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5281 { 5282 pd_entry_t *pdep, pde; 5283 pt_entry_t *ptep, pte; 5284 vaddr_t pa; 5285 int rv = 0; 5286 5287 /* 5288 * Make sure the descriptor itself has the correct cache mode 5289 */ 5290 pdep = &kl1[L1_IDX(va)]; 5291 pde = *pdep; 5292 5293 if (l1pte_section_p(pde)) { 5294 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5295 *pdep = (pde & ~L1_S_CACHE_MASK) | 5296 pte_l1_s_cache_mode_pt; 5297 PTE_SYNC(pdep); 5298 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5299 rv = 1; 5300 } 5301 } else { 5302 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5303 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5304 if (ptep == NULL) 5305 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5306 5307 ptep = &ptep[l2pte_index(va)]; 5308 pte = *ptep; 5309 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5310 *ptep = (pte & ~L2_S_CACHE_MASK) | 5311 pte_l2_s_cache_mode_pt; 5312 PTE_SYNC(ptep); 5313 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5314 rv = 1; 5315 } 5316 } 5317 5318 return (rv); 5319 } 5320 5321 static void 5322 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5323 { 5324 vaddr_t va = *availp; 5325 struct l2_bucket *l2b; 5326 5327 if (ptep) { 5328 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5329 if (l2b == NULL) 5330 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5331 5332 if (ptep) 5333 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5334 } 5335 5336 *vap = va; 5337 *availp = va + (PAGE_SIZE * pages); 5338 } 5339 5340 void 5341 pmap_init(void) 5342 { 5343 5344 /* 5345 * Set the available memory vars - These do not map to real memory 5346 * addresses and cannot as the physical memory is fragmented. 5347 * They are used by ps for %mem calculations. 5348 * One could argue whether this should be the entire memory or just 5349 * the memory that is useable in a user process. 5350 */ 5351 avail_start = ptoa(vm_physmem[0].start); 5352 avail_end = ptoa(vm_physmem[vm_nphysseg - 1].end); 5353 5354 /* 5355 * Now we need to free enough pv_entry structures to allow us to get 5356 * the kmem_map/kmem_object allocated and inited (done after this 5357 * function is finished). to do this we allocate one bootstrap page out 5358 * of kernel_map and use it to provide an initial pool of pv_entry 5359 * structures. we never free this page. 5360 */ 5361 pool_setlowat(&pmap_pv_pool, 5362 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5363 5364 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5365 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5366 UVM_KMF_WIRED|UVM_KMF_ZERO); 5367 5368 pmap_initialized = true; 5369 } 5370 5371 static vaddr_t last_bootstrap_page = 0; 5372 static void *free_bootstrap_pages = NULL; 5373 5374 static void * 5375 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5376 { 5377 extern void *pool_page_alloc(struct pool *, int); 5378 vaddr_t new_page; 5379 void *rv; 5380 5381 if (pmap_initialized) 5382 return (pool_page_alloc(pp, flags)); 5383 5384 if (free_bootstrap_pages) { 5385 rv = free_bootstrap_pages; 5386 free_bootstrap_pages = *((void **)rv); 5387 return (rv); 5388 } 5389 5390 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5391 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5392 5393 KASSERT(new_page > last_bootstrap_page); 5394 last_bootstrap_page = new_page; 5395 return ((void *)new_page); 5396 } 5397 5398 static void 5399 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5400 { 5401 extern void pool_page_free(struct pool *, void *); 5402 5403 if ((vaddr_t)v <= last_bootstrap_page) { 5404 *((void **)v) = free_bootstrap_pages; 5405 free_bootstrap_pages = v; 5406 return; 5407 } 5408 5409 if (pmap_initialized) { 5410 pool_page_free(pp, v); 5411 return; 5412 } 5413 } 5414 5415 /* 5416 * pmap_postinit() 5417 * 5418 * This routine is called after the vm and kmem subsystems have been 5419 * initialised. This allows the pmap code to perform any initialisation 5420 * that can only be done one the memory allocation is in place. 5421 */ 5422 void 5423 pmap_postinit(void) 5424 { 5425 extern paddr_t physical_start, physical_end; 5426 struct l2_bucket *l2b; 5427 struct l1_ttable *l1; 5428 struct pglist plist; 5429 struct vm_page *m; 5430 pd_entry_t *pl1pt; 5431 pt_entry_t *ptep, pte; 5432 vaddr_t va, eva; 5433 u_int loop, needed; 5434 int error; 5435 5436 pool_cache_setlowat(&pmap_l2ptp_cache, 5437 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5438 pool_cache_setlowat(&pmap_l2dtable_cache, 5439 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5440 5441 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5442 needed -= 1; 5443 5444 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5445 5446 for (loop = 0; loop < needed; loop++, l1++) { 5447 /* Allocate a L1 page table */ 5448 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5449 if (va == 0) 5450 panic("Cannot allocate L1 KVM"); 5451 5452 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5453 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5454 if (error) 5455 panic("Cannot allocate L1 physical pages"); 5456 5457 m = TAILQ_FIRST(&plist); 5458 eva = va + L1_TABLE_SIZE; 5459 pl1pt = (pd_entry_t *)va; 5460 5461 while (m && va < eva) { 5462 paddr_t pa = VM_PAGE_TO_PHYS(m); 5463 5464 pmap_kenter_pa(va, pa, 5465 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); 5466 5467 /* 5468 * Make sure the L1 descriptor table is mapped 5469 * with the cache-mode set to write-through. 5470 */ 5471 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5472 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5473 pte = *ptep; 5474 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5475 *ptep = pte; 5476 PTE_SYNC(ptep); 5477 cpu_tlb_flushD_SE(va); 5478 5479 va += PAGE_SIZE; 5480 m = TAILQ_NEXT(m, pageq.queue); 5481 } 5482 5483 #ifdef DIAGNOSTIC 5484 if (m) 5485 panic("pmap_alloc_l1pt: pglist not empty"); 5486 #endif /* DIAGNOSTIC */ 5487 5488 pmap_init_l1(l1, pl1pt); 5489 } 5490 5491 #ifdef DEBUG 5492 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5493 needed); 5494 #endif 5495 } 5496 5497 /* 5498 * Note that the following routines are used by board-specific initialisation 5499 * code to configure the initial kernel page tables. 5500 * 5501 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5502 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5503 * behaviour of the old pmap, and provides an easy migration path for 5504 * initial bring-up of the new pmap on existing ports. Fortunately, 5505 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5506 * will be deprecated. 5507 * 5508 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5509 * tables. 5510 */ 5511 5512 /* 5513 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5514 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5515 * find them as necessary. 5516 * 5517 * Note that the data on this list MUST remain valid after initarm() returns, 5518 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5519 */ 5520 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5521 5522 static vaddr_t 5523 kernel_pt_lookup(paddr_t pa) 5524 { 5525 pv_addr_t *pv; 5526 5527 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5528 #ifndef ARM32_NEW_VM_LAYOUT 5529 if (pv->pv_pa == (pa & ~PGOFSET)) 5530 return (pv->pv_va | (pa & PGOFSET)); 5531 #else 5532 if (pv->pv_pa == pa) 5533 return (pv->pv_va); 5534 #endif 5535 } 5536 return (0); 5537 } 5538 5539 /* 5540 * pmap_map_section: 5541 * 5542 * Create a single section mapping. 5543 */ 5544 void 5545 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5546 { 5547 pd_entry_t *pde = (pd_entry_t *) l1pt; 5548 pd_entry_t fl; 5549 5550 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5551 5552 switch (cache) { 5553 case PTE_NOCACHE: 5554 default: 5555 fl = 0; 5556 break; 5557 5558 case PTE_CACHE: 5559 fl = pte_l1_s_cache_mode; 5560 break; 5561 5562 case PTE_PAGETABLE: 5563 fl = pte_l1_s_cache_mode_pt; 5564 break; 5565 } 5566 5567 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5568 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5569 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5570 } 5571 5572 /* 5573 * pmap_map_entry: 5574 * 5575 * Create a single page mapping. 5576 */ 5577 void 5578 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5579 { 5580 pd_entry_t *pde = (pd_entry_t *) l1pt; 5581 pt_entry_t fl; 5582 pt_entry_t *pte; 5583 5584 KASSERT(((va | pa) & PGOFSET) == 0); 5585 5586 switch (cache) { 5587 case PTE_NOCACHE: 5588 default: 5589 fl = 0; 5590 break; 5591 5592 case PTE_CACHE: 5593 fl = pte_l2_s_cache_mode; 5594 break; 5595 5596 case PTE_PAGETABLE: 5597 fl = pte_l2_s_cache_mode_pt; 5598 break; 5599 } 5600 5601 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5602 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5603 5604 #ifndef ARM32_NEW_VM_LAYOUT 5605 pte = (pt_entry_t *) 5606 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5607 #else 5608 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5609 #endif 5610 if (pte == NULL) 5611 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5612 5613 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5614 #ifndef ARM32_NEW_VM_LAYOUT 5615 pte += (va >> PGSHIFT) & 0x3ff; 5616 #else 5617 pte += l2pte_index(va); 5618 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5619 #endif 5620 *pte = fl; 5621 PTE_SYNC(pte); 5622 } 5623 5624 /* 5625 * pmap_link_l2pt: 5626 * 5627 * Link the L2 page table specified by "l2pv" into the L1 5628 * page table at the slot for "va". 5629 */ 5630 void 5631 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5632 { 5633 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5634 u_int slot = va >> L1_S_SHIFT; 5635 5636 #ifndef ARM32_NEW_VM_LAYOUT 5637 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5638 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5639 #endif 5640 5641 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5642 5643 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5644 #ifdef ARM32_NEW_VM_LAYOUT 5645 PTE_SYNC(&pde[slot]); 5646 #else 5647 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5648 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5649 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5650 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5651 #endif 5652 5653 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5654 } 5655 5656 /* 5657 * pmap_map_chunk: 5658 * 5659 * Map a chunk of memory using the most efficient mappings 5660 * possible (section, large page, small page) into the 5661 * provided L1 and L2 tables at the specified virtual address. 5662 */ 5663 vsize_t 5664 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5665 int prot, int cache) 5666 { 5667 pd_entry_t *pde = (pd_entry_t *) l1pt; 5668 pt_entry_t *pte, f1, f2s, f2l; 5669 vsize_t resid; 5670 int i; 5671 5672 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5673 5674 if (l1pt == 0) 5675 panic("pmap_map_chunk: no L1 table provided"); 5676 5677 #ifdef VERBOSE_INIT_ARM 5678 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5679 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5680 #endif 5681 5682 switch (cache) { 5683 case PTE_NOCACHE: 5684 default: 5685 f1 = 0; 5686 f2l = 0; 5687 f2s = 0; 5688 break; 5689 5690 case PTE_CACHE: 5691 f1 = pte_l1_s_cache_mode; 5692 f2l = pte_l2_l_cache_mode; 5693 f2s = pte_l2_s_cache_mode; 5694 break; 5695 5696 case PTE_PAGETABLE: 5697 f1 = pte_l1_s_cache_mode_pt; 5698 f2l = pte_l2_l_cache_mode_pt; 5699 f2s = pte_l2_s_cache_mode_pt; 5700 break; 5701 } 5702 5703 size = resid; 5704 5705 while (resid > 0) { 5706 /* See if we can use a section mapping. */ 5707 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5708 #ifdef VERBOSE_INIT_ARM 5709 printf("S"); 5710 #endif 5711 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5712 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5713 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5714 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5715 va += L1_S_SIZE; 5716 pa += L1_S_SIZE; 5717 resid -= L1_S_SIZE; 5718 continue; 5719 } 5720 5721 /* 5722 * Ok, we're going to use an L2 table. Make sure 5723 * one is actually in the corresponding L1 slot 5724 * for the current VA. 5725 */ 5726 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5727 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5728 5729 #ifndef ARM32_NEW_VM_LAYOUT 5730 pte = (pt_entry_t *) 5731 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5732 #else 5733 pte = (pt_entry_t *) kernel_pt_lookup( 5734 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5735 #endif 5736 if (pte == NULL) 5737 panic("pmap_map_chunk: can't find L2 table for VA" 5738 "0x%08lx", va); 5739 5740 /* See if we can use a L2 large page mapping. */ 5741 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5742 #ifdef VERBOSE_INIT_ARM 5743 printf("L"); 5744 #endif 5745 for (i = 0; i < 16; i++) { 5746 #ifndef ARM32_NEW_VM_LAYOUT 5747 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5748 L2_L_PROTO | pa | 5749 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5750 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5751 #else 5752 pte[l2pte_index(va) + i] = 5753 L2_L_PROTO | pa | 5754 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5755 PTE_SYNC(&pte[l2pte_index(va) + i]); 5756 #endif 5757 } 5758 va += L2_L_SIZE; 5759 pa += L2_L_SIZE; 5760 resid -= L2_L_SIZE; 5761 continue; 5762 } 5763 5764 /* Use a small page mapping. */ 5765 #ifdef VERBOSE_INIT_ARM 5766 printf("P"); 5767 #endif 5768 #ifndef ARM32_NEW_VM_LAYOUT 5769 pte[(va >> PGSHIFT) & 0x3ff] = 5770 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5771 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5772 #else 5773 pte[l2pte_index(va)] = 5774 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5775 PTE_SYNC(&pte[l2pte_index(va)]); 5776 #endif 5777 va += PAGE_SIZE; 5778 pa += PAGE_SIZE; 5779 resid -= PAGE_SIZE; 5780 } 5781 #ifdef VERBOSE_INIT_ARM 5782 printf("\n"); 5783 #endif 5784 return (size); 5785 } 5786 5787 /********************** Static device map routines ***************************/ 5788 5789 static const struct pmap_devmap *pmap_devmap_table; 5790 5791 /* 5792 * Register the devmap table. This is provided in case early console 5793 * initialization needs to register mappings created by bootstrap code 5794 * before pmap_devmap_bootstrap() is called. 5795 */ 5796 void 5797 pmap_devmap_register(const struct pmap_devmap *table) 5798 { 5799 5800 pmap_devmap_table = table; 5801 } 5802 5803 /* 5804 * Map all of the static regions in the devmap table, and remember 5805 * the devmap table so other parts of the kernel can look up entries 5806 * later. 5807 */ 5808 void 5809 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5810 { 5811 int i; 5812 5813 pmap_devmap_table = table; 5814 5815 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5816 #ifdef VERBOSE_INIT_ARM 5817 printf("devmap: %08lx -> %08lx @ %08lx\n", 5818 pmap_devmap_table[i].pd_pa, 5819 pmap_devmap_table[i].pd_pa + 5820 pmap_devmap_table[i].pd_size - 1, 5821 pmap_devmap_table[i].pd_va); 5822 #endif 5823 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5824 pmap_devmap_table[i].pd_pa, 5825 pmap_devmap_table[i].pd_size, 5826 pmap_devmap_table[i].pd_prot, 5827 pmap_devmap_table[i].pd_cache); 5828 } 5829 } 5830 5831 const struct pmap_devmap * 5832 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5833 { 5834 uint64_t endpa; 5835 int i; 5836 5837 if (pmap_devmap_table == NULL) 5838 return (NULL); 5839 5840 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5841 5842 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5843 if (pa >= pmap_devmap_table[i].pd_pa && 5844 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5845 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5846 return (&pmap_devmap_table[i]); 5847 } 5848 5849 return (NULL); 5850 } 5851 5852 const struct pmap_devmap * 5853 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5854 { 5855 int i; 5856 5857 if (pmap_devmap_table == NULL) 5858 return (NULL); 5859 5860 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5861 if (va >= pmap_devmap_table[i].pd_va && 5862 va + size - 1 <= pmap_devmap_table[i].pd_va + 5863 pmap_devmap_table[i].pd_size - 1) 5864 return (&pmap_devmap_table[i]); 5865 } 5866 5867 return (NULL); 5868 } 5869 5870 /********************** PTE initialization routines **************************/ 5871 5872 /* 5873 * These routines are called when the CPU type is identified to set up 5874 * the PTE prototypes, cache modes, etc. 5875 * 5876 * The variables are always here, just in case modules need to reference 5877 * them (though, they shouldn't). 5878 */ 5879 5880 pt_entry_t pte_l1_s_cache_mode; 5881 pt_entry_t pte_l1_s_cache_mode_pt; 5882 pt_entry_t pte_l1_s_cache_mask; 5883 5884 pt_entry_t pte_l2_l_cache_mode; 5885 pt_entry_t pte_l2_l_cache_mode_pt; 5886 pt_entry_t pte_l2_l_cache_mask; 5887 5888 pt_entry_t pte_l2_s_cache_mode; 5889 pt_entry_t pte_l2_s_cache_mode_pt; 5890 pt_entry_t pte_l2_s_cache_mask; 5891 5892 pt_entry_t pte_l2_s_prot_u; 5893 pt_entry_t pte_l2_s_prot_w; 5894 pt_entry_t pte_l2_s_prot_mask; 5895 5896 pt_entry_t pte_l1_s_proto; 5897 pt_entry_t pte_l1_c_proto; 5898 pt_entry_t pte_l2_s_proto; 5899 5900 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5901 void (*pmap_zero_page_func)(paddr_t); 5902 5903 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5904 void 5905 pmap_pte_init_generic(void) 5906 { 5907 5908 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5909 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5910 5911 pte_l2_l_cache_mode = L2_B|L2_C; 5912 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5913 5914 pte_l2_s_cache_mode = L2_B|L2_C; 5915 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5916 5917 /* 5918 * If we have a write-through cache, set B and C. If 5919 * we have a write-back cache, then we assume setting 5920 * only C will make those pages write-through. 5921 */ 5922 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5923 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5924 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5925 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5926 } else { 5927 #if ARM_MMU_V6 > 1 5928 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5929 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5930 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5931 #else 5932 pte_l1_s_cache_mode_pt = L1_S_C; 5933 pte_l2_l_cache_mode_pt = L2_C; 5934 pte_l2_s_cache_mode_pt = L2_C; 5935 #endif 5936 } 5937 5938 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5939 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5940 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5941 5942 pte_l1_s_proto = L1_S_PROTO_generic; 5943 pte_l1_c_proto = L1_C_PROTO_generic; 5944 pte_l2_s_proto = L2_S_PROTO_generic; 5945 5946 pmap_copy_page_func = pmap_copy_page_generic; 5947 pmap_zero_page_func = pmap_zero_page_generic; 5948 } 5949 5950 #if defined(CPU_ARM8) 5951 void 5952 pmap_pte_init_arm8(void) 5953 { 5954 5955 /* 5956 * ARM8 is compatible with generic, but we need to use 5957 * the page tables uncached. 5958 */ 5959 pmap_pte_init_generic(); 5960 5961 pte_l1_s_cache_mode_pt = 0; 5962 pte_l2_l_cache_mode_pt = 0; 5963 pte_l2_s_cache_mode_pt = 0; 5964 } 5965 #endif /* CPU_ARM8 */ 5966 5967 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5968 void 5969 pmap_pte_init_arm9(void) 5970 { 5971 5972 /* 5973 * ARM9 is compatible with generic, but we want to use 5974 * write-through caching for now. 5975 */ 5976 pmap_pte_init_generic(); 5977 5978 pte_l1_s_cache_mode = L1_S_C; 5979 pte_l2_l_cache_mode = L2_C; 5980 pte_l2_s_cache_mode = L2_C; 5981 5982 pte_l1_s_cache_mode_pt = L1_S_C; 5983 pte_l2_l_cache_mode_pt = L2_C; 5984 pte_l2_s_cache_mode_pt = L2_C; 5985 } 5986 #endif /* CPU_ARM9 */ 5987 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5988 5989 #if defined(CPU_ARM10) 5990 void 5991 pmap_pte_init_arm10(void) 5992 { 5993 5994 /* 5995 * ARM10 is compatible with generic, but we want to use 5996 * write-through caching for now. 5997 */ 5998 pmap_pte_init_generic(); 5999 6000 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6001 pte_l2_l_cache_mode = L2_B | L2_C; 6002 pte_l2_s_cache_mode = L2_B | L2_C; 6003 6004 pte_l1_s_cache_mode_pt = L1_S_C; 6005 pte_l2_l_cache_mode_pt = L2_C; 6006 pte_l2_s_cache_mode_pt = L2_C; 6007 6008 } 6009 #endif /* CPU_ARM10 */ 6010 6011 #if ARM_MMU_SA1 == 1 6012 void 6013 pmap_pte_init_sa1(void) 6014 { 6015 6016 /* 6017 * The StrongARM SA-1 cache does not have a write-through 6018 * mode. So, do the generic initialization, then reset 6019 * the page table cache mode to B=1,C=1, and note that 6020 * the PTEs need to be sync'd. 6021 */ 6022 pmap_pte_init_generic(); 6023 6024 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6025 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6026 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6027 6028 pmap_needs_pte_sync = 1; 6029 } 6030 #endif /* ARM_MMU_SA1 == 1*/ 6031 6032 #if ARM_MMU_XSCALE == 1 6033 #if (ARM_NMMUS > 1) 6034 static u_int xscale_use_minidata; 6035 #endif 6036 6037 void 6038 pmap_pte_init_xscale(void) 6039 { 6040 uint32_t auxctl; 6041 int write_through = 0; 6042 6043 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6044 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6045 6046 pte_l2_l_cache_mode = L2_B|L2_C; 6047 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6048 6049 pte_l2_s_cache_mode = L2_B|L2_C; 6050 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6051 6052 pte_l1_s_cache_mode_pt = L1_S_C; 6053 pte_l2_l_cache_mode_pt = L2_C; 6054 pte_l2_s_cache_mode_pt = L2_C; 6055 6056 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6057 /* 6058 * The XScale core has an enhanced mode where writes that 6059 * miss the cache cause a cache line to be allocated. This 6060 * is significantly faster than the traditional, write-through 6061 * behavior of this case. 6062 */ 6063 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6064 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6065 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6066 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6067 6068 #ifdef XSCALE_CACHE_WRITE_THROUGH 6069 /* 6070 * Some versions of the XScale core have various bugs in 6071 * their cache units, the work-around for which is to run 6072 * the cache in write-through mode. Unfortunately, this 6073 * has a major (negative) impact on performance. So, we 6074 * go ahead and run fast-and-loose, in the hopes that we 6075 * don't line up the planets in a way that will trip the 6076 * bugs. 6077 * 6078 * However, we give you the option to be slow-but-correct. 6079 */ 6080 write_through = 1; 6081 #elif defined(XSCALE_CACHE_WRITE_BACK) 6082 /* force write back cache mode */ 6083 write_through = 0; 6084 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6085 /* 6086 * Intel PXA2[15]0 processors are known to have a bug in 6087 * write-back cache on revision 4 and earlier (stepping 6088 * A[01] and B[012]). Fixed for C0 and later. 6089 */ 6090 { 6091 uint32_t id, type; 6092 6093 id = cpufunc_id(); 6094 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6095 6096 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6097 if ((id & CPU_ID_REVISION_MASK) < 5) { 6098 /* write through for stepping A0-1 and B0-2 */ 6099 write_through = 1; 6100 } 6101 } 6102 } 6103 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6104 6105 if (write_through) { 6106 pte_l1_s_cache_mode = L1_S_C; 6107 pte_l2_l_cache_mode = L2_C; 6108 pte_l2_s_cache_mode = L2_C; 6109 } 6110 6111 #if (ARM_NMMUS > 1) 6112 xscale_use_minidata = 1; 6113 #endif 6114 6115 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6116 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6117 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6118 6119 pte_l1_s_proto = L1_S_PROTO_xscale; 6120 pte_l1_c_proto = L1_C_PROTO_xscale; 6121 pte_l2_s_proto = L2_S_PROTO_xscale; 6122 6123 pmap_copy_page_func = pmap_copy_page_xscale; 6124 pmap_zero_page_func = pmap_zero_page_xscale; 6125 6126 /* 6127 * Disable ECC protection of page table access, for now. 6128 */ 6129 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6130 auxctl &= ~XSCALE_AUXCTL_P; 6131 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6132 } 6133 6134 /* 6135 * xscale_setup_minidata: 6136 * 6137 * Set up the mini-data cache clean area. We require the 6138 * caller to allocate the right amount of physically and 6139 * virtually contiguous space. 6140 */ 6141 void 6142 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6143 { 6144 extern vaddr_t xscale_minidata_clean_addr; 6145 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6146 pd_entry_t *pde = (pd_entry_t *) l1pt; 6147 pt_entry_t *pte; 6148 vsize_t size; 6149 uint32_t auxctl; 6150 6151 xscale_minidata_clean_addr = va; 6152 6153 /* Round it to page size. */ 6154 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6155 6156 for (; size != 0; 6157 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6158 #ifndef ARM32_NEW_VM_LAYOUT 6159 pte = (pt_entry_t *) 6160 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6161 #else 6162 pte = (pt_entry_t *) kernel_pt_lookup( 6163 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6164 #endif 6165 if (pte == NULL) 6166 panic("xscale_setup_minidata: can't find L2 table for " 6167 "VA 0x%08lx", va); 6168 #ifndef ARM32_NEW_VM_LAYOUT 6169 pte[(va >> PGSHIFT) & 0x3ff] = 6170 #else 6171 pte[l2pte_index(va)] = 6172 #endif 6173 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6174 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6175 } 6176 6177 /* 6178 * Configure the mini-data cache for write-back with 6179 * read/write-allocate. 6180 * 6181 * NOTE: In order to reconfigure the mini-data cache, we must 6182 * make sure it contains no valid data! In order to do that, 6183 * we must issue a global data cache invalidate command! 6184 * 6185 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6186 * THIS IS VERY IMPORTANT! 6187 */ 6188 6189 /* Invalidate data and mini-data. */ 6190 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6191 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6192 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6193 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6194 } 6195 6196 /* 6197 * Change the PTEs for the specified kernel mappings such that they 6198 * will use the mini data cache instead of the main data cache. 6199 */ 6200 void 6201 pmap_uarea(vaddr_t va) 6202 { 6203 struct l2_bucket *l2b; 6204 pt_entry_t *ptep, *sptep, pte; 6205 vaddr_t next_bucket, eva; 6206 6207 #if (ARM_NMMUS > 1) 6208 if (xscale_use_minidata == 0) 6209 return; 6210 #endif 6211 6212 eva = va + USPACE; 6213 6214 while (va < eva) { 6215 next_bucket = L2_NEXT_BUCKET(va); 6216 if (next_bucket > eva) 6217 next_bucket = eva; 6218 6219 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6220 KDASSERT(l2b != NULL); 6221 6222 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6223 6224 while (va < next_bucket) { 6225 pte = *ptep; 6226 if (!l2pte_minidata(pte)) { 6227 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6228 cpu_tlb_flushD_SE(va); 6229 *ptep = pte & ~L2_B; 6230 } 6231 ptep++; 6232 va += PAGE_SIZE; 6233 } 6234 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6235 } 6236 cpu_cpwait(); 6237 } 6238 #endif /* ARM_MMU_XSCALE == 1 */ 6239 6240 /* 6241 * return the PA of the current L1 table, for use when handling a crash dump 6242 */ 6243 uint32_t pmap_kernel_L1_addr() 6244 { 6245 return pmap_kernel()->pm_l1->l1_physaddr; 6246 } 6247 6248 #if defined(DDB) 6249 /* 6250 * A couple of ddb-callable functions for dumping pmaps 6251 */ 6252 void pmap_dump_all(void); 6253 void pmap_dump(pmap_t); 6254 6255 void 6256 pmap_dump_all(void) 6257 { 6258 pmap_t pm; 6259 6260 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6261 if (pm == pmap_kernel()) 6262 continue; 6263 pmap_dump(pm); 6264 printf("\n"); 6265 } 6266 } 6267 6268 static pt_entry_t ncptes[64]; 6269 static void pmap_dump_ncpg(pmap_t); 6270 6271 void 6272 pmap_dump(pmap_t pm) 6273 { 6274 struct l2_dtable *l2; 6275 struct l2_bucket *l2b; 6276 pt_entry_t *ptep, pte; 6277 vaddr_t l2_va, l2b_va, va; 6278 int i, j, k, occ, rows = 0; 6279 6280 if (pm == pmap_kernel()) 6281 printf("pmap_kernel (%p): ", pm); 6282 else 6283 printf("user pmap (%p): ", pm); 6284 6285 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6286 6287 l2_va = 0; 6288 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6289 l2 = pm->pm_l2[i]; 6290 6291 if (l2 == NULL || l2->l2_occupancy == 0) 6292 continue; 6293 6294 l2b_va = l2_va; 6295 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6296 l2b = &l2->l2_bucket[j]; 6297 6298 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6299 continue; 6300 6301 ptep = l2b->l2b_kva; 6302 6303 for (k = 0; k < 256 && ptep[k] == 0; k++) 6304 ; 6305 6306 k &= ~63; 6307 occ = l2b->l2b_occupancy; 6308 va = l2b_va + (k * 4096); 6309 for (; k < 256; k++, va += 0x1000) { 6310 char ch = ' '; 6311 if ((k % 64) == 0) { 6312 if ((rows % 8) == 0) { 6313 printf( 6314 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6315 } 6316 printf("%08lx: ", va); 6317 } 6318 6319 ncptes[k & 63] = 0; 6320 pte = ptep[k]; 6321 if (pte == 0) { 6322 ch = '.'; 6323 } else { 6324 occ--; 6325 switch (pte & 0x0c) { 6326 case 0x00: 6327 ch = 'D'; /* No cache No buff */ 6328 break; 6329 case 0x04: 6330 ch = 'B'; /* No cache buff */ 6331 break; 6332 case 0x08: 6333 if (pte & 0x40) 6334 ch = 'm'; 6335 else 6336 ch = 'C'; /* Cache No buff */ 6337 break; 6338 case 0x0c: 6339 ch = 'F'; /* Cache Buff */ 6340 break; 6341 } 6342 6343 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6344 ch += 0x20; 6345 6346 if ((pte & 0xc) == 0) 6347 ncptes[k & 63] = pte; 6348 } 6349 6350 if ((k % 64) == 63) { 6351 rows++; 6352 printf("%c\n", ch); 6353 pmap_dump_ncpg(pm); 6354 if (occ == 0) 6355 break; 6356 } else 6357 printf("%c", ch); 6358 } 6359 } 6360 } 6361 } 6362 6363 static void 6364 pmap_dump_ncpg(pmap_t pm) 6365 { 6366 struct vm_page *pg; 6367 struct pv_entry *pv; 6368 int i; 6369 6370 for (i = 0; i < 63; i++) { 6371 if (ncptes[i] == 0) 6372 continue; 6373 6374 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6375 if (pg == NULL) 6376 continue; 6377 6378 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6379 VM_PAGE_TO_PHYS(pg), 6380 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 6381 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 6382 6383 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 6384 printf(" %c va 0x%08lx, flags 0x%x\n", 6385 (pm == pv->pv_pmap) ? '*' : ' ', 6386 pv->pv_va, pv->pv_flags); 6387 } 6388 } 6389 } 6390 #endif 6391 6392 #ifdef PMAP_STEAL_MEMORY 6393 void 6394 pmap_boot_pageadd(pv_addr_t *newpv) 6395 { 6396 pv_addr_t *pv, *npv; 6397 6398 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6399 if (newpv->pv_pa < pv->pv_va) { 6400 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6401 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6402 newpv->pv_size += pv->pv_size; 6403 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6404 } 6405 pv = NULL; 6406 } else { 6407 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6408 pv = npv) { 6409 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6410 KASSERT(pv->pv_pa < newpv->pv_pa); 6411 if (newpv->pv_pa > npv->pv_pa) 6412 continue; 6413 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6414 pv->pv_size += newpv->pv_size; 6415 return; 6416 } 6417 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6418 break; 6419 newpv->pv_size += npv->pv_size; 6420 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6421 SLIST_REMOVE_AFTER(newpv, pv_list); 6422 return; 6423 } 6424 } 6425 } 6426 6427 if (pv) { 6428 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6429 } else { 6430 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6431 } 6432 } 6433 6434 void 6435 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6436 pv_addr_t *rpv) 6437 { 6438 pv_addr_t *pv, **pvp; 6439 struct vm_physseg *ps; 6440 size_t i; 6441 6442 KASSERT(amount & PGOFSET); 6443 KASSERT((mask & PGOFSET) == 0); 6444 KASSERT((match & PGOFSET) == 0); 6445 KASSERT(amount != 0); 6446 6447 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6448 (pv = *pvp) != NULL; 6449 pvp = &SLIST_NEXT(pv, pv_list)) { 6450 pv_addr_t *newpv; 6451 psize_t off; 6452 /* 6453 * If this entry is too small to satify the request... 6454 */ 6455 KASSERT(pv->pv_size > 0); 6456 if (pv->pv_size < amount) 6457 continue; 6458 6459 for (off = 0; off <= mask; off += PAGE_SIZE) { 6460 if (((pv->pv_pa + off) & mask) == match 6461 && off + amount <= pv->pv_size) 6462 break; 6463 } 6464 if (off > mask) 6465 continue; 6466 6467 rpv->pv_va = pv->pv_va + off; 6468 rpv->pv_pa = pv->pv_pa + off; 6469 rpv->pv_size = amount; 6470 pv->pv_size -= amount; 6471 if (pv->pv_size == 0) { 6472 KASSERT(off == 0); 6473 KASSERT((vaddr_t) pv == rpv->pv_va); 6474 *pvp = SLIST_NEXT(pv, pv_list); 6475 } else if (off == 0) { 6476 KASSERT((vaddr_t) pv == rpv->pv_va); 6477 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6478 *newpv = *pv; 6479 newpv->pv_pa += amount; 6480 newpv->pv_va += amount; 6481 *pvp = newpv; 6482 } else if (off < pv->pv_size) { 6483 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6484 *newpv = *pv; 6485 newpv->pv_size -= off; 6486 newpv->pv_pa += off + amount; 6487 newpv->pv_va += off + amount; 6488 6489 SLIST_NEXT(pv, pv_list) = newpv; 6490 pv->pv_size = off; 6491 } else { 6492 KASSERT((vaddr_t) pv != rpv->pv_va); 6493 } 6494 memset((void *)rpv->pv_va, 0, amount); 6495 return; 6496 } 6497 6498 if (vm_nphysseg == 0) 6499 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6500 6501 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6502 (pv = *pvp) != NULL; 6503 pvp = &SLIST_NEXT(pv, pv_list)) { 6504 if (SLIST_NEXT(pv, pv_list) == NULL) 6505 break; 6506 } 6507 KASSERT(mask == 0); 6508 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6509 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6510 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6511 rpv->pv_va = pv->pv_va; 6512 rpv->pv_pa = pv->pv_pa; 6513 rpv->pv_size = amount; 6514 *pvp = NULL; 6515 pmap_map_chunk(kernel_l1pt.pv_va, 6516 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6517 ptoa(ps->avail_start), 6518 amount - pv->pv_size, 6519 VM_PROT_READ|VM_PROT_WRITE, 6520 PTE_CACHE); 6521 ps->avail_start += atop(amount - pv->pv_size); 6522 /* 6523 * If we consumed the entire physseg, remove it. 6524 */ 6525 if (ps->avail_start == ps->avail_end) { 6526 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6527 ps[0] = ps[1]; 6528 } 6529 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6530 return; 6531 } 6532 } 6533 6534 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6535 } 6536 6537 vaddr_t 6538 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6539 { 6540 pv_addr_t pv; 6541 6542 pmap_boot_pagealloc(size, 0, 0, &pv); 6543 6544 return pv.pv_va; 6545 } 6546 #endif /* PMAP_STEAL_MEMORY */ 6547 6548 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6549 { 6550 sysctl_createv(clog, 0, NULL, NULL, 6551 CTLFLAG_PERMANENT, 6552 CTLTYPE_NODE, "machdep", NULL, 6553 NULL, 0, NULL, 0, 6554 CTL_MACHDEP, CTL_EOL); 6555 6556 sysctl_createv(clog, 0, NULL, NULL, 6557 CTLFLAG_PERMANENT, 6558 CTLTYPE_INT, "kmpages", 6559 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6560 NULL, 0, &pmap_kmpages, 0, 6561 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6562 } 6563
Indexes created Thu Sep 25 02:09:54 GMT 2025