pmap.c revision 1.201
1 /* $NetBSD: pmap.c,v 1.201 2009/11/07 07:27:41 cegger Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/user.h> 202 #include <sys/pool.h> 203 #include <sys/cdefs.h> 204 #include <sys/cpu.h> 205 #include <sys/sysctl.h> 206 207 #include <uvm/uvm.h> 208 209 #include <machine/bus.h> 210 #include <machine/pmap.h> 211 #include <machine/pcb.h> 212 #include <machine/param.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.201 2009/11/07 07:27:41 cegger Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 #define PDB_EXEC 0x80000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 static struct pmap kernel_pmap_store; 259 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 260 261 /* 262 * Which pmap is currently 'live' in the cache 263 * 264 * XXXSCW: Fix for SMP ... 265 */ 266 static pmap_t pmap_recent_user; 267 268 /* 269 * Pointer to last active lwp, or NULL if it exited. 270 */ 271 struct lwp *pmap_previous_active_lwp; 272 273 /* 274 * Pool and cache that pmap structures are allocated from. 275 * We use a cache to avoid clearing the pm_l2[] array (1KB) 276 * in pmap_create(). 277 */ 278 static struct pool_cache pmap_cache; 279 static LIST_HEAD(, pmap) pmap_pmaps; 280 281 /* 282 * Pool of PV structures 283 */ 284 static struct pool pmap_pv_pool; 285 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 286 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 287 static struct pool_allocator pmap_bootstrap_pv_allocator = { 288 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 289 }; 290 291 /* 292 * Pool and cache of l2_dtable structures. 293 * We use a cache to avoid clearing the structures when they're 294 * allocated. (196 bytes) 295 */ 296 static struct pool_cache pmap_l2dtable_cache; 297 static vaddr_t pmap_kernel_l2dtable_kva; 298 299 /* 300 * Pool and cache of L2 page descriptors. 301 * We use a cache to avoid clearing the descriptor table 302 * when they're allocated. (1KB) 303 */ 304 static struct pool_cache pmap_l2ptp_cache; 305 static vaddr_t pmap_kernel_l2ptp_kva; 306 static paddr_t pmap_kernel_l2ptp_phys; 307 308 #ifdef PMAPCOUNTERS 309 #define PMAP_EVCNT_INITIALIZER(name) \ 310 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 311 312 #ifdef PMAP_CACHE_VIPT 313 static struct evcnt pmap_ev_vac_clean_one = 314 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 315 static struct evcnt pmap_ev_vac_flush_one = 316 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 317 static struct evcnt pmap_ev_vac_flush_lots = 318 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 319 static struct evcnt pmap_ev_vac_flush_lots2 = 320 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 325 326 static struct evcnt pmap_ev_vac_color_new = 327 PMAP_EVCNT_INITIALIZER("new page color"); 328 static struct evcnt pmap_ev_vac_color_reuse = 329 PMAP_EVCNT_INITIALIZER("ok first page color"); 330 static struct evcnt pmap_ev_vac_color_ok = 331 PMAP_EVCNT_INITIALIZER("ok page color"); 332 static struct evcnt pmap_ev_vac_color_blind = 333 PMAP_EVCNT_INITIALIZER("blind page color"); 334 static struct evcnt pmap_ev_vac_color_change = 335 PMAP_EVCNT_INITIALIZER("change page color"); 336 static struct evcnt pmap_ev_vac_color_erase = 337 PMAP_EVCNT_INITIALIZER("erase page color"); 338 static struct evcnt pmap_ev_vac_color_none = 339 PMAP_EVCNT_INITIALIZER("no page color"); 340 static struct evcnt pmap_ev_vac_color_restore = 341 PMAP_EVCNT_INITIALIZER("restore page color"); 342 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 351 #endif 352 353 static struct evcnt pmap_ev_mappings = 354 PMAP_EVCNT_INITIALIZER("pages mapped"); 355 static struct evcnt pmap_ev_unmappings = 356 PMAP_EVCNT_INITIALIZER("pages unmapped"); 357 static struct evcnt pmap_ev_remappings = 358 PMAP_EVCNT_INITIALIZER("pages remapped"); 359 360 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 362 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 363 364 static struct evcnt pmap_ev_kernel_mappings = 365 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 366 static struct evcnt pmap_ev_kernel_unmappings = 367 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 368 static struct evcnt pmap_ev_kernel_remappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 370 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 373 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 374 375 static struct evcnt pmap_ev_kenter_mappings = 376 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 377 static struct evcnt pmap_ev_kenter_unmappings = 378 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 379 static struct evcnt pmap_ev_kenter_remappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 381 static struct evcnt pmap_ev_pt_mappings = 382 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 383 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 387 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 388 389 #ifdef PMAP_CACHE_VIPT 390 static struct evcnt pmap_ev_exec_mappings = 391 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 392 static struct evcnt pmap_ev_exec_cached = 393 PMAP_EVCNT_INITIALIZER("exec pages cached"); 394 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 397 398 static struct evcnt pmap_ev_exec_synced = 399 PMAP_EVCNT_INITIALIZER("exec pages synced"); 400 static struct evcnt pmap_ev_exec_synced_map = 401 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 402 static struct evcnt pmap_ev_exec_synced_unmap = 403 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 404 static struct evcnt pmap_ev_exec_synced_remap = 405 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 406 static struct evcnt pmap_ev_exec_synced_clearbit = 407 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 408 static struct evcnt pmap_ev_exec_synced_kremove = 409 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 410 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 417 418 static struct evcnt pmap_ev_exec_discarded_unmap = 419 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 420 static struct evcnt pmap_ev_exec_discarded_zero = 421 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 422 static struct evcnt pmap_ev_exec_discarded_copy = 423 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 424 static struct evcnt pmap_ev_exec_discarded_page_protect = 425 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 426 static struct evcnt pmap_ev_exec_discarded_clearbit = 427 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 428 static struct evcnt pmap_ev_exec_discarded_kremove = 429 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 430 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 437 #endif /* PMAP_CACHE_VIPT */ 438 439 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 440 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 441 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 442 443 EVCNT_ATTACH_STATIC(pmap_ev_updates); 444 EVCNT_ATTACH_STATIC(pmap_ev_collects); 445 EVCNT_ATTACH_STATIC(pmap_ev_activations); 446 447 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 448 #else 449 #define PMAPCOUNT(x) ((void)0) 450 #endif 451 452 /* 453 * pmap copy/zero page, and mem(5) hook point 454 */ 455 static pt_entry_t *csrc_pte, *cdst_pte; 456 static vaddr_t csrcp, cdstp; 457 vaddr_t memhook; /* used by mem.c */ 458 kmutex_t memlock; /* used by mem.c */ 459 void *zeropage; /* used by mem.c */ 460 extern void *msgbufaddr; 461 int pmap_kmpages; 462 /* 463 * Flag to indicate if pmap_init() has done its thing 464 */ 465 bool pmap_initialized; 466 467 /* 468 * Misc. locking data structures 469 */ 470 471 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 472 static struct lock pmap_main_lock; 473 474 #define PMAP_MAP_TO_HEAD_LOCK() \ 475 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 476 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 477 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 478 #define PMAP_HEAD_TO_MAP_LOCK() \ 479 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 480 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 481 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 482 #else 483 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 484 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 485 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 486 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 487 #endif 488 489 #define pmap_acquire_pmap_lock(pm) \ 490 do { \ 491 if ((pm) != pmap_kernel()) \ 492 mutex_enter(&(pm)->pm_lock); \ 493 } while (/*CONSTCOND*/0) 494 495 #define pmap_release_pmap_lock(pm) \ 496 do { \ 497 if ((pm) != pmap_kernel()) \ 498 mutex_exit(&(pm)->pm_lock); \ 499 } while (/*CONSTCOND*/0) 500 501 502 /* 503 * Metadata for L1 translation tables. 504 */ 505 struct l1_ttable { 506 /* Entry on the L1 Table list */ 507 SLIST_ENTRY(l1_ttable) l1_link; 508 509 /* Entry on the L1 Least Recently Used list */ 510 TAILQ_ENTRY(l1_ttable) l1_lru; 511 512 /* Track how many domains are allocated from this L1 */ 513 volatile u_int l1_domain_use_count; 514 515 /* 516 * A free-list of domain numbers for this L1. 517 * We avoid using ffs() and a bitmap to track domains since ffs() 518 * is slow on ARM. 519 */ 520 u_int8_t l1_domain_first; 521 u_int8_t l1_domain_free[PMAP_DOMAINS]; 522 523 /* Physical address of this L1 page table */ 524 paddr_t l1_physaddr; 525 526 /* KVA of this L1 page table */ 527 pd_entry_t *l1_kva; 528 }; 529 530 /* 531 * Convert a virtual address into its L1 table index. That is, the 532 * index used to locate the L2 descriptor table pointer in an L1 table. 533 * This is basically used to index l1->l1_kva[]. 534 * 535 * Each L2 descriptor table represents 1MB of VA space. 536 */ 537 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 538 539 /* 540 * L1 Page Tables are tracked using a Least Recently Used list. 541 * - New L1s are allocated from the HEAD. 542 * - Freed L1s are added to the TAIl. 543 * - Recently accessed L1s (where an 'access' is some change to one of 544 * the userland pmaps which owns this L1) are moved to the TAIL. 545 */ 546 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 547 static struct simplelock l1_lru_lock; 548 549 /* 550 * A list of all L1 tables 551 */ 552 static SLIST_HEAD(, l1_ttable) l1_list; 553 554 /* 555 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 556 * 557 * This is normally 16MB worth L2 page descriptors for any given pmap. 558 * Reference counts are maintained for L2 descriptors so they can be 559 * freed when empty. 560 */ 561 struct l2_dtable { 562 /* The number of L2 page descriptors allocated to this l2_dtable */ 563 u_int l2_occupancy; 564 565 /* List of L2 page descriptors */ 566 struct l2_bucket { 567 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 568 paddr_t l2b_phys; /* Physical address of same */ 569 u_short l2b_l1idx; /* This L2 table's L1 index */ 570 u_short l2b_occupancy; /* How many active descriptors */ 571 } l2_bucket[L2_BUCKET_SIZE]; 572 }; 573 574 /* 575 * Given an L1 table index, calculate the corresponding l2_dtable index 576 * and bucket index within the l2_dtable. 577 */ 578 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 579 (L2_SIZE - 1)) 580 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 581 582 /* 583 * Given a virtual address, this macro returns the 584 * virtual address required to drop into the next L2 bucket. 585 */ 586 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 587 588 /* 589 * L2 allocation. 590 */ 591 #define pmap_alloc_l2_dtable() \ 592 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 593 #define pmap_free_l2_dtable(l2) \ 594 pool_cache_put(&pmap_l2dtable_cache, (l2)) 595 #define pmap_alloc_l2_ptp(pap) \ 596 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 597 PR_NOWAIT, (pap))) 598 599 /* 600 * We try to map the page tables write-through, if possible. However, not 601 * all CPUs have a write-through cache mode, so on those we have to sync 602 * the cache when we frob page tables. 603 * 604 * We try to evaluate this at compile time, if possible. However, it's 605 * not always possible to do that, hence this run-time var. 606 */ 607 int pmap_needs_pte_sync; 608 609 /* 610 * Real definition of pv_entry. 611 */ 612 struct pv_entry { 613 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 614 pmap_t pv_pmap; /* pmap where mapping lies */ 615 vaddr_t pv_va; /* virtual address for mapping */ 616 u_int pv_flags; /* flags */ 617 }; 618 619 /* 620 * Macro to determine if a mapping might be resident in the 621 * instruction cache and/or TLB 622 */ 623 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 624 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 625 626 /* 627 * Macro to determine if a mapping might be resident in the 628 * data cache and/or TLB 629 */ 630 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 631 632 /* 633 * Local prototypes 634 */ 635 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 636 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 637 pt_entry_t **); 638 static bool pmap_is_current(pmap_t); 639 static bool pmap_is_cached(pmap_t); 640 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 641 pmap_t, vaddr_t, u_int); 642 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 643 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t); 644 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 645 u_int, u_int); 646 647 static void pmap_pinit(pmap_t); 648 static int pmap_pmap_ctor(void *, void *, int); 649 650 static void pmap_alloc_l1(pmap_t); 651 static void pmap_free_l1(pmap_t); 652 static void pmap_use_l1(pmap_t); 653 654 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 655 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 656 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 657 static int pmap_l2ptp_ctor(void *, void *, int); 658 static int pmap_l2dtable_ctor(void *, void *, int); 659 660 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 661 #ifdef PMAP_CACHE_VIVT 662 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 663 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 664 #endif 665 666 static void pmap_clearbit(struct vm_page *, u_int); 667 #ifdef PMAP_CACHE_VIVT 668 static int pmap_clean_page(struct pv_entry *, bool); 669 #endif 670 #ifdef PMAP_CACHE_VIPT 671 static void pmap_syncicache_page(struct vm_page *); 672 enum pmap_flush_op { 673 PMAP_FLUSH_PRIMARY, 674 PMAP_FLUSH_SECONDARY, 675 PMAP_CLEAN_PRIMARY 676 }; 677 static void pmap_flush_page(struct vm_page *, enum pmap_flush_op); 678 #endif 679 static void pmap_page_remove(struct vm_page *); 680 681 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 682 static vaddr_t kernel_pt_lookup(paddr_t); 683 684 685 /* 686 * External function prototypes 687 */ 688 extern void bzero_page(vaddr_t); 689 extern void bcopy_page(vaddr_t, vaddr_t); 690 691 /* 692 * Misc variables 693 */ 694 vaddr_t virtual_avail; 695 vaddr_t virtual_end; 696 vaddr_t pmap_curmaxkvaddr; 697 698 paddr_t avail_start; 699 paddr_t avail_end; 700 701 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 702 pv_addr_t kernelpages; 703 pv_addr_t kernel_l1pt; 704 pv_addr_t systempage; 705 706 /* Function to set the debug level of the pmap code */ 707 708 #ifdef PMAP_DEBUG 709 void 710 pmap_debug(int level) 711 { 712 pmap_debug_level = level; 713 printf("pmap_debug: level=%d\n", pmap_debug_level); 714 } 715 #endif /* PMAP_DEBUG */ 716 717 /* 718 * A bunch of routines to conditionally flush the caches/TLB depending 719 * on whether the specified pmap actually needs to be flushed at any 720 * given time. 721 */ 722 static inline void 723 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 724 { 725 726 if (pm->pm_cstate.cs_tlb_id) 727 cpu_tlb_flushID_SE(va); 728 } 729 730 static inline void 731 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 732 { 733 734 if (pm->pm_cstate.cs_tlb_d) 735 cpu_tlb_flushD_SE(va); 736 } 737 738 static inline void 739 pmap_tlb_flushID(pmap_t pm) 740 { 741 742 if (pm->pm_cstate.cs_tlb_id) { 743 cpu_tlb_flushID(); 744 pm->pm_cstate.cs_tlb = 0; 745 } 746 } 747 748 static inline void 749 pmap_tlb_flushD(pmap_t pm) 750 { 751 752 if (pm->pm_cstate.cs_tlb_d) { 753 cpu_tlb_flushD(); 754 pm->pm_cstate.cs_tlb_d = 0; 755 } 756 } 757 758 #ifdef PMAP_CACHE_VIVT 759 static inline void 760 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 761 { 762 if (pm->pm_cstate.cs_cache_id) { 763 cpu_idcache_wbinv_range(va, len); 764 } 765 } 766 767 static inline void 768 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 769 bool do_inv, bool rd_only) 770 { 771 772 if (pm->pm_cstate.cs_cache_d) { 773 if (do_inv) { 774 if (rd_only) 775 cpu_dcache_inv_range(va, len); 776 else 777 cpu_dcache_wbinv_range(va, len); 778 } else 779 if (!rd_only) 780 cpu_dcache_wb_range(va, len); 781 } 782 } 783 784 static inline void 785 pmap_idcache_wbinv_all(pmap_t pm) 786 { 787 if (pm->pm_cstate.cs_cache_id) { 788 cpu_idcache_wbinv_all(); 789 pm->pm_cstate.cs_cache = 0; 790 } 791 } 792 793 static inline void 794 pmap_dcache_wbinv_all(pmap_t pm) 795 { 796 if (pm->pm_cstate.cs_cache_d) { 797 cpu_dcache_wbinv_all(); 798 pm->pm_cstate.cs_cache_d = 0; 799 } 800 } 801 #endif /* PMAP_CACHE_VIVT */ 802 803 static inline bool 804 pmap_is_current(pmap_t pm) 805 { 806 807 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 808 return true; 809 810 return false; 811 } 812 813 static inline bool 814 pmap_is_cached(pmap_t pm) 815 { 816 817 if (pm == pmap_kernel() || pmap_recent_user == NULL || 818 pmap_recent_user == pm) 819 return (true); 820 821 return false; 822 } 823 824 /* 825 * PTE_SYNC_CURRENT: 826 * 827 * Make sure the pte is written out to RAM. 828 * We need to do this for one of two cases: 829 * - We're dealing with the kernel pmap 830 * - There is no pmap active in the cache/tlb. 831 * - The specified pmap is 'active' in the cache/tlb. 832 */ 833 #ifdef PMAP_INCLUDE_PTE_SYNC 834 #define PTE_SYNC_CURRENT(pm, ptep) \ 835 do { \ 836 if (PMAP_NEEDS_PTE_SYNC && \ 837 pmap_is_cached(pm)) \ 838 PTE_SYNC(ptep); \ 839 } while (/*CONSTCOND*/0) 840 #else 841 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 842 #endif 843 844 /* 845 * main pv_entry manipulation functions: 846 * pmap_enter_pv: enter a mapping onto a vm_page list 847 * pmap_remove_pv: remove a mappiing from a vm_page list 848 * 849 * NOTE: pmap_enter_pv expects to lock the pvh itself 850 * pmap_remove_pv expects te caller to lock the pvh before calling 851 */ 852 853 /* 854 * pmap_enter_pv: enter a mapping onto a vm_page lst 855 * 856 * => caller should hold the proper lock on pmap_main_lock 857 * => caller should have pmap locked 858 * => we will gain the lock on the vm_page and allocate the new pv_entry 859 * => caller should adjust ptp's wire_count before calling 860 * => caller should not adjust pmap's wire_count 861 */ 862 static void 863 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 864 vaddr_t va, u_int flags) 865 { 866 struct pv_entry **pvp; 867 868 NPDEBUG(PDB_PVDUMP, 869 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 870 871 pve->pv_pmap = pm; 872 pve->pv_va = va; 873 pve->pv_flags = flags; 874 875 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 876 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 877 #ifdef PMAP_CACHE_VIPT 878 /* 879 * Insert unmanaged entries, writeable first, at the head of 880 * the pv list. 881 */ 882 if (__predict_true((flags & PVF_KENTRY) == 0)) { 883 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 884 pvp = &SLIST_NEXT(*pvp, pv_link); 885 } else if ((flags & PVF_WRITE) == 0) { 886 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 887 pvp = &SLIST_NEXT(*pvp, pv_link); 888 } 889 #endif 890 SLIST_NEXT(pve, pv_link) = *pvp; /* add to ... */ 891 *pvp = pve; /* ... locked list */ 892 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 893 #ifdef PMAP_CACHE_VIPT 894 if ((pve->pv_flags & PVF_KWRITE) == PVF_KWRITE) 895 pg->mdpage.pvh_attrs |= PVF_KMOD; 896 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 897 pg->mdpage.pvh_attrs |= PVF_DIRTY; 898 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 899 #endif 900 if (pm == pmap_kernel()) { 901 PMAPCOUNT(kernel_mappings); 902 if (flags & PVF_WRITE) 903 pg->mdpage.krw_mappings++; 904 else 905 pg->mdpage.kro_mappings++; 906 } else 907 if (flags & PVF_WRITE) 908 pg->mdpage.urw_mappings++; 909 else 910 pg->mdpage.uro_mappings++; 911 912 #ifdef PMAP_CACHE_VIPT 913 /* 914 * If this is an exec mapping and its the first exec mapping 915 * for this page, make sure to sync the I-cache. 916 */ 917 if (PV_IS_EXEC_P(flags)) { 918 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 919 pmap_syncicache_page(pg); 920 PMAPCOUNT(exec_synced_map); 921 } 922 PMAPCOUNT(exec_mappings); 923 } 924 #endif 925 926 PMAPCOUNT(mappings); 927 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 928 929 if (pve->pv_flags & PVF_WIRED) 930 ++pm->pm_stats.wired_count; 931 } 932 933 /* 934 * 935 * pmap_find_pv: Find a pv entry 936 * 937 * => caller should hold lock on vm_page 938 */ 939 static inline struct pv_entry * 940 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 941 { 942 struct pv_entry *pv; 943 944 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 945 if (pm == pv->pv_pmap && va == pv->pv_va) 946 break; 947 } 948 949 return (pv); 950 } 951 952 /* 953 * pmap_remove_pv: try to remove a mapping from a pv_list 954 * 955 * => caller should hold proper lock on pmap_main_lock 956 * => pmap should be locked 957 * => caller should hold lock on vm_page [so that attrs can be adjusted] 958 * => caller should adjust ptp's wire_count and free PTP if needed 959 * => caller should NOT adjust pmap's wire_count 960 * => we return the removed pve 961 */ 962 static struct pv_entry * 963 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 964 { 965 struct pv_entry *pve, **prevptr; 966 967 NPDEBUG(PDB_PVDUMP, 968 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 969 970 prevptr = &SLIST_FIRST(&pg->mdpage.pvh_list); /* prev pv_entry ptr */ 971 pve = *prevptr; 972 973 while (pve) { 974 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 975 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 976 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 977 if (pve->pv_flags & PVF_WIRED) { 978 --pm->pm_stats.wired_count; 979 } 980 *prevptr = SLIST_NEXT(pve, pv_link); /* remove it! */ 981 if (pm == pmap_kernel()) { 982 PMAPCOUNT(kernel_unmappings); 983 if (pve->pv_flags & PVF_WRITE) 984 pg->mdpage.krw_mappings--; 985 else 986 pg->mdpage.kro_mappings--; 987 } else 988 if (pve->pv_flags & PVF_WRITE) 989 pg->mdpage.urw_mappings--; 990 else 991 pg->mdpage.uro_mappings--; 992 993 PMAPCOUNT(unmappings); 994 #ifdef PMAP_CACHE_VIPT 995 if (!(pve->pv_flags & PVF_WRITE)) 996 break; 997 /* 998 * If this page has had an exec mapping, then if 999 * this was the last mapping, discard the contents, 1000 * otherwise sync the i-cache for this page. 1001 */ 1002 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 1003 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 1004 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 1005 PMAPCOUNT(exec_discarded_unmap); 1006 } else { 1007 pmap_syncicache_page(pg); 1008 PMAPCOUNT(exec_synced_unmap); 1009 } 1010 } 1011 #endif /* PMAP_CACHE_VIPT */ 1012 break; 1013 } 1014 prevptr = &SLIST_NEXT(pve, pv_link); /* previous pointer */ 1015 pve = *prevptr; /* advance */ 1016 } 1017 1018 #ifdef PMAP_CACHE_VIPT 1019 /* 1020 * If we no longer have a WRITEABLE KENTRY at the head of list, 1021 * clear the KMOD attribute from the page. 1022 */ 1023 if (SLIST_FIRST(&pg->mdpage.pvh_list) == NULL 1024 || (SLIST_FIRST(&pg->mdpage.pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1025 pg->mdpage.pvh_attrs &= ~PVF_KMOD; 1026 1027 /* 1028 * If this was a writeable page and there are no more writeable 1029 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1030 * the contents to memory. 1031 */ 1032 if (pg->mdpage.krw_mappings + pg->mdpage.urw_mappings == 0) 1033 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1034 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1035 #endif /* PMAP_CACHE_VIPT */ 1036 1037 return(pve); /* return removed pve */ 1038 } 1039 1040 /* 1041 * 1042 * pmap_modify_pv: Update pv flags 1043 * 1044 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1045 * => caller should NOT adjust pmap's wire_count 1046 * => caller must call pmap_vac_me_harder() if writable status of a page 1047 * may have changed. 1048 * => we return the old flags 1049 * 1050 * Modify a physical-virtual mapping in the pv table 1051 */ 1052 static u_int 1053 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 1054 u_int clr_mask, u_int set_mask) 1055 { 1056 struct pv_entry *npv; 1057 u_int flags, oflags; 1058 1059 KASSERT((clr_mask & PVF_KENTRY) == 0); 1060 KASSERT((set_mask & PVF_KENTRY) == 0); 1061 1062 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1063 return (0); 1064 1065 NPDEBUG(PDB_PVDUMP, 1066 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 1067 1068 /* 1069 * There is at least one VA mapping this page. 1070 */ 1071 1072 if (clr_mask & (PVF_REF | PVF_MOD)) { 1073 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1074 #ifdef PMAP_CACHE_VIPT 1075 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1076 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1077 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1078 #endif 1079 } 1080 1081 oflags = npv->pv_flags; 1082 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1083 1084 if ((flags ^ oflags) & PVF_WIRED) { 1085 if (flags & PVF_WIRED) 1086 ++pm->pm_stats.wired_count; 1087 else 1088 --pm->pm_stats.wired_count; 1089 } 1090 1091 if ((flags ^ oflags) & PVF_WRITE) { 1092 if (pm == pmap_kernel()) { 1093 if (flags & PVF_WRITE) { 1094 pg->mdpage.krw_mappings++; 1095 pg->mdpage.kro_mappings--; 1096 } else { 1097 pg->mdpage.kro_mappings++; 1098 pg->mdpage.krw_mappings--; 1099 } 1100 } else 1101 if (flags & PVF_WRITE) { 1102 pg->mdpage.urw_mappings++; 1103 pg->mdpage.uro_mappings--; 1104 } else { 1105 pg->mdpage.uro_mappings++; 1106 pg->mdpage.urw_mappings--; 1107 } 1108 } 1109 #ifdef PMAP_CACHE_VIPT 1110 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 1111 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1112 /* 1113 * We have two cases here: the first is from enter_pv (new exec 1114 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1115 * Since in latter, pmap_enter_pv won't do anything, we just have 1116 * to do what pmap_remove_pv would do. 1117 */ 1118 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1119 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1120 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1121 pmap_syncicache_page(pg); 1122 PMAPCOUNT(exec_synced_remap); 1123 } 1124 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1125 #endif 1126 1127 PMAPCOUNT(remappings); 1128 1129 return (oflags); 1130 } 1131 1132 /* 1133 * Allocate an L1 translation table for the specified pmap. 1134 * This is called at pmap creation time. 1135 */ 1136 static void 1137 pmap_alloc_l1(pmap_t pm) 1138 { 1139 struct l1_ttable *l1; 1140 u_int8_t domain; 1141 1142 /* 1143 * Remove the L1 at the head of the LRU list 1144 */ 1145 simple_lock(&l1_lru_lock); 1146 l1 = TAILQ_FIRST(&l1_lru_list); 1147 KDASSERT(l1 != NULL); 1148 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1149 1150 /* 1151 * Pick the first available domain number, and update 1152 * the link to the next number. 1153 */ 1154 domain = l1->l1_domain_first; 1155 l1->l1_domain_first = l1->l1_domain_free[domain]; 1156 1157 /* 1158 * If there are still free domain numbers in this L1, 1159 * put it back on the TAIL of the LRU list. 1160 */ 1161 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1162 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1163 1164 simple_unlock(&l1_lru_lock); 1165 1166 /* 1167 * Fix up the relevant bits in the pmap structure 1168 */ 1169 pm->pm_l1 = l1; 1170 pm->pm_domain = domain; 1171 } 1172 1173 /* 1174 * Free an L1 translation table. 1175 * This is called at pmap destruction time. 1176 */ 1177 static void 1178 pmap_free_l1(pmap_t pm) 1179 { 1180 struct l1_ttable *l1 = pm->pm_l1; 1181 1182 simple_lock(&l1_lru_lock); 1183 1184 /* 1185 * If this L1 is currently on the LRU list, remove it. 1186 */ 1187 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1188 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1189 1190 /* 1191 * Free up the domain number which was allocated to the pmap 1192 */ 1193 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1194 l1->l1_domain_first = pm->pm_domain; 1195 l1->l1_domain_use_count--; 1196 1197 /* 1198 * The L1 now must have at least 1 free domain, so add 1199 * it back to the LRU list. If the use count is zero, 1200 * put it at the head of the list, otherwise it goes 1201 * to the tail. 1202 */ 1203 if (l1->l1_domain_use_count == 0) 1204 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1205 else 1206 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1207 1208 simple_unlock(&l1_lru_lock); 1209 } 1210 1211 static inline void 1212 pmap_use_l1(pmap_t pm) 1213 { 1214 struct l1_ttable *l1; 1215 1216 /* 1217 * Do nothing if we're in interrupt context. 1218 * Access to an L1 by the kernel pmap must not affect 1219 * the LRU list. 1220 */ 1221 if (cpu_intr_p() || pm == pmap_kernel()) 1222 return; 1223 1224 l1 = pm->pm_l1; 1225 1226 /* 1227 * If the L1 is not currently on the LRU list, just return 1228 */ 1229 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1230 return; 1231 1232 simple_lock(&l1_lru_lock); 1233 1234 /* 1235 * Check the use count again, now that we've acquired the lock 1236 */ 1237 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1238 simple_unlock(&l1_lru_lock); 1239 return; 1240 } 1241 1242 /* 1243 * Move the L1 to the back of the LRU list 1244 */ 1245 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1246 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1247 1248 simple_unlock(&l1_lru_lock); 1249 } 1250 1251 /* 1252 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1253 * 1254 * Free an L2 descriptor table. 1255 */ 1256 static inline void 1257 #ifndef PMAP_INCLUDE_PTE_SYNC 1258 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1259 #else 1260 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1261 #endif 1262 { 1263 #ifdef PMAP_INCLUDE_PTE_SYNC 1264 #ifdef PMAP_CACHE_VIVT 1265 /* 1266 * Note: With a write-back cache, we may need to sync this 1267 * L2 table before re-using it. 1268 * This is because it may have belonged to a non-current 1269 * pmap, in which case the cache syncs would have been 1270 * skipped for the pages that were being unmapped. If the 1271 * L2 table were then to be immediately re-allocated to 1272 * the *current* pmap, it may well contain stale mappings 1273 * which have not yet been cleared by a cache write-back 1274 * and so would still be visible to the mmu. 1275 */ 1276 if (need_sync) 1277 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1278 #endif /* PMAP_CACHE_VIVT */ 1279 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1280 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1281 } 1282 1283 /* 1284 * Returns a pointer to the L2 bucket associated with the specified pmap 1285 * and VA, or NULL if no L2 bucket exists for the address. 1286 */ 1287 static inline struct l2_bucket * 1288 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1289 { 1290 struct l2_dtable *l2; 1291 struct l2_bucket *l2b; 1292 u_short l1idx; 1293 1294 l1idx = L1_IDX(va); 1295 1296 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1297 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1298 return (NULL); 1299 1300 return (l2b); 1301 } 1302 1303 /* 1304 * Returns a pointer to the L2 bucket associated with the specified pmap 1305 * and VA. 1306 * 1307 * If no L2 bucket exists, perform the necessary allocations to put an L2 1308 * bucket/page table in place. 1309 * 1310 * Note that if a new L2 bucket/page was allocated, the caller *must* 1311 * increment the bucket occupancy counter appropriately *before* 1312 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1313 * the bucket/page in the meantime. 1314 */ 1315 static struct l2_bucket * 1316 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1317 { 1318 struct l2_dtable *l2; 1319 struct l2_bucket *l2b; 1320 u_short l1idx; 1321 1322 l1idx = L1_IDX(va); 1323 1324 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1325 /* 1326 * No mapping at this address, as there is 1327 * no entry in the L1 table. 1328 * Need to allocate a new l2_dtable. 1329 */ 1330 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1331 return (NULL); 1332 1333 /* 1334 * Link it into the parent pmap 1335 */ 1336 pm->pm_l2[L2_IDX(l1idx)] = l2; 1337 } 1338 1339 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1340 1341 /* 1342 * Fetch pointer to the L2 page table associated with the address. 1343 */ 1344 if (l2b->l2b_kva == NULL) { 1345 pt_entry_t *ptep; 1346 1347 /* 1348 * No L2 page table has been allocated. Chances are, this 1349 * is because we just allocated the l2_dtable, above. 1350 */ 1351 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1352 /* 1353 * Oops, no more L2 page tables available at this 1354 * time. We may need to deallocate the l2_dtable 1355 * if we allocated a new one above. 1356 */ 1357 if (l2->l2_occupancy == 0) { 1358 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1359 pmap_free_l2_dtable(l2); 1360 } 1361 return (NULL); 1362 } 1363 1364 l2->l2_occupancy++; 1365 l2b->l2b_kva = ptep; 1366 l2b->l2b_l1idx = l1idx; 1367 } 1368 1369 return (l2b); 1370 } 1371 1372 /* 1373 * One or more mappings in the specified L2 descriptor table have just been 1374 * invalidated. 1375 * 1376 * Garbage collect the metadata and descriptor table itself if necessary. 1377 * 1378 * The pmap lock must be acquired when this is called (not necessary 1379 * for the kernel pmap). 1380 */ 1381 static void 1382 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1383 { 1384 struct l2_dtable *l2; 1385 pd_entry_t *pl1pd, l1pd; 1386 pt_entry_t *ptep; 1387 u_short l1idx; 1388 1389 KDASSERT(count <= l2b->l2b_occupancy); 1390 1391 /* 1392 * Update the bucket's reference count according to how many 1393 * PTEs the caller has just invalidated. 1394 */ 1395 l2b->l2b_occupancy -= count; 1396 1397 /* 1398 * Note: 1399 * 1400 * Level 2 page tables allocated to the kernel pmap are never freed 1401 * as that would require checking all Level 1 page tables and 1402 * removing any references to the Level 2 page table. See also the 1403 * comment elsewhere about never freeing bootstrap L2 descriptors. 1404 * 1405 * We make do with just invalidating the mapping in the L2 table. 1406 * 1407 * This isn't really a big deal in practice and, in fact, leads 1408 * to a performance win over time as we don't need to continually 1409 * alloc/free. 1410 */ 1411 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1412 return; 1413 1414 /* 1415 * There are no more valid mappings in this level 2 page table. 1416 * Go ahead and NULL-out the pointer in the bucket, then 1417 * free the page table. 1418 */ 1419 l1idx = l2b->l2b_l1idx; 1420 ptep = l2b->l2b_kva; 1421 l2b->l2b_kva = NULL; 1422 1423 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1424 1425 /* 1426 * If the L1 slot matches the pmap's domain 1427 * number, then invalidate it. 1428 */ 1429 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1430 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1431 *pl1pd = 0; 1432 PTE_SYNC(pl1pd); 1433 } 1434 1435 /* 1436 * Release the L2 descriptor table back to the pool cache. 1437 */ 1438 #ifndef PMAP_INCLUDE_PTE_SYNC 1439 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1440 #else 1441 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1442 #endif 1443 1444 /* 1445 * Update the reference count in the associated l2_dtable 1446 */ 1447 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1448 if (--l2->l2_occupancy > 0) 1449 return; 1450 1451 /* 1452 * There are no more valid mappings in any of the Level 1 1453 * slots managed by this l2_dtable. Go ahead and NULL-out 1454 * the pointer in the parent pmap and free the l2_dtable. 1455 */ 1456 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1457 pmap_free_l2_dtable(l2); 1458 } 1459 1460 /* 1461 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1462 * structures. 1463 */ 1464 static int 1465 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1466 { 1467 #ifndef PMAP_INCLUDE_PTE_SYNC 1468 struct l2_bucket *l2b; 1469 pt_entry_t *ptep, pte; 1470 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1471 1472 /* 1473 * The mappings for these page tables were initially made using 1474 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1475 * mode will not be right for page table mappings. To avoid 1476 * polluting the pmap_kenter_pa() code with a special case for 1477 * page tables, we simply fix up the cache-mode here if it's not 1478 * correct. 1479 */ 1480 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1481 KDASSERT(l2b != NULL); 1482 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1483 pte = *ptep; 1484 1485 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1486 /* 1487 * Page tables must have the cache-mode set to Write-Thru. 1488 */ 1489 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1490 PTE_SYNC(ptep); 1491 cpu_tlb_flushD_SE(va); 1492 cpu_cpwait(); 1493 } 1494 #endif 1495 1496 memset(v, 0, L2_TABLE_SIZE_REAL); 1497 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1498 return (0); 1499 } 1500 1501 static int 1502 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1503 { 1504 1505 memset(v, 0, sizeof(struct l2_dtable)); 1506 return (0); 1507 } 1508 1509 static int 1510 pmap_pmap_ctor(void *arg, void *v, int flags) 1511 { 1512 1513 memset(v, 0, sizeof(struct pmap)); 1514 return (0); 1515 } 1516 1517 static void 1518 pmap_pinit(pmap_t pm) 1519 { 1520 struct l2_bucket *l2b; 1521 1522 if (vector_page < KERNEL_BASE) { 1523 /* 1524 * Map the vector page. 1525 */ 1526 pmap_enter(pm, vector_page, systempage.pv_pa, 1527 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1528 pmap_update(pm); 1529 1530 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1531 l2b = pmap_get_l2_bucket(pm, vector_page); 1532 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1533 L1_C_DOM(pm->pm_domain); 1534 } else 1535 pm->pm_pl1vec = NULL; 1536 } 1537 1538 #ifdef PMAP_CACHE_VIVT 1539 /* 1540 * Since we have a virtually indexed cache, we may need to inhibit caching if 1541 * there is more than one mapping and at least one of them is writable. 1542 * Since we purge the cache on every context switch, we only need to check for 1543 * other mappings within the same pmap, or kernel_pmap. 1544 * This function is also called when a page is unmapped, to possibly reenable 1545 * caching on any remaining mappings. 1546 * 1547 * The code implements the following logic, where: 1548 * 1549 * KW = # of kernel read/write pages 1550 * KR = # of kernel read only pages 1551 * UW = # of user read/write pages 1552 * UR = # of user read only pages 1553 * 1554 * KC = kernel mapping is cacheable 1555 * UC = user mapping is cacheable 1556 * 1557 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1558 * +--------------------------------------------- 1559 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1560 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1561 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1562 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1563 */ 1564 1565 static const int pmap_vac_flags[4][4] = { 1566 {-1, 0, 0, PVF_KNC}, 1567 {0, 0, PVF_NC, PVF_NC}, 1568 {0, PVF_NC, PVF_NC, PVF_NC}, 1569 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1570 }; 1571 1572 static inline int 1573 pmap_get_vac_flags(const struct vm_page *pg) 1574 { 1575 int kidx, uidx; 1576 1577 kidx = 0; 1578 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1579 kidx |= 1; 1580 if (pg->mdpage.krw_mappings) 1581 kidx |= 2; 1582 1583 uidx = 0; 1584 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1585 uidx |= 1; 1586 if (pg->mdpage.urw_mappings) 1587 uidx |= 2; 1588 1589 return (pmap_vac_flags[uidx][kidx]); 1590 } 1591 1592 static inline void 1593 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1594 { 1595 int nattr; 1596 1597 nattr = pmap_get_vac_flags(pg); 1598 1599 if (nattr < 0) { 1600 pg->mdpage.pvh_attrs &= ~PVF_NC; 1601 return; 1602 } 1603 1604 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1605 return; 1606 1607 if (pm == pmap_kernel()) 1608 pmap_vac_me_kpmap(pg, pm, va); 1609 else 1610 pmap_vac_me_user(pg, pm, va); 1611 1612 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1613 } 1614 1615 static void 1616 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1617 { 1618 u_int u_cacheable, u_entries; 1619 struct pv_entry *pv; 1620 pmap_t last_pmap = pm; 1621 1622 /* 1623 * Pass one, see if there are both kernel and user pmaps for 1624 * this page. Calculate whether there are user-writable or 1625 * kernel-writable pages. 1626 */ 1627 u_cacheable = 0; 1628 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1629 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1630 u_cacheable++; 1631 } 1632 1633 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1634 1635 /* 1636 * We know we have just been updating a kernel entry, so if 1637 * all user pages are already cacheable, then there is nothing 1638 * further to do. 1639 */ 1640 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1641 return; 1642 1643 if (u_entries) { 1644 /* 1645 * Scan over the list again, for each entry, if it 1646 * might not be set correctly, call pmap_vac_me_user 1647 * to recalculate the settings. 1648 */ 1649 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1650 /* 1651 * We know kernel mappings will get set 1652 * correctly in other calls. We also know 1653 * that if the pmap is the same as last_pmap 1654 * then we've just handled this entry. 1655 */ 1656 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1657 continue; 1658 1659 /* 1660 * If there are kernel entries and this page 1661 * is writable but non-cacheable, then we can 1662 * skip this entry also. 1663 */ 1664 if (pg->mdpage.k_mappings && 1665 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1666 (PVF_NC | PVF_WRITE)) 1667 continue; 1668 1669 /* 1670 * Similarly if there are no kernel-writable 1671 * entries and the page is already 1672 * read-only/cacheable. 1673 */ 1674 if (pg->mdpage.krw_mappings == 0 && 1675 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1676 continue; 1677 1678 /* 1679 * For some of the remaining cases, we know 1680 * that we must recalculate, but for others we 1681 * can't tell if they are correct or not, so 1682 * we recalculate anyway. 1683 */ 1684 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1685 } 1686 1687 if (pg->mdpage.k_mappings == 0) 1688 return; 1689 } 1690 1691 pmap_vac_me_user(pg, pm, va); 1692 } 1693 1694 static void 1695 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1696 { 1697 pmap_t kpmap = pmap_kernel(); 1698 struct pv_entry *pv, *npv = NULL; 1699 struct l2_bucket *l2b; 1700 pt_entry_t *ptep, pte; 1701 u_int entries = 0; 1702 u_int writable = 0; 1703 u_int cacheable_entries = 0; 1704 u_int kern_cacheable = 0; 1705 u_int other_writable = 0; 1706 1707 /* 1708 * Count mappings and writable mappings in this pmap. 1709 * Include kernel mappings as part of our own. 1710 * Keep a pointer to the first one. 1711 */ 1712 npv = NULL; 1713 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1714 /* Count mappings in the same pmap */ 1715 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1716 if (entries++ == 0) 1717 npv = pv; 1718 1719 /* Cacheable mappings */ 1720 if ((pv->pv_flags & PVF_NC) == 0) { 1721 cacheable_entries++; 1722 if (kpmap == pv->pv_pmap) 1723 kern_cacheable++; 1724 } 1725 1726 /* Writable mappings */ 1727 if (pv->pv_flags & PVF_WRITE) 1728 ++writable; 1729 } else 1730 if (pv->pv_flags & PVF_WRITE) 1731 other_writable = 1; 1732 } 1733 1734 /* 1735 * Enable or disable caching as necessary. 1736 * Note: the first entry might be part of the kernel pmap, 1737 * so we can't assume this is indicative of the state of the 1738 * other (maybe non-kpmap) entries. 1739 */ 1740 if ((entries > 1 && writable) || 1741 (entries > 0 && pm == kpmap && other_writable)) { 1742 if (cacheable_entries == 0) 1743 return; 1744 1745 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1746 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1747 (pv->pv_flags & PVF_NC)) 1748 continue; 1749 1750 pv->pv_flags |= PVF_NC; 1751 1752 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1753 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1754 pte = *ptep & ~L2_S_CACHE_MASK; 1755 1756 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1757 l2pte_valid(pte)) { 1758 if (PV_BEEN_EXECD(pv->pv_flags)) { 1759 #ifdef PMAP_CACHE_VIVT 1760 pmap_idcache_wbinv_range(pv->pv_pmap, 1761 pv->pv_va, PAGE_SIZE); 1762 #endif 1763 pmap_tlb_flushID_SE(pv->pv_pmap, 1764 pv->pv_va); 1765 } else 1766 if (PV_BEEN_REFD(pv->pv_flags)) { 1767 #ifdef PMAP_CACHE_VIVT 1768 pmap_dcache_wb_range(pv->pv_pmap, 1769 pv->pv_va, PAGE_SIZE, true, 1770 (pv->pv_flags & PVF_WRITE) == 0); 1771 #endif 1772 pmap_tlb_flushD_SE(pv->pv_pmap, 1773 pv->pv_va); 1774 } 1775 } 1776 1777 *ptep = pte; 1778 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1779 } 1780 cpu_cpwait(); 1781 } else 1782 if (entries > cacheable_entries) { 1783 /* 1784 * Turn cacheing back on for some pages. If it is a kernel 1785 * page, only do so if there are no other writable pages. 1786 */ 1787 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1788 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1789 (kpmap != pv->pv_pmap || other_writable))) 1790 continue; 1791 1792 pv->pv_flags &= ~PVF_NC; 1793 1794 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1795 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1796 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1797 1798 if (l2pte_valid(pte)) { 1799 if (PV_BEEN_EXECD(pv->pv_flags)) { 1800 pmap_tlb_flushID_SE(pv->pv_pmap, 1801 pv->pv_va); 1802 } else 1803 if (PV_BEEN_REFD(pv->pv_flags)) { 1804 pmap_tlb_flushD_SE(pv->pv_pmap, 1805 pv->pv_va); 1806 } 1807 } 1808 1809 *ptep = pte; 1810 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1811 } 1812 } 1813 } 1814 #endif 1815 1816 #ifdef PMAP_CACHE_VIPT 1817 static void 1818 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1819 { 1820 struct pv_entry *pv; 1821 vaddr_t tst_mask; 1822 bool bad_alias; 1823 struct l2_bucket *l2b; 1824 pt_entry_t *ptep, pte, opte; 1825 const u_int 1826 rw_mappings = pg->mdpage.urw_mappings + pg->mdpage.krw_mappings, 1827 ro_mappings = pg->mdpage.uro_mappings + pg->mdpage.kro_mappings; 1828 1829 /* do we need to do anything? */ 1830 if (arm_cache_prefer_mask == 0) 1831 return; 1832 1833 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1834 pg, pm, va)); 1835 1836 KASSERT(!va || pm); 1837 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1838 1839 /* Already a conflict? */ 1840 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1841 /* just an add, things are already non-cached */ 1842 KASSERT(!(pg->mdpage.pvh_attrs & PVF_DIRTY)); 1843 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 1844 bad_alias = false; 1845 if (va) { 1846 PMAPCOUNT(vac_color_none); 1847 bad_alias = true; 1848 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1849 goto fixup; 1850 } 1851 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1852 /* the list can't be empty because it would be cachable */ 1853 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) { 1854 tst_mask = pg->mdpage.pvh_attrs; 1855 } else { 1856 KASSERT(pv); 1857 tst_mask = pv->pv_va; 1858 pv = SLIST_NEXT(pv, pv_link); 1859 } 1860 /* 1861 * Only check for a bad alias if we have writable mappings. 1862 */ 1863 tst_mask &= arm_cache_prefer_mask; 1864 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1865 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1866 /* if there's a bad alias, stop checking. */ 1867 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1868 bad_alias = true; 1869 } 1870 pg->mdpage.pvh_attrs |= PVF_WRITE; 1871 if (!bad_alias) 1872 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1873 } else { 1874 /* 1875 * We have only read-only mappings. Let's see if there 1876 * are multiple colors in use or if we mapped a KMPAGE. 1877 * If the latter, we have a bad alias. If the former, 1878 * we need to remember that. 1879 */ 1880 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1881 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1882 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) 1883 bad_alias = true; 1884 break; 1885 } 1886 } 1887 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1888 /* 1889 * No KMPAGE and we exited early, so we must have 1890 * multiple color mappings. 1891 */ 1892 if (!bad_alias && pv != NULL) 1893 pg->mdpage.pvh_attrs |= PVF_MULTCLR; 1894 } 1895 1896 /* If no conflicting colors, set everything back to cached */ 1897 if (!bad_alias) { 1898 #ifdef DEBUG 1899 if ((pg->mdpage.pvh_attrs & PVF_WRITE) 1900 || ro_mappings < 2) { 1901 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1902 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1903 } 1904 #endif 1905 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1906 pg->mdpage.pvh_attrs |= tst_mask | PVF_COLORED; 1907 /* 1908 * Restore DIRTY bit if page is modified 1909 */ 1910 if (pg->mdpage.pvh_attrs & PVF_DMOD) 1911 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1912 PMAPCOUNT(vac_color_restore); 1913 } else { 1914 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1915 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1916 } 1917 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1918 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1919 } else if (!va) { 1920 KASSERT(pmap_is_page_colored_p(pg)); 1921 KASSERT(!(pg->mdpage.pvh_attrs & PVF_WRITE) 1922 || (pg->mdpage.pvh_attrs & PVF_DIRTY)); 1923 if (rw_mappings == 0) { 1924 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1925 if (ro_mappings == 1 1926 && (pg->mdpage.pvh_attrs & PVF_MULTCLR)) { 1927 /* 1928 * If this is the last readonly mapping 1929 * but it doesn't match the current color 1930 * for the page, change the current color 1931 * to match this last readonly mapping. 1932 */ 1933 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1934 tst_mask = (pg->mdpage.pvh_attrs ^ pv->pv_va) 1935 & arm_cache_prefer_mask; 1936 if (tst_mask) { 1937 pg->mdpage.pvh_attrs ^= tst_mask; 1938 PMAPCOUNT(vac_color_change); 1939 } 1940 } 1941 } 1942 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1943 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1944 return; 1945 } else if (!pmap_is_page_colored_p(pg)) { 1946 /* not colored so we just use its color */ 1947 KASSERT(pg->mdpage.pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1948 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 1949 PMAPCOUNT(vac_color_new); 1950 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1951 pg->mdpage.pvh_attrs |= PVF_COLORED 1952 | (va & arm_cache_prefer_mask) 1953 | (rw_mappings > 0 ? PVF_WRITE : 0); 1954 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1955 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1956 return; 1957 } else if (((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1958 bad_alias = false; 1959 if (rw_mappings > 0) { 1960 /* 1961 * We now have writeable mappings and if we have 1962 * readonly mappings in more than once color, we have 1963 * an aliasing problem. Regardless mark the page as 1964 * writeable. 1965 */ 1966 if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 1967 if (ro_mappings < 2) { 1968 /* 1969 * If we only have less than two 1970 * read-only mappings, just flush the 1971 * non-primary colors from the cache. 1972 */ 1973 pmap_flush_page(pg, 1974 PMAP_FLUSH_SECONDARY); 1975 } else { 1976 bad_alias = true; 1977 } 1978 } 1979 pg->mdpage.pvh_attrs |= PVF_WRITE; 1980 } 1981 /* If no conflicting colors, set everything back to cached */ 1982 if (!bad_alias) { 1983 #ifdef DEBUG 1984 if (rw_mappings > 0 1985 || (pg->mdpage.pvh_attrs & PMAP_KMPAGE)) { 1986 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1987 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1988 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1989 } 1990 #endif 1991 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) 1992 PMAPCOUNT(vac_color_reuse); 1993 else 1994 PMAPCOUNT(vac_color_ok); 1995 1996 /* matching color, just return */ 1997 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1998 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1999 return; 2000 } 2001 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 2002 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 2003 2004 /* color conflict. evict from cache. */ 2005 2006 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 2007 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2008 pg->mdpage.pvh_attrs |= PVF_NC; 2009 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2010 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 2011 PMAPCOUNT(vac_color_erase); 2012 } else if (rw_mappings == 0 2013 && (pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2014 KASSERT((pg->mdpage.pvh_attrs & PVF_WRITE) == 0); 2015 2016 /* 2017 * If the page has dirty cache lines, clean it. 2018 */ 2019 if (pg->mdpage.pvh_attrs & PVF_DIRTY) 2020 pmap_flush_page(pg, PMAP_CLEAN_PRIMARY); 2021 2022 /* 2023 * If this is the first remapping (we know that there are no 2024 * writeable mappings), then this is a simple color change. 2025 * Otherwise this is a seconary r/o mapping, which means 2026 * we don't have to do anything. 2027 */ 2028 if (ro_mappings == 1) { 2029 KASSERT(((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2030 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2031 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2032 PMAPCOUNT(vac_color_change); 2033 } else { 2034 PMAPCOUNT(vac_color_blind); 2035 } 2036 pg->mdpage.pvh_attrs |= PVF_MULTCLR; 2037 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2038 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2039 return; 2040 } else { 2041 if (rw_mappings > 0) 2042 pg->mdpage.pvh_attrs |= PVF_WRITE; 2043 2044 /* color conflict. evict from cache. */ 2045 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 2046 2047 /* the list can't be empty because this was a enter/modify */ 2048 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2049 if ((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2050 KASSERT(pv); 2051 /* 2052 * If there's only one mapped page, change color to the 2053 * page's new color and return. Restore the DIRTY bit 2054 * that was erased by pmap_flush_page. 2055 */ 2056 if (SLIST_NEXT(pv, pv_link) == NULL) { 2057 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2058 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2059 if (pg->mdpage.pvh_attrs & PVF_DMOD) 2060 pg->mdpage.pvh_attrs |= PVF_DIRTY; 2061 PMAPCOUNT(vac_color_change); 2062 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2063 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2064 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 2065 return; 2066 } 2067 } 2068 bad_alias = true; 2069 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2070 pg->mdpage.pvh_attrs |= PVF_NC; 2071 PMAPCOUNT(vac_color_erase); 2072 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2073 } 2074 2075 fixup: 2076 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2077 2078 /* 2079 * Turn cacheing on/off for all pages. 2080 */ 2081 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2082 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2083 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2084 opte = *ptep; 2085 pte = opte & ~L2_S_CACHE_MASK; 2086 if (bad_alias) { 2087 pv->pv_flags |= PVF_NC; 2088 } else { 2089 pv->pv_flags &= ~PVF_NC; 2090 pte |= pte_l2_s_cache_mode; 2091 } 2092 2093 if (opte == pte) /* only update is there's a change */ 2094 continue; 2095 2096 if (l2pte_valid(pte)) { 2097 if (PV_BEEN_EXECD(pv->pv_flags)) { 2098 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2099 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2100 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2101 } 2102 } 2103 2104 *ptep = pte; 2105 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2106 } 2107 } 2108 #endif /* PMAP_CACHE_VIPT */ 2109 2110 2111 /* 2112 * Modify pte bits for all ptes corresponding to the given physical address. 2113 * We use `maskbits' rather than `clearbits' because we're always passing 2114 * constants and the latter would require an extra inversion at run-time. 2115 */ 2116 static void 2117 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2118 { 2119 struct l2_bucket *l2b; 2120 struct pv_entry *pv; 2121 pt_entry_t *ptep, npte, opte; 2122 pmap_t pm; 2123 vaddr_t va; 2124 u_int oflags; 2125 #ifdef PMAP_CACHE_VIPT 2126 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 2127 bool need_syncicache = false; 2128 bool did_syncicache = false; 2129 bool need_vac_me_harder = false; 2130 #endif 2131 2132 NPDEBUG(PDB_BITS, 2133 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2134 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2135 2136 PMAP_HEAD_TO_MAP_LOCK(); 2137 simple_lock(&pg->mdpage.pvh_slock); 2138 2139 #ifdef PMAP_CACHE_VIPT 2140 /* 2141 * If we might want to sync the I-cache and we've modified it, 2142 * then we know we definitely need to sync or discard it. 2143 */ 2144 if (want_syncicache) 2145 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 2146 #endif 2147 /* 2148 * Clear saved attributes (modify, reference) 2149 */ 2150 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2151 2152 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 2153 #ifdef PMAP_CACHE_VIPT 2154 if (need_syncicache) { 2155 /* 2156 * No one has it mapped, so just discard it. The next 2157 * exec remapping will cause it to be synced. 2158 */ 2159 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2160 PMAPCOUNT(exec_discarded_clearbit); 2161 } 2162 #endif 2163 simple_unlock(&pg->mdpage.pvh_slock); 2164 PMAP_HEAD_TO_MAP_UNLOCK(); 2165 return; 2166 } 2167 2168 /* 2169 * Loop over all current mappings setting/clearing as appropos 2170 */ 2171 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2172 va = pv->pv_va; 2173 pm = pv->pv_pmap; 2174 oflags = pv->pv_flags; 2175 /* 2176 * Kernel entries are unmanaged and as such not to be changed. 2177 */ 2178 if (oflags & PVF_KENTRY) 2179 continue; 2180 pv->pv_flags &= ~maskbits; 2181 2182 pmap_acquire_pmap_lock(pm); 2183 2184 l2b = pmap_get_l2_bucket(pm, va); 2185 KDASSERT(l2b != NULL); 2186 2187 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2188 npte = opte = *ptep; 2189 2190 NPDEBUG(PDB_BITS, 2191 printf( 2192 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2193 pv, pv->pv_pmap, pv->pv_va, oflags)); 2194 2195 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2196 #ifdef PMAP_CACHE_VIVT 2197 if ((pv->pv_flags & PVF_NC)) { 2198 /* 2199 * Entry is not cacheable: 2200 * 2201 * Don't turn caching on again if this is a 2202 * modified emulation. This would be 2203 * inconsitent with the settings created by 2204 * pmap_vac_me_harder(). Otherwise, it's safe 2205 * to re-enable cacheing. 2206 * 2207 * There's no need to call pmap_vac_me_harder() 2208 * here: all pages are losing their write 2209 * permission. 2210 */ 2211 if (maskbits & PVF_WRITE) { 2212 npte |= pte_l2_s_cache_mode; 2213 pv->pv_flags &= ~PVF_NC; 2214 } 2215 } else 2216 if (opte & L2_S_PROT_W) { 2217 /* 2218 * Entry is writable/cacheable: check if pmap 2219 * is current if it is flush it, otherwise it 2220 * won't be in the cache 2221 */ 2222 if (PV_BEEN_EXECD(oflags)) 2223 pmap_idcache_wbinv_range(pm, pv->pv_va, 2224 PAGE_SIZE); 2225 else 2226 if (PV_BEEN_REFD(oflags)) 2227 pmap_dcache_wb_range(pm, pv->pv_va, 2228 PAGE_SIZE, 2229 (maskbits & PVF_REF) != 0, false); 2230 } 2231 #endif 2232 2233 /* make the pte read only */ 2234 npte &= ~L2_S_PROT_W; 2235 2236 if (maskbits & oflags & PVF_WRITE) { 2237 /* 2238 * Keep alias accounting up to date 2239 */ 2240 if (pv->pv_pmap == pmap_kernel()) { 2241 pg->mdpage.krw_mappings--; 2242 pg->mdpage.kro_mappings++; 2243 } else { 2244 pg->mdpage.urw_mappings--; 2245 pg->mdpage.uro_mappings++; 2246 } 2247 #ifdef PMAP_CACHE_VIPT 2248 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 2249 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2250 if (want_syncicache) 2251 need_syncicache = true; 2252 need_vac_me_harder = true; 2253 #endif 2254 } 2255 } 2256 2257 if (maskbits & PVF_REF) { 2258 if ((pv->pv_flags & PVF_NC) == 0 && 2259 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2260 l2pte_valid(npte)) { 2261 #ifdef PMAP_CACHE_VIVT 2262 /* 2263 * Check npte here; we may have already 2264 * done the wbinv above, and the validity 2265 * of the PTE is the same for opte and 2266 * npte. 2267 */ 2268 /* XXXJRT need idcache_inv_range */ 2269 if (PV_BEEN_EXECD(oflags)) 2270 pmap_idcache_wbinv_range(pm, 2271 pv->pv_va, PAGE_SIZE); 2272 else 2273 if (PV_BEEN_REFD(oflags)) 2274 pmap_dcache_wb_range(pm, 2275 pv->pv_va, PAGE_SIZE, 2276 true, true); 2277 #endif 2278 } 2279 2280 /* 2281 * Make the PTE invalid so that we will take a 2282 * page fault the next time the mapping is 2283 * referenced. 2284 */ 2285 npte &= ~L2_TYPE_MASK; 2286 npte |= L2_TYPE_INV; 2287 } 2288 2289 if (npte != opte) { 2290 *ptep = npte; 2291 PTE_SYNC(ptep); 2292 /* Flush the TLB entry if a current pmap. */ 2293 if (PV_BEEN_EXECD(oflags)) 2294 pmap_tlb_flushID_SE(pm, pv->pv_va); 2295 else 2296 if (PV_BEEN_REFD(oflags)) 2297 pmap_tlb_flushD_SE(pm, pv->pv_va); 2298 } 2299 2300 pmap_release_pmap_lock(pm); 2301 2302 NPDEBUG(PDB_BITS, 2303 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2304 pm, va, opte, npte)); 2305 } 2306 2307 #ifdef PMAP_CACHE_VIPT 2308 /* 2309 * If we need to sync the I-cache and we haven't done it yet, do it. 2310 */ 2311 if (need_syncicache && !did_syncicache) { 2312 pmap_syncicache_page(pg); 2313 PMAPCOUNT(exec_synced_clearbit); 2314 } 2315 /* 2316 * If we are changing this to read-only, we need to call vac_me_harder 2317 * so we can change all the read-only pages to cacheable. We pretend 2318 * this as a page deletion. 2319 */ 2320 if (need_vac_me_harder) { 2321 if (pg->mdpage.pvh_attrs & PVF_NC) 2322 pmap_vac_me_harder(pg, NULL, 0); 2323 } 2324 #endif 2325 2326 simple_unlock(&pg->mdpage.pvh_slock); 2327 PMAP_HEAD_TO_MAP_UNLOCK(); 2328 } 2329 2330 /* 2331 * pmap_clean_page() 2332 * 2333 * This is a local function used to work out the best strategy to clean 2334 * a single page referenced by its entry in the PV table. It's used by 2335 * pmap_copy_page, pmap_zero page and maybe some others later on. 2336 * 2337 * Its policy is effectively: 2338 * o If there are no mappings, we don't bother doing anything with the cache. 2339 * o If there is one mapping, we clean just that page. 2340 * o If there are multiple mappings, we clean the entire cache. 2341 * 2342 * So that some functions can be further optimised, it returns 0 if it didn't 2343 * clean the entire cache, or 1 if it did. 2344 * 2345 * XXX One bug in this routine is that if the pv_entry has a single page 2346 * mapped at 0x00000000 a whole cache clean will be performed rather than 2347 * just the 1 page. Since this should not occur in everyday use and if it does 2348 * it will just result in not the most efficient clean for the page. 2349 */ 2350 #ifdef PMAP_CACHE_VIVT 2351 static int 2352 pmap_clean_page(struct pv_entry *pv, bool is_src) 2353 { 2354 pmap_t pm, pm_to_clean = NULL; 2355 struct pv_entry *npv; 2356 u_int cache_needs_cleaning = 0; 2357 u_int flags = 0; 2358 vaddr_t page_to_clean = 0; 2359 2360 if (pv == NULL) { 2361 /* nothing mapped in so nothing to flush */ 2362 return (0); 2363 } 2364 2365 /* 2366 * Since we flush the cache each time we change to a different 2367 * user vmspace, we only need to flush the page if it is in the 2368 * current pmap. 2369 */ 2370 pm = curproc->p_vmspace->vm_map.pmap; 2371 2372 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2373 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2374 flags |= npv->pv_flags; 2375 /* 2376 * The page is mapped non-cacheable in 2377 * this map. No need to flush the cache. 2378 */ 2379 if (npv->pv_flags & PVF_NC) { 2380 #ifdef DIAGNOSTIC 2381 if (cache_needs_cleaning) 2382 panic("pmap_clean_page: " 2383 "cache inconsistency"); 2384 #endif 2385 break; 2386 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2387 continue; 2388 if (cache_needs_cleaning) { 2389 page_to_clean = 0; 2390 break; 2391 } else { 2392 page_to_clean = npv->pv_va; 2393 pm_to_clean = npv->pv_pmap; 2394 } 2395 cache_needs_cleaning = 1; 2396 } 2397 } 2398 2399 if (page_to_clean) { 2400 if (PV_BEEN_EXECD(flags)) 2401 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2402 PAGE_SIZE); 2403 else 2404 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2405 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2406 } else if (cache_needs_cleaning) { 2407 if (PV_BEEN_EXECD(flags)) 2408 pmap_idcache_wbinv_all(pm); 2409 else 2410 pmap_dcache_wbinv_all(pm); 2411 return (1); 2412 } 2413 return (0); 2414 } 2415 #endif 2416 2417 #ifdef PMAP_CACHE_VIPT 2418 /* 2419 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2420 * right cache alias to make sure we flush the right stuff. 2421 */ 2422 void 2423 pmap_syncicache_page(struct vm_page *pg) 2424 { 2425 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2426 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2427 2428 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2429 pg, pg->mdpage.pvh_attrs)); 2430 /* 2431 * No need to clean the page if it's non-cached. 2432 */ 2433 if (pg->mdpage.pvh_attrs & PVF_NC) 2434 return; 2435 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2436 2437 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2438 /* 2439 * Set up a PTE with the right coloring to flush existing cache lines. 2440 */ 2441 *ptep = L2_S_PROTO | 2442 VM_PAGE_TO_PHYS(pg) 2443 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2444 | pte_l2_s_cache_mode; 2445 PTE_SYNC(ptep); 2446 2447 /* 2448 * Flush it. 2449 */ 2450 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2451 /* 2452 * Unmap the page. 2453 */ 2454 *ptep = 0; 2455 PTE_SYNC(ptep); 2456 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2457 2458 pg->mdpage.pvh_attrs |= PVF_EXEC; 2459 PMAPCOUNT(exec_synced); 2460 } 2461 2462 void 2463 pmap_flush_page(struct vm_page *pg, enum pmap_flush_op flush) 2464 { 2465 vsize_t va_offset, end_va; 2466 void (*cf)(vaddr_t, vsize_t); 2467 2468 if (arm_cache_prefer_mask == 0) 2469 return; 2470 2471 switch (flush) { 2472 case PMAP_FLUSH_PRIMARY: 2473 if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 2474 va_offset = 0; 2475 end_va = arm_cache_prefer_mask; 2476 pg->mdpage.pvh_attrs &= ~PVF_MULTCLR; 2477 PMAPCOUNT(vac_flush_lots); 2478 } else { 2479 va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2480 end_va = va_offset; 2481 PMAPCOUNT(vac_flush_one); 2482 } 2483 /* 2484 * Mark that the page is no longer dirty. 2485 */ 2486 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2487 cf = cpufuncs.cf_idcache_wbinv_range; 2488 break; 2489 case PMAP_FLUSH_SECONDARY: 2490 va_offset = 0; 2491 end_va = arm_cache_prefer_mask; 2492 cf = cpufuncs.cf_idcache_wbinv_range; 2493 pg->mdpage.pvh_attrs &= ~PVF_MULTCLR; 2494 PMAPCOUNT(vac_flush_lots); 2495 break; 2496 case PMAP_CLEAN_PRIMARY: 2497 va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2498 end_va = va_offset; 2499 cf = cpufuncs.cf_dcache_wb_range; 2500 /* 2501 * Mark that the page is no longer dirty. 2502 */ 2503 if ((pg->mdpage.pvh_attrs & PVF_DMOD) == 0) 2504 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2505 PMAPCOUNT(vac_clean_one); 2506 break; 2507 default: 2508 return; 2509 } 2510 2511 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2512 2513 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2514 pg, pg->mdpage.pvh_attrs)); 2515 2516 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2517 const size_t pte_offset = va_offset >> PGSHIFT; 2518 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2519 const pt_entry_t oldpte = *ptep; 2520 2521 if (flush == PMAP_FLUSH_SECONDARY 2522 && va_offset == (pg->mdpage.pvh_attrs & arm_cache_prefer_mask)) 2523 continue; 2524 2525 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2526 /* 2527 * Set up a PTE with the right coloring to flush 2528 * existing cache entries. 2529 */ 2530 *ptep = L2_S_PROTO 2531 | VM_PAGE_TO_PHYS(pg) 2532 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2533 | pte_l2_s_cache_mode; 2534 PTE_SYNC(ptep); 2535 2536 /* 2537 * Flush it. 2538 */ 2539 (*cf)(cdstp + va_offset, PAGE_SIZE); 2540 2541 /* 2542 * Restore the page table entry since we might have interrupted 2543 * pmap_zero_page or pmap_copy_page which was already using 2544 * this pte. 2545 */ 2546 *ptep = oldpte; 2547 PTE_SYNC(ptep); 2548 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2549 } 2550 } 2551 #endif /* PMAP_CACHE_VIPT */ 2552 2553 /* 2554 * Routine: pmap_page_remove 2555 * Function: 2556 * Removes this physical page from 2557 * all physical maps in which it resides. 2558 * Reflects back modify bits to the pager. 2559 */ 2560 static void 2561 pmap_page_remove(struct vm_page *pg) 2562 { 2563 struct l2_bucket *l2b; 2564 struct pv_entry *pv, *npv, **pvp; 2565 pmap_t pm, curpm; 2566 pt_entry_t *ptep, pte; 2567 bool flush; 2568 u_int flags; 2569 2570 NPDEBUG(PDB_FOLLOW, 2571 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2572 VM_PAGE_TO_PHYS(pg))); 2573 2574 PMAP_HEAD_TO_MAP_LOCK(); 2575 simple_lock(&pg->mdpage.pvh_slock); 2576 2577 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2578 if (pv == NULL) { 2579 #ifdef PMAP_CACHE_VIPT 2580 /* 2581 * We *know* the page contents are about to be replaced. 2582 * Discard the exec contents 2583 */ 2584 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2585 PMAPCOUNT(exec_discarded_page_protect); 2586 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2587 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2588 #endif 2589 simple_unlock(&pg->mdpage.pvh_slock); 2590 PMAP_HEAD_TO_MAP_UNLOCK(); 2591 return; 2592 } 2593 #ifdef PMAP_CACHE_VIPT 2594 KASSERT(pmap_is_page_colored_p(pg)); 2595 #endif 2596 2597 /* 2598 * Clear alias counts 2599 */ 2600 #ifdef PMAP_CACHE_VIVT 2601 pg->mdpage.k_mappings = 0; 2602 #endif 2603 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2604 2605 flush = false; 2606 flags = 0; 2607 curpm = curproc->p_vmspace->vm_map.pmap; 2608 2609 #ifdef PMAP_CACHE_VIVT 2610 pmap_clean_page(pv, false); 2611 #endif 2612 2613 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 2614 while (pv) { 2615 pm = pv->pv_pmap; 2616 npv = SLIST_NEXT(pv, pv_link); 2617 if (flush == false && (pm == curpm || pm == pmap_kernel())) 2618 flush = true; 2619 2620 if (pm == pmap_kernel()) { 2621 #ifdef PMAP_CACHE_VIPT 2622 /* 2623 * If this was unmanaged mapping, it must be preserved. 2624 * Move it back on the list and advance the end-of-list 2625 * pointer. 2626 */ 2627 if (pv->pv_flags & PVF_KENTRY) { 2628 *pvp = pv; 2629 pvp = &SLIST_NEXT(pv, pv_link); 2630 pv = npv; 2631 continue; 2632 } 2633 if (pv->pv_flags & PVF_WRITE) 2634 pg->mdpage.krw_mappings--; 2635 else 2636 pg->mdpage.kro_mappings--; 2637 #endif 2638 PMAPCOUNT(kernel_unmappings); 2639 } 2640 PMAPCOUNT(unmappings); 2641 2642 pmap_acquire_pmap_lock(pm); 2643 2644 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2645 KDASSERT(l2b != NULL); 2646 2647 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2648 pte = *ptep; 2649 2650 /* 2651 * Update statistics 2652 */ 2653 --pm->pm_stats.resident_count; 2654 2655 /* Wired bit */ 2656 if (pv->pv_flags & PVF_WIRED) 2657 --pm->pm_stats.wired_count; 2658 2659 flags |= pv->pv_flags; 2660 2661 /* 2662 * Invalidate the PTEs. 2663 */ 2664 *ptep = 0; 2665 PTE_SYNC_CURRENT(pm, ptep); 2666 pmap_free_l2_bucket(pm, l2b, 1); 2667 2668 pool_put(&pmap_pv_pool, pv); 2669 pv = npv; 2670 /* 2671 * if we reach the end of the list and there are still 2672 * mappings, they might be able to be cached now. 2673 */ 2674 if (pv == NULL) { 2675 *pvp = NULL; 2676 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 2677 pmap_vac_me_harder(pg, pm, 0); 2678 } 2679 pmap_release_pmap_lock(pm); 2680 } 2681 #ifdef PMAP_CACHE_VIPT 2682 /* 2683 * Its EXEC cache is now gone. 2684 */ 2685 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2686 PMAPCOUNT(exec_discarded_page_protect); 2687 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2688 KASSERT(pg->mdpage.urw_mappings == 0); 2689 KASSERT(pg->mdpage.uro_mappings == 0); 2690 if (pg->mdpage.krw_mappings == 0) 2691 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2692 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2693 #endif 2694 simple_unlock(&pg->mdpage.pvh_slock); 2695 PMAP_HEAD_TO_MAP_UNLOCK(); 2696 2697 if (flush) { 2698 /* 2699 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2700 * would need a subsequent call to pmap_update() to ensure 2701 * curpm->pm_cstate.cs_all is reset. Our callers are not 2702 * required to do that (see pmap(9)), so we can't modify 2703 * the current pmap's state. 2704 */ 2705 if (PV_BEEN_EXECD(flags)) 2706 cpu_tlb_flushID(); 2707 else 2708 cpu_tlb_flushD(); 2709 } 2710 cpu_cpwait(); 2711 } 2712 2713 /* 2714 * pmap_t pmap_create(void) 2715 * 2716 * Create a new pmap structure from scratch. 2717 */ 2718 pmap_t 2719 pmap_create(void) 2720 { 2721 pmap_t pm; 2722 2723 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2724 2725 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2726 pm->pm_stats.wired_count = 0; 2727 pm->pm_stats.resident_count = 1; 2728 pm->pm_cstate.cs_all = 0; 2729 pmap_alloc_l1(pm); 2730 2731 /* 2732 * Note: The pool cache ensures that the pm_l2[] array is already 2733 * initialised to zero. 2734 */ 2735 2736 pmap_pinit(pm); 2737 2738 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2739 2740 return (pm); 2741 } 2742 2743 /* 2744 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2745 * u_int flags) 2746 * 2747 * Insert the given physical page (p) at 2748 * the specified virtual address (v) in the 2749 * target physical map with the protection requested. 2750 * 2751 * NB: This is the only routine which MAY NOT lazy-evaluate 2752 * or lose information. That is, this routine must actually 2753 * insert this page into the given map NOW. 2754 */ 2755 int 2756 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2757 { 2758 struct l2_bucket *l2b; 2759 struct vm_page *pg, *opg; 2760 struct pv_entry *pve; 2761 pt_entry_t *ptep, npte, opte; 2762 u_int nflags; 2763 u_int oflags; 2764 2765 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2766 2767 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2768 KDASSERT(((va | pa) & PGOFSET) == 0); 2769 2770 /* 2771 * Get a pointer to the page. Later on in this function, we 2772 * test for a managed page by checking pg != NULL. 2773 */ 2774 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2775 2776 nflags = 0; 2777 if (prot & VM_PROT_WRITE) 2778 nflags |= PVF_WRITE; 2779 if (prot & VM_PROT_EXECUTE) 2780 nflags |= PVF_EXEC; 2781 if (flags & PMAP_WIRED) 2782 nflags |= PVF_WIRED; 2783 2784 PMAP_MAP_TO_HEAD_LOCK(); 2785 pmap_acquire_pmap_lock(pm); 2786 2787 /* 2788 * Fetch the L2 bucket which maps this page, allocating one if 2789 * necessary for user pmaps. 2790 */ 2791 if (pm == pmap_kernel()) 2792 l2b = pmap_get_l2_bucket(pm, va); 2793 else 2794 l2b = pmap_alloc_l2_bucket(pm, va); 2795 if (l2b == NULL) { 2796 if (flags & PMAP_CANFAIL) { 2797 pmap_release_pmap_lock(pm); 2798 PMAP_MAP_TO_HEAD_UNLOCK(); 2799 return (ENOMEM); 2800 } 2801 panic("pmap_enter: failed to allocate L2 bucket"); 2802 } 2803 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2804 opte = *ptep; 2805 npte = pa; 2806 oflags = 0; 2807 2808 if (opte) { 2809 /* 2810 * There is already a mapping at this address. 2811 * If the physical address is different, lookup the 2812 * vm_page. 2813 */ 2814 if (l2pte_pa(opte) != pa) 2815 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2816 else 2817 opg = pg; 2818 } else 2819 opg = NULL; 2820 2821 if (pg) { 2822 /* 2823 * This is to be a managed mapping. 2824 */ 2825 if ((flags & VM_PROT_ALL) || 2826 (pg->mdpage.pvh_attrs & PVF_REF)) { 2827 /* 2828 * - The access type indicates that we don't need 2829 * to do referenced emulation. 2830 * OR 2831 * - The physical page has already been referenced 2832 * so no need to re-do referenced emulation here. 2833 */ 2834 npte |= L2_S_PROTO; 2835 2836 nflags |= PVF_REF; 2837 2838 if ((prot & VM_PROT_WRITE) != 0 && 2839 ((flags & VM_PROT_WRITE) != 0 || 2840 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2841 /* 2842 * This is a writable mapping, and the 2843 * page's mod state indicates it has 2844 * already been modified. Make it 2845 * writable from the outset. 2846 */ 2847 npte |= L2_S_PROT_W; 2848 nflags |= PVF_MOD; 2849 } 2850 } else { 2851 /* 2852 * Need to do page referenced emulation. 2853 */ 2854 npte |= L2_TYPE_INV; 2855 } 2856 2857 npte |= pte_l2_s_cache_mode; 2858 2859 if (pg == opg) { 2860 /* 2861 * We're changing the attrs of an existing mapping. 2862 */ 2863 simple_lock(&pg->mdpage.pvh_slock); 2864 oflags = pmap_modify_pv(pg, pm, va, 2865 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2866 PVF_MOD | PVF_REF, nflags); 2867 simple_unlock(&pg->mdpage.pvh_slock); 2868 2869 #ifdef PMAP_CACHE_VIVT 2870 /* 2871 * We may need to flush the cache if we're 2872 * doing rw-ro... 2873 */ 2874 if (pm->pm_cstate.cs_cache_d && 2875 (oflags & PVF_NC) == 0 && 2876 (opte & L2_S_PROT_W) != 0 && 2877 (prot & VM_PROT_WRITE) == 0) 2878 cpu_dcache_wb_range(va, PAGE_SIZE); 2879 #endif 2880 } else { 2881 /* 2882 * New mapping, or changing the backing page 2883 * of an existing mapping. 2884 */ 2885 if (opg) { 2886 /* 2887 * Replacing an existing mapping with a new one. 2888 * It is part of our managed memory so we 2889 * must remove it from the PV list 2890 */ 2891 simple_lock(&opg->mdpage.pvh_slock); 2892 pve = pmap_remove_pv(opg, pm, va); 2893 pmap_vac_me_harder(opg, pm, 0); 2894 simple_unlock(&opg->mdpage.pvh_slock); 2895 oflags = pve->pv_flags; 2896 2897 #ifdef PMAP_CACHE_VIVT 2898 /* 2899 * If the old mapping was valid (ref/mod 2900 * emulation creates 'invalid' mappings 2901 * initially) then make sure to frob 2902 * the cache. 2903 */ 2904 if ((oflags & PVF_NC) == 0 && 2905 l2pte_valid(opte)) { 2906 if (PV_BEEN_EXECD(oflags)) { 2907 pmap_idcache_wbinv_range(pm, va, 2908 PAGE_SIZE); 2909 } else 2910 if (PV_BEEN_REFD(oflags)) { 2911 pmap_dcache_wb_range(pm, va, 2912 PAGE_SIZE, true, 2913 (oflags & PVF_WRITE) == 0); 2914 } 2915 } 2916 #endif 2917 } else 2918 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2919 if ((flags & PMAP_CANFAIL) == 0) 2920 panic("pmap_enter: no pv entries"); 2921 2922 if (pm != pmap_kernel()) 2923 pmap_free_l2_bucket(pm, l2b, 0); 2924 pmap_release_pmap_lock(pm); 2925 PMAP_MAP_TO_HEAD_UNLOCK(); 2926 NPDEBUG(PDB_ENTER, 2927 printf("pmap_enter: ENOMEM\n")); 2928 return (ENOMEM); 2929 } 2930 2931 pmap_enter_pv(pg, pve, pm, va, nflags); 2932 } 2933 } else { 2934 /* 2935 * We're mapping an unmanaged page. 2936 * These are always readable, and possibly writable, from 2937 * the get go as we don't need to track ref/mod status. 2938 */ 2939 npte |= L2_S_PROTO; 2940 if (prot & VM_PROT_WRITE) 2941 npte |= L2_S_PROT_W; 2942 2943 /* 2944 * Make sure the vector table is mapped cacheable 2945 */ 2946 if (pm != pmap_kernel() && va == vector_page) 2947 npte |= pte_l2_s_cache_mode; 2948 2949 if (opg) { 2950 /* 2951 * Looks like there's an existing 'managed' mapping 2952 * at this address. 2953 */ 2954 simple_lock(&opg->mdpage.pvh_slock); 2955 pve = pmap_remove_pv(opg, pm, va); 2956 pmap_vac_me_harder(opg, pm, 0); 2957 simple_unlock(&opg->mdpage.pvh_slock); 2958 oflags = pve->pv_flags; 2959 2960 #ifdef PMAP_CACHE_VIVT 2961 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2962 if (PV_BEEN_EXECD(oflags)) 2963 pmap_idcache_wbinv_range(pm, va, 2964 PAGE_SIZE); 2965 else 2966 if (PV_BEEN_REFD(oflags)) 2967 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2968 true, (oflags & PVF_WRITE) == 0); 2969 } 2970 #endif 2971 pool_put(&pmap_pv_pool, pve); 2972 } 2973 } 2974 2975 /* 2976 * Make sure userland mappings get the right permissions 2977 */ 2978 if (pm != pmap_kernel() && va != vector_page) 2979 npte |= L2_S_PROT_U; 2980 2981 /* 2982 * Keep the stats up to date 2983 */ 2984 if (opte == 0) { 2985 l2b->l2b_occupancy++; 2986 pm->pm_stats.resident_count++; 2987 } 2988 2989 NPDEBUG(PDB_ENTER, 2990 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2991 2992 /* 2993 * If this is just a wiring change, the two PTEs will be 2994 * identical, so there's no need to update the page table. 2995 */ 2996 if (npte != opte) { 2997 bool is_cached = pmap_is_cached(pm); 2998 2999 *ptep = npte; 3000 if (is_cached) { 3001 /* 3002 * We only need to frob the cache/tlb if this pmap 3003 * is current 3004 */ 3005 PTE_SYNC(ptep); 3006 if (va != vector_page && l2pte_valid(npte)) { 3007 /* 3008 * This mapping is likely to be accessed as 3009 * soon as we return to userland. Fix up the 3010 * L1 entry to avoid taking another 3011 * page/domain fault. 3012 */ 3013 pd_entry_t *pl1pd, l1pd; 3014 3015 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3016 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3017 L1_C_PROTO; 3018 if (*pl1pd != l1pd) { 3019 *pl1pd = l1pd; 3020 PTE_SYNC(pl1pd); 3021 } 3022 } 3023 } 3024 3025 if (PV_BEEN_EXECD(oflags)) 3026 pmap_tlb_flushID_SE(pm, va); 3027 else 3028 if (PV_BEEN_REFD(oflags)) 3029 pmap_tlb_flushD_SE(pm, va); 3030 3031 NPDEBUG(PDB_ENTER, 3032 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3033 is_cached, pm->pm_cstate.cs_all)); 3034 3035 if (pg != NULL) { 3036 simple_lock(&pg->mdpage.pvh_slock); 3037 pmap_vac_me_harder(pg, pm, va); 3038 simple_unlock(&pg->mdpage.pvh_slock); 3039 } 3040 } 3041 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3042 if (pg) { 3043 simple_lock(&pg->mdpage.pvh_slock); 3044 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3045 KASSERT(((pg->mdpage.pvh_attrs & PVF_WRITE) == 0) == (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0)); 3046 simple_unlock(&pg->mdpage.pvh_slock); 3047 } 3048 #endif 3049 3050 pmap_release_pmap_lock(pm); 3051 PMAP_MAP_TO_HEAD_UNLOCK(); 3052 3053 return (0); 3054 } 3055 3056 /* 3057 * pmap_remove() 3058 * 3059 * pmap_remove is responsible for nuking a number of mappings for a range 3060 * of virtual address space in the current pmap. To do this efficiently 3061 * is interesting, because in a number of cases a wide virtual address 3062 * range may be supplied that contains few actual mappings. So, the 3063 * optimisations are: 3064 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3065 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3066 * maybe do just a partial cache clean. This path of execution is 3067 * complicated by the fact that the cache must be flushed _before_ 3068 * the PTE is nuked, being a VAC :-) 3069 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3070 * all invalidations until pmap_update(), since pmap_remove_all() has 3071 * already flushed the cache. 3072 * 4. Maybe later fast-case a single page, but I don't think this is 3073 * going to make _that_ much difference overall. 3074 */ 3075 3076 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3077 3078 void 3079 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3080 { 3081 struct l2_bucket *l2b; 3082 vaddr_t next_bucket; 3083 pt_entry_t *ptep; 3084 u_int cleanlist_idx, total, cnt; 3085 struct { 3086 vaddr_t va; 3087 pt_entry_t *ptep; 3088 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3089 u_int mappings, is_exec, is_refd; 3090 3091 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3092 "eva=%08lx\n", pm, sva, eva)); 3093 3094 /* 3095 * we lock in the pmap => pv_head direction 3096 */ 3097 PMAP_MAP_TO_HEAD_LOCK(); 3098 pmap_acquire_pmap_lock(pm); 3099 3100 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3101 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3102 if (pm->pm_cstate.cs_tlb == 0) 3103 pm->pm_remove_all = true; 3104 } else 3105 cleanlist_idx = 0; 3106 3107 total = 0; 3108 3109 while (sva < eva) { 3110 /* 3111 * Do one L2 bucket's worth at a time. 3112 */ 3113 next_bucket = L2_NEXT_BUCKET(sva); 3114 if (next_bucket > eva) 3115 next_bucket = eva; 3116 3117 l2b = pmap_get_l2_bucket(pm, sva); 3118 if (l2b == NULL) { 3119 sva = next_bucket; 3120 continue; 3121 } 3122 3123 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3124 3125 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3126 struct vm_page *pg; 3127 pt_entry_t pte; 3128 paddr_t pa; 3129 3130 pte = *ptep; 3131 3132 if (pte == 0) { 3133 /* Nothing here, move along */ 3134 continue; 3135 } 3136 3137 pa = l2pte_pa(pte); 3138 is_exec = 0; 3139 is_refd = 1; 3140 3141 /* 3142 * Update flags. In a number of circumstances, 3143 * we could cluster a lot of these and do a 3144 * number of sequential pages in one go. 3145 */ 3146 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3147 struct pv_entry *pve; 3148 simple_lock(&pg->mdpage.pvh_slock); 3149 pve = pmap_remove_pv(pg, pm, sva); 3150 pmap_vac_me_harder(pg, pm, 0); 3151 simple_unlock(&pg->mdpage.pvh_slock); 3152 if (pve != NULL) { 3153 if (pm->pm_remove_all == false) { 3154 is_exec = 3155 PV_BEEN_EXECD(pve->pv_flags); 3156 is_refd = 3157 PV_BEEN_REFD(pve->pv_flags); 3158 } 3159 pool_put(&pmap_pv_pool, pve); 3160 } 3161 } 3162 mappings++; 3163 3164 if (!l2pte_valid(pte)) { 3165 /* 3166 * Ref/Mod emulation is still active for this 3167 * mapping, therefore it is has not yet been 3168 * accessed. No need to frob the cache/tlb. 3169 */ 3170 *ptep = 0; 3171 PTE_SYNC_CURRENT(pm, ptep); 3172 continue; 3173 } 3174 3175 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3176 /* Add to the clean list. */ 3177 cleanlist[cleanlist_idx].ptep = ptep; 3178 cleanlist[cleanlist_idx].va = 3179 sva | (is_exec & 1); 3180 cleanlist_idx++; 3181 } else 3182 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3183 /* Nuke everything if needed. */ 3184 #ifdef PMAP_CACHE_VIVT 3185 pmap_idcache_wbinv_all(pm); 3186 #endif 3187 pmap_tlb_flushID(pm); 3188 3189 /* 3190 * Roll back the previous PTE list, 3191 * and zero out the current PTE. 3192 */ 3193 for (cnt = 0; 3194 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3195 *cleanlist[cnt].ptep = 0; 3196 PTE_SYNC(cleanlist[cnt].ptep); 3197 } 3198 *ptep = 0; 3199 PTE_SYNC(ptep); 3200 cleanlist_idx++; 3201 pm->pm_remove_all = true; 3202 } else { 3203 *ptep = 0; 3204 PTE_SYNC(ptep); 3205 if (pm->pm_remove_all == false) { 3206 if (is_exec) 3207 pmap_tlb_flushID_SE(pm, sva); 3208 else 3209 if (is_refd) 3210 pmap_tlb_flushD_SE(pm, sva); 3211 } 3212 } 3213 } 3214 3215 /* 3216 * Deal with any left overs 3217 */ 3218 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3219 total += cleanlist_idx; 3220 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3221 if (pm->pm_cstate.cs_all != 0) { 3222 vaddr_t clva = cleanlist[cnt].va & ~1; 3223 if (cleanlist[cnt].va & 1) { 3224 #ifdef PMAP_CACHE_VIVT 3225 pmap_idcache_wbinv_range(pm, 3226 clva, PAGE_SIZE); 3227 #endif 3228 pmap_tlb_flushID_SE(pm, clva); 3229 } else { 3230 #ifdef PMAP_CACHE_VIVT 3231 pmap_dcache_wb_range(pm, 3232 clva, PAGE_SIZE, true, 3233 false); 3234 #endif 3235 pmap_tlb_flushD_SE(pm, clva); 3236 } 3237 } 3238 *cleanlist[cnt].ptep = 0; 3239 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3240 } 3241 3242 /* 3243 * If it looks like we're removing a whole bunch 3244 * of mappings, it's faster to just write-back 3245 * the whole cache now and defer TLB flushes until 3246 * pmap_update() is called. 3247 */ 3248 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3249 cleanlist_idx = 0; 3250 else { 3251 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3252 #ifdef PMAP_CACHE_VIVT 3253 pmap_idcache_wbinv_all(pm); 3254 #endif 3255 pm->pm_remove_all = true; 3256 } 3257 } 3258 3259 pmap_free_l2_bucket(pm, l2b, mappings); 3260 pm->pm_stats.resident_count -= mappings; 3261 } 3262 3263 pmap_release_pmap_lock(pm); 3264 PMAP_MAP_TO_HEAD_UNLOCK(); 3265 } 3266 3267 #ifdef PMAP_CACHE_VIPT 3268 static struct pv_entry * 3269 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3270 { 3271 struct pv_entry *pv; 3272 3273 simple_lock(&pg->mdpage.pvh_slock); 3274 KASSERT(pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 3275 KASSERT((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3276 3277 pv = pmap_remove_pv(pg, pmap_kernel(), va); 3278 KASSERT(pv); 3279 KASSERT(pv->pv_flags & PVF_KENTRY); 3280 3281 /* 3282 * If we are removing a writeable mapping to a cached exec page, 3283 * if it's the last mapping then clear it execness other sync 3284 * the page to the icache. 3285 */ 3286 if ((pg->mdpage.pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3287 && (pv->pv_flags & PVF_WRITE) != 0) { 3288 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 3289 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 3290 PMAPCOUNT(exec_discarded_kremove); 3291 } else { 3292 pmap_syncicache_page(pg); 3293 PMAPCOUNT(exec_synced_kremove); 3294 } 3295 } 3296 pmap_vac_me_harder(pg, pmap_kernel(), 0); 3297 simple_unlock(&pg->mdpage.pvh_slock); 3298 3299 return pv; 3300 } 3301 #endif /* PMAP_CACHE_VIPT */ 3302 3303 /* 3304 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3305 * 3306 * We assume there is already sufficient KVM space available 3307 * to do this, as we can't allocate L2 descriptor tables/metadata 3308 * from here. 3309 */ 3310 void 3311 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3312 { 3313 struct l2_bucket *l2b; 3314 pt_entry_t *ptep, opte; 3315 #ifdef PMAP_CACHE_VIVT 3316 struct vm_page *pg = (prot & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3317 #endif 3318 #ifdef PMAP_CACHE_VIPT 3319 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3320 struct vm_page *opg; 3321 struct pv_entry *pv = NULL; 3322 #endif 3323 3324 NPDEBUG(PDB_KENTER, 3325 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3326 va, pa, prot)); 3327 3328 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3329 KDASSERT(l2b != NULL); 3330 3331 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3332 opte = *ptep; 3333 3334 if (opte == 0) { 3335 PMAPCOUNT(kenter_mappings); 3336 l2b->l2b_occupancy++; 3337 } else { 3338 PMAPCOUNT(kenter_remappings); 3339 #ifdef PMAP_CACHE_VIPT 3340 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3341 if (opg) { 3342 KASSERT(opg != pg); 3343 KASSERT((opg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3344 KASSERT((prot & PMAP_KMPAGE) == 0); 3345 simple_lock(&opg->mdpage.pvh_slock); 3346 pv = pmap_kremove_pg(opg, va); 3347 simple_unlock(&opg->mdpage.pvh_slock); 3348 } 3349 #endif 3350 if (l2pte_valid(opte)) { 3351 #ifdef PMAP_CACHE_VIVT 3352 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3353 #endif 3354 cpu_tlb_flushD_SE(va); 3355 cpu_cpwait(); 3356 } 3357 } 3358 3359 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3360 pte_l2_s_cache_mode; 3361 PTE_SYNC(ptep); 3362 3363 if (pg) { 3364 if (prot & PMAP_KMPAGE) { 3365 simple_lock(&pg->mdpage.pvh_slock); 3366 KASSERT(pg->mdpage.urw_mappings == 0); 3367 KASSERT(pg->mdpage.uro_mappings == 0); 3368 KASSERT(pg->mdpage.krw_mappings == 0); 3369 KASSERT(pg->mdpage.kro_mappings == 0); 3370 #ifdef PMAP_CACHE_VIPT 3371 KASSERT(pv == NULL); 3372 KASSERT((va & PVF_COLORED) == 0); 3373 KASSERT((pg->mdpage.pvh_attrs & PVF_NC) == 0); 3374 /* if there is a color conflict, evict from cache. */ 3375 if (pmap_is_page_colored_p(pg) 3376 && ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask)) { 3377 PMAPCOUNT(vac_color_change); 3378 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 3379 } else if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 3380 /* 3381 * If this page has multiple colors, expunge 3382 * them. 3383 */ 3384 PMAPCOUNT(vac_flush_lots2); 3385 pmap_flush_page(pg, PMAP_FLUSH_SECONDARY); 3386 } 3387 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 3388 pg->mdpage.pvh_attrs |= PVF_KMPAGE 3389 | PVF_COLORED | PVF_DIRTY 3390 | (va & arm_cache_prefer_mask); 3391 #endif 3392 #ifdef PMAP_CACHE_VIVT 3393 pg->mdpage.pvh_attrs |= PVF_KMPAGE; 3394 #endif 3395 pmap_kmpages++; 3396 simple_unlock(&pg->mdpage.pvh_slock); 3397 #ifdef PMAP_CACHE_VIPT 3398 } else { 3399 if (pv == NULL) { 3400 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3401 KASSERT(pv != NULL); 3402 } 3403 pmap_enter_pv(pg, pv, pmap_kernel(), va, 3404 PVF_WIRED | PVF_KENTRY 3405 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3406 if ((prot & VM_PROT_WRITE) 3407 && !(pg->mdpage.pvh_attrs & PVF_NC)) 3408 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3409 KASSERT((prot & VM_PROT_WRITE) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3410 simple_lock(&pg->mdpage.pvh_slock); 3411 pmap_vac_me_harder(pg, pmap_kernel(), va); 3412 simple_unlock(&pg->mdpage.pvh_slock); 3413 #endif 3414 } 3415 #ifdef PMAP_CACHE_VIPT 3416 } else { 3417 if (pv != NULL) 3418 pool_put(&pmap_pv_pool, pv); 3419 #endif 3420 } 3421 } 3422 3423 void 3424 pmap_kremove(vaddr_t va, vsize_t len) 3425 { 3426 struct l2_bucket *l2b; 3427 pt_entry_t *ptep, *sptep, opte; 3428 vaddr_t next_bucket, eva; 3429 u_int mappings; 3430 struct vm_page *opg; 3431 3432 PMAPCOUNT(kenter_unmappings); 3433 3434 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3435 va, len)); 3436 3437 eva = va + len; 3438 3439 while (va < eva) { 3440 next_bucket = L2_NEXT_BUCKET(va); 3441 if (next_bucket > eva) 3442 next_bucket = eva; 3443 3444 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3445 KDASSERT(l2b != NULL); 3446 3447 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3448 mappings = 0; 3449 3450 while (va < next_bucket) { 3451 opte = *ptep; 3452 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3453 if (opg) { 3454 if (opg->mdpage.pvh_attrs & PVF_KMPAGE) { 3455 simple_lock(&opg->mdpage.pvh_slock); 3456 KASSERT(opg->mdpage.urw_mappings == 0); 3457 KASSERT(opg->mdpage.uro_mappings == 0); 3458 KASSERT(opg->mdpage.krw_mappings == 0); 3459 KASSERT(opg->mdpage.kro_mappings == 0); 3460 opg->mdpage.pvh_attrs &= ~PVF_KMPAGE; 3461 #ifdef PMAP_CACHE_VIPT 3462 opg->mdpage.pvh_attrs &= ~PVF_WRITE; 3463 #endif 3464 pmap_kmpages--; 3465 simple_unlock(&opg->mdpage.pvh_slock); 3466 #ifdef PMAP_CACHE_VIPT 3467 } else { 3468 pool_put(&pmap_pv_pool, 3469 pmap_kremove_pg(opg, va)); 3470 #endif 3471 } 3472 } 3473 if (l2pte_valid(opte)) { 3474 #ifdef PMAP_CACHE_VIVT 3475 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3476 #endif 3477 cpu_tlb_flushD_SE(va); 3478 } 3479 if (opte) { 3480 *ptep = 0; 3481 mappings++; 3482 } 3483 va += PAGE_SIZE; 3484 ptep++; 3485 } 3486 KDASSERT(mappings <= l2b->l2b_occupancy); 3487 l2b->l2b_occupancy -= mappings; 3488 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3489 } 3490 cpu_cpwait(); 3491 } 3492 3493 bool 3494 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3495 { 3496 struct l2_dtable *l2; 3497 pd_entry_t *pl1pd, l1pd; 3498 pt_entry_t *ptep, pte; 3499 paddr_t pa; 3500 u_int l1idx; 3501 3502 pmap_acquire_pmap_lock(pm); 3503 3504 l1idx = L1_IDX(va); 3505 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3506 l1pd = *pl1pd; 3507 3508 if (l1pte_section_p(l1pd)) { 3509 /* 3510 * These should only happen for pmap_kernel() 3511 */ 3512 KDASSERT(pm == pmap_kernel()); 3513 pmap_release_pmap_lock(pm); 3514 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3515 } else { 3516 /* 3517 * Note that we can't rely on the validity of the L1 3518 * descriptor as an indication that a mapping exists. 3519 * We have to look it up in the L2 dtable. 3520 */ 3521 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3522 3523 if (l2 == NULL || 3524 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3525 pmap_release_pmap_lock(pm); 3526 return false; 3527 } 3528 3529 ptep = &ptep[l2pte_index(va)]; 3530 pte = *ptep; 3531 pmap_release_pmap_lock(pm); 3532 3533 if (pte == 0) 3534 return false; 3535 3536 switch (pte & L2_TYPE_MASK) { 3537 case L2_TYPE_L: 3538 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3539 break; 3540 3541 default: 3542 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3543 break; 3544 } 3545 } 3546 3547 if (pap != NULL) 3548 *pap = pa; 3549 3550 return true; 3551 } 3552 3553 void 3554 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3555 { 3556 struct l2_bucket *l2b; 3557 pt_entry_t *ptep, pte; 3558 vaddr_t next_bucket; 3559 u_int flags; 3560 u_int clr_mask; 3561 int flush; 3562 3563 NPDEBUG(PDB_PROTECT, 3564 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3565 pm, sva, eva, prot)); 3566 3567 if ((prot & VM_PROT_READ) == 0) { 3568 pmap_remove(pm, sva, eva); 3569 return; 3570 } 3571 3572 if (prot & VM_PROT_WRITE) { 3573 /* 3574 * If this is a read->write transition, just ignore it and let 3575 * uvm_fault() take care of it later. 3576 */ 3577 return; 3578 } 3579 3580 PMAP_MAP_TO_HEAD_LOCK(); 3581 pmap_acquire_pmap_lock(pm); 3582 3583 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3584 flags = 0; 3585 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3586 3587 while (sva < eva) { 3588 next_bucket = L2_NEXT_BUCKET(sva); 3589 if (next_bucket > eva) 3590 next_bucket = eva; 3591 3592 l2b = pmap_get_l2_bucket(pm, sva); 3593 if (l2b == NULL) { 3594 sva = next_bucket; 3595 continue; 3596 } 3597 3598 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3599 3600 while (sva < next_bucket) { 3601 pte = *ptep; 3602 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3603 struct vm_page *pg; 3604 u_int f; 3605 3606 #ifdef PMAP_CACHE_VIVT 3607 /* 3608 * OK, at this point, we know we're doing 3609 * write-protect operation. If the pmap is 3610 * active, write-back the page. 3611 */ 3612 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3613 false, false); 3614 #endif 3615 3616 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3617 pte &= ~L2_S_PROT_W; 3618 *ptep = pte; 3619 PTE_SYNC(ptep); 3620 3621 if (pg != NULL) { 3622 simple_lock(&pg->mdpage.pvh_slock); 3623 f = pmap_modify_pv(pg, pm, sva, 3624 clr_mask, 0); 3625 pmap_vac_me_harder(pg, pm, sva); 3626 simple_unlock(&pg->mdpage.pvh_slock); 3627 } else 3628 f = PVF_REF | PVF_EXEC; 3629 3630 if (flush >= 0) { 3631 flush++; 3632 flags |= f; 3633 } else 3634 if (PV_BEEN_EXECD(f)) 3635 pmap_tlb_flushID_SE(pm, sva); 3636 else 3637 if (PV_BEEN_REFD(f)) 3638 pmap_tlb_flushD_SE(pm, sva); 3639 } 3640 3641 sva += PAGE_SIZE; 3642 ptep++; 3643 } 3644 } 3645 3646 pmap_release_pmap_lock(pm); 3647 PMAP_MAP_TO_HEAD_UNLOCK(); 3648 3649 if (flush) { 3650 if (PV_BEEN_EXECD(flags)) 3651 pmap_tlb_flushID(pm); 3652 else 3653 if (PV_BEEN_REFD(flags)) 3654 pmap_tlb_flushD(pm); 3655 } 3656 } 3657 3658 void 3659 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3660 { 3661 struct l2_bucket *l2b; 3662 pt_entry_t *ptep; 3663 vaddr_t next_bucket; 3664 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3665 3666 NPDEBUG(PDB_EXEC, 3667 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3668 pm, sva, eva)); 3669 3670 PMAP_MAP_TO_HEAD_LOCK(); 3671 pmap_acquire_pmap_lock(pm); 3672 3673 while (sva < eva) { 3674 next_bucket = L2_NEXT_BUCKET(sva); 3675 if (next_bucket > eva) 3676 next_bucket = eva; 3677 3678 l2b = pmap_get_l2_bucket(pm, sva); 3679 if (l2b == NULL) { 3680 sva = next_bucket; 3681 continue; 3682 } 3683 3684 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3685 sva < next_bucket; 3686 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3687 if (l2pte_valid(*ptep)) { 3688 cpu_icache_sync_range(sva, 3689 min(page_size, eva - sva)); 3690 } 3691 } 3692 } 3693 3694 pmap_release_pmap_lock(pm); 3695 PMAP_MAP_TO_HEAD_UNLOCK(); 3696 } 3697 3698 void 3699 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3700 { 3701 3702 NPDEBUG(PDB_PROTECT, 3703 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3704 pg, VM_PAGE_TO_PHYS(pg), prot)); 3705 3706 switch(prot) { 3707 return; 3708 case VM_PROT_READ|VM_PROT_WRITE: 3709 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3710 pmap_clearbit(pg, PVF_EXEC); 3711 break; 3712 #endif 3713 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3714 break; 3715 3716 case VM_PROT_READ: 3717 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3718 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3719 break; 3720 #endif 3721 case VM_PROT_READ|VM_PROT_EXECUTE: 3722 pmap_clearbit(pg, PVF_WRITE); 3723 break; 3724 3725 default: 3726 pmap_page_remove(pg); 3727 break; 3728 } 3729 } 3730 3731 /* 3732 * pmap_clear_modify: 3733 * 3734 * Clear the "modified" attribute for a page. 3735 */ 3736 bool 3737 pmap_clear_modify(struct vm_page *pg) 3738 { 3739 bool rv; 3740 3741 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3742 rv = true; 3743 #ifdef PMAP_CACHE_VIPT 3744 /* 3745 * If we are going to clear the modified bit and there are 3746 * no other modified bits set, flush the page to memory and 3747 * mark it clean. 3748 */ 3749 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3750 pmap_flush_page(pg, PMAP_CLEAN_PRIMARY); 3751 #endif 3752 pmap_clearbit(pg, PVF_MOD); 3753 } else 3754 rv = false; 3755 3756 return (rv); 3757 } 3758 3759 /* 3760 * pmap_clear_reference: 3761 * 3762 * Clear the "referenced" attribute for a page. 3763 */ 3764 bool 3765 pmap_clear_reference(struct vm_page *pg) 3766 { 3767 bool rv; 3768 3769 if (pg->mdpage.pvh_attrs & PVF_REF) { 3770 rv = true; 3771 pmap_clearbit(pg, PVF_REF); 3772 } else 3773 rv = false; 3774 3775 return (rv); 3776 } 3777 3778 /* 3779 * pmap_is_modified: 3780 * 3781 * Test if a page has the "modified" attribute. 3782 */ 3783 /* See <arm/arm32/pmap.h> */ 3784 3785 /* 3786 * pmap_is_referenced: 3787 * 3788 * Test if a page has the "referenced" attribute. 3789 */ 3790 /* See <arm/arm32/pmap.h> */ 3791 3792 int 3793 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3794 { 3795 struct l2_dtable *l2; 3796 struct l2_bucket *l2b; 3797 pd_entry_t *pl1pd, l1pd; 3798 pt_entry_t *ptep, pte; 3799 paddr_t pa; 3800 u_int l1idx; 3801 int rv = 0; 3802 3803 PMAP_MAP_TO_HEAD_LOCK(); 3804 pmap_acquire_pmap_lock(pm); 3805 3806 l1idx = L1_IDX(va); 3807 3808 /* 3809 * If there is no l2_dtable for this address, then the process 3810 * has no business accessing it. 3811 * 3812 * Note: This will catch userland processes trying to access 3813 * kernel addresses. 3814 */ 3815 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3816 if (l2 == NULL) 3817 goto out; 3818 3819 /* 3820 * Likewise if there is no L2 descriptor table 3821 */ 3822 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3823 if (l2b->l2b_kva == NULL) 3824 goto out; 3825 3826 /* 3827 * Check the PTE itself. 3828 */ 3829 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3830 pte = *ptep; 3831 if (pte == 0) 3832 goto out; 3833 3834 /* 3835 * Catch a userland access to the vector page mapped at 0x0 3836 */ 3837 if (user && (pte & L2_S_PROT_U) == 0) 3838 goto out; 3839 3840 pa = l2pte_pa(pte); 3841 3842 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3843 /* 3844 * This looks like a good candidate for "page modified" 3845 * emulation... 3846 */ 3847 struct pv_entry *pv; 3848 struct vm_page *pg; 3849 3850 /* Extract the physical address of the page */ 3851 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3852 goto out; 3853 3854 /* Get the current flags for this page. */ 3855 simple_lock(&pg->mdpage.pvh_slock); 3856 3857 pv = pmap_find_pv(pg, pm, va); 3858 if (pv == NULL) { 3859 simple_unlock(&pg->mdpage.pvh_slock); 3860 goto out; 3861 } 3862 3863 /* 3864 * Do the flags say this page is writable? If not then it 3865 * is a genuine write fault. If yes then the write fault is 3866 * our fault as we did not reflect the write access in the 3867 * PTE. Now we know a write has occurred we can correct this 3868 * and also set the modified bit 3869 */ 3870 if ((pv->pv_flags & PVF_WRITE) == 0) { 3871 simple_unlock(&pg->mdpage.pvh_slock); 3872 goto out; 3873 } 3874 3875 NPDEBUG(PDB_FOLLOW, 3876 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3877 pm, va, VM_PAGE_TO_PHYS(pg))); 3878 3879 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 3880 pv->pv_flags |= PVF_REF | PVF_MOD; 3881 #ifdef PMAP_CACHE_VIPT 3882 /* 3883 * If there are cacheable mappings for this page, mark it dirty. 3884 */ 3885 if ((pg->mdpage.pvh_attrs & PVF_NC) == 0) 3886 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3887 #endif 3888 simple_unlock(&pg->mdpage.pvh_slock); 3889 3890 /* 3891 * Re-enable write permissions for the page. No need to call 3892 * pmap_vac_me_harder(), since this is just a 3893 * modified-emulation fault, and the PVF_WRITE bit isn't 3894 * changing. We've already set the cacheable bits based on 3895 * the assumption that we can write to this page. 3896 */ 3897 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3898 PTE_SYNC(ptep); 3899 rv = 1; 3900 } else 3901 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3902 /* 3903 * This looks like a good candidate for "page referenced" 3904 * emulation. 3905 */ 3906 struct pv_entry *pv; 3907 struct vm_page *pg; 3908 3909 /* Extract the physical address of the page */ 3910 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3911 goto out; 3912 3913 /* Get the current flags for this page. */ 3914 simple_lock(&pg->mdpage.pvh_slock); 3915 3916 pv = pmap_find_pv(pg, pm, va); 3917 if (pv == NULL) { 3918 simple_unlock(&pg->mdpage.pvh_slock); 3919 goto out; 3920 } 3921 3922 pg->mdpage.pvh_attrs |= PVF_REF; 3923 pv->pv_flags |= PVF_REF; 3924 simple_unlock(&pg->mdpage.pvh_slock); 3925 3926 NPDEBUG(PDB_FOLLOW, 3927 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3928 pm, va, VM_PAGE_TO_PHYS(pg))); 3929 3930 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3931 PTE_SYNC(ptep); 3932 rv = 1; 3933 } 3934 3935 /* 3936 * We know there is a valid mapping here, so simply 3937 * fix up the L1 if necessary. 3938 */ 3939 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3940 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3941 if (*pl1pd != l1pd) { 3942 *pl1pd = l1pd; 3943 PTE_SYNC(pl1pd); 3944 rv = 1; 3945 } 3946 3947 #ifdef CPU_SA110 3948 /* 3949 * There are bugs in the rev K SA110. This is a check for one 3950 * of them. 3951 */ 3952 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3953 curcpu()->ci_arm_cpurev < 3) { 3954 /* Always current pmap */ 3955 if (l2pte_valid(pte)) { 3956 extern int kernel_debug; 3957 if (kernel_debug & 1) { 3958 struct proc *p = curlwp->l_proc; 3959 printf("prefetch_abort: page is already " 3960 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3961 printf("prefetch_abort: pc=%08lx proc=%p " 3962 "process=%s\n", va, p, p->p_comm); 3963 printf("prefetch_abort: far=%08x fs=%x\n", 3964 cpu_faultaddress(), cpu_faultstatus()); 3965 } 3966 #ifdef DDB 3967 if (kernel_debug & 2) 3968 Debugger(); 3969 #endif 3970 rv = 1; 3971 } 3972 } 3973 #endif /* CPU_SA110 */ 3974 3975 #ifdef DEBUG 3976 /* 3977 * If 'rv == 0' at this point, it generally indicates that there is a 3978 * stale TLB entry for the faulting address. This happens when two or 3979 * more processes are sharing an L1. Since we don't flush the TLB on 3980 * a context switch between such processes, we can take domain faults 3981 * for mappings which exist at the same VA in both processes. EVEN IF 3982 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3983 * example. 3984 * 3985 * This is extremely likely to happen if pmap_enter() updated the L1 3986 * entry for a recently entered mapping. In this case, the TLB is 3987 * flushed for the new mapping, but there may still be TLB entries for 3988 * other mappings belonging to other processes in the 1MB range 3989 * covered by the L1 entry. 3990 * 3991 * Since 'rv == 0', we know that the L1 already contains the correct 3992 * value, so the fault must be due to a stale TLB entry. 3993 * 3994 * Since we always need to flush the TLB anyway in the case where we 3995 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 3996 * stale TLB entries dynamically. 3997 * 3998 * However, the above condition can ONLY happen if the current L1 is 3999 * being shared. If it happens when the L1 is unshared, it indicates 4000 * that other parts of the pmap are not doing their job WRT managing 4001 * the TLB. 4002 */ 4003 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4004 extern int last_fault_code; 4005 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4006 pm, va, ftype); 4007 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4008 l2, l2b, ptep, pl1pd); 4009 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4010 pte, l1pd, last_fault_code); 4011 #ifdef DDB 4012 Debugger(); 4013 #endif 4014 } 4015 #endif 4016 4017 cpu_tlb_flushID_SE(va); 4018 cpu_cpwait(); 4019 4020 rv = 1; 4021 4022 out: 4023 pmap_release_pmap_lock(pm); 4024 PMAP_MAP_TO_HEAD_UNLOCK(); 4025 4026 return (rv); 4027 } 4028 4029 /* 4030 * Routine: pmap_procwr 4031 * 4032 * Function: 4033 * Synchronize caches corresponding to [addr, addr+len) in p. 4034 * 4035 */ 4036 void 4037 pmap_procwr(struct proc *p, vaddr_t va, int len) 4038 { 4039 /* We only need to do anything if it is the current process. */ 4040 if (p == curproc) 4041 cpu_icache_sync_range(va, len); 4042 } 4043 4044 /* 4045 * Routine: pmap_unwire 4046 * Function: Clear the wired attribute for a map/virtual-address pair. 4047 * 4048 * In/out conditions: 4049 * The mapping must already exist in the pmap. 4050 */ 4051 void 4052 pmap_unwire(pmap_t pm, vaddr_t va) 4053 { 4054 struct l2_bucket *l2b; 4055 pt_entry_t *ptep, pte; 4056 struct vm_page *pg; 4057 paddr_t pa; 4058 4059 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4060 4061 PMAP_MAP_TO_HEAD_LOCK(); 4062 pmap_acquire_pmap_lock(pm); 4063 4064 l2b = pmap_get_l2_bucket(pm, va); 4065 KDASSERT(l2b != NULL); 4066 4067 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4068 pte = *ptep; 4069 4070 /* Extract the physical address of the page */ 4071 pa = l2pte_pa(pte); 4072 4073 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4074 /* Update the wired bit in the pv entry for this page. */ 4075 simple_lock(&pg->mdpage.pvh_slock); 4076 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 4077 simple_unlock(&pg->mdpage.pvh_slock); 4078 } 4079 4080 pmap_release_pmap_lock(pm); 4081 PMAP_MAP_TO_HEAD_UNLOCK(); 4082 } 4083 4084 void 4085 pmap_activate(struct lwp *l) 4086 { 4087 extern int block_userspace_access; 4088 pmap_t opm, npm, rpm; 4089 uint32_t odacr, ndacr; 4090 int oldirqstate; 4091 4092 /* 4093 * If activating a non-current lwp or the current lwp is 4094 * already active, just return. 4095 */ 4096 if (l != curlwp || 4097 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4098 return; 4099 4100 npm = l->l_proc->p_vmspace->vm_map.pmap; 4101 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4102 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4103 4104 /* 4105 * If TTB and DACR are unchanged, short-circuit all the 4106 * TLB/cache management stuff. 4107 */ 4108 if (pmap_previous_active_lwp != NULL) { 4109 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4110 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4111 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4112 4113 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4114 goto all_done; 4115 } else 4116 opm = NULL; 4117 4118 PMAPCOUNT(activations); 4119 block_userspace_access = 1; 4120 4121 /* 4122 * If switching to a user vmspace which is different to the 4123 * most recent one, and the most recent one is potentially 4124 * live in the cache, we must write-back and invalidate the 4125 * entire cache. 4126 */ 4127 rpm = pmap_recent_user; 4128 if (npm != pmap_kernel() && rpm && npm != rpm && 4129 rpm->pm_cstate.cs_cache) { 4130 rpm->pm_cstate.cs_cache = 0; 4131 #ifdef PMAP_CACHE_VIVT 4132 cpu_idcache_wbinv_all(); 4133 #endif 4134 } 4135 4136 /* No interrupts while we frob the TTB/DACR */ 4137 oldirqstate = disable_interrupts(IF32_bits); 4138 4139 /* 4140 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4141 * entry corresponding to 'vector_page' in the incoming L1 table 4142 * before switching to it otherwise subsequent interrupts/exceptions 4143 * (including domain faults!) will jump into hyperspace. 4144 */ 4145 if (npm->pm_pl1vec != NULL) { 4146 cpu_tlb_flushID_SE((u_int)vector_page); 4147 cpu_cpwait(); 4148 *npm->pm_pl1vec = npm->pm_l1vec; 4149 PTE_SYNC(npm->pm_pl1vec); 4150 } 4151 4152 cpu_domains(ndacr); 4153 4154 if (npm == pmap_kernel() || npm == rpm) { 4155 /* 4156 * Switching to a kernel thread, or back to the 4157 * same user vmspace as before... Simply update 4158 * the TTB (no TLB flush required) 4159 */ 4160 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4161 "r"(npm->pm_l1->l1_physaddr)); 4162 cpu_cpwait(); 4163 } else { 4164 /* 4165 * Otherwise, update TTB and flush TLB 4166 */ 4167 cpu_context_switch(npm->pm_l1->l1_physaddr); 4168 if (rpm != NULL) 4169 rpm->pm_cstate.cs_tlb = 0; 4170 } 4171 4172 restore_interrupts(oldirqstate); 4173 4174 block_userspace_access = 0; 4175 4176 all_done: 4177 /* 4178 * The new pmap is resident. Make sure it's marked 4179 * as resident in the cache/TLB. 4180 */ 4181 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4182 if (npm != pmap_kernel()) 4183 pmap_recent_user = npm; 4184 4185 /* The old pmap is not longer active */ 4186 if (opm != NULL) 4187 opm->pm_activated = false; 4188 4189 /* But the new one is */ 4190 npm->pm_activated = true; 4191 } 4192 4193 void 4194 pmap_deactivate(struct lwp *l) 4195 { 4196 4197 /* 4198 * If the process is exiting, make sure pmap_activate() does 4199 * a full MMU context-switch and cache flush, which we might 4200 * otherwise skip. See PR port-arm/38950. 4201 */ 4202 if (l->l_proc->p_sflag & PS_WEXIT) 4203 pmap_previous_active_lwp = NULL; 4204 4205 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4206 } 4207 4208 void 4209 pmap_update(pmap_t pm) 4210 { 4211 4212 if (pm->pm_remove_all) { 4213 /* 4214 * Finish up the pmap_remove_all() optimisation by flushing 4215 * the TLB. 4216 */ 4217 pmap_tlb_flushID(pm); 4218 pm->pm_remove_all = false; 4219 } 4220 4221 if (pmap_is_current(pm)) { 4222 /* 4223 * If we're dealing with a current userland pmap, move its L1 4224 * to the end of the LRU. 4225 */ 4226 if (pm != pmap_kernel()) 4227 pmap_use_l1(pm); 4228 4229 /* 4230 * We can assume we're done with frobbing the cache/tlb for 4231 * now. Make sure any future pmap ops don't skip cache/tlb 4232 * flushes. 4233 */ 4234 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4235 } 4236 4237 PMAPCOUNT(updates); 4238 4239 /* 4240 * make sure TLB/cache operations have completed. 4241 */ 4242 cpu_cpwait(); 4243 } 4244 4245 void 4246 pmap_remove_all(pmap_t pm) 4247 { 4248 4249 /* 4250 * The vmspace described by this pmap is about to be torn down. 4251 * Until pmap_update() is called, UVM will only make calls 4252 * to pmap_remove(). We can make life much simpler by flushing 4253 * the cache now, and deferring TLB invalidation to pmap_update(). 4254 */ 4255 #ifdef PMAP_CACHE_VIVT 4256 pmap_idcache_wbinv_all(pm); 4257 #endif 4258 pm->pm_remove_all = true; 4259 } 4260 4261 /* 4262 * Retire the given physical map from service. 4263 * Should only be called if the map contains no valid mappings. 4264 */ 4265 void 4266 pmap_destroy(pmap_t pm) 4267 { 4268 u_int count; 4269 4270 if (pm == NULL) 4271 return; 4272 4273 if (pm->pm_remove_all) { 4274 pmap_tlb_flushID(pm); 4275 pm->pm_remove_all = false; 4276 } 4277 4278 /* 4279 * Drop reference count 4280 */ 4281 mutex_enter(&pm->pm_lock); 4282 count = --pm->pm_obj.uo_refs; 4283 mutex_exit(&pm->pm_lock); 4284 if (count > 0) { 4285 if (pmap_is_current(pm)) { 4286 if (pm != pmap_kernel()) 4287 pmap_use_l1(pm); 4288 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4289 } 4290 return; 4291 } 4292 4293 /* 4294 * reference count is zero, free pmap resources and then free pmap. 4295 */ 4296 4297 if (vector_page < KERNEL_BASE) { 4298 KDASSERT(!pmap_is_current(pm)); 4299 4300 /* Remove the vector page mapping */ 4301 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4302 pmap_update(pm); 4303 } 4304 4305 LIST_REMOVE(pm, pm_list); 4306 4307 pmap_free_l1(pm); 4308 4309 if (pmap_recent_user == pm) 4310 pmap_recent_user = NULL; 4311 4312 UVM_OBJ_DESTROY(&pm->pm_obj); 4313 4314 /* return the pmap to the pool */ 4315 pool_cache_put(&pmap_cache, pm); 4316 } 4317 4318 4319 /* 4320 * void pmap_reference(pmap_t pm) 4321 * 4322 * Add a reference to the specified pmap. 4323 */ 4324 void 4325 pmap_reference(pmap_t pm) 4326 { 4327 4328 if (pm == NULL) 4329 return; 4330 4331 pmap_use_l1(pm); 4332 4333 mutex_enter(&pm->pm_lock); 4334 pm->pm_obj.uo_refs++; 4335 mutex_exit(&pm->pm_lock); 4336 } 4337 4338 #if ARM_MMU_V6 > 0 4339 4340 static struct evcnt pmap_prefer_nochange_ev = 4341 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4342 static struct evcnt pmap_prefer_change_ev = 4343 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4344 4345 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4346 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4347 4348 void 4349 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4350 { 4351 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4352 vaddr_t va = *vap; 4353 vaddr_t diff = (hint - va) & mask; 4354 if (diff == 0) { 4355 pmap_prefer_nochange_ev.ev_count++; 4356 } else { 4357 pmap_prefer_change_ev.ev_count++; 4358 if (__predict_false(td)) 4359 va -= mask + 1; 4360 *vap = va + diff; 4361 } 4362 } 4363 #endif /* ARM_MMU_V6 */ 4364 4365 /* 4366 * pmap_zero_page() 4367 * 4368 * Zero a given physical page by mapping it at a page hook point. 4369 * In doing the zero page op, the page we zero is mapped cachable, as with 4370 * StrongARM accesses to non-cached pages are non-burst making writing 4371 * _any_ bulk data very slow. 4372 */ 4373 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4374 void 4375 pmap_zero_page_generic(paddr_t phys) 4376 { 4377 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4378 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4379 #endif 4380 #ifdef PMAP_CACHE_VIPT 4381 /* Choose the last page color it had, if any */ 4382 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4383 #else 4384 const vsize_t va_offset = 0; 4385 #endif 4386 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4387 4388 #ifdef DEBUG 4389 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4390 panic("pmap_zero_page: page has mappings"); 4391 #endif 4392 4393 KDASSERT((phys & PGOFSET) == 0); 4394 4395 /* 4396 * Hook in the page, zero it, and purge the cache for that 4397 * zeroed page. Invalidate the TLB as needed. 4398 */ 4399 *ptep = L2_S_PROTO | phys | 4400 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4401 PTE_SYNC(ptep); 4402 cpu_tlb_flushD_SE(cdstp + va_offset); 4403 cpu_cpwait(); 4404 bzero_page(cdstp + va_offset); 4405 /* 4406 * Unmap the page. 4407 */ 4408 *ptep = 0; 4409 PTE_SYNC(ptep); 4410 cpu_tlb_flushD_SE(cdstp + va_offset); 4411 #ifdef PMAP_CACHE_VIVT 4412 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4413 #endif 4414 #ifdef PMAP_CACHE_VIPT 4415 /* 4416 * This page is now cache resident so it now has a page color. 4417 * Any contents have been obliterated so clear the EXEC flag. 4418 */ 4419 if (!pmap_is_page_colored_p(pg)) { 4420 PMAPCOUNT(vac_color_new); 4421 pg->mdpage.pvh_attrs |= PVF_COLORED; 4422 } 4423 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4424 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4425 PMAPCOUNT(exec_discarded_zero); 4426 } 4427 pg->mdpage.pvh_attrs |= PVF_DIRTY; 4428 #endif 4429 } 4430 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4431 4432 #if ARM_MMU_XSCALE == 1 4433 void 4434 pmap_zero_page_xscale(paddr_t phys) 4435 { 4436 #ifdef DEBUG 4437 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4438 4439 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4440 panic("pmap_zero_page: page has mappings"); 4441 #endif 4442 4443 KDASSERT((phys & PGOFSET) == 0); 4444 4445 /* 4446 * Hook in the page, zero it, and purge the cache for that 4447 * zeroed page. Invalidate the TLB as needed. 4448 */ 4449 *cdst_pte = L2_S_PROTO | phys | 4450 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4451 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4452 PTE_SYNC(cdst_pte); 4453 cpu_tlb_flushD_SE(cdstp); 4454 cpu_cpwait(); 4455 bzero_page(cdstp); 4456 xscale_cache_clean_minidata(); 4457 } 4458 #endif /* ARM_MMU_XSCALE == 1 */ 4459 4460 /* pmap_pageidlezero() 4461 * 4462 * The same as above, except that we assume that the page is not 4463 * mapped. This means we never have to flush the cache first. Called 4464 * from the idle loop. 4465 */ 4466 bool 4467 pmap_pageidlezero(paddr_t phys) 4468 { 4469 unsigned int i; 4470 int *ptr; 4471 bool rv = true; 4472 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4473 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4474 #endif 4475 #ifdef PMAP_CACHE_VIPT 4476 /* Choose the last page color it had, if any */ 4477 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4478 #else 4479 const vsize_t va_offset = 0; 4480 #endif 4481 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4482 4483 4484 #ifdef DEBUG 4485 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4486 panic("pmap_pageidlezero: page has mappings"); 4487 #endif 4488 4489 KDASSERT((phys & PGOFSET) == 0); 4490 4491 /* 4492 * Hook in the page, zero it, and purge the cache for that 4493 * zeroed page. Invalidate the TLB as needed. 4494 */ 4495 *ptep = L2_S_PROTO | phys | 4496 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4497 PTE_SYNC(ptep); 4498 cpu_tlb_flushD_SE(cdstp + va_offset); 4499 cpu_cpwait(); 4500 4501 for (i = 0, ptr = (int *)(cdstp + va_offset); 4502 i < (PAGE_SIZE / sizeof(int)); i++) { 4503 if (sched_curcpu_runnable_p() != 0) { 4504 /* 4505 * A process has become ready. Abort now, 4506 * so we don't keep it waiting while we 4507 * do slow memory access to finish this 4508 * page. 4509 */ 4510 rv = false; 4511 break; 4512 } 4513 *ptr++ = 0; 4514 } 4515 4516 #ifdef PMAP_CACHE_VIVT 4517 if (rv) 4518 /* 4519 * if we aborted we'll rezero this page again later so don't 4520 * purge it unless we finished it 4521 */ 4522 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4523 #elif defined(PMAP_CACHE_VIPT) 4524 /* 4525 * This page is now cache resident so it now has a page color. 4526 * Any contents have been obliterated so clear the EXEC flag. 4527 */ 4528 if (!pmap_is_page_colored_p(pg)) { 4529 PMAPCOUNT(vac_color_new); 4530 pg->mdpage.pvh_attrs |= PVF_COLORED; 4531 } 4532 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4533 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4534 PMAPCOUNT(exec_discarded_zero); 4535 } 4536 #endif 4537 /* 4538 * Unmap the page. 4539 */ 4540 *ptep = 0; 4541 PTE_SYNC(ptep); 4542 cpu_tlb_flushD_SE(cdstp + va_offset); 4543 4544 return (rv); 4545 } 4546 4547 /* 4548 * pmap_copy_page() 4549 * 4550 * Copy one physical page into another, by mapping the pages into 4551 * hook points. The same comment regarding cachability as in 4552 * pmap_zero_page also applies here. 4553 */ 4554 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4555 void 4556 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4557 { 4558 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4559 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4560 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4561 #endif 4562 #ifdef PMAP_CACHE_VIPT 4563 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4564 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4565 #else 4566 const vsize_t src_va_offset = 0; 4567 const vsize_t dst_va_offset = 0; 4568 #endif 4569 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4570 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4571 4572 #ifdef DEBUG 4573 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4574 panic("pmap_copy_page: dst page has mappings"); 4575 #endif 4576 4577 #ifdef PMAP_CACHE_VIPT 4578 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4579 #endif 4580 KDASSERT((src & PGOFSET) == 0); 4581 KDASSERT((dst & PGOFSET) == 0); 4582 4583 /* 4584 * Clean the source page. Hold the source page's lock for 4585 * the duration of the copy so that no other mappings can 4586 * be created while we have a potentially aliased mapping. 4587 */ 4588 simple_lock(&src_pg->mdpage.pvh_slock); 4589 #ifdef PMAP_CACHE_VIVT 4590 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4591 #endif 4592 4593 /* 4594 * Map the pages into the page hook points, copy them, and purge 4595 * the cache for the appropriate page. Invalidate the TLB 4596 * as required. 4597 */ 4598 *src_ptep = L2_S_PROTO 4599 | src 4600 #ifdef PMAP_CACHE_VIPT 4601 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4602 #endif 4603 #ifdef PMAP_CACHE_VIVT 4604 | pte_l2_s_cache_mode 4605 #endif 4606 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4607 *dst_ptep = L2_S_PROTO | dst | 4608 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4609 PTE_SYNC(src_ptep); 4610 PTE_SYNC(dst_ptep); 4611 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4612 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4613 cpu_cpwait(); 4614 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4615 #ifdef PMAP_CACHE_VIVT 4616 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4617 #endif 4618 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4619 #ifdef PMAP_CACHE_VIVT 4620 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4621 #endif 4622 /* 4623 * Unmap the pages. 4624 */ 4625 *src_ptep = 0; 4626 *dst_ptep = 0; 4627 PTE_SYNC(src_ptep); 4628 PTE_SYNC(dst_ptep); 4629 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4630 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4631 #ifdef PMAP_CACHE_VIPT 4632 /* 4633 * Now that the destination page is in the cache, mark it as colored. 4634 * If this was an exec page, discard it. 4635 */ 4636 if (!pmap_is_page_colored_p(dst_pg)) { 4637 PMAPCOUNT(vac_color_new); 4638 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4639 } 4640 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4641 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4642 PMAPCOUNT(exec_discarded_copy); 4643 } 4644 dst_pg->mdpage.pvh_attrs |= PVF_DIRTY; 4645 #endif 4646 } 4647 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4648 4649 #if ARM_MMU_XSCALE == 1 4650 void 4651 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4652 { 4653 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4654 #ifdef DEBUG 4655 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4656 4657 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4658 panic("pmap_copy_page: dst page has mappings"); 4659 #endif 4660 4661 KDASSERT((src & PGOFSET) == 0); 4662 KDASSERT((dst & PGOFSET) == 0); 4663 4664 /* 4665 * Clean the source page. Hold the source page's lock for 4666 * the duration of the copy so that no other mappings can 4667 * be created while we have a potentially aliased mapping. 4668 */ 4669 simple_lock(&src_pg->mdpage.pvh_slock); 4670 #ifdef PMAP_CACHE_VIVT 4671 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4672 #endif 4673 4674 /* 4675 * Map the pages into the page hook points, copy them, and purge 4676 * the cache for the appropriate page. Invalidate the TLB 4677 * as required. 4678 */ 4679 *csrc_pte = L2_S_PROTO | src | 4680 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4681 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4682 PTE_SYNC(csrc_pte); 4683 *cdst_pte = L2_S_PROTO | dst | 4684 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4685 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4686 PTE_SYNC(cdst_pte); 4687 cpu_tlb_flushD_SE(csrcp); 4688 cpu_tlb_flushD_SE(cdstp); 4689 cpu_cpwait(); 4690 bcopy_page(csrcp, cdstp); 4691 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4692 xscale_cache_clean_minidata(); 4693 } 4694 #endif /* ARM_MMU_XSCALE == 1 */ 4695 4696 /* 4697 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4698 * 4699 * Return the start and end addresses of the kernel's virtual space. 4700 * These values are setup in pmap_bootstrap and are updated as pages 4701 * are allocated. 4702 */ 4703 void 4704 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4705 { 4706 *start = virtual_avail; 4707 *end = virtual_end; 4708 } 4709 4710 /* 4711 * Helper function for pmap_grow_l2_bucket() 4712 */ 4713 static inline int 4714 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4715 { 4716 struct l2_bucket *l2b; 4717 pt_entry_t *ptep; 4718 paddr_t pa; 4719 4720 if (uvm.page_init_done == false) { 4721 #ifdef PMAP_STEAL_MEMORY 4722 pv_addr_t pv; 4723 pmap_boot_pagealloc(PAGE_SIZE, 4724 #ifdef PMAP_CACHE_VIPT 4725 arm_cache_prefer_mask, 4726 va & arm_cache_prefer_mask, 4727 #else 4728 0, 0, 4729 #endif 4730 &pv); 4731 pa = pv.pv_pa; 4732 #else 4733 if (uvm_page_physget(&pa) == false) 4734 return (1); 4735 #endif /* PMAP_STEAL_MEMORY */ 4736 } else { 4737 struct vm_page *pg; 4738 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4739 if (pg == NULL) 4740 return (1); 4741 pa = VM_PAGE_TO_PHYS(pg); 4742 #ifdef PMAP_CACHE_VIPT 4743 /* 4744 * This new page must not have any mappings. Enter it via 4745 * pmap_kenter_pa and let that routine do the hard work. 4746 */ 4747 KASSERT(SLIST_EMPTY(&pg->mdpage.pvh_list)); 4748 pmap_kenter_pa(va, pa, 4749 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); 4750 #endif 4751 } 4752 4753 if (pap) 4754 *pap = pa; 4755 4756 PMAPCOUNT(pt_mappings); 4757 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4758 KDASSERT(l2b != NULL); 4759 4760 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4761 *ptep = L2_S_PROTO | pa | cache_mode | 4762 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4763 PTE_SYNC(ptep); 4764 memset((void *)va, 0, PAGE_SIZE); 4765 return (0); 4766 } 4767 4768 /* 4769 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4770 * used by pmap_growkernel(). 4771 */ 4772 static inline struct l2_bucket * 4773 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4774 { 4775 struct l2_dtable *l2; 4776 struct l2_bucket *l2b; 4777 u_short l1idx; 4778 vaddr_t nva; 4779 4780 l1idx = L1_IDX(va); 4781 4782 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4783 /* 4784 * No mapping at this address, as there is 4785 * no entry in the L1 table. 4786 * Need to allocate a new l2_dtable. 4787 */ 4788 nva = pmap_kernel_l2dtable_kva; 4789 if ((nva & PGOFSET) == 0) { 4790 /* 4791 * Need to allocate a backing page 4792 */ 4793 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4794 return (NULL); 4795 } 4796 4797 l2 = (struct l2_dtable *)nva; 4798 nva += sizeof(struct l2_dtable); 4799 4800 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4801 /* 4802 * The new l2_dtable straddles a page boundary. 4803 * Map in another page to cover it. 4804 */ 4805 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4806 return (NULL); 4807 } 4808 4809 pmap_kernel_l2dtable_kva = nva; 4810 4811 /* 4812 * Link it into the parent pmap 4813 */ 4814 pm->pm_l2[L2_IDX(l1idx)] = l2; 4815 } 4816 4817 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4818 4819 /* 4820 * Fetch pointer to the L2 page table associated with the address. 4821 */ 4822 if (l2b->l2b_kva == NULL) { 4823 pt_entry_t *ptep; 4824 4825 /* 4826 * No L2 page table has been allocated. Chances are, this 4827 * is because we just allocated the l2_dtable, above. 4828 */ 4829 nva = pmap_kernel_l2ptp_kva; 4830 ptep = (pt_entry_t *)nva; 4831 if ((nva & PGOFSET) == 0) { 4832 /* 4833 * Need to allocate a backing page 4834 */ 4835 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4836 &pmap_kernel_l2ptp_phys)) 4837 return (NULL); 4838 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4839 } 4840 4841 l2->l2_occupancy++; 4842 l2b->l2b_kva = ptep; 4843 l2b->l2b_l1idx = l1idx; 4844 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4845 4846 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4847 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4848 } 4849 4850 return (l2b); 4851 } 4852 4853 vaddr_t 4854 pmap_growkernel(vaddr_t maxkvaddr) 4855 { 4856 pmap_t kpm = pmap_kernel(); 4857 struct l1_ttable *l1; 4858 struct l2_bucket *l2b; 4859 pd_entry_t *pl1pd; 4860 int s; 4861 4862 if (maxkvaddr <= pmap_curmaxkvaddr) 4863 goto out; /* we are OK */ 4864 4865 NPDEBUG(PDB_GROWKERN, 4866 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4867 pmap_curmaxkvaddr, maxkvaddr)); 4868 4869 KDASSERT(maxkvaddr <= virtual_end); 4870 4871 /* 4872 * whoops! we need to add kernel PTPs 4873 */ 4874 4875 s = splhigh(); /* to be safe */ 4876 mutex_enter(&kpm->pm_lock); 4877 4878 /* Map 1MB at a time */ 4879 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4880 4881 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4882 KDASSERT(l2b != NULL); 4883 4884 /* Distribute new L1 entry to all other L1s */ 4885 SLIST_FOREACH(l1, &l1_list, l1_link) { 4886 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4887 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4888 L1_C_PROTO; 4889 PTE_SYNC(pl1pd); 4890 } 4891 } 4892 4893 /* 4894 * flush out the cache, expensive but growkernel will happen so 4895 * rarely 4896 */ 4897 cpu_dcache_wbinv_all(); 4898 cpu_tlb_flushD(); 4899 cpu_cpwait(); 4900 4901 mutex_exit(&kpm->pm_lock); 4902 splx(s); 4903 4904 out: 4905 return (pmap_curmaxkvaddr); 4906 } 4907 4908 /************************ Utility routines ****************************/ 4909 4910 /* 4911 * vector_page_setprot: 4912 * 4913 * Manipulate the protection of the vector page. 4914 */ 4915 void 4916 vector_page_setprot(int prot) 4917 { 4918 struct l2_bucket *l2b; 4919 pt_entry_t *ptep; 4920 4921 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4922 KDASSERT(l2b != NULL); 4923 4924 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4925 4926 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4927 PTE_SYNC(ptep); 4928 cpu_tlb_flushD_SE(vector_page); 4929 cpu_cpwait(); 4930 } 4931 4932 /* 4933 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4934 * Returns true if the mapping exists, else false. 4935 * 4936 * NOTE: This function is only used by a couple of arm-specific modules. 4937 * It is not safe to take any pmap locks here, since we could be right 4938 * in the middle of debugging the pmap anyway... 4939 * 4940 * It is possible for this routine to return false even though a valid 4941 * mapping does exist. This is because we don't lock, so the metadata 4942 * state may be inconsistent. 4943 * 4944 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4945 * a "section" mapping. 4946 */ 4947 bool 4948 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4949 { 4950 struct l2_dtable *l2; 4951 pd_entry_t *pl1pd, l1pd; 4952 pt_entry_t *ptep; 4953 u_short l1idx; 4954 4955 if (pm->pm_l1 == NULL) 4956 return false; 4957 4958 l1idx = L1_IDX(va); 4959 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4960 l1pd = *pl1pd; 4961 4962 if (l1pte_section_p(l1pd)) { 4963 *ptp = NULL; 4964 return true; 4965 } 4966 4967 if (pm->pm_l2 == NULL) 4968 return false; 4969 4970 l2 = pm->pm_l2[L2_IDX(l1idx)]; 4971 4972 if (l2 == NULL || 4973 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 4974 return false; 4975 } 4976 4977 *ptp = &ptep[l2pte_index(va)]; 4978 return true; 4979 } 4980 4981 bool 4982 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 4983 { 4984 u_short l1idx; 4985 4986 if (pm->pm_l1 == NULL) 4987 return false; 4988 4989 l1idx = L1_IDX(va); 4990 *pdp = &pm->pm_l1->l1_kva[l1idx]; 4991 4992 return true; 4993 } 4994 4995 /************************ Bootstrapping routines ****************************/ 4996 4997 static void 4998 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 4999 { 5000 int i; 5001 5002 l1->l1_kva = l1pt; 5003 l1->l1_domain_use_count = 0; 5004 l1->l1_domain_first = 0; 5005 5006 for (i = 0; i < PMAP_DOMAINS; i++) 5007 l1->l1_domain_free[i] = i + 1; 5008 5009 /* 5010 * Copy the kernel's L1 entries to each new L1. 5011 */ 5012 if (pmap_initialized) 5013 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5014 5015 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5016 &l1->l1_physaddr) == false) 5017 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5018 5019 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5020 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5021 } 5022 5023 /* 5024 * pmap_bootstrap() is called from the board-specific initarm() routine 5025 * once the kernel L1/L2 descriptors tables have been set up. 5026 * 5027 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5028 * spread over a number of disparate files/functions. 5029 * 5030 * We are passed the following parameters 5031 * - kernel_l1pt 5032 * This is a pointer to the base of the kernel's L1 translation table. 5033 * - vstart 5034 * 1MB-aligned start of managed kernel virtual memory. 5035 * - vend 5036 * 1MB-aligned end of managed kernel virtual memory. 5037 * 5038 * We use the first parameter to build the metadata (struct l1_ttable and 5039 * struct l2_dtable) necessary to track kernel mappings. 5040 */ 5041 #define PMAP_STATIC_L2_SIZE 16 5042 void 5043 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5044 { 5045 static struct l1_ttable static_l1; 5046 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5047 struct l1_ttable *l1 = &static_l1; 5048 struct l2_dtable *l2; 5049 struct l2_bucket *l2b; 5050 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5051 pmap_t pm = pmap_kernel(); 5052 pd_entry_t pde; 5053 pt_entry_t *ptep; 5054 paddr_t pa; 5055 vaddr_t va; 5056 vsize_t size; 5057 int nptes, l1idx, l2idx, l2next = 0; 5058 5059 /* 5060 * Initialise the kernel pmap object 5061 */ 5062 pm->pm_l1 = l1; 5063 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5064 pm->pm_activated = true; 5065 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5066 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5067 5068 /* 5069 * Scan the L1 translation table created by initarm() and create 5070 * the required metadata for all valid mappings found in it. 5071 */ 5072 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5073 pde = l1pt[l1idx]; 5074 5075 /* 5076 * We're only interested in Coarse mappings. 5077 * pmap_extract() can deal with section mappings without 5078 * recourse to checking L2 metadata. 5079 */ 5080 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5081 continue; 5082 5083 /* 5084 * Lookup the KVA of this L2 descriptor table 5085 */ 5086 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5087 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5088 if (ptep == NULL) { 5089 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5090 (u_int)l1idx << L1_S_SHIFT, pa); 5091 } 5092 5093 /* 5094 * Fetch the associated L2 metadata structure. 5095 * Allocate a new one if necessary. 5096 */ 5097 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5098 if (l2next == PMAP_STATIC_L2_SIZE) 5099 panic("pmap_bootstrap: out of static L2s"); 5100 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5101 } 5102 5103 /* 5104 * One more L1 slot tracked... 5105 */ 5106 l2->l2_occupancy++; 5107 5108 /* 5109 * Fill in the details of the L2 descriptor in the 5110 * appropriate bucket. 5111 */ 5112 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5113 l2b->l2b_kva = ptep; 5114 l2b->l2b_phys = pa; 5115 l2b->l2b_l1idx = l1idx; 5116 5117 /* 5118 * Establish an initial occupancy count for this descriptor 5119 */ 5120 for (l2idx = 0; 5121 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5122 l2idx++) { 5123 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5124 l2b->l2b_occupancy++; 5125 } 5126 } 5127 5128 /* 5129 * Make sure the descriptor itself has the correct cache mode. 5130 * If not, fix it, but whine about the problem. Port-meisters 5131 * should consider this a clue to fix up their initarm() 5132 * function. :) 5133 */ 5134 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5135 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5136 "L2 pte @ %p\n", ptep); 5137 } 5138 } 5139 5140 /* 5141 * Ensure the primary (kernel) L1 has the correct cache mode for 5142 * a page table. Bitch if it is not correctly set. 5143 */ 5144 for (va = (vaddr_t)l1pt; 5145 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5146 if (pmap_set_pt_cache_mode(l1pt, va)) 5147 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5148 "primary L1 @ 0x%lx\n", va); 5149 } 5150 5151 cpu_dcache_wbinv_all(); 5152 cpu_tlb_flushID(); 5153 cpu_cpwait(); 5154 5155 /* 5156 * now we allocate the "special" VAs which are used for tmp mappings 5157 * by the pmap (and other modules). we allocate the VAs by advancing 5158 * virtual_avail (note that there are no pages mapped at these VAs). 5159 * 5160 * Managed KVM space start from wherever initarm() tells us. 5161 */ 5162 virtual_avail = vstart; 5163 virtual_end = vend; 5164 5165 #ifdef PMAP_CACHE_VIPT 5166 /* 5167 * If we have a VIPT cache, we need one page/pte per possible alias 5168 * page so we won't violate cache aliasing rules. 5169 */ 5170 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5171 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5172 #else 5173 nptes = 1; 5174 #endif 5175 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5176 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5177 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5178 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5179 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5180 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5181 (void *)&msgbufaddr, NULL); 5182 5183 /* 5184 * Allocate a range of kernel virtual address space to be used 5185 * for L2 descriptor tables and metadata allocation in 5186 * pmap_growkernel(). 5187 */ 5188 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5189 pmap_alloc_specials(&virtual_avail, 5190 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5191 &pmap_kernel_l2ptp_kva, NULL); 5192 5193 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5194 pmap_alloc_specials(&virtual_avail, 5195 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5196 &pmap_kernel_l2dtable_kva, NULL); 5197 5198 /* 5199 * init the static-global locks and global pmap list. 5200 */ 5201 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5202 5203 /* 5204 * We can now initialise the first L1's metadata. 5205 */ 5206 SLIST_INIT(&l1_list); 5207 TAILQ_INIT(&l1_lru_list); 5208 simple_lock_init(&l1_lru_lock); 5209 pmap_init_l1(l1, l1pt); 5210 5211 /* Set up vector page L1 details, if necessary */ 5212 if (vector_page < KERNEL_BASE) { 5213 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5214 l2b = pmap_get_l2_bucket(pm, vector_page); 5215 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5216 L1_C_DOM(pm->pm_domain); 5217 } else 5218 pm->pm_pl1vec = NULL; 5219 5220 /* 5221 * Initialize the pmap cache 5222 */ 5223 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5224 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5225 LIST_INIT(&pmap_pmaps); 5226 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5227 5228 /* 5229 * Initialize the pv pool. 5230 */ 5231 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5232 &pmap_bootstrap_pv_allocator, IPL_NONE); 5233 5234 /* 5235 * Initialize the L2 dtable pool and cache. 5236 */ 5237 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5238 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5239 5240 /* 5241 * Initialise the L2 descriptor table pool and cache 5242 */ 5243 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5244 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5245 pmap_l2ptp_ctor, NULL, NULL); 5246 5247 cpu_dcache_wbinv_all(); 5248 } 5249 5250 static int 5251 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5252 { 5253 pd_entry_t *pdep, pde; 5254 pt_entry_t *ptep, pte; 5255 vaddr_t pa; 5256 int rv = 0; 5257 5258 /* 5259 * Make sure the descriptor itself has the correct cache mode 5260 */ 5261 pdep = &kl1[L1_IDX(va)]; 5262 pde = *pdep; 5263 5264 if (l1pte_section_p(pde)) { 5265 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5266 *pdep = (pde & ~L1_S_CACHE_MASK) | 5267 pte_l1_s_cache_mode_pt; 5268 PTE_SYNC(pdep); 5269 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5270 rv = 1; 5271 } 5272 } else { 5273 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5274 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5275 if (ptep == NULL) 5276 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5277 5278 ptep = &ptep[l2pte_index(va)]; 5279 pte = *ptep; 5280 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5281 *ptep = (pte & ~L2_S_CACHE_MASK) | 5282 pte_l2_s_cache_mode_pt; 5283 PTE_SYNC(ptep); 5284 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5285 rv = 1; 5286 } 5287 } 5288 5289 return (rv); 5290 } 5291 5292 static void 5293 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5294 { 5295 vaddr_t va = *availp; 5296 struct l2_bucket *l2b; 5297 5298 if (ptep) { 5299 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5300 if (l2b == NULL) 5301 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5302 5303 if (ptep) 5304 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5305 } 5306 5307 *vap = va; 5308 *availp = va + (PAGE_SIZE * pages); 5309 } 5310 5311 void 5312 pmap_init(void) 5313 { 5314 5315 /* 5316 * Set the available memory vars - These do not map to real memory 5317 * addresses and cannot as the physical memory is fragmented. 5318 * They are used by ps for %mem calculations. 5319 * One could argue whether this should be the entire memory or just 5320 * the memory that is useable in a user process. 5321 */ 5322 avail_start = ptoa(vm_physmem[0].start); 5323 avail_end = ptoa(vm_physmem[vm_nphysseg - 1].end); 5324 5325 /* 5326 * Now we need to free enough pv_entry structures to allow us to get 5327 * the kmem_map/kmem_object allocated and inited (done after this 5328 * function is finished). to do this we allocate one bootstrap page out 5329 * of kernel_map and use it to provide an initial pool of pv_entry 5330 * structures. we never free this page. 5331 */ 5332 pool_setlowat(&pmap_pv_pool, 5333 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5334 5335 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5336 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5337 UVM_KMF_WIRED|UVM_KMF_ZERO); 5338 5339 pmap_initialized = true; 5340 } 5341 5342 static vaddr_t last_bootstrap_page = 0; 5343 static void *free_bootstrap_pages = NULL; 5344 5345 static void * 5346 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5347 { 5348 extern void *pool_page_alloc(struct pool *, int); 5349 vaddr_t new_page; 5350 void *rv; 5351 5352 if (pmap_initialized) 5353 return (pool_page_alloc(pp, flags)); 5354 5355 if (free_bootstrap_pages) { 5356 rv = free_bootstrap_pages; 5357 free_bootstrap_pages = *((void **)rv); 5358 return (rv); 5359 } 5360 5361 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5362 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5363 5364 KASSERT(new_page > last_bootstrap_page); 5365 last_bootstrap_page = new_page; 5366 return ((void *)new_page); 5367 } 5368 5369 static void 5370 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5371 { 5372 extern void pool_page_free(struct pool *, void *); 5373 5374 if ((vaddr_t)v <= last_bootstrap_page) { 5375 *((void **)v) = free_bootstrap_pages; 5376 free_bootstrap_pages = v; 5377 return; 5378 } 5379 5380 if (pmap_initialized) { 5381 pool_page_free(pp, v); 5382 return; 5383 } 5384 } 5385 5386 /* 5387 * pmap_postinit() 5388 * 5389 * This routine is called after the vm and kmem subsystems have been 5390 * initialised. This allows the pmap code to perform any initialisation 5391 * that can only be done one the memory allocation is in place. 5392 */ 5393 void 5394 pmap_postinit(void) 5395 { 5396 extern paddr_t physical_start, physical_end; 5397 struct l2_bucket *l2b; 5398 struct l1_ttable *l1; 5399 struct pglist plist; 5400 struct vm_page *m; 5401 pd_entry_t *pl1pt; 5402 pt_entry_t *ptep, pte; 5403 vaddr_t va, eva; 5404 u_int loop, needed; 5405 int error; 5406 5407 pool_cache_setlowat(&pmap_l2ptp_cache, 5408 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5409 pool_cache_setlowat(&pmap_l2dtable_cache, 5410 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5411 5412 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5413 needed -= 1; 5414 5415 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5416 5417 for (loop = 0; loop < needed; loop++, l1++) { 5418 /* Allocate a L1 page table */ 5419 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5420 if (va == 0) 5421 panic("Cannot allocate L1 KVM"); 5422 5423 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5424 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5425 if (error) 5426 panic("Cannot allocate L1 physical pages"); 5427 5428 m = TAILQ_FIRST(&plist); 5429 eva = va + L1_TABLE_SIZE; 5430 pl1pt = (pd_entry_t *)va; 5431 5432 while (m && va < eva) { 5433 paddr_t pa = VM_PAGE_TO_PHYS(m); 5434 5435 pmap_kenter_pa(va, pa, 5436 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); 5437 5438 /* 5439 * Make sure the L1 descriptor table is mapped 5440 * with the cache-mode set to write-through. 5441 */ 5442 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5443 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5444 pte = *ptep; 5445 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5446 *ptep = pte; 5447 PTE_SYNC(ptep); 5448 cpu_tlb_flushD_SE(va); 5449 5450 va += PAGE_SIZE; 5451 m = TAILQ_NEXT(m, pageq.queue); 5452 } 5453 5454 #ifdef DIAGNOSTIC 5455 if (m) 5456 panic("pmap_alloc_l1pt: pglist not empty"); 5457 #endif /* DIAGNOSTIC */ 5458 5459 pmap_init_l1(l1, pl1pt); 5460 } 5461 5462 #ifdef DEBUG 5463 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5464 needed); 5465 #endif 5466 } 5467 5468 /* 5469 * Note that the following routines are used by board-specific initialisation 5470 * code to configure the initial kernel page tables. 5471 * 5472 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5473 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5474 * behaviour of the old pmap, and provides an easy migration path for 5475 * initial bring-up of the new pmap on existing ports. Fortunately, 5476 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5477 * will be deprecated. 5478 * 5479 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5480 * tables. 5481 */ 5482 5483 /* 5484 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5485 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5486 * find them as necessary. 5487 * 5488 * Note that the data on this list MUST remain valid after initarm() returns, 5489 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5490 */ 5491 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5492 5493 static vaddr_t 5494 kernel_pt_lookup(paddr_t pa) 5495 { 5496 pv_addr_t *pv; 5497 5498 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5499 #ifndef ARM32_NEW_VM_LAYOUT 5500 if (pv->pv_pa == (pa & ~PGOFSET)) 5501 return (pv->pv_va | (pa & PGOFSET)); 5502 #else 5503 if (pv->pv_pa == pa) 5504 return (pv->pv_va); 5505 #endif 5506 } 5507 return (0); 5508 } 5509 5510 /* 5511 * pmap_map_section: 5512 * 5513 * Create a single section mapping. 5514 */ 5515 void 5516 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5517 { 5518 pd_entry_t *pde = (pd_entry_t *) l1pt; 5519 pd_entry_t fl; 5520 5521 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5522 5523 switch (cache) { 5524 case PTE_NOCACHE: 5525 default: 5526 fl = 0; 5527 break; 5528 5529 case PTE_CACHE: 5530 fl = pte_l1_s_cache_mode; 5531 break; 5532 5533 case PTE_PAGETABLE: 5534 fl = pte_l1_s_cache_mode_pt; 5535 break; 5536 } 5537 5538 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5539 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5540 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5541 } 5542 5543 /* 5544 * pmap_map_entry: 5545 * 5546 * Create a single page mapping. 5547 */ 5548 void 5549 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5550 { 5551 pd_entry_t *pde = (pd_entry_t *) l1pt; 5552 pt_entry_t fl; 5553 pt_entry_t *pte; 5554 5555 KASSERT(((va | pa) & PGOFSET) == 0); 5556 5557 switch (cache) { 5558 case PTE_NOCACHE: 5559 default: 5560 fl = 0; 5561 break; 5562 5563 case PTE_CACHE: 5564 fl = pte_l2_s_cache_mode; 5565 break; 5566 5567 case PTE_PAGETABLE: 5568 fl = pte_l2_s_cache_mode_pt; 5569 break; 5570 } 5571 5572 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5573 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5574 5575 #ifndef ARM32_NEW_VM_LAYOUT 5576 pte = (pt_entry_t *) 5577 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5578 #else 5579 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5580 #endif 5581 if (pte == NULL) 5582 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5583 5584 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5585 #ifndef ARM32_NEW_VM_LAYOUT 5586 pte += (va >> PGSHIFT) & 0x3ff; 5587 #else 5588 pte += l2pte_index(va); 5589 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5590 #endif 5591 *pte = fl; 5592 PTE_SYNC(pte); 5593 } 5594 5595 /* 5596 * pmap_link_l2pt: 5597 * 5598 * Link the L2 page table specified by "l2pv" into the L1 5599 * page table at the slot for "va". 5600 */ 5601 void 5602 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5603 { 5604 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5605 u_int slot = va >> L1_S_SHIFT; 5606 5607 #ifndef ARM32_NEW_VM_LAYOUT 5608 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5609 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5610 #endif 5611 5612 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5613 5614 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5615 #ifdef ARM32_NEW_VM_LAYOUT 5616 PTE_SYNC(&pde[slot]); 5617 #else 5618 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5619 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5620 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5621 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5622 #endif 5623 5624 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5625 } 5626 5627 /* 5628 * pmap_map_chunk: 5629 * 5630 * Map a chunk of memory using the most efficient mappings 5631 * possible (section, large page, small page) into the 5632 * provided L1 and L2 tables at the specified virtual address. 5633 */ 5634 vsize_t 5635 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5636 int prot, int cache) 5637 { 5638 pd_entry_t *pde = (pd_entry_t *) l1pt; 5639 pt_entry_t *pte, f1, f2s, f2l; 5640 vsize_t resid; 5641 int i; 5642 5643 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5644 5645 if (l1pt == 0) 5646 panic("pmap_map_chunk: no L1 table provided"); 5647 5648 #ifdef VERBOSE_INIT_ARM 5649 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5650 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5651 #endif 5652 5653 switch (cache) { 5654 case PTE_NOCACHE: 5655 default: 5656 f1 = 0; 5657 f2l = 0; 5658 f2s = 0; 5659 break; 5660 5661 case PTE_CACHE: 5662 f1 = pte_l1_s_cache_mode; 5663 f2l = pte_l2_l_cache_mode; 5664 f2s = pte_l2_s_cache_mode; 5665 break; 5666 5667 case PTE_PAGETABLE: 5668 f1 = pte_l1_s_cache_mode_pt; 5669 f2l = pte_l2_l_cache_mode_pt; 5670 f2s = pte_l2_s_cache_mode_pt; 5671 break; 5672 } 5673 5674 size = resid; 5675 5676 while (resid > 0) { 5677 /* See if we can use a section mapping. */ 5678 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5679 #ifdef VERBOSE_INIT_ARM 5680 printf("S"); 5681 #endif 5682 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5683 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5684 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5685 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5686 va += L1_S_SIZE; 5687 pa += L1_S_SIZE; 5688 resid -= L1_S_SIZE; 5689 continue; 5690 } 5691 5692 /* 5693 * Ok, we're going to use an L2 table. Make sure 5694 * one is actually in the corresponding L1 slot 5695 * for the current VA. 5696 */ 5697 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5698 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5699 5700 #ifndef ARM32_NEW_VM_LAYOUT 5701 pte = (pt_entry_t *) 5702 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5703 #else 5704 pte = (pt_entry_t *) kernel_pt_lookup( 5705 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5706 #endif 5707 if (pte == NULL) 5708 panic("pmap_map_chunk: can't find L2 table for VA" 5709 "0x%08lx", va); 5710 5711 /* See if we can use a L2 large page mapping. */ 5712 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5713 #ifdef VERBOSE_INIT_ARM 5714 printf("L"); 5715 #endif 5716 for (i = 0; i < 16; i++) { 5717 #ifndef ARM32_NEW_VM_LAYOUT 5718 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5719 L2_L_PROTO | pa | 5720 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5721 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5722 #else 5723 pte[l2pte_index(va) + i] = 5724 L2_L_PROTO | pa | 5725 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5726 PTE_SYNC(&pte[l2pte_index(va) + i]); 5727 #endif 5728 } 5729 va += L2_L_SIZE; 5730 pa += L2_L_SIZE; 5731 resid -= L2_L_SIZE; 5732 continue; 5733 } 5734 5735 /* Use a small page mapping. */ 5736 #ifdef VERBOSE_INIT_ARM 5737 printf("P"); 5738 #endif 5739 #ifndef ARM32_NEW_VM_LAYOUT 5740 pte[(va >> PGSHIFT) & 0x3ff] = 5741 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5742 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5743 #else 5744 pte[l2pte_index(va)] = 5745 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5746 PTE_SYNC(&pte[l2pte_index(va)]); 5747 #endif 5748 va += PAGE_SIZE; 5749 pa += PAGE_SIZE; 5750 resid -= PAGE_SIZE; 5751 } 5752 #ifdef VERBOSE_INIT_ARM 5753 printf("\n"); 5754 #endif 5755 return (size); 5756 } 5757 5758 /********************** Static device map routines ***************************/ 5759 5760 static const struct pmap_devmap *pmap_devmap_table; 5761 5762 /* 5763 * Register the devmap table. This is provided in case early console 5764 * initialization needs to register mappings created by bootstrap code 5765 * before pmap_devmap_bootstrap() is called. 5766 */ 5767 void 5768 pmap_devmap_register(const struct pmap_devmap *table) 5769 { 5770 5771 pmap_devmap_table = table; 5772 } 5773 5774 /* 5775 * Map all of the static regions in the devmap table, and remember 5776 * the devmap table so other parts of the kernel can look up entries 5777 * later. 5778 */ 5779 void 5780 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5781 { 5782 int i; 5783 5784 pmap_devmap_table = table; 5785 5786 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5787 #ifdef VERBOSE_INIT_ARM 5788 printf("devmap: %08lx -> %08lx @ %08lx\n", 5789 pmap_devmap_table[i].pd_pa, 5790 pmap_devmap_table[i].pd_pa + 5791 pmap_devmap_table[i].pd_size - 1, 5792 pmap_devmap_table[i].pd_va); 5793 #endif 5794 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5795 pmap_devmap_table[i].pd_pa, 5796 pmap_devmap_table[i].pd_size, 5797 pmap_devmap_table[i].pd_prot, 5798 pmap_devmap_table[i].pd_cache); 5799 } 5800 } 5801 5802 const struct pmap_devmap * 5803 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5804 { 5805 uint64_t endpa; 5806 int i; 5807 5808 if (pmap_devmap_table == NULL) 5809 return (NULL); 5810 5811 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5812 5813 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5814 if (pa >= pmap_devmap_table[i].pd_pa && 5815 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5816 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5817 return (&pmap_devmap_table[i]); 5818 } 5819 5820 return (NULL); 5821 } 5822 5823 const struct pmap_devmap * 5824 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5825 { 5826 int i; 5827 5828 if (pmap_devmap_table == NULL) 5829 return (NULL); 5830 5831 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5832 if (va >= pmap_devmap_table[i].pd_va && 5833 va + size - 1 <= pmap_devmap_table[i].pd_va + 5834 pmap_devmap_table[i].pd_size - 1) 5835 return (&pmap_devmap_table[i]); 5836 } 5837 5838 return (NULL); 5839 } 5840 5841 /********************** PTE initialization routines **************************/ 5842 5843 /* 5844 * These routines are called when the CPU type is identified to set up 5845 * the PTE prototypes, cache modes, etc. 5846 * 5847 * The variables are always here, just in case modules need to reference 5848 * them (though, they shouldn't). 5849 */ 5850 5851 pt_entry_t pte_l1_s_cache_mode; 5852 pt_entry_t pte_l1_s_cache_mode_pt; 5853 pt_entry_t pte_l1_s_cache_mask; 5854 5855 pt_entry_t pte_l2_l_cache_mode; 5856 pt_entry_t pte_l2_l_cache_mode_pt; 5857 pt_entry_t pte_l2_l_cache_mask; 5858 5859 pt_entry_t pte_l2_s_cache_mode; 5860 pt_entry_t pte_l2_s_cache_mode_pt; 5861 pt_entry_t pte_l2_s_cache_mask; 5862 5863 pt_entry_t pte_l2_s_prot_u; 5864 pt_entry_t pte_l2_s_prot_w; 5865 pt_entry_t pte_l2_s_prot_mask; 5866 5867 pt_entry_t pte_l1_s_proto; 5868 pt_entry_t pte_l1_c_proto; 5869 pt_entry_t pte_l2_s_proto; 5870 5871 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5872 void (*pmap_zero_page_func)(paddr_t); 5873 5874 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5875 void 5876 pmap_pte_init_generic(void) 5877 { 5878 5879 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5880 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5881 5882 pte_l2_l_cache_mode = L2_B|L2_C; 5883 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5884 5885 pte_l2_s_cache_mode = L2_B|L2_C; 5886 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5887 5888 /* 5889 * If we have a write-through cache, set B and C. If 5890 * we have a write-back cache, then we assume setting 5891 * only C will make those pages write-through. 5892 */ 5893 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5894 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5895 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5896 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5897 } else { 5898 #if ARM_MMU_V6 > 1 5899 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5900 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5901 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5902 #else 5903 pte_l1_s_cache_mode_pt = L1_S_C; 5904 pte_l2_l_cache_mode_pt = L2_C; 5905 pte_l2_s_cache_mode_pt = L2_C; 5906 #endif 5907 } 5908 5909 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5910 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5911 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5912 5913 pte_l1_s_proto = L1_S_PROTO_generic; 5914 pte_l1_c_proto = L1_C_PROTO_generic; 5915 pte_l2_s_proto = L2_S_PROTO_generic; 5916 5917 pmap_copy_page_func = pmap_copy_page_generic; 5918 pmap_zero_page_func = pmap_zero_page_generic; 5919 } 5920 5921 #if defined(CPU_ARM8) 5922 void 5923 pmap_pte_init_arm8(void) 5924 { 5925 5926 /* 5927 * ARM8 is compatible with generic, but we need to use 5928 * the page tables uncached. 5929 */ 5930 pmap_pte_init_generic(); 5931 5932 pte_l1_s_cache_mode_pt = 0; 5933 pte_l2_l_cache_mode_pt = 0; 5934 pte_l2_s_cache_mode_pt = 0; 5935 } 5936 #endif /* CPU_ARM8 */ 5937 5938 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5939 void 5940 pmap_pte_init_arm9(void) 5941 { 5942 5943 /* 5944 * ARM9 is compatible with generic, but we want to use 5945 * write-through caching for now. 5946 */ 5947 pmap_pte_init_generic(); 5948 5949 pte_l1_s_cache_mode = L1_S_C; 5950 pte_l2_l_cache_mode = L2_C; 5951 pte_l2_s_cache_mode = L2_C; 5952 5953 pte_l1_s_cache_mode_pt = L1_S_C; 5954 pte_l2_l_cache_mode_pt = L2_C; 5955 pte_l2_s_cache_mode_pt = L2_C; 5956 } 5957 #endif /* CPU_ARM9 */ 5958 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5959 5960 #if defined(CPU_ARM10) 5961 void 5962 pmap_pte_init_arm10(void) 5963 { 5964 5965 /* 5966 * ARM10 is compatible with generic, but we want to use 5967 * write-through caching for now. 5968 */ 5969 pmap_pte_init_generic(); 5970 5971 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 5972 pte_l2_l_cache_mode = L2_B | L2_C; 5973 pte_l2_s_cache_mode = L2_B | L2_C; 5974 5975 pte_l1_s_cache_mode_pt = L1_S_C; 5976 pte_l2_l_cache_mode_pt = L2_C; 5977 pte_l2_s_cache_mode_pt = L2_C; 5978 5979 } 5980 #endif /* CPU_ARM10 */ 5981 5982 #if ARM_MMU_SA1 == 1 5983 void 5984 pmap_pte_init_sa1(void) 5985 { 5986 5987 /* 5988 * The StrongARM SA-1 cache does not have a write-through 5989 * mode. So, do the generic initialization, then reset 5990 * the page table cache mode to B=1,C=1, and note that 5991 * the PTEs need to be sync'd. 5992 */ 5993 pmap_pte_init_generic(); 5994 5995 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5996 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5997 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5998 5999 pmap_needs_pte_sync = 1; 6000 } 6001 #endif /* ARM_MMU_SA1 == 1*/ 6002 6003 #if ARM_MMU_XSCALE == 1 6004 #if (ARM_NMMUS > 1) 6005 static u_int xscale_use_minidata; 6006 #endif 6007 6008 void 6009 pmap_pte_init_xscale(void) 6010 { 6011 uint32_t auxctl; 6012 int write_through = 0; 6013 6014 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6015 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6016 6017 pte_l2_l_cache_mode = L2_B|L2_C; 6018 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6019 6020 pte_l2_s_cache_mode = L2_B|L2_C; 6021 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6022 6023 pte_l1_s_cache_mode_pt = L1_S_C; 6024 pte_l2_l_cache_mode_pt = L2_C; 6025 pte_l2_s_cache_mode_pt = L2_C; 6026 6027 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6028 /* 6029 * The XScale core has an enhanced mode where writes that 6030 * miss the cache cause a cache line to be allocated. This 6031 * is significantly faster than the traditional, write-through 6032 * behavior of this case. 6033 */ 6034 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6035 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6036 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6037 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6038 6039 #ifdef XSCALE_CACHE_WRITE_THROUGH 6040 /* 6041 * Some versions of the XScale core have various bugs in 6042 * their cache units, the work-around for which is to run 6043 * the cache in write-through mode. Unfortunately, this 6044 * has a major (negative) impact on performance. So, we 6045 * go ahead and run fast-and-loose, in the hopes that we 6046 * don't line up the planets in a way that will trip the 6047 * bugs. 6048 * 6049 * However, we give you the option to be slow-but-correct. 6050 */ 6051 write_through = 1; 6052 #elif defined(XSCALE_CACHE_WRITE_BACK) 6053 /* force write back cache mode */ 6054 write_through = 0; 6055 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6056 /* 6057 * Intel PXA2[15]0 processors are known to have a bug in 6058 * write-back cache on revision 4 and earlier (stepping 6059 * A[01] and B[012]). Fixed for C0 and later. 6060 */ 6061 { 6062 uint32_t id, type; 6063 6064 id = cpufunc_id(); 6065 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6066 6067 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6068 if ((id & CPU_ID_REVISION_MASK) < 5) { 6069 /* write through for stepping A0-1 and B0-2 */ 6070 write_through = 1; 6071 } 6072 } 6073 } 6074 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6075 6076 if (write_through) { 6077 pte_l1_s_cache_mode = L1_S_C; 6078 pte_l2_l_cache_mode = L2_C; 6079 pte_l2_s_cache_mode = L2_C; 6080 } 6081 6082 #if (ARM_NMMUS > 1) 6083 xscale_use_minidata = 1; 6084 #endif 6085 6086 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6087 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6088 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6089 6090 pte_l1_s_proto = L1_S_PROTO_xscale; 6091 pte_l1_c_proto = L1_C_PROTO_xscale; 6092 pte_l2_s_proto = L2_S_PROTO_xscale; 6093 6094 pmap_copy_page_func = pmap_copy_page_xscale; 6095 pmap_zero_page_func = pmap_zero_page_xscale; 6096 6097 /* 6098 * Disable ECC protection of page table access, for now. 6099 */ 6100 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6101 auxctl &= ~XSCALE_AUXCTL_P; 6102 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6103 } 6104 6105 /* 6106 * xscale_setup_minidata: 6107 * 6108 * Set up the mini-data cache clean area. We require the 6109 * caller to allocate the right amount of physically and 6110 * virtually contiguous space. 6111 */ 6112 void 6113 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6114 { 6115 extern vaddr_t xscale_minidata_clean_addr; 6116 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6117 pd_entry_t *pde = (pd_entry_t *) l1pt; 6118 pt_entry_t *pte; 6119 vsize_t size; 6120 uint32_t auxctl; 6121 6122 xscale_minidata_clean_addr = va; 6123 6124 /* Round it to page size. */ 6125 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6126 6127 for (; size != 0; 6128 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6129 #ifndef ARM32_NEW_VM_LAYOUT 6130 pte = (pt_entry_t *) 6131 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6132 #else 6133 pte = (pt_entry_t *) kernel_pt_lookup( 6134 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6135 #endif 6136 if (pte == NULL) 6137 panic("xscale_setup_minidata: can't find L2 table for " 6138 "VA 0x%08lx", va); 6139 #ifndef ARM32_NEW_VM_LAYOUT 6140 pte[(va >> PGSHIFT) & 0x3ff] = 6141 #else 6142 pte[l2pte_index(va)] = 6143 #endif 6144 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6145 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6146 } 6147 6148 /* 6149 * Configure the mini-data cache for write-back with 6150 * read/write-allocate. 6151 * 6152 * NOTE: In order to reconfigure the mini-data cache, we must 6153 * make sure it contains no valid data! In order to do that, 6154 * we must issue a global data cache invalidate command! 6155 * 6156 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6157 * THIS IS VERY IMPORTANT! 6158 */ 6159 6160 /* Invalidate data and mini-data. */ 6161 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6162 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6163 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6164 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6165 } 6166 6167 /* 6168 * Change the PTEs for the specified kernel mappings such that they 6169 * will use the mini data cache instead of the main data cache. 6170 */ 6171 void 6172 pmap_uarea(vaddr_t va) 6173 { 6174 struct l2_bucket *l2b; 6175 pt_entry_t *ptep, *sptep, pte; 6176 vaddr_t next_bucket, eva; 6177 6178 #if (ARM_NMMUS > 1) 6179 if (xscale_use_minidata == 0) 6180 return; 6181 #endif 6182 6183 eva = va + USPACE; 6184 6185 while (va < eva) { 6186 next_bucket = L2_NEXT_BUCKET(va); 6187 if (next_bucket > eva) 6188 next_bucket = eva; 6189 6190 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6191 KDASSERT(l2b != NULL); 6192 6193 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6194 6195 while (va < next_bucket) { 6196 pte = *ptep; 6197 if (!l2pte_minidata(pte)) { 6198 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6199 cpu_tlb_flushD_SE(va); 6200 *ptep = pte & ~L2_B; 6201 } 6202 ptep++; 6203 va += PAGE_SIZE; 6204 } 6205 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6206 } 6207 cpu_cpwait(); 6208 } 6209 #endif /* ARM_MMU_XSCALE == 1 */ 6210 6211 /* 6212 * return the PA of the current L1 table, for use when handling a crash dump 6213 */ 6214 uint32_t pmap_kernel_L1_addr(void) 6215 { 6216 return pmap_kernel()->pm_l1->l1_physaddr; 6217 } 6218 6219 #if defined(DDB) 6220 /* 6221 * A couple of ddb-callable functions for dumping pmaps 6222 */ 6223 void pmap_dump_all(void); 6224 void pmap_dump(pmap_t); 6225 6226 void 6227 pmap_dump_all(void) 6228 { 6229 pmap_t pm; 6230 6231 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6232 if (pm == pmap_kernel()) 6233 continue; 6234 pmap_dump(pm); 6235 printf("\n"); 6236 } 6237 } 6238 6239 static pt_entry_t ncptes[64]; 6240 static void pmap_dump_ncpg(pmap_t); 6241 6242 void 6243 pmap_dump(pmap_t pm) 6244 { 6245 struct l2_dtable *l2; 6246 struct l2_bucket *l2b; 6247 pt_entry_t *ptep, pte; 6248 vaddr_t l2_va, l2b_va, va; 6249 int i, j, k, occ, rows = 0; 6250 6251 if (pm == pmap_kernel()) 6252 printf("pmap_kernel (%p): ", pm); 6253 else 6254 printf("user pmap (%p): ", pm); 6255 6256 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6257 6258 l2_va = 0; 6259 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6260 l2 = pm->pm_l2[i]; 6261 6262 if (l2 == NULL || l2->l2_occupancy == 0) 6263 continue; 6264 6265 l2b_va = l2_va; 6266 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6267 l2b = &l2->l2_bucket[j]; 6268 6269 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6270 continue; 6271 6272 ptep = l2b->l2b_kva; 6273 6274 for (k = 0; k < 256 && ptep[k] == 0; k++) 6275 ; 6276 6277 k &= ~63; 6278 occ = l2b->l2b_occupancy; 6279 va = l2b_va + (k * 4096); 6280 for (; k < 256; k++, va += 0x1000) { 6281 char ch = ' '; 6282 if ((k % 64) == 0) { 6283 if ((rows % 8) == 0) { 6284 printf( 6285 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6286 } 6287 printf("%08lx: ", va); 6288 } 6289 6290 ncptes[k & 63] = 0; 6291 pte = ptep[k]; 6292 if (pte == 0) { 6293 ch = '.'; 6294 } else { 6295 occ--; 6296 switch (pte & 0x0c) { 6297 case 0x00: 6298 ch = 'D'; /* No cache No buff */ 6299 break; 6300 case 0x04: 6301 ch = 'B'; /* No cache buff */ 6302 break; 6303 case 0x08: 6304 if (pte & 0x40) 6305 ch = 'm'; 6306 else 6307 ch = 'C'; /* Cache No buff */ 6308 break; 6309 case 0x0c: 6310 ch = 'F'; /* Cache Buff */ 6311 break; 6312 } 6313 6314 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6315 ch += 0x20; 6316 6317 if ((pte & 0xc) == 0) 6318 ncptes[k & 63] = pte; 6319 } 6320 6321 if ((k % 64) == 63) { 6322 rows++; 6323 printf("%c\n", ch); 6324 pmap_dump_ncpg(pm); 6325 if (occ == 0) 6326 break; 6327 } else 6328 printf("%c", ch); 6329 } 6330 } 6331 } 6332 } 6333 6334 static void 6335 pmap_dump_ncpg(pmap_t pm) 6336 { 6337 struct vm_page *pg; 6338 struct pv_entry *pv; 6339 int i; 6340 6341 for (i = 0; i < 63; i++) { 6342 if (ncptes[i] == 0) 6343 continue; 6344 6345 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6346 if (pg == NULL) 6347 continue; 6348 6349 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6350 VM_PAGE_TO_PHYS(pg), 6351 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 6352 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 6353 6354 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 6355 printf(" %c va 0x%08lx, flags 0x%x\n", 6356 (pm == pv->pv_pmap) ? '*' : ' ', 6357 pv->pv_va, pv->pv_flags); 6358 } 6359 } 6360 } 6361 #endif 6362 6363 #ifdef PMAP_STEAL_MEMORY 6364 void 6365 pmap_boot_pageadd(pv_addr_t *newpv) 6366 { 6367 pv_addr_t *pv, *npv; 6368 6369 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6370 if (newpv->pv_pa < pv->pv_va) { 6371 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6372 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6373 newpv->pv_size += pv->pv_size; 6374 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6375 } 6376 pv = NULL; 6377 } else { 6378 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6379 pv = npv) { 6380 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6381 KASSERT(pv->pv_pa < newpv->pv_pa); 6382 if (newpv->pv_pa > npv->pv_pa) 6383 continue; 6384 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6385 pv->pv_size += newpv->pv_size; 6386 return; 6387 } 6388 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6389 break; 6390 newpv->pv_size += npv->pv_size; 6391 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6392 SLIST_REMOVE_AFTER(newpv, pv_list); 6393 return; 6394 } 6395 } 6396 } 6397 6398 if (pv) { 6399 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6400 } else { 6401 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6402 } 6403 } 6404 6405 void 6406 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6407 pv_addr_t *rpv) 6408 { 6409 pv_addr_t *pv, **pvp; 6410 struct vm_physseg *ps; 6411 size_t i; 6412 6413 KASSERT(amount & PGOFSET); 6414 KASSERT((mask & PGOFSET) == 0); 6415 KASSERT((match & PGOFSET) == 0); 6416 KASSERT(amount != 0); 6417 6418 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6419 (pv = *pvp) != NULL; 6420 pvp = &SLIST_NEXT(pv, pv_list)) { 6421 pv_addr_t *newpv; 6422 psize_t off; 6423 /* 6424 * If this entry is too small to satify the request... 6425 */ 6426 KASSERT(pv->pv_size > 0); 6427 if (pv->pv_size < amount) 6428 continue; 6429 6430 for (off = 0; off <= mask; off += PAGE_SIZE) { 6431 if (((pv->pv_pa + off) & mask) == match 6432 && off + amount <= pv->pv_size) 6433 break; 6434 } 6435 if (off > mask) 6436 continue; 6437 6438 rpv->pv_va = pv->pv_va + off; 6439 rpv->pv_pa = pv->pv_pa + off; 6440 rpv->pv_size = amount; 6441 pv->pv_size -= amount; 6442 if (pv->pv_size == 0) { 6443 KASSERT(off == 0); 6444 KASSERT((vaddr_t) pv == rpv->pv_va); 6445 *pvp = SLIST_NEXT(pv, pv_list); 6446 } else if (off == 0) { 6447 KASSERT((vaddr_t) pv == rpv->pv_va); 6448 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6449 *newpv = *pv; 6450 newpv->pv_pa += amount; 6451 newpv->pv_va += amount; 6452 *pvp = newpv; 6453 } else if (off < pv->pv_size) { 6454 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6455 *newpv = *pv; 6456 newpv->pv_size -= off; 6457 newpv->pv_pa += off + amount; 6458 newpv->pv_va += off + amount; 6459 6460 SLIST_NEXT(pv, pv_list) = newpv; 6461 pv->pv_size = off; 6462 } else { 6463 KASSERT((vaddr_t) pv != rpv->pv_va); 6464 } 6465 memset((void *)rpv->pv_va, 0, amount); 6466 return; 6467 } 6468 6469 if (vm_nphysseg == 0) 6470 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6471 6472 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6473 (pv = *pvp) != NULL; 6474 pvp = &SLIST_NEXT(pv, pv_list)) { 6475 if (SLIST_NEXT(pv, pv_list) == NULL) 6476 break; 6477 } 6478 KASSERT(mask == 0); 6479 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6480 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6481 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6482 rpv->pv_va = pv->pv_va; 6483 rpv->pv_pa = pv->pv_pa; 6484 rpv->pv_size = amount; 6485 *pvp = NULL; 6486 pmap_map_chunk(kernel_l1pt.pv_va, 6487 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6488 ptoa(ps->avail_start), 6489 amount - pv->pv_size, 6490 VM_PROT_READ|VM_PROT_WRITE, 6491 PTE_CACHE); 6492 ps->avail_start += atop(amount - pv->pv_size); 6493 /* 6494 * If we consumed the entire physseg, remove it. 6495 */ 6496 if (ps->avail_start == ps->avail_end) { 6497 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6498 ps[0] = ps[1]; 6499 } 6500 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6501 return; 6502 } 6503 } 6504 6505 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6506 } 6507 6508 vaddr_t 6509 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6510 { 6511 pv_addr_t pv; 6512 6513 pmap_boot_pagealloc(size, 0, 0, &pv); 6514 6515 return pv.pv_va; 6516 } 6517 #endif /* PMAP_STEAL_MEMORY */ 6518 6519 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6520 { 6521 sysctl_createv(clog, 0, NULL, NULL, 6522 CTLFLAG_PERMANENT, 6523 CTLTYPE_NODE, "machdep", NULL, 6524 NULL, 0, NULL, 0, 6525 CTL_MACHDEP, CTL_EOL); 6526 6527 sysctl_createv(clog, 0, NULL, NULL, 6528 CTLFLAG_PERMANENT, 6529 CTLTYPE_INT, "kmpages", 6530 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6531 NULL, 0, &pmap_kmpages, 0, 6532 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6533 } 6534
Indexes created Sun Sep 28 12:09:53 GMT 2025