pmap.c revision 1.203
1 /* $NetBSD: pmap.c,v 1.203 2009/11/28 11:44:45 scw Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/pool.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <machine/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.203 2009/11/28 11:44:45 scw Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 static struct pmap kernel_pmap_store; 258 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 #ifdef PMAPCOUNTERS 308 #define PMAP_EVCNT_INITIALIZER(name) \ 309 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 310 311 #ifdef PMAP_CACHE_VIPT 312 static struct evcnt pmap_ev_vac_clean_one = 313 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 314 static struct evcnt pmap_ev_vac_flush_one = 315 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_lots = 317 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 318 static struct evcnt pmap_ev_vac_flush_lots2 = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 324 325 static struct evcnt pmap_ev_vac_color_new = 326 PMAP_EVCNT_INITIALIZER("new page color"); 327 static struct evcnt pmap_ev_vac_color_reuse = 328 PMAP_EVCNT_INITIALIZER("ok first page color"); 329 static struct evcnt pmap_ev_vac_color_ok = 330 PMAP_EVCNT_INITIALIZER("ok page color"); 331 static struct evcnt pmap_ev_vac_color_blind = 332 PMAP_EVCNT_INITIALIZER("blind page color"); 333 static struct evcnt pmap_ev_vac_color_change = 334 PMAP_EVCNT_INITIALIZER("change page color"); 335 static struct evcnt pmap_ev_vac_color_erase = 336 PMAP_EVCNT_INITIALIZER("erase page color"); 337 static struct evcnt pmap_ev_vac_color_none = 338 PMAP_EVCNT_INITIALIZER("no page color"); 339 static struct evcnt pmap_ev_vac_color_restore = 340 PMAP_EVCNT_INITIALIZER("restore page color"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 350 #endif 351 352 static struct evcnt pmap_ev_mappings = 353 PMAP_EVCNT_INITIALIZER("pages mapped"); 354 static struct evcnt pmap_ev_unmappings = 355 PMAP_EVCNT_INITIALIZER("pages unmapped"); 356 static struct evcnt pmap_ev_remappings = 357 PMAP_EVCNT_INITIALIZER("pages remapped"); 358 359 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 360 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 362 363 static struct evcnt pmap_ev_kernel_mappings = 364 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 365 static struct evcnt pmap_ev_kernel_unmappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 367 static struct evcnt pmap_ev_kernel_remappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 373 374 static struct evcnt pmap_ev_kenter_mappings = 375 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 376 static struct evcnt pmap_ev_kenter_unmappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 378 static struct evcnt pmap_ev_kenter_remappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 380 static struct evcnt pmap_ev_pt_mappings = 381 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 382 383 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 387 388 #ifdef PMAP_CACHE_VIPT 389 static struct evcnt pmap_ev_exec_mappings = 390 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 391 static struct evcnt pmap_ev_exec_cached = 392 PMAP_EVCNT_INITIALIZER("exec pages cached"); 393 394 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 396 397 static struct evcnt pmap_ev_exec_synced = 398 PMAP_EVCNT_INITIALIZER("exec pages synced"); 399 static struct evcnt pmap_ev_exec_synced_map = 400 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 401 static struct evcnt pmap_ev_exec_synced_unmap = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 403 static struct evcnt pmap_ev_exec_synced_remap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 405 static struct evcnt pmap_ev_exec_synced_clearbit = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 407 static struct evcnt pmap_ev_exec_synced_kremove = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 409 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 416 417 static struct evcnt pmap_ev_exec_discarded_unmap = 418 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 419 static struct evcnt pmap_ev_exec_discarded_zero = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 421 static struct evcnt pmap_ev_exec_discarded_copy = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 423 static struct evcnt pmap_ev_exec_discarded_page_protect = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 425 static struct evcnt pmap_ev_exec_discarded_clearbit = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 427 static struct evcnt pmap_ev_exec_discarded_kremove = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 429 430 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 436 #endif /* PMAP_CACHE_VIPT */ 437 438 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 439 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 440 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 441 442 EVCNT_ATTACH_STATIC(pmap_ev_updates); 443 EVCNT_ATTACH_STATIC(pmap_ev_collects); 444 EVCNT_ATTACH_STATIC(pmap_ev_activations); 445 446 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 447 #else 448 #define PMAPCOUNT(x) ((void)0) 449 #endif 450 451 /* 452 * pmap copy/zero page, and mem(5) hook point 453 */ 454 static pt_entry_t *csrc_pte, *cdst_pte; 455 static vaddr_t csrcp, cdstp; 456 vaddr_t memhook; /* used by mem.c */ 457 kmutex_t memlock; /* used by mem.c */ 458 void *zeropage; /* used by mem.c */ 459 extern void *msgbufaddr; 460 int pmap_kmpages; 461 /* 462 * Flag to indicate if pmap_init() has done its thing 463 */ 464 bool pmap_initialized; 465 466 /* 467 * Misc. locking data structures 468 */ 469 470 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 471 static struct lock pmap_main_lock; 472 473 #define PMAP_MAP_TO_HEAD_LOCK() \ 474 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 475 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 476 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 477 #define PMAP_HEAD_TO_MAP_LOCK() \ 478 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 479 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 480 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 481 #else 482 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 483 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 484 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 485 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 486 #endif 487 488 #define pmap_acquire_pmap_lock(pm) \ 489 do { \ 490 if ((pm) != pmap_kernel()) \ 491 mutex_enter(&(pm)->pm_lock); \ 492 } while (/*CONSTCOND*/0) 493 494 #define pmap_release_pmap_lock(pm) \ 495 do { \ 496 if ((pm) != pmap_kernel()) \ 497 mutex_exit(&(pm)->pm_lock); \ 498 } while (/*CONSTCOND*/0) 499 500 501 /* 502 * Metadata for L1 translation tables. 503 */ 504 struct l1_ttable { 505 /* Entry on the L1 Table list */ 506 SLIST_ENTRY(l1_ttable) l1_link; 507 508 /* Entry on the L1 Least Recently Used list */ 509 TAILQ_ENTRY(l1_ttable) l1_lru; 510 511 /* Track how many domains are allocated from this L1 */ 512 volatile u_int l1_domain_use_count; 513 514 /* 515 * A free-list of domain numbers for this L1. 516 * We avoid using ffs() and a bitmap to track domains since ffs() 517 * is slow on ARM. 518 */ 519 u_int8_t l1_domain_first; 520 u_int8_t l1_domain_free[PMAP_DOMAINS]; 521 522 /* Physical address of this L1 page table */ 523 paddr_t l1_physaddr; 524 525 /* KVA of this L1 page table */ 526 pd_entry_t *l1_kva; 527 }; 528 529 /* 530 * Convert a virtual address into its L1 table index. That is, the 531 * index used to locate the L2 descriptor table pointer in an L1 table. 532 * This is basically used to index l1->l1_kva[]. 533 * 534 * Each L2 descriptor table represents 1MB of VA space. 535 */ 536 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 537 538 /* 539 * L1 Page Tables are tracked using a Least Recently Used list. 540 * - New L1s are allocated from the HEAD. 541 * - Freed L1s are added to the TAIl. 542 * - Recently accessed L1s (where an 'access' is some change to one of 543 * the userland pmaps which owns this L1) are moved to the TAIL. 544 */ 545 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 546 static struct simplelock l1_lru_lock; 547 548 /* 549 * A list of all L1 tables 550 */ 551 static SLIST_HEAD(, l1_ttable) l1_list; 552 553 /* 554 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 555 * 556 * This is normally 16MB worth L2 page descriptors for any given pmap. 557 * Reference counts are maintained for L2 descriptors so they can be 558 * freed when empty. 559 */ 560 struct l2_dtable { 561 /* The number of L2 page descriptors allocated to this l2_dtable */ 562 u_int l2_occupancy; 563 564 /* List of L2 page descriptors */ 565 struct l2_bucket { 566 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 567 paddr_t l2b_phys; /* Physical address of same */ 568 u_short l2b_l1idx; /* This L2 table's L1 index */ 569 u_short l2b_occupancy; /* How many active descriptors */ 570 } l2_bucket[L2_BUCKET_SIZE]; 571 }; 572 573 /* 574 * Given an L1 table index, calculate the corresponding l2_dtable index 575 * and bucket index within the l2_dtable. 576 */ 577 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 578 (L2_SIZE - 1)) 579 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 580 581 /* 582 * Given a virtual address, this macro returns the 583 * virtual address required to drop into the next L2 bucket. 584 */ 585 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 586 587 /* 588 * L2 allocation. 589 */ 590 #define pmap_alloc_l2_dtable() \ 591 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 592 #define pmap_free_l2_dtable(l2) \ 593 pool_cache_put(&pmap_l2dtable_cache, (l2)) 594 #define pmap_alloc_l2_ptp(pap) \ 595 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 596 PR_NOWAIT, (pap))) 597 598 /* 599 * We try to map the page tables write-through, if possible. However, not 600 * all CPUs have a write-through cache mode, so on those we have to sync 601 * the cache when we frob page tables. 602 * 603 * We try to evaluate this at compile time, if possible. However, it's 604 * not always possible to do that, hence this run-time var. 605 */ 606 int pmap_needs_pte_sync; 607 608 /* 609 * Real definition of pv_entry. 610 */ 611 struct pv_entry { 612 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 613 pmap_t pv_pmap; /* pmap where mapping lies */ 614 vaddr_t pv_va; /* virtual address for mapping */ 615 u_int pv_flags; /* flags */ 616 }; 617 618 /* 619 * Macro to determine if a mapping might be resident in the 620 * instruction cache and/or TLB 621 */ 622 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 623 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 624 625 /* 626 * Macro to determine if a mapping might be resident in the 627 * data cache and/or TLB 628 */ 629 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 630 631 /* 632 * Local prototypes 633 */ 634 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 635 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 636 pt_entry_t **); 637 static bool pmap_is_current(pmap_t); 638 static bool pmap_is_cached(pmap_t); 639 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 640 pmap_t, vaddr_t, u_int); 641 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 642 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t); 643 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 644 u_int, u_int); 645 646 static void pmap_pinit(pmap_t); 647 static int pmap_pmap_ctor(void *, void *, int); 648 649 static void pmap_alloc_l1(pmap_t); 650 static void pmap_free_l1(pmap_t); 651 static void pmap_use_l1(pmap_t); 652 653 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 654 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 655 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 656 static int pmap_l2ptp_ctor(void *, void *, int); 657 static int pmap_l2dtable_ctor(void *, void *, int); 658 659 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 660 #ifdef PMAP_CACHE_VIVT 661 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 662 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 663 #endif 664 665 static void pmap_clearbit(struct vm_page *, u_int); 666 #ifdef PMAP_CACHE_VIVT 667 static int pmap_clean_page(struct pv_entry *, bool); 668 #endif 669 #ifdef PMAP_CACHE_VIPT 670 static void pmap_syncicache_page(struct vm_page *); 671 enum pmap_flush_op { 672 PMAP_FLUSH_PRIMARY, 673 PMAP_FLUSH_SECONDARY, 674 PMAP_CLEAN_PRIMARY 675 }; 676 static void pmap_flush_page(struct vm_page *, enum pmap_flush_op); 677 #endif 678 static void pmap_page_remove(struct vm_page *); 679 680 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 681 static vaddr_t kernel_pt_lookup(paddr_t); 682 683 684 /* 685 * External function prototypes 686 */ 687 extern void bzero_page(vaddr_t); 688 extern void bcopy_page(vaddr_t, vaddr_t); 689 690 /* 691 * Misc variables 692 */ 693 vaddr_t virtual_avail; 694 vaddr_t virtual_end; 695 vaddr_t pmap_curmaxkvaddr; 696 697 paddr_t avail_start; 698 paddr_t avail_end; 699 700 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 701 pv_addr_t kernelpages; 702 pv_addr_t kernel_l1pt; 703 pv_addr_t systempage; 704 705 /* Function to set the debug level of the pmap code */ 706 707 #ifdef PMAP_DEBUG 708 void 709 pmap_debug(int level) 710 { 711 pmap_debug_level = level; 712 printf("pmap_debug: level=%d\n", pmap_debug_level); 713 } 714 #endif /* PMAP_DEBUG */ 715 716 /* 717 * A bunch of routines to conditionally flush the caches/TLB depending 718 * on whether the specified pmap actually needs to be flushed at any 719 * given time. 720 */ 721 static inline void 722 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 723 { 724 725 if (pm->pm_cstate.cs_tlb_id) 726 cpu_tlb_flushID_SE(va); 727 } 728 729 static inline void 730 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 731 { 732 733 if (pm->pm_cstate.cs_tlb_d) 734 cpu_tlb_flushD_SE(va); 735 } 736 737 static inline void 738 pmap_tlb_flushID(pmap_t pm) 739 { 740 741 if (pm->pm_cstate.cs_tlb_id) { 742 cpu_tlb_flushID(); 743 pm->pm_cstate.cs_tlb = 0; 744 } 745 } 746 747 static inline void 748 pmap_tlb_flushD(pmap_t pm) 749 { 750 751 if (pm->pm_cstate.cs_tlb_d) { 752 cpu_tlb_flushD(); 753 pm->pm_cstate.cs_tlb_d = 0; 754 } 755 } 756 757 #ifdef PMAP_CACHE_VIVT 758 static inline void 759 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 760 { 761 if (pm->pm_cstate.cs_cache_id) { 762 cpu_idcache_wbinv_range(va, len); 763 } 764 } 765 766 static inline void 767 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 768 bool do_inv, bool rd_only) 769 { 770 771 if (pm->pm_cstate.cs_cache_d) { 772 if (do_inv) { 773 if (rd_only) 774 cpu_dcache_inv_range(va, len); 775 else 776 cpu_dcache_wbinv_range(va, len); 777 } else 778 if (!rd_only) 779 cpu_dcache_wb_range(va, len); 780 } 781 } 782 783 static inline void 784 pmap_idcache_wbinv_all(pmap_t pm) 785 { 786 if (pm->pm_cstate.cs_cache_id) { 787 cpu_idcache_wbinv_all(); 788 pm->pm_cstate.cs_cache = 0; 789 } 790 } 791 792 static inline void 793 pmap_dcache_wbinv_all(pmap_t pm) 794 { 795 if (pm->pm_cstate.cs_cache_d) { 796 cpu_dcache_wbinv_all(); 797 pm->pm_cstate.cs_cache_d = 0; 798 } 799 } 800 #endif /* PMAP_CACHE_VIVT */ 801 802 static inline bool 803 pmap_is_current(pmap_t pm) 804 { 805 806 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 807 return true; 808 809 return false; 810 } 811 812 static inline bool 813 pmap_is_cached(pmap_t pm) 814 { 815 816 if (pm == pmap_kernel() || pmap_recent_user == NULL || 817 pmap_recent_user == pm) 818 return (true); 819 820 return false; 821 } 822 823 /* 824 * PTE_SYNC_CURRENT: 825 * 826 * Make sure the pte is written out to RAM. 827 * We need to do this for one of two cases: 828 * - We're dealing with the kernel pmap 829 * - There is no pmap active in the cache/tlb. 830 * - The specified pmap is 'active' in the cache/tlb. 831 */ 832 #ifdef PMAP_INCLUDE_PTE_SYNC 833 #define PTE_SYNC_CURRENT(pm, ptep) \ 834 do { \ 835 if (PMAP_NEEDS_PTE_SYNC && \ 836 pmap_is_cached(pm)) \ 837 PTE_SYNC(ptep); \ 838 } while (/*CONSTCOND*/0) 839 #else 840 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 841 #endif 842 843 /* 844 * main pv_entry manipulation functions: 845 * pmap_enter_pv: enter a mapping onto a vm_page list 846 * pmap_remove_pv: remove a mappiing from a vm_page list 847 * 848 * NOTE: pmap_enter_pv expects to lock the pvh itself 849 * pmap_remove_pv expects te caller to lock the pvh before calling 850 */ 851 852 /* 853 * pmap_enter_pv: enter a mapping onto a vm_page lst 854 * 855 * => caller should hold the proper lock on pmap_main_lock 856 * => caller should have pmap locked 857 * => we will gain the lock on the vm_page and allocate the new pv_entry 858 * => caller should adjust ptp's wire_count before calling 859 * => caller should not adjust pmap's wire_count 860 */ 861 static void 862 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 863 vaddr_t va, u_int flags) 864 { 865 struct pv_entry **pvp; 866 867 NPDEBUG(PDB_PVDUMP, 868 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 869 870 pve->pv_pmap = pm; 871 pve->pv_va = va; 872 pve->pv_flags = flags; 873 874 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 875 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 876 #ifdef PMAP_CACHE_VIPT 877 /* 878 * Insert unmanaged entries, writeable first, at the head of 879 * the pv list. 880 */ 881 if (__predict_true((flags & PVF_KENTRY) == 0)) { 882 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 883 pvp = &SLIST_NEXT(*pvp, pv_link); 884 } else if ((flags & PVF_WRITE) == 0) { 885 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 886 pvp = &SLIST_NEXT(*pvp, pv_link); 887 } 888 #endif 889 SLIST_NEXT(pve, pv_link) = *pvp; /* add to ... */ 890 *pvp = pve; /* ... locked list */ 891 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 892 #ifdef PMAP_CACHE_VIPT 893 if ((pve->pv_flags & PVF_KWRITE) == PVF_KWRITE) 894 pg->mdpage.pvh_attrs |= PVF_KMOD; 895 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 896 pg->mdpage.pvh_attrs |= PVF_DIRTY; 897 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 898 #endif 899 if (pm == pmap_kernel()) { 900 PMAPCOUNT(kernel_mappings); 901 if (flags & PVF_WRITE) 902 pg->mdpage.krw_mappings++; 903 else 904 pg->mdpage.kro_mappings++; 905 } else 906 if (flags & PVF_WRITE) 907 pg->mdpage.urw_mappings++; 908 else 909 pg->mdpage.uro_mappings++; 910 911 #ifdef PMAP_CACHE_VIPT 912 /* 913 * If this is an exec mapping and its the first exec mapping 914 * for this page, make sure to sync the I-cache. 915 */ 916 if (PV_IS_EXEC_P(flags)) { 917 if (!PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 918 pmap_syncicache_page(pg); 919 PMAPCOUNT(exec_synced_map); 920 } 921 PMAPCOUNT(exec_mappings); 922 } 923 #endif 924 925 PMAPCOUNT(mappings); 926 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 927 928 if (pve->pv_flags & PVF_WIRED) 929 ++pm->pm_stats.wired_count; 930 } 931 932 /* 933 * 934 * pmap_find_pv: Find a pv entry 935 * 936 * => caller should hold lock on vm_page 937 */ 938 static inline struct pv_entry * 939 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 940 { 941 struct pv_entry *pv; 942 943 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 944 if (pm == pv->pv_pmap && va == pv->pv_va) 945 break; 946 } 947 948 return (pv); 949 } 950 951 /* 952 * pmap_remove_pv: try to remove a mapping from a pv_list 953 * 954 * => caller should hold proper lock on pmap_main_lock 955 * => pmap should be locked 956 * => caller should hold lock on vm_page [so that attrs can be adjusted] 957 * => caller should adjust ptp's wire_count and free PTP if needed 958 * => caller should NOT adjust pmap's wire_count 959 * => we return the removed pve 960 */ 961 static struct pv_entry * 962 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 963 { 964 struct pv_entry *pve, **prevptr; 965 966 NPDEBUG(PDB_PVDUMP, 967 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 968 969 prevptr = &SLIST_FIRST(&pg->mdpage.pvh_list); /* prev pv_entry ptr */ 970 pve = *prevptr; 971 972 while (pve) { 973 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 974 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, pg " 975 "%p, flags 0x%x\n", pm, pg, pve->pv_flags)); 976 if (pve->pv_flags & PVF_WIRED) { 977 --pm->pm_stats.wired_count; 978 } 979 *prevptr = SLIST_NEXT(pve, pv_link); /* remove it! */ 980 if (pm == pmap_kernel()) { 981 PMAPCOUNT(kernel_unmappings); 982 if (pve->pv_flags & PVF_WRITE) 983 pg->mdpage.krw_mappings--; 984 else 985 pg->mdpage.kro_mappings--; 986 } else 987 if (pve->pv_flags & PVF_WRITE) 988 pg->mdpage.urw_mappings--; 989 else 990 pg->mdpage.uro_mappings--; 991 992 PMAPCOUNT(unmappings); 993 #ifdef PMAP_CACHE_VIPT 994 if (!(pve->pv_flags & PVF_WRITE)) 995 break; 996 /* 997 * If this page has had an exec mapping, then if 998 * this was the last mapping, discard the contents, 999 * otherwise sync the i-cache for this page. 1000 */ 1001 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 1002 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 1003 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 1004 PMAPCOUNT(exec_discarded_unmap); 1005 } else { 1006 pmap_syncicache_page(pg); 1007 PMAPCOUNT(exec_synced_unmap); 1008 } 1009 } 1010 #endif /* PMAP_CACHE_VIPT */ 1011 break; 1012 } 1013 prevptr = &SLIST_NEXT(pve, pv_link); /* previous pointer */ 1014 pve = *prevptr; /* advance */ 1015 } 1016 1017 #ifdef PMAP_CACHE_VIPT 1018 /* 1019 * If we no longer have a WRITEABLE KENTRY at the head of list, 1020 * clear the KMOD attribute from the page. 1021 */ 1022 if (SLIST_FIRST(&pg->mdpage.pvh_list) == NULL 1023 || (SLIST_FIRST(&pg->mdpage.pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1024 pg->mdpage.pvh_attrs &= ~PVF_KMOD; 1025 1026 /* 1027 * If this was a writeable page and there are no more writeable 1028 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1029 * the contents to memory. 1030 */ 1031 if (pg->mdpage.krw_mappings + pg->mdpage.urw_mappings == 0) 1032 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1033 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1034 #endif /* PMAP_CACHE_VIPT */ 1035 1036 return(pve); /* return removed pve */ 1037 } 1038 1039 /* 1040 * 1041 * pmap_modify_pv: Update pv flags 1042 * 1043 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1044 * => caller should NOT adjust pmap's wire_count 1045 * => caller must call pmap_vac_me_harder() if writable status of a page 1046 * may have changed. 1047 * => we return the old flags 1048 * 1049 * Modify a physical-virtual mapping in the pv table 1050 */ 1051 static u_int 1052 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 1053 u_int clr_mask, u_int set_mask) 1054 { 1055 struct pv_entry *npv; 1056 u_int flags, oflags; 1057 1058 KASSERT((clr_mask & PVF_KENTRY) == 0); 1059 KASSERT((set_mask & PVF_KENTRY) == 0); 1060 1061 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1062 return (0); 1063 1064 NPDEBUG(PDB_PVDUMP, 1065 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 1066 1067 /* 1068 * There is at least one VA mapping this page. 1069 */ 1070 1071 if (clr_mask & (PVF_REF | PVF_MOD)) { 1072 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1073 #ifdef PMAP_CACHE_VIPT 1074 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1075 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1076 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1077 #endif 1078 } 1079 1080 oflags = npv->pv_flags; 1081 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1082 1083 if ((flags ^ oflags) & PVF_WIRED) { 1084 if (flags & PVF_WIRED) 1085 ++pm->pm_stats.wired_count; 1086 else 1087 --pm->pm_stats.wired_count; 1088 } 1089 1090 if ((flags ^ oflags) & PVF_WRITE) { 1091 if (pm == pmap_kernel()) { 1092 if (flags & PVF_WRITE) { 1093 pg->mdpage.krw_mappings++; 1094 pg->mdpage.kro_mappings--; 1095 } else { 1096 pg->mdpage.kro_mappings++; 1097 pg->mdpage.krw_mappings--; 1098 } 1099 } else 1100 if (flags & PVF_WRITE) { 1101 pg->mdpage.urw_mappings++; 1102 pg->mdpage.uro_mappings--; 1103 } else { 1104 pg->mdpage.uro_mappings++; 1105 pg->mdpage.urw_mappings--; 1106 } 1107 } 1108 #ifdef PMAP_CACHE_VIPT 1109 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 1110 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1111 /* 1112 * We have two cases here: the first is from enter_pv (new exec 1113 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1114 * Since in latter, pmap_enter_pv won't do anything, we just have 1115 * to do what pmap_remove_pv would do. 1116 */ 1117 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 1118 || (PV_IS_EXEC_P(pg->mdpage.pvh_attrs) 1119 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1120 pmap_syncicache_page(pg); 1121 PMAPCOUNT(exec_synced_remap); 1122 } 1123 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1124 #endif 1125 1126 PMAPCOUNT(remappings); 1127 1128 return (oflags); 1129 } 1130 1131 /* 1132 * Allocate an L1 translation table for the specified pmap. 1133 * This is called at pmap creation time. 1134 */ 1135 static void 1136 pmap_alloc_l1(pmap_t pm) 1137 { 1138 struct l1_ttable *l1; 1139 u_int8_t domain; 1140 1141 /* 1142 * Remove the L1 at the head of the LRU list 1143 */ 1144 simple_lock(&l1_lru_lock); 1145 l1 = TAILQ_FIRST(&l1_lru_list); 1146 KDASSERT(l1 != NULL); 1147 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1148 1149 /* 1150 * Pick the first available domain number, and update 1151 * the link to the next number. 1152 */ 1153 domain = l1->l1_domain_first; 1154 l1->l1_domain_first = l1->l1_domain_free[domain]; 1155 1156 /* 1157 * If there are still free domain numbers in this L1, 1158 * put it back on the TAIL of the LRU list. 1159 */ 1160 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1161 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1162 1163 simple_unlock(&l1_lru_lock); 1164 1165 /* 1166 * Fix up the relevant bits in the pmap structure 1167 */ 1168 pm->pm_l1 = l1; 1169 pm->pm_domain = domain; 1170 } 1171 1172 /* 1173 * Free an L1 translation table. 1174 * This is called at pmap destruction time. 1175 */ 1176 static void 1177 pmap_free_l1(pmap_t pm) 1178 { 1179 struct l1_ttable *l1 = pm->pm_l1; 1180 1181 simple_lock(&l1_lru_lock); 1182 1183 /* 1184 * If this L1 is currently on the LRU list, remove it. 1185 */ 1186 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1187 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1188 1189 /* 1190 * Free up the domain number which was allocated to the pmap 1191 */ 1192 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1193 l1->l1_domain_first = pm->pm_domain; 1194 l1->l1_domain_use_count--; 1195 1196 /* 1197 * The L1 now must have at least 1 free domain, so add 1198 * it back to the LRU list. If the use count is zero, 1199 * put it at the head of the list, otherwise it goes 1200 * to the tail. 1201 */ 1202 if (l1->l1_domain_use_count == 0) 1203 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1204 else 1205 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1206 1207 simple_unlock(&l1_lru_lock); 1208 } 1209 1210 static inline void 1211 pmap_use_l1(pmap_t pm) 1212 { 1213 struct l1_ttable *l1; 1214 1215 /* 1216 * Do nothing if we're in interrupt context. 1217 * Access to an L1 by the kernel pmap must not affect 1218 * the LRU list. 1219 */ 1220 if (cpu_intr_p() || pm == pmap_kernel()) 1221 return; 1222 1223 l1 = pm->pm_l1; 1224 1225 /* 1226 * If the L1 is not currently on the LRU list, just return 1227 */ 1228 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1229 return; 1230 1231 simple_lock(&l1_lru_lock); 1232 1233 /* 1234 * Check the use count again, now that we've acquired the lock 1235 */ 1236 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1237 simple_unlock(&l1_lru_lock); 1238 return; 1239 } 1240 1241 /* 1242 * Move the L1 to the back of the LRU list 1243 */ 1244 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1245 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1246 1247 simple_unlock(&l1_lru_lock); 1248 } 1249 1250 /* 1251 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1252 * 1253 * Free an L2 descriptor table. 1254 */ 1255 static inline void 1256 #ifndef PMAP_INCLUDE_PTE_SYNC 1257 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1258 #else 1259 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1260 #endif 1261 { 1262 #ifdef PMAP_INCLUDE_PTE_SYNC 1263 #ifdef PMAP_CACHE_VIVT 1264 /* 1265 * Note: With a write-back cache, we may need to sync this 1266 * L2 table before re-using it. 1267 * This is because it may have belonged to a non-current 1268 * pmap, in which case the cache syncs would have been 1269 * skipped for the pages that were being unmapped. If the 1270 * L2 table were then to be immediately re-allocated to 1271 * the *current* pmap, it may well contain stale mappings 1272 * which have not yet been cleared by a cache write-back 1273 * and so would still be visible to the mmu. 1274 */ 1275 if (need_sync) 1276 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1277 #endif /* PMAP_CACHE_VIVT */ 1278 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1279 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1280 } 1281 1282 /* 1283 * Returns a pointer to the L2 bucket associated with the specified pmap 1284 * and VA, or NULL if no L2 bucket exists for the address. 1285 */ 1286 static inline struct l2_bucket * 1287 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1288 { 1289 struct l2_dtable *l2; 1290 struct l2_bucket *l2b; 1291 u_short l1idx; 1292 1293 l1idx = L1_IDX(va); 1294 1295 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1296 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1297 return (NULL); 1298 1299 return (l2b); 1300 } 1301 1302 /* 1303 * Returns a pointer to the L2 bucket associated with the specified pmap 1304 * and VA. 1305 * 1306 * If no L2 bucket exists, perform the necessary allocations to put an L2 1307 * bucket/page table in place. 1308 * 1309 * Note that if a new L2 bucket/page was allocated, the caller *must* 1310 * increment the bucket occupancy counter appropriately *before* 1311 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1312 * the bucket/page in the meantime. 1313 */ 1314 static struct l2_bucket * 1315 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1316 { 1317 struct l2_dtable *l2; 1318 struct l2_bucket *l2b; 1319 u_short l1idx; 1320 1321 l1idx = L1_IDX(va); 1322 1323 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1324 /* 1325 * No mapping at this address, as there is 1326 * no entry in the L1 table. 1327 * Need to allocate a new l2_dtable. 1328 */ 1329 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1330 return (NULL); 1331 1332 /* 1333 * Link it into the parent pmap 1334 */ 1335 pm->pm_l2[L2_IDX(l1idx)] = l2; 1336 } 1337 1338 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1339 1340 /* 1341 * Fetch pointer to the L2 page table associated with the address. 1342 */ 1343 if (l2b->l2b_kva == NULL) { 1344 pt_entry_t *ptep; 1345 1346 /* 1347 * No L2 page table has been allocated. Chances are, this 1348 * is because we just allocated the l2_dtable, above. 1349 */ 1350 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1351 /* 1352 * Oops, no more L2 page tables available at this 1353 * time. We may need to deallocate the l2_dtable 1354 * if we allocated a new one above. 1355 */ 1356 if (l2->l2_occupancy == 0) { 1357 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1358 pmap_free_l2_dtable(l2); 1359 } 1360 return (NULL); 1361 } 1362 1363 l2->l2_occupancy++; 1364 l2b->l2b_kva = ptep; 1365 l2b->l2b_l1idx = l1idx; 1366 } 1367 1368 return (l2b); 1369 } 1370 1371 /* 1372 * One or more mappings in the specified L2 descriptor table have just been 1373 * invalidated. 1374 * 1375 * Garbage collect the metadata and descriptor table itself if necessary. 1376 * 1377 * The pmap lock must be acquired when this is called (not necessary 1378 * for the kernel pmap). 1379 */ 1380 static void 1381 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1382 { 1383 struct l2_dtable *l2; 1384 pd_entry_t *pl1pd, l1pd; 1385 pt_entry_t *ptep; 1386 u_short l1idx; 1387 1388 KDASSERT(count <= l2b->l2b_occupancy); 1389 1390 /* 1391 * Update the bucket's reference count according to how many 1392 * PTEs the caller has just invalidated. 1393 */ 1394 l2b->l2b_occupancy -= count; 1395 1396 /* 1397 * Note: 1398 * 1399 * Level 2 page tables allocated to the kernel pmap are never freed 1400 * as that would require checking all Level 1 page tables and 1401 * removing any references to the Level 2 page table. See also the 1402 * comment elsewhere about never freeing bootstrap L2 descriptors. 1403 * 1404 * We make do with just invalidating the mapping in the L2 table. 1405 * 1406 * This isn't really a big deal in practice and, in fact, leads 1407 * to a performance win over time as we don't need to continually 1408 * alloc/free. 1409 */ 1410 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1411 return; 1412 1413 /* 1414 * There are no more valid mappings in this level 2 page table. 1415 * Go ahead and NULL-out the pointer in the bucket, then 1416 * free the page table. 1417 */ 1418 l1idx = l2b->l2b_l1idx; 1419 ptep = l2b->l2b_kva; 1420 l2b->l2b_kva = NULL; 1421 1422 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1423 1424 /* 1425 * If the L1 slot matches the pmap's domain 1426 * number, then invalidate it. 1427 */ 1428 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1429 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1430 *pl1pd = 0; 1431 PTE_SYNC(pl1pd); 1432 } 1433 1434 /* 1435 * Release the L2 descriptor table back to the pool cache. 1436 */ 1437 #ifndef PMAP_INCLUDE_PTE_SYNC 1438 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1439 #else 1440 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1441 #endif 1442 1443 /* 1444 * Update the reference count in the associated l2_dtable 1445 */ 1446 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1447 if (--l2->l2_occupancy > 0) 1448 return; 1449 1450 /* 1451 * There are no more valid mappings in any of the Level 1 1452 * slots managed by this l2_dtable. Go ahead and NULL-out 1453 * the pointer in the parent pmap and free the l2_dtable. 1454 */ 1455 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1456 pmap_free_l2_dtable(l2); 1457 } 1458 1459 /* 1460 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1461 * structures. 1462 */ 1463 static int 1464 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1465 { 1466 #ifndef PMAP_INCLUDE_PTE_SYNC 1467 struct l2_bucket *l2b; 1468 pt_entry_t *ptep, pte; 1469 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1470 1471 /* 1472 * The mappings for these page tables were initially made using 1473 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1474 * mode will not be right for page table mappings. To avoid 1475 * polluting the pmap_kenter_pa() code with a special case for 1476 * page tables, we simply fix up the cache-mode here if it's not 1477 * correct. 1478 */ 1479 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1480 KDASSERT(l2b != NULL); 1481 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1482 pte = *ptep; 1483 1484 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1485 /* 1486 * Page tables must have the cache-mode set to Write-Thru. 1487 */ 1488 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1489 PTE_SYNC(ptep); 1490 cpu_tlb_flushD_SE(va); 1491 cpu_cpwait(); 1492 } 1493 #endif 1494 1495 memset(v, 0, L2_TABLE_SIZE_REAL); 1496 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1497 return (0); 1498 } 1499 1500 static int 1501 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1502 { 1503 1504 memset(v, 0, sizeof(struct l2_dtable)); 1505 return (0); 1506 } 1507 1508 static int 1509 pmap_pmap_ctor(void *arg, void *v, int flags) 1510 { 1511 1512 memset(v, 0, sizeof(struct pmap)); 1513 return (0); 1514 } 1515 1516 static void 1517 pmap_pinit(pmap_t pm) 1518 { 1519 struct l2_bucket *l2b; 1520 1521 if (vector_page < KERNEL_BASE) { 1522 /* 1523 * Map the vector page. 1524 */ 1525 pmap_enter(pm, vector_page, systempage.pv_pa, 1526 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1527 pmap_update(pm); 1528 1529 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1530 l2b = pmap_get_l2_bucket(pm, vector_page); 1531 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1532 L1_C_DOM(pm->pm_domain); 1533 } else 1534 pm->pm_pl1vec = NULL; 1535 } 1536 1537 #ifdef PMAP_CACHE_VIVT 1538 /* 1539 * Since we have a virtually indexed cache, we may need to inhibit caching if 1540 * there is more than one mapping and at least one of them is writable. 1541 * Since we purge the cache on every context switch, we only need to check for 1542 * other mappings within the same pmap, or kernel_pmap. 1543 * This function is also called when a page is unmapped, to possibly reenable 1544 * caching on any remaining mappings. 1545 * 1546 * The code implements the following logic, where: 1547 * 1548 * KW = # of kernel read/write pages 1549 * KR = # of kernel read only pages 1550 * UW = # of user read/write pages 1551 * UR = # of user read only pages 1552 * 1553 * KC = kernel mapping is cacheable 1554 * UC = user mapping is cacheable 1555 * 1556 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1557 * +--------------------------------------------- 1558 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1559 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1560 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1561 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1562 */ 1563 1564 static const int pmap_vac_flags[4][4] = { 1565 {-1, 0, 0, PVF_KNC}, 1566 {0, 0, PVF_NC, PVF_NC}, 1567 {0, PVF_NC, PVF_NC, PVF_NC}, 1568 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1569 }; 1570 1571 static inline int 1572 pmap_get_vac_flags(const struct vm_page *pg) 1573 { 1574 int kidx, uidx; 1575 1576 kidx = 0; 1577 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1578 kidx |= 1; 1579 if (pg->mdpage.krw_mappings) 1580 kidx |= 2; 1581 1582 uidx = 0; 1583 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1584 uidx |= 1; 1585 if (pg->mdpage.urw_mappings) 1586 uidx |= 2; 1587 1588 return (pmap_vac_flags[uidx][kidx]); 1589 } 1590 1591 static inline void 1592 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1593 { 1594 int nattr; 1595 1596 nattr = pmap_get_vac_flags(pg); 1597 1598 if (nattr < 0) { 1599 pg->mdpage.pvh_attrs &= ~PVF_NC; 1600 return; 1601 } 1602 1603 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1604 return; 1605 1606 if (pm == pmap_kernel()) 1607 pmap_vac_me_kpmap(pg, pm, va); 1608 else 1609 pmap_vac_me_user(pg, pm, va); 1610 1611 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1612 } 1613 1614 static void 1615 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1616 { 1617 u_int u_cacheable, u_entries; 1618 struct pv_entry *pv; 1619 pmap_t last_pmap = pm; 1620 1621 /* 1622 * Pass one, see if there are both kernel and user pmaps for 1623 * this page. Calculate whether there are user-writable or 1624 * kernel-writable pages. 1625 */ 1626 u_cacheable = 0; 1627 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1628 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1629 u_cacheable++; 1630 } 1631 1632 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1633 1634 /* 1635 * We know we have just been updating a kernel entry, so if 1636 * all user pages are already cacheable, then there is nothing 1637 * further to do. 1638 */ 1639 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1640 return; 1641 1642 if (u_entries) { 1643 /* 1644 * Scan over the list again, for each entry, if it 1645 * might not be set correctly, call pmap_vac_me_user 1646 * to recalculate the settings. 1647 */ 1648 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1649 /* 1650 * We know kernel mappings will get set 1651 * correctly in other calls. We also know 1652 * that if the pmap is the same as last_pmap 1653 * then we've just handled this entry. 1654 */ 1655 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1656 continue; 1657 1658 /* 1659 * If there are kernel entries and this page 1660 * is writable but non-cacheable, then we can 1661 * skip this entry also. 1662 */ 1663 if (pg->mdpage.k_mappings && 1664 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1665 (PVF_NC | PVF_WRITE)) 1666 continue; 1667 1668 /* 1669 * Similarly if there are no kernel-writable 1670 * entries and the page is already 1671 * read-only/cacheable. 1672 */ 1673 if (pg->mdpage.krw_mappings == 0 && 1674 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1675 continue; 1676 1677 /* 1678 * For some of the remaining cases, we know 1679 * that we must recalculate, but for others we 1680 * can't tell if they are correct or not, so 1681 * we recalculate anyway. 1682 */ 1683 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1684 } 1685 1686 if (pg->mdpage.k_mappings == 0) 1687 return; 1688 } 1689 1690 pmap_vac_me_user(pg, pm, va); 1691 } 1692 1693 static void 1694 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1695 { 1696 pmap_t kpmap = pmap_kernel(); 1697 struct pv_entry *pv, *npv = NULL; 1698 struct l2_bucket *l2b; 1699 pt_entry_t *ptep, pte; 1700 u_int entries = 0; 1701 u_int writable = 0; 1702 u_int cacheable_entries = 0; 1703 u_int kern_cacheable = 0; 1704 u_int other_writable = 0; 1705 1706 /* 1707 * Count mappings and writable mappings in this pmap. 1708 * Include kernel mappings as part of our own. 1709 * Keep a pointer to the first one. 1710 */ 1711 npv = NULL; 1712 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 1713 /* Count mappings in the same pmap */ 1714 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1715 if (entries++ == 0) 1716 npv = pv; 1717 1718 /* Cacheable mappings */ 1719 if ((pv->pv_flags & PVF_NC) == 0) { 1720 cacheable_entries++; 1721 if (kpmap == pv->pv_pmap) 1722 kern_cacheable++; 1723 } 1724 1725 /* Writable mappings */ 1726 if (pv->pv_flags & PVF_WRITE) 1727 ++writable; 1728 } else 1729 if (pv->pv_flags & PVF_WRITE) 1730 other_writable = 1; 1731 } 1732 1733 /* 1734 * Enable or disable caching as necessary. 1735 * Note: the first entry might be part of the kernel pmap, 1736 * so we can't assume this is indicative of the state of the 1737 * other (maybe non-kpmap) entries. 1738 */ 1739 if ((entries > 1 && writable) || 1740 (entries > 0 && pm == kpmap && other_writable)) { 1741 if (cacheable_entries == 0) 1742 return; 1743 1744 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1745 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1746 (pv->pv_flags & PVF_NC)) 1747 continue; 1748 1749 pv->pv_flags |= PVF_NC; 1750 1751 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1752 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1753 pte = *ptep & ~L2_S_CACHE_MASK; 1754 1755 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1756 l2pte_valid(pte)) { 1757 if (PV_BEEN_EXECD(pv->pv_flags)) { 1758 #ifdef PMAP_CACHE_VIVT 1759 pmap_idcache_wbinv_range(pv->pv_pmap, 1760 pv->pv_va, PAGE_SIZE); 1761 #endif 1762 pmap_tlb_flushID_SE(pv->pv_pmap, 1763 pv->pv_va); 1764 } else 1765 if (PV_BEEN_REFD(pv->pv_flags)) { 1766 #ifdef PMAP_CACHE_VIVT 1767 pmap_dcache_wb_range(pv->pv_pmap, 1768 pv->pv_va, PAGE_SIZE, true, 1769 (pv->pv_flags & PVF_WRITE) == 0); 1770 #endif 1771 pmap_tlb_flushD_SE(pv->pv_pmap, 1772 pv->pv_va); 1773 } 1774 } 1775 1776 *ptep = pte; 1777 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1778 } 1779 cpu_cpwait(); 1780 } else 1781 if (entries > cacheable_entries) { 1782 /* 1783 * Turn cacheing back on for some pages. If it is a kernel 1784 * page, only do so if there are no other writable pages. 1785 */ 1786 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1787 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1788 (kpmap != pv->pv_pmap || other_writable))) 1789 continue; 1790 1791 pv->pv_flags &= ~PVF_NC; 1792 1793 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1794 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1795 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1796 1797 if (l2pte_valid(pte)) { 1798 if (PV_BEEN_EXECD(pv->pv_flags)) { 1799 pmap_tlb_flushID_SE(pv->pv_pmap, 1800 pv->pv_va); 1801 } else 1802 if (PV_BEEN_REFD(pv->pv_flags)) { 1803 pmap_tlb_flushD_SE(pv->pv_pmap, 1804 pv->pv_va); 1805 } 1806 } 1807 1808 *ptep = pte; 1809 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1810 } 1811 } 1812 } 1813 #endif 1814 1815 #ifdef PMAP_CACHE_VIPT 1816 static void 1817 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1818 { 1819 struct pv_entry *pv; 1820 vaddr_t tst_mask; 1821 bool bad_alias; 1822 struct l2_bucket *l2b; 1823 pt_entry_t *ptep, pte, opte; 1824 const u_int 1825 rw_mappings = pg->mdpage.urw_mappings + pg->mdpage.krw_mappings, 1826 ro_mappings = pg->mdpage.uro_mappings + pg->mdpage.kro_mappings; 1827 1828 /* do we need to do anything? */ 1829 if (arm_cache_prefer_mask == 0) 1830 return; 1831 1832 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n", 1833 pg, pm, va)); 1834 1835 KASSERT(!va || pm); 1836 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1837 1838 /* Already a conflict? */ 1839 if (__predict_false(pg->mdpage.pvh_attrs & PVF_NC)) { 1840 /* just an add, things are already non-cached */ 1841 KASSERT(!(pg->mdpage.pvh_attrs & PVF_DIRTY)); 1842 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 1843 bad_alias = false; 1844 if (va) { 1845 PMAPCOUNT(vac_color_none); 1846 bad_alias = true; 1847 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1848 goto fixup; 1849 } 1850 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1851 /* the list can't be empty because it would be cachable */ 1852 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) { 1853 tst_mask = pg->mdpage.pvh_attrs; 1854 } else { 1855 KASSERT(pv); 1856 tst_mask = pv->pv_va; 1857 pv = SLIST_NEXT(pv, pv_link); 1858 } 1859 /* 1860 * Only check for a bad alias if we have writable mappings. 1861 */ 1862 tst_mask &= arm_cache_prefer_mask; 1863 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1864 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1865 /* if there's a bad alias, stop checking. */ 1866 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1867 bad_alias = true; 1868 } 1869 pg->mdpage.pvh_attrs |= PVF_WRITE; 1870 if (!bad_alias) 1871 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1872 } else { 1873 /* 1874 * We have only read-only mappings. Let's see if there 1875 * are multiple colors in use or if we mapped a KMPAGE. 1876 * If the latter, we have a bad alias. If the former, 1877 * we need to remember that. 1878 */ 1879 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1880 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1881 if (pg->mdpage.pvh_attrs & PVF_KMPAGE) 1882 bad_alias = true; 1883 break; 1884 } 1885 } 1886 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1887 /* 1888 * No KMPAGE and we exited early, so we must have 1889 * multiple color mappings. 1890 */ 1891 if (!bad_alias && pv != NULL) 1892 pg->mdpage.pvh_attrs |= PVF_MULTCLR; 1893 } 1894 1895 /* If no conflicting colors, set everything back to cached */ 1896 if (!bad_alias) { 1897 #ifdef DEBUG 1898 if ((pg->mdpage.pvh_attrs & PVF_WRITE) 1899 || ro_mappings < 2) { 1900 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1901 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1902 } 1903 #endif 1904 pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1905 pg->mdpage.pvh_attrs |= tst_mask | PVF_COLORED; 1906 /* 1907 * Restore DIRTY bit if page is modified 1908 */ 1909 if (pg->mdpage.pvh_attrs & PVF_DMOD) 1910 pg->mdpage.pvh_attrs |= PVF_DIRTY; 1911 PMAPCOUNT(vac_color_restore); 1912 } else { 1913 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 1914 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 1915 } 1916 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1917 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1918 } else if (!va) { 1919 KASSERT(pmap_is_page_colored_p(pg)); 1920 KASSERT(!(pg->mdpage.pvh_attrs & PVF_WRITE) 1921 || (pg->mdpage.pvh_attrs & PVF_DIRTY)); 1922 if (rw_mappings == 0) { 1923 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 1924 if (ro_mappings == 1 1925 && (pg->mdpage.pvh_attrs & PVF_MULTCLR)) { 1926 /* 1927 * If this is the last readonly mapping 1928 * but it doesn't match the current color 1929 * for the page, change the current color 1930 * to match this last readonly mapping. 1931 */ 1932 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 1933 tst_mask = (pg->mdpage.pvh_attrs ^ pv->pv_va) 1934 & arm_cache_prefer_mask; 1935 if (tst_mask) { 1936 pg->mdpage.pvh_attrs ^= tst_mask; 1937 PMAPCOUNT(vac_color_change); 1938 } 1939 } 1940 } 1941 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1942 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1943 return; 1944 } else if (!pmap_is_page_colored_p(pg)) { 1945 /* not colored so we just use its color */ 1946 KASSERT(pg->mdpage.pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1947 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 1948 PMAPCOUNT(vac_color_new); 1949 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 1950 pg->mdpage.pvh_attrs |= PVF_COLORED 1951 | (va & arm_cache_prefer_mask) 1952 | (rw_mappings > 0 ? PVF_WRITE : 0); 1953 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1954 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1955 return; 1956 } else if (((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1957 bad_alias = false; 1958 if (rw_mappings > 0) { 1959 /* 1960 * We now have writeable mappings and if we have 1961 * readonly mappings in more than once color, we have 1962 * an aliasing problem. Regardless mark the page as 1963 * writeable. 1964 */ 1965 if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 1966 if (ro_mappings < 2) { 1967 /* 1968 * If we only have less than two 1969 * read-only mappings, just flush the 1970 * non-primary colors from the cache. 1971 */ 1972 pmap_flush_page(pg, 1973 PMAP_FLUSH_SECONDARY); 1974 } else { 1975 bad_alias = true; 1976 } 1977 } 1978 pg->mdpage.pvh_attrs |= PVF_WRITE; 1979 } 1980 /* If no conflicting colors, set everything back to cached */ 1981 if (!bad_alias) { 1982 #ifdef DEBUG 1983 if (rw_mappings > 0 1984 || (pg->mdpage.pvh_attrs & PMAP_KMPAGE)) { 1985 tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 1986 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) 1987 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1988 } 1989 #endif 1990 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) 1991 PMAPCOUNT(vac_color_reuse); 1992 else 1993 PMAPCOUNT(vac_color_ok); 1994 1995 /* matching color, just return */ 1996 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 1997 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 1998 return; 1999 } 2000 KASSERT(SLIST_FIRST(&pg->mdpage.pvh_list) != NULL); 2001 KASSERT(SLIST_NEXT(SLIST_FIRST(&pg->mdpage.pvh_list), pv_link) != NULL); 2002 2003 /* color conflict. evict from cache. */ 2004 2005 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 2006 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2007 pg->mdpage.pvh_attrs |= PVF_NC; 2008 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2009 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 2010 PMAPCOUNT(vac_color_erase); 2011 } else if (rw_mappings == 0 2012 && (pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2013 KASSERT((pg->mdpage.pvh_attrs & PVF_WRITE) == 0); 2014 2015 /* 2016 * If the page has dirty cache lines, clean it. 2017 */ 2018 if (pg->mdpage.pvh_attrs & PVF_DIRTY) 2019 pmap_flush_page(pg, PMAP_CLEAN_PRIMARY); 2020 2021 /* 2022 * If this is the first remapping (we know that there are no 2023 * writeable mappings), then this is a simple color change. 2024 * Otherwise this is a seconary r/o mapping, which means 2025 * we don't have to do anything. 2026 */ 2027 if (ro_mappings == 1) { 2028 KASSERT(((pg->mdpage.pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2029 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2030 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2031 PMAPCOUNT(vac_color_change); 2032 } else { 2033 PMAPCOUNT(vac_color_blind); 2034 } 2035 pg->mdpage.pvh_attrs |= PVF_MULTCLR; 2036 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2037 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2038 return; 2039 } else { 2040 if (rw_mappings > 0) 2041 pg->mdpage.pvh_attrs |= PVF_WRITE; 2042 2043 /* color conflict. evict from cache. */ 2044 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 2045 2046 /* the list can't be empty because this was a enter/modify */ 2047 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2048 if ((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0) { 2049 KASSERT(pv); 2050 /* 2051 * If there's only one mapped page, change color to the 2052 * page's new color and return. Restore the DIRTY bit 2053 * that was erased by pmap_flush_page. 2054 */ 2055 if (SLIST_NEXT(pv, pv_link) == NULL) { 2056 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 2057 pg->mdpage.pvh_attrs |= (va & arm_cache_prefer_mask); 2058 if (pg->mdpage.pvh_attrs & PVF_DMOD) 2059 pg->mdpage.pvh_attrs |= PVF_DIRTY; 2060 PMAPCOUNT(vac_color_change); 2061 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2062 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2063 KASSERT(!(pg->mdpage.pvh_attrs & PVF_MULTCLR)); 2064 return; 2065 } 2066 } 2067 bad_alias = true; 2068 pg->mdpage.pvh_attrs &= ~PVF_COLORED; 2069 pg->mdpage.pvh_attrs |= PVF_NC; 2070 PMAPCOUNT(vac_color_erase); 2071 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 2072 } 2073 2074 fixup: 2075 KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2076 2077 /* 2078 * Turn cacheing on/off for all pages. 2079 */ 2080 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2081 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2082 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2083 opte = *ptep; 2084 pte = opte & ~L2_S_CACHE_MASK; 2085 if (bad_alias) { 2086 pv->pv_flags |= PVF_NC; 2087 } else { 2088 pv->pv_flags &= ~PVF_NC; 2089 pte |= pte_l2_s_cache_mode; 2090 } 2091 2092 if (opte == pte) /* only update is there's a change */ 2093 continue; 2094 2095 if (l2pte_valid(pte)) { 2096 if (PV_BEEN_EXECD(pv->pv_flags)) { 2097 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2098 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2099 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2100 } 2101 } 2102 2103 *ptep = pte; 2104 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2105 } 2106 } 2107 #endif /* PMAP_CACHE_VIPT */ 2108 2109 2110 /* 2111 * Modify pte bits for all ptes corresponding to the given physical address. 2112 * We use `maskbits' rather than `clearbits' because we're always passing 2113 * constants and the latter would require an extra inversion at run-time. 2114 */ 2115 static void 2116 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2117 { 2118 struct l2_bucket *l2b; 2119 struct pv_entry *pv; 2120 pt_entry_t *ptep, npte, opte; 2121 pmap_t pm; 2122 vaddr_t va; 2123 u_int oflags; 2124 #ifdef PMAP_CACHE_VIPT 2125 const bool want_syncicache = PV_IS_EXEC_P(pg->mdpage.pvh_attrs); 2126 bool need_syncicache = false; 2127 bool did_syncicache = false; 2128 bool need_vac_me_harder = false; 2129 #endif 2130 2131 NPDEBUG(PDB_BITS, 2132 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2133 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2134 2135 PMAP_HEAD_TO_MAP_LOCK(); 2136 simple_lock(&pg->mdpage.pvh_slock); 2137 2138 #ifdef PMAP_CACHE_VIPT 2139 /* 2140 * If we might want to sync the I-cache and we've modified it, 2141 * then we know we definitely need to sync or discard it. 2142 */ 2143 if (want_syncicache) 2144 need_syncicache = pg->mdpage.pvh_attrs & PVF_MOD; 2145 #endif 2146 /* 2147 * Clear saved attributes (modify, reference) 2148 */ 2149 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2150 2151 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 2152 #ifdef PMAP_CACHE_VIPT 2153 if (need_syncicache) { 2154 /* 2155 * No one has it mapped, so just discard it. The next 2156 * exec remapping will cause it to be synced. 2157 */ 2158 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2159 PMAPCOUNT(exec_discarded_clearbit); 2160 } 2161 #endif 2162 simple_unlock(&pg->mdpage.pvh_slock); 2163 PMAP_HEAD_TO_MAP_UNLOCK(); 2164 return; 2165 } 2166 2167 /* 2168 * Loop over all current mappings setting/clearing as appropos 2169 */ 2170 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 2171 va = pv->pv_va; 2172 pm = pv->pv_pmap; 2173 oflags = pv->pv_flags; 2174 /* 2175 * Kernel entries are unmanaged and as such not to be changed. 2176 */ 2177 if (oflags & PVF_KENTRY) 2178 continue; 2179 pv->pv_flags &= ~maskbits; 2180 2181 pmap_acquire_pmap_lock(pm); 2182 2183 l2b = pmap_get_l2_bucket(pm, va); 2184 KDASSERT(l2b != NULL); 2185 2186 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2187 npte = opte = *ptep; 2188 2189 NPDEBUG(PDB_BITS, 2190 printf( 2191 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2192 pv, pv->pv_pmap, pv->pv_va, oflags)); 2193 2194 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2195 #ifdef PMAP_CACHE_VIVT 2196 if ((pv->pv_flags & PVF_NC)) { 2197 /* 2198 * Entry is not cacheable: 2199 * 2200 * Don't turn caching on again if this is a 2201 * modified emulation. This would be 2202 * inconsitent with the settings created by 2203 * pmap_vac_me_harder(). Otherwise, it's safe 2204 * to re-enable cacheing. 2205 * 2206 * There's no need to call pmap_vac_me_harder() 2207 * here: all pages are losing their write 2208 * permission. 2209 */ 2210 if (maskbits & PVF_WRITE) { 2211 npte |= pte_l2_s_cache_mode; 2212 pv->pv_flags &= ~PVF_NC; 2213 } 2214 } else 2215 if (opte & L2_S_PROT_W) { 2216 /* 2217 * Entry is writable/cacheable: check if pmap 2218 * is current if it is flush it, otherwise it 2219 * won't be in the cache 2220 */ 2221 if (PV_BEEN_EXECD(oflags)) 2222 pmap_idcache_wbinv_range(pm, pv->pv_va, 2223 PAGE_SIZE); 2224 else 2225 if (PV_BEEN_REFD(oflags)) 2226 pmap_dcache_wb_range(pm, pv->pv_va, 2227 PAGE_SIZE, 2228 (maskbits & PVF_REF) != 0, false); 2229 } 2230 #endif 2231 2232 /* make the pte read only */ 2233 npte &= ~L2_S_PROT_W; 2234 2235 if (maskbits & oflags & PVF_WRITE) { 2236 /* 2237 * Keep alias accounting up to date 2238 */ 2239 if (pv->pv_pmap == pmap_kernel()) { 2240 pg->mdpage.krw_mappings--; 2241 pg->mdpage.kro_mappings++; 2242 } else { 2243 pg->mdpage.urw_mappings--; 2244 pg->mdpage.uro_mappings++; 2245 } 2246 #ifdef PMAP_CACHE_VIPT 2247 if (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) 2248 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2249 if (want_syncicache) 2250 need_syncicache = true; 2251 need_vac_me_harder = true; 2252 #endif 2253 } 2254 } 2255 2256 if (maskbits & PVF_REF) { 2257 if ((pv->pv_flags & PVF_NC) == 0 && 2258 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2259 l2pte_valid(npte)) { 2260 #ifdef PMAP_CACHE_VIVT 2261 /* 2262 * Check npte here; we may have already 2263 * done the wbinv above, and the validity 2264 * of the PTE is the same for opte and 2265 * npte. 2266 */ 2267 /* XXXJRT need idcache_inv_range */ 2268 if (PV_BEEN_EXECD(oflags)) 2269 pmap_idcache_wbinv_range(pm, 2270 pv->pv_va, PAGE_SIZE); 2271 else 2272 if (PV_BEEN_REFD(oflags)) 2273 pmap_dcache_wb_range(pm, 2274 pv->pv_va, PAGE_SIZE, 2275 true, true); 2276 #endif 2277 } 2278 2279 /* 2280 * Make the PTE invalid so that we will take a 2281 * page fault the next time the mapping is 2282 * referenced. 2283 */ 2284 npte &= ~L2_TYPE_MASK; 2285 npte |= L2_TYPE_INV; 2286 } 2287 2288 if (npte != opte) { 2289 *ptep = npte; 2290 PTE_SYNC(ptep); 2291 /* Flush the TLB entry if a current pmap. */ 2292 if (PV_BEEN_EXECD(oflags)) 2293 pmap_tlb_flushID_SE(pm, pv->pv_va); 2294 else 2295 if (PV_BEEN_REFD(oflags)) 2296 pmap_tlb_flushD_SE(pm, pv->pv_va); 2297 } 2298 2299 pmap_release_pmap_lock(pm); 2300 2301 NPDEBUG(PDB_BITS, 2302 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2303 pm, va, opte, npte)); 2304 } 2305 2306 #ifdef PMAP_CACHE_VIPT 2307 /* 2308 * If we need to sync the I-cache and we haven't done it yet, do it. 2309 */ 2310 if (need_syncicache && !did_syncicache) { 2311 pmap_syncicache_page(pg); 2312 PMAPCOUNT(exec_synced_clearbit); 2313 } 2314 /* 2315 * If we are changing this to read-only, we need to call vac_me_harder 2316 * so we can change all the read-only pages to cacheable. We pretend 2317 * this as a page deletion. 2318 */ 2319 if (need_vac_me_harder) { 2320 if (pg->mdpage.pvh_attrs & PVF_NC) 2321 pmap_vac_me_harder(pg, NULL, 0); 2322 } 2323 #endif 2324 2325 simple_unlock(&pg->mdpage.pvh_slock); 2326 PMAP_HEAD_TO_MAP_UNLOCK(); 2327 } 2328 2329 /* 2330 * pmap_clean_page() 2331 * 2332 * This is a local function used to work out the best strategy to clean 2333 * a single page referenced by its entry in the PV table. It's used by 2334 * pmap_copy_page, pmap_zero page and maybe some others later on. 2335 * 2336 * Its policy is effectively: 2337 * o If there are no mappings, we don't bother doing anything with the cache. 2338 * o If there is one mapping, we clean just that page. 2339 * o If there are multiple mappings, we clean the entire cache. 2340 * 2341 * So that some functions can be further optimised, it returns 0 if it didn't 2342 * clean the entire cache, or 1 if it did. 2343 * 2344 * XXX One bug in this routine is that if the pv_entry has a single page 2345 * mapped at 0x00000000 a whole cache clean will be performed rather than 2346 * just the 1 page. Since this should not occur in everyday use and if it does 2347 * it will just result in not the most efficient clean for the page. 2348 */ 2349 #ifdef PMAP_CACHE_VIVT 2350 static int 2351 pmap_clean_page(struct pv_entry *pv, bool is_src) 2352 { 2353 pmap_t pm, pm_to_clean = NULL; 2354 struct pv_entry *npv; 2355 u_int cache_needs_cleaning = 0; 2356 u_int flags = 0; 2357 vaddr_t page_to_clean = 0; 2358 2359 if (pv == NULL) { 2360 /* nothing mapped in so nothing to flush */ 2361 return (0); 2362 } 2363 2364 /* 2365 * Since we flush the cache each time we change to a different 2366 * user vmspace, we only need to flush the page if it is in the 2367 * current pmap. 2368 */ 2369 pm = curproc->p_vmspace->vm_map.pmap; 2370 2371 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2372 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 2373 flags |= npv->pv_flags; 2374 /* 2375 * The page is mapped non-cacheable in 2376 * this map. No need to flush the cache. 2377 */ 2378 if (npv->pv_flags & PVF_NC) { 2379 #ifdef DIAGNOSTIC 2380 if (cache_needs_cleaning) 2381 panic("pmap_clean_page: " 2382 "cache inconsistency"); 2383 #endif 2384 break; 2385 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2386 continue; 2387 if (cache_needs_cleaning) { 2388 page_to_clean = 0; 2389 break; 2390 } else { 2391 page_to_clean = npv->pv_va; 2392 pm_to_clean = npv->pv_pmap; 2393 } 2394 cache_needs_cleaning = 1; 2395 } 2396 } 2397 2398 if (page_to_clean) { 2399 if (PV_BEEN_EXECD(flags)) 2400 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2401 PAGE_SIZE); 2402 else 2403 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2404 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2405 } else if (cache_needs_cleaning) { 2406 if (PV_BEEN_EXECD(flags)) 2407 pmap_idcache_wbinv_all(pm); 2408 else 2409 pmap_dcache_wbinv_all(pm); 2410 return (1); 2411 } 2412 return (0); 2413 } 2414 #endif 2415 2416 #ifdef PMAP_CACHE_VIPT 2417 /* 2418 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2419 * right cache alias to make sure we flush the right stuff. 2420 */ 2421 void 2422 pmap_syncicache_page(struct vm_page *pg) 2423 { 2424 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2425 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2426 2427 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: pg=%p (attrs=%#x)\n", 2428 pg, pg->mdpage.pvh_attrs)); 2429 /* 2430 * No need to clean the page if it's non-cached. 2431 */ 2432 if (pg->mdpage.pvh_attrs & PVF_NC) 2433 return; 2434 KASSERT(pg->mdpage.pvh_attrs & PVF_COLORED); 2435 2436 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2437 /* 2438 * Set up a PTE with the right coloring to flush existing cache lines. 2439 */ 2440 *ptep = L2_S_PROTO | 2441 VM_PAGE_TO_PHYS(pg) 2442 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2443 | pte_l2_s_cache_mode; 2444 PTE_SYNC(ptep); 2445 2446 /* 2447 * Flush it. 2448 */ 2449 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2450 /* 2451 * Unmap the page. 2452 */ 2453 *ptep = 0; 2454 PTE_SYNC(ptep); 2455 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2456 2457 pg->mdpage.pvh_attrs |= PVF_EXEC; 2458 PMAPCOUNT(exec_synced); 2459 } 2460 2461 void 2462 pmap_flush_page(struct vm_page *pg, enum pmap_flush_op flush) 2463 { 2464 vsize_t va_offset, end_va; 2465 void (*cf)(vaddr_t, vsize_t); 2466 2467 if (arm_cache_prefer_mask == 0) 2468 return; 2469 2470 switch (flush) { 2471 case PMAP_FLUSH_PRIMARY: 2472 if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 2473 va_offset = 0; 2474 end_va = arm_cache_prefer_mask; 2475 pg->mdpage.pvh_attrs &= ~PVF_MULTCLR; 2476 PMAPCOUNT(vac_flush_lots); 2477 } else { 2478 va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2479 end_va = va_offset; 2480 PMAPCOUNT(vac_flush_one); 2481 } 2482 /* 2483 * Mark that the page is no longer dirty. 2484 */ 2485 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2486 cf = cpufuncs.cf_idcache_wbinv_range; 2487 break; 2488 case PMAP_FLUSH_SECONDARY: 2489 va_offset = 0; 2490 end_va = arm_cache_prefer_mask; 2491 cf = cpufuncs.cf_idcache_wbinv_range; 2492 pg->mdpage.pvh_attrs &= ~PVF_MULTCLR; 2493 PMAPCOUNT(vac_flush_lots); 2494 break; 2495 case PMAP_CLEAN_PRIMARY: 2496 va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 2497 end_va = va_offset; 2498 cf = cpufuncs.cf_dcache_wb_range; 2499 /* 2500 * Mark that the page is no longer dirty. 2501 */ 2502 if ((pg->mdpage.pvh_attrs & PVF_DMOD) == 0) 2503 pg->mdpage.pvh_attrs &= ~PVF_DIRTY; 2504 PMAPCOUNT(vac_clean_one); 2505 break; 2506 default: 2507 return; 2508 } 2509 2510 KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC)); 2511 2512 NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n", 2513 pg, pg->mdpage.pvh_attrs)); 2514 2515 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2516 const size_t pte_offset = va_offset >> PGSHIFT; 2517 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2518 const pt_entry_t oldpte = *ptep; 2519 2520 if (flush == PMAP_FLUSH_SECONDARY 2521 && va_offset == (pg->mdpage.pvh_attrs & arm_cache_prefer_mask)) 2522 continue; 2523 2524 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2525 /* 2526 * Set up a PTE with the right coloring to flush 2527 * existing cache entries. 2528 */ 2529 *ptep = L2_S_PROTO 2530 | VM_PAGE_TO_PHYS(pg) 2531 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2532 | pte_l2_s_cache_mode; 2533 PTE_SYNC(ptep); 2534 2535 /* 2536 * Flush it. 2537 */ 2538 (*cf)(cdstp + va_offset, PAGE_SIZE); 2539 2540 /* 2541 * Restore the page table entry since we might have interrupted 2542 * pmap_zero_page or pmap_copy_page which was already using 2543 * this pte. 2544 */ 2545 *ptep = oldpte; 2546 PTE_SYNC(ptep); 2547 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2548 } 2549 } 2550 #endif /* PMAP_CACHE_VIPT */ 2551 2552 /* 2553 * Routine: pmap_page_remove 2554 * Function: 2555 * Removes this physical page from 2556 * all physical maps in which it resides. 2557 * Reflects back modify bits to the pager. 2558 */ 2559 static void 2560 pmap_page_remove(struct vm_page *pg) 2561 { 2562 struct l2_bucket *l2b; 2563 struct pv_entry *pv, *npv, **pvp; 2564 pmap_t pm, curpm; 2565 pt_entry_t *ptep, pte; 2566 bool flush; 2567 u_int flags; 2568 2569 NPDEBUG(PDB_FOLLOW, 2570 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2571 VM_PAGE_TO_PHYS(pg))); 2572 2573 PMAP_HEAD_TO_MAP_LOCK(); 2574 simple_lock(&pg->mdpage.pvh_slock); 2575 2576 pv = SLIST_FIRST(&pg->mdpage.pvh_list); 2577 if (pv == NULL) { 2578 #ifdef PMAP_CACHE_VIPT 2579 /* 2580 * We *know* the page contents are about to be replaced. 2581 * Discard the exec contents 2582 */ 2583 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2584 PMAPCOUNT(exec_discarded_page_protect); 2585 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2586 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2587 #endif 2588 simple_unlock(&pg->mdpage.pvh_slock); 2589 PMAP_HEAD_TO_MAP_UNLOCK(); 2590 return; 2591 } 2592 #ifdef PMAP_CACHE_VIPT 2593 KASSERT(pmap_is_page_colored_p(pg)); 2594 #endif 2595 2596 /* 2597 * Clear alias counts 2598 */ 2599 #ifdef PMAP_CACHE_VIVT 2600 pg->mdpage.k_mappings = 0; 2601 #endif 2602 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 2603 2604 flush = false; 2605 flags = 0; 2606 curpm = curproc->p_vmspace->vm_map.pmap; 2607 2608 #ifdef PMAP_CACHE_VIVT 2609 pmap_clean_page(pv, false); 2610 #endif 2611 2612 pvp = &SLIST_FIRST(&pg->mdpage.pvh_list); 2613 while (pv) { 2614 pm = pv->pv_pmap; 2615 npv = SLIST_NEXT(pv, pv_link); 2616 if (flush == false && (pm == curpm || pm == pmap_kernel())) 2617 flush = true; 2618 2619 if (pm == pmap_kernel()) { 2620 #ifdef PMAP_CACHE_VIPT 2621 /* 2622 * If this was unmanaged mapping, it must be preserved. 2623 * Move it back on the list and advance the end-of-list 2624 * pointer. 2625 */ 2626 if (pv->pv_flags & PVF_KENTRY) { 2627 *pvp = pv; 2628 pvp = &SLIST_NEXT(pv, pv_link); 2629 pv = npv; 2630 continue; 2631 } 2632 if (pv->pv_flags & PVF_WRITE) 2633 pg->mdpage.krw_mappings--; 2634 else 2635 pg->mdpage.kro_mappings--; 2636 #endif 2637 PMAPCOUNT(kernel_unmappings); 2638 } 2639 PMAPCOUNT(unmappings); 2640 2641 pmap_acquire_pmap_lock(pm); 2642 2643 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2644 KDASSERT(l2b != NULL); 2645 2646 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2647 pte = *ptep; 2648 2649 /* 2650 * Update statistics 2651 */ 2652 --pm->pm_stats.resident_count; 2653 2654 /* Wired bit */ 2655 if (pv->pv_flags & PVF_WIRED) 2656 --pm->pm_stats.wired_count; 2657 2658 flags |= pv->pv_flags; 2659 2660 /* 2661 * Invalidate the PTEs. 2662 */ 2663 *ptep = 0; 2664 PTE_SYNC_CURRENT(pm, ptep); 2665 pmap_free_l2_bucket(pm, l2b, 1); 2666 2667 pool_put(&pmap_pv_pool, pv); 2668 pv = npv; 2669 /* 2670 * if we reach the end of the list and there are still 2671 * mappings, they might be able to be cached now. 2672 */ 2673 if (pv == NULL) { 2674 *pvp = NULL; 2675 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 2676 pmap_vac_me_harder(pg, pm, 0); 2677 } 2678 pmap_release_pmap_lock(pm); 2679 } 2680 #ifdef PMAP_CACHE_VIPT 2681 /* 2682 * Its EXEC cache is now gone. 2683 */ 2684 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) 2685 PMAPCOUNT(exec_discarded_page_protect); 2686 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 2687 KASSERT(pg->mdpage.urw_mappings == 0); 2688 KASSERT(pg->mdpage.uro_mappings == 0); 2689 if (pg->mdpage.krw_mappings == 0) 2690 pg->mdpage.pvh_attrs &= ~PVF_WRITE; 2691 KASSERT((pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE)); 2692 #endif 2693 simple_unlock(&pg->mdpage.pvh_slock); 2694 PMAP_HEAD_TO_MAP_UNLOCK(); 2695 2696 if (flush) { 2697 /* 2698 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2699 * would need a subsequent call to pmap_update() to ensure 2700 * curpm->pm_cstate.cs_all is reset. Our callers are not 2701 * required to do that (see pmap(9)), so we can't modify 2702 * the current pmap's state. 2703 */ 2704 if (PV_BEEN_EXECD(flags)) 2705 cpu_tlb_flushID(); 2706 else 2707 cpu_tlb_flushD(); 2708 } 2709 cpu_cpwait(); 2710 } 2711 2712 /* 2713 * pmap_t pmap_create(void) 2714 * 2715 * Create a new pmap structure from scratch. 2716 */ 2717 pmap_t 2718 pmap_create(void) 2719 { 2720 pmap_t pm; 2721 2722 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2723 2724 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2725 pm->pm_stats.wired_count = 0; 2726 pm->pm_stats.resident_count = 1; 2727 pm->pm_cstate.cs_all = 0; 2728 pmap_alloc_l1(pm); 2729 2730 /* 2731 * Note: The pool cache ensures that the pm_l2[] array is already 2732 * initialised to zero. 2733 */ 2734 2735 pmap_pinit(pm); 2736 2737 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2738 2739 return (pm); 2740 } 2741 2742 /* 2743 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2744 * u_int flags) 2745 * 2746 * Insert the given physical page (p) at 2747 * the specified virtual address (v) in the 2748 * target physical map with the protection requested. 2749 * 2750 * NB: This is the only routine which MAY NOT lazy-evaluate 2751 * or lose information. That is, this routine must actually 2752 * insert this page into the given map NOW. 2753 */ 2754 int 2755 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2756 { 2757 struct l2_bucket *l2b; 2758 struct vm_page *pg, *opg; 2759 struct pv_entry *pve; 2760 pt_entry_t *ptep, npte, opte; 2761 u_int nflags; 2762 u_int oflags; 2763 2764 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2765 2766 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2767 KDASSERT(((va | pa) & PGOFSET) == 0); 2768 2769 /* 2770 * Get a pointer to the page. Later on in this function, we 2771 * test for a managed page by checking pg != NULL. 2772 */ 2773 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2774 2775 nflags = 0; 2776 if (prot & VM_PROT_WRITE) 2777 nflags |= PVF_WRITE; 2778 if (prot & VM_PROT_EXECUTE) 2779 nflags |= PVF_EXEC; 2780 if (flags & PMAP_WIRED) 2781 nflags |= PVF_WIRED; 2782 2783 PMAP_MAP_TO_HEAD_LOCK(); 2784 pmap_acquire_pmap_lock(pm); 2785 2786 /* 2787 * Fetch the L2 bucket which maps this page, allocating one if 2788 * necessary for user pmaps. 2789 */ 2790 if (pm == pmap_kernel()) 2791 l2b = pmap_get_l2_bucket(pm, va); 2792 else 2793 l2b = pmap_alloc_l2_bucket(pm, va); 2794 if (l2b == NULL) { 2795 if (flags & PMAP_CANFAIL) { 2796 pmap_release_pmap_lock(pm); 2797 PMAP_MAP_TO_HEAD_UNLOCK(); 2798 return (ENOMEM); 2799 } 2800 panic("pmap_enter: failed to allocate L2 bucket"); 2801 } 2802 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2803 opte = *ptep; 2804 npte = pa; 2805 oflags = 0; 2806 2807 if (opte) { 2808 /* 2809 * There is already a mapping at this address. 2810 * If the physical address is different, lookup the 2811 * vm_page. 2812 */ 2813 if (l2pte_pa(opte) != pa) 2814 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2815 else 2816 opg = pg; 2817 } else 2818 opg = NULL; 2819 2820 if (pg) { 2821 /* 2822 * This is to be a managed mapping. 2823 */ 2824 if ((flags & VM_PROT_ALL) || 2825 (pg->mdpage.pvh_attrs & PVF_REF)) { 2826 /* 2827 * - The access type indicates that we don't need 2828 * to do referenced emulation. 2829 * OR 2830 * - The physical page has already been referenced 2831 * so no need to re-do referenced emulation here. 2832 */ 2833 npte |= L2_S_PROTO; 2834 2835 nflags |= PVF_REF; 2836 2837 if ((prot & VM_PROT_WRITE) != 0 && 2838 ((flags & VM_PROT_WRITE) != 0 || 2839 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2840 /* 2841 * This is a writable mapping, and the 2842 * page's mod state indicates it has 2843 * already been modified. Make it 2844 * writable from the outset. 2845 */ 2846 npte |= L2_S_PROT_W; 2847 nflags |= PVF_MOD; 2848 } 2849 } else { 2850 /* 2851 * Need to do page referenced emulation. 2852 */ 2853 npte |= L2_TYPE_INV; 2854 } 2855 2856 npte |= pte_l2_s_cache_mode; 2857 2858 if (pg == opg) { 2859 /* 2860 * We're changing the attrs of an existing mapping. 2861 */ 2862 simple_lock(&pg->mdpage.pvh_slock); 2863 oflags = pmap_modify_pv(pg, pm, va, 2864 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2865 PVF_MOD | PVF_REF, nflags); 2866 simple_unlock(&pg->mdpage.pvh_slock); 2867 2868 #ifdef PMAP_CACHE_VIVT 2869 /* 2870 * We may need to flush the cache if we're 2871 * doing rw-ro... 2872 */ 2873 if (pm->pm_cstate.cs_cache_d && 2874 (oflags & PVF_NC) == 0 && 2875 (opte & L2_S_PROT_W) != 0 && 2876 (prot & VM_PROT_WRITE) == 0) 2877 cpu_dcache_wb_range(va, PAGE_SIZE); 2878 #endif 2879 } else { 2880 /* 2881 * New mapping, or changing the backing page 2882 * of an existing mapping. 2883 */ 2884 if (opg) { 2885 /* 2886 * Replacing an existing mapping with a new one. 2887 * It is part of our managed memory so we 2888 * must remove it from the PV list 2889 */ 2890 simple_lock(&opg->mdpage.pvh_slock); 2891 pve = pmap_remove_pv(opg, pm, va); 2892 pmap_vac_me_harder(opg, pm, 0); 2893 simple_unlock(&opg->mdpage.pvh_slock); 2894 oflags = pve->pv_flags; 2895 2896 #ifdef PMAP_CACHE_VIVT 2897 /* 2898 * If the old mapping was valid (ref/mod 2899 * emulation creates 'invalid' mappings 2900 * initially) then make sure to frob 2901 * the cache. 2902 */ 2903 if ((oflags & PVF_NC) == 0 && 2904 l2pte_valid(opte)) { 2905 if (PV_BEEN_EXECD(oflags)) { 2906 pmap_idcache_wbinv_range(pm, va, 2907 PAGE_SIZE); 2908 } else 2909 if (PV_BEEN_REFD(oflags)) { 2910 pmap_dcache_wb_range(pm, va, 2911 PAGE_SIZE, true, 2912 (oflags & PVF_WRITE) == 0); 2913 } 2914 } 2915 #endif 2916 } else 2917 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2918 if ((flags & PMAP_CANFAIL) == 0) 2919 panic("pmap_enter: no pv entries"); 2920 2921 if (pm != pmap_kernel()) 2922 pmap_free_l2_bucket(pm, l2b, 0); 2923 pmap_release_pmap_lock(pm); 2924 PMAP_MAP_TO_HEAD_UNLOCK(); 2925 NPDEBUG(PDB_ENTER, 2926 printf("pmap_enter: ENOMEM\n")); 2927 return (ENOMEM); 2928 } 2929 2930 pmap_enter_pv(pg, pve, pm, va, nflags); 2931 } 2932 } else { 2933 /* 2934 * We're mapping an unmanaged page. 2935 * These are always readable, and possibly writable, from 2936 * the get go as we don't need to track ref/mod status. 2937 */ 2938 npte |= L2_S_PROTO; 2939 if (prot & VM_PROT_WRITE) 2940 npte |= L2_S_PROT_W; 2941 2942 /* 2943 * Make sure the vector table is mapped cacheable 2944 */ 2945 if (pm != pmap_kernel() && va == vector_page) 2946 npte |= pte_l2_s_cache_mode; 2947 2948 if (opg) { 2949 /* 2950 * Looks like there's an existing 'managed' mapping 2951 * at this address. 2952 */ 2953 simple_lock(&opg->mdpage.pvh_slock); 2954 pve = pmap_remove_pv(opg, pm, va); 2955 pmap_vac_me_harder(opg, pm, 0); 2956 simple_unlock(&opg->mdpage.pvh_slock); 2957 oflags = pve->pv_flags; 2958 2959 #ifdef PMAP_CACHE_VIVT 2960 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2961 if (PV_BEEN_EXECD(oflags)) 2962 pmap_idcache_wbinv_range(pm, va, 2963 PAGE_SIZE); 2964 else 2965 if (PV_BEEN_REFD(oflags)) 2966 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2967 true, (oflags & PVF_WRITE) == 0); 2968 } 2969 #endif 2970 pool_put(&pmap_pv_pool, pve); 2971 } 2972 } 2973 2974 /* 2975 * Make sure userland mappings get the right permissions 2976 */ 2977 if (pm != pmap_kernel() && va != vector_page) 2978 npte |= L2_S_PROT_U; 2979 2980 /* 2981 * Keep the stats up to date 2982 */ 2983 if (opte == 0) { 2984 l2b->l2b_occupancy++; 2985 pm->pm_stats.resident_count++; 2986 } 2987 2988 NPDEBUG(PDB_ENTER, 2989 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2990 2991 /* 2992 * If this is just a wiring change, the two PTEs will be 2993 * identical, so there's no need to update the page table. 2994 */ 2995 if (npte != opte) { 2996 bool is_cached = pmap_is_cached(pm); 2997 2998 *ptep = npte; 2999 if (is_cached) { 3000 /* 3001 * We only need to frob the cache/tlb if this pmap 3002 * is current 3003 */ 3004 PTE_SYNC(ptep); 3005 if (va != vector_page && l2pte_valid(npte)) { 3006 /* 3007 * This mapping is likely to be accessed as 3008 * soon as we return to userland. Fix up the 3009 * L1 entry to avoid taking another 3010 * page/domain fault. 3011 */ 3012 pd_entry_t *pl1pd, l1pd; 3013 3014 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3015 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3016 L1_C_PROTO; 3017 if (*pl1pd != l1pd) { 3018 *pl1pd = l1pd; 3019 PTE_SYNC(pl1pd); 3020 } 3021 } 3022 } 3023 3024 if (PV_BEEN_EXECD(oflags)) 3025 pmap_tlb_flushID_SE(pm, va); 3026 else 3027 if (PV_BEEN_REFD(oflags)) 3028 pmap_tlb_flushD_SE(pm, va); 3029 3030 NPDEBUG(PDB_ENTER, 3031 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3032 is_cached, pm->pm_cstate.cs_all)); 3033 3034 if (pg != NULL) { 3035 simple_lock(&pg->mdpage.pvh_slock); 3036 pmap_vac_me_harder(pg, pm, va); 3037 simple_unlock(&pg->mdpage.pvh_slock); 3038 } 3039 } 3040 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3041 if (pg) { 3042 simple_lock(&pg->mdpage.pvh_slock); 3043 KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3044 KASSERT(((pg->mdpage.pvh_attrs & PVF_WRITE) == 0) == (pg->mdpage.urw_mappings + pg->mdpage.krw_mappings == 0)); 3045 simple_unlock(&pg->mdpage.pvh_slock); 3046 } 3047 #endif 3048 3049 pmap_release_pmap_lock(pm); 3050 PMAP_MAP_TO_HEAD_UNLOCK(); 3051 3052 return (0); 3053 } 3054 3055 /* 3056 * pmap_remove() 3057 * 3058 * pmap_remove is responsible for nuking a number of mappings for a range 3059 * of virtual address space in the current pmap. To do this efficiently 3060 * is interesting, because in a number of cases a wide virtual address 3061 * range may be supplied that contains few actual mappings. So, the 3062 * optimisations are: 3063 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3064 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3065 * maybe do just a partial cache clean. This path of execution is 3066 * complicated by the fact that the cache must be flushed _before_ 3067 * the PTE is nuked, being a VAC :-) 3068 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3069 * all invalidations until pmap_update(), since pmap_remove_all() has 3070 * already flushed the cache. 3071 * 4. Maybe later fast-case a single page, but I don't think this is 3072 * going to make _that_ much difference overall. 3073 */ 3074 3075 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3076 3077 void 3078 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3079 { 3080 struct l2_bucket *l2b; 3081 vaddr_t next_bucket; 3082 pt_entry_t *ptep; 3083 u_int cleanlist_idx, total, cnt; 3084 struct { 3085 vaddr_t va; 3086 pt_entry_t *ptep; 3087 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3088 u_int mappings, is_exec, is_refd; 3089 3090 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3091 "eva=%08lx\n", pm, sva, eva)); 3092 3093 /* 3094 * we lock in the pmap => pv_head direction 3095 */ 3096 PMAP_MAP_TO_HEAD_LOCK(); 3097 pmap_acquire_pmap_lock(pm); 3098 3099 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3100 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3101 if (pm->pm_cstate.cs_tlb == 0) 3102 pm->pm_remove_all = true; 3103 } else 3104 cleanlist_idx = 0; 3105 3106 total = 0; 3107 3108 while (sva < eva) { 3109 /* 3110 * Do one L2 bucket's worth at a time. 3111 */ 3112 next_bucket = L2_NEXT_BUCKET(sva); 3113 if (next_bucket > eva) 3114 next_bucket = eva; 3115 3116 l2b = pmap_get_l2_bucket(pm, sva); 3117 if (l2b == NULL) { 3118 sva = next_bucket; 3119 continue; 3120 } 3121 3122 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3123 3124 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3125 struct vm_page *pg; 3126 pt_entry_t pte; 3127 paddr_t pa; 3128 3129 pte = *ptep; 3130 3131 if (pte == 0) { 3132 /* Nothing here, move along */ 3133 continue; 3134 } 3135 3136 pa = l2pte_pa(pte); 3137 is_exec = 0; 3138 is_refd = 1; 3139 3140 /* 3141 * Update flags. In a number of circumstances, 3142 * we could cluster a lot of these and do a 3143 * number of sequential pages in one go. 3144 */ 3145 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3146 struct pv_entry *pve; 3147 simple_lock(&pg->mdpage.pvh_slock); 3148 pve = pmap_remove_pv(pg, pm, sva); 3149 pmap_vac_me_harder(pg, pm, 0); 3150 simple_unlock(&pg->mdpage.pvh_slock); 3151 if (pve != NULL) { 3152 if (pm->pm_remove_all == false) { 3153 is_exec = 3154 PV_BEEN_EXECD(pve->pv_flags); 3155 is_refd = 3156 PV_BEEN_REFD(pve->pv_flags); 3157 } 3158 pool_put(&pmap_pv_pool, pve); 3159 } 3160 } 3161 mappings++; 3162 3163 if (!l2pte_valid(pte)) { 3164 /* 3165 * Ref/Mod emulation is still active for this 3166 * mapping, therefore it is has not yet been 3167 * accessed. No need to frob the cache/tlb. 3168 */ 3169 *ptep = 0; 3170 PTE_SYNC_CURRENT(pm, ptep); 3171 continue; 3172 } 3173 3174 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3175 /* Add to the clean list. */ 3176 cleanlist[cleanlist_idx].ptep = ptep; 3177 cleanlist[cleanlist_idx].va = 3178 sva | (is_exec & 1); 3179 cleanlist_idx++; 3180 } else 3181 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3182 /* Nuke everything if needed. */ 3183 #ifdef PMAP_CACHE_VIVT 3184 pmap_idcache_wbinv_all(pm); 3185 #endif 3186 pmap_tlb_flushID(pm); 3187 3188 /* 3189 * Roll back the previous PTE list, 3190 * and zero out the current PTE. 3191 */ 3192 for (cnt = 0; 3193 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3194 *cleanlist[cnt].ptep = 0; 3195 PTE_SYNC(cleanlist[cnt].ptep); 3196 } 3197 *ptep = 0; 3198 PTE_SYNC(ptep); 3199 cleanlist_idx++; 3200 pm->pm_remove_all = true; 3201 } else { 3202 *ptep = 0; 3203 PTE_SYNC(ptep); 3204 if (pm->pm_remove_all == false) { 3205 if (is_exec) 3206 pmap_tlb_flushID_SE(pm, sva); 3207 else 3208 if (is_refd) 3209 pmap_tlb_flushD_SE(pm, sva); 3210 } 3211 } 3212 } 3213 3214 /* 3215 * Deal with any left overs 3216 */ 3217 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3218 total += cleanlist_idx; 3219 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3220 if (pm->pm_cstate.cs_all != 0) { 3221 vaddr_t clva = cleanlist[cnt].va & ~1; 3222 if (cleanlist[cnt].va & 1) { 3223 #ifdef PMAP_CACHE_VIVT 3224 pmap_idcache_wbinv_range(pm, 3225 clva, PAGE_SIZE); 3226 #endif 3227 pmap_tlb_flushID_SE(pm, clva); 3228 } else { 3229 #ifdef PMAP_CACHE_VIVT 3230 pmap_dcache_wb_range(pm, 3231 clva, PAGE_SIZE, true, 3232 false); 3233 #endif 3234 pmap_tlb_flushD_SE(pm, clva); 3235 } 3236 } 3237 *cleanlist[cnt].ptep = 0; 3238 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3239 } 3240 3241 /* 3242 * If it looks like we're removing a whole bunch 3243 * of mappings, it's faster to just write-back 3244 * the whole cache now and defer TLB flushes until 3245 * pmap_update() is called. 3246 */ 3247 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3248 cleanlist_idx = 0; 3249 else { 3250 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3251 #ifdef PMAP_CACHE_VIVT 3252 pmap_idcache_wbinv_all(pm); 3253 #endif 3254 pm->pm_remove_all = true; 3255 } 3256 } 3257 3258 pmap_free_l2_bucket(pm, l2b, mappings); 3259 pm->pm_stats.resident_count -= mappings; 3260 } 3261 3262 pmap_release_pmap_lock(pm); 3263 PMAP_MAP_TO_HEAD_UNLOCK(); 3264 } 3265 3266 #ifdef PMAP_CACHE_VIPT 3267 static struct pv_entry * 3268 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3269 { 3270 struct pv_entry *pv; 3271 3272 simple_lock(&pg->mdpage.pvh_slock); 3273 KASSERT(pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 3274 KASSERT((pg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3275 3276 pv = pmap_remove_pv(pg, pmap_kernel(), va); 3277 KASSERT(pv); 3278 KASSERT(pv->pv_flags & PVF_KENTRY); 3279 3280 /* 3281 * If we are removing a writeable mapping to a cached exec page, 3282 * if it's the last mapping then clear it execness other sync 3283 * the page to the icache. 3284 */ 3285 if ((pg->mdpage.pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3286 && (pv->pv_flags & PVF_WRITE) != 0) { 3287 if (SLIST_EMPTY(&pg->mdpage.pvh_list)) { 3288 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 3289 PMAPCOUNT(exec_discarded_kremove); 3290 } else { 3291 pmap_syncicache_page(pg); 3292 PMAPCOUNT(exec_synced_kremove); 3293 } 3294 } 3295 pmap_vac_me_harder(pg, pmap_kernel(), 0); 3296 simple_unlock(&pg->mdpage.pvh_slock); 3297 3298 return pv; 3299 } 3300 #endif /* PMAP_CACHE_VIPT */ 3301 3302 /* 3303 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3304 * 3305 * We assume there is already sufficient KVM space available 3306 * to do this, as we can't allocate L2 descriptor tables/metadata 3307 * from here. 3308 */ 3309 void 3310 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3311 { 3312 struct l2_bucket *l2b; 3313 pt_entry_t *ptep, opte; 3314 #ifdef PMAP_CACHE_VIVT 3315 struct vm_page *pg = (prot & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3316 #endif 3317 #ifdef PMAP_CACHE_VIPT 3318 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3319 struct vm_page *opg; 3320 struct pv_entry *pv = NULL; 3321 #endif 3322 3323 NPDEBUG(PDB_KENTER, 3324 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3325 va, pa, prot)); 3326 3327 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3328 KDASSERT(l2b != NULL); 3329 3330 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3331 opte = *ptep; 3332 3333 if (opte == 0) { 3334 PMAPCOUNT(kenter_mappings); 3335 l2b->l2b_occupancy++; 3336 } else { 3337 PMAPCOUNT(kenter_remappings); 3338 #ifdef PMAP_CACHE_VIPT 3339 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3340 if (opg) { 3341 KASSERT(opg != pg); 3342 KASSERT((opg->mdpage.pvh_attrs & PVF_KMPAGE) == 0); 3343 KASSERT((prot & PMAP_KMPAGE) == 0); 3344 simple_lock(&opg->mdpage.pvh_slock); 3345 pv = pmap_kremove_pg(opg, va); 3346 simple_unlock(&opg->mdpage.pvh_slock); 3347 } 3348 #endif 3349 if (l2pte_valid(opte)) { 3350 #ifdef PMAP_CACHE_VIVT 3351 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3352 #endif 3353 cpu_tlb_flushD_SE(va); 3354 cpu_cpwait(); 3355 } 3356 } 3357 3358 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3359 pte_l2_s_cache_mode; 3360 PTE_SYNC(ptep); 3361 3362 if (pg) { 3363 if (prot & PMAP_KMPAGE) { 3364 simple_lock(&pg->mdpage.pvh_slock); 3365 KASSERT(pg->mdpage.urw_mappings == 0); 3366 KASSERT(pg->mdpage.uro_mappings == 0); 3367 KASSERT(pg->mdpage.krw_mappings == 0); 3368 KASSERT(pg->mdpage.kro_mappings == 0); 3369 #ifdef PMAP_CACHE_VIPT 3370 KASSERT(pv == NULL); 3371 KASSERT((va & PVF_COLORED) == 0); 3372 KASSERT((pg->mdpage.pvh_attrs & PVF_NC) == 0); 3373 /* if there is a color conflict, evict from cache. */ 3374 if (pmap_is_page_colored_p(pg) 3375 && ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask)) { 3376 PMAPCOUNT(vac_color_change); 3377 pmap_flush_page(pg, PMAP_FLUSH_PRIMARY); 3378 } else if (pg->mdpage.pvh_attrs & PVF_MULTCLR) { 3379 /* 3380 * If this page has multiple colors, expunge 3381 * them. 3382 */ 3383 PMAPCOUNT(vac_flush_lots2); 3384 pmap_flush_page(pg, PMAP_FLUSH_SECONDARY); 3385 } 3386 pg->mdpage.pvh_attrs &= PAGE_SIZE - 1; 3387 pg->mdpage.pvh_attrs |= PVF_KMPAGE 3388 | PVF_COLORED | PVF_DIRTY 3389 | (va & arm_cache_prefer_mask); 3390 #endif 3391 #ifdef PMAP_CACHE_VIVT 3392 pg->mdpage.pvh_attrs |= PVF_KMPAGE; 3393 #endif 3394 pmap_kmpages++; 3395 simple_unlock(&pg->mdpage.pvh_slock); 3396 #ifdef PMAP_CACHE_VIPT 3397 } else { 3398 if (pv == NULL) { 3399 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3400 KASSERT(pv != NULL); 3401 } 3402 pmap_enter_pv(pg, pv, pmap_kernel(), va, 3403 PVF_WIRED | PVF_KENTRY 3404 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3405 if ((prot & VM_PROT_WRITE) 3406 && !(pg->mdpage.pvh_attrs & PVF_NC)) 3407 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3408 KASSERT((prot & VM_PROT_WRITE) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC))); 3409 simple_lock(&pg->mdpage.pvh_slock); 3410 pmap_vac_me_harder(pg, pmap_kernel(), va); 3411 simple_unlock(&pg->mdpage.pvh_slock); 3412 #endif 3413 } 3414 #ifdef PMAP_CACHE_VIPT 3415 } else { 3416 if (pv != NULL) 3417 pool_put(&pmap_pv_pool, pv); 3418 #endif 3419 } 3420 } 3421 3422 void 3423 pmap_kremove(vaddr_t va, vsize_t len) 3424 { 3425 struct l2_bucket *l2b; 3426 pt_entry_t *ptep, *sptep, opte; 3427 vaddr_t next_bucket, eva; 3428 u_int mappings; 3429 struct vm_page *opg; 3430 3431 PMAPCOUNT(kenter_unmappings); 3432 3433 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3434 va, len)); 3435 3436 eva = va + len; 3437 3438 while (va < eva) { 3439 next_bucket = L2_NEXT_BUCKET(va); 3440 if (next_bucket > eva) 3441 next_bucket = eva; 3442 3443 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3444 KDASSERT(l2b != NULL); 3445 3446 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3447 mappings = 0; 3448 3449 while (va < next_bucket) { 3450 opte = *ptep; 3451 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3452 if (opg) { 3453 if (opg->mdpage.pvh_attrs & PVF_KMPAGE) { 3454 simple_lock(&opg->mdpage.pvh_slock); 3455 KASSERT(opg->mdpage.urw_mappings == 0); 3456 KASSERT(opg->mdpage.uro_mappings == 0); 3457 KASSERT(opg->mdpage.krw_mappings == 0); 3458 KASSERT(opg->mdpage.kro_mappings == 0); 3459 opg->mdpage.pvh_attrs &= ~PVF_KMPAGE; 3460 #ifdef PMAP_CACHE_VIPT 3461 opg->mdpage.pvh_attrs &= ~PVF_WRITE; 3462 #endif 3463 pmap_kmpages--; 3464 simple_unlock(&opg->mdpage.pvh_slock); 3465 #ifdef PMAP_CACHE_VIPT 3466 } else { 3467 pool_put(&pmap_pv_pool, 3468 pmap_kremove_pg(opg, va)); 3469 #endif 3470 } 3471 } 3472 if (l2pte_valid(opte)) { 3473 #ifdef PMAP_CACHE_VIVT 3474 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3475 #endif 3476 cpu_tlb_flushD_SE(va); 3477 } 3478 if (opte) { 3479 *ptep = 0; 3480 mappings++; 3481 } 3482 va += PAGE_SIZE; 3483 ptep++; 3484 } 3485 KDASSERT(mappings <= l2b->l2b_occupancy); 3486 l2b->l2b_occupancy -= mappings; 3487 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3488 } 3489 cpu_cpwait(); 3490 } 3491 3492 bool 3493 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3494 { 3495 struct l2_dtable *l2; 3496 pd_entry_t *pl1pd, l1pd; 3497 pt_entry_t *ptep, pte; 3498 paddr_t pa; 3499 u_int l1idx; 3500 3501 pmap_acquire_pmap_lock(pm); 3502 3503 l1idx = L1_IDX(va); 3504 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3505 l1pd = *pl1pd; 3506 3507 if (l1pte_section_p(l1pd)) { 3508 /* 3509 * These should only happen for pmap_kernel() 3510 */ 3511 KDASSERT(pm == pmap_kernel()); 3512 pmap_release_pmap_lock(pm); 3513 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3514 } else { 3515 /* 3516 * Note that we can't rely on the validity of the L1 3517 * descriptor as an indication that a mapping exists. 3518 * We have to look it up in the L2 dtable. 3519 */ 3520 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3521 3522 if (l2 == NULL || 3523 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3524 pmap_release_pmap_lock(pm); 3525 return false; 3526 } 3527 3528 ptep = &ptep[l2pte_index(va)]; 3529 pte = *ptep; 3530 pmap_release_pmap_lock(pm); 3531 3532 if (pte == 0) 3533 return false; 3534 3535 switch (pte & L2_TYPE_MASK) { 3536 case L2_TYPE_L: 3537 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3538 break; 3539 3540 default: 3541 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3542 break; 3543 } 3544 } 3545 3546 if (pap != NULL) 3547 *pap = pa; 3548 3549 return true; 3550 } 3551 3552 void 3553 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3554 { 3555 struct l2_bucket *l2b; 3556 pt_entry_t *ptep, pte; 3557 vaddr_t next_bucket; 3558 u_int flags; 3559 u_int clr_mask; 3560 int flush; 3561 3562 NPDEBUG(PDB_PROTECT, 3563 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3564 pm, sva, eva, prot)); 3565 3566 if ((prot & VM_PROT_READ) == 0) { 3567 pmap_remove(pm, sva, eva); 3568 return; 3569 } 3570 3571 if (prot & VM_PROT_WRITE) { 3572 /* 3573 * If this is a read->write transition, just ignore it and let 3574 * uvm_fault() take care of it later. 3575 */ 3576 return; 3577 } 3578 3579 PMAP_MAP_TO_HEAD_LOCK(); 3580 pmap_acquire_pmap_lock(pm); 3581 3582 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3583 flags = 0; 3584 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3585 3586 while (sva < eva) { 3587 next_bucket = L2_NEXT_BUCKET(sva); 3588 if (next_bucket > eva) 3589 next_bucket = eva; 3590 3591 l2b = pmap_get_l2_bucket(pm, sva); 3592 if (l2b == NULL) { 3593 sva = next_bucket; 3594 continue; 3595 } 3596 3597 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3598 3599 while (sva < next_bucket) { 3600 pte = *ptep; 3601 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3602 struct vm_page *pg; 3603 u_int f; 3604 3605 #ifdef PMAP_CACHE_VIVT 3606 /* 3607 * OK, at this point, we know we're doing 3608 * write-protect operation. If the pmap is 3609 * active, write-back the page. 3610 */ 3611 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3612 false, false); 3613 #endif 3614 3615 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3616 pte &= ~L2_S_PROT_W; 3617 *ptep = pte; 3618 PTE_SYNC(ptep); 3619 3620 if (pg != NULL) { 3621 simple_lock(&pg->mdpage.pvh_slock); 3622 f = pmap_modify_pv(pg, pm, sva, 3623 clr_mask, 0); 3624 pmap_vac_me_harder(pg, pm, sva); 3625 simple_unlock(&pg->mdpage.pvh_slock); 3626 } else 3627 f = PVF_REF | PVF_EXEC; 3628 3629 if (flush >= 0) { 3630 flush++; 3631 flags |= f; 3632 } else 3633 if (PV_BEEN_EXECD(f)) 3634 pmap_tlb_flushID_SE(pm, sva); 3635 else 3636 if (PV_BEEN_REFD(f)) 3637 pmap_tlb_flushD_SE(pm, sva); 3638 } 3639 3640 sva += PAGE_SIZE; 3641 ptep++; 3642 } 3643 } 3644 3645 pmap_release_pmap_lock(pm); 3646 PMAP_MAP_TO_HEAD_UNLOCK(); 3647 3648 if (flush) { 3649 if (PV_BEEN_EXECD(flags)) 3650 pmap_tlb_flushID(pm); 3651 else 3652 if (PV_BEEN_REFD(flags)) 3653 pmap_tlb_flushD(pm); 3654 } 3655 } 3656 3657 void 3658 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3659 { 3660 struct l2_bucket *l2b; 3661 pt_entry_t *ptep; 3662 vaddr_t next_bucket; 3663 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3664 3665 NPDEBUG(PDB_EXEC, 3666 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3667 pm, sva, eva)); 3668 3669 PMAP_MAP_TO_HEAD_LOCK(); 3670 pmap_acquire_pmap_lock(pm); 3671 3672 while (sva < eva) { 3673 next_bucket = L2_NEXT_BUCKET(sva); 3674 if (next_bucket > eva) 3675 next_bucket = eva; 3676 3677 l2b = pmap_get_l2_bucket(pm, sva); 3678 if (l2b == NULL) { 3679 sva = next_bucket; 3680 continue; 3681 } 3682 3683 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3684 sva < next_bucket; 3685 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3686 if (l2pte_valid(*ptep)) { 3687 cpu_icache_sync_range(sva, 3688 min(page_size, eva - sva)); 3689 } 3690 } 3691 } 3692 3693 pmap_release_pmap_lock(pm); 3694 PMAP_MAP_TO_HEAD_UNLOCK(); 3695 } 3696 3697 void 3698 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3699 { 3700 3701 NPDEBUG(PDB_PROTECT, 3702 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3703 pg, VM_PAGE_TO_PHYS(pg), prot)); 3704 3705 switch(prot) { 3706 case VM_PROT_READ|VM_PROT_WRITE: 3707 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3708 pmap_clearbit(pg, PVF_EXEC); 3709 break; 3710 #endif 3711 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3712 break; 3713 3714 case VM_PROT_READ: 3715 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3716 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3717 break; 3718 #endif 3719 case VM_PROT_READ|VM_PROT_EXECUTE: 3720 pmap_clearbit(pg, PVF_WRITE); 3721 break; 3722 3723 default: 3724 pmap_page_remove(pg); 3725 break; 3726 } 3727 } 3728 3729 /* 3730 * pmap_clear_modify: 3731 * 3732 * Clear the "modified" attribute for a page. 3733 */ 3734 bool 3735 pmap_clear_modify(struct vm_page *pg) 3736 { 3737 bool rv; 3738 3739 if (pg->mdpage.pvh_attrs & PVF_MOD) { 3740 rv = true; 3741 #ifdef PMAP_CACHE_VIPT 3742 /* 3743 * If we are going to clear the modified bit and there are 3744 * no other modified bits set, flush the page to memory and 3745 * mark it clean. 3746 */ 3747 if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3748 pmap_flush_page(pg, PMAP_CLEAN_PRIMARY); 3749 #endif 3750 pmap_clearbit(pg, PVF_MOD); 3751 } else 3752 rv = false; 3753 3754 return (rv); 3755 } 3756 3757 /* 3758 * pmap_clear_reference: 3759 * 3760 * Clear the "referenced" attribute for a page. 3761 */ 3762 bool 3763 pmap_clear_reference(struct vm_page *pg) 3764 { 3765 bool rv; 3766 3767 if (pg->mdpage.pvh_attrs & PVF_REF) { 3768 rv = true; 3769 pmap_clearbit(pg, PVF_REF); 3770 } else 3771 rv = false; 3772 3773 return (rv); 3774 } 3775 3776 /* 3777 * pmap_is_modified: 3778 * 3779 * Test if a page has the "modified" attribute. 3780 */ 3781 /* See <arm/arm32/pmap.h> */ 3782 3783 /* 3784 * pmap_is_referenced: 3785 * 3786 * Test if a page has the "referenced" attribute. 3787 */ 3788 /* See <arm/arm32/pmap.h> */ 3789 3790 int 3791 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3792 { 3793 struct l2_dtable *l2; 3794 struct l2_bucket *l2b; 3795 pd_entry_t *pl1pd, l1pd; 3796 pt_entry_t *ptep, pte; 3797 paddr_t pa; 3798 u_int l1idx; 3799 int rv = 0; 3800 3801 PMAP_MAP_TO_HEAD_LOCK(); 3802 pmap_acquire_pmap_lock(pm); 3803 3804 l1idx = L1_IDX(va); 3805 3806 /* 3807 * If there is no l2_dtable for this address, then the process 3808 * has no business accessing it. 3809 * 3810 * Note: This will catch userland processes trying to access 3811 * kernel addresses. 3812 */ 3813 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3814 if (l2 == NULL) 3815 goto out; 3816 3817 /* 3818 * Likewise if there is no L2 descriptor table 3819 */ 3820 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3821 if (l2b->l2b_kva == NULL) 3822 goto out; 3823 3824 /* 3825 * Check the PTE itself. 3826 */ 3827 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3828 pte = *ptep; 3829 if (pte == 0) 3830 goto out; 3831 3832 /* 3833 * Catch a userland access to the vector page mapped at 0x0 3834 */ 3835 if (user && (pte & L2_S_PROT_U) == 0) 3836 goto out; 3837 3838 pa = l2pte_pa(pte); 3839 3840 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3841 /* 3842 * This looks like a good candidate for "page modified" 3843 * emulation... 3844 */ 3845 struct pv_entry *pv; 3846 struct vm_page *pg; 3847 3848 /* Extract the physical address of the page */ 3849 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3850 goto out; 3851 3852 /* Get the current flags for this page. */ 3853 simple_lock(&pg->mdpage.pvh_slock); 3854 3855 pv = pmap_find_pv(pg, pm, va); 3856 if (pv == NULL) { 3857 simple_unlock(&pg->mdpage.pvh_slock); 3858 goto out; 3859 } 3860 3861 /* 3862 * Do the flags say this page is writable? If not then it 3863 * is a genuine write fault. If yes then the write fault is 3864 * our fault as we did not reflect the write access in the 3865 * PTE. Now we know a write has occurred we can correct this 3866 * and also set the modified bit 3867 */ 3868 if ((pv->pv_flags & PVF_WRITE) == 0) { 3869 simple_unlock(&pg->mdpage.pvh_slock); 3870 goto out; 3871 } 3872 3873 NPDEBUG(PDB_FOLLOW, 3874 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3875 pm, va, VM_PAGE_TO_PHYS(pg))); 3876 3877 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 3878 pv->pv_flags |= PVF_REF | PVF_MOD; 3879 #ifdef PMAP_CACHE_VIPT 3880 /* 3881 * If there are cacheable mappings for this page, mark it dirty. 3882 */ 3883 if ((pg->mdpage.pvh_attrs & PVF_NC) == 0) 3884 pg->mdpage.pvh_attrs |= PVF_DIRTY; 3885 #endif 3886 simple_unlock(&pg->mdpage.pvh_slock); 3887 3888 /* 3889 * Re-enable write permissions for the page. No need to call 3890 * pmap_vac_me_harder(), since this is just a 3891 * modified-emulation fault, and the PVF_WRITE bit isn't 3892 * changing. We've already set the cacheable bits based on 3893 * the assumption that we can write to this page. 3894 */ 3895 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3896 PTE_SYNC(ptep); 3897 rv = 1; 3898 } else 3899 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3900 /* 3901 * This looks like a good candidate for "page referenced" 3902 * emulation. 3903 */ 3904 struct pv_entry *pv; 3905 struct vm_page *pg; 3906 3907 /* Extract the physical address of the page */ 3908 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3909 goto out; 3910 3911 /* Get the current flags for this page. */ 3912 simple_lock(&pg->mdpage.pvh_slock); 3913 3914 pv = pmap_find_pv(pg, pm, va); 3915 if (pv == NULL) { 3916 simple_unlock(&pg->mdpage.pvh_slock); 3917 goto out; 3918 } 3919 3920 pg->mdpage.pvh_attrs |= PVF_REF; 3921 pv->pv_flags |= PVF_REF; 3922 simple_unlock(&pg->mdpage.pvh_slock); 3923 3924 NPDEBUG(PDB_FOLLOW, 3925 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3926 pm, va, VM_PAGE_TO_PHYS(pg))); 3927 3928 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3929 PTE_SYNC(ptep); 3930 rv = 1; 3931 } 3932 3933 /* 3934 * We know there is a valid mapping here, so simply 3935 * fix up the L1 if necessary. 3936 */ 3937 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3938 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3939 if (*pl1pd != l1pd) { 3940 *pl1pd = l1pd; 3941 PTE_SYNC(pl1pd); 3942 rv = 1; 3943 } 3944 3945 #ifdef CPU_SA110 3946 /* 3947 * There are bugs in the rev K SA110. This is a check for one 3948 * of them. 3949 */ 3950 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3951 curcpu()->ci_arm_cpurev < 3) { 3952 /* Always current pmap */ 3953 if (l2pte_valid(pte)) { 3954 extern int kernel_debug; 3955 if (kernel_debug & 1) { 3956 struct proc *p = curlwp->l_proc; 3957 printf("prefetch_abort: page is already " 3958 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3959 printf("prefetch_abort: pc=%08lx proc=%p " 3960 "process=%s\n", va, p, p->p_comm); 3961 printf("prefetch_abort: far=%08x fs=%x\n", 3962 cpu_faultaddress(), cpu_faultstatus()); 3963 } 3964 #ifdef DDB 3965 if (kernel_debug & 2) 3966 Debugger(); 3967 #endif 3968 rv = 1; 3969 } 3970 } 3971 #endif /* CPU_SA110 */ 3972 3973 #ifdef DEBUG 3974 /* 3975 * If 'rv == 0' at this point, it generally indicates that there is a 3976 * stale TLB entry for the faulting address. This happens when two or 3977 * more processes are sharing an L1. Since we don't flush the TLB on 3978 * a context switch between such processes, we can take domain faults 3979 * for mappings which exist at the same VA in both processes. EVEN IF 3980 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 3981 * example. 3982 * 3983 * This is extremely likely to happen if pmap_enter() updated the L1 3984 * entry for a recently entered mapping. In this case, the TLB is 3985 * flushed for the new mapping, but there may still be TLB entries for 3986 * other mappings belonging to other processes in the 1MB range 3987 * covered by the L1 entry. 3988 * 3989 * Since 'rv == 0', we know that the L1 already contains the correct 3990 * value, so the fault must be due to a stale TLB entry. 3991 * 3992 * Since we always need to flush the TLB anyway in the case where we 3993 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 3994 * stale TLB entries dynamically. 3995 * 3996 * However, the above condition can ONLY happen if the current L1 is 3997 * being shared. If it happens when the L1 is unshared, it indicates 3998 * that other parts of the pmap are not doing their job WRT managing 3999 * the TLB. 4000 */ 4001 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4002 extern int last_fault_code; 4003 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4004 pm, va, ftype); 4005 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4006 l2, l2b, ptep, pl1pd); 4007 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4008 pte, l1pd, last_fault_code); 4009 #ifdef DDB 4010 Debugger(); 4011 #endif 4012 } 4013 #endif 4014 4015 cpu_tlb_flushID_SE(va); 4016 cpu_cpwait(); 4017 4018 rv = 1; 4019 4020 out: 4021 pmap_release_pmap_lock(pm); 4022 PMAP_MAP_TO_HEAD_UNLOCK(); 4023 4024 return (rv); 4025 } 4026 4027 /* 4028 * Routine: pmap_procwr 4029 * 4030 * Function: 4031 * Synchronize caches corresponding to [addr, addr+len) in p. 4032 * 4033 */ 4034 void 4035 pmap_procwr(struct proc *p, vaddr_t va, int len) 4036 { 4037 /* We only need to do anything if it is the current process. */ 4038 if (p == curproc) 4039 cpu_icache_sync_range(va, len); 4040 } 4041 4042 /* 4043 * Routine: pmap_unwire 4044 * Function: Clear the wired attribute for a map/virtual-address pair. 4045 * 4046 * In/out conditions: 4047 * The mapping must already exist in the pmap. 4048 */ 4049 void 4050 pmap_unwire(pmap_t pm, vaddr_t va) 4051 { 4052 struct l2_bucket *l2b; 4053 pt_entry_t *ptep, pte; 4054 struct vm_page *pg; 4055 paddr_t pa; 4056 4057 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4058 4059 PMAP_MAP_TO_HEAD_LOCK(); 4060 pmap_acquire_pmap_lock(pm); 4061 4062 l2b = pmap_get_l2_bucket(pm, va); 4063 KDASSERT(l2b != NULL); 4064 4065 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4066 pte = *ptep; 4067 4068 /* Extract the physical address of the page */ 4069 pa = l2pte_pa(pte); 4070 4071 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4072 /* Update the wired bit in the pv entry for this page. */ 4073 simple_lock(&pg->mdpage.pvh_slock); 4074 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 4075 simple_unlock(&pg->mdpage.pvh_slock); 4076 } 4077 4078 pmap_release_pmap_lock(pm); 4079 PMAP_MAP_TO_HEAD_UNLOCK(); 4080 } 4081 4082 void 4083 pmap_activate(struct lwp *l) 4084 { 4085 extern int block_userspace_access; 4086 pmap_t opm, npm, rpm; 4087 uint32_t odacr, ndacr; 4088 int oldirqstate; 4089 4090 /* 4091 * If activating a non-current lwp or the current lwp is 4092 * already active, just return. 4093 */ 4094 if (l != curlwp || 4095 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4096 return; 4097 4098 npm = l->l_proc->p_vmspace->vm_map.pmap; 4099 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4100 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4101 4102 /* 4103 * If TTB and DACR are unchanged, short-circuit all the 4104 * TLB/cache management stuff. 4105 */ 4106 if (pmap_previous_active_lwp != NULL) { 4107 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4108 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4109 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4110 4111 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4112 goto all_done; 4113 } else 4114 opm = NULL; 4115 4116 PMAPCOUNT(activations); 4117 block_userspace_access = 1; 4118 4119 /* 4120 * If switching to a user vmspace which is different to the 4121 * most recent one, and the most recent one is potentially 4122 * live in the cache, we must write-back and invalidate the 4123 * entire cache. 4124 */ 4125 rpm = pmap_recent_user; 4126 4127 /* 4128 * XXXSCW: There's a corner case here which can leave turds in the cache as 4129 * reported in kern/41058. They're probably left over during tear-down and 4130 * switching away from an exiting process. Until the root cause is identified 4131 * and fixed, zap the cache when switching pmaps. This will result in a few 4132 * unnecessary cache flushes, but that's better than silently corrupting data. 4133 */ 4134 #if 0 4135 if (npm != pmap_kernel() && rpm && npm != rpm && 4136 rpm->pm_cstate.cs_cache) { 4137 rpm->pm_cstate.cs_cache = 0; 4138 #ifdef PMAP_CACHE_VIVT 4139 cpu_idcache_wbinv_all(); 4140 #endif 4141 } 4142 #else 4143 if (rpm) { 4144 rpm->pm_cstate.cs_cache = 0; 4145 if (npm == pmap_kernel()) 4146 pmap_recent_user = NULL; 4147 #ifdef PMAP_CACHE_VIVT 4148 cpu_idcache_wbinv_all(); 4149 #endif 4150 } 4151 #endif 4152 4153 /* No interrupts while we frob the TTB/DACR */ 4154 oldirqstate = disable_interrupts(IF32_bits); 4155 4156 /* 4157 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4158 * entry corresponding to 'vector_page' in the incoming L1 table 4159 * before switching to it otherwise subsequent interrupts/exceptions 4160 * (including domain faults!) will jump into hyperspace. 4161 */ 4162 if (npm->pm_pl1vec != NULL) { 4163 cpu_tlb_flushID_SE((u_int)vector_page); 4164 cpu_cpwait(); 4165 *npm->pm_pl1vec = npm->pm_l1vec; 4166 PTE_SYNC(npm->pm_pl1vec); 4167 } 4168 4169 cpu_domains(ndacr); 4170 4171 if (npm == pmap_kernel() || npm == rpm) { 4172 /* 4173 * Switching to a kernel thread, or back to the 4174 * same user vmspace as before... Simply update 4175 * the TTB (no TLB flush required) 4176 */ 4177 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4178 "r"(npm->pm_l1->l1_physaddr)); 4179 cpu_cpwait(); 4180 } else { 4181 /* 4182 * Otherwise, update TTB and flush TLB 4183 */ 4184 cpu_context_switch(npm->pm_l1->l1_physaddr); 4185 if (rpm != NULL) 4186 rpm->pm_cstate.cs_tlb = 0; 4187 } 4188 4189 restore_interrupts(oldirqstate); 4190 4191 block_userspace_access = 0; 4192 4193 all_done: 4194 /* 4195 * The new pmap is resident. Make sure it's marked 4196 * as resident in the cache/TLB. 4197 */ 4198 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4199 if (npm != pmap_kernel()) 4200 pmap_recent_user = npm; 4201 4202 /* The old pmap is not longer active */ 4203 if (opm != NULL) 4204 opm->pm_activated = false; 4205 4206 /* But the new one is */ 4207 npm->pm_activated = true; 4208 } 4209 4210 void 4211 pmap_deactivate(struct lwp *l) 4212 { 4213 4214 /* 4215 * If the process is exiting, make sure pmap_activate() does 4216 * a full MMU context-switch and cache flush, which we might 4217 * otherwise skip. See PR port-arm/38950. 4218 */ 4219 if (l->l_proc->p_sflag & PS_WEXIT) 4220 pmap_previous_active_lwp = NULL; 4221 4222 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4223 } 4224 4225 void 4226 pmap_update(pmap_t pm) 4227 { 4228 4229 if (pm->pm_remove_all) { 4230 /* 4231 * Finish up the pmap_remove_all() optimisation by flushing 4232 * the TLB. 4233 */ 4234 pmap_tlb_flushID(pm); 4235 pm->pm_remove_all = false; 4236 } 4237 4238 if (pmap_is_current(pm)) { 4239 /* 4240 * If we're dealing with a current userland pmap, move its L1 4241 * to the end of the LRU. 4242 */ 4243 if (pm != pmap_kernel()) 4244 pmap_use_l1(pm); 4245 4246 /* 4247 * We can assume we're done with frobbing the cache/tlb for 4248 * now. Make sure any future pmap ops don't skip cache/tlb 4249 * flushes. 4250 */ 4251 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4252 } 4253 4254 PMAPCOUNT(updates); 4255 4256 /* 4257 * make sure TLB/cache operations have completed. 4258 */ 4259 cpu_cpwait(); 4260 } 4261 4262 void 4263 pmap_remove_all(pmap_t pm) 4264 { 4265 4266 /* 4267 * The vmspace described by this pmap is about to be torn down. 4268 * Until pmap_update() is called, UVM will only make calls 4269 * to pmap_remove(). We can make life much simpler by flushing 4270 * the cache now, and deferring TLB invalidation to pmap_update(). 4271 */ 4272 #ifdef PMAP_CACHE_VIVT 4273 pmap_idcache_wbinv_all(pm); 4274 #endif 4275 pm->pm_remove_all = true; 4276 } 4277 4278 /* 4279 * Retire the given physical map from service. 4280 * Should only be called if the map contains no valid mappings. 4281 */ 4282 void 4283 pmap_destroy(pmap_t pm) 4284 { 4285 u_int count; 4286 4287 if (pm == NULL) 4288 return; 4289 4290 if (pm->pm_remove_all) { 4291 pmap_tlb_flushID(pm); 4292 pm->pm_remove_all = false; 4293 } 4294 4295 /* 4296 * Drop reference count 4297 */ 4298 mutex_enter(&pm->pm_lock); 4299 count = --pm->pm_obj.uo_refs; 4300 mutex_exit(&pm->pm_lock); 4301 if (count > 0) { 4302 if (pmap_is_current(pm)) { 4303 if (pm != pmap_kernel()) 4304 pmap_use_l1(pm); 4305 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4306 } 4307 return; 4308 } 4309 4310 /* 4311 * reference count is zero, free pmap resources and then free pmap. 4312 */ 4313 4314 if (vector_page < KERNEL_BASE) { 4315 KDASSERT(!pmap_is_current(pm)); 4316 4317 /* Remove the vector page mapping */ 4318 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4319 pmap_update(pm); 4320 } 4321 4322 LIST_REMOVE(pm, pm_list); 4323 4324 pmap_free_l1(pm); 4325 4326 if (pmap_recent_user == pm) 4327 pmap_recent_user = NULL; 4328 4329 UVM_OBJ_DESTROY(&pm->pm_obj); 4330 4331 /* return the pmap to the pool */ 4332 pool_cache_put(&pmap_cache, pm); 4333 } 4334 4335 4336 /* 4337 * void pmap_reference(pmap_t pm) 4338 * 4339 * Add a reference to the specified pmap. 4340 */ 4341 void 4342 pmap_reference(pmap_t pm) 4343 { 4344 4345 if (pm == NULL) 4346 return; 4347 4348 pmap_use_l1(pm); 4349 4350 mutex_enter(&pm->pm_lock); 4351 pm->pm_obj.uo_refs++; 4352 mutex_exit(&pm->pm_lock); 4353 } 4354 4355 #if ARM_MMU_V6 > 0 4356 4357 static struct evcnt pmap_prefer_nochange_ev = 4358 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4359 static struct evcnt pmap_prefer_change_ev = 4360 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4361 4362 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4363 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4364 4365 void 4366 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4367 { 4368 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4369 vaddr_t va = *vap; 4370 vaddr_t diff = (hint - va) & mask; 4371 if (diff == 0) { 4372 pmap_prefer_nochange_ev.ev_count++; 4373 } else { 4374 pmap_prefer_change_ev.ev_count++; 4375 if (__predict_false(td)) 4376 va -= mask + 1; 4377 *vap = va + diff; 4378 } 4379 } 4380 #endif /* ARM_MMU_V6 */ 4381 4382 /* 4383 * pmap_zero_page() 4384 * 4385 * Zero a given physical page by mapping it at a page hook point. 4386 * In doing the zero page op, the page we zero is mapped cachable, as with 4387 * StrongARM accesses to non-cached pages are non-burst making writing 4388 * _any_ bulk data very slow. 4389 */ 4390 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4391 void 4392 pmap_zero_page_generic(paddr_t phys) 4393 { 4394 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4395 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4396 #endif 4397 #ifdef PMAP_CACHE_VIPT 4398 /* Choose the last page color it had, if any */ 4399 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4400 #else 4401 const vsize_t va_offset = 0; 4402 #endif 4403 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4404 4405 #ifdef DEBUG 4406 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4407 panic("pmap_zero_page: page has mappings"); 4408 #endif 4409 4410 KDASSERT((phys & PGOFSET) == 0); 4411 4412 /* 4413 * Hook in the page, zero it, and purge the cache for that 4414 * zeroed page. Invalidate the TLB as needed. 4415 */ 4416 *ptep = L2_S_PROTO | phys | 4417 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4418 PTE_SYNC(ptep); 4419 cpu_tlb_flushD_SE(cdstp + va_offset); 4420 cpu_cpwait(); 4421 bzero_page(cdstp + va_offset); 4422 /* 4423 * Unmap the page. 4424 */ 4425 *ptep = 0; 4426 PTE_SYNC(ptep); 4427 cpu_tlb_flushD_SE(cdstp + va_offset); 4428 #ifdef PMAP_CACHE_VIVT 4429 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4430 #endif 4431 #ifdef PMAP_CACHE_VIPT 4432 /* 4433 * This page is now cache resident so it now has a page color. 4434 * Any contents have been obliterated so clear the EXEC flag. 4435 */ 4436 if (!pmap_is_page_colored_p(pg)) { 4437 PMAPCOUNT(vac_color_new); 4438 pg->mdpage.pvh_attrs |= PVF_COLORED; 4439 } 4440 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4441 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4442 PMAPCOUNT(exec_discarded_zero); 4443 } 4444 pg->mdpage.pvh_attrs |= PVF_DIRTY; 4445 #endif 4446 } 4447 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4448 4449 #if ARM_MMU_XSCALE == 1 4450 void 4451 pmap_zero_page_xscale(paddr_t phys) 4452 { 4453 #ifdef DEBUG 4454 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4455 4456 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4457 panic("pmap_zero_page: page has mappings"); 4458 #endif 4459 4460 KDASSERT((phys & PGOFSET) == 0); 4461 4462 /* 4463 * Hook in the page, zero it, and purge the cache for that 4464 * zeroed page. Invalidate the TLB as needed. 4465 */ 4466 *cdst_pte = L2_S_PROTO | phys | 4467 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4468 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4469 PTE_SYNC(cdst_pte); 4470 cpu_tlb_flushD_SE(cdstp); 4471 cpu_cpwait(); 4472 bzero_page(cdstp); 4473 xscale_cache_clean_minidata(); 4474 } 4475 #endif /* ARM_MMU_XSCALE == 1 */ 4476 4477 /* pmap_pageidlezero() 4478 * 4479 * The same as above, except that we assume that the page is not 4480 * mapped. This means we never have to flush the cache first. Called 4481 * from the idle loop. 4482 */ 4483 bool 4484 pmap_pageidlezero(paddr_t phys) 4485 { 4486 unsigned int i; 4487 int *ptr; 4488 bool rv = true; 4489 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4490 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4491 #endif 4492 #ifdef PMAP_CACHE_VIPT 4493 /* Choose the last page color it had, if any */ 4494 const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4495 #else 4496 const vsize_t va_offset = 0; 4497 #endif 4498 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4499 4500 4501 #ifdef DEBUG 4502 if (!SLIST_EMPTY(&pg->mdpage.pvh_list)) 4503 panic("pmap_pageidlezero: page has mappings"); 4504 #endif 4505 4506 KDASSERT((phys & PGOFSET) == 0); 4507 4508 /* 4509 * Hook in the page, zero it, and purge the cache for that 4510 * zeroed page. Invalidate the TLB as needed. 4511 */ 4512 *ptep = L2_S_PROTO | phys | 4513 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4514 PTE_SYNC(ptep); 4515 cpu_tlb_flushD_SE(cdstp + va_offset); 4516 cpu_cpwait(); 4517 4518 for (i = 0, ptr = (int *)(cdstp + va_offset); 4519 i < (PAGE_SIZE / sizeof(int)); i++) { 4520 if (sched_curcpu_runnable_p() != 0) { 4521 /* 4522 * A process has become ready. Abort now, 4523 * so we don't keep it waiting while we 4524 * do slow memory access to finish this 4525 * page. 4526 */ 4527 rv = false; 4528 break; 4529 } 4530 *ptr++ = 0; 4531 } 4532 4533 #ifdef PMAP_CACHE_VIVT 4534 if (rv) 4535 /* 4536 * if we aborted we'll rezero this page again later so don't 4537 * purge it unless we finished it 4538 */ 4539 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4540 #elif defined(PMAP_CACHE_VIPT) 4541 /* 4542 * This page is now cache resident so it now has a page color. 4543 * Any contents have been obliterated so clear the EXEC flag. 4544 */ 4545 if (!pmap_is_page_colored_p(pg)) { 4546 PMAPCOUNT(vac_color_new); 4547 pg->mdpage.pvh_attrs |= PVF_COLORED; 4548 } 4549 if (PV_IS_EXEC_P(pg->mdpage.pvh_attrs)) { 4550 pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4551 PMAPCOUNT(exec_discarded_zero); 4552 } 4553 #endif 4554 /* 4555 * Unmap the page. 4556 */ 4557 *ptep = 0; 4558 PTE_SYNC(ptep); 4559 cpu_tlb_flushD_SE(cdstp + va_offset); 4560 4561 return (rv); 4562 } 4563 4564 /* 4565 * pmap_copy_page() 4566 * 4567 * Copy one physical page into another, by mapping the pages into 4568 * hook points. The same comment regarding cachability as in 4569 * pmap_zero_page also applies here. 4570 */ 4571 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4572 void 4573 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4574 { 4575 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4576 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4577 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4578 #endif 4579 #ifdef PMAP_CACHE_VIPT 4580 const vsize_t src_va_offset = src_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4581 const vsize_t dst_va_offset = dst_pg->mdpage.pvh_attrs & arm_cache_prefer_mask; 4582 #else 4583 const vsize_t src_va_offset = 0; 4584 const vsize_t dst_va_offset = 0; 4585 #endif 4586 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4587 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4588 4589 #ifdef DEBUG 4590 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4591 panic("pmap_copy_page: dst page has mappings"); 4592 #endif 4593 4594 #ifdef PMAP_CACHE_VIPT 4595 KASSERT(src_pg->mdpage.pvh_attrs & (PVF_COLORED|PVF_NC)); 4596 #endif 4597 KDASSERT((src & PGOFSET) == 0); 4598 KDASSERT((dst & PGOFSET) == 0); 4599 4600 /* 4601 * Clean the source page. Hold the source page's lock for 4602 * the duration of the copy so that no other mappings can 4603 * be created while we have a potentially aliased mapping. 4604 */ 4605 simple_lock(&src_pg->mdpage.pvh_slock); 4606 #ifdef PMAP_CACHE_VIVT 4607 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4608 #endif 4609 4610 /* 4611 * Map the pages into the page hook points, copy them, and purge 4612 * the cache for the appropriate page. Invalidate the TLB 4613 * as required. 4614 */ 4615 *src_ptep = L2_S_PROTO 4616 | src 4617 #ifdef PMAP_CACHE_VIPT 4618 | ((src_pg->mdpage.pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4619 #endif 4620 #ifdef PMAP_CACHE_VIVT 4621 | pte_l2_s_cache_mode 4622 #endif 4623 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4624 *dst_ptep = L2_S_PROTO | dst | 4625 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4626 PTE_SYNC(src_ptep); 4627 PTE_SYNC(dst_ptep); 4628 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4629 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4630 cpu_cpwait(); 4631 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4632 #ifdef PMAP_CACHE_VIVT 4633 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4634 #endif 4635 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4636 #ifdef PMAP_CACHE_VIVT 4637 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4638 #endif 4639 /* 4640 * Unmap the pages. 4641 */ 4642 *src_ptep = 0; 4643 *dst_ptep = 0; 4644 PTE_SYNC(src_ptep); 4645 PTE_SYNC(dst_ptep); 4646 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4647 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4648 #ifdef PMAP_CACHE_VIPT 4649 /* 4650 * Now that the destination page is in the cache, mark it as colored. 4651 * If this was an exec page, discard it. 4652 */ 4653 if (!pmap_is_page_colored_p(dst_pg)) { 4654 PMAPCOUNT(vac_color_new); 4655 dst_pg->mdpage.pvh_attrs |= PVF_COLORED; 4656 } 4657 if (PV_IS_EXEC_P(dst_pg->mdpage.pvh_attrs)) { 4658 dst_pg->mdpage.pvh_attrs &= ~PVF_EXEC; 4659 PMAPCOUNT(exec_discarded_copy); 4660 } 4661 dst_pg->mdpage.pvh_attrs |= PVF_DIRTY; 4662 #endif 4663 } 4664 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4665 4666 #if ARM_MMU_XSCALE == 1 4667 void 4668 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4669 { 4670 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4671 #ifdef DEBUG 4672 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4673 4674 if (!SLIST_EMPTY(&dst_pg->mdpage.pvh_list)) 4675 panic("pmap_copy_page: dst page has mappings"); 4676 #endif 4677 4678 KDASSERT((src & PGOFSET) == 0); 4679 KDASSERT((dst & PGOFSET) == 0); 4680 4681 /* 4682 * Clean the source page. Hold the source page's lock for 4683 * the duration of the copy so that no other mappings can 4684 * be created while we have a potentially aliased mapping. 4685 */ 4686 simple_lock(&src_pg->mdpage.pvh_slock); 4687 #ifdef PMAP_CACHE_VIVT 4688 (void) pmap_clean_page(SLIST_FIRST(&src_pg->mdpage.pvh_list), true); 4689 #endif 4690 4691 /* 4692 * Map the pages into the page hook points, copy them, and purge 4693 * the cache for the appropriate page. Invalidate the TLB 4694 * as required. 4695 */ 4696 *csrc_pte = L2_S_PROTO | src | 4697 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4698 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4699 PTE_SYNC(csrc_pte); 4700 *cdst_pte = L2_S_PROTO | dst | 4701 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4702 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4703 PTE_SYNC(cdst_pte); 4704 cpu_tlb_flushD_SE(csrcp); 4705 cpu_tlb_flushD_SE(cdstp); 4706 cpu_cpwait(); 4707 bcopy_page(csrcp, cdstp); 4708 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 4709 xscale_cache_clean_minidata(); 4710 } 4711 #endif /* ARM_MMU_XSCALE == 1 */ 4712 4713 /* 4714 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4715 * 4716 * Return the start and end addresses of the kernel's virtual space. 4717 * These values are setup in pmap_bootstrap and are updated as pages 4718 * are allocated. 4719 */ 4720 void 4721 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4722 { 4723 *start = virtual_avail; 4724 *end = virtual_end; 4725 } 4726 4727 /* 4728 * Helper function for pmap_grow_l2_bucket() 4729 */ 4730 static inline int 4731 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4732 { 4733 struct l2_bucket *l2b; 4734 pt_entry_t *ptep; 4735 paddr_t pa; 4736 4737 if (uvm.page_init_done == false) { 4738 #ifdef PMAP_STEAL_MEMORY 4739 pv_addr_t pv; 4740 pmap_boot_pagealloc(PAGE_SIZE, 4741 #ifdef PMAP_CACHE_VIPT 4742 arm_cache_prefer_mask, 4743 va & arm_cache_prefer_mask, 4744 #else 4745 0, 0, 4746 #endif 4747 &pv); 4748 pa = pv.pv_pa; 4749 #else 4750 if (uvm_page_physget(&pa) == false) 4751 return (1); 4752 #endif /* PMAP_STEAL_MEMORY */ 4753 } else { 4754 struct vm_page *pg; 4755 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4756 if (pg == NULL) 4757 return (1); 4758 pa = VM_PAGE_TO_PHYS(pg); 4759 #ifdef PMAP_CACHE_VIPT 4760 /* 4761 * This new page must not have any mappings. Enter it via 4762 * pmap_kenter_pa and let that routine do the hard work. 4763 */ 4764 KASSERT(SLIST_EMPTY(&pg->mdpage.pvh_list)); 4765 pmap_kenter_pa(va, pa, 4766 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); 4767 #endif 4768 } 4769 4770 if (pap) 4771 *pap = pa; 4772 4773 PMAPCOUNT(pt_mappings); 4774 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4775 KDASSERT(l2b != NULL); 4776 4777 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4778 *ptep = L2_S_PROTO | pa | cache_mode | 4779 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4780 PTE_SYNC(ptep); 4781 memset((void *)va, 0, PAGE_SIZE); 4782 return (0); 4783 } 4784 4785 /* 4786 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4787 * used by pmap_growkernel(). 4788 */ 4789 static inline struct l2_bucket * 4790 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4791 { 4792 struct l2_dtable *l2; 4793 struct l2_bucket *l2b; 4794 u_short l1idx; 4795 vaddr_t nva; 4796 4797 l1idx = L1_IDX(va); 4798 4799 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4800 /* 4801 * No mapping at this address, as there is 4802 * no entry in the L1 table. 4803 * Need to allocate a new l2_dtable. 4804 */ 4805 nva = pmap_kernel_l2dtable_kva; 4806 if ((nva & PGOFSET) == 0) { 4807 /* 4808 * Need to allocate a backing page 4809 */ 4810 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4811 return (NULL); 4812 } 4813 4814 l2 = (struct l2_dtable *)nva; 4815 nva += sizeof(struct l2_dtable); 4816 4817 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4818 /* 4819 * The new l2_dtable straddles a page boundary. 4820 * Map in another page to cover it. 4821 */ 4822 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4823 return (NULL); 4824 } 4825 4826 pmap_kernel_l2dtable_kva = nva; 4827 4828 /* 4829 * Link it into the parent pmap 4830 */ 4831 pm->pm_l2[L2_IDX(l1idx)] = l2; 4832 } 4833 4834 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4835 4836 /* 4837 * Fetch pointer to the L2 page table associated with the address. 4838 */ 4839 if (l2b->l2b_kva == NULL) { 4840 pt_entry_t *ptep; 4841 4842 /* 4843 * No L2 page table has been allocated. Chances are, this 4844 * is because we just allocated the l2_dtable, above. 4845 */ 4846 nva = pmap_kernel_l2ptp_kva; 4847 ptep = (pt_entry_t *)nva; 4848 if ((nva & PGOFSET) == 0) { 4849 /* 4850 * Need to allocate a backing page 4851 */ 4852 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4853 &pmap_kernel_l2ptp_phys)) 4854 return (NULL); 4855 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4856 } 4857 4858 l2->l2_occupancy++; 4859 l2b->l2b_kva = ptep; 4860 l2b->l2b_l1idx = l1idx; 4861 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4862 4863 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4864 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4865 } 4866 4867 return (l2b); 4868 } 4869 4870 vaddr_t 4871 pmap_growkernel(vaddr_t maxkvaddr) 4872 { 4873 pmap_t kpm = pmap_kernel(); 4874 struct l1_ttable *l1; 4875 struct l2_bucket *l2b; 4876 pd_entry_t *pl1pd; 4877 int s; 4878 4879 if (maxkvaddr <= pmap_curmaxkvaddr) 4880 goto out; /* we are OK */ 4881 4882 NPDEBUG(PDB_GROWKERN, 4883 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4884 pmap_curmaxkvaddr, maxkvaddr)); 4885 4886 KDASSERT(maxkvaddr <= virtual_end); 4887 4888 /* 4889 * whoops! we need to add kernel PTPs 4890 */ 4891 4892 s = splhigh(); /* to be safe */ 4893 mutex_enter(&kpm->pm_lock); 4894 4895 /* Map 1MB at a time */ 4896 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4897 4898 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4899 KDASSERT(l2b != NULL); 4900 4901 /* Distribute new L1 entry to all other L1s */ 4902 SLIST_FOREACH(l1, &l1_list, l1_link) { 4903 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4904 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4905 L1_C_PROTO; 4906 PTE_SYNC(pl1pd); 4907 } 4908 } 4909 4910 /* 4911 * flush out the cache, expensive but growkernel will happen so 4912 * rarely 4913 */ 4914 cpu_dcache_wbinv_all(); 4915 cpu_tlb_flushD(); 4916 cpu_cpwait(); 4917 4918 mutex_exit(&kpm->pm_lock); 4919 splx(s); 4920 4921 out: 4922 return (pmap_curmaxkvaddr); 4923 } 4924 4925 /************************ Utility routines ****************************/ 4926 4927 /* 4928 * vector_page_setprot: 4929 * 4930 * Manipulate the protection of the vector page. 4931 */ 4932 void 4933 vector_page_setprot(int prot) 4934 { 4935 struct l2_bucket *l2b; 4936 pt_entry_t *ptep; 4937 4938 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4939 KDASSERT(l2b != NULL); 4940 4941 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4942 4943 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4944 PTE_SYNC(ptep); 4945 cpu_tlb_flushD_SE(vector_page); 4946 cpu_cpwait(); 4947 } 4948 4949 /* 4950 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4951 * Returns true if the mapping exists, else false. 4952 * 4953 * NOTE: This function is only used by a couple of arm-specific modules. 4954 * It is not safe to take any pmap locks here, since we could be right 4955 * in the middle of debugging the pmap anyway... 4956 * 4957 * It is possible for this routine to return false even though a valid 4958 * mapping does exist. This is because we don't lock, so the metadata 4959 * state may be inconsistent. 4960 * 4961 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4962 * a "section" mapping. 4963 */ 4964 bool 4965 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 4966 { 4967 struct l2_dtable *l2; 4968 pd_entry_t *pl1pd, l1pd; 4969 pt_entry_t *ptep; 4970 u_short l1idx; 4971 4972 if (pm->pm_l1 == NULL) 4973 return false; 4974 4975 l1idx = L1_IDX(va); 4976 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 4977 l1pd = *pl1pd; 4978 4979 if (l1pte_section_p(l1pd)) { 4980 *ptp = NULL; 4981 return true; 4982 } 4983 4984 if (pm->pm_l2 == NULL) 4985 return false; 4986 4987 l2 = pm->pm_l2[L2_IDX(l1idx)]; 4988 4989 if (l2 == NULL || 4990 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 4991 return false; 4992 } 4993 4994 *ptp = &ptep[l2pte_index(va)]; 4995 return true; 4996 } 4997 4998 bool 4999 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5000 { 5001 u_short l1idx; 5002 5003 if (pm->pm_l1 == NULL) 5004 return false; 5005 5006 l1idx = L1_IDX(va); 5007 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5008 5009 return true; 5010 } 5011 5012 /************************ Bootstrapping routines ****************************/ 5013 5014 static void 5015 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5016 { 5017 int i; 5018 5019 l1->l1_kva = l1pt; 5020 l1->l1_domain_use_count = 0; 5021 l1->l1_domain_first = 0; 5022 5023 for (i = 0; i < PMAP_DOMAINS; i++) 5024 l1->l1_domain_free[i] = i + 1; 5025 5026 /* 5027 * Copy the kernel's L1 entries to each new L1. 5028 */ 5029 if (pmap_initialized) 5030 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5031 5032 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5033 &l1->l1_physaddr) == false) 5034 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5035 5036 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5037 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5038 } 5039 5040 /* 5041 * pmap_bootstrap() is called from the board-specific initarm() routine 5042 * once the kernel L1/L2 descriptors tables have been set up. 5043 * 5044 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5045 * spread over a number of disparate files/functions. 5046 * 5047 * We are passed the following parameters 5048 * - kernel_l1pt 5049 * This is a pointer to the base of the kernel's L1 translation table. 5050 * - vstart 5051 * 1MB-aligned start of managed kernel virtual memory. 5052 * - vend 5053 * 1MB-aligned end of managed kernel virtual memory. 5054 * 5055 * We use the first parameter to build the metadata (struct l1_ttable and 5056 * struct l2_dtable) necessary to track kernel mappings. 5057 */ 5058 #define PMAP_STATIC_L2_SIZE 16 5059 void 5060 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5061 { 5062 static struct l1_ttable static_l1; 5063 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5064 struct l1_ttable *l1 = &static_l1; 5065 struct l2_dtable *l2; 5066 struct l2_bucket *l2b; 5067 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5068 pmap_t pm = pmap_kernel(); 5069 pd_entry_t pde; 5070 pt_entry_t *ptep; 5071 paddr_t pa; 5072 vaddr_t va; 5073 vsize_t size; 5074 int nptes, l1idx, l2idx, l2next = 0; 5075 5076 /* 5077 * Initialise the kernel pmap object 5078 */ 5079 pm->pm_l1 = l1; 5080 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5081 pm->pm_activated = true; 5082 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5083 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5084 5085 /* 5086 * Scan the L1 translation table created by initarm() and create 5087 * the required metadata for all valid mappings found in it. 5088 */ 5089 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5090 pde = l1pt[l1idx]; 5091 5092 /* 5093 * We're only interested in Coarse mappings. 5094 * pmap_extract() can deal with section mappings without 5095 * recourse to checking L2 metadata. 5096 */ 5097 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5098 continue; 5099 5100 /* 5101 * Lookup the KVA of this L2 descriptor table 5102 */ 5103 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5104 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5105 if (ptep == NULL) { 5106 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5107 (u_int)l1idx << L1_S_SHIFT, pa); 5108 } 5109 5110 /* 5111 * Fetch the associated L2 metadata structure. 5112 * Allocate a new one if necessary. 5113 */ 5114 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5115 if (l2next == PMAP_STATIC_L2_SIZE) 5116 panic("pmap_bootstrap: out of static L2s"); 5117 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5118 } 5119 5120 /* 5121 * One more L1 slot tracked... 5122 */ 5123 l2->l2_occupancy++; 5124 5125 /* 5126 * Fill in the details of the L2 descriptor in the 5127 * appropriate bucket. 5128 */ 5129 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5130 l2b->l2b_kva = ptep; 5131 l2b->l2b_phys = pa; 5132 l2b->l2b_l1idx = l1idx; 5133 5134 /* 5135 * Establish an initial occupancy count for this descriptor 5136 */ 5137 for (l2idx = 0; 5138 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5139 l2idx++) { 5140 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5141 l2b->l2b_occupancy++; 5142 } 5143 } 5144 5145 /* 5146 * Make sure the descriptor itself has the correct cache mode. 5147 * If not, fix it, but whine about the problem. Port-meisters 5148 * should consider this a clue to fix up their initarm() 5149 * function. :) 5150 */ 5151 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5152 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5153 "L2 pte @ %p\n", ptep); 5154 } 5155 } 5156 5157 /* 5158 * Ensure the primary (kernel) L1 has the correct cache mode for 5159 * a page table. Bitch if it is not correctly set. 5160 */ 5161 for (va = (vaddr_t)l1pt; 5162 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5163 if (pmap_set_pt_cache_mode(l1pt, va)) 5164 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5165 "primary L1 @ 0x%lx\n", va); 5166 } 5167 5168 cpu_dcache_wbinv_all(); 5169 cpu_tlb_flushID(); 5170 cpu_cpwait(); 5171 5172 /* 5173 * now we allocate the "special" VAs which are used for tmp mappings 5174 * by the pmap (and other modules). we allocate the VAs by advancing 5175 * virtual_avail (note that there are no pages mapped at these VAs). 5176 * 5177 * Managed KVM space start from wherever initarm() tells us. 5178 */ 5179 virtual_avail = vstart; 5180 virtual_end = vend; 5181 5182 #ifdef PMAP_CACHE_VIPT 5183 /* 5184 * If we have a VIPT cache, we need one page/pte per possible alias 5185 * page so we won't violate cache aliasing rules. 5186 */ 5187 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5188 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5189 #else 5190 nptes = 1; 5191 #endif 5192 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5193 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5194 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5195 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5196 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5197 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5198 (void *)&msgbufaddr, NULL); 5199 5200 /* 5201 * Allocate a range of kernel virtual address space to be used 5202 * for L2 descriptor tables and metadata allocation in 5203 * pmap_growkernel(). 5204 */ 5205 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5206 pmap_alloc_specials(&virtual_avail, 5207 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5208 &pmap_kernel_l2ptp_kva, NULL); 5209 5210 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5211 pmap_alloc_specials(&virtual_avail, 5212 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5213 &pmap_kernel_l2dtable_kva, NULL); 5214 5215 /* 5216 * init the static-global locks and global pmap list. 5217 */ 5218 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5219 5220 /* 5221 * We can now initialise the first L1's metadata. 5222 */ 5223 SLIST_INIT(&l1_list); 5224 TAILQ_INIT(&l1_lru_list); 5225 simple_lock_init(&l1_lru_lock); 5226 pmap_init_l1(l1, l1pt); 5227 5228 /* Set up vector page L1 details, if necessary */ 5229 if (vector_page < KERNEL_BASE) { 5230 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5231 l2b = pmap_get_l2_bucket(pm, vector_page); 5232 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5233 L1_C_DOM(pm->pm_domain); 5234 } else 5235 pm->pm_pl1vec = NULL; 5236 5237 /* 5238 * Initialize the pmap cache 5239 */ 5240 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5241 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5242 LIST_INIT(&pmap_pmaps); 5243 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5244 5245 /* 5246 * Initialize the pv pool. 5247 */ 5248 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5249 &pmap_bootstrap_pv_allocator, IPL_NONE); 5250 5251 /* 5252 * Initialize the L2 dtable pool and cache. 5253 */ 5254 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5255 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5256 5257 /* 5258 * Initialise the L2 descriptor table pool and cache 5259 */ 5260 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5261 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5262 pmap_l2ptp_ctor, NULL, NULL); 5263 5264 cpu_dcache_wbinv_all(); 5265 } 5266 5267 static int 5268 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5269 { 5270 pd_entry_t *pdep, pde; 5271 pt_entry_t *ptep, pte; 5272 vaddr_t pa; 5273 int rv = 0; 5274 5275 /* 5276 * Make sure the descriptor itself has the correct cache mode 5277 */ 5278 pdep = &kl1[L1_IDX(va)]; 5279 pde = *pdep; 5280 5281 if (l1pte_section_p(pde)) { 5282 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5283 *pdep = (pde & ~L1_S_CACHE_MASK) | 5284 pte_l1_s_cache_mode_pt; 5285 PTE_SYNC(pdep); 5286 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5287 rv = 1; 5288 } 5289 } else { 5290 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5291 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5292 if (ptep == NULL) 5293 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5294 5295 ptep = &ptep[l2pte_index(va)]; 5296 pte = *ptep; 5297 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5298 *ptep = (pte & ~L2_S_CACHE_MASK) | 5299 pte_l2_s_cache_mode_pt; 5300 PTE_SYNC(ptep); 5301 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5302 rv = 1; 5303 } 5304 } 5305 5306 return (rv); 5307 } 5308 5309 static void 5310 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5311 { 5312 vaddr_t va = *availp; 5313 struct l2_bucket *l2b; 5314 5315 if (ptep) { 5316 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5317 if (l2b == NULL) 5318 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5319 5320 if (ptep) 5321 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5322 } 5323 5324 *vap = va; 5325 *availp = va + (PAGE_SIZE * pages); 5326 } 5327 5328 void 5329 pmap_init(void) 5330 { 5331 5332 /* 5333 * Set the available memory vars - These do not map to real memory 5334 * addresses and cannot as the physical memory is fragmented. 5335 * They are used by ps for %mem calculations. 5336 * One could argue whether this should be the entire memory or just 5337 * the memory that is useable in a user process. 5338 */ 5339 avail_start = ptoa(vm_physmem[0].start); 5340 avail_end = ptoa(vm_physmem[vm_nphysseg - 1].end); 5341 5342 /* 5343 * Now we need to free enough pv_entry structures to allow us to get 5344 * the kmem_map/kmem_object allocated and inited (done after this 5345 * function is finished). to do this we allocate one bootstrap page out 5346 * of kernel_map and use it to provide an initial pool of pv_entry 5347 * structures. we never free this page. 5348 */ 5349 pool_setlowat(&pmap_pv_pool, 5350 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5351 5352 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5353 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5354 UVM_KMF_WIRED|UVM_KMF_ZERO); 5355 5356 pmap_initialized = true; 5357 } 5358 5359 static vaddr_t last_bootstrap_page = 0; 5360 static void *free_bootstrap_pages = NULL; 5361 5362 static void * 5363 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5364 { 5365 extern void *pool_page_alloc(struct pool *, int); 5366 vaddr_t new_page; 5367 void *rv; 5368 5369 if (pmap_initialized) 5370 return (pool_page_alloc(pp, flags)); 5371 5372 if (free_bootstrap_pages) { 5373 rv = free_bootstrap_pages; 5374 free_bootstrap_pages = *((void **)rv); 5375 return (rv); 5376 } 5377 5378 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5379 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5380 5381 KASSERT(new_page > last_bootstrap_page); 5382 last_bootstrap_page = new_page; 5383 return ((void *)new_page); 5384 } 5385 5386 static void 5387 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5388 { 5389 extern void pool_page_free(struct pool *, void *); 5390 5391 if ((vaddr_t)v <= last_bootstrap_page) { 5392 *((void **)v) = free_bootstrap_pages; 5393 free_bootstrap_pages = v; 5394 return; 5395 } 5396 5397 if (pmap_initialized) { 5398 pool_page_free(pp, v); 5399 return; 5400 } 5401 } 5402 5403 /* 5404 * pmap_postinit() 5405 * 5406 * This routine is called after the vm and kmem subsystems have been 5407 * initialised. This allows the pmap code to perform any initialisation 5408 * that can only be done one the memory allocation is in place. 5409 */ 5410 void 5411 pmap_postinit(void) 5412 { 5413 extern paddr_t physical_start, physical_end; 5414 struct l2_bucket *l2b; 5415 struct l1_ttable *l1; 5416 struct pglist plist; 5417 struct vm_page *m; 5418 pd_entry_t *pl1pt; 5419 pt_entry_t *ptep, pte; 5420 vaddr_t va, eva; 5421 u_int loop, needed; 5422 int error; 5423 5424 pool_cache_setlowat(&pmap_l2ptp_cache, 5425 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5426 pool_cache_setlowat(&pmap_l2dtable_cache, 5427 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5428 5429 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5430 needed -= 1; 5431 5432 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5433 5434 for (loop = 0; loop < needed; loop++, l1++) { 5435 /* Allocate a L1 page table */ 5436 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5437 if (va == 0) 5438 panic("Cannot allocate L1 KVM"); 5439 5440 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5441 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5442 if (error) 5443 panic("Cannot allocate L1 physical pages"); 5444 5445 m = TAILQ_FIRST(&plist); 5446 eva = va + L1_TABLE_SIZE; 5447 pl1pt = (pd_entry_t *)va; 5448 5449 while (m && va < eva) { 5450 paddr_t pa = VM_PAGE_TO_PHYS(m); 5451 5452 pmap_kenter_pa(va, pa, 5453 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); 5454 5455 /* 5456 * Make sure the L1 descriptor table is mapped 5457 * with the cache-mode set to write-through. 5458 */ 5459 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5460 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5461 pte = *ptep; 5462 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5463 *ptep = pte; 5464 PTE_SYNC(ptep); 5465 cpu_tlb_flushD_SE(va); 5466 5467 va += PAGE_SIZE; 5468 m = TAILQ_NEXT(m, pageq.queue); 5469 } 5470 5471 #ifdef DIAGNOSTIC 5472 if (m) 5473 panic("pmap_alloc_l1pt: pglist not empty"); 5474 #endif /* DIAGNOSTIC */ 5475 5476 pmap_init_l1(l1, pl1pt); 5477 } 5478 5479 #ifdef DEBUG 5480 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5481 needed); 5482 #endif 5483 } 5484 5485 /* 5486 * Note that the following routines are used by board-specific initialisation 5487 * code to configure the initial kernel page tables. 5488 * 5489 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5490 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5491 * behaviour of the old pmap, and provides an easy migration path for 5492 * initial bring-up of the new pmap on existing ports. Fortunately, 5493 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5494 * will be deprecated. 5495 * 5496 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5497 * tables. 5498 */ 5499 5500 /* 5501 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5502 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5503 * find them as necessary. 5504 * 5505 * Note that the data on this list MUST remain valid after initarm() returns, 5506 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5507 */ 5508 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5509 5510 static vaddr_t 5511 kernel_pt_lookup(paddr_t pa) 5512 { 5513 pv_addr_t *pv; 5514 5515 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5516 #ifndef ARM32_NEW_VM_LAYOUT 5517 if (pv->pv_pa == (pa & ~PGOFSET)) 5518 return (pv->pv_va | (pa & PGOFSET)); 5519 #else 5520 if (pv->pv_pa == pa) 5521 return (pv->pv_va); 5522 #endif 5523 } 5524 return (0); 5525 } 5526 5527 /* 5528 * pmap_map_section: 5529 * 5530 * Create a single section mapping. 5531 */ 5532 void 5533 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5534 { 5535 pd_entry_t *pde = (pd_entry_t *) l1pt; 5536 pd_entry_t fl; 5537 5538 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5539 5540 switch (cache) { 5541 case PTE_NOCACHE: 5542 default: 5543 fl = 0; 5544 break; 5545 5546 case PTE_CACHE: 5547 fl = pte_l1_s_cache_mode; 5548 break; 5549 5550 case PTE_PAGETABLE: 5551 fl = pte_l1_s_cache_mode_pt; 5552 break; 5553 } 5554 5555 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5556 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5557 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5558 } 5559 5560 /* 5561 * pmap_map_entry: 5562 * 5563 * Create a single page mapping. 5564 */ 5565 void 5566 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5567 { 5568 pd_entry_t *pde = (pd_entry_t *) l1pt; 5569 pt_entry_t fl; 5570 pt_entry_t *pte; 5571 5572 KASSERT(((va | pa) & PGOFSET) == 0); 5573 5574 switch (cache) { 5575 case PTE_NOCACHE: 5576 default: 5577 fl = 0; 5578 break; 5579 5580 case PTE_CACHE: 5581 fl = pte_l2_s_cache_mode; 5582 break; 5583 5584 case PTE_PAGETABLE: 5585 fl = pte_l2_s_cache_mode_pt; 5586 break; 5587 } 5588 5589 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5590 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5591 5592 #ifndef ARM32_NEW_VM_LAYOUT 5593 pte = (pt_entry_t *) 5594 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5595 #else 5596 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5597 #endif 5598 if (pte == NULL) 5599 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5600 5601 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5602 #ifndef ARM32_NEW_VM_LAYOUT 5603 pte += (va >> PGSHIFT) & 0x3ff; 5604 #else 5605 pte += l2pte_index(va); 5606 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5607 #endif 5608 *pte = fl; 5609 PTE_SYNC(pte); 5610 } 5611 5612 /* 5613 * pmap_link_l2pt: 5614 * 5615 * Link the L2 page table specified by "l2pv" into the L1 5616 * page table at the slot for "va". 5617 */ 5618 void 5619 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5620 { 5621 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5622 u_int slot = va >> L1_S_SHIFT; 5623 5624 #ifndef ARM32_NEW_VM_LAYOUT 5625 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5626 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5627 #endif 5628 5629 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5630 5631 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5632 #ifdef ARM32_NEW_VM_LAYOUT 5633 PTE_SYNC(&pde[slot]); 5634 #else 5635 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5636 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5637 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5638 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5639 #endif 5640 5641 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5642 } 5643 5644 /* 5645 * pmap_map_chunk: 5646 * 5647 * Map a chunk of memory using the most efficient mappings 5648 * possible (section, large page, small page) into the 5649 * provided L1 and L2 tables at the specified virtual address. 5650 */ 5651 vsize_t 5652 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5653 int prot, int cache) 5654 { 5655 pd_entry_t *pde = (pd_entry_t *) l1pt; 5656 pt_entry_t *pte, f1, f2s, f2l; 5657 vsize_t resid; 5658 int i; 5659 5660 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5661 5662 if (l1pt == 0) 5663 panic("pmap_map_chunk: no L1 table provided"); 5664 5665 #ifdef VERBOSE_INIT_ARM 5666 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5667 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5668 #endif 5669 5670 switch (cache) { 5671 case PTE_NOCACHE: 5672 default: 5673 f1 = 0; 5674 f2l = 0; 5675 f2s = 0; 5676 break; 5677 5678 case PTE_CACHE: 5679 f1 = pte_l1_s_cache_mode; 5680 f2l = pte_l2_l_cache_mode; 5681 f2s = pte_l2_s_cache_mode; 5682 break; 5683 5684 case PTE_PAGETABLE: 5685 f1 = pte_l1_s_cache_mode_pt; 5686 f2l = pte_l2_l_cache_mode_pt; 5687 f2s = pte_l2_s_cache_mode_pt; 5688 break; 5689 } 5690 5691 size = resid; 5692 5693 while (resid > 0) { 5694 /* See if we can use a section mapping. */ 5695 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5696 #ifdef VERBOSE_INIT_ARM 5697 printf("S"); 5698 #endif 5699 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5700 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5701 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5702 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5703 va += L1_S_SIZE; 5704 pa += L1_S_SIZE; 5705 resid -= L1_S_SIZE; 5706 continue; 5707 } 5708 5709 /* 5710 * Ok, we're going to use an L2 table. Make sure 5711 * one is actually in the corresponding L1 slot 5712 * for the current VA. 5713 */ 5714 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5715 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5716 5717 #ifndef ARM32_NEW_VM_LAYOUT 5718 pte = (pt_entry_t *) 5719 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5720 #else 5721 pte = (pt_entry_t *) kernel_pt_lookup( 5722 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5723 #endif 5724 if (pte == NULL) 5725 panic("pmap_map_chunk: can't find L2 table for VA" 5726 "0x%08lx", va); 5727 5728 /* See if we can use a L2 large page mapping. */ 5729 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5730 #ifdef VERBOSE_INIT_ARM 5731 printf("L"); 5732 #endif 5733 for (i = 0; i < 16; i++) { 5734 #ifndef ARM32_NEW_VM_LAYOUT 5735 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5736 L2_L_PROTO | pa | 5737 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5738 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5739 #else 5740 pte[l2pte_index(va) + i] = 5741 L2_L_PROTO | pa | 5742 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5743 PTE_SYNC(&pte[l2pte_index(va) + i]); 5744 #endif 5745 } 5746 va += L2_L_SIZE; 5747 pa += L2_L_SIZE; 5748 resid -= L2_L_SIZE; 5749 continue; 5750 } 5751 5752 /* Use a small page mapping. */ 5753 #ifdef VERBOSE_INIT_ARM 5754 printf("P"); 5755 #endif 5756 #ifndef ARM32_NEW_VM_LAYOUT 5757 pte[(va >> PGSHIFT) & 0x3ff] = 5758 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5759 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5760 #else 5761 pte[l2pte_index(va)] = 5762 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5763 PTE_SYNC(&pte[l2pte_index(va)]); 5764 #endif 5765 va += PAGE_SIZE; 5766 pa += PAGE_SIZE; 5767 resid -= PAGE_SIZE; 5768 } 5769 #ifdef VERBOSE_INIT_ARM 5770 printf("\n"); 5771 #endif 5772 return (size); 5773 } 5774 5775 /********************** Static device map routines ***************************/ 5776 5777 static const struct pmap_devmap *pmap_devmap_table; 5778 5779 /* 5780 * Register the devmap table. This is provided in case early console 5781 * initialization needs to register mappings created by bootstrap code 5782 * before pmap_devmap_bootstrap() is called. 5783 */ 5784 void 5785 pmap_devmap_register(const struct pmap_devmap *table) 5786 { 5787 5788 pmap_devmap_table = table; 5789 } 5790 5791 /* 5792 * Map all of the static regions in the devmap table, and remember 5793 * the devmap table so other parts of the kernel can look up entries 5794 * later. 5795 */ 5796 void 5797 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5798 { 5799 int i; 5800 5801 pmap_devmap_table = table; 5802 5803 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5804 #ifdef VERBOSE_INIT_ARM 5805 printf("devmap: %08lx -> %08lx @ %08lx\n", 5806 pmap_devmap_table[i].pd_pa, 5807 pmap_devmap_table[i].pd_pa + 5808 pmap_devmap_table[i].pd_size - 1, 5809 pmap_devmap_table[i].pd_va); 5810 #endif 5811 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5812 pmap_devmap_table[i].pd_pa, 5813 pmap_devmap_table[i].pd_size, 5814 pmap_devmap_table[i].pd_prot, 5815 pmap_devmap_table[i].pd_cache); 5816 } 5817 } 5818 5819 const struct pmap_devmap * 5820 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5821 { 5822 uint64_t endpa; 5823 int i; 5824 5825 if (pmap_devmap_table == NULL) 5826 return (NULL); 5827 5828 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5829 5830 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5831 if (pa >= pmap_devmap_table[i].pd_pa && 5832 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5833 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5834 return (&pmap_devmap_table[i]); 5835 } 5836 5837 return (NULL); 5838 } 5839 5840 const struct pmap_devmap * 5841 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5842 { 5843 int i; 5844 5845 if (pmap_devmap_table == NULL) 5846 return (NULL); 5847 5848 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5849 if (va >= pmap_devmap_table[i].pd_va && 5850 va + size - 1 <= pmap_devmap_table[i].pd_va + 5851 pmap_devmap_table[i].pd_size - 1) 5852 return (&pmap_devmap_table[i]); 5853 } 5854 5855 return (NULL); 5856 } 5857 5858 /********************** PTE initialization routines **************************/ 5859 5860 /* 5861 * These routines are called when the CPU type is identified to set up 5862 * the PTE prototypes, cache modes, etc. 5863 * 5864 * The variables are always here, just in case modules need to reference 5865 * them (though, they shouldn't). 5866 */ 5867 5868 pt_entry_t pte_l1_s_cache_mode; 5869 pt_entry_t pte_l1_s_cache_mode_pt; 5870 pt_entry_t pte_l1_s_cache_mask; 5871 5872 pt_entry_t pte_l2_l_cache_mode; 5873 pt_entry_t pte_l2_l_cache_mode_pt; 5874 pt_entry_t pte_l2_l_cache_mask; 5875 5876 pt_entry_t pte_l2_s_cache_mode; 5877 pt_entry_t pte_l2_s_cache_mode_pt; 5878 pt_entry_t pte_l2_s_cache_mask; 5879 5880 pt_entry_t pte_l2_s_prot_u; 5881 pt_entry_t pte_l2_s_prot_w; 5882 pt_entry_t pte_l2_s_prot_mask; 5883 5884 pt_entry_t pte_l1_s_proto; 5885 pt_entry_t pte_l1_c_proto; 5886 pt_entry_t pte_l2_s_proto; 5887 5888 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5889 void (*pmap_zero_page_func)(paddr_t); 5890 5891 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5892 void 5893 pmap_pte_init_generic(void) 5894 { 5895 5896 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5897 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5898 5899 pte_l2_l_cache_mode = L2_B|L2_C; 5900 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5901 5902 pte_l2_s_cache_mode = L2_B|L2_C; 5903 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5904 5905 /* 5906 * If we have a write-through cache, set B and C. If 5907 * we have a write-back cache, then we assume setting 5908 * only C will make those pages write-through. 5909 */ 5910 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5911 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5912 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5913 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5914 } else { 5915 #if ARM_MMU_V6 > 1 5916 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5917 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5918 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5919 #else 5920 pte_l1_s_cache_mode_pt = L1_S_C; 5921 pte_l2_l_cache_mode_pt = L2_C; 5922 pte_l2_s_cache_mode_pt = L2_C; 5923 #endif 5924 } 5925 5926 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5927 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5928 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5929 5930 pte_l1_s_proto = L1_S_PROTO_generic; 5931 pte_l1_c_proto = L1_C_PROTO_generic; 5932 pte_l2_s_proto = L2_S_PROTO_generic; 5933 5934 pmap_copy_page_func = pmap_copy_page_generic; 5935 pmap_zero_page_func = pmap_zero_page_generic; 5936 } 5937 5938 #if defined(CPU_ARM8) 5939 void 5940 pmap_pte_init_arm8(void) 5941 { 5942 5943 /* 5944 * ARM8 is compatible with generic, but we need to use 5945 * the page tables uncached. 5946 */ 5947 pmap_pte_init_generic(); 5948 5949 pte_l1_s_cache_mode_pt = 0; 5950 pte_l2_l_cache_mode_pt = 0; 5951 pte_l2_s_cache_mode_pt = 0; 5952 } 5953 #endif /* CPU_ARM8 */ 5954 5955 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5956 void 5957 pmap_pte_init_arm9(void) 5958 { 5959 5960 /* 5961 * ARM9 is compatible with generic, but we want to use 5962 * write-through caching for now. 5963 */ 5964 pmap_pte_init_generic(); 5965 5966 pte_l1_s_cache_mode = L1_S_C; 5967 pte_l2_l_cache_mode = L2_C; 5968 pte_l2_s_cache_mode = L2_C; 5969 5970 pte_l1_s_cache_mode_pt = L1_S_C; 5971 pte_l2_l_cache_mode_pt = L2_C; 5972 pte_l2_s_cache_mode_pt = L2_C; 5973 } 5974 #endif /* CPU_ARM9 */ 5975 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5976 5977 #if defined(CPU_ARM10) 5978 void 5979 pmap_pte_init_arm10(void) 5980 { 5981 5982 /* 5983 * ARM10 is compatible with generic, but we want to use 5984 * write-through caching for now. 5985 */ 5986 pmap_pte_init_generic(); 5987 5988 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 5989 pte_l2_l_cache_mode = L2_B | L2_C; 5990 pte_l2_s_cache_mode = L2_B | L2_C; 5991 5992 pte_l1_s_cache_mode_pt = L1_S_C; 5993 pte_l2_l_cache_mode_pt = L2_C; 5994 pte_l2_s_cache_mode_pt = L2_C; 5995 5996 } 5997 #endif /* CPU_ARM10 */ 5998 5999 #if ARM_MMU_SA1 == 1 6000 void 6001 pmap_pte_init_sa1(void) 6002 { 6003 6004 /* 6005 * The StrongARM SA-1 cache does not have a write-through 6006 * mode. So, do the generic initialization, then reset 6007 * the page table cache mode to B=1,C=1, and note that 6008 * the PTEs need to be sync'd. 6009 */ 6010 pmap_pte_init_generic(); 6011 6012 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6013 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6014 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6015 6016 pmap_needs_pte_sync = 1; 6017 } 6018 #endif /* ARM_MMU_SA1 == 1*/ 6019 6020 #if ARM_MMU_XSCALE == 1 6021 #if (ARM_NMMUS > 1) 6022 static u_int xscale_use_minidata; 6023 #endif 6024 6025 void 6026 pmap_pte_init_xscale(void) 6027 { 6028 uint32_t auxctl; 6029 int write_through = 0; 6030 6031 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6032 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6033 6034 pte_l2_l_cache_mode = L2_B|L2_C; 6035 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6036 6037 pte_l2_s_cache_mode = L2_B|L2_C; 6038 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6039 6040 pte_l1_s_cache_mode_pt = L1_S_C; 6041 pte_l2_l_cache_mode_pt = L2_C; 6042 pte_l2_s_cache_mode_pt = L2_C; 6043 6044 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6045 /* 6046 * The XScale core has an enhanced mode where writes that 6047 * miss the cache cause a cache line to be allocated. This 6048 * is significantly faster than the traditional, write-through 6049 * behavior of this case. 6050 */ 6051 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6052 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6053 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6054 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6055 6056 #ifdef XSCALE_CACHE_WRITE_THROUGH 6057 /* 6058 * Some versions of the XScale core have various bugs in 6059 * their cache units, the work-around for which is to run 6060 * the cache in write-through mode. Unfortunately, this 6061 * has a major (negative) impact on performance. So, we 6062 * go ahead and run fast-and-loose, in the hopes that we 6063 * don't line up the planets in a way that will trip the 6064 * bugs. 6065 * 6066 * However, we give you the option to be slow-but-correct. 6067 */ 6068 write_through = 1; 6069 #elif defined(XSCALE_CACHE_WRITE_BACK) 6070 /* force write back cache mode */ 6071 write_through = 0; 6072 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6073 /* 6074 * Intel PXA2[15]0 processors are known to have a bug in 6075 * write-back cache on revision 4 and earlier (stepping 6076 * A[01] and B[012]). Fixed for C0 and later. 6077 */ 6078 { 6079 uint32_t id, type; 6080 6081 id = cpufunc_id(); 6082 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6083 6084 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6085 if ((id & CPU_ID_REVISION_MASK) < 5) { 6086 /* write through for stepping A0-1 and B0-2 */ 6087 write_through = 1; 6088 } 6089 } 6090 } 6091 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6092 6093 if (write_through) { 6094 pte_l1_s_cache_mode = L1_S_C; 6095 pte_l2_l_cache_mode = L2_C; 6096 pte_l2_s_cache_mode = L2_C; 6097 } 6098 6099 #if (ARM_NMMUS > 1) 6100 xscale_use_minidata = 1; 6101 #endif 6102 6103 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6104 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6105 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6106 6107 pte_l1_s_proto = L1_S_PROTO_xscale; 6108 pte_l1_c_proto = L1_C_PROTO_xscale; 6109 pte_l2_s_proto = L2_S_PROTO_xscale; 6110 6111 pmap_copy_page_func = pmap_copy_page_xscale; 6112 pmap_zero_page_func = pmap_zero_page_xscale; 6113 6114 /* 6115 * Disable ECC protection of page table access, for now. 6116 */ 6117 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6118 auxctl &= ~XSCALE_AUXCTL_P; 6119 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6120 } 6121 6122 /* 6123 * xscale_setup_minidata: 6124 * 6125 * Set up the mini-data cache clean area. We require the 6126 * caller to allocate the right amount of physically and 6127 * virtually contiguous space. 6128 */ 6129 void 6130 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6131 { 6132 extern vaddr_t xscale_minidata_clean_addr; 6133 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6134 pd_entry_t *pde = (pd_entry_t *) l1pt; 6135 pt_entry_t *pte; 6136 vsize_t size; 6137 uint32_t auxctl; 6138 6139 xscale_minidata_clean_addr = va; 6140 6141 /* Round it to page size. */ 6142 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6143 6144 for (; size != 0; 6145 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6146 #ifndef ARM32_NEW_VM_LAYOUT 6147 pte = (pt_entry_t *) 6148 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6149 #else 6150 pte = (pt_entry_t *) kernel_pt_lookup( 6151 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6152 #endif 6153 if (pte == NULL) 6154 panic("xscale_setup_minidata: can't find L2 table for " 6155 "VA 0x%08lx", va); 6156 #ifndef ARM32_NEW_VM_LAYOUT 6157 pte[(va >> PGSHIFT) & 0x3ff] = 6158 #else 6159 pte[l2pte_index(va)] = 6160 #endif 6161 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6162 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6163 } 6164 6165 /* 6166 * Configure the mini-data cache for write-back with 6167 * read/write-allocate. 6168 * 6169 * NOTE: In order to reconfigure the mini-data cache, we must 6170 * make sure it contains no valid data! In order to do that, 6171 * we must issue a global data cache invalidate command! 6172 * 6173 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6174 * THIS IS VERY IMPORTANT! 6175 */ 6176 6177 /* Invalidate data and mini-data. */ 6178 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6179 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6180 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6181 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6182 } 6183 6184 /* 6185 * Change the PTEs for the specified kernel mappings such that they 6186 * will use the mini data cache instead of the main data cache. 6187 */ 6188 void 6189 pmap_uarea(vaddr_t va) 6190 { 6191 struct l2_bucket *l2b; 6192 pt_entry_t *ptep, *sptep, pte; 6193 vaddr_t next_bucket, eva; 6194 6195 #if (ARM_NMMUS > 1) 6196 if (xscale_use_minidata == 0) 6197 return; 6198 #endif 6199 6200 eva = va + USPACE; 6201 6202 while (va < eva) { 6203 next_bucket = L2_NEXT_BUCKET(va); 6204 if (next_bucket > eva) 6205 next_bucket = eva; 6206 6207 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6208 KDASSERT(l2b != NULL); 6209 6210 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6211 6212 while (va < next_bucket) { 6213 pte = *ptep; 6214 if (!l2pte_minidata(pte)) { 6215 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6216 cpu_tlb_flushD_SE(va); 6217 *ptep = pte & ~L2_B; 6218 } 6219 ptep++; 6220 va += PAGE_SIZE; 6221 } 6222 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6223 } 6224 cpu_cpwait(); 6225 } 6226 #endif /* ARM_MMU_XSCALE == 1 */ 6227 6228 /* 6229 * return the PA of the current L1 table, for use when handling a crash dump 6230 */ 6231 uint32_t pmap_kernel_L1_addr(void) 6232 { 6233 return pmap_kernel()->pm_l1->l1_physaddr; 6234 } 6235 6236 #if defined(DDB) 6237 /* 6238 * A couple of ddb-callable functions for dumping pmaps 6239 */ 6240 void pmap_dump_all(void); 6241 void pmap_dump(pmap_t); 6242 6243 void 6244 pmap_dump_all(void) 6245 { 6246 pmap_t pm; 6247 6248 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6249 if (pm == pmap_kernel()) 6250 continue; 6251 pmap_dump(pm); 6252 printf("\n"); 6253 } 6254 } 6255 6256 static pt_entry_t ncptes[64]; 6257 static void pmap_dump_ncpg(pmap_t); 6258 6259 void 6260 pmap_dump(pmap_t pm) 6261 { 6262 struct l2_dtable *l2; 6263 struct l2_bucket *l2b; 6264 pt_entry_t *ptep, pte; 6265 vaddr_t l2_va, l2b_va, va; 6266 int i, j, k, occ, rows = 0; 6267 6268 if (pm == pmap_kernel()) 6269 printf("pmap_kernel (%p): ", pm); 6270 else 6271 printf("user pmap (%p): ", pm); 6272 6273 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6274 6275 l2_va = 0; 6276 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6277 l2 = pm->pm_l2[i]; 6278 6279 if (l2 == NULL || l2->l2_occupancy == 0) 6280 continue; 6281 6282 l2b_va = l2_va; 6283 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6284 l2b = &l2->l2_bucket[j]; 6285 6286 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6287 continue; 6288 6289 ptep = l2b->l2b_kva; 6290 6291 for (k = 0; k < 256 && ptep[k] == 0; k++) 6292 ; 6293 6294 k &= ~63; 6295 occ = l2b->l2b_occupancy; 6296 va = l2b_va + (k * 4096); 6297 for (; k < 256; k++, va += 0x1000) { 6298 char ch = ' '; 6299 if ((k % 64) == 0) { 6300 if ((rows % 8) == 0) { 6301 printf( 6302 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6303 } 6304 printf("%08lx: ", va); 6305 } 6306 6307 ncptes[k & 63] = 0; 6308 pte = ptep[k]; 6309 if (pte == 0) { 6310 ch = '.'; 6311 } else { 6312 occ--; 6313 switch (pte & 0x0c) { 6314 case 0x00: 6315 ch = 'D'; /* No cache No buff */ 6316 break; 6317 case 0x04: 6318 ch = 'B'; /* No cache buff */ 6319 break; 6320 case 0x08: 6321 if (pte & 0x40) 6322 ch = 'm'; 6323 else 6324 ch = 'C'; /* Cache No buff */ 6325 break; 6326 case 0x0c: 6327 ch = 'F'; /* Cache Buff */ 6328 break; 6329 } 6330 6331 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6332 ch += 0x20; 6333 6334 if ((pte & 0xc) == 0) 6335 ncptes[k & 63] = pte; 6336 } 6337 6338 if ((k % 64) == 63) { 6339 rows++; 6340 printf("%c\n", ch); 6341 pmap_dump_ncpg(pm); 6342 if (occ == 0) 6343 break; 6344 } else 6345 printf("%c", ch); 6346 } 6347 } 6348 } 6349 } 6350 6351 static void 6352 pmap_dump_ncpg(pmap_t pm) 6353 { 6354 struct vm_page *pg; 6355 struct pv_entry *pv; 6356 int i; 6357 6358 for (i = 0; i < 63; i++) { 6359 if (ncptes[i] == 0) 6360 continue; 6361 6362 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6363 if (pg == NULL) 6364 continue; 6365 6366 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6367 VM_PAGE_TO_PHYS(pg), 6368 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 6369 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 6370 6371 SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) { 6372 printf(" %c va 0x%08lx, flags 0x%x\n", 6373 (pm == pv->pv_pmap) ? '*' : ' ', 6374 pv->pv_va, pv->pv_flags); 6375 } 6376 } 6377 } 6378 #endif 6379 6380 #ifdef PMAP_STEAL_MEMORY 6381 void 6382 pmap_boot_pageadd(pv_addr_t *newpv) 6383 { 6384 pv_addr_t *pv, *npv; 6385 6386 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6387 if (newpv->pv_pa < pv->pv_va) { 6388 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6389 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6390 newpv->pv_size += pv->pv_size; 6391 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6392 } 6393 pv = NULL; 6394 } else { 6395 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6396 pv = npv) { 6397 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6398 KASSERT(pv->pv_pa < newpv->pv_pa); 6399 if (newpv->pv_pa > npv->pv_pa) 6400 continue; 6401 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6402 pv->pv_size += newpv->pv_size; 6403 return; 6404 } 6405 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6406 break; 6407 newpv->pv_size += npv->pv_size; 6408 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6409 SLIST_REMOVE_AFTER(newpv, pv_list); 6410 return; 6411 } 6412 } 6413 } 6414 6415 if (pv) { 6416 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6417 } else { 6418 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6419 } 6420 } 6421 6422 void 6423 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6424 pv_addr_t *rpv) 6425 { 6426 pv_addr_t *pv, **pvp; 6427 struct vm_physseg *ps; 6428 size_t i; 6429 6430 KASSERT(amount & PGOFSET); 6431 KASSERT((mask & PGOFSET) == 0); 6432 KASSERT((match & PGOFSET) == 0); 6433 KASSERT(amount != 0); 6434 6435 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6436 (pv = *pvp) != NULL; 6437 pvp = &SLIST_NEXT(pv, pv_list)) { 6438 pv_addr_t *newpv; 6439 psize_t off; 6440 /* 6441 * If this entry is too small to satify the request... 6442 */ 6443 KASSERT(pv->pv_size > 0); 6444 if (pv->pv_size < amount) 6445 continue; 6446 6447 for (off = 0; off <= mask; off += PAGE_SIZE) { 6448 if (((pv->pv_pa + off) & mask) == match 6449 && off + amount <= pv->pv_size) 6450 break; 6451 } 6452 if (off > mask) 6453 continue; 6454 6455 rpv->pv_va = pv->pv_va + off; 6456 rpv->pv_pa = pv->pv_pa + off; 6457 rpv->pv_size = amount; 6458 pv->pv_size -= amount; 6459 if (pv->pv_size == 0) { 6460 KASSERT(off == 0); 6461 KASSERT((vaddr_t) pv == rpv->pv_va); 6462 *pvp = SLIST_NEXT(pv, pv_list); 6463 } else if (off == 0) { 6464 KASSERT((vaddr_t) pv == rpv->pv_va); 6465 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6466 *newpv = *pv; 6467 newpv->pv_pa += amount; 6468 newpv->pv_va += amount; 6469 *pvp = newpv; 6470 } else if (off < pv->pv_size) { 6471 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6472 *newpv = *pv; 6473 newpv->pv_size -= off; 6474 newpv->pv_pa += off + amount; 6475 newpv->pv_va += off + amount; 6476 6477 SLIST_NEXT(pv, pv_list) = newpv; 6478 pv->pv_size = off; 6479 } else { 6480 KASSERT((vaddr_t) pv != rpv->pv_va); 6481 } 6482 memset((void *)rpv->pv_va, 0, amount); 6483 return; 6484 } 6485 6486 if (vm_nphysseg == 0) 6487 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6488 6489 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6490 (pv = *pvp) != NULL; 6491 pvp = &SLIST_NEXT(pv, pv_list)) { 6492 if (SLIST_NEXT(pv, pv_list) == NULL) 6493 break; 6494 } 6495 KASSERT(mask == 0); 6496 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6497 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6498 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6499 rpv->pv_va = pv->pv_va; 6500 rpv->pv_pa = pv->pv_pa; 6501 rpv->pv_size = amount; 6502 *pvp = NULL; 6503 pmap_map_chunk(kernel_l1pt.pv_va, 6504 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6505 ptoa(ps->avail_start), 6506 amount - pv->pv_size, 6507 VM_PROT_READ|VM_PROT_WRITE, 6508 PTE_CACHE); 6509 ps->avail_start += atop(amount - pv->pv_size); 6510 /* 6511 * If we consumed the entire physseg, remove it. 6512 */ 6513 if (ps->avail_start == ps->avail_end) { 6514 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6515 ps[0] = ps[1]; 6516 } 6517 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6518 return; 6519 } 6520 } 6521 6522 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6523 } 6524 6525 vaddr_t 6526 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6527 { 6528 pv_addr_t pv; 6529 6530 pmap_boot_pagealloc(size, 0, 0, &pv); 6531 6532 return pv.pv_va; 6533 } 6534 #endif /* PMAP_STEAL_MEMORY */ 6535 6536 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6537 { 6538 sysctl_createv(clog, 0, NULL, NULL, 6539 CTLFLAG_PERMANENT, 6540 CTLTYPE_NODE, "machdep", NULL, 6541 NULL, 0, NULL, 0, 6542 CTL_MACHDEP, CTL_EOL); 6543 6544 sysctl_createv(clog, 0, NULL, NULL, 6545 CTLFLAG_PERMANENT, 6546 CTLTYPE_INT, "kmpages", 6547 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6548 NULL, 0, &pmap_kmpages, 0, 6549 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6550 } 6551
Indexes created Thu Sep 25 16:09:42 GMT 2025