pmap.c revision 1.211.2.13
1 /* $NetBSD: pmap.c,v 1.211.2.13 2010/05/31 13:26:36 uebayasi Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 #include "opt_direct_page.h" 195 #include "opt_xip.h" 196 197 #include <sys/param.h> 198 #include <sys/types.h> 199 #include <sys/kernel.h> 200 #include <sys/systm.h> 201 #include <sys/proc.h> 202 #include <sys/malloc.h> 203 #include <sys/pool.h> 204 #include <sys/cdefs.h> 205 #include <sys/cpu.h> 206 #include <sys/sysctl.h> 207 208 #include <uvm/uvm.h> 209 210 #include <machine/bus.h> 211 #include <machine/pmap.h> 212 #include <machine/pcb.h> 213 #include <machine/param.h> 214 #include <arm/arm32/katelib.h> 215 216 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.211.2.13 2010/05/31 13:26:36 uebayasi Exp $"); 217 218 #ifdef PMAP_DEBUG 219 220 /* XXX need to get rid of all refs to this */ 221 int pmap_debug_level = 0; 222 223 /* 224 * for switching to potentially finer grained debugging 225 */ 226 #define PDB_FOLLOW 0x0001 227 #define PDB_INIT 0x0002 228 #define PDB_ENTER 0x0004 229 #define PDB_REMOVE 0x0008 230 #define PDB_CREATE 0x0010 231 #define PDB_PTPAGE 0x0020 232 #define PDB_GROWKERN 0x0040 233 #define PDB_BITS 0x0080 234 #define PDB_COLLECT 0x0100 235 #define PDB_PROTECT 0x0200 236 #define PDB_MAP_L1 0x0400 237 #define PDB_BOOTSTRAP 0x1000 238 #define PDB_PARANOIA 0x2000 239 #define PDB_WIRING 0x4000 240 #define PDB_PVDUMP 0x8000 241 #define PDB_VAC 0x10000 242 #define PDB_KENTER 0x20000 243 #define PDB_KREMOVE 0x40000 244 #define PDB_EXEC 0x80000 245 246 int debugmap = 1; 247 int pmapdebug = 0; 248 #define NPDEBUG(_lev_,_stat_) \ 249 if (pmapdebug & (_lev_)) \ 250 ((_stat_)) 251 252 #else /* PMAP_DEBUG */ 253 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 254 #endif /* PMAP_DEBUG */ 255 256 /* 257 * pmap_kernel() points here 258 */ 259 static struct pmap kernel_pmap_store; 260 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 261 262 /* 263 * Which pmap is currently 'live' in the cache 264 * 265 * XXXSCW: Fix for SMP ... 266 */ 267 static pmap_t pmap_recent_user; 268 269 /* 270 * Pointer to last active lwp, or NULL if it exited. 271 */ 272 struct lwp *pmap_previous_active_lwp; 273 274 /* 275 * Pool and cache that pmap structures are allocated from. 276 * We use a cache to avoid clearing the pm_l2[] array (1KB) 277 * in pmap_create(). 278 */ 279 static struct pool_cache pmap_cache; 280 static LIST_HEAD(, pmap) pmap_pmaps; 281 282 /* 283 * Pool of PV structures 284 */ 285 static struct pool pmap_pv_pool; 286 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 287 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 288 static struct pool_allocator pmap_bootstrap_pv_allocator = { 289 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 290 }; 291 292 /* 293 * Pool and cache of l2_dtable structures. 294 * We use a cache to avoid clearing the structures when they're 295 * allocated. (196 bytes) 296 */ 297 static struct pool_cache pmap_l2dtable_cache; 298 static vaddr_t pmap_kernel_l2dtable_kva; 299 300 /* 301 * Pool and cache of L2 page descriptors. 302 * We use a cache to avoid clearing the descriptor table 303 * when they're allocated. (1KB) 304 */ 305 static struct pool_cache pmap_l2ptp_cache; 306 static vaddr_t pmap_kernel_l2ptp_kva; 307 static paddr_t pmap_kernel_l2ptp_phys; 308 309 #ifdef PMAPCOUNTERS 310 #define PMAP_EVCNT_INITIALIZER(name) \ 311 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 312 313 #ifdef PMAP_CACHE_VIPT 314 static struct evcnt pmap_ev_vac_clean_one = 315 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_one = 317 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_lots = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 320 static struct evcnt pmap_ev_vac_flush_lots2 = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 326 327 static struct evcnt pmap_ev_vac_color_new = 328 PMAP_EVCNT_INITIALIZER("new page color"); 329 static struct evcnt pmap_ev_vac_color_reuse = 330 PMAP_EVCNT_INITIALIZER("ok first page color"); 331 static struct evcnt pmap_ev_vac_color_ok = 332 PMAP_EVCNT_INITIALIZER("ok page color"); 333 static struct evcnt pmap_ev_vac_color_blind = 334 PMAP_EVCNT_INITIALIZER("blind page color"); 335 static struct evcnt pmap_ev_vac_color_change = 336 PMAP_EVCNT_INITIALIZER("change page color"); 337 static struct evcnt pmap_ev_vac_color_erase = 338 PMAP_EVCNT_INITIALIZER("erase page color"); 339 static struct evcnt pmap_ev_vac_color_none = 340 PMAP_EVCNT_INITIALIZER("no page color"); 341 static struct evcnt pmap_ev_vac_color_restore = 342 PMAP_EVCNT_INITIALIZER("restore page color"); 343 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 352 #endif 353 354 static struct evcnt pmap_ev_mappings = 355 PMAP_EVCNT_INITIALIZER("pages mapped"); 356 static struct evcnt pmap_ev_unmappings = 357 PMAP_EVCNT_INITIALIZER("pages unmapped"); 358 static struct evcnt pmap_ev_remappings = 359 PMAP_EVCNT_INITIALIZER("pages remapped"); 360 361 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 362 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 363 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 364 365 static struct evcnt pmap_ev_kernel_mappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 367 static struct evcnt pmap_ev_kernel_unmappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 369 static struct evcnt pmap_ev_kernel_remappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 371 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 373 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 375 376 static struct evcnt pmap_ev_kenter_mappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 378 static struct evcnt pmap_ev_kenter_unmappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 380 static struct evcnt pmap_ev_kenter_remappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 382 static struct evcnt pmap_ev_pt_mappings = 383 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 384 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 389 390 #ifdef PMAP_CACHE_VIPT 391 static struct evcnt pmap_ev_exec_mappings = 392 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 393 static struct evcnt pmap_ev_exec_cached = 394 PMAP_EVCNT_INITIALIZER("exec pages cached"); 395 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 397 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 398 399 static struct evcnt pmap_ev_exec_synced = 400 PMAP_EVCNT_INITIALIZER("exec pages synced"); 401 static struct evcnt pmap_ev_exec_synced_map = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 403 static struct evcnt pmap_ev_exec_synced_unmap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 405 static struct evcnt pmap_ev_exec_synced_remap = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 407 static struct evcnt pmap_ev_exec_synced_clearbit = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 409 static struct evcnt pmap_ev_exec_synced_kremove = 410 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 411 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 418 419 static struct evcnt pmap_ev_exec_discarded_unmap = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 421 static struct evcnt pmap_ev_exec_discarded_zero = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 423 static struct evcnt pmap_ev_exec_discarded_copy = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 425 static struct evcnt pmap_ev_exec_discarded_page_protect = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 427 static struct evcnt pmap_ev_exec_discarded_clearbit = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 429 static struct evcnt pmap_ev_exec_discarded_kremove = 430 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 431 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 438 #endif /* PMAP_CACHE_VIPT */ 439 440 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 441 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 442 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 443 444 EVCNT_ATTACH_STATIC(pmap_ev_updates); 445 EVCNT_ATTACH_STATIC(pmap_ev_collects); 446 EVCNT_ATTACH_STATIC(pmap_ev_activations); 447 448 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 449 #else 450 #define PMAPCOUNT(x) ((void)0) 451 #endif 452 453 /* 454 * pmap copy/zero page, and mem(5) hook point 455 */ 456 static pt_entry_t *csrc_pte, *cdst_pte; 457 static vaddr_t csrcp, cdstp; 458 vaddr_t memhook; /* used by mem.c */ 459 kmutex_t memlock; /* used by mem.c */ 460 void *zeropage; /* used by mem.c */ 461 extern void *msgbufaddr; 462 int pmap_kmpages; 463 /* 464 * Flag to indicate if pmap_init() has done its thing 465 */ 466 bool pmap_initialized; 467 468 /* 469 * Misc. locking data structures 470 */ 471 472 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 473 static struct lock pmap_main_lock; 474 475 #define PMAP_MAP_TO_HEAD_LOCK() \ 476 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 477 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 478 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 479 #define PMAP_HEAD_TO_MAP_LOCK() \ 480 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 481 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 482 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 483 #else 484 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 485 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 486 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 487 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 488 #endif 489 490 #define pmap_acquire_pmap_lock(pm) \ 491 do { \ 492 if ((pm) != pmap_kernel()) \ 493 mutex_enter(&(pm)->pm_lock); \ 494 } while (/*CONSTCOND*/0) 495 496 #define pmap_release_pmap_lock(pm) \ 497 do { \ 498 if ((pm) != pmap_kernel()) \ 499 mutex_exit(&(pm)->pm_lock); \ 500 } while (/*CONSTCOND*/0) 501 502 503 /* 504 * Metadata for L1 translation tables. 505 */ 506 struct l1_ttable { 507 /* Entry on the L1 Table list */ 508 SLIST_ENTRY(l1_ttable) l1_link; 509 510 /* Entry on the L1 Least Recently Used list */ 511 TAILQ_ENTRY(l1_ttable) l1_lru; 512 513 /* Track how many domains are allocated from this L1 */ 514 volatile u_int l1_domain_use_count; 515 516 /* 517 * A free-list of domain numbers for this L1. 518 * We avoid using ffs() and a bitmap to track domains since ffs() 519 * is slow on ARM. 520 */ 521 u_int8_t l1_domain_first; 522 u_int8_t l1_domain_free[PMAP_DOMAINS]; 523 524 /* Physical address of this L1 page table */ 525 paddr_t l1_physaddr; 526 527 /* KVA of this L1 page table */ 528 pd_entry_t *l1_kva; 529 }; 530 531 /* 532 * Convert a virtual address into its L1 table index. That is, the 533 * index used to locate the L2 descriptor table pointer in an L1 table. 534 * This is basically used to index l1->l1_kva[]. 535 * 536 * Each L2 descriptor table represents 1MB of VA space. 537 */ 538 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 539 540 /* 541 * L1 Page Tables are tracked using a Least Recently Used list. 542 * - New L1s are allocated from the HEAD. 543 * - Freed L1s are added to the TAIl. 544 * - Recently accessed L1s (where an 'access' is some change to one of 545 * the userland pmaps which owns this L1) are moved to the TAIL. 546 */ 547 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 548 static struct simplelock l1_lru_lock; 549 550 /* 551 * A list of all L1 tables 552 */ 553 static SLIST_HEAD(, l1_ttable) l1_list; 554 555 /* 556 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 557 * 558 * This is normally 16MB worth L2 page descriptors for any given pmap. 559 * Reference counts are maintained for L2 descriptors so they can be 560 * freed when empty. 561 */ 562 struct l2_dtable { 563 /* The number of L2 page descriptors allocated to this l2_dtable */ 564 u_int l2_occupancy; 565 566 /* List of L2 page descriptors */ 567 struct l2_bucket { 568 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 569 paddr_t l2b_phys; /* Physical address of same */ 570 u_short l2b_l1idx; /* This L2 table's L1 index */ 571 u_short l2b_occupancy; /* How many active descriptors */ 572 } l2_bucket[L2_BUCKET_SIZE]; 573 }; 574 575 /* 576 * Given an L1 table index, calculate the corresponding l2_dtable index 577 * and bucket index within the l2_dtable. 578 */ 579 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 580 (L2_SIZE - 1)) 581 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 582 583 /* 584 * Given a virtual address, this macro returns the 585 * virtual address required to drop into the next L2 bucket. 586 */ 587 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 588 589 /* 590 * L2 allocation. 591 */ 592 #define pmap_alloc_l2_dtable() \ 593 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 594 #define pmap_free_l2_dtable(l2) \ 595 pool_cache_put(&pmap_l2dtable_cache, (l2)) 596 #define pmap_alloc_l2_ptp(pap) \ 597 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 598 PR_NOWAIT, (pap))) 599 600 /* 601 * We try to map the page tables write-through, if possible. However, not 602 * all CPUs have a write-through cache mode, so on those we have to sync 603 * the cache when we frob page tables. 604 * 605 * We try to evaluate this at compile time, if possible. However, it's 606 * not always possible to do that, hence this run-time var. 607 */ 608 int pmap_needs_pte_sync; 609 610 /* 611 * Real definition of pv_entry. 612 */ 613 struct pv_entry { 614 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 615 pmap_t pv_pmap; /* pmap where mapping lies */ 616 vaddr_t pv_va; /* virtual address for mapping */ 617 u_int pv_flags; /* flags */ 618 }; 619 620 /* 621 * Macro to determine if a mapping might be resident in the 622 * instruction cache and/or TLB 623 */ 624 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 625 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 626 627 /* 628 * Macro to determine if a mapping might be resident in the 629 * data cache and/or TLB 630 */ 631 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 632 633 /* 634 * Local prototypes 635 */ 636 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 637 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 638 pt_entry_t **); 639 static bool pmap_is_current(pmap_t); 640 static bool pmap_is_cached(pmap_t); 641 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 642 pmap_t, vaddr_t, u_int); 643 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 644 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 645 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 646 u_int, u_int); 647 648 static void pmap_pinit(pmap_t); 649 static int pmap_pmap_ctor(void *, void *, int); 650 651 static void pmap_alloc_l1(pmap_t); 652 static void pmap_free_l1(pmap_t); 653 static void pmap_use_l1(pmap_t); 654 655 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 656 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 657 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 658 static int pmap_l2ptp_ctor(void *, void *, int); 659 static int pmap_l2dtable_ctor(void *, void *, int); 660 661 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 662 #ifdef PMAP_CACHE_VIVT 663 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 664 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 665 #endif 666 667 static void pmap_clearbit(struct vm_page *, u_int); 668 #ifdef PMAP_CACHE_VIVT 669 static int pmap_clean_page(struct pv_entry *, bool); 670 #endif 671 #ifdef PMAP_CACHE_VIPT 672 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 673 enum pmap_flush_op { 674 PMAP_FLUSH_PRIMARY, 675 PMAP_FLUSH_SECONDARY, 676 PMAP_CLEAN_PRIMARY 677 }; 678 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 679 #endif 680 static void pmap_page_remove(struct vm_page *); 681 682 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 683 static vaddr_t kernel_pt_lookup(paddr_t); 684 685 686 /* 687 * External function prototypes 688 */ 689 extern void bzero_page(vaddr_t); 690 extern void bcopy_page(vaddr_t, vaddr_t); 691 692 /* 693 * Misc variables 694 */ 695 vaddr_t virtual_avail; 696 vaddr_t virtual_end; 697 vaddr_t pmap_curmaxkvaddr; 698 699 paddr_t avail_start; 700 paddr_t avail_end; 701 702 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 703 pv_addr_t kernelpages; 704 pv_addr_t kernel_l1pt; 705 pv_addr_t systempage; 706 707 /* Function to set the debug level of the pmap code */ 708 709 #ifdef PMAP_DEBUG 710 void 711 pmap_debug(int level) 712 { 713 pmap_debug_level = level; 714 printf("pmap_debug: level=%d\n", pmap_debug_level); 715 } 716 #endif /* PMAP_DEBUG */ 717 718 /* 719 * A bunch of routines to conditionally flush the caches/TLB depending 720 * on whether the specified pmap actually needs to be flushed at any 721 * given time. 722 */ 723 static inline void 724 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 725 { 726 727 if (pm->pm_cstate.cs_tlb_id) 728 cpu_tlb_flushID_SE(va); 729 } 730 731 static inline void 732 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 733 { 734 735 if (pm->pm_cstate.cs_tlb_d) 736 cpu_tlb_flushD_SE(va); 737 } 738 739 static inline void 740 pmap_tlb_flushID(pmap_t pm) 741 { 742 743 if (pm->pm_cstate.cs_tlb_id) { 744 cpu_tlb_flushID(); 745 pm->pm_cstate.cs_tlb = 0; 746 } 747 } 748 749 static inline void 750 pmap_tlb_flushD(pmap_t pm) 751 { 752 753 if (pm->pm_cstate.cs_tlb_d) { 754 cpu_tlb_flushD(); 755 pm->pm_cstate.cs_tlb_d = 0; 756 } 757 } 758 759 #ifdef PMAP_CACHE_VIVT 760 static inline void 761 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 762 { 763 if (pm->pm_cstate.cs_cache_id) { 764 cpu_idcache_wbinv_range(va, len); 765 } 766 } 767 768 static inline void 769 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 770 bool do_inv, bool rd_only) 771 { 772 773 if (pm->pm_cstate.cs_cache_d) { 774 if (do_inv) { 775 if (rd_only) 776 cpu_dcache_inv_range(va, len); 777 else 778 cpu_dcache_wbinv_range(va, len); 779 } else 780 if (!rd_only) 781 cpu_dcache_wb_range(va, len); 782 } 783 } 784 785 static inline void 786 pmap_idcache_wbinv_all(pmap_t pm) 787 { 788 if (pm->pm_cstate.cs_cache_id) { 789 cpu_idcache_wbinv_all(); 790 pm->pm_cstate.cs_cache = 0; 791 } 792 } 793 794 static inline void 795 pmap_dcache_wbinv_all(pmap_t pm) 796 { 797 if (pm->pm_cstate.cs_cache_d) { 798 cpu_dcache_wbinv_all(); 799 pm->pm_cstate.cs_cache_d = 0; 800 } 801 } 802 #endif /* PMAP_CACHE_VIVT */ 803 804 static inline bool 805 pmap_is_current(pmap_t pm) 806 { 807 808 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 809 return true; 810 811 return false; 812 } 813 814 static inline bool 815 pmap_is_cached(pmap_t pm) 816 { 817 818 if (pm == pmap_kernel() || pmap_recent_user == NULL || 819 pmap_recent_user == pm) 820 return (true); 821 822 return false; 823 } 824 825 /* 826 * PTE_SYNC_CURRENT: 827 * 828 * Make sure the pte is written out to RAM. 829 * We need to do this for one of two cases: 830 * - We're dealing with the kernel pmap 831 * - There is no pmap active in the cache/tlb. 832 * - The specified pmap is 'active' in the cache/tlb. 833 */ 834 #ifdef PMAP_INCLUDE_PTE_SYNC 835 #define PTE_SYNC_CURRENT(pm, ptep) \ 836 do { \ 837 if (PMAP_NEEDS_PTE_SYNC && \ 838 pmap_is_cached(pm)) \ 839 PTE_SYNC(ptep); \ 840 } while (/*CONSTCOND*/0) 841 #else 842 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 843 #endif 844 845 /* 846 * main pv_entry manipulation functions: 847 * pmap_enter_pv: enter a mapping onto a vm_page list 848 * pmap_remove_pv: remove a mappiing from a vm_page list 849 * 850 * NOTE: pmap_enter_pv expects to lock the pvh itself 851 * pmap_remove_pv expects te caller to lock the pvh before calling 852 */ 853 854 /* 855 * pmap_enter_pv: enter a mapping onto a vm_page lst 856 * 857 * => caller should hold the proper lock on pmap_main_lock 858 * => caller should have pmap locked 859 * => we will gain the lock on the vm_page and allocate the new pv_entry 860 * => caller should adjust ptp's wire_count before calling 861 * => caller should not adjust pmap's wire_count 862 */ 863 static void 864 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 865 vaddr_t va, u_int flags) 866 { 867 struct pv_entry **pvp; 868 869 NPDEBUG(PDB_PVDUMP, 870 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 871 872 pv->pv_pmap = pm; 873 pv->pv_va = va; 874 pv->pv_flags = flags; 875 876 simple_lock(&md->pvh_slock); /* lock vm_page */ 877 pvp = &SLIST_FIRST(&md->pvh_list); 878 #ifdef PMAP_CACHE_VIPT 879 /* 880 * Insert unmanaged entries, writeable first, at the head of 881 * the pv list. 882 */ 883 if (__predict_true((flags & PVF_KENTRY) == 0)) { 884 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 885 pvp = &SLIST_NEXT(*pvp, pv_link); 886 } else if ((flags & PVF_WRITE) == 0) { 887 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 888 pvp = &SLIST_NEXT(*pvp, pv_link); 889 } 890 #endif 891 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 892 *pvp = pv; /* ... locked list */ 893 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 894 #ifdef PMAP_CACHE_VIPT 895 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 896 md->pvh_attrs |= PVF_KMOD; 897 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 898 md->pvh_attrs |= PVF_DIRTY; 899 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 900 #endif 901 if (pm == pmap_kernel()) { 902 PMAPCOUNT(kernel_mappings); 903 if (flags & PVF_WRITE) 904 md->krw_mappings++; 905 else 906 md->kro_mappings++; 907 } else { 908 if (flags & PVF_WRITE) 909 md->urw_mappings++; 910 else 911 md->uro_mappings++; 912 } 913 914 #ifdef PMAP_CACHE_VIPT 915 /* 916 * If this is an exec mapping and its the first exec mapping 917 * for this page, make sure to sync the I-cache. 918 */ 919 if (PV_IS_EXEC_P(flags)) { 920 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 921 pmap_syncicache_page(md, pa); 922 PMAPCOUNT(exec_synced_map); 923 } 924 PMAPCOUNT(exec_mappings); 925 } 926 #endif 927 928 PMAPCOUNT(mappings); 929 simple_unlock(&md->pvh_slock); /* unlock, done! */ 930 931 if (pv->pv_flags & PVF_WIRED) 932 ++pm->pm_stats.wired_count; 933 } 934 935 /* 936 * 937 * pmap_find_pv: Find a pv entry 938 * 939 * => caller should hold lock on vm_page 940 */ 941 static inline struct pv_entry * 942 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 943 { 944 struct pv_entry *pv; 945 946 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 947 if (pm == pv->pv_pmap && va == pv->pv_va) 948 break; 949 } 950 951 return (pv); 952 } 953 954 /* 955 * pmap_remove_pv: try to remove a mapping from a pv_list 956 * 957 * => caller should hold proper lock on pmap_main_lock 958 * => pmap should be locked 959 * => caller should hold lock on vm_page [so that attrs can be adjusted] 960 * => caller should adjust ptp's wire_count and free PTP if needed 961 * => caller should NOT adjust pmap's wire_count 962 * => we return the removed pv 963 */ 964 static struct pv_entry * 965 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 966 { 967 struct pv_entry *pv, **prevptr; 968 969 NPDEBUG(PDB_PVDUMP, 970 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 971 972 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 973 pv = *prevptr; 974 975 while (pv) { 976 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 977 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 978 "%p\n", pm, md)); 979 if (pv->pv_flags & PVF_WIRED) { 980 --pm->pm_stats.wired_count; 981 } 982 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 983 if (pm == pmap_kernel()) { 984 PMAPCOUNT(kernel_unmappings); 985 if (pv->pv_flags & PVF_WRITE) 986 md->krw_mappings--; 987 else 988 md->kro_mappings--; 989 } else { 990 if (pv->pv_flags & PVF_WRITE) 991 md->urw_mappings--; 992 else 993 md->uro_mappings--; 994 } 995 996 PMAPCOUNT(unmappings); 997 #ifdef PMAP_CACHE_VIPT 998 if (!(pv->pv_flags & PVF_WRITE)) 999 break; 1000 /* 1001 * If this page has had an exec mapping, then if 1002 * this was the last mapping, discard the contents, 1003 * otherwise sync the i-cache for this page. 1004 */ 1005 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1006 if (SLIST_EMPTY(&md->pvh_list)) { 1007 md->pvh_attrs &= ~PVF_EXEC; 1008 PMAPCOUNT(exec_discarded_unmap); 1009 } else { 1010 pmap_syncicache_page(md, pa); 1011 PMAPCOUNT(exec_synced_unmap); 1012 } 1013 } 1014 #endif /* PMAP_CACHE_VIPT */ 1015 break; 1016 } 1017 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1018 pv = *prevptr; /* advance */ 1019 } 1020 1021 #ifdef PMAP_CACHE_VIPT 1022 /* 1023 * If we no longer have a WRITEABLE KENTRY at the head of list, 1024 * clear the KMOD attribute from the page. 1025 */ 1026 if (SLIST_FIRST(&md->pvh_list) == NULL 1027 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1028 md->pvh_attrs &= ~PVF_KMOD; 1029 1030 /* 1031 * If this was a writeable page and there are no more writeable 1032 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1033 * the contents to memory. 1034 */ 1035 if (md->krw_mappings + md->urw_mappings == 0) 1036 md->pvh_attrs &= ~PVF_WRITE; 1037 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1038 #endif /* PMAP_CACHE_VIPT */ 1039 1040 return(pv); /* return removed pv */ 1041 } 1042 1043 /* 1044 * 1045 * pmap_modify_pv: Update pv flags 1046 * 1047 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1048 * => caller should NOT adjust pmap's wire_count 1049 * => caller must call pmap_vac_me_harder() if writable status of a page 1050 * may have changed. 1051 * => we return the old flags 1052 * 1053 * Modify a physical-virtual mapping in the pv table 1054 */ 1055 static u_int 1056 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1057 u_int clr_mask, u_int set_mask) 1058 { 1059 struct pv_entry *npv; 1060 u_int flags, oflags; 1061 1062 KASSERT((clr_mask & PVF_KENTRY) == 0); 1063 KASSERT((set_mask & PVF_KENTRY) == 0); 1064 1065 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1066 return (0); 1067 1068 NPDEBUG(PDB_PVDUMP, 1069 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1070 1071 /* 1072 * There is at least one VA mapping this page. 1073 */ 1074 1075 if (clr_mask & (PVF_REF | PVF_MOD)) { 1076 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1077 #ifdef PMAP_CACHE_VIPT 1078 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1079 md->pvh_attrs |= PVF_DIRTY; 1080 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1081 #endif 1082 } 1083 1084 oflags = npv->pv_flags; 1085 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1086 1087 if ((flags ^ oflags) & PVF_WIRED) { 1088 if (flags & PVF_WIRED) 1089 ++pm->pm_stats.wired_count; 1090 else 1091 --pm->pm_stats.wired_count; 1092 } 1093 1094 if ((flags ^ oflags) & PVF_WRITE) { 1095 if (pm == pmap_kernel()) { 1096 if (flags & PVF_WRITE) { 1097 md->krw_mappings++; 1098 md->kro_mappings--; 1099 } else { 1100 md->kro_mappings++; 1101 md->krw_mappings--; 1102 } 1103 } else { 1104 if (flags & PVF_WRITE) { 1105 md->urw_mappings++; 1106 md->uro_mappings--; 1107 } else { 1108 md->uro_mappings++; 1109 md->urw_mappings--; 1110 } 1111 } 1112 } 1113 #ifdef PMAP_CACHE_VIPT 1114 if (md->urw_mappings + md->krw_mappings == 0) 1115 md->pvh_attrs &= ~PVF_WRITE; 1116 /* 1117 * We have two cases here: the first is from enter_pv (new exec 1118 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1119 * Since in latter, pmap_enter_pv won't do anything, we just have 1120 * to do what pmap_remove_pv would do. 1121 */ 1122 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1123 || (PV_IS_EXEC_P(md->pvh_attrs) 1124 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1125 pmap_syncicache_page(md, pa); 1126 PMAPCOUNT(exec_synced_remap); 1127 } 1128 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1129 #endif 1130 1131 PMAPCOUNT(remappings); 1132 1133 return (oflags); 1134 } 1135 1136 /* 1137 * Allocate an L1 translation table for the specified pmap. 1138 * This is called at pmap creation time. 1139 */ 1140 static void 1141 pmap_alloc_l1(pmap_t pm) 1142 { 1143 struct l1_ttable *l1; 1144 u_int8_t domain; 1145 1146 /* 1147 * Remove the L1 at the head of the LRU list 1148 */ 1149 simple_lock(&l1_lru_lock); 1150 l1 = TAILQ_FIRST(&l1_lru_list); 1151 KDASSERT(l1 != NULL); 1152 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1153 1154 /* 1155 * Pick the first available domain number, and update 1156 * the link to the next number. 1157 */ 1158 domain = l1->l1_domain_first; 1159 l1->l1_domain_first = l1->l1_domain_free[domain]; 1160 1161 /* 1162 * If there are still free domain numbers in this L1, 1163 * put it back on the TAIL of the LRU list. 1164 */ 1165 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1166 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1167 1168 simple_unlock(&l1_lru_lock); 1169 1170 /* 1171 * Fix up the relevant bits in the pmap structure 1172 */ 1173 pm->pm_l1 = l1; 1174 pm->pm_domain = domain; 1175 } 1176 1177 /* 1178 * Free an L1 translation table. 1179 * This is called at pmap destruction time. 1180 */ 1181 static void 1182 pmap_free_l1(pmap_t pm) 1183 { 1184 struct l1_ttable *l1 = pm->pm_l1; 1185 1186 simple_lock(&l1_lru_lock); 1187 1188 /* 1189 * If this L1 is currently on the LRU list, remove it. 1190 */ 1191 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1192 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1193 1194 /* 1195 * Free up the domain number which was allocated to the pmap 1196 */ 1197 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1198 l1->l1_domain_first = pm->pm_domain; 1199 l1->l1_domain_use_count--; 1200 1201 /* 1202 * The L1 now must have at least 1 free domain, so add 1203 * it back to the LRU list. If the use count is zero, 1204 * put it at the head of the list, otherwise it goes 1205 * to the tail. 1206 */ 1207 if (l1->l1_domain_use_count == 0) 1208 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1209 else 1210 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1211 1212 simple_unlock(&l1_lru_lock); 1213 } 1214 1215 static inline void 1216 pmap_use_l1(pmap_t pm) 1217 { 1218 struct l1_ttable *l1; 1219 1220 /* 1221 * Do nothing if we're in interrupt context. 1222 * Access to an L1 by the kernel pmap must not affect 1223 * the LRU list. 1224 */ 1225 if (cpu_intr_p() || pm == pmap_kernel()) 1226 return; 1227 1228 l1 = pm->pm_l1; 1229 1230 /* 1231 * If the L1 is not currently on the LRU list, just return 1232 */ 1233 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1234 return; 1235 1236 simple_lock(&l1_lru_lock); 1237 1238 /* 1239 * Check the use count again, now that we've acquired the lock 1240 */ 1241 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1242 simple_unlock(&l1_lru_lock); 1243 return; 1244 } 1245 1246 /* 1247 * Move the L1 to the back of the LRU list 1248 */ 1249 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1250 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1251 1252 simple_unlock(&l1_lru_lock); 1253 } 1254 1255 /* 1256 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1257 * 1258 * Free an L2 descriptor table. 1259 */ 1260 static inline void 1261 #ifndef PMAP_INCLUDE_PTE_SYNC 1262 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1263 #else 1264 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1265 #endif 1266 { 1267 #ifdef PMAP_INCLUDE_PTE_SYNC 1268 #ifdef PMAP_CACHE_VIVT 1269 /* 1270 * Note: With a write-back cache, we may need to sync this 1271 * L2 table before re-using it. 1272 * This is because it may have belonged to a non-current 1273 * pmap, in which case the cache syncs would have been 1274 * skipped for the pages that were being unmapped. If the 1275 * L2 table were then to be immediately re-allocated to 1276 * the *current* pmap, it may well contain stale mappings 1277 * which have not yet been cleared by a cache write-back 1278 * and so would still be visible to the mmu. 1279 */ 1280 if (need_sync) 1281 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1282 #endif /* PMAP_CACHE_VIVT */ 1283 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1284 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1285 } 1286 1287 /* 1288 * Returns a pointer to the L2 bucket associated with the specified pmap 1289 * and VA, or NULL if no L2 bucket exists for the address. 1290 */ 1291 static inline struct l2_bucket * 1292 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1293 { 1294 struct l2_dtable *l2; 1295 struct l2_bucket *l2b; 1296 u_short l1idx; 1297 1298 l1idx = L1_IDX(va); 1299 1300 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1301 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1302 return (NULL); 1303 1304 return (l2b); 1305 } 1306 1307 /* 1308 * Returns a pointer to the L2 bucket associated with the specified pmap 1309 * and VA. 1310 * 1311 * If no L2 bucket exists, perform the necessary allocations to put an L2 1312 * bucket/page table in place. 1313 * 1314 * Note that if a new L2 bucket/page was allocated, the caller *must* 1315 * increment the bucket occupancy counter appropriately *before* 1316 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1317 * the bucket/page in the meantime. 1318 */ 1319 static struct l2_bucket * 1320 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1321 { 1322 struct l2_dtable *l2; 1323 struct l2_bucket *l2b; 1324 u_short l1idx; 1325 1326 l1idx = L1_IDX(va); 1327 1328 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1329 /* 1330 * No mapping at this address, as there is 1331 * no entry in the L1 table. 1332 * Need to allocate a new l2_dtable. 1333 */ 1334 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1335 return (NULL); 1336 1337 /* 1338 * Link it into the parent pmap 1339 */ 1340 pm->pm_l2[L2_IDX(l1idx)] = l2; 1341 } 1342 1343 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1344 1345 /* 1346 * Fetch pointer to the L2 page table associated with the address. 1347 */ 1348 if (l2b->l2b_kva == NULL) { 1349 pt_entry_t *ptep; 1350 1351 /* 1352 * No L2 page table has been allocated. Chances are, this 1353 * is because we just allocated the l2_dtable, above. 1354 */ 1355 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1356 /* 1357 * Oops, no more L2 page tables available at this 1358 * time. We may need to deallocate the l2_dtable 1359 * if we allocated a new one above. 1360 */ 1361 if (l2->l2_occupancy == 0) { 1362 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1363 pmap_free_l2_dtable(l2); 1364 } 1365 return (NULL); 1366 } 1367 1368 l2->l2_occupancy++; 1369 l2b->l2b_kva = ptep; 1370 l2b->l2b_l1idx = l1idx; 1371 } 1372 1373 return (l2b); 1374 } 1375 1376 /* 1377 * One or more mappings in the specified L2 descriptor table have just been 1378 * invalidated. 1379 * 1380 * Garbage collect the metadata and descriptor table itself if necessary. 1381 * 1382 * The pmap lock must be acquired when this is called (not necessary 1383 * for the kernel pmap). 1384 */ 1385 static void 1386 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1387 { 1388 struct l2_dtable *l2; 1389 pd_entry_t *pl1pd, l1pd; 1390 pt_entry_t *ptep; 1391 u_short l1idx; 1392 1393 KDASSERT(count <= l2b->l2b_occupancy); 1394 1395 /* 1396 * Update the bucket's reference count according to how many 1397 * PTEs the caller has just invalidated. 1398 */ 1399 l2b->l2b_occupancy -= count; 1400 1401 /* 1402 * Note: 1403 * 1404 * Level 2 page tables allocated to the kernel pmap are never freed 1405 * as that would require checking all Level 1 page tables and 1406 * removing any references to the Level 2 page table. See also the 1407 * comment elsewhere about never freeing bootstrap L2 descriptors. 1408 * 1409 * We make do with just invalidating the mapping in the L2 table. 1410 * 1411 * This isn't really a big deal in practice and, in fact, leads 1412 * to a performance win over time as we don't need to continually 1413 * alloc/free. 1414 */ 1415 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1416 return; 1417 1418 /* 1419 * There are no more valid mappings in this level 2 page table. 1420 * Go ahead and NULL-out the pointer in the bucket, then 1421 * free the page table. 1422 */ 1423 l1idx = l2b->l2b_l1idx; 1424 ptep = l2b->l2b_kva; 1425 l2b->l2b_kva = NULL; 1426 1427 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1428 1429 /* 1430 * If the L1 slot matches the pmap's domain 1431 * number, then invalidate it. 1432 */ 1433 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1434 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1435 *pl1pd = 0; 1436 PTE_SYNC(pl1pd); 1437 } 1438 1439 /* 1440 * Release the L2 descriptor table back to the pool cache. 1441 */ 1442 #ifndef PMAP_INCLUDE_PTE_SYNC 1443 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1444 #else 1445 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1446 #endif 1447 1448 /* 1449 * Update the reference count in the associated l2_dtable 1450 */ 1451 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1452 if (--l2->l2_occupancy > 0) 1453 return; 1454 1455 /* 1456 * There are no more valid mappings in any of the Level 1 1457 * slots managed by this l2_dtable. Go ahead and NULL-out 1458 * the pointer in the parent pmap and free the l2_dtable. 1459 */ 1460 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1461 pmap_free_l2_dtable(l2); 1462 } 1463 1464 /* 1465 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1466 * structures. 1467 */ 1468 static int 1469 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1470 { 1471 #ifndef PMAP_INCLUDE_PTE_SYNC 1472 struct l2_bucket *l2b; 1473 pt_entry_t *ptep, pte; 1474 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1475 1476 /* 1477 * The mappings for these page tables were initially made using 1478 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1479 * mode will not be right for page table mappings. To avoid 1480 * polluting the pmap_kenter_pa() code with a special case for 1481 * page tables, we simply fix up the cache-mode here if it's not 1482 * correct. 1483 */ 1484 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1485 KDASSERT(l2b != NULL); 1486 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1487 pte = *ptep; 1488 1489 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1490 /* 1491 * Page tables must have the cache-mode set to Write-Thru. 1492 */ 1493 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1494 PTE_SYNC(ptep); 1495 cpu_tlb_flushD_SE(va); 1496 cpu_cpwait(); 1497 } 1498 #endif 1499 1500 memset(v, 0, L2_TABLE_SIZE_REAL); 1501 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1502 return (0); 1503 } 1504 1505 static int 1506 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1507 { 1508 1509 memset(v, 0, sizeof(struct l2_dtable)); 1510 return (0); 1511 } 1512 1513 static int 1514 pmap_pmap_ctor(void *arg, void *v, int flags) 1515 { 1516 1517 memset(v, 0, sizeof(struct pmap)); 1518 return (0); 1519 } 1520 1521 static void 1522 pmap_pinit(pmap_t pm) 1523 { 1524 struct l2_bucket *l2b; 1525 1526 if (vector_page < KERNEL_BASE) { 1527 /* 1528 * Map the vector page. 1529 */ 1530 pmap_enter(pm, vector_page, systempage.pv_pa, 1531 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1532 pmap_update(pm); 1533 1534 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1535 l2b = pmap_get_l2_bucket(pm, vector_page); 1536 KDASSERT(l2b != NULL); 1537 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1538 L1_C_DOM(pm->pm_domain); 1539 } else 1540 pm->pm_pl1vec = NULL; 1541 } 1542 1543 #ifdef PMAP_CACHE_VIVT 1544 /* 1545 * Since we have a virtually indexed cache, we may need to inhibit caching if 1546 * there is more than one mapping and at least one of them is writable. 1547 * Since we purge the cache on every context switch, we only need to check for 1548 * other mappings within the same pmap, or kernel_pmap. 1549 * This function is also called when a page is unmapped, to possibly reenable 1550 * caching on any remaining mappings. 1551 * 1552 * The code implements the following logic, where: 1553 * 1554 * KW = # of kernel read/write pages 1555 * KR = # of kernel read only pages 1556 * UW = # of user read/write pages 1557 * UR = # of user read only pages 1558 * 1559 * KC = kernel mapping is cacheable 1560 * UC = user mapping is cacheable 1561 * 1562 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1563 * +--------------------------------------------- 1564 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1565 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1566 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1567 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1568 */ 1569 1570 static const int pmap_vac_flags[4][4] = { 1571 {-1, 0, 0, PVF_KNC}, 1572 {0, 0, PVF_NC, PVF_NC}, 1573 {0, PVF_NC, PVF_NC, PVF_NC}, 1574 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1575 }; 1576 1577 static inline int 1578 pmap_get_vac_flags(const struct vm_page_md *md) 1579 { 1580 int kidx, uidx; 1581 1582 kidx = 0; 1583 if (md->kro_mappings || md->krw_mappings > 1) 1584 kidx |= 1; 1585 if (md->krw_mappings) 1586 kidx |= 2; 1587 1588 uidx = 0; 1589 if (md->uro_mappings || md->urw_mappings > 1) 1590 uidx |= 1; 1591 if (md->urw_mappings) 1592 uidx |= 2; 1593 1594 return (pmap_vac_flags[uidx][kidx]); 1595 } 1596 1597 static inline void 1598 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1599 { 1600 int nattr; 1601 1602 nattr = pmap_get_vac_flags(md); 1603 1604 if (nattr < 0) { 1605 md->pvh_attrs &= ~PVF_NC; 1606 return; 1607 } 1608 1609 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1610 return; 1611 1612 if (pm == pmap_kernel()) 1613 pmap_vac_me_kpmap(md, pa, pm, va); 1614 else 1615 pmap_vac_me_user(md, pa, pm, va); 1616 1617 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1618 } 1619 1620 static void 1621 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1622 { 1623 u_int u_cacheable, u_entries; 1624 struct pv_entry *pv; 1625 pmap_t last_pmap = pm; 1626 1627 /* 1628 * Pass one, see if there are both kernel and user pmaps for 1629 * this page. Calculate whether there are user-writable or 1630 * kernel-writable pages. 1631 */ 1632 u_cacheable = 0; 1633 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1634 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1635 u_cacheable++; 1636 } 1637 1638 u_entries = md->urw_mappings + md->uro_mappings; 1639 1640 /* 1641 * We know we have just been updating a kernel entry, so if 1642 * all user pages are already cacheable, then there is nothing 1643 * further to do. 1644 */ 1645 if (md->k_mappings == 0 && u_cacheable == u_entries) 1646 return; 1647 1648 if (u_entries) { 1649 /* 1650 * Scan over the list again, for each entry, if it 1651 * might not be set correctly, call pmap_vac_me_user 1652 * to recalculate the settings. 1653 */ 1654 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1655 /* 1656 * We know kernel mappings will get set 1657 * correctly in other calls. We also know 1658 * that if the pmap is the same as last_pmap 1659 * then we've just handled this entry. 1660 */ 1661 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1662 continue; 1663 1664 /* 1665 * If there are kernel entries and this page 1666 * is writable but non-cacheable, then we can 1667 * skip this entry also. 1668 */ 1669 if (md->k_mappings && 1670 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1671 (PVF_NC | PVF_WRITE)) 1672 continue; 1673 1674 /* 1675 * Similarly if there are no kernel-writable 1676 * entries and the page is already 1677 * read-only/cacheable. 1678 */ 1679 if (md->krw_mappings == 0 && 1680 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1681 continue; 1682 1683 /* 1684 * For some of the remaining cases, we know 1685 * that we must recalculate, but for others we 1686 * can't tell if they are correct or not, so 1687 * we recalculate anyway. 1688 */ 1689 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1690 } 1691 1692 if (md->k_mappings == 0) 1693 return; 1694 } 1695 1696 pmap_vac_me_user(md, pa, pm, va); 1697 } 1698 1699 static void 1700 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1701 { 1702 pmap_t kpmap = pmap_kernel(); 1703 struct pv_entry *pv, *npv = NULL; 1704 struct l2_bucket *l2b; 1705 pt_entry_t *ptep, pte; 1706 u_int entries = 0; 1707 u_int writable = 0; 1708 u_int cacheable_entries = 0; 1709 u_int kern_cacheable = 0; 1710 u_int other_writable = 0; 1711 1712 /* 1713 * Count mappings and writable mappings in this pmap. 1714 * Include kernel mappings as part of our own. 1715 * Keep a pointer to the first one. 1716 */ 1717 npv = NULL; 1718 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1719 /* Count mappings in the same pmap */ 1720 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1721 if (entries++ == 0) 1722 npv = pv; 1723 1724 /* Cacheable mappings */ 1725 if ((pv->pv_flags & PVF_NC) == 0) { 1726 cacheable_entries++; 1727 if (kpmap == pv->pv_pmap) 1728 kern_cacheable++; 1729 } 1730 1731 /* Writable mappings */ 1732 if (pv->pv_flags & PVF_WRITE) 1733 ++writable; 1734 } else 1735 if (pv->pv_flags & PVF_WRITE) 1736 other_writable = 1; 1737 } 1738 1739 /* 1740 * Enable or disable caching as necessary. 1741 * Note: the first entry might be part of the kernel pmap, 1742 * so we can't assume this is indicative of the state of the 1743 * other (maybe non-kpmap) entries. 1744 */ 1745 if ((entries > 1 && writable) || 1746 (entries > 0 && pm == kpmap && other_writable)) { 1747 if (cacheable_entries == 0) 1748 return; 1749 1750 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1751 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1752 (pv->pv_flags & PVF_NC)) 1753 continue; 1754 1755 pv->pv_flags |= PVF_NC; 1756 1757 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1758 KDASSERT(l2b != NULL); 1759 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1760 pte = *ptep & ~L2_S_CACHE_MASK; 1761 1762 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1763 l2pte_valid(pte)) { 1764 if (PV_BEEN_EXECD(pv->pv_flags)) { 1765 #ifdef PMAP_CACHE_VIVT 1766 pmap_idcache_wbinv_range(pv->pv_pmap, 1767 pv->pv_va, PAGE_SIZE); 1768 #endif 1769 pmap_tlb_flushID_SE(pv->pv_pmap, 1770 pv->pv_va); 1771 } else 1772 if (PV_BEEN_REFD(pv->pv_flags)) { 1773 #ifdef PMAP_CACHE_VIVT 1774 pmap_dcache_wb_range(pv->pv_pmap, 1775 pv->pv_va, PAGE_SIZE, true, 1776 (pv->pv_flags & PVF_WRITE) == 0); 1777 #endif 1778 pmap_tlb_flushD_SE(pv->pv_pmap, 1779 pv->pv_va); 1780 } 1781 } 1782 1783 *ptep = pte; 1784 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1785 } 1786 cpu_cpwait(); 1787 } else 1788 if (entries > cacheable_entries) { 1789 /* 1790 * Turn cacheing back on for some pages. If it is a kernel 1791 * page, only do so if there are no other writable pages. 1792 */ 1793 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1794 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1795 (kpmap != pv->pv_pmap || other_writable))) 1796 continue; 1797 1798 pv->pv_flags &= ~PVF_NC; 1799 1800 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1801 KDASSERT(l2b != NULL); 1802 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1803 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1804 1805 if (l2pte_valid(pte)) { 1806 if (PV_BEEN_EXECD(pv->pv_flags)) { 1807 pmap_tlb_flushID_SE(pv->pv_pmap, 1808 pv->pv_va); 1809 } else 1810 if (PV_BEEN_REFD(pv->pv_flags)) { 1811 pmap_tlb_flushD_SE(pv->pv_pmap, 1812 pv->pv_va); 1813 } 1814 } 1815 1816 *ptep = pte; 1817 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1818 } 1819 } 1820 } 1821 #endif 1822 1823 #ifdef PMAP_CACHE_VIPT 1824 static void 1825 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1826 { 1827 struct pv_entry *pv; 1828 vaddr_t tst_mask; 1829 bool bad_alias; 1830 struct l2_bucket *l2b; 1831 pt_entry_t *ptep, pte, opte; 1832 const u_int 1833 rw_mappings = md->urw_mappings + md->krw_mappings, 1834 ro_mappings = md->uro_mappings + md->kro_mappings; 1835 1836 /* do we need to do anything? */ 1837 if (arm_cache_prefer_mask == 0) 1838 return; 1839 1840 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1841 md, pm, va)); 1842 1843 KASSERT(!va || pm); 1844 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1845 1846 /* Already a conflict? */ 1847 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1848 /* just an add, things are already non-cached */ 1849 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1850 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1851 bad_alias = false; 1852 if (va) { 1853 PMAPCOUNT(vac_color_none); 1854 bad_alias = true; 1855 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1856 goto fixup; 1857 } 1858 pv = SLIST_FIRST(&md->pvh_list); 1859 /* the list can't be empty because it would be cachable */ 1860 if (md->pvh_attrs & PVF_KMPAGE) { 1861 tst_mask = md->pvh_attrs; 1862 } else { 1863 KASSERT(pv); 1864 tst_mask = pv->pv_va; 1865 pv = SLIST_NEXT(pv, pv_link); 1866 } 1867 /* 1868 * Only check for a bad alias if we have writable mappings. 1869 */ 1870 tst_mask &= arm_cache_prefer_mask; 1871 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1872 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1873 /* if there's a bad alias, stop checking. */ 1874 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1875 bad_alias = true; 1876 } 1877 md->pvh_attrs |= PVF_WRITE; 1878 if (!bad_alias) 1879 md->pvh_attrs |= PVF_DIRTY; 1880 } else { 1881 /* 1882 * We have only read-only mappings. Let's see if there 1883 * are multiple colors in use or if we mapped a KMPAGE. 1884 * If the latter, we have a bad alias. If the former, 1885 * we need to remember that. 1886 */ 1887 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1888 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1889 if (md->pvh_attrs & PVF_KMPAGE) 1890 bad_alias = true; 1891 break; 1892 } 1893 } 1894 md->pvh_attrs &= ~PVF_WRITE; 1895 /* 1896 * No KMPAGE and we exited early, so we must have 1897 * multiple color mappings. 1898 */ 1899 if (!bad_alias && pv != NULL) 1900 md->pvh_attrs |= PVF_MULTCLR; 1901 } 1902 1903 /* If no conflicting colors, set everything back to cached */ 1904 if (!bad_alias) { 1905 #ifdef DEBUG 1906 if ((md->pvh_attrs & PVF_WRITE) 1907 || ro_mappings < 2) { 1908 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1909 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1910 } 1911 #endif 1912 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1913 md->pvh_attrs |= tst_mask | PVF_COLORED; 1914 /* 1915 * Restore DIRTY bit if page is modified 1916 */ 1917 if (md->pvh_attrs & PVF_DMOD) 1918 md->pvh_attrs |= PVF_DIRTY; 1919 PMAPCOUNT(vac_color_restore); 1920 } else { 1921 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1922 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1923 } 1924 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1925 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1926 } else if (!va) { 1927 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1928 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1929 || (md->pvh_attrs & PVF_DIRTY)); 1930 if (rw_mappings == 0) { 1931 md->pvh_attrs &= ~PVF_WRITE; 1932 if (ro_mappings == 1 1933 && (md->pvh_attrs & PVF_MULTCLR)) { 1934 /* 1935 * If this is the last readonly mapping 1936 * but it doesn't match the current color 1937 * for the page, change the current color 1938 * to match this last readonly mapping. 1939 */ 1940 pv = SLIST_FIRST(&md->pvh_list); 1941 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1942 & arm_cache_prefer_mask; 1943 if (tst_mask) { 1944 md->pvh_attrs ^= tst_mask; 1945 PMAPCOUNT(vac_color_change); 1946 } 1947 } 1948 } 1949 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1950 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1951 return; 1952 } else if (!pmap_is_page_colored_p(md)) { 1953 /* not colored so we just use its color */ 1954 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1955 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1956 PMAPCOUNT(vac_color_new); 1957 md->pvh_attrs &= PAGE_SIZE - 1; 1958 md->pvh_attrs |= PVF_COLORED 1959 | (va & arm_cache_prefer_mask) 1960 | (rw_mappings > 0 ? PVF_WRITE : 0); 1961 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1962 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1963 return; 1964 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1965 bad_alias = false; 1966 if (rw_mappings > 0) { 1967 /* 1968 * We now have writeable mappings and if we have 1969 * readonly mappings in more than once color, we have 1970 * an aliasing problem. Regardless mark the page as 1971 * writeable. 1972 */ 1973 if (md->pvh_attrs & PVF_MULTCLR) { 1974 if (ro_mappings < 2) { 1975 /* 1976 * If we only have less than two 1977 * read-only mappings, just flush the 1978 * non-primary colors from the cache. 1979 */ 1980 pmap_flush_page(md, pa, 1981 PMAP_FLUSH_SECONDARY); 1982 } else { 1983 bad_alias = true; 1984 } 1985 } 1986 md->pvh_attrs |= PVF_WRITE; 1987 } 1988 /* If no conflicting colors, set everything back to cached */ 1989 if (!bad_alias) { 1990 #ifdef DEBUG 1991 if (rw_mappings > 0 1992 || (md->pvh_attrs & PMAP_KMPAGE)) { 1993 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1994 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1995 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1996 } 1997 #endif 1998 if (SLIST_EMPTY(&md->pvh_list)) 1999 PMAPCOUNT(vac_color_reuse); 2000 else 2001 PMAPCOUNT(vac_color_ok); 2002 2003 /* matching color, just return */ 2004 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2005 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2006 return; 2007 } 2008 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2009 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2010 2011 /* color conflict. evict from cache. */ 2012 2013 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2014 md->pvh_attrs &= ~PVF_COLORED; 2015 md->pvh_attrs |= PVF_NC; 2016 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2017 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2018 PMAPCOUNT(vac_color_erase); 2019 } else if (rw_mappings == 0 2020 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2021 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2022 2023 /* 2024 * If the page has dirty cache lines, clean it. 2025 */ 2026 if (md->pvh_attrs & PVF_DIRTY) 2027 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2028 2029 /* 2030 * If this is the first remapping (we know that there are no 2031 * writeable mappings), then this is a simple color change. 2032 * Otherwise this is a seconary r/o mapping, which means 2033 * we don't have to do anything. 2034 */ 2035 if (ro_mappings == 1) { 2036 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2037 md->pvh_attrs &= PAGE_SIZE - 1; 2038 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2039 PMAPCOUNT(vac_color_change); 2040 } else { 2041 PMAPCOUNT(vac_color_blind); 2042 } 2043 md->pvh_attrs |= PVF_MULTCLR; 2044 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2045 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2046 return; 2047 } else { 2048 if (rw_mappings > 0) 2049 md->pvh_attrs |= PVF_WRITE; 2050 2051 /* color conflict. evict from cache. */ 2052 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2053 2054 /* the list can't be empty because this was a enter/modify */ 2055 pv = SLIST_FIRST(&md->pvh_list); 2056 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2057 KASSERT(pv); 2058 /* 2059 * If there's only one mapped page, change color to the 2060 * page's new color and return. Restore the DIRTY bit 2061 * that was erased by pmap_flush_page. 2062 */ 2063 if (SLIST_NEXT(pv, pv_link) == NULL) { 2064 md->pvh_attrs &= PAGE_SIZE - 1; 2065 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2066 if (md->pvh_attrs & PVF_DMOD) 2067 md->pvh_attrs |= PVF_DIRTY; 2068 PMAPCOUNT(vac_color_change); 2069 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2070 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2071 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2072 return; 2073 } 2074 } 2075 bad_alias = true; 2076 md->pvh_attrs &= ~PVF_COLORED; 2077 md->pvh_attrs |= PVF_NC; 2078 PMAPCOUNT(vac_color_erase); 2079 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2080 } 2081 2082 fixup: 2083 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2084 2085 /* 2086 * Turn cacheing on/off for all pages. 2087 */ 2088 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2089 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2090 KDASSERT(l2b != NULL); 2091 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2092 opte = *ptep; 2093 pte = opte & ~L2_S_CACHE_MASK; 2094 if (bad_alias) { 2095 pv->pv_flags |= PVF_NC; 2096 } else { 2097 pv->pv_flags &= ~PVF_NC; 2098 pte |= pte_l2_s_cache_mode; 2099 } 2100 2101 if (opte == pte) /* only update is there's a change */ 2102 continue; 2103 2104 if (l2pte_valid(pte)) { 2105 if (PV_BEEN_EXECD(pv->pv_flags)) { 2106 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2107 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2108 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2109 } 2110 } 2111 2112 *ptep = pte; 2113 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2114 } 2115 } 2116 #endif /* PMAP_CACHE_VIPT */ 2117 2118 2119 /* 2120 * Modify pte bits for all ptes corresponding to the given physical address. 2121 * We use `maskbits' rather than `clearbits' because we're always passing 2122 * constants and the latter would require an extra inversion at run-time. 2123 */ 2124 static void 2125 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2126 { 2127 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2128 struct l2_bucket *l2b; 2129 struct pv_entry *pv; 2130 pt_entry_t *ptep, npte, opte; 2131 pmap_t pm; 2132 vaddr_t va; 2133 u_int oflags; 2134 #ifdef PMAP_CACHE_VIPT 2135 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2136 bool need_syncicache = false; 2137 bool did_syncicache = false; 2138 bool need_vac_me_harder = false; 2139 #endif 2140 2141 NPDEBUG(PDB_BITS, 2142 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2143 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2144 2145 PMAP_HEAD_TO_MAP_LOCK(); 2146 simple_lock(&md->pvh_slock); 2147 2148 #ifdef PMAP_CACHE_VIPT 2149 /* 2150 * If we might want to sync the I-cache and we've modified it, 2151 * then we know we definitely need to sync or discard it. 2152 */ 2153 if (want_syncicache) 2154 need_syncicache = md->pvh_attrs & PVF_MOD; 2155 #endif 2156 /* 2157 * Clear saved attributes (modify, reference) 2158 */ 2159 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2160 2161 if (SLIST_EMPTY(&md->pvh_list)) { 2162 #ifdef PMAP_CACHE_VIPT 2163 if (need_syncicache) { 2164 /* 2165 * No one has it mapped, so just discard it. The next 2166 * exec remapping will cause it to be synced. 2167 */ 2168 md->pvh_attrs &= ~PVF_EXEC; 2169 PMAPCOUNT(exec_discarded_clearbit); 2170 } 2171 #endif 2172 simple_unlock(&md->pvh_slock); 2173 PMAP_HEAD_TO_MAP_UNLOCK(); 2174 return; 2175 } 2176 2177 /* 2178 * Loop over all current mappings setting/clearing as appropos 2179 */ 2180 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2181 va = pv->pv_va; 2182 pm = pv->pv_pmap; 2183 oflags = pv->pv_flags; 2184 /* 2185 * Kernel entries are unmanaged and as such not to be changed. 2186 */ 2187 if (oflags & PVF_KENTRY) 2188 continue; 2189 pv->pv_flags &= ~maskbits; 2190 2191 pmap_acquire_pmap_lock(pm); 2192 2193 l2b = pmap_get_l2_bucket(pm, va); 2194 KDASSERT(l2b != NULL); 2195 2196 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2197 npte = opte = *ptep; 2198 2199 NPDEBUG(PDB_BITS, 2200 printf( 2201 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2202 pv, pv->pv_pmap, pv->pv_va, oflags)); 2203 2204 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2205 #ifdef PMAP_CACHE_VIVT 2206 if ((pv->pv_flags & PVF_NC)) { 2207 /* 2208 * Entry is not cacheable: 2209 * 2210 * Don't turn caching on again if this is a 2211 * modified emulation. This would be 2212 * inconsitent with the settings created by 2213 * pmap_vac_me_harder(). Otherwise, it's safe 2214 * to re-enable cacheing. 2215 * 2216 * There's no need to call pmap_vac_me_harder() 2217 * here: all pages are losing their write 2218 * permission. 2219 */ 2220 if (maskbits & PVF_WRITE) { 2221 npte |= pte_l2_s_cache_mode; 2222 pv->pv_flags &= ~PVF_NC; 2223 } 2224 } else 2225 if (opte & L2_S_PROT_W) { 2226 /* 2227 * Entry is writable/cacheable: check if pmap 2228 * is current if it is flush it, otherwise it 2229 * won't be in the cache 2230 */ 2231 if (PV_BEEN_EXECD(oflags)) 2232 pmap_idcache_wbinv_range(pm, pv->pv_va, 2233 PAGE_SIZE); 2234 else 2235 if (PV_BEEN_REFD(oflags)) 2236 pmap_dcache_wb_range(pm, pv->pv_va, 2237 PAGE_SIZE, 2238 (maskbits & PVF_REF) != 0, false); 2239 } 2240 #endif 2241 2242 /* make the pte read only */ 2243 npte &= ~L2_S_PROT_W; 2244 2245 if (maskbits & oflags & PVF_WRITE) { 2246 /* 2247 * Keep alias accounting up to date 2248 */ 2249 if (pv->pv_pmap == pmap_kernel()) { 2250 md->krw_mappings--; 2251 md->kro_mappings++; 2252 } else { 2253 md->urw_mappings--; 2254 md->uro_mappings++; 2255 } 2256 #ifdef PMAP_CACHE_VIPT 2257 if (md->urw_mappings + md->krw_mappings == 0) 2258 md->pvh_attrs &= ~PVF_WRITE; 2259 if (want_syncicache) 2260 need_syncicache = true; 2261 need_vac_me_harder = true; 2262 #endif 2263 } 2264 } 2265 2266 if (maskbits & PVF_REF) { 2267 if ((pv->pv_flags & PVF_NC) == 0 && 2268 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2269 l2pte_valid(npte)) { 2270 #ifdef PMAP_CACHE_VIVT 2271 /* 2272 * Check npte here; we may have already 2273 * done the wbinv above, and the validity 2274 * of the PTE is the same for opte and 2275 * npte. 2276 */ 2277 /* XXXJRT need idcache_inv_range */ 2278 if (PV_BEEN_EXECD(oflags)) 2279 pmap_idcache_wbinv_range(pm, 2280 pv->pv_va, PAGE_SIZE); 2281 else 2282 if (PV_BEEN_REFD(oflags)) 2283 pmap_dcache_wb_range(pm, 2284 pv->pv_va, PAGE_SIZE, 2285 true, true); 2286 #endif 2287 } 2288 2289 /* 2290 * Make the PTE invalid so that we will take a 2291 * page fault the next time the mapping is 2292 * referenced. 2293 */ 2294 npte &= ~L2_TYPE_MASK; 2295 npte |= L2_TYPE_INV; 2296 } 2297 2298 if (npte != opte) { 2299 *ptep = npte; 2300 PTE_SYNC(ptep); 2301 /* Flush the TLB entry if a current pmap. */ 2302 if (PV_BEEN_EXECD(oflags)) 2303 pmap_tlb_flushID_SE(pm, pv->pv_va); 2304 else 2305 if (PV_BEEN_REFD(oflags)) 2306 pmap_tlb_flushD_SE(pm, pv->pv_va); 2307 } 2308 2309 pmap_release_pmap_lock(pm); 2310 2311 NPDEBUG(PDB_BITS, 2312 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2313 pm, va, opte, npte)); 2314 } 2315 2316 #ifdef PMAP_CACHE_VIPT 2317 /* 2318 * If we need to sync the I-cache and we haven't done it yet, do it. 2319 */ 2320 if (need_syncicache && !did_syncicache) { 2321 pmap_syncicache_page(md, VM_PAGE_TO_PHYS(pg)); 2322 PMAPCOUNT(exec_synced_clearbit); 2323 } 2324 /* 2325 * If we are changing this to read-only, we need to call vac_me_harder 2326 * so we can change all the read-only pages to cacheable. We pretend 2327 * this as a page deletion. 2328 */ 2329 if (need_vac_me_harder) { 2330 if (md->pvh_attrs & PVF_NC) 2331 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), NULL, 0); 2332 } 2333 #endif 2334 2335 simple_unlock(&md->pvh_slock); 2336 PMAP_HEAD_TO_MAP_UNLOCK(); 2337 } 2338 2339 /* 2340 * pmap_clean_page() 2341 * 2342 * This is a local function used to work out the best strategy to clean 2343 * a single page referenced by its entry in the PV table. It's used by 2344 * pmap_copy_page, pmap_zero page and maybe some others later on. 2345 * 2346 * Its policy is effectively: 2347 * o If there are no mappings, we don't bother doing anything with the cache. 2348 * o If there is one mapping, we clean just that page. 2349 * o If there are multiple mappings, we clean the entire cache. 2350 * 2351 * So that some functions can be further optimised, it returns 0 if it didn't 2352 * clean the entire cache, or 1 if it did. 2353 * 2354 * XXX One bug in this routine is that if the pv_entry has a single page 2355 * mapped at 0x00000000 a whole cache clean will be performed rather than 2356 * just the 1 page. Since this should not occur in everyday use and if it does 2357 * it will just result in not the most efficient clean for the page. 2358 */ 2359 #ifdef PMAP_CACHE_VIVT 2360 static int 2361 pmap_clean_page(struct pv_entry *pv, bool is_src) 2362 { 2363 pmap_t pm_to_clean = NULL; 2364 struct pv_entry *npv; 2365 u_int cache_needs_cleaning = 0; 2366 u_int flags = 0; 2367 vaddr_t page_to_clean = 0; 2368 2369 if (pv == NULL) { 2370 /* nothing mapped in so nothing to flush */ 2371 return (0); 2372 } 2373 2374 /* 2375 * Since we flush the cache each time we change to a different 2376 * user vmspace, we only need to flush the page if it is in the 2377 * current pmap. 2378 */ 2379 2380 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2381 if (pmap_is_current(npv->pv_pmap)) { 2382 flags |= npv->pv_flags; 2383 /* 2384 * The page is mapped non-cacheable in 2385 * this map. No need to flush the cache. 2386 */ 2387 if (npv->pv_flags & PVF_NC) { 2388 #ifdef DIAGNOSTIC 2389 if (cache_needs_cleaning) 2390 panic("pmap_clean_page: " 2391 "cache inconsistency"); 2392 #endif 2393 break; 2394 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2395 continue; 2396 if (cache_needs_cleaning) { 2397 page_to_clean = 0; 2398 break; 2399 } else { 2400 page_to_clean = npv->pv_va; 2401 pm_to_clean = npv->pv_pmap; 2402 } 2403 cache_needs_cleaning = 1; 2404 } 2405 } 2406 2407 if (page_to_clean) { 2408 if (PV_BEEN_EXECD(flags)) 2409 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2410 PAGE_SIZE); 2411 else 2412 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2413 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2414 } else if (cache_needs_cleaning) { 2415 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2416 2417 if (PV_BEEN_EXECD(flags)) 2418 pmap_idcache_wbinv_all(pm); 2419 else 2420 pmap_dcache_wbinv_all(pm); 2421 return (1); 2422 } 2423 return (0); 2424 } 2425 #endif 2426 2427 #ifdef PMAP_CACHE_VIPT 2428 /* 2429 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2430 * right cache alias to make sure we flush the right stuff. 2431 */ 2432 void 2433 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2434 { 2435 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2436 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2437 2438 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2439 md, md->pvh_attrs)); 2440 /* 2441 * No need to clean the page if it's non-cached. 2442 */ 2443 if (md->pvh_attrs & PVF_NC) 2444 return; 2445 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2446 2447 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2448 /* 2449 * Set up a PTE with the right coloring to flush existing cache lines. 2450 */ 2451 *ptep = L2_S_PROTO | 2452 pa 2453 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2454 | pte_l2_s_cache_mode; 2455 PTE_SYNC(ptep); 2456 2457 /* 2458 * Flush it. 2459 */ 2460 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2461 /* 2462 * Unmap the page. 2463 */ 2464 *ptep = 0; 2465 PTE_SYNC(ptep); 2466 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2467 2468 md->pvh_attrs |= PVF_EXEC; 2469 PMAPCOUNT(exec_synced); 2470 } 2471 2472 void 2473 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2474 { 2475 vsize_t va_offset, end_va; 2476 void (*cf)(vaddr_t, vsize_t); 2477 2478 if (arm_cache_prefer_mask == 0) 2479 return; 2480 2481 switch (flush) { 2482 case PMAP_FLUSH_PRIMARY: 2483 if (md->pvh_attrs & PVF_MULTCLR) { 2484 va_offset = 0; 2485 end_va = arm_cache_prefer_mask; 2486 md->pvh_attrs &= ~PVF_MULTCLR; 2487 PMAPCOUNT(vac_flush_lots); 2488 } else { 2489 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2490 end_va = va_offset; 2491 PMAPCOUNT(vac_flush_one); 2492 } 2493 /* 2494 * Mark that the page is no longer dirty. 2495 */ 2496 md->pvh_attrs &= ~PVF_DIRTY; 2497 cf = cpufuncs.cf_idcache_wbinv_range; 2498 break; 2499 case PMAP_FLUSH_SECONDARY: 2500 va_offset = 0; 2501 end_va = arm_cache_prefer_mask; 2502 cf = cpufuncs.cf_idcache_wbinv_range; 2503 md->pvh_attrs &= ~PVF_MULTCLR; 2504 PMAPCOUNT(vac_flush_lots); 2505 break; 2506 case PMAP_CLEAN_PRIMARY: 2507 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2508 end_va = va_offset; 2509 cf = cpufuncs.cf_dcache_wb_range; 2510 /* 2511 * Mark that the page is no longer dirty. 2512 */ 2513 if ((md->pvh_attrs & PVF_DMOD) == 0) 2514 md->pvh_attrs &= ~PVF_DIRTY; 2515 PMAPCOUNT(vac_clean_one); 2516 break; 2517 default: 2518 return; 2519 } 2520 2521 KASSERT(!(md->pvh_attrs & PVF_NC)); 2522 2523 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2524 md, md->pvh_attrs)); 2525 2526 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2527 const size_t pte_offset = va_offset >> PGSHIFT; 2528 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2529 const pt_entry_t oldpte = *ptep; 2530 2531 if (flush == PMAP_FLUSH_SECONDARY 2532 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2533 continue; 2534 2535 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2536 /* 2537 * Set up a PTE with the right coloring to flush 2538 * existing cache entries. 2539 */ 2540 *ptep = L2_S_PROTO 2541 | pa 2542 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2543 | pte_l2_s_cache_mode; 2544 PTE_SYNC(ptep); 2545 2546 /* 2547 * Flush it. 2548 */ 2549 (*cf)(cdstp + va_offset, PAGE_SIZE); 2550 2551 /* 2552 * Restore the page table entry since we might have interrupted 2553 * pmap_zero_page or pmap_copy_page which was already using 2554 * this pte. 2555 */ 2556 *ptep = oldpte; 2557 PTE_SYNC(ptep); 2558 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2559 } 2560 } 2561 #endif /* PMAP_CACHE_VIPT */ 2562 2563 /* 2564 * Routine: pmap_page_remove 2565 * Function: 2566 * Removes this physical page from 2567 * all physical maps in which it resides. 2568 * Reflects back modify bits to the pager. 2569 */ 2570 static void 2571 pmap_page_remove(struct vm_page *pg) 2572 { 2573 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2574 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2575 struct l2_bucket *l2b; 2576 struct pv_entry *pv, *npv, **pvp; 2577 pmap_t pm; 2578 pt_entry_t *ptep; 2579 bool flush; 2580 u_int flags; 2581 2582 NPDEBUG(PDB_FOLLOW, 2583 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2584 pa)); 2585 2586 PMAP_HEAD_TO_MAP_LOCK(); 2587 simple_lock(&md->pvh_slock); 2588 2589 pv = SLIST_FIRST(&md->pvh_list); 2590 if (pv == NULL) { 2591 #ifdef PMAP_CACHE_VIPT 2592 /* 2593 * We *know* the page contents are about to be replaced. 2594 * Discard the exec contents 2595 */ 2596 if (PV_IS_EXEC_P(md->pvh_attrs)) 2597 PMAPCOUNT(exec_discarded_page_protect); 2598 md->pvh_attrs &= ~PVF_EXEC; 2599 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2600 #endif 2601 simple_unlock(&md->pvh_slock); 2602 PMAP_HEAD_TO_MAP_UNLOCK(); 2603 return; 2604 } 2605 #ifdef PMAP_CACHE_VIPT 2606 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2607 #endif 2608 2609 /* 2610 * Clear alias counts 2611 */ 2612 #ifdef PMAP_CACHE_VIVT 2613 md->k_mappings = 0; 2614 #endif 2615 md->urw_mappings = md->uro_mappings = 0; 2616 2617 flush = false; 2618 flags = 0; 2619 2620 #ifdef PMAP_CACHE_VIVT 2621 pmap_clean_page(pv, false); 2622 #endif 2623 2624 pvp = &SLIST_FIRST(&md->pvh_list); 2625 while (pv) { 2626 pm = pv->pv_pmap; 2627 npv = SLIST_NEXT(pv, pv_link); 2628 if (flush == false && pmap_is_current(pm)) 2629 flush = true; 2630 2631 if (pm == pmap_kernel()) { 2632 #ifdef PMAP_CACHE_VIPT 2633 /* 2634 * If this was unmanaged mapping, it must be preserved. 2635 * Move it back on the list and advance the end-of-list 2636 * pointer. 2637 */ 2638 if (pv->pv_flags & PVF_KENTRY) { 2639 *pvp = pv; 2640 pvp = &SLIST_NEXT(pv, pv_link); 2641 pv = npv; 2642 continue; 2643 } 2644 if (pv->pv_flags & PVF_WRITE) 2645 md->krw_mappings--; 2646 else 2647 md->kro_mappings--; 2648 #endif 2649 PMAPCOUNT(kernel_unmappings); 2650 } 2651 PMAPCOUNT(unmappings); 2652 2653 pmap_acquire_pmap_lock(pm); 2654 2655 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2656 KDASSERT(l2b != NULL); 2657 2658 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2659 2660 /* 2661 * Update statistics 2662 */ 2663 --pm->pm_stats.resident_count; 2664 2665 /* Wired bit */ 2666 if (pv->pv_flags & PVF_WIRED) 2667 --pm->pm_stats.wired_count; 2668 2669 flags |= pv->pv_flags; 2670 2671 /* 2672 * Invalidate the PTEs. 2673 */ 2674 *ptep = 0; 2675 PTE_SYNC_CURRENT(pm, ptep); 2676 pmap_free_l2_bucket(pm, l2b, 1); 2677 2678 pool_put(&pmap_pv_pool, pv); 2679 pv = npv; 2680 /* 2681 * if we reach the end of the list and there are still 2682 * mappings, they might be able to be cached now. 2683 */ 2684 if (pv == NULL) { 2685 *pvp = NULL; 2686 if (!SLIST_EMPTY(&md->pvh_list)) 2687 pmap_vac_me_harder(md, pa, pm, 0); 2688 } 2689 pmap_release_pmap_lock(pm); 2690 } 2691 #ifdef PMAP_CACHE_VIPT 2692 /* 2693 * Its EXEC cache is now gone. 2694 */ 2695 if (PV_IS_EXEC_P(md->pvh_attrs)) 2696 PMAPCOUNT(exec_discarded_page_protect); 2697 md->pvh_attrs &= ~PVF_EXEC; 2698 KASSERT(md->urw_mappings == 0); 2699 KASSERT(md->uro_mappings == 0); 2700 if (md->krw_mappings == 0) 2701 md->pvh_attrs &= ~PVF_WRITE; 2702 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2703 #endif 2704 simple_unlock(&md->pvh_slock); 2705 PMAP_HEAD_TO_MAP_UNLOCK(); 2706 2707 if (flush) { 2708 /* 2709 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2710 * would need a subsequent call to pmap_update() to ensure 2711 * curpm->pm_cstate.cs_all is reset. Our callers are not 2712 * required to do that (see pmap(9)), so we can't modify 2713 * the current pmap's state. 2714 */ 2715 if (PV_BEEN_EXECD(flags)) 2716 cpu_tlb_flushID(); 2717 else 2718 cpu_tlb_flushD(); 2719 } 2720 cpu_cpwait(); 2721 } 2722 2723 /* 2724 * pmap_t pmap_create(void) 2725 * 2726 * Create a new pmap structure from scratch. 2727 */ 2728 pmap_t 2729 pmap_create(void) 2730 { 2731 pmap_t pm; 2732 2733 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2734 2735 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2736 pm->pm_stats.wired_count = 0; 2737 pm->pm_stats.resident_count = 1; 2738 pm->pm_cstate.cs_all = 0; 2739 pmap_alloc_l1(pm); 2740 2741 /* 2742 * Note: The pool cache ensures that the pm_l2[] array is already 2743 * initialised to zero. 2744 */ 2745 2746 pmap_pinit(pm); 2747 2748 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2749 2750 return (pm); 2751 } 2752 2753 /* 2754 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2755 * u_int flags) 2756 * 2757 * Insert the given physical page (p) at 2758 * the specified virtual address (v) in the 2759 * target physical map with the protection requested. 2760 * 2761 * NB: This is the only routine which MAY NOT lazy-evaluate 2762 * or lose information. That is, this routine must actually 2763 * insert this page into the given map NOW. 2764 */ 2765 int 2766 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2767 { 2768 struct l2_bucket *l2b; 2769 struct vm_page *pg, *opg; 2770 struct pv_entry *pv; 2771 pt_entry_t *ptep, npte, opte; 2772 u_int nflags; 2773 u_int oflags; 2774 2775 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2776 2777 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2778 KDASSERT(((va | pa) & PGOFSET) == 0); 2779 2780 /* 2781 * Get a pointer to the page. Later on in this function, we 2782 * test for a managed page by checking pg != NULL. 2783 */ 2784 pg = (pmap_initialized && ((flags & PMAP_UNMANAGED) == 0)) ? 2785 PHYS_TO_VM_PAGE(pa) : NULL; 2786 2787 nflags = 0; 2788 if (prot & VM_PROT_WRITE) 2789 nflags |= PVF_WRITE; 2790 if (prot & VM_PROT_EXECUTE) 2791 nflags |= PVF_EXEC; 2792 if (flags & PMAP_WIRED) 2793 nflags |= PVF_WIRED; 2794 2795 PMAP_MAP_TO_HEAD_LOCK(); 2796 pmap_acquire_pmap_lock(pm); 2797 2798 /* 2799 * Fetch the L2 bucket which maps this page, allocating one if 2800 * necessary for user pmaps. 2801 */ 2802 if (pm == pmap_kernel()) 2803 l2b = pmap_get_l2_bucket(pm, va); 2804 else 2805 l2b = pmap_alloc_l2_bucket(pm, va); 2806 if (l2b == NULL) { 2807 if (flags & PMAP_CANFAIL) { 2808 pmap_release_pmap_lock(pm); 2809 PMAP_MAP_TO_HEAD_UNLOCK(); 2810 return (ENOMEM); 2811 } 2812 panic("pmap_enter: failed to allocate L2 bucket"); 2813 } 2814 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2815 opte = *ptep; 2816 npte = pa; 2817 oflags = 0; 2818 2819 if (opte) { 2820 /* 2821 * There is already a mapping at this address. 2822 * If the physical address is different, lookup the 2823 * vm_page. 2824 */ 2825 if (l2pte_pa(opte) != pa) 2826 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2827 else 2828 opg = pg; 2829 } else 2830 opg = NULL; 2831 2832 if (pg) { 2833 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2834 2835 /* 2836 * This is to be a managed mapping. 2837 */ 2838 if ((flags & VM_PROT_ALL) || 2839 (md->pvh_attrs & PVF_REF)) { 2840 /* 2841 * - The access type indicates that we don't need 2842 * to do referenced emulation. 2843 * OR 2844 * - The physical page has already been referenced 2845 * so no need to re-do referenced emulation here. 2846 */ 2847 npte |= L2_S_PROTO; 2848 2849 nflags |= PVF_REF; 2850 2851 if ((prot & VM_PROT_WRITE) != 0 && 2852 ((flags & VM_PROT_WRITE) != 0 || 2853 (md->pvh_attrs & PVF_MOD) != 0)) { 2854 /* 2855 * This is a writable mapping, and the 2856 * page's mod state indicates it has 2857 * already been modified. Make it 2858 * writable from the outset. 2859 */ 2860 npte |= L2_S_PROT_W; 2861 nflags |= PVF_MOD; 2862 } 2863 } else { 2864 /* 2865 * Need to do page referenced emulation. 2866 */ 2867 npte |= L2_TYPE_INV; 2868 } 2869 2870 npte |= pte_l2_s_cache_mode; 2871 2872 if (pg == opg) { 2873 /* 2874 * We're changing the attrs of an existing mapping. 2875 */ 2876 simple_lock(&md->pvh_slock); 2877 oflags = pmap_modify_pv(md, pa, pm, va, 2878 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2879 PVF_MOD | PVF_REF, nflags); 2880 simple_unlock(&md->pvh_slock); 2881 2882 #ifdef PMAP_CACHE_VIVT 2883 /* 2884 * We may need to flush the cache if we're 2885 * doing rw-ro... 2886 */ 2887 if (pm->pm_cstate.cs_cache_d && 2888 (oflags & PVF_NC) == 0 && 2889 (opte & L2_S_PROT_W) != 0 && 2890 (prot & VM_PROT_WRITE) == 0) 2891 cpu_dcache_wb_range(va, PAGE_SIZE); 2892 #endif 2893 } else { 2894 /* 2895 * New mapping, or changing the backing page 2896 * of an existing mapping. 2897 */ 2898 if (opg) { 2899 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2900 paddr_t opa; 2901 2902 opa = VM_PAGE_TO_PHYS(opg); 2903 2904 /* 2905 * Replacing an existing mapping with a new one. 2906 * It is part of our managed memory so we 2907 * must remove it from the PV list 2908 */ 2909 simple_lock(&omd->pvh_slock); 2910 pv = pmap_remove_pv(omd, opa, pm, va); 2911 pmap_vac_me_harder(omd, opa, pm, 0); 2912 simple_unlock(&omd->pvh_slock); 2913 oflags = pv->pv_flags; 2914 2915 #ifdef PMAP_CACHE_VIVT 2916 /* 2917 * If the old mapping was valid (ref/mod 2918 * emulation creates 'invalid' mappings 2919 * initially) then make sure to frob 2920 * the cache. 2921 */ 2922 if ((oflags & PVF_NC) == 0 && 2923 l2pte_valid(opte)) { 2924 if (PV_BEEN_EXECD(oflags)) { 2925 pmap_idcache_wbinv_range(pm, va, 2926 PAGE_SIZE); 2927 } else 2928 if (PV_BEEN_REFD(oflags)) { 2929 pmap_dcache_wb_range(pm, va, 2930 PAGE_SIZE, true, 2931 (oflags & PVF_WRITE) == 0); 2932 } 2933 } 2934 #endif 2935 } else 2936 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2937 if ((flags & PMAP_CANFAIL) == 0) 2938 panic("pmap_enter: no pv entries"); 2939 2940 if (pm != pmap_kernel()) 2941 pmap_free_l2_bucket(pm, l2b, 0); 2942 pmap_release_pmap_lock(pm); 2943 PMAP_MAP_TO_HEAD_UNLOCK(); 2944 NPDEBUG(PDB_ENTER, 2945 printf("pmap_enter: ENOMEM\n")); 2946 return (ENOMEM); 2947 } 2948 2949 pmap_enter_pv(md, VM_PAGE_TO_PHYS(pg), pv, pm, va, nflags); 2950 } 2951 } else { 2952 /* 2953 * We're mapping an unmanaged page. 2954 * These are always readable, and possibly writable, from 2955 * the get go as we don't need to track ref/mod status. 2956 */ 2957 npte |= L2_S_PROTO; 2958 if (prot & VM_PROT_WRITE) 2959 npte |= L2_S_PROT_W; 2960 2961 /* 2962 * Make sure the vector table is mapped cacheable 2963 */ 2964 if (pm != pmap_kernel() && va == vector_page) 2965 npte |= pte_l2_s_cache_mode; 2966 2967 if (opg) { 2968 /* 2969 * Looks like there's an existing 'managed' mapping 2970 * at this address. 2971 */ 2972 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2973 simple_lock(&omd->pvh_slock); 2974 pv = pmap_remove_pv(omd, VM_PAGE_TO_PHYS(opg), pm, va); 2975 pmap_vac_me_harder(omd, VM_PAGE_TO_PHYS(opg), pm, 0); 2976 simple_unlock(&omd->pvh_slock); 2977 oflags = pv->pv_flags; 2978 2979 #ifdef PMAP_CACHE_VIVT 2980 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2981 if (PV_BEEN_EXECD(oflags)) 2982 pmap_idcache_wbinv_range(pm, va, 2983 PAGE_SIZE); 2984 else 2985 if (PV_BEEN_REFD(oflags)) 2986 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2987 true, (oflags & PVF_WRITE) == 0); 2988 } 2989 #endif 2990 pool_put(&pmap_pv_pool, pv); 2991 } 2992 } 2993 2994 /* 2995 * Make sure userland mappings get the right permissions 2996 */ 2997 if (pm != pmap_kernel() && va != vector_page) 2998 npte |= L2_S_PROT_U; 2999 3000 /* 3001 * Keep the stats up to date 3002 */ 3003 if (opte == 0) { 3004 l2b->l2b_occupancy++; 3005 pm->pm_stats.resident_count++; 3006 } 3007 3008 NPDEBUG(PDB_ENTER, 3009 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3010 3011 /* 3012 * If this is just a wiring change, the two PTEs will be 3013 * identical, so there's no need to update the page table. 3014 */ 3015 if (npte != opte) { 3016 bool is_cached = pmap_is_cached(pm); 3017 3018 *ptep = npte; 3019 if (is_cached) { 3020 /* 3021 * We only need to frob the cache/tlb if this pmap 3022 * is current 3023 */ 3024 PTE_SYNC(ptep); 3025 if (va != vector_page && l2pte_valid(npte)) { 3026 /* 3027 * This mapping is likely to be accessed as 3028 * soon as we return to userland. Fix up the 3029 * L1 entry to avoid taking another 3030 * page/domain fault. 3031 */ 3032 pd_entry_t *pl1pd, l1pd; 3033 3034 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3035 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3036 L1_C_PROTO; 3037 if (*pl1pd != l1pd) { 3038 *pl1pd = l1pd; 3039 PTE_SYNC(pl1pd); 3040 } 3041 } 3042 } 3043 3044 if (PV_BEEN_EXECD(oflags)) 3045 pmap_tlb_flushID_SE(pm, va); 3046 else 3047 if (PV_BEEN_REFD(oflags)) 3048 pmap_tlb_flushD_SE(pm, va); 3049 3050 NPDEBUG(PDB_ENTER, 3051 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3052 is_cached, pm->pm_cstate.cs_all)); 3053 3054 if (pg != NULL) { 3055 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3056 simple_lock(&md->pvh_slock); 3057 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pm, va); 3058 simple_unlock(&md->pvh_slock); 3059 } 3060 } 3061 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3062 if (pg) { 3063 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3064 simple_lock(&md->pvh_slock); 3065 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3066 KASSERT(((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0)); 3067 simple_unlock(&md->pvh_slock); 3068 } 3069 #endif 3070 3071 pmap_release_pmap_lock(pm); 3072 PMAP_MAP_TO_HEAD_UNLOCK(); 3073 3074 return (0); 3075 } 3076 3077 /* 3078 * pmap_remove() 3079 * 3080 * pmap_remove is responsible for nuking a number of mappings for a range 3081 * of virtual address space in the current pmap. To do this efficiently 3082 * is interesting, because in a number of cases a wide virtual address 3083 * range may be supplied that contains few actual mappings. So, the 3084 * optimisations are: 3085 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3086 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3087 * maybe do just a partial cache clean. This path of execution is 3088 * complicated by the fact that the cache must be flushed _before_ 3089 * the PTE is nuked, being a VAC :-) 3090 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3091 * all invalidations until pmap_update(), since pmap_remove_all() has 3092 * already flushed the cache. 3093 * 4. Maybe later fast-case a single page, but I don't think this is 3094 * going to make _that_ much difference overall. 3095 */ 3096 3097 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3098 3099 void 3100 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3101 { 3102 struct l2_bucket *l2b; 3103 vaddr_t next_bucket; 3104 pt_entry_t *ptep; 3105 u_int cleanlist_idx, total, cnt; 3106 struct { 3107 vaddr_t va; 3108 pt_entry_t *ptep; 3109 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3110 u_int mappings, is_exec, is_refd; 3111 3112 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3113 "eva=%08lx\n", pm, sva, eva)); 3114 3115 /* 3116 * we lock in the pmap => pv_head direction 3117 */ 3118 PMAP_MAP_TO_HEAD_LOCK(); 3119 pmap_acquire_pmap_lock(pm); 3120 3121 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3122 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3123 if (pm->pm_cstate.cs_tlb == 0) 3124 pm->pm_remove_all = true; 3125 } else 3126 cleanlist_idx = 0; 3127 3128 total = 0; 3129 3130 while (sva < eva) { 3131 /* 3132 * Do one L2 bucket's worth at a time. 3133 */ 3134 next_bucket = L2_NEXT_BUCKET(sva); 3135 if (next_bucket > eva) 3136 next_bucket = eva; 3137 3138 l2b = pmap_get_l2_bucket(pm, sva); 3139 if (l2b == NULL) { 3140 sva = next_bucket; 3141 continue; 3142 } 3143 3144 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3145 3146 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3147 struct vm_page *pg; 3148 pt_entry_t pte; 3149 paddr_t pa; 3150 3151 pte = *ptep; 3152 3153 if (pte == 0) { 3154 /* Nothing here, move along */ 3155 continue; 3156 } 3157 3158 pa = l2pte_pa(pte); 3159 is_exec = 0; 3160 is_refd = 1; 3161 3162 /* 3163 * Update flags. In a number of circumstances, 3164 * we could cluster a lot of these and do a 3165 * number of sequential pages in one go. 3166 */ 3167 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3168 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3169 struct pv_entry *pv; 3170 simple_lock(&md->pvh_slock); 3171 pv = pmap_remove_pv(md, VM_PAGE_TO_PHYS(pg), pm, sva); 3172 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pm, 0); 3173 simple_unlock(&md->pvh_slock); 3174 if (pv != NULL) { 3175 if (pm->pm_remove_all == false) { 3176 is_exec = 3177 PV_BEEN_EXECD(pv->pv_flags); 3178 is_refd = 3179 PV_BEEN_REFD(pv->pv_flags); 3180 } 3181 pool_put(&pmap_pv_pool, pv); 3182 } 3183 } 3184 mappings++; 3185 3186 if (!l2pte_valid(pte)) { 3187 /* 3188 * Ref/Mod emulation is still active for this 3189 * mapping, therefore it is has not yet been 3190 * accessed. No need to frob the cache/tlb. 3191 */ 3192 *ptep = 0; 3193 PTE_SYNC_CURRENT(pm, ptep); 3194 continue; 3195 } 3196 3197 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3198 /* Add to the clean list. */ 3199 cleanlist[cleanlist_idx].ptep = ptep; 3200 cleanlist[cleanlist_idx].va = 3201 sva | (is_exec & 1); 3202 cleanlist_idx++; 3203 } else 3204 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3205 /* Nuke everything if needed. */ 3206 #ifdef PMAP_CACHE_VIVT 3207 pmap_idcache_wbinv_all(pm); 3208 #endif 3209 pmap_tlb_flushID(pm); 3210 3211 /* 3212 * Roll back the previous PTE list, 3213 * and zero out the current PTE. 3214 */ 3215 for (cnt = 0; 3216 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3217 *cleanlist[cnt].ptep = 0; 3218 PTE_SYNC(cleanlist[cnt].ptep); 3219 } 3220 *ptep = 0; 3221 PTE_SYNC(ptep); 3222 cleanlist_idx++; 3223 pm->pm_remove_all = true; 3224 } else { 3225 *ptep = 0; 3226 PTE_SYNC(ptep); 3227 if (pm->pm_remove_all == false) { 3228 if (is_exec) 3229 pmap_tlb_flushID_SE(pm, sva); 3230 else 3231 if (is_refd) 3232 pmap_tlb_flushD_SE(pm, sva); 3233 } 3234 } 3235 } 3236 3237 /* 3238 * Deal with any left overs 3239 */ 3240 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3241 total += cleanlist_idx; 3242 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3243 if (pm->pm_cstate.cs_all != 0) { 3244 vaddr_t clva = cleanlist[cnt].va & ~1; 3245 if (cleanlist[cnt].va & 1) { 3246 #ifdef PMAP_CACHE_VIVT 3247 pmap_idcache_wbinv_range(pm, 3248 clva, PAGE_SIZE); 3249 #endif 3250 pmap_tlb_flushID_SE(pm, clva); 3251 } else { 3252 #ifdef PMAP_CACHE_VIVT 3253 pmap_dcache_wb_range(pm, 3254 clva, PAGE_SIZE, true, 3255 false); 3256 #endif 3257 pmap_tlb_flushD_SE(pm, clva); 3258 } 3259 } 3260 *cleanlist[cnt].ptep = 0; 3261 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3262 } 3263 3264 /* 3265 * If it looks like we're removing a whole bunch 3266 * of mappings, it's faster to just write-back 3267 * the whole cache now and defer TLB flushes until 3268 * pmap_update() is called. 3269 */ 3270 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3271 cleanlist_idx = 0; 3272 else { 3273 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3274 #ifdef PMAP_CACHE_VIVT 3275 pmap_idcache_wbinv_all(pm); 3276 #endif 3277 pm->pm_remove_all = true; 3278 } 3279 } 3280 3281 pmap_free_l2_bucket(pm, l2b, mappings); 3282 pm->pm_stats.resident_count -= mappings; 3283 } 3284 3285 pmap_release_pmap_lock(pm); 3286 PMAP_MAP_TO_HEAD_UNLOCK(); 3287 } 3288 3289 #ifdef PMAP_CACHE_VIPT 3290 static struct pv_entry * 3291 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3292 { 3293 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3294 struct pv_entry *pv; 3295 3296 simple_lock(&md->pvh_slock); 3297 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3298 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3299 3300 pv = pmap_remove_pv(md, VM_PAGE_TO_PHYS(pg), pmap_kernel(), va); 3301 KASSERT(pv); 3302 KASSERT(pv->pv_flags & PVF_KENTRY); 3303 3304 /* 3305 * If we are removing a writeable mapping to a cached exec page, 3306 * if it's the last mapping then clear it execness other sync 3307 * the page to the icache. 3308 */ 3309 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3310 && (pv->pv_flags & PVF_WRITE) != 0) { 3311 if (SLIST_EMPTY(&md->pvh_list)) { 3312 md->pvh_attrs &= ~PVF_EXEC; 3313 PMAPCOUNT(exec_discarded_kremove); 3314 } else { 3315 pmap_syncicache_page(md, VM_PAGE_TO_PHYS(pg)); 3316 PMAPCOUNT(exec_synced_kremove); 3317 } 3318 } 3319 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pmap_kernel(), 0); 3320 simple_unlock(&md->pvh_slock); 3321 3322 return pv; 3323 } 3324 #endif /* PMAP_CACHE_VIPT */ 3325 3326 /* 3327 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3328 * 3329 * We assume there is already sufficient KVM space available 3330 * to do this, as we can't allocate L2 descriptor tables/metadata 3331 * from here. 3332 */ 3333 void 3334 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3335 { 3336 struct l2_bucket *l2b; 3337 pt_entry_t *ptep, opte; 3338 #ifdef PMAP_CACHE_VIVT 3339 struct vm_page *pg = (prot & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3340 #endif 3341 #ifdef PMAP_CACHE_VIPT 3342 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3343 struct vm_page *opg; 3344 struct pv_entry *pv = NULL; 3345 #endif 3346 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3347 3348 NPDEBUG(PDB_KENTER, 3349 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x pg %p md %p\n", 3350 va, pa, prot, pg, md)); 3351 3352 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3353 KDASSERT(l2b != NULL); 3354 3355 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3356 opte = *ptep; 3357 3358 if (opte == 0) { 3359 PMAPCOUNT(kenter_mappings); 3360 l2b->l2b_occupancy++; 3361 } else { 3362 PMAPCOUNT(kenter_remappings); 3363 #ifdef PMAP_CACHE_VIPT 3364 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3365 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3366 if (opg) { 3367 KASSERT(opg != pg); 3368 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3369 KASSERT((prot & PMAP_KMPAGE) == 0); 3370 simple_lock(&omd->pvh_slock); 3371 pv = pmap_kremove_pg(opg, va); 3372 simple_unlock(&omd->pvh_slock); 3373 } 3374 #endif 3375 if (l2pte_valid(opte)) { 3376 #ifdef PMAP_CACHE_VIVT 3377 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3378 #endif 3379 cpu_tlb_flushD_SE(va); 3380 cpu_cpwait(); 3381 } 3382 } 3383 3384 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3385 pte_l2_s_cache_mode; 3386 PTE_SYNC(ptep); 3387 3388 if (pg) { 3389 if (prot & PMAP_KMPAGE) { 3390 simple_lock(&md->pvh_slock); 3391 KASSERT(md->urw_mappings == 0); 3392 KASSERT(md->uro_mappings == 0); 3393 KASSERT(md->krw_mappings == 0); 3394 KASSERT(md->kro_mappings == 0); 3395 #ifdef PMAP_CACHE_VIPT 3396 KASSERT(pv == NULL); 3397 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3398 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3399 /* if there is a color conflict, evict from cache. */ 3400 if (pmap_is_page_colored_p(md) 3401 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3402 PMAPCOUNT(vac_color_change); 3403 pmap_flush_page(md, VM_PAGE_TO_PHYS(pg), PMAP_FLUSH_PRIMARY); 3404 } else if (md->pvh_attrs & PVF_MULTCLR) { 3405 /* 3406 * If this page has multiple colors, expunge 3407 * them. 3408 */ 3409 PMAPCOUNT(vac_flush_lots2); 3410 pmap_flush_page(md, VM_PAGE_TO_PHYS(pg), PMAP_FLUSH_SECONDARY); 3411 } 3412 md->pvh_attrs &= PAGE_SIZE - 1; 3413 md->pvh_attrs |= PVF_KMPAGE 3414 | PVF_COLORED | PVF_DIRTY 3415 | (va & arm_cache_prefer_mask); 3416 #endif 3417 #ifdef PMAP_CACHE_VIVT 3418 md->pvh_attrs |= PVF_KMPAGE; 3419 #endif 3420 pmap_kmpages++; 3421 simple_unlock(&md->pvh_slock); 3422 #ifdef PMAP_CACHE_VIPT 3423 } else { 3424 if (pv == NULL) { 3425 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3426 KASSERT(pv != NULL); 3427 } 3428 pmap_enter_pv(md, VM_PAGE_TO_PHYS(pg), pv, pmap_kernel(), va, 3429 PVF_WIRED | PVF_KENTRY 3430 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3431 if ((prot & VM_PROT_WRITE) 3432 && !(md->pvh_attrs & PVF_NC)) 3433 md->pvh_attrs |= PVF_DIRTY; 3434 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3435 simple_lock(&md->pvh_slock); 3436 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pmap_kernel(), va); 3437 simple_unlock(&md->pvh_slock); 3438 #endif 3439 } 3440 #ifdef PMAP_CACHE_VIPT 3441 } else { 3442 if (pv != NULL) 3443 pool_put(&pmap_pv_pool, pv); 3444 #endif 3445 } 3446 } 3447 3448 void 3449 pmap_kremove(vaddr_t va, vsize_t len) 3450 { 3451 struct l2_bucket *l2b; 3452 pt_entry_t *ptep, *sptep, opte; 3453 vaddr_t next_bucket, eva; 3454 u_int mappings; 3455 struct vm_page *opg; 3456 3457 PMAPCOUNT(kenter_unmappings); 3458 3459 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3460 va, len)); 3461 3462 eva = va + len; 3463 3464 while (va < eva) { 3465 next_bucket = L2_NEXT_BUCKET(va); 3466 if (next_bucket > eva) 3467 next_bucket = eva; 3468 3469 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3470 KDASSERT(l2b != NULL); 3471 3472 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3473 mappings = 0; 3474 3475 while (va < next_bucket) { 3476 opte = *ptep; 3477 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3478 if (opg) { 3479 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3480 if (omd->pvh_attrs & PVF_KMPAGE) { 3481 simple_lock(&omd->pvh_slock); 3482 KASSERT(omd->urw_mappings == 0); 3483 KASSERT(omd->uro_mappings == 0); 3484 KASSERT(omd->krw_mappings == 0); 3485 KASSERT(omd->kro_mappings == 0); 3486 omd->pvh_attrs &= ~PVF_KMPAGE; 3487 #ifdef PMAP_CACHE_VIPT 3488 omd->pvh_attrs &= ~PVF_WRITE; 3489 #endif 3490 pmap_kmpages--; 3491 simple_unlock(&omd->pvh_slock); 3492 #ifdef PMAP_CACHE_VIPT 3493 } else { 3494 pool_put(&pmap_pv_pool, 3495 pmap_kremove_pg(opg, va)); 3496 #endif 3497 } 3498 } 3499 if (l2pte_valid(opte)) { 3500 #ifdef PMAP_CACHE_VIVT 3501 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3502 #endif 3503 cpu_tlb_flushD_SE(va); 3504 } 3505 if (opte) { 3506 *ptep = 0; 3507 mappings++; 3508 } 3509 va += PAGE_SIZE; 3510 ptep++; 3511 } 3512 KDASSERT(mappings <= l2b->l2b_occupancy); 3513 l2b->l2b_occupancy -= mappings; 3514 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3515 } 3516 cpu_cpwait(); 3517 } 3518 3519 bool 3520 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3521 { 3522 struct l2_dtable *l2; 3523 pd_entry_t *pl1pd, l1pd; 3524 pt_entry_t *ptep, pte; 3525 paddr_t pa; 3526 u_int l1idx; 3527 3528 pmap_acquire_pmap_lock(pm); 3529 3530 l1idx = L1_IDX(va); 3531 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3532 l1pd = *pl1pd; 3533 3534 if (l1pte_section_p(l1pd)) { 3535 /* 3536 * These should only happen for pmap_kernel() 3537 */ 3538 KDASSERT(pm == pmap_kernel()); 3539 pmap_release_pmap_lock(pm); 3540 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3541 } else { 3542 /* 3543 * Note that we can't rely on the validity of the L1 3544 * descriptor as an indication that a mapping exists. 3545 * We have to look it up in the L2 dtable. 3546 */ 3547 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3548 3549 if (l2 == NULL || 3550 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3551 pmap_release_pmap_lock(pm); 3552 return false; 3553 } 3554 3555 ptep = &ptep[l2pte_index(va)]; 3556 pte = *ptep; 3557 pmap_release_pmap_lock(pm); 3558 3559 if (pte == 0) 3560 return false; 3561 3562 switch (pte & L2_TYPE_MASK) { 3563 case L2_TYPE_L: 3564 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3565 break; 3566 3567 default: 3568 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3569 break; 3570 } 3571 } 3572 3573 if (pap != NULL) 3574 *pap = pa; 3575 3576 return true; 3577 } 3578 3579 void 3580 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3581 { 3582 struct l2_bucket *l2b; 3583 pt_entry_t *ptep, pte; 3584 vaddr_t next_bucket; 3585 u_int flags; 3586 u_int clr_mask; 3587 int flush; 3588 3589 NPDEBUG(PDB_PROTECT, 3590 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3591 pm, sva, eva, prot)); 3592 3593 if ((prot & VM_PROT_READ) == 0) { 3594 pmap_remove(pm, sva, eva); 3595 return; 3596 } 3597 3598 if (prot & VM_PROT_WRITE) { 3599 /* 3600 * If this is a read->write transition, just ignore it and let 3601 * uvm_fault() take care of it later. 3602 */ 3603 return; 3604 } 3605 3606 PMAP_MAP_TO_HEAD_LOCK(); 3607 pmap_acquire_pmap_lock(pm); 3608 3609 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3610 flags = 0; 3611 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3612 3613 while (sva < eva) { 3614 next_bucket = L2_NEXT_BUCKET(sva); 3615 if (next_bucket > eva) 3616 next_bucket = eva; 3617 3618 l2b = pmap_get_l2_bucket(pm, sva); 3619 if (l2b == NULL) { 3620 sva = next_bucket; 3621 continue; 3622 } 3623 3624 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3625 3626 while (sva < next_bucket) { 3627 pte = *ptep; 3628 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3629 struct vm_page *pg; 3630 u_int f; 3631 3632 #ifdef PMAP_CACHE_VIVT 3633 /* 3634 * OK, at this point, we know we're doing 3635 * write-protect operation. If the pmap is 3636 * active, write-back the page. 3637 */ 3638 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3639 false, false); 3640 #endif 3641 3642 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3643 pte &= ~L2_S_PROT_W; 3644 *ptep = pte; 3645 PTE_SYNC(ptep); 3646 3647 if (pg != NULL) { 3648 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3649 simple_lock(&md->pvh_slock); 3650 f = pmap_modify_pv(md, VM_PAGE_TO_PHYS(pg), pm, sva, 3651 clr_mask, 0); 3652 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pm, sva); 3653 simple_unlock(&md->pvh_slock); 3654 } else 3655 f = PVF_REF | PVF_EXEC; 3656 3657 if (flush >= 0) { 3658 flush++; 3659 flags |= f; 3660 } else 3661 if (PV_BEEN_EXECD(f)) 3662 pmap_tlb_flushID_SE(pm, sva); 3663 else 3664 if (PV_BEEN_REFD(f)) 3665 pmap_tlb_flushD_SE(pm, sva); 3666 } 3667 3668 sva += PAGE_SIZE; 3669 ptep++; 3670 } 3671 } 3672 3673 pmap_release_pmap_lock(pm); 3674 PMAP_MAP_TO_HEAD_UNLOCK(); 3675 3676 if (flush) { 3677 if (PV_BEEN_EXECD(flags)) 3678 pmap_tlb_flushID(pm); 3679 else 3680 if (PV_BEEN_REFD(flags)) 3681 pmap_tlb_flushD(pm); 3682 } 3683 } 3684 3685 void 3686 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3687 { 3688 struct l2_bucket *l2b; 3689 pt_entry_t *ptep; 3690 vaddr_t next_bucket; 3691 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3692 3693 NPDEBUG(PDB_EXEC, 3694 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3695 pm, sva, eva)); 3696 3697 PMAP_MAP_TO_HEAD_LOCK(); 3698 pmap_acquire_pmap_lock(pm); 3699 3700 while (sva < eva) { 3701 next_bucket = L2_NEXT_BUCKET(sva); 3702 if (next_bucket > eva) 3703 next_bucket = eva; 3704 3705 l2b = pmap_get_l2_bucket(pm, sva); 3706 if (l2b == NULL) { 3707 sva = next_bucket; 3708 continue; 3709 } 3710 3711 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3712 sva < next_bucket; 3713 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3714 if (l2pte_valid(*ptep)) { 3715 cpu_icache_sync_range(sva, 3716 min(page_size, eva - sva)); 3717 } 3718 } 3719 } 3720 3721 pmap_release_pmap_lock(pm); 3722 PMAP_MAP_TO_HEAD_UNLOCK(); 3723 } 3724 3725 void 3726 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3727 { 3728 3729 NPDEBUG(PDB_PROTECT, 3730 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3731 pg, VM_PAGE_TO_PHYS(pg), prot)); 3732 3733 switch(prot) { 3734 case VM_PROT_READ|VM_PROT_WRITE: 3735 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3736 pmap_clearbit(pg, PVF_EXEC); 3737 break; 3738 #endif 3739 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3740 break; 3741 3742 case VM_PROT_READ: 3743 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3744 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3745 break; 3746 #endif 3747 case VM_PROT_READ|VM_PROT_EXECUTE: 3748 pmap_clearbit(pg, PVF_WRITE); 3749 break; 3750 3751 default: 3752 pmap_page_remove(pg); 3753 break; 3754 } 3755 } 3756 3757 /* 3758 * pmap_clear_modify: 3759 * 3760 * Clear the "modified" attribute for a page. 3761 */ 3762 bool 3763 pmap_clear_modify(struct vm_page *pg) 3764 { 3765 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3766 bool rv; 3767 3768 if (md->pvh_attrs & PVF_MOD) { 3769 rv = true; 3770 #ifdef PMAP_CACHE_VIPT 3771 /* 3772 * If we are going to clear the modified bit and there are 3773 * no other modified bits set, flush the page to memory and 3774 * mark it clean. 3775 */ 3776 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3777 pmap_flush_page(md, VM_PAGE_TO_PHYS(pg), PMAP_CLEAN_PRIMARY); 3778 #endif 3779 pmap_clearbit(pg, PVF_MOD); 3780 } else 3781 rv = false; 3782 3783 return (rv); 3784 } 3785 3786 /* 3787 * pmap_clear_reference: 3788 * 3789 * Clear the "referenced" attribute for a page. 3790 */ 3791 bool 3792 pmap_clear_reference(struct vm_page *pg) 3793 { 3794 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3795 bool rv; 3796 3797 if (md->pvh_attrs & PVF_REF) { 3798 rv = true; 3799 pmap_clearbit(pg, PVF_REF); 3800 } else 3801 rv = false; 3802 3803 return (rv); 3804 } 3805 3806 /* 3807 * pmap_is_modified: 3808 * 3809 * Test if a page has the "modified" attribute. 3810 */ 3811 /* See <arm/arm32/pmap.h> */ 3812 3813 /* 3814 * pmap_is_referenced: 3815 * 3816 * Test if a page has the "referenced" attribute. 3817 */ 3818 /* See <arm/arm32/pmap.h> */ 3819 3820 int 3821 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3822 { 3823 struct l2_dtable *l2; 3824 struct l2_bucket *l2b; 3825 pd_entry_t *pl1pd, l1pd; 3826 pt_entry_t *ptep, pte; 3827 paddr_t pa; 3828 u_int l1idx; 3829 int rv = 0; 3830 3831 PMAP_MAP_TO_HEAD_LOCK(); 3832 pmap_acquire_pmap_lock(pm); 3833 3834 l1idx = L1_IDX(va); 3835 3836 /* 3837 * If there is no l2_dtable for this address, then the process 3838 * has no business accessing it. 3839 * 3840 * Note: This will catch userland processes trying to access 3841 * kernel addresses. 3842 */ 3843 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3844 if (l2 == NULL) 3845 goto out; 3846 3847 /* 3848 * Likewise if there is no L2 descriptor table 3849 */ 3850 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3851 if (l2b->l2b_kva == NULL) 3852 goto out; 3853 3854 /* 3855 * Check the PTE itself. 3856 */ 3857 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3858 pte = *ptep; 3859 if (pte == 0) 3860 goto out; 3861 3862 /* 3863 * Catch a userland access to the vector page mapped at 0x0 3864 */ 3865 if (user && (pte & L2_S_PROT_U) == 0) 3866 goto out; 3867 3868 pa = l2pte_pa(pte); 3869 3870 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3871 /* 3872 * This looks like a good candidate for "page modified" 3873 * emulation... 3874 */ 3875 struct pv_entry *pv; 3876 struct vm_page *pg; 3877 3878 /* Extract the physical address of the page */ 3879 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3880 goto out; 3881 3882 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3883 3884 /* Get the current flags for this page. */ 3885 simple_lock(&md->pvh_slock); 3886 3887 pv = pmap_find_pv(md, pm, va); 3888 if (pv == NULL) { 3889 simple_unlock(&md->pvh_slock); 3890 goto out; 3891 } 3892 3893 /* 3894 * Do the flags say this page is writable? If not then it 3895 * is a genuine write fault. If yes then the write fault is 3896 * our fault as we did not reflect the write access in the 3897 * PTE. Now we know a write has occurred we can correct this 3898 * and also set the modified bit 3899 */ 3900 if ((pv->pv_flags & PVF_WRITE) == 0) { 3901 simple_unlock(&md->pvh_slock); 3902 goto out; 3903 } 3904 3905 NPDEBUG(PDB_FOLLOW, 3906 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3907 pm, va, VM_PAGE_TO_PHYS(pg))); 3908 3909 md->pvh_attrs |= PVF_REF | PVF_MOD; 3910 pv->pv_flags |= PVF_REF | PVF_MOD; 3911 #ifdef PMAP_CACHE_VIPT 3912 /* 3913 * If there are cacheable mappings for this page, mark it dirty. 3914 */ 3915 if ((md->pvh_attrs & PVF_NC) == 0) 3916 md->pvh_attrs |= PVF_DIRTY; 3917 #endif 3918 simple_unlock(&md->pvh_slock); 3919 3920 /* 3921 * Re-enable write permissions for the page. No need to call 3922 * pmap_vac_me_harder(), since this is just a 3923 * modified-emulation fault, and the PVF_WRITE bit isn't 3924 * changing. We've already set the cacheable bits based on 3925 * the assumption that we can write to this page. 3926 */ 3927 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3928 PTE_SYNC(ptep); 3929 rv = 1; 3930 } else 3931 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3932 /* 3933 * This looks like a good candidate for "page referenced" 3934 * emulation. 3935 */ 3936 struct pv_entry *pv; 3937 struct vm_page *pg; 3938 3939 /* Extract the physical address of the page */ 3940 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3941 goto out; 3942 3943 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3944 3945 /* Get the current flags for this page. */ 3946 simple_lock(&md->pvh_slock); 3947 3948 pv = pmap_find_pv(md, pm, va); 3949 if (pv == NULL) { 3950 simple_unlock(&md->pvh_slock); 3951 goto out; 3952 } 3953 3954 md->pvh_attrs |= PVF_REF; 3955 pv->pv_flags |= PVF_REF; 3956 simple_unlock(&md->pvh_slock); 3957 3958 NPDEBUG(PDB_FOLLOW, 3959 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3960 pm, va, VM_PAGE_TO_PHYS(pg))); 3961 3962 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3963 PTE_SYNC(ptep); 3964 rv = 1; 3965 } 3966 3967 /* 3968 * We know there is a valid mapping here, so simply 3969 * fix up the L1 if necessary. 3970 */ 3971 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3972 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3973 if (*pl1pd != l1pd) { 3974 *pl1pd = l1pd; 3975 PTE_SYNC(pl1pd); 3976 rv = 1; 3977 } 3978 3979 #ifdef CPU_SA110 3980 /* 3981 * There are bugs in the rev K SA110. This is a check for one 3982 * of them. 3983 */ 3984 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3985 curcpu()->ci_arm_cpurev < 3) { 3986 /* Always current pmap */ 3987 if (l2pte_valid(pte)) { 3988 extern int kernel_debug; 3989 if (kernel_debug & 1) { 3990 struct proc *p = curlwp->l_proc; 3991 printf("prefetch_abort: page is already " 3992 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3993 printf("prefetch_abort: pc=%08lx proc=%p " 3994 "process=%s\n", va, p, p->p_comm); 3995 printf("prefetch_abort: far=%08x fs=%x\n", 3996 cpu_faultaddress(), cpu_faultstatus()); 3997 } 3998 #ifdef DDB 3999 if (kernel_debug & 2) 4000 Debugger(); 4001 #endif 4002 rv = 1; 4003 } 4004 } 4005 #endif /* CPU_SA110 */ 4006 4007 #ifdef DEBUG 4008 /* 4009 * If 'rv == 0' at this point, it generally indicates that there is a 4010 * stale TLB entry for the faulting address. This happens when two or 4011 * more processes are sharing an L1. Since we don't flush the TLB on 4012 * a context switch between such processes, we can take domain faults 4013 * for mappings which exist at the same VA in both processes. EVEN IF 4014 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4015 * example. 4016 * 4017 * This is extremely likely to happen if pmap_enter() updated the L1 4018 * entry for a recently entered mapping. In this case, the TLB is 4019 * flushed for the new mapping, but there may still be TLB entries for 4020 * other mappings belonging to other processes in the 1MB range 4021 * covered by the L1 entry. 4022 * 4023 * Since 'rv == 0', we know that the L1 already contains the correct 4024 * value, so the fault must be due to a stale TLB entry. 4025 * 4026 * Since we always need to flush the TLB anyway in the case where we 4027 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4028 * stale TLB entries dynamically. 4029 * 4030 * However, the above condition can ONLY happen if the current L1 is 4031 * being shared. If it happens when the L1 is unshared, it indicates 4032 * that other parts of the pmap are not doing their job WRT managing 4033 * the TLB. 4034 */ 4035 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4036 extern int last_fault_code; 4037 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4038 pm, va, ftype); 4039 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4040 l2, l2b, ptep, pl1pd); 4041 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4042 pte, l1pd, last_fault_code); 4043 #ifdef DDB 4044 Debugger(); 4045 #endif 4046 } 4047 #endif 4048 4049 cpu_tlb_flushID_SE(va); 4050 cpu_cpwait(); 4051 4052 rv = 1; 4053 4054 out: 4055 pmap_release_pmap_lock(pm); 4056 PMAP_MAP_TO_HEAD_UNLOCK(); 4057 4058 return (rv); 4059 } 4060 4061 /* 4062 * Routine: pmap_procwr 4063 * 4064 * Function: 4065 * Synchronize caches corresponding to [addr, addr+len) in p. 4066 * 4067 */ 4068 void 4069 pmap_procwr(struct proc *p, vaddr_t va, int len) 4070 { 4071 /* We only need to do anything if it is the current process. */ 4072 if (p == curproc) 4073 cpu_icache_sync_range(va, len); 4074 } 4075 4076 /* 4077 * Routine: pmap_unwire 4078 * Function: Clear the wired attribute for a map/virtual-address pair. 4079 * 4080 * In/out conditions: 4081 * The mapping must already exist in the pmap. 4082 */ 4083 void 4084 pmap_unwire(pmap_t pm, vaddr_t va) 4085 { 4086 struct l2_bucket *l2b; 4087 pt_entry_t *ptep, pte; 4088 struct vm_page *pg; 4089 paddr_t pa; 4090 4091 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4092 4093 PMAP_MAP_TO_HEAD_LOCK(); 4094 pmap_acquire_pmap_lock(pm); 4095 4096 l2b = pmap_get_l2_bucket(pm, va); 4097 KDASSERT(l2b != NULL); 4098 4099 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4100 pte = *ptep; 4101 4102 /* Extract the physical address of the page */ 4103 pa = l2pte_pa(pte); 4104 4105 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4106 /* Update the wired bit in the pv entry for this page. */ 4107 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4108 simple_lock(&md->pvh_slock); 4109 (void) pmap_modify_pv(md, VM_PAGE_TO_PHYS(pg), pm, va, PVF_WIRED, 0); 4110 simple_unlock(&md->pvh_slock); 4111 } 4112 4113 pmap_release_pmap_lock(pm); 4114 PMAP_MAP_TO_HEAD_UNLOCK(); 4115 } 4116 4117 void 4118 pmap_activate(struct lwp *l) 4119 { 4120 extern int block_userspace_access; 4121 pmap_t opm, npm, rpm; 4122 uint32_t odacr, ndacr; 4123 int oldirqstate; 4124 4125 /* 4126 * If activating a non-current lwp or the current lwp is 4127 * already active, just return. 4128 */ 4129 if (l != curlwp || 4130 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4131 return; 4132 4133 npm = l->l_proc->p_vmspace->vm_map.pmap; 4134 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4135 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4136 4137 /* 4138 * If TTB and DACR are unchanged, short-circuit all the 4139 * TLB/cache management stuff. 4140 */ 4141 if (pmap_previous_active_lwp != NULL) { 4142 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4143 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4144 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4145 4146 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4147 goto all_done; 4148 } else 4149 opm = NULL; 4150 4151 PMAPCOUNT(activations); 4152 block_userspace_access = 1; 4153 4154 /* 4155 * If switching to a user vmspace which is different to the 4156 * most recent one, and the most recent one is potentially 4157 * live in the cache, we must write-back and invalidate the 4158 * entire cache. 4159 */ 4160 rpm = pmap_recent_user; 4161 4162 /* 4163 * XXXSCW: There's a corner case here which can leave turds in the cache as 4164 * reported in kern/41058. They're probably left over during tear-down and 4165 * switching away from an exiting process. Until the root cause is identified 4166 * and fixed, zap the cache when switching pmaps. This will result in a few 4167 * unnecessary cache flushes, but that's better than silently corrupting data. 4168 */ 4169 #if 0 4170 if (npm != pmap_kernel() && rpm && npm != rpm && 4171 rpm->pm_cstate.cs_cache) { 4172 rpm->pm_cstate.cs_cache = 0; 4173 #ifdef PMAP_CACHE_VIVT 4174 cpu_idcache_wbinv_all(); 4175 #endif 4176 } 4177 #else 4178 if (rpm) { 4179 rpm->pm_cstate.cs_cache = 0; 4180 if (npm == pmap_kernel()) 4181 pmap_recent_user = NULL; 4182 #ifdef PMAP_CACHE_VIVT 4183 cpu_idcache_wbinv_all(); 4184 #endif 4185 } 4186 #endif 4187 4188 /* No interrupts while we frob the TTB/DACR */ 4189 oldirqstate = disable_interrupts(IF32_bits); 4190 4191 /* 4192 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4193 * entry corresponding to 'vector_page' in the incoming L1 table 4194 * before switching to it otherwise subsequent interrupts/exceptions 4195 * (including domain faults!) will jump into hyperspace. 4196 */ 4197 if (npm->pm_pl1vec != NULL) { 4198 cpu_tlb_flushID_SE((u_int)vector_page); 4199 cpu_cpwait(); 4200 *npm->pm_pl1vec = npm->pm_l1vec; 4201 PTE_SYNC(npm->pm_pl1vec); 4202 } 4203 4204 cpu_domains(ndacr); 4205 4206 if (npm == pmap_kernel() || npm == rpm) { 4207 /* 4208 * Switching to a kernel thread, or back to the 4209 * same user vmspace as before... Simply update 4210 * the TTB (no TLB flush required) 4211 */ 4212 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4213 "r"(npm->pm_l1->l1_physaddr)); 4214 cpu_cpwait(); 4215 } else { 4216 /* 4217 * Otherwise, update TTB and flush TLB 4218 */ 4219 cpu_context_switch(npm->pm_l1->l1_physaddr); 4220 if (rpm != NULL) 4221 rpm->pm_cstate.cs_tlb = 0; 4222 } 4223 4224 restore_interrupts(oldirqstate); 4225 4226 block_userspace_access = 0; 4227 4228 all_done: 4229 /* 4230 * The new pmap is resident. Make sure it's marked 4231 * as resident in the cache/TLB. 4232 */ 4233 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4234 if (npm != pmap_kernel()) 4235 pmap_recent_user = npm; 4236 4237 /* The old pmap is not longer active */ 4238 if (opm != NULL) 4239 opm->pm_activated = false; 4240 4241 /* But the new one is */ 4242 npm->pm_activated = true; 4243 } 4244 4245 void 4246 pmap_deactivate(struct lwp *l) 4247 { 4248 4249 /* 4250 * If the process is exiting, make sure pmap_activate() does 4251 * a full MMU context-switch and cache flush, which we might 4252 * otherwise skip. See PR port-arm/38950. 4253 */ 4254 if (l->l_proc->p_sflag & PS_WEXIT) 4255 pmap_previous_active_lwp = NULL; 4256 4257 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4258 } 4259 4260 void 4261 pmap_update(pmap_t pm) 4262 { 4263 4264 if (pm->pm_remove_all) { 4265 /* 4266 * Finish up the pmap_remove_all() optimisation by flushing 4267 * the TLB. 4268 */ 4269 pmap_tlb_flushID(pm); 4270 pm->pm_remove_all = false; 4271 } 4272 4273 if (pmap_is_current(pm)) { 4274 /* 4275 * If we're dealing with a current userland pmap, move its L1 4276 * to the end of the LRU. 4277 */ 4278 if (pm != pmap_kernel()) 4279 pmap_use_l1(pm); 4280 4281 /* 4282 * We can assume we're done with frobbing the cache/tlb for 4283 * now. Make sure any future pmap ops don't skip cache/tlb 4284 * flushes. 4285 */ 4286 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4287 } 4288 4289 PMAPCOUNT(updates); 4290 4291 /* 4292 * make sure TLB/cache operations have completed. 4293 */ 4294 cpu_cpwait(); 4295 } 4296 4297 void 4298 pmap_remove_all(pmap_t pm) 4299 { 4300 4301 /* 4302 * The vmspace described by this pmap is about to be torn down. 4303 * Until pmap_update() is called, UVM will only make calls 4304 * to pmap_remove(). We can make life much simpler by flushing 4305 * the cache now, and deferring TLB invalidation to pmap_update(). 4306 */ 4307 #ifdef PMAP_CACHE_VIVT 4308 pmap_idcache_wbinv_all(pm); 4309 #endif 4310 pm->pm_remove_all = true; 4311 } 4312 4313 /* 4314 * Retire the given physical map from service. 4315 * Should only be called if the map contains no valid mappings. 4316 */ 4317 void 4318 pmap_destroy(pmap_t pm) 4319 { 4320 u_int count; 4321 4322 if (pm == NULL) 4323 return; 4324 4325 if (pm->pm_remove_all) { 4326 pmap_tlb_flushID(pm); 4327 pm->pm_remove_all = false; 4328 } 4329 4330 /* 4331 * Drop reference count 4332 */ 4333 mutex_enter(&pm->pm_lock); 4334 count = --pm->pm_obj.uo_refs; 4335 mutex_exit(&pm->pm_lock); 4336 if (count > 0) { 4337 if (pmap_is_current(pm)) { 4338 if (pm != pmap_kernel()) 4339 pmap_use_l1(pm); 4340 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4341 } 4342 return; 4343 } 4344 4345 /* 4346 * reference count is zero, free pmap resources and then free pmap. 4347 */ 4348 4349 if (vector_page < KERNEL_BASE) { 4350 KDASSERT(!pmap_is_current(pm)); 4351 4352 /* Remove the vector page mapping */ 4353 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4354 pmap_update(pm); 4355 } 4356 4357 LIST_REMOVE(pm, pm_list); 4358 4359 pmap_free_l1(pm); 4360 4361 if (pmap_recent_user == pm) 4362 pmap_recent_user = NULL; 4363 4364 UVM_OBJ_DESTROY(&pm->pm_obj); 4365 4366 /* return the pmap to the pool */ 4367 pool_cache_put(&pmap_cache, pm); 4368 } 4369 4370 4371 /* 4372 * void pmap_reference(pmap_t pm) 4373 * 4374 * Add a reference to the specified pmap. 4375 */ 4376 void 4377 pmap_reference(pmap_t pm) 4378 { 4379 4380 if (pm == NULL) 4381 return; 4382 4383 pmap_use_l1(pm); 4384 4385 mutex_enter(&pm->pm_lock); 4386 pm->pm_obj.uo_refs++; 4387 mutex_exit(&pm->pm_lock); 4388 } 4389 4390 #if ARM_MMU_V6 > 0 4391 4392 static struct evcnt pmap_prefer_nochange_ev = 4393 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4394 static struct evcnt pmap_prefer_change_ev = 4395 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4396 4397 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4398 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4399 4400 void 4401 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4402 { 4403 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4404 vaddr_t va = *vap; 4405 vaddr_t diff = (hint - va) & mask; 4406 if (diff == 0) { 4407 pmap_prefer_nochange_ev.ev_count++; 4408 } else { 4409 pmap_prefer_change_ev.ev_count++; 4410 if (__predict_false(td)) 4411 va -= mask + 1; 4412 *vap = va + diff; 4413 } 4414 } 4415 #endif /* ARM_MMU_V6 */ 4416 4417 /* 4418 * pmap_zero_page() 4419 * 4420 * Zero a given physical page by mapping it at a page hook point. 4421 * In doing the zero page op, the page we zero is mapped cachable, as with 4422 * StrongARM accesses to non-cached pages are non-burst making writing 4423 * _any_ bulk data very slow. 4424 */ 4425 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4426 void 4427 pmap_zero_page_generic(paddr_t phys) 4428 { 4429 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4430 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4431 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4432 #endif 4433 #ifdef PMAP_CACHE_VIPT 4434 /* Choose the last page color it had, if any */ 4435 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4436 #else 4437 const vsize_t va_offset = 0; 4438 #endif 4439 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4440 4441 #ifdef DEBUG 4442 if (!SLIST_EMPTY(&md->pvh_list)) 4443 panic("pmap_zero_page: page has mappings"); 4444 #endif 4445 4446 KDASSERT((phys & PGOFSET) == 0); 4447 4448 /* 4449 * Hook in the page, zero it, and purge the cache for that 4450 * zeroed page. Invalidate the TLB as needed. 4451 */ 4452 *ptep = L2_S_PROTO | phys | 4453 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4454 PTE_SYNC(ptep); 4455 cpu_tlb_flushD_SE(cdstp + va_offset); 4456 cpu_cpwait(); 4457 bzero_page(cdstp + va_offset); 4458 /* 4459 * Unmap the page. 4460 */ 4461 *ptep = 0; 4462 PTE_SYNC(ptep); 4463 cpu_tlb_flushD_SE(cdstp + va_offset); 4464 #ifdef PMAP_CACHE_VIVT 4465 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4466 #endif 4467 #ifdef PMAP_CACHE_VIPT 4468 /* 4469 * This page is now cache resident so it now has a page color. 4470 * Any contents have been obliterated so clear the EXEC flag. 4471 */ 4472 if (!pmap_is_page_colored_p(md)) { 4473 PMAPCOUNT(vac_color_new); 4474 md->pvh_attrs |= PVF_COLORED; 4475 } 4476 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4477 md->pvh_attrs &= ~PVF_EXEC; 4478 PMAPCOUNT(exec_discarded_zero); 4479 } 4480 md->pvh_attrs |= PVF_DIRTY; 4481 #endif 4482 } 4483 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4484 4485 #if ARM_MMU_XSCALE == 1 4486 void 4487 pmap_zero_page_xscale(paddr_t phys) 4488 { 4489 #ifdef DEBUG 4490 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4491 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4492 4493 if (!SLIST_EMPTY(&md->pvh_list)) 4494 panic("pmap_zero_page: page has mappings"); 4495 #endif 4496 4497 KDASSERT((phys & PGOFSET) == 0); 4498 4499 /* 4500 * Hook in the page, zero it, and purge the cache for that 4501 * zeroed page. Invalidate the TLB as needed. 4502 */ 4503 *cdst_pte = L2_S_PROTO | phys | 4504 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4505 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4506 PTE_SYNC(cdst_pte); 4507 cpu_tlb_flushD_SE(cdstp); 4508 cpu_cpwait(); 4509 bzero_page(cdstp); 4510 xscale_cache_clean_minidata(); 4511 } 4512 #endif /* ARM_MMU_XSCALE == 1 */ 4513 4514 /* pmap_pageidlezero() 4515 * 4516 * The same as above, except that we assume that the page is not 4517 * mapped. This means we never have to flush the cache first. Called 4518 * from the idle loop. 4519 */ 4520 bool 4521 pmap_pageidlezero(paddr_t phys) 4522 { 4523 unsigned int i; 4524 int *ptr; 4525 bool rv = true; 4526 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4527 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4528 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4529 #endif 4530 #ifdef PMAP_CACHE_VIPT 4531 /* Choose the last page color it had, if any */ 4532 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4533 #else 4534 const vsize_t va_offset = 0; 4535 #endif 4536 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4537 4538 4539 #ifdef DEBUG 4540 if (!SLIST_EMPTY(&md->pvh_list)) 4541 panic("pmap_pageidlezero: page has mappings"); 4542 #endif 4543 4544 KDASSERT((phys & PGOFSET) == 0); 4545 4546 /* 4547 * Hook in the page, zero it, and purge the cache for that 4548 * zeroed page. Invalidate the TLB as needed. 4549 */ 4550 *ptep = L2_S_PROTO | phys | 4551 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4552 PTE_SYNC(ptep); 4553 cpu_tlb_flushD_SE(cdstp + va_offset); 4554 cpu_cpwait(); 4555 4556 for (i = 0, ptr = (int *)(cdstp + va_offset); 4557 i < (PAGE_SIZE / sizeof(int)); i++) { 4558 if (sched_curcpu_runnable_p() != 0) { 4559 /* 4560 * A process has become ready. Abort now, 4561 * so we don't keep it waiting while we 4562 * do slow memory access to finish this 4563 * page. 4564 */ 4565 rv = false; 4566 break; 4567 } 4568 *ptr++ = 0; 4569 } 4570 4571 #ifdef PMAP_CACHE_VIVT 4572 if (rv) 4573 /* 4574 * if we aborted we'll rezero this page again later so don't 4575 * purge it unless we finished it 4576 */ 4577 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4578 #elif defined(PMAP_CACHE_VIPT) 4579 /* 4580 * This page is now cache resident so it now has a page color. 4581 * Any contents have been obliterated so clear the EXEC flag. 4582 */ 4583 if (!pmap_is_page_colored_p(md)) { 4584 PMAPCOUNT(vac_color_new); 4585 md->pvh_attrs |= PVF_COLORED; 4586 } 4587 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4588 md->pvh_attrs &= ~PVF_EXEC; 4589 PMAPCOUNT(exec_discarded_zero); 4590 } 4591 #endif 4592 /* 4593 * Unmap the page. 4594 */ 4595 *ptep = 0; 4596 PTE_SYNC(ptep); 4597 cpu_tlb_flushD_SE(cdstp + va_offset); 4598 4599 return (rv); 4600 } 4601 4602 /* 4603 * pmap_copy_page() 4604 * 4605 * Copy one physical page into another, by mapping the pages into 4606 * hook points. The same comment regarding cachability as in 4607 * pmap_zero_page also applies here. 4608 */ 4609 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4610 void 4611 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4612 { 4613 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4614 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4615 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4616 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4617 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4618 #endif 4619 #ifdef PMAP_CACHE_VIPT 4620 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4621 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4622 #else 4623 const vsize_t src_va_offset = 0; 4624 const vsize_t dst_va_offset = 0; 4625 #endif 4626 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4627 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4628 4629 #ifdef DEBUG 4630 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4631 panic("pmap_copy_page: dst page has mappings"); 4632 #endif 4633 4634 #ifdef PMAP_CACHE_VIPT 4635 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4636 #endif 4637 KDASSERT((src & PGOFSET) == 0); 4638 KDASSERT((dst & PGOFSET) == 0); 4639 4640 /* 4641 * Clean the source page. Hold the source page's lock for 4642 * the duration of the copy so that no other mappings can 4643 * be created while we have a potentially aliased mapping. 4644 */ 4645 simple_lock(&src_md->pvh_slock); 4646 #ifdef PMAP_CACHE_VIVT 4647 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4648 #endif 4649 4650 /* 4651 * Map the pages into the page hook points, copy them, and purge 4652 * the cache for the appropriate page. Invalidate the TLB 4653 * as required. 4654 */ 4655 *src_ptep = L2_S_PROTO 4656 | src 4657 #ifdef PMAP_CACHE_VIPT 4658 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4659 #endif 4660 #ifdef PMAP_CACHE_VIVT 4661 | pte_l2_s_cache_mode 4662 #endif 4663 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4664 *dst_ptep = L2_S_PROTO | dst | 4665 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4666 PTE_SYNC(src_ptep); 4667 PTE_SYNC(dst_ptep); 4668 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4669 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4670 cpu_cpwait(); 4671 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4672 #ifdef PMAP_CACHE_VIVT 4673 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4674 #endif 4675 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4676 #ifdef PMAP_CACHE_VIVT 4677 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4678 #endif 4679 /* 4680 * Unmap the pages. 4681 */ 4682 *src_ptep = 0; 4683 *dst_ptep = 0; 4684 PTE_SYNC(src_ptep); 4685 PTE_SYNC(dst_ptep); 4686 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4687 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4688 #ifdef PMAP_CACHE_VIPT 4689 /* 4690 * Now that the destination page is in the cache, mark it as colored. 4691 * If this was an exec page, discard it. 4692 */ 4693 if (!pmap_is_page_colored_p(dst_md)) { 4694 PMAPCOUNT(vac_color_new); 4695 dst_md->pvh_attrs |= PVF_COLORED; 4696 } 4697 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4698 dst_md->pvh_attrs &= ~PVF_EXEC; 4699 PMAPCOUNT(exec_discarded_copy); 4700 } 4701 dst_md->pvh_attrs |= PVF_DIRTY; 4702 #endif 4703 } 4704 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4705 4706 #if ARM_MMU_XSCALE == 1 4707 void 4708 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4709 { 4710 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4711 #ifdef DEBUG 4712 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4713 4714 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4715 panic("pmap_copy_page: dst page has mappings"); 4716 #endif 4717 4718 KDASSERT((src & PGOFSET) == 0); 4719 KDASSERT((dst & PGOFSET) == 0); 4720 4721 /* 4722 * Clean the source page. Hold the source page's lock for 4723 * the duration of the copy so that no other mappings can 4724 * be created while we have a potentially aliased mapping. 4725 */ 4726 simple_lock(&src_md->pvh_slock); 4727 #ifdef PMAP_CACHE_VIVT 4728 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4729 #endif 4730 4731 /* 4732 * Map the pages into the page hook points, copy them, and purge 4733 * the cache for the appropriate page. Invalidate the TLB 4734 * as required. 4735 */ 4736 *csrc_pte = L2_S_PROTO | src | 4737 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4738 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4739 PTE_SYNC(csrc_pte); 4740 *cdst_pte = L2_S_PROTO | dst | 4741 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4742 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4743 PTE_SYNC(cdst_pte); 4744 cpu_tlb_flushD_SE(csrcp); 4745 cpu_tlb_flushD_SE(cdstp); 4746 cpu_cpwait(); 4747 bcopy_page(csrcp, cdstp); 4748 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4749 xscale_cache_clean_minidata(); 4750 } 4751 #endif /* ARM_MMU_XSCALE == 1 */ 4752 4753 /* 4754 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4755 * 4756 * Return the start and end addresses of the kernel's virtual space. 4757 * These values are setup in pmap_bootstrap and are updated as pages 4758 * are allocated. 4759 */ 4760 void 4761 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4762 { 4763 *start = virtual_avail; 4764 *end = virtual_end; 4765 } 4766 4767 /* 4768 * Helper function for pmap_grow_l2_bucket() 4769 */ 4770 static inline int 4771 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4772 { 4773 struct l2_bucket *l2b; 4774 pt_entry_t *ptep; 4775 paddr_t pa; 4776 4777 if (uvm.page_init_done == false) { 4778 #ifdef PMAP_STEAL_MEMORY 4779 pv_addr_t pv; 4780 pmap_boot_pagealloc(PAGE_SIZE, 4781 #ifdef PMAP_CACHE_VIPT 4782 arm_cache_prefer_mask, 4783 va & arm_cache_prefer_mask, 4784 #else 4785 0, 0, 4786 #endif 4787 &pv); 4788 pa = pv.pv_pa; 4789 #else 4790 if (uvm_page_physget(&pa) == false) 4791 return (1); 4792 #endif /* PMAP_STEAL_MEMORY */ 4793 } else { 4794 struct vm_page *pg; 4795 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4796 if (pg == NULL) 4797 return (1); 4798 pa = VM_PAGE_TO_PHYS(pg); 4799 #ifdef PMAP_CACHE_VIPT 4800 #ifdef DIAGNOSTIC 4801 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4802 #endif 4803 /* 4804 * This new page must not have any mappings. Enter it via 4805 * pmap_kenter_pa and let that routine do the hard work. 4806 */ 4807 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4808 pmap_kenter_pa(va, pa, 4809 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); 4810 #endif 4811 } 4812 4813 if (pap) 4814 *pap = pa; 4815 4816 PMAPCOUNT(pt_mappings); 4817 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4818 KDASSERT(l2b != NULL); 4819 4820 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4821 *ptep = L2_S_PROTO | pa | cache_mode | 4822 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4823 PTE_SYNC(ptep); 4824 memset((void *)va, 0, PAGE_SIZE); 4825 return (0); 4826 } 4827 4828 /* 4829 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4830 * used by pmap_growkernel(). 4831 */ 4832 static inline struct l2_bucket * 4833 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4834 { 4835 struct l2_dtable *l2; 4836 struct l2_bucket *l2b; 4837 u_short l1idx; 4838 vaddr_t nva; 4839 4840 l1idx = L1_IDX(va); 4841 4842 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4843 /* 4844 * No mapping at this address, as there is 4845 * no entry in the L1 table. 4846 * Need to allocate a new l2_dtable. 4847 */ 4848 nva = pmap_kernel_l2dtable_kva; 4849 if ((nva & PGOFSET) == 0) { 4850 /* 4851 * Need to allocate a backing page 4852 */ 4853 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4854 return (NULL); 4855 } 4856 4857 l2 = (struct l2_dtable *)nva; 4858 nva += sizeof(struct l2_dtable); 4859 4860 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4861 /* 4862 * The new l2_dtable straddles a page boundary. 4863 * Map in another page to cover it. 4864 */ 4865 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4866 return (NULL); 4867 } 4868 4869 pmap_kernel_l2dtable_kva = nva; 4870 4871 /* 4872 * Link it into the parent pmap 4873 */ 4874 pm->pm_l2[L2_IDX(l1idx)] = l2; 4875 } 4876 4877 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4878 4879 /* 4880 * Fetch pointer to the L2 page table associated with the address. 4881 */ 4882 if (l2b->l2b_kva == NULL) { 4883 pt_entry_t *ptep; 4884 4885 /* 4886 * No L2 page table has been allocated. Chances are, this 4887 * is because we just allocated the l2_dtable, above. 4888 */ 4889 nva = pmap_kernel_l2ptp_kva; 4890 ptep = (pt_entry_t *)nva; 4891 if ((nva & PGOFSET) == 0) { 4892 /* 4893 * Need to allocate a backing page 4894 */ 4895 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4896 &pmap_kernel_l2ptp_phys)) 4897 return (NULL); 4898 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4899 } 4900 4901 l2->l2_occupancy++; 4902 l2b->l2b_kva = ptep; 4903 l2b->l2b_l1idx = l1idx; 4904 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4905 4906 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4907 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4908 } 4909 4910 return (l2b); 4911 } 4912 4913 vaddr_t 4914 pmap_growkernel(vaddr_t maxkvaddr) 4915 { 4916 pmap_t kpm = pmap_kernel(); 4917 struct l1_ttable *l1; 4918 struct l2_bucket *l2b; 4919 pd_entry_t *pl1pd; 4920 int s; 4921 4922 if (maxkvaddr <= pmap_curmaxkvaddr) 4923 goto out; /* we are OK */ 4924 4925 NPDEBUG(PDB_GROWKERN, 4926 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4927 pmap_curmaxkvaddr, maxkvaddr)); 4928 4929 KDASSERT(maxkvaddr <= virtual_end); 4930 4931 /* 4932 * whoops! we need to add kernel PTPs 4933 */ 4934 4935 s = splhigh(); /* to be safe */ 4936 mutex_enter(&kpm->pm_lock); 4937 4938 /* Map 1MB at a time */ 4939 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4940 4941 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4942 KDASSERT(l2b != NULL); 4943 4944 /* Distribute new L1 entry to all other L1s */ 4945 SLIST_FOREACH(l1, &l1_list, l1_link) { 4946 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4947 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4948 L1_C_PROTO; 4949 PTE_SYNC(pl1pd); 4950 } 4951 } 4952 4953 /* 4954 * flush out the cache, expensive but growkernel will happen so 4955 * rarely 4956 */ 4957 cpu_dcache_wbinv_all(); 4958 cpu_tlb_flushD(); 4959 cpu_cpwait(); 4960 4961 mutex_exit(&kpm->pm_lock); 4962 splx(s); 4963 4964 out: 4965 return (pmap_curmaxkvaddr); 4966 } 4967 4968 /************************ Utility routines ****************************/ 4969 4970 /* 4971 * vector_page_setprot: 4972 * 4973 * Manipulate the protection of the vector page. 4974 */ 4975 void 4976 vector_page_setprot(int prot) 4977 { 4978 struct l2_bucket *l2b; 4979 pt_entry_t *ptep; 4980 4981 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4982 KDASSERT(l2b != NULL); 4983 4984 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4985 4986 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4987 PTE_SYNC(ptep); 4988 cpu_tlb_flushD_SE(vector_page); 4989 cpu_cpwait(); 4990 } 4991 4992 /* 4993 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4994 * Returns true if the mapping exists, else false. 4995 * 4996 * NOTE: This function is only used by a couple of arm-specific modules. 4997 * It is not safe to take any pmap locks here, since we could be right 4998 * in the middle of debugging the pmap anyway... 4999 * 5000 * It is possible for this routine to return false even though a valid 5001 * mapping does exist. This is because we don't lock, so the metadata 5002 * state may be inconsistent. 5003 * 5004 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5005 * a "section" mapping. 5006 */ 5007 bool 5008 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5009 { 5010 struct l2_dtable *l2; 5011 pd_entry_t *pl1pd, l1pd; 5012 pt_entry_t *ptep; 5013 u_short l1idx; 5014 5015 if (pm->pm_l1 == NULL) 5016 return false; 5017 5018 l1idx = L1_IDX(va); 5019 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5020 l1pd = *pl1pd; 5021 5022 if (l1pte_section_p(l1pd)) { 5023 *ptp = NULL; 5024 return true; 5025 } 5026 5027 if (pm->pm_l2 == NULL) 5028 return false; 5029 5030 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5031 5032 if (l2 == NULL || 5033 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5034 return false; 5035 } 5036 5037 *ptp = &ptep[l2pte_index(va)]; 5038 return true; 5039 } 5040 5041 bool 5042 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5043 { 5044 u_short l1idx; 5045 5046 if (pm->pm_l1 == NULL) 5047 return false; 5048 5049 l1idx = L1_IDX(va); 5050 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5051 5052 return true; 5053 } 5054 5055 /************************ Bootstrapping routines ****************************/ 5056 5057 static void 5058 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5059 { 5060 int i; 5061 5062 l1->l1_kva = l1pt; 5063 l1->l1_domain_use_count = 0; 5064 l1->l1_domain_first = 0; 5065 5066 for (i = 0; i < PMAP_DOMAINS; i++) 5067 l1->l1_domain_free[i] = i + 1; 5068 5069 /* 5070 * Copy the kernel's L1 entries to each new L1. 5071 */ 5072 if (pmap_initialized) 5073 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5074 5075 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5076 &l1->l1_physaddr) == false) 5077 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5078 5079 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5080 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5081 } 5082 5083 /* 5084 * pmap_bootstrap() is called from the board-specific initarm() routine 5085 * once the kernel L1/L2 descriptors tables have been set up. 5086 * 5087 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5088 * spread over a number of disparate files/functions. 5089 * 5090 * We are passed the following parameters 5091 * - kernel_l1pt 5092 * This is a pointer to the base of the kernel's L1 translation table. 5093 * - vstart 5094 * 1MB-aligned start of managed kernel virtual memory. 5095 * - vend 5096 * 1MB-aligned end of managed kernel virtual memory. 5097 * 5098 * We use the first parameter to build the metadata (struct l1_ttable and 5099 * struct l2_dtable) necessary to track kernel mappings. 5100 */ 5101 #define PMAP_STATIC_L2_SIZE 16 5102 void 5103 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5104 { 5105 static struct l1_ttable static_l1; 5106 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5107 struct l1_ttable *l1 = &static_l1; 5108 struct l2_dtable *l2; 5109 struct l2_bucket *l2b; 5110 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5111 pmap_t pm = pmap_kernel(); 5112 pd_entry_t pde; 5113 pt_entry_t *ptep; 5114 paddr_t pa; 5115 vaddr_t va; 5116 vsize_t size; 5117 int nptes, l1idx, l2idx, l2next = 0; 5118 5119 /* 5120 * Initialise the kernel pmap object 5121 */ 5122 pm->pm_l1 = l1; 5123 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5124 pm->pm_activated = true; 5125 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5126 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5127 5128 /* 5129 * Scan the L1 translation table created by initarm() and create 5130 * the required metadata for all valid mappings found in it. 5131 */ 5132 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5133 pde = l1pt[l1idx]; 5134 5135 /* 5136 * We're only interested in Coarse mappings. 5137 * pmap_extract() can deal with section mappings without 5138 * recourse to checking L2 metadata. 5139 */ 5140 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5141 continue; 5142 5143 /* 5144 * Lookup the KVA of this L2 descriptor table 5145 */ 5146 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5147 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5148 if (ptep == NULL) { 5149 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5150 (u_int)l1idx << L1_S_SHIFT, pa); 5151 } 5152 5153 /* 5154 * Fetch the associated L2 metadata structure. 5155 * Allocate a new one if necessary. 5156 */ 5157 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5158 if (l2next == PMAP_STATIC_L2_SIZE) 5159 panic("pmap_bootstrap: out of static L2s"); 5160 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5161 } 5162 5163 /* 5164 * One more L1 slot tracked... 5165 */ 5166 l2->l2_occupancy++; 5167 5168 /* 5169 * Fill in the details of the L2 descriptor in the 5170 * appropriate bucket. 5171 */ 5172 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5173 l2b->l2b_kva = ptep; 5174 l2b->l2b_phys = pa; 5175 l2b->l2b_l1idx = l1idx; 5176 5177 /* 5178 * Establish an initial occupancy count for this descriptor 5179 */ 5180 for (l2idx = 0; 5181 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5182 l2idx++) { 5183 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5184 l2b->l2b_occupancy++; 5185 } 5186 } 5187 5188 /* 5189 * Make sure the descriptor itself has the correct cache mode. 5190 * If not, fix it, but whine about the problem. Port-meisters 5191 * should consider this a clue to fix up their initarm() 5192 * function. :) 5193 */ 5194 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5195 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5196 "L2 pte @ %p\n", ptep); 5197 } 5198 } 5199 5200 /* 5201 * Ensure the primary (kernel) L1 has the correct cache mode for 5202 * a page table. Bitch if it is not correctly set. 5203 */ 5204 for (va = (vaddr_t)l1pt; 5205 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5206 if (pmap_set_pt_cache_mode(l1pt, va)) 5207 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5208 "primary L1 @ 0x%lx\n", va); 5209 } 5210 5211 cpu_dcache_wbinv_all(); 5212 cpu_tlb_flushID(); 5213 cpu_cpwait(); 5214 5215 /* 5216 * now we allocate the "special" VAs which are used for tmp mappings 5217 * by the pmap (and other modules). we allocate the VAs by advancing 5218 * virtual_avail (note that there are no pages mapped at these VAs). 5219 * 5220 * Managed KVM space start from wherever initarm() tells us. 5221 */ 5222 virtual_avail = vstart; 5223 virtual_end = vend; 5224 5225 #ifdef PMAP_CACHE_VIPT 5226 /* 5227 * If we have a VIPT cache, we need one page/pte per possible alias 5228 * page so we won't violate cache aliasing rules. 5229 */ 5230 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5231 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5232 #else 5233 nptes = 1; 5234 #endif 5235 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5236 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5237 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5238 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5239 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5240 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5241 (void *)&msgbufaddr, NULL); 5242 5243 /* 5244 * Allocate a range of kernel virtual address space to be used 5245 * for L2 descriptor tables and metadata allocation in 5246 * pmap_growkernel(). 5247 */ 5248 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5249 pmap_alloc_specials(&virtual_avail, 5250 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5251 &pmap_kernel_l2ptp_kva, NULL); 5252 5253 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5254 pmap_alloc_specials(&virtual_avail, 5255 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5256 &pmap_kernel_l2dtable_kva, NULL); 5257 5258 /* 5259 * init the static-global locks and global pmap list. 5260 */ 5261 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5262 5263 /* 5264 * We can now initialise the first L1's metadata. 5265 */ 5266 SLIST_INIT(&l1_list); 5267 TAILQ_INIT(&l1_lru_list); 5268 simple_lock_init(&l1_lru_lock); 5269 pmap_init_l1(l1, l1pt); 5270 5271 /* Set up vector page L1 details, if necessary */ 5272 if (vector_page < KERNEL_BASE) { 5273 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5274 l2b = pmap_get_l2_bucket(pm, vector_page); 5275 KDASSERT(l2b != NULL); 5276 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5277 L1_C_DOM(pm->pm_domain); 5278 } else 5279 pm->pm_pl1vec = NULL; 5280 5281 /* 5282 * Initialize the pmap cache 5283 */ 5284 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5285 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5286 LIST_INIT(&pmap_pmaps); 5287 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5288 5289 /* 5290 * Initialize the pv pool. 5291 */ 5292 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5293 &pmap_bootstrap_pv_allocator, IPL_NONE); 5294 5295 /* 5296 * Initialize the L2 dtable pool and cache. 5297 */ 5298 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5299 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5300 5301 /* 5302 * Initialise the L2 descriptor table pool and cache 5303 */ 5304 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5305 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5306 pmap_l2ptp_ctor, NULL, NULL); 5307 5308 cpu_dcache_wbinv_all(); 5309 } 5310 5311 static int 5312 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5313 { 5314 pd_entry_t *pdep, pde; 5315 pt_entry_t *ptep, pte; 5316 vaddr_t pa; 5317 int rv = 0; 5318 5319 /* 5320 * Make sure the descriptor itself has the correct cache mode 5321 */ 5322 pdep = &kl1[L1_IDX(va)]; 5323 pde = *pdep; 5324 5325 if (l1pte_section_p(pde)) { 5326 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5327 *pdep = (pde & ~L1_S_CACHE_MASK) | 5328 pte_l1_s_cache_mode_pt; 5329 PTE_SYNC(pdep); 5330 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5331 rv = 1; 5332 } 5333 } else { 5334 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5335 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5336 if (ptep == NULL) 5337 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5338 5339 ptep = &ptep[l2pte_index(va)]; 5340 pte = *ptep; 5341 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5342 *ptep = (pte & ~L2_S_CACHE_MASK) | 5343 pte_l2_s_cache_mode_pt; 5344 PTE_SYNC(ptep); 5345 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5346 rv = 1; 5347 } 5348 } 5349 5350 return (rv); 5351 } 5352 5353 static void 5354 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5355 { 5356 vaddr_t va = *availp; 5357 struct l2_bucket *l2b; 5358 5359 if (ptep) { 5360 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5361 if (l2b == NULL) 5362 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5363 5364 if (ptep) 5365 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5366 } 5367 5368 *vap = va; 5369 *availp = va + (PAGE_SIZE * pages); 5370 } 5371 5372 void 5373 pmap_init(void) 5374 { 5375 5376 /* 5377 * Set the available memory vars - These do not map to real memory 5378 * addresses and cannot as the physical memory is fragmented. 5379 * They are used by ps for %mem calculations. 5380 * One could argue whether this should be the entire memory or just 5381 * the memory that is useable in a user process. 5382 */ 5383 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5384 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5385 5386 /* 5387 * Now we need to free enough pv_entry structures to allow us to get 5388 * the kmem_map/kmem_object allocated and inited (done after this 5389 * function is finished). to do this we allocate one bootstrap page out 5390 * of kernel_map and use it to provide an initial pool of pv_entry 5391 * structures. we never free this page. 5392 */ 5393 pool_setlowat(&pmap_pv_pool, 5394 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5395 5396 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5397 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5398 UVM_KMF_WIRED|UVM_KMF_ZERO); 5399 5400 pmap_initialized = true; 5401 } 5402 5403 static vaddr_t last_bootstrap_page = 0; 5404 static void *free_bootstrap_pages = NULL; 5405 5406 static void * 5407 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5408 { 5409 extern void *pool_page_alloc(struct pool *, int); 5410 vaddr_t new_page; 5411 void *rv; 5412 5413 if (pmap_initialized) 5414 return (pool_page_alloc(pp, flags)); 5415 5416 if (free_bootstrap_pages) { 5417 rv = free_bootstrap_pages; 5418 free_bootstrap_pages = *((void **)rv); 5419 return (rv); 5420 } 5421 5422 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5423 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5424 5425 KASSERT(new_page > last_bootstrap_page); 5426 last_bootstrap_page = new_page; 5427 return ((void *)new_page); 5428 } 5429 5430 static void 5431 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5432 { 5433 extern void pool_page_free(struct pool *, void *); 5434 5435 if ((vaddr_t)v <= last_bootstrap_page) { 5436 *((void **)v) = free_bootstrap_pages; 5437 free_bootstrap_pages = v; 5438 return; 5439 } 5440 5441 if (pmap_initialized) { 5442 pool_page_free(pp, v); 5443 return; 5444 } 5445 } 5446 5447 /* 5448 * pmap_postinit() 5449 * 5450 * This routine is called after the vm and kmem subsystems have been 5451 * initialised. This allows the pmap code to perform any initialisation 5452 * that can only be done one the memory allocation is in place. 5453 */ 5454 void 5455 pmap_postinit(void) 5456 { 5457 extern paddr_t physical_start, physical_end; 5458 struct l2_bucket *l2b; 5459 struct l1_ttable *l1; 5460 struct pglist plist; 5461 struct vm_page *m; 5462 pd_entry_t *pl1pt; 5463 pt_entry_t *ptep, pte; 5464 vaddr_t va, eva; 5465 u_int loop, needed; 5466 int error; 5467 5468 pool_cache_setlowat(&pmap_l2ptp_cache, 5469 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5470 pool_cache_setlowat(&pmap_l2dtable_cache, 5471 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5472 5473 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5474 needed -= 1; 5475 5476 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5477 5478 for (loop = 0; loop < needed; loop++, l1++) { 5479 /* Allocate a L1 page table */ 5480 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5481 if (va == 0) 5482 panic("Cannot allocate L1 KVM"); 5483 5484 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5485 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5486 if (error) 5487 panic("Cannot allocate L1 physical pages"); 5488 5489 m = TAILQ_FIRST(&plist); 5490 eva = va + L1_TABLE_SIZE; 5491 pl1pt = (pd_entry_t *)va; 5492 5493 while (m && va < eva) { 5494 paddr_t pa = VM_PAGE_TO_PHYS(m); 5495 5496 pmap_kenter_pa(va, pa, 5497 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); 5498 5499 /* 5500 * Make sure the L1 descriptor table is mapped 5501 * with the cache-mode set to write-through. 5502 */ 5503 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5504 KDASSERT(l2b != NULL); 5505 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5506 pte = *ptep; 5507 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5508 *ptep = pte; 5509 PTE_SYNC(ptep); 5510 cpu_tlb_flushD_SE(va); 5511 5512 va += PAGE_SIZE; 5513 m = TAILQ_NEXT(m, pageq.queue); 5514 } 5515 5516 #ifdef DIAGNOSTIC 5517 if (m) 5518 panic("pmap_alloc_l1pt: pglist not empty"); 5519 #endif /* DIAGNOSTIC */ 5520 5521 pmap_init_l1(l1, pl1pt); 5522 } 5523 5524 #ifdef DEBUG 5525 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5526 needed); 5527 #endif 5528 } 5529 5530 /* 5531 * Note that the following routines are used by board-specific initialisation 5532 * code to configure the initial kernel page tables. 5533 * 5534 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5535 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5536 * behaviour of the old pmap, and provides an easy migration path for 5537 * initial bring-up of the new pmap on existing ports. Fortunately, 5538 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5539 * will be deprecated. 5540 * 5541 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5542 * tables. 5543 */ 5544 5545 /* 5546 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5547 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5548 * find them as necessary. 5549 * 5550 * Note that the data on this list MUST remain valid after initarm() returns, 5551 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5552 */ 5553 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5554 5555 static vaddr_t 5556 kernel_pt_lookup(paddr_t pa) 5557 { 5558 pv_addr_t *pv; 5559 5560 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5561 #ifndef ARM32_NEW_VM_LAYOUT 5562 if (pv->pv_pa == (pa & ~PGOFSET)) 5563 return (pv->pv_va | (pa & PGOFSET)); 5564 #else 5565 if (pv->pv_pa == pa) 5566 return (pv->pv_va); 5567 #endif 5568 } 5569 return (0); 5570 } 5571 5572 /* 5573 * pmap_map_section: 5574 * 5575 * Create a single section mapping. 5576 */ 5577 void 5578 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5579 { 5580 pd_entry_t *pde = (pd_entry_t *) l1pt; 5581 pd_entry_t fl; 5582 5583 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5584 5585 switch (cache) { 5586 case PTE_NOCACHE: 5587 default: 5588 fl = 0; 5589 break; 5590 5591 case PTE_CACHE: 5592 fl = pte_l1_s_cache_mode; 5593 break; 5594 5595 case PTE_PAGETABLE: 5596 fl = pte_l1_s_cache_mode_pt; 5597 break; 5598 } 5599 5600 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5601 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5602 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5603 } 5604 5605 /* 5606 * pmap_map_entry: 5607 * 5608 * Create a single page mapping. 5609 */ 5610 void 5611 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5612 { 5613 pd_entry_t *pde = (pd_entry_t *) l1pt; 5614 pt_entry_t fl; 5615 pt_entry_t *pte; 5616 5617 KASSERT(((va | pa) & PGOFSET) == 0); 5618 5619 switch (cache) { 5620 case PTE_NOCACHE: 5621 default: 5622 fl = 0; 5623 break; 5624 5625 case PTE_CACHE: 5626 fl = pte_l2_s_cache_mode; 5627 break; 5628 5629 case PTE_PAGETABLE: 5630 fl = pte_l2_s_cache_mode_pt; 5631 break; 5632 } 5633 5634 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5635 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5636 5637 #ifndef ARM32_NEW_VM_LAYOUT 5638 pte = (pt_entry_t *) 5639 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5640 #else 5641 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5642 #endif 5643 if (pte == NULL) 5644 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5645 5646 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5647 #ifndef ARM32_NEW_VM_LAYOUT 5648 pte += (va >> PGSHIFT) & 0x3ff; 5649 #else 5650 pte += l2pte_index(va); 5651 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5652 #endif 5653 *pte = fl; 5654 PTE_SYNC(pte); 5655 } 5656 5657 /* 5658 * pmap_link_l2pt: 5659 * 5660 * Link the L2 page table specified by "l2pv" into the L1 5661 * page table at the slot for "va". 5662 */ 5663 void 5664 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5665 { 5666 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5667 u_int slot = va >> L1_S_SHIFT; 5668 5669 #ifndef ARM32_NEW_VM_LAYOUT 5670 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5671 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5672 #endif 5673 5674 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5675 5676 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5677 #ifdef ARM32_NEW_VM_LAYOUT 5678 PTE_SYNC(&pde[slot]); 5679 #else 5680 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5681 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5682 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5683 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5684 #endif 5685 5686 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5687 } 5688 5689 /* 5690 * pmap_map_chunk: 5691 * 5692 * Map a chunk of memory using the most efficient mappings 5693 * possible (section, large page, small page) into the 5694 * provided L1 and L2 tables at the specified virtual address. 5695 */ 5696 vsize_t 5697 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5698 int prot, int cache) 5699 { 5700 pd_entry_t *pde = (pd_entry_t *) l1pt; 5701 pt_entry_t *pte, f1, f2s, f2l; 5702 vsize_t resid; 5703 int i; 5704 5705 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5706 5707 if (l1pt == 0) 5708 panic("pmap_map_chunk: no L1 table provided"); 5709 5710 #ifdef VERBOSE_INIT_ARM 5711 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5712 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5713 #endif 5714 5715 switch (cache) { 5716 case PTE_NOCACHE: 5717 default: 5718 f1 = 0; 5719 f2l = 0; 5720 f2s = 0; 5721 break; 5722 5723 case PTE_CACHE: 5724 f1 = pte_l1_s_cache_mode; 5725 f2l = pte_l2_l_cache_mode; 5726 f2s = pte_l2_s_cache_mode; 5727 break; 5728 5729 case PTE_PAGETABLE: 5730 f1 = pte_l1_s_cache_mode_pt; 5731 f2l = pte_l2_l_cache_mode_pt; 5732 f2s = pte_l2_s_cache_mode_pt; 5733 break; 5734 } 5735 5736 size = resid; 5737 5738 while (resid > 0) { 5739 /* See if we can use a section mapping. */ 5740 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5741 #ifdef VERBOSE_INIT_ARM 5742 printf("S"); 5743 #endif 5744 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5745 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5746 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5747 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5748 va += L1_S_SIZE; 5749 pa += L1_S_SIZE; 5750 resid -= L1_S_SIZE; 5751 continue; 5752 } 5753 5754 /* 5755 * Ok, we're going to use an L2 table. Make sure 5756 * one is actually in the corresponding L1 slot 5757 * for the current VA. 5758 */ 5759 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5760 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5761 5762 #ifndef ARM32_NEW_VM_LAYOUT 5763 pte = (pt_entry_t *) 5764 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5765 #else 5766 pte = (pt_entry_t *) kernel_pt_lookup( 5767 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5768 #endif 5769 if (pte == NULL) 5770 panic("pmap_map_chunk: can't find L2 table for VA" 5771 "0x%08lx", va); 5772 5773 /* See if we can use a L2 large page mapping. */ 5774 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5775 #ifdef VERBOSE_INIT_ARM 5776 printf("L"); 5777 #endif 5778 for (i = 0; i < 16; i++) { 5779 #ifndef ARM32_NEW_VM_LAYOUT 5780 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5781 L2_L_PROTO | pa | 5782 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5783 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5784 #else 5785 pte[l2pte_index(va) + i] = 5786 L2_L_PROTO | pa | 5787 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5788 PTE_SYNC(&pte[l2pte_index(va) + i]); 5789 #endif 5790 } 5791 va += L2_L_SIZE; 5792 pa += L2_L_SIZE; 5793 resid -= L2_L_SIZE; 5794 continue; 5795 } 5796 5797 /* Use a small page mapping. */ 5798 #ifdef VERBOSE_INIT_ARM 5799 printf("P"); 5800 #endif 5801 #ifndef ARM32_NEW_VM_LAYOUT 5802 pte[(va >> PGSHIFT) & 0x3ff] = 5803 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5804 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5805 #else 5806 pte[l2pte_index(va)] = 5807 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5808 PTE_SYNC(&pte[l2pte_index(va)]); 5809 #endif 5810 va += PAGE_SIZE; 5811 pa += PAGE_SIZE; 5812 resid -= PAGE_SIZE; 5813 } 5814 #ifdef VERBOSE_INIT_ARM 5815 printf("\n"); 5816 #endif 5817 return (size); 5818 } 5819 5820 /********************** Static device map routines ***************************/ 5821 5822 static const struct pmap_devmap *pmap_devmap_table; 5823 5824 /* 5825 * Register the devmap table. This is provided in case early console 5826 * initialization needs to register mappings created by bootstrap code 5827 * before pmap_devmap_bootstrap() is called. 5828 */ 5829 void 5830 pmap_devmap_register(const struct pmap_devmap *table) 5831 { 5832 5833 pmap_devmap_table = table; 5834 } 5835 5836 /* 5837 * Map all of the static regions in the devmap table, and remember 5838 * the devmap table so other parts of the kernel can look up entries 5839 * later. 5840 */ 5841 void 5842 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5843 { 5844 int i; 5845 5846 pmap_devmap_table = table; 5847 5848 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5849 #ifdef VERBOSE_INIT_ARM 5850 printf("devmap: %08lx -> %08lx @ %08lx\n", 5851 pmap_devmap_table[i].pd_pa, 5852 pmap_devmap_table[i].pd_pa + 5853 pmap_devmap_table[i].pd_size - 1, 5854 pmap_devmap_table[i].pd_va); 5855 #endif 5856 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5857 pmap_devmap_table[i].pd_pa, 5858 pmap_devmap_table[i].pd_size, 5859 pmap_devmap_table[i].pd_prot, 5860 pmap_devmap_table[i].pd_cache); 5861 } 5862 } 5863 5864 const struct pmap_devmap * 5865 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5866 { 5867 uint64_t endpa; 5868 int i; 5869 5870 if (pmap_devmap_table == NULL) 5871 return (NULL); 5872 5873 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5874 5875 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5876 if (pa >= pmap_devmap_table[i].pd_pa && 5877 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5878 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5879 return (&pmap_devmap_table[i]); 5880 } 5881 5882 return (NULL); 5883 } 5884 5885 const struct pmap_devmap * 5886 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5887 { 5888 int i; 5889 5890 if (pmap_devmap_table == NULL) 5891 return (NULL); 5892 5893 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5894 if (va >= pmap_devmap_table[i].pd_va && 5895 va + size - 1 <= pmap_devmap_table[i].pd_va + 5896 pmap_devmap_table[i].pd_size - 1) 5897 return (&pmap_devmap_table[i]); 5898 } 5899 5900 return (NULL); 5901 } 5902 5903 /********************** PTE initialization routines **************************/ 5904 5905 /* 5906 * These routines are called when the CPU type is identified to set up 5907 * the PTE prototypes, cache modes, etc. 5908 * 5909 * The variables are always here, just in case modules need to reference 5910 * them (though, they shouldn't). 5911 */ 5912 5913 pt_entry_t pte_l1_s_cache_mode; 5914 pt_entry_t pte_l1_s_cache_mode_pt; 5915 pt_entry_t pte_l1_s_cache_mask; 5916 5917 pt_entry_t pte_l2_l_cache_mode; 5918 pt_entry_t pte_l2_l_cache_mode_pt; 5919 pt_entry_t pte_l2_l_cache_mask; 5920 5921 pt_entry_t pte_l2_s_cache_mode; 5922 pt_entry_t pte_l2_s_cache_mode_pt; 5923 pt_entry_t pte_l2_s_cache_mask; 5924 5925 pt_entry_t pte_l2_s_prot_u; 5926 pt_entry_t pte_l2_s_prot_w; 5927 pt_entry_t pte_l2_s_prot_mask; 5928 5929 pt_entry_t pte_l1_s_proto; 5930 pt_entry_t pte_l1_c_proto; 5931 pt_entry_t pte_l2_s_proto; 5932 5933 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5934 void (*pmap_zero_page_func)(paddr_t); 5935 5936 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5937 void 5938 pmap_pte_init_generic(void) 5939 { 5940 5941 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5942 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5943 5944 pte_l2_l_cache_mode = L2_B|L2_C; 5945 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5946 5947 pte_l2_s_cache_mode = L2_B|L2_C; 5948 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5949 5950 /* 5951 * If we have a write-through cache, set B and C. If 5952 * we have a write-back cache, then we assume setting 5953 * only C will make those pages write-through. 5954 */ 5955 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5956 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5957 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5958 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5959 } else { 5960 #if ARM_MMU_V6 > 1 5961 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5962 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5963 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5964 #else 5965 pte_l1_s_cache_mode_pt = L1_S_C; 5966 pte_l2_l_cache_mode_pt = L2_C; 5967 pte_l2_s_cache_mode_pt = L2_C; 5968 #endif 5969 } 5970 5971 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5972 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5973 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5974 5975 pte_l1_s_proto = L1_S_PROTO_generic; 5976 pte_l1_c_proto = L1_C_PROTO_generic; 5977 pte_l2_s_proto = L2_S_PROTO_generic; 5978 5979 pmap_copy_page_func = pmap_copy_page_generic; 5980 pmap_zero_page_func = pmap_zero_page_generic; 5981 } 5982 5983 #if defined(CPU_ARM8) 5984 void 5985 pmap_pte_init_arm8(void) 5986 { 5987 5988 /* 5989 * ARM8 is compatible with generic, but we need to use 5990 * the page tables uncached. 5991 */ 5992 pmap_pte_init_generic(); 5993 5994 pte_l1_s_cache_mode_pt = 0; 5995 pte_l2_l_cache_mode_pt = 0; 5996 pte_l2_s_cache_mode_pt = 0; 5997 } 5998 #endif /* CPU_ARM8 */ 5999 6000 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6001 void 6002 pmap_pte_init_arm9(void) 6003 { 6004 6005 /* 6006 * ARM9 is compatible with generic, but we want to use 6007 * write-through caching for now. 6008 */ 6009 pmap_pte_init_generic(); 6010 6011 pte_l1_s_cache_mode = L1_S_C; 6012 pte_l2_l_cache_mode = L2_C; 6013 pte_l2_s_cache_mode = L2_C; 6014 6015 pte_l1_s_cache_mode_pt = L1_S_C; 6016 pte_l2_l_cache_mode_pt = L2_C; 6017 pte_l2_s_cache_mode_pt = L2_C; 6018 } 6019 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6020 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6021 6022 #if defined(CPU_ARM10) 6023 void 6024 pmap_pte_init_arm10(void) 6025 { 6026 6027 /* 6028 * ARM10 is compatible with generic, but we want to use 6029 * write-through caching for now. 6030 */ 6031 pmap_pte_init_generic(); 6032 6033 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6034 pte_l2_l_cache_mode = L2_B | L2_C; 6035 pte_l2_s_cache_mode = L2_B | L2_C; 6036 6037 pte_l1_s_cache_mode_pt = L1_S_C; 6038 pte_l2_l_cache_mode_pt = L2_C; 6039 pte_l2_s_cache_mode_pt = L2_C; 6040 6041 } 6042 #endif /* CPU_ARM10 */ 6043 6044 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6045 void 6046 pmap_pte_init_arm11(void) 6047 { 6048 6049 /* 6050 * ARM11 is compatible with generic, but we want to use 6051 * write-through caching for now. 6052 */ 6053 pmap_pte_init_generic(); 6054 6055 pte_l1_s_cache_mode = L1_S_C; 6056 pte_l2_l_cache_mode = L2_C; 6057 pte_l2_s_cache_mode = L2_C; 6058 6059 pte_l1_s_cache_mode_pt = L1_S_C; 6060 pte_l2_l_cache_mode_pt = L2_C; 6061 pte_l2_s_cache_mode_pt = L2_C; 6062 } 6063 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6064 6065 #if ARM_MMU_SA1 == 1 6066 void 6067 pmap_pte_init_sa1(void) 6068 { 6069 6070 /* 6071 * The StrongARM SA-1 cache does not have a write-through 6072 * mode. So, do the generic initialization, then reset 6073 * the page table cache mode to B=1,C=1, and note that 6074 * the PTEs need to be sync'd. 6075 */ 6076 pmap_pte_init_generic(); 6077 6078 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6079 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6080 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6081 6082 pmap_needs_pte_sync = 1; 6083 } 6084 #endif /* ARM_MMU_SA1 == 1*/ 6085 6086 #if ARM_MMU_XSCALE == 1 6087 #if (ARM_NMMUS > 1) 6088 static u_int xscale_use_minidata; 6089 #endif 6090 6091 void 6092 pmap_pte_init_xscale(void) 6093 { 6094 uint32_t auxctl; 6095 int write_through = 0; 6096 6097 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6098 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6099 6100 pte_l2_l_cache_mode = L2_B|L2_C; 6101 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6102 6103 pte_l2_s_cache_mode = L2_B|L2_C; 6104 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6105 6106 pte_l1_s_cache_mode_pt = L1_S_C; 6107 pte_l2_l_cache_mode_pt = L2_C; 6108 pte_l2_s_cache_mode_pt = L2_C; 6109 6110 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6111 /* 6112 * The XScale core has an enhanced mode where writes that 6113 * miss the cache cause a cache line to be allocated. This 6114 * is significantly faster than the traditional, write-through 6115 * behavior of this case. 6116 */ 6117 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6118 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6119 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6120 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6121 6122 #ifdef XSCALE_CACHE_WRITE_THROUGH 6123 /* 6124 * Some versions of the XScale core have various bugs in 6125 * their cache units, the work-around for which is to run 6126 * the cache in write-through mode. Unfortunately, this 6127 * has a major (negative) impact on performance. So, we 6128 * go ahead and run fast-and-loose, in the hopes that we 6129 * don't line up the planets in a way that will trip the 6130 * bugs. 6131 * 6132 * However, we give you the option to be slow-but-correct. 6133 */ 6134 write_through = 1; 6135 #elif defined(XSCALE_CACHE_WRITE_BACK) 6136 /* force write back cache mode */ 6137 write_through = 0; 6138 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6139 /* 6140 * Intel PXA2[15]0 processors are known to have a bug in 6141 * write-back cache on revision 4 and earlier (stepping 6142 * A[01] and B[012]). Fixed for C0 and later. 6143 */ 6144 { 6145 uint32_t id, type; 6146 6147 id = cpufunc_id(); 6148 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6149 6150 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6151 if ((id & CPU_ID_REVISION_MASK) < 5) { 6152 /* write through for stepping A0-1 and B0-2 */ 6153 write_through = 1; 6154 } 6155 } 6156 } 6157 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6158 6159 if (write_through) { 6160 pte_l1_s_cache_mode = L1_S_C; 6161 pte_l2_l_cache_mode = L2_C; 6162 pte_l2_s_cache_mode = L2_C; 6163 } 6164 6165 #if (ARM_NMMUS > 1) 6166 xscale_use_minidata = 1; 6167 #endif 6168 6169 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6170 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6171 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6172 6173 pte_l1_s_proto = L1_S_PROTO_xscale; 6174 pte_l1_c_proto = L1_C_PROTO_xscale; 6175 pte_l2_s_proto = L2_S_PROTO_xscale; 6176 6177 pmap_copy_page_func = pmap_copy_page_xscale; 6178 pmap_zero_page_func = pmap_zero_page_xscale; 6179 6180 /* 6181 * Disable ECC protection of page table access, for now. 6182 */ 6183 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6184 auxctl &= ~XSCALE_AUXCTL_P; 6185 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6186 } 6187 6188 /* 6189 * xscale_setup_minidata: 6190 * 6191 * Set up the mini-data cache clean area. We require the 6192 * caller to allocate the right amount of physically and 6193 * virtually contiguous space. 6194 */ 6195 void 6196 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6197 { 6198 extern vaddr_t xscale_minidata_clean_addr; 6199 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6200 pd_entry_t *pde = (pd_entry_t *) l1pt; 6201 pt_entry_t *pte; 6202 vsize_t size; 6203 uint32_t auxctl; 6204 6205 xscale_minidata_clean_addr = va; 6206 6207 /* Round it to page size. */ 6208 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6209 6210 for (; size != 0; 6211 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6212 #ifndef ARM32_NEW_VM_LAYOUT 6213 pte = (pt_entry_t *) 6214 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6215 #else 6216 pte = (pt_entry_t *) kernel_pt_lookup( 6217 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6218 #endif 6219 if (pte == NULL) 6220 panic("xscale_setup_minidata: can't find L2 table for " 6221 "VA 0x%08lx", va); 6222 #ifndef ARM32_NEW_VM_LAYOUT 6223 pte[(va >> PGSHIFT) & 0x3ff] = 6224 #else 6225 pte[l2pte_index(va)] = 6226 #endif 6227 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6228 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6229 } 6230 6231 /* 6232 * Configure the mini-data cache for write-back with 6233 * read/write-allocate. 6234 * 6235 * NOTE: In order to reconfigure the mini-data cache, we must 6236 * make sure it contains no valid data! In order to do that, 6237 * we must issue a global data cache invalidate command! 6238 * 6239 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6240 * THIS IS VERY IMPORTANT! 6241 */ 6242 6243 /* Invalidate data and mini-data. */ 6244 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6245 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6246 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6247 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6248 } 6249 6250 /* 6251 * Change the PTEs for the specified kernel mappings such that they 6252 * will use the mini data cache instead of the main data cache. 6253 */ 6254 void 6255 pmap_uarea(vaddr_t va) 6256 { 6257 struct l2_bucket *l2b; 6258 pt_entry_t *ptep, *sptep, pte; 6259 vaddr_t next_bucket, eva; 6260 6261 #if (ARM_NMMUS > 1) 6262 if (xscale_use_minidata == 0) 6263 return; 6264 #endif 6265 6266 eva = va + USPACE; 6267 6268 while (va < eva) { 6269 next_bucket = L2_NEXT_BUCKET(va); 6270 if (next_bucket > eva) 6271 next_bucket = eva; 6272 6273 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6274 KDASSERT(l2b != NULL); 6275 6276 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6277 6278 while (va < next_bucket) { 6279 pte = *ptep; 6280 if (!l2pte_minidata(pte)) { 6281 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6282 cpu_tlb_flushD_SE(va); 6283 *ptep = pte & ~L2_B; 6284 } 6285 ptep++; 6286 va += PAGE_SIZE; 6287 } 6288 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6289 } 6290 cpu_cpwait(); 6291 } 6292 #endif /* ARM_MMU_XSCALE == 1 */ 6293 6294 /* 6295 * return the PA of the current L1 table, for use when handling a crash dump 6296 */ 6297 uint32_t pmap_kernel_L1_addr(void) 6298 { 6299 return pmap_kernel()->pm_l1->l1_physaddr; 6300 } 6301 6302 #if defined(DDB) 6303 /* 6304 * A couple of ddb-callable functions for dumping pmaps 6305 */ 6306 void pmap_dump_all(void); 6307 void pmap_dump(pmap_t); 6308 6309 void 6310 pmap_dump_all(void) 6311 { 6312 pmap_t pm; 6313 6314 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6315 if (pm == pmap_kernel()) 6316 continue; 6317 pmap_dump(pm); 6318 printf("\n"); 6319 } 6320 } 6321 6322 static pt_entry_t ncptes[64]; 6323 static void pmap_dump_ncpg(pmap_t); 6324 6325 void 6326 pmap_dump(pmap_t pm) 6327 { 6328 struct l2_dtable *l2; 6329 struct l2_bucket *l2b; 6330 pt_entry_t *ptep, pte; 6331 vaddr_t l2_va, l2b_va, va; 6332 int i, j, k, occ, rows = 0; 6333 6334 if (pm == pmap_kernel()) 6335 printf("pmap_kernel (%p): ", pm); 6336 else 6337 printf("user pmap (%p): ", pm); 6338 6339 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6340 6341 l2_va = 0; 6342 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6343 l2 = pm->pm_l2[i]; 6344 6345 if (l2 == NULL || l2->l2_occupancy == 0) 6346 continue; 6347 6348 l2b_va = l2_va; 6349 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6350 l2b = &l2->l2_bucket[j]; 6351 6352 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6353 continue; 6354 6355 ptep = l2b->l2b_kva; 6356 6357 for (k = 0; k < 256 && ptep[k] == 0; k++) 6358 ; 6359 6360 k &= ~63; 6361 occ = l2b->l2b_occupancy; 6362 va = l2b_va + (k * 4096); 6363 for (; k < 256; k++, va += 0x1000) { 6364 char ch = ' '; 6365 if ((k % 64) == 0) { 6366 if ((rows % 8) == 0) { 6367 printf( 6368 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6369 } 6370 printf("%08lx: ", va); 6371 } 6372 6373 ncptes[k & 63] = 0; 6374 pte = ptep[k]; 6375 if (pte == 0) { 6376 ch = '.'; 6377 } else { 6378 occ--; 6379 switch (pte & 0x0c) { 6380 case 0x00: 6381 ch = 'D'; /* No cache No buff */ 6382 break; 6383 case 0x04: 6384 ch = 'B'; /* No cache buff */ 6385 break; 6386 case 0x08: 6387 if (pte & 0x40) 6388 ch = 'm'; 6389 else 6390 ch = 'C'; /* Cache No buff */ 6391 break; 6392 case 0x0c: 6393 ch = 'F'; /* Cache Buff */ 6394 break; 6395 } 6396 6397 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6398 ch += 0x20; 6399 6400 if ((pte & 0xc) == 0) 6401 ncptes[k & 63] = pte; 6402 } 6403 6404 if ((k % 64) == 63) { 6405 rows++; 6406 printf("%c\n", ch); 6407 pmap_dump_ncpg(pm); 6408 if (occ == 0) 6409 break; 6410 } else 6411 printf("%c", ch); 6412 } 6413 } 6414 } 6415 } 6416 6417 static void 6418 pmap_dump_ncpg(pmap_t pm) 6419 { 6420 struct vm_page *pg; 6421 struct vm_page_md *md; 6422 struct pv_entry *pv; 6423 int i; 6424 6425 for (i = 0; i < 63; i++) { 6426 if (ncptes[i] == 0) 6427 continue; 6428 6429 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6430 if (pg == NULL) 6431 continue; 6432 md = VM_PAGE_TO_MD(pg); 6433 6434 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6435 VM_PAGE_TO_PHYS(pg), 6436 md->krw_mappings, md->kro_mappings, 6437 md->urw_mappings, md->uro_mappings); 6438 6439 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6440 printf(" %c va 0x%08lx, flags 0x%x\n", 6441 (pm == pv->pv_pmap) ? '*' : ' ', 6442 pv->pv_va, pv->pv_flags); 6443 } 6444 } 6445 } 6446 #endif 6447 6448 #ifdef PMAP_STEAL_MEMORY 6449 void 6450 pmap_boot_pageadd(pv_addr_t *newpv) 6451 { 6452 pv_addr_t *pv, *npv; 6453 6454 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6455 if (newpv->pv_pa < pv->pv_va) { 6456 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6457 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6458 newpv->pv_size += pv->pv_size; 6459 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6460 } 6461 pv = NULL; 6462 } else { 6463 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6464 pv = npv) { 6465 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6466 KASSERT(pv->pv_pa < newpv->pv_pa); 6467 if (newpv->pv_pa > npv->pv_pa) 6468 continue; 6469 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6470 pv->pv_size += newpv->pv_size; 6471 return; 6472 } 6473 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6474 break; 6475 newpv->pv_size += npv->pv_size; 6476 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6477 SLIST_REMOVE_AFTER(newpv, pv_list); 6478 return; 6479 } 6480 } 6481 } 6482 6483 if (pv) { 6484 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6485 } else { 6486 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6487 } 6488 } 6489 6490 void 6491 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6492 pv_addr_t *rpv) 6493 { 6494 pv_addr_t *pv, **pvp; 6495 struct vm_physseg *ps; 6496 size_t i; 6497 6498 KASSERT(amount & PGOFSET); 6499 KASSERT((mask & PGOFSET) == 0); 6500 KASSERT((match & PGOFSET) == 0); 6501 KASSERT(amount != 0); 6502 6503 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6504 (pv = *pvp) != NULL; 6505 pvp = &SLIST_NEXT(pv, pv_list)) { 6506 pv_addr_t *newpv; 6507 psize_t off; 6508 /* 6509 * If this entry is too small to satify the request... 6510 */ 6511 KASSERT(pv->pv_size > 0); 6512 if (pv->pv_size < amount) 6513 continue; 6514 6515 for (off = 0; off <= mask; off += PAGE_SIZE) { 6516 if (((pv->pv_pa + off) & mask) == match 6517 && off + amount <= pv->pv_size) 6518 break; 6519 } 6520 if (off > mask) 6521 continue; 6522 6523 rpv->pv_va = pv->pv_va + off; 6524 rpv->pv_pa = pv->pv_pa + off; 6525 rpv->pv_size = amount; 6526 pv->pv_size -= amount; 6527 if (pv->pv_size == 0) { 6528 KASSERT(off == 0); 6529 KASSERT((vaddr_t) pv == rpv->pv_va); 6530 *pvp = SLIST_NEXT(pv, pv_list); 6531 } else if (off == 0) { 6532 KASSERT((vaddr_t) pv == rpv->pv_va); 6533 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6534 *newpv = *pv; 6535 newpv->pv_pa += amount; 6536 newpv->pv_va += amount; 6537 *pvp = newpv; 6538 } else if (off < pv->pv_size) { 6539 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6540 *newpv = *pv; 6541 newpv->pv_size -= off; 6542 newpv->pv_pa += off + amount; 6543 newpv->pv_va += off + amount; 6544 6545 SLIST_NEXT(pv, pv_list) = newpv; 6546 pv->pv_size = off; 6547 } else { 6548 KASSERT((vaddr_t) pv != rpv->pv_va); 6549 } 6550 memset((void *)rpv->pv_va, 0, amount); 6551 return; 6552 } 6553 6554 if (vm_nphysseg == 0) 6555 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6556 6557 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6558 (pv = *pvp) != NULL; 6559 pvp = &SLIST_NEXT(pv, pv_list)) { 6560 if (SLIST_NEXT(pv, pv_list) == NULL) 6561 break; 6562 } 6563 KASSERT(mask == 0); 6564 for (i = 0; i < vm_nphysseg; i++) { 6565 ps = vm_physmem_ptrs[i]; 6566 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6567 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6568 rpv->pv_va = pv->pv_va; 6569 rpv->pv_pa = pv->pv_pa; 6570 rpv->pv_size = amount; 6571 *pvp = NULL; 6572 pmap_map_chunk(kernel_l1pt.pv_va, 6573 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6574 ptoa(ps->avail_start), 6575 amount - pv->pv_size, 6576 VM_PROT_READ|VM_PROT_WRITE, 6577 PTE_CACHE); 6578 ps->avail_start += atop(amount - pv->pv_size); 6579 /* 6580 * If we consumed the entire physseg, remove it. 6581 */ 6582 if (ps->avail_start == ps->avail_end) { 6583 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6584 ps[0] = ps[1]; 6585 } 6586 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6587 return; 6588 } 6589 } 6590 6591 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6592 } 6593 6594 vaddr_t 6595 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6596 { 6597 pv_addr_t pv; 6598 6599 pmap_boot_pagealloc(size, 0, 0, &pv); 6600 6601 return pv.pv_va; 6602 } 6603 #endif /* PMAP_STEAL_MEMORY */ 6604 6605 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6606 { 6607 sysctl_createv(clog, 0, NULL, NULL, 6608 CTLFLAG_PERMANENT, 6609 CTLTYPE_NODE, "machdep", NULL, 6610 NULL, 0, NULL, 0, 6611 CTL_MACHDEP, CTL_EOL); 6612 6613 sysctl_createv(clog, 0, NULL, NULL, 6614 CTLFLAG_PERMANENT, 6615 CTLTYPE_INT, "kmpages", 6616 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6617 NULL, 0, &pmap_kmpages, 0, 6618 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6619 } 6620
Indexes created Thu Oct 23 22:10:10 GMT 2025