pmap.c revision 1.211.2.23
1 /* $NetBSD: pmap.c,v 1.211.2.23 2010/11/15 15:11:53 uebayasi Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/pool.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <machine/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.211.2.23 2010/11/15 15:11:53 uebayasi Exp $"); 215 216 #define VM_PAGE_TO_MD(pg) (&(pg)->mdpage) 217 218 #ifdef PMAP_DEBUG 219 220 /* XXX need to get rid of all refs to this */ 221 int pmap_debug_level = 0; 222 223 /* 224 * for switching to potentially finer grained debugging 225 */ 226 #define PDB_FOLLOW 0x0001 227 #define PDB_INIT 0x0002 228 #define PDB_ENTER 0x0004 229 #define PDB_REMOVE 0x0008 230 #define PDB_CREATE 0x0010 231 #define PDB_PTPAGE 0x0020 232 #define PDB_GROWKERN 0x0040 233 #define PDB_BITS 0x0080 234 #define PDB_COLLECT 0x0100 235 #define PDB_PROTECT 0x0200 236 #define PDB_MAP_L1 0x0400 237 #define PDB_BOOTSTRAP 0x1000 238 #define PDB_PARANOIA 0x2000 239 #define PDB_WIRING 0x4000 240 #define PDB_PVDUMP 0x8000 241 #define PDB_VAC 0x10000 242 #define PDB_KENTER 0x20000 243 #define PDB_KREMOVE 0x40000 244 #define PDB_EXEC 0x80000 245 246 int debugmap = 1; 247 int pmapdebug = 0; 248 #define NPDEBUG(_lev_,_stat_) \ 249 if (pmapdebug & (_lev_)) \ 250 ((_stat_)) 251 252 #else /* PMAP_DEBUG */ 253 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 254 #endif /* PMAP_DEBUG */ 255 256 /* 257 * pmap_kernel() points here 258 */ 259 static struct pmap kernel_pmap_store; 260 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 261 262 /* 263 * Which pmap is currently 'live' in the cache 264 * 265 * XXXSCW: Fix for SMP ... 266 */ 267 static pmap_t pmap_recent_user; 268 269 /* 270 * Pointer to last active lwp, or NULL if it exited. 271 */ 272 struct lwp *pmap_previous_active_lwp; 273 274 /* 275 * Pool and cache that pmap structures are allocated from. 276 * We use a cache to avoid clearing the pm_l2[] array (1KB) 277 * in pmap_create(). 278 */ 279 static struct pool_cache pmap_cache; 280 static LIST_HEAD(, pmap) pmap_pmaps; 281 282 /* 283 * Pool of PV structures 284 */ 285 static struct pool pmap_pv_pool; 286 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 287 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 288 static struct pool_allocator pmap_bootstrap_pv_allocator = { 289 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 290 }; 291 292 /* 293 * Pool and cache of l2_dtable structures. 294 * We use a cache to avoid clearing the structures when they're 295 * allocated. (196 bytes) 296 */ 297 static struct pool_cache pmap_l2dtable_cache; 298 static vaddr_t pmap_kernel_l2dtable_kva; 299 300 /* 301 * Pool and cache of L2 page descriptors. 302 * We use a cache to avoid clearing the descriptor table 303 * when they're allocated. (1KB) 304 */ 305 static struct pool_cache pmap_l2ptp_cache; 306 static vaddr_t pmap_kernel_l2ptp_kva; 307 static paddr_t pmap_kernel_l2ptp_phys; 308 309 #ifdef PMAPCOUNTERS 310 #define PMAP_EVCNT_INITIALIZER(name) \ 311 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 312 313 #ifdef PMAP_CACHE_VIPT 314 static struct evcnt pmap_ev_vac_clean_one = 315 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_one = 317 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_lots = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 320 static struct evcnt pmap_ev_vac_flush_lots2 = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 326 327 static struct evcnt pmap_ev_vac_color_new = 328 PMAP_EVCNT_INITIALIZER("new page color"); 329 static struct evcnt pmap_ev_vac_color_reuse = 330 PMAP_EVCNT_INITIALIZER("ok first page color"); 331 static struct evcnt pmap_ev_vac_color_ok = 332 PMAP_EVCNT_INITIALIZER("ok page color"); 333 static struct evcnt pmap_ev_vac_color_blind = 334 PMAP_EVCNT_INITIALIZER("blind page color"); 335 static struct evcnt pmap_ev_vac_color_change = 336 PMAP_EVCNT_INITIALIZER("change page color"); 337 static struct evcnt pmap_ev_vac_color_erase = 338 PMAP_EVCNT_INITIALIZER("erase page color"); 339 static struct evcnt pmap_ev_vac_color_none = 340 PMAP_EVCNT_INITIALIZER("no page color"); 341 static struct evcnt pmap_ev_vac_color_restore = 342 PMAP_EVCNT_INITIALIZER("restore page color"); 343 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 352 #endif 353 354 static struct evcnt pmap_ev_mappings = 355 PMAP_EVCNT_INITIALIZER("pages mapped"); 356 static struct evcnt pmap_ev_unmappings = 357 PMAP_EVCNT_INITIALIZER("pages unmapped"); 358 static struct evcnt pmap_ev_remappings = 359 PMAP_EVCNT_INITIALIZER("pages remapped"); 360 361 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 362 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 363 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 364 365 static struct evcnt pmap_ev_kernel_mappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 367 static struct evcnt pmap_ev_kernel_unmappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 369 static struct evcnt pmap_ev_kernel_remappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 371 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 373 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 375 376 static struct evcnt pmap_ev_kenter_mappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 378 static struct evcnt pmap_ev_kenter_unmappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 380 static struct evcnt pmap_ev_kenter_remappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 382 static struct evcnt pmap_ev_pt_mappings = 383 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 384 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 389 390 #ifdef PMAP_CACHE_VIPT 391 static struct evcnt pmap_ev_exec_mappings = 392 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 393 static struct evcnt pmap_ev_exec_cached = 394 PMAP_EVCNT_INITIALIZER("exec pages cached"); 395 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 397 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 398 399 static struct evcnt pmap_ev_exec_synced = 400 PMAP_EVCNT_INITIALIZER("exec pages synced"); 401 static struct evcnt pmap_ev_exec_synced_map = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 403 static struct evcnt pmap_ev_exec_synced_unmap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 405 static struct evcnt pmap_ev_exec_synced_remap = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 407 static struct evcnt pmap_ev_exec_synced_clearbit = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 409 static struct evcnt pmap_ev_exec_synced_kremove = 410 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 411 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 418 419 static struct evcnt pmap_ev_exec_discarded_unmap = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 421 static struct evcnt pmap_ev_exec_discarded_zero = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 423 static struct evcnt pmap_ev_exec_discarded_copy = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 425 static struct evcnt pmap_ev_exec_discarded_page_protect = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 427 static struct evcnt pmap_ev_exec_discarded_clearbit = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 429 static struct evcnt pmap_ev_exec_discarded_kremove = 430 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 431 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 438 #endif /* PMAP_CACHE_VIPT */ 439 440 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 441 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 442 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 443 444 EVCNT_ATTACH_STATIC(pmap_ev_updates); 445 EVCNT_ATTACH_STATIC(pmap_ev_collects); 446 EVCNT_ATTACH_STATIC(pmap_ev_activations); 447 448 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 449 #else 450 #define PMAPCOUNT(x) ((void)0) 451 #endif 452 453 /* 454 * pmap copy/zero page, and mem(5) hook point 455 */ 456 static pt_entry_t *csrc_pte, *cdst_pte; 457 static vaddr_t csrcp, cdstp; 458 vaddr_t memhook; /* used by mem.c */ 459 kmutex_t memlock; /* used by mem.c */ 460 void *zeropage; /* used by mem.c */ 461 extern void *msgbufaddr; 462 int pmap_kmpages; 463 /* 464 * Flag to indicate if pmap_init() has done its thing 465 */ 466 bool pmap_initialized; 467 468 /* 469 * Misc. locking data structures 470 */ 471 472 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 473 static struct lock pmap_main_lock; 474 475 #define PMAP_MAP_TO_HEAD_LOCK() \ 476 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 477 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 478 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 479 #define PMAP_HEAD_TO_MAP_LOCK() \ 480 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 481 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 482 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 483 #else 484 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 485 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 486 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 487 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 488 #endif 489 490 #define pmap_acquire_pmap_lock(pm) \ 491 do { \ 492 if ((pm) != pmap_kernel()) \ 493 mutex_enter(&(pm)->pm_lock); \ 494 } while (/*CONSTCOND*/0) 495 496 #define pmap_release_pmap_lock(pm) \ 497 do { \ 498 if ((pm) != pmap_kernel()) \ 499 mutex_exit(&(pm)->pm_lock); \ 500 } while (/*CONSTCOND*/0) 501 502 503 /* 504 * Metadata for L1 translation tables. 505 */ 506 struct l1_ttable { 507 /* Entry on the L1 Table list */ 508 SLIST_ENTRY(l1_ttable) l1_link; 509 510 /* Entry on the L1 Least Recently Used list */ 511 TAILQ_ENTRY(l1_ttable) l1_lru; 512 513 /* Track how many domains are allocated from this L1 */ 514 volatile u_int l1_domain_use_count; 515 516 /* 517 * A free-list of domain numbers for this L1. 518 * We avoid using ffs() and a bitmap to track domains since ffs() 519 * is slow on ARM. 520 */ 521 u_int8_t l1_domain_first; 522 u_int8_t l1_domain_free[PMAP_DOMAINS]; 523 524 /* Physical address of this L1 page table */ 525 paddr_t l1_physaddr; 526 527 /* KVA of this L1 page table */ 528 pd_entry_t *l1_kva; 529 }; 530 531 /* 532 * Convert a virtual address into its L1 table index. That is, the 533 * index used to locate the L2 descriptor table pointer in an L1 table. 534 * This is basically used to index l1->l1_kva[]. 535 * 536 * Each L2 descriptor table represents 1MB of VA space. 537 */ 538 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 539 540 /* 541 * L1 Page Tables are tracked using a Least Recently Used list. 542 * - New L1s are allocated from the HEAD. 543 * - Freed L1s are added to the TAIl. 544 * - Recently accessed L1s (where an 'access' is some change to one of 545 * the userland pmaps which owns this L1) are moved to the TAIL. 546 */ 547 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 548 static struct simplelock l1_lru_lock; 549 550 /* 551 * A list of all L1 tables 552 */ 553 static SLIST_HEAD(, l1_ttable) l1_list; 554 555 /* 556 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 557 * 558 * This is normally 16MB worth L2 page descriptors for any given pmap. 559 * Reference counts are maintained for L2 descriptors so they can be 560 * freed when empty. 561 */ 562 struct l2_dtable { 563 /* The number of L2 page descriptors allocated to this l2_dtable */ 564 u_int l2_occupancy; 565 566 /* List of L2 page descriptors */ 567 struct l2_bucket { 568 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 569 paddr_t l2b_phys; /* Physical address of same */ 570 u_short l2b_l1idx; /* This L2 table's L1 index */ 571 u_short l2b_occupancy; /* How many active descriptors */ 572 } l2_bucket[L2_BUCKET_SIZE]; 573 }; 574 575 /* 576 * Given an L1 table index, calculate the corresponding l2_dtable index 577 * and bucket index within the l2_dtable. 578 */ 579 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 580 (L2_SIZE - 1)) 581 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 582 583 /* 584 * Given a virtual address, this macro returns the 585 * virtual address required to drop into the next L2 bucket. 586 */ 587 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 588 589 /* 590 * L2 allocation. 591 */ 592 #define pmap_alloc_l2_dtable() \ 593 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 594 #define pmap_free_l2_dtable(l2) \ 595 pool_cache_put(&pmap_l2dtable_cache, (l2)) 596 #define pmap_alloc_l2_ptp(pap) \ 597 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 598 PR_NOWAIT, (pap))) 599 600 /* 601 * We try to map the page tables write-through, if possible. However, not 602 * all CPUs have a write-through cache mode, so on those we have to sync 603 * the cache when we frob page tables. 604 * 605 * We try to evaluate this at compile time, if possible. However, it's 606 * not always possible to do that, hence this run-time var. 607 */ 608 int pmap_needs_pte_sync; 609 610 /* 611 * Real definition of pv_entry. 612 */ 613 struct pv_entry { 614 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 615 pmap_t pv_pmap; /* pmap where mapping lies */ 616 vaddr_t pv_va; /* virtual address for mapping */ 617 u_int pv_flags; /* flags */ 618 }; 619 620 /* 621 * Macro to determine if a mapping might be resident in the 622 * instruction cache and/or TLB 623 */ 624 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 625 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 626 627 /* 628 * Macro to determine if a mapping might be resident in the 629 * data cache and/or TLB 630 */ 631 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 632 633 /* 634 * Local prototypes 635 */ 636 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 637 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 638 pt_entry_t **); 639 static bool pmap_is_current(pmap_t); 640 static bool pmap_is_cached(pmap_t); 641 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 642 pmap_t, vaddr_t, u_int); 643 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 644 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 645 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 646 u_int, u_int); 647 648 static void pmap_pinit(pmap_t); 649 static int pmap_pmap_ctor(void *, void *, int); 650 651 static void pmap_alloc_l1(pmap_t); 652 static void pmap_free_l1(pmap_t); 653 static void pmap_use_l1(pmap_t); 654 655 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 656 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 657 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 658 static int pmap_l2ptp_ctor(void *, void *, int); 659 static int pmap_l2dtable_ctor(void *, void *, int); 660 661 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 662 #ifdef PMAP_CACHE_VIVT 663 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 664 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 665 #endif 666 667 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 668 #ifdef PMAP_CACHE_VIVT 669 static int pmap_clean_page(struct pv_entry *, bool); 670 #endif 671 #ifdef PMAP_CACHE_VIPT 672 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 673 enum pmap_flush_op { 674 PMAP_FLUSH_PRIMARY, 675 PMAP_FLUSH_SECONDARY, 676 PMAP_CLEAN_PRIMARY 677 }; 678 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 679 #endif 680 static void pmap_page_remove(struct vm_page_md *, paddr_t); 681 682 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 683 static vaddr_t kernel_pt_lookup(paddr_t); 684 685 686 /* 687 * External function prototypes 688 */ 689 extern void bzero_page(vaddr_t); 690 extern void bcopy_page(vaddr_t, vaddr_t); 691 692 /* 693 * Misc variables 694 */ 695 vaddr_t virtual_avail; 696 vaddr_t virtual_end; 697 vaddr_t pmap_curmaxkvaddr; 698 699 paddr_t avail_start; 700 paddr_t avail_end; 701 702 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 703 pv_addr_t kernelpages; 704 pv_addr_t kernel_l1pt; 705 pv_addr_t systempage; 706 707 /* Function to set the debug level of the pmap code */ 708 709 #ifdef PMAP_DEBUG 710 void 711 pmap_debug(int level) 712 { 713 pmap_debug_level = level; 714 printf("pmap_debug: level=%d\n", pmap_debug_level); 715 } 716 #endif /* PMAP_DEBUG */ 717 718 /* 719 * A bunch of routines to conditionally flush the caches/TLB depending 720 * on whether the specified pmap actually needs to be flushed at any 721 * given time. 722 */ 723 static inline void 724 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 725 { 726 727 if (pm->pm_cstate.cs_tlb_id) 728 cpu_tlb_flushID_SE(va); 729 } 730 731 static inline void 732 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 733 { 734 735 if (pm->pm_cstate.cs_tlb_d) 736 cpu_tlb_flushD_SE(va); 737 } 738 739 static inline void 740 pmap_tlb_flushID(pmap_t pm) 741 { 742 743 if (pm->pm_cstate.cs_tlb_id) { 744 cpu_tlb_flushID(); 745 pm->pm_cstate.cs_tlb = 0; 746 } 747 } 748 749 static inline void 750 pmap_tlb_flushD(pmap_t pm) 751 { 752 753 if (pm->pm_cstate.cs_tlb_d) { 754 cpu_tlb_flushD(); 755 pm->pm_cstate.cs_tlb_d = 0; 756 } 757 } 758 759 #ifdef PMAP_CACHE_VIVT 760 static inline void 761 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 762 { 763 if (pm->pm_cstate.cs_cache_id) { 764 cpu_idcache_wbinv_range(va, len); 765 } 766 } 767 768 static inline void 769 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 770 bool do_inv, bool rd_only) 771 { 772 773 if (pm->pm_cstate.cs_cache_d) { 774 if (do_inv) { 775 if (rd_only) 776 cpu_dcache_inv_range(va, len); 777 else 778 cpu_dcache_wbinv_range(va, len); 779 } else 780 if (!rd_only) 781 cpu_dcache_wb_range(va, len); 782 } 783 } 784 785 static inline void 786 pmap_idcache_wbinv_all(pmap_t pm) 787 { 788 if (pm->pm_cstate.cs_cache_id) { 789 cpu_idcache_wbinv_all(); 790 pm->pm_cstate.cs_cache = 0; 791 } 792 } 793 794 static inline void 795 pmap_dcache_wbinv_all(pmap_t pm) 796 { 797 if (pm->pm_cstate.cs_cache_d) { 798 cpu_dcache_wbinv_all(); 799 pm->pm_cstate.cs_cache_d = 0; 800 } 801 } 802 #endif /* PMAP_CACHE_VIVT */ 803 804 static inline bool 805 pmap_is_current(pmap_t pm) 806 { 807 808 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 809 return true; 810 811 return false; 812 } 813 814 static inline bool 815 pmap_is_cached(pmap_t pm) 816 { 817 818 if (pm == pmap_kernel() || pmap_recent_user == NULL || 819 pmap_recent_user == pm) 820 return (true); 821 822 return false; 823 } 824 825 /* 826 * PTE_SYNC_CURRENT: 827 * 828 * Make sure the pte is written out to RAM. 829 * We need to do this for one of two cases: 830 * - We're dealing with the kernel pmap 831 * - There is no pmap active in the cache/tlb. 832 * - The specified pmap is 'active' in the cache/tlb. 833 */ 834 #ifdef PMAP_INCLUDE_PTE_SYNC 835 #define PTE_SYNC_CURRENT(pm, ptep) \ 836 do { \ 837 if (PMAP_NEEDS_PTE_SYNC && \ 838 pmap_is_cached(pm)) \ 839 PTE_SYNC(ptep); \ 840 } while (/*CONSTCOND*/0) 841 #else 842 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 843 #endif 844 845 /* 846 * main pv_entry manipulation functions: 847 * pmap_enter_pv: enter a mapping onto a vm_page list 848 * pmap_remove_pv: remove a mappiing from a vm_page list 849 * 850 * NOTE: pmap_enter_pv expects to lock the pvh itself 851 * pmap_remove_pv expects te caller to lock the pvh before calling 852 */ 853 854 /* 855 * pmap_enter_pv: enter a mapping onto a vm_page lst 856 * 857 * => caller should hold the proper lock on pmap_main_lock 858 * => caller should have pmap locked 859 * => we will gain the lock on the vm_page and allocate the new pv_entry 860 * => caller should adjust ptp's wire_count before calling 861 * => caller should not adjust pmap's wire_count 862 */ 863 static void 864 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 865 vaddr_t va, u_int flags) 866 { 867 struct pv_entry **pvp; 868 869 NPDEBUG(PDB_PVDUMP, 870 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 871 872 pv->pv_pmap = pm; 873 pv->pv_va = va; 874 pv->pv_flags = flags; 875 876 simple_lock(&md->pvh_slock); /* lock vm_page */ 877 pvp = &SLIST_FIRST(&md->pvh_list); 878 #ifdef PMAP_CACHE_VIPT 879 /* 880 * Insert unmanaged entries, writeable first, at the head of 881 * the pv list. 882 */ 883 if (__predict_true((flags & PVF_KENTRY) == 0)) { 884 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 885 pvp = &SLIST_NEXT(*pvp, pv_link); 886 } else if ((flags & PVF_WRITE) == 0) { 887 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 888 pvp = &SLIST_NEXT(*pvp, pv_link); 889 } 890 #endif 891 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 892 *pvp = pv; /* ... locked list */ 893 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 894 #ifdef PMAP_CACHE_VIPT 895 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 896 md->pvh_attrs |= PVF_KMOD; 897 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 898 md->pvh_attrs |= PVF_DIRTY; 899 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 900 #endif 901 if (pm == pmap_kernel()) { 902 PMAPCOUNT(kernel_mappings); 903 if (flags & PVF_WRITE) 904 md->krw_mappings++; 905 else 906 md->kro_mappings++; 907 } else { 908 if (flags & PVF_WRITE) 909 md->urw_mappings++; 910 else 911 md->uro_mappings++; 912 } 913 914 #ifdef PMAP_CACHE_VIPT 915 /* 916 * If this is an exec mapping and its the first exec mapping 917 * for this page, make sure to sync the I-cache. 918 */ 919 if (PV_IS_EXEC_P(flags)) { 920 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 921 pmap_syncicache_page(md, pa); 922 PMAPCOUNT(exec_synced_map); 923 } 924 PMAPCOUNT(exec_mappings); 925 } 926 #endif 927 928 PMAPCOUNT(mappings); 929 simple_unlock(&md->pvh_slock); /* unlock, done! */ 930 931 if (pv->pv_flags & PVF_WIRED) 932 ++pm->pm_stats.wired_count; 933 } 934 935 /* 936 * 937 * pmap_find_pv: Find a pv entry 938 * 939 * => caller should hold lock on vm_page 940 */ 941 static inline struct pv_entry * 942 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 943 { 944 struct pv_entry *pv; 945 946 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 947 if (pm == pv->pv_pmap && va == pv->pv_va) 948 break; 949 } 950 951 return (pv); 952 } 953 954 /* 955 * pmap_remove_pv: try to remove a mapping from a pv_list 956 * 957 * => caller should hold proper lock on pmap_main_lock 958 * => pmap should be locked 959 * => caller should hold lock on vm_page [so that attrs can be adjusted] 960 * => caller should adjust ptp's wire_count and free PTP if needed 961 * => caller should NOT adjust pmap's wire_count 962 * => we return the removed pv 963 */ 964 static struct pv_entry * 965 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 966 { 967 struct pv_entry *pv, **prevptr; 968 969 NPDEBUG(PDB_PVDUMP, 970 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 971 972 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 973 pv = *prevptr; 974 975 while (pv) { 976 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 977 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 978 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 979 if (pv->pv_flags & PVF_WIRED) { 980 --pm->pm_stats.wired_count; 981 } 982 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 983 if (pm == pmap_kernel()) { 984 PMAPCOUNT(kernel_unmappings); 985 if (pv->pv_flags & PVF_WRITE) 986 md->krw_mappings--; 987 else 988 md->kro_mappings--; 989 } else { 990 if (pv->pv_flags & PVF_WRITE) 991 md->urw_mappings--; 992 else 993 md->uro_mappings--; 994 } 995 996 PMAPCOUNT(unmappings); 997 #ifdef PMAP_CACHE_VIPT 998 if (!(pv->pv_flags & PVF_WRITE)) 999 break; 1000 /* 1001 * If this page has had an exec mapping, then if 1002 * this was the last mapping, discard the contents, 1003 * otherwise sync the i-cache for this page. 1004 */ 1005 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1006 if (SLIST_EMPTY(&md->pvh_list)) { 1007 md->pvh_attrs &= ~PVF_EXEC; 1008 PMAPCOUNT(exec_discarded_unmap); 1009 } else { 1010 pmap_syncicache_page(md, pa); 1011 PMAPCOUNT(exec_synced_unmap); 1012 } 1013 } 1014 #endif /* PMAP_CACHE_VIPT */ 1015 break; 1016 } 1017 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1018 pv = *prevptr; /* advance */ 1019 } 1020 1021 #ifdef PMAP_CACHE_VIPT 1022 /* 1023 * If we no longer have a WRITEABLE KENTRY at the head of list, 1024 * clear the KMOD attribute from the page. 1025 */ 1026 if (SLIST_FIRST(&md->pvh_list) == NULL 1027 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1028 md->pvh_attrs &= ~PVF_KMOD; 1029 1030 /* 1031 * If this was a writeable page and there are no more writeable 1032 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1033 * the contents to memory. 1034 */ 1035 if (md->krw_mappings + md->urw_mappings == 0) 1036 md->pvh_attrs &= ~PVF_WRITE; 1037 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1038 #endif /* PMAP_CACHE_VIPT */ 1039 1040 return(pv); /* return removed pv */ 1041 } 1042 1043 /* 1044 * 1045 * pmap_modify_pv: Update pv flags 1046 * 1047 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1048 * => caller should NOT adjust pmap's wire_count 1049 * => caller must call pmap_vac_me_harder() if writable status of a page 1050 * may have changed. 1051 * => we return the old flags 1052 * 1053 * Modify a physical-virtual mapping in the pv table 1054 */ 1055 static u_int 1056 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1057 u_int clr_mask, u_int set_mask) 1058 { 1059 struct pv_entry *npv; 1060 u_int flags, oflags; 1061 1062 KASSERT((clr_mask & PVF_KENTRY) == 0); 1063 KASSERT((set_mask & PVF_KENTRY) == 0); 1064 1065 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1066 return (0); 1067 1068 NPDEBUG(PDB_PVDUMP, 1069 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1070 1071 /* 1072 * There is at least one VA mapping this page. 1073 */ 1074 1075 if (clr_mask & (PVF_REF | PVF_MOD)) { 1076 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1077 #ifdef PMAP_CACHE_VIPT 1078 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1079 md->pvh_attrs |= PVF_DIRTY; 1080 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1081 #endif 1082 } 1083 1084 oflags = npv->pv_flags; 1085 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1086 1087 if ((flags ^ oflags) & PVF_WIRED) { 1088 if (flags & PVF_WIRED) 1089 ++pm->pm_stats.wired_count; 1090 else 1091 --pm->pm_stats.wired_count; 1092 } 1093 1094 if ((flags ^ oflags) & PVF_WRITE) { 1095 if (pm == pmap_kernel()) { 1096 if (flags & PVF_WRITE) { 1097 md->krw_mappings++; 1098 md->kro_mappings--; 1099 } else { 1100 md->kro_mappings++; 1101 md->krw_mappings--; 1102 } 1103 } else { 1104 if (flags & PVF_WRITE) { 1105 md->urw_mappings++; 1106 md->uro_mappings--; 1107 } else { 1108 md->uro_mappings++; 1109 md->urw_mappings--; 1110 } 1111 } 1112 } 1113 #ifdef PMAP_CACHE_VIPT 1114 if (md->urw_mappings + md->krw_mappings == 0) 1115 md->pvh_attrs &= ~PVF_WRITE; 1116 /* 1117 * We have two cases here: the first is from enter_pv (new exec 1118 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1119 * Since in latter, pmap_enter_pv won't do anything, we just have 1120 * to do what pmap_remove_pv would do. 1121 */ 1122 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1123 || (PV_IS_EXEC_P(md->pvh_attrs) 1124 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1125 pmap_syncicache_page(md, pa); 1126 PMAPCOUNT(exec_synced_remap); 1127 } 1128 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1129 #endif 1130 1131 PMAPCOUNT(remappings); 1132 1133 return (oflags); 1134 } 1135 1136 /* 1137 * Allocate an L1 translation table for the specified pmap. 1138 * This is called at pmap creation time. 1139 */ 1140 static void 1141 pmap_alloc_l1(pmap_t pm) 1142 { 1143 struct l1_ttable *l1; 1144 u_int8_t domain; 1145 1146 /* 1147 * Remove the L1 at the head of the LRU list 1148 */ 1149 simple_lock(&l1_lru_lock); 1150 l1 = TAILQ_FIRST(&l1_lru_list); 1151 KDASSERT(l1 != NULL); 1152 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1153 1154 /* 1155 * Pick the first available domain number, and update 1156 * the link to the next number. 1157 */ 1158 domain = l1->l1_domain_first; 1159 l1->l1_domain_first = l1->l1_domain_free[domain]; 1160 1161 /* 1162 * If there are still free domain numbers in this L1, 1163 * put it back on the TAIL of the LRU list. 1164 */ 1165 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1166 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1167 1168 simple_unlock(&l1_lru_lock); 1169 1170 /* 1171 * Fix up the relevant bits in the pmap structure 1172 */ 1173 pm->pm_l1 = l1; 1174 pm->pm_domain = domain; 1175 } 1176 1177 /* 1178 * Free an L1 translation table. 1179 * This is called at pmap destruction time. 1180 */ 1181 static void 1182 pmap_free_l1(pmap_t pm) 1183 { 1184 struct l1_ttable *l1 = pm->pm_l1; 1185 1186 simple_lock(&l1_lru_lock); 1187 1188 /* 1189 * If this L1 is currently on the LRU list, remove it. 1190 */ 1191 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1192 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1193 1194 /* 1195 * Free up the domain number which was allocated to the pmap 1196 */ 1197 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1198 l1->l1_domain_first = pm->pm_domain; 1199 l1->l1_domain_use_count--; 1200 1201 /* 1202 * The L1 now must have at least 1 free domain, so add 1203 * it back to the LRU list. If the use count is zero, 1204 * put it at the head of the list, otherwise it goes 1205 * to the tail. 1206 */ 1207 if (l1->l1_domain_use_count == 0) 1208 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1209 else 1210 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1211 1212 simple_unlock(&l1_lru_lock); 1213 } 1214 1215 static inline void 1216 pmap_use_l1(pmap_t pm) 1217 { 1218 struct l1_ttable *l1; 1219 1220 /* 1221 * Do nothing if we're in interrupt context. 1222 * Access to an L1 by the kernel pmap must not affect 1223 * the LRU list. 1224 */ 1225 if (cpu_intr_p() || pm == pmap_kernel()) 1226 return; 1227 1228 l1 = pm->pm_l1; 1229 1230 /* 1231 * If the L1 is not currently on the LRU list, just return 1232 */ 1233 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1234 return; 1235 1236 simple_lock(&l1_lru_lock); 1237 1238 /* 1239 * Check the use count again, now that we've acquired the lock 1240 */ 1241 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1242 simple_unlock(&l1_lru_lock); 1243 return; 1244 } 1245 1246 /* 1247 * Move the L1 to the back of the LRU list 1248 */ 1249 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1250 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1251 1252 simple_unlock(&l1_lru_lock); 1253 } 1254 1255 /* 1256 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1257 * 1258 * Free an L2 descriptor table. 1259 */ 1260 static inline void 1261 #ifndef PMAP_INCLUDE_PTE_SYNC 1262 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1263 #else 1264 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1265 #endif 1266 { 1267 #ifdef PMAP_INCLUDE_PTE_SYNC 1268 #ifdef PMAP_CACHE_VIVT 1269 /* 1270 * Note: With a write-back cache, we may need to sync this 1271 * L2 table before re-using it. 1272 * This is because it may have belonged to a non-current 1273 * pmap, in which case the cache syncs would have been 1274 * skipped for the pages that were being unmapped. If the 1275 * L2 table were then to be immediately re-allocated to 1276 * the *current* pmap, it may well contain stale mappings 1277 * which have not yet been cleared by a cache write-back 1278 * and so would still be visible to the mmu. 1279 */ 1280 if (need_sync) 1281 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1282 #endif /* PMAP_CACHE_VIVT */ 1283 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1284 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1285 } 1286 1287 /* 1288 * Returns a pointer to the L2 bucket associated with the specified pmap 1289 * and VA, or NULL if no L2 bucket exists for the address. 1290 */ 1291 static inline struct l2_bucket * 1292 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1293 { 1294 struct l2_dtable *l2; 1295 struct l2_bucket *l2b; 1296 u_short l1idx; 1297 1298 l1idx = L1_IDX(va); 1299 1300 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1301 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1302 return (NULL); 1303 1304 return (l2b); 1305 } 1306 1307 /* 1308 * Returns a pointer to the L2 bucket associated with the specified pmap 1309 * and VA. 1310 * 1311 * If no L2 bucket exists, perform the necessary allocations to put an L2 1312 * bucket/page table in place. 1313 * 1314 * Note that if a new L2 bucket/page was allocated, the caller *must* 1315 * increment the bucket occupancy counter appropriately *before* 1316 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1317 * the bucket/page in the meantime. 1318 */ 1319 static struct l2_bucket * 1320 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1321 { 1322 struct l2_dtable *l2; 1323 struct l2_bucket *l2b; 1324 u_short l1idx; 1325 1326 l1idx = L1_IDX(va); 1327 1328 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1329 /* 1330 * No mapping at this address, as there is 1331 * no entry in the L1 table. 1332 * Need to allocate a new l2_dtable. 1333 */ 1334 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1335 return (NULL); 1336 1337 /* 1338 * Link it into the parent pmap 1339 */ 1340 pm->pm_l2[L2_IDX(l1idx)] = l2; 1341 } 1342 1343 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1344 1345 /* 1346 * Fetch pointer to the L2 page table associated with the address. 1347 */ 1348 if (l2b->l2b_kva == NULL) { 1349 pt_entry_t *ptep; 1350 1351 /* 1352 * No L2 page table has been allocated. Chances are, this 1353 * is because we just allocated the l2_dtable, above. 1354 */ 1355 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1356 /* 1357 * Oops, no more L2 page tables available at this 1358 * time. We may need to deallocate the l2_dtable 1359 * if we allocated a new one above. 1360 */ 1361 if (l2->l2_occupancy == 0) { 1362 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1363 pmap_free_l2_dtable(l2); 1364 } 1365 return (NULL); 1366 } 1367 1368 l2->l2_occupancy++; 1369 l2b->l2b_kva = ptep; 1370 l2b->l2b_l1idx = l1idx; 1371 } 1372 1373 return (l2b); 1374 } 1375 1376 /* 1377 * One or more mappings in the specified L2 descriptor table have just been 1378 * invalidated. 1379 * 1380 * Garbage collect the metadata and descriptor table itself if necessary. 1381 * 1382 * The pmap lock must be acquired when this is called (not necessary 1383 * for the kernel pmap). 1384 */ 1385 static void 1386 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1387 { 1388 struct l2_dtable *l2; 1389 pd_entry_t *pl1pd, l1pd; 1390 pt_entry_t *ptep; 1391 u_short l1idx; 1392 1393 KDASSERT(count <= l2b->l2b_occupancy); 1394 1395 /* 1396 * Update the bucket's reference count according to how many 1397 * PTEs the caller has just invalidated. 1398 */ 1399 l2b->l2b_occupancy -= count; 1400 1401 /* 1402 * Note: 1403 * 1404 * Level 2 page tables allocated to the kernel pmap are never freed 1405 * as that would require checking all Level 1 page tables and 1406 * removing any references to the Level 2 page table. See also the 1407 * comment elsewhere about never freeing bootstrap L2 descriptors. 1408 * 1409 * We make do with just invalidating the mapping in the L2 table. 1410 * 1411 * This isn't really a big deal in practice and, in fact, leads 1412 * to a performance win over time as we don't need to continually 1413 * alloc/free. 1414 */ 1415 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1416 return; 1417 1418 /* 1419 * There are no more valid mappings in this level 2 page table. 1420 * Go ahead and NULL-out the pointer in the bucket, then 1421 * free the page table. 1422 */ 1423 l1idx = l2b->l2b_l1idx; 1424 ptep = l2b->l2b_kva; 1425 l2b->l2b_kva = NULL; 1426 1427 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1428 1429 /* 1430 * If the L1 slot matches the pmap's domain 1431 * number, then invalidate it. 1432 */ 1433 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1434 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1435 *pl1pd = 0; 1436 PTE_SYNC(pl1pd); 1437 } 1438 1439 /* 1440 * Release the L2 descriptor table back to the pool cache. 1441 */ 1442 #ifndef PMAP_INCLUDE_PTE_SYNC 1443 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1444 #else 1445 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1446 #endif 1447 1448 /* 1449 * Update the reference count in the associated l2_dtable 1450 */ 1451 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1452 if (--l2->l2_occupancy > 0) 1453 return; 1454 1455 /* 1456 * There are no more valid mappings in any of the Level 1 1457 * slots managed by this l2_dtable. Go ahead and NULL-out 1458 * the pointer in the parent pmap and free the l2_dtable. 1459 */ 1460 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1461 pmap_free_l2_dtable(l2); 1462 } 1463 1464 /* 1465 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1466 * structures. 1467 */ 1468 static int 1469 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1470 { 1471 #ifndef PMAP_INCLUDE_PTE_SYNC 1472 struct l2_bucket *l2b; 1473 pt_entry_t *ptep, pte; 1474 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1475 1476 /* 1477 * The mappings for these page tables were initially made using 1478 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1479 * mode will not be right for page table mappings. To avoid 1480 * polluting the pmap_kenter_pa() code with a special case for 1481 * page tables, we simply fix up the cache-mode here if it's not 1482 * correct. 1483 */ 1484 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1485 KDASSERT(l2b != NULL); 1486 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1487 pte = *ptep; 1488 1489 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1490 /* 1491 * Page tables must have the cache-mode set to Write-Thru. 1492 */ 1493 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1494 PTE_SYNC(ptep); 1495 cpu_tlb_flushD_SE(va); 1496 cpu_cpwait(); 1497 } 1498 #endif 1499 1500 memset(v, 0, L2_TABLE_SIZE_REAL); 1501 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1502 return (0); 1503 } 1504 1505 static int 1506 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1507 { 1508 1509 memset(v, 0, sizeof(struct l2_dtable)); 1510 return (0); 1511 } 1512 1513 static int 1514 pmap_pmap_ctor(void *arg, void *v, int flags) 1515 { 1516 1517 memset(v, 0, sizeof(struct pmap)); 1518 return (0); 1519 } 1520 1521 static void 1522 pmap_pinit(pmap_t pm) 1523 { 1524 struct l2_bucket *l2b; 1525 1526 if (vector_page < KERNEL_BASE) { 1527 /* 1528 * Map the vector page. 1529 */ 1530 pmap_enter(pm, vector_page, systempage.pv_pa, 1531 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1532 pmap_update(pm); 1533 1534 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1535 l2b = pmap_get_l2_bucket(pm, vector_page); 1536 KDASSERT(l2b != NULL); 1537 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1538 L1_C_DOM(pm->pm_domain); 1539 } else 1540 pm->pm_pl1vec = NULL; 1541 } 1542 1543 #ifdef PMAP_CACHE_VIVT 1544 /* 1545 * Since we have a virtually indexed cache, we may need to inhibit caching if 1546 * there is more than one mapping and at least one of them is writable. 1547 * Since we purge the cache on every context switch, we only need to check for 1548 * other mappings within the same pmap, or kernel_pmap. 1549 * This function is also called when a page is unmapped, to possibly reenable 1550 * caching on any remaining mappings. 1551 * 1552 * The code implements the following logic, where: 1553 * 1554 * KW = # of kernel read/write pages 1555 * KR = # of kernel read only pages 1556 * UW = # of user read/write pages 1557 * UR = # of user read only pages 1558 * 1559 * KC = kernel mapping is cacheable 1560 * UC = user mapping is cacheable 1561 * 1562 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1563 * +--------------------------------------------- 1564 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1565 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1566 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1567 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1568 */ 1569 1570 static const int pmap_vac_flags[4][4] = { 1571 {-1, 0, 0, PVF_KNC}, 1572 {0, 0, PVF_NC, PVF_NC}, 1573 {0, PVF_NC, PVF_NC, PVF_NC}, 1574 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1575 }; 1576 1577 static inline int 1578 pmap_get_vac_flags(const struct vm_page_md *md) 1579 { 1580 int kidx, uidx; 1581 1582 kidx = 0; 1583 if (md->kro_mappings || md->krw_mappings > 1) 1584 kidx |= 1; 1585 if (md->krw_mappings) 1586 kidx |= 2; 1587 1588 uidx = 0; 1589 if (md->uro_mappings || md->urw_mappings > 1) 1590 uidx |= 1; 1591 if (md->urw_mappings) 1592 uidx |= 2; 1593 1594 return (pmap_vac_flags[uidx][kidx]); 1595 } 1596 1597 static inline void 1598 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1599 { 1600 int nattr; 1601 1602 nattr = pmap_get_vac_flags(md); 1603 1604 if (nattr < 0) { 1605 md->pvh_attrs &= ~PVF_NC; 1606 return; 1607 } 1608 1609 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1610 return; 1611 1612 if (pm == pmap_kernel()) 1613 pmap_vac_me_kpmap(md, pa, pm, va); 1614 else 1615 pmap_vac_me_user(md, pa, pm, va); 1616 1617 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1618 } 1619 1620 static void 1621 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1622 { 1623 u_int u_cacheable, u_entries; 1624 struct pv_entry *pv; 1625 pmap_t last_pmap = pm; 1626 1627 /* 1628 * Pass one, see if there are both kernel and user pmaps for 1629 * this page. Calculate whether there are user-writable or 1630 * kernel-writable pages. 1631 */ 1632 u_cacheable = 0; 1633 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1634 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1635 u_cacheable++; 1636 } 1637 1638 u_entries = md->urw_mappings + md->uro_mappings; 1639 1640 /* 1641 * We know we have just been updating a kernel entry, so if 1642 * all user pages are already cacheable, then there is nothing 1643 * further to do. 1644 */ 1645 if (md->k_mappings == 0 && u_cacheable == u_entries) 1646 return; 1647 1648 if (u_entries) { 1649 /* 1650 * Scan over the list again, for each entry, if it 1651 * might not be set correctly, call pmap_vac_me_user 1652 * to recalculate the settings. 1653 */ 1654 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1655 /* 1656 * We know kernel mappings will get set 1657 * correctly in other calls. We also know 1658 * that if the pmap is the same as last_pmap 1659 * then we've just handled this entry. 1660 */ 1661 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1662 continue; 1663 1664 /* 1665 * If there are kernel entries and this page 1666 * is writable but non-cacheable, then we can 1667 * skip this entry also. 1668 */ 1669 if (md->k_mappings && 1670 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1671 (PVF_NC | PVF_WRITE)) 1672 continue; 1673 1674 /* 1675 * Similarly if there are no kernel-writable 1676 * entries and the page is already 1677 * read-only/cacheable. 1678 */ 1679 if (md->krw_mappings == 0 && 1680 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1681 continue; 1682 1683 /* 1684 * For some of the remaining cases, we know 1685 * that we must recalculate, but for others we 1686 * can't tell if they are correct or not, so 1687 * we recalculate anyway. 1688 */ 1689 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1690 } 1691 1692 if (md->k_mappings == 0) 1693 return; 1694 } 1695 1696 pmap_vac_me_user(md, pa, pm, va); 1697 } 1698 1699 static void 1700 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1701 { 1702 pmap_t kpmap = pmap_kernel(); 1703 struct pv_entry *pv, *npv = NULL; 1704 struct l2_bucket *l2b; 1705 pt_entry_t *ptep, pte; 1706 u_int entries = 0; 1707 u_int writable = 0; 1708 u_int cacheable_entries = 0; 1709 u_int kern_cacheable = 0; 1710 u_int other_writable = 0; 1711 1712 /* 1713 * Count mappings and writable mappings in this pmap. 1714 * Include kernel mappings as part of our own. 1715 * Keep a pointer to the first one. 1716 */ 1717 npv = NULL; 1718 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1719 /* Count mappings in the same pmap */ 1720 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1721 if (entries++ == 0) 1722 npv = pv; 1723 1724 /* Cacheable mappings */ 1725 if ((pv->pv_flags & PVF_NC) == 0) { 1726 cacheable_entries++; 1727 if (kpmap == pv->pv_pmap) 1728 kern_cacheable++; 1729 } 1730 1731 /* Writable mappings */ 1732 if (pv->pv_flags & PVF_WRITE) 1733 ++writable; 1734 } else 1735 if (pv->pv_flags & PVF_WRITE) 1736 other_writable = 1; 1737 } 1738 1739 /* 1740 * Enable or disable caching as necessary. 1741 * Note: the first entry might be part of the kernel pmap, 1742 * so we can't assume this is indicative of the state of the 1743 * other (maybe non-kpmap) entries. 1744 */ 1745 if ((entries > 1 && writable) || 1746 (entries > 0 && pm == kpmap && other_writable)) { 1747 if (cacheable_entries == 0) 1748 return; 1749 1750 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1751 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1752 (pv->pv_flags & PVF_NC)) 1753 continue; 1754 1755 pv->pv_flags |= PVF_NC; 1756 1757 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1758 KDASSERT(l2b != NULL); 1759 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1760 pte = *ptep & ~L2_S_CACHE_MASK; 1761 1762 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1763 l2pte_valid(pte)) { 1764 if (PV_BEEN_EXECD(pv->pv_flags)) { 1765 #ifdef PMAP_CACHE_VIVT 1766 pmap_idcache_wbinv_range(pv->pv_pmap, 1767 pv->pv_va, PAGE_SIZE); 1768 #endif 1769 pmap_tlb_flushID_SE(pv->pv_pmap, 1770 pv->pv_va); 1771 } else 1772 if (PV_BEEN_REFD(pv->pv_flags)) { 1773 #ifdef PMAP_CACHE_VIVT 1774 pmap_dcache_wb_range(pv->pv_pmap, 1775 pv->pv_va, PAGE_SIZE, true, 1776 (pv->pv_flags & PVF_WRITE) == 0); 1777 #endif 1778 pmap_tlb_flushD_SE(pv->pv_pmap, 1779 pv->pv_va); 1780 } 1781 } 1782 1783 *ptep = pte; 1784 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1785 } 1786 cpu_cpwait(); 1787 } else 1788 if (entries > cacheable_entries) { 1789 /* 1790 * Turn cacheing back on for some pages. If it is a kernel 1791 * page, only do so if there are no other writable pages. 1792 */ 1793 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1794 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1795 (kpmap != pv->pv_pmap || other_writable))) 1796 continue; 1797 1798 pv->pv_flags &= ~PVF_NC; 1799 1800 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1801 KDASSERT(l2b != NULL); 1802 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1803 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1804 1805 if (l2pte_valid(pte)) { 1806 if (PV_BEEN_EXECD(pv->pv_flags)) { 1807 pmap_tlb_flushID_SE(pv->pv_pmap, 1808 pv->pv_va); 1809 } else 1810 if (PV_BEEN_REFD(pv->pv_flags)) { 1811 pmap_tlb_flushD_SE(pv->pv_pmap, 1812 pv->pv_va); 1813 } 1814 } 1815 1816 *ptep = pte; 1817 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1818 } 1819 } 1820 } 1821 #endif 1822 1823 #ifdef PMAP_CACHE_VIPT 1824 static void 1825 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1826 { 1827 struct pv_entry *pv; 1828 vaddr_t tst_mask; 1829 bool bad_alias; 1830 struct l2_bucket *l2b; 1831 pt_entry_t *ptep, pte, opte; 1832 const u_int 1833 rw_mappings = md->urw_mappings + md->krw_mappings, 1834 ro_mappings = md->uro_mappings + md->kro_mappings; 1835 1836 /* do we need to do anything? */ 1837 if (arm_cache_prefer_mask == 0) 1838 return; 1839 1840 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1841 md, pm, va)); 1842 1843 KASSERT(!va || pm); 1844 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1845 1846 /* Already a conflict? */ 1847 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1848 /* just an add, things are already non-cached */ 1849 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1850 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1851 bad_alias = false; 1852 if (va) { 1853 PMAPCOUNT(vac_color_none); 1854 bad_alias = true; 1855 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1856 goto fixup; 1857 } 1858 pv = SLIST_FIRST(&md->pvh_list); 1859 /* the list can't be empty because it would be cachable */ 1860 if (md->pvh_attrs & PVF_KMPAGE) { 1861 tst_mask = md->pvh_attrs; 1862 } else { 1863 KASSERT(pv); 1864 tst_mask = pv->pv_va; 1865 pv = SLIST_NEXT(pv, pv_link); 1866 } 1867 /* 1868 * Only check for a bad alias if we have writable mappings. 1869 */ 1870 tst_mask &= arm_cache_prefer_mask; 1871 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1872 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1873 /* if there's a bad alias, stop checking. */ 1874 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1875 bad_alias = true; 1876 } 1877 md->pvh_attrs |= PVF_WRITE; 1878 if (!bad_alias) 1879 md->pvh_attrs |= PVF_DIRTY; 1880 } else { 1881 /* 1882 * We have only read-only mappings. Let's see if there 1883 * are multiple colors in use or if we mapped a KMPAGE. 1884 * If the latter, we have a bad alias. If the former, 1885 * we need to remember that. 1886 */ 1887 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1888 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1889 if (md->pvh_attrs & PVF_KMPAGE) 1890 bad_alias = true; 1891 break; 1892 } 1893 } 1894 md->pvh_attrs &= ~PVF_WRITE; 1895 /* 1896 * No KMPAGE and we exited early, so we must have 1897 * multiple color mappings. 1898 */ 1899 if (!bad_alias && pv != NULL) 1900 md->pvh_attrs |= PVF_MULTCLR; 1901 } 1902 1903 /* If no conflicting colors, set everything back to cached */ 1904 if (!bad_alias) { 1905 #ifdef DEBUG 1906 if ((md->pvh_attrs & PVF_WRITE) 1907 || ro_mappings < 2) { 1908 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1909 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1910 } 1911 #endif 1912 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1913 md->pvh_attrs |= tst_mask | PVF_COLORED; 1914 /* 1915 * Restore DIRTY bit if page is modified 1916 */ 1917 if (md->pvh_attrs & PVF_DMOD) 1918 md->pvh_attrs |= PVF_DIRTY; 1919 PMAPCOUNT(vac_color_restore); 1920 } else { 1921 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1922 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1923 } 1924 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1925 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1926 } else if (!va) { 1927 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1928 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1929 || (md->pvh_attrs & PVF_DIRTY)); 1930 if (rw_mappings == 0) { 1931 md->pvh_attrs &= ~PVF_WRITE; 1932 if (ro_mappings == 1 1933 && (md->pvh_attrs & PVF_MULTCLR)) { 1934 /* 1935 * If this is the last readonly mapping 1936 * but it doesn't match the current color 1937 * for the page, change the current color 1938 * to match this last readonly mapping. 1939 */ 1940 pv = SLIST_FIRST(&md->pvh_list); 1941 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1942 & arm_cache_prefer_mask; 1943 if (tst_mask) { 1944 md->pvh_attrs ^= tst_mask; 1945 PMAPCOUNT(vac_color_change); 1946 } 1947 } 1948 } 1949 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1950 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1951 return; 1952 } else if (!pmap_is_page_colored_p(md)) { 1953 /* not colored so we just use its color */ 1954 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1955 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1956 PMAPCOUNT(vac_color_new); 1957 md->pvh_attrs &= PAGE_SIZE - 1; 1958 md->pvh_attrs |= PVF_COLORED 1959 | (va & arm_cache_prefer_mask) 1960 | (rw_mappings > 0 ? PVF_WRITE : 0); 1961 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1962 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1963 return; 1964 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1965 bad_alias = false; 1966 if (rw_mappings > 0) { 1967 /* 1968 * We now have writeable mappings and if we have 1969 * readonly mappings in more than once color, we have 1970 * an aliasing problem. Regardless mark the page as 1971 * writeable. 1972 */ 1973 if (md->pvh_attrs & PVF_MULTCLR) { 1974 if (ro_mappings < 2) { 1975 /* 1976 * If we only have less than two 1977 * read-only mappings, just flush the 1978 * non-primary colors from the cache. 1979 */ 1980 pmap_flush_page(md, pa, 1981 PMAP_FLUSH_SECONDARY); 1982 } else { 1983 bad_alias = true; 1984 } 1985 } 1986 md->pvh_attrs |= PVF_WRITE; 1987 } 1988 /* If no conflicting colors, set everything back to cached */ 1989 if (!bad_alias) { 1990 #ifdef DEBUG 1991 if (rw_mappings > 0 1992 || (md->pvh_attrs & PMAP_KMPAGE)) { 1993 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1994 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1995 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1996 } 1997 #endif 1998 if (SLIST_EMPTY(&md->pvh_list)) 1999 PMAPCOUNT(vac_color_reuse); 2000 else 2001 PMAPCOUNT(vac_color_ok); 2002 2003 /* matching color, just return */ 2004 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2005 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2006 return; 2007 } 2008 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2009 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2010 2011 /* color conflict. evict from cache. */ 2012 2013 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2014 md->pvh_attrs &= ~PVF_COLORED; 2015 md->pvh_attrs |= PVF_NC; 2016 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2017 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2018 PMAPCOUNT(vac_color_erase); 2019 } else if (rw_mappings == 0 2020 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2021 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2022 2023 /* 2024 * If the page has dirty cache lines, clean it. 2025 */ 2026 if (md->pvh_attrs & PVF_DIRTY) 2027 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2028 2029 /* 2030 * If this is the first remapping (we know that there are no 2031 * writeable mappings), then this is a simple color change. 2032 * Otherwise this is a seconary r/o mapping, which means 2033 * we don't have to do anything. 2034 */ 2035 if (ro_mappings == 1) { 2036 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2037 md->pvh_attrs &= PAGE_SIZE - 1; 2038 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2039 PMAPCOUNT(vac_color_change); 2040 } else { 2041 PMAPCOUNT(vac_color_blind); 2042 } 2043 md->pvh_attrs |= PVF_MULTCLR; 2044 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2045 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2046 return; 2047 } else { 2048 if (rw_mappings > 0) 2049 md->pvh_attrs |= PVF_WRITE; 2050 2051 /* color conflict. evict from cache. */ 2052 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2053 2054 /* the list can't be empty because this was a enter/modify */ 2055 pv = SLIST_FIRST(&md->pvh_list); 2056 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2057 KASSERT(pv); 2058 /* 2059 * If there's only one mapped page, change color to the 2060 * page's new color and return. Restore the DIRTY bit 2061 * that was erased by pmap_flush_page. 2062 */ 2063 if (SLIST_NEXT(pv, pv_link) == NULL) { 2064 md->pvh_attrs &= PAGE_SIZE - 1; 2065 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2066 if (md->pvh_attrs & PVF_DMOD) 2067 md->pvh_attrs |= PVF_DIRTY; 2068 PMAPCOUNT(vac_color_change); 2069 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2070 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2071 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2072 return; 2073 } 2074 } 2075 bad_alias = true; 2076 md->pvh_attrs &= ~PVF_COLORED; 2077 md->pvh_attrs |= PVF_NC; 2078 PMAPCOUNT(vac_color_erase); 2079 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2080 } 2081 2082 fixup: 2083 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2084 2085 /* 2086 * Turn cacheing on/off for all pages. 2087 */ 2088 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2089 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2090 KDASSERT(l2b != NULL); 2091 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2092 opte = *ptep; 2093 pte = opte & ~L2_S_CACHE_MASK; 2094 if (bad_alias) { 2095 pv->pv_flags |= PVF_NC; 2096 } else { 2097 pv->pv_flags &= ~PVF_NC; 2098 pte |= pte_l2_s_cache_mode; 2099 } 2100 2101 if (opte == pte) /* only update is there's a change */ 2102 continue; 2103 2104 if (l2pte_valid(pte)) { 2105 if (PV_BEEN_EXECD(pv->pv_flags)) { 2106 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2107 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2108 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2109 } 2110 } 2111 2112 *ptep = pte; 2113 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2114 } 2115 } 2116 #endif /* PMAP_CACHE_VIPT */ 2117 2118 2119 /* 2120 * Modify pte bits for all ptes corresponding to the given physical address. 2121 * We use `maskbits' rather than `clearbits' because we're always passing 2122 * constants and the latter would require an extra inversion at run-time. 2123 */ 2124 static void 2125 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2126 { 2127 struct l2_bucket *l2b; 2128 struct pv_entry *pv; 2129 pt_entry_t *ptep, npte, opte; 2130 pmap_t pm; 2131 vaddr_t va; 2132 u_int oflags; 2133 #ifdef PMAP_CACHE_VIPT 2134 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2135 bool need_syncicache = false; 2136 bool did_syncicache = false; 2137 bool need_vac_me_harder = false; 2138 #endif 2139 2140 NPDEBUG(PDB_BITS, 2141 printf("pmap_clearbit: md %p mask 0x%x\n", 2142 md, maskbits)); 2143 2144 PMAP_HEAD_TO_MAP_LOCK(); 2145 simple_lock(&md->pvh_slock); 2146 2147 #ifdef PMAP_CACHE_VIPT 2148 /* 2149 * If we might want to sync the I-cache and we've modified it, 2150 * then we know we definitely need to sync or discard it. 2151 */ 2152 if (want_syncicache) 2153 need_syncicache = md->pvh_attrs & PVF_MOD; 2154 #endif 2155 /* 2156 * Clear saved attributes (modify, reference) 2157 */ 2158 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2159 2160 if (SLIST_EMPTY(&md->pvh_list)) { 2161 #ifdef PMAP_CACHE_VIPT 2162 if (need_syncicache) { 2163 /* 2164 * No one has it mapped, so just discard it. The next 2165 * exec remapping will cause it to be synced. 2166 */ 2167 md->pvh_attrs &= ~PVF_EXEC; 2168 PMAPCOUNT(exec_discarded_clearbit); 2169 } 2170 #endif 2171 simple_unlock(&md->pvh_slock); 2172 PMAP_HEAD_TO_MAP_UNLOCK(); 2173 return; 2174 } 2175 2176 /* 2177 * Loop over all current mappings setting/clearing as appropos 2178 */ 2179 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2180 va = pv->pv_va; 2181 pm = pv->pv_pmap; 2182 oflags = pv->pv_flags; 2183 /* 2184 * Kernel entries are unmanaged and as such not to be changed. 2185 */ 2186 if (oflags & PVF_KENTRY) 2187 continue; 2188 pv->pv_flags &= ~maskbits; 2189 2190 pmap_acquire_pmap_lock(pm); 2191 2192 l2b = pmap_get_l2_bucket(pm, va); 2193 KDASSERT(l2b != NULL); 2194 2195 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2196 npte = opte = *ptep; 2197 2198 NPDEBUG(PDB_BITS, 2199 printf( 2200 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2201 pv, pv->pv_pmap, pv->pv_va, oflags)); 2202 2203 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2204 #ifdef PMAP_CACHE_VIVT 2205 if ((pv->pv_flags & PVF_NC)) { 2206 /* 2207 * Entry is not cacheable: 2208 * 2209 * Don't turn caching on again if this is a 2210 * modified emulation. This would be 2211 * inconsitent with the settings created by 2212 * pmap_vac_me_harder(). Otherwise, it's safe 2213 * to re-enable cacheing. 2214 * 2215 * There's no need to call pmap_vac_me_harder() 2216 * here: all pages are losing their write 2217 * permission. 2218 */ 2219 if (maskbits & PVF_WRITE) { 2220 npte |= pte_l2_s_cache_mode; 2221 pv->pv_flags &= ~PVF_NC; 2222 } 2223 } else 2224 if (l2pte_writable_p(opte)) { 2225 /* 2226 * Entry is writable/cacheable: check if pmap 2227 * is current if it is flush it, otherwise it 2228 * won't be in the cache 2229 */ 2230 if (PV_BEEN_EXECD(oflags)) 2231 pmap_idcache_wbinv_range(pm, pv->pv_va, 2232 PAGE_SIZE); 2233 else 2234 if (PV_BEEN_REFD(oflags)) 2235 pmap_dcache_wb_range(pm, pv->pv_va, 2236 PAGE_SIZE, 2237 (maskbits & PVF_REF) != 0, false); 2238 } 2239 #endif 2240 2241 /* make the pte read only */ 2242 npte = l2pte_set_readonly(npte); 2243 2244 if (maskbits & oflags & PVF_WRITE) { 2245 /* 2246 * Keep alias accounting up to date 2247 */ 2248 if (pv->pv_pmap == pmap_kernel()) { 2249 md->krw_mappings--; 2250 md->kro_mappings++; 2251 } else { 2252 md->urw_mappings--; 2253 md->uro_mappings++; 2254 } 2255 #ifdef PMAP_CACHE_VIPT 2256 if (md->urw_mappings + md->krw_mappings == 0) 2257 md->pvh_attrs &= ~PVF_WRITE; 2258 if (want_syncicache) 2259 need_syncicache = true; 2260 need_vac_me_harder = true; 2261 #endif 2262 } 2263 } 2264 2265 if (maskbits & PVF_REF) { 2266 if ((pv->pv_flags & PVF_NC) == 0 && 2267 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2268 l2pte_valid(npte)) { 2269 #ifdef PMAP_CACHE_VIVT 2270 /* 2271 * Check npte here; we may have already 2272 * done the wbinv above, and the validity 2273 * of the PTE is the same for opte and 2274 * npte. 2275 */ 2276 /* XXXJRT need idcache_inv_range */ 2277 if (PV_BEEN_EXECD(oflags)) 2278 pmap_idcache_wbinv_range(pm, 2279 pv->pv_va, PAGE_SIZE); 2280 else 2281 if (PV_BEEN_REFD(oflags)) 2282 pmap_dcache_wb_range(pm, 2283 pv->pv_va, PAGE_SIZE, 2284 true, true); 2285 #endif 2286 } 2287 2288 /* 2289 * Make the PTE invalid so that we will take a 2290 * page fault the next time the mapping is 2291 * referenced. 2292 */ 2293 npte &= ~L2_TYPE_MASK; 2294 npte |= L2_TYPE_INV; 2295 } 2296 2297 if (npte != opte) { 2298 *ptep = npte; 2299 PTE_SYNC(ptep); 2300 /* Flush the TLB entry if a current pmap. */ 2301 if (PV_BEEN_EXECD(oflags)) 2302 pmap_tlb_flushID_SE(pm, pv->pv_va); 2303 else 2304 if (PV_BEEN_REFD(oflags)) 2305 pmap_tlb_flushD_SE(pm, pv->pv_va); 2306 } 2307 2308 pmap_release_pmap_lock(pm); 2309 2310 NPDEBUG(PDB_BITS, 2311 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2312 pm, va, opte, npte)); 2313 } 2314 2315 #ifdef PMAP_CACHE_VIPT 2316 /* 2317 * If we need to sync the I-cache and we haven't done it yet, do it. 2318 */ 2319 if (need_syncicache && !did_syncicache) { 2320 pmap_syncicache_page(md, pa); 2321 PMAPCOUNT(exec_synced_clearbit); 2322 } 2323 /* 2324 * If we are changing this to read-only, we need to call vac_me_harder 2325 * so we can change all the read-only pages to cacheable. We pretend 2326 * this as a page deletion. 2327 */ 2328 if (need_vac_me_harder) { 2329 if (md->pvh_attrs & PVF_NC) 2330 pmap_vac_me_harder(md, pa, NULL, 0); 2331 } 2332 #endif 2333 2334 simple_unlock(&md->pvh_slock); 2335 PMAP_HEAD_TO_MAP_UNLOCK(); 2336 } 2337 2338 /* 2339 * pmap_clean_page() 2340 * 2341 * This is a local function used to work out the best strategy to clean 2342 * a single page referenced by its entry in the PV table. It's used by 2343 * pmap_copy_page, pmap_zero page and maybe some others later on. 2344 * 2345 * Its policy is effectively: 2346 * o If there are no mappings, we don't bother doing anything with the cache. 2347 * o If there is one mapping, we clean just that page. 2348 * o If there are multiple mappings, we clean the entire cache. 2349 * 2350 * So that some functions can be further optimised, it returns 0 if it didn't 2351 * clean the entire cache, or 1 if it did. 2352 * 2353 * XXX One bug in this routine is that if the pv_entry has a single page 2354 * mapped at 0x00000000 a whole cache clean will be performed rather than 2355 * just the 1 page. Since this should not occur in everyday use and if it does 2356 * it will just result in not the most efficient clean for the page. 2357 */ 2358 #ifdef PMAP_CACHE_VIVT 2359 static int 2360 pmap_clean_page(struct pv_entry *pv, bool is_src) 2361 { 2362 pmap_t pm_to_clean = NULL; 2363 struct pv_entry *npv; 2364 u_int cache_needs_cleaning = 0; 2365 u_int flags = 0; 2366 vaddr_t page_to_clean = 0; 2367 2368 if (pv == NULL) { 2369 /* nothing mapped in so nothing to flush */ 2370 return (0); 2371 } 2372 2373 /* 2374 * Since we flush the cache each time we change to a different 2375 * user vmspace, we only need to flush the page if it is in the 2376 * current pmap. 2377 */ 2378 2379 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2380 if (pmap_is_current(npv->pv_pmap)) { 2381 flags |= npv->pv_flags; 2382 /* 2383 * The page is mapped non-cacheable in 2384 * this map. No need to flush the cache. 2385 */ 2386 if (npv->pv_flags & PVF_NC) { 2387 #ifdef DIAGNOSTIC 2388 if (cache_needs_cleaning) 2389 panic("pmap_clean_page: " 2390 "cache inconsistency"); 2391 #endif 2392 break; 2393 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2394 continue; 2395 if (cache_needs_cleaning) { 2396 page_to_clean = 0; 2397 break; 2398 } else { 2399 page_to_clean = npv->pv_va; 2400 pm_to_clean = npv->pv_pmap; 2401 } 2402 cache_needs_cleaning = 1; 2403 } 2404 } 2405 2406 if (page_to_clean) { 2407 if (PV_BEEN_EXECD(flags)) 2408 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2409 PAGE_SIZE); 2410 else 2411 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2412 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2413 } else if (cache_needs_cleaning) { 2414 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2415 2416 if (PV_BEEN_EXECD(flags)) 2417 pmap_idcache_wbinv_all(pm); 2418 else 2419 pmap_dcache_wbinv_all(pm); 2420 return (1); 2421 } 2422 return (0); 2423 } 2424 #endif 2425 2426 #ifdef PMAP_CACHE_VIPT 2427 /* 2428 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2429 * right cache alias to make sure we flush the right stuff. 2430 */ 2431 void 2432 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2433 { 2434 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2435 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2436 2437 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2438 md, md->pvh_attrs)); 2439 /* 2440 * No need to clean the page if it's non-cached. 2441 */ 2442 if (md->pvh_attrs & PVF_NC) 2443 return; 2444 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2445 2446 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2447 /* 2448 * Set up a PTE with the right coloring to flush existing cache lines. 2449 */ 2450 *ptep = L2_S_PROTO | 2451 pa 2452 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2453 | pte_l2_s_cache_mode; 2454 PTE_SYNC(ptep); 2455 2456 /* 2457 * Flush it. 2458 */ 2459 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2460 /* 2461 * Unmap the page. 2462 */ 2463 *ptep = 0; 2464 PTE_SYNC(ptep); 2465 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2466 2467 md->pvh_attrs |= PVF_EXEC; 2468 PMAPCOUNT(exec_synced); 2469 } 2470 2471 void 2472 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2473 { 2474 vsize_t va_offset, end_va; 2475 void (*cf)(vaddr_t, vsize_t); 2476 2477 if (arm_cache_prefer_mask == 0) 2478 return; 2479 2480 switch (flush) { 2481 case PMAP_FLUSH_PRIMARY: 2482 if (md->pvh_attrs & PVF_MULTCLR) { 2483 va_offset = 0; 2484 end_va = arm_cache_prefer_mask; 2485 md->pvh_attrs &= ~PVF_MULTCLR; 2486 PMAPCOUNT(vac_flush_lots); 2487 } else { 2488 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2489 end_va = va_offset; 2490 PMAPCOUNT(vac_flush_one); 2491 } 2492 /* 2493 * Mark that the page is no longer dirty. 2494 */ 2495 md->pvh_attrs &= ~PVF_DIRTY; 2496 cf = cpufuncs.cf_idcache_wbinv_range; 2497 break; 2498 case PMAP_FLUSH_SECONDARY: 2499 va_offset = 0; 2500 end_va = arm_cache_prefer_mask; 2501 cf = cpufuncs.cf_idcache_wbinv_range; 2502 md->pvh_attrs &= ~PVF_MULTCLR; 2503 PMAPCOUNT(vac_flush_lots); 2504 break; 2505 case PMAP_CLEAN_PRIMARY: 2506 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2507 end_va = va_offset; 2508 cf = cpufuncs.cf_dcache_wb_range; 2509 /* 2510 * Mark that the page is no longer dirty. 2511 */ 2512 if ((md->pvh_attrs & PVF_DMOD) == 0) 2513 md->pvh_attrs &= ~PVF_DIRTY; 2514 PMAPCOUNT(vac_clean_one); 2515 break; 2516 default: 2517 return; 2518 } 2519 2520 KASSERT(!(md->pvh_attrs & PVF_NC)); 2521 2522 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2523 md, md->pvh_attrs)); 2524 2525 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2526 const size_t pte_offset = va_offset >> PGSHIFT; 2527 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2528 const pt_entry_t oldpte = *ptep; 2529 2530 if (flush == PMAP_FLUSH_SECONDARY 2531 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2532 continue; 2533 2534 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2535 /* 2536 * Set up a PTE with the right coloring to flush 2537 * existing cache entries. 2538 */ 2539 *ptep = L2_S_PROTO 2540 | pa 2541 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2542 | pte_l2_s_cache_mode; 2543 PTE_SYNC(ptep); 2544 2545 /* 2546 * Flush it. 2547 */ 2548 (*cf)(cdstp + va_offset, PAGE_SIZE); 2549 2550 /* 2551 * Restore the page table entry since we might have interrupted 2552 * pmap_zero_page or pmap_copy_page which was already using 2553 * this pte. 2554 */ 2555 *ptep = oldpte; 2556 PTE_SYNC(ptep); 2557 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2558 } 2559 } 2560 #endif /* PMAP_CACHE_VIPT */ 2561 2562 /* 2563 * Routine: pmap_page_remove 2564 * Function: 2565 * Removes this physical page from 2566 * all physical maps in which it resides. 2567 * Reflects back modify bits to the pager. 2568 */ 2569 static void 2570 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2571 { 2572 struct l2_bucket *l2b; 2573 struct pv_entry *pv, *npv, **pvp; 2574 pmap_t pm; 2575 pt_entry_t *ptep; 2576 bool flush; 2577 u_int flags; 2578 2579 NPDEBUG(PDB_FOLLOW, 2580 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2581 pa)); 2582 2583 PMAP_HEAD_TO_MAP_LOCK(); 2584 simple_lock(&md->pvh_slock); 2585 2586 pv = SLIST_FIRST(&md->pvh_list); 2587 if (pv == NULL) { 2588 #ifdef PMAP_CACHE_VIPT 2589 /* 2590 * We *know* the page contents are about to be replaced. 2591 * Discard the exec contents 2592 */ 2593 if (PV_IS_EXEC_P(md->pvh_attrs)) 2594 PMAPCOUNT(exec_discarded_page_protect); 2595 md->pvh_attrs &= ~PVF_EXEC; 2596 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2597 #endif 2598 simple_unlock(&md->pvh_slock); 2599 PMAP_HEAD_TO_MAP_UNLOCK(); 2600 return; 2601 } 2602 #ifdef PMAP_CACHE_VIPT 2603 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2604 #endif 2605 2606 /* 2607 * Clear alias counts 2608 */ 2609 #ifdef PMAP_CACHE_VIVT 2610 md->k_mappings = 0; 2611 #endif 2612 md->urw_mappings = md->uro_mappings = 0; 2613 2614 flush = false; 2615 flags = 0; 2616 2617 #ifdef PMAP_CACHE_VIVT 2618 pmap_clean_page(pv, false); 2619 #endif 2620 2621 pvp = &SLIST_FIRST(&md->pvh_list); 2622 while (pv) { 2623 pm = pv->pv_pmap; 2624 npv = SLIST_NEXT(pv, pv_link); 2625 if (flush == false && pmap_is_current(pm)) 2626 flush = true; 2627 2628 if (pm == pmap_kernel()) { 2629 #ifdef PMAP_CACHE_VIPT 2630 /* 2631 * If this was unmanaged mapping, it must be preserved. 2632 * Move it back on the list and advance the end-of-list 2633 * pointer. 2634 */ 2635 if (pv->pv_flags & PVF_KENTRY) { 2636 *pvp = pv; 2637 pvp = &SLIST_NEXT(pv, pv_link); 2638 pv = npv; 2639 continue; 2640 } 2641 if (pv->pv_flags & PVF_WRITE) 2642 md->krw_mappings--; 2643 else 2644 md->kro_mappings--; 2645 #endif 2646 PMAPCOUNT(kernel_unmappings); 2647 } 2648 PMAPCOUNT(unmappings); 2649 2650 pmap_acquire_pmap_lock(pm); 2651 2652 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2653 KDASSERT(l2b != NULL); 2654 2655 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2656 2657 /* 2658 * Update statistics 2659 */ 2660 --pm->pm_stats.resident_count; 2661 2662 /* Wired bit */ 2663 if (pv->pv_flags & PVF_WIRED) 2664 --pm->pm_stats.wired_count; 2665 2666 flags |= pv->pv_flags; 2667 2668 /* 2669 * Invalidate the PTEs. 2670 */ 2671 *ptep = 0; 2672 PTE_SYNC_CURRENT(pm, ptep); 2673 pmap_free_l2_bucket(pm, l2b, 1); 2674 2675 pool_put(&pmap_pv_pool, pv); 2676 pv = npv; 2677 /* 2678 * if we reach the end of the list and there are still 2679 * mappings, they might be able to be cached now. 2680 */ 2681 if (pv == NULL) { 2682 *pvp = NULL; 2683 if (!SLIST_EMPTY(&md->pvh_list)) 2684 pmap_vac_me_harder(md, pa, pm, 0); 2685 } 2686 pmap_release_pmap_lock(pm); 2687 } 2688 #ifdef PMAP_CACHE_VIPT 2689 /* 2690 * Its EXEC cache is now gone. 2691 */ 2692 if (PV_IS_EXEC_P(md->pvh_attrs)) 2693 PMAPCOUNT(exec_discarded_page_protect); 2694 md->pvh_attrs &= ~PVF_EXEC; 2695 KASSERT(md->urw_mappings == 0); 2696 KASSERT(md->uro_mappings == 0); 2697 if (md->krw_mappings == 0) 2698 md->pvh_attrs &= ~PVF_WRITE; 2699 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2700 #endif 2701 simple_unlock(&md->pvh_slock); 2702 PMAP_HEAD_TO_MAP_UNLOCK(); 2703 2704 if (flush) { 2705 /* 2706 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2707 * would need a subsequent call to pmap_update() to ensure 2708 * curpm->pm_cstate.cs_all is reset. Our callers are not 2709 * required to do that (see pmap(9)), so we can't modify 2710 * the current pmap's state. 2711 */ 2712 if (PV_BEEN_EXECD(flags)) 2713 cpu_tlb_flushID(); 2714 else 2715 cpu_tlb_flushD(); 2716 } 2717 cpu_cpwait(); 2718 } 2719 2720 /* 2721 * pmap_t pmap_create(void) 2722 * 2723 * Create a new pmap structure from scratch. 2724 */ 2725 pmap_t 2726 pmap_create(void) 2727 { 2728 pmap_t pm; 2729 2730 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2731 2732 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2733 pm->pm_stats.wired_count = 0; 2734 pm->pm_stats.resident_count = 1; 2735 pm->pm_cstate.cs_all = 0; 2736 pmap_alloc_l1(pm); 2737 2738 /* 2739 * Note: The pool cache ensures that the pm_l2[] array is already 2740 * initialised to zero. 2741 */ 2742 2743 pmap_pinit(pm); 2744 2745 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2746 2747 return (pm); 2748 } 2749 2750 /* 2751 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2752 * u_int flags) 2753 * 2754 * Insert the given physical page (p) at 2755 * the specified virtual address (v) in the 2756 * target physical map with the protection requested. 2757 * 2758 * NB: This is the only routine which MAY NOT lazy-evaluate 2759 * or lose information. That is, this routine must actually 2760 * insert this page into the given map NOW. 2761 */ 2762 int 2763 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2764 { 2765 struct l2_bucket *l2b; 2766 struct vm_page *pg, *opg; 2767 struct pv_entry *pv; 2768 pt_entry_t *ptep, npte, opte; 2769 u_int nflags; 2770 u_int oflags; 2771 2772 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2773 2774 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2775 KDASSERT(((va | pa) & PGOFSET) == 0); 2776 2777 /* 2778 * Get a pointer to the page. Later on in this function, we 2779 * test for a managed page by checking pg != NULL. 2780 */ 2781 pg = (pmap_initialized && ((flags & PMAP_NOCACHE) == 0)) ? 2782 PHYS_TO_VM_PAGE(pa) : NULL; 2783 2784 nflags = 0; 2785 if (prot & VM_PROT_WRITE) 2786 nflags |= PVF_WRITE; 2787 if (prot & VM_PROT_EXECUTE) 2788 nflags |= PVF_EXEC; 2789 if (flags & PMAP_WIRED) 2790 nflags |= PVF_WIRED; 2791 2792 PMAP_MAP_TO_HEAD_LOCK(); 2793 pmap_acquire_pmap_lock(pm); 2794 2795 /* 2796 * Fetch the L2 bucket which maps this page, allocating one if 2797 * necessary for user pmaps. 2798 */ 2799 if (pm == pmap_kernel()) 2800 l2b = pmap_get_l2_bucket(pm, va); 2801 else 2802 l2b = pmap_alloc_l2_bucket(pm, va); 2803 if (l2b == NULL) { 2804 if (flags & PMAP_CANFAIL) { 2805 pmap_release_pmap_lock(pm); 2806 PMAP_MAP_TO_HEAD_UNLOCK(); 2807 return (ENOMEM); 2808 } 2809 panic("pmap_enter: failed to allocate L2 bucket"); 2810 } 2811 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2812 opte = *ptep; 2813 npte = pa; 2814 oflags = 0; 2815 2816 if (opte) { 2817 /* 2818 * There is already a mapping at this address. 2819 * If the physical address is different, lookup the 2820 * vm_page. 2821 */ 2822 if (l2pte_pa(opte) != pa) 2823 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2824 else 2825 opg = pg; 2826 } else 2827 opg = NULL; 2828 2829 if (pg) { 2830 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2831 2832 /* 2833 * This is to be a managed mapping. 2834 */ 2835 if ((flags & VM_PROT_ALL) || 2836 (md->pvh_attrs & PVF_REF)) { 2837 /* 2838 * - The access type indicates that we don't need 2839 * to do referenced emulation. 2840 * OR 2841 * - The physical page has already been referenced 2842 * so no need to re-do referenced emulation here. 2843 */ 2844 npte |= l2pte_set_readonly(L2_S_PROTO); 2845 2846 nflags |= PVF_REF; 2847 2848 if ((prot & VM_PROT_WRITE) != 0 && 2849 ((flags & VM_PROT_WRITE) != 0 || 2850 (md->pvh_attrs & PVF_MOD) != 0)) { 2851 /* 2852 * This is a writable mapping, and the 2853 * page's mod state indicates it has 2854 * already been modified. Make it 2855 * writable from the outset. 2856 */ 2857 npte = l2pte_set_writable(npte); 2858 nflags |= PVF_MOD; 2859 } 2860 } else { 2861 /* 2862 * Need to do page referenced emulation. 2863 */ 2864 npte |= L2_TYPE_INV; 2865 } 2866 2867 npte |= pte_l2_s_cache_mode; 2868 2869 if (pg == opg) { 2870 /* 2871 * We're changing the attrs of an existing mapping. 2872 */ 2873 simple_lock(&md->pvh_slock); 2874 oflags = pmap_modify_pv(md, pa, pm, va, 2875 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2876 PVF_MOD | PVF_REF, nflags); 2877 simple_unlock(&md->pvh_slock); 2878 2879 #ifdef PMAP_CACHE_VIVT 2880 /* 2881 * We may need to flush the cache if we're 2882 * doing rw-ro... 2883 */ 2884 if (pm->pm_cstate.cs_cache_d && 2885 (oflags & PVF_NC) == 0 && 2886 l2pte_writable_p(opte) && 2887 (prot & VM_PROT_WRITE) == 0) 2888 cpu_dcache_wb_range(va, PAGE_SIZE); 2889 #endif 2890 } else { 2891 /* 2892 * New mapping, or changing the backing page 2893 * of an existing mapping. 2894 */ 2895 if (opg) { 2896 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2897 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2898 2899 /* 2900 * Replacing an existing mapping with a new one. 2901 * It is part of our managed memory so we 2902 * must remove it from the PV list 2903 */ 2904 simple_lock(&omd->pvh_slock); 2905 pv = pmap_remove_pv(omd, opa, pm, va); 2906 pmap_vac_me_harder(omd, opa, pm, 0); 2907 simple_unlock(&omd->pvh_slock); 2908 oflags = pv->pv_flags; 2909 2910 #ifdef PMAP_CACHE_VIVT 2911 /* 2912 * If the old mapping was valid (ref/mod 2913 * emulation creates 'invalid' mappings 2914 * initially) then make sure to frob 2915 * the cache. 2916 */ 2917 if ((oflags & PVF_NC) == 0 && 2918 l2pte_valid(opte)) { 2919 if (PV_BEEN_EXECD(oflags)) { 2920 pmap_idcache_wbinv_range(pm, va, 2921 PAGE_SIZE); 2922 } else 2923 if (PV_BEEN_REFD(oflags)) { 2924 pmap_dcache_wb_range(pm, va, 2925 PAGE_SIZE, true, 2926 (oflags & PVF_WRITE) == 0); 2927 } 2928 } 2929 #endif 2930 } else 2931 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2932 if ((flags & PMAP_CANFAIL) == 0) 2933 panic("pmap_enter: no pv entries"); 2934 2935 if (pm != pmap_kernel()) 2936 pmap_free_l2_bucket(pm, l2b, 0); 2937 pmap_release_pmap_lock(pm); 2938 PMAP_MAP_TO_HEAD_UNLOCK(); 2939 NPDEBUG(PDB_ENTER, 2940 printf("pmap_enter: ENOMEM\n")); 2941 return (ENOMEM); 2942 } 2943 2944 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2945 } 2946 } else { 2947 /* 2948 * We're mapping an unmanaged page. 2949 * These are always readable, and possibly writable, from 2950 * the get go as we don't need to track ref/mod status. 2951 */ 2952 npte |= l2pte_set_readonly(L2_S_PROTO); 2953 if (prot & VM_PROT_WRITE) 2954 npte = l2pte_set_writable(npte); 2955 2956 /* 2957 * Make sure the vector table is mapped cacheable 2958 */ 2959 if (pm != pmap_kernel() && va == vector_page) 2960 npte |= pte_l2_s_cache_mode; 2961 2962 if (opg) { 2963 /* 2964 * Looks like there's an existing 'managed' mapping 2965 * at this address. 2966 */ 2967 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2968 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2969 2970 simple_lock(&omd->pvh_slock); 2971 pv = pmap_remove_pv(omd, opa, pm, va); 2972 pmap_vac_me_harder(omd, opa, pm, 0); 2973 simple_unlock(&omd->pvh_slock); 2974 oflags = pv->pv_flags; 2975 2976 #ifdef PMAP_CACHE_VIVT 2977 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2978 if (PV_BEEN_EXECD(oflags)) 2979 pmap_idcache_wbinv_range(pm, va, 2980 PAGE_SIZE); 2981 else 2982 if (PV_BEEN_REFD(oflags)) 2983 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2984 true, (oflags & PVF_WRITE) == 0); 2985 } 2986 #endif 2987 pool_put(&pmap_pv_pool, pv); 2988 } 2989 } 2990 2991 /* 2992 * Make sure userland mappings get the right permissions 2993 */ 2994 if (pm != pmap_kernel() && va != vector_page) 2995 npte |= L2_S_PROT_U; 2996 2997 /* 2998 * Keep the stats up to date 2999 */ 3000 if (opte == 0) { 3001 l2b->l2b_occupancy++; 3002 pm->pm_stats.resident_count++; 3003 } 3004 3005 NPDEBUG(PDB_ENTER, 3006 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3007 3008 /* 3009 * If this is just a wiring change, the two PTEs will be 3010 * identical, so there's no need to update the page table. 3011 */ 3012 if (npte != opte) { 3013 bool is_cached = pmap_is_cached(pm); 3014 3015 *ptep = npte; 3016 if (is_cached) { 3017 /* 3018 * We only need to frob the cache/tlb if this pmap 3019 * is current 3020 */ 3021 PTE_SYNC(ptep); 3022 if (va != vector_page && l2pte_valid(npte)) { 3023 /* 3024 * This mapping is likely to be accessed as 3025 * soon as we return to userland. Fix up the 3026 * L1 entry to avoid taking another 3027 * page/domain fault. 3028 */ 3029 pd_entry_t *pl1pd, l1pd; 3030 3031 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3032 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3033 L1_C_PROTO; 3034 if (*pl1pd != l1pd) { 3035 *pl1pd = l1pd; 3036 PTE_SYNC(pl1pd); 3037 } 3038 } 3039 } 3040 3041 if (PV_BEEN_EXECD(oflags)) 3042 pmap_tlb_flushID_SE(pm, va); 3043 else 3044 if (PV_BEEN_REFD(oflags)) 3045 pmap_tlb_flushD_SE(pm, va); 3046 3047 NPDEBUG(PDB_ENTER, 3048 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3049 is_cached, pm->pm_cstate.cs_all)); 3050 3051 if (pg != NULL) { 3052 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3053 3054 simple_lock(&md->pvh_slock); 3055 pmap_vac_me_harder(md, pa, pm, va); 3056 simple_unlock(&md->pvh_slock); 3057 } 3058 } 3059 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3060 if (pg) { 3061 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3062 3063 simple_lock(&md->pvh_slock); 3064 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3065 KASSERT(((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0)); 3066 simple_unlock(&md->pvh_slock); 3067 } 3068 #endif 3069 3070 pmap_release_pmap_lock(pm); 3071 PMAP_MAP_TO_HEAD_UNLOCK(); 3072 3073 return (0); 3074 } 3075 3076 /* 3077 * pmap_remove() 3078 * 3079 * pmap_remove is responsible for nuking a number of mappings for a range 3080 * of virtual address space in the current pmap. To do this efficiently 3081 * is interesting, because in a number of cases a wide virtual address 3082 * range may be supplied that contains few actual mappings. So, the 3083 * optimisations are: 3084 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3085 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3086 * maybe do just a partial cache clean. This path of execution is 3087 * complicated by the fact that the cache must be flushed _before_ 3088 * the PTE is nuked, being a VAC :-) 3089 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3090 * all invalidations until pmap_update(), since pmap_remove_all() has 3091 * already flushed the cache. 3092 * 4. Maybe later fast-case a single page, but I don't think this is 3093 * going to make _that_ much difference overall. 3094 */ 3095 3096 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3097 3098 void 3099 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3100 { 3101 struct l2_bucket *l2b; 3102 vaddr_t next_bucket; 3103 pt_entry_t *ptep; 3104 u_int cleanlist_idx, total, cnt; 3105 struct { 3106 vaddr_t va; 3107 pt_entry_t *ptep; 3108 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3109 u_int mappings, is_exec, is_refd; 3110 3111 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3112 "eva=%08lx\n", pm, sva, eva)); 3113 3114 /* 3115 * we lock in the pmap => pv_head direction 3116 */ 3117 PMAP_MAP_TO_HEAD_LOCK(); 3118 pmap_acquire_pmap_lock(pm); 3119 3120 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3121 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3122 if (pm->pm_cstate.cs_tlb == 0) 3123 pm->pm_remove_all = true; 3124 } else 3125 cleanlist_idx = 0; 3126 3127 total = 0; 3128 3129 while (sva < eva) { 3130 /* 3131 * Do one L2 bucket's worth at a time. 3132 */ 3133 next_bucket = L2_NEXT_BUCKET(sva); 3134 if (next_bucket > eva) 3135 next_bucket = eva; 3136 3137 l2b = pmap_get_l2_bucket(pm, sva); 3138 if (l2b == NULL) { 3139 sva = next_bucket; 3140 continue; 3141 } 3142 3143 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3144 3145 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3146 struct vm_page *pg; 3147 pt_entry_t pte; 3148 paddr_t pa; 3149 3150 pte = *ptep; 3151 3152 if (pte == 0) { 3153 /* Nothing here, move along */ 3154 continue; 3155 } 3156 3157 pa = l2pte_pa(pte); 3158 is_exec = 0; 3159 is_refd = 1; 3160 3161 /* 3162 * Update flags. In a number of circumstances, 3163 * we could cluster a lot of these and do a 3164 * number of sequential pages in one go. 3165 */ 3166 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3167 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3168 struct pv_entry *pv; 3169 3170 simple_lock(&md->pvh_slock); 3171 pv = pmap_remove_pv(md, pa, pm, sva); 3172 pmap_vac_me_harder(md, pa, pm, 0); 3173 simple_unlock(&md->pvh_slock); 3174 if (pv != NULL) { 3175 if (pm->pm_remove_all == false) { 3176 is_exec = 3177 PV_BEEN_EXECD(pv->pv_flags); 3178 is_refd = 3179 PV_BEEN_REFD(pv->pv_flags); 3180 } 3181 pool_put(&pmap_pv_pool, pv); 3182 } 3183 } 3184 mappings++; 3185 3186 if (!l2pte_valid(pte)) { 3187 /* 3188 * Ref/Mod emulation is still active for this 3189 * mapping, therefore it is has not yet been 3190 * accessed. No need to frob the cache/tlb. 3191 */ 3192 *ptep = 0; 3193 PTE_SYNC_CURRENT(pm, ptep); 3194 continue; 3195 } 3196 3197 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3198 /* Add to the clean list. */ 3199 cleanlist[cleanlist_idx].ptep = ptep; 3200 cleanlist[cleanlist_idx].va = 3201 sva | (is_exec & 1); 3202 cleanlist_idx++; 3203 } else 3204 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3205 /* Nuke everything if needed. */ 3206 #ifdef PMAP_CACHE_VIVT 3207 pmap_idcache_wbinv_all(pm); 3208 #endif 3209 pmap_tlb_flushID(pm); 3210 3211 /* 3212 * Roll back the previous PTE list, 3213 * and zero out the current PTE. 3214 */ 3215 for (cnt = 0; 3216 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3217 *cleanlist[cnt].ptep = 0; 3218 PTE_SYNC(cleanlist[cnt].ptep); 3219 } 3220 *ptep = 0; 3221 PTE_SYNC(ptep); 3222 cleanlist_idx++; 3223 pm->pm_remove_all = true; 3224 } else { 3225 *ptep = 0; 3226 PTE_SYNC(ptep); 3227 if (pm->pm_remove_all == false) { 3228 if (is_exec) 3229 pmap_tlb_flushID_SE(pm, sva); 3230 else 3231 if (is_refd) 3232 pmap_tlb_flushD_SE(pm, sva); 3233 } 3234 } 3235 } 3236 3237 /* 3238 * Deal with any left overs 3239 */ 3240 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3241 total += cleanlist_idx; 3242 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3243 if (pm->pm_cstate.cs_all != 0) { 3244 vaddr_t clva = cleanlist[cnt].va & ~1; 3245 if (cleanlist[cnt].va & 1) { 3246 #ifdef PMAP_CACHE_VIVT 3247 pmap_idcache_wbinv_range(pm, 3248 clva, PAGE_SIZE); 3249 #endif 3250 pmap_tlb_flushID_SE(pm, clva); 3251 } else { 3252 #ifdef PMAP_CACHE_VIVT 3253 pmap_dcache_wb_range(pm, 3254 clva, PAGE_SIZE, true, 3255 false); 3256 #endif 3257 pmap_tlb_flushD_SE(pm, clva); 3258 } 3259 } 3260 *cleanlist[cnt].ptep = 0; 3261 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3262 } 3263 3264 /* 3265 * If it looks like we're removing a whole bunch 3266 * of mappings, it's faster to just write-back 3267 * the whole cache now and defer TLB flushes until 3268 * pmap_update() is called. 3269 */ 3270 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3271 cleanlist_idx = 0; 3272 else { 3273 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3274 #ifdef PMAP_CACHE_VIVT 3275 pmap_idcache_wbinv_all(pm); 3276 #endif 3277 pm->pm_remove_all = true; 3278 } 3279 } 3280 3281 pmap_free_l2_bucket(pm, l2b, mappings); 3282 pm->pm_stats.resident_count -= mappings; 3283 } 3284 3285 pmap_release_pmap_lock(pm); 3286 PMAP_MAP_TO_HEAD_UNLOCK(); 3287 } 3288 3289 #ifdef PMAP_CACHE_VIPT 3290 static struct pv_entry * 3291 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3292 { 3293 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3294 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3295 struct pv_entry *pv; 3296 3297 simple_lock(&md->pvh_slock); 3298 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3299 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3300 3301 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3302 KASSERT(pv); 3303 KASSERT(pv->pv_flags & PVF_KENTRY); 3304 3305 /* 3306 * If we are removing a writeable mapping to a cached exec page, 3307 * if it's the last mapping then clear it execness other sync 3308 * the page to the icache. 3309 */ 3310 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3311 && (pv->pv_flags & PVF_WRITE) != 0) { 3312 if (SLIST_EMPTY(&md->pvh_list)) { 3313 md->pvh_attrs &= ~PVF_EXEC; 3314 PMAPCOUNT(exec_discarded_kremove); 3315 } else { 3316 pmap_syncicache_page(md, pa); 3317 PMAPCOUNT(exec_synced_kremove); 3318 } 3319 } 3320 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3321 simple_unlock(&md->pvh_slock); 3322 3323 return pv; 3324 } 3325 #endif /* PMAP_CACHE_VIPT */ 3326 3327 /* 3328 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3329 * 3330 * We assume there is already sufficient KVM space available 3331 * to do this, as we can't allocate L2 descriptor tables/metadata 3332 * from here. 3333 */ 3334 void 3335 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3336 { 3337 struct l2_bucket *l2b; 3338 pt_entry_t *ptep, opte; 3339 #ifdef PMAP_CACHE_VIVT 3340 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3341 #endif 3342 #ifdef PMAP_CACHE_VIPT 3343 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3344 struct vm_page *opg; 3345 struct pv_entry *pv = NULL; 3346 #endif 3347 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3348 3349 NPDEBUG(PDB_KENTER, 3350 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3351 va, pa, prot)); 3352 3353 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3354 KDASSERT(l2b != NULL); 3355 3356 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3357 opte = *ptep; 3358 3359 if (opte == 0) { 3360 PMAPCOUNT(kenter_mappings); 3361 l2b->l2b_occupancy++; 3362 } else { 3363 PMAPCOUNT(kenter_remappings); 3364 #ifdef PMAP_CACHE_VIPT 3365 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3366 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3367 if (opg) { 3368 KASSERT(opg != pg); 3369 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3370 KASSERT((flags & PMAP_KMPAGE) == 0); 3371 simple_lock(&omd->pvh_slock); 3372 pv = pmap_kremove_pg(opg, va); 3373 simple_unlock(&omd->pvh_slock); 3374 } 3375 #endif 3376 if (l2pte_valid(opte)) { 3377 #ifdef PMAP_CACHE_VIVT 3378 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3379 #endif 3380 cpu_tlb_flushD_SE(va); 3381 cpu_cpwait(); 3382 } 3383 } 3384 3385 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3386 pte_l2_s_cache_mode; 3387 PTE_SYNC(ptep); 3388 3389 if (pg) { 3390 if (flags & PMAP_KMPAGE) { 3391 simple_lock(&md->pvh_slock); 3392 KASSERT(md->urw_mappings == 0); 3393 KASSERT(md->uro_mappings == 0); 3394 KASSERT(md->krw_mappings == 0); 3395 KASSERT(md->kro_mappings == 0); 3396 #ifdef PMAP_CACHE_VIPT 3397 KASSERT(pv == NULL); 3398 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3399 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3400 /* if there is a color conflict, evict from cache. */ 3401 if (pmap_is_page_colored_p(md) 3402 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3403 PMAPCOUNT(vac_color_change); 3404 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3405 } else if (md->pvh_attrs & PVF_MULTCLR) { 3406 /* 3407 * If this page has multiple colors, expunge 3408 * them. 3409 */ 3410 PMAPCOUNT(vac_flush_lots2); 3411 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3412 } 3413 md->pvh_attrs &= PAGE_SIZE - 1; 3414 md->pvh_attrs |= PVF_KMPAGE 3415 | PVF_COLORED | PVF_DIRTY 3416 | (va & arm_cache_prefer_mask); 3417 #endif 3418 #ifdef PMAP_CACHE_VIVT 3419 md->pvh_attrs |= PVF_KMPAGE; 3420 #endif 3421 pmap_kmpages++; 3422 simple_unlock(&md->pvh_slock); 3423 #ifdef PMAP_CACHE_VIPT 3424 } else { 3425 if (pv == NULL) { 3426 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3427 KASSERT(pv != NULL); 3428 } 3429 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3430 PVF_WIRED | PVF_KENTRY 3431 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3432 if ((prot & VM_PROT_WRITE) 3433 && !(md->pvh_attrs & PVF_NC)) 3434 md->pvh_attrs |= PVF_DIRTY; 3435 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3436 simple_lock(&md->pvh_slock); 3437 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3438 simple_unlock(&md->pvh_slock); 3439 #endif 3440 } 3441 #ifdef PMAP_CACHE_VIPT 3442 } else { 3443 if (pv != NULL) 3444 pool_put(&pmap_pv_pool, pv); 3445 #endif 3446 } 3447 } 3448 3449 void 3450 pmap_kremove(vaddr_t va, vsize_t len) 3451 { 3452 struct l2_bucket *l2b; 3453 pt_entry_t *ptep, *sptep, opte; 3454 vaddr_t next_bucket, eva; 3455 u_int mappings; 3456 struct vm_page *opg; 3457 3458 PMAPCOUNT(kenter_unmappings); 3459 3460 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3461 va, len)); 3462 3463 eva = va + len; 3464 3465 while (va < eva) { 3466 next_bucket = L2_NEXT_BUCKET(va); 3467 if (next_bucket > eva) 3468 next_bucket = eva; 3469 3470 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3471 KDASSERT(l2b != NULL); 3472 3473 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3474 mappings = 0; 3475 3476 while (va < next_bucket) { 3477 opte = *ptep; 3478 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3479 if (opg) { 3480 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3481 3482 if (omd->pvh_attrs & PVF_KMPAGE) { 3483 simple_lock(&omd->pvh_slock); 3484 KASSERT(omd->urw_mappings == 0); 3485 KASSERT(omd->uro_mappings == 0); 3486 KASSERT(omd->krw_mappings == 0); 3487 KASSERT(omd->kro_mappings == 0); 3488 omd->pvh_attrs &= ~PVF_KMPAGE; 3489 #ifdef PMAP_CACHE_VIPT 3490 omd->pvh_attrs &= ~PVF_WRITE; 3491 #endif 3492 pmap_kmpages--; 3493 simple_unlock(&omd->pvh_slock); 3494 #ifdef PMAP_CACHE_VIPT 3495 } else { 3496 pool_put(&pmap_pv_pool, 3497 pmap_kremove_pg(opg, va)); 3498 #endif 3499 } 3500 } 3501 if (l2pte_valid(opte)) { 3502 #ifdef PMAP_CACHE_VIVT 3503 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3504 #endif 3505 cpu_tlb_flushD_SE(va); 3506 } 3507 if (opte) { 3508 *ptep = 0; 3509 mappings++; 3510 } 3511 va += PAGE_SIZE; 3512 ptep++; 3513 } 3514 KDASSERT(mappings <= l2b->l2b_occupancy); 3515 l2b->l2b_occupancy -= mappings; 3516 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3517 } 3518 cpu_cpwait(); 3519 } 3520 3521 bool 3522 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3523 { 3524 struct l2_dtable *l2; 3525 pd_entry_t *pl1pd, l1pd; 3526 pt_entry_t *ptep, pte; 3527 paddr_t pa; 3528 u_int l1idx; 3529 3530 pmap_acquire_pmap_lock(pm); 3531 3532 l1idx = L1_IDX(va); 3533 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3534 l1pd = *pl1pd; 3535 3536 if (l1pte_section_p(l1pd)) { 3537 /* 3538 * These should only happen for pmap_kernel() 3539 */ 3540 KDASSERT(pm == pmap_kernel()); 3541 pmap_release_pmap_lock(pm); 3542 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3543 } else { 3544 /* 3545 * Note that we can't rely on the validity of the L1 3546 * descriptor as an indication that a mapping exists. 3547 * We have to look it up in the L2 dtable. 3548 */ 3549 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3550 3551 if (l2 == NULL || 3552 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3553 pmap_release_pmap_lock(pm); 3554 return false; 3555 } 3556 3557 ptep = &ptep[l2pte_index(va)]; 3558 pte = *ptep; 3559 pmap_release_pmap_lock(pm); 3560 3561 if (pte == 0) 3562 return false; 3563 3564 switch (pte & L2_TYPE_MASK) { 3565 case L2_TYPE_L: 3566 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3567 break; 3568 3569 default: 3570 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3571 break; 3572 } 3573 } 3574 3575 if (pap != NULL) 3576 *pap = pa; 3577 3578 return true; 3579 } 3580 3581 void 3582 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3583 { 3584 struct l2_bucket *l2b; 3585 pt_entry_t *ptep, pte; 3586 vaddr_t next_bucket; 3587 u_int flags; 3588 u_int clr_mask; 3589 int flush; 3590 3591 NPDEBUG(PDB_PROTECT, 3592 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3593 pm, sva, eva, prot)); 3594 3595 if ((prot & VM_PROT_READ) == 0) { 3596 pmap_remove(pm, sva, eva); 3597 return; 3598 } 3599 3600 if (prot & VM_PROT_WRITE) { 3601 /* 3602 * If this is a read->write transition, just ignore it and let 3603 * uvm_fault() take care of it later. 3604 */ 3605 return; 3606 } 3607 3608 PMAP_MAP_TO_HEAD_LOCK(); 3609 pmap_acquire_pmap_lock(pm); 3610 3611 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3612 flags = 0; 3613 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3614 3615 while (sva < eva) { 3616 next_bucket = L2_NEXT_BUCKET(sva); 3617 if (next_bucket > eva) 3618 next_bucket = eva; 3619 3620 l2b = pmap_get_l2_bucket(pm, sva); 3621 if (l2b == NULL) { 3622 sva = next_bucket; 3623 continue; 3624 } 3625 3626 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3627 3628 while (sva < next_bucket) { 3629 pte = *ptep; 3630 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3631 struct vm_page *pg; 3632 u_int f; 3633 3634 #ifdef PMAP_CACHE_VIVT 3635 /* 3636 * OK, at this point, we know we're doing 3637 * write-protect operation. If the pmap is 3638 * active, write-back the page. 3639 */ 3640 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3641 false, false); 3642 #endif 3643 3644 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3645 pte = l2pte_set_readonly(pte); 3646 *ptep = pte; 3647 PTE_SYNC(ptep); 3648 3649 if (pg != NULL) { 3650 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3651 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3652 3653 simple_lock(&md->pvh_slock); 3654 f = pmap_modify_pv(md, pa, pm, sva, 3655 clr_mask, 0); 3656 pmap_vac_me_harder(md, pa, pm, sva); 3657 simple_unlock(&md->pvh_slock); 3658 } else 3659 f = PVF_REF | PVF_EXEC; 3660 3661 if (flush >= 0) { 3662 flush++; 3663 flags |= f; 3664 } else 3665 if (PV_BEEN_EXECD(f)) 3666 pmap_tlb_flushID_SE(pm, sva); 3667 else 3668 if (PV_BEEN_REFD(f)) 3669 pmap_tlb_flushD_SE(pm, sva); 3670 } 3671 3672 sva += PAGE_SIZE; 3673 ptep++; 3674 } 3675 } 3676 3677 pmap_release_pmap_lock(pm); 3678 PMAP_MAP_TO_HEAD_UNLOCK(); 3679 3680 if (flush) { 3681 if (PV_BEEN_EXECD(flags)) 3682 pmap_tlb_flushID(pm); 3683 else 3684 if (PV_BEEN_REFD(flags)) 3685 pmap_tlb_flushD(pm); 3686 } 3687 } 3688 3689 void 3690 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3691 { 3692 struct l2_bucket *l2b; 3693 pt_entry_t *ptep; 3694 vaddr_t next_bucket; 3695 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3696 3697 NPDEBUG(PDB_EXEC, 3698 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3699 pm, sva, eva)); 3700 3701 PMAP_MAP_TO_HEAD_LOCK(); 3702 pmap_acquire_pmap_lock(pm); 3703 3704 while (sva < eva) { 3705 next_bucket = L2_NEXT_BUCKET(sva); 3706 if (next_bucket > eva) 3707 next_bucket = eva; 3708 3709 l2b = pmap_get_l2_bucket(pm, sva); 3710 if (l2b == NULL) { 3711 sva = next_bucket; 3712 continue; 3713 } 3714 3715 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3716 sva < next_bucket; 3717 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3718 if (l2pte_valid(*ptep)) { 3719 cpu_icache_sync_range(sva, 3720 min(page_size, eva - sva)); 3721 } 3722 } 3723 } 3724 3725 pmap_release_pmap_lock(pm); 3726 PMAP_MAP_TO_HEAD_UNLOCK(); 3727 } 3728 3729 void 3730 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3731 { 3732 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3733 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3734 3735 NPDEBUG(PDB_PROTECT, 3736 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3737 md, pa, prot)); 3738 3739 switch(prot) { 3740 case VM_PROT_READ|VM_PROT_WRITE: 3741 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3742 pmap_clearbit(md, pa, PVF_EXEC); 3743 break; 3744 #endif 3745 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3746 break; 3747 3748 case VM_PROT_READ: 3749 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3750 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3751 break; 3752 #endif 3753 case VM_PROT_READ|VM_PROT_EXECUTE: 3754 pmap_clearbit(md, pa, PVF_WRITE); 3755 break; 3756 3757 default: 3758 pmap_page_remove(md, pa); 3759 break; 3760 } 3761 } 3762 3763 /* 3764 * pmap_clear_modify: 3765 * 3766 * Clear the "modified" attribute for a page. 3767 */ 3768 bool 3769 pmap_clear_modify(struct vm_page *pg) 3770 { 3771 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3772 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3773 bool rv; 3774 3775 if (md->pvh_attrs & PVF_MOD) { 3776 rv = true; 3777 #ifdef PMAP_CACHE_VIPT 3778 /* 3779 * If we are going to clear the modified bit and there are 3780 * no other modified bits set, flush the page to memory and 3781 * mark it clean. 3782 */ 3783 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3784 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3785 #endif 3786 pmap_clearbit(md, pa, PVF_MOD); 3787 } else 3788 rv = false; 3789 3790 return (rv); 3791 } 3792 3793 /* 3794 * pmap_clear_reference: 3795 * 3796 * Clear the "referenced" attribute for a page. 3797 */ 3798 bool 3799 pmap_clear_reference(struct vm_page *pg) 3800 { 3801 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3802 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3803 bool rv; 3804 3805 if (md->pvh_attrs & PVF_REF) { 3806 rv = true; 3807 pmap_clearbit(md, pa, PVF_REF); 3808 } else 3809 rv = false; 3810 3811 return (rv); 3812 } 3813 3814 /* 3815 * pmap_is_modified: 3816 * 3817 * Test if a page has the "modified" attribute. 3818 */ 3819 /* See <arm/arm32/pmap.h> */ 3820 3821 /* 3822 * pmap_is_referenced: 3823 * 3824 * Test if a page has the "referenced" attribute. 3825 */ 3826 /* See <arm/arm32/pmap.h> */ 3827 3828 int 3829 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3830 { 3831 struct l2_dtable *l2; 3832 struct l2_bucket *l2b; 3833 pd_entry_t *pl1pd, l1pd; 3834 pt_entry_t *ptep, pte; 3835 paddr_t pa; 3836 u_int l1idx; 3837 int rv = 0; 3838 3839 PMAP_MAP_TO_HEAD_LOCK(); 3840 pmap_acquire_pmap_lock(pm); 3841 3842 l1idx = L1_IDX(va); 3843 3844 /* 3845 * If there is no l2_dtable for this address, then the process 3846 * has no business accessing it. 3847 * 3848 * Note: This will catch userland processes trying to access 3849 * kernel addresses. 3850 */ 3851 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3852 if (l2 == NULL) 3853 goto out; 3854 3855 /* 3856 * Likewise if there is no L2 descriptor table 3857 */ 3858 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3859 if (l2b->l2b_kva == NULL) 3860 goto out; 3861 3862 /* 3863 * Check the PTE itself. 3864 */ 3865 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3866 pte = *ptep; 3867 if (pte == 0) 3868 goto out; 3869 3870 /* 3871 * Catch a userland access to the vector page mapped at 0x0 3872 */ 3873 if (user && (pte & L2_S_PROT_U) == 0) 3874 goto out; 3875 3876 pa = l2pte_pa(pte); 3877 3878 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3879 /* 3880 * This looks like a good candidate for "page modified" 3881 * emulation... 3882 */ 3883 struct pv_entry *pv; 3884 struct vm_page *pg; 3885 3886 /* Extract the physical address of the page */ 3887 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3888 goto out; 3889 3890 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3891 3892 /* Get the current flags for this page. */ 3893 simple_lock(&md->pvh_slock); 3894 3895 pv = pmap_find_pv(md, pm, va); 3896 if (pv == NULL) { 3897 simple_unlock(&md->pvh_slock); 3898 goto out; 3899 } 3900 3901 /* 3902 * Do the flags say this page is writable? If not then it 3903 * is a genuine write fault. If yes then the write fault is 3904 * our fault as we did not reflect the write access in the 3905 * PTE. Now we know a write has occurred we can correct this 3906 * and also set the modified bit 3907 */ 3908 if ((pv->pv_flags & PVF_WRITE) == 0) { 3909 simple_unlock(&md->pvh_slock); 3910 goto out; 3911 } 3912 3913 NPDEBUG(PDB_FOLLOW, 3914 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3915 pm, va, pa)); 3916 3917 md->pvh_attrs |= PVF_REF | PVF_MOD; 3918 pv->pv_flags |= PVF_REF | PVF_MOD; 3919 #ifdef PMAP_CACHE_VIPT 3920 /* 3921 * If there are cacheable mappings for this page, mark it dirty. 3922 */ 3923 if ((md->pvh_attrs & PVF_NC) == 0) 3924 md->pvh_attrs |= PVF_DIRTY; 3925 #endif 3926 simple_unlock(&md->pvh_slock); 3927 3928 /* 3929 * Re-enable write permissions for the page. No need to call 3930 * pmap_vac_me_harder(), since this is just a 3931 * modified-emulation fault, and the PVF_WRITE bit isn't 3932 * changing. We've already set the cacheable bits based on 3933 * the assumption that we can write to this page. 3934 */ 3935 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3936 PTE_SYNC(ptep); 3937 rv = 1; 3938 } else 3939 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3940 /* 3941 * This looks like a good candidate for "page referenced" 3942 * emulation. 3943 */ 3944 struct pv_entry *pv; 3945 struct vm_page *pg; 3946 3947 /* Extract the physical address of the page */ 3948 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3949 goto out; 3950 3951 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3952 3953 /* Get the current flags for this page. */ 3954 simple_lock(&md->pvh_slock); 3955 3956 pv = pmap_find_pv(md, pm, va); 3957 if (pv == NULL) { 3958 simple_unlock(&md->pvh_slock); 3959 goto out; 3960 } 3961 3962 md->pvh_attrs |= PVF_REF; 3963 pv->pv_flags |= PVF_REF; 3964 simple_unlock(&md->pvh_slock); 3965 3966 NPDEBUG(PDB_FOLLOW, 3967 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3968 pm, va, pa)); 3969 3970 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3971 PTE_SYNC(ptep); 3972 rv = 1; 3973 } 3974 3975 /* 3976 * We know there is a valid mapping here, so simply 3977 * fix up the L1 if necessary. 3978 */ 3979 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3980 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3981 if (*pl1pd != l1pd) { 3982 *pl1pd = l1pd; 3983 PTE_SYNC(pl1pd); 3984 rv = 1; 3985 } 3986 3987 #ifdef CPU_SA110 3988 /* 3989 * There are bugs in the rev K SA110. This is a check for one 3990 * of them. 3991 */ 3992 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3993 curcpu()->ci_arm_cpurev < 3) { 3994 /* Always current pmap */ 3995 if (l2pte_valid(pte)) { 3996 extern int kernel_debug; 3997 if (kernel_debug & 1) { 3998 struct proc *p = curlwp->l_proc; 3999 printf("prefetch_abort: page is already " 4000 "mapped - pte=%p *pte=%08x\n", ptep, pte); 4001 printf("prefetch_abort: pc=%08lx proc=%p " 4002 "process=%s\n", va, p, p->p_comm); 4003 printf("prefetch_abort: far=%08x fs=%x\n", 4004 cpu_faultaddress(), cpu_faultstatus()); 4005 } 4006 #ifdef DDB 4007 if (kernel_debug & 2) 4008 Debugger(); 4009 #endif 4010 rv = 1; 4011 } 4012 } 4013 #endif /* CPU_SA110 */ 4014 4015 #ifdef DEBUG 4016 /* 4017 * If 'rv == 0' at this point, it generally indicates that there is a 4018 * stale TLB entry for the faulting address. This happens when two or 4019 * more processes are sharing an L1. Since we don't flush the TLB on 4020 * a context switch between such processes, we can take domain faults 4021 * for mappings which exist at the same VA in both processes. EVEN IF 4022 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4023 * example. 4024 * 4025 * This is extremely likely to happen if pmap_enter() updated the L1 4026 * entry for a recently entered mapping. In this case, the TLB is 4027 * flushed for the new mapping, but there may still be TLB entries for 4028 * other mappings belonging to other processes in the 1MB range 4029 * covered by the L1 entry. 4030 * 4031 * Since 'rv == 0', we know that the L1 already contains the correct 4032 * value, so the fault must be due to a stale TLB entry. 4033 * 4034 * Since we always need to flush the TLB anyway in the case where we 4035 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4036 * stale TLB entries dynamically. 4037 * 4038 * However, the above condition can ONLY happen if the current L1 is 4039 * being shared. If it happens when the L1 is unshared, it indicates 4040 * that other parts of the pmap are not doing their job WRT managing 4041 * the TLB. 4042 */ 4043 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4044 extern int last_fault_code; 4045 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4046 pm, va, ftype); 4047 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4048 l2, l2b, ptep, pl1pd); 4049 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4050 pte, l1pd, last_fault_code); 4051 #ifdef DDB 4052 Debugger(); 4053 #endif 4054 } 4055 #endif 4056 4057 cpu_tlb_flushID_SE(va); 4058 cpu_cpwait(); 4059 4060 rv = 1; 4061 4062 out: 4063 pmap_release_pmap_lock(pm); 4064 PMAP_MAP_TO_HEAD_UNLOCK(); 4065 4066 return (rv); 4067 } 4068 4069 /* 4070 * Routine: pmap_procwr 4071 * 4072 * Function: 4073 * Synchronize caches corresponding to [addr, addr+len) in p. 4074 * 4075 */ 4076 void 4077 pmap_procwr(struct proc *p, vaddr_t va, int len) 4078 { 4079 /* We only need to do anything if it is the current process. */ 4080 if (p == curproc) 4081 cpu_icache_sync_range(va, len); 4082 } 4083 4084 /* 4085 * Routine: pmap_unwire 4086 * Function: Clear the wired attribute for a map/virtual-address pair. 4087 * 4088 * In/out conditions: 4089 * The mapping must already exist in the pmap. 4090 */ 4091 void 4092 pmap_unwire(pmap_t pm, vaddr_t va) 4093 { 4094 struct l2_bucket *l2b; 4095 pt_entry_t *ptep, pte; 4096 struct vm_page *pg; 4097 paddr_t pa; 4098 4099 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4100 4101 PMAP_MAP_TO_HEAD_LOCK(); 4102 pmap_acquire_pmap_lock(pm); 4103 4104 l2b = pmap_get_l2_bucket(pm, va); 4105 KDASSERT(l2b != NULL); 4106 4107 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4108 pte = *ptep; 4109 4110 /* Extract the physical address of the page */ 4111 pa = l2pte_pa(pte); 4112 4113 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4114 /* Update the wired bit in the pv entry for this page. */ 4115 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4116 4117 simple_lock(&md->pvh_slock); 4118 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4119 simple_unlock(&md->pvh_slock); 4120 } 4121 4122 pmap_release_pmap_lock(pm); 4123 PMAP_MAP_TO_HEAD_UNLOCK(); 4124 } 4125 4126 void 4127 pmap_activate(struct lwp *l) 4128 { 4129 extern int block_userspace_access; 4130 pmap_t opm, npm, rpm; 4131 uint32_t odacr, ndacr; 4132 int oldirqstate; 4133 4134 /* 4135 * If activating a non-current lwp or the current lwp is 4136 * already active, just return. 4137 */ 4138 if (l != curlwp || 4139 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4140 return; 4141 4142 npm = l->l_proc->p_vmspace->vm_map.pmap; 4143 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4144 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4145 4146 /* 4147 * If TTB and DACR are unchanged, short-circuit all the 4148 * TLB/cache management stuff. 4149 */ 4150 if (pmap_previous_active_lwp != NULL) { 4151 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4152 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4153 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4154 4155 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4156 goto all_done; 4157 } else 4158 opm = NULL; 4159 4160 PMAPCOUNT(activations); 4161 block_userspace_access = 1; 4162 4163 /* 4164 * If switching to a user vmspace which is different to the 4165 * most recent one, and the most recent one is potentially 4166 * live in the cache, we must write-back and invalidate the 4167 * entire cache. 4168 */ 4169 rpm = pmap_recent_user; 4170 4171 /* 4172 * XXXSCW: There's a corner case here which can leave turds in the cache as 4173 * reported in kern/41058. They're probably left over during tear-down and 4174 * switching away from an exiting process. Until the root cause is identified 4175 * and fixed, zap the cache when switching pmaps. This will result in a few 4176 * unnecessary cache flushes, but that's better than silently corrupting data. 4177 */ 4178 #if 0 4179 if (npm != pmap_kernel() && rpm && npm != rpm && 4180 rpm->pm_cstate.cs_cache) { 4181 rpm->pm_cstate.cs_cache = 0; 4182 #ifdef PMAP_CACHE_VIVT 4183 cpu_idcache_wbinv_all(); 4184 #endif 4185 } 4186 #else 4187 if (rpm) { 4188 rpm->pm_cstate.cs_cache = 0; 4189 if (npm == pmap_kernel()) 4190 pmap_recent_user = NULL; 4191 #ifdef PMAP_CACHE_VIVT 4192 cpu_idcache_wbinv_all(); 4193 #endif 4194 } 4195 #endif 4196 4197 /* No interrupts while we frob the TTB/DACR */ 4198 oldirqstate = disable_interrupts(IF32_bits); 4199 4200 /* 4201 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4202 * entry corresponding to 'vector_page' in the incoming L1 table 4203 * before switching to it otherwise subsequent interrupts/exceptions 4204 * (including domain faults!) will jump into hyperspace. 4205 */ 4206 if (npm->pm_pl1vec != NULL) { 4207 cpu_tlb_flushID_SE((u_int)vector_page); 4208 cpu_cpwait(); 4209 *npm->pm_pl1vec = npm->pm_l1vec; 4210 PTE_SYNC(npm->pm_pl1vec); 4211 } 4212 4213 cpu_domains(ndacr); 4214 4215 if (npm == pmap_kernel() || npm == rpm) { 4216 /* 4217 * Switching to a kernel thread, or back to the 4218 * same user vmspace as before... Simply update 4219 * the TTB (no TLB flush required) 4220 */ 4221 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4222 "r"(npm->pm_l1->l1_physaddr)); 4223 cpu_cpwait(); 4224 } else { 4225 /* 4226 * Otherwise, update TTB and flush TLB 4227 */ 4228 cpu_context_switch(npm->pm_l1->l1_physaddr); 4229 if (rpm != NULL) 4230 rpm->pm_cstate.cs_tlb = 0; 4231 } 4232 4233 restore_interrupts(oldirqstate); 4234 4235 block_userspace_access = 0; 4236 4237 all_done: 4238 /* 4239 * The new pmap is resident. Make sure it's marked 4240 * as resident in the cache/TLB. 4241 */ 4242 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4243 if (npm != pmap_kernel()) 4244 pmap_recent_user = npm; 4245 4246 /* The old pmap is not longer active */ 4247 if (opm != NULL) 4248 opm->pm_activated = false; 4249 4250 /* But the new one is */ 4251 npm->pm_activated = true; 4252 } 4253 4254 void 4255 pmap_deactivate(struct lwp *l) 4256 { 4257 4258 /* 4259 * If the process is exiting, make sure pmap_activate() does 4260 * a full MMU context-switch and cache flush, which we might 4261 * otherwise skip. See PR port-arm/38950. 4262 */ 4263 if (l->l_proc->p_sflag & PS_WEXIT) 4264 pmap_previous_active_lwp = NULL; 4265 4266 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4267 } 4268 4269 void 4270 pmap_update(pmap_t pm) 4271 { 4272 4273 if (pm->pm_remove_all) { 4274 /* 4275 * Finish up the pmap_remove_all() optimisation by flushing 4276 * the TLB. 4277 */ 4278 pmap_tlb_flushID(pm); 4279 pm->pm_remove_all = false; 4280 } 4281 4282 if (pmap_is_current(pm)) { 4283 /* 4284 * If we're dealing with a current userland pmap, move its L1 4285 * to the end of the LRU. 4286 */ 4287 if (pm != pmap_kernel()) 4288 pmap_use_l1(pm); 4289 4290 /* 4291 * We can assume we're done with frobbing the cache/tlb for 4292 * now. Make sure any future pmap ops don't skip cache/tlb 4293 * flushes. 4294 */ 4295 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4296 } 4297 4298 PMAPCOUNT(updates); 4299 4300 /* 4301 * make sure TLB/cache operations have completed. 4302 */ 4303 cpu_cpwait(); 4304 } 4305 4306 void 4307 pmap_remove_all(pmap_t pm) 4308 { 4309 4310 /* 4311 * The vmspace described by this pmap is about to be torn down. 4312 * Until pmap_update() is called, UVM will only make calls 4313 * to pmap_remove(). We can make life much simpler by flushing 4314 * the cache now, and deferring TLB invalidation to pmap_update(). 4315 */ 4316 #ifdef PMAP_CACHE_VIVT 4317 pmap_idcache_wbinv_all(pm); 4318 #endif 4319 pm->pm_remove_all = true; 4320 } 4321 4322 /* 4323 * Retire the given physical map from service. 4324 * Should only be called if the map contains no valid mappings. 4325 */ 4326 void 4327 pmap_destroy(pmap_t pm) 4328 { 4329 u_int count; 4330 4331 if (pm == NULL) 4332 return; 4333 4334 if (pm->pm_remove_all) { 4335 pmap_tlb_flushID(pm); 4336 pm->pm_remove_all = false; 4337 } 4338 4339 /* 4340 * Drop reference count 4341 */ 4342 mutex_enter(&pm->pm_lock); 4343 count = --pm->pm_obj.uo_refs; 4344 mutex_exit(&pm->pm_lock); 4345 if (count > 0) { 4346 if (pmap_is_current(pm)) { 4347 if (pm != pmap_kernel()) 4348 pmap_use_l1(pm); 4349 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4350 } 4351 return; 4352 } 4353 4354 /* 4355 * reference count is zero, free pmap resources and then free pmap. 4356 */ 4357 4358 if (vector_page < KERNEL_BASE) { 4359 KDASSERT(!pmap_is_current(pm)); 4360 4361 /* Remove the vector page mapping */ 4362 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4363 pmap_update(pm); 4364 } 4365 4366 LIST_REMOVE(pm, pm_list); 4367 4368 pmap_free_l1(pm); 4369 4370 if (pmap_recent_user == pm) 4371 pmap_recent_user = NULL; 4372 4373 UVM_OBJ_DESTROY(&pm->pm_obj); 4374 4375 /* return the pmap to the pool */ 4376 pool_cache_put(&pmap_cache, pm); 4377 } 4378 4379 4380 /* 4381 * void pmap_reference(pmap_t pm) 4382 * 4383 * Add a reference to the specified pmap. 4384 */ 4385 void 4386 pmap_reference(pmap_t pm) 4387 { 4388 4389 if (pm == NULL) 4390 return; 4391 4392 pmap_use_l1(pm); 4393 4394 mutex_enter(&pm->pm_lock); 4395 pm->pm_obj.uo_refs++; 4396 mutex_exit(&pm->pm_lock); 4397 } 4398 4399 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4400 4401 static struct evcnt pmap_prefer_nochange_ev = 4402 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4403 static struct evcnt pmap_prefer_change_ev = 4404 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4405 4406 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4407 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4408 4409 void 4410 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4411 { 4412 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4413 vaddr_t va = *vap; 4414 vaddr_t diff = (hint - va) & mask; 4415 if (diff == 0) { 4416 pmap_prefer_nochange_ev.ev_count++; 4417 } else { 4418 pmap_prefer_change_ev.ev_count++; 4419 if (__predict_false(td)) 4420 va -= mask + 1; 4421 *vap = va + diff; 4422 } 4423 } 4424 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4425 4426 /* 4427 * pmap_zero_page() 4428 * 4429 * Zero a given physical page by mapping it at a page hook point. 4430 * In doing the zero page op, the page we zero is mapped cachable, as with 4431 * StrongARM accesses to non-cached pages are non-burst making writing 4432 * _any_ bulk data very slow. 4433 */ 4434 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4435 void 4436 pmap_zero_page_generic(paddr_t phys) 4437 { 4438 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4439 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4440 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4441 #endif 4442 #ifdef PMAP_CACHE_VIPT 4443 /* Choose the last page color it had, if any */ 4444 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4445 #else 4446 const vsize_t va_offset = 0; 4447 #endif 4448 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4449 4450 #ifdef DEBUG 4451 if (!SLIST_EMPTY(&md->pvh_list)) 4452 panic("pmap_zero_page: page has mappings"); 4453 #endif 4454 4455 KDASSERT((phys & PGOFSET) == 0); 4456 4457 /* 4458 * Hook in the page, zero it, and purge the cache for that 4459 * zeroed page. Invalidate the TLB as needed. 4460 */ 4461 *ptep = L2_S_PROTO | phys | 4462 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4463 PTE_SYNC(ptep); 4464 cpu_tlb_flushD_SE(cdstp + va_offset); 4465 cpu_cpwait(); 4466 bzero_page(cdstp + va_offset); 4467 /* 4468 * Unmap the page. 4469 */ 4470 *ptep = 0; 4471 PTE_SYNC(ptep); 4472 cpu_tlb_flushD_SE(cdstp + va_offset); 4473 #ifdef PMAP_CACHE_VIVT 4474 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4475 #endif 4476 #ifdef PMAP_CACHE_VIPT 4477 /* 4478 * This page is now cache resident so it now has a page color. 4479 * Any contents have been obliterated so clear the EXEC flag. 4480 */ 4481 if (!pmap_is_page_colored_p(md)) { 4482 PMAPCOUNT(vac_color_new); 4483 md->pvh_attrs |= PVF_COLORED; 4484 } 4485 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4486 md->pvh_attrs &= ~PVF_EXEC; 4487 PMAPCOUNT(exec_discarded_zero); 4488 } 4489 md->pvh_attrs |= PVF_DIRTY; 4490 #endif 4491 } 4492 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4493 4494 #if ARM_MMU_XSCALE == 1 4495 void 4496 pmap_zero_page_xscale(paddr_t phys) 4497 { 4498 #ifdef DEBUG 4499 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4500 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4501 4502 if (!SLIST_EMPTY(&md->pvh_list)) 4503 panic("pmap_zero_page: page has mappings"); 4504 #endif 4505 4506 KDASSERT((phys & PGOFSET) == 0); 4507 4508 /* 4509 * Hook in the page, zero it, and purge the cache for that 4510 * zeroed page. Invalidate the TLB as needed. 4511 */ 4512 *cdst_pte = L2_S_PROTO | phys | 4513 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4514 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4515 PTE_SYNC(cdst_pte); 4516 cpu_tlb_flushD_SE(cdstp); 4517 cpu_cpwait(); 4518 bzero_page(cdstp); 4519 xscale_cache_clean_minidata(); 4520 } 4521 #endif /* ARM_MMU_XSCALE == 1 */ 4522 4523 /* pmap_pageidlezero() 4524 * 4525 * The same as above, except that we assume that the page is not 4526 * mapped. This means we never have to flush the cache first. Called 4527 * from the idle loop. 4528 */ 4529 bool 4530 pmap_pageidlezero(paddr_t phys) 4531 { 4532 unsigned int i; 4533 int *ptr; 4534 bool rv = true; 4535 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4536 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4537 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4538 #endif 4539 #ifdef PMAP_CACHE_VIPT 4540 /* Choose the last page color it had, if any */ 4541 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4542 #else 4543 const vsize_t va_offset = 0; 4544 #endif 4545 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4546 4547 4548 #ifdef DEBUG 4549 if (!SLIST_EMPTY(&md->pvh_list)) 4550 panic("pmap_pageidlezero: page has mappings"); 4551 #endif 4552 4553 KDASSERT((phys & PGOFSET) == 0); 4554 4555 /* 4556 * Hook in the page, zero it, and purge the cache for that 4557 * zeroed page. Invalidate the TLB as needed. 4558 */ 4559 *ptep = L2_S_PROTO | phys | 4560 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4561 PTE_SYNC(ptep); 4562 cpu_tlb_flushD_SE(cdstp + va_offset); 4563 cpu_cpwait(); 4564 4565 for (i = 0, ptr = (int *)(cdstp + va_offset); 4566 i < (PAGE_SIZE / sizeof(int)); i++) { 4567 if (sched_curcpu_runnable_p() != 0) { 4568 /* 4569 * A process has become ready. Abort now, 4570 * so we don't keep it waiting while we 4571 * do slow memory access to finish this 4572 * page. 4573 */ 4574 rv = false; 4575 break; 4576 } 4577 *ptr++ = 0; 4578 } 4579 4580 #ifdef PMAP_CACHE_VIVT 4581 if (rv) 4582 /* 4583 * if we aborted we'll rezero this page again later so don't 4584 * purge it unless we finished it 4585 */ 4586 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4587 #elif defined(PMAP_CACHE_VIPT) 4588 /* 4589 * This page is now cache resident so it now has a page color. 4590 * Any contents have been obliterated so clear the EXEC flag. 4591 */ 4592 if (!pmap_is_page_colored_p(md)) { 4593 PMAPCOUNT(vac_color_new); 4594 md->pvh_attrs |= PVF_COLORED; 4595 } 4596 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4597 md->pvh_attrs &= ~PVF_EXEC; 4598 PMAPCOUNT(exec_discarded_zero); 4599 } 4600 #endif 4601 /* 4602 * Unmap the page. 4603 */ 4604 *ptep = 0; 4605 PTE_SYNC(ptep); 4606 cpu_tlb_flushD_SE(cdstp + va_offset); 4607 4608 return (rv); 4609 } 4610 4611 /* 4612 * pmap_copy_page() 4613 * 4614 * Copy one physical page into another, by mapping the pages into 4615 * hook points. The same comment regarding cachability as in 4616 * pmap_zero_page also applies here. 4617 */ 4618 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4619 void 4620 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4621 { 4622 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4623 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4624 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4625 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4626 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4627 #endif 4628 #ifdef PMAP_CACHE_VIPT 4629 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4630 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4631 #else 4632 const vsize_t src_va_offset = 0; 4633 const vsize_t dst_va_offset = 0; 4634 #endif 4635 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4636 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4637 4638 #ifdef DEBUG 4639 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4640 panic("pmap_copy_page: dst page has mappings"); 4641 #endif 4642 4643 #ifdef PMAP_CACHE_VIPT 4644 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4645 #endif 4646 KDASSERT((src & PGOFSET) == 0); 4647 KDASSERT((dst & PGOFSET) == 0); 4648 4649 /* 4650 * Clean the source page. Hold the source page's lock for 4651 * the duration of the copy so that no other mappings can 4652 * be created while we have a potentially aliased mapping. 4653 */ 4654 simple_lock(&src_md->pvh_slock); 4655 #ifdef PMAP_CACHE_VIVT 4656 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4657 #endif 4658 4659 /* 4660 * Map the pages into the page hook points, copy them, and purge 4661 * the cache for the appropriate page. Invalidate the TLB 4662 * as required. 4663 */ 4664 *src_ptep = L2_S_PROTO 4665 | src 4666 #ifdef PMAP_CACHE_VIPT 4667 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4668 #endif 4669 #ifdef PMAP_CACHE_VIVT 4670 | pte_l2_s_cache_mode 4671 #endif 4672 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4673 *dst_ptep = L2_S_PROTO | dst | 4674 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4675 PTE_SYNC(src_ptep); 4676 PTE_SYNC(dst_ptep); 4677 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4678 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4679 cpu_cpwait(); 4680 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4681 #ifdef PMAP_CACHE_VIVT 4682 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4683 #endif 4684 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4685 #ifdef PMAP_CACHE_VIVT 4686 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4687 #endif 4688 /* 4689 * Unmap the pages. 4690 */ 4691 *src_ptep = 0; 4692 *dst_ptep = 0; 4693 PTE_SYNC(src_ptep); 4694 PTE_SYNC(dst_ptep); 4695 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4696 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4697 #ifdef PMAP_CACHE_VIPT 4698 /* 4699 * Now that the destination page is in the cache, mark it as colored. 4700 * If this was an exec page, discard it. 4701 */ 4702 if (!pmap_is_page_colored_p(dst_md)) { 4703 PMAPCOUNT(vac_color_new); 4704 dst_md->pvh_attrs |= PVF_COLORED; 4705 } 4706 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4707 dst_md->pvh_attrs &= ~PVF_EXEC; 4708 PMAPCOUNT(exec_discarded_copy); 4709 } 4710 dst_md->pvh_attrs |= PVF_DIRTY; 4711 #endif 4712 } 4713 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4714 4715 #if ARM_MMU_XSCALE == 1 4716 void 4717 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4718 { 4719 struct vm_page_md *src_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(src)); 4720 #ifdef DEBUG 4721 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4722 4723 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4724 panic("pmap_copy_page: dst page has mappings"); 4725 #endif 4726 4727 KDASSERT((src & PGOFSET) == 0); 4728 KDASSERT((dst & PGOFSET) == 0); 4729 4730 /* 4731 * Clean the source page. Hold the source page's lock for 4732 * the duration of the copy so that no other mappings can 4733 * be created while we have a potentially aliased mapping. 4734 */ 4735 simple_lock(&src_md->pvh_slock); 4736 #ifdef PMAP_CACHE_VIVT 4737 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4738 #endif 4739 4740 /* 4741 * Map the pages into the page hook points, copy them, and purge 4742 * the cache for the appropriate page. Invalidate the TLB 4743 * as required. 4744 */ 4745 *csrc_pte = L2_S_PROTO | src | 4746 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4747 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4748 PTE_SYNC(csrc_pte); 4749 *cdst_pte = L2_S_PROTO | dst | 4750 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4751 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4752 PTE_SYNC(cdst_pte); 4753 cpu_tlb_flushD_SE(csrcp); 4754 cpu_tlb_flushD_SE(cdstp); 4755 cpu_cpwait(); 4756 bcopy_page(csrcp, cdstp); 4757 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4758 xscale_cache_clean_minidata(); 4759 } 4760 #endif /* ARM_MMU_XSCALE == 1 */ 4761 4762 /* 4763 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4764 * 4765 * Return the start and end addresses of the kernel's virtual space. 4766 * These values are setup in pmap_bootstrap and are updated as pages 4767 * are allocated. 4768 */ 4769 void 4770 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4771 { 4772 *start = virtual_avail; 4773 *end = virtual_end; 4774 } 4775 4776 /* 4777 * Helper function for pmap_grow_l2_bucket() 4778 */ 4779 static inline int 4780 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4781 { 4782 struct l2_bucket *l2b; 4783 pt_entry_t *ptep; 4784 paddr_t pa; 4785 4786 if (uvm.page_init_done == false) { 4787 #ifdef PMAP_STEAL_MEMORY 4788 pv_addr_t pv; 4789 pmap_boot_pagealloc(PAGE_SIZE, 4790 #ifdef PMAP_CACHE_VIPT 4791 arm_cache_prefer_mask, 4792 va & arm_cache_prefer_mask, 4793 #else 4794 0, 0, 4795 #endif 4796 &pv); 4797 pa = pv.pv_pa; 4798 #else 4799 if (uvm_page_physget(&pa) == false) 4800 return (1); 4801 #endif /* PMAP_STEAL_MEMORY */ 4802 } else { 4803 struct vm_page *pg; 4804 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4805 if (pg == NULL) 4806 return (1); 4807 pa = VM_PAGE_TO_PHYS(pg); 4808 #ifdef PMAP_CACHE_VIPT 4809 #ifdef DIAGNOSTIC 4810 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4811 #endif 4812 /* 4813 * This new page must not have any mappings. Enter it via 4814 * pmap_kenter_pa and let that routine do the hard work. 4815 */ 4816 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4817 pmap_kenter_pa(va, pa, 4818 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4819 #endif 4820 } 4821 4822 if (pap) 4823 *pap = pa; 4824 4825 PMAPCOUNT(pt_mappings); 4826 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4827 KDASSERT(l2b != NULL); 4828 4829 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4830 *ptep = L2_S_PROTO | pa | cache_mode | 4831 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4832 PTE_SYNC(ptep); 4833 memset((void *)va, 0, PAGE_SIZE); 4834 return (0); 4835 } 4836 4837 /* 4838 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4839 * used by pmap_growkernel(). 4840 */ 4841 static inline struct l2_bucket * 4842 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4843 { 4844 struct l2_dtable *l2; 4845 struct l2_bucket *l2b; 4846 u_short l1idx; 4847 vaddr_t nva; 4848 4849 l1idx = L1_IDX(va); 4850 4851 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4852 /* 4853 * No mapping at this address, as there is 4854 * no entry in the L1 table. 4855 * Need to allocate a new l2_dtable. 4856 */ 4857 nva = pmap_kernel_l2dtable_kva; 4858 if ((nva & PGOFSET) == 0) { 4859 /* 4860 * Need to allocate a backing page 4861 */ 4862 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4863 return (NULL); 4864 } 4865 4866 l2 = (struct l2_dtable *)nva; 4867 nva += sizeof(struct l2_dtable); 4868 4869 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4870 /* 4871 * The new l2_dtable straddles a page boundary. 4872 * Map in another page to cover it. 4873 */ 4874 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4875 return (NULL); 4876 } 4877 4878 pmap_kernel_l2dtable_kva = nva; 4879 4880 /* 4881 * Link it into the parent pmap 4882 */ 4883 pm->pm_l2[L2_IDX(l1idx)] = l2; 4884 } 4885 4886 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4887 4888 /* 4889 * Fetch pointer to the L2 page table associated with the address. 4890 */ 4891 if (l2b->l2b_kva == NULL) { 4892 pt_entry_t *ptep; 4893 4894 /* 4895 * No L2 page table has been allocated. Chances are, this 4896 * is because we just allocated the l2_dtable, above. 4897 */ 4898 nva = pmap_kernel_l2ptp_kva; 4899 ptep = (pt_entry_t *)nva; 4900 if ((nva & PGOFSET) == 0) { 4901 /* 4902 * Need to allocate a backing page 4903 */ 4904 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4905 &pmap_kernel_l2ptp_phys)) 4906 return (NULL); 4907 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4908 } 4909 4910 l2->l2_occupancy++; 4911 l2b->l2b_kva = ptep; 4912 l2b->l2b_l1idx = l1idx; 4913 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4914 4915 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4916 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4917 } 4918 4919 return (l2b); 4920 } 4921 4922 vaddr_t 4923 pmap_growkernel(vaddr_t maxkvaddr) 4924 { 4925 pmap_t kpm = pmap_kernel(); 4926 struct l1_ttable *l1; 4927 struct l2_bucket *l2b; 4928 pd_entry_t *pl1pd; 4929 int s; 4930 4931 if (maxkvaddr <= pmap_curmaxkvaddr) 4932 goto out; /* we are OK */ 4933 4934 NPDEBUG(PDB_GROWKERN, 4935 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4936 pmap_curmaxkvaddr, maxkvaddr)); 4937 4938 KDASSERT(maxkvaddr <= virtual_end); 4939 4940 /* 4941 * whoops! we need to add kernel PTPs 4942 */ 4943 4944 s = splhigh(); /* to be safe */ 4945 mutex_enter(&kpm->pm_lock); 4946 4947 /* Map 1MB at a time */ 4948 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4949 4950 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4951 KDASSERT(l2b != NULL); 4952 4953 /* Distribute new L1 entry to all other L1s */ 4954 SLIST_FOREACH(l1, &l1_list, l1_link) { 4955 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4956 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4957 L1_C_PROTO; 4958 PTE_SYNC(pl1pd); 4959 } 4960 } 4961 4962 /* 4963 * flush out the cache, expensive but growkernel will happen so 4964 * rarely 4965 */ 4966 cpu_dcache_wbinv_all(); 4967 cpu_tlb_flushD(); 4968 cpu_cpwait(); 4969 4970 mutex_exit(&kpm->pm_lock); 4971 splx(s); 4972 4973 out: 4974 return (pmap_curmaxkvaddr); 4975 } 4976 4977 /************************ Utility routines ****************************/ 4978 4979 /* 4980 * vector_page_setprot: 4981 * 4982 * Manipulate the protection of the vector page. 4983 */ 4984 void 4985 vector_page_setprot(int prot) 4986 { 4987 struct l2_bucket *l2b; 4988 pt_entry_t *ptep; 4989 4990 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4991 KDASSERT(l2b != NULL); 4992 4993 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4994 4995 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4996 PTE_SYNC(ptep); 4997 cpu_tlb_flushD_SE(vector_page); 4998 cpu_cpwait(); 4999 } 5000 5001 /* 5002 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5003 * Returns true if the mapping exists, else false. 5004 * 5005 * NOTE: This function is only used by a couple of arm-specific modules. 5006 * It is not safe to take any pmap locks here, since we could be right 5007 * in the middle of debugging the pmap anyway... 5008 * 5009 * It is possible for this routine to return false even though a valid 5010 * mapping does exist. This is because we don't lock, so the metadata 5011 * state may be inconsistent. 5012 * 5013 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5014 * a "section" mapping. 5015 */ 5016 bool 5017 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5018 { 5019 struct l2_dtable *l2; 5020 pd_entry_t *pl1pd, l1pd; 5021 pt_entry_t *ptep; 5022 u_short l1idx; 5023 5024 if (pm->pm_l1 == NULL) 5025 return false; 5026 5027 l1idx = L1_IDX(va); 5028 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5029 l1pd = *pl1pd; 5030 5031 if (l1pte_section_p(l1pd)) { 5032 *ptp = NULL; 5033 return true; 5034 } 5035 5036 if (pm->pm_l2 == NULL) 5037 return false; 5038 5039 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5040 5041 if (l2 == NULL || 5042 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5043 return false; 5044 } 5045 5046 *ptp = &ptep[l2pte_index(va)]; 5047 return true; 5048 } 5049 5050 bool 5051 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5052 { 5053 u_short l1idx; 5054 5055 if (pm->pm_l1 == NULL) 5056 return false; 5057 5058 l1idx = L1_IDX(va); 5059 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5060 5061 return true; 5062 } 5063 5064 /************************ Bootstrapping routines ****************************/ 5065 5066 static void 5067 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5068 { 5069 int i; 5070 5071 l1->l1_kva = l1pt; 5072 l1->l1_domain_use_count = 0; 5073 l1->l1_domain_first = 0; 5074 5075 for (i = 0; i < PMAP_DOMAINS; i++) 5076 l1->l1_domain_free[i] = i + 1; 5077 5078 /* 5079 * Copy the kernel's L1 entries to each new L1. 5080 */ 5081 if (pmap_initialized) 5082 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5083 5084 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5085 &l1->l1_physaddr) == false) 5086 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5087 5088 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5089 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5090 } 5091 5092 /* 5093 * pmap_bootstrap() is called from the board-specific initarm() routine 5094 * once the kernel L1/L2 descriptors tables have been set up. 5095 * 5096 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5097 * spread over a number of disparate files/functions. 5098 * 5099 * We are passed the following parameters 5100 * - kernel_l1pt 5101 * This is a pointer to the base of the kernel's L1 translation table. 5102 * - vstart 5103 * 1MB-aligned start of managed kernel virtual memory. 5104 * - vend 5105 * 1MB-aligned end of managed kernel virtual memory. 5106 * 5107 * We use the first parameter to build the metadata (struct l1_ttable and 5108 * struct l2_dtable) necessary to track kernel mappings. 5109 */ 5110 #define PMAP_STATIC_L2_SIZE 16 5111 void 5112 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5113 { 5114 static struct l1_ttable static_l1; 5115 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5116 struct l1_ttable *l1 = &static_l1; 5117 struct l2_dtable *l2; 5118 struct l2_bucket *l2b; 5119 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5120 pmap_t pm = pmap_kernel(); 5121 pd_entry_t pde; 5122 pt_entry_t *ptep; 5123 paddr_t pa; 5124 vaddr_t va; 5125 vsize_t size; 5126 int nptes, l1idx, l2idx, l2next = 0; 5127 5128 /* 5129 * Initialise the kernel pmap object 5130 */ 5131 pm->pm_l1 = l1; 5132 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5133 pm->pm_activated = true; 5134 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5135 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5136 5137 /* 5138 * Scan the L1 translation table created by initarm() and create 5139 * the required metadata for all valid mappings found in it. 5140 */ 5141 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5142 pde = l1pt[l1idx]; 5143 5144 /* 5145 * We're only interested in Coarse mappings. 5146 * pmap_extract() can deal with section mappings without 5147 * recourse to checking L2 metadata. 5148 */ 5149 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5150 continue; 5151 5152 /* 5153 * Lookup the KVA of this L2 descriptor table 5154 */ 5155 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5156 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5157 if (ptep == NULL) { 5158 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5159 (u_int)l1idx << L1_S_SHIFT, pa); 5160 } 5161 5162 /* 5163 * Fetch the associated L2 metadata structure. 5164 * Allocate a new one if necessary. 5165 */ 5166 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5167 if (l2next == PMAP_STATIC_L2_SIZE) 5168 panic("pmap_bootstrap: out of static L2s"); 5169 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5170 } 5171 5172 /* 5173 * One more L1 slot tracked... 5174 */ 5175 l2->l2_occupancy++; 5176 5177 /* 5178 * Fill in the details of the L2 descriptor in the 5179 * appropriate bucket. 5180 */ 5181 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5182 l2b->l2b_kva = ptep; 5183 l2b->l2b_phys = pa; 5184 l2b->l2b_l1idx = l1idx; 5185 5186 /* 5187 * Establish an initial occupancy count for this descriptor 5188 */ 5189 for (l2idx = 0; 5190 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5191 l2idx++) { 5192 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5193 l2b->l2b_occupancy++; 5194 } 5195 } 5196 5197 /* 5198 * Make sure the descriptor itself has the correct cache mode. 5199 * If not, fix it, but whine about the problem. Port-meisters 5200 * should consider this a clue to fix up their initarm() 5201 * function. :) 5202 */ 5203 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5204 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5205 "L2 pte @ %p\n", ptep); 5206 } 5207 } 5208 5209 /* 5210 * Ensure the primary (kernel) L1 has the correct cache mode for 5211 * a page table. Bitch if it is not correctly set. 5212 */ 5213 for (va = (vaddr_t)l1pt; 5214 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5215 if (pmap_set_pt_cache_mode(l1pt, va)) 5216 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5217 "primary L1 @ 0x%lx\n", va); 5218 } 5219 5220 cpu_dcache_wbinv_all(); 5221 cpu_tlb_flushID(); 5222 cpu_cpwait(); 5223 5224 /* 5225 * now we allocate the "special" VAs which are used for tmp mappings 5226 * by the pmap (and other modules). we allocate the VAs by advancing 5227 * virtual_avail (note that there are no pages mapped at these VAs). 5228 * 5229 * Managed KVM space start from wherever initarm() tells us. 5230 */ 5231 virtual_avail = vstart; 5232 virtual_end = vend; 5233 5234 #ifdef PMAP_CACHE_VIPT 5235 /* 5236 * If we have a VIPT cache, we need one page/pte per possible alias 5237 * page so we won't violate cache aliasing rules. 5238 */ 5239 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5240 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5241 #else 5242 nptes = 1; 5243 #endif 5244 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5245 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5246 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5247 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5248 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5249 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5250 (void *)&msgbufaddr, NULL); 5251 5252 /* 5253 * Allocate a range of kernel virtual address space to be used 5254 * for L2 descriptor tables and metadata allocation in 5255 * pmap_growkernel(). 5256 */ 5257 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5258 pmap_alloc_specials(&virtual_avail, 5259 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5260 &pmap_kernel_l2ptp_kva, NULL); 5261 5262 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5263 pmap_alloc_specials(&virtual_avail, 5264 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5265 &pmap_kernel_l2dtable_kva, NULL); 5266 5267 /* 5268 * init the static-global locks and global pmap list. 5269 */ 5270 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5271 5272 /* 5273 * We can now initialise the first L1's metadata. 5274 */ 5275 SLIST_INIT(&l1_list); 5276 TAILQ_INIT(&l1_lru_list); 5277 simple_lock_init(&l1_lru_lock); 5278 pmap_init_l1(l1, l1pt); 5279 5280 /* Set up vector page L1 details, if necessary */ 5281 if (vector_page < KERNEL_BASE) { 5282 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5283 l2b = pmap_get_l2_bucket(pm, vector_page); 5284 KDASSERT(l2b != NULL); 5285 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5286 L1_C_DOM(pm->pm_domain); 5287 } else 5288 pm->pm_pl1vec = NULL; 5289 5290 /* 5291 * Initialize the pmap cache 5292 */ 5293 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5294 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5295 LIST_INIT(&pmap_pmaps); 5296 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5297 5298 /* 5299 * Initialize the pv pool. 5300 */ 5301 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5302 &pmap_bootstrap_pv_allocator, IPL_NONE); 5303 5304 /* 5305 * Initialize the L2 dtable pool and cache. 5306 */ 5307 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5308 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5309 5310 /* 5311 * Initialise the L2 descriptor table pool and cache 5312 */ 5313 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5314 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5315 pmap_l2ptp_ctor, NULL, NULL); 5316 5317 cpu_dcache_wbinv_all(); 5318 } 5319 5320 static int 5321 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5322 { 5323 pd_entry_t *pdep, pde; 5324 pt_entry_t *ptep, pte; 5325 vaddr_t pa; 5326 int rv = 0; 5327 5328 /* 5329 * Make sure the descriptor itself has the correct cache mode 5330 */ 5331 pdep = &kl1[L1_IDX(va)]; 5332 pde = *pdep; 5333 5334 if (l1pte_section_p(pde)) { 5335 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5336 *pdep = (pde & ~L1_S_CACHE_MASK) | 5337 pte_l1_s_cache_mode_pt; 5338 PTE_SYNC(pdep); 5339 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5340 rv = 1; 5341 } 5342 } else { 5343 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5344 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5345 if (ptep == NULL) 5346 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5347 5348 ptep = &ptep[l2pte_index(va)]; 5349 pte = *ptep; 5350 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5351 *ptep = (pte & ~L2_S_CACHE_MASK) | 5352 pte_l2_s_cache_mode_pt; 5353 PTE_SYNC(ptep); 5354 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5355 rv = 1; 5356 } 5357 } 5358 5359 return (rv); 5360 } 5361 5362 static void 5363 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5364 { 5365 vaddr_t va = *availp; 5366 struct l2_bucket *l2b; 5367 5368 if (ptep) { 5369 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5370 if (l2b == NULL) 5371 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5372 5373 if (ptep) 5374 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5375 } 5376 5377 *vap = va; 5378 *availp = va + (PAGE_SIZE * pages); 5379 } 5380 5381 void 5382 pmap_init(void) 5383 { 5384 5385 /* 5386 * Set the available memory vars - These do not map to real memory 5387 * addresses and cannot as the physical memory is fragmented. 5388 * They are used by ps for %mem calculations. 5389 * One could argue whether this should be the entire memory or just 5390 * the memory that is useable in a user process. 5391 */ 5392 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5393 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5394 5395 /* 5396 * Now we need to free enough pv_entry structures to allow us to get 5397 * the kmem_map/kmem_object allocated and inited (done after this 5398 * function is finished). to do this we allocate one bootstrap page out 5399 * of kernel_map and use it to provide an initial pool of pv_entry 5400 * structures. we never free this page. 5401 */ 5402 pool_setlowat(&pmap_pv_pool, 5403 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5404 5405 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5406 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5407 UVM_KMF_WIRED|UVM_KMF_ZERO); 5408 5409 pmap_initialized = true; 5410 } 5411 5412 static vaddr_t last_bootstrap_page = 0; 5413 static void *free_bootstrap_pages = NULL; 5414 5415 static void * 5416 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5417 { 5418 extern void *pool_page_alloc(struct pool *, int); 5419 vaddr_t new_page; 5420 void *rv; 5421 5422 if (pmap_initialized) 5423 return (pool_page_alloc(pp, flags)); 5424 5425 if (free_bootstrap_pages) { 5426 rv = free_bootstrap_pages; 5427 free_bootstrap_pages = *((void **)rv); 5428 return (rv); 5429 } 5430 5431 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5432 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5433 5434 KASSERT(new_page > last_bootstrap_page); 5435 last_bootstrap_page = new_page; 5436 return ((void *)new_page); 5437 } 5438 5439 static void 5440 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5441 { 5442 extern void pool_page_free(struct pool *, void *); 5443 5444 if ((vaddr_t)v <= last_bootstrap_page) { 5445 *((void **)v) = free_bootstrap_pages; 5446 free_bootstrap_pages = v; 5447 return; 5448 } 5449 5450 if (pmap_initialized) { 5451 pool_page_free(pp, v); 5452 return; 5453 } 5454 } 5455 5456 /* 5457 * pmap_postinit() 5458 * 5459 * This routine is called after the vm and kmem subsystems have been 5460 * initialised. This allows the pmap code to perform any initialisation 5461 * that can only be done one the memory allocation is in place. 5462 */ 5463 void 5464 pmap_postinit(void) 5465 { 5466 extern paddr_t physical_start, physical_end; 5467 struct l2_bucket *l2b; 5468 struct l1_ttable *l1; 5469 struct pglist plist; 5470 struct vm_page *m; 5471 pd_entry_t *pl1pt; 5472 pt_entry_t *ptep, pte; 5473 vaddr_t va, eva; 5474 u_int loop, needed; 5475 int error; 5476 5477 pool_cache_setlowat(&pmap_l2ptp_cache, 5478 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5479 pool_cache_setlowat(&pmap_l2dtable_cache, 5480 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5481 5482 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5483 needed -= 1; 5484 5485 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5486 5487 for (loop = 0; loop < needed; loop++, l1++) { 5488 /* Allocate a L1 page table */ 5489 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5490 if (va == 0) 5491 panic("Cannot allocate L1 KVM"); 5492 5493 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5494 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5495 if (error) 5496 panic("Cannot allocate L1 physical pages"); 5497 5498 m = TAILQ_FIRST(&plist); 5499 eva = va + L1_TABLE_SIZE; 5500 pl1pt = (pd_entry_t *)va; 5501 5502 while (m && va < eva) { 5503 paddr_t pa = VM_PAGE_TO_PHYS(m); 5504 5505 pmap_kenter_pa(va, pa, 5506 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5507 5508 /* 5509 * Make sure the L1 descriptor table is mapped 5510 * with the cache-mode set to write-through. 5511 */ 5512 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5513 KDASSERT(l2b != NULL); 5514 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5515 pte = *ptep; 5516 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5517 *ptep = pte; 5518 PTE_SYNC(ptep); 5519 cpu_tlb_flushD_SE(va); 5520 5521 va += PAGE_SIZE; 5522 m = TAILQ_NEXT(m, pageq.queue); 5523 } 5524 5525 #ifdef DIAGNOSTIC 5526 if (m) 5527 panic("pmap_alloc_l1pt: pglist not empty"); 5528 #endif /* DIAGNOSTIC */ 5529 5530 pmap_init_l1(l1, pl1pt); 5531 } 5532 5533 #ifdef DEBUG 5534 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5535 needed); 5536 #endif 5537 } 5538 5539 /* 5540 * Note that the following routines are used by board-specific initialisation 5541 * code to configure the initial kernel page tables. 5542 * 5543 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5544 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5545 * behaviour of the old pmap, and provides an easy migration path for 5546 * initial bring-up of the new pmap on existing ports. Fortunately, 5547 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5548 * will be deprecated. 5549 * 5550 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5551 * tables. 5552 */ 5553 5554 /* 5555 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5556 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5557 * find them as necessary. 5558 * 5559 * Note that the data on this list MUST remain valid after initarm() returns, 5560 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5561 */ 5562 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5563 5564 static vaddr_t 5565 kernel_pt_lookup(paddr_t pa) 5566 { 5567 pv_addr_t *pv; 5568 5569 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5570 #ifndef ARM32_NEW_VM_LAYOUT 5571 if (pv->pv_pa == (pa & ~PGOFSET)) 5572 return (pv->pv_va | (pa & PGOFSET)); 5573 #else 5574 if (pv->pv_pa == pa) 5575 return (pv->pv_va); 5576 #endif 5577 } 5578 return (0); 5579 } 5580 5581 /* 5582 * pmap_map_section: 5583 * 5584 * Create a single section mapping. 5585 */ 5586 void 5587 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5588 { 5589 pd_entry_t *pde = (pd_entry_t *) l1pt; 5590 pd_entry_t fl; 5591 5592 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5593 5594 switch (cache) { 5595 case PTE_NOCACHE: 5596 default: 5597 fl = 0; 5598 break; 5599 5600 case PTE_CACHE: 5601 fl = pte_l1_s_cache_mode; 5602 break; 5603 5604 case PTE_PAGETABLE: 5605 fl = pte_l1_s_cache_mode_pt; 5606 break; 5607 } 5608 5609 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5610 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5611 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5612 } 5613 5614 /* 5615 * pmap_map_entry: 5616 * 5617 * Create a single page mapping. 5618 */ 5619 void 5620 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5621 { 5622 pd_entry_t *pde = (pd_entry_t *) l1pt; 5623 pt_entry_t fl; 5624 pt_entry_t *pte; 5625 5626 KASSERT(((va | pa) & PGOFSET) == 0); 5627 5628 switch (cache) { 5629 case PTE_NOCACHE: 5630 default: 5631 fl = 0; 5632 break; 5633 5634 case PTE_CACHE: 5635 fl = pte_l2_s_cache_mode; 5636 break; 5637 5638 case PTE_PAGETABLE: 5639 fl = pte_l2_s_cache_mode_pt; 5640 break; 5641 } 5642 5643 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5644 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5645 5646 #ifndef ARM32_NEW_VM_LAYOUT 5647 pte = (pt_entry_t *) 5648 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5649 #else 5650 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5651 #endif 5652 if (pte == NULL) 5653 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5654 5655 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5656 #ifndef ARM32_NEW_VM_LAYOUT 5657 pte += (va >> PGSHIFT) & 0x3ff; 5658 #else 5659 pte += l2pte_index(va); 5660 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5661 #endif 5662 *pte = fl; 5663 PTE_SYNC(pte); 5664 } 5665 5666 /* 5667 * pmap_link_l2pt: 5668 * 5669 * Link the L2 page table specified by "l2pv" into the L1 5670 * page table at the slot for "va". 5671 */ 5672 void 5673 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5674 { 5675 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5676 u_int slot = va >> L1_S_SHIFT; 5677 5678 #ifndef ARM32_NEW_VM_LAYOUT 5679 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5680 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5681 #endif 5682 5683 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5684 5685 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5686 #ifdef ARM32_NEW_VM_LAYOUT 5687 PTE_SYNC(&pde[slot]); 5688 #else 5689 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5690 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5691 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5692 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5693 #endif 5694 5695 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5696 } 5697 5698 /* 5699 * pmap_map_chunk: 5700 * 5701 * Map a chunk of memory using the most efficient mappings 5702 * possible (section, large page, small page) into the 5703 * provided L1 and L2 tables at the specified virtual address. 5704 */ 5705 vsize_t 5706 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5707 int prot, int cache) 5708 { 5709 pd_entry_t *pde = (pd_entry_t *) l1pt; 5710 pt_entry_t *pte, f1, f2s, f2l; 5711 vsize_t resid; 5712 int i; 5713 5714 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5715 5716 if (l1pt == 0) 5717 panic("pmap_map_chunk: no L1 table provided"); 5718 5719 #ifdef VERBOSE_INIT_ARM 5720 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5721 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5722 #endif 5723 5724 switch (cache) { 5725 case PTE_NOCACHE: 5726 default: 5727 f1 = 0; 5728 f2l = 0; 5729 f2s = 0; 5730 break; 5731 5732 case PTE_CACHE: 5733 f1 = pte_l1_s_cache_mode; 5734 f2l = pte_l2_l_cache_mode; 5735 f2s = pte_l2_s_cache_mode; 5736 break; 5737 5738 case PTE_PAGETABLE: 5739 f1 = pte_l1_s_cache_mode_pt; 5740 f2l = pte_l2_l_cache_mode_pt; 5741 f2s = pte_l2_s_cache_mode_pt; 5742 break; 5743 } 5744 5745 size = resid; 5746 5747 while (resid > 0) { 5748 /* See if we can use a section mapping. */ 5749 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5750 #ifdef VERBOSE_INIT_ARM 5751 printf("S"); 5752 #endif 5753 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5754 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5755 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5756 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5757 va += L1_S_SIZE; 5758 pa += L1_S_SIZE; 5759 resid -= L1_S_SIZE; 5760 continue; 5761 } 5762 5763 /* 5764 * Ok, we're going to use an L2 table. Make sure 5765 * one is actually in the corresponding L1 slot 5766 * for the current VA. 5767 */ 5768 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5769 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5770 5771 #ifndef ARM32_NEW_VM_LAYOUT 5772 pte = (pt_entry_t *) 5773 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5774 #else 5775 pte = (pt_entry_t *) kernel_pt_lookup( 5776 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5777 #endif 5778 if (pte == NULL) 5779 panic("pmap_map_chunk: can't find L2 table for VA" 5780 "0x%08lx", va); 5781 5782 /* See if we can use a L2 large page mapping. */ 5783 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5784 #ifdef VERBOSE_INIT_ARM 5785 printf("L"); 5786 #endif 5787 for (i = 0; i < 16; i++) { 5788 #ifndef ARM32_NEW_VM_LAYOUT 5789 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5790 L2_L_PROTO | pa | 5791 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5792 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5793 #else 5794 pte[l2pte_index(va) + i] = 5795 L2_L_PROTO | pa | 5796 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5797 PTE_SYNC(&pte[l2pte_index(va) + i]); 5798 #endif 5799 } 5800 va += L2_L_SIZE; 5801 pa += L2_L_SIZE; 5802 resid -= L2_L_SIZE; 5803 continue; 5804 } 5805 5806 /* Use a small page mapping. */ 5807 #ifdef VERBOSE_INIT_ARM 5808 printf("P"); 5809 #endif 5810 #ifndef ARM32_NEW_VM_LAYOUT 5811 pte[(va >> PGSHIFT) & 0x3ff] = 5812 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5813 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5814 #else 5815 pte[l2pte_index(va)] = 5816 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5817 PTE_SYNC(&pte[l2pte_index(va)]); 5818 #endif 5819 va += PAGE_SIZE; 5820 pa += PAGE_SIZE; 5821 resid -= PAGE_SIZE; 5822 } 5823 #ifdef VERBOSE_INIT_ARM 5824 printf("\n"); 5825 #endif 5826 return (size); 5827 } 5828 5829 /********************** Static device map routines ***************************/ 5830 5831 static const struct pmap_devmap *pmap_devmap_table; 5832 5833 /* 5834 * Register the devmap table. This is provided in case early console 5835 * initialization needs to register mappings created by bootstrap code 5836 * before pmap_devmap_bootstrap() is called. 5837 */ 5838 void 5839 pmap_devmap_register(const struct pmap_devmap *table) 5840 { 5841 5842 pmap_devmap_table = table; 5843 } 5844 5845 /* 5846 * Map all of the static regions in the devmap table, and remember 5847 * the devmap table so other parts of the kernel can look up entries 5848 * later. 5849 */ 5850 void 5851 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5852 { 5853 int i; 5854 5855 pmap_devmap_table = table; 5856 5857 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5858 #ifdef VERBOSE_INIT_ARM 5859 printf("devmap: %08lx -> %08lx @ %08lx\n", 5860 pmap_devmap_table[i].pd_pa, 5861 pmap_devmap_table[i].pd_pa + 5862 pmap_devmap_table[i].pd_size - 1, 5863 pmap_devmap_table[i].pd_va); 5864 #endif 5865 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5866 pmap_devmap_table[i].pd_pa, 5867 pmap_devmap_table[i].pd_size, 5868 pmap_devmap_table[i].pd_prot, 5869 pmap_devmap_table[i].pd_cache); 5870 } 5871 } 5872 5873 const struct pmap_devmap * 5874 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5875 { 5876 uint64_t endpa; 5877 int i; 5878 5879 if (pmap_devmap_table == NULL) 5880 return (NULL); 5881 5882 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5883 5884 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5885 if (pa >= pmap_devmap_table[i].pd_pa && 5886 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5887 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5888 return (&pmap_devmap_table[i]); 5889 } 5890 5891 return (NULL); 5892 } 5893 5894 const struct pmap_devmap * 5895 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5896 { 5897 int i; 5898 5899 if (pmap_devmap_table == NULL) 5900 return (NULL); 5901 5902 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5903 if (va >= pmap_devmap_table[i].pd_va && 5904 va + size - 1 <= pmap_devmap_table[i].pd_va + 5905 pmap_devmap_table[i].pd_size - 1) 5906 return (&pmap_devmap_table[i]); 5907 } 5908 5909 return (NULL); 5910 } 5911 5912 /********************** PTE initialization routines **************************/ 5913 5914 /* 5915 * These routines are called when the CPU type is identified to set up 5916 * the PTE prototypes, cache modes, etc. 5917 * 5918 * The variables are always here, just in case modules need to reference 5919 * them (though, they shouldn't). 5920 */ 5921 5922 pt_entry_t pte_l1_s_cache_mode; 5923 pt_entry_t pte_l1_s_cache_mode_pt; 5924 pt_entry_t pte_l1_s_cache_mask; 5925 5926 pt_entry_t pte_l2_l_cache_mode; 5927 pt_entry_t pte_l2_l_cache_mode_pt; 5928 pt_entry_t pte_l2_l_cache_mask; 5929 5930 pt_entry_t pte_l2_s_cache_mode; 5931 pt_entry_t pte_l2_s_cache_mode_pt; 5932 pt_entry_t pte_l2_s_cache_mask; 5933 5934 pt_entry_t pte_l1_s_prot_u; 5935 pt_entry_t pte_l1_s_prot_w; 5936 pt_entry_t pte_l1_s_prot_ro; 5937 pt_entry_t pte_l1_s_prot_mask; 5938 5939 pt_entry_t pte_l2_s_prot_u; 5940 pt_entry_t pte_l2_s_prot_w; 5941 pt_entry_t pte_l2_s_prot_ro; 5942 pt_entry_t pte_l2_s_prot_mask; 5943 5944 pt_entry_t pte_l2_l_prot_u; 5945 pt_entry_t pte_l2_l_prot_w; 5946 pt_entry_t pte_l2_l_prot_ro; 5947 pt_entry_t pte_l2_l_prot_mask; 5948 5949 pt_entry_t pte_l1_s_proto; 5950 pt_entry_t pte_l1_c_proto; 5951 pt_entry_t pte_l2_s_proto; 5952 5953 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5954 void (*pmap_zero_page_func)(paddr_t); 5955 5956 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5957 void 5958 pmap_pte_init_generic(void) 5959 { 5960 5961 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5962 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5963 5964 pte_l2_l_cache_mode = L2_B|L2_C; 5965 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5966 5967 pte_l2_s_cache_mode = L2_B|L2_C; 5968 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5969 5970 /* 5971 * If we have a write-through cache, set B and C. If 5972 * we have a write-back cache, then we assume setting 5973 * only C will make those pages write-through. 5974 */ 5975 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5976 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5977 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5978 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5979 } else { 5980 #if ARM_MMU_V6 > 1 5981 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5982 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5983 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5984 #else 5985 pte_l1_s_cache_mode_pt = L1_S_C; 5986 pte_l2_l_cache_mode_pt = L2_C; 5987 pte_l2_s_cache_mode_pt = L2_C; 5988 #endif 5989 } 5990 5991 pte_l1_s_prot_u = L1_S_PROT_U_generic; 5992 pte_l1_s_prot_w = L1_S_PROT_W_generic; 5993 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 5994 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 5995 5996 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5997 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5998 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 5999 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6000 6001 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6002 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6003 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6004 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6005 6006 pte_l1_s_proto = L1_S_PROTO_generic; 6007 pte_l1_c_proto = L1_C_PROTO_generic; 6008 pte_l2_s_proto = L2_S_PROTO_generic; 6009 6010 pmap_copy_page_func = pmap_copy_page_generic; 6011 pmap_zero_page_func = pmap_zero_page_generic; 6012 } 6013 6014 #if defined(CPU_ARM8) 6015 void 6016 pmap_pte_init_arm8(void) 6017 { 6018 6019 /* 6020 * ARM8 is compatible with generic, but we need to use 6021 * the page tables uncached. 6022 */ 6023 pmap_pte_init_generic(); 6024 6025 pte_l1_s_cache_mode_pt = 0; 6026 pte_l2_l_cache_mode_pt = 0; 6027 pte_l2_s_cache_mode_pt = 0; 6028 } 6029 #endif /* CPU_ARM8 */ 6030 6031 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6032 void 6033 pmap_pte_init_arm9(void) 6034 { 6035 6036 /* 6037 * ARM9 is compatible with generic, but we want to use 6038 * write-through caching for now. 6039 */ 6040 pmap_pte_init_generic(); 6041 6042 pte_l1_s_cache_mode = L1_S_C; 6043 pte_l2_l_cache_mode = L2_C; 6044 pte_l2_s_cache_mode = L2_C; 6045 6046 pte_l1_s_cache_mode_pt = L1_S_C; 6047 pte_l2_l_cache_mode_pt = L2_C; 6048 pte_l2_s_cache_mode_pt = L2_C; 6049 } 6050 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6051 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6052 6053 #if defined(CPU_ARM10) 6054 void 6055 pmap_pte_init_arm10(void) 6056 { 6057 6058 /* 6059 * ARM10 is compatible with generic, but we want to use 6060 * write-through caching for now. 6061 */ 6062 pmap_pte_init_generic(); 6063 6064 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6065 pte_l2_l_cache_mode = L2_B | L2_C; 6066 pte_l2_s_cache_mode = L2_B | L2_C; 6067 6068 pte_l1_s_cache_mode_pt = L1_S_C; 6069 pte_l2_l_cache_mode_pt = L2_C; 6070 pte_l2_s_cache_mode_pt = L2_C; 6071 6072 } 6073 #endif /* CPU_ARM10 */ 6074 6075 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6076 void 6077 pmap_pte_init_arm11(void) 6078 { 6079 6080 /* 6081 * ARM11 is compatible with generic, but we want to use 6082 * write-through caching for now. 6083 */ 6084 pmap_pte_init_generic(); 6085 6086 pte_l1_s_cache_mode = L1_S_C; 6087 pte_l2_l_cache_mode = L2_C; 6088 pte_l2_s_cache_mode = L2_C; 6089 6090 pte_l1_s_cache_mode_pt = L1_S_C; 6091 pte_l2_l_cache_mode_pt = L2_C; 6092 pte_l2_s_cache_mode_pt = L2_C; 6093 } 6094 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6095 6096 #if ARM_MMU_SA1 == 1 6097 void 6098 pmap_pte_init_sa1(void) 6099 { 6100 6101 /* 6102 * The StrongARM SA-1 cache does not have a write-through 6103 * mode. So, do the generic initialization, then reset 6104 * the page table cache mode to B=1,C=1, and note that 6105 * the PTEs need to be sync'd. 6106 */ 6107 pmap_pte_init_generic(); 6108 6109 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6110 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6111 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6112 6113 pmap_needs_pte_sync = 1; 6114 } 6115 #endif /* ARM_MMU_SA1 == 1*/ 6116 6117 #if ARM_MMU_XSCALE == 1 6118 #if (ARM_NMMUS > 1) 6119 static u_int xscale_use_minidata; 6120 #endif 6121 6122 void 6123 pmap_pte_init_xscale(void) 6124 { 6125 uint32_t auxctl; 6126 int write_through = 0; 6127 6128 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6129 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6130 6131 pte_l2_l_cache_mode = L2_B|L2_C; 6132 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6133 6134 pte_l2_s_cache_mode = L2_B|L2_C; 6135 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6136 6137 pte_l1_s_cache_mode_pt = L1_S_C; 6138 pte_l2_l_cache_mode_pt = L2_C; 6139 pte_l2_s_cache_mode_pt = L2_C; 6140 6141 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6142 /* 6143 * The XScale core has an enhanced mode where writes that 6144 * miss the cache cause a cache line to be allocated. This 6145 * is significantly faster than the traditional, write-through 6146 * behavior of this case. 6147 */ 6148 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6149 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6150 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6151 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6152 6153 #ifdef XSCALE_CACHE_WRITE_THROUGH 6154 /* 6155 * Some versions of the XScale core have various bugs in 6156 * their cache units, the work-around for which is to run 6157 * the cache in write-through mode. Unfortunately, this 6158 * has a major (negative) impact on performance. So, we 6159 * go ahead and run fast-and-loose, in the hopes that we 6160 * don't line up the planets in a way that will trip the 6161 * bugs. 6162 * 6163 * However, we give you the option to be slow-but-correct. 6164 */ 6165 write_through = 1; 6166 #elif defined(XSCALE_CACHE_WRITE_BACK) 6167 /* force write back cache mode */ 6168 write_through = 0; 6169 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6170 /* 6171 * Intel PXA2[15]0 processors are known to have a bug in 6172 * write-back cache on revision 4 and earlier (stepping 6173 * A[01] and B[012]). Fixed for C0 and later. 6174 */ 6175 { 6176 uint32_t id, type; 6177 6178 id = cpufunc_id(); 6179 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6180 6181 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6182 if ((id & CPU_ID_REVISION_MASK) < 5) { 6183 /* write through for stepping A0-1 and B0-2 */ 6184 write_through = 1; 6185 } 6186 } 6187 } 6188 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6189 6190 if (write_through) { 6191 pte_l1_s_cache_mode = L1_S_C; 6192 pte_l2_l_cache_mode = L2_C; 6193 pte_l2_s_cache_mode = L2_C; 6194 } 6195 6196 #if (ARM_NMMUS > 1) 6197 xscale_use_minidata = 1; 6198 #endif 6199 6200 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6201 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6202 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6203 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6204 6205 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6206 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6207 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6208 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6209 6210 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6211 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6212 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6213 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6214 6215 pte_l1_s_proto = L1_S_PROTO_xscale; 6216 pte_l1_c_proto = L1_C_PROTO_xscale; 6217 pte_l2_s_proto = L2_S_PROTO_xscale; 6218 6219 pmap_copy_page_func = pmap_copy_page_xscale; 6220 pmap_zero_page_func = pmap_zero_page_xscale; 6221 6222 /* 6223 * Disable ECC protection of page table access, for now. 6224 */ 6225 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6226 auxctl &= ~XSCALE_AUXCTL_P; 6227 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6228 } 6229 6230 /* 6231 * xscale_setup_minidata: 6232 * 6233 * Set up the mini-data cache clean area. We require the 6234 * caller to allocate the right amount of physically and 6235 * virtually contiguous space. 6236 */ 6237 void 6238 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6239 { 6240 extern vaddr_t xscale_minidata_clean_addr; 6241 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6242 pd_entry_t *pde = (pd_entry_t *) l1pt; 6243 pt_entry_t *pte; 6244 vsize_t size; 6245 uint32_t auxctl; 6246 6247 xscale_minidata_clean_addr = va; 6248 6249 /* Round it to page size. */ 6250 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6251 6252 for (; size != 0; 6253 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6254 #ifndef ARM32_NEW_VM_LAYOUT 6255 pte = (pt_entry_t *) 6256 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6257 #else 6258 pte = (pt_entry_t *) kernel_pt_lookup( 6259 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6260 #endif 6261 if (pte == NULL) 6262 panic("xscale_setup_minidata: can't find L2 table for " 6263 "VA 0x%08lx", va); 6264 #ifndef ARM32_NEW_VM_LAYOUT 6265 pte[(va >> PGSHIFT) & 0x3ff] = 6266 #else 6267 pte[l2pte_index(va)] = 6268 #endif 6269 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6270 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6271 } 6272 6273 /* 6274 * Configure the mini-data cache for write-back with 6275 * read/write-allocate. 6276 * 6277 * NOTE: In order to reconfigure the mini-data cache, we must 6278 * make sure it contains no valid data! In order to do that, 6279 * we must issue a global data cache invalidate command! 6280 * 6281 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6282 * THIS IS VERY IMPORTANT! 6283 */ 6284 6285 /* Invalidate data and mini-data. */ 6286 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6287 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6288 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6289 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6290 } 6291 6292 /* 6293 * Change the PTEs for the specified kernel mappings such that they 6294 * will use the mini data cache instead of the main data cache. 6295 */ 6296 void 6297 pmap_uarea(vaddr_t va) 6298 { 6299 struct l2_bucket *l2b; 6300 pt_entry_t *ptep, *sptep, pte; 6301 vaddr_t next_bucket, eva; 6302 6303 #if (ARM_NMMUS > 1) 6304 if (xscale_use_minidata == 0) 6305 return; 6306 #endif 6307 6308 eva = va + USPACE; 6309 6310 while (va < eva) { 6311 next_bucket = L2_NEXT_BUCKET(va); 6312 if (next_bucket > eva) 6313 next_bucket = eva; 6314 6315 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6316 KDASSERT(l2b != NULL); 6317 6318 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6319 6320 while (va < next_bucket) { 6321 pte = *ptep; 6322 if (!l2pte_minidata(pte)) { 6323 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6324 cpu_tlb_flushD_SE(va); 6325 *ptep = pte & ~L2_B; 6326 } 6327 ptep++; 6328 va += PAGE_SIZE; 6329 } 6330 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6331 } 6332 cpu_cpwait(); 6333 } 6334 #endif /* ARM_MMU_XSCALE == 1 */ 6335 6336 #if ARM_MMU_V7 == 1 6337 void 6338 pmap_pte_init_armv7(void) 6339 { 6340 /* 6341 * The ARMv7-A MMU is mostly compatible with generic. If the 6342 * AP field is zero, that now means "no access" rather than 6343 * read-only. The prototypes are a little different because of 6344 * the XN bit. 6345 */ 6346 pmap_pte_init_generic(); 6347 6348 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6349 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6350 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6351 6352 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6353 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6354 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6355 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6356 6357 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6358 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6359 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6360 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6361 6362 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6363 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6364 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6365 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6366 6367 pte_l1_s_proto = L1_S_PROTO_armv7; 6368 pte_l1_c_proto = L1_C_PROTO_armv7; 6369 pte_l2_s_proto = L2_S_PROTO_armv7; 6370 } 6371 #endif /* ARM_MMU_V7 */ 6372 6373 /* 6374 * return the PA of the current L1 table, for use when handling a crash dump 6375 */ 6376 uint32_t pmap_kernel_L1_addr(void) 6377 { 6378 return pmap_kernel()->pm_l1->l1_physaddr; 6379 } 6380 6381 #if defined(DDB) 6382 /* 6383 * A couple of ddb-callable functions for dumping pmaps 6384 */ 6385 void pmap_dump_all(void); 6386 void pmap_dump(pmap_t); 6387 6388 void 6389 pmap_dump_all(void) 6390 { 6391 pmap_t pm; 6392 6393 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6394 if (pm == pmap_kernel()) 6395 continue; 6396 pmap_dump(pm); 6397 printf("\n"); 6398 } 6399 } 6400 6401 static pt_entry_t ncptes[64]; 6402 static void pmap_dump_ncpg(pmap_t); 6403 6404 void 6405 pmap_dump(pmap_t pm) 6406 { 6407 struct l2_dtable *l2; 6408 struct l2_bucket *l2b; 6409 pt_entry_t *ptep, pte; 6410 vaddr_t l2_va, l2b_va, va; 6411 int i, j, k, occ, rows = 0; 6412 6413 if (pm == pmap_kernel()) 6414 printf("pmap_kernel (%p): ", pm); 6415 else 6416 printf("user pmap (%p): ", pm); 6417 6418 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6419 6420 l2_va = 0; 6421 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6422 l2 = pm->pm_l2[i]; 6423 6424 if (l2 == NULL || l2->l2_occupancy == 0) 6425 continue; 6426 6427 l2b_va = l2_va; 6428 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6429 l2b = &l2->l2_bucket[j]; 6430 6431 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6432 continue; 6433 6434 ptep = l2b->l2b_kva; 6435 6436 for (k = 0; k < 256 && ptep[k] == 0; k++) 6437 ; 6438 6439 k &= ~63; 6440 occ = l2b->l2b_occupancy; 6441 va = l2b_va + (k * 4096); 6442 for (; k < 256; k++, va += 0x1000) { 6443 char ch = ' '; 6444 if ((k % 64) == 0) { 6445 if ((rows % 8) == 0) { 6446 printf( 6447 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6448 } 6449 printf("%08lx: ", va); 6450 } 6451 6452 ncptes[k & 63] = 0; 6453 pte = ptep[k]; 6454 if (pte == 0) { 6455 ch = '.'; 6456 } else { 6457 occ--; 6458 switch (pte & 0x0c) { 6459 case 0x00: 6460 ch = 'D'; /* No cache No buff */ 6461 break; 6462 case 0x04: 6463 ch = 'B'; /* No cache buff */ 6464 break; 6465 case 0x08: 6466 if (pte & 0x40) 6467 ch = 'm'; 6468 else 6469 ch = 'C'; /* Cache No buff */ 6470 break; 6471 case 0x0c: 6472 ch = 'F'; /* Cache Buff */ 6473 break; 6474 } 6475 6476 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6477 ch += 0x20; 6478 6479 if ((pte & 0xc) == 0) 6480 ncptes[k & 63] = pte; 6481 } 6482 6483 if ((k % 64) == 63) { 6484 rows++; 6485 printf("%c\n", ch); 6486 pmap_dump_ncpg(pm); 6487 if (occ == 0) 6488 break; 6489 } else 6490 printf("%c", ch); 6491 } 6492 } 6493 } 6494 } 6495 6496 static void 6497 pmap_dump_ncpg(pmap_t pm) 6498 { 6499 struct vm_page *pg; 6500 struct vm_page_md *md; 6501 struct pv_entry *pv; 6502 int i; 6503 6504 for (i = 0; i < 63; i++) { 6505 if (ncptes[i] == 0) 6506 continue; 6507 6508 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6509 if (pg == NULL) 6510 continue; 6511 md = VM_PAGE_TO_MD(pg); 6512 6513 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6514 VM_PAGE_TO_PHYS(pg), 6515 md->krw_mappings, md->kro_mappings, 6516 md->urw_mappings, md->uro_mappings); 6517 6518 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6519 printf(" %c va 0x%08lx, flags 0x%x\n", 6520 (pm == pv->pv_pmap) ? '*' : ' ', 6521 pv->pv_va, pv->pv_flags); 6522 } 6523 } 6524 } 6525 #endif 6526 6527 #ifdef PMAP_STEAL_MEMORY 6528 void 6529 pmap_boot_pageadd(pv_addr_t *newpv) 6530 { 6531 pv_addr_t *pv, *npv; 6532 6533 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6534 if (newpv->pv_pa < pv->pv_va) { 6535 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6536 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6537 newpv->pv_size += pv->pv_size; 6538 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6539 } 6540 pv = NULL; 6541 } else { 6542 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6543 pv = npv) { 6544 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6545 KASSERT(pv->pv_pa < newpv->pv_pa); 6546 if (newpv->pv_pa > npv->pv_pa) 6547 continue; 6548 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6549 pv->pv_size += newpv->pv_size; 6550 return; 6551 } 6552 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6553 break; 6554 newpv->pv_size += npv->pv_size; 6555 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6556 SLIST_REMOVE_AFTER(newpv, pv_list); 6557 return; 6558 } 6559 } 6560 } 6561 6562 if (pv) { 6563 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6564 } else { 6565 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6566 } 6567 } 6568 6569 void 6570 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6571 pv_addr_t *rpv) 6572 { 6573 pv_addr_t *pv, **pvp; 6574 struct vm_physseg *ps; 6575 size_t i; 6576 6577 KASSERT(amount & PGOFSET); 6578 KASSERT((mask & PGOFSET) == 0); 6579 KASSERT((match & PGOFSET) == 0); 6580 KASSERT(amount != 0); 6581 6582 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6583 (pv = *pvp) != NULL; 6584 pvp = &SLIST_NEXT(pv, pv_list)) { 6585 pv_addr_t *newpv; 6586 psize_t off; 6587 /* 6588 * If this entry is too small to satify the request... 6589 */ 6590 KASSERT(pv->pv_size > 0); 6591 if (pv->pv_size < amount) 6592 continue; 6593 6594 for (off = 0; off <= mask; off += PAGE_SIZE) { 6595 if (((pv->pv_pa + off) & mask) == match 6596 && off + amount <= pv->pv_size) 6597 break; 6598 } 6599 if (off > mask) 6600 continue; 6601 6602 rpv->pv_va = pv->pv_va + off; 6603 rpv->pv_pa = pv->pv_pa + off; 6604 rpv->pv_size = amount; 6605 pv->pv_size -= amount; 6606 if (pv->pv_size == 0) { 6607 KASSERT(off == 0); 6608 KASSERT((vaddr_t) pv == rpv->pv_va); 6609 *pvp = SLIST_NEXT(pv, pv_list); 6610 } else if (off == 0) { 6611 KASSERT((vaddr_t) pv == rpv->pv_va); 6612 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6613 *newpv = *pv; 6614 newpv->pv_pa += amount; 6615 newpv->pv_va += amount; 6616 *pvp = newpv; 6617 } else if (off < pv->pv_size) { 6618 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6619 *newpv = *pv; 6620 newpv->pv_size -= off; 6621 newpv->pv_pa += off + amount; 6622 newpv->pv_va += off + amount; 6623 6624 SLIST_NEXT(pv, pv_list) = newpv; 6625 pv->pv_size = off; 6626 } else { 6627 KASSERT((vaddr_t) pv != rpv->pv_va); 6628 } 6629 memset((void *)rpv->pv_va, 0, amount); 6630 return; 6631 } 6632 6633 if (vm_nphysseg == 0) 6634 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6635 6636 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6637 (pv = *pvp) != NULL; 6638 pvp = &SLIST_NEXT(pv, pv_list)) { 6639 if (SLIST_NEXT(pv, pv_list) == NULL) 6640 break; 6641 } 6642 KASSERT(mask == 0); 6643 for (i = 0; i < vm_nphysseg; i++) { 6644 ps = VM_PHYSMEM_PTR(i); 6645 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6646 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6647 rpv->pv_va = pv->pv_va; 6648 rpv->pv_pa = pv->pv_pa; 6649 rpv->pv_size = amount; 6650 *pvp = NULL; 6651 pmap_map_chunk(kernel_l1pt.pv_va, 6652 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6653 ptoa(ps->avail_start), 6654 amount - pv->pv_size, 6655 VM_PROT_READ|VM_PROT_WRITE, 6656 PTE_CACHE); 6657 ps->avail_start += atop(amount - pv->pv_size); 6658 /* 6659 * If we consumed the entire physseg, remove it. 6660 */ 6661 if (ps->avail_start == ps->avail_end) { 6662 for (--vm_nphysseg; i < vm_nphysseg; i++) 6663 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6664 } 6665 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6666 return; 6667 } 6668 } 6669 6670 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6671 } 6672 6673 vaddr_t 6674 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6675 { 6676 pv_addr_t pv; 6677 6678 pmap_boot_pagealloc(size, 0, 0, &pv); 6679 6680 return pv.pv_va; 6681 } 6682 #endif /* PMAP_STEAL_MEMORY */ 6683 6684 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6685 { 6686 sysctl_createv(clog, 0, NULL, NULL, 6687 CTLFLAG_PERMANENT, 6688 CTLTYPE_NODE, "machdep", NULL, 6689 NULL, 0, NULL, 0, 6690 CTL_MACHDEP, CTL_EOL); 6691 6692 sysctl_createv(clog, 0, NULL, NULL, 6693 CTLFLAG_PERMANENT, 6694 CTLTYPE_INT, "kmpages", 6695 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6696 NULL, 0, &pmap_kmpages, 0, 6697 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6698 } 6699
Indexes created Sat Oct 25 16:10:12 GMT 2025