pmap.c revision 1.211.2.6
1 /* $NetBSD: pmap.c,v 1.211.2.6 2010/02/10 15:37:48 uebayasi Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/pool.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <machine/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.211.2.6 2010/02/10 15:37:48 uebayasi Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 static struct pmap kernel_pmap_store; 258 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 #ifdef PMAPCOUNTERS 308 #define PMAP_EVCNT_INITIALIZER(name) \ 309 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 310 311 #ifdef PMAP_CACHE_VIPT 312 static struct evcnt pmap_ev_vac_clean_one = 313 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 314 static struct evcnt pmap_ev_vac_flush_one = 315 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_lots = 317 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 318 static struct evcnt pmap_ev_vac_flush_lots2 = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 324 325 static struct evcnt pmap_ev_vac_color_new = 326 PMAP_EVCNT_INITIALIZER("new page color"); 327 static struct evcnt pmap_ev_vac_color_reuse = 328 PMAP_EVCNT_INITIALIZER("ok first page color"); 329 static struct evcnt pmap_ev_vac_color_ok = 330 PMAP_EVCNT_INITIALIZER("ok page color"); 331 static struct evcnt pmap_ev_vac_color_blind = 332 PMAP_EVCNT_INITIALIZER("blind page color"); 333 static struct evcnt pmap_ev_vac_color_change = 334 PMAP_EVCNT_INITIALIZER("change page color"); 335 static struct evcnt pmap_ev_vac_color_erase = 336 PMAP_EVCNT_INITIALIZER("erase page color"); 337 static struct evcnt pmap_ev_vac_color_none = 338 PMAP_EVCNT_INITIALIZER("no page color"); 339 static struct evcnt pmap_ev_vac_color_restore = 340 PMAP_EVCNT_INITIALIZER("restore page color"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 350 #endif 351 352 static struct evcnt pmap_ev_mappings = 353 PMAP_EVCNT_INITIALIZER("pages mapped"); 354 static struct evcnt pmap_ev_unmappings = 355 PMAP_EVCNT_INITIALIZER("pages unmapped"); 356 static struct evcnt pmap_ev_remappings = 357 PMAP_EVCNT_INITIALIZER("pages remapped"); 358 359 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 360 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 362 363 static struct evcnt pmap_ev_kernel_mappings = 364 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 365 static struct evcnt pmap_ev_kernel_unmappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 367 static struct evcnt pmap_ev_kernel_remappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 373 374 static struct evcnt pmap_ev_kenter_mappings = 375 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 376 static struct evcnt pmap_ev_kenter_unmappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 378 static struct evcnt pmap_ev_kenter_remappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 380 static struct evcnt pmap_ev_pt_mappings = 381 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 382 383 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 387 388 #ifdef PMAP_CACHE_VIPT 389 static struct evcnt pmap_ev_exec_mappings = 390 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 391 static struct evcnt pmap_ev_exec_cached = 392 PMAP_EVCNT_INITIALIZER("exec pages cached"); 393 394 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 396 397 static struct evcnt pmap_ev_exec_synced = 398 PMAP_EVCNT_INITIALIZER("exec pages synced"); 399 static struct evcnt pmap_ev_exec_synced_map = 400 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 401 static struct evcnt pmap_ev_exec_synced_unmap = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 403 static struct evcnt pmap_ev_exec_synced_remap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 405 static struct evcnt pmap_ev_exec_synced_clearbit = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 407 static struct evcnt pmap_ev_exec_synced_kremove = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 409 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 416 417 static struct evcnt pmap_ev_exec_discarded_unmap = 418 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 419 static struct evcnt pmap_ev_exec_discarded_zero = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 421 static struct evcnt pmap_ev_exec_discarded_copy = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 423 static struct evcnt pmap_ev_exec_discarded_page_protect = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 425 static struct evcnt pmap_ev_exec_discarded_clearbit = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 427 static struct evcnt pmap_ev_exec_discarded_kremove = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 429 430 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 436 #endif /* PMAP_CACHE_VIPT */ 437 438 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 439 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 440 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 441 442 EVCNT_ATTACH_STATIC(pmap_ev_updates); 443 EVCNT_ATTACH_STATIC(pmap_ev_collects); 444 EVCNT_ATTACH_STATIC(pmap_ev_activations); 445 446 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 447 #else 448 #define PMAPCOUNT(x) ((void)0) 449 #endif 450 451 /* 452 * pmap copy/zero page, and mem(5) hook point 453 */ 454 static pt_entry_t *csrc_pte, *cdst_pte; 455 static vaddr_t csrcp, cdstp; 456 vaddr_t memhook; /* used by mem.c */ 457 kmutex_t memlock; /* used by mem.c */ 458 void *zeropage; /* used by mem.c */ 459 extern void *msgbufaddr; 460 int pmap_kmpages; 461 /* 462 * Flag to indicate if pmap_init() has done its thing 463 */ 464 bool pmap_initialized; 465 466 /* 467 * Misc. locking data structures 468 */ 469 470 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 471 static struct lock pmap_main_lock; 472 473 #define PMAP_MAP_TO_HEAD_LOCK() \ 474 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 475 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 476 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 477 #define PMAP_HEAD_TO_MAP_LOCK() \ 478 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 479 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 480 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 481 #else 482 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 483 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 484 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 485 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 486 #endif 487 488 #define pmap_acquire_pmap_lock(pm) \ 489 do { \ 490 if ((pm) != pmap_kernel()) \ 491 mutex_enter(&(pm)->pm_lock); \ 492 } while (/*CONSTCOND*/0) 493 494 #define pmap_release_pmap_lock(pm) \ 495 do { \ 496 if ((pm) != pmap_kernel()) \ 497 mutex_exit(&(pm)->pm_lock); \ 498 } while (/*CONSTCOND*/0) 499 500 501 /* 502 * Metadata for L1 translation tables. 503 */ 504 struct l1_ttable { 505 /* Entry on the L1 Table list */ 506 SLIST_ENTRY(l1_ttable) l1_link; 507 508 /* Entry on the L1 Least Recently Used list */ 509 TAILQ_ENTRY(l1_ttable) l1_lru; 510 511 /* Track how many domains are allocated from this L1 */ 512 volatile u_int l1_domain_use_count; 513 514 /* 515 * A free-list of domain numbers for this L1. 516 * We avoid using ffs() and a bitmap to track domains since ffs() 517 * is slow on ARM. 518 */ 519 u_int8_t l1_domain_first; 520 u_int8_t l1_domain_free[PMAP_DOMAINS]; 521 522 /* Physical address of this L1 page table */ 523 paddr_t l1_physaddr; 524 525 /* KVA of this L1 page table */ 526 pd_entry_t *l1_kva; 527 }; 528 529 /* 530 * Convert a virtual address into its L1 table index. That is, the 531 * index used to locate the L2 descriptor table pointer in an L1 table. 532 * This is basically used to index l1->l1_kva[]. 533 * 534 * Each L2 descriptor table represents 1MB of VA space. 535 */ 536 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 537 538 /* 539 * L1 Page Tables are tracked using a Least Recently Used list. 540 * - New L1s are allocated from the HEAD. 541 * - Freed L1s are added to the TAIl. 542 * - Recently accessed L1s (where an 'access' is some change to one of 543 * the userland pmaps which owns this L1) are moved to the TAIL. 544 */ 545 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 546 static struct simplelock l1_lru_lock; 547 548 /* 549 * A list of all L1 tables 550 */ 551 static SLIST_HEAD(, l1_ttable) l1_list; 552 553 /* 554 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 555 * 556 * This is normally 16MB worth L2 page descriptors for any given pmap. 557 * Reference counts are maintained for L2 descriptors so they can be 558 * freed when empty. 559 */ 560 struct l2_dtable { 561 /* The number of L2 page descriptors allocated to this l2_dtable */ 562 u_int l2_occupancy; 563 564 /* List of L2 page descriptors */ 565 struct l2_bucket { 566 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 567 paddr_t l2b_phys; /* Physical address of same */ 568 u_short l2b_l1idx; /* This L2 table's L1 index */ 569 u_short l2b_occupancy; /* How many active descriptors */ 570 } l2_bucket[L2_BUCKET_SIZE]; 571 }; 572 573 /* 574 * Given an L1 table index, calculate the corresponding l2_dtable index 575 * and bucket index within the l2_dtable. 576 */ 577 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 578 (L2_SIZE - 1)) 579 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 580 581 /* 582 * Given a virtual address, this macro returns the 583 * virtual address required to drop into the next L2 bucket. 584 */ 585 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 586 587 /* 588 * L2 allocation. 589 */ 590 #define pmap_alloc_l2_dtable() \ 591 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 592 #define pmap_free_l2_dtable(l2) \ 593 pool_cache_put(&pmap_l2dtable_cache, (l2)) 594 #define pmap_alloc_l2_ptp(pap) \ 595 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 596 PR_NOWAIT, (pap))) 597 598 /* 599 * We try to map the page tables write-through, if possible. However, not 600 * all CPUs have a write-through cache mode, so on those we have to sync 601 * the cache when we frob page tables. 602 * 603 * We try to evaluate this at compile time, if possible. However, it's 604 * not always possible to do that, hence this run-time var. 605 */ 606 int pmap_needs_pte_sync; 607 608 /* 609 * Real definition of pv_entry. 610 */ 611 struct pv_entry { 612 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 613 pmap_t pv_pmap; /* pmap where mapping lies */ 614 vaddr_t pv_va; /* virtual address for mapping */ 615 u_int pv_flags; /* flags */ 616 }; 617 618 /* 619 * Macro to determine if a mapping might be resident in the 620 * instruction cache and/or TLB 621 */ 622 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 623 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 624 625 /* 626 * Macro to determine if a mapping might be resident in the 627 * data cache and/or TLB 628 */ 629 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 630 631 /* 632 * Local prototypes 633 */ 634 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 635 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 636 pt_entry_t **); 637 static bool pmap_is_current(pmap_t); 638 static bool pmap_is_cached(pmap_t); 639 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 640 pmap_t, vaddr_t, u_int); 641 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 642 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 643 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 644 u_int, u_int); 645 646 static void pmap_pinit(pmap_t); 647 static int pmap_pmap_ctor(void *, void *, int); 648 649 static void pmap_alloc_l1(pmap_t); 650 static void pmap_free_l1(pmap_t); 651 static void pmap_use_l1(pmap_t); 652 653 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 654 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 655 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 656 static int pmap_l2ptp_ctor(void *, void *, int); 657 static int pmap_l2dtable_ctor(void *, void *, int); 658 659 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 660 #ifdef PMAP_CACHE_VIVT 661 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 662 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 663 #endif 664 665 static void pmap_clearbit(struct vm_page *, u_int); 666 #ifdef PMAP_CACHE_VIVT 667 static int pmap_clean_page(struct pv_entry *, bool); 668 #endif 669 #ifdef PMAP_CACHE_VIPT 670 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 671 enum pmap_flush_op { 672 PMAP_FLUSH_PRIMARY, 673 PMAP_FLUSH_SECONDARY, 674 PMAP_CLEAN_PRIMARY 675 }; 676 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 677 #endif 678 static void pmap_page_remove(struct vm_page *); 679 680 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 681 static vaddr_t kernel_pt_lookup(paddr_t); 682 683 684 /* 685 * External function prototypes 686 */ 687 extern void bzero_page(vaddr_t); 688 extern void bcopy_page(vaddr_t, vaddr_t); 689 690 /* 691 * Misc variables 692 */ 693 vaddr_t virtual_avail; 694 vaddr_t virtual_end; 695 vaddr_t pmap_curmaxkvaddr; 696 697 paddr_t avail_start; 698 paddr_t avail_end; 699 700 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 701 pv_addr_t kernelpages; 702 pv_addr_t kernel_l1pt; 703 pv_addr_t systempage; 704 705 /* Function to set the debug level of the pmap code */ 706 707 #ifdef PMAP_DEBUG 708 void 709 pmap_debug(int level) 710 { 711 pmap_debug_level = level; 712 printf("pmap_debug: level=%d\n", pmap_debug_level); 713 } 714 #endif /* PMAP_DEBUG */ 715 716 /* 717 * A bunch of routines to conditionally flush the caches/TLB depending 718 * on whether the specified pmap actually needs to be flushed at any 719 * given time. 720 */ 721 static inline void 722 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 723 { 724 725 if (pm->pm_cstate.cs_tlb_id) 726 cpu_tlb_flushID_SE(va); 727 } 728 729 static inline void 730 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 731 { 732 733 if (pm->pm_cstate.cs_tlb_d) 734 cpu_tlb_flushD_SE(va); 735 } 736 737 static inline void 738 pmap_tlb_flushID(pmap_t pm) 739 { 740 741 if (pm->pm_cstate.cs_tlb_id) { 742 cpu_tlb_flushID(); 743 pm->pm_cstate.cs_tlb = 0; 744 } 745 } 746 747 static inline void 748 pmap_tlb_flushD(pmap_t pm) 749 { 750 751 if (pm->pm_cstate.cs_tlb_d) { 752 cpu_tlb_flushD(); 753 pm->pm_cstate.cs_tlb_d = 0; 754 } 755 } 756 757 #ifdef PMAP_CACHE_VIVT 758 static inline void 759 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 760 { 761 if (pm->pm_cstate.cs_cache_id) { 762 cpu_idcache_wbinv_range(va, len); 763 } 764 } 765 766 static inline void 767 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 768 bool do_inv, bool rd_only) 769 { 770 771 if (pm->pm_cstate.cs_cache_d) { 772 if (do_inv) { 773 if (rd_only) 774 cpu_dcache_inv_range(va, len); 775 else 776 cpu_dcache_wbinv_range(va, len); 777 } else 778 if (!rd_only) 779 cpu_dcache_wb_range(va, len); 780 } 781 } 782 783 static inline void 784 pmap_idcache_wbinv_all(pmap_t pm) 785 { 786 if (pm->pm_cstate.cs_cache_id) { 787 cpu_idcache_wbinv_all(); 788 pm->pm_cstate.cs_cache = 0; 789 } 790 } 791 792 static inline void 793 pmap_dcache_wbinv_all(pmap_t pm) 794 { 795 if (pm->pm_cstate.cs_cache_d) { 796 cpu_dcache_wbinv_all(); 797 pm->pm_cstate.cs_cache_d = 0; 798 } 799 } 800 #endif /* PMAP_CACHE_VIVT */ 801 802 static inline bool 803 pmap_is_current(pmap_t pm) 804 { 805 806 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 807 return true; 808 809 return false; 810 } 811 812 static inline bool 813 pmap_is_cached(pmap_t pm) 814 { 815 816 if (pm == pmap_kernel() || pmap_recent_user == NULL || 817 pmap_recent_user == pm) 818 return (true); 819 820 return false; 821 } 822 823 /* 824 * PTE_SYNC_CURRENT: 825 * 826 * Make sure the pte is written out to RAM. 827 * We need to do this for one of two cases: 828 * - We're dealing with the kernel pmap 829 * - There is no pmap active in the cache/tlb. 830 * - The specified pmap is 'active' in the cache/tlb. 831 */ 832 #ifdef PMAP_INCLUDE_PTE_SYNC 833 #define PTE_SYNC_CURRENT(pm, ptep) \ 834 do { \ 835 if (PMAP_NEEDS_PTE_SYNC && \ 836 pmap_is_cached(pm)) \ 837 PTE_SYNC(ptep); \ 838 } while (/*CONSTCOND*/0) 839 #else 840 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 841 #endif 842 843 /* 844 * main pv_entry manipulation functions: 845 * pmap_enter_pv: enter a mapping onto a vm_page list 846 * pmap_remove_pv: remove a mappiing from a vm_page list 847 * 848 * NOTE: pmap_enter_pv expects to lock the pvh itself 849 * pmap_remove_pv expects te caller to lock the pvh before calling 850 */ 851 852 /* 853 * pmap_enter_pv: enter a mapping onto a vm_page lst 854 * 855 * => caller should hold the proper lock on pmap_main_lock 856 * => caller should have pmap locked 857 * => we will gain the lock on the vm_page and allocate the new pv_entry 858 * => caller should adjust ptp's wire_count before calling 859 * => caller should not adjust pmap's wire_count 860 */ 861 static void 862 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 863 vaddr_t va, u_int flags) 864 { 865 struct pv_entry **pvp; 866 867 NPDEBUG(PDB_PVDUMP, 868 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 869 870 pv->pv_pmap = pm; 871 pv->pv_va = va; 872 pv->pv_flags = flags; 873 874 simple_lock(&md->pvh_slock); /* lock vm_page */ 875 pvp = &SLIST_FIRST(&md->pvh_list); 876 #ifdef PMAP_CACHE_VIPT 877 /* 878 * Insert unmanaged entries, writeable first, at the head of 879 * the pv list. 880 */ 881 if (__predict_true((flags & PVF_KENTRY) == 0)) { 882 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 883 pvp = &SLIST_NEXT(*pvp, pv_link); 884 } else if ((flags & PVF_WRITE) == 0) { 885 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 886 pvp = &SLIST_NEXT(*pvp, pv_link); 887 } 888 #endif 889 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 890 *pvp = pv; /* ... locked list */ 891 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 892 #ifdef PMAP_CACHE_VIPT 893 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 894 md->pvh_attrs |= PVF_KMOD; 895 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 896 md->pvh_attrs |= PVF_DIRTY; 897 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 898 #endif 899 if (pm == pmap_kernel()) { 900 PMAPCOUNT(kernel_mappings); 901 if (flags & PVF_WRITE) 902 md->krw_mappings++; 903 else 904 md->kro_mappings++; 905 } else { 906 if (flags & PVF_WRITE) 907 md->urw_mappings++; 908 else 909 md->uro_mappings++; 910 } 911 912 #ifdef PMAP_CACHE_VIPT 913 /* 914 * If this is an exec mapping and its the first exec mapping 915 * for this page, make sure to sync the I-cache. 916 */ 917 if (PV_IS_EXEC_P(flags)) { 918 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 919 pmap_syncicache_page(md, pa); 920 PMAPCOUNT(exec_synced_map); 921 } 922 PMAPCOUNT(exec_mappings); 923 } 924 #endif 925 926 PMAPCOUNT(mappings); 927 simple_unlock(&md->pvh_slock); /* unlock, done! */ 928 929 if (pv->pv_flags & PVF_WIRED) 930 ++pm->pm_stats.wired_count; 931 } 932 933 /* 934 * 935 * pmap_find_pv: Find a pv entry 936 * 937 * => caller should hold lock on vm_page 938 */ 939 static inline struct pv_entry * 940 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 941 { 942 struct pv_entry *pv; 943 944 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 945 if (pm == pv->pv_pmap && va == pv->pv_va) 946 break; 947 } 948 949 return (pv); 950 } 951 952 /* 953 * pmap_remove_pv: try to remove a mapping from a pv_list 954 * 955 * => caller should hold proper lock on pmap_main_lock 956 * => pmap should be locked 957 * => caller should hold lock on vm_page [so that attrs can be adjusted] 958 * => caller should adjust ptp's wire_count and free PTP if needed 959 * => caller should NOT adjust pmap's wire_count 960 * => we return the removed pv 961 */ 962 static struct pv_entry * 963 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 964 { 965 struct pv_entry *pv, **prevptr; 966 967 NPDEBUG(PDB_PVDUMP, 968 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 969 970 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 971 pv = *prevptr; 972 973 while (pv) { 974 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 975 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 976 "%p\n", pm, md)); 977 if (pv->pv_flags & PVF_WIRED) { 978 --pm->pm_stats.wired_count; 979 } 980 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 981 if (pm == pmap_kernel()) { 982 PMAPCOUNT(kernel_unmappings); 983 if (pv->pv_flags & PVF_WRITE) 984 md->krw_mappings--; 985 else 986 md->kro_mappings--; 987 } else { 988 if (pv->pv_flags & PVF_WRITE) 989 md->urw_mappings--; 990 else 991 md->uro_mappings--; 992 } 993 994 PMAPCOUNT(unmappings); 995 #ifdef PMAP_CACHE_VIPT 996 if (!(pv->pv_flags & PVF_WRITE)) 997 break; 998 /* 999 * If this page has had an exec mapping, then if 1000 * this was the last mapping, discard the contents, 1001 * otherwise sync the i-cache for this page. 1002 */ 1003 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1004 if (SLIST_EMPTY(&md->pvh_list)) { 1005 md->pvh_attrs &= ~PVF_EXEC; 1006 PMAPCOUNT(exec_discarded_unmap); 1007 } else { 1008 pmap_syncicache_page(md, pa); 1009 PMAPCOUNT(exec_synced_unmap); 1010 } 1011 } 1012 #endif /* PMAP_CACHE_VIPT */ 1013 break; 1014 } 1015 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1016 pv = *prevptr; /* advance */ 1017 } 1018 1019 #ifdef PMAP_CACHE_VIPT 1020 /* 1021 * If we no longer have a WRITEABLE KENTRY at the head of list, 1022 * clear the KMOD attribute from the page. 1023 */ 1024 if (SLIST_FIRST(&md->pvh_list) == NULL 1025 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1026 md->pvh_attrs &= ~PVF_KMOD; 1027 1028 /* 1029 * If this was a writeable page and there are no more writeable 1030 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1031 * the contents to memory. 1032 */ 1033 if (md->krw_mappings + md->urw_mappings == 0) 1034 md->pvh_attrs &= ~PVF_WRITE; 1035 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1036 #endif /* PMAP_CACHE_VIPT */ 1037 1038 return(pv); /* return removed pv */ 1039 } 1040 1041 /* 1042 * 1043 * pmap_modify_pv: Update pv flags 1044 * 1045 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1046 * => caller should NOT adjust pmap's wire_count 1047 * => caller must call pmap_vac_me_harder() if writable status of a page 1048 * may have changed. 1049 * => we return the old flags 1050 * 1051 * Modify a physical-virtual mapping in the pv table 1052 */ 1053 static u_int 1054 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1055 u_int clr_mask, u_int set_mask) 1056 { 1057 struct pv_entry *npv; 1058 u_int flags, oflags; 1059 1060 KASSERT((clr_mask & PVF_KENTRY) == 0); 1061 KASSERT((set_mask & PVF_KENTRY) == 0); 1062 1063 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1064 return (0); 1065 1066 NPDEBUG(PDB_PVDUMP, 1067 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1068 1069 /* 1070 * There is at least one VA mapping this page. 1071 */ 1072 1073 if (clr_mask & (PVF_REF | PVF_MOD)) { 1074 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1075 #ifdef PMAP_CACHE_VIPT 1076 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1077 md->pvh_attrs |= PVF_DIRTY; 1078 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1079 #endif 1080 } 1081 1082 oflags = npv->pv_flags; 1083 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1084 1085 if ((flags ^ oflags) & PVF_WIRED) { 1086 if (flags & PVF_WIRED) 1087 ++pm->pm_stats.wired_count; 1088 else 1089 --pm->pm_stats.wired_count; 1090 } 1091 1092 if ((flags ^ oflags) & PVF_WRITE) { 1093 if (pm == pmap_kernel()) { 1094 if (flags & PVF_WRITE) { 1095 md->krw_mappings++; 1096 md->kro_mappings--; 1097 } else { 1098 md->kro_mappings++; 1099 md->krw_mappings--; 1100 } 1101 } else { 1102 if (flags & PVF_WRITE) { 1103 md->urw_mappings++; 1104 md->uro_mappings--; 1105 } else { 1106 md->uro_mappings++; 1107 md->urw_mappings--; 1108 } 1109 } 1110 } 1111 #ifdef PMAP_CACHE_VIPT 1112 if (md->urw_mappings + md->krw_mappings == 0) 1113 md->pvh_attrs &= ~PVF_WRITE; 1114 /* 1115 * We have two cases here: the first is from enter_pv (new exec 1116 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1117 * Since in latter, pmap_enter_pv won't do anything, we just have 1118 * to do what pmap_remove_pv would do. 1119 */ 1120 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1121 || (PV_IS_EXEC_P(md->pvh_attrs) 1122 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1123 pmap_syncicache_page(md, pa); 1124 PMAPCOUNT(exec_synced_remap); 1125 } 1126 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1127 #endif 1128 1129 PMAPCOUNT(remappings); 1130 1131 return (oflags); 1132 } 1133 1134 /* 1135 * Allocate an L1 translation table for the specified pmap. 1136 * This is called at pmap creation time. 1137 */ 1138 static void 1139 pmap_alloc_l1(pmap_t pm) 1140 { 1141 struct l1_ttable *l1; 1142 u_int8_t domain; 1143 1144 /* 1145 * Remove the L1 at the head of the LRU list 1146 */ 1147 simple_lock(&l1_lru_lock); 1148 l1 = TAILQ_FIRST(&l1_lru_list); 1149 KDASSERT(l1 != NULL); 1150 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1151 1152 /* 1153 * Pick the first available domain number, and update 1154 * the link to the next number. 1155 */ 1156 domain = l1->l1_domain_first; 1157 l1->l1_domain_first = l1->l1_domain_free[domain]; 1158 1159 /* 1160 * If there are still free domain numbers in this L1, 1161 * put it back on the TAIL of the LRU list. 1162 */ 1163 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1164 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1165 1166 simple_unlock(&l1_lru_lock); 1167 1168 /* 1169 * Fix up the relevant bits in the pmap structure 1170 */ 1171 pm->pm_l1 = l1; 1172 pm->pm_domain = domain; 1173 } 1174 1175 /* 1176 * Free an L1 translation table. 1177 * This is called at pmap destruction time. 1178 */ 1179 static void 1180 pmap_free_l1(pmap_t pm) 1181 { 1182 struct l1_ttable *l1 = pm->pm_l1; 1183 1184 simple_lock(&l1_lru_lock); 1185 1186 /* 1187 * If this L1 is currently on the LRU list, remove it. 1188 */ 1189 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1190 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1191 1192 /* 1193 * Free up the domain number which was allocated to the pmap 1194 */ 1195 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1196 l1->l1_domain_first = pm->pm_domain; 1197 l1->l1_domain_use_count--; 1198 1199 /* 1200 * The L1 now must have at least 1 free domain, so add 1201 * it back to the LRU list. If the use count is zero, 1202 * put it at the head of the list, otherwise it goes 1203 * to the tail. 1204 */ 1205 if (l1->l1_domain_use_count == 0) 1206 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1207 else 1208 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1209 1210 simple_unlock(&l1_lru_lock); 1211 } 1212 1213 static inline void 1214 pmap_use_l1(pmap_t pm) 1215 { 1216 struct l1_ttable *l1; 1217 1218 /* 1219 * Do nothing if we're in interrupt context. 1220 * Access to an L1 by the kernel pmap must not affect 1221 * the LRU list. 1222 */ 1223 if (cpu_intr_p() || pm == pmap_kernel()) 1224 return; 1225 1226 l1 = pm->pm_l1; 1227 1228 /* 1229 * If the L1 is not currently on the LRU list, just return 1230 */ 1231 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1232 return; 1233 1234 simple_lock(&l1_lru_lock); 1235 1236 /* 1237 * Check the use count again, now that we've acquired the lock 1238 */ 1239 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1240 simple_unlock(&l1_lru_lock); 1241 return; 1242 } 1243 1244 /* 1245 * Move the L1 to the back of the LRU list 1246 */ 1247 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1248 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1249 1250 simple_unlock(&l1_lru_lock); 1251 } 1252 1253 /* 1254 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1255 * 1256 * Free an L2 descriptor table. 1257 */ 1258 static inline void 1259 #ifndef PMAP_INCLUDE_PTE_SYNC 1260 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1261 #else 1262 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1263 #endif 1264 { 1265 #ifdef PMAP_INCLUDE_PTE_SYNC 1266 #ifdef PMAP_CACHE_VIVT 1267 /* 1268 * Note: With a write-back cache, we may need to sync this 1269 * L2 table before re-using it. 1270 * This is because it may have belonged to a non-current 1271 * pmap, in which case the cache syncs would have been 1272 * skipped for the pages that were being unmapped. If the 1273 * L2 table were then to be immediately re-allocated to 1274 * the *current* pmap, it may well contain stale mappings 1275 * which have not yet been cleared by a cache write-back 1276 * and so would still be visible to the mmu. 1277 */ 1278 if (need_sync) 1279 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1280 #endif /* PMAP_CACHE_VIVT */ 1281 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1282 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1283 } 1284 1285 /* 1286 * Returns a pointer to the L2 bucket associated with the specified pmap 1287 * and VA, or NULL if no L2 bucket exists for the address. 1288 */ 1289 static inline struct l2_bucket * 1290 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1291 { 1292 struct l2_dtable *l2; 1293 struct l2_bucket *l2b; 1294 u_short l1idx; 1295 1296 l1idx = L1_IDX(va); 1297 1298 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1299 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1300 return (NULL); 1301 1302 return (l2b); 1303 } 1304 1305 /* 1306 * Returns a pointer to the L2 bucket associated with the specified pmap 1307 * and VA. 1308 * 1309 * If no L2 bucket exists, perform the necessary allocations to put an L2 1310 * bucket/page table in place. 1311 * 1312 * Note that if a new L2 bucket/page was allocated, the caller *must* 1313 * increment the bucket occupancy counter appropriately *before* 1314 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1315 * the bucket/page in the meantime. 1316 */ 1317 static struct l2_bucket * 1318 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1319 { 1320 struct l2_dtable *l2; 1321 struct l2_bucket *l2b; 1322 u_short l1idx; 1323 1324 l1idx = L1_IDX(va); 1325 1326 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1327 /* 1328 * No mapping at this address, as there is 1329 * no entry in the L1 table. 1330 * Need to allocate a new l2_dtable. 1331 */ 1332 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1333 return (NULL); 1334 1335 /* 1336 * Link it into the parent pmap 1337 */ 1338 pm->pm_l2[L2_IDX(l1idx)] = l2; 1339 } 1340 1341 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1342 1343 /* 1344 * Fetch pointer to the L2 page table associated with the address. 1345 */ 1346 if (l2b->l2b_kva == NULL) { 1347 pt_entry_t *ptep; 1348 1349 /* 1350 * No L2 page table has been allocated. Chances are, this 1351 * is because we just allocated the l2_dtable, above. 1352 */ 1353 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1354 /* 1355 * Oops, no more L2 page tables available at this 1356 * time. We may need to deallocate the l2_dtable 1357 * if we allocated a new one above. 1358 */ 1359 if (l2->l2_occupancy == 0) { 1360 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1361 pmap_free_l2_dtable(l2); 1362 } 1363 return (NULL); 1364 } 1365 1366 l2->l2_occupancy++; 1367 l2b->l2b_kva = ptep; 1368 l2b->l2b_l1idx = l1idx; 1369 } 1370 1371 return (l2b); 1372 } 1373 1374 /* 1375 * One or more mappings in the specified L2 descriptor table have just been 1376 * invalidated. 1377 * 1378 * Garbage collect the metadata and descriptor table itself if necessary. 1379 * 1380 * The pmap lock must be acquired when this is called (not necessary 1381 * for the kernel pmap). 1382 */ 1383 static void 1384 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1385 { 1386 struct l2_dtable *l2; 1387 pd_entry_t *pl1pd, l1pd; 1388 pt_entry_t *ptep; 1389 u_short l1idx; 1390 1391 KDASSERT(count <= l2b->l2b_occupancy); 1392 1393 /* 1394 * Update the bucket's reference count according to how many 1395 * PTEs the caller has just invalidated. 1396 */ 1397 l2b->l2b_occupancy -= count; 1398 1399 /* 1400 * Note: 1401 * 1402 * Level 2 page tables allocated to the kernel pmap are never freed 1403 * as that would require checking all Level 1 page tables and 1404 * removing any references to the Level 2 page table. See also the 1405 * comment elsewhere about never freeing bootstrap L2 descriptors. 1406 * 1407 * We make do with just invalidating the mapping in the L2 table. 1408 * 1409 * This isn't really a big deal in practice and, in fact, leads 1410 * to a performance win over time as we don't need to continually 1411 * alloc/free. 1412 */ 1413 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1414 return; 1415 1416 /* 1417 * There are no more valid mappings in this level 2 page table. 1418 * Go ahead and NULL-out the pointer in the bucket, then 1419 * free the page table. 1420 */ 1421 l1idx = l2b->l2b_l1idx; 1422 ptep = l2b->l2b_kva; 1423 l2b->l2b_kva = NULL; 1424 1425 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1426 1427 /* 1428 * If the L1 slot matches the pmap's domain 1429 * number, then invalidate it. 1430 */ 1431 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1432 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1433 *pl1pd = 0; 1434 PTE_SYNC(pl1pd); 1435 } 1436 1437 /* 1438 * Release the L2 descriptor table back to the pool cache. 1439 */ 1440 #ifndef PMAP_INCLUDE_PTE_SYNC 1441 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1442 #else 1443 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1444 #endif 1445 1446 /* 1447 * Update the reference count in the associated l2_dtable 1448 */ 1449 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1450 if (--l2->l2_occupancy > 0) 1451 return; 1452 1453 /* 1454 * There are no more valid mappings in any of the Level 1 1455 * slots managed by this l2_dtable. Go ahead and NULL-out 1456 * the pointer in the parent pmap and free the l2_dtable. 1457 */ 1458 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1459 pmap_free_l2_dtable(l2); 1460 } 1461 1462 /* 1463 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1464 * structures. 1465 */ 1466 static int 1467 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1468 { 1469 #ifndef PMAP_INCLUDE_PTE_SYNC 1470 struct l2_bucket *l2b; 1471 pt_entry_t *ptep, pte; 1472 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1473 1474 /* 1475 * The mappings for these page tables were initially made using 1476 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1477 * mode will not be right for page table mappings. To avoid 1478 * polluting the pmap_kenter_pa() code with a special case for 1479 * page tables, we simply fix up the cache-mode here if it's not 1480 * correct. 1481 */ 1482 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1483 KDASSERT(l2b != NULL); 1484 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1485 pte = *ptep; 1486 1487 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1488 /* 1489 * Page tables must have the cache-mode set to Write-Thru. 1490 */ 1491 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1492 PTE_SYNC(ptep); 1493 cpu_tlb_flushD_SE(va); 1494 cpu_cpwait(); 1495 } 1496 #endif 1497 1498 memset(v, 0, L2_TABLE_SIZE_REAL); 1499 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1500 return (0); 1501 } 1502 1503 static int 1504 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1505 { 1506 1507 memset(v, 0, sizeof(struct l2_dtable)); 1508 return (0); 1509 } 1510 1511 static int 1512 pmap_pmap_ctor(void *arg, void *v, int flags) 1513 { 1514 1515 memset(v, 0, sizeof(struct pmap)); 1516 return (0); 1517 } 1518 1519 static void 1520 pmap_pinit(pmap_t pm) 1521 { 1522 struct l2_bucket *l2b; 1523 1524 if (vector_page < KERNEL_BASE) { 1525 /* 1526 * Map the vector page. 1527 */ 1528 pmap_enter(pm, vector_page, systempage.pv_pa, 1529 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1530 pmap_update(pm); 1531 1532 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1533 l2b = pmap_get_l2_bucket(pm, vector_page); 1534 KDASSERT(l2b != NULL); 1535 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1536 L1_C_DOM(pm->pm_domain); 1537 } else 1538 pm->pm_pl1vec = NULL; 1539 } 1540 1541 #ifdef PMAP_CACHE_VIVT 1542 /* 1543 * Since we have a virtually indexed cache, we may need to inhibit caching if 1544 * there is more than one mapping and at least one of them is writable. 1545 * Since we purge the cache on every context switch, we only need to check for 1546 * other mappings within the same pmap, or kernel_pmap. 1547 * This function is also called when a page is unmapped, to possibly reenable 1548 * caching on any remaining mappings. 1549 * 1550 * The code implements the following logic, where: 1551 * 1552 * KW = # of kernel read/write pages 1553 * KR = # of kernel read only pages 1554 * UW = # of user read/write pages 1555 * UR = # of user read only pages 1556 * 1557 * KC = kernel mapping is cacheable 1558 * UC = user mapping is cacheable 1559 * 1560 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1561 * +--------------------------------------------- 1562 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1563 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1564 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1565 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1566 */ 1567 1568 static const int pmap_vac_flags[4][4] = { 1569 {-1, 0, 0, PVF_KNC}, 1570 {0, 0, PVF_NC, PVF_NC}, 1571 {0, PVF_NC, PVF_NC, PVF_NC}, 1572 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1573 }; 1574 1575 static inline int 1576 pmap_get_vac_flags(const struct vm_page_md *md) 1577 { 1578 int kidx, uidx; 1579 1580 kidx = 0; 1581 if (md->kro_mappings || md->krw_mappings > 1) 1582 kidx |= 1; 1583 if (md->krw_mappings) 1584 kidx |= 2; 1585 1586 uidx = 0; 1587 if (md->uro_mappings || md->urw_mappings > 1) 1588 uidx |= 1; 1589 if (md->urw_mappings) 1590 uidx |= 2; 1591 1592 return (pmap_vac_flags[uidx][kidx]); 1593 } 1594 1595 static inline void 1596 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1597 { 1598 int nattr; 1599 1600 nattr = pmap_get_vac_flags(md); 1601 1602 if (nattr < 0) { 1603 md->pvh_attrs &= ~PVF_NC; 1604 return; 1605 } 1606 1607 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1608 return; 1609 1610 if (pm == pmap_kernel()) 1611 pmap_vac_me_kpmap(md, pa, pm, va); 1612 else 1613 pmap_vac_me_user(md, pa, pm, va); 1614 1615 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1616 } 1617 1618 static void 1619 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1620 { 1621 u_int u_cacheable, u_entries; 1622 struct pv_entry *pv; 1623 pmap_t last_pmap = pm; 1624 1625 /* 1626 * Pass one, see if there are both kernel and user pmaps for 1627 * this page. Calculate whether there are user-writable or 1628 * kernel-writable pages. 1629 */ 1630 u_cacheable = 0; 1631 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1632 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1633 u_cacheable++; 1634 } 1635 1636 u_entries = md->urw_mappings + md->uro_mappings; 1637 1638 /* 1639 * We know we have just been updating a kernel entry, so if 1640 * all user pages are already cacheable, then there is nothing 1641 * further to do. 1642 */ 1643 if (md->k_mappings == 0 && u_cacheable == u_entries) 1644 return; 1645 1646 if (u_entries) { 1647 /* 1648 * Scan over the list again, for each entry, if it 1649 * might not be set correctly, call pmap_vac_me_user 1650 * to recalculate the settings. 1651 */ 1652 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1653 /* 1654 * We know kernel mappings will get set 1655 * correctly in other calls. We also know 1656 * that if the pmap is the same as last_pmap 1657 * then we've just handled this entry. 1658 */ 1659 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1660 continue; 1661 1662 /* 1663 * If there are kernel entries and this page 1664 * is writable but non-cacheable, then we can 1665 * skip this entry also. 1666 */ 1667 if (md->k_mappings && 1668 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1669 (PVF_NC | PVF_WRITE)) 1670 continue; 1671 1672 /* 1673 * Similarly if there are no kernel-writable 1674 * entries and the page is already 1675 * read-only/cacheable. 1676 */ 1677 if (md->krw_mappings == 0 && 1678 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1679 continue; 1680 1681 /* 1682 * For some of the remaining cases, we know 1683 * that we must recalculate, but for others we 1684 * can't tell if they are correct or not, so 1685 * we recalculate anyway. 1686 */ 1687 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1688 } 1689 1690 if (md->k_mappings == 0) 1691 return; 1692 } 1693 1694 pmap_vac_me_user(md, pa, pm, va); 1695 } 1696 1697 static void 1698 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1699 { 1700 pmap_t kpmap = pmap_kernel(); 1701 struct pv_entry *pv, *npv = NULL; 1702 struct l2_bucket *l2b; 1703 pt_entry_t *ptep, pte; 1704 u_int entries = 0; 1705 u_int writable = 0; 1706 u_int cacheable_entries = 0; 1707 u_int kern_cacheable = 0; 1708 u_int other_writable = 0; 1709 1710 /* 1711 * Count mappings and writable mappings in this pmap. 1712 * Include kernel mappings as part of our own. 1713 * Keep a pointer to the first one. 1714 */ 1715 npv = NULL; 1716 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1717 /* Count mappings in the same pmap */ 1718 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1719 if (entries++ == 0) 1720 npv = pv; 1721 1722 /* Cacheable mappings */ 1723 if ((pv->pv_flags & PVF_NC) == 0) { 1724 cacheable_entries++; 1725 if (kpmap == pv->pv_pmap) 1726 kern_cacheable++; 1727 } 1728 1729 /* Writable mappings */ 1730 if (pv->pv_flags & PVF_WRITE) 1731 ++writable; 1732 } else 1733 if (pv->pv_flags & PVF_WRITE) 1734 other_writable = 1; 1735 } 1736 1737 /* 1738 * Enable or disable caching as necessary. 1739 * Note: the first entry might be part of the kernel pmap, 1740 * so we can't assume this is indicative of the state of the 1741 * other (maybe non-kpmap) entries. 1742 */ 1743 if ((entries > 1 && writable) || 1744 (entries > 0 && pm == kpmap && other_writable)) { 1745 if (cacheable_entries == 0) 1746 return; 1747 1748 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1749 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1750 (pv->pv_flags & PVF_NC)) 1751 continue; 1752 1753 pv->pv_flags |= PVF_NC; 1754 1755 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1756 KDASSERT(l2b != NULL); 1757 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1758 pte = *ptep & ~L2_S_CACHE_MASK; 1759 1760 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1761 l2pte_valid(pte)) { 1762 if (PV_BEEN_EXECD(pv->pv_flags)) { 1763 #ifdef PMAP_CACHE_VIVT 1764 pmap_idcache_wbinv_range(pv->pv_pmap, 1765 pv->pv_va, PAGE_SIZE); 1766 #endif 1767 pmap_tlb_flushID_SE(pv->pv_pmap, 1768 pv->pv_va); 1769 } else 1770 if (PV_BEEN_REFD(pv->pv_flags)) { 1771 #ifdef PMAP_CACHE_VIVT 1772 pmap_dcache_wb_range(pv->pv_pmap, 1773 pv->pv_va, PAGE_SIZE, true, 1774 (pv->pv_flags & PVF_WRITE) == 0); 1775 #endif 1776 pmap_tlb_flushD_SE(pv->pv_pmap, 1777 pv->pv_va); 1778 } 1779 } 1780 1781 *ptep = pte; 1782 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1783 } 1784 cpu_cpwait(); 1785 } else 1786 if (entries > cacheable_entries) { 1787 /* 1788 * Turn cacheing back on for some pages. If it is a kernel 1789 * page, only do so if there are no other writable pages. 1790 */ 1791 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1792 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1793 (kpmap != pv->pv_pmap || other_writable))) 1794 continue; 1795 1796 pv->pv_flags &= ~PVF_NC; 1797 1798 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1799 KDASSERT(l2b != NULL); 1800 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1801 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1802 1803 if (l2pte_valid(pte)) { 1804 if (PV_BEEN_EXECD(pv->pv_flags)) { 1805 pmap_tlb_flushID_SE(pv->pv_pmap, 1806 pv->pv_va); 1807 } else 1808 if (PV_BEEN_REFD(pv->pv_flags)) { 1809 pmap_tlb_flushD_SE(pv->pv_pmap, 1810 pv->pv_va); 1811 } 1812 } 1813 1814 *ptep = pte; 1815 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1816 } 1817 } 1818 } 1819 #endif 1820 1821 #ifdef PMAP_CACHE_VIPT 1822 static void 1823 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1824 { 1825 struct pv_entry *pv; 1826 vaddr_t tst_mask; 1827 bool bad_alias; 1828 struct l2_bucket *l2b; 1829 pt_entry_t *ptep, pte, opte; 1830 const u_int 1831 rw_mappings = md->urw_mappings + md->krw_mappings, 1832 ro_mappings = md->uro_mappings + md->kro_mappings; 1833 1834 /* do we need to do anything? */ 1835 if (arm_cache_prefer_mask == 0) 1836 return; 1837 1838 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1839 md, pm, va)); 1840 1841 KASSERT(!va || pm); 1842 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1843 1844 /* Already a conflict? */ 1845 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1846 /* just an add, things are already non-cached */ 1847 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1848 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1849 bad_alias = false; 1850 if (va) { 1851 PMAPCOUNT(vac_color_none); 1852 bad_alias = true; 1853 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1854 goto fixup; 1855 } 1856 pv = SLIST_FIRST(&md->pvh_list); 1857 /* the list can't be empty because it would be cachable */ 1858 if (md->pvh_attrs & PVF_KMPAGE) { 1859 tst_mask = md->pvh_attrs; 1860 } else { 1861 KASSERT(pv); 1862 tst_mask = pv->pv_va; 1863 pv = SLIST_NEXT(pv, pv_link); 1864 } 1865 /* 1866 * Only check for a bad alias if we have writable mappings. 1867 */ 1868 tst_mask &= arm_cache_prefer_mask; 1869 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1870 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1871 /* if there's a bad alias, stop checking. */ 1872 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1873 bad_alias = true; 1874 } 1875 md->pvh_attrs |= PVF_WRITE; 1876 if (!bad_alias) 1877 md->pvh_attrs |= PVF_DIRTY; 1878 } else { 1879 /* 1880 * We have only read-only mappings. Let's see if there 1881 * are multiple colors in use or if we mapped a KMPAGE. 1882 * If the latter, we have a bad alias. If the former, 1883 * we need to remember that. 1884 */ 1885 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1886 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1887 if (md->pvh_attrs & PVF_KMPAGE) 1888 bad_alias = true; 1889 break; 1890 } 1891 } 1892 md->pvh_attrs &= ~PVF_WRITE; 1893 /* 1894 * No KMPAGE and we exited early, so we must have 1895 * multiple color mappings. 1896 */ 1897 if (!bad_alias && pv != NULL) 1898 md->pvh_attrs |= PVF_MULTCLR; 1899 } 1900 1901 /* If no conflicting colors, set everything back to cached */ 1902 if (!bad_alias) { 1903 #ifdef DEBUG 1904 if ((md->pvh_attrs & PVF_WRITE) 1905 || ro_mappings < 2) { 1906 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1907 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1908 } 1909 #endif 1910 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1911 md->pvh_attrs |= tst_mask | PVF_COLORED; 1912 /* 1913 * Restore DIRTY bit if page is modified 1914 */ 1915 if (md->pvh_attrs & PVF_DMOD) 1916 md->pvh_attrs |= PVF_DIRTY; 1917 PMAPCOUNT(vac_color_restore); 1918 } else { 1919 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1920 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1921 } 1922 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1923 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1924 } else if (!va) { 1925 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1926 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1927 || (md->pvh_attrs & PVF_DIRTY)); 1928 if (rw_mappings == 0) { 1929 md->pvh_attrs &= ~PVF_WRITE; 1930 if (ro_mappings == 1 1931 && (md->pvh_attrs & PVF_MULTCLR)) { 1932 /* 1933 * If this is the last readonly mapping 1934 * but it doesn't match the current color 1935 * for the page, change the current color 1936 * to match this last readonly mapping. 1937 */ 1938 pv = SLIST_FIRST(&md->pvh_list); 1939 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1940 & arm_cache_prefer_mask; 1941 if (tst_mask) { 1942 md->pvh_attrs ^= tst_mask; 1943 PMAPCOUNT(vac_color_change); 1944 } 1945 } 1946 } 1947 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1948 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1949 return; 1950 } else if (!pmap_is_page_colored_p(md)) { 1951 /* not colored so we just use its color */ 1952 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1953 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1954 PMAPCOUNT(vac_color_new); 1955 md->pvh_attrs &= PAGE_SIZE - 1; 1956 md->pvh_attrs |= PVF_COLORED 1957 | (va & arm_cache_prefer_mask) 1958 | (rw_mappings > 0 ? PVF_WRITE : 0); 1959 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1960 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1961 return; 1962 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1963 bad_alias = false; 1964 if (rw_mappings > 0) { 1965 /* 1966 * We now have writeable mappings and if we have 1967 * readonly mappings in more than once color, we have 1968 * an aliasing problem. Regardless mark the page as 1969 * writeable. 1970 */ 1971 if (md->pvh_attrs & PVF_MULTCLR) { 1972 if (ro_mappings < 2) { 1973 /* 1974 * If we only have less than two 1975 * read-only mappings, just flush the 1976 * non-primary colors from the cache. 1977 */ 1978 pmap_flush_page(md, pa, 1979 PMAP_FLUSH_SECONDARY); 1980 } else { 1981 bad_alias = true; 1982 } 1983 } 1984 md->pvh_attrs |= PVF_WRITE; 1985 } 1986 /* If no conflicting colors, set everything back to cached */ 1987 if (!bad_alias) { 1988 #ifdef DEBUG 1989 if (rw_mappings > 0 1990 || (md->pvh_attrs & PMAP_KMPAGE)) { 1991 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1992 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1993 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1994 } 1995 #endif 1996 if (SLIST_EMPTY(&md->pvh_list)) 1997 PMAPCOUNT(vac_color_reuse); 1998 else 1999 PMAPCOUNT(vac_color_ok); 2000 2001 /* matching color, just return */ 2002 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2003 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2004 return; 2005 } 2006 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2007 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2008 2009 /* color conflict. evict from cache. */ 2010 2011 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2012 md->pvh_attrs &= ~PVF_COLORED; 2013 md->pvh_attrs |= PVF_NC; 2014 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2015 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2016 PMAPCOUNT(vac_color_erase); 2017 } else if (rw_mappings == 0 2018 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2019 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2020 2021 /* 2022 * If the page has dirty cache lines, clean it. 2023 */ 2024 if (md->pvh_attrs & PVF_DIRTY) 2025 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2026 2027 /* 2028 * If this is the first remapping (we know that there are no 2029 * writeable mappings), then this is a simple color change. 2030 * Otherwise this is a seconary r/o mapping, which means 2031 * we don't have to do anything. 2032 */ 2033 if (ro_mappings == 1) { 2034 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2035 md->pvh_attrs &= PAGE_SIZE - 1; 2036 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2037 PMAPCOUNT(vac_color_change); 2038 } else { 2039 PMAPCOUNT(vac_color_blind); 2040 } 2041 md->pvh_attrs |= PVF_MULTCLR; 2042 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2043 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2044 return; 2045 } else { 2046 if (rw_mappings > 0) 2047 md->pvh_attrs |= PVF_WRITE; 2048 2049 /* color conflict. evict from cache. */ 2050 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2051 2052 /* the list can't be empty because this was a enter/modify */ 2053 pv = SLIST_FIRST(&md->pvh_list); 2054 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2055 KASSERT(pv); 2056 /* 2057 * If there's only one mapped page, change color to the 2058 * page's new color and return. Restore the DIRTY bit 2059 * that was erased by pmap_flush_page. 2060 */ 2061 if (SLIST_NEXT(pv, pv_link) == NULL) { 2062 md->pvh_attrs &= PAGE_SIZE - 1; 2063 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2064 if (md->pvh_attrs & PVF_DMOD) 2065 md->pvh_attrs |= PVF_DIRTY; 2066 PMAPCOUNT(vac_color_change); 2067 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2068 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2069 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2070 return; 2071 } 2072 } 2073 bad_alias = true; 2074 md->pvh_attrs &= ~PVF_COLORED; 2075 md->pvh_attrs |= PVF_NC; 2076 PMAPCOUNT(vac_color_erase); 2077 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2078 } 2079 2080 fixup: 2081 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2082 2083 /* 2084 * Turn cacheing on/off for all pages. 2085 */ 2086 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2087 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2088 KDASSERT(l2b != NULL); 2089 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2090 opte = *ptep; 2091 pte = opte & ~L2_S_CACHE_MASK; 2092 if (bad_alias) { 2093 pv->pv_flags |= PVF_NC; 2094 } else { 2095 pv->pv_flags &= ~PVF_NC; 2096 pte |= pte_l2_s_cache_mode; 2097 } 2098 2099 if (opte == pte) /* only update is there's a change */ 2100 continue; 2101 2102 if (l2pte_valid(pte)) { 2103 if (PV_BEEN_EXECD(pv->pv_flags)) { 2104 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2105 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2106 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2107 } 2108 } 2109 2110 *ptep = pte; 2111 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2112 } 2113 } 2114 #endif /* PMAP_CACHE_VIPT */ 2115 2116 2117 /* 2118 * Modify pte bits for all ptes corresponding to the given physical address. 2119 * We use `maskbits' rather than `clearbits' because we're always passing 2120 * constants and the latter would require an extra inversion at run-time. 2121 */ 2122 static void 2123 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2124 { 2125 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2126 struct l2_bucket *l2b; 2127 struct pv_entry *pv; 2128 pt_entry_t *ptep, npte, opte; 2129 pmap_t pm; 2130 vaddr_t va; 2131 u_int oflags; 2132 #ifdef PMAP_CACHE_VIPT 2133 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2134 bool need_syncicache = false; 2135 bool did_syncicache = false; 2136 bool need_vac_me_harder = false; 2137 #endif 2138 2139 NPDEBUG(PDB_BITS, 2140 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2141 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2142 2143 PMAP_HEAD_TO_MAP_LOCK(); 2144 simple_lock(&md->pvh_slock); 2145 2146 #ifdef PMAP_CACHE_VIPT 2147 /* 2148 * If we might want to sync the I-cache and we've modified it, 2149 * then we know we definitely need to sync or discard it. 2150 */ 2151 if (want_syncicache) 2152 need_syncicache = md->pvh_attrs & PVF_MOD; 2153 #endif 2154 /* 2155 * Clear saved attributes (modify, reference) 2156 */ 2157 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2158 2159 if (SLIST_EMPTY(&md->pvh_list)) { 2160 #ifdef PMAP_CACHE_VIPT 2161 if (need_syncicache) { 2162 /* 2163 * No one has it mapped, so just discard it. The next 2164 * exec remapping will cause it to be synced. 2165 */ 2166 md->pvh_attrs &= ~PVF_EXEC; 2167 PMAPCOUNT(exec_discarded_clearbit); 2168 } 2169 #endif 2170 simple_unlock(&md->pvh_slock); 2171 PMAP_HEAD_TO_MAP_UNLOCK(); 2172 return; 2173 } 2174 2175 /* 2176 * Loop over all current mappings setting/clearing as appropos 2177 */ 2178 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2179 va = pv->pv_va; 2180 pm = pv->pv_pmap; 2181 oflags = pv->pv_flags; 2182 /* 2183 * Kernel entries are unmanaged and as such not to be changed. 2184 */ 2185 if (oflags & PVF_KENTRY) 2186 continue; 2187 pv->pv_flags &= ~maskbits; 2188 2189 pmap_acquire_pmap_lock(pm); 2190 2191 l2b = pmap_get_l2_bucket(pm, va); 2192 KDASSERT(l2b != NULL); 2193 2194 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2195 npte = opte = *ptep; 2196 2197 NPDEBUG(PDB_BITS, 2198 printf( 2199 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2200 pv, pv->pv_pmap, pv->pv_va, oflags)); 2201 2202 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2203 #ifdef PMAP_CACHE_VIVT 2204 if ((pv->pv_flags & PVF_NC)) { 2205 /* 2206 * Entry is not cacheable: 2207 * 2208 * Don't turn caching on again if this is a 2209 * modified emulation. This would be 2210 * inconsitent with the settings created by 2211 * pmap_vac_me_harder(). Otherwise, it's safe 2212 * to re-enable cacheing. 2213 * 2214 * There's no need to call pmap_vac_me_harder() 2215 * here: all pages are losing their write 2216 * permission. 2217 */ 2218 if (maskbits & PVF_WRITE) { 2219 npte |= pte_l2_s_cache_mode; 2220 pv->pv_flags &= ~PVF_NC; 2221 } 2222 } else 2223 if (opte & L2_S_PROT_W) { 2224 /* 2225 * Entry is writable/cacheable: check if pmap 2226 * is current if it is flush it, otherwise it 2227 * won't be in the cache 2228 */ 2229 if (PV_BEEN_EXECD(oflags)) 2230 pmap_idcache_wbinv_range(pm, pv->pv_va, 2231 PAGE_SIZE); 2232 else 2233 if (PV_BEEN_REFD(oflags)) 2234 pmap_dcache_wb_range(pm, pv->pv_va, 2235 PAGE_SIZE, 2236 (maskbits & PVF_REF) != 0, false); 2237 } 2238 #endif 2239 2240 /* make the pte read only */ 2241 npte &= ~L2_S_PROT_W; 2242 2243 if (maskbits & oflags & PVF_WRITE) { 2244 /* 2245 * Keep alias accounting up to date 2246 */ 2247 if (pv->pv_pmap == pmap_kernel()) { 2248 md->krw_mappings--; 2249 md->kro_mappings++; 2250 } else { 2251 md->urw_mappings--; 2252 md->uro_mappings++; 2253 } 2254 #ifdef PMAP_CACHE_VIPT 2255 if (md->urw_mappings + md->krw_mappings == 0) 2256 md->pvh_attrs &= ~PVF_WRITE; 2257 if (want_syncicache) 2258 need_syncicache = true; 2259 need_vac_me_harder = true; 2260 #endif 2261 } 2262 } 2263 2264 if (maskbits & PVF_REF) { 2265 if ((pv->pv_flags & PVF_NC) == 0 && 2266 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2267 l2pte_valid(npte)) { 2268 #ifdef PMAP_CACHE_VIVT 2269 /* 2270 * Check npte here; we may have already 2271 * done the wbinv above, and the validity 2272 * of the PTE is the same for opte and 2273 * npte. 2274 */ 2275 /* XXXJRT need idcache_inv_range */ 2276 if (PV_BEEN_EXECD(oflags)) 2277 pmap_idcache_wbinv_range(pm, 2278 pv->pv_va, PAGE_SIZE); 2279 else 2280 if (PV_BEEN_REFD(oflags)) 2281 pmap_dcache_wb_range(pm, 2282 pv->pv_va, PAGE_SIZE, 2283 true, true); 2284 #endif 2285 } 2286 2287 /* 2288 * Make the PTE invalid so that we will take a 2289 * page fault the next time the mapping is 2290 * referenced. 2291 */ 2292 npte &= ~L2_TYPE_MASK; 2293 npte |= L2_TYPE_INV; 2294 } 2295 2296 if (npte != opte) { 2297 *ptep = npte; 2298 PTE_SYNC(ptep); 2299 /* Flush the TLB entry if a current pmap. */ 2300 if (PV_BEEN_EXECD(oflags)) 2301 pmap_tlb_flushID_SE(pm, pv->pv_va); 2302 else 2303 if (PV_BEEN_REFD(oflags)) 2304 pmap_tlb_flushD_SE(pm, pv->pv_va); 2305 } 2306 2307 pmap_release_pmap_lock(pm); 2308 2309 NPDEBUG(PDB_BITS, 2310 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2311 pm, va, opte, npte)); 2312 } 2313 2314 #ifdef PMAP_CACHE_VIPT 2315 /* 2316 * If we need to sync the I-cache and we haven't done it yet, do it. 2317 */ 2318 if (need_syncicache && !did_syncicache) { 2319 pmap_syncicache_page(md, VM_PAGE_TO_PHYS(pg)); 2320 PMAPCOUNT(exec_synced_clearbit); 2321 } 2322 /* 2323 * If we are changing this to read-only, we need to call vac_me_harder 2324 * so we can change all the read-only pages to cacheable. We pretend 2325 * this as a page deletion. 2326 */ 2327 if (need_vac_me_harder) { 2328 if (md->pvh_attrs & PVF_NC) 2329 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), NULL, 0); 2330 } 2331 #endif 2332 2333 simple_unlock(&md->pvh_slock); 2334 PMAP_HEAD_TO_MAP_UNLOCK(); 2335 } 2336 2337 /* 2338 * pmap_clean_page() 2339 * 2340 * This is a local function used to work out the best strategy to clean 2341 * a single page referenced by its entry in the PV table. It's used by 2342 * pmap_copy_page, pmap_zero page and maybe some others later on. 2343 * 2344 * Its policy is effectively: 2345 * o If there are no mappings, we don't bother doing anything with the cache. 2346 * o If there is one mapping, we clean just that page. 2347 * o If there are multiple mappings, we clean the entire cache. 2348 * 2349 * So that some functions can be further optimised, it returns 0 if it didn't 2350 * clean the entire cache, or 1 if it did. 2351 * 2352 * XXX One bug in this routine is that if the pv_entry has a single page 2353 * mapped at 0x00000000 a whole cache clean will be performed rather than 2354 * just the 1 page. Since this should not occur in everyday use and if it does 2355 * it will just result in not the most efficient clean for the page. 2356 */ 2357 #ifdef PMAP_CACHE_VIVT 2358 static int 2359 pmap_clean_page(struct pv_entry *pv, bool is_src) 2360 { 2361 pmap_t pm_to_clean = NULL; 2362 struct pv_entry *npv; 2363 u_int cache_needs_cleaning = 0; 2364 u_int flags = 0; 2365 vaddr_t page_to_clean = 0; 2366 2367 if (pv == NULL) { 2368 /* nothing mapped in so nothing to flush */ 2369 return (0); 2370 } 2371 2372 /* 2373 * Since we flush the cache each time we change to a different 2374 * user vmspace, we only need to flush the page if it is in the 2375 * current pmap. 2376 */ 2377 2378 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2379 if (pmap_is_current(npv->pv_pmap)) { 2380 flags |= npv->pv_flags; 2381 /* 2382 * The page is mapped non-cacheable in 2383 * this map. No need to flush the cache. 2384 */ 2385 if (npv->pv_flags & PVF_NC) { 2386 #ifdef DIAGNOSTIC 2387 if (cache_needs_cleaning) 2388 panic("pmap_clean_page: " 2389 "cache inconsistency"); 2390 #endif 2391 break; 2392 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2393 continue; 2394 if (cache_needs_cleaning) { 2395 page_to_clean = 0; 2396 break; 2397 } else { 2398 page_to_clean = npv->pv_va; 2399 pm_to_clean = npv->pv_pmap; 2400 } 2401 cache_needs_cleaning = 1; 2402 } 2403 } 2404 2405 if (page_to_clean) { 2406 if (PV_BEEN_EXECD(flags)) 2407 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2408 PAGE_SIZE); 2409 else 2410 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2411 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2412 } else if (cache_needs_cleaning) { 2413 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2414 2415 if (PV_BEEN_EXECD(flags)) 2416 pmap_idcache_wbinv_all(pm); 2417 else 2418 pmap_dcache_wbinv_all(pm); 2419 return (1); 2420 } 2421 return (0); 2422 } 2423 #endif 2424 2425 #ifdef PMAP_CACHE_VIPT 2426 /* 2427 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2428 * right cache alias to make sure we flush the right stuff. 2429 */ 2430 void 2431 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2432 { 2433 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2434 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2435 2436 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2437 md, md->pvh_attrs)); 2438 /* 2439 * No need to clean the page if it's non-cached. 2440 */ 2441 if (md->pvh_attrs & PVF_NC) 2442 return; 2443 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2444 2445 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2446 /* 2447 * Set up a PTE with the right coloring to flush existing cache lines. 2448 */ 2449 *ptep = L2_S_PROTO | 2450 pa 2451 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2452 | pte_l2_s_cache_mode; 2453 PTE_SYNC(ptep); 2454 2455 /* 2456 * Flush it. 2457 */ 2458 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2459 /* 2460 * Unmap the page. 2461 */ 2462 *ptep = 0; 2463 PTE_SYNC(ptep); 2464 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2465 2466 md->pvh_attrs |= PVF_EXEC; 2467 PMAPCOUNT(exec_synced); 2468 } 2469 2470 void 2471 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2472 { 2473 vsize_t va_offset, end_va; 2474 void (*cf)(vaddr_t, vsize_t); 2475 2476 if (arm_cache_prefer_mask == 0) 2477 return; 2478 2479 switch (flush) { 2480 case PMAP_FLUSH_PRIMARY: 2481 if (md->pvh_attrs & PVF_MULTCLR) { 2482 va_offset = 0; 2483 end_va = arm_cache_prefer_mask; 2484 md->pvh_attrs &= ~PVF_MULTCLR; 2485 PMAPCOUNT(vac_flush_lots); 2486 } else { 2487 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2488 end_va = va_offset; 2489 PMAPCOUNT(vac_flush_one); 2490 } 2491 /* 2492 * Mark that the page is no longer dirty. 2493 */ 2494 md->pvh_attrs &= ~PVF_DIRTY; 2495 cf = cpufuncs.cf_idcache_wbinv_range; 2496 break; 2497 case PMAP_FLUSH_SECONDARY: 2498 va_offset = 0; 2499 end_va = arm_cache_prefer_mask; 2500 cf = cpufuncs.cf_idcache_wbinv_range; 2501 md->pvh_attrs &= ~PVF_MULTCLR; 2502 PMAPCOUNT(vac_flush_lots); 2503 break; 2504 case PMAP_CLEAN_PRIMARY: 2505 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2506 end_va = va_offset; 2507 cf = cpufuncs.cf_dcache_wb_range; 2508 /* 2509 * Mark that the page is no longer dirty. 2510 */ 2511 if ((md->pvh_attrs & PVF_DMOD) == 0) 2512 md->pvh_attrs &= ~PVF_DIRTY; 2513 PMAPCOUNT(vac_clean_one); 2514 break; 2515 default: 2516 return; 2517 } 2518 2519 KASSERT(!(md->pvh_attrs & PVF_NC)); 2520 2521 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2522 md, md->pvh_attrs)); 2523 2524 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2525 const size_t pte_offset = va_offset >> PGSHIFT; 2526 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2527 const pt_entry_t oldpte = *ptep; 2528 2529 if (flush == PMAP_FLUSH_SECONDARY 2530 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2531 continue; 2532 2533 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2534 /* 2535 * Set up a PTE with the right coloring to flush 2536 * existing cache entries. 2537 */ 2538 *ptep = L2_S_PROTO 2539 | pa 2540 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2541 | pte_l2_s_cache_mode; 2542 PTE_SYNC(ptep); 2543 2544 /* 2545 * Flush it. 2546 */ 2547 (*cf)(cdstp + va_offset, PAGE_SIZE); 2548 2549 /* 2550 * Restore the page table entry since we might have interrupted 2551 * pmap_zero_page or pmap_copy_page which was already using 2552 * this pte. 2553 */ 2554 *ptep = oldpte; 2555 PTE_SYNC(ptep); 2556 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2557 } 2558 } 2559 #endif /* PMAP_CACHE_VIPT */ 2560 2561 /* 2562 * Routine: pmap_page_remove 2563 * Function: 2564 * Removes this physical page from 2565 * all physical maps in which it resides. 2566 * Reflects back modify bits to the pager. 2567 */ 2568 static void 2569 pmap_page_remove(struct vm_page *pg) 2570 { 2571 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2572 struct l2_bucket *l2b; 2573 struct pv_entry *pv, *npv, **pvp; 2574 pmap_t pm; 2575 pt_entry_t *ptep; 2576 bool flush; 2577 u_int flags; 2578 2579 NPDEBUG(PDB_FOLLOW, 2580 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2581 VM_PAGE_TO_PHYS(pg))); 2582 2583 PMAP_HEAD_TO_MAP_LOCK(); 2584 simple_lock(&md->pvh_slock); 2585 2586 pv = SLIST_FIRST(&md->pvh_list); 2587 if (pv == NULL) { 2588 #ifdef PMAP_CACHE_VIPT 2589 /* 2590 * We *know* the page contents are about to be replaced. 2591 * Discard the exec contents 2592 */ 2593 if (PV_IS_EXEC_P(md->pvh_attrs)) 2594 PMAPCOUNT(exec_discarded_page_protect); 2595 md->pvh_attrs &= ~PVF_EXEC; 2596 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2597 #endif 2598 simple_unlock(&md->pvh_slock); 2599 PMAP_HEAD_TO_MAP_UNLOCK(); 2600 return; 2601 } 2602 #ifdef PMAP_CACHE_VIPT 2603 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2604 #endif 2605 2606 /* 2607 * Clear alias counts 2608 */ 2609 #ifdef PMAP_CACHE_VIVT 2610 md->k_mappings = 0; 2611 #endif 2612 md->urw_mappings = md->uro_mappings = 0; 2613 2614 flush = false; 2615 flags = 0; 2616 2617 #ifdef PMAP_CACHE_VIVT 2618 pmap_clean_page(pv, false); 2619 #endif 2620 2621 pvp = &SLIST_FIRST(&md->pvh_list); 2622 while (pv) { 2623 pm = pv->pv_pmap; 2624 npv = SLIST_NEXT(pv, pv_link); 2625 if (flush == false && pmap_is_current(pm)) 2626 flush = true; 2627 2628 if (pm == pmap_kernel()) { 2629 #ifdef PMAP_CACHE_VIPT 2630 /* 2631 * If this was unmanaged mapping, it must be preserved. 2632 * Move it back on the list and advance the end-of-list 2633 * pointer. 2634 */ 2635 if (pv->pv_flags & PVF_KENTRY) { 2636 *pvp = pv; 2637 pvp = &SLIST_NEXT(pv, pv_link); 2638 pv = npv; 2639 continue; 2640 } 2641 if (pv->pv_flags & PVF_WRITE) 2642 md->krw_mappings--; 2643 else 2644 md->kro_mappings--; 2645 #endif 2646 PMAPCOUNT(kernel_unmappings); 2647 } 2648 PMAPCOUNT(unmappings); 2649 2650 pmap_acquire_pmap_lock(pm); 2651 2652 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2653 KDASSERT(l2b != NULL); 2654 2655 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2656 2657 /* 2658 * Update statistics 2659 */ 2660 --pm->pm_stats.resident_count; 2661 2662 /* Wired bit */ 2663 if (pv->pv_flags & PVF_WIRED) 2664 --pm->pm_stats.wired_count; 2665 2666 flags |= pv->pv_flags; 2667 2668 /* 2669 * Invalidate the PTEs. 2670 */ 2671 *ptep = 0; 2672 PTE_SYNC_CURRENT(pm, ptep); 2673 pmap_free_l2_bucket(pm, l2b, 1); 2674 2675 pool_put(&pmap_pv_pool, pv); 2676 pv = npv; 2677 /* 2678 * if we reach the end of the list and there are still 2679 * mappings, they might be able to be cached now. 2680 */ 2681 if (pv == NULL) { 2682 *pvp = NULL; 2683 if (!SLIST_EMPTY(&md->pvh_list)) 2684 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pm, 0); 2685 } 2686 pmap_release_pmap_lock(pm); 2687 } 2688 #ifdef PMAP_CACHE_VIPT 2689 /* 2690 * Its EXEC cache is now gone. 2691 */ 2692 if (PV_IS_EXEC_P(md->pvh_attrs)) 2693 PMAPCOUNT(exec_discarded_page_protect); 2694 md->pvh_attrs &= ~PVF_EXEC; 2695 KASSERT(md->urw_mappings == 0); 2696 KASSERT(md->uro_mappings == 0); 2697 if (md->krw_mappings == 0) 2698 md->pvh_attrs &= ~PVF_WRITE; 2699 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2700 #endif 2701 simple_unlock(&md->pvh_slock); 2702 PMAP_HEAD_TO_MAP_UNLOCK(); 2703 2704 if (flush) { 2705 /* 2706 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2707 * would need a subsequent call to pmap_update() to ensure 2708 * curpm->pm_cstate.cs_all is reset. Our callers are not 2709 * required to do that (see pmap(9)), so we can't modify 2710 * the current pmap's state. 2711 */ 2712 if (PV_BEEN_EXECD(flags)) 2713 cpu_tlb_flushID(); 2714 else 2715 cpu_tlb_flushD(); 2716 } 2717 cpu_cpwait(); 2718 } 2719 2720 /* 2721 * pmap_t pmap_create(void) 2722 * 2723 * Create a new pmap structure from scratch. 2724 */ 2725 pmap_t 2726 pmap_create(void) 2727 { 2728 pmap_t pm; 2729 2730 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2731 2732 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2733 pm->pm_stats.wired_count = 0; 2734 pm->pm_stats.resident_count = 1; 2735 pm->pm_cstate.cs_all = 0; 2736 pmap_alloc_l1(pm); 2737 2738 /* 2739 * Note: The pool cache ensures that the pm_l2[] array is already 2740 * initialised to zero. 2741 */ 2742 2743 pmap_pinit(pm); 2744 2745 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2746 2747 return (pm); 2748 } 2749 2750 /* 2751 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2752 * u_int flags) 2753 * 2754 * Insert the given physical page (p) at 2755 * the specified virtual address (v) in the 2756 * target physical map with the protection requested. 2757 * 2758 * NB: This is the only routine which MAY NOT lazy-evaluate 2759 * or lose information. That is, this routine must actually 2760 * insert this page into the given map NOW. 2761 */ 2762 int 2763 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2764 { 2765 struct l2_bucket *l2b; 2766 struct vm_page *pg, *opg; 2767 struct pv_entry *pv; 2768 pt_entry_t *ptep, npte, opte; 2769 u_int nflags; 2770 u_int oflags; 2771 2772 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2773 2774 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2775 KDASSERT(((va | pa) & PGOFSET) == 0); 2776 2777 /* 2778 * Get a pointer to the page. Later on in this function, we 2779 * test for a managed page by checking pg != NULL. 2780 */ 2781 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2782 2783 nflags = 0; 2784 if (prot & VM_PROT_WRITE) 2785 nflags |= PVF_WRITE; 2786 if (prot & VM_PROT_EXECUTE) 2787 nflags |= PVF_EXEC; 2788 if (flags & PMAP_WIRED) 2789 nflags |= PVF_WIRED; 2790 2791 PMAP_MAP_TO_HEAD_LOCK(); 2792 pmap_acquire_pmap_lock(pm); 2793 2794 /* 2795 * Fetch the L2 bucket which maps this page, allocating one if 2796 * necessary for user pmaps. 2797 */ 2798 if (pm == pmap_kernel()) 2799 l2b = pmap_get_l2_bucket(pm, va); 2800 else 2801 l2b = pmap_alloc_l2_bucket(pm, va); 2802 if (l2b == NULL) { 2803 if (flags & PMAP_CANFAIL) { 2804 pmap_release_pmap_lock(pm); 2805 PMAP_MAP_TO_HEAD_UNLOCK(); 2806 return (ENOMEM); 2807 } 2808 panic("pmap_enter: failed to allocate L2 bucket"); 2809 } 2810 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2811 opte = *ptep; 2812 npte = pa; 2813 oflags = 0; 2814 2815 if (opte) { 2816 /* 2817 * There is already a mapping at this address. 2818 * If the physical address is different, lookup the 2819 * vm_page. 2820 */ 2821 if (l2pte_pa(opte) != pa) 2822 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2823 else 2824 opg = pg; 2825 } else 2826 opg = NULL; 2827 2828 if (pg) { 2829 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2830 2831 /* 2832 * This is to be a managed mapping. 2833 */ 2834 if ((flags & VM_PROT_ALL) || 2835 (md->pvh_attrs & PVF_REF)) { 2836 /* 2837 * - The access type indicates that we don't need 2838 * to do referenced emulation. 2839 * OR 2840 * - The physical page has already been referenced 2841 * so no need to re-do referenced emulation here. 2842 */ 2843 npte |= L2_S_PROTO; 2844 2845 nflags |= PVF_REF; 2846 2847 if ((prot & VM_PROT_WRITE) != 0 && 2848 ((flags & VM_PROT_WRITE) != 0 || 2849 (md->pvh_attrs & PVF_MOD) != 0)) { 2850 /* 2851 * This is a writable mapping, and the 2852 * page's mod state indicates it has 2853 * already been modified. Make it 2854 * writable from the outset. 2855 */ 2856 npte |= L2_S_PROT_W; 2857 nflags |= PVF_MOD; 2858 } 2859 } else { 2860 /* 2861 * Need to do page referenced emulation. 2862 */ 2863 npte |= L2_TYPE_INV; 2864 } 2865 2866 npte |= pte_l2_s_cache_mode; 2867 2868 if (pg == opg) { 2869 /* 2870 * We're changing the attrs of an existing mapping. 2871 */ 2872 simple_lock(&md->pvh_slock); 2873 oflags = pmap_modify_pv(md, pa, pm, va, 2874 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2875 PVF_MOD | PVF_REF, nflags); 2876 simple_unlock(&md->pvh_slock); 2877 2878 #ifdef PMAP_CACHE_VIVT 2879 /* 2880 * We may need to flush the cache if we're 2881 * doing rw-ro... 2882 */ 2883 if (pm->pm_cstate.cs_cache_d && 2884 (oflags & PVF_NC) == 0 && 2885 (opte & L2_S_PROT_W) != 0 && 2886 (prot & VM_PROT_WRITE) == 0) 2887 cpu_dcache_wb_range(va, PAGE_SIZE); 2888 #endif 2889 } else { 2890 /* 2891 * New mapping, or changing the backing page 2892 * of an existing mapping. 2893 */ 2894 if (opg) { 2895 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2896 paddr_t opa; 2897 2898 opa = VM_PAGE_TO_PHYS(opg); 2899 2900 /* 2901 * Replacing an existing mapping with a new one. 2902 * It is part of our managed memory so we 2903 * must remove it from the PV list 2904 */ 2905 simple_lock(&omd->pvh_slock); 2906 pv = pmap_remove_pv(omd, opa, pm, va); 2907 pmap_vac_me_harder(omd, opa, pm, 0); 2908 simple_unlock(&omd->pvh_slock); 2909 oflags = pv->pv_flags; 2910 2911 #ifdef PMAP_CACHE_VIVT 2912 /* 2913 * If the old mapping was valid (ref/mod 2914 * emulation creates 'invalid' mappings 2915 * initially) then make sure to frob 2916 * the cache. 2917 */ 2918 if ((oflags & PVF_NC) == 0 && 2919 l2pte_valid(opte)) { 2920 if (PV_BEEN_EXECD(oflags)) { 2921 pmap_idcache_wbinv_range(pm, va, 2922 PAGE_SIZE); 2923 } else 2924 if (PV_BEEN_REFD(oflags)) { 2925 pmap_dcache_wb_range(pm, va, 2926 PAGE_SIZE, true, 2927 (oflags & PVF_WRITE) == 0); 2928 } 2929 } 2930 #endif 2931 } else 2932 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2933 if ((flags & PMAP_CANFAIL) == 0) 2934 panic("pmap_enter: no pv entries"); 2935 2936 if (pm != pmap_kernel()) 2937 pmap_free_l2_bucket(pm, l2b, 0); 2938 pmap_release_pmap_lock(pm); 2939 PMAP_MAP_TO_HEAD_UNLOCK(); 2940 NPDEBUG(PDB_ENTER, 2941 printf("pmap_enter: ENOMEM\n")); 2942 return (ENOMEM); 2943 } 2944 2945 pmap_enter_pv(md, VM_PAGE_TO_PHYS(pg), pv, pm, va, nflags); 2946 } 2947 } else { 2948 /* 2949 * We're mapping an unmanaged page. 2950 * These are always readable, and possibly writable, from 2951 * the get go as we don't need to track ref/mod status. 2952 */ 2953 npte |= L2_S_PROTO; 2954 if (prot & VM_PROT_WRITE) 2955 npte |= L2_S_PROT_W; 2956 2957 /* 2958 * Make sure the vector table is mapped cacheable 2959 */ 2960 if (pm != pmap_kernel() && va == vector_page) 2961 npte |= pte_l2_s_cache_mode; 2962 2963 if (opg) { 2964 /* 2965 * Looks like there's an existing 'managed' mapping 2966 * at this address. 2967 */ 2968 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2969 simple_lock(&omd->pvh_slock); 2970 pv = pmap_remove_pv(omd, VM_PAGE_TO_PHYS(opg), pm, va); 2971 pmap_vac_me_harder(omd, VM_PAGE_TO_PHYS(opg), pm, 0); 2972 simple_unlock(&omd->pvh_slock); 2973 oflags = pv->pv_flags; 2974 2975 #ifdef PMAP_CACHE_VIVT 2976 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2977 if (PV_BEEN_EXECD(oflags)) 2978 pmap_idcache_wbinv_range(pm, va, 2979 PAGE_SIZE); 2980 else 2981 if (PV_BEEN_REFD(oflags)) 2982 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2983 true, (oflags & PVF_WRITE) == 0); 2984 } 2985 #endif 2986 pool_put(&pmap_pv_pool, pv); 2987 } 2988 } 2989 2990 /* 2991 * Make sure userland mappings get the right permissions 2992 */ 2993 if (pm != pmap_kernel() && va != vector_page) 2994 npte |= L2_S_PROT_U; 2995 2996 /* 2997 * Keep the stats up to date 2998 */ 2999 if (opte == 0) { 3000 l2b->l2b_occupancy++; 3001 pm->pm_stats.resident_count++; 3002 } 3003 3004 NPDEBUG(PDB_ENTER, 3005 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3006 3007 /* 3008 * If this is just a wiring change, the two PTEs will be 3009 * identical, so there's no need to update the page table. 3010 */ 3011 if (npte != opte) { 3012 bool is_cached = pmap_is_cached(pm); 3013 3014 *ptep = npte; 3015 if (is_cached) { 3016 /* 3017 * We only need to frob the cache/tlb if this pmap 3018 * is current 3019 */ 3020 PTE_SYNC(ptep); 3021 if (va != vector_page && l2pte_valid(npte)) { 3022 /* 3023 * This mapping is likely to be accessed as 3024 * soon as we return to userland. Fix up the 3025 * L1 entry to avoid taking another 3026 * page/domain fault. 3027 */ 3028 pd_entry_t *pl1pd, l1pd; 3029 3030 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3031 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3032 L1_C_PROTO; 3033 if (*pl1pd != l1pd) { 3034 *pl1pd = l1pd; 3035 PTE_SYNC(pl1pd); 3036 } 3037 } 3038 } 3039 3040 if (PV_BEEN_EXECD(oflags)) 3041 pmap_tlb_flushID_SE(pm, va); 3042 else 3043 if (PV_BEEN_REFD(oflags)) 3044 pmap_tlb_flushD_SE(pm, va); 3045 3046 NPDEBUG(PDB_ENTER, 3047 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3048 is_cached, pm->pm_cstate.cs_all)); 3049 3050 if (pg != NULL) { 3051 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3052 simple_lock(&md->pvh_slock); 3053 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pm, va); 3054 simple_unlock(&md->pvh_slock); 3055 } 3056 } 3057 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3058 if (pg) { 3059 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3060 simple_lock(&md->pvh_slock); 3061 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3062 KASSERT(((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0)); 3063 simple_unlock(&md->pvh_slock); 3064 } 3065 #endif 3066 3067 pmap_release_pmap_lock(pm); 3068 PMAP_MAP_TO_HEAD_UNLOCK(); 3069 3070 return (0); 3071 } 3072 3073 /* 3074 * pmap_remove() 3075 * 3076 * pmap_remove is responsible for nuking a number of mappings for a range 3077 * of virtual address space in the current pmap. To do this efficiently 3078 * is interesting, because in a number of cases a wide virtual address 3079 * range may be supplied that contains few actual mappings. So, the 3080 * optimisations are: 3081 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3082 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3083 * maybe do just a partial cache clean. This path of execution is 3084 * complicated by the fact that the cache must be flushed _before_ 3085 * the PTE is nuked, being a VAC :-) 3086 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3087 * all invalidations until pmap_update(), since pmap_remove_all() has 3088 * already flushed the cache. 3089 * 4. Maybe later fast-case a single page, but I don't think this is 3090 * going to make _that_ much difference overall. 3091 */ 3092 3093 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3094 3095 void 3096 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3097 { 3098 struct l2_bucket *l2b; 3099 vaddr_t next_bucket; 3100 pt_entry_t *ptep; 3101 u_int cleanlist_idx, total, cnt; 3102 struct { 3103 vaddr_t va; 3104 pt_entry_t *ptep; 3105 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3106 u_int mappings, is_exec, is_refd; 3107 3108 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3109 "eva=%08lx\n", pm, sva, eva)); 3110 3111 /* 3112 * we lock in the pmap => pv_head direction 3113 */ 3114 PMAP_MAP_TO_HEAD_LOCK(); 3115 pmap_acquire_pmap_lock(pm); 3116 3117 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3118 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3119 if (pm->pm_cstate.cs_tlb == 0) 3120 pm->pm_remove_all = true; 3121 } else 3122 cleanlist_idx = 0; 3123 3124 total = 0; 3125 3126 while (sva < eva) { 3127 /* 3128 * Do one L2 bucket's worth at a time. 3129 */ 3130 next_bucket = L2_NEXT_BUCKET(sva); 3131 if (next_bucket > eva) 3132 next_bucket = eva; 3133 3134 l2b = pmap_get_l2_bucket(pm, sva); 3135 if (l2b == NULL) { 3136 sva = next_bucket; 3137 continue; 3138 } 3139 3140 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3141 3142 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3143 struct vm_page *pg; 3144 pt_entry_t pte; 3145 paddr_t pa; 3146 3147 pte = *ptep; 3148 3149 if (pte == 0) { 3150 /* Nothing here, move along */ 3151 continue; 3152 } 3153 3154 pa = l2pte_pa(pte); 3155 is_exec = 0; 3156 is_refd = 1; 3157 3158 /* 3159 * Update flags. In a number of circumstances, 3160 * we could cluster a lot of these and do a 3161 * number of sequential pages in one go. 3162 */ 3163 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3164 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3165 struct pv_entry *pv; 3166 simple_lock(&md->pvh_slock); 3167 pv = pmap_remove_pv(md, VM_PAGE_TO_PHYS(pg), pm, sva); 3168 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pm, 0); 3169 simple_unlock(&md->pvh_slock); 3170 if (pv != NULL) { 3171 if (pm->pm_remove_all == false) { 3172 is_exec = 3173 PV_BEEN_EXECD(pv->pv_flags); 3174 is_refd = 3175 PV_BEEN_REFD(pv->pv_flags); 3176 } 3177 pool_put(&pmap_pv_pool, pv); 3178 } 3179 } 3180 mappings++; 3181 3182 if (!l2pte_valid(pte)) { 3183 /* 3184 * Ref/Mod emulation is still active for this 3185 * mapping, therefore it is has not yet been 3186 * accessed. No need to frob the cache/tlb. 3187 */ 3188 *ptep = 0; 3189 PTE_SYNC_CURRENT(pm, ptep); 3190 continue; 3191 } 3192 3193 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3194 /* Add to the clean list. */ 3195 cleanlist[cleanlist_idx].ptep = ptep; 3196 cleanlist[cleanlist_idx].va = 3197 sva | (is_exec & 1); 3198 cleanlist_idx++; 3199 } else 3200 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3201 /* Nuke everything if needed. */ 3202 #ifdef PMAP_CACHE_VIVT 3203 pmap_idcache_wbinv_all(pm); 3204 #endif 3205 pmap_tlb_flushID(pm); 3206 3207 /* 3208 * Roll back the previous PTE list, 3209 * and zero out the current PTE. 3210 */ 3211 for (cnt = 0; 3212 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3213 *cleanlist[cnt].ptep = 0; 3214 PTE_SYNC(cleanlist[cnt].ptep); 3215 } 3216 *ptep = 0; 3217 PTE_SYNC(ptep); 3218 cleanlist_idx++; 3219 pm->pm_remove_all = true; 3220 } else { 3221 *ptep = 0; 3222 PTE_SYNC(ptep); 3223 if (pm->pm_remove_all == false) { 3224 if (is_exec) 3225 pmap_tlb_flushID_SE(pm, sva); 3226 else 3227 if (is_refd) 3228 pmap_tlb_flushD_SE(pm, sva); 3229 } 3230 } 3231 } 3232 3233 /* 3234 * Deal with any left overs 3235 */ 3236 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3237 total += cleanlist_idx; 3238 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3239 if (pm->pm_cstate.cs_all != 0) { 3240 vaddr_t clva = cleanlist[cnt].va & ~1; 3241 if (cleanlist[cnt].va & 1) { 3242 #ifdef PMAP_CACHE_VIVT 3243 pmap_idcache_wbinv_range(pm, 3244 clva, PAGE_SIZE); 3245 #endif 3246 pmap_tlb_flushID_SE(pm, clva); 3247 } else { 3248 #ifdef PMAP_CACHE_VIVT 3249 pmap_dcache_wb_range(pm, 3250 clva, PAGE_SIZE, true, 3251 false); 3252 #endif 3253 pmap_tlb_flushD_SE(pm, clva); 3254 } 3255 } 3256 *cleanlist[cnt].ptep = 0; 3257 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3258 } 3259 3260 /* 3261 * If it looks like we're removing a whole bunch 3262 * of mappings, it's faster to just write-back 3263 * the whole cache now and defer TLB flushes until 3264 * pmap_update() is called. 3265 */ 3266 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3267 cleanlist_idx = 0; 3268 else { 3269 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3270 #ifdef PMAP_CACHE_VIVT 3271 pmap_idcache_wbinv_all(pm); 3272 #endif 3273 pm->pm_remove_all = true; 3274 } 3275 } 3276 3277 pmap_free_l2_bucket(pm, l2b, mappings); 3278 pm->pm_stats.resident_count -= mappings; 3279 } 3280 3281 pmap_release_pmap_lock(pm); 3282 PMAP_MAP_TO_HEAD_UNLOCK(); 3283 } 3284 3285 #ifdef PMAP_CACHE_VIPT 3286 static struct pv_entry * 3287 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3288 { 3289 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3290 struct pv_entry *pv; 3291 3292 simple_lock(&md->pvh_slock); 3293 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3294 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3295 3296 pv = pmap_remove_pv(md, VM_PAGE_TO_PHYS(pg), pmap_kernel(), va); 3297 KASSERT(pv); 3298 KASSERT(pv->pv_flags & PVF_KENTRY); 3299 3300 /* 3301 * If we are removing a writeable mapping to a cached exec page, 3302 * if it's the last mapping then clear it execness other sync 3303 * the page to the icache. 3304 */ 3305 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3306 && (pv->pv_flags & PVF_WRITE) != 0) { 3307 if (SLIST_EMPTY(&md->pvh_list)) { 3308 md->pvh_attrs &= ~PVF_EXEC; 3309 PMAPCOUNT(exec_discarded_kremove); 3310 } else { 3311 pmap_syncicache_page(md, VM_PAGE_TO_PHYS(pg)); 3312 PMAPCOUNT(exec_synced_kremove); 3313 } 3314 } 3315 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pmap_kernel(), 0); 3316 simple_unlock(&md->pvh_slock); 3317 3318 return pv; 3319 } 3320 #endif /* PMAP_CACHE_VIPT */ 3321 3322 /* 3323 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3324 * 3325 * We assume there is already sufficient KVM space available 3326 * to do this, as we can't allocate L2 descriptor tables/metadata 3327 * from here. 3328 */ 3329 void 3330 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3331 { 3332 struct l2_bucket *l2b; 3333 pt_entry_t *ptep, opte; 3334 #ifdef PMAP_CACHE_VIVT 3335 struct vm_page *pg = (prot & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3336 #endif 3337 #ifdef PMAP_CACHE_VIPT 3338 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3339 struct vm_page *opg; 3340 struct pv_entry *pv = NULL; 3341 #endif 3342 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3343 3344 NPDEBUG(PDB_KENTER, 3345 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3346 va, pa, prot)); 3347 3348 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3349 KDASSERT(l2b != NULL); 3350 3351 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3352 opte = *ptep; 3353 3354 if (opte == 0) { 3355 PMAPCOUNT(kenter_mappings); 3356 l2b->l2b_occupancy++; 3357 } else { 3358 PMAPCOUNT(kenter_remappings); 3359 #ifdef PMAP_CACHE_VIPT 3360 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3361 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3362 if (opg) { 3363 KASSERT(opg != pg); 3364 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3365 KASSERT((prot & PMAP_KMPAGE) == 0); 3366 simple_lock(&omd->pvh_slock); 3367 pv = pmap_kremove_pg(opg, va); 3368 simple_unlock(&omd->pvh_slock); 3369 } 3370 #endif 3371 if (l2pte_valid(opte)) { 3372 #ifdef PMAP_CACHE_VIVT 3373 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3374 #endif 3375 cpu_tlb_flushD_SE(va); 3376 cpu_cpwait(); 3377 } 3378 } 3379 3380 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3381 pte_l2_s_cache_mode; 3382 PTE_SYNC(ptep); 3383 3384 if (pg) { 3385 if (prot & PMAP_KMPAGE) { 3386 simple_lock(&md->pvh_slock); 3387 KASSERT(md->urw_mappings == 0); 3388 KASSERT(md->uro_mappings == 0); 3389 KASSERT(md->krw_mappings == 0); 3390 KASSERT(md->kro_mappings == 0); 3391 #ifdef PMAP_CACHE_VIPT 3392 KASSERT(pv == NULL); 3393 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3394 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3395 /* if there is a color conflict, evict from cache. */ 3396 if (pmap_is_page_colored_p(md) 3397 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3398 PMAPCOUNT(vac_color_change); 3399 pmap_flush_page(md, VM_PAGE_TO_PHYS(pg), PMAP_FLUSH_PRIMARY); 3400 } else if (md->pvh_attrs & PVF_MULTCLR) { 3401 /* 3402 * If this page has multiple colors, expunge 3403 * them. 3404 */ 3405 PMAPCOUNT(vac_flush_lots2); 3406 pmap_flush_page(md, VM_PAGE_TO_PHYS(pg), PMAP_FLUSH_SECONDARY); 3407 } 3408 md->pvh_attrs &= PAGE_SIZE - 1; 3409 md->pvh_attrs |= PVF_KMPAGE 3410 | PVF_COLORED | PVF_DIRTY 3411 | (va & arm_cache_prefer_mask); 3412 #endif 3413 #ifdef PMAP_CACHE_VIVT 3414 md->pvh_attrs |= PVF_KMPAGE; 3415 #endif 3416 pmap_kmpages++; 3417 simple_unlock(&md->pvh_slock); 3418 #ifdef PMAP_CACHE_VIPT 3419 } else { 3420 if (pv == NULL) { 3421 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3422 KASSERT(pv != NULL); 3423 } 3424 pmap_enter_pv(md, VM_PAGE_TO_PHYS(pg), pv, pmap_kernel(), va, 3425 PVF_WIRED | PVF_KENTRY 3426 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3427 if ((prot & VM_PROT_WRITE) 3428 && !(md->pvh_attrs & PVF_NC)) 3429 md->pvh_attrs |= PVF_DIRTY; 3430 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3431 simple_lock(&md->pvh_slock); 3432 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pmap_kernel(), va); 3433 simple_unlock(&md->pvh_slock); 3434 #endif 3435 } 3436 #ifdef PMAP_CACHE_VIPT 3437 } else { 3438 if (pv != NULL) 3439 pool_put(&pmap_pv_pool, pv); 3440 #endif 3441 } 3442 } 3443 3444 void 3445 pmap_kremove(vaddr_t va, vsize_t len) 3446 { 3447 struct l2_bucket *l2b; 3448 pt_entry_t *ptep, *sptep, opte; 3449 vaddr_t next_bucket, eva; 3450 u_int mappings; 3451 struct vm_page *opg; 3452 3453 PMAPCOUNT(kenter_unmappings); 3454 3455 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3456 va, len)); 3457 3458 eva = va + len; 3459 3460 while (va < eva) { 3461 next_bucket = L2_NEXT_BUCKET(va); 3462 if (next_bucket > eva) 3463 next_bucket = eva; 3464 3465 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3466 KDASSERT(l2b != NULL); 3467 3468 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3469 mappings = 0; 3470 3471 while (va < next_bucket) { 3472 opte = *ptep; 3473 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3474 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3475 if (opg) { 3476 if (omd->pvh_attrs & PVF_KMPAGE) { 3477 simple_lock(&omd->pvh_slock); 3478 KASSERT(omd->urw_mappings == 0); 3479 KASSERT(omd->uro_mappings == 0); 3480 KASSERT(omd->krw_mappings == 0); 3481 KASSERT(omd->kro_mappings == 0); 3482 omd->pvh_attrs &= ~PVF_KMPAGE; 3483 #ifdef PMAP_CACHE_VIPT 3484 omd->pvh_attrs &= ~PVF_WRITE; 3485 #endif 3486 pmap_kmpages--; 3487 simple_unlock(&omd->pvh_slock); 3488 #ifdef PMAP_CACHE_VIPT 3489 } else { 3490 pool_put(&pmap_pv_pool, 3491 pmap_kremove_pg(opg, va)); 3492 #endif 3493 } 3494 } 3495 if (l2pte_valid(opte)) { 3496 #ifdef PMAP_CACHE_VIVT 3497 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3498 #endif 3499 cpu_tlb_flushD_SE(va); 3500 } 3501 if (opte) { 3502 *ptep = 0; 3503 mappings++; 3504 } 3505 va += PAGE_SIZE; 3506 ptep++; 3507 } 3508 KDASSERT(mappings <= l2b->l2b_occupancy); 3509 l2b->l2b_occupancy -= mappings; 3510 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3511 } 3512 cpu_cpwait(); 3513 } 3514 3515 bool 3516 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3517 { 3518 struct l2_dtable *l2; 3519 pd_entry_t *pl1pd, l1pd; 3520 pt_entry_t *ptep, pte; 3521 paddr_t pa; 3522 u_int l1idx; 3523 3524 pmap_acquire_pmap_lock(pm); 3525 3526 l1idx = L1_IDX(va); 3527 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3528 l1pd = *pl1pd; 3529 3530 if (l1pte_section_p(l1pd)) { 3531 /* 3532 * These should only happen for pmap_kernel() 3533 */ 3534 KDASSERT(pm == pmap_kernel()); 3535 pmap_release_pmap_lock(pm); 3536 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3537 } else { 3538 /* 3539 * Note that we can't rely on the validity of the L1 3540 * descriptor as an indication that a mapping exists. 3541 * We have to look it up in the L2 dtable. 3542 */ 3543 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3544 3545 if (l2 == NULL || 3546 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3547 pmap_release_pmap_lock(pm); 3548 return false; 3549 } 3550 3551 ptep = &ptep[l2pte_index(va)]; 3552 pte = *ptep; 3553 pmap_release_pmap_lock(pm); 3554 3555 if (pte == 0) 3556 return false; 3557 3558 switch (pte & L2_TYPE_MASK) { 3559 case L2_TYPE_L: 3560 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3561 break; 3562 3563 default: 3564 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3565 break; 3566 } 3567 } 3568 3569 if (pap != NULL) 3570 *pap = pa; 3571 3572 return true; 3573 } 3574 3575 void 3576 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3577 { 3578 struct l2_bucket *l2b; 3579 pt_entry_t *ptep, pte; 3580 vaddr_t next_bucket; 3581 u_int flags; 3582 u_int clr_mask; 3583 int flush; 3584 3585 NPDEBUG(PDB_PROTECT, 3586 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3587 pm, sva, eva, prot)); 3588 3589 if ((prot & VM_PROT_READ) == 0) { 3590 pmap_remove(pm, sva, eva); 3591 return; 3592 } 3593 3594 if (prot & VM_PROT_WRITE) { 3595 /* 3596 * If this is a read->write transition, just ignore it and let 3597 * uvm_fault() take care of it later. 3598 */ 3599 return; 3600 } 3601 3602 PMAP_MAP_TO_HEAD_LOCK(); 3603 pmap_acquire_pmap_lock(pm); 3604 3605 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3606 flags = 0; 3607 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3608 3609 while (sva < eva) { 3610 next_bucket = L2_NEXT_BUCKET(sva); 3611 if (next_bucket > eva) 3612 next_bucket = eva; 3613 3614 l2b = pmap_get_l2_bucket(pm, sva); 3615 if (l2b == NULL) { 3616 sva = next_bucket; 3617 continue; 3618 } 3619 3620 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3621 3622 while (sva < next_bucket) { 3623 pte = *ptep; 3624 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3625 struct vm_page *pg; 3626 u_int f; 3627 3628 #ifdef PMAP_CACHE_VIVT 3629 /* 3630 * OK, at this point, we know we're doing 3631 * write-protect operation. If the pmap is 3632 * active, write-back the page. 3633 */ 3634 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3635 false, false); 3636 #endif 3637 3638 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3639 pte &= ~L2_S_PROT_W; 3640 *ptep = pte; 3641 PTE_SYNC(ptep); 3642 3643 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3644 if (pg != NULL) { 3645 simple_lock(&md->pvh_slock); 3646 f = pmap_modify_pv(md, VM_PAGE_TO_PHYS(pg), pm, sva, 3647 clr_mask, 0); 3648 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pm, sva); 3649 simple_unlock(&md->pvh_slock); 3650 } else 3651 f = PVF_REF | PVF_EXEC; 3652 3653 if (flush >= 0) { 3654 flush++; 3655 flags |= f; 3656 } else 3657 if (PV_BEEN_EXECD(f)) 3658 pmap_tlb_flushID_SE(pm, sva); 3659 else 3660 if (PV_BEEN_REFD(f)) 3661 pmap_tlb_flushD_SE(pm, sva); 3662 } 3663 3664 sva += PAGE_SIZE; 3665 ptep++; 3666 } 3667 } 3668 3669 pmap_release_pmap_lock(pm); 3670 PMAP_MAP_TO_HEAD_UNLOCK(); 3671 3672 if (flush) { 3673 if (PV_BEEN_EXECD(flags)) 3674 pmap_tlb_flushID(pm); 3675 else 3676 if (PV_BEEN_REFD(flags)) 3677 pmap_tlb_flushD(pm); 3678 } 3679 } 3680 3681 void 3682 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3683 { 3684 struct l2_bucket *l2b; 3685 pt_entry_t *ptep; 3686 vaddr_t next_bucket; 3687 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3688 3689 NPDEBUG(PDB_EXEC, 3690 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3691 pm, sva, eva)); 3692 3693 PMAP_MAP_TO_HEAD_LOCK(); 3694 pmap_acquire_pmap_lock(pm); 3695 3696 while (sva < eva) { 3697 next_bucket = L2_NEXT_BUCKET(sva); 3698 if (next_bucket > eva) 3699 next_bucket = eva; 3700 3701 l2b = pmap_get_l2_bucket(pm, sva); 3702 if (l2b == NULL) { 3703 sva = next_bucket; 3704 continue; 3705 } 3706 3707 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3708 sva < next_bucket; 3709 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3710 if (l2pte_valid(*ptep)) { 3711 cpu_icache_sync_range(sva, 3712 min(page_size, eva - sva)); 3713 } 3714 } 3715 } 3716 3717 pmap_release_pmap_lock(pm); 3718 PMAP_MAP_TO_HEAD_UNLOCK(); 3719 } 3720 3721 void 3722 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3723 { 3724 3725 NPDEBUG(PDB_PROTECT, 3726 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3727 pg, VM_PAGE_TO_PHYS(pg), prot)); 3728 3729 switch(prot) { 3730 case VM_PROT_READ|VM_PROT_WRITE: 3731 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3732 pmap_clearbit(pg, PVF_EXEC); 3733 break; 3734 #endif 3735 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3736 break; 3737 3738 case VM_PROT_READ: 3739 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3740 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3741 break; 3742 #endif 3743 case VM_PROT_READ|VM_PROT_EXECUTE: 3744 pmap_clearbit(pg, PVF_WRITE); 3745 break; 3746 3747 default: 3748 pmap_page_remove(pg); 3749 break; 3750 } 3751 } 3752 3753 /* 3754 * pmap_clear_modify: 3755 * 3756 * Clear the "modified" attribute for a page. 3757 */ 3758 bool 3759 pmap_clear_modify(struct vm_page *pg) 3760 { 3761 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3762 bool rv; 3763 3764 if (md->pvh_attrs & PVF_MOD) { 3765 rv = true; 3766 #ifdef PMAP_CACHE_VIPT 3767 /* 3768 * If we are going to clear the modified bit and there are 3769 * no other modified bits set, flush the page to memory and 3770 * mark it clean. 3771 */ 3772 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3773 pmap_flush_page(md, VM_PAGE_TO_PHYS(pg), PMAP_CLEAN_PRIMARY); 3774 #endif 3775 pmap_clearbit(pg, PVF_MOD); 3776 } else 3777 rv = false; 3778 3779 return (rv); 3780 } 3781 3782 /* 3783 * pmap_clear_reference: 3784 * 3785 * Clear the "referenced" attribute for a page. 3786 */ 3787 bool 3788 pmap_clear_reference(struct vm_page *pg) 3789 { 3790 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3791 bool rv; 3792 3793 if (md->pvh_attrs & PVF_REF) { 3794 rv = true; 3795 pmap_clearbit(pg, PVF_REF); 3796 } else 3797 rv = false; 3798 3799 return (rv); 3800 } 3801 3802 /* 3803 * pmap_is_modified: 3804 * 3805 * Test if a page has the "modified" attribute. 3806 */ 3807 /* See <arm/arm32/pmap.h> */ 3808 3809 /* 3810 * pmap_is_referenced: 3811 * 3812 * Test if a page has the "referenced" attribute. 3813 */ 3814 /* See <arm/arm32/pmap.h> */ 3815 3816 int 3817 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3818 { 3819 struct l2_dtable *l2; 3820 struct l2_bucket *l2b; 3821 pd_entry_t *pl1pd, l1pd; 3822 pt_entry_t *ptep, pte; 3823 paddr_t pa; 3824 u_int l1idx; 3825 int rv = 0; 3826 3827 PMAP_MAP_TO_HEAD_LOCK(); 3828 pmap_acquire_pmap_lock(pm); 3829 3830 l1idx = L1_IDX(va); 3831 3832 /* 3833 * If there is no l2_dtable for this address, then the process 3834 * has no business accessing it. 3835 * 3836 * Note: This will catch userland processes trying to access 3837 * kernel addresses. 3838 */ 3839 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3840 if (l2 == NULL) 3841 goto out; 3842 3843 /* 3844 * Likewise if there is no L2 descriptor table 3845 */ 3846 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3847 if (l2b->l2b_kva == NULL) 3848 goto out; 3849 3850 /* 3851 * Check the PTE itself. 3852 */ 3853 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3854 pte = *ptep; 3855 if (pte == 0) 3856 goto out; 3857 3858 /* 3859 * Catch a userland access to the vector page mapped at 0x0 3860 */ 3861 if (user && (pte & L2_S_PROT_U) == 0) 3862 goto out; 3863 3864 pa = l2pte_pa(pte); 3865 3866 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3867 /* 3868 * This looks like a good candidate for "page modified" 3869 * emulation... 3870 */ 3871 struct pv_entry *pv; 3872 struct vm_page *pg; 3873 3874 /* Extract the physical address of the page */ 3875 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3876 goto out; 3877 3878 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3879 3880 /* Get the current flags for this page. */ 3881 simple_lock(&md->pvh_slock); 3882 3883 pv = pmap_find_pv(md, pm, va); 3884 if (pv == NULL) { 3885 simple_unlock(&md->pvh_slock); 3886 goto out; 3887 } 3888 3889 /* 3890 * Do the flags say this page is writable? If not then it 3891 * is a genuine write fault. If yes then the write fault is 3892 * our fault as we did not reflect the write access in the 3893 * PTE. Now we know a write has occurred we can correct this 3894 * and also set the modified bit 3895 */ 3896 if ((pv->pv_flags & PVF_WRITE) == 0) { 3897 simple_unlock(&md->pvh_slock); 3898 goto out; 3899 } 3900 3901 NPDEBUG(PDB_FOLLOW, 3902 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3903 pm, va, VM_PAGE_TO_PHYS(pg))); 3904 3905 md->pvh_attrs |= PVF_REF | PVF_MOD; 3906 pv->pv_flags |= PVF_REF | PVF_MOD; 3907 #ifdef PMAP_CACHE_VIPT 3908 /* 3909 * If there are cacheable mappings for this page, mark it dirty. 3910 */ 3911 if ((md->pvh_attrs & PVF_NC) == 0) 3912 md->pvh_attrs |= PVF_DIRTY; 3913 #endif 3914 simple_unlock(&md->pvh_slock); 3915 3916 /* 3917 * Re-enable write permissions for the page. No need to call 3918 * pmap_vac_me_harder(), since this is just a 3919 * modified-emulation fault, and the PVF_WRITE bit isn't 3920 * changing. We've already set the cacheable bits based on 3921 * the assumption that we can write to this page. 3922 */ 3923 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3924 PTE_SYNC(ptep); 3925 rv = 1; 3926 } else 3927 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3928 /* 3929 * This looks like a good candidate for "page referenced" 3930 * emulation. 3931 */ 3932 struct pv_entry *pv; 3933 struct vm_page *pg; 3934 3935 /* Extract the physical address of the page */ 3936 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3937 goto out; 3938 3939 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3940 3941 /* Get the current flags for this page. */ 3942 simple_lock(&md->pvh_slock); 3943 3944 pv = pmap_find_pv(md, pm, va); 3945 if (pv == NULL) { 3946 simple_unlock(&md->pvh_slock); 3947 goto out; 3948 } 3949 3950 md->pvh_attrs |= PVF_REF; 3951 pv->pv_flags |= PVF_REF; 3952 simple_unlock(&md->pvh_slock); 3953 3954 NPDEBUG(PDB_FOLLOW, 3955 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3956 pm, va, VM_PAGE_TO_PHYS(pg))); 3957 3958 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3959 PTE_SYNC(ptep); 3960 rv = 1; 3961 } 3962 3963 /* 3964 * We know there is a valid mapping here, so simply 3965 * fix up the L1 if necessary. 3966 */ 3967 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3968 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3969 if (*pl1pd != l1pd) { 3970 *pl1pd = l1pd; 3971 PTE_SYNC(pl1pd); 3972 rv = 1; 3973 } 3974 3975 #ifdef CPU_SA110 3976 /* 3977 * There are bugs in the rev K SA110. This is a check for one 3978 * of them. 3979 */ 3980 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3981 curcpu()->ci_arm_cpurev < 3) { 3982 /* Always current pmap */ 3983 if (l2pte_valid(pte)) { 3984 extern int kernel_debug; 3985 if (kernel_debug & 1) { 3986 struct proc *p = curlwp->l_proc; 3987 printf("prefetch_abort: page is already " 3988 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3989 printf("prefetch_abort: pc=%08lx proc=%p " 3990 "process=%s\n", va, p, p->p_comm); 3991 printf("prefetch_abort: far=%08x fs=%x\n", 3992 cpu_faultaddress(), cpu_faultstatus()); 3993 } 3994 #ifdef DDB 3995 if (kernel_debug & 2) 3996 Debugger(); 3997 #endif 3998 rv = 1; 3999 } 4000 } 4001 #endif /* CPU_SA110 */ 4002 4003 #ifdef DEBUG 4004 /* 4005 * If 'rv == 0' at this point, it generally indicates that there is a 4006 * stale TLB entry for the faulting address. This happens when two or 4007 * more processes are sharing an L1. Since we don't flush the TLB on 4008 * a context switch between such processes, we can take domain faults 4009 * for mappings which exist at the same VA in both processes. EVEN IF 4010 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4011 * example. 4012 * 4013 * This is extremely likely to happen if pmap_enter() updated the L1 4014 * entry for a recently entered mapping. In this case, the TLB is 4015 * flushed for the new mapping, but there may still be TLB entries for 4016 * other mappings belonging to other processes in the 1MB range 4017 * covered by the L1 entry. 4018 * 4019 * Since 'rv == 0', we know that the L1 already contains the correct 4020 * value, so the fault must be due to a stale TLB entry. 4021 * 4022 * Since we always need to flush the TLB anyway in the case where we 4023 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4024 * stale TLB entries dynamically. 4025 * 4026 * However, the above condition can ONLY happen if the current L1 is 4027 * being shared. If it happens when the L1 is unshared, it indicates 4028 * that other parts of the pmap are not doing their job WRT managing 4029 * the TLB. 4030 */ 4031 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4032 extern int last_fault_code; 4033 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4034 pm, va, ftype); 4035 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4036 l2, l2b, ptep, pl1pd); 4037 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4038 pte, l1pd, last_fault_code); 4039 #ifdef DDB 4040 Debugger(); 4041 #endif 4042 } 4043 #endif 4044 4045 cpu_tlb_flushID_SE(va); 4046 cpu_cpwait(); 4047 4048 rv = 1; 4049 4050 out: 4051 pmap_release_pmap_lock(pm); 4052 PMAP_MAP_TO_HEAD_UNLOCK(); 4053 4054 return (rv); 4055 } 4056 4057 /* 4058 * Routine: pmap_procwr 4059 * 4060 * Function: 4061 * Synchronize caches corresponding to [addr, addr+len) in p. 4062 * 4063 */ 4064 void 4065 pmap_procwr(struct proc *p, vaddr_t va, int len) 4066 { 4067 /* We only need to do anything if it is the current process. */ 4068 if (p == curproc) 4069 cpu_icache_sync_range(va, len); 4070 } 4071 4072 /* 4073 * Routine: pmap_unwire 4074 * Function: Clear the wired attribute for a map/virtual-address pair. 4075 * 4076 * In/out conditions: 4077 * The mapping must already exist in the pmap. 4078 */ 4079 void 4080 pmap_unwire(pmap_t pm, vaddr_t va) 4081 { 4082 struct l2_bucket *l2b; 4083 pt_entry_t *ptep, pte; 4084 struct vm_page *pg; 4085 paddr_t pa; 4086 4087 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4088 4089 PMAP_MAP_TO_HEAD_LOCK(); 4090 pmap_acquire_pmap_lock(pm); 4091 4092 l2b = pmap_get_l2_bucket(pm, va); 4093 KDASSERT(l2b != NULL); 4094 4095 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4096 pte = *ptep; 4097 4098 /* Extract the physical address of the page */ 4099 pa = l2pte_pa(pte); 4100 4101 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4102 /* Update the wired bit in the pv entry for this page. */ 4103 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4104 simple_lock(&md->pvh_slock); 4105 (void) pmap_modify_pv(md, VM_PAGE_TO_PHYS(pg), pm, va, PVF_WIRED, 0); 4106 simple_unlock(&md->pvh_slock); 4107 } 4108 4109 pmap_release_pmap_lock(pm); 4110 PMAP_MAP_TO_HEAD_UNLOCK(); 4111 } 4112 4113 void 4114 pmap_activate(struct lwp *l) 4115 { 4116 extern int block_userspace_access; 4117 pmap_t opm, npm, rpm; 4118 uint32_t odacr, ndacr; 4119 int oldirqstate; 4120 4121 /* 4122 * If activating a non-current lwp or the current lwp is 4123 * already active, just return. 4124 */ 4125 if (l != curlwp || 4126 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4127 return; 4128 4129 npm = l->l_proc->p_vmspace->vm_map.pmap; 4130 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4131 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4132 4133 /* 4134 * If TTB and DACR are unchanged, short-circuit all the 4135 * TLB/cache management stuff. 4136 */ 4137 if (pmap_previous_active_lwp != NULL) { 4138 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4139 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4140 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4141 4142 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4143 goto all_done; 4144 } else 4145 opm = NULL; 4146 4147 PMAPCOUNT(activations); 4148 block_userspace_access = 1; 4149 4150 /* 4151 * If switching to a user vmspace which is different to the 4152 * most recent one, and the most recent one is potentially 4153 * live in the cache, we must write-back and invalidate the 4154 * entire cache. 4155 */ 4156 rpm = pmap_recent_user; 4157 4158 /* 4159 * XXXSCW: There's a corner case here which can leave turds in the cache as 4160 * reported in kern/41058. They're probably left over during tear-down and 4161 * switching away from an exiting process. Until the root cause is identified 4162 * and fixed, zap the cache when switching pmaps. This will result in a few 4163 * unnecessary cache flushes, but that's better than silently corrupting data. 4164 */ 4165 #if 0 4166 if (npm != pmap_kernel() && rpm && npm != rpm && 4167 rpm->pm_cstate.cs_cache) { 4168 rpm->pm_cstate.cs_cache = 0; 4169 #ifdef PMAP_CACHE_VIVT 4170 cpu_idcache_wbinv_all(); 4171 #endif 4172 } 4173 #else 4174 if (rpm) { 4175 rpm->pm_cstate.cs_cache = 0; 4176 if (npm == pmap_kernel()) 4177 pmap_recent_user = NULL; 4178 #ifdef PMAP_CACHE_VIVT 4179 cpu_idcache_wbinv_all(); 4180 #endif 4181 } 4182 #endif 4183 4184 /* No interrupts while we frob the TTB/DACR */ 4185 oldirqstate = disable_interrupts(IF32_bits); 4186 4187 /* 4188 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4189 * entry corresponding to 'vector_page' in the incoming L1 table 4190 * before switching to it otherwise subsequent interrupts/exceptions 4191 * (including domain faults!) will jump into hyperspace. 4192 */ 4193 if (npm->pm_pl1vec != NULL) { 4194 cpu_tlb_flushID_SE((u_int)vector_page); 4195 cpu_cpwait(); 4196 *npm->pm_pl1vec = npm->pm_l1vec; 4197 PTE_SYNC(npm->pm_pl1vec); 4198 } 4199 4200 cpu_domains(ndacr); 4201 4202 if (npm == pmap_kernel() || npm == rpm) { 4203 /* 4204 * Switching to a kernel thread, or back to the 4205 * same user vmspace as before... Simply update 4206 * the TTB (no TLB flush required) 4207 */ 4208 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4209 "r"(npm->pm_l1->l1_physaddr)); 4210 cpu_cpwait(); 4211 } else { 4212 /* 4213 * Otherwise, update TTB and flush TLB 4214 */ 4215 cpu_context_switch(npm->pm_l1->l1_physaddr); 4216 if (rpm != NULL) 4217 rpm->pm_cstate.cs_tlb = 0; 4218 } 4219 4220 restore_interrupts(oldirqstate); 4221 4222 block_userspace_access = 0; 4223 4224 all_done: 4225 /* 4226 * The new pmap is resident. Make sure it's marked 4227 * as resident in the cache/TLB. 4228 */ 4229 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4230 if (npm != pmap_kernel()) 4231 pmap_recent_user = npm; 4232 4233 /* The old pmap is not longer active */ 4234 if (opm != NULL) 4235 opm->pm_activated = false; 4236 4237 /* But the new one is */ 4238 npm->pm_activated = true; 4239 } 4240 4241 void 4242 pmap_deactivate(struct lwp *l) 4243 { 4244 4245 /* 4246 * If the process is exiting, make sure pmap_activate() does 4247 * a full MMU context-switch and cache flush, which we might 4248 * otherwise skip. See PR port-arm/38950. 4249 */ 4250 if (l->l_proc->p_sflag & PS_WEXIT) 4251 pmap_previous_active_lwp = NULL; 4252 4253 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4254 } 4255 4256 void 4257 pmap_update(pmap_t pm) 4258 { 4259 4260 if (pm->pm_remove_all) { 4261 /* 4262 * Finish up the pmap_remove_all() optimisation by flushing 4263 * the TLB. 4264 */ 4265 pmap_tlb_flushID(pm); 4266 pm->pm_remove_all = false; 4267 } 4268 4269 if (pmap_is_current(pm)) { 4270 /* 4271 * If we're dealing with a current userland pmap, move its L1 4272 * to the end of the LRU. 4273 */ 4274 if (pm != pmap_kernel()) 4275 pmap_use_l1(pm); 4276 4277 /* 4278 * We can assume we're done with frobbing the cache/tlb for 4279 * now. Make sure any future pmap ops don't skip cache/tlb 4280 * flushes. 4281 */ 4282 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4283 } 4284 4285 PMAPCOUNT(updates); 4286 4287 /* 4288 * make sure TLB/cache operations have completed. 4289 */ 4290 cpu_cpwait(); 4291 } 4292 4293 void 4294 pmap_remove_all(pmap_t pm) 4295 { 4296 4297 /* 4298 * The vmspace described by this pmap is about to be torn down. 4299 * Until pmap_update() is called, UVM will only make calls 4300 * to pmap_remove(). We can make life much simpler by flushing 4301 * the cache now, and deferring TLB invalidation to pmap_update(). 4302 */ 4303 #ifdef PMAP_CACHE_VIVT 4304 pmap_idcache_wbinv_all(pm); 4305 #endif 4306 pm->pm_remove_all = true; 4307 } 4308 4309 /* 4310 * Retire the given physical map from service. 4311 * Should only be called if the map contains no valid mappings. 4312 */ 4313 void 4314 pmap_destroy(pmap_t pm) 4315 { 4316 u_int count; 4317 4318 if (pm == NULL) 4319 return; 4320 4321 if (pm->pm_remove_all) { 4322 pmap_tlb_flushID(pm); 4323 pm->pm_remove_all = false; 4324 } 4325 4326 /* 4327 * Drop reference count 4328 */ 4329 mutex_enter(&pm->pm_lock); 4330 count = --pm->pm_obj.uo_refs; 4331 mutex_exit(&pm->pm_lock); 4332 if (count > 0) { 4333 if (pmap_is_current(pm)) { 4334 if (pm != pmap_kernel()) 4335 pmap_use_l1(pm); 4336 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4337 } 4338 return; 4339 } 4340 4341 /* 4342 * reference count is zero, free pmap resources and then free pmap. 4343 */ 4344 4345 if (vector_page < KERNEL_BASE) { 4346 KDASSERT(!pmap_is_current(pm)); 4347 4348 /* Remove the vector page mapping */ 4349 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4350 pmap_update(pm); 4351 } 4352 4353 LIST_REMOVE(pm, pm_list); 4354 4355 pmap_free_l1(pm); 4356 4357 if (pmap_recent_user == pm) 4358 pmap_recent_user = NULL; 4359 4360 UVM_OBJ_DESTROY(&pm->pm_obj); 4361 4362 /* return the pmap to the pool */ 4363 pool_cache_put(&pmap_cache, pm); 4364 } 4365 4366 4367 /* 4368 * void pmap_reference(pmap_t pm) 4369 * 4370 * Add a reference to the specified pmap. 4371 */ 4372 void 4373 pmap_reference(pmap_t pm) 4374 { 4375 4376 if (pm == NULL) 4377 return; 4378 4379 pmap_use_l1(pm); 4380 4381 mutex_enter(&pm->pm_lock); 4382 pm->pm_obj.uo_refs++; 4383 mutex_exit(&pm->pm_lock); 4384 } 4385 4386 #if ARM_MMU_V6 > 0 4387 4388 static struct evcnt pmap_prefer_nochange_ev = 4389 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4390 static struct evcnt pmap_prefer_change_ev = 4391 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4392 4393 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4394 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4395 4396 void 4397 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4398 { 4399 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4400 vaddr_t va = *vap; 4401 vaddr_t diff = (hint - va) & mask; 4402 if (diff == 0) { 4403 pmap_prefer_nochange_ev.ev_count++; 4404 } else { 4405 pmap_prefer_change_ev.ev_count++; 4406 if (__predict_false(td)) 4407 va -= mask + 1; 4408 *vap = va + diff; 4409 } 4410 } 4411 #endif /* ARM_MMU_V6 */ 4412 4413 /* 4414 * pmap_zero_page() 4415 * 4416 * Zero a given physical page by mapping it at a page hook point. 4417 * In doing the zero page op, the page we zero is mapped cachable, as with 4418 * StrongARM accesses to non-cached pages are non-burst making writing 4419 * _any_ bulk data very slow. 4420 */ 4421 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4422 void 4423 pmap_zero_page_generic(paddr_t phys) 4424 { 4425 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4426 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4427 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4428 #endif 4429 #ifdef PMAP_CACHE_VIPT 4430 /* Choose the last page color it had, if any */ 4431 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4432 #else 4433 const vsize_t va_offset = 0; 4434 #endif 4435 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4436 4437 #ifdef DEBUG 4438 if (!SLIST_EMPTY(&md->pvh_list)) 4439 panic("pmap_zero_page: page has mappings"); 4440 #endif 4441 4442 KDASSERT((phys & PGOFSET) == 0); 4443 4444 /* 4445 * Hook in the page, zero it, and purge the cache for that 4446 * zeroed page. Invalidate the TLB as needed. 4447 */ 4448 *ptep = L2_S_PROTO | phys | 4449 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4450 PTE_SYNC(ptep); 4451 cpu_tlb_flushD_SE(cdstp + va_offset); 4452 cpu_cpwait(); 4453 bzero_page(cdstp + va_offset); 4454 /* 4455 * Unmap the page. 4456 */ 4457 *ptep = 0; 4458 PTE_SYNC(ptep); 4459 cpu_tlb_flushD_SE(cdstp + va_offset); 4460 #ifdef PMAP_CACHE_VIVT 4461 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4462 #endif 4463 #ifdef PMAP_CACHE_VIPT 4464 /* 4465 * This page is now cache resident so it now has a page color. 4466 * Any contents have been obliterated so clear the EXEC flag. 4467 */ 4468 if (!pmap_is_page_colored_p(md)) { 4469 PMAPCOUNT(vac_color_new); 4470 md->pvh_attrs |= PVF_COLORED; 4471 } 4472 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4473 md->pvh_attrs &= ~PVF_EXEC; 4474 PMAPCOUNT(exec_discarded_zero); 4475 } 4476 md->pvh_attrs |= PVF_DIRTY; 4477 #endif 4478 } 4479 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4480 4481 #if ARM_MMU_XSCALE == 1 4482 void 4483 pmap_zero_page_xscale(paddr_t phys) 4484 { 4485 #ifdef DEBUG 4486 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4487 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4488 4489 if (!SLIST_EMPTY(&md->pvh_list)) 4490 panic("pmap_zero_page: page has mappings"); 4491 #endif 4492 4493 KDASSERT((phys & PGOFSET) == 0); 4494 4495 /* 4496 * Hook in the page, zero it, and purge the cache for that 4497 * zeroed page. Invalidate the TLB as needed. 4498 */ 4499 *cdst_pte = L2_S_PROTO | phys | 4500 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4501 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4502 PTE_SYNC(cdst_pte); 4503 cpu_tlb_flushD_SE(cdstp); 4504 cpu_cpwait(); 4505 bzero_page(cdstp); 4506 xscale_cache_clean_minidata(); 4507 } 4508 #endif /* ARM_MMU_XSCALE == 1 */ 4509 4510 /* pmap_pageidlezero() 4511 * 4512 * The same as above, except that we assume that the page is not 4513 * mapped. This means we never have to flush the cache first. Called 4514 * from the idle loop. 4515 */ 4516 bool 4517 pmap_pageidlezero(paddr_t phys) 4518 { 4519 unsigned int i; 4520 int *ptr; 4521 bool rv = true; 4522 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4523 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4524 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4525 #endif 4526 #ifdef PMAP_CACHE_VIPT 4527 /* Choose the last page color it had, if any */ 4528 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4529 #else 4530 const vsize_t va_offset = 0; 4531 #endif 4532 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4533 4534 4535 #ifdef DEBUG 4536 if (!SLIST_EMPTY(&md->pvh_list)) 4537 panic("pmap_pageidlezero: page has mappings"); 4538 #endif 4539 4540 KDASSERT((phys & PGOFSET) == 0); 4541 4542 /* 4543 * Hook in the page, zero it, and purge the cache for that 4544 * zeroed page. Invalidate the TLB as needed. 4545 */ 4546 *ptep = L2_S_PROTO | phys | 4547 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4548 PTE_SYNC(ptep); 4549 cpu_tlb_flushD_SE(cdstp + va_offset); 4550 cpu_cpwait(); 4551 4552 for (i = 0, ptr = (int *)(cdstp + va_offset); 4553 i < (PAGE_SIZE / sizeof(int)); i++) { 4554 if (sched_curcpu_runnable_p() != 0) { 4555 /* 4556 * A process has become ready. Abort now, 4557 * so we don't keep it waiting while we 4558 * do slow memory access to finish this 4559 * page. 4560 */ 4561 rv = false; 4562 break; 4563 } 4564 *ptr++ = 0; 4565 } 4566 4567 #ifdef PMAP_CACHE_VIVT 4568 if (rv) 4569 /* 4570 * if we aborted we'll rezero this page again later so don't 4571 * purge it unless we finished it 4572 */ 4573 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4574 #elif defined(PMAP_CACHE_VIPT) 4575 /* 4576 * This page is now cache resident so it now has a page color. 4577 * Any contents have been obliterated so clear the EXEC flag. 4578 */ 4579 if (!pmap_is_page_colored_p(md)) { 4580 PMAPCOUNT(vac_color_new); 4581 md->pvh_attrs |= PVF_COLORED; 4582 } 4583 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4584 md->pvh_attrs &= ~PVF_EXEC; 4585 PMAPCOUNT(exec_discarded_zero); 4586 } 4587 #endif 4588 /* 4589 * Unmap the page. 4590 */ 4591 *ptep = 0; 4592 PTE_SYNC(ptep); 4593 cpu_tlb_flushD_SE(cdstp + va_offset); 4594 4595 return (rv); 4596 } 4597 4598 /* 4599 * pmap_copy_page() 4600 * 4601 * Copy one physical page into another, by mapping the pages into 4602 * hook points. The same comment regarding cachability as in 4603 * pmap_zero_page also applies here. 4604 */ 4605 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4606 void 4607 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4608 { 4609 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4610 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4611 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4612 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4613 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4614 #endif 4615 #ifdef PMAP_CACHE_VIPT 4616 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4617 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4618 #else 4619 const vsize_t src_va_offset = 0; 4620 const vsize_t dst_va_offset = 0; 4621 #endif 4622 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4623 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4624 4625 #ifdef DEBUG 4626 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4627 panic("pmap_copy_page: dst page has mappings"); 4628 #endif 4629 4630 #ifdef PMAP_CACHE_VIPT 4631 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4632 #endif 4633 KDASSERT((src & PGOFSET) == 0); 4634 KDASSERT((dst & PGOFSET) == 0); 4635 4636 /* 4637 * Clean the source page. Hold the source page's lock for 4638 * the duration of the copy so that no other mappings can 4639 * be created while we have a potentially aliased mapping. 4640 */ 4641 simple_lock(&src_md->pvh_slock); 4642 #ifdef PMAP_CACHE_VIVT 4643 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4644 #endif 4645 4646 /* 4647 * Map the pages into the page hook points, copy them, and purge 4648 * the cache for the appropriate page. Invalidate the TLB 4649 * as required. 4650 */ 4651 *src_ptep = L2_S_PROTO 4652 | src 4653 #ifdef PMAP_CACHE_VIPT 4654 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4655 #endif 4656 #ifdef PMAP_CACHE_VIVT 4657 | pte_l2_s_cache_mode 4658 #endif 4659 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4660 *dst_ptep = L2_S_PROTO | dst | 4661 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4662 PTE_SYNC(src_ptep); 4663 PTE_SYNC(dst_ptep); 4664 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4665 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4666 cpu_cpwait(); 4667 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4668 #ifdef PMAP_CACHE_VIVT 4669 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4670 #endif 4671 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4672 #ifdef PMAP_CACHE_VIVT 4673 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4674 #endif 4675 /* 4676 * Unmap the pages. 4677 */ 4678 *src_ptep = 0; 4679 *dst_ptep = 0; 4680 PTE_SYNC(src_ptep); 4681 PTE_SYNC(dst_ptep); 4682 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4683 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4684 #ifdef PMAP_CACHE_VIPT 4685 /* 4686 * Now that the destination page is in the cache, mark it as colored. 4687 * If this was an exec page, discard it. 4688 */ 4689 if (!pmap_is_page_colored_p(dst_md)) { 4690 PMAPCOUNT(vac_color_new); 4691 dst_md->pvh_attrs |= PVF_COLORED; 4692 } 4693 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4694 dst_md->pvh_attrs &= ~PVF_EXEC; 4695 PMAPCOUNT(exec_discarded_copy); 4696 } 4697 dst_md->pvh_attrs |= PVF_DIRTY; 4698 #endif 4699 } 4700 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4701 4702 #if ARM_MMU_XSCALE == 1 4703 void 4704 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4705 { 4706 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4707 #ifdef DEBUG 4708 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4709 4710 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4711 panic("pmap_copy_page: dst page has mappings"); 4712 #endif 4713 4714 KDASSERT((src & PGOFSET) == 0); 4715 KDASSERT((dst & PGOFSET) == 0); 4716 4717 /* 4718 * Clean the source page. Hold the source page's lock for 4719 * the duration of the copy so that no other mappings can 4720 * be created while we have a potentially aliased mapping. 4721 */ 4722 simple_lock(&src_md->pvh_slock); 4723 #ifdef PMAP_CACHE_VIVT 4724 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4725 #endif 4726 4727 /* 4728 * Map the pages into the page hook points, copy them, and purge 4729 * the cache for the appropriate page. Invalidate the TLB 4730 * as required. 4731 */ 4732 *csrc_pte = L2_S_PROTO | src | 4733 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4734 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4735 PTE_SYNC(csrc_pte); 4736 *cdst_pte = L2_S_PROTO | dst | 4737 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4738 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4739 PTE_SYNC(cdst_pte); 4740 cpu_tlb_flushD_SE(csrcp); 4741 cpu_tlb_flushD_SE(cdstp); 4742 cpu_cpwait(); 4743 bcopy_page(csrcp, cdstp); 4744 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4745 xscale_cache_clean_minidata(); 4746 } 4747 #endif /* ARM_MMU_XSCALE == 1 */ 4748 4749 /* 4750 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4751 * 4752 * Return the start and end addresses of the kernel's virtual space. 4753 * These values are setup in pmap_bootstrap and are updated as pages 4754 * are allocated. 4755 */ 4756 void 4757 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4758 { 4759 *start = virtual_avail; 4760 *end = virtual_end; 4761 } 4762 4763 /* 4764 * Helper function for pmap_grow_l2_bucket() 4765 */ 4766 static inline int 4767 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4768 { 4769 struct l2_bucket *l2b; 4770 pt_entry_t *ptep; 4771 paddr_t pa; 4772 4773 if (uvm.page_init_done == false) { 4774 #ifdef PMAP_STEAL_MEMORY 4775 pv_addr_t pv; 4776 pmap_boot_pagealloc(PAGE_SIZE, 4777 #ifdef PMAP_CACHE_VIPT 4778 arm_cache_prefer_mask, 4779 va & arm_cache_prefer_mask, 4780 #else 4781 0, 0, 4782 #endif 4783 &pv); 4784 pa = pv.pv_pa; 4785 #else 4786 if (uvm_page_physget(&pa) == false) 4787 return (1); 4788 #endif /* PMAP_STEAL_MEMORY */ 4789 } else { 4790 struct vm_page *pg; 4791 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4792 if (pg == NULL) 4793 return (1); 4794 pa = VM_PAGE_TO_PHYS(pg); 4795 #ifdef PMAP_CACHE_VIPT 4796 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4797 /* 4798 * This new page must not have any mappings. Enter it via 4799 * pmap_kenter_pa and let that routine do the hard work. 4800 */ 4801 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4802 pmap_kenter_pa(va, pa, 4803 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); 4804 #endif 4805 } 4806 4807 if (pap) 4808 *pap = pa; 4809 4810 PMAPCOUNT(pt_mappings); 4811 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4812 KDASSERT(l2b != NULL); 4813 4814 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4815 *ptep = L2_S_PROTO | pa | cache_mode | 4816 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4817 PTE_SYNC(ptep); 4818 memset((void *)va, 0, PAGE_SIZE); 4819 return (0); 4820 } 4821 4822 /* 4823 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4824 * used by pmap_growkernel(). 4825 */ 4826 static inline struct l2_bucket * 4827 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4828 { 4829 struct l2_dtable *l2; 4830 struct l2_bucket *l2b; 4831 u_short l1idx; 4832 vaddr_t nva; 4833 4834 l1idx = L1_IDX(va); 4835 4836 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4837 /* 4838 * No mapping at this address, as there is 4839 * no entry in the L1 table. 4840 * Need to allocate a new l2_dtable. 4841 */ 4842 nva = pmap_kernel_l2dtable_kva; 4843 if ((nva & PGOFSET) == 0) { 4844 /* 4845 * Need to allocate a backing page 4846 */ 4847 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4848 return (NULL); 4849 } 4850 4851 l2 = (struct l2_dtable *)nva; 4852 nva += sizeof(struct l2_dtable); 4853 4854 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4855 /* 4856 * The new l2_dtable straddles a page boundary. 4857 * Map in another page to cover it. 4858 */ 4859 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4860 return (NULL); 4861 } 4862 4863 pmap_kernel_l2dtable_kva = nva; 4864 4865 /* 4866 * Link it into the parent pmap 4867 */ 4868 pm->pm_l2[L2_IDX(l1idx)] = l2; 4869 } 4870 4871 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4872 4873 /* 4874 * Fetch pointer to the L2 page table associated with the address. 4875 */ 4876 if (l2b->l2b_kva == NULL) { 4877 pt_entry_t *ptep; 4878 4879 /* 4880 * No L2 page table has been allocated. Chances are, this 4881 * is because we just allocated the l2_dtable, above. 4882 */ 4883 nva = pmap_kernel_l2ptp_kva; 4884 ptep = (pt_entry_t *)nva; 4885 if ((nva & PGOFSET) == 0) { 4886 /* 4887 * Need to allocate a backing page 4888 */ 4889 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4890 &pmap_kernel_l2ptp_phys)) 4891 return (NULL); 4892 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4893 } 4894 4895 l2->l2_occupancy++; 4896 l2b->l2b_kva = ptep; 4897 l2b->l2b_l1idx = l1idx; 4898 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4899 4900 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4901 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4902 } 4903 4904 return (l2b); 4905 } 4906 4907 vaddr_t 4908 pmap_growkernel(vaddr_t maxkvaddr) 4909 { 4910 pmap_t kpm = pmap_kernel(); 4911 struct l1_ttable *l1; 4912 struct l2_bucket *l2b; 4913 pd_entry_t *pl1pd; 4914 int s; 4915 4916 if (maxkvaddr <= pmap_curmaxkvaddr) 4917 goto out; /* we are OK */ 4918 4919 NPDEBUG(PDB_GROWKERN, 4920 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4921 pmap_curmaxkvaddr, maxkvaddr)); 4922 4923 KDASSERT(maxkvaddr <= virtual_end); 4924 4925 /* 4926 * whoops! we need to add kernel PTPs 4927 */ 4928 4929 s = splhigh(); /* to be safe */ 4930 mutex_enter(&kpm->pm_lock); 4931 4932 /* Map 1MB at a time */ 4933 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4934 4935 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4936 KDASSERT(l2b != NULL); 4937 4938 /* Distribute new L1 entry to all other L1s */ 4939 SLIST_FOREACH(l1, &l1_list, l1_link) { 4940 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4941 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4942 L1_C_PROTO; 4943 PTE_SYNC(pl1pd); 4944 } 4945 } 4946 4947 /* 4948 * flush out the cache, expensive but growkernel will happen so 4949 * rarely 4950 */ 4951 cpu_dcache_wbinv_all(); 4952 cpu_tlb_flushD(); 4953 cpu_cpwait(); 4954 4955 mutex_exit(&kpm->pm_lock); 4956 splx(s); 4957 4958 out: 4959 return (pmap_curmaxkvaddr); 4960 } 4961 4962 /************************ Utility routines ****************************/ 4963 4964 /* 4965 * vector_page_setprot: 4966 * 4967 * Manipulate the protection of the vector page. 4968 */ 4969 void 4970 vector_page_setprot(int prot) 4971 { 4972 struct l2_bucket *l2b; 4973 pt_entry_t *ptep; 4974 4975 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4976 KDASSERT(l2b != NULL); 4977 4978 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4979 4980 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4981 PTE_SYNC(ptep); 4982 cpu_tlb_flushD_SE(vector_page); 4983 cpu_cpwait(); 4984 } 4985 4986 /* 4987 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4988 * Returns true if the mapping exists, else false. 4989 * 4990 * NOTE: This function is only used by a couple of arm-specific modules. 4991 * It is not safe to take any pmap locks here, since we could be right 4992 * in the middle of debugging the pmap anyway... 4993 * 4994 * It is possible for this routine to return false even though a valid 4995 * mapping does exist. This is because we don't lock, so the metadata 4996 * state may be inconsistent. 4997 * 4998 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4999 * a "section" mapping. 5000 */ 5001 bool 5002 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5003 { 5004 struct l2_dtable *l2; 5005 pd_entry_t *pl1pd, l1pd; 5006 pt_entry_t *ptep; 5007 u_short l1idx; 5008 5009 if (pm->pm_l1 == NULL) 5010 return false; 5011 5012 l1idx = L1_IDX(va); 5013 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5014 l1pd = *pl1pd; 5015 5016 if (l1pte_section_p(l1pd)) { 5017 *ptp = NULL; 5018 return true; 5019 } 5020 5021 if (pm->pm_l2 == NULL) 5022 return false; 5023 5024 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5025 5026 if (l2 == NULL || 5027 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5028 return false; 5029 } 5030 5031 *ptp = &ptep[l2pte_index(va)]; 5032 return true; 5033 } 5034 5035 bool 5036 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5037 { 5038 u_short l1idx; 5039 5040 if (pm->pm_l1 == NULL) 5041 return false; 5042 5043 l1idx = L1_IDX(va); 5044 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5045 5046 return true; 5047 } 5048 5049 /************************ Bootstrapping routines ****************************/ 5050 5051 static void 5052 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5053 { 5054 int i; 5055 5056 l1->l1_kva = l1pt; 5057 l1->l1_domain_use_count = 0; 5058 l1->l1_domain_first = 0; 5059 5060 for (i = 0; i < PMAP_DOMAINS; i++) 5061 l1->l1_domain_free[i] = i + 1; 5062 5063 /* 5064 * Copy the kernel's L1 entries to each new L1. 5065 */ 5066 if (pmap_initialized) 5067 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5068 5069 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5070 &l1->l1_physaddr) == false) 5071 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5072 5073 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5074 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5075 } 5076 5077 /* 5078 * pmap_bootstrap() is called from the board-specific initarm() routine 5079 * once the kernel L1/L2 descriptors tables have been set up. 5080 * 5081 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5082 * spread over a number of disparate files/functions. 5083 * 5084 * We are passed the following parameters 5085 * - kernel_l1pt 5086 * This is a pointer to the base of the kernel's L1 translation table. 5087 * - vstart 5088 * 1MB-aligned start of managed kernel virtual memory. 5089 * - vend 5090 * 1MB-aligned end of managed kernel virtual memory. 5091 * 5092 * We use the first parameter to build the metadata (struct l1_ttable and 5093 * struct l2_dtable) necessary to track kernel mappings. 5094 */ 5095 #define PMAP_STATIC_L2_SIZE 16 5096 void 5097 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5098 { 5099 static struct l1_ttable static_l1; 5100 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5101 struct l1_ttable *l1 = &static_l1; 5102 struct l2_dtable *l2; 5103 struct l2_bucket *l2b; 5104 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5105 pmap_t pm = pmap_kernel(); 5106 pd_entry_t pde; 5107 pt_entry_t *ptep; 5108 paddr_t pa; 5109 vaddr_t va; 5110 vsize_t size; 5111 int nptes, l1idx, l2idx, l2next = 0; 5112 5113 /* 5114 * Initialise the kernel pmap object 5115 */ 5116 pm->pm_l1 = l1; 5117 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5118 pm->pm_activated = true; 5119 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5120 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5121 5122 /* 5123 * Scan the L1 translation table created by initarm() and create 5124 * the required metadata for all valid mappings found in it. 5125 */ 5126 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5127 pde = l1pt[l1idx]; 5128 5129 /* 5130 * We're only interested in Coarse mappings. 5131 * pmap_extract() can deal with section mappings without 5132 * recourse to checking L2 metadata. 5133 */ 5134 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5135 continue; 5136 5137 /* 5138 * Lookup the KVA of this L2 descriptor table 5139 */ 5140 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5141 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5142 if (ptep == NULL) { 5143 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5144 (u_int)l1idx << L1_S_SHIFT, pa); 5145 } 5146 5147 /* 5148 * Fetch the associated L2 metadata structure. 5149 * Allocate a new one if necessary. 5150 */ 5151 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5152 if (l2next == PMAP_STATIC_L2_SIZE) 5153 panic("pmap_bootstrap: out of static L2s"); 5154 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5155 } 5156 5157 /* 5158 * One more L1 slot tracked... 5159 */ 5160 l2->l2_occupancy++; 5161 5162 /* 5163 * Fill in the details of the L2 descriptor in the 5164 * appropriate bucket. 5165 */ 5166 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5167 l2b->l2b_kva = ptep; 5168 l2b->l2b_phys = pa; 5169 l2b->l2b_l1idx = l1idx; 5170 5171 /* 5172 * Establish an initial occupancy count for this descriptor 5173 */ 5174 for (l2idx = 0; 5175 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5176 l2idx++) { 5177 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5178 l2b->l2b_occupancy++; 5179 } 5180 } 5181 5182 /* 5183 * Make sure the descriptor itself has the correct cache mode. 5184 * If not, fix it, but whine about the problem. Port-meisters 5185 * should consider this a clue to fix up their initarm() 5186 * function. :) 5187 */ 5188 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5189 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5190 "L2 pte @ %p\n", ptep); 5191 } 5192 } 5193 5194 /* 5195 * Ensure the primary (kernel) L1 has the correct cache mode for 5196 * a page table. Bitch if it is not correctly set. 5197 */ 5198 for (va = (vaddr_t)l1pt; 5199 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5200 if (pmap_set_pt_cache_mode(l1pt, va)) 5201 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5202 "primary L1 @ 0x%lx\n", va); 5203 } 5204 5205 cpu_dcache_wbinv_all(); 5206 cpu_tlb_flushID(); 5207 cpu_cpwait(); 5208 5209 /* 5210 * now we allocate the "special" VAs which are used for tmp mappings 5211 * by the pmap (and other modules). we allocate the VAs by advancing 5212 * virtual_avail (note that there are no pages mapped at these VAs). 5213 * 5214 * Managed KVM space start from wherever initarm() tells us. 5215 */ 5216 virtual_avail = vstart; 5217 virtual_end = vend; 5218 5219 #ifdef PMAP_CACHE_VIPT 5220 /* 5221 * If we have a VIPT cache, we need one page/pte per possible alias 5222 * page so we won't violate cache aliasing rules. 5223 */ 5224 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5225 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5226 #else 5227 nptes = 1; 5228 #endif 5229 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5230 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5231 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5232 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5233 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5234 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5235 (void *)&msgbufaddr, NULL); 5236 5237 /* 5238 * Allocate a range of kernel virtual address space to be used 5239 * for L2 descriptor tables and metadata allocation in 5240 * pmap_growkernel(). 5241 */ 5242 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5243 pmap_alloc_specials(&virtual_avail, 5244 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5245 &pmap_kernel_l2ptp_kva, NULL); 5246 5247 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5248 pmap_alloc_specials(&virtual_avail, 5249 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5250 &pmap_kernel_l2dtable_kva, NULL); 5251 5252 /* 5253 * init the static-global locks and global pmap list. 5254 */ 5255 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5256 5257 /* 5258 * We can now initialise the first L1's metadata. 5259 */ 5260 SLIST_INIT(&l1_list); 5261 TAILQ_INIT(&l1_lru_list); 5262 simple_lock_init(&l1_lru_lock); 5263 pmap_init_l1(l1, l1pt); 5264 5265 /* Set up vector page L1 details, if necessary */ 5266 if (vector_page < KERNEL_BASE) { 5267 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5268 l2b = pmap_get_l2_bucket(pm, vector_page); 5269 KDASSERT(l2b != NULL); 5270 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5271 L1_C_DOM(pm->pm_domain); 5272 } else 5273 pm->pm_pl1vec = NULL; 5274 5275 /* 5276 * Initialize the pmap cache 5277 */ 5278 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5279 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5280 LIST_INIT(&pmap_pmaps); 5281 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5282 5283 /* 5284 * Initialize the pv pool. 5285 */ 5286 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5287 &pmap_bootstrap_pv_allocator, IPL_NONE); 5288 5289 /* 5290 * Initialize the L2 dtable pool and cache. 5291 */ 5292 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5293 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5294 5295 /* 5296 * Initialise the L2 descriptor table pool and cache 5297 */ 5298 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5299 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5300 pmap_l2ptp_ctor, NULL, NULL); 5301 5302 cpu_dcache_wbinv_all(); 5303 } 5304 5305 static int 5306 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5307 { 5308 pd_entry_t *pdep, pde; 5309 pt_entry_t *ptep, pte; 5310 vaddr_t pa; 5311 int rv = 0; 5312 5313 /* 5314 * Make sure the descriptor itself has the correct cache mode 5315 */ 5316 pdep = &kl1[L1_IDX(va)]; 5317 pde = *pdep; 5318 5319 if (l1pte_section_p(pde)) { 5320 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5321 *pdep = (pde & ~L1_S_CACHE_MASK) | 5322 pte_l1_s_cache_mode_pt; 5323 PTE_SYNC(pdep); 5324 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5325 rv = 1; 5326 } 5327 } else { 5328 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5329 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5330 if (ptep == NULL) 5331 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5332 5333 ptep = &ptep[l2pte_index(va)]; 5334 pte = *ptep; 5335 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5336 *ptep = (pte & ~L2_S_CACHE_MASK) | 5337 pte_l2_s_cache_mode_pt; 5338 PTE_SYNC(ptep); 5339 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5340 rv = 1; 5341 } 5342 } 5343 5344 return (rv); 5345 } 5346 5347 static void 5348 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5349 { 5350 vaddr_t va = *availp; 5351 struct l2_bucket *l2b; 5352 5353 if (ptep) { 5354 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5355 if (l2b == NULL) 5356 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5357 5358 if (ptep) 5359 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5360 } 5361 5362 *vap = va; 5363 *availp = va + (PAGE_SIZE * pages); 5364 } 5365 5366 void 5367 pmap_init(void) 5368 { 5369 5370 /* 5371 * Set the available memory vars - These do not map to real memory 5372 * addresses and cannot as the physical memory is fragmented. 5373 * They are used by ps for %mem calculations. 5374 * One could argue whether this should be the entire memory or just 5375 * the memory that is useable in a user process. 5376 */ 5377 avail_start = ptoa(vm_physmem[0].start); 5378 avail_end = ptoa(vm_physmem[vm_nphysseg - 1].end); 5379 5380 /* 5381 * Now we need to free enough pv_entry structures to allow us to get 5382 * the kmem_map/kmem_object allocated and inited (done after this 5383 * function is finished). to do this we allocate one bootstrap page out 5384 * of kernel_map and use it to provide an initial pool of pv_entry 5385 * structures. we never free this page. 5386 */ 5387 pool_setlowat(&pmap_pv_pool, 5388 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5389 5390 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5391 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5392 UVM_KMF_WIRED|UVM_KMF_ZERO); 5393 5394 pmap_initialized = true; 5395 } 5396 5397 static vaddr_t last_bootstrap_page = 0; 5398 static void *free_bootstrap_pages = NULL; 5399 5400 static void * 5401 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5402 { 5403 extern void *pool_page_alloc(struct pool *, int); 5404 vaddr_t new_page; 5405 void *rv; 5406 5407 if (pmap_initialized) 5408 return (pool_page_alloc(pp, flags)); 5409 5410 if (free_bootstrap_pages) { 5411 rv = free_bootstrap_pages; 5412 free_bootstrap_pages = *((void **)rv); 5413 return (rv); 5414 } 5415 5416 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5417 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5418 5419 KASSERT(new_page > last_bootstrap_page); 5420 last_bootstrap_page = new_page; 5421 return ((void *)new_page); 5422 } 5423 5424 static void 5425 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5426 { 5427 extern void pool_page_free(struct pool *, void *); 5428 5429 if ((vaddr_t)v <= last_bootstrap_page) { 5430 *((void **)v) = free_bootstrap_pages; 5431 free_bootstrap_pages = v; 5432 return; 5433 } 5434 5435 if (pmap_initialized) { 5436 pool_page_free(pp, v); 5437 return; 5438 } 5439 } 5440 5441 /* 5442 * pmap_postinit() 5443 * 5444 * This routine is called after the vm and kmem subsystems have been 5445 * initialised. This allows the pmap code to perform any initialisation 5446 * that can only be done one the memory allocation is in place. 5447 */ 5448 void 5449 pmap_postinit(void) 5450 { 5451 extern paddr_t physical_start, physical_end; 5452 struct l2_bucket *l2b; 5453 struct l1_ttable *l1; 5454 struct pglist plist; 5455 struct vm_page *m; 5456 pd_entry_t *pl1pt; 5457 pt_entry_t *ptep, pte; 5458 vaddr_t va, eva; 5459 u_int loop, needed; 5460 int error; 5461 5462 pool_cache_setlowat(&pmap_l2ptp_cache, 5463 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5464 pool_cache_setlowat(&pmap_l2dtable_cache, 5465 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5466 5467 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5468 needed -= 1; 5469 5470 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5471 5472 for (loop = 0; loop < needed; loop++, l1++) { 5473 /* Allocate a L1 page table */ 5474 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5475 if (va == 0) 5476 panic("Cannot allocate L1 KVM"); 5477 5478 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5479 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5480 if (error) 5481 panic("Cannot allocate L1 physical pages"); 5482 5483 m = TAILQ_FIRST(&plist); 5484 eva = va + L1_TABLE_SIZE; 5485 pl1pt = (pd_entry_t *)va; 5486 5487 while (m && va < eva) { 5488 paddr_t pa = VM_PAGE_TO_PHYS(m); 5489 5490 pmap_kenter_pa(va, pa, 5491 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); 5492 5493 /* 5494 * Make sure the L1 descriptor table is mapped 5495 * with the cache-mode set to write-through. 5496 */ 5497 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5498 KDASSERT(l2b != NULL); 5499 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5500 pte = *ptep; 5501 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5502 *ptep = pte; 5503 PTE_SYNC(ptep); 5504 cpu_tlb_flushD_SE(va); 5505 5506 va += PAGE_SIZE; 5507 m = TAILQ_NEXT(m, pageq.queue); 5508 } 5509 5510 #ifdef DIAGNOSTIC 5511 if (m) 5512 panic("pmap_alloc_l1pt: pglist not empty"); 5513 #endif /* DIAGNOSTIC */ 5514 5515 pmap_init_l1(l1, pl1pt); 5516 } 5517 5518 #ifdef DEBUG 5519 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5520 needed); 5521 #endif 5522 } 5523 5524 /* 5525 * Note that the following routines are used by board-specific initialisation 5526 * code to configure the initial kernel page tables. 5527 * 5528 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5529 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5530 * behaviour of the old pmap, and provides an easy migration path for 5531 * initial bring-up of the new pmap on existing ports. Fortunately, 5532 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5533 * will be deprecated. 5534 * 5535 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5536 * tables. 5537 */ 5538 5539 /* 5540 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5541 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5542 * find them as necessary. 5543 * 5544 * Note that the data on this list MUST remain valid after initarm() returns, 5545 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5546 */ 5547 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5548 5549 static vaddr_t 5550 kernel_pt_lookup(paddr_t pa) 5551 { 5552 pv_addr_t *pv; 5553 5554 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5555 #ifndef ARM32_NEW_VM_LAYOUT 5556 if (pv->pv_pa == (pa & ~PGOFSET)) 5557 return (pv->pv_va | (pa & PGOFSET)); 5558 #else 5559 if (pv->pv_pa == pa) 5560 return (pv->pv_va); 5561 #endif 5562 } 5563 return (0); 5564 } 5565 5566 /* 5567 * pmap_map_section: 5568 * 5569 * Create a single section mapping. 5570 */ 5571 void 5572 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5573 { 5574 pd_entry_t *pde = (pd_entry_t *) l1pt; 5575 pd_entry_t fl; 5576 5577 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5578 5579 switch (cache) { 5580 case PTE_NOCACHE: 5581 default: 5582 fl = 0; 5583 break; 5584 5585 case PTE_CACHE: 5586 fl = pte_l1_s_cache_mode; 5587 break; 5588 5589 case PTE_PAGETABLE: 5590 fl = pte_l1_s_cache_mode_pt; 5591 break; 5592 } 5593 5594 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5595 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5596 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5597 } 5598 5599 /* 5600 * pmap_map_entry: 5601 * 5602 * Create a single page mapping. 5603 */ 5604 void 5605 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5606 { 5607 pd_entry_t *pde = (pd_entry_t *) l1pt; 5608 pt_entry_t fl; 5609 pt_entry_t *pte; 5610 5611 KASSERT(((va | pa) & PGOFSET) == 0); 5612 5613 switch (cache) { 5614 case PTE_NOCACHE: 5615 default: 5616 fl = 0; 5617 break; 5618 5619 case PTE_CACHE: 5620 fl = pte_l2_s_cache_mode; 5621 break; 5622 5623 case PTE_PAGETABLE: 5624 fl = pte_l2_s_cache_mode_pt; 5625 break; 5626 } 5627 5628 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5629 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5630 5631 #ifndef ARM32_NEW_VM_LAYOUT 5632 pte = (pt_entry_t *) 5633 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5634 #else 5635 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5636 #endif 5637 if (pte == NULL) 5638 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5639 5640 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5641 #ifndef ARM32_NEW_VM_LAYOUT 5642 pte += (va >> PGSHIFT) & 0x3ff; 5643 #else 5644 pte += l2pte_index(va); 5645 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5646 #endif 5647 *pte = fl; 5648 PTE_SYNC(pte); 5649 } 5650 5651 /* 5652 * pmap_link_l2pt: 5653 * 5654 * Link the L2 page table specified by "l2pv" into the L1 5655 * page table at the slot for "va". 5656 */ 5657 void 5658 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5659 { 5660 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5661 u_int slot = va >> L1_S_SHIFT; 5662 5663 #ifndef ARM32_NEW_VM_LAYOUT 5664 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5665 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5666 #endif 5667 5668 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5669 5670 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5671 #ifdef ARM32_NEW_VM_LAYOUT 5672 PTE_SYNC(&pde[slot]); 5673 #else 5674 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5675 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5676 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5677 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5678 #endif 5679 5680 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5681 } 5682 5683 /* 5684 * pmap_map_chunk: 5685 * 5686 * Map a chunk of memory using the most efficient mappings 5687 * possible (section, large page, small page) into the 5688 * provided L1 and L2 tables at the specified virtual address. 5689 */ 5690 vsize_t 5691 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5692 int prot, int cache) 5693 { 5694 pd_entry_t *pde = (pd_entry_t *) l1pt; 5695 pt_entry_t *pte, f1, f2s, f2l; 5696 vsize_t resid; 5697 int i; 5698 5699 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5700 5701 if (l1pt == 0) 5702 panic("pmap_map_chunk: no L1 table provided"); 5703 5704 #ifdef VERBOSE_INIT_ARM 5705 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5706 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5707 #endif 5708 5709 switch (cache) { 5710 case PTE_NOCACHE: 5711 default: 5712 f1 = 0; 5713 f2l = 0; 5714 f2s = 0; 5715 break; 5716 5717 case PTE_CACHE: 5718 f1 = pte_l1_s_cache_mode; 5719 f2l = pte_l2_l_cache_mode; 5720 f2s = pte_l2_s_cache_mode; 5721 break; 5722 5723 case PTE_PAGETABLE: 5724 f1 = pte_l1_s_cache_mode_pt; 5725 f2l = pte_l2_l_cache_mode_pt; 5726 f2s = pte_l2_s_cache_mode_pt; 5727 break; 5728 } 5729 5730 size = resid; 5731 5732 while (resid > 0) { 5733 /* See if we can use a section mapping. */ 5734 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5735 #ifdef VERBOSE_INIT_ARM 5736 printf("S"); 5737 #endif 5738 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5739 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5740 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5741 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5742 va += L1_S_SIZE; 5743 pa += L1_S_SIZE; 5744 resid -= L1_S_SIZE; 5745 continue; 5746 } 5747 5748 /* 5749 * Ok, we're going to use an L2 table. Make sure 5750 * one is actually in the corresponding L1 slot 5751 * for the current VA. 5752 */ 5753 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5754 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5755 5756 #ifndef ARM32_NEW_VM_LAYOUT 5757 pte = (pt_entry_t *) 5758 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5759 #else 5760 pte = (pt_entry_t *) kernel_pt_lookup( 5761 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5762 #endif 5763 if (pte == NULL) 5764 panic("pmap_map_chunk: can't find L2 table for VA" 5765 "0x%08lx", va); 5766 5767 /* See if we can use a L2 large page mapping. */ 5768 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5769 #ifdef VERBOSE_INIT_ARM 5770 printf("L"); 5771 #endif 5772 for (i = 0; i < 16; i++) { 5773 #ifndef ARM32_NEW_VM_LAYOUT 5774 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5775 L2_L_PROTO | pa | 5776 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5777 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5778 #else 5779 pte[l2pte_index(va) + i] = 5780 L2_L_PROTO | pa | 5781 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5782 PTE_SYNC(&pte[l2pte_index(va) + i]); 5783 #endif 5784 } 5785 va += L2_L_SIZE; 5786 pa += L2_L_SIZE; 5787 resid -= L2_L_SIZE; 5788 continue; 5789 } 5790 5791 /* Use a small page mapping. */ 5792 #ifdef VERBOSE_INIT_ARM 5793 printf("P"); 5794 #endif 5795 #ifndef ARM32_NEW_VM_LAYOUT 5796 pte[(va >> PGSHIFT) & 0x3ff] = 5797 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5798 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5799 #else 5800 pte[l2pte_index(va)] = 5801 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5802 PTE_SYNC(&pte[l2pte_index(va)]); 5803 #endif 5804 va += PAGE_SIZE; 5805 pa += PAGE_SIZE; 5806 resid -= PAGE_SIZE; 5807 } 5808 #ifdef VERBOSE_INIT_ARM 5809 printf("\n"); 5810 #endif 5811 return (size); 5812 } 5813 5814 /********************** Static device map routines ***************************/ 5815 5816 static const struct pmap_devmap *pmap_devmap_table; 5817 5818 /* 5819 * Register the devmap table. This is provided in case early console 5820 * initialization needs to register mappings created by bootstrap code 5821 * before pmap_devmap_bootstrap() is called. 5822 */ 5823 void 5824 pmap_devmap_register(const struct pmap_devmap *table) 5825 { 5826 5827 pmap_devmap_table = table; 5828 } 5829 5830 /* 5831 * Map all of the static regions in the devmap table, and remember 5832 * the devmap table so other parts of the kernel can look up entries 5833 * later. 5834 */ 5835 void 5836 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5837 { 5838 int i; 5839 5840 pmap_devmap_table = table; 5841 5842 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5843 #ifdef VERBOSE_INIT_ARM 5844 printf("devmap: %08lx -> %08lx @ %08lx\n", 5845 pmap_devmap_table[i].pd_pa, 5846 pmap_devmap_table[i].pd_pa + 5847 pmap_devmap_table[i].pd_size - 1, 5848 pmap_devmap_table[i].pd_va); 5849 #endif 5850 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5851 pmap_devmap_table[i].pd_pa, 5852 pmap_devmap_table[i].pd_size, 5853 pmap_devmap_table[i].pd_prot, 5854 pmap_devmap_table[i].pd_cache); 5855 } 5856 } 5857 5858 const struct pmap_devmap * 5859 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5860 { 5861 uint64_t endpa; 5862 int i; 5863 5864 if (pmap_devmap_table == NULL) 5865 return (NULL); 5866 5867 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5868 5869 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5870 if (pa >= pmap_devmap_table[i].pd_pa && 5871 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5872 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5873 return (&pmap_devmap_table[i]); 5874 } 5875 5876 return (NULL); 5877 } 5878 5879 const struct pmap_devmap * 5880 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5881 { 5882 int i; 5883 5884 if (pmap_devmap_table == NULL) 5885 return (NULL); 5886 5887 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5888 if (va >= pmap_devmap_table[i].pd_va && 5889 va + size - 1 <= pmap_devmap_table[i].pd_va + 5890 pmap_devmap_table[i].pd_size - 1) 5891 return (&pmap_devmap_table[i]); 5892 } 5893 5894 return (NULL); 5895 } 5896 5897 /********************** PTE initialization routines **************************/ 5898 5899 /* 5900 * These routines are called when the CPU type is identified to set up 5901 * the PTE prototypes, cache modes, etc. 5902 * 5903 * The variables are always here, just in case modules need to reference 5904 * them (though, they shouldn't). 5905 */ 5906 5907 pt_entry_t pte_l1_s_cache_mode; 5908 pt_entry_t pte_l1_s_cache_mode_pt; 5909 pt_entry_t pte_l1_s_cache_mask; 5910 5911 pt_entry_t pte_l2_l_cache_mode; 5912 pt_entry_t pte_l2_l_cache_mode_pt; 5913 pt_entry_t pte_l2_l_cache_mask; 5914 5915 pt_entry_t pte_l2_s_cache_mode; 5916 pt_entry_t pte_l2_s_cache_mode_pt; 5917 pt_entry_t pte_l2_s_cache_mask; 5918 5919 pt_entry_t pte_l2_s_prot_u; 5920 pt_entry_t pte_l2_s_prot_w; 5921 pt_entry_t pte_l2_s_prot_mask; 5922 5923 pt_entry_t pte_l1_s_proto; 5924 pt_entry_t pte_l1_c_proto; 5925 pt_entry_t pte_l2_s_proto; 5926 5927 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5928 void (*pmap_zero_page_func)(paddr_t); 5929 5930 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5931 void 5932 pmap_pte_init_generic(void) 5933 { 5934 5935 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5936 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5937 5938 pte_l2_l_cache_mode = L2_B|L2_C; 5939 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5940 5941 pte_l2_s_cache_mode = L2_B|L2_C; 5942 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5943 5944 /* 5945 * If we have a write-through cache, set B and C. If 5946 * we have a write-back cache, then we assume setting 5947 * only C will make those pages write-through. 5948 */ 5949 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5950 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5951 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5952 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5953 } else { 5954 #if ARM_MMU_V6 > 1 5955 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5956 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5957 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5958 #else 5959 pte_l1_s_cache_mode_pt = L1_S_C; 5960 pte_l2_l_cache_mode_pt = L2_C; 5961 pte_l2_s_cache_mode_pt = L2_C; 5962 #endif 5963 } 5964 5965 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5966 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5967 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5968 5969 pte_l1_s_proto = L1_S_PROTO_generic; 5970 pte_l1_c_proto = L1_C_PROTO_generic; 5971 pte_l2_s_proto = L2_S_PROTO_generic; 5972 5973 pmap_copy_page_func = pmap_copy_page_generic; 5974 pmap_zero_page_func = pmap_zero_page_generic; 5975 } 5976 5977 #if defined(CPU_ARM8) 5978 void 5979 pmap_pte_init_arm8(void) 5980 { 5981 5982 /* 5983 * ARM8 is compatible with generic, but we need to use 5984 * the page tables uncached. 5985 */ 5986 pmap_pte_init_generic(); 5987 5988 pte_l1_s_cache_mode_pt = 0; 5989 pte_l2_l_cache_mode_pt = 0; 5990 pte_l2_s_cache_mode_pt = 0; 5991 } 5992 #endif /* CPU_ARM8 */ 5993 5994 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5995 void 5996 pmap_pte_init_arm9(void) 5997 { 5998 5999 /* 6000 * ARM9 is compatible with generic, but we want to use 6001 * write-through caching for now. 6002 */ 6003 pmap_pte_init_generic(); 6004 6005 pte_l1_s_cache_mode = L1_S_C; 6006 pte_l2_l_cache_mode = L2_C; 6007 pte_l2_s_cache_mode = L2_C; 6008 6009 pte_l1_s_cache_mode_pt = L1_S_C; 6010 pte_l2_l_cache_mode_pt = L2_C; 6011 pte_l2_s_cache_mode_pt = L2_C; 6012 } 6013 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6014 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6015 6016 #if defined(CPU_ARM10) 6017 void 6018 pmap_pte_init_arm10(void) 6019 { 6020 6021 /* 6022 * ARM10 is compatible with generic, but we want to use 6023 * write-through caching for now. 6024 */ 6025 pmap_pte_init_generic(); 6026 6027 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6028 pte_l2_l_cache_mode = L2_B | L2_C; 6029 pte_l2_s_cache_mode = L2_B | L2_C; 6030 6031 pte_l1_s_cache_mode_pt = L1_S_C; 6032 pte_l2_l_cache_mode_pt = L2_C; 6033 pte_l2_s_cache_mode_pt = L2_C; 6034 6035 } 6036 #endif /* CPU_ARM10 */ 6037 6038 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6039 void 6040 pmap_pte_init_arm11(void) 6041 { 6042 6043 /* 6044 * ARM11 is compatible with generic, but we want to use 6045 * write-through caching for now. 6046 */ 6047 pmap_pte_init_generic(); 6048 6049 pte_l1_s_cache_mode = L1_S_C; 6050 pte_l2_l_cache_mode = L2_C; 6051 pte_l2_s_cache_mode = L2_C; 6052 6053 pte_l1_s_cache_mode_pt = L1_S_C; 6054 pte_l2_l_cache_mode_pt = L2_C; 6055 pte_l2_s_cache_mode_pt = L2_C; 6056 } 6057 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6058 6059 #if ARM_MMU_SA1 == 1 6060 void 6061 pmap_pte_init_sa1(void) 6062 { 6063 6064 /* 6065 * The StrongARM SA-1 cache does not have a write-through 6066 * mode. So, do the generic initialization, then reset 6067 * the page table cache mode to B=1,C=1, and note that 6068 * the PTEs need to be sync'd. 6069 */ 6070 pmap_pte_init_generic(); 6071 6072 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6073 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6074 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6075 6076 pmap_needs_pte_sync = 1; 6077 } 6078 #endif /* ARM_MMU_SA1 == 1*/ 6079 6080 #if ARM_MMU_XSCALE == 1 6081 #if (ARM_NMMUS > 1) 6082 static u_int xscale_use_minidata; 6083 #endif 6084 6085 void 6086 pmap_pte_init_xscale(void) 6087 { 6088 uint32_t auxctl; 6089 int write_through = 0; 6090 6091 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6092 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6093 6094 pte_l2_l_cache_mode = L2_B|L2_C; 6095 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6096 6097 pte_l2_s_cache_mode = L2_B|L2_C; 6098 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6099 6100 pte_l1_s_cache_mode_pt = L1_S_C; 6101 pte_l2_l_cache_mode_pt = L2_C; 6102 pte_l2_s_cache_mode_pt = L2_C; 6103 6104 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6105 /* 6106 * The XScale core has an enhanced mode where writes that 6107 * miss the cache cause a cache line to be allocated. This 6108 * is significantly faster than the traditional, write-through 6109 * behavior of this case. 6110 */ 6111 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6112 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6113 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6114 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6115 6116 #ifdef XSCALE_CACHE_WRITE_THROUGH 6117 /* 6118 * Some versions of the XScale core have various bugs in 6119 * their cache units, the work-around for which is to run 6120 * the cache in write-through mode. Unfortunately, this 6121 * has a major (negative) impact on performance. So, we 6122 * go ahead and run fast-and-loose, in the hopes that we 6123 * don't line up the planets in a way that will trip the 6124 * bugs. 6125 * 6126 * However, we give you the option to be slow-but-correct. 6127 */ 6128 write_through = 1; 6129 #elif defined(XSCALE_CACHE_WRITE_BACK) 6130 /* force write back cache mode */ 6131 write_through = 0; 6132 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6133 /* 6134 * Intel PXA2[15]0 processors are known to have a bug in 6135 * write-back cache on revision 4 and earlier (stepping 6136 * A[01] and B[012]). Fixed for C0 and later. 6137 */ 6138 { 6139 uint32_t id, type; 6140 6141 id = cpufunc_id(); 6142 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6143 6144 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6145 if ((id & CPU_ID_REVISION_MASK) < 5) { 6146 /* write through for stepping A0-1 and B0-2 */ 6147 write_through = 1; 6148 } 6149 } 6150 } 6151 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6152 6153 if (write_through) { 6154 pte_l1_s_cache_mode = L1_S_C; 6155 pte_l2_l_cache_mode = L2_C; 6156 pte_l2_s_cache_mode = L2_C; 6157 } 6158 6159 #if (ARM_NMMUS > 1) 6160 xscale_use_minidata = 1; 6161 #endif 6162 6163 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6164 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6165 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6166 6167 pte_l1_s_proto = L1_S_PROTO_xscale; 6168 pte_l1_c_proto = L1_C_PROTO_xscale; 6169 pte_l2_s_proto = L2_S_PROTO_xscale; 6170 6171 pmap_copy_page_func = pmap_copy_page_xscale; 6172 pmap_zero_page_func = pmap_zero_page_xscale; 6173 6174 /* 6175 * Disable ECC protection of page table access, for now. 6176 */ 6177 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6178 auxctl &= ~XSCALE_AUXCTL_P; 6179 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6180 } 6181 6182 /* 6183 * xscale_setup_minidata: 6184 * 6185 * Set up the mini-data cache clean area. We require the 6186 * caller to allocate the right amount of physically and 6187 * virtually contiguous space. 6188 */ 6189 void 6190 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6191 { 6192 extern vaddr_t xscale_minidata_clean_addr; 6193 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6194 pd_entry_t *pde = (pd_entry_t *) l1pt; 6195 pt_entry_t *pte; 6196 vsize_t size; 6197 uint32_t auxctl; 6198 6199 xscale_minidata_clean_addr = va; 6200 6201 /* Round it to page size. */ 6202 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6203 6204 for (; size != 0; 6205 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6206 #ifndef ARM32_NEW_VM_LAYOUT 6207 pte = (pt_entry_t *) 6208 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6209 #else 6210 pte = (pt_entry_t *) kernel_pt_lookup( 6211 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6212 #endif 6213 if (pte == NULL) 6214 panic("xscale_setup_minidata: can't find L2 table for " 6215 "VA 0x%08lx", va); 6216 #ifndef ARM32_NEW_VM_LAYOUT 6217 pte[(va >> PGSHIFT) & 0x3ff] = 6218 #else 6219 pte[l2pte_index(va)] = 6220 #endif 6221 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6222 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6223 } 6224 6225 /* 6226 * Configure the mini-data cache for write-back with 6227 * read/write-allocate. 6228 * 6229 * NOTE: In order to reconfigure the mini-data cache, we must 6230 * make sure it contains no valid data! In order to do that, 6231 * we must issue a global data cache invalidate command! 6232 * 6233 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6234 * THIS IS VERY IMPORTANT! 6235 */ 6236 6237 /* Invalidate data and mini-data. */ 6238 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6239 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6240 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6241 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6242 } 6243 6244 /* 6245 * Change the PTEs for the specified kernel mappings such that they 6246 * will use the mini data cache instead of the main data cache. 6247 */ 6248 void 6249 pmap_uarea(vaddr_t va) 6250 { 6251 struct l2_bucket *l2b; 6252 pt_entry_t *ptep, *sptep, pte; 6253 vaddr_t next_bucket, eva; 6254 6255 #if (ARM_NMMUS > 1) 6256 if (xscale_use_minidata == 0) 6257 return; 6258 #endif 6259 6260 eva = va + USPACE; 6261 6262 while (va < eva) { 6263 next_bucket = L2_NEXT_BUCKET(va); 6264 if (next_bucket > eva) 6265 next_bucket = eva; 6266 6267 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6268 KDASSERT(l2b != NULL); 6269 6270 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6271 6272 while (va < next_bucket) { 6273 pte = *ptep; 6274 if (!l2pte_minidata(pte)) { 6275 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6276 cpu_tlb_flushD_SE(va); 6277 *ptep = pte & ~L2_B; 6278 } 6279 ptep++; 6280 va += PAGE_SIZE; 6281 } 6282 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6283 } 6284 cpu_cpwait(); 6285 } 6286 #endif /* ARM_MMU_XSCALE == 1 */ 6287 6288 /* 6289 * return the PA of the current L1 table, for use when handling a crash dump 6290 */ 6291 uint32_t pmap_kernel_L1_addr(void) 6292 { 6293 return pmap_kernel()->pm_l1->l1_physaddr; 6294 } 6295 6296 #if defined(DDB) 6297 /* 6298 * A couple of ddb-callable functions for dumping pmaps 6299 */ 6300 void pmap_dump_all(void); 6301 void pmap_dump(pmap_t); 6302 6303 void 6304 pmap_dump_all(void) 6305 { 6306 pmap_t pm; 6307 6308 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6309 if (pm == pmap_kernel()) 6310 continue; 6311 pmap_dump(pm); 6312 printf("\n"); 6313 } 6314 } 6315 6316 static pt_entry_t ncptes[64]; 6317 static void pmap_dump_ncpg(pmap_t); 6318 6319 void 6320 pmap_dump(pmap_t pm) 6321 { 6322 struct l2_dtable *l2; 6323 struct l2_bucket *l2b; 6324 pt_entry_t *ptep, pte; 6325 vaddr_t l2_va, l2b_va, va; 6326 int i, j, k, occ, rows = 0; 6327 6328 if (pm == pmap_kernel()) 6329 printf("pmap_kernel (%p): ", pm); 6330 else 6331 printf("user pmap (%p): ", pm); 6332 6333 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6334 6335 l2_va = 0; 6336 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6337 l2 = pm->pm_l2[i]; 6338 6339 if (l2 == NULL || l2->l2_occupancy == 0) 6340 continue; 6341 6342 l2b_va = l2_va; 6343 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6344 l2b = &l2->l2_bucket[j]; 6345 6346 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6347 continue; 6348 6349 ptep = l2b->l2b_kva; 6350 6351 for (k = 0; k < 256 && ptep[k] == 0; k++) 6352 ; 6353 6354 k &= ~63; 6355 occ = l2b->l2b_occupancy; 6356 va = l2b_va + (k * 4096); 6357 for (; k < 256; k++, va += 0x1000) { 6358 char ch = ' '; 6359 if ((k % 64) == 0) { 6360 if ((rows % 8) == 0) { 6361 printf( 6362 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6363 } 6364 printf("%08lx: ", va); 6365 } 6366 6367 ncptes[k & 63] = 0; 6368 pte = ptep[k]; 6369 if (pte == 0) { 6370 ch = '.'; 6371 } else { 6372 occ--; 6373 switch (pte & 0x0c) { 6374 case 0x00: 6375 ch = 'D'; /* No cache No buff */ 6376 break; 6377 case 0x04: 6378 ch = 'B'; /* No cache buff */ 6379 break; 6380 case 0x08: 6381 if (pte & 0x40) 6382 ch = 'm'; 6383 else 6384 ch = 'C'; /* Cache No buff */ 6385 break; 6386 case 0x0c: 6387 ch = 'F'; /* Cache Buff */ 6388 break; 6389 } 6390 6391 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6392 ch += 0x20; 6393 6394 if ((pte & 0xc) == 0) 6395 ncptes[k & 63] = pte; 6396 } 6397 6398 if ((k % 64) == 63) { 6399 rows++; 6400 printf("%c\n", ch); 6401 pmap_dump_ncpg(pm); 6402 if (occ == 0) 6403 break; 6404 } else 6405 printf("%c", ch); 6406 } 6407 } 6408 } 6409 } 6410 6411 static void 6412 pmap_dump_ncpg(pmap_t pm) 6413 { 6414 struct vm_page *pg; 6415 struct vm_page_md *md; 6416 struct pv_entry *pv; 6417 int i; 6418 6419 for (i = 0; i < 63; i++) { 6420 if (ncptes[i] == 0) 6421 continue; 6422 6423 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6424 if (pg == NULL) 6425 continue; 6426 md = VM_PAGE_TO_MD(pg); 6427 6428 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6429 VM_PAGE_TO_PHYS(pg), 6430 md->krw_mappings, md->kro_mappings, 6431 md->urw_mappings, md->uro_mappings); 6432 6433 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6434 printf(" %c va 0x%08lx, flags 0x%x\n", 6435 (pm == pv->pv_pmap) ? '*' : ' ', 6436 pv->pv_va, pv->pv_flags); 6437 } 6438 } 6439 } 6440 #endif 6441 6442 #ifdef PMAP_STEAL_MEMORY 6443 void 6444 pmap_boot_pageadd(pv_addr_t *newpv) 6445 { 6446 pv_addr_t *pv, *npv; 6447 6448 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6449 if (newpv->pv_pa < pv->pv_va) { 6450 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6451 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6452 newpv->pv_size += pv->pv_size; 6453 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6454 } 6455 pv = NULL; 6456 } else { 6457 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6458 pv = npv) { 6459 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6460 KASSERT(pv->pv_pa < newpv->pv_pa); 6461 if (newpv->pv_pa > npv->pv_pa) 6462 continue; 6463 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6464 pv->pv_size += newpv->pv_size; 6465 return; 6466 } 6467 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6468 break; 6469 newpv->pv_size += npv->pv_size; 6470 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6471 SLIST_REMOVE_AFTER(newpv, pv_list); 6472 return; 6473 } 6474 } 6475 } 6476 6477 if (pv) { 6478 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6479 } else { 6480 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6481 } 6482 } 6483 6484 void 6485 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6486 pv_addr_t *rpv) 6487 { 6488 pv_addr_t *pv, **pvp; 6489 struct vm_physseg *ps; 6490 size_t i; 6491 6492 KASSERT(amount & PGOFSET); 6493 KASSERT((mask & PGOFSET) == 0); 6494 KASSERT((match & PGOFSET) == 0); 6495 KASSERT(amount != 0); 6496 6497 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6498 (pv = *pvp) != NULL; 6499 pvp = &SLIST_NEXT(pv, pv_list)) { 6500 pv_addr_t *newpv; 6501 psize_t off; 6502 /* 6503 * If this entry is too small to satify the request... 6504 */ 6505 KASSERT(pv->pv_size > 0); 6506 if (pv->pv_size < amount) 6507 continue; 6508 6509 for (off = 0; off <= mask; off += PAGE_SIZE) { 6510 if (((pv->pv_pa + off) & mask) == match 6511 && off + amount <= pv->pv_size) 6512 break; 6513 } 6514 if (off > mask) 6515 continue; 6516 6517 rpv->pv_va = pv->pv_va + off; 6518 rpv->pv_pa = pv->pv_pa + off; 6519 rpv->pv_size = amount; 6520 pv->pv_size -= amount; 6521 if (pv->pv_size == 0) { 6522 KASSERT(off == 0); 6523 KASSERT((vaddr_t) pv == rpv->pv_va); 6524 *pvp = SLIST_NEXT(pv, pv_list); 6525 } else if (off == 0) { 6526 KASSERT((vaddr_t) pv == rpv->pv_va); 6527 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6528 *newpv = *pv; 6529 newpv->pv_pa += amount; 6530 newpv->pv_va += amount; 6531 *pvp = newpv; 6532 } else if (off < pv->pv_size) { 6533 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6534 *newpv = *pv; 6535 newpv->pv_size -= off; 6536 newpv->pv_pa += off + amount; 6537 newpv->pv_va += off + amount; 6538 6539 SLIST_NEXT(pv, pv_list) = newpv; 6540 pv->pv_size = off; 6541 } else { 6542 KASSERT((vaddr_t) pv != rpv->pv_va); 6543 } 6544 memset((void *)rpv->pv_va, 0, amount); 6545 return; 6546 } 6547 6548 if (vm_nphysseg == 0) 6549 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6550 6551 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6552 (pv = *pvp) != NULL; 6553 pvp = &SLIST_NEXT(pv, pv_list)) { 6554 if (SLIST_NEXT(pv, pv_list) == NULL) 6555 break; 6556 } 6557 KASSERT(mask == 0); 6558 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6559 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6560 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6561 rpv->pv_va = pv->pv_va; 6562 rpv->pv_pa = pv->pv_pa; 6563 rpv->pv_size = amount; 6564 *pvp = NULL; 6565 pmap_map_chunk(kernel_l1pt.pv_va, 6566 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6567 ptoa(ps->avail_start), 6568 amount - pv->pv_size, 6569 VM_PROT_READ|VM_PROT_WRITE, 6570 PTE_CACHE); 6571 ps->avail_start += atop(amount - pv->pv_size); 6572 /* 6573 * If we consumed the entire physseg, remove it. 6574 */ 6575 if (ps->avail_start == ps->avail_end) { 6576 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6577 ps[0] = ps[1]; 6578 } 6579 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6580 return; 6581 } 6582 } 6583 6584 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6585 } 6586 6587 vaddr_t 6588 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6589 { 6590 pv_addr_t pv; 6591 6592 pmap_boot_pagealloc(size, 0, 0, &pv); 6593 6594 return pv.pv_va; 6595 } 6596 #endif /* PMAP_STEAL_MEMORY */ 6597 6598 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6599 { 6600 sysctl_createv(clog, 0, NULL, NULL, 6601 CTLFLAG_PERMANENT, 6602 CTLTYPE_NODE, "machdep", NULL, 6603 NULL, 0, NULL, 0, 6604 CTL_MACHDEP, CTL_EOL); 6605 6606 sysctl_createv(clog, 0, NULL, NULL, 6607 CTLFLAG_PERMANENT, 6608 CTLTYPE_INT, "kmpages", 6609 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6610 NULL, 0, &pmap_kmpages, 0, 6611 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6612 } 6613
Indexes created Thu Oct 23 22:10:10 GMT 2025