pmap.c revision 1.211.2.7
1 /* $NetBSD: pmap.c,v 1.211.2.7 2010/02/10 15:48:28 uebayasi Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/pool.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <machine/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.211.2.7 2010/02/10 15:48:28 uebayasi Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 static struct pmap kernel_pmap_store; 258 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 #ifdef PMAPCOUNTERS 308 #define PMAP_EVCNT_INITIALIZER(name) \ 309 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 310 311 #ifdef PMAP_CACHE_VIPT 312 static struct evcnt pmap_ev_vac_clean_one = 313 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 314 static struct evcnt pmap_ev_vac_flush_one = 315 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_lots = 317 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 318 static struct evcnt pmap_ev_vac_flush_lots2 = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 324 325 static struct evcnt pmap_ev_vac_color_new = 326 PMAP_EVCNT_INITIALIZER("new page color"); 327 static struct evcnt pmap_ev_vac_color_reuse = 328 PMAP_EVCNT_INITIALIZER("ok first page color"); 329 static struct evcnt pmap_ev_vac_color_ok = 330 PMAP_EVCNT_INITIALIZER("ok page color"); 331 static struct evcnt pmap_ev_vac_color_blind = 332 PMAP_EVCNT_INITIALIZER("blind page color"); 333 static struct evcnt pmap_ev_vac_color_change = 334 PMAP_EVCNT_INITIALIZER("change page color"); 335 static struct evcnt pmap_ev_vac_color_erase = 336 PMAP_EVCNT_INITIALIZER("erase page color"); 337 static struct evcnt pmap_ev_vac_color_none = 338 PMAP_EVCNT_INITIALIZER("no page color"); 339 static struct evcnt pmap_ev_vac_color_restore = 340 PMAP_EVCNT_INITIALIZER("restore page color"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 350 #endif 351 352 static struct evcnt pmap_ev_mappings = 353 PMAP_EVCNT_INITIALIZER("pages mapped"); 354 static struct evcnt pmap_ev_unmappings = 355 PMAP_EVCNT_INITIALIZER("pages unmapped"); 356 static struct evcnt pmap_ev_remappings = 357 PMAP_EVCNT_INITIALIZER("pages remapped"); 358 359 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 360 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 362 363 static struct evcnt pmap_ev_kernel_mappings = 364 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 365 static struct evcnt pmap_ev_kernel_unmappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 367 static struct evcnt pmap_ev_kernel_remappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 373 374 static struct evcnt pmap_ev_kenter_mappings = 375 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 376 static struct evcnt pmap_ev_kenter_unmappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 378 static struct evcnt pmap_ev_kenter_remappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 380 static struct evcnt pmap_ev_pt_mappings = 381 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 382 383 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 387 388 #ifdef PMAP_CACHE_VIPT 389 static struct evcnt pmap_ev_exec_mappings = 390 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 391 static struct evcnt pmap_ev_exec_cached = 392 PMAP_EVCNT_INITIALIZER("exec pages cached"); 393 394 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 396 397 static struct evcnt pmap_ev_exec_synced = 398 PMAP_EVCNT_INITIALIZER("exec pages synced"); 399 static struct evcnt pmap_ev_exec_synced_map = 400 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 401 static struct evcnt pmap_ev_exec_synced_unmap = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 403 static struct evcnt pmap_ev_exec_synced_remap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 405 static struct evcnt pmap_ev_exec_synced_clearbit = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 407 static struct evcnt pmap_ev_exec_synced_kremove = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 409 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 416 417 static struct evcnt pmap_ev_exec_discarded_unmap = 418 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 419 static struct evcnt pmap_ev_exec_discarded_zero = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 421 static struct evcnt pmap_ev_exec_discarded_copy = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 423 static struct evcnt pmap_ev_exec_discarded_page_protect = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 425 static struct evcnt pmap_ev_exec_discarded_clearbit = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 427 static struct evcnt pmap_ev_exec_discarded_kremove = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 429 430 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 436 #endif /* PMAP_CACHE_VIPT */ 437 438 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 439 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 440 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 441 442 EVCNT_ATTACH_STATIC(pmap_ev_updates); 443 EVCNT_ATTACH_STATIC(pmap_ev_collects); 444 EVCNT_ATTACH_STATIC(pmap_ev_activations); 445 446 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 447 #else 448 #define PMAPCOUNT(x) ((void)0) 449 #endif 450 451 /* 452 * pmap copy/zero page, and mem(5) hook point 453 */ 454 static pt_entry_t *csrc_pte, *cdst_pte; 455 static vaddr_t csrcp, cdstp; 456 vaddr_t memhook; /* used by mem.c */ 457 kmutex_t memlock; /* used by mem.c */ 458 void *zeropage; /* used by mem.c */ 459 extern void *msgbufaddr; 460 int pmap_kmpages; 461 /* 462 * Flag to indicate if pmap_init() has done its thing 463 */ 464 bool pmap_initialized; 465 466 /* 467 * Misc. locking data structures 468 */ 469 470 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 471 static struct lock pmap_main_lock; 472 473 #define PMAP_MAP_TO_HEAD_LOCK() \ 474 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 475 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 476 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 477 #define PMAP_HEAD_TO_MAP_LOCK() \ 478 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 479 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 480 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 481 #else 482 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 483 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 484 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 485 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 486 #endif 487 488 #define pmap_acquire_pmap_lock(pm) \ 489 do { \ 490 if ((pm) != pmap_kernel()) \ 491 mutex_enter(&(pm)->pm_lock); \ 492 } while (/*CONSTCOND*/0) 493 494 #define pmap_release_pmap_lock(pm) \ 495 do { \ 496 if ((pm) != pmap_kernel()) \ 497 mutex_exit(&(pm)->pm_lock); \ 498 } while (/*CONSTCOND*/0) 499 500 501 /* 502 * Metadata for L1 translation tables. 503 */ 504 struct l1_ttable { 505 /* Entry on the L1 Table list */ 506 SLIST_ENTRY(l1_ttable) l1_link; 507 508 /* Entry on the L1 Least Recently Used list */ 509 TAILQ_ENTRY(l1_ttable) l1_lru; 510 511 /* Track how many domains are allocated from this L1 */ 512 volatile u_int l1_domain_use_count; 513 514 /* 515 * A free-list of domain numbers for this L1. 516 * We avoid using ffs() and a bitmap to track domains since ffs() 517 * is slow on ARM. 518 */ 519 u_int8_t l1_domain_first; 520 u_int8_t l1_domain_free[PMAP_DOMAINS]; 521 522 /* Physical address of this L1 page table */ 523 paddr_t l1_physaddr; 524 525 /* KVA of this L1 page table */ 526 pd_entry_t *l1_kva; 527 }; 528 529 /* 530 * Convert a virtual address into its L1 table index. That is, the 531 * index used to locate the L2 descriptor table pointer in an L1 table. 532 * This is basically used to index l1->l1_kva[]. 533 * 534 * Each L2 descriptor table represents 1MB of VA space. 535 */ 536 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 537 538 /* 539 * L1 Page Tables are tracked using a Least Recently Used list. 540 * - New L1s are allocated from the HEAD. 541 * - Freed L1s are added to the TAIl. 542 * - Recently accessed L1s (where an 'access' is some change to one of 543 * the userland pmaps which owns this L1) are moved to the TAIL. 544 */ 545 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 546 static struct simplelock l1_lru_lock; 547 548 /* 549 * A list of all L1 tables 550 */ 551 static SLIST_HEAD(, l1_ttable) l1_list; 552 553 /* 554 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 555 * 556 * This is normally 16MB worth L2 page descriptors for any given pmap. 557 * Reference counts are maintained for L2 descriptors so they can be 558 * freed when empty. 559 */ 560 struct l2_dtable { 561 /* The number of L2 page descriptors allocated to this l2_dtable */ 562 u_int l2_occupancy; 563 564 /* List of L2 page descriptors */ 565 struct l2_bucket { 566 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 567 paddr_t l2b_phys; /* Physical address of same */ 568 u_short l2b_l1idx; /* This L2 table's L1 index */ 569 u_short l2b_occupancy; /* How many active descriptors */ 570 } l2_bucket[L2_BUCKET_SIZE]; 571 }; 572 573 /* 574 * Given an L1 table index, calculate the corresponding l2_dtable index 575 * and bucket index within the l2_dtable. 576 */ 577 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 578 (L2_SIZE - 1)) 579 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 580 581 /* 582 * Given a virtual address, this macro returns the 583 * virtual address required to drop into the next L2 bucket. 584 */ 585 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 586 587 /* 588 * L2 allocation. 589 */ 590 #define pmap_alloc_l2_dtable() \ 591 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 592 #define pmap_free_l2_dtable(l2) \ 593 pool_cache_put(&pmap_l2dtable_cache, (l2)) 594 #define pmap_alloc_l2_ptp(pap) \ 595 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 596 PR_NOWAIT, (pap))) 597 598 /* 599 * We try to map the page tables write-through, if possible. However, not 600 * all CPUs have a write-through cache mode, so on those we have to sync 601 * the cache when we frob page tables. 602 * 603 * We try to evaluate this at compile time, if possible. However, it's 604 * not always possible to do that, hence this run-time var. 605 */ 606 int pmap_needs_pte_sync; 607 608 /* 609 * Real definition of pv_entry. 610 */ 611 struct pv_entry { 612 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 613 pmap_t pv_pmap; /* pmap where mapping lies */ 614 vaddr_t pv_va; /* virtual address for mapping */ 615 u_int pv_flags; /* flags */ 616 }; 617 618 /* 619 * Macro to determine if a mapping might be resident in the 620 * instruction cache and/or TLB 621 */ 622 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 623 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 624 625 /* 626 * Macro to determine if a mapping might be resident in the 627 * data cache and/or TLB 628 */ 629 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 630 631 /* 632 * Local prototypes 633 */ 634 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 635 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 636 pt_entry_t **); 637 static bool pmap_is_current(pmap_t); 638 static bool pmap_is_cached(pmap_t); 639 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 640 pmap_t, vaddr_t, u_int); 641 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 642 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 643 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 644 u_int, u_int); 645 646 static void pmap_pinit(pmap_t); 647 static int pmap_pmap_ctor(void *, void *, int); 648 649 static void pmap_alloc_l1(pmap_t); 650 static void pmap_free_l1(pmap_t); 651 static void pmap_use_l1(pmap_t); 652 653 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 654 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 655 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 656 static int pmap_l2ptp_ctor(void *, void *, int); 657 static int pmap_l2dtable_ctor(void *, void *, int); 658 659 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 660 #ifdef PMAP_CACHE_VIVT 661 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 662 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 663 #endif 664 665 static void pmap_clearbit(struct vm_page *, u_int); 666 #ifdef PMAP_CACHE_VIVT 667 static int pmap_clean_page(struct pv_entry *, bool); 668 #endif 669 #ifdef PMAP_CACHE_VIPT 670 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 671 enum pmap_flush_op { 672 PMAP_FLUSH_PRIMARY, 673 PMAP_FLUSH_SECONDARY, 674 PMAP_CLEAN_PRIMARY 675 }; 676 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 677 #endif 678 static void pmap_page_remove(struct vm_page *); 679 680 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 681 static vaddr_t kernel_pt_lookup(paddr_t); 682 683 684 /* 685 * External function prototypes 686 */ 687 extern void bzero_page(vaddr_t); 688 extern void bcopy_page(vaddr_t, vaddr_t); 689 690 /* 691 * Misc variables 692 */ 693 vaddr_t virtual_avail; 694 vaddr_t virtual_end; 695 vaddr_t pmap_curmaxkvaddr; 696 697 paddr_t avail_start; 698 paddr_t avail_end; 699 700 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 701 pv_addr_t kernelpages; 702 pv_addr_t kernel_l1pt; 703 pv_addr_t systempage; 704 705 /* Function to set the debug level of the pmap code */ 706 707 #ifdef PMAP_DEBUG 708 void 709 pmap_debug(int level) 710 { 711 pmap_debug_level = level; 712 printf("pmap_debug: level=%d\n", pmap_debug_level); 713 } 714 #endif /* PMAP_DEBUG */ 715 716 /* 717 * A bunch of routines to conditionally flush the caches/TLB depending 718 * on whether the specified pmap actually needs to be flushed at any 719 * given time. 720 */ 721 static inline void 722 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 723 { 724 725 if (pm->pm_cstate.cs_tlb_id) 726 cpu_tlb_flushID_SE(va); 727 } 728 729 static inline void 730 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 731 { 732 733 if (pm->pm_cstate.cs_tlb_d) 734 cpu_tlb_flushD_SE(va); 735 } 736 737 static inline void 738 pmap_tlb_flushID(pmap_t pm) 739 { 740 741 if (pm->pm_cstate.cs_tlb_id) { 742 cpu_tlb_flushID(); 743 pm->pm_cstate.cs_tlb = 0; 744 } 745 } 746 747 static inline void 748 pmap_tlb_flushD(pmap_t pm) 749 { 750 751 if (pm->pm_cstate.cs_tlb_d) { 752 cpu_tlb_flushD(); 753 pm->pm_cstate.cs_tlb_d = 0; 754 } 755 } 756 757 #ifdef PMAP_CACHE_VIVT 758 static inline void 759 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 760 { 761 if (pm->pm_cstate.cs_cache_id) { 762 cpu_idcache_wbinv_range(va, len); 763 } 764 } 765 766 static inline void 767 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 768 bool do_inv, bool rd_only) 769 { 770 771 if (pm->pm_cstate.cs_cache_d) { 772 if (do_inv) { 773 if (rd_only) 774 cpu_dcache_inv_range(va, len); 775 else 776 cpu_dcache_wbinv_range(va, len); 777 } else 778 if (!rd_only) 779 cpu_dcache_wb_range(va, len); 780 } 781 } 782 783 static inline void 784 pmap_idcache_wbinv_all(pmap_t pm) 785 { 786 if (pm->pm_cstate.cs_cache_id) { 787 cpu_idcache_wbinv_all(); 788 pm->pm_cstate.cs_cache = 0; 789 } 790 } 791 792 static inline void 793 pmap_dcache_wbinv_all(pmap_t pm) 794 { 795 if (pm->pm_cstate.cs_cache_d) { 796 cpu_dcache_wbinv_all(); 797 pm->pm_cstate.cs_cache_d = 0; 798 } 799 } 800 #endif /* PMAP_CACHE_VIVT */ 801 802 static inline bool 803 pmap_is_current(pmap_t pm) 804 { 805 806 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 807 return true; 808 809 return false; 810 } 811 812 static inline bool 813 pmap_is_cached(pmap_t pm) 814 { 815 816 if (pm == pmap_kernel() || pmap_recent_user == NULL || 817 pmap_recent_user == pm) 818 return (true); 819 820 return false; 821 } 822 823 /* 824 * PTE_SYNC_CURRENT: 825 * 826 * Make sure the pte is written out to RAM. 827 * We need to do this for one of two cases: 828 * - We're dealing with the kernel pmap 829 * - There is no pmap active in the cache/tlb. 830 * - The specified pmap is 'active' in the cache/tlb. 831 */ 832 #ifdef PMAP_INCLUDE_PTE_SYNC 833 #define PTE_SYNC_CURRENT(pm, ptep) \ 834 do { \ 835 if (PMAP_NEEDS_PTE_SYNC && \ 836 pmap_is_cached(pm)) \ 837 PTE_SYNC(ptep); \ 838 } while (/*CONSTCOND*/0) 839 #else 840 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 841 #endif 842 843 /* 844 * main pv_entry manipulation functions: 845 * pmap_enter_pv: enter a mapping onto a vm_page list 846 * pmap_remove_pv: remove a mappiing from a vm_page list 847 * 848 * NOTE: pmap_enter_pv expects to lock the pvh itself 849 * pmap_remove_pv expects te caller to lock the pvh before calling 850 */ 851 852 /* 853 * pmap_enter_pv: enter a mapping onto a vm_page lst 854 * 855 * => caller should hold the proper lock on pmap_main_lock 856 * => caller should have pmap locked 857 * => we will gain the lock on the vm_page and allocate the new pv_entry 858 * => caller should adjust ptp's wire_count before calling 859 * => caller should not adjust pmap's wire_count 860 */ 861 static void 862 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 863 vaddr_t va, u_int flags) 864 { 865 struct pv_entry **pvp; 866 867 NPDEBUG(PDB_PVDUMP, 868 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 869 870 pv->pv_pmap = pm; 871 pv->pv_va = va; 872 pv->pv_flags = flags; 873 874 simple_lock(&md->pvh_slock); /* lock vm_page */ 875 pvp = &SLIST_FIRST(&md->pvh_list); 876 #ifdef PMAP_CACHE_VIPT 877 /* 878 * Insert unmanaged entries, writeable first, at the head of 879 * the pv list. 880 */ 881 if (__predict_true((flags & PVF_KENTRY) == 0)) { 882 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 883 pvp = &SLIST_NEXT(*pvp, pv_link); 884 } else if ((flags & PVF_WRITE) == 0) { 885 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 886 pvp = &SLIST_NEXT(*pvp, pv_link); 887 } 888 #endif 889 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 890 *pvp = pv; /* ... locked list */ 891 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 892 #ifdef PMAP_CACHE_VIPT 893 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 894 md->pvh_attrs |= PVF_KMOD; 895 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 896 md->pvh_attrs |= PVF_DIRTY; 897 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 898 #endif 899 if (pm == pmap_kernel()) { 900 PMAPCOUNT(kernel_mappings); 901 if (flags & PVF_WRITE) 902 md->krw_mappings++; 903 else 904 md->kro_mappings++; 905 } else { 906 if (flags & PVF_WRITE) 907 md->urw_mappings++; 908 else 909 md->uro_mappings++; 910 } 911 912 #ifdef PMAP_CACHE_VIPT 913 /* 914 * If this is an exec mapping and its the first exec mapping 915 * for this page, make sure to sync the I-cache. 916 */ 917 if (PV_IS_EXEC_P(flags)) { 918 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 919 pmap_syncicache_page(md, pa); 920 PMAPCOUNT(exec_synced_map); 921 } 922 PMAPCOUNT(exec_mappings); 923 } 924 #endif 925 926 PMAPCOUNT(mappings); 927 simple_unlock(&md->pvh_slock); /* unlock, done! */ 928 929 if (pv->pv_flags & PVF_WIRED) 930 ++pm->pm_stats.wired_count; 931 } 932 933 /* 934 * 935 * pmap_find_pv: Find a pv entry 936 * 937 * => caller should hold lock on vm_page 938 */ 939 static inline struct pv_entry * 940 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 941 { 942 struct pv_entry *pv; 943 944 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 945 if (pm == pv->pv_pmap && va == pv->pv_va) 946 break; 947 } 948 949 return (pv); 950 } 951 952 /* 953 * pmap_remove_pv: try to remove a mapping from a pv_list 954 * 955 * => caller should hold proper lock on pmap_main_lock 956 * => pmap should be locked 957 * => caller should hold lock on vm_page [so that attrs can be adjusted] 958 * => caller should adjust ptp's wire_count and free PTP if needed 959 * => caller should NOT adjust pmap's wire_count 960 * => we return the removed pv 961 */ 962 static struct pv_entry * 963 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 964 { 965 struct pv_entry *pv, **prevptr; 966 967 NPDEBUG(PDB_PVDUMP, 968 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 969 970 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 971 pv = *prevptr; 972 973 while (pv) { 974 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 975 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 976 "%p\n", pm, md)); 977 if (pv->pv_flags & PVF_WIRED) { 978 --pm->pm_stats.wired_count; 979 } 980 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 981 if (pm == pmap_kernel()) { 982 PMAPCOUNT(kernel_unmappings); 983 if (pv->pv_flags & PVF_WRITE) 984 md->krw_mappings--; 985 else 986 md->kro_mappings--; 987 } else { 988 if (pv->pv_flags & PVF_WRITE) 989 md->urw_mappings--; 990 else 991 md->uro_mappings--; 992 } 993 994 PMAPCOUNT(unmappings); 995 #ifdef PMAP_CACHE_VIPT 996 if (!(pv->pv_flags & PVF_WRITE)) 997 break; 998 /* 999 * If this page has had an exec mapping, then if 1000 * this was the last mapping, discard the contents, 1001 * otherwise sync the i-cache for this page. 1002 */ 1003 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1004 if (SLIST_EMPTY(&md->pvh_list)) { 1005 md->pvh_attrs &= ~PVF_EXEC; 1006 PMAPCOUNT(exec_discarded_unmap); 1007 } else { 1008 pmap_syncicache_page(md, pa); 1009 PMAPCOUNT(exec_synced_unmap); 1010 } 1011 } 1012 #endif /* PMAP_CACHE_VIPT */ 1013 break; 1014 } 1015 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1016 pv = *prevptr; /* advance */ 1017 } 1018 1019 #ifdef PMAP_CACHE_VIPT 1020 /* 1021 * If we no longer have a WRITEABLE KENTRY at the head of list, 1022 * clear the KMOD attribute from the page. 1023 */ 1024 if (SLIST_FIRST(&md->pvh_list) == NULL 1025 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1026 md->pvh_attrs &= ~PVF_KMOD; 1027 1028 /* 1029 * If this was a writeable page and there are no more writeable 1030 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1031 * the contents to memory. 1032 */ 1033 if (md->krw_mappings + md->urw_mappings == 0) 1034 md->pvh_attrs &= ~PVF_WRITE; 1035 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1036 #endif /* PMAP_CACHE_VIPT */ 1037 1038 return(pv); /* return removed pv */ 1039 } 1040 1041 /* 1042 * 1043 * pmap_modify_pv: Update pv flags 1044 * 1045 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1046 * => caller should NOT adjust pmap's wire_count 1047 * => caller must call pmap_vac_me_harder() if writable status of a page 1048 * may have changed. 1049 * => we return the old flags 1050 * 1051 * Modify a physical-virtual mapping in the pv table 1052 */ 1053 static u_int 1054 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1055 u_int clr_mask, u_int set_mask) 1056 { 1057 struct pv_entry *npv; 1058 u_int flags, oflags; 1059 1060 KASSERT((clr_mask & PVF_KENTRY) == 0); 1061 KASSERT((set_mask & PVF_KENTRY) == 0); 1062 1063 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1064 return (0); 1065 1066 NPDEBUG(PDB_PVDUMP, 1067 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1068 1069 /* 1070 * There is at least one VA mapping this page. 1071 */ 1072 1073 if (clr_mask & (PVF_REF | PVF_MOD)) { 1074 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1075 #ifdef PMAP_CACHE_VIPT 1076 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1077 md->pvh_attrs |= PVF_DIRTY; 1078 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1079 #endif 1080 } 1081 1082 oflags = npv->pv_flags; 1083 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1084 1085 if ((flags ^ oflags) & PVF_WIRED) { 1086 if (flags & PVF_WIRED) 1087 ++pm->pm_stats.wired_count; 1088 else 1089 --pm->pm_stats.wired_count; 1090 } 1091 1092 if ((flags ^ oflags) & PVF_WRITE) { 1093 if (pm == pmap_kernel()) { 1094 if (flags & PVF_WRITE) { 1095 md->krw_mappings++; 1096 md->kro_mappings--; 1097 } else { 1098 md->kro_mappings++; 1099 md->krw_mappings--; 1100 } 1101 } else { 1102 if (flags & PVF_WRITE) { 1103 md->urw_mappings++; 1104 md->uro_mappings--; 1105 } else { 1106 md->uro_mappings++; 1107 md->urw_mappings--; 1108 } 1109 } 1110 } 1111 #ifdef PMAP_CACHE_VIPT 1112 if (md->urw_mappings + md->krw_mappings == 0) 1113 md->pvh_attrs &= ~PVF_WRITE; 1114 /* 1115 * We have two cases here: the first is from enter_pv (new exec 1116 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1117 * Since in latter, pmap_enter_pv won't do anything, we just have 1118 * to do what pmap_remove_pv would do. 1119 */ 1120 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1121 || (PV_IS_EXEC_P(md->pvh_attrs) 1122 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1123 pmap_syncicache_page(md, pa); 1124 PMAPCOUNT(exec_synced_remap); 1125 } 1126 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1127 #endif 1128 1129 PMAPCOUNT(remappings); 1130 1131 return (oflags); 1132 } 1133 1134 /* 1135 * Allocate an L1 translation table for the specified pmap. 1136 * This is called at pmap creation time. 1137 */ 1138 static void 1139 pmap_alloc_l1(pmap_t pm) 1140 { 1141 struct l1_ttable *l1; 1142 u_int8_t domain; 1143 1144 /* 1145 * Remove the L1 at the head of the LRU list 1146 */ 1147 simple_lock(&l1_lru_lock); 1148 l1 = TAILQ_FIRST(&l1_lru_list); 1149 KDASSERT(l1 != NULL); 1150 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1151 1152 /* 1153 * Pick the first available domain number, and update 1154 * the link to the next number. 1155 */ 1156 domain = l1->l1_domain_first; 1157 l1->l1_domain_first = l1->l1_domain_free[domain]; 1158 1159 /* 1160 * If there are still free domain numbers in this L1, 1161 * put it back on the TAIL of the LRU list. 1162 */ 1163 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1164 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1165 1166 simple_unlock(&l1_lru_lock); 1167 1168 /* 1169 * Fix up the relevant bits in the pmap structure 1170 */ 1171 pm->pm_l1 = l1; 1172 pm->pm_domain = domain; 1173 } 1174 1175 /* 1176 * Free an L1 translation table. 1177 * This is called at pmap destruction time. 1178 */ 1179 static void 1180 pmap_free_l1(pmap_t pm) 1181 { 1182 struct l1_ttable *l1 = pm->pm_l1; 1183 1184 simple_lock(&l1_lru_lock); 1185 1186 /* 1187 * If this L1 is currently on the LRU list, remove it. 1188 */ 1189 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1190 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1191 1192 /* 1193 * Free up the domain number which was allocated to the pmap 1194 */ 1195 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1196 l1->l1_domain_first = pm->pm_domain; 1197 l1->l1_domain_use_count--; 1198 1199 /* 1200 * The L1 now must have at least 1 free domain, so add 1201 * it back to the LRU list. If the use count is zero, 1202 * put it at the head of the list, otherwise it goes 1203 * to the tail. 1204 */ 1205 if (l1->l1_domain_use_count == 0) 1206 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1207 else 1208 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1209 1210 simple_unlock(&l1_lru_lock); 1211 } 1212 1213 static inline void 1214 pmap_use_l1(pmap_t pm) 1215 { 1216 struct l1_ttable *l1; 1217 1218 /* 1219 * Do nothing if we're in interrupt context. 1220 * Access to an L1 by the kernel pmap must not affect 1221 * the LRU list. 1222 */ 1223 if (cpu_intr_p() || pm == pmap_kernel()) 1224 return; 1225 1226 l1 = pm->pm_l1; 1227 1228 /* 1229 * If the L1 is not currently on the LRU list, just return 1230 */ 1231 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1232 return; 1233 1234 simple_lock(&l1_lru_lock); 1235 1236 /* 1237 * Check the use count again, now that we've acquired the lock 1238 */ 1239 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1240 simple_unlock(&l1_lru_lock); 1241 return; 1242 } 1243 1244 /* 1245 * Move the L1 to the back of the LRU list 1246 */ 1247 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1248 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1249 1250 simple_unlock(&l1_lru_lock); 1251 } 1252 1253 /* 1254 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1255 * 1256 * Free an L2 descriptor table. 1257 */ 1258 static inline void 1259 #ifndef PMAP_INCLUDE_PTE_SYNC 1260 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1261 #else 1262 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1263 #endif 1264 { 1265 #ifdef PMAP_INCLUDE_PTE_SYNC 1266 #ifdef PMAP_CACHE_VIVT 1267 /* 1268 * Note: With a write-back cache, we may need to sync this 1269 * L2 table before re-using it. 1270 * This is because it may have belonged to a non-current 1271 * pmap, in which case the cache syncs would have been 1272 * skipped for the pages that were being unmapped. If the 1273 * L2 table were then to be immediately re-allocated to 1274 * the *current* pmap, it may well contain stale mappings 1275 * which have not yet been cleared by a cache write-back 1276 * and so would still be visible to the mmu. 1277 */ 1278 if (need_sync) 1279 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1280 #endif /* PMAP_CACHE_VIVT */ 1281 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1282 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1283 } 1284 1285 /* 1286 * Returns a pointer to the L2 bucket associated with the specified pmap 1287 * and VA, or NULL if no L2 bucket exists for the address. 1288 */ 1289 static inline struct l2_bucket * 1290 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1291 { 1292 struct l2_dtable *l2; 1293 struct l2_bucket *l2b; 1294 u_short l1idx; 1295 1296 l1idx = L1_IDX(va); 1297 1298 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1299 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1300 return (NULL); 1301 1302 return (l2b); 1303 } 1304 1305 /* 1306 * Returns a pointer to the L2 bucket associated with the specified pmap 1307 * and VA. 1308 * 1309 * If no L2 bucket exists, perform the necessary allocations to put an L2 1310 * bucket/page table in place. 1311 * 1312 * Note that if a new L2 bucket/page was allocated, the caller *must* 1313 * increment the bucket occupancy counter appropriately *before* 1314 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1315 * the bucket/page in the meantime. 1316 */ 1317 static struct l2_bucket * 1318 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1319 { 1320 struct l2_dtable *l2; 1321 struct l2_bucket *l2b; 1322 u_short l1idx; 1323 1324 l1idx = L1_IDX(va); 1325 1326 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1327 /* 1328 * No mapping at this address, as there is 1329 * no entry in the L1 table. 1330 * Need to allocate a new l2_dtable. 1331 */ 1332 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1333 return (NULL); 1334 1335 /* 1336 * Link it into the parent pmap 1337 */ 1338 pm->pm_l2[L2_IDX(l1idx)] = l2; 1339 } 1340 1341 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1342 1343 /* 1344 * Fetch pointer to the L2 page table associated with the address. 1345 */ 1346 if (l2b->l2b_kva == NULL) { 1347 pt_entry_t *ptep; 1348 1349 /* 1350 * No L2 page table has been allocated. Chances are, this 1351 * is because we just allocated the l2_dtable, above. 1352 */ 1353 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1354 /* 1355 * Oops, no more L2 page tables available at this 1356 * time. We may need to deallocate the l2_dtable 1357 * if we allocated a new one above. 1358 */ 1359 if (l2->l2_occupancy == 0) { 1360 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1361 pmap_free_l2_dtable(l2); 1362 } 1363 return (NULL); 1364 } 1365 1366 l2->l2_occupancy++; 1367 l2b->l2b_kva = ptep; 1368 l2b->l2b_l1idx = l1idx; 1369 } 1370 1371 return (l2b); 1372 } 1373 1374 /* 1375 * One or more mappings in the specified L2 descriptor table have just been 1376 * invalidated. 1377 * 1378 * Garbage collect the metadata and descriptor table itself if necessary. 1379 * 1380 * The pmap lock must be acquired when this is called (not necessary 1381 * for the kernel pmap). 1382 */ 1383 static void 1384 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1385 { 1386 struct l2_dtable *l2; 1387 pd_entry_t *pl1pd, l1pd; 1388 pt_entry_t *ptep; 1389 u_short l1idx; 1390 1391 KDASSERT(count <= l2b->l2b_occupancy); 1392 1393 /* 1394 * Update the bucket's reference count according to how many 1395 * PTEs the caller has just invalidated. 1396 */ 1397 l2b->l2b_occupancy -= count; 1398 1399 /* 1400 * Note: 1401 * 1402 * Level 2 page tables allocated to the kernel pmap are never freed 1403 * as that would require checking all Level 1 page tables and 1404 * removing any references to the Level 2 page table. See also the 1405 * comment elsewhere about never freeing bootstrap L2 descriptors. 1406 * 1407 * We make do with just invalidating the mapping in the L2 table. 1408 * 1409 * This isn't really a big deal in practice and, in fact, leads 1410 * to a performance win over time as we don't need to continually 1411 * alloc/free. 1412 */ 1413 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1414 return; 1415 1416 /* 1417 * There are no more valid mappings in this level 2 page table. 1418 * Go ahead and NULL-out the pointer in the bucket, then 1419 * free the page table. 1420 */ 1421 l1idx = l2b->l2b_l1idx; 1422 ptep = l2b->l2b_kva; 1423 l2b->l2b_kva = NULL; 1424 1425 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1426 1427 /* 1428 * If the L1 slot matches the pmap's domain 1429 * number, then invalidate it. 1430 */ 1431 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1432 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1433 *pl1pd = 0; 1434 PTE_SYNC(pl1pd); 1435 } 1436 1437 /* 1438 * Release the L2 descriptor table back to the pool cache. 1439 */ 1440 #ifndef PMAP_INCLUDE_PTE_SYNC 1441 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1442 #else 1443 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1444 #endif 1445 1446 /* 1447 * Update the reference count in the associated l2_dtable 1448 */ 1449 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1450 if (--l2->l2_occupancy > 0) 1451 return; 1452 1453 /* 1454 * There are no more valid mappings in any of the Level 1 1455 * slots managed by this l2_dtable. Go ahead and NULL-out 1456 * the pointer in the parent pmap and free the l2_dtable. 1457 */ 1458 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1459 pmap_free_l2_dtable(l2); 1460 } 1461 1462 /* 1463 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1464 * structures. 1465 */ 1466 static int 1467 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1468 { 1469 #ifndef PMAP_INCLUDE_PTE_SYNC 1470 struct l2_bucket *l2b; 1471 pt_entry_t *ptep, pte; 1472 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1473 1474 /* 1475 * The mappings for these page tables were initially made using 1476 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1477 * mode will not be right for page table mappings. To avoid 1478 * polluting the pmap_kenter_pa() code with a special case for 1479 * page tables, we simply fix up the cache-mode here if it's not 1480 * correct. 1481 */ 1482 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1483 KDASSERT(l2b != NULL); 1484 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1485 pte = *ptep; 1486 1487 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1488 /* 1489 * Page tables must have the cache-mode set to Write-Thru. 1490 */ 1491 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1492 PTE_SYNC(ptep); 1493 cpu_tlb_flushD_SE(va); 1494 cpu_cpwait(); 1495 } 1496 #endif 1497 1498 memset(v, 0, L2_TABLE_SIZE_REAL); 1499 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1500 return (0); 1501 } 1502 1503 static int 1504 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1505 { 1506 1507 memset(v, 0, sizeof(struct l2_dtable)); 1508 return (0); 1509 } 1510 1511 static int 1512 pmap_pmap_ctor(void *arg, void *v, int flags) 1513 { 1514 1515 memset(v, 0, sizeof(struct pmap)); 1516 return (0); 1517 } 1518 1519 static void 1520 pmap_pinit(pmap_t pm) 1521 { 1522 struct l2_bucket *l2b; 1523 1524 if (vector_page < KERNEL_BASE) { 1525 /* 1526 * Map the vector page. 1527 */ 1528 pmap_enter(pm, vector_page, systempage.pv_pa, 1529 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1530 pmap_update(pm); 1531 1532 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1533 l2b = pmap_get_l2_bucket(pm, vector_page); 1534 KDASSERT(l2b != NULL); 1535 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1536 L1_C_DOM(pm->pm_domain); 1537 } else 1538 pm->pm_pl1vec = NULL; 1539 } 1540 1541 #ifdef PMAP_CACHE_VIVT 1542 /* 1543 * Since we have a virtually indexed cache, we may need to inhibit caching if 1544 * there is more than one mapping and at least one of them is writable. 1545 * Since we purge the cache on every context switch, we only need to check for 1546 * other mappings within the same pmap, or kernel_pmap. 1547 * This function is also called when a page is unmapped, to possibly reenable 1548 * caching on any remaining mappings. 1549 * 1550 * The code implements the following logic, where: 1551 * 1552 * KW = # of kernel read/write pages 1553 * KR = # of kernel read only pages 1554 * UW = # of user read/write pages 1555 * UR = # of user read only pages 1556 * 1557 * KC = kernel mapping is cacheable 1558 * UC = user mapping is cacheable 1559 * 1560 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1561 * +--------------------------------------------- 1562 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1563 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1564 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1565 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1566 */ 1567 1568 static const int pmap_vac_flags[4][4] = { 1569 {-1, 0, 0, PVF_KNC}, 1570 {0, 0, PVF_NC, PVF_NC}, 1571 {0, PVF_NC, PVF_NC, PVF_NC}, 1572 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1573 }; 1574 1575 static inline int 1576 pmap_get_vac_flags(const struct vm_page_md *md) 1577 { 1578 int kidx, uidx; 1579 1580 kidx = 0; 1581 if (md->kro_mappings || md->krw_mappings > 1) 1582 kidx |= 1; 1583 if (md->krw_mappings) 1584 kidx |= 2; 1585 1586 uidx = 0; 1587 if (md->uro_mappings || md->urw_mappings > 1) 1588 uidx |= 1; 1589 if (md->urw_mappings) 1590 uidx |= 2; 1591 1592 return (pmap_vac_flags[uidx][kidx]); 1593 } 1594 1595 static inline void 1596 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1597 { 1598 int nattr; 1599 1600 nattr = pmap_get_vac_flags(md); 1601 1602 if (nattr < 0) { 1603 md->pvh_attrs &= ~PVF_NC; 1604 return; 1605 } 1606 1607 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1608 return; 1609 1610 if (pm == pmap_kernel()) 1611 pmap_vac_me_kpmap(md, pa, pm, va); 1612 else 1613 pmap_vac_me_user(md, pa, pm, va); 1614 1615 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1616 } 1617 1618 static void 1619 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1620 { 1621 u_int u_cacheable, u_entries; 1622 struct pv_entry *pv; 1623 pmap_t last_pmap = pm; 1624 1625 /* 1626 * Pass one, see if there are both kernel and user pmaps for 1627 * this page. Calculate whether there are user-writable or 1628 * kernel-writable pages. 1629 */ 1630 u_cacheable = 0; 1631 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1632 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1633 u_cacheable++; 1634 } 1635 1636 u_entries = md->urw_mappings + md->uro_mappings; 1637 1638 /* 1639 * We know we have just been updating a kernel entry, so if 1640 * all user pages are already cacheable, then there is nothing 1641 * further to do. 1642 */ 1643 if (md->k_mappings == 0 && u_cacheable == u_entries) 1644 return; 1645 1646 if (u_entries) { 1647 /* 1648 * Scan over the list again, for each entry, if it 1649 * might not be set correctly, call pmap_vac_me_user 1650 * to recalculate the settings. 1651 */ 1652 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1653 /* 1654 * We know kernel mappings will get set 1655 * correctly in other calls. We also know 1656 * that if the pmap is the same as last_pmap 1657 * then we've just handled this entry. 1658 */ 1659 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1660 continue; 1661 1662 /* 1663 * If there are kernel entries and this page 1664 * is writable but non-cacheable, then we can 1665 * skip this entry also. 1666 */ 1667 if (md->k_mappings && 1668 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1669 (PVF_NC | PVF_WRITE)) 1670 continue; 1671 1672 /* 1673 * Similarly if there are no kernel-writable 1674 * entries and the page is already 1675 * read-only/cacheable. 1676 */ 1677 if (md->krw_mappings == 0 && 1678 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1679 continue; 1680 1681 /* 1682 * For some of the remaining cases, we know 1683 * that we must recalculate, but for others we 1684 * can't tell if they are correct or not, so 1685 * we recalculate anyway. 1686 */ 1687 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1688 } 1689 1690 if (md->k_mappings == 0) 1691 return; 1692 } 1693 1694 pmap_vac_me_user(md, pa, pm, va); 1695 } 1696 1697 static void 1698 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1699 { 1700 pmap_t kpmap = pmap_kernel(); 1701 struct pv_entry *pv, *npv = NULL; 1702 struct l2_bucket *l2b; 1703 pt_entry_t *ptep, pte; 1704 u_int entries = 0; 1705 u_int writable = 0; 1706 u_int cacheable_entries = 0; 1707 u_int kern_cacheable = 0; 1708 u_int other_writable = 0; 1709 1710 /* 1711 * Count mappings and writable mappings in this pmap. 1712 * Include kernel mappings as part of our own. 1713 * Keep a pointer to the first one. 1714 */ 1715 npv = NULL; 1716 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1717 /* Count mappings in the same pmap */ 1718 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1719 if (entries++ == 0) 1720 npv = pv; 1721 1722 /* Cacheable mappings */ 1723 if ((pv->pv_flags & PVF_NC) == 0) { 1724 cacheable_entries++; 1725 if (kpmap == pv->pv_pmap) 1726 kern_cacheable++; 1727 } 1728 1729 /* Writable mappings */ 1730 if (pv->pv_flags & PVF_WRITE) 1731 ++writable; 1732 } else 1733 if (pv->pv_flags & PVF_WRITE) 1734 other_writable = 1; 1735 } 1736 1737 /* 1738 * Enable or disable caching as necessary. 1739 * Note: the first entry might be part of the kernel pmap, 1740 * so we can't assume this is indicative of the state of the 1741 * other (maybe non-kpmap) entries. 1742 */ 1743 if ((entries > 1 && writable) || 1744 (entries > 0 && pm == kpmap && other_writable)) { 1745 if (cacheable_entries == 0) 1746 return; 1747 1748 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1749 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1750 (pv->pv_flags & PVF_NC)) 1751 continue; 1752 1753 pv->pv_flags |= PVF_NC; 1754 1755 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1756 KDASSERT(l2b != NULL); 1757 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1758 pte = *ptep & ~L2_S_CACHE_MASK; 1759 1760 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1761 l2pte_valid(pte)) { 1762 if (PV_BEEN_EXECD(pv->pv_flags)) { 1763 #ifdef PMAP_CACHE_VIVT 1764 pmap_idcache_wbinv_range(pv->pv_pmap, 1765 pv->pv_va, PAGE_SIZE); 1766 #endif 1767 pmap_tlb_flushID_SE(pv->pv_pmap, 1768 pv->pv_va); 1769 } else 1770 if (PV_BEEN_REFD(pv->pv_flags)) { 1771 #ifdef PMAP_CACHE_VIVT 1772 pmap_dcache_wb_range(pv->pv_pmap, 1773 pv->pv_va, PAGE_SIZE, true, 1774 (pv->pv_flags & PVF_WRITE) == 0); 1775 #endif 1776 pmap_tlb_flushD_SE(pv->pv_pmap, 1777 pv->pv_va); 1778 } 1779 } 1780 1781 *ptep = pte; 1782 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1783 } 1784 cpu_cpwait(); 1785 } else 1786 if (entries > cacheable_entries) { 1787 /* 1788 * Turn cacheing back on for some pages. If it is a kernel 1789 * page, only do so if there are no other writable pages. 1790 */ 1791 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1792 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1793 (kpmap != pv->pv_pmap || other_writable))) 1794 continue; 1795 1796 pv->pv_flags &= ~PVF_NC; 1797 1798 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1799 KDASSERT(l2b != NULL); 1800 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1801 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1802 1803 if (l2pte_valid(pte)) { 1804 if (PV_BEEN_EXECD(pv->pv_flags)) { 1805 pmap_tlb_flushID_SE(pv->pv_pmap, 1806 pv->pv_va); 1807 } else 1808 if (PV_BEEN_REFD(pv->pv_flags)) { 1809 pmap_tlb_flushD_SE(pv->pv_pmap, 1810 pv->pv_va); 1811 } 1812 } 1813 1814 *ptep = pte; 1815 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1816 } 1817 } 1818 } 1819 #endif 1820 1821 #ifdef PMAP_CACHE_VIPT 1822 static void 1823 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1824 { 1825 struct pv_entry *pv; 1826 vaddr_t tst_mask; 1827 bool bad_alias; 1828 struct l2_bucket *l2b; 1829 pt_entry_t *ptep, pte, opte; 1830 const u_int 1831 rw_mappings = md->urw_mappings + md->krw_mappings, 1832 ro_mappings = md->uro_mappings + md->kro_mappings; 1833 1834 /* do we need to do anything? */ 1835 if (arm_cache_prefer_mask == 0) 1836 return; 1837 1838 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1839 md, pm, va)); 1840 1841 KASSERT(!va || pm); 1842 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1843 1844 /* Already a conflict? */ 1845 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1846 /* just an add, things are already non-cached */ 1847 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1848 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1849 bad_alias = false; 1850 if (va) { 1851 PMAPCOUNT(vac_color_none); 1852 bad_alias = true; 1853 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1854 goto fixup; 1855 } 1856 pv = SLIST_FIRST(&md->pvh_list); 1857 /* the list can't be empty because it would be cachable */ 1858 if (md->pvh_attrs & PVF_KMPAGE) { 1859 tst_mask = md->pvh_attrs; 1860 } else { 1861 KASSERT(pv); 1862 tst_mask = pv->pv_va; 1863 pv = SLIST_NEXT(pv, pv_link); 1864 } 1865 /* 1866 * Only check for a bad alias if we have writable mappings. 1867 */ 1868 tst_mask &= arm_cache_prefer_mask; 1869 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1870 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1871 /* if there's a bad alias, stop checking. */ 1872 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1873 bad_alias = true; 1874 } 1875 md->pvh_attrs |= PVF_WRITE; 1876 if (!bad_alias) 1877 md->pvh_attrs |= PVF_DIRTY; 1878 } else { 1879 /* 1880 * We have only read-only mappings. Let's see if there 1881 * are multiple colors in use or if we mapped a KMPAGE. 1882 * If the latter, we have a bad alias. If the former, 1883 * we need to remember that. 1884 */ 1885 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1886 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1887 if (md->pvh_attrs & PVF_KMPAGE) 1888 bad_alias = true; 1889 break; 1890 } 1891 } 1892 md->pvh_attrs &= ~PVF_WRITE; 1893 /* 1894 * No KMPAGE and we exited early, so we must have 1895 * multiple color mappings. 1896 */ 1897 if (!bad_alias && pv != NULL) 1898 md->pvh_attrs |= PVF_MULTCLR; 1899 } 1900 1901 /* If no conflicting colors, set everything back to cached */ 1902 if (!bad_alias) { 1903 #ifdef DEBUG 1904 if ((md->pvh_attrs & PVF_WRITE) 1905 || ro_mappings < 2) { 1906 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1907 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1908 } 1909 #endif 1910 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1911 md->pvh_attrs |= tst_mask | PVF_COLORED; 1912 /* 1913 * Restore DIRTY bit if page is modified 1914 */ 1915 if (md->pvh_attrs & PVF_DMOD) 1916 md->pvh_attrs |= PVF_DIRTY; 1917 PMAPCOUNT(vac_color_restore); 1918 } else { 1919 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1920 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1921 } 1922 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1923 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1924 } else if (!va) { 1925 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1926 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1927 || (md->pvh_attrs & PVF_DIRTY)); 1928 if (rw_mappings == 0) { 1929 md->pvh_attrs &= ~PVF_WRITE; 1930 if (ro_mappings == 1 1931 && (md->pvh_attrs & PVF_MULTCLR)) { 1932 /* 1933 * If this is the last readonly mapping 1934 * but it doesn't match the current color 1935 * for the page, change the current color 1936 * to match this last readonly mapping. 1937 */ 1938 pv = SLIST_FIRST(&md->pvh_list); 1939 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1940 & arm_cache_prefer_mask; 1941 if (tst_mask) { 1942 md->pvh_attrs ^= tst_mask; 1943 PMAPCOUNT(vac_color_change); 1944 } 1945 } 1946 } 1947 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1948 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1949 return; 1950 } else if (!pmap_is_page_colored_p(md)) { 1951 /* not colored so we just use its color */ 1952 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1953 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1954 PMAPCOUNT(vac_color_new); 1955 md->pvh_attrs &= PAGE_SIZE - 1; 1956 md->pvh_attrs |= PVF_COLORED 1957 | (va & arm_cache_prefer_mask) 1958 | (rw_mappings > 0 ? PVF_WRITE : 0); 1959 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1960 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1961 return; 1962 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1963 bad_alias = false; 1964 if (rw_mappings > 0) { 1965 /* 1966 * We now have writeable mappings and if we have 1967 * readonly mappings in more than once color, we have 1968 * an aliasing problem. Regardless mark the page as 1969 * writeable. 1970 */ 1971 if (md->pvh_attrs & PVF_MULTCLR) { 1972 if (ro_mappings < 2) { 1973 /* 1974 * If we only have less than two 1975 * read-only mappings, just flush the 1976 * non-primary colors from the cache. 1977 */ 1978 pmap_flush_page(md, pa, 1979 PMAP_FLUSH_SECONDARY); 1980 } else { 1981 bad_alias = true; 1982 } 1983 } 1984 md->pvh_attrs |= PVF_WRITE; 1985 } 1986 /* If no conflicting colors, set everything back to cached */ 1987 if (!bad_alias) { 1988 #ifdef DEBUG 1989 if (rw_mappings > 0 1990 || (md->pvh_attrs & PMAP_KMPAGE)) { 1991 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1992 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1993 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1994 } 1995 #endif 1996 if (SLIST_EMPTY(&md->pvh_list)) 1997 PMAPCOUNT(vac_color_reuse); 1998 else 1999 PMAPCOUNT(vac_color_ok); 2000 2001 /* matching color, just return */ 2002 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2003 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2004 return; 2005 } 2006 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2007 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2008 2009 /* color conflict. evict from cache. */ 2010 2011 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2012 md->pvh_attrs &= ~PVF_COLORED; 2013 md->pvh_attrs |= PVF_NC; 2014 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2015 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2016 PMAPCOUNT(vac_color_erase); 2017 } else if (rw_mappings == 0 2018 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2019 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2020 2021 /* 2022 * If the page has dirty cache lines, clean it. 2023 */ 2024 if (md->pvh_attrs & PVF_DIRTY) 2025 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2026 2027 /* 2028 * If this is the first remapping (we know that there are no 2029 * writeable mappings), then this is a simple color change. 2030 * Otherwise this is a seconary r/o mapping, which means 2031 * we don't have to do anything. 2032 */ 2033 if (ro_mappings == 1) { 2034 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2035 md->pvh_attrs &= PAGE_SIZE - 1; 2036 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2037 PMAPCOUNT(vac_color_change); 2038 } else { 2039 PMAPCOUNT(vac_color_blind); 2040 } 2041 md->pvh_attrs |= PVF_MULTCLR; 2042 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2043 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2044 return; 2045 } else { 2046 if (rw_mappings > 0) 2047 md->pvh_attrs |= PVF_WRITE; 2048 2049 /* color conflict. evict from cache. */ 2050 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2051 2052 /* the list can't be empty because this was a enter/modify */ 2053 pv = SLIST_FIRST(&md->pvh_list); 2054 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2055 KASSERT(pv); 2056 /* 2057 * If there's only one mapped page, change color to the 2058 * page's new color and return. Restore the DIRTY bit 2059 * that was erased by pmap_flush_page. 2060 */ 2061 if (SLIST_NEXT(pv, pv_link) == NULL) { 2062 md->pvh_attrs &= PAGE_SIZE - 1; 2063 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2064 if (md->pvh_attrs & PVF_DMOD) 2065 md->pvh_attrs |= PVF_DIRTY; 2066 PMAPCOUNT(vac_color_change); 2067 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2068 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2069 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2070 return; 2071 } 2072 } 2073 bad_alias = true; 2074 md->pvh_attrs &= ~PVF_COLORED; 2075 md->pvh_attrs |= PVF_NC; 2076 PMAPCOUNT(vac_color_erase); 2077 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2078 } 2079 2080 fixup: 2081 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2082 2083 /* 2084 * Turn cacheing on/off for all pages. 2085 */ 2086 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2087 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2088 KDASSERT(l2b != NULL); 2089 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2090 opte = *ptep; 2091 pte = opte & ~L2_S_CACHE_MASK; 2092 if (bad_alias) { 2093 pv->pv_flags |= PVF_NC; 2094 } else { 2095 pv->pv_flags &= ~PVF_NC; 2096 pte |= pte_l2_s_cache_mode; 2097 } 2098 2099 if (opte == pte) /* only update is there's a change */ 2100 continue; 2101 2102 if (l2pte_valid(pte)) { 2103 if (PV_BEEN_EXECD(pv->pv_flags)) { 2104 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2105 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2106 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2107 } 2108 } 2109 2110 *ptep = pte; 2111 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2112 } 2113 } 2114 #endif /* PMAP_CACHE_VIPT */ 2115 2116 2117 /* 2118 * Modify pte bits for all ptes corresponding to the given physical address. 2119 * We use `maskbits' rather than `clearbits' because we're always passing 2120 * constants and the latter would require an extra inversion at run-time. 2121 */ 2122 static void 2123 pmap_clearbit(struct vm_page *pg, u_int maskbits) 2124 { 2125 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2126 struct l2_bucket *l2b; 2127 struct pv_entry *pv; 2128 pt_entry_t *ptep, npte, opte; 2129 pmap_t pm; 2130 vaddr_t va; 2131 u_int oflags; 2132 #ifdef PMAP_CACHE_VIPT 2133 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2134 bool need_syncicache = false; 2135 bool did_syncicache = false; 2136 bool need_vac_me_harder = false; 2137 #endif 2138 2139 NPDEBUG(PDB_BITS, 2140 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 2141 pg, VM_PAGE_TO_PHYS(pg), maskbits)); 2142 2143 PMAP_HEAD_TO_MAP_LOCK(); 2144 simple_lock(&md->pvh_slock); 2145 2146 #ifdef PMAP_CACHE_VIPT 2147 /* 2148 * If we might want to sync the I-cache and we've modified it, 2149 * then we know we definitely need to sync or discard it. 2150 */ 2151 if (want_syncicache) 2152 need_syncicache = md->pvh_attrs & PVF_MOD; 2153 #endif 2154 /* 2155 * Clear saved attributes (modify, reference) 2156 */ 2157 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2158 2159 if (SLIST_EMPTY(&md->pvh_list)) { 2160 #ifdef PMAP_CACHE_VIPT 2161 if (need_syncicache) { 2162 /* 2163 * No one has it mapped, so just discard it. The next 2164 * exec remapping will cause it to be synced. 2165 */ 2166 md->pvh_attrs &= ~PVF_EXEC; 2167 PMAPCOUNT(exec_discarded_clearbit); 2168 } 2169 #endif 2170 simple_unlock(&md->pvh_slock); 2171 PMAP_HEAD_TO_MAP_UNLOCK(); 2172 return; 2173 } 2174 2175 /* 2176 * Loop over all current mappings setting/clearing as appropos 2177 */ 2178 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2179 va = pv->pv_va; 2180 pm = pv->pv_pmap; 2181 oflags = pv->pv_flags; 2182 /* 2183 * Kernel entries are unmanaged and as such not to be changed. 2184 */ 2185 if (oflags & PVF_KENTRY) 2186 continue; 2187 pv->pv_flags &= ~maskbits; 2188 2189 pmap_acquire_pmap_lock(pm); 2190 2191 l2b = pmap_get_l2_bucket(pm, va); 2192 KDASSERT(l2b != NULL); 2193 2194 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2195 npte = opte = *ptep; 2196 2197 NPDEBUG(PDB_BITS, 2198 printf( 2199 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2200 pv, pv->pv_pmap, pv->pv_va, oflags)); 2201 2202 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2203 #ifdef PMAP_CACHE_VIVT 2204 if ((pv->pv_flags & PVF_NC)) { 2205 /* 2206 * Entry is not cacheable: 2207 * 2208 * Don't turn caching on again if this is a 2209 * modified emulation. This would be 2210 * inconsitent with the settings created by 2211 * pmap_vac_me_harder(). Otherwise, it's safe 2212 * to re-enable cacheing. 2213 * 2214 * There's no need to call pmap_vac_me_harder() 2215 * here: all pages are losing their write 2216 * permission. 2217 */ 2218 if (maskbits & PVF_WRITE) { 2219 npte |= pte_l2_s_cache_mode; 2220 pv->pv_flags &= ~PVF_NC; 2221 } 2222 } else 2223 if (opte & L2_S_PROT_W) { 2224 /* 2225 * Entry is writable/cacheable: check if pmap 2226 * is current if it is flush it, otherwise it 2227 * won't be in the cache 2228 */ 2229 if (PV_BEEN_EXECD(oflags)) 2230 pmap_idcache_wbinv_range(pm, pv->pv_va, 2231 PAGE_SIZE); 2232 else 2233 if (PV_BEEN_REFD(oflags)) 2234 pmap_dcache_wb_range(pm, pv->pv_va, 2235 PAGE_SIZE, 2236 (maskbits & PVF_REF) != 0, false); 2237 } 2238 #endif 2239 2240 /* make the pte read only */ 2241 npte &= ~L2_S_PROT_W; 2242 2243 if (maskbits & oflags & PVF_WRITE) { 2244 /* 2245 * Keep alias accounting up to date 2246 */ 2247 if (pv->pv_pmap == pmap_kernel()) { 2248 md->krw_mappings--; 2249 md->kro_mappings++; 2250 } else { 2251 md->urw_mappings--; 2252 md->uro_mappings++; 2253 } 2254 #ifdef PMAP_CACHE_VIPT 2255 if (md->urw_mappings + md->krw_mappings == 0) 2256 md->pvh_attrs &= ~PVF_WRITE; 2257 if (want_syncicache) 2258 need_syncicache = true; 2259 need_vac_me_harder = true; 2260 #endif 2261 } 2262 } 2263 2264 if (maskbits & PVF_REF) { 2265 if ((pv->pv_flags & PVF_NC) == 0 && 2266 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2267 l2pte_valid(npte)) { 2268 #ifdef PMAP_CACHE_VIVT 2269 /* 2270 * Check npte here; we may have already 2271 * done the wbinv above, and the validity 2272 * of the PTE is the same for opte and 2273 * npte. 2274 */ 2275 /* XXXJRT need idcache_inv_range */ 2276 if (PV_BEEN_EXECD(oflags)) 2277 pmap_idcache_wbinv_range(pm, 2278 pv->pv_va, PAGE_SIZE); 2279 else 2280 if (PV_BEEN_REFD(oflags)) 2281 pmap_dcache_wb_range(pm, 2282 pv->pv_va, PAGE_SIZE, 2283 true, true); 2284 #endif 2285 } 2286 2287 /* 2288 * Make the PTE invalid so that we will take a 2289 * page fault the next time the mapping is 2290 * referenced. 2291 */ 2292 npte &= ~L2_TYPE_MASK; 2293 npte |= L2_TYPE_INV; 2294 } 2295 2296 if (npte != opte) { 2297 *ptep = npte; 2298 PTE_SYNC(ptep); 2299 /* Flush the TLB entry if a current pmap. */ 2300 if (PV_BEEN_EXECD(oflags)) 2301 pmap_tlb_flushID_SE(pm, pv->pv_va); 2302 else 2303 if (PV_BEEN_REFD(oflags)) 2304 pmap_tlb_flushD_SE(pm, pv->pv_va); 2305 } 2306 2307 pmap_release_pmap_lock(pm); 2308 2309 NPDEBUG(PDB_BITS, 2310 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2311 pm, va, opte, npte)); 2312 } 2313 2314 #ifdef PMAP_CACHE_VIPT 2315 /* 2316 * If we need to sync the I-cache and we haven't done it yet, do it. 2317 */ 2318 if (need_syncicache && !did_syncicache) { 2319 pmap_syncicache_page(md, VM_PAGE_TO_PHYS(pg)); 2320 PMAPCOUNT(exec_synced_clearbit); 2321 } 2322 /* 2323 * If we are changing this to read-only, we need to call vac_me_harder 2324 * so we can change all the read-only pages to cacheable. We pretend 2325 * this as a page deletion. 2326 */ 2327 if (need_vac_me_harder) { 2328 if (md->pvh_attrs & PVF_NC) 2329 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), NULL, 0); 2330 } 2331 #endif 2332 2333 simple_unlock(&md->pvh_slock); 2334 PMAP_HEAD_TO_MAP_UNLOCK(); 2335 } 2336 2337 /* 2338 * pmap_clean_page() 2339 * 2340 * This is a local function used to work out the best strategy to clean 2341 * a single page referenced by its entry in the PV table. It's used by 2342 * pmap_copy_page, pmap_zero page and maybe some others later on. 2343 * 2344 * Its policy is effectively: 2345 * o If there are no mappings, we don't bother doing anything with the cache. 2346 * o If there is one mapping, we clean just that page. 2347 * o If there are multiple mappings, we clean the entire cache. 2348 * 2349 * So that some functions can be further optimised, it returns 0 if it didn't 2350 * clean the entire cache, or 1 if it did. 2351 * 2352 * XXX One bug in this routine is that if the pv_entry has a single page 2353 * mapped at 0x00000000 a whole cache clean will be performed rather than 2354 * just the 1 page. Since this should not occur in everyday use and if it does 2355 * it will just result in not the most efficient clean for the page. 2356 */ 2357 #ifdef PMAP_CACHE_VIVT 2358 static int 2359 pmap_clean_page(struct pv_entry *pv, bool is_src) 2360 { 2361 pmap_t pm_to_clean = NULL; 2362 struct pv_entry *npv; 2363 u_int cache_needs_cleaning = 0; 2364 u_int flags = 0; 2365 vaddr_t page_to_clean = 0; 2366 2367 if (pv == NULL) { 2368 /* nothing mapped in so nothing to flush */ 2369 return (0); 2370 } 2371 2372 /* 2373 * Since we flush the cache each time we change to a different 2374 * user vmspace, we only need to flush the page if it is in the 2375 * current pmap. 2376 */ 2377 2378 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2379 if (pmap_is_current(npv->pv_pmap)) { 2380 flags |= npv->pv_flags; 2381 /* 2382 * The page is mapped non-cacheable in 2383 * this map. No need to flush the cache. 2384 */ 2385 if (npv->pv_flags & PVF_NC) { 2386 #ifdef DIAGNOSTIC 2387 if (cache_needs_cleaning) 2388 panic("pmap_clean_page: " 2389 "cache inconsistency"); 2390 #endif 2391 break; 2392 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2393 continue; 2394 if (cache_needs_cleaning) { 2395 page_to_clean = 0; 2396 break; 2397 } else { 2398 page_to_clean = npv->pv_va; 2399 pm_to_clean = npv->pv_pmap; 2400 } 2401 cache_needs_cleaning = 1; 2402 } 2403 } 2404 2405 if (page_to_clean) { 2406 if (PV_BEEN_EXECD(flags)) 2407 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2408 PAGE_SIZE); 2409 else 2410 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2411 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2412 } else if (cache_needs_cleaning) { 2413 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2414 2415 if (PV_BEEN_EXECD(flags)) 2416 pmap_idcache_wbinv_all(pm); 2417 else 2418 pmap_dcache_wbinv_all(pm); 2419 return (1); 2420 } 2421 return (0); 2422 } 2423 #endif 2424 2425 #ifdef PMAP_CACHE_VIPT 2426 /* 2427 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2428 * right cache alias to make sure we flush the right stuff. 2429 */ 2430 void 2431 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2432 { 2433 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2434 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2435 2436 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2437 md, md->pvh_attrs)); 2438 /* 2439 * No need to clean the page if it's non-cached. 2440 */ 2441 if (md->pvh_attrs & PVF_NC) 2442 return; 2443 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2444 2445 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2446 /* 2447 * Set up a PTE with the right coloring to flush existing cache lines. 2448 */ 2449 *ptep = L2_S_PROTO | 2450 pa 2451 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2452 | pte_l2_s_cache_mode; 2453 PTE_SYNC(ptep); 2454 2455 /* 2456 * Flush it. 2457 */ 2458 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2459 /* 2460 * Unmap the page. 2461 */ 2462 *ptep = 0; 2463 PTE_SYNC(ptep); 2464 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2465 2466 md->pvh_attrs |= PVF_EXEC; 2467 PMAPCOUNT(exec_synced); 2468 } 2469 2470 void 2471 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2472 { 2473 vsize_t va_offset, end_va; 2474 void (*cf)(vaddr_t, vsize_t); 2475 2476 if (arm_cache_prefer_mask == 0) 2477 return; 2478 2479 switch (flush) { 2480 case PMAP_FLUSH_PRIMARY: 2481 if (md->pvh_attrs & PVF_MULTCLR) { 2482 va_offset = 0; 2483 end_va = arm_cache_prefer_mask; 2484 md->pvh_attrs &= ~PVF_MULTCLR; 2485 PMAPCOUNT(vac_flush_lots); 2486 } else { 2487 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2488 end_va = va_offset; 2489 PMAPCOUNT(vac_flush_one); 2490 } 2491 /* 2492 * Mark that the page is no longer dirty. 2493 */ 2494 md->pvh_attrs &= ~PVF_DIRTY; 2495 cf = cpufuncs.cf_idcache_wbinv_range; 2496 break; 2497 case PMAP_FLUSH_SECONDARY: 2498 va_offset = 0; 2499 end_va = arm_cache_prefer_mask; 2500 cf = cpufuncs.cf_idcache_wbinv_range; 2501 md->pvh_attrs &= ~PVF_MULTCLR; 2502 PMAPCOUNT(vac_flush_lots); 2503 break; 2504 case PMAP_CLEAN_PRIMARY: 2505 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2506 end_va = va_offset; 2507 cf = cpufuncs.cf_dcache_wb_range; 2508 /* 2509 * Mark that the page is no longer dirty. 2510 */ 2511 if ((md->pvh_attrs & PVF_DMOD) == 0) 2512 md->pvh_attrs &= ~PVF_DIRTY; 2513 PMAPCOUNT(vac_clean_one); 2514 break; 2515 default: 2516 return; 2517 } 2518 2519 KASSERT(!(md->pvh_attrs & PVF_NC)); 2520 2521 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2522 md, md->pvh_attrs)); 2523 2524 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2525 const size_t pte_offset = va_offset >> PGSHIFT; 2526 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2527 const pt_entry_t oldpte = *ptep; 2528 2529 if (flush == PMAP_FLUSH_SECONDARY 2530 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2531 continue; 2532 2533 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2534 /* 2535 * Set up a PTE with the right coloring to flush 2536 * existing cache entries. 2537 */ 2538 *ptep = L2_S_PROTO 2539 | pa 2540 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2541 | pte_l2_s_cache_mode; 2542 PTE_SYNC(ptep); 2543 2544 /* 2545 * Flush it. 2546 */ 2547 (*cf)(cdstp + va_offset, PAGE_SIZE); 2548 2549 /* 2550 * Restore the page table entry since we might have interrupted 2551 * pmap_zero_page or pmap_copy_page which was already using 2552 * this pte. 2553 */ 2554 *ptep = oldpte; 2555 PTE_SYNC(ptep); 2556 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2557 } 2558 } 2559 #endif /* PMAP_CACHE_VIPT */ 2560 2561 /* 2562 * Routine: pmap_page_remove 2563 * Function: 2564 * Removes this physical page from 2565 * all physical maps in which it resides. 2566 * Reflects back modify bits to the pager. 2567 */ 2568 static void 2569 pmap_page_remove(struct vm_page *pg) 2570 { 2571 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2572 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2573 struct l2_bucket *l2b; 2574 struct pv_entry *pv, *npv, **pvp; 2575 pmap_t pm; 2576 pt_entry_t *ptep; 2577 bool flush; 2578 u_int flags; 2579 2580 NPDEBUG(PDB_FOLLOW, 2581 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2582 pa)); 2583 2584 PMAP_HEAD_TO_MAP_LOCK(); 2585 simple_lock(&md->pvh_slock); 2586 2587 pv = SLIST_FIRST(&md->pvh_list); 2588 if (pv == NULL) { 2589 #ifdef PMAP_CACHE_VIPT 2590 /* 2591 * We *know* the page contents are about to be replaced. 2592 * Discard the exec contents 2593 */ 2594 if (PV_IS_EXEC_P(md->pvh_attrs)) 2595 PMAPCOUNT(exec_discarded_page_protect); 2596 md->pvh_attrs &= ~PVF_EXEC; 2597 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2598 #endif 2599 simple_unlock(&md->pvh_slock); 2600 PMAP_HEAD_TO_MAP_UNLOCK(); 2601 return; 2602 } 2603 #ifdef PMAP_CACHE_VIPT 2604 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2605 #endif 2606 2607 /* 2608 * Clear alias counts 2609 */ 2610 #ifdef PMAP_CACHE_VIVT 2611 md->k_mappings = 0; 2612 #endif 2613 md->urw_mappings = md->uro_mappings = 0; 2614 2615 flush = false; 2616 flags = 0; 2617 2618 #ifdef PMAP_CACHE_VIVT 2619 pmap_clean_page(pv, false); 2620 #endif 2621 2622 pvp = &SLIST_FIRST(&md->pvh_list); 2623 while (pv) { 2624 pm = pv->pv_pmap; 2625 npv = SLIST_NEXT(pv, pv_link); 2626 if (flush == false && pmap_is_current(pm)) 2627 flush = true; 2628 2629 if (pm == pmap_kernel()) { 2630 #ifdef PMAP_CACHE_VIPT 2631 /* 2632 * If this was unmanaged mapping, it must be preserved. 2633 * Move it back on the list and advance the end-of-list 2634 * pointer. 2635 */ 2636 if (pv->pv_flags & PVF_KENTRY) { 2637 *pvp = pv; 2638 pvp = &SLIST_NEXT(pv, pv_link); 2639 pv = npv; 2640 continue; 2641 } 2642 if (pv->pv_flags & PVF_WRITE) 2643 md->krw_mappings--; 2644 else 2645 md->kro_mappings--; 2646 #endif 2647 PMAPCOUNT(kernel_unmappings); 2648 } 2649 PMAPCOUNT(unmappings); 2650 2651 pmap_acquire_pmap_lock(pm); 2652 2653 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2654 KDASSERT(l2b != NULL); 2655 2656 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2657 2658 /* 2659 * Update statistics 2660 */ 2661 --pm->pm_stats.resident_count; 2662 2663 /* Wired bit */ 2664 if (pv->pv_flags & PVF_WIRED) 2665 --pm->pm_stats.wired_count; 2666 2667 flags |= pv->pv_flags; 2668 2669 /* 2670 * Invalidate the PTEs. 2671 */ 2672 *ptep = 0; 2673 PTE_SYNC_CURRENT(pm, ptep); 2674 pmap_free_l2_bucket(pm, l2b, 1); 2675 2676 pool_put(&pmap_pv_pool, pv); 2677 pv = npv; 2678 /* 2679 * if we reach the end of the list and there are still 2680 * mappings, they might be able to be cached now. 2681 */ 2682 if (pv == NULL) { 2683 *pvp = NULL; 2684 if (!SLIST_EMPTY(&md->pvh_list)) 2685 pmap_vac_me_harder(md, pa, pm, 0); 2686 } 2687 pmap_release_pmap_lock(pm); 2688 } 2689 #ifdef PMAP_CACHE_VIPT 2690 /* 2691 * Its EXEC cache is now gone. 2692 */ 2693 if (PV_IS_EXEC_P(md->pvh_attrs)) 2694 PMAPCOUNT(exec_discarded_page_protect); 2695 md->pvh_attrs &= ~PVF_EXEC; 2696 KASSERT(md->urw_mappings == 0); 2697 KASSERT(md->uro_mappings == 0); 2698 if (md->krw_mappings == 0) 2699 md->pvh_attrs &= ~PVF_WRITE; 2700 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2701 #endif 2702 simple_unlock(&md->pvh_slock); 2703 PMAP_HEAD_TO_MAP_UNLOCK(); 2704 2705 if (flush) { 2706 /* 2707 * Note: We can't use pmap_tlb_flush{I,}D() here since that 2708 * would need a subsequent call to pmap_update() to ensure 2709 * curpm->pm_cstate.cs_all is reset. Our callers are not 2710 * required to do that (see pmap(9)), so we can't modify 2711 * the current pmap's state. 2712 */ 2713 if (PV_BEEN_EXECD(flags)) 2714 cpu_tlb_flushID(); 2715 else 2716 cpu_tlb_flushD(); 2717 } 2718 cpu_cpwait(); 2719 } 2720 2721 /* 2722 * pmap_t pmap_create(void) 2723 * 2724 * Create a new pmap structure from scratch. 2725 */ 2726 pmap_t 2727 pmap_create(void) 2728 { 2729 pmap_t pm; 2730 2731 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2732 2733 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2734 pm->pm_stats.wired_count = 0; 2735 pm->pm_stats.resident_count = 1; 2736 pm->pm_cstate.cs_all = 0; 2737 pmap_alloc_l1(pm); 2738 2739 /* 2740 * Note: The pool cache ensures that the pm_l2[] array is already 2741 * initialised to zero. 2742 */ 2743 2744 pmap_pinit(pm); 2745 2746 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2747 2748 return (pm); 2749 } 2750 2751 /* 2752 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2753 * u_int flags) 2754 * 2755 * Insert the given physical page (p) at 2756 * the specified virtual address (v) in the 2757 * target physical map with the protection requested. 2758 * 2759 * NB: This is the only routine which MAY NOT lazy-evaluate 2760 * or lose information. That is, this routine must actually 2761 * insert this page into the given map NOW. 2762 */ 2763 int 2764 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2765 { 2766 struct l2_bucket *l2b; 2767 struct vm_page *pg, *opg; 2768 struct pv_entry *pv; 2769 pt_entry_t *ptep, npte, opte; 2770 u_int nflags; 2771 u_int oflags; 2772 2773 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2774 2775 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2776 KDASSERT(((va | pa) & PGOFSET) == 0); 2777 2778 /* 2779 * Get a pointer to the page. Later on in this function, we 2780 * test for a managed page by checking pg != NULL. 2781 */ 2782 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2783 2784 nflags = 0; 2785 if (prot & VM_PROT_WRITE) 2786 nflags |= PVF_WRITE; 2787 if (prot & VM_PROT_EXECUTE) 2788 nflags |= PVF_EXEC; 2789 if (flags & PMAP_WIRED) 2790 nflags |= PVF_WIRED; 2791 2792 PMAP_MAP_TO_HEAD_LOCK(); 2793 pmap_acquire_pmap_lock(pm); 2794 2795 /* 2796 * Fetch the L2 bucket which maps this page, allocating one if 2797 * necessary for user pmaps. 2798 */ 2799 if (pm == pmap_kernel()) 2800 l2b = pmap_get_l2_bucket(pm, va); 2801 else 2802 l2b = pmap_alloc_l2_bucket(pm, va); 2803 if (l2b == NULL) { 2804 if (flags & PMAP_CANFAIL) { 2805 pmap_release_pmap_lock(pm); 2806 PMAP_MAP_TO_HEAD_UNLOCK(); 2807 return (ENOMEM); 2808 } 2809 panic("pmap_enter: failed to allocate L2 bucket"); 2810 } 2811 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2812 opte = *ptep; 2813 npte = pa; 2814 oflags = 0; 2815 2816 if (opte) { 2817 /* 2818 * There is already a mapping at this address. 2819 * If the physical address is different, lookup the 2820 * vm_page. 2821 */ 2822 if (l2pte_pa(opte) != pa) 2823 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2824 else 2825 opg = pg; 2826 } else 2827 opg = NULL; 2828 2829 if (pg) { 2830 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2831 2832 /* 2833 * This is to be a managed mapping. 2834 */ 2835 if ((flags & VM_PROT_ALL) || 2836 (md->pvh_attrs & PVF_REF)) { 2837 /* 2838 * - The access type indicates that we don't need 2839 * to do referenced emulation. 2840 * OR 2841 * - The physical page has already been referenced 2842 * so no need to re-do referenced emulation here. 2843 */ 2844 npte |= L2_S_PROTO; 2845 2846 nflags |= PVF_REF; 2847 2848 if ((prot & VM_PROT_WRITE) != 0 && 2849 ((flags & VM_PROT_WRITE) != 0 || 2850 (md->pvh_attrs & PVF_MOD) != 0)) { 2851 /* 2852 * This is a writable mapping, and the 2853 * page's mod state indicates it has 2854 * already been modified. Make it 2855 * writable from the outset. 2856 */ 2857 npte |= L2_S_PROT_W; 2858 nflags |= PVF_MOD; 2859 } 2860 } else { 2861 /* 2862 * Need to do page referenced emulation. 2863 */ 2864 npte |= L2_TYPE_INV; 2865 } 2866 2867 npte |= pte_l2_s_cache_mode; 2868 2869 if (pg == opg) { 2870 /* 2871 * We're changing the attrs of an existing mapping. 2872 */ 2873 simple_lock(&md->pvh_slock); 2874 oflags = pmap_modify_pv(md, pa, pm, va, 2875 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2876 PVF_MOD | PVF_REF, nflags); 2877 simple_unlock(&md->pvh_slock); 2878 2879 #ifdef PMAP_CACHE_VIVT 2880 /* 2881 * We may need to flush the cache if we're 2882 * doing rw-ro... 2883 */ 2884 if (pm->pm_cstate.cs_cache_d && 2885 (oflags & PVF_NC) == 0 && 2886 (opte & L2_S_PROT_W) != 0 && 2887 (prot & VM_PROT_WRITE) == 0) 2888 cpu_dcache_wb_range(va, PAGE_SIZE); 2889 #endif 2890 } else { 2891 /* 2892 * New mapping, or changing the backing page 2893 * of an existing mapping. 2894 */ 2895 if (opg) { 2896 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2897 paddr_t opa; 2898 2899 opa = VM_PAGE_TO_PHYS(opg); 2900 2901 /* 2902 * Replacing an existing mapping with a new one. 2903 * It is part of our managed memory so we 2904 * must remove it from the PV list 2905 */ 2906 simple_lock(&omd->pvh_slock); 2907 pv = pmap_remove_pv(omd, opa, pm, va); 2908 pmap_vac_me_harder(omd, opa, pm, 0); 2909 simple_unlock(&omd->pvh_slock); 2910 oflags = pv->pv_flags; 2911 2912 #ifdef PMAP_CACHE_VIVT 2913 /* 2914 * If the old mapping was valid (ref/mod 2915 * emulation creates 'invalid' mappings 2916 * initially) then make sure to frob 2917 * the cache. 2918 */ 2919 if ((oflags & PVF_NC) == 0 && 2920 l2pte_valid(opte)) { 2921 if (PV_BEEN_EXECD(oflags)) { 2922 pmap_idcache_wbinv_range(pm, va, 2923 PAGE_SIZE); 2924 } else 2925 if (PV_BEEN_REFD(oflags)) { 2926 pmap_dcache_wb_range(pm, va, 2927 PAGE_SIZE, true, 2928 (oflags & PVF_WRITE) == 0); 2929 } 2930 } 2931 #endif 2932 } else 2933 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2934 if ((flags & PMAP_CANFAIL) == 0) 2935 panic("pmap_enter: no pv entries"); 2936 2937 if (pm != pmap_kernel()) 2938 pmap_free_l2_bucket(pm, l2b, 0); 2939 pmap_release_pmap_lock(pm); 2940 PMAP_MAP_TO_HEAD_UNLOCK(); 2941 NPDEBUG(PDB_ENTER, 2942 printf("pmap_enter: ENOMEM\n")); 2943 return (ENOMEM); 2944 } 2945 2946 pmap_enter_pv(md, VM_PAGE_TO_PHYS(pg), pv, pm, va, nflags); 2947 } 2948 } else { 2949 /* 2950 * We're mapping an unmanaged page. 2951 * These are always readable, and possibly writable, from 2952 * the get go as we don't need to track ref/mod status. 2953 */ 2954 npte |= L2_S_PROTO; 2955 if (prot & VM_PROT_WRITE) 2956 npte |= L2_S_PROT_W; 2957 2958 /* 2959 * Make sure the vector table is mapped cacheable 2960 */ 2961 if (pm != pmap_kernel() && va == vector_page) 2962 npte |= pte_l2_s_cache_mode; 2963 2964 if (opg) { 2965 /* 2966 * Looks like there's an existing 'managed' mapping 2967 * at this address. 2968 */ 2969 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2970 simple_lock(&omd->pvh_slock); 2971 pv = pmap_remove_pv(omd, VM_PAGE_TO_PHYS(opg), pm, va); 2972 pmap_vac_me_harder(omd, VM_PAGE_TO_PHYS(opg), pm, 0); 2973 simple_unlock(&omd->pvh_slock); 2974 oflags = pv->pv_flags; 2975 2976 #ifdef PMAP_CACHE_VIVT 2977 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2978 if (PV_BEEN_EXECD(oflags)) 2979 pmap_idcache_wbinv_range(pm, va, 2980 PAGE_SIZE); 2981 else 2982 if (PV_BEEN_REFD(oflags)) 2983 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2984 true, (oflags & PVF_WRITE) == 0); 2985 } 2986 #endif 2987 pool_put(&pmap_pv_pool, pv); 2988 } 2989 } 2990 2991 /* 2992 * Make sure userland mappings get the right permissions 2993 */ 2994 if (pm != pmap_kernel() && va != vector_page) 2995 npte |= L2_S_PROT_U; 2996 2997 /* 2998 * Keep the stats up to date 2999 */ 3000 if (opte == 0) { 3001 l2b->l2b_occupancy++; 3002 pm->pm_stats.resident_count++; 3003 } 3004 3005 NPDEBUG(PDB_ENTER, 3006 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3007 3008 /* 3009 * If this is just a wiring change, the two PTEs will be 3010 * identical, so there's no need to update the page table. 3011 */ 3012 if (npte != opte) { 3013 bool is_cached = pmap_is_cached(pm); 3014 3015 *ptep = npte; 3016 if (is_cached) { 3017 /* 3018 * We only need to frob the cache/tlb if this pmap 3019 * is current 3020 */ 3021 PTE_SYNC(ptep); 3022 if (va != vector_page && l2pte_valid(npte)) { 3023 /* 3024 * This mapping is likely to be accessed as 3025 * soon as we return to userland. Fix up the 3026 * L1 entry to avoid taking another 3027 * page/domain fault. 3028 */ 3029 pd_entry_t *pl1pd, l1pd; 3030 3031 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3032 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3033 L1_C_PROTO; 3034 if (*pl1pd != l1pd) { 3035 *pl1pd = l1pd; 3036 PTE_SYNC(pl1pd); 3037 } 3038 } 3039 } 3040 3041 if (PV_BEEN_EXECD(oflags)) 3042 pmap_tlb_flushID_SE(pm, va); 3043 else 3044 if (PV_BEEN_REFD(oflags)) 3045 pmap_tlb_flushD_SE(pm, va); 3046 3047 NPDEBUG(PDB_ENTER, 3048 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3049 is_cached, pm->pm_cstate.cs_all)); 3050 3051 if (pg != NULL) { 3052 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3053 simple_lock(&md->pvh_slock); 3054 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pm, va); 3055 simple_unlock(&md->pvh_slock); 3056 } 3057 } 3058 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3059 if (pg) { 3060 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3061 simple_lock(&md->pvh_slock); 3062 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3063 KASSERT(((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0)); 3064 simple_unlock(&md->pvh_slock); 3065 } 3066 #endif 3067 3068 pmap_release_pmap_lock(pm); 3069 PMAP_MAP_TO_HEAD_UNLOCK(); 3070 3071 return (0); 3072 } 3073 3074 /* 3075 * pmap_remove() 3076 * 3077 * pmap_remove is responsible for nuking a number of mappings for a range 3078 * of virtual address space in the current pmap. To do this efficiently 3079 * is interesting, because in a number of cases a wide virtual address 3080 * range may be supplied that contains few actual mappings. So, the 3081 * optimisations are: 3082 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3083 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3084 * maybe do just a partial cache clean. This path of execution is 3085 * complicated by the fact that the cache must be flushed _before_ 3086 * the PTE is nuked, being a VAC :-) 3087 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3088 * all invalidations until pmap_update(), since pmap_remove_all() has 3089 * already flushed the cache. 3090 * 4. Maybe later fast-case a single page, but I don't think this is 3091 * going to make _that_ much difference overall. 3092 */ 3093 3094 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3095 3096 void 3097 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3098 { 3099 struct l2_bucket *l2b; 3100 vaddr_t next_bucket; 3101 pt_entry_t *ptep; 3102 u_int cleanlist_idx, total, cnt; 3103 struct { 3104 vaddr_t va; 3105 pt_entry_t *ptep; 3106 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3107 u_int mappings, is_exec, is_refd; 3108 3109 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3110 "eva=%08lx\n", pm, sva, eva)); 3111 3112 /* 3113 * we lock in the pmap => pv_head direction 3114 */ 3115 PMAP_MAP_TO_HEAD_LOCK(); 3116 pmap_acquire_pmap_lock(pm); 3117 3118 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3119 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3120 if (pm->pm_cstate.cs_tlb == 0) 3121 pm->pm_remove_all = true; 3122 } else 3123 cleanlist_idx = 0; 3124 3125 total = 0; 3126 3127 while (sva < eva) { 3128 /* 3129 * Do one L2 bucket's worth at a time. 3130 */ 3131 next_bucket = L2_NEXT_BUCKET(sva); 3132 if (next_bucket > eva) 3133 next_bucket = eva; 3134 3135 l2b = pmap_get_l2_bucket(pm, sva); 3136 if (l2b == NULL) { 3137 sva = next_bucket; 3138 continue; 3139 } 3140 3141 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3142 3143 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3144 struct vm_page *pg; 3145 pt_entry_t pte; 3146 paddr_t pa; 3147 3148 pte = *ptep; 3149 3150 if (pte == 0) { 3151 /* Nothing here, move along */ 3152 continue; 3153 } 3154 3155 pa = l2pte_pa(pte); 3156 is_exec = 0; 3157 is_refd = 1; 3158 3159 /* 3160 * Update flags. In a number of circumstances, 3161 * we could cluster a lot of these and do a 3162 * number of sequential pages in one go. 3163 */ 3164 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3165 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3166 struct pv_entry *pv; 3167 simple_lock(&md->pvh_slock); 3168 pv = pmap_remove_pv(md, VM_PAGE_TO_PHYS(pg), pm, sva); 3169 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pm, 0); 3170 simple_unlock(&md->pvh_slock); 3171 if (pv != NULL) { 3172 if (pm->pm_remove_all == false) { 3173 is_exec = 3174 PV_BEEN_EXECD(pv->pv_flags); 3175 is_refd = 3176 PV_BEEN_REFD(pv->pv_flags); 3177 } 3178 pool_put(&pmap_pv_pool, pv); 3179 } 3180 } 3181 mappings++; 3182 3183 if (!l2pte_valid(pte)) { 3184 /* 3185 * Ref/Mod emulation is still active for this 3186 * mapping, therefore it is has not yet been 3187 * accessed. No need to frob the cache/tlb. 3188 */ 3189 *ptep = 0; 3190 PTE_SYNC_CURRENT(pm, ptep); 3191 continue; 3192 } 3193 3194 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3195 /* Add to the clean list. */ 3196 cleanlist[cleanlist_idx].ptep = ptep; 3197 cleanlist[cleanlist_idx].va = 3198 sva | (is_exec & 1); 3199 cleanlist_idx++; 3200 } else 3201 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3202 /* Nuke everything if needed. */ 3203 #ifdef PMAP_CACHE_VIVT 3204 pmap_idcache_wbinv_all(pm); 3205 #endif 3206 pmap_tlb_flushID(pm); 3207 3208 /* 3209 * Roll back the previous PTE list, 3210 * and zero out the current PTE. 3211 */ 3212 for (cnt = 0; 3213 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3214 *cleanlist[cnt].ptep = 0; 3215 PTE_SYNC(cleanlist[cnt].ptep); 3216 } 3217 *ptep = 0; 3218 PTE_SYNC(ptep); 3219 cleanlist_idx++; 3220 pm->pm_remove_all = true; 3221 } else { 3222 *ptep = 0; 3223 PTE_SYNC(ptep); 3224 if (pm->pm_remove_all == false) { 3225 if (is_exec) 3226 pmap_tlb_flushID_SE(pm, sva); 3227 else 3228 if (is_refd) 3229 pmap_tlb_flushD_SE(pm, sva); 3230 } 3231 } 3232 } 3233 3234 /* 3235 * Deal with any left overs 3236 */ 3237 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3238 total += cleanlist_idx; 3239 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3240 if (pm->pm_cstate.cs_all != 0) { 3241 vaddr_t clva = cleanlist[cnt].va & ~1; 3242 if (cleanlist[cnt].va & 1) { 3243 #ifdef PMAP_CACHE_VIVT 3244 pmap_idcache_wbinv_range(pm, 3245 clva, PAGE_SIZE); 3246 #endif 3247 pmap_tlb_flushID_SE(pm, clva); 3248 } else { 3249 #ifdef PMAP_CACHE_VIVT 3250 pmap_dcache_wb_range(pm, 3251 clva, PAGE_SIZE, true, 3252 false); 3253 #endif 3254 pmap_tlb_flushD_SE(pm, clva); 3255 } 3256 } 3257 *cleanlist[cnt].ptep = 0; 3258 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3259 } 3260 3261 /* 3262 * If it looks like we're removing a whole bunch 3263 * of mappings, it's faster to just write-back 3264 * the whole cache now and defer TLB flushes until 3265 * pmap_update() is called. 3266 */ 3267 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3268 cleanlist_idx = 0; 3269 else { 3270 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3271 #ifdef PMAP_CACHE_VIVT 3272 pmap_idcache_wbinv_all(pm); 3273 #endif 3274 pm->pm_remove_all = true; 3275 } 3276 } 3277 3278 pmap_free_l2_bucket(pm, l2b, mappings); 3279 pm->pm_stats.resident_count -= mappings; 3280 } 3281 3282 pmap_release_pmap_lock(pm); 3283 PMAP_MAP_TO_HEAD_UNLOCK(); 3284 } 3285 3286 #ifdef PMAP_CACHE_VIPT 3287 static struct pv_entry * 3288 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3289 { 3290 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3291 struct pv_entry *pv; 3292 3293 simple_lock(&md->pvh_slock); 3294 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3295 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3296 3297 pv = pmap_remove_pv(md, VM_PAGE_TO_PHYS(pg), pmap_kernel(), va); 3298 KASSERT(pv); 3299 KASSERT(pv->pv_flags & PVF_KENTRY); 3300 3301 /* 3302 * If we are removing a writeable mapping to a cached exec page, 3303 * if it's the last mapping then clear it execness other sync 3304 * the page to the icache. 3305 */ 3306 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3307 && (pv->pv_flags & PVF_WRITE) != 0) { 3308 if (SLIST_EMPTY(&md->pvh_list)) { 3309 md->pvh_attrs &= ~PVF_EXEC; 3310 PMAPCOUNT(exec_discarded_kremove); 3311 } else { 3312 pmap_syncicache_page(md, VM_PAGE_TO_PHYS(pg)); 3313 PMAPCOUNT(exec_synced_kremove); 3314 } 3315 } 3316 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pmap_kernel(), 0); 3317 simple_unlock(&md->pvh_slock); 3318 3319 return pv; 3320 } 3321 #endif /* PMAP_CACHE_VIPT */ 3322 3323 /* 3324 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3325 * 3326 * We assume there is already sufficient KVM space available 3327 * to do this, as we can't allocate L2 descriptor tables/metadata 3328 * from here. 3329 */ 3330 void 3331 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3332 { 3333 struct l2_bucket *l2b; 3334 pt_entry_t *ptep, opte; 3335 #ifdef PMAP_CACHE_VIVT 3336 struct vm_page *pg = (prot & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3337 #endif 3338 #ifdef PMAP_CACHE_VIPT 3339 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3340 struct vm_page *opg; 3341 struct pv_entry *pv = NULL; 3342 #endif 3343 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3344 3345 NPDEBUG(PDB_KENTER, 3346 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3347 va, pa, prot)); 3348 3349 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3350 KDASSERT(l2b != NULL); 3351 3352 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3353 opte = *ptep; 3354 3355 if (opte == 0) { 3356 PMAPCOUNT(kenter_mappings); 3357 l2b->l2b_occupancy++; 3358 } else { 3359 PMAPCOUNT(kenter_remappings); 3360 #ifdef PMAP_CACHE_VIPT 3361 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3362 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3363 if (opg) { 3364 KASSERT(opg != pg); 3365 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3366 KASSERT((prot & PMAP_KMPAGE) == 0); 3367 simple_lock(&omd->pvh_slock); 3368 pv = pmap_kremove_pg(opg, va); 3369 simple_unlock(&omd->pvh_slock); 3370 } 3371 #endif 3372 if (l2pte_valid(opte)) { 3373 #ifdef PMAP_CACHE_VIVT 3374 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3375 #endif 3376 cpu_tlb_flushD_SE(va); 3377 cpu_cpwait(); 3378 } 3379 } 3380 3381 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3382 pte_l2_s_cache_mode; 3383 PTE_SYNC(ptep); 3384 3385 if (pg) { 3386 if (prot & PMAP_KMPAGE) { 3387 simple_lock(&md->pvh_slock); 3388 KASSERT(md->urw_mappings == 0); 3389 KASSERT(md->uro_mappings == 0); 3390 KASSERT(md->krw_mappings == 0); 3391 KASSERT(md->kro_mappings == 0); 3392 #ifdef PMAP_CACHE_VIPT 3393 KASSERT(pv == NULL); 3394 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3395 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3396 /* if there is a color conflict, evict from cache. */ 3397 if (pmap_is_page_colored_p(md) 3398 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3399 PMAPCOUNT(vac_color_change); 3400 pmap_flush_page(md, VM_PAGE_TO_PHYS(pg), PMAP_FLUSH_PRIMARY); 3401 } else if (md->pvh_attrs & PVF_MULTCLR) { 3402 /* 3403 * If this page has multiple colors, expunge 3404 * them. 3405 */ 3406 PMAPCOUNT(vac_flush_lots2); 3407 pmap_flush_page(md, VM_PAGE_TO_PHYS(pg), PMAP_FLUSH_SECONDARY); 3408 } 3409 md->pvh_attrs &= PAGE_SIZE - 1; 3410 md->pvh_attrs |= PVF_KMPAGE 3411 | PVF_COLORED | PVF_DIRTY 3412 | (va & arm_cache_prefer_mask); 3413 #endif 3414 #ifdef PMAP_CACHE_VIVT 3415 md->pvh_attrs |= PVF_KMPAGE; 3416 #endif 3417 pmap_kmpages++; 3418 simple_unlock(&md->pvh_slock); 3419 #ifdef PMAP_CACHE_VIPT 3420 } else { 3421 if (pv == NULL) { 3422 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3423 KASSERT(pv != NULL); 3424 } 3425 pmap_enter_pv(md, VM_PAGE_TO_PHYS(pg), pv, pmap_kernel(), va, 3426 PVF_WIRED | PVF_KENTRY 3427 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3428 if ((prot & VM_PROT_WRITE) 3429 && !(md->pvh_attrs & PVF_NC)) 3430 md->pvh_attrs |= PVF_DIRTY; 3431 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3432 simple_lock(&md->pvh_slock); 3433 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pmap_kernel(), va); 3434 simple_unlock(&md->pvh_slock); 3435 #endif 3436 } 3437 #ifdef PMAP_CACHE_VIPT 3438 } else { 3439 if (pv != NULL) 3440 pool_put(&pmap_pv_pool, pv); 3441 #endif 3442 } 3443 } 3444 3445 void 3446 pmap_kremove(vaddr_t va, vsize_t len) 3447 { 3448 struct l2_bucket *l2b; 3449 pt_entry_t *ptep, *sptep, opte; 3450 vaddr_t next_bucket, eva; 3451 u_int mappings; 3452 struct vm_page *opg; 3453 3454 PMAPCOUNT(kenter_unmappings); 3455 3456 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3457 va, len)); 3458 3459 eva = va + len; 3460 3461 while (va < eva) { 3462 next_bucket = L2_NEXT_BUCKET(va); 3463 if (next_bucket > eva) 3464 next_bucket = eva; 3465 3466 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3467 KDASSERT(l2b != NULL); 3468 3469 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3470 mappings = 0; 3471 3472 while (va < next_bucket) { 3473 opte = *ptep; 3474 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3475 if (opg) { 3476 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3477 if (omd->pvh_attrs & PVF_KMPAGE) { 3478 simple_lock(&omd->pvh_slock); 3479 KASSERT(omd->urw_mappings == 0); 3480 KASSERT(omd->uro_mappings == 0); 3481 KASSERT(omd->krw_mappings == 0); 3482 KASSERT(omd->kro_mappings == 0); 3483 omd->pvh_attrs &= ~PVF_KMPAGE; 3484 #ifdef PMAP_CACHE_VIPT 3485 omd->pvh_attrs &= ~PVF_WRITE; 3486 #endif 3487 pmap_kmpages--; 3488 simple_unlock(&omd->pvh_slock); 3489 #ifdef PMAP_CACHE_VIPT 3490 } else { 3491 pool_put(&pmap_pv_pool, 3492 pmap_kremove_pg(opg, va)); 3493 #endif 3494 } 3495 } 3496 if (l2pte_valid(opte)) { 3497 #ifdef PMAP_CACHE_VIVT 3498 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3499 #endif 3500 cpu_tlb_flushD_SE(va); 3501 } 3502 if (opte) { 3503 *ptep = 0; 3504 mappings++; 3505 } 3506 va += PAGE_SIZE; 3507 ptep++; 3508 } 3509 KDASSERT(mappings <= l2b->l2b_occupancy); 3510 l2b->l2b_occupancy -= mappings; 3511 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3512 } 3513 cpu_cpwait(); 3514 } 3515 3516 bool 3517 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3518 { 3519 struct l2_dtable *l2; 3520 pd_entry_t *pl1pd, l1pd; 3521 pt_entry_t *ptep, pte; 3522 paddr_t pa; 3523 u_int l1idx; 3524 3525 pmap_acquire_pmap_lock(pm); 3526 3527 l1idx = L1_IDX(va); 3528 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3529 l1pd = *pl1pd; 3530 3531 if (l1pte_section_p(l1pd)) { 3532 /* 3533 * These should only happen for pmap_kernel() 3534 */ 3535 KDASSERT(pm == pmap_kernel()); 3536 pmap_release_pmap_lock(pm); 3537 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3538 } else { 3539 /* 3540 * Note that we can't rely on the validity of the L1 3541 * descriptor as an indication that a mapping exists. 3542 * We have to look it up in the L2 dtable. 3543 */ 3544 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3545 3546 if (l2 == NULL || 3547 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3548 pmap_release_pmap_lock(pm); 3549 return false; 3550 } 3551 3552 ptep = &ptep[l2pte_index(va)]; 3553 pte = *ptep; 3554 pmap_release_pmap_lock(pm); 3555 3556 if (pte == 0) 3557 return false; 3558 3559 switch (pte & L2_TYPE_MASK) { 3560 case L2_TYPE_L: 3561 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3562 break; 3563 3564 default: 3565 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3566 break; 3567 } 3568 } 3569 3570 if (pap != NULL) 3571 *pap = pa; 3572 3573 return true; 3574 } 3575 3576 void 3577 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3578 { 3579 struct l2_bucket *l2b; 3580 pt_entry_t *ptep, pte; 3581 vaddr_t next_bucket; 3582 u_int flags; 3583 u_int clr_mask; 3584 int flush; 3585 3586 NPDEBUG(PDB_PROTECT, 3587 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3588 pm, sva, eva, prot)); 3589 3590 if ((prot & VM_PROT_READ) == 0) { 3591 pmap_remove(pm, sva, eva); 3592 return; 3593 } 3594 3595 if (prot & VM_PROT_WRITE) { 3596 /* 3597 * If this is a read->write transition, just ignore it and let 3598 * uvm_fault() take care of it later. 3599 */ 3600 return; 3601 } 3602 3603 PMAP_MAP_TO_HEAD_LOCK(); 3604 pmap_acquire_pmap_lock(pm); 3605 3606 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3607 flags = 0; 3608 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3609 3610 while (sva < eva) { 3611 next_bucket = L2_NEXT_BUCKET(sva); 3612 if (next_bucket > eva) 3613 next_bucket = eva; 3614 3615 l2b = pmap_get_l2_bucket(pm, sva); 3616 if (l2b == NULL) { 3617 sva = next_bucket; 3618 continue; 3619 } 3620 3621 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3622 3623 while (sva < next_bucket) { 3624 pte = *ptep; 3625 if (l2pte_valid(pte) != 0 && (pte & L2_S_PROT_W) != 0) { 3626 struct vm_page *pg; 3627 u_int f; 3628 3629 #ifdef PMAP_CACHE_VIVT 3630 /* 3631 * OK, at this point, we know we're doing 3632 * write-protect operation. If the pmap is 3633 * active, write-back the page. 3634 */ 3635 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3636 false, false); 3637 #endif 3638 3639 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3640 pte &= ~L2_S_PROT_W; 3641 *ptep = pte; 3642 PTE_SYNC(ptep); 3643 3644 if (pg != NULL) { 3645 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3646 simple_lock(&md->pvh_slock); 3647 f = pmap_modify_pv(md, VM_PAGE_TO_PHYS(pg), pm, sva, 3648 clr_mask, 0); 3649 pmap_vac_me_harder(md, VM_PAGE_TO_PHYS(pg), pm, sva); 3650 simple_unlock(&md->pvh_slock); 3651 } else 3652 f = PVF_REF | PVF_EXEC; 3653 3654 if (flush >= 0) { 3655 flush++; 3656 flags |= f; 3657 } else 3658 if (PV_BEEN_EXECD(f)) 3659 pmap_tlb_flushID_SE(pm, sva); 3660 else 3661 if (PV_BEEN_REFD(f)) 3662 pmap_tlb_flushD_SE(pm, sva); 3663 } 3664 3665 sva += PAGE_SIZE; 3666 ptep++; 3667 } 3668 } 3669 3670 pmap_release_pmap_lock(pm); 3671 PMAP_MAP_TO_HEAD_UNLOCK(); 3672 3673 if (flush) { 3674 if (PV_BEEN_EXECD(flags)) 3675 pmap_tlb_flushID(pm); 3676 else 3677 if (PV_BEEN_REFD(flags)) 3678 pmap_tlb_flushD(pm); 3679 } 3680 } 3681 3682 void 3683 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3684 { 3685 struct l2_bucket *l2b; 3686 pt_entry_t *ptep; 3687 vaddr_t next_bucket; 3688 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3689 3690 NPDEBUG(PDB_EXEC, 3691 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3692 pm, sva, eva)); 3693 3694 PMAP_MAP_TO_HEAD_LOCK(); 3695 pmap_acquire_pmap_lock(pm); 3696 3697 while (sva < eva) { 3698 next_bucket = L2_NEXT_BUCKET(sva); 3699 if (next_bucket > eva) 3700 next_bucket = eva; 3701 3702 l2b = pmap_get_l2_bucket(pm, sva); 3703 if (l2b == NULL) { 3704 sva = next_bucket; 3705 continue; 3706 } 3707 3708 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3709 sva < next_bucket; 3710 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3711 if (l2pte_valid(*ptep)) { 3712 cpu_icache_sync_range(sva, 3713 min(page_size, eva - sva)); 3714 } 3715 } 3716 } 3717 3718 pmap_release_pmap_lock(pm); 3719 PMAP_MAP_TO_HEAD_UNLOCK(); 3720 } 3721 3722 void 3723 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3724 { 3725 3726 NPDEBUG(PDB_PROTECT, 3727 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 3728 pg, VM_PAGE_TO_PHYS(pg), prot)); 3729 3730 switch(prot) { 3731 case VM_PROT_READ|VM_PROT_WRITE: 3732 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3733 pmap_clearbit(pg, PVF_EXEC); 3734 break; 3735 #endif 3736 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3737 break; 3738 3739 case VM_PROT_READ: 3740 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3741 pmap_clearbit(pg, PVF_WRITE|PVF_EXEC); 3742 break; 3743 #endif 3744 case VM_PROT_READ|VM_PROT_EXECUTE: 3745 pmap_clearbit(pg, PVF_WRITE); 3746 break; 3747 3748 default: 3749 pmap_page_remove(pg); 3750 break; 3751 } 3752 } 3753 3754 /* 3755 * pmap_clear_modify: 3756 * 3757 * Clear the "modified" attribute for a page. 3758 */ 3759 bool 3760 pmap_clear_modify(struct vm_page *pg) 3761 { 3762 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3763 bool rv; 3764 3765 if (md->pvh_attrs & PVF_MOD) { 3766 rv = true; 3767 #ifdef PMAP_CACHE_VIPT 3768 /* 3769 * If we are going to clear the modified bit and there are 3770 * no other modified bits set, flush the page to memory and 3771 * mark it clean. 3772 */ 3773 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3774 pmap_flush_page(md, VM_PAGE_TO_PHYS(pg), PMAP_CLEAN_PRIMARY); 3775 #endif 3776 pmap_clearbit(pg, PVF_MOD); 3777 } else 3778 rv = false; 3779 3780 return (rv); 3781 } 3782 3783 /* 3784 * pmap_clear_reference: 3785 * 3786 * Clear the "referenced" attribute for a page. 3787 */ 3788 bool 3789 pmap_clear_reference(struct vm_page *pg) 3790 { 3791 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3792 bool rv; 3793 3794 if (md->pvh_attrs & PVF_REF) { 3795 rv = true; 3796 pmap_clearbit(pg, PVF_REF); 3797 } else 3798 rv = false; 3799 3800 return (rv); 3801 } 3802 3803 /* 3804 * pmap_is_modified: 3805 * 3806 * Test if a page has the "modified" attribute. 3807 */ 3808 /* See <arm/arm32/pmap.h> */ 3809 3810 /* 3811 * pmap_is_referenced: 3812 * 3813 * Test if a page has the "referenced" attribute. 3814 */ 3815 /* See <arm/arm32/pmap.h> */ 3816 3817 int 3818 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3819 { 3820 struct l2_dtable *l2; 3821 struct l2_bucket *l2b; 3822 pd_entry_t *pl1pd, l1pd; 3823 pt_entry_t *ptep, pte; 3824 paddr_t pa; 3825 u_int l1idx; 3826 int rv = 0; 3827 3828 PMAP_MAP_TO_HEAD_LOCK(); 3829 pmap_acquire_pmap_lock(pm); 3830 3831 l1idx = L1_IDX(va); 3832 3833 /* 3834 * If there is no l2_dtable for this address, then the process 3835 * has no business accessing it. 3836 * 3837 * Note: This will catch userland processes trying to access 3838 * kernel addresses. 3839 */ 3840 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3841 if (l2 == NULL) 3842 goto out; 3843 3844 /* 3845 * Likewise if there is no L2 descriptor table 3846 */ 3847 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3848 if (l2b->l2b_kva == NULL) 3849 goto out; 3850 3851 /* 3852 * Check the PTE itself. 3853 */ 3854 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3855 pte = *ptep; 3856 if (pte == 0) 3857 goto out; 3858 3859 /* 3860 * Catch a userland access to the vector page mapped at 0x0 3861 */ 3862 if (user && (pte & L2_S_PROT_U) == 0) 3863 goto out; 3864 3865 pa = l2pte_pa(pte); 3866 3867 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 3868 /* 3869 * This looks like a good candidate for "page modified" 3870 * emulation... 3871 */ 3872 struct pv_entry *pv; 3873 struct vm_page *pg; 3874 3875 /* Extract the physical address of the page */ 3876 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3877 goto out; 3878 3879 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3880 3881 /* Get the current flags for this page. */ 3882 simple_lock(&md->pvh_slock); 3883 3884 pv = pmap_find_pv(md, pm, va); 3885 if (pv == NULL) { 3886 simple_unlock(&md->pvh_slock); 3887 goto out; 3888 } 3889 3890 /* 3891 * Do the flags say this page is writable? If not then it 3892 * is a genuine write fault. If yes then the write fault is 3893 * our fault as we did not reflect the write access in the 3894 * PTE. Now we know a write has occurred we can correct this 3895 * and also set the modified bit 3896 */ 3897 if ((pv->pv_flags & PVF_WRITE) == 0) { 3898 simple_unlock(&md->pvh_slock); 3899 goto out; 3900 } 3901 3902 NPDEBUG(PDB_FOLLOW, 3903 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3904 pm, va, VM_PAGE_TO_PHYS(pg))); 3905 3906 md->pvh_attrs |= PVF_REF | PVF_MOD; 3907 pv->pv_flags |= PVF_REF | PVF_MOD; 3908 #ifdef PMAP_CACHE_VIPT 3909 /* 3910 * If there are cacheable mappings for this page, mark it dirty. 3911 */ 3912 if ((md->pvh_attrs & PVF_NC) == 0) 3913 md->pvh_attrs |= PVF_DIRTY; 3914 #endif 3915 simple_unlock(&md->pvh_slock); 3916 3917 /* 3918 * Re-enable write permissions for the page. No need to call 3919 * pmap_vac_me_harder(), since this is just a 3920 * modified-emulation fault, and the PVF_WRITE bit isn't 3921 * changing. We've already set the cacheable bits based on 3922 * the assumption that we can write to this page. 3923 */ 3924 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 3925 PTE_SYNC(ptep); 3926 rv = 1; 3927 } else 3928 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3929 /* 3930 * This looks like a good candidate for "page referenced" 3931 * emulation. 3932 */ 3933 struct pv_entry *pv; 3934 struct vm_page *pg; 3935 3936 /* Extract the physical address of the page */ 3937 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3938 goto out; 3939 3940 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3941 3942 /* Get the current flags for this page. */ 3943 simple_lock(&md->pvh_slock); 3944 3945 pv = pmap_find_pv(md, pm, va); 3946 if (pv == NULL) { 3947 simple_unlock(&md->pvh_slock); 3948 goto out; 3949 } 3950 3951 md->pvh_attrs |= PVF_REF; 3952 pv->pv_flags |= PVF_REF; 3953 simple_unlock(&md->pvh_slock); 3954 3955 NPDEBUG(PDB_FOLLOW, 3956 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3957 pm, va, VM_PAGE_TO_PHYS(pg))); 3958 3959 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 3960 PTE_SYNC(ptep); 3961 rv = 1; 3962 } 3963 3964 /* 3965 * We know there is a valid mapping here, so simply 3966 * fix up the L1 if necessary. 3967 */ 3968 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3969 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3970 if (*pl1pd != l1pd) { 3971 *pl1pd = l1pd; 3972 PTE_SYNC(pl1pd); 3973 rv = 1; 3974 } 3975 3976 #ifdef CPU_SA110 3977 /* 3978 * There are bugs in the rev K SA110. This is a check for one 3979 * of them. 3980 */ 3981 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3982 curcpu()->ci_arm_cpurev < 3) { 3983 /* Always current pmap */ 3984 if (l2pte_valid(pte)) { 3985 extern int kernel_debug; 3986 if (kernel_debug & 1) { 3987 struct proc *p = curlwp->l_proc; 3988 printf("prefetch_abort: page is already " 3989 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3990 printf("prefetch_abort: pc=%08lx proc=%p " 3991 "process=%s\n", va, p, p->p_comm); 3992 printf("prefetch_abort: far=%08x fs=%x\n", 3993 cpu_faultaddress(), cpu_faultstatus()); 3994 } 3995 #ifdef DDB 3996 if (kernel_debug & 2) 3997 Debugger(); 3998 #endif 3999 rv = 1; 4000 } 4001 } 4002 #endif /* CPU_SA110 */ 4003 4004 #ifdef DEBUG 4005 /* 4006 * If 'rv == 0' at this point, it generally indicates that there is a 4007 * stale TLB entry for the faulting address. This happens when two or 4008 * more processes are sharing an L1. Since we don't flush the TLB on 4009 * a context switch between such processes, we can take domain faults 4010 * for mappings which exist at the same VA in both processes. EVEN IF 4011 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4012 * example. 4013 * 4014 * This is extremely likely to happen if pmap_enter() updated the L1 4015 * entry for a recently entered mapping. In this case, the TLB is 4016 * flushed for the new mapping, but there may still be TLB entries for 4017 * other mappings belonging to other processes in the 1MB range 4018 * covered by the L1 entry. 4019 * 4020 * Since 'rv == 0', we know that the L1 already contains the correct 4021 * value, so the fault must be due to a stale TLB entry. 4022 * 4023 * Since we always need to flush the TLB anyway in the case where we 4024 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4025 * stale TLB entries dynamically. 4026 * 4027 * However, the above condition can ONLY happen if the current L1 is 4028 * being shared. If it happens when the L1 is unshared, it indicates 4029 * that other parts of the pmap are not doing their job WRT managing 4030 * the TLB. 4031 */ 4032 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4033 extern int last_fault_code; 4034 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4035 pm, va, ftype); 4036 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4037 l2, l2b, ptep, pl1pd); 4038 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4039 pte, l1pd, last_fault_code); 4040 #ifdef DDB 4041 Debugger(); 4042 #endif 4043 } 4044 #endif 4045 4046 cpu_tlb_flushID_SE(va); 4047 cpu_cpwait(); 4048 4049 rv = 1; 4050 4051 out: 4052 pmap_release_pmap_lock(pm); 4053 PMAP_MAP_TO_HEAD_UNLOCK(); 4054 4055 return (rv); 4056 } 4057 4058 /* 4059 * Routine: pmap_procwr 4060 * 4061 * Function: 4062 * Synchronize caches corresponding to [addr, addr+len) in p. 4063 * 4064 */ 4065 void 4066 pmap_procwr(struct proc *p, vaddr_t va, int len) 4067 { 4068 /* We only need to do anything if it is the current process. */ 4069 if (p == curproc) 4070 cpu_icache_sync_range(va, len); 4071 } 4072 4073 /* 4074 * Routine: pmap_unwire 4075 * Function: Clear the wired attribute for a map/virtual-address pair. 4076 * 4077 * In/out conditions: 4078 * The mapping must already exist in the pmap. 4079 */ 4080 void 4081 pmap_unwire(pmap_t pm, vaddr_t va) 4082 { 4083 struct l2_bucket *l2b; 4084 pt_entry_t *ptep, pte; 4085 struct vm_page *pg; 4086 paddr_t pa; 4087 4088 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4089 4090 PMAP_MAP_TO_HEAD_LOCK(); 4091 pmap_acquire_pmap_lock(pm); 4092 4093 l2b = pmap_get_l2_bucket(pm, va); 4094 KDASSERT(l2b != NULL); 4095 4096 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4097 pte = *ptep; 4098 4099 /* Extract the physical address of the page */ 4100 pa = l2pte_pa(pte); 4101 4102 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4103 /* Update the wired bit in the pv entry for this page. */ 4104 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4105 simple_lock(&md->pvh_slock); 4106 (void) pmap_modify_pv(md, VM_PAGE_TO_PHYS(pg), pm, va, PVF_WIRED, 0); 4107 simple_unlock(&md->pvh_slock); 4108 } 4109 4110 pmap_release_pmap_lock(pm); 4111 PMAP_MAP_TO_HEAD_UNLOCK(); 4112 } 4113 4114 void 4115 pmap_activate(struct lwp *l) 4116 { 4117 extern int block_userspace_access; 4118 pmap_t opm, npm, rpm; 4119 uint32_t odacr, ndacr; 4120 int oldirqstate; 4121 4122 /* 4123 * If activating a non-current lwp or the current lwp is 4124 * already active, just return. 4125 */ 4126 if (l != curlwp || 4127 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4128 return; 4129 4130 npm = l->l_proc->p_vmspace->vm_map.pmap; 4131 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4132 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4133 4134 /* 4135 * If TTB and DACR are unchanged, short-circuit all the 4136 * TLB/cache management stuff. 4137 */ 4138 if (pmap_previous_active_lwp != NULL) { 4139 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4140 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4141 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4142 4143 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4144 goto all_done; 4145 } else 4146 opm = NULL; 4147 4148 PMAPCOUNT(activations); 4149 block_userspace_access = 1; 4150 4151 /* 4152 * If switching to a user vmspace which is different to the 4153 * most recent one, and the most recent one is potentially 4154 * live in the cache, we must write-back and invalidate the 4155 * entire cache. 4156 */ 4157 rpm = pmap_recent_user; 4158 4159 /* 4160 * XXXSCW: There's a corner case here which can leave turds in the cache as 4161 * reported in kern/41058. They're probably left over during tear-down and 4162 * switching away from an exiting process. Until the root cause is identified 4163 * and fixed, zap the cache when switching pmaps. This will result in a few 4164 * unnecessary cache flushes, but that's better than silently corrupting data. 4165 */ 4166 #if 0 4167 if (npm != pmap_kernel() && rpm && npm != rpm && 4168 rpm->pm_cstate.cs_cache) { 4169 rpm->pm_cstate.cs_cache = 0; 4170 #ifdef PMAP_CACHE_VIVT 4171 cpu_idcache_wbinv_all(); 4172 #endif 4173 } 4174 #else 4175 if (rpm) { 4176 rpm->pm_cstate.cs_cache = 0; 4177 if (npm == pmap_kernel()) 4178 pmap_recent_user = NULL; 4179 #ifdef PMAP_CACHE_VIVT 4180 cpu_idcache_wbinv_all(); 4181 #endif 4182 } 4183 #endif 4184 4185 /* No interrupts while we frob the TTB/DACR */ 4186 oldirqstate = disable_interrupts(IF32_bits); 4187 4188 /* 4189 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4190 * entry corresponding to 'vector_page' in the incoming L1 table 4191 * before switching to it otherwise subsequent interrupts/exceptions 4192 * (including domain faults!) will jump into hyperspace. 4193 */ 4194 if (npm->pm_pl1vec != NULL) { 4195 cpu_tlb_flushID_SE((u_int)vector_page); 4196 cpu_cpwait(); 4197 *npm->pm_pl1vec = npm->pm_l1vec; 4198 PTE_SYNC(npm->pm_pl1vec); 4199 } 4200 4201 cpu_domains(ndacr); 4202 4203 if (npm == pmap_kernel() || npm == rpm) { 4204 /* 4205 * Switching to a kernel thread, or back to the 4206 * same user vmspace as before... Simply update 4207 * the TTB (no TLB flush required) 4208 */ 4209 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4210 "r"(npm->pm_l1->l1_physaddr)); 4211 cpu_cpwait(); 4212 } else { 4213 /* 4214 * Otherwise, update TTB and flush TLB 4215 */ 4216 cpu_context_switch(npm->pm_l1->l1_physaddr); 4217 if (rpm != NULL) 4218 rpm->pm_cstate.cs_tlb = 0; 4219 } 4220 4221 restore_interrupts(oldirqstate); 4222 4223 block_userspace_access = 0; 4224 4225 all_done: 4226 /* 4227 * The new pmap is resident. Make sure it's marked 4228 * as resident in the cache/TLB. 4229 */ 4230 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4231 if (npm != pmap_kernel()) 4232 pmap_recent_user = npm; 4233 4234 /* The old pmap is not longer active */ 4235 if (opm != NULL) 4236 opm->pm_activated = false; 4237 4238 /* But the new one is */ 4239 npm->pm_activated = true; 4240 } 4241 4242 void 4243 pmap_deactivate(struct lwp *l) 4244 { 4245 4246 /* 4247 * If the process is exiting, make sure pmap_activate() does 4248 * a full MMU context-switch and cache flush, which we might 4249 * otherwise skip. See PR port-arm/38950. 4250 */ 4251 if (l->l_proc->p_sflag & PS_WEXIT) 4252 pmap_previous_active_lwp = NULL; 4253 4254 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4255 } 4256 4257 void 4258 pmap_update(pmap_t pm) 4259 { 4260 4261 if (pm->pm_remove_all) { 4262 /* 4263 * Finish up the pmap_remove_all() optimisation by flushing 4264 * the TLB. 4265 */ 4266 pmap_tlb_flushID(pm); 4267 pm->pm_remove_all = false; 4268 } 4269 4270 if (pmap_is_current(pm)) { 4271 /* 4272 * If we're dealing with a current userland pmap, move its L1 4273 * to the end of the LRU. 4274 */ 4275 if (pm != pmap_kernel()) 4276 pmap_use_l1(pm); 4277 4278 /* 4279 * We can assume we're done with frobbing the cache/tlb for 4280 * now. Make sure any future pmap ops don't skip cache/tlb 4281 * flushes. 4282 */ 4283 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4284 } 4285 4286 PMAPCOUNT(updates); 4287 4288 /* 4289 * make sure TLB/cache operations have completed. 4290 */ 4291 cpu_cpwait(); 4292 } 4293 4294 void 4295 pmap_remove_all(pmap_t pm) 4296 { 4297 4298 /* 4299 * The vmspace described by this pmap is about to be torn down. 4300 * Until pmap_update() is called, UVM will only make calls 4301 * to pmap_remove(). We can make life much simpler by flushing 4302 * the cache now, and deferring TLB invalidation to pmap_update(). 4303 */ 4304 #ifdef PMAP_CACHE_VIVT 4305 pmap_idcache_wbinv_all(pm); 4306 #endif 4307 pm->pm_remove_all = true; 4308 } 4309 4310 /* 4311 * Retire the given physical map from service. 4312 * Should only be called if the map contains no valid mappings. 4313 */ 4314 void 4315 pmap_destroy(pmap_t pm) 4316 { 4317 u_int count; 4318 4319 if (pm == NULL) 4320 return; 4321 4322 if (pm->pm_remove_all) { 4323 pmap_tlb_flushID(pm); 4324 pm->pm_remove_all = false; 4325 } 4326 4327 /* 4328 * Drop reference count 4329 */ 4330 mutex_enter(&pm->pm_lock); 4331 count = --pm->pm_obj.uo_refs; 4332 mutex_exit(&pm->pm_lock); 4333 if (count > 0) { 4334 if (pmap_is_current(pm)) { 4335 if (pm != pmap_kernel()) 4336 pmap_use_l1(pm); 4337 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4338 } 4339 return; 4340 } 4341 4342 /* 4343 * reference count is zero, free pmap resources and then free pmap. 4344 */ 4345 4346 if (vector_page < KERNEL_BASE) { 4347 KDASSERT(!pmap_is_current(pm)); 4348 4349 /* Remove the vector page mapping */ 4350 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4351 pmap_update(pm); 4352 } 4353 4354 LIST_REMOVE(pm, pm_list); 4355 4356 pmap_free_l1(pm); 4357 4358 if (pmap_recent_user == pm) 4359 pmap_recent_user = NULL; 4360 4361 UVM_OBJ_DESTROY(&pm->pm_obj); 4362 4363 /* return the pmap to the pool */ 4364 pool_cache_put(&pmap_cache, pm); 4365 } 4366 4367 4368 /* 4369 * void pmap_reference(pmap_t pm) 4370 * 4371 * Add a reference to the specified pmap. 4372 */ 4373 void 4374 pmap_reference(pmap_t pm) 4375 { 4376 4377 if (pm == NULL) 4378 return; 4379 4380 pmap_use_l1(pm); 4381 4382 mutex_enter(&pm->pm_lock); 4383 pm->pm_obj.uo_refs++; 4384 mutex_exit(&pm->pm_lock); 4385 } 4386 4387 #if ARM_MMU_V6 > 0 4388 4389 static struct evcnt pmap_prefer_nochange_ev = 4390 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4391 static struct evcnt pmap_prefer_change_ev = 4392 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4393 4394 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4395 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4396 4397 void 4398 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4399 { 4400 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4401 vaddr_t va = *vap; 4402 vaddr_t diff = (hint - va) & mask; 4403 if (diff == 0) { 4404 pmap_prefer_nochange_ev.ev_count++; 4405 } else { 4406 pmap_prefer_change_ev.ev_count++; 4407 if (__predict_false(td)) 4408 va -= mask + 1; 4409 *vap = va + diff; 4410 } 4411 } 4412 #endif /* ARM_MMU_V6 */ 4413 4414 /* 4415 * pmap_zero_page() 4416 * 4417 * Zero a given physical page by mapping it at a page hook point. 4418 * In doing the zero page op, the page we zero is mapped cachable, as with 4419 * StrongARM accesses to non-cached pages are non-burst making writing 4420 * _any_ bulk data very slow. 4421 */ 4422 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4423 void 4424 pmap_zero_page_generic(paddr_t phys) 4425 { 4426 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4427 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4428 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4429 #endif 4430 #ifdef PMAP_CACHE_VIPT 4431 /* Choose the last page color it had, if any */ 4432 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4433 #else 4434 const vsize_t va_offset = 0; 4435 #endif 4436 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4437 4438 #ifdef DEBUG 4439 if (!SLIST_EMPTY(&md->pvh_list)) 4440 panic("pmap_zero_page: page has mappings"); 4441 #endif 4442 4443 KDASSERT((phys & PGOFSET) == 0); 4444 4445 /* 4446 * Hook in the page, zero it, and purge the cache for that 4447 * zeroed page. Invalidate the TLB as needed. 4448 */ 4449 *ptep = L2_S_PROTO | phys | 4450 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4451 PTE_SYNC(ptep); 4452 cpu_tlb_flushD_SE(cdstp + va_offset); 4453 cpu_cpwait(); 4454 bzero_page(cdstp + va_offset); 4455 /* 4456 * Unmap the page. 4457 */ 4458 *ptep = 0; 4459 PTE_SYNC(ptep); 4460 cpu_tlb_flushD_SE(cdstp + va_offset); 4461 #ifdef PMAP_CACHE_VIVT 4462 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4463 #endif 4464 #ifdef PMAP_CACHE_VIPT 4465 /* 4466 * This page is now cache resident so it now has a page color. 4467 * Any contents have been obliterated so clear the EXEC flag. 4468 */ 4469 if (!pmap_is_page_colored_p(md)) { 4470 PMAPCOUNT(vac_color_new); 4471 md->pvh_attrs |= PVF_COLORED; 4472 } 4473 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4474 md->pvh_attrs &= ~PVF_EXEC; 4475 PMAPCOUNT(exec_discarded_zero); 4476 } 4477 md->pvh_attrs |= PVF_DIRTY; 4478 #endif 4479 } 4480 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4481 4482 #if ARM_MMU_XSCALE == 1 4483 void 4484 pmap_zero_page_xscale(paddr_t phys) 4485 { 4486 #ifdef DEBUG 4487 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4488 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4489 4490 if (!SLIST_EMPTY(&md->pvh_list)) 4491 panic("pmap_zero_page: page has mappings"); 4492 #endif 4493 4494 KDASSERT((phys & PGOFSET) == 0); 4495 4496 /* 4497 * Hook in the page, zero it, and purge the cache for that 4498 * zeroed page. Invalidate the TLB as needed. 4499 */ 4500 *cdst_pte = L2_S_PROTO | phys | 4501 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4502 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4503 PTE_SYNC(cdst_pte); 4504 cpu_tlb_flushD_SE(cdstp); 4505 cpu_cpwait(); 4506 bzero_page(cdstp); 4507 xscale_cache_clean_minidata(); 4508 } 4509 #endif /* ARM_MMU_XSCALE == 1 */ 4510 4511 /* pmap_pageidlezero() 4512 * 4513 * The same as above, except that we assume that the page is not 4514 * mapped. This means we never have to flush the cache first. Called 4515 * from the idle loop. 4516 */ 4517 bool 4518 pmap_pageidlezero(paddr_t phys) 4519 { 4520 unsigned int i; 4521 int *ptr; 4522 bool rv = true; 4523 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4524 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4525 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4526 #endif 4527 #ifdef PMAP_CACHE_VIPT 4528 /* Choose the last page color it had, if any */ 4529 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4530 #else 4531 const vsize_t va_offset = 0; 4532 #endif 4533 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4534 4535 4536 #ifdef DEBUG 4537 if (!SLIST_EMPTY(&md->pvh_list)) 4538 panic("pmap_pageidlezero: page has mappings"); 4539 #endif 4540 4541 KDASSERT((phys & PGOFSET) == 0); 4542 4543 /* 4544 * Hook in the page, zero it, and purge the cache for that 4545 * zeroed page. Invalidate the TLB as needed. 4546 */ 4547 *ptep = L2_S_PROTO | phys | 4548 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4549 PTE_SYNC(ptep); 4550 cpu_tlb_flushD_SE(cdstp + va_offset); 4551 cpu_cpwait(); 4552 4553 for (i = 0, ptr = (int *)(cdstp + va_offset); 4554 i < (PAGE_SIZE / sizeof(int)); i++) { 4555 if (sched_curcpu_runnable_p() != 0) { 4556 /* 4557 * A process has become ready. Abort now, 4558 * so we don't keep it waiting while we 4559 * do slow memory access to finish this 4560 * page. 4561 */ 4562 rv = false; 4563 break; 4564 } 4565 *ptr++ = 0; 4566 } 4567 4568 #ifdef PMAP_CACHE_VIVT 4569 if (rv) 4570 /* 4571 * if we aborted we'll rezero this page again later so don't 4572 * purge it unless we finished it 4573 */ 4574 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4575 #elif defined(PMAP_CACHE_VIPT) 4576 /* 4577 * This page is now cache resident so it now has a page color. 4578 * Any contents have been obliterated so clear the EXEC flag. 4579 */ 4580 if (!pmap_is_page_colored_p(md)) { 4581 PMAPCOUNT(vac_color_new); 4582 md->pvh_attrs |= PVF_COLORED; 4583 } 4584 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4585 md->pvh_attrs &= ~PVF_EXEC; 4586 PMAPCOUNT(exec_discarded_zero); 4587 } 4588 #endif 4589 /* 4590 * Unmap the page. 4591 */ 4592 *ptep = 0; 4593 PTE_SYNC(ptep); 4594 cpu_tlb_flushD_SE(cdstp + va_offset); 4595 4596 return (rv); 4597 } 4598 4599 /* 4600 * pmap_copy_page() 4601 * 4602 * Copy one physical page into another, by mapping the pages into 4603 * hook points. The same comment regarding cachability as in 4604 * pmap_zero_page also applies here. 4605 */ 4606 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 4607 void 4608 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4609 { 4610 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4611 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4612 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4613 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4614 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4615 #endif 4616 #ifdef PMAP_CACHE_VIPT 4617 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4618 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4619 #else 4620 const vsize_t src_va_offset = 0; 4621 const vsize_t dst_va_offset = 0; 4622 #endif 4623 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4624 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4625 4626 #ifdef DEBUG 4627 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4628 panic("pmap_copy_page: dst page has mappings"); 4629 #endif 4630 4631 #ifdef PMAP_CACHE_VIPT 4632 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4633 #endif 4634 KDASSERT((src & PGOFSET) == 0); 4635 KDASSERT((dst & PGOFSET) == 0); 4636 4637 /* 4638 * Clean the source page. Hold the source page's lock for 4639 * the duration of the copy so that no other mappings can 4640 * be created while we have a potentially aliased mapping. 4641 */ 4642 simple_lock(&src_md->pvh_slock); 4643 #ifdef PMAP_CACHE_VIVT 4644 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4645 #endif 4646 4647 /* 4648 * Map the pages into the page hook points, copy them, and purge 4649 * the cache for the appropriate page. Invalidate the TLB 4650 * as required. 4651 */ 4652 *src_ptep = L2_S_PROTO 4653 | src 4654 #ifdef PMAP_CACHE_VIPT 4655 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4656 #endif 4657 #ifdef PMAP_CACHE_VIVT 4658 | pte_l2_s_cache_mode 4659 #endif 4660 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4661 *dst_ptep = L2_S_PROTO | dst | 4662 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4663 PTE_SYNC(src_ptep); 4664 PTE_SYNC(dst_ptep); 4665 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4666 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4667 cpu_cpwait(); 4668 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4669 #ifdef PMAP_CACHE_VIVT 4670 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4671 #endif 4672 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4673 #ifdef PMAP_CACHE_VIVT 4674 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4675 #endif 4676 /* 4677 * Unmap the pages. 4678 */ 4679 *src_ptep = 0; 4680 *dst_ptep = 0; 4681 PTE_SYNC(src_ptep); 4682 PTE_SYNC(dst_ptep); 4683 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4684 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4685 #ifdef PMAP_CACHE_VIPT 4686 /* 4687 * Now that the destination page is in the cache, mark it as colored. 4688 * If this was an exec page, discard it. 4689 */ 4690 if (!pmap_is_page_colored_p(dst_md)) { 4691 PMAPCOUNT(vac_color_new); 4692 dst_md->pvh_attrs |= PVF_COLORED; 4693 } 4694 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4695 dst_md->pvh_attrs &= ~PVF_EXEC; 4696 PMAPCOUNT(exec_discarded_copy); 4697 } 4698 dst_md->pvh_attrs |= PVF_DIRTY; 4699 #endif 4700 } 4701 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4702 4703 #if ARM_MMU_XSCALE == 1 4704 void 4705 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4706 { 4707 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4708 #ifdef DEBUG 4709 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4710 4711 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4712 panic("pmap_copy_page: dst page has mappings"); 4713 #endif 4714 4715 KDASSERT((src & PGOFSET) == 0); 4716 KDASSERT((dst & PGOFSET) == 0); 4717 4718 /* 4719 * Clean the source page. Hold the source page's lock for 4720 * the duration of the copy so that no other mappings can 4721 * be created while we have a potentially aliased mapping. 4722 */ 4723 simple_lock(&src_md->pvh_slock); 4724 #ifdef PMAP_CACHE_VIVT 4725 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4726 #endif 4727 4728 /* 4729 * Map the pages into the page hook points, copy them, and purge 4730 * the cache for the appropriate page. Invalidate the TLB 4731 * as required. 4732 */ 4733 *csrc_pte = L2_S_PROTO | src | 4734 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4735 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4736 PTE_SYNC(csrc_pte); 4737 *cdst_pte = L2_S_PROTO | dst | 4738 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4739 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4740 PTE_SYNC(cdst_pte); 4741 cpu_tlb_flushD_SE(csrcp); 4742 cpu_tlb_flushD_SE(cdstp); 4743 cpu_cpwait(); 4744 bcopy_page(csrcp, cdstp); 4745 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4746 xscale_cache_clean_minidata(); 4747 } 4748 #endif /* ARM_MMU_XSCALE == 1 */ 4749 4750 /* 4751 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4752 * 4753 * Return the start and end addresses of the kernel's virtual space. 4754 * These values are setup in pmap_bootstrap and are updated as pages 4755 * are allocated. 4756 */ 4757 void 4758 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4759 { 4760 *start = virtual_avail; 4761 *end = virtual_end; 4762 } 4763 4764 /* 4765 * Helper function for pmap_grow_l2_bucket() 4766 */ 4767 static inline int 4768 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4769 { 4770 struct l2_bucket *l2b; 4771 pt_entry_t *ptep; 4772 paddr_t pa; 4773 4774 if (uvm.page_init_done == false) { 4775 #ifdef PMAP_STEAL_MEMORY 4776 pv_addr_t pv; 4777 pmap_boot_pagealloc(PAGE_SIZE, 4778 #ifdef PMAP_CACHE_VIPT 4779 arm_cache_prefer_mask, 4780 va & arm_cache_prefer_mask, 4781 #else 4782 0, 0, 4783 #endif 4784 &pv); 4785 pa = pv.pv_pa; 4786 #else 4787 if (uvm_page_physget(&pa) == false) 4788 return (1); 4789 #endif /* PMAP_STEAL_MEMORY */ 4790 } else { 4791 struct vm_page *pg; 4792 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4793 if (pg == NULL) 4794 return (1); 4795 pa = VM_PAGE_TO_PHYS(pg); 4796 #ifdef PMAP_CACHE_VIPT 4797 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4798 /* 4799 * This new page must not have any mappings. Enter it via 4800 * pmap_kenter_pa and let that routine do the hard work. 4801 */ 4802 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4803 pmap_kenter_pa(va, pa, 4804 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); 4805 #endif 4806 } 4807 4808 if (pap) 4809 *pap = pa; 4810 4811 PMAPCOUNT(pt_mappings); 4812 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4813 KDASSERT(l2b != NULL); 4814 4815 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4816 *ptep = L2_S_PROTO | pa | cache_mode | 4817 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4818 PTE_SYNC(ptep); 4819 memset((void *)va, 0, PAGE_SIZE); 4820 return (0); 4821 } 4822 4823 /* 4824 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4825 * used by pmap_growkernel(). 4826 */ 4827 static inline struct l2_bucket * 4828 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4829 { 4830 struct l2_dtable *l2; 4831 struct l2_bucket *l2b; 4832 u_short l1idx; 4833 vaddr_t nva; 4834 4835 l1idx = L1_IDX(va); 4836 4837 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4838 /* 4839 * No mapping at this address, as there is 4840 * no entry in the L1 table. 4841 * Need to allocate a new l2_dtable. 4842 */ 4843 nva = pmap_kernel_l2dtable_kva; 4844 if ((nva & PGOFSET) == 0) { 4845 /* 4846 * Need to allocate a backing page 4847 */ 4848 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4849 return (NULL); 4850 } 4851 4852 l2 = (struct l2_dtable *)nva; 4853 nva += sizeof(struct l2_dtable); 4854 4855 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4856 /* 4857 * The new l2_dtable straddles a page boundary. 4858 * Map in another page to cover it. 4859 */ 4860 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4861 return (NULL); 4862 } 4863 4864 pmap_kernel_l2dtable_kva = nva; 4865 4866 /* 4867 * Link it into the parent pmap 4868 */ 4869 pm->pm_l2[L2_IDX(l1idx)] = l2; 4870 } 4871 4872 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4873 4874 /* 4875 * Fetch pointer to the L2 page table associated with the address. 4876 */ 4877 if (l2b->l2b_kva == NULL) { 4878 pt_entry_t *ptep; 4879 4880 /* 4881 * No L2 page table has been allocated. Chances are, this 4882 * is because we just allocated the l2_dtable, above. 4883 */ 4884 nva = pmap_kernel_l2ptp_kva; 4885 ptep = (pt_entry_t *)nva; 4886 if ((nva & PGOFSET) == 0) { 4887 /* 4888 * Need to allocate a backing page 4889 */ 4890 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4891 &pmap_kernel_l2ptp_phys)) 4892 return (NULL); 4893 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4894 } 4895 4896 l2->l2_occupancy++; 4897 l2b->l2b_kva = ptep; 4898 l2b->l2b_l1idx = l1idx; 4899 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4900 4901 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4902 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4903 } 4904 4905 return (l2b); 4906 } 4907 4908 vaddr_t 4909 pmap_growkernel(vaddr_t maxkvaddr) 4910 { 4911 pmap_t kpm = pmap_kernel(); 4912 struct l1_ttable *l1; 4913 struct l2_bucket *l2b; 4914 pd_entry_t *pl1pd; 4915 int s; 4916 4917 if (maxkvaddr <= pmap_curmaxkvaddr) 4918 goto out; /* we are OK */ 4919 4920 NPDEBUG(PDB_GROWKERN, 4921 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4922 pmap_curmaxkvaddr, maxkvaddr)); 4923 4924 KDASSERT(maxkvaddr <= virtual_end); 4925 4926 /* 4927 * whoops! we need to add kernel PTPs 4928 */ 4929 4930 s = splhigh(); /* to be safe */ 4931 mutex_enter(&kpm->pm_lock); 4932 4933 /* Map 1MB at a time */ 4934 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4935 4936 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4937 KDASSERT(l2b != NULL); 4938 4939 /* Distribute new L1 entry to all other L1s */ 4940 SLIST_FOREACH(l1, &l1_list, l1_link) { 4941 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4942 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4943 L1_C_PROTO; 4944 PTE_SYNC(pl1pd); 4945 } 4946 } 4947 4948 /* 4949 * flush out the cache, expensive but growkernel will happen so 4950 * rarely 4951 */ 4952 cpu_dcache_wbinv_all(); 4953 cpu_tlb_flushD(); 4954 cpu_cpwait(); 4955 4956 mutex_exit(&kpm->pm_lock); 4957 splx(s); 4958 4959 out: 4960 return (pmap_curmaxkvaddr); 4961 } 4962 4963 /************************ Utility routines ****************************/ 4964 4965 /* 4966 * vector_page_setprot: 4967 * 4968 * Manipulate the protection of the vector page. 4969 */ 4970 void 4971 vector_page_setprot(int prot) 4972 { 4973 struct l2_bucket *l2b; 4974 pt_entry_t *ptep; 4975 4976 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4977 KDASSERT(l2b != NULL); 4978 4979 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4980 4981 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4982 PTE_SYNC(ptep); 4983 cpu_tlb_flushD_SE(vector_page); 4984 cpu_cpwait(); 4985 } 4986 4987 /* 4988 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4989 * Returns true if the mapping exists, else false. 4990 * 4991 * NOTE: This function is only used by a couple of arm-specific modules. 4992 * It is not safe to take any pmap locks here, since we could be right 4993 * in the middle of debugging the pmap anyway... 4994 * 4995 * It is possible for this routine to return false even though a valid 4996 * mapping does exist. This is because we don't lock, so the metadata 4997 * state may be inconsistent. 4998 * 4999 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5000 * a "section" mapping. 5001 */ 5002 bool 5003 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5004 { 5005 struct l2_dtable *l2; 5006 pd_entry_t *pl1pd, l1pd; 5007 pt_entry_t *ptep; 5008 u_short l1idx; 5009 5010 if (pm->pm_l1 == NULL) 5011 return false; 5012 5013 l1idx = L1_IDX(va); 5014 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5015 l1pd = *pl1pd; 5016 5017 if (l1pte_section_p(l1pd)) { 5018 *ptp = NULL; 5019 return true; 5020 } 5021 5022 if (pm->pm_l2 == NULL) 5023 return false; 5024 5025 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5026 5027 if (l2 == NULL || 5028 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5029 return false; 5030 } 5031 5032 *ptp = &ptep[l2pte_index(va)]; 5033 return true; 5034 } 5035 5036 bool 5037 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5038 { 5039 u_short l1idx; 5040 5041 if (pm->pm_l1 == NULL) 5042 return false; 5043 5044 l1idx = L1_IDX(va); 5045 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5046 5047 return true; 5048 } 5049 5050 /************************ Bootstrapping routines ****************************/ 5051 5052 static void 5053 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5054 { 5055 int i; 5056 5057 l1->l1_kva = l1pt; 5058 l1->l1_domain_use_count = 0; 5059 l1->l1_domain_first = 0; 5060 5061 for (i = 0; i < PMAP_DOMAINS; i++) 5062 l1->l1_domain_free[i] = i + 1; 5063 5064 /* 5065 * Copy the kernel's L1 entries to each new L1. 5066 */ 5067 if (pmap_initialized) 5068 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5069 5070 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5071 &l1->l1_physaddr) == false) 5072 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5073 5074 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5075 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5076 } 5077 5078 /* 5079 * pmap_bootstrap() is called from the board-specific initarm() routine 5080 * once the kernel L1/L2 descriptors tables have been set up. 5081 * 5082 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5083 * spread over a number of disparate files/functions. 5084 * 5085 * We are passed the following parameters 5086 * - kernel_l1pt 5087 * This is a pointer to the base of the kernel's L1 translation table. 5088 * - vstart 5089 * 1MB-aligned start of managed kernel virtual memory. 5090 * - vend 5091 * 1MB-aligned end of managed kernel virtual memory. 5092 * 5093 * We use the first parameter to build the metadata (struct l1_ttable and 5094 * struct l2_dtable) necessary to track kernel mappings. 5095 */ 5096 #define PMAP_STATIC_L2_SIZE 16 5097 void 5098 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5099 { 5100 static struct l1_ttable static_l1; 5101 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5102 struct l1_ttable *l1 = &static_l1; 5103 struct l2_dtable *l2; 5104 struct l2_bucket *l2b; 5105 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5106 pmap_t pm = pmap_kernel(); 5107 pd_entry_t pde; 5108 pt_entry_t *ptep; 5109 paddr_t pa; 5110 vaddr_t va; 5111 vsize_t size; 5112 int nptes, l1idx, l2idx, l2next = 0; 5113 5114 /* 5115 * Initialise the kernel pmap object 5116 */ 5117 pm->pm_l1 = l1; 5118 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5119 pm->pm_activated = true; 5120 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5121 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5122 5123 /* 5124 * Scan the L1 translation table created by initarm() and create 5125 * the required metadata for all valid mappings found in it. 5126 */ 5127 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5128 pde = l1pt[l1idx]; 5129 5130 /* 5131 * We're only interested in Coarse mappings. 5132 * pmap_extract() can deal with section mappings without 5133 * recourse to checking L2 metadata. 5134 */ 5135 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5136 continue; 5137 5138 /* 5139 * Lookup the KVA of this L2 descriptor table 5140 */ 5141 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5142 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5143 if (ptep == NULL) { 5144 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5145 (u_int)l1idx << L1_S_SHIFT, pa); 5146 } 5147 5148 /* 5149 * Fetch the associated L2 metadata structure. 5150 * Allocate a new one if necessary. 5151 */ 5152 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5153 if (l2next == PMAP_STATIC_L2_SIZE) 5154 panic("pmap_bootstrap: out of static L2s"); 5155 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5156 } 5157 5158 /* 5159 * One more L1 slot tracked... 5160 */ 5161 l2->l2_occupancy++; 5162 5163 /* 5164 * Fill in the details of the L2 descriptor in the 5165 * appropriate bucket. 5166 */ 5167 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5168 l2b->l2b_kva = ptep; 5169 l2b->l2b_phys = pa; 5170 l2b->l2b_l1idx = l1idx; 5171 5172 /* 5173 * Establish an initial occupancy count for this descriptor 5174 */ 5175 for (l2idx = 0; 5176 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5177 l2idx++) { 5178 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5179 l2b->l2b_occupancy++; 5180 } 5181 } 5182 5183 /* 5184 * Make sure the descriptor itself has the correct cache mode. 5185 * If not, fix it, but whine about the problem. Port-meisters 5186 * should consider this a clue to fix up their initarm() 5187 * function. :) 5188 */ 5189 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5190 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5191 "L2 pte @ %p\n", ptep); 5192 } 5193 } 5194 5195 /* 5196 * Ensure the primary (kernel) L1 has the correct cache mode for 5197 * a page table. Bitch if it is not correctly set. 5198 */ 5199 for (va = (vaddr_t)l1pt; 5200 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5201 if (pmap_set_pt_cache_mode(l1pt, va)) 5202 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5203 "primary L1 @ 0x%lx\n", va); 5204 } 5205 5206 cpu_dcache_wbinv_all(); 5207 cpu_tlb_flushID(); 5208 cpu_cpwait(); 5209 5210 /* 5211 * now we allocate the "special" VAs which are used for tmp mappings 5212 * by the pmap (and other modules). we allocate the VAs by advancing 5213 * virtual_avail (note that there are no pages mapped at these VAs). 5214 * 5215 * Managed KVM space start from wherever initarm() tells us. 5216 */ 5217 virtual_avail = vstart; 5218 virtual_end = vend; 5219 5220 #ifdef PMAP_CACHE_VIPT 5221 /* 5222 * If we have a VIPT cache, we need one page/pte per possible alias 5223 * page so we won't violate cache aliasing rules. 5224 */ 5225 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5226 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5227 #else 5228 nptes = 1; 5229 #endif 5230 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5231 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5232 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5233 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5234 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5235 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5236 (void *)&msgbufaddr, NULL); 5237 5238 /* 5239 * Allocate a range of kernel virtual address space to be used 5240 * for L2 descriptor tables and metadata allocation in 5241 * pmap_growkernel(). 5242 */ 5243 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5244 pmap_alloc_specials(&virtual_avail, 5245 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5246 &pmap_kernel_l2ptp_kva, NULL); 5247 5248 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5249 pmap_alloc_specials(&virtual_avail, 5250 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5251 &pmap_kernel_l2dtable_kva, NULL); 5252 5253 /* 5254 * init the static-global locks and global pmap list. 5255 */ 5256 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5257 5258 /* 5259 * We can now initialise the first L1's metadata. 5260 */ 5261 SLIST_INIT(&l1_list); 5262 TAILQ_INIT(&l1_lru_list); 5263 simple_lock_init(&l1_lru_lock); 5264 pmap_init_l1(l1, l1pt); 5265 5266 /* Set up vector page L1 details, if necessary */ 5267 if (vector_page < KERNEL_BASE) { 5268 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5269 l2b = pmap_get_l2_bucket(pm, vector_page); 5270 KDASSERT(l2b != NULL); 5271 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5272 L1_C_DOM(pm->pm_domain); 5273 } else 5274 pm->pm_pl1vec = NULL; 5275 5276 /* 5277 * Initialize the pmap cache 5278 */ 5279 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5280 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5281 LIST_INIT(&pmap_pmaps); 5282 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5283 5284 /* 5285 * Initialize the pv pool. 5286 */ 5287 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5288 &pmap_bootstrap_pv_allocator, IPL_NONE); 5289 5290 /* 5291 * Initialize the L2 dtable pool and cache. 5292 */ 5293 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5294 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5295 5296 /* 5297 * Initialise the L2 descriptor table pool and cache 5298 */ 5299 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5300 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5301 pmap_l2ptp_ctor, NULL, NULL); 5302 5303 cpu_dcache_wbinv_all(); 5304 } 5305 5306 static int 5307 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5308 { 5309 pd_entry_t *pdep, pde; 5310 pt_entry_t *ptep, pte; 5311 vaddr_t pa; 5312 int rv = 0; 5313 5314 /* 5315 * Make sure the descriptor itself has the correct cache mode 5316 */ 5317 pdep = &kl1[L1_IDX(va)]; 5318 pde = *pdep; 5319 5320 if (l1pte_section_p(pde)) { 5321 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5322 *pdep = (pde & ~L1_S_CACHE_MASK) | 5323 pte_l1_s_cache_mode_pt; 5324 PTE_SYNC(pdep); 5325 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5326 rv = 1; 5327 } 5328 } else { 5329 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5330 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5331 if (ptep == NULL) 5332 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5333 5334 ptep = &ptep[l2pte_index(va)]; 5335 pte = *ptep; 5336 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5337 *ptep = (pte & ~L2_S_CACHE_MASK) | 5338 pte_l2_s_cache_mode_pt; 5339 PTE_SYNC(ptep); 5340 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5341 rv = 1; 5342 } 5343 } 5344 5345 return (rv); 5346 } 5347 5348 static void 5349 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5350 { 5351 vaddr_t va = *availp; 5352 struct l2_bucket *l2b; 5353 5354 if (ptep) { 5355 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5356 if (l2b == NULL) 5357 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5358 5359 if (ptep) 5360 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5361 } 5362 5363 *vap = va; 5364 *availp = va + (PAGE_SIZE * pages); 5365 } 5366 5367 void 5368 pmap_init(void) 5369 { 5370 5371 /* 5372 * Set the available memory vars - These do not map to real memory 5373 * addresses and cannot as the physical memory is fragmented. 5374 * They are used by ps for %mem calculations. 5375 * One could argue whether this should be the entire memory or just 5376 * the memory that is useable in a user process. 5377 */ 5378 avail_start = ptoa(vm_physmem[0].start); 5379 avail_end = ptoa(vm_physmem[vm_nphysseg - 1].end); 5380 5381 /* 5382 * Now we need to free enough pv_entry structures to allow us to get 5383 * the kmem_map/kmem_object allocated and inited (done after this 5384 * function is finished). to do this we allocate one bootstrap page out 5385 * of kernel_map and use it to provide an initial pool of pv_entry 5386 * structures. we never free this page. 5387 */ 5388 pool_setlowat(&pmap_pv_pool, 5389 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5390 5391 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5392 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5393 UVM_KMF_WIRED|UVM_KMF_ZERO); 5394 5395 pmap_initialized = true; 5396 } 5397 5398 static vaddr_t last_bootstrap_page = 0; 5399 static void *free_bootstrap_pages = NULL; 5400 5401 static void * 5402 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5403 { 5404 extern void *pool_page_alloc(struct pool *, int); 5405 vaddr_t new_page; 5406 void *rv; 5407 5408 if (pmap_initialized) 5409 return (pool_page_alloc(pp, flags)); 5410 5411 if (free_bootstrap_pages) { 5412 rv = free_bootstrap_pages; 5413 free_bootstrap_pages = *((void **)rv); 5414 return (rv); 5415 } 5416 5417 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5418 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5419 5420 KASSERT(new_page > last_bootstrap_page); 5421 last_bootstrap_page = new_page; 5422 return ((void *)new_page); 5423 } 5424 5425 static void 5426 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5427 { 5428 extern void pool_page_free(struct pool *, void *); 5429 5430 if ((vaddr_t)v <= last_bootstrap_page) { 5431 *((void **)v) = free_bootstrap_pages; 5432 free_bootstrap_pages = v; 5433 return; 5434 } 5435 5436 if (pmap_initialized) { 5437 pool_page_free(pp, v); 5438 return; 5439 } 5440 } 5441 5442 /* 5443 * pmap_postinit() 5444 * 5445 * This routine is called after the vm and kmem subsystems have been 5446 * initialised. This allows the pmap code to perform any initialisation 5447 * that can only be done one the memory allocation is in place. 5448 */ 5449 void 5450 pmap_postinit(void) 5451 { 5452 extern paddr_t physical_start, physical_end; 5453 struct l2_bucket *l2b; 5454 struct l1_ttable *l1; 5455 struct pglist plist; 5456 struct vm_page *m; 5457 pd_entry_t *pl1pt; 5458 pt_entry_t *ptep, pte; 5459 vaddr_t va, eva; 5460 u_int loop, needed; 5461 int error; 5462 5463 pool_cache_setlowat(&pmap_l2ptp_cache, 5464 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5465 pool_cache_setlowat(&pmap_l2dtable_cache, 5466 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5467 5468 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5469 needed -= 1; 5470 5471 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5472 5473 for (loop = 0; loop < needed; loop++, l1++) { 5474 /* Allocate a L1 page table */ 5475 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5476 if (va == 0) 5477 panic("Cannot allocate L1 KVM"); 5478 5479 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5480 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5481 if (error) 5482 panic("Cannot allocate L1 physical pages"); 5483 5484 m = TAILQ_FIRST(&plist); 5485 eva = va + L1_TABLE_SIZE; 5486 pl1pt = (pd_entry_t *)va; 5487 5488 while (m && va < eva) { 5489 paddr_t pa = VM_PAGE_TO_PHYS(m); 5490 5491 pmap_kenter_pa(va, pa, 5492 VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); 5493 5494 /* 5495 * Make sure the L1 descriptor table is mapped 5496 * with the cache-mode set to write-through. 5497 */ 5498 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5499 KDASSERT(l2b != NULL); 5500 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5501 pte = *ptep; 5502 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5503 *ptep = pte; 5504 PTE_SYNC(ptep); 5505 cpu_tlb_flushD_SE(va); 5506 5507 va += PAGE_SIZE; 5508 m = TAILQ_NEXT(m, pageq.queue); 5509 } 5510 5511 #ifdef DIAGNOSTIC 5512 if (m) 5513 panic("pmap_alloc_l1pt: pglist not empty"); 5514 #endif /* DIAGNOSTIC */ 5515 5516 pmap_init_l1(l1, pl1pt); 5517 } 5518 5519 #ifdef DEBUG 5520 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5521 needed); 5522 #endif 5523 } 5524 5525 /* 5526 * Note that the following routines are used by board-specific initialisation 5527 * code to configure the initial kernel page tables. 5528 * 5529 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5530 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5531 * behaviour of the old pmap, and provides an easy migration path for 5532 * initial bring-up of the new pmap on existing ports. Fortunately, 5533 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5534 * will be deprecated. 5535 * 5536 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5537 * tables. 5538 */ 5539 5540 /* 5541 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5542 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5543 * find them as necessary. 5544 * 5545 * Note that the data on this list MUST remain valid after initarm() returns, 5546 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5547 */ 5548 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5549 5550 static vaddr_t 5551 kernel_pt_lookup(paddr_t pa) 5552 { 5553 pv_addr_t *pv; 5554 5555 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5556 #ifndef ARM32_NEW_VM_LAYOUT 5557 if (pv->pv_pa == (pa & ~PGOFSET)) 5558 return (pv->pv_va | (pa & PGOFSET)); 5559 #else 5560 if (pv->pv_pa == pa) 5561 return (pv->pv_va); 5562 #endif 5563 } 5564 return (0); 5565 } 5566 5567 /* 5568 * pmap_map_section: 5569 * 5570 * Create a single section mapping. 5571 */ 5572 void 5573 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5574 { 5575 pd_entry_t *pde = (pd_entry_t *) l1pt; 5576 pd_entry_t fl; 5577 5578 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5579 5580 switch (cache) { 5581 case PTE_NOCACHE: 5582 default: 5583 fl = 0; 5584 break; 5585 5586 case PTE_CACHE: 5587 fl = pte_l1_s_cache_mode; 5588 break; 5589 5590 case PTE_PAGETABLE: 5591 fl = pte_l1_s_cache_mode_pt; 5592 break; 5593 } 5594 5595 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5596 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5597 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5598 } 5599 5600 /* 5601 * pmap_map_entry: 5602 * 5603 * Create a single page mapping. 5604 */ 5605 void 5606 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5607 { 5608 pd_entry_t *pde = (pd_entry_t *) l1pt; 5609 pt_entry_t fl; 5610 pt_entry_t *pte; 5611 5612 KASSERT(((va | pa) & PGOFSET) == 0); 5613 5614 switch (cache) { 5615 case PTE_NOCACHE: 5616 default: 5617 fl = 0; 5618 break; 5619 5620 case PTE_CACHE: 5621 fl = pte_l2_s_cache_mode; 5622 break; 5623 5624 case PTE_PAGETABLE: 5625 fl = pte_l2_s_cache_mode_pt; 5626 break; 5627 } 5628 5629 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5630 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5631 5632 #ifndef ARM32_NEW_VM_LAYOUT 5633 pte = (pt_entry_t *) 5634 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5635 #else 5636 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5637 #endif 5638 if (pte == NULL) 5639 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5640 5641 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5642 #ifndef ARM32_NEW_VM_LAYOUT 5643 pte += (va >> PGSHIFT) & 0x3ff; 5644 #else 5645 pte += l2pte_index(va); 5646 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5647 #endif 5648 *pte = fl; 5649 PTE_SYNC(pte); 5650 } 5651 5652 /* 5653 * pmap_link_l2pt: 5654 * 5655 * Link the L2 page table specified by "l2pv" into the L1 5656 * page table at the slot for "va". 5657 */ 5658 void 5659 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5660 { 5661 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5662 u_int slot = va >> L1_S_SHIFT; 5663 5664 #ifndef ARM32_NEW_VM_LAYOUT 5665 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5666 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5667 #endif 5668 5669 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5670 5671 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5672 #ifdef ARM32_NEW_VM_LAYOUT 5673 PTE_SYNC(&pde[slot]); 5674 #else 5675 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5676 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5677 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5678 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5679 #endif 5680 5681 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5682 } 5683 5684 /* 5685 * pmap_map_chunk: 5686 * 5687 * Map a chunk of memory using the most efficient mappings 5688 * possible (section, large page, small page) into the 5689 * provided L1 and L2 tables at the specified virtual address. 5690 */ 5691 vsize_t 5692 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5693 int prot, int cache) 5694 { 5695 pd_entry_t *pde = (pd_entry_t *) l1pt; 5696 pt_entry_t *pte, f1, f2s, f2l; 5697 vsize_t resid; 5698 int i; 5699 5700 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5701 5702 if (l1pt == 0) 5703 panic("pmap_map_chunk: no L1 table provided"); 5704 5705 #ifdef VERBOSE_INIT_ARM 5706 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5707 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5708 #endif 5709 5710 switch (cache) { 5711 case PTE_NOCACHE: 5712 default: 5713 f1 = 0; 5714 f2l = 0; 5715 f2s = 0; 5716 break; 5717 5718 case PTE_CACHE: 5719 f1 = pte_l1_s_cache_mode; 5720 f2l = pte_l2_l_cache_mode; 5721 f2s = pte_l2_s_cache_mode; 5722 break; 5723 5724 case PTE_PAGETABLE: 5725 f1 = pte_l1_s_cache_mode_pt; 5726 f2l = pte_l2_l_cache_mode_pt; 5727 f2s = pte_l2_s_cache_mode_pt; 5728 break; 5729 } 5730 5731 size = resid; 5732 5733 while (resid > 0) { 5734 /* See if we can use a section mapping. */ 5735 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5736 #ifdef VERBOSE_INIT_ARM 5737 printf("S"); 5738 #endif 5739 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5740 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5741 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5742 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5743 va += L1_S_SIZE; 5744 pa += L1_S_SIZE; 5745 resid -= L1_S_SIZE; 5746 continue; 5747 } 5748 5749 /* 5750 * Ok, we're going to use an L2 table. Make sure 5751 * one is actually in the corresponding L1 slot 5752 * for the current VA. 5753 */ 5754 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5755 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5756 5757 #ifndef ARM32_NEW_VM_LAYOUT 5758 pte = (pt_entry_t *) 5759 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5760 #else 5761 pte = (pt_entry_t *) kernel_pt_lookup( 5762 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5763 #endif 5764 if (pte == NULL) 5765 panic("pmap_map_chunk: can't find L2 table for VA" 5766 "0x%08lx", va); 5767 5768 /* See if we can use a L2 large page mapping. */ 5769 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5770 #ifdef VERBOSE_INIT_ARM 5771 printf("L"); 5772 #endif 5773 for (i = 0; i < 16; i++) { 5774 #ifndef ARM32_NEW_VM_LAYOUT 5775 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5776 L2_L_PROTO | pa | 5777 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5778 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5779 #else 5780 pte[l2pte_index(va) + i] = 5781 L2_L_PROTO | pa | 5782 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5783 PTE_SYNC(&pte[l2pte_index(va) + i]); 5784 #endif 5785 } 5786 va += L2_L_SIZE; 5787 pa += L2_L_SIZE; 5788 resid -= L2_L_SIZE; 5789 continue; 5790 } 5791 5792 /* Use a small page mapping. */ 5793 #ifdef VERBOSE_INIT_ARM 5794 printf("P"); 5795 #endif 5796 #ifndef ARM32_NEW_VM_LAYOUT 5797 pte[(va >> PGSHIFT) & 0x3ff] = 5798 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5799 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5800 #else 5801 pte[l2pte_index(va)] = 5802 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5803 PTE_SYNC(&pte[l2pte_index(va)]); 5804 #endif 5805 va += PAGE_SIZE; 5806 pa += PAGE_SIZE; 5807 resid -= PAGE_SIZE; 5808 } 5809 #ifdef VERBOSE_INIT_ARM 5810 printf("\n"); 5811 #endif 5812 return (size); 5813 } 5814 5815 /********************** Static device map routines ***************************/ 5816 5817 static const struct pmap_devmap *pmap_devmap_table; 5818 5819 /* 5820 * Register the devmap table. This is provided in case early console 5821 * initialization needs to register mappings created by bootstrap code 5822 * before pmap_devmap_bootstrap() is called. 5823 */ 5824 void 5825 pmap_devmap_register(const struct pmap_devmap *table) 5826 { 5827 5828 pmap_devmap_table = table; 5829 } 5830 5831 /* 5832 * Map all of the static regions in the devmap table, and remember 5833 * the devmap table so other parts of the kernel can look up entries 5834 * later. 5835 */ 5836 void 5837 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5838 { 5839 int i; 5840 5841 pmap_devmap_table = table; 5842 5843 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5844 #ifdef VERBOSE_INIT_ARM 5845 printf("devmap: %08lx -> %08lx @ %08lx\n", 5846 pmap_devmap_table[i].pd_pa, 5847 pmap_devmap_table[i].pd_pa + 5848 pmap_devmap_table[i].pd_size - 1, 5849 pmap_devmap_table[i].pd_va); 5850 #endif 5851 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5852 pmap_devmap_table[i].pd_pa, 5853 pmap_devmap_table[i].pd_size, 5854 pmap_devmap_table[i].pd_prot, 5855 pmap_devmap_table[i].pd_cache); 5856 } 5857 } 5858 5859 const struct pmap_devmap * 5860 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5861 { 5862 uint64_t endpa; 5863 int i; 5864 5865 if (pmap_devmap_table == NULL) 5866 return (NULL); 5867 5868 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5869 5870 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5871 if (pa >= pmap_devmap_table[i].pd_pa && 5872 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5873 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5874 return (&pmap_devmap_table[i]); 5875 } 5876 5877 return (NULL); 5878 } 5879 5880 const struct pmap_devmap * 5881 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5882 { 5883 int i; 5884 5885 if (pmap_devmap_table == NULL) 5886 return (NULL); 5887 5888 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5889 if (va >= pmap_devmap_table[i].pd_va && 5890 va + size - 1 <= pmap_devmap_table[i].pd_va + 5891 pmap_devmap_table[i].pd_size - 1) 5892 return (&pmap_devmap_table[i]); 5893 } 5894 5895 return (NULL); 5896 } 5897 5898 /********************** PTE initialization routines **************************/ 5899 5900 /* 5901 * These routines are called when the CPU type is identified to set up 5902 * the PTE prototypes, cache modes, etc. 5903 * 5904 * The variables are always here, just in case modules need to reference 5905 * them (though, they shouldn't). 5906 */ 5907 5908 pt_entry_t pte_l1_s_cache_mode; 5909 pt_entry_t pte_l1_s_cache_mode_pt; 5910 pt_entry_t pte_l1_s_cache_mask; 5911 5912 pt_entry_t pte_l2_l_cache_mode; 5913 pt_entry_t pte_l2_l_cache_mode_pt; 5914 pt_entry_t pte_l2_l_cache_mask; 5915 5916 pt_entry_t pte_l2_s_cache_mode; 5917 pt_entry_t pte_l2_s_cache_mode_pt; 5918 pt_entry_t pte_l2_s_cache_mask; 5919 5920 pt_entry_t pte_l2_s_prot_u; 5921 pt_entry_t pte_l2_s_prot_w; 5922 pt_entry_t pte_l2_s_prot_mask; 5923 5924 pt_entry_t pte_l1_s_proto; 5925 pt_entry_t pte_l1_c_proto; 5926 pt_entry_t pte_l2_s_proto; 5927 5928 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5929 void (*pmap_zero_page_func)(paddr_t); 5930 5931 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 5932 void 5933 pmap_pte_init_generic(void) 5934 { 5935 5936 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5937 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5938 5939 pte_l2_l_cache_mode = L2_B|L2_C; 5940 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5941 5942 pte_l2_s_cache_mode = L2_B|L2_C; 5943 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5944 5945 /* 5946 * If we have a write-through cache, set B and C. If 5947 * we have a write-back cache, then we assume setting 5948 * only C will make those pages write-through. 5949 */ 5950 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5951 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5952 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5953 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5954 } else { 5955 #if ARM_MMU_V6 > 1 5956 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5957 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5958 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5959 #else 5960 pte_l1_s_cache_mode_pt = L1_S_C; 5961 pte_l2_l_cache_mode_pt = L2_C; 5962 pte_l2_s_cache_mode_pt = L2_C; 5963 #endif 5964 } 5965 5966 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5967 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5968 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5969 5970 pte_l1_s_proto = L1_S_PROTO_generic; 5971 pte_l1_c_proto = L1_C_PROTO_generic; 5972 pte_l2_s_proto = L2_S_PROTO_generic; 5973 5974 pmap_copy_page_func = pmap_copy_page_generic; 5975 pmap_zero_page_func = pmap_zero_page_generic; 5976 } 5977 5978 #if defined(CPU_ARM8) 5979 void 5980 pmap_pte_init_arm8(void) 5981 { 5982 5983 /* 5984 * ARM8 is compatible with generic, but we need to use 5985 * the page tables uncached. 5986 */ 5987 pmap_pte_init_generic(); 5988 5989 pte_l1_s_cache_mode_pt = 0; 5990 pte_l2_l_cache_mode_pt = 0; 5991 pte_l2_s_cache_mode_pt = 0; 5992 } 5993 #endif /* CPU_ARM8 */ 5994 5995 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 5996 void 5997 pmap_pte_init_arm9(void) 5998 { 5999 6000 /* 6001 * ARM9 is compatible with generic, but we want to use 6002 * write-through caching for now. 6003 */ 6004 pmap_pte_init_generic(); 6005 6006 pte_l1_s_cache_mode = L1_S_C; 6007 pte_l2_l_cache_mode = L2_C; 6008 pte_l2_s_cache_mode = L2_C; 6009 6010 pte_l1_s_cache_mode_pt = L1_S_C; 6011 pte_l2_l_cache_mode_pt = L2_C; 6012 pte_l2_s_cache_mode_pt = L2_C; 6013 } 6014 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6015 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6016 6017 #if defined(CPU_ARM10) 6018 void 6019 pmap_pte_init_arm10(void) 6020 { 6021 6022 /* 6023 * ARM10 is compatible with generic, but we want to use 6024 * write-through caching for now. 6025 */ 6026 pmap_pte_init_generic(); 6027 6028 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6029 pte_l2_l_cache_mode = L2_B | L2_C; 6030 pte_l2_s_cache_mode = L2_B | L2_C; 6031 6032 pte_l1_s_cache_mode_pt = L1_S_C; 6033 pte_l2_l_cache_mode_pt = L2_C; 6034 pte_l2_s_cache_mode_pt = L2_C; 6035 6036 } 6037 #endif /* CPU_ARM10 */ 6038 6039 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6040 void 6041 pmap_pte_init_arm11(void) 6042 { 6043 6044 /* 6045 * ARM11 is compatible with generic, but we want to use 6046 * write-through caching for now. 6047 */ 6048 pmap_pte_init_generic(); 6049 6050 pte_l1_s_cache_mode = L1_S_C; 6051 pte_l2_l_cache_mode = L2_C; 6052 pte_l2_s_cache_mode = L2_C; 6053 6054 pte_l1_s_cache_mode_pt = L1_S_C; 6055 pte_l2_l_cache_mode_pt = L2_C; 6056 pte_l2_s_cache_mode_pt = L2_C; 6057 } 6058 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6059 6060 #if ARM_MMU_SA1 == 1 6061 void 6062 pmap_pte_init_sa1(void) 6063 { 6064 6065 /* 6066 * The StrongARM SA-1 cache does not have a write-through 6067 * mode. So, do the generic initialization, then reset 6068 * the page table cache mode to B=1,C=1, and note that 6069 * the PTEs need to be sync'd. 6070 */ 6071 pmap_pte_init_generic(); 6072 6073 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6074 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6075 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6076 6077 pmap_needs_pte_sync = 1; 6078 } 6079 #endif /* ARM_MMU_SA1 == 1*/ 6080 6081 #if ARM_MMU_XSCALE == 1 6082 #if (ARM_NMMUS > 1) 6083 static u_int xscale_use_minidata; 6084 #endif 6085 6086 void 6087 pmap_pte_init_xscale(void) 6088 { 6089 uint32_t auxctl; 6090 int write_through = 0; 6091 6092 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6093 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6094 6095 pte_l2_l_cache_mode = L2_B|L2_C; 6096 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6097 6098 pte_l2_s_cache_mode = L2_B|L2_C; 6099 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6100 6101 pte_l1_s_cache_mode_pt = L1_S_C; 6102 pte_l2_l_cache_mode_pt = L2_C; 6103 pte_l2_s_cache_mode_pt = L2_C; 6104 6105 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6106 /* 6107 * The XScale core has an enhanced mode where writes that 6108 * miss the cache cause a cache line to be allocated. This 6109 * is significantly faster than the traditional, write-through 6110 * behavior of this case. 6111 */ 6112 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6113 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6114 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6115 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6116 6117 #ifdef XSCALE_CACHE_WRITE_THROUGH 6118 /* 6119 * Some versions of the XScale core have various bugs in 6120 * their cache units, the work-around for which is to run 6121 * the cache in write-through mode. Unfortunately, this 6122 * has a major (negative) impact on performance. So, we 6123 * go ahead and run fast-and-loose, in the hopes that we 6124 * don't line up the planets in a way that will trip the 6125 * bugs. 6126 * 6127 * However, we give you the option to be slow-but-correct. 6128 */ 6129 write_through = 1; 6130 #elif defined(XSCALE_CACHE_WRITE_BACK) 6131 /* force write back cache mode */ 6132 write_through = 0; 6133 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6134 /* 6135 * Intel PXA2[15]0 processors are known to have a bug in 6136 * write-back cache on revision 4 and earlier (stepping 6137 * A[01] and B[012]). Fixed for C0 and later. 6138 */ 6139 { 6140 uint32_t id, type; 6141 6142 id = cpufunc_id(); 6143 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6144 6145 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6146 if ((id & CPU_ID_REVISION_MASK) < 5) { 6147 /* write through for stepping A0-1 and B0-2 */ 6148 write_through = 1; 6149 } 6150 } 6151 } 6152 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6153 6154 if (write_through) { 6155 pte_l1_s_cache_mode = L1_S_C; 6156 pte_l2_l_cache_mode = L2_C; 6157 pte_l2_s_cache_mode = L2_C; 6158 } 6159 6160 #if (ARM_NMMUS > 1) 6161 xscale_use_minidata = 1; 6162 #endif 6163 6164 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6165 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6166 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6167 6168 pte_l1_s_proto = L1_S_PROTO_xscale; 6169 pte_l1_c_proto = L1_C_PROTO_xscale; 6170 pte_l2_s_proto = L2_S_PROTO_xscale; 6171 6172 pmap_copy_page_func = pmap_copy_page_xscale; 6173 pmap_zero_page_func = pmap_zero_page_xscale; 6174 6175 /* 6176 * Disable ECC protection of page table access, for now. 6177 */ 6178 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6179 auxctl &= ~XSCALE_AUXCTL_P; 6180 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6181 } 6182 6183 /* 6184 * xscale_setup_minidata: 6185 * 6186 * Set up the mini-data cache clean area. We require the 6187 * caller to allocate the right amount of physically and 6188 * virtually contiguous space. 6189 */ 6190 void 6191 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6192 { 6193 extern vaddr_t xscale_minidata_clean_addr; 6194 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6195 pd_entry_t *pde = (pd_entry_t *) l1pt; 6196 pt_entry_t *pte; 6197 vsize_t size; 6198 uint32_t auxctl; 6199 6200 xscale_minidata_clean_addr = va; 6201 6202 /* Round it to page size. */ 6203 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6204 6205 for (; size != 0; 6206 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6207 #ifndef ARM32_NEW_VM_LAYOUT 6208 pte = (pt_entry_t *) 6209 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6210 #else 6211 pte = (pt_entry_t *) kernel_pt_lookup( 6212 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6213 #endif 6214 if (pte == NULL) 6215 panic("xscale_setup_minidata: can't find L2 table for " 6216 "VA 0x%08lx", va); 6217 #ifndef ARM32_NEW_VM_LAYOUT 6218 pte[(va >> PGSHIFT) & 0x3ff] = 6219 #else 6220 pte[l2pte_index(va)] = 6221 #endif 6222 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6223 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6224 } 6225 6226 /* 6227 * Configure the mini-data cache for write-back with 6228 * read/write-allocate. 6229 * 6230 * NOTE: In order to reconfigure the mini-data cache, we must 6231 * make sure it contains no valid data! In order to do that, 6232 * we must issue a global data cache invalidate command! 6233 * 6234 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6235 * THIS IS VERY IMPORTANT! 6236 */ 6237 6238 /* Invalidate data and mini-data. */ 6239 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6240 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6241 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6242 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6243 } 6244 6245 /* 6246 * Change the PTEs for the specified kernel mappings such that they 6247 * will use the mini data cache instead of the main data cache. 6248 */ 6249 void 6250 pmap_uarea(vaddr_t va) 6251 { 6252 struct l2_bucket *l2b; 6253 pt_entry_t *ptep, *sptep, pte; 6254 vaddr_t next_bucket, eva; 6255 6256 #if (ARM_NMMUS > 1) 6257 if (xscale_use_minidata == 0) 6258 return; 6259 #endif 6260 6261 eva = va + USPACE; 6262 6263 while (va < eva) { 6264 next_bucket = L2_NEXT_BUCKET(va); 6265 if (next_bucket > eva) 6266 next_bucket = eva; 6267 6268 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6269 KDASSERT(l2b != NULL); 6270 6271 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6272 6273 while (va < next_bucket) { 6274 pte = *ptep; 6275 if (!l2pte_minidata(pte)) { 6276 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6277 cpu_tlb_flushD_SE(va); 6278 *ptep = pte & ~L2_B; 6279 } 6280 ptep++; 6281 va += PAGE_SIZE; 6282 } 6283 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6284 } 6285 cpu_cpwait(); 6286 } 6287 #endif /* ARM_MMU_XSCALE == 1 */ 6288 6289 /* 6290 * return the PA of the current L1 table, for use when handling a crash dump 6291 */ 6292 uint32_t pmap_kernel_L1_addr(void) 6293 { 6294 return pmap_kernel()->pm_l1->l1_physaddr; 6295 } 6296 6297 #if defined(DDB) 6298 /* 6299 * A couple of ddb-callable functions for dumping pmaps 6300 */ 6301 void pmap_dump_all(void); 6302 void pmap_dump(pmap_t); 6303 6304 void 6305 pmap_dump_all(void) 6306 { 6307 pmap_t pm; 6308 6309 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6310 if (pm == pmap_kernel()) 6311 continue; 6312 pmap_dump(pm); 6313 printf("\n"); 6314 } 6315 } 6316 6317 static pt_entry_t ncptes[64]; 6318 static void pmap_dump_ncpg(pmap_t); 6319 6320 void 6321 pmap_dump(pmap_t pm) 6322 { 6323 struct l2_dtable *l2; 6324 struct l2_bucket *l2b; 6325 pt_entry_t *ptep, pte; 6326 vaddr_t l2_va, l2b_va, va; 6327 int i, j, k, occ, rows = 0; 6328 6329 if (pm == pmap_kernel()) 6330 printf("pmap_kernel (%p): ", pm); 6331 else 6332 printf("user pmap (%p): ", pm); 6333 6334 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6335 6336 l2_va = 0; 6337 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6338 l2 = pm->pm_l2[i]; 6339 6340 if (l2 == NULL || l2->l2_occupancy == 0) 6341 continue; 6342 6343 l2b_va = l2_va; 6344 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6345 l2b = &l2->l2_bucket[j]; 6346 6347 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6348 continue; 6349 6350 ptep = l2b->l2b_kva; 6351 6352 for (k = 0; k < 256 && ptep[k] == 0; k++) 6353 ; 6354 6355 k &= ~63; 6356 occ = l2b->l2b_occupancy; 6357 va = l2b_va + (k * 4096); 6358 for (; k < 256; k++, va += 0x1000) { 6359 char ch = ' '; 6360 if ((k % 64) == 0) { 6361 if ((rows % 8) == 0) { 6362 printf( 6363 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6364 } 6365 printf("%08lx: ", va); 6366 } 6367 6368 ncptes[k & 63] = 0; 6369 pte = ptep[k]; 6370 if (pte == 0) { 6371 ch = '.'; 6372 } else { 6373 occ--; 6374 switch (pte & 0x0c) { 6375 case 0x00: 6376 ch = 'D'; /* No cache No buff */ 6377 break; 6378 case 0x04: 6379 ch = 'B'; /* No cache buff */ 6380 break; 6381 case 0x08: 6382 if (pte & 0x40) 6383 ch = 'm'; 6384 else 6385 ch = 'C'; /* Cache No buff */ 6386 break; 6387 case 0x0c: 6388 ch = 'F'; /* Cache Buff */ 6389 break; 6390 } 6391 6392 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6393 ch += 0x20; 6394 6395 if ((pte & 0xc) == 0) 6396 ncptes[k & 63] = pte; 6397 } 6398 6399 if ((k % 64) == 63) { 6400 rows++; 6401 printf("%c\n", ch); 6402 pmap_dump_ncpg(pm); 6403 if (occ == 0) 6404 break; 6405 } else 6406 printf("%c", ch); 6407 } 6408 } 6409 } 6410 } 6411 6412 static void 6413 pmap_dump_ncpg(pmap_t pm) 6414 { 6415 struct vm_page *pg; 6416 struct vm_page_md *md; 6417 struct pv_entry *pv; 6418 int i; 6419 6420 for (i = 0; i < 63; i++) { 6421 if (ncptes[i] == 0) 6422 continue; 6423 6424 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6425 if (pg == NULL) 6426 continue; 6427 md = VM_PAGE_TO_MD(pg); 6428 6429 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6430 VM_PAGE_TO_PHYS(pg), 6431 md->krw_mappings, md->kro_mappings, 6432 md->urw_mappings, md->uro_mappings); 6433 6434 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6435 printf(" %c va 0x%08lx, flags 0x%x\n", 6436 (pm == pv->pv_pmap) ? '*' : ' ', 6437 pv->pv_va, pv->pv_flags); 6438 } 6439 } 6440 } 6441 #endif 6442 6443 #ifdef PMAP_STEAL_MEMORY 6444 void 6445 pmap_boot_pageadd(pv_addr_t *newpv) 6446 { 6447 pv_addr_t *pv, *npv; 6448 6449 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6450 if (newpv->pv_pa < pv->pv_va) { 6451 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6452 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6453 newpv->pv_size += pv->pv_size; 6454 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6455 } 6456 pv = NULL; 6457 } else { 6458 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6459 pv = npv) { 6460 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6461 KASSERT(pv->pv_pa < newpv->pv_pa); 6462 if (newpv->pv_pa > npv->pv_pa) 6463 continue; 6464 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6465 pv->pv_size += newpv->pv_size; 6466 return; 6467 } 6468 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6469 break; 6470 newpv->pv_size += npv->pv_size; 6471 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6472 SLIST_REMOVE_AFTER(newpv, pv_list); 6473 return; 6474 } 6475 } 6476 } 6477 6478 if (pv) { 6479 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6480 } else { 6481 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6482 } 6483 } 6484 6485 void 6486 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6487 pv_addr_t *rpv) 6488 { 6489 pv_addr_t *pv, **pvp; 6490 struct vm_physseg *ps; 6491 size_t i; 6492 6493 KASSERT(amount & PGOFSET); 6494 KASSERT((mask & PGOFSET) == 0); 6495 KASSERT((match & PGOFSET) == 0); 6496 KASSERT(amount != 0); 6497 6498 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6499 (pv = *pvp) != NULL; 6500 pvp = &SLIST_NEXT(pv, pv_list)) { 6501 pv_addr_t *newpv; 6502 psize_t off; 6503 /* 6504 * If this entry is too small to satify the request... 6505 */ 6506 KASSERT(pv->pv_size > 0); 6507 if (pv->pv_size < amount) 6508 continue; 6509 6510 for (off = 0; off <= mask; off += PAGE_SIZE) { 6511 if (((pv->pv_pa + off) & mask) == match 6512 && off + amount <= pv->pv_size) 6513 break; 6514 } 6515 if (off > mask) 6516 continue; 6517 6518 rpv->pv_va = pv->pv_va + off; 6519 rpv->pv_pa = pv->pv_pa + off; 6520 rpv->pv_size = amount; 6521 pv->pv_size -= amount; 6522 if (pv->pv_size == 0) { 6523 KASSERT(off == 0); 6524 KASSERT((vaddr_t) pv == rpv->pv_va); 6525 *pvp = SLIST_NEXT(pv, pv_list); 6526 } else if (off == 0) { 6527 KASSERT((vaddr_t) pv == rpv->pv_va); 6528 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6529 *newpv = *pv; 6530 newpv->pv_pa += amount; 6531 newpv->pv_va += amount; 6532 *pvp = newpv; 6533 } else if (off < pv->pv_size) { 6534 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6535 *newpv = *pv; 6536 newpv->pv_size -= off; 6537 newpv->pv_pa += off + amount; 6538 newpv->pv_va += off + amount; 6539 6540 SLIST_NEXT(pv, pv_list) = newpv; 6541 pv->pv_size = off; 6542 } else { 6543 KASSERT((vaddr_t) pv != rpv->pv_va); 6544 } 6545 memset((void *)rpv->pv_va, 0, amount); 6546 return; 6547 } 6548 6549 if (vm_nphysseg == 0) 6550 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6551 6552 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6553 (pv = *pvp) != NULL; 6554 pvp = &SLIST_NEXT(pv, pv_list)) { 6555 if (SLIST_NEXT(pv, pv_list) == NULL) 6556 break; 6557 } 6558 KASSERT(mask == 0); 6559 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6560 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6561 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6562 rpv->pv_va = pv->pv_va; 6563 rpv->pv_pa = pv->pv_pa; 6564 rpv->pv_size = amount; 6565 *pvp = NULL; 6566 pmap_map_chunk(kernel_l1pt.pv_va, 6567 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6568 ptoa(ps->avail_start), 6569 amount - pv->pv_size, 6570 VM_PROT_READ|VM_PROT_WRITE, 6571 PTE_CACHE); 6572 ps->avail_start += atop(amount - pv->pv_size); 6573 /* 6574 * If we consumed the entire physseg, remove it. 6575 */ 6576 if (ps->avail_start == ps->avail_end) { 6577 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6578 ps[0] = ps[1]; 6579 } 6580 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6581 return; 6582 } 6583 } 6584 6585 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6586 } 6587 6588 vaddr_t 6589 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6590 { 6591 pv_addr_t pv; 6592 6593 pmap_boot_pagealloc(size, 0, 0, &pv); 6594 6595 return pv.pv_va; 6596 } 6597 #endif /* PMAP_STEAL_MEMORY */ 6598 6599 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6600 { 6601 sysctl_createv(clog, 0, NULL, NULL, 6602 CTLFLAG_PERMANENT, 6603 CTLTYPE_NODE, "machdep", NULL, 6604 NULL, 0, NULL, 0, 6605 CTL_MACHDEP, CTL_EOL); 6606 6607 sysctl_createv(clog, 0, NULL, NULL, 6608 CTLFLAG_PERMANENT, 6609 CTLTYPE_INT, "kmpages", 6610 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6611 NULL, 0, &pmap_kmpages, 0, 6612 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6613 } 6614
Indexes created Thu Oct 23 22:10:10 GMT 2025