pmap.c revision 1.216
1 /* $NetBSD: pmap.c,v 1.216 2010/11/02 06:33:22 uebayasi Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/pool.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <machine/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.216 2010/11/02 06:33:22 uebayasi Exp $"); 215 216 #define VM_PAGE_TO_MD(pg) (&(pg)->mdpage) 217 218 #ifdef PMAP_DEBUG 219 220 /* XXX need to get rid of all refs to this */ 221 int pmap_debug_level = 0; 222 223 /* 224 * for switching to potentially finer grained debugging 225 */ 226 #define PDB_FOLLOW 0x0001 227 #define PDB_INIT 0x0002 228 #define PDB_ENTER 0x0004 229 #define PDB_REMOVE 0x0008 230 #define PDB_CREATE 0x0010 231 #define PDB_PTPAGE 0x0020 232 #define PDB_GROWKERN 0x0040 233 #define PDB_BITS 0x0080 234 #define PDB_COLLECT 0x0100 235 #define PDB_PROTECT 0x0200 236 #define PDB_MAP_L1 0x0400 237 #define PDB_BOOTSTRAP 0x1000 238 #define PDB_PARANOIA 0x2000 239 #define PDB_WIRING 0x4000 240 #define PDB_PVDUMP 0x8000 241 #define PDB_VAC 0x10000 242 #define PDB_KENTER 0x20000 243 #define PDB_KREMOVE 0x40000 244 #define PDB_EXEC 0x80000 245 246 int debugmap = 1; 247 int pmapdebug = 0; 248 #define NPDEBUG(_lev_,_stat_) \ 249 if (pmapdebug & (_lev_)) \ 250 ((_stat_)) 251 252 #else /* PMAP_DEBUG */ 253 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 254 #endif /* PMAP_DEBUG */ 255 256 /* 257 * pmap_kernel() points here 258 */ 259 static struct pmap kernel_pmap_store; 260 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 261 262 /* 263 * Which pmap is currently 'live' in the cache 264 * 265 * XXXSCW: Fix for SMP ... 266 */ 267 static pmap_t pmap_recent_user; 268 269 /* 270 * Pointer to last active lwp, or NULL if it exited. 271 */ 272 struct lwp *pmap_previous_active_lwp; 273 274 /* 275 * Pool and cache that pmap structures are allocated from. 276 * We use a cache to avoid clearing the pm_l2[] array (1KB) 277 * in pmap_create(). 278 */ 279 static struct pool_cache pmap_cache; 280 static LIST_HEAD(, pmap) pmap_pmaps; 281 282 /* 283 * Pool of PV structures 284 */ 285 static struct pool pmap_pv_pool; 286 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 287 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 288 static struct pool_allocator pmap_bootstrap_pv_allocator = { 289 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 290 }; 291 292 /* 293 * Pool and cache of l2_dtable structures. 294 * We use a cache to avoid clearing the structures when they're 295 * allocated. (196 bytes) 296 */ 297 static struct pool_cache pmap_l2dtable_cache; 298 static vaddr_t pmap_kernel_l2dtable_kva; 299 300 /* 301 * Pool and cache of L2 page descriptors. 302 * We use a cache to avoid clearing the descriptor table 303 * when they're allocated. (1KB) 304 */ 305 static struct pool_cache pmap_l2ptp_cache; 306 static vaddr_t pmap_kernel_l2ptp_kva; 307 static paddr_t pmap_kernel_l2ptp_phys; 308 309 #ifdef PMAPCOUNTERS 310 #define PMAP_EVCNT_INITIALIZER(name) \ 311 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 312 313 #ifdef PMAP_CACHE_VIPT 314 static struct evcnt pmap_ev_vac_clean_one = 315 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_one = 317 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_lots = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 320 static struct evcnt pmap_ev_vac_flush_lots2 = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 326 327 static struct evcnt pmap_ev_vac_color_new = 328 PMAP_EVCNT_INITIALIZER("new page color"); 329 static struct evcnt pmap_ev_vac_color_reuse = 330 PMAP_EVCNT_INITIALIZER("ok first page color"); 331 static struct evcnt pmap_ev_vac_color_ok = 332 PMAP_EVCNT_INITIALIZER("ok page color"); 333 static struct evcnt pmap_ev_vac_color_blind = 334 PMAP_EVCNT_INITIALIZER("blind page color"); 335 static struct evcnt pmap_ev_vac_color_change = 336 PMAP_EVCNT_INITIALIZER("change page color"); 337 static struct evcnt pmap_ev_vac_color_erase = 338 PMAP_EVCNT_INITIALIZER("erase page color"); 339 static struct evcnt pmap_ev_vac_color_none = 340 PMAP_EVCNT_INITIALIZER("no page color"); 341 static struct evcnt pmap_ev_vac_color_restore = 342 PMAP_EVCNT_INITIALIZER("restore page color"); 343 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 352 #endif 353 354 static struct evcnt pmap_ev_mappings = 355 PMAP_EVCNT_INITIALIZER("pages mapped"); 356 static struct evcnt pmap_ev_unmappings = 357 PMAP_EVCNT_INITIALIZER("pages unmapped"); 358 static struct evcnt pmap_ev_remappings = 359 PMAP_EVCNT_INITIALIZER("pages remapped"); 360 361 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 362 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 363 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 364 365 static struct evcnt pmap_ev_kernel_mappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 367 static struct evcnt pmap_ev_kernel_unmappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 369 static struct evcnt pmap_ev_kernel_remappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 371 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 373 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 375 376 static struct evcnt pmap_ev_kenter_mappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 378 static struct evcnt pmap_ev_kenter_unmappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 380 static struct evcnt pmap_ev_kenter_remappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 382 static struct evcnt pmap_ev_pt_mappings = 383 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 384 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 389 390 #ifdef PMAP_CACHE_VIPT 391 static struct evcnt pmap_ev_exec_mappings = 392 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 393 static struct evcnt pmap_ev_exec_cached = 394 PMAP_EVCNT_INITIALIZER("exec pages cached"); 395 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 397 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 398 399 static struct evcnt pmap_ev_exec_synced = 400 PMAP_EVCNT_INITIALIZER("exec pages synced"); 401 static struct evcnt pmap_ev_exec_synced_map = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 403 static struct evcnt pmap_ev_exec_synced_unmap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 405 static struct evcnt pmap_ev_exec_synced_remap = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 407 static struct evcnt pmap_ev_exec_synced_clearbit = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 409 static struct evcnt pmap_ev_exec_synced_kremove = 410 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 411 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 418 419 static struct evcnt pmap_ev_exec_discarded_unmap = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 421 static struct evcnt pmap_ev_exec_discarded_zero = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 423 static struct evcnt pmap_ev_exec_discarded_copy = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 425 static struct evcnt pmap_ev_exec_discarded_page_protect = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 427 static struct evcnt pmap_ev_exec_discarded_clearbit = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 429 static struct evcnt pmap_ev_exec_discarded_kremove = 430 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 431 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 438 #endif /* PMAP_CACHE_VIPT */ 439 440 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 441 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 442 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 443 444 EVCNT_ATTACH_STATIC(pmap_ev_updates); 445 EVCNT_ATTACH_STATIC(pmap_ev_collects); 446 EVCNT_ATTACH_STATIC(pmap_ev_activations); 447 448 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 449 #else 450 #define PMAPCOUNT(x) ((void)0) 451 #endif 452 453 /* 454 * pmap copy/zero page, and mem(5) hook point 455 */ 456 static pt_entry_t *csrc_pte, *cdst_pte; 457 static vaddr_t csrcp, cdstp; 458 vaddr_t memhook; /* used by mem.c */ 459 kmutex_t memlock; /* used by mem.c */ 460 void *zeropage; /* used by mem.c */ 461 extern void *msgbufaddr; 462 int pmap_kmpages; 463 /* 464 * Flag to indicate if pmap_init() has done its thing 465 */ 466 bool pmap_initialized; 467 468 /* 469 * Misc. locking data structures 470 */ 471 472 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 473 static struct lock pmap_main_lock; 474 475 #define PMAP_MAP_TO_HEAD_LOCK() \ 476 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 477 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 478 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 479 #define PMAP_HEAD_TO_MAP_LOCK() \ 480 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 481 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 482 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 483 #else 484 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 485 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 486 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 487 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 488 #endif 489 490 #define pmap_acquire_pmap_lock(pm) \ 491 do { \ 492 if ((pm) != pmap_kernel()) \ 493 mutex_enter(&(pm)->pm_lock); \ 494 } while (/*CONSTCOND*/0) 495 496 #define pmap_release_pmap_lock(pm) \ 497 do { \ 498 if ((pm) != pmap_kernel()) \ 499 mutex_exit(&(pm)->pm_lock); \ 500 } while (/*CONSTCOND*/0) 501 502 503 /* 504 * Metadata for L1 translation tables. 505 */ 506 struct l1_ttable { 507 /* Entry on the L1 Table list */ 508 SLIST_ENTRY(l1_ttable) l1_link; 509 510 /* Entry on the L1 Least Recently Used list */ 511 TAILQ_ENTRY(l1_ttable) l1_lru; 512 513 /* Track how many domains are allocated from this L1 */ 514 volatile u_int l1_domain_use_count; 515 516 /* 517 * A free-list of domain numbers for this L1. 518 * We avoid using ffs() and a bitmap to track domains since ffs() 519 * is slow on ARM. 520 */ 521 u_int8_t l1_domain_first; 522 u_int8_t l1_domain_free[PMAP_DOMAINS]; 523 524 /* Physical address of this L1 page table */ 525 paddr_t l1_physaddr; 526 527 /* KVA of this L1 page table */ 528 pd_entry_t *l1_kva; 529 }; 530 531 /* 532 * Convert a virtual address into its L1 table index. That is, the 533 * index used to locate the L2 descriptor table pointer in an L1 table. 534 * This is basically used to index l1->l1_kva[]. 535 * 536 * Each L2 descriptor table represents 1MB of VA space. 537 */ 538 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 539 540 /* 541 * L1 Page Tables are tracked using a Least Recently Used list. 542 * - New L1s are allocated from the HEAD. 543 * - Freed L1s are added to the TAIl. 544 * - Recently accessed L1s (where an 'access' is some change to one of 545 * the userland pmaps which owns this L1) are moved to the TAIL. 546 */ 547 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 548 static struct simplelock l1_lru_lock; 549 550 /* 551 * A list of all L1 tables 552 */ 553 static SLIST_HEAD(, l1_ttable) l1_list; 554 555 /* 556 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 557 * 558 * This is normally 16MB worth L2 page descriptors for any given pmap. 559 * Reference counts are maintained for L2 descriptors so they can be 560 * freed when empty. 561 */ 562 struct l2_dtable { 563 /* The number of L2 page descriptors allocated to this l2_dtable */ 564 u_int l2_occupancy; 565 566 /* List of L2 page descriptors */ 567 struct l2_bucket { 568 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 569 paddr_t l2b_phys; /* Physical address of same */ 570 u_short l2b_l1idx; /* This L2 table's L1 index */ 571 u_short l2b_occupancy; /* How many active descriptors */ 572 } l2_bucket[L2_BUCKET_SIZE]; 573 }; 574 575 /* 576 * Given an L1 table index, calculate the corresponding l2_dtable index 577 * and bucket index within the l2_dtable. 578 */ 579 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 580 (L2_SIZE - 1)) 581 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 582 583 /* 584 * Given a virtual address, this macro returns the 585 * virtual address required to drop into the next L2 bucket. 586 */ 587 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 588 589 /* 590 * L2 allocation. 591 */ 592 #define pmap_alloc_l2_dtable() \ 593 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 594 #define pmap_free_l2_dtable(l2) \ 595 pool_cache_put(&pmap_l2dtable_cache, (l2)) 596 #define pmap_alloc_l2_ptp(pap) \ 597 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 598 PR_NOWAIT, (pap))) 599 600 /* 601 * We try to map the page tables write-through, if possible. However, not 602 * all CPUs have a write-through cache mode, so on those we have to sync 603 * the cache when we frob page tables. 604 * 605 * We try to evaluate this at compile time, if possible. However, it's 606 * not always possible to do that, hence this run-time var. 607 */ 608 int pmap_needs_pte_sync; 609 610 /* 611 * Real definition of pv_entry. 612 */ 613 struct pv_entry { 614 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 615 pmap_t pv_pmap; /* pmap where mapping lies */ 616 vaddr_t pv_va; /* virtual address for mapping */ 617 u_int pv_flags; /* flags */ 618 }; 619 620 /* 621 * Macro to determine if a mapping might be resident in the 622 * instruction cache and/or TLB 623 */ 624 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 625 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 626 627 /* 628 * Macro to determine if a mapping might be resident in the 629 * data cache and/or TLB 630 */ 631 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 632 633 /* 634 * Local prototypes 635 */ 636 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 637 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 638 pt_entry_t **); 639 static bool pmap_is_current(pmap_t); 640 static bool pmap_is_cached(pmap_t); 641 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 642 pmap_t, vaddr_t, u_int); 643 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 644 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 645 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 646 u_int, u_int); 647 648 static void pmap_pinit(pmap_t); 649 static int pmap_pmap_ctor(void *, void *, int); 650 651 static void pmap_alloc_l1(pmap_t); 652 static void pmap_free_l1(pmap_t); 653 static void pmap_use_l1(pmap_t); 654 655 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 656 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 657 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 658 static int pmap_l2ptp_ctor(void *, void *, int); 659 static int pmap_l2dtable_ctor(void *, void *, int); 660 661 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 662 #ifdef PMAP_CACHE_VIVT 663 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 664 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 665 #endif 666 667 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 668 #ifdef PMAP_CACHE_VIVT 669 static int pmap_clean_page(struct pv_entry *, bool); 670 #endif 671 #ifdef PMAP_CACHE_VIPT 672 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 673 enum pmap_flush_op { 674 PMAP_FLUSH_PRIMARY, 675 PMAP_FLUSH_SECONDARY, 676 PMAP_CLEAN_PRIMARY 677 }; 678 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 679 #endif 680 static void pmap_page_remove(struct vm_page_md *, paddr_t); 681 682 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 683 static vaddr_t kernel_pt_lookup(paddr_t); 684 685 686 /* 687 * External function prototypes 688 */ 689 extern void bzero_page(vaddr_t); 690 extern void bcopy_page(vaddr_t, vaddr_t); 691 692 /* 693 * Misc variables 694 */ 695 vaddr_t virtual_avail; 696 vaddr_t virtual_end; 697 vaddr_t pmap_curmaxkvaddr; 698 699 paddr_t avail_start; 700 paddr_t avail_end; 701 702 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 703 pv_addr_t kernelpages; 704 pv_addr_t kernel_l1pt; 705 pv_addr_t systempage; 706 707 /* Function to set the debug level of the pmap code */ 708 709 #ifdef PMAP_DEBUG 710 void 711 pmap_debug(int level) 712 { 713 pmap_debug_level = level; 714 printf("pmap_debug: level=%d\n", pmap_debug_level); 715 } 716 #endif /* PMAP_DEBUG */ 717 718 /* 719 * A bunch of routines to conditionally flush the caches/TLB depending 720 * on whether the specified pmap actually needs to be flushed at any 721 * given time. 722 */ 723 static inline void 724 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 725 { 726 727 if (pm->pm_cstate.cs_tlb_id) 728 cpu_tlb_flushID_SE(va); 729 } 730 731 static inline void 732 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 733 { 734 735 if (pm->pm_cstate.cs_tlb_d) 736 cpu_tlb_flushD_SE(va); 737 } 738 739 static inline void 740 pmap_tlb_flushID(pmap_t pm) 741 { 742 743 if (pm->pm_cstate.cs_tlb_id) { 744 cpu_tlb_flushID(); 745 pm->pm_cstate.cs_tlb = 0; 746 } 747 } 748 749 static inline void 750 pmap_tlb_flushD(pmap_t pm) 751 { 752 753 if (pm->pm_cstate.cs_tlb_d) { 754 cpu_tlb_flushD(); 755 pm->pm_cstate.cs_tlb_d = 0; 756 } 757 } 758 759 #ifdef PMAP_CACHE_VIVT 760 static inline void 761 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 762 { 763 if (pm->pm_cstate.cs_cache_id) { 764 cpu_idcache_wbinv_range(va, len); 765 } 766 } 767 768 static inline void 769 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 770 bool do_inv, bool rd_only) 771 { 772 773 if (pm->pm_cstate.cs_cache_d) { 774 if (do_inv) { 775 if (rd_only) 776 cpu_dcache_inv_range(va, len); 777 else 778 cpu_dcache_wbinv_range(va, len); 779 } else 780 if (!rd_only) 781 cpu_dcache_wb_range(va, len); 782 } 783 } 784 785 static inline void 786 pmap_idcache_wbinv_all(pmap_t pm) 787 { 788 if (pm->pm_cstate.cs_cache_id) { 789 cpu_idcache_wbinv_all(); 790 pm->pm_cstate.cs_cache = 0; 791 } 792 } 793 794 static inline void 795 pmap_dcache_wbinv_all(pmap_t pm) 796 { 797 if (pm->pm_cstate.cs_cache_d) { 798 cpu_dcache_wbinv_all(); 799 pm->pm_cstate.cs_cache_d = 0; 800 } 801 } 802 #endif /* PMAP_CACHE_VIVT */ 803 804 static inline bool 805 pmap_is_current(pmap_t pm) 806 { 807 808 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 809 return true; 810 811 return false; 812 } 813 814 static inline bool 815 pmap_is_cached(pmap_t pm) 816 { 817 818 if (pm == pmap_kernel() || pmap_recent_user == NULL || 819 pmap_recent_user == pm) 820 return (true); 821 822 return false; 823 } 824 825 /* 826 * PTE_SYNC_CURRENT: 827 * 828 * Make sure the pte is written out to RAM. 829 * We need to do this for one of two cases: 830 * - We're dealing with the kernel pmap 831 * - There is no pmap active in the cache/tlb. 832 * - The specified pmap is 'active' in the cache/tlb. 833 */ 834 #ifdef PMAP_INCLUDE_PTE_SYNC 835 #define PTE_SYNC_CURRENT(pm, ptep) \ 836 do { \ 837 if (PMAP_NEEDS_PTE_SYNC && \ 838 pmap_is_cached(pm)) \ 839 PTE_SYNC(ptep); \ 840 } while (/*CONSTCOND*/0) 841 #else 842 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 843 #endif 844 845 /* 846 * main pv_entry manipulation functions: 847 * pmap_enter_pv: enter a mapping onto a vm_page list 848 * pmap_remove_pv: remove a mappiing from a vm_page list 849 * 850 * NOTE: pmap_enter_pv expects to lock the pvh itself 851 * pmap_remove_pv expects te caller to lock the pvh before calling 852 */ 853 854 /* 855 * pmap_enter_pv: enter a mapping onto a vm_page lst 856 * 857 * => caller should hold the proper lock on pmap_main_lock 858 * => caller should have pmap locked 859 * => we will gain the lock on the vm_page and allocate the new pv_entry 860 * => caller should adjust ptp's wire_count before calling 861 * => caller should not adjust pmap's wire_count 862 */ 863 static void 864 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 865 vaddr_t va, u_int flags) 866 { 867 struct pv_entry **pvp; 868 869 NPDEBUG(PDB_PVDUMP, 870 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 871 872 pv->pv_pmap = pm; 873 pv->pv_va = va; 874 pv->pv_flags = flags; 875 876 simple_lock(&md->pvh_slock); /* lock vm_page */ 877 pvp = &SLIST_FIRST(&md->pvh_list); 878 #ifdef PMAP_CACHE_VIPT 879 /* 880 * Insert unmanaged entries, writeable first, at the head of 881 * the pv list. 882 */ 883 if (__predict_true((flags & PVF_KENTRY) == 0)) { 884 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 885 pvp = &SLIST_NEXT(*pvp, pv_link); 886 } else if ((flags & PVF_WRITE) == 0) { 887 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 888 pvp = &SLIST_NEXT(*pvp, pv_link); 889 } 890 #endif 891 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 892 *pvp = pv; /* ... locked list */ 893 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 894 #ifdef PMAP_CACHE_VIPT 895 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 896 md->pvh_attrs |= PVF_KMOD; 897 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 898 md->pvh_attrs |= PVF_DIRTY; 899 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 900 #endif 901 if (pm == pmap_kernel()) { 902 PMAPCOUNT(kernel_mappings); 903 if (flags & PVF_WRITE) 904 md->krw_mappings++; 905 else 906 md->kro_mappings++; 907 } else { 908 if (flags & PVF_WRITE) 909 md->urw_mappings++; 910 else 911 md->uro_mappings++; 912 } 913 914 #ifdef PMAP_CACHE_VIPT 915 /* 916 * If this is an exec mapping and its the first exec mapping 917 * for this page, make sure to sync the I-cache. 918 */ 919 if (PV_IS_EXEC_P(flags)) { 920 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 921 pmap_syncicache_page(md, pa); 922 PMAPCOUNT(exec_synced_map); 923 } 924 PMAPCOUNT(exec_mappings); 925 } 926 #endif 927 928 PMAPCOUNT(mappings); 929 simple_unlock(&md->pvh_slock); /* unlock, done! */ 930 931 if (pv->pv_flags & PVF_WIRED) 932 ++pm->pm_stats.wired_count; 933 } 934 935 /* 936 * 937 * pmap_find_pv: Find a pv entry 938 * 939 * => caller should hold lock on vm_page 940 */ 941 static inline struct pv_entry * 942 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 943 { 944 struct pv_entry *pv; 945 946 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 947 if (pm == pv->pv_pmap && va == pv->pv_va) 948 break; 949 } 950 951 return (pv); 952 } 953 954 /* 955 * pmap_remove_pv: try to remove a mapping from a pv_list 956 * 957 * => caller should hold proper lock on pmap_main_lock 958 * => pmap should be locked 959 * => caller should hold lock on vm_page [so that attrs can be adjusted] 960 * => caller should adjust ptp's wire_count and free PTP if needed 961 * => caller should NOT adjust pmap's wire_count 962 * => we return the removed pv 963 */ 964 static struct pv_entry * 965 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 966 { 967 struct pv_entry *pv, **prevptr; 968 969 NPDEBUG(PDB_PVDUMP, 970 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 971 972 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 973 pv = *prevptr; 974 975 while (pv) { 976 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 977 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 978 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 979 if (pv->pv_flags & PVF_WIRED) { 980 --pm->pm_stats.wired_count; 981 } 982 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 983 if (pm == pmap_kernel()) { 984 PMAPCOUNT(kernel_unmappings); 985 if (pv->pv_flags & PVF_WRITE) 986 md->krw_mappings--; 987 else 988 md->kro_mappings--; 989 } else { 990 if (pv->pv_flags & PVF_WRITE) 991 md->urw_mappings--; 992 else 993 md->uro_mappings--; 994 } 995 996 PMAPCOUNT(unmappings); 997 #ifdef PMAP_CACHE_VIPT 998 if (!(pv->pv_flags & PVF_WRITE)) 999 break; 1000 /* 1001 * If this page has had an exec mapping, then if 1002 * this was the last mapping, discard the contents, 1003 * otherwise sync the i-cache for this page. 1004 */ 1005 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1006 if (SLIST_EMPTY(&md->pvh_list)) { 1007 md->pvh_attrs &= ~PVF_EXEC; 1008 PMAPCOUNT(exec_discarded_unmap); 1009 } else { 1010 pmap_syncicache_page(md, pa); 1011 PMAPCOUNT(exec_synced_unmap); 1012 } 1013 } 1014 #endif /* PMAP_CACHE_VIPT */ 1015 break; 1016 } 1017 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1018 pv = *prevptr; /* advance */ 1019 } 1020 1021 #ifdef PMAP_CACHE_VIPT 1022 /* 1023 * If we no longer have a WRITEABLE KENTRY at the head of list, 1024 * clear the KMOD attribute from the page. 1025 */ 1026 if (SLIST_FIRST(&md->pvh_list) == NULL 1027 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1028 md->pvh_attrs &= ~PVF_KMOD; 1029 1030 /* 1031 * If this was a writeable page and there are no more writeable 1032 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1033 * the contents to memory. 1034 */ 1035 if (md->krw_mappings + md->urw_mappings == 0) 1036 md->pvh_attrs &= ~PVF_WRITE; 1037 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1038 #endif /* PMAP_CACHE_VIPT */ 1039 1040 return(pv); /* return removed pv */ 1041 } 1042 1043 /* 1044 * 1045 * pmap_modify_pv: Update pv flags 1046 * 1047 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1048 * => caller should NOT adjust pmap's wire_count 1049 * => caller must call pmap_vac_me_harder() if writable status of a page 1050 * may have changed. 1051 * => we return the old flags 1052 * 1053 * Modify a physical-virtual mapping in the pv table 1054 */ 1055 static u_int 1056 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1057 u_int clr_mask, u_int set_mask) 1058 { 1059 struct pv_entry *npv; 1060 u_int flags, oflags; 1061 1062 KASSERT((clr_mask & PVF_KENTRY) == 0); 1063 KASSERT((set_mask & PVF_KENTRY) == 0); 1064 1065 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1066 return (0); 1067 1068 NPDEBUG(PDB_PVDUMP, 1069 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1070 1071 /* 1072 * There is at least one VA mapping this page. 1073 */ 1074 1075 if (clr_mask & (PVF_REF | PVF_MOD)) { 1076 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1077 #ifdef PMAP_CACHE_VIPT 1078 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1079 md->pvh_attrs |= PVF_DIRTY; 1080 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1081 #endif 1082 } 1083 1084 oflags = npv->pv_flags; 1085 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1086 1087 if ((flags ^ oflags) & PVF_WIRED) { 1088 if (flags & PVF_WIRED) 1089 ++pm->pm_stats.wired_count; 1090 else 1091 --pm->pm_stats.wired_count; 1092 } 1093 1094 if ((flags ^ oflags) & PVF_WRITE) { 1095 if (pm == pmap_kernel()) { 1096 if (flags & PVF_WRITE) { 1097 md->krw_mappings++; 1098 md->kro_mappings--; 1099 } else { 1100 md->kro_mappings++; 1101 md->krw_mappings--; 1102 } 1103 } else { 1104 if (flags & PVF_WRITE) { 1105 md->urw_mappings++; 1106 md->uro_mappings--; 1107 } else { 1108 md->uro_mappings++; 1109 md->urw_mappings--; 1110 } 1111 } 1112 } 1113 #ifdef PMAP_CACHE_VIPT 1114 if (md->urw_mappings + md->krw_mappings == 0) 1115 md->pvh_attrs &= ~PVF_WRITE; 1116 /* 1117 * We have two cases here: the first is from enter_pv (new exec 1118 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1119 * Since in latter, pmap_enter_pv won't do anything, we just have 1120 * to do what pmap_remove_pv would do. 1121 */ 1122 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1123 || (PV_IS_EXEC_P(md->pvh_attrs) 1124 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1125 pmap_syncicache_page(md, pa); 1126 PMAPCOUNT(exec_synced_remap); 1127 } 1128 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1129 #endif 1130 1131 PMAPCOUNT(remappings); 1132 1133 return (oflags); 1134 } 1135 1136 /* 1137 * Allocate an L1 translation table for the specified pmap. 1138 * This is called at pmap creation time. 1139 */ 1140 static void 1141 pmap_alloc_l1(pmap_t pm) 1142 { 1143 struct l1_ttable *l1; 1144 u_int8_t domain; 1145 1146 /* 1147 * Remove the L1 at the head of the LRU list 1148 */ 1149 simple_lock(&l1_lru_lock); 1150 l1 = TAILQ_FIRST(&l1_lru_list); 1151 KDASSERT(l1 != NULL); 1152 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1153 1154 /* 1155 * Pick the first available domain number, and update 1156 * the link to the next number. 1157 */ 1158 domain = l1->l1_domain_first; 1159 l1->l1_domain_first = l1->l1_domain_free[domain]; 1160 1161 /* 1162 * If there are still free domain numbers in this L1, 1163 * put it back on the TAIL of the LRU list. 1164 */ 1165 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1166 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1167 1168 simple_unlock(&l1_lru_lock); 1169 1170 /* 1171 * Fix up the relevant bits in the pmap structure 1172 */ 1173 pm->pm_l1 = l1; 1174 pm->pm_domain = domain; 1175 } 1176 1177 /* 1178 * Free an L1 translation table. 1179 * This is called at pmap destruction time. 1180 */ 1181 static void 1182 pmap_free_l1(pmap_t pm) 1183 { 1184 struct l1_ttable *l1 = pm->pm_l1; 1185 1186 simple_lock(&l1_lru_lock); 1187 1188 /* 1189 * If this L1 is currently on the LRU list, remove it. 1190 */ 1191 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1192 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1193 1194 /* 1195 * Free up the domain number which was allocated to the pmap 1196 */ 1197 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1198 l1->l1_domain_first = pm->pm_domain; 1199 l1->l1_domain_use_count--; 1200 1201 /* 1202 * The L1 now must have at least 1 free domain, so add 1203 * it back to the LRU list. If the use count is zero, 1204 * put it at the head of the list, otherwise it goes 1205 * to the tail. 1206 */ 1207 if (l1->l1_domain_use_count == 0) 1208 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1209 else 1210 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1211 1212 simple_unlock(&l1_lru_lock); 1213 } 1214 1215 static inline void 1216 pmap_use_l1(pmap_t pm) 1217 { 1218 struct l1_ttable *l1; 1219 1220 /* 1221 * Do nothing if we're in interrupt context. 1222 * Access to an L1 by the kernel pmap must not affect 1223 * the LRU list. 1224 */ 1225 if (cpu_intr_p() || pm == pmap_kernel()) 1226 return; 1227 1228 l1 = pm->pm_l1; 1229 1230 /* 1231 * If the L1 is not currently on the LRU list, just return 1232 */ 1233 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1234 return; 1235 1236 simple_lock(&l1_lru_lock); 1237 1238 /* 1239 * Check the use count again, now that we've acquired the lock 1240 */ 1241 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1242 simple_unlock(&l1_lru_lock); 1243 return; 1244 } 1245 1246 /* 1247 * Move the L1 to the back of the LRU list 1248 */ 1249 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1250 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1251 1252 simple_unlock(&l1_lru_lock); 1253 } 1254 1255 /* 1256 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1257 * 1258 * Free an L2 descriptor table. 1259 */ 1260 static inline void 1261 #ifndef PMAP_INCLUDE_PTE_SYNC 1262 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1263 #else 1264 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1265 #endif 1266 { 1267 #ifdef PMAP_INCLUDE_PTE_SYNC 1268 #ifdef PMAP_CACHE_VIVT 1269 /* 1270 * Note: With a write-back cache, we may need to sync this 1271 * L2 table before re-using it. 1272 * This is because it may have belonged to a non-current 1273 * pmap, in which case the cache syncs would have been 1274 * skipped for the pages that were being unmapped. If the 1275 * L2 table were then to be immediately re-allocated to 1276 * the *current* pmap, it may well contain stale mappings 1277 * which have not yet been cleared by a cache write-back 1278 * and so would still be visible to the mmu. 1279 */ 1280 if (need_sync) 1281 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1282 #endif /* PMAP_CACHE_VIVT */ 1283 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1284 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1285 } 1286 1287 /* 1288 * Returns a pointer to the L2 bucket associated with the specified pmap 1289 * and VA, or NULL if no L2 bucket exists for the address. 1290 */ 1291 static inline struct l2_bucket * 1292 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1293 { 1294 struct l2_dtable *l2; 1295 struct l2_bucket *l2b; 1296 u_short l1idx; 1297 1298 l1idx = L1_IDX(va); 1299 1300 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1301 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1302 return (NULL); 1303 1304 return (l2b); 1305 } 1306 1307 /* 1308 * Returns a pointer to the L2 bucket associated with the specified pmap 1309 * and VA. 1310 * 1311 * If no L2 bucket exists, perform the necessary allocations to put an L2 1312 * bucket/page table in place. 1313 * 1314 * Note that if a new L2 bucket/page was allocated, the caller *must* 1315 * increment the bucket occupancy counter appropriately *before* 1316 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1317 * the bucket/page in the meantime. 1318 */ 1319 static struct l2_bucket * 1320 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1321 { 1322 struct l2_dtable *l2; 1323 struct l2_bucket *l2b; 1324 u_short l1idx; 1325 1326 l1idx = L1_IDX(va); 1327 1328 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1329 /* 1330 * No mapping at this address, as there is 1331 * no entry in the L1 table. 1332 * Need to allocate a new l2_dtable. 1333 */ 1334 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1335 return (NULL); 1336 1337 /* 1338 * Link it into the parent pmap 1339 */ 1340 pm->pm_l2[L2_IDX(l1idx)] = l2; 1341 } 1342 1343 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1344 1345 /* 1346 * Fetch pointer to the L2 page table associated with the address. 1347 */ 1348 if (l2b->l2b_kva == NULL) { 1349 pt_entry_t *ptep; 1350 1351 /* 1352 * No L2 page table has been allocated. Chances are, this 1353 * is because we just allocated the l2_dtable, above. 1354 */ 1355 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1356 /* 1357 * Oops, no more L2 page tables available at this 1358 * time. We may need to deallocate the l2_dtable 1359 * if we allocated a new one above. 1360 */ 1361 if (l2->l2_occupancy == 0) { 1362 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1363 pmap_free_l2_dtable(l2); 1364 } 1365 return (NULL); 1366 } 1367 1368 l2->l2_occupancy++; 1369 l2b->l2b_kva = ptep; 1370 l2b->l2b_l1idx = l1idx; 1371 } 1372 1373 return (l2b); 1374 } 1375 1376 /* 1377 * One or more mappings in the specified L2 descriptor table have just been 1378 * invalidated. 1379 * 1380 * Garbage collect the metadata and descriptor table itself if necessary. 1381 * 1382 * The pmap lock must be acquired when this is called (not necessary 1383 * for the kernel pmap). 1384 */ 1385 static void 1386 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1387 { 1388 struct l2_dtable *l2; 1389 pd_entry_t *pl1pd, l1pd; 1390 pt_entry_t *ptep; 1391 u_short l1idx; 1392 1393 KDASSERT(count <= l2b->l2b_occupancy); 1394 1395 /* 1396 * Update the bucket's reference count according to how many 1397 * PTEs the caller has just invalidated. 1398 */ 1399 l2b->l2b_occupancy -= count; 1400 1401 /* 1402 * Note: 1403 * 1404 * Level 2 page tables allocated to the kernel pmap are never freed 1405 * as that would require checking all Level 1 page tables and 1406 * removing any references to the Level 2 page table. See also the 1407 * comment elsewhere about never freeing bootstrap L2 descriptors. 1408 * 1409 * We make do with just invalidating the mapping in the L2 table. 1410 * 1411 * This isn't really a big deal in practice and, in fact, leads 1412 * to a performance win over time as we don't need to continually 1413 * alloc/free. 1414 */ 1415 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1416 return; 1417 1418 /* 1419 * There are no more valid mappings in this level 2 page table. 1420 * Go ahead and NULL-out the pointer in the bucket, then 1421 * free the page table. 1422 */ 1423 l1idx = l2b->l2b_l1idx; 1424 ptep = l2b->l2b_kva; 1425 l2b->l2b_kva = NULL; 1426 1427 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1428 1429 /* 1430 * If the L1 slot matches the pmap's domain 1431 * number, then invalidate it. 1432 */ 1433 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1434 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1435 *pl1pd = 0; 1436 PTE_SYNC(pl1pd); 1437 } 1438 1439 /* 1440 * Release the L2 descriptor table back to the pool cache. 1441 */ 1442 #ifndef PMAP_INCLUDE_PTE_SYNC 1443 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1444 #else 1445 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1446 #endif 1447 1448 /* 1449 * Update the reference count in the associated l2_dtable 1450 */ 1451 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1452 if (--l2->l2_occupancy > 0) 1453 return; 1454 1455 /* 1456 * There are no more valid mappings in any of the Level 1 1457 * slots managed by this l2_dtable. Go ahead and NULL-out 1458 * the pointer in the parent pmap and free the l2_dtable. 1459 */ 1460 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1461 pmap_free_l2_dtable(l2); 1462 } 1463 1464 /* 1465 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1466 * structures. 1467 */ 1468 static int 1469 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1470 { 1471 #ifndef PMAP_INCLUDE_PTE_SYNC 1472 struct l2_bucket *l2b; 1473 pt_entry_t *ptep, pte; 1474 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1475 1476 /* 1477 * The mappings for these page tables were initially made using 1478 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1479 * mode will not be right for page table mappings. To avoid 1480 * polluting the pmap_kenter_pa() code with a special case for 1481 * page tables, we simply fix up the cache-mode here if it's not 1482 * correct. 1483 */ 1484 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1485 KDASSERT(l2b != NULL); 1486 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1487 pte = *ptep; 1488 1489 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1490 /* 1491 * Page tables must have the cache-mode set to Write-Thru. 1492 */ 1493 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1494 PTE_SYNC(ptep); 1495 cpu_tlb_flushD_SE(va); 1496 cpu_cpwait(); 1497 } 1498 #endif 1499 1500 memset(v, 0, L2_TABLE_SIZE_REAL); 1501 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1502 return (0); 1503 } 1504 1505 static int 1506 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1507 { 1508 1509 memset(v, 0, sizeof(struct l2_dtable)); 1510 return (0); 1511 } 1512 1513 static int 1514 pmap_pmap_ctor(void *arg, void *v, int flags) 1515 { 1516 1517 memset(v, 0, sizeof(struct pmap)); 1518 return (0); 1519 } 1520 1521 static void 1522 pmap_pinit(pmap_t pm) 1523 { 1524 struct l2_bucket *l2b; 1525 1526 if (vector_page < KERNEL_BASE) { 1527 /* 1528 * Map the vector page. 1529 */ 1530 pmap_enter(pm, vector_page, systempage.pv_pa, 1531 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1532 pmap_update(pm); 1533 1534 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1535 l2b = pmap_get_l2_bucket(pm, vector_page); 1536 KDASSERT(l2b != NULL); 1537 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1538 L1_C_DOM(pm->pm_domain); 1539 } else 1540 pm->pm_pl1vec = NULL; 1541 } 1542 1543 #ifdef PMAP_CACHE_VIVT 1544 /* 1545 * Since we have a virtually indexed cache, we may need to inhibit caching if 1546 * there is more than one mapping and at least one of them is writable. 1547 * Since we purge the cache on every context switch, we only need to check for 1548 * other mappings within the same pmap, or kernel_pmap. 1549 * This function is also called when a page is unmapped, to possibly reenable 1550 * caching on any remaining mappings. 1551 * 1552 * The code implements the following logic, where: 1553 * 1554 * KW = # of kernel read/write pages 1555 * KR = # of kernel read only pages 1556 * UW = # of user read/write pages 1557 * UR = # of user read only pages 1558 * 1559 * KC = kernel mapping is cacheable 1560 * UC = user mapping is cacheable 1561 * 1562 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1563 * +--------------------------------------------- 1564 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1565 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1566 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1567 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1568 */ 1569 1570 static const int pmap_vac_flags[4][4] = { 1571 {-1, 0, 0, PVF_KNC}, 1572 {0, 0, PVF_NC, PVF_NC}, 1573 {0, PVF_NC, PVF_NC, PVF_NC}, 1574 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1575 }; 1576 1577 static inline int 1578 pmap_get_vac_flags(const struct vm_page_md *md) 1579 { 1580 int kidx, uidx; 1581 1582 kidx = 0; 1583 if (md->kro_mappings || md->krw_mappings > 1) 1584 kidx |= 1; 1585 if (md->krw_mappings) 1586 kidx |= 2; 1587 1588 uidx = 0; 1589 if (md->uro_mappings || md->urw_mappings > 1) 1590 uidx |= 1; 1591 if (md->urw_mappings) 1592 uidx |= 2; 1593 1594 return (pmap_vac_flags[uidx][kidx]); 1595 } 1596 1597 static inline void 1598 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1599 { 1600 int nattr; 1601 1602 nattr = pmap_get_vac_flags(md); 1603 1604 if (nattr < 0) { 1605 md->pvh_attrs &= ~PVF_NC; 1606 return; 1607 } 1608 1609 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1610 return; 1611 1612 if (pm == pmap_kernel()) 1613 pmap_vac_me_kpmap(md, pa, pm, va); 1614 else 1615 pmap_vac_me_user(md, pa, pm, va); 1616 1617 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1618 } 1619 1620 static void 1621 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1622 { 1623 u_int u_cacheable, u_entries; 1624 struct pv_entry *pv; 1625 pmap_t last_pmap = pm; 1626 1627 /* 1628 * Pass one, see if there are both kernel and user pmaps for 1629 * this page. Calculate whether there are user-writable or 1630 * kernel-writable pages. 1631 */ 1632 u_cacheable = 0; 1633 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1634 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1635 u_cacheable++; 1636 } 1637 1638 u_entries = md->urw_mappings + md->uro_mappings; 1639 1640 /* 1641 * We know we have just been updating a kernel entry, so if 1642 * all user pages are already cacheable, then there is nothing 1643 * further to do. 1644 */ 1645 if (md->k_mappings == 0 && u_cacheable == u_entries) 1646 return; 1647 1648 if (u_entries) { 1649 /* 1650 * Scan over the list again, for each entry, if it 1651 * might not be set correctly, call pmap_vac_me_user 1652 * to recalculate the settings. 1653 */ 1654 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1655 /* 1656 * We know kernel mappings will get set 1657 * correctly in other calls. We also know 1658 * that if the pmap is the same as last_pmap 1659 * then we've just handled this entry. 1660 */ 1661 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1662 continue; 1663 1664 /* 1665 * If there are kernel entries and this page 1666 * is writable but non-cacheable, then we can 1667 * skip this entry also. 1668 */ 1669 if (md->k_mappings && 1670 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1671 (PVF_NC | PVF_WRITE)) 1672 continue; 1673 1674 /* 1675 * Similarly if there are no kernel-writable 1676 * entries and the page is already 1677 * read-only/cacheable. 1678 */ 1679 if (md->krw_mappings == 0 && 1680 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1681 continue; 1682 1683 /* 1684 * For some of the remaining cases, we know 1685 * that we must recalculate, but for others we 1686 * can't tell if they are correct or not, so 1687 * we recalculate anyway. 1688 */ 1689 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1690 } 1691 1692 if (md->k_mappings == 0) 1693 return; 1694 } 1695 1696 pmap_vac_me_user(md, pa, pm, va); 1697 } 1698 1699 static void 1700 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1701 { 1702 pmap_t kpmap = pmap_kernel(); 1703 struct pv_entry *pv, *npv = NULL; 1704 struct l2_bucket *l2b; 1705 pt_entry_t *ptep, pte; 1706 u_int entries = 0; 1707 u_int writable = 0; 1708 u_int cacheable_entries = 0; 1709 u_int kern_cacheable = 0; 1710 u_int other_writable = 0; 1711 1712 /* 1713 * Count mappings and writable mappings in this pmap. 1714 * Include kernel mappings as part of our own. 1715 * Keep a pointer to the first one. 1716 */ 1717 npv = NULL; 1718 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1719 /* Count mappings in the same pmap */ 1720 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1721 if (entries++ == 0) 1722 npv = pv; 1723 1724 /* Cacheable mappings */ 1725 if ((pv->pv_flags & PVF_NC) == 0) { 1726 cacheable_entries++; 1727 if (kpmap == pv->pv_pmap) 1728 kern_cacheable++; 1729 } 1730 1731 /* Writable mappings */ 1732 if (pv->pv_flags & PVF_WRITE) 1733 ++writable; 1734 } else 1735 if (pv->pv_flags & PVF_WRITE) 1736 other_writable = 1; 1737 } 1738 1739 /* 1740 * Enable or disable caching as necessary. 1741 * Note: the first entry might be part of the kernel pmap, 1742 * so we can't assume this is indicative of the state of the 1743 * other (maybe non-kpmap) entries. 1744 */ 1745 if ((entries > 1 && writable) || 1746 (entries > 0 && pm == kpmap && other_writable)) { 1747 if (cacheable_entries == 0) 1748 return; 1749 1750 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1751 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1752 (pv->pv_flags & PVF_NC)) 1753 continue; 1754 1755 pv->pv_flags |= PVF_NC; 1756 1757 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1758 KDASSERT(l2b != NULL); 1759 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1760 pte = *ptep & ~L2_S_CACHE_MASK; 1761 1762 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1763 l2pte_valid(pte)) { 1764 if (PV_BEEN_EXECD(pv->pv_flags)) { 1765 #ifdef PMAP_CACHE_VIVT 1766 pmap_idcache_wbinv_range(pv->pv_pmap, 1767 pv->pv_va, PAGE_SIZE); 1768 #endif 1769 pmap_tlb_flushID_SE(pv->pv_pmap, 1770 pv->pv_va); 1771 } else 1772 if (PV_BEEN_REFD(pv->pv_flags)) { 1773 #ifdef PMAP_CACHE_VIVT 1774 pmap_dcache_wb_range(pv->pv_pmap, 1775 pv->pv_va, PAGE_SIZE, true, 1776 (pv->pv_flags & PVF_WRITE) == 0); 1777 #endif 1778 pmap_tlb_flushD_SE(pv->pv_pmap, 1779 pv->pv_va); 1780 } 1781 } 1782 1783 *ptep = pte; 1784 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1785 } 1786 cpu_cpwait(); 1787 } else 1788 if (entries > cacheable_entries) { 1789 /* 1790 * Turn cacheing back on for some pages. If it is a kernel 1791 * page, only do so if there are no other writable pages. 1792 */ 1793 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1794 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1795 (kpmap != pv->pv_pmap || other_writable))) 1796 continue; 1797 1798 pv->pv_flags &= ~PVF_NC; 1799 1800 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1801 KDASSERT(l2b != NULL); 1802 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1803 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1804 1805 if (l2pte_valid(pte)) { 1806 if (PV_BEEN_EXECD(pv->pv_flags)) { 1807 pmap_tlb_flushID_SE(pv->pv_pmap, 1808 pv->pv_va); 1809 } else 1810 if (PV_BEEN_REFD(pv->pv_flags)) { 1811 pmap_tlb_flushD_SE(pv->pv_pmap, 1812 pv->pv_va); 1813 } 1814 } 1815 1816 *ptep = pte; 1817 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1818 } 1819 } 1820 } 1821 #endif 1822 1823 #ifdef PMAP_CACHE_VIPT 1824 static void 1825 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1826 { 1827 struct pv_entry *pv; 1828 vaddr_t tst_mask; 1829 bool bad_alias; 1830 struct l2_bucket *l2b; 1831 pt_entry_t *ptep, pte, opte; 1832 const u_int 1833 rw_mappings = md->urw_mappings + md->krw_mappings, 1834 ro_mappings = md->uro_mappings + md->kro_mappings; 1835 1836 /* do we need to do anything? */ 1837 if (arm_cache_prefer_mask == 0) 1838 return; 1839 1840 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1841 md, pm, va)); 1842 1843 KASSERT(!va || pm); 1844 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1845 1846 /* Already a conflict? */ 1847 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1848 /* just an add, things are already non-cached */ 1849 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1850 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1851 bad_alias = false; 1852 if (va) { 1853 PMAPCOUNT(vac_color_none); 1854 bad_alias = true; 1855 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1856 goto fixup; 1857 } 1858 pv = SLIST_FIRST(&md->pvh_list); 1859 /* the list can't be empty because it would be cachable */ 1860 if (md->pvh_attrs & PVF_KMPAGE) { 1861 tst_mask = md->pvh_attrs; 1862 } else { 1863 KASSERT(pv); 1864 tst_mask = pv->pv_va; 1865 pv = SLIST_NEXT(pv, pv_link); 1866 } 1867 /* 1868 * Only check for a bad alias if we have writable mappings. 1869 */ 1870 tst_mask &= arm_cache_prefer_mask; 1871 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1872 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1873 /* if there's a bad alias, stop checking. */ 1874 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1875 bad_alias = true; 1876 } 1877 md->pvh_attrs |= PVF_WRITE; 1878 if (!bad_alias) 1879 md->pvh_attrs |= PVF_DIRTY; 1880 } else { 1881 /* 1882 * We have only read-only mappings. Let's see if there 1883 * are multiple colors in use or if we mapped a KMPAGE. 1884 * If the latter, we have a bad alias. If the former, 1885 * we need to remember that. 1886 */ 1887 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1888 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1889 if (md->pvh_attrs & PVF_KMPAGE) 1890 bad_alias = true; 1891 break; 1892 } 1893 } 1894 md->pvh_attrs &= ~PVF_WRITE; 1895 /* 1896 * No KMPAGE and we exited early, so we must have 1897 * multiple color mappings. 1898 */ 1899 if (!bad_alias && pv != NULL) 1900 md->pvh_attrs |= PVF_MULTCLR; 1901 } 1902 1903 /* If no conflicting colors, set everything back to cached */ 1904 if (!bad_alias) { 1905 #ifdef DEBUG 1906 if ((md->pvh_attrs & PVF_WRITE) 1907 || ro_mappings < 2) { 1908 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1909 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1910 } 1911 #endif 1912 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1913 md->pvh_attrs |= tst_mask | PVF_COLORED; 1914 /* 1915 * Restore DIRTY bit if page is modified 1916 */ 1917 if (md->pvh_attrs & PVF_DMOD) 1918 md->pvh_attrs |= PVF_DIRTY; 1919 PMAPCOUNT(vac_color_restore); 1920 } else { 1921 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1922 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1923 } 1924 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1925 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1926 } else if (!va) { 1927 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1928 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1929 || (md->pvh_attrs & PVF_DIRTY)); 1930 if (rw_mappings == 0) { 1931 md->pvh_attrs &= ~PVF_WRITE; 1932 if (ro_mappings == 1 1933 && (md->pvh_attrs & PVF_MULTCLR)) { 1934 /* 1935 * If this is the last readonly mapping 1936 * but it doesn't match the current color 1937 * for the page, change the current color 1938 * to match this last readonly mapping. 1939 */ 1940 pv = SLIST_FIRST(&md->pvh_list); 1941 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1942 & arm_cache_prefer_mask; 1943 if (tst_mask) { 1944 md->pvh_attrs ^= tst_mask; 1945 PMAPCOUNT(vac_color_change); 1946 } 1947 } 1948 } 1949 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1950 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1951 return; 1952 } else if (!pmap_is_page_colored_p(md)) { 1953 /* not colored so we just use its color */ 1954 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1955 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1956 PMAPCOUNT(vac_color_new); 1957 md->pvh_attrs &= PAGE_SIZE - 1; 1958 md->pvh_attrs |= PVF_COLORED 1959 | (va & arm_cache_prefer_mask) 1960 | (rw_mappings > 0 ? PVF_WRITE : 0); 1961 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1962 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1963 return; 1964 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1965 bad_alias = false; 1966 if (rw_mappings > 0) { 1967 /* 1968 * We now have writeable mappings and if we have 1969 * readonly mappings in more than once color, we have 1970 * an aliasing problem. Regardless mark the page as 1971 * writeable. 1972 */ 1973 if (md->pvh_attrs & PVF_MULTCLR) { 1974 if (ro_mappings < 2) { 1975 /* 1976 * If we only have less than two 1977 * read-only mappings, just flush the 1978 * non-primary colors from the cache. 1979 */ 1980 pmap_flush_page(md, pa, 1981 PMAP_FLUSH_SECONDARY); 1982 } else { 1983 bad_alias = true; 1984 } 1985 } 1986 md->pvh_attrs |= PVF_WRITE; 1987 } 1988 /* If no conflicting colors, set everything back to cached */ 1989 if (!bad_alias) { 1990 #ifdef DEBUG 1991 if (rw_mappings > 0 1992 || (md->pvh_attrs & PMAP_KMPAGE)) { 1993 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1994 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1995 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1996 } 1997 #endif 1998 if (SLIST_EMPTY(&md->pvh_list)) 1999 PMAPCOUNT(vac_color_reuse); 2000 else 2001 PMAPCOUNT(vac_color_ok); 2002 2003 /* matching color, just return */ 2004 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2005 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2006 return; 2007 } 2008 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2009 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2010 2011 /* color conflict. evict from cache. */ 2012 2013 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2014 md->pvh_attrs &= ~PVF_COLORED; 2015 md->pvh_attrs |= PVF_NC; 2016 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2017 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2018 PMAPCOUNT(vac_color_erase); 2019 } else if (rw_mappings == 0 2020 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2021 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2022 2023 /* 2024 * If the page has dirty cache lines, clean it. 2025 */ 2026 if (md->pvh_attrs & PVF_DIRTY) 2027 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2028 2029 /* 2030 * If this is the first remapping (we know that there are no 2031 * writeable mappings), then this is a simple color change. 2032 * Otherwise this is a seconary r/o mapping, which means 2033 * we don't have to do anything. 2034 */ 2035 if (ro_mappings == 1) { 2036 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2037 md->pvh_attrs &= PAGE_SIZE - 1; 2038 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2039 PMAPCOUNT(vac_color_change); 2040 } else { 2041 PMAPCOUNT(vac_color_blind); 2042 } 2043 md->pvh_attrs |= PVF_MULTCLR; 2044 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2045 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2046 return; 2047 } else { 2048 if (rw_mappings > 0) 2049 md->pvh_attrs |= PVF_WRITE; 2050 2051 /* color conflict. evict from cache. */ 2052 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2053 2054 /* the list can't be empty because this was a enter/modify */ 2055 pv = SLIST_FIRST(&md->pvh_list); 2056 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2057 KASSERT(pv); 2058 /* 2059 * If there's only one mapped page, change color to the 2060 * page's new color and return. Restore the DIRTY bit 2061 * that was erased by pmap_flush_page. 2062 */ 2063 if (SLIST_NEXT(pv, pv_link) == NULL) { 2064 md->pvh_attrs &= PAGE_SIZE - 1; 2065 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2066 if (md->pvh_attrs & PVF_DMOD) 2067 md->pvh_attrs |= PVF_DIRTY; 2068 PMAPCOUNT(vac_color_change); 2069 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2070 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2071 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2072 return; 2073 } 2074 } 2075 bad_alias = true; 2076 md->pvh_attrs &= ~PVF_COLORED; 2077 md->pvh_attrs |= PVF_NC; 2078 PMAPCOUNT(vac_color_erase); 2079 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2080 } 2081 2082 fixup: 2083 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2084 2085 /* 2086 * Turn cacheing on/off for all pages. 2087 */ 2088 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2089 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2090 KDASSERT(l2b != NULL); 2091 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2092 opte = *ptep; 2093 pte = opte & ~L2_S_CACHE_MASK; 2094 if (bad_alias) { 2095 pv->pv_flags |= PVF_NC; 2096 } else { 2097 pv->pv_flags &= ~PVF_NC; 2098 pte |= pte_l2_s_cache_mode; 2099 } 2100 2101 if (opte == pte) /* only update is there's a change */ 2102 continue; 2103 2104 if (l2pte_valid(pte)) { 2105 if (PV_BEEN_EXECD(pv->pv_flags)) { 2106 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2107 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2108 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2109 } 2110 } 2111 2112 *ptep = pte; 2113 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2114 } 2115 } 2116 #endif /* PMAP_CACHE_VIPT */ 2117 2118 2119 /* 2120 * Modify pte bits for all ptes corresponding to the given physical address. 2121 * We use `maskbits' rather than `clearbits' because we're always passing 2122 * constants and the latter would require an extra inversion at run-time. 2123 */ 2124 static void 2125 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2126 { 2127 struct l2_bucket *l2b; 2128 struct pv_entry *pv; 2129 pt_entry_t *ptep, npte, opte; 2130 pmap_t pm; 2131 vaddr_t va; 2132 u_int oflags; 2133 #ifdef PMAP_CACHE_VIPT 2134 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2135 bool need_syncicache = false; 2136 bool did_syncicache = false; 2137 bool need_vac_me_harder = false; 2138 #endif 2139 2140 NPDEBUG(PDB_BITS, 2141 printf("pmap_clearbit: md %p mask 0x%x\n", 2142 md, maskbits)); 2143 2144 PMAP_HEAD_TO_MAP_LOCK(); 2145 simple_lock(&md->pvh_slock); 2146 2147 #ifdef PMAP_CACHE_VIPT 2148 /* 2149 * If we might want to sync the I-cache and we've modified it, 2150 * then we know we definitely need to sync or discard it. 2151 */ 2152 if (want_syncicache) 2153 need_syncicache = md->pvh_attrs & PVF_MOD; 2154 #endif 2155 /* 2156 * Clear saved attributes (modify, reference) 2157 */ 2158 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2159 2160 if (SLIST_EMPTY(&md->pvh_list)) { 2161 #ifdef PMAP_CACHE_VIPT 2162 if (need_syncicache) { 2163 /* 2164 * No one has it mapped, so just discard it. The next 2165 * exec remapping will cause it to be synced. 2166 */ 2167 md->pvh_attrs &= ~PVF_EXEC; 2168 PMAPCOUNT(exec_discarded_clearbit); 2169 } 2170 #endif 2171 simple_unlock(&md->pvh_slock); 2172 PMAP_HEAD_TO_MAP_UNLOCK(); 2173 return; 2174 } 2175 2176 /* 2177 * Loop over all current mappings setting/clearing as appropos 2178 */ 2179 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2180 va = pv->pv_va; 2181 pm = pv->pv_pmap; 2182 oflags = pv->pv_flags; 2183 /* 2184 * Kernel entries are unmanaged and as such not to be changed. 2185 */ 2186 if (oflags & PVF_KENTRY) 2187 continue; 2188 pv->pv_flags &= ~maskbits; 2189 2190 pmap_acquire_pmap_lock(pm); 2191 2192 l2b = pmap_get_l2_bucket(pm, va); 2193 KDASSERT(l2b != NULL); 2194 2195 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2196 npte = opte = *ptep; 2197 2198 NPDEBUG(PDB_BITS, 2199 printf( 2200 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2201 pv, pv->pv_pmap, pv->pv_va, oflags)); 2202 2203 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2204 #ifdef PMAP_CACHE_VIVT 2205 if ((pv->pv_flags & PVF_NC)) { 2206 /* 2207 * Entry is not cacheable: 2208 * 2209 * Don't turn caching on again if this is a 2210 * modified emulation. This would be 2211 * inconsitent with the settings created by 2212 * pmap_vac_me_harder(). Otherwise, it's safe 2213 * to re-enable cacheing. 2214 * 2215 * There's no need to call pmap_vac_me_harder() 2216 * here: all pages are losing their write 2217 * permission. 2218 */ 2219 if (maskbits & PVF_WRITE) { 2220 npte |= pte_l2_s_cache_mode; 2221 pv->pv_flags &= ~PVF_NC; 2222 } 2223 } else 2224 if (l2pte_writable_p(opte)) { 2225 /* 2226 * Entry is writable/cacheable: check if pmap 2227 * is current if it is flush it, otherwise it 2228 * won't be in the cache 2229 */ 2230 if (PV_BEEN_EXECD(oflags)) 2231 pmap_idcache_wbinv_range(pm, pv->pv_va, 2232 PAGE_SIZE); 2233 else 2234 if (PV_BEEN_REFD(oflags)) 2235 pmap_dcache_wb_range(pm, pv->pv_va, 2236 PAGE_SIZE, 2237 (maskbits & PVF_REF) != 0, false); 2238 } 2239 #endif 2240 2241 /* make the pte read only */ 2242 npte = l2pte_set_readonly(npte); 2243 2244 if (maskbits & oflags & PVF_WRITE) { 2245 /* 2246 * Keep alias accounting up to date 2247 */ 2248 if (pv->pv_pmap == pmap_kernel()) { 2249 md->krw_mappings--; 2250 md->kro_mappings++; 2251 } else { 2252 md->urw_mappings--; 2253 md->uro_mappings++; 2254 } 2255 #ifdef PMAP_CACHE_VIPT 2256 if (md->urw_mappings + md->krw_mappings == 0) 2257 md->pvh_attrs &= ~PVF_WRITE; 2258 if (want_syncicache) 2259 need_syncicache = true; 2260 need_vac_me_harder = true; 2261 #endif 2262 } 2263 } 2264 2265 if (maskbits & PVF_REF) { 2266 if ((pv->pv_flags & PVF_NC) == 0 && 2267 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2268 l2pte_valid(npte)) { 2269 #ifdef PMAP_CACHE_VIVT 2270 /* 2271 * Check npte here; we may have already 2272 * done the wbinv above, and the validity 2273 * of the PTE is the same for opte and 2274 * npte. 2275 */ 2276 /* XXXJRT need idcache_inv_range */ 2277 if (PV_BEEN_EXECD(oflags)) 2278 pmap_idcache_wbinv_range(pm, 2279 pv->pv_va, PAGE_SIZE); 2280 else 2281 if (PV_BEEN_REFD(oflags)) 2282 pmap_dcache_wb_range(pm, 2283 pv->pv_va, PAGE_SIZE, 2284 true, true); 2285 #endif 2286 } 2287 2288 /* 2289 * Make the PTE invalid so that we will take a 2290 * page fault the next time the mapping is 2291 * referenced. 2292 */ 2293 npte &= ~L2_TYPE_MASK; 2294 npte |= L2_TYPE_INV; 2295 } 2296 2297 if (npte != opte) { 2298 *ptep = npte; 2299 PTE_SYNC(ptep); 2300 /* Flush the TLB entry if a current pmap. */ 2301 if (PV_BEEN_EXECD(oflags)) 2302 pmap_tlb_flushID_SE(pm, pv->pv_va); 2303 else 2304 if (PV_BEEN_REFD(oflags)) 2305 pmap_tlb_flushD_SE(pm, pv->pv_va); 2306 } 2307 2308 pmap_release_pmap_lock(pm); 2309 2310 NPDEBUG(PDB_BITS, 2311 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2312 pm, va, opte, npte)); 2313 } 2314 2315 #ifdef PMAP_CACHE_VIPT 2316 /* 2317 * If we need to sync the I-cache and we haven't done it yet, do it. 2318 */ 2319 if (need_syncicache && !did_syncicache) { 2320 pmap_syncicache_page(md, pa); 2321 PMAPCOUNT(exec_synced_clearbit); 2322 } 2323 /* 2324 * If we are changing this to read-only, we need to call vac_me_harder 2325 * so we can change all the read-only pages to cacheable. We pretend 2326 * this as a page deletion. 2327 */ 2328 if (need_vac_me_harder) { 2329 if (md->pvh_attrs & PVF_NC) 2330 pmap_vac_me_harder(md, pa, NULL, 0); 2331 } 2332 #endif 2333 2334 simple_unlock(&md->pvh_slock); 2335 PMAP_HEAD_TO_MAP_UNLOCK(); 2336 } 2337 2338 /* 2339 * pmap_clean_page() 2340 * 2341 * This is a local function used to work out the best strategy to clean 2342 * a single page referenced by its entry in the PV table. It's used by 2343 * pmap_copy_page, pmap_zero page and maybe some others later on. 2344 * 2345 * Its policy is effectively: 2346 * o If there are no mappings, we don't bother doing anything with the cache. 2347 * o If there is one mapping, we clean just that page. 2348 * o If there are multiple mappings, we clean the entire cache. 2349 * 2350 * So that some functions can be further optimised, it returns 0 if it didn't 2351 * clean the entire cache, or 1 if it did. 2352 * 2353 * XXX One bug in this routine is that if the pv_entry has a single page 2354 * mapped at 0x00000000 a whole cache clean will be performed rather than 2355 * just the 1 page. Since this should not occur in everyday use and if it does 2356 * it will just result in not the most efficient clean for the page. 2357 */ 2358 #ifdef PMAP_CACHE_VIVT 2359 static int 2360 pmap_clean_page(struct pv_entry *pv, bool is_src) 2361 { 2362 pmap_t pm_to_clean = NULL; 2363 struct pv_entry *npv; 2364 u_int cache_needs_cleaning = 0; 2365 u_int flags = 0; 2366 vaddr_t page_to_clean = 0; 2367 2368 if (pv == NULL) { 2369 /* nothing mapped in so nothing to flush */ 2370 return (0); 2371 } 2372 2373 /* 2374 * Since we flush the cache each time we change to a different 2375 * user vmspace, we only need to flush the page if it is in the 2376 * current pmap. 2377 */ 2378 2379 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2380 if (pmap_is_current(npv->pv_pmap)) { 2381 flags |= npv->pv_flags; 2382 /* 2383 * The page is mapped non-cacheable in 2384 * this map. No need to flush the cache. 2385 */ 2386 if (npv->pv_flags & PVF_NC) { 2387 #ifdef DIAGNOSTIC 2388 if (cache_needs_cleaning) 2389 panic("pmap_clean_page: " 2390 "cache inconsistency"); 2391 #endif 2392 break; 2393 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2394 continue; 2395 if (cache_needs_cleaning) { 2396 page_to_clean = 0; 2397 break; 2398 } else { 2399 page_to_clean = npv->pv_va; 2400 pm_to_clean = npv->pv_pmap; 2401 } 2402 cache_needs_cleaning = 1; 2403 } 2404 } 2405 2406 if (page_to_clean) { 2407 if (PV_BEEN_EXECD(flags)) 2408 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2409 PAGE_SIZE); 2410 else 2411 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2412 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2413 } else if (cache_needs_cleaning) { 2414 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2415 2416 if (PV_BEEN_EXECD(flags)) 2417 pmap_idcache_wbinv_all(pm); 2418 else 2419 pmap_dcache_wbinv_all(pm); 2420 return (1); 2421 } 2422 return (0); 2423 } 2424 #endif 2425 2426 #ifdef PMAP_CACHE_VIPT 2427 /* 2428 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2429 * right cache alias to make sure we flush the right stuff. 2430 */ 2431 void 2432 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2433 { 2434 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2435 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2436 2437 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2438 md, md->pvh_attrs)); 2439 /* 2440 * No need to clean the page if it's non-cached. 2441 */ 2442 if (md->pvh_attrs & PVF_NC) 2443 return; 2444 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2445 2446 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2447 /* 2448 * Set up a PTE with the right coloring to flush existing cache lines. 2449 */ 2450 *ptep = L2_S_PROTO | 2451 pa 2452 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2453 | pte_l2_s_cache_mode; 2454 PTE_SYNC(ptep); 2455 2456 /* 2457 * Flush it. 2458 */ 2459 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2460 /* 2461 * Unmap the page. 2462 */ 2463 *ptep = 0; 2464 PTE_SYNC(ptep); 2465 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2466 2467 md->pvh_attrs |= PVF_EXEC; 2468 PMAPCOUNT(exec_synced); 2469 } 2470 2471 void 2472 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2473 { 2474 vsize_t va_offset, end_va; 2475 void (*cf)(vaddr_t, vsize_t); 2476 2477 if (arm_cache_prefer_mask == 0) 2478 return; 2479 2480 switch (flush) { 2481 case PMAP_FLUSH_PRIMARY: 2482 if (md->pvh_attrs & PVF_MULTCLR) { 2483 va_offset = 0; 2484 end_va = arm_cache_prefer_mask; 2485 md->pvh_attrs &= ~PVF_MULTCLR; 2486 PMAPCOUNT(vac_flush_lots); 2487 } else { 2488 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2489 end_va = va_offset; 2490 PMAPCOUNT(vac_flush_one); 2491 } 2492 /* 2493 * Mark that the page is no longer dirty. 2494 */ 2495 md->pvh_attrs &= ~PVF_DIRTY; 2496 cf = cpufuncs.cf_idcache_wbinv_range; 2497 break; 2498 case PMAP_FLUSH_SECONDARY: 2499 va_offset = 0; 2500 end_va = arm_cache_prefer_mask; 2501 cf = cpufuncs.cf_idcache_wbinv_range; 2502 md->pvh_attrs &= ~PVF_MULTCLR; 2503 PMAPCOUNT(vac_flush_lots); 2504 break; 2505 case PMAP_CLEAN_PRIMARY: 2506 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2507 end_va = va_offset; 2508 cf = cpufuncs.cf_dcache_wb_range; 2509 /* 2510 * Mark that the page is no longer dirty. 2511 */ 2512 if ((md->pvh_attrs & PVF_DMOD) == 0) 2513 md->pvh_attrs &= ~PVF_DIRTY; 2514 PMAPCOUNT(vac_clean_one); 2515 break; 2516 default: 2517 return; 2518 } 2519 2520 KASSERT(!(md->pvh_attrs & PVF_NC)); 2521 2522 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2523 md, md->pvh_attrs)); 2524 2525 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2526 const size_t pte_offset = va_offset >> PGSHIFT; 2527 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2528 const pt_entry_t oldpte = *ptep; 2529 2530 if (flush == PMAP_FLUSH_SECONDARY 2531 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2532 continue; 2533 2534 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2535 /* 2536 * Set up a PTE with the right coloring to flush 2537 * existing cache entries. 2538 */ 2539 *ptep = L2_S_PROTO 2540 | pa 2541 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2542 | pte_l2_s_cache_mode; 2543 PTE_SYNC(ptep); 2544 2545 /* 2546 * Flush it. 2547 */ 2548 (*cf)(cdstp + va_offset, PAGE_SIZE); 2549 2550 /* 2551 * Restore the page table entry since we might have interrupted 2552 * pmap_zero_page or pmap_copy_page which was already using 2553 * this pte. 2554 */ 2555 *ptep = oldpte; 2556 PTE_SYNC(ptep); 2557 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2558 } 2559 } 2560 #endif /* PMAP_CACHE_VIPT */ 2561 2562 /* 2563 * Routine: pmap_page_remove 2564 * Function: 2565 * Removes this physical page from 2566 * all physical maps in which it resides. 2567 * Reflects back modify bits to the pager. 2568 */ 2569 static void 2570 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2571 { 2572 struct l2_bucket *l2b; 2573 struct pv_entry *pv, *npv, **pvp; 2574 pmap_t pm; 2575 pt_entry_t *ptep; 2576 bool flush; 2577 u_int flags; 2578 2579 NPDEBUG(PDB_FOLLOW, 2580 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, 2581 pa)); 2582 2583 PMAP_HEAD_TO_MAP_LOCK(); 2584 simple_lock(&md->pvh_slock); 2585 2586 pv = SLIST_FIRST(&md->pvh_list); 2587 if (pv == NULL) { 2588 #ifdef PMAP_CACHE_VIPT 2589 /* 2590 * We *know* the page contents are about to be replaced. 2591 * Discard the exec contents 2592 */ 2593 if (PV_IS_EXEC_P(md->pvh_attrs)) 2594 PMAPCOUNT(exec_discarded_page_protect); 2595 md->pvh_attrs &= ~PVF_EXEC; 2596 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2597 #endif 2598 simple_unlock(&md->pvh_slock); 2599 PMAP_HEAD_TO_MAP_UNLOCK(); 2600 return; 2601 } 2602 #ifdef PMAP_CACHE_VIPT 2603 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2604 #endif 2605 2606 /* 2607 * Clear alias counts 2608 */ 2609 #ifdef PMAP_CACHE_VIVT 2610 md->k_mappings = 0; 2611 #endif 2612 md->urw_mappings = md->uro_mappings = 0; 2613 2614 flush = false; 2615 flags = 0; 2616 2617 #ifdef PMAP_CACHE_VIVT 2618 pmap_clean_page(pv, false); 2619 #endif 2620 2621 pvp = &SLIST_FIRST(&md->pvh_list); 2622 while (pv) { 2623 pm = pv->pv_pmap; 2624 npv = SLIST_NEXT(pv, pv_link); 2625 if (flush == false && pmap_is_current(pm)) 2626 flush = true; 2627 2628 if (pm == pmap_kernel()) { 2629 #ifdef PMAP_CACHE_VIPT 2630 /* 2631 * If this was unmanaged mapping, it must be preserved. 2632 * Move it back on the list and advance the end-of-list 2633 * pointer. 2634 */ 2635 if (pv->pv_flags & PVF_KENTRY) { 2636 *pvp = pv; 2637 pvp = &SLIST_NEXT(pv, pv_link); 2638 pv = npv; 2639 continue; 2640 } 2641 if (pv->pv_flags & PVF_WRITE) 2642 md->krw_mappings--; 2643 else 2644 md->kro_mappings--; 2645 #endif 2646 PMAPCOUNT(kernel_unmappings); 2647 } 2648 PMAPCOUNT(unmappings); 2649 2650 pmap_acquire_pmap_lock(pm); 2651 2652 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2653 KDASSERT(l2b != NULL); 2654 2655 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2656 2657 /* 2658 * Update statistics 2659 */ 2660 --pm->pm_stats.resident_count; 2661 2662 /* Wired bit */ 2663 if (pv->pv_flags & PVF_WIRED) 2664 --pm->pm_stats.wired_count; 2665 2666 flags |= pv->pv_flags; 2667 2668 /* 2669 * Invalidate the PTEs. 2670 */ 2671 *ptep = 0; 2672 PTE_SYNC_CURRENT(pm, ptep); 2673 pmap_free_l2_bucket(pm, l2b, 1); 2674 2675 pool_put(&pmap_pv_pool, pv); 2676 pv = npv; 2677 /* 2678 * if we reach the end of the list and there are still 2679 * mappings, they might be able to be cached now. 2680 */ 2681 if (pv == NULL) { 2682 *pvp = NULL; 2683 if (!SLIST_EMPTY(&md->pvh_list)) 2684 pmap_vac_me_harder(md, pa, pm, 0); 2685 } 2686 pmap_release_pmap_lock(pm); 2687 } 2688 #ifdef PMAP_CACHE_VIPT 2689 /* 2690 * Its EXEC cache is now gone. 2691 */ 2692 if (PV_IS_EXEC_P(md->pvh_attrs)) 2693 PMAPCOUNT(exec_discarded_page_protect); 2694 md->pvh_attrs &= ~PVF_EXEC; 2695 KASSERT(md->urw_mappings == 0); 2696 KASSERT(md->uro_mappings == 0); 2697 if (md->krw_mappings == 0) 2698 md->pvh_attrs &= ~PVF_WRITE; 2699 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2700 #endif 2701 simple_unlock(&md->pvh_slock); 2702 PMAP_HEAD_TO_MAP_UNLOCK(); 2703 2704 if (flush) { 2705 /* 2706 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2707 * would need a subsequent call to pmap_update() to ensure 2708 * curpm->pm_cstate.cs_all is reset. Our callers are not 2709 * required to do that (see pmap(9)), so we can't modify 2710 * the current pmap's state. 2711 */ 2712 if (PV_BEEN_EXECD(flags)) 2713 cpu_tlb_flushID(); 2714 else 2715 cpu_tlb_flushD(); 2716 } 2717 cpu_cpwait(); 2718 } 2719 2720 /* 2721 * pmap_t pmap_create(void) 2722 * 2723 * Create a new pmap structure from scratch. 2724 */ 2725 pmap_t 2726 pmap_create(void) 2727 { 2728 pmap_t pm; 2729 2730 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2731 2732 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2733 pm->pm_stats.wired_count = 0; 2734 pm->pm_stats.resident_count = 1; 2735 pm->pm_cstate.cs_all = 0; 2736 pmap_alloc_l1(pm); 2737 2738 /* 2739 * Note: The pool cache ensures that the pm_l2[] array is already 2740 * initialised to zero. 2741 */ 2742 2743 pmap_pinit(pm); 2744 2745 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2746 2747 return (pm); 2748 } 2749 2750 /* 2751 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2752 * u_int flags) 2753 * 2754 * Insert the given physical page (p) at 2755 * the specified virtual address (v) in the 2756 * target physical map with the protection requested. 2757 * 2758 * NB: This is the only routine which MAY NOT lazy-evaluate 2759 * or lose information. That is, this routine must actually 2760 * insert this page into the given map NOW. 2761 */ 2762 int 2763 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2764 { 2765 struct l2_bucket *l2b; 2766 struct vm_page *pg, *opg; 2767 struct pv_entry *pv; 2768 pt_entry_t *ptep, npte, opte; 2769 u_int nflags; 2770 u_int oflags; 2771 2772 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2773 2774 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2775 KDASSERT(((va | pa) & PGOFSET) == 0); 2776 2777 /* 2778 * Get a pointer to the page. Later on in this function, we 2779 * test for a managed page by checking pg != NULL. 2780 */ 2781 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2782 2783 nflags = 0; 2784 if (prot & VM_PROT_WRITE) 2785 nflags |= PVF_WRITE; 2786 if (prot & VM_PROT_EXECUTE) 2787 nflags |= PVF_EXEC; 2788 if (flags & PMAP_WIRED) 2789 nflags |= PVF_WIRED; 2790 2791 PMAP_MAP_TO_HEAD_LOCK(); 2792 pmap_acquire_pmap_lock(pm); 2793 2794 /* 2795 * Fetch the L2 bucket which maps this page, allocating one if 2796 * necessary for user pmaps. 2797 */ 2798 if (pm == pmap_kernel()) 2799 l2b = pmap_get_l2_bucket(pm, va); 2800 else 2801 l2b = pmap_alloc_l2_bucket(pm, va); 2802 if (l2b == NULL) { 2803 if (flags & PMAP_CANFAIL) { 2804 pmap_release_pmap_lock(pm); 2805 PMAP_MAP_TO_HEAD_UNLOCK(); 2806 return (ENOMEM); 2807 } 2808 panic("pmap_enter: failed to allocate L2 bucket"); 2809 } 2810 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2811 opte = *ptep; 2812 npte = pa; 2813 oflags = 0; 2814 2815 if (opte) { 2816 /* 2817 * There is already a mapping at this address. 2818 * If the physical address is different, lookup the 2819 * vm_page. 2820 */ 2821 if (l2pte_pa(opte) != pa) 2822 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2823 else 2824 opg = pg; 2825 } else 2826 opg = NULL; 2827 2828 if (pg) { 2829 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2830 2831 /* 2832 * This is to be a managed mapping. 2833 */ 2834 if ((flags & VM_PROT_ALL) || 2835 (md->pvh_attrs & PVF_REF)) { 2836 /* 2837 * - The access type indicates that we don't need 2838 * to do referenced emulation. 2839 * OR 2840 * - The physical page has already been referenced 2841 * so no need to re-do referenced emulation here. 2842 */ 2843 npte |= l2pte_set_readonly(L2_S_PROTO); 2844 2845 nflags |= PVF_REF; 2846 2847 if ((prot & VM_PROT_WRITE) != 0 && 2848 ((flags & VM_PROT_WRITE) != 0 || 2849 (md->pvh_attrs & PVF_MOD) != 0)) { 2850 /* 2851 * This is a writable mapping, and the 2852 * page's mod state indicates it has 2853 * already been modified. Make it 2854 * writable from the outset. 2855 */ 2856 npte = l2pte_set_writable(npte); 2857 nflags |= PVF_MOD; 2858 } 2859 } else { 2860 /* 2861 * Need to do page referenced emulation. 2862 */ 2863 npte |= L2_TYPE_INV; 2864 } 2865 2866 npte |= pte_l2_s_cache_mode; 2867 2868 if (pg == opg) { 2869 /* 2870 * We're changing the attrs of an existing mapping. 2871 */ 2872 simple_lock(&md->pvh_slock); 2873 oflags = pmap_modify_pv(md, pa, pm, va, 2874 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2875 PVF_MOD | PVF_REF, nflags); 2876 simple_unlock(&md->pvh_slock); 2877 2878 #ifdef PMAP_CACHE_VIVT 2879 /* 2880 * We may need to flush the cache if we're 2881 * doing rw-ro... 2882 */ 2883 if (pm->pm_cstate.cs_cache_d && 2884 (oflags & PVF_NC) == 0 && 2885 l2pte_writable_p(opte) && 2886 (prot & VM_PROT_WRITE) == 0) 2887 cpu_dcache_wb_range(va, PAGE_SIZE); 2888 #endif 2889 } else { 2890 /* 2891 * New mapping, or changing the backing page 2892 * of an existing mapping. 2893 */ 2894 if (opg) { 2895 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2896 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2897 2898 /* 2899 * Replacing an existing mapping with a new one. 2900 * It is part of our managed memory so we 2901 * must remove it from the PV list 2902 */ 2903 simple_lock(&omd->pvh_slock); 2904 pv = pmap_remove_pv(omd, opa, pm, va); 2905 pmap_vac_me_harder(omd, opa, pm, 0); 2906 simple_unlock(&omd->pvh_slock); 2907 oflags = pv->pv_flags; 2908 2909 #ifdef PMAP_CACHE_VIVT 2910 /* 2911 * If the old mapping was valid (ref/mod 2912 * emulation creates 'invalid' mappings 2913 * initially) then make sure to frob 2914 * the cache. 2915 */ 2916 if ((oflags & PVF_NC) == 0 && 2917 l2pte_valid(opte)) { 2918 if (PV_BEEN_EXECD(oflags)) { 2919 pmap_idcache_wbinv_range(pm, va, 2920 PAGE_SIZE); 2921 } else 2922 if (PV_BEEN_REFD(oflags)) { 2923 pmap_dcache_wb_range(pm, va, 2924 PAGE_SIZE, true, 2925 (oflags & PVF_WRITE) == 0); 2926 } 2927 } 2928 #endif 2929 } else 2930 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2931 if ((flags & PMAP_CANFAIL) == 0) 2932 panic("pmap_enter: no pv entries"); 2933 2934 if (pm != pmap_kernel()) 2935 pmap_free_l2_bucket(pm, l2b, 0); 2936 pmap_release_pmap_lock(pm); 2937 PMAP_MAP_TO_HEAD_UNLOCK(); 2938 NPDEBUG(PDB_ENTER, 2939 printf("pmap_enter: ENOMEM\n")); 2940 return (ENOMEM); 2941 } 2942 2943 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2944 } 2945 } else { 2946 /* 2947 * We're mapping an unmanaged page. 2948 * These are always readable, and possibly writable, from 2949 * the get go as we don't need to track ref/mod status. 2950 */ 2951 npte |= l2pte_set_readonly(L2_S_PROTO); 2952 if (prot & VM_PROT_WRITE) 2953 npte = l2pte_set_writable(npte); 2954 2955 /* 2956 * Make sure the vector table is mapped cacheable 2957 */ 2958 if (pm != pmap_kernel() && va == vector_page) 2959 npte |= pte_l2_s_cache_mode; 2960 2961 if (opg) { 2962 /* 2963 * Looks like there's an existing 'managed' mapping 2964 * at this address. 2965 */ 2966 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2967 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2968 2969 simple_lock(&omd->pvh_slock); 2970 pv = pmap_remove_pv(omd, opa, pm, va); 2971 pmap_vac_me_harder(omd, opa, pm, 0); 2972 simple_unlock(&omd->pvh_slock); 2973 oflags = pv->pv_flags; 2974 2975 #ifdef PMAP_CACHE_VIVT 2976 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2977 if (PV_BEEN_EXECD(oflags)) 2978 pmap_idcache_wbinv_range(pm, va, 2979 PAGE_SIZE); 2980 else 2981 if (PV_BEEN_REFD(oflags)) 2982 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2983 true, (oflags & PVF_WRITE) == 0); 2984 } 2985 #endif 2986 pool_put(&pmap_pv_pool, pv); 2987 } 2988 } 2989 2990 /* 2991 * Make sure userland mappings get the right permissions 2992 */ 2993 if (pm != pmap_kernel() && va != vector_page) 2994 npte |= L2_S_PROT_U; 2995 2996 /* 2997 * Keep the stats up to date 2998 */ 2999 if (opte == 0) { 3000 l2b->l2b_occupancy++; 3001 pm->pm_stats.resident_count++; 3002 } 3003 3004 NPDEBUG(PDB_ENTER, 3005 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3006 3007 /* 3008 * If this is just a wiring change, the two PTEs will be 3009 * identical, so there's no need to update the page table. 3010 */ 3011 if (npte != opte) { 3012 bool is_cached = pmap_is_cached(pm); 3013 3014 *ptep = npte; 3015 if (is_cached) { 3016 /* 3017 * We only need to frob the cache/tlb if this pmap 3018 * is current 3019 */ 3020 PTE_SYNC(ptep); 3021 if (va != vector_page && l2pte_valid(npte)) { 3022 /* 3023 * This mapping is likely to be accessed as 3024 * soon as we return to userland. Fix up the 3025 * L1 entry to avoid taking another 3026 * page/domain fault. 3027 */ 3028 pd_entry_t *pl1pd, l1pd; 3029 3030 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3031 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3032 L1_C_PROTO; 3033 if (*pl1pd != l1pd) { 3034 *pl1pd = l1pd; 3035 PTE_SYNC(pl1pd); 3036 } 3037 } 3038 } 3039 3040 if (PV_BEEN_EXECD(oflags)) 3041 pmap_tlb_flushID_SE(pm, va); 3042 else 3043 if (PV_BEEN_REFD(oflags)) 3044 pmap_tlb_flushD_SE(pm, va); 3045 3046 NPDEBUG(PDB_ENTER, 3047 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3048 is_cached, pm->pm_cstate.cs_all)); 3049 3050 if (pg != NULL) { 3051 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3052 3053 simple_lock(&md->pvh_slock); 3054 pmap_vac_me_harder(md, pa, pm, va); 3055 simple_unlock(&md->pvh_slock); 3056 } 3057 } 3058 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3059 if (pg) { 3060 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3061 3062 simple_lock(&md->pvh_slock); 3063 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3064 KASSERT(((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0)); 3065 simple_unlock(&md->pvh_slock); 3066 } 3067 #endif 3068 3069 pmap_release_pmap_lock(pm); 3070 PMAP_MAP_TO_HEAD_UNLOCK(); 3071 3072 return (0); 3073 } 3074 3075 /* 3076 * pmap_remove() 3077 * 3078 * pmap_remove is responsible for nuking a number of mappings for a range 3079 * of virtual address space in the current pmap. To do this efficiently 3080 * is interesting, because in a number of cases a wide virtual address 3081 * range may be supplied that contains few actual mappings. So, the 3082 * optimisations are: 3083 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3084 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3085 * maybe do just a partial cache clean. This path of execution is 3086 * complicated by the fact that the cache must be flushed _before_ 3087 * the PTE is nuked, being a VAC :-) 3088 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3089 * all invalidations until pmap_update(), since pmap_remove_all() has 3090 * already flushed the cache. 3091 * 4. Maybe later fast-case a single page, but I don't think this is 3092 * going to make _that_ much difference overall. 3093 */ 3094 3095 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3096 3097 void 3098 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3099 { 3100 struct l2_bucket *l2b; 3101 vaddr_t next_bucket; 3102 pt_entry_t *ptep; 3103 u_int cleanlist_idx, total, cnt; 3104 struct { 3105 vaddr_t va; 3106 pt_entry_t *ptep; 3107 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3108 u_int mappings, is_exec, is_refd; 3109 3110 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3111 "eva=%08lx\n", pm, sva, eva)); 3112 3113 /* 3114 * we lock in the pmap => pv_head direction 3115 */ 3116 PMAP_MAP_TO_HEAD_LOCK(); 3117 pmap_acquire_pmap_lock(pm); 3118 3119 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3120 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3121 if (pm->pm_cstate.cs_tlb == 0) 3122 pm->pm_remove_all = true; 3123 } else 3124 cleanlist_idx = 0; 3125 3126 total = 0; 3127 3128 while (sva < eva) { 3129 /* 3130 * Do one L2 bucket's worth at a time. 3131 */ 3132 next_bucket = L2_NEXT_BUCKET(sva); 3133 if (next_bucket > eva) 3134 next_bucket = eva; 3135 3136 l2b = pmap_get_l2_bucket(pm, sva); 3137 if (l2b == NULL) { 3138 sva = next_bucket; 3139 continue; 3140 } 3141 3142 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3143 3144 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3145 struct vm_page *pg; 3146 pt_entry_t pte; 3147 paddr_t pa; 3148 3149 pte = *ptep; 3150 3151 if (pte == 0) { 3152 /* Nothing here, move along */ 3153 continue; 3154 } 3155 3156 pa = l2pte_pa(pte); 3157 is_exec = 0; 3158 is_refd = 1; 3159 3160 /* 3161 * Update flags. In a number of circumstances, 3162 * we could cluster a lot of these and do a 3163 * number of sequential pages in one go. 3164 */ 3165 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3166 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3167 struct pv_entry *pv; 3168 3169 simple_lock(&md->pvh_slock); 3170 pv = pmap_remove_pv(md, pa, pm, sva); 3171 pmap_vac_me_harder(md, pa, pm, 0); 3172 simple_unlock(&md->pvh_slock); 3173 if (pv != NULL) { 3174 if (pm->pm_remove_all == false) { 3175 is_exec = 3176 PV_BEEN_EXECD(pv->pv_flags); 3177 is_refd = 3178 PV_BEEN_REFD(pv->pv_flags); 3179 } 3180 pool_put(&pmap_pv_pool, pv); 3181 } 3182 } 3183 mappings++; 3184 3185 if (!l2pte_valid(pte)) { 3186 /* 3187 * Ref/Mod emulation is still active for this 3188 * mapping, therefore it is has not yet been 3189 * accessed. No need to frob the cache/tlb. 3190 */ 3191 *ptep = 0; 3192 PTE_SYNC_CURRENT(pm, ptep); 3193 continue; 3194 } 3195 3196 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3197 /* Add to the clean list. */ 3198 cleanlist[cleanlist_idx].ptep = ptep; 3199 cleanlist[cleanlist_idx].va = 3200 sva | (is_exec & 1); 3201 cleanlist_idx++; 3202 } else 3203 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3204 /* Nuke everything if needed. */ 3205 #ifdef PMAP_CACHE_VIVT 3206 pmap_idcache_wbinv_all(pm); 3207 #endif 3208 pmap_tlb_flushID(pm); 3209 3210 /* 3211 * Roll back the previous PTE list, 3212 * and zero out the current PTE. 3213 */ 3214 for (cnt = 0; 3215 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3216 *cleanlist[cnt].ptep = 0; 3217 PTE_SYNC(cleanlist[cnt].ptep); 3218 } 3219 *ptep = 0; 3220 PTE_SYNC(ptep); 3221 cleanlist_idx++; 3222 pm->pm_remove_all = true; 3223 } else { 3224 *ptep = 0; 3225 PTE_SYNC(ptep); 3226 if (pm->pm_remove_all == false) { 3227 if (is_exec) 3228 pmap_tlb_flushID_SE(pm, sva); 3229 else 3230 if (is_refd) 3231 pmap_tlb_flushD_SE(pm, sva); 3232 } 3233 } 3234 } 3235 3236 /* 3237 * Deal with any left overs 3238 */ 3239 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3240 total += cleanlist_idx; 3241 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3242 if (pm->pm_cstate.cs_all != 0) { 3243 vaddr_t clva = cleanlist[cnt].va & ~1; 3244 if (cleanlist[cnt].va & 1) { 3245 #ifdef PMAP_CACHE_VIVT 3246 pmap_idcache_wbinv_range(pm, 3247 clva, PAGE_SIZE); 3248 #endif 3249 pmap_tlb_flushID_SE(pm, clva); 3250 } else { 3251 #ifdef PMAP_CACHE_VIVT 3252 pmap_dcache_wb_range(pm, 3253 clva, PAGE_SIZE, true, 3254 false); 3255 #endif 3256 pmap_tlb_flushD_SE(pm, clva); 3257 } 3258 } 3259 *cleanlist[cnt].ptep = 0; 3260 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3261 } 3262 3263 /* 3264 * If it looks like we're removing a whole bunch 3265 * of mappings, it's faster to just write-back 3266 * the whole cache now and defer TLB flushes until 3267 * pmap_update() is called. 3268 */ 3269 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3270 cleanlist_idx = 0; 3271 else { 3272 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3273 #ifdef PMAP_CACHE_VIVT 3274 pmap_idcache_wbinv_all(pm); 3275 #endif 3276 pm->pm_remove_all = true; 3277 } 3278 } 3279 3280 pmap_free_l2_bucket(pm, l2b, mappings); 3281 pm->pm_stats.resident_count -= mappings; 3282 } 3283 3284 pmap_release_pmap_lock(pm); 3285 PMAP_MAP_TO_HEAD_UNLOCK(); 3286 } 3287 3288 #ifdef PMAP_CACHE_VIPT 3289 static struct pv_entry * 3290 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3291 { 3292 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3293 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3294 struct pv_entry *pv; 3295 3296 simple_lock(&md->pvh_slock); 3297 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3298 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3299 3300 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3301 KASSERT(pv); 3302 KASSERT(pv->pv_flags & PVF_KENTRY); 3303 3304 /* 3305 * If we are removing a writeable mapping to a cached exec page, 3306 * if it's the last mapping then clear it execness other sync 3307 * the page to the icache. 3308 */ 3309 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3310 && (pv->pv_flags & PVF_WRITE) != 0) { 3311 if (SLIST_EMPTY(&md->pvh_list)) { 3312 md->pvh_attrs &= ~PVF_EXEC; 3313 PMAPCOUNT(exec_discarded_kremove); 3314 } else { 3315 pmap_syncicache_page(md, pa); 3316 PMAPCOUNT(exec_synced_kremove); 3317 } 3318 } 3319 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3320 simple_unlock(&md->pvh_slock); 3321 3322 return pv; 3323 } 3324 #endif /* PMAP_CACHE_VIPT */ 3325 3326 /* 3327 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3328 * 3329 * We assume there is already sufficient KVM space available 3330 * to do this, as we can't allocate L2 descriptor tables/metadata 3331 * from here. 3332 */ 3333 void 3334 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3335 { 3336 struct l2_bucket *l2b; 3337 pt_entry_t *ptep, opte; 3338 #ifdef PMAP_CACHE_VIVT 3339 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3340 #endif 3341 #ifdef PMAP_CACHE_VIPT 3342 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3343 struct vm_page *opg; 3344 struct pv_entry *pv = NULL; 3345 #endif 3346 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3347 3348 NPDEBUG(PDB_KENTER, 3349 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3350 va, pa, prot)); 3351 3352 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3353 KDASSERT(l2b != NULL); 3354 3355 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3356 opte = *ptep; 3357 3358 if (opte == 0) { 3359 PMAPCOUNT(kenter_mappings); 3360 l2b->l2b_occupancy++; 3361 } else { 3362 PMAPCOUNT(kenter_remappings); 3363 #ifdef PMAP_CACHE_VIPT 3364 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3365 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3366 if (opg) { 3367 KASSERT(opg != pg); 3368 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3369 KASSERT((flags & PMAP_KMPAGE) == 0); 3370 simple_lock(&omd->pvh_slock); 3371 pv = pmap_kremove_pg(opg, va); 3372 simple_unlock(&omd->pvh_slock); 3373 } 3374 #endif 3375 if (l2pte_valid(opte)) { 3376 #ifdef PMAP_CACHE_VIVT 3377 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3378 #endif 3379 cpu_tlb_flushD_SE(va); 3380 cpu_cpwait(); 3381 } 3382 } 3383 3384 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3385 pte_l2_s_cache_mode; 3386 PTE_SYNC(ptep); 3387 3388 if (pg) { 3389 if (flags & PMAP_KMPAGE) { 3390 simple_lock(&md->pvh_slock); 3391 KASSERT(md->urw_mappings == 0); 3392 KASSERT(md->uro_mappings == 0); 3393 KASSERT(md->krw_mappings == 0); 3394 KASSERT(md->kro_mappings == 0); 3395 #ifdef PMAP_CACHE_VIPT 3396 KASSERT(pv == NULL); 3397 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3398 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3399 /* if there is a color conflict, evict from cache. */ 3400 if (pmap_is_page_colored_p(md) 3401 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3402 PMAPCOUNT(vac_color_change); 3403 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3404 } else if (md->pvh_attrs & PVF_MULTCLR) { 3405 /* 3406 * If this page has multiple colors, expunge 3407 * them. 3408 */ 3409 PMAPCOUNT(vac_flush_lots2); 3410 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3411 } 3412 md->pvh_attrs &= PAGE_SIZE - 1; 3413 md->pvh_attrs |= PVF_KMPAGE 3414 | PVF_COLORED | PVF_DIRTY 3415 | (va & arm_cache_prefer_mask); 3416 #endif 3417 #ifdef PMAP_CACHE_VIVT 3418 md->pvh_attrs |= PVF_KMPAGE; 3419 #endif 3420 pmap_kmpages++; 3421 simple_unlock(&md->pvh_slock); 3422 #ifdef PMAP_CACHE_VIPT 3423 } else { 3424 if (pv == NULL) { 3425 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3426 KASSERT(pv != NULL); 3427 } 3428 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3429 PVF_WIRED | PVF_KENTRY 3430 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3431 if ((prot & VM_PROT_WRITE) 3432 && !(md->pvh_attrs & PVF_NC)) 3433 md->pvh_attrs |= PVF_DIRTY; 3434 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3435 simple_lock(&md->pvh_slock); 3436 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3437 simple_unlock(&md->pvh_slock); 3438 #endif 3439 } 3440 #ifdef PMAP_CACHE_VIPT 3441 } else { 3442 if (pv != NULL) 3443 pool_put(&pmap_pv_pool, pv); 3444 #endif 3445 } 3446 } 3447 3448 void 3449 pmap_kremove(vaddr_t va, vsize_t len) 3450 { 3451 struct l2_bucket *l2b; 3452 pt_entry_t *ptep, *sptep, opte; 3453 vaddr_t next_bucket, eva; 3454 u_int mappings; 3455 struct vm_page *opg; 3456 3457 PMAPCOUNT(kenter_unmappings); 3458 3459 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3460 va, len)); 3461 3462 eva = va + len; 3463 3464 while (va < eva) { 3465 next_bucket = L2_NEXT_BUCKET(va); 3466 if (next_bucket > eva) 3467 next_bucket = eva; 3468 3469 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3470 KDASSERT(l2b != NULL); 3471 3472 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3473 mappings = 0; 3474 3475 while (va < next_bucket) { 3476 opte = *ptep; 3477 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3478 if (opg) { 3479 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3480 3481 if (omd->pvh_attrs & PVF_KMPAGE) { 3482 simple_lock(&omd->pvh_slock); 3483 KASSERT(omd->urw_mappings == 0); 3484 KASSERT(omd->uro_mappings == 0); 3485 KASSERT(omd->krw_mappings == 0); 3486 KASSERT(omd->kro_mappings == 0); 3487 omd->pvh_attrs &= ~PVF_KMPAGE; 3488 #ifdef PMAP_CACHE_VIPT 3489 omd->pvh_attrs &= ~PVF_WRITE; 3490 #endif 3491 pmap_kmpages--; 3492 simple_unlock(&omd->pvh_slock); 3493 #ifdef PMAP_CACHE_VIPT 3494 } else { 3495 pool_put(&pmap_pv_pool, 3496 pmap_kremove_pg(opg, va)); 3497 #endif 3498 } 3499 } 3500 if (l2pte_valid(opte)) { 3501 #ifdef PMAP_CACHE_VIVT 3502 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3503 #endif 3504 cpu_tlb_flushD_SE(va); 3505 } 3506 if (opte) { 3507 *ptep = 0; 3508 mappings++; 3509 } 3510 va += PAGE_SIZE; 3511 ptep++; 3512 } 3513 KDASSERT(mappings <= l2b->l2b_occupancy); 3514 l2b->l2b_occupancy -= mappings; 3515 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3516 } 3517 cpu_cpwait(); 3518 } 3519 3520 bool 3521 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3522 { 3523 struct l2_dtable *l2; 3524 pd_entry_t *pl1pd, l1pd; 3525 pt_entry_t *ptep, pte; 3526 paddr_t pa; 3527 u_int l1idx; 3528 3529 pmap_acquire_pmap_lock(pm); 3530 3531 l1idx = L1_IDX(va); 3532 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3533 l1pd = *pl1pd; 3534 3535 if (l1pte_section_p(l1pd)) { 3536 /* 3537 * These should only happen for pmap_kernel() 3538 */ 3539 KDASSERT(pm == pmap_kernel()); 3540 pmap_release_pmap_lock(pm); 3541 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3542 } else { 3543 /* 3544 * Note that we can't rely on the validity of the L1 3545 * descriptor as an indication that a mapping exists. 3546 * We have to look it up in the L2 dtable. 3547 */ 3548 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3549 3550 if (l2 == NULL || 3551 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3552 pmap_release_pmap_lock(pm); 3553 return false; 3554 } 3555 3556 ptep = &ptep[l2pte_index(va)]; 3557 pte = *ptep; 3558 pmap_release_pmap_lock(pm); 3559 3560 if (pte == 0) 3561 return false; 3562 3563 switch (pte & L2_TYPE_MASK) { 3564 case L2_TYPE_L: 3565 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3566 break; 3567 3568 default: 3569 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3570 break; 3571 } 3572 } 3573 3574 if (pap != NULL) 3575 *pap = pa; 3576 3577 return true; 3578 } 3579 3580 void 3581 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3582 { 3583 struct l2_bucket *l2b; 3584 pt_entry_t *ptep, pte; 3585 vaddr_t next_bucket; 3586 u_int flags; 3587 u_int clr_mask; 3588 int flush; 3589 3590 NPDEBUG(PDB_PROTECT, 3591 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3592 pm, sva, eva, prot)); 3593 3594 if ((prot & VM_PROT_READ) == 0) { 3595 pmap_remove(pm, sva, eva); 3596 return; 3597 } 3598 3599 if (prot & VM_PROT_WRITE) { 3600 /* 3601 * If this is a read->write transition, just ignore it and let 3602 * uvm_fault() take care of it later. 3603 */ 3604 return; 3605 } 3606 3607 PMAP_MAP_TO_HEAD_LOCK(); 3608 pmap_acquire_pmap_lock(pm); 3609 3610 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3611 flags = 0; 3612 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3613 3614 while (sva < eva) { 3615 next_bucket = L2_NEXT_BUCKET(sva); 3616 if (next_bucket > eva) 3617 next_bucket = eva; 3618 3619 l2b = pmap_get_l2_bucket(pm, sva); 3620 if (l2b == NULL) { 3621 sva = next_bucket; 3622 continue; 3623 } 3624 3625 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3626 3627 while (sva < next_bucket) { 3628 pte = *ptep; 3629 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3630 struct vm_page *pg; 3631 u_int f; 3632 3633 #ifdef PMAP_CACHE_VIVT 3634 /* 3635 * OK, at this point, we know we're doing 3636 * write-protect operation. If the pmap is 3637 * active, write-back the page. 3638 */ 3639 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3640 false, false); 3641 #endif 3642 3643 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3644 pte = l2pte_set_readonly(pte); 3645 *ptep = pte; 3646 PTE_SYNC(ptep); 3647 3648 if (pg != NULL) { 3649 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3650 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3651 3652 simple_lock(&md->pvh_slock); 3653 f = pmap_modify_pv(md, pa, pm, sva, 3654 clr_mask, 0); 3655 pmap_vac_me_harder(md, pa, pm, sva); 3656 simple_unlock(&md->pvh_slock); 3657 } else 3658 f = PVF_REF | PVF_EXEC; 3659 3660 if (flush >= 0) { 3661 flush++; 3662 flags |= f; 3663 } else 3664 if (PV_BEEN_EXECD(f)) 3665 pmap_tlb_flushID_SE(pm, sva); 3666 else 3667 if (PV_BEEN_REFD(f)) 3668 pmap_tlb_flushD_SE(pm, sva); 3669 } 3670 3671 sva += PAGE_SIZE; 3672 ptep++; 3673 } 3674 } 3675 3676 pmap_release_pmap_lock(pm); 3677 PMAP_MAP_TO_HEAD_UNLOCK(); 3678 3679 if (flush) { 3680 if (PV_BEEN_EXECD(flags)) 3681 pmap_tlb_flushID(pm); 3682 else 3683 if (PV_BEEN_REFD(flags)) 3684 pmap_tlb_flushD(pm); 3685 } 3686 } 3687 3688 void 3689 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3690 { 3691 struct l2_bucket *l2b; 3692 pt_entry_t *ptep; 3693 vaddr_t next_bucket; 3694 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3695 3696 NPDEBUG(PDB_EXEC, 3697 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3698 pm, sva, eva)); 3699 3700 PMAP_MAP_TO_HEAD_LOCK(); 3701 pmap_acquire_pmap_lock(pm); 3702 3703 while (sva < eva) { 3704 next_bucket = L2_NEXT_BUCKET(sva); 3705 if (next_bucket > eva) 3706 next_bucket = eva; 3707 3708 l2b = pmap_get_l2_bucket(pm, sva); 3709 if (l2b == NULL) { 3710 sva = next_bucket; 3711 continue; 3712 } 3713 3714 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3715 sva < next_bucket; 3716 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3717 if (l2pte_valid(*ptep)) { 3718 cpu_icache_sync_range(sva, 3719 min(page_size, eva - sva)); 3720 } 3721 } 3722 } 3723 3724 pmap_release_pmap_lock(pm); 3725 PMAP_MAP_TO_HEAD_UNLOCK(); 3726 } 3727 3728 void 3729 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3730 { 3731 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3732 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3733 3734 NPDEBUG(PDB_PROTECT, 3735 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3736 md, pa, prot)); 3737 3738 switch(prot) { 3739 case VM_PROT_READ|VM_PROT_WRITE: 3740 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3741 pmap_clearbit(md, pa, PVF_EXEC); 3742 break; 3743 #endif 3744 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3745 break; 3746 3747 case VM_PROT_READ: 3748 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3749 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3750 break; 3751 #endif 3752 case VM_PROT_READ|VM_PROT_EXECUTE: 3753 pmap_clearbit(md, pa, PVF_WRITE); 3754 break; 3755 3756 default: 3757 pmap_page_remove(md, pa); 3758 break; 3759 } 3760 } 3761 3762 /* 3763 * pmap_clear_modify: 3764 * 3765 * Clear the "modified" attribute for a page. 3766 */ 3767 bool 3768 pmap_clear_modify(struct vm_page *pg) 3769 { 3770 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3771 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3772 bool rv; 3773 3774 if (md->pvh_attrs & PVF_MOD) { 3775 rv = true; 3776 #ifdef PMAP_CACHE_VIPT 3777 /* 3778 * If we are going to clear the modified bit and there are 3779 * no other modified bits set, flush the page to memory and 3780 * mark it clean. 3781 */ 3782 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3783 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3784 #endif 3785 pmap_clearbit(md, pa, PVF_MOD); 3786 } else 3787 rv = false; 3788 3789 return (rv); 3790 } 3791 3792 /* 3793 * pmap_clear_reference: 3794 * 3795 * Clear the "referenced" attribute for a page. 3796 */ 3797 bool 3798 pmap_clear_reference(struct vm_page *pg) 3799 { 3800 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3801 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3802 bool rv; 3803 3804 if (md->pvh_attrs & PVF_REF) { 3805 rv = true; 3806 pmap_clearbit(md, pa, PVF_REF); 3807 } else 3808 rv = false; 3809 3810 return (rv); 3811 } 3812 3813 /* 3814 * pmap_is_modified: 3815 * 3816 * Test if a page has the "modified" attribute. 3817 */ 3818 /* See <arm/arm32/pmap.h> */ 3819 3820 /* 3821 * pmap_is_referenced: 3822 * 3823 * Test if a page has the "referenced" attribute. 3824 */ 3825 /* See <arm/arm32/pmap.h> */ 3826 3827 int 3828 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3829 { 3830 struct l2_dtable *l2; 3831 struct l2_bucket *l2b; 3832 pd_entry_t *pl1pd, l1pd; 3833 pt_entry_t *ptep, pte; 3834 paddr_t pa; 3835 u_int l1idx; 3836 int rv = 0; 3837 3838 PMAP_MAP_TO_HEAD_LOCK(); 3839 pmap_acquire_pmap_lock(pm); 3840 3841 l1idx = L1_IDX(va); 3842 3843 /* 3844 * If there is no l2_dtable for this address, then the process 3845 * has no business accessing it. 3846 * 3847 * Note: This will catch userland processes trying to access 3848 * kernel addresses. 3849 */ 3850 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3851 if (l2 == NULL) 3852 goto out; 3853 3854 /* 3855 * Likewise if there is no L2 descriptor table 3856 */ 3857 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3858 if (l2b->l2b_kva == NULL) 3859 goto out; 3860 3861 /* 3862 * Check the PTE itself. 3863 */ 3864 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3865 pte = *ptep; 3866 if (pte == 0) 3867 goto out; 3868 3869 /* 3870 * Catch a userland access to the vector page mapped at 0x0 3871 */ 3872 if (user && (pte & L2_S_PROT_U) == 0) 3873 goto out; 3874 3875 pa = l2pte_pa(pte); 3876 3877 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3878 /* 3879 * This looks like a good candidate for "page modified" 3880 * emulation... 3881 */ 3882 struct pv_entry *pv; 3883 struct vm_page *pg; 3884 3885 /* Extract the physical address of the page */ 3886 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3887 goto out; 3888 3889 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3890 3891 /* Get the current flags for this page. */ 3892 simple_lock(&md->pvh_slock); 3893 3894 pv = pmap_find_pv(md, pm, va); 3895 if (pv == NULL) { 3896 simple_unlock(&md->pvh_slock); 3897 goto out; 3898 } 3899 3900 /* 3901 * Do the flags say this page is writable? If not then it 3902 * is a genuine write fault. If yes then the write fault is 3903 * our fault as we did not reflect the write access in the 3904 * PTE. Now we know a write has occurred we can correct this 3905 * and also set the modified bit 3906 */ 3907 if ((pv->pv_flags & PVF_WRITE) == 0) { 3908 simple_unlock(&md->pvh_slock); 3909 goto out; 3910 } 3911 3912 NPDEBUG(PDB_FOLLOW, 3913 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3914 pm, va, pa)); 3915 3916 md->pvh_attrs |= PVF_REF | PVF_MOD; 3917 pv->pv_flags |= PVF_REF | PVF_MOD; 3918 #ifdef PMAP_CACHE_VIPT 3919 /* 3920 * If there are cacheable mappings for this page, mark it dirty. 3921 */ 3922 if ((md->pvh_attrs & PVF_NC) == 0) 3923 md->pvh_attrs |= PVF_DIRTY; 3924 #endif 3925 simple_unlock(&md->pvh_slock); 3926 3927 /* 3928 * Re-enable write permissions for the page. No need to call 3929 * pmap_vac_me_harder(), since this is just a 3930 * modified-emulation fault, and the PVF_WRITE bit isn't 3931 * changing. We've already set the cacheable bits based on 3932 * the assumption that we can write to this page. 3933 */ 3934 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3935 PTE_SYNC(ptep); 3936 rv = 1; 3937 } else 3938 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3939 /* 3940 * This looks like a good candidate for "page referenced" 3941 * emulation. 3942 */ 3943 struct pv_entry *pv; 3944 struct vm_page *pg; 3945 3946 /* Extract the physical address of the page */ 3947 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3948 goto out; 3949 3950 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3951 3952 /* Get the current flags for this page. */ 3953 simple_lock(&md->pvh_slock); 3954 3955 pv = pmap_find_pv(md, pm, va); 3956 if (pv == NULL) { 3957 simple_unlock(&md->pvh_slock); 3958 goto out; 3959 } 3960 3961 md->pvh_attrs |= PVF_REF; 3962 pv->pv_flags |= PVF_REF; 3963 simple_unlock(&md->pvh_slock); 3964 3965 NPDEBUG(PDB_FOLLOW, 3966 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3967 pm, va, pa)); 3968 3969 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3970 PTE_SYNC(ptep); 3971 rv = 1; 3972 } 3973 3974 /* 3975 * We know there is a valid mapping here, so simply 3976 * fix up the L1 if necessary. 3977 */ 3978 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3979 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3980 if (*pl1pd != l1pd) { 3981 *pl1pd = l1pd; 3982 PTE_SYNC(pl1pd); 3983 rv = 1; 3984 } 3985 3986 #ifdef CPU_SA110 3987 /* 3988 * There are bugs in the rev K SA110. This is a check for one 3989 * of them. 3990 */ 3991 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3992 curcpu()->ci_arm_cpurev < 3) { 3993 /* Always current pmap */ 3994 if (l2pte_valid(pte)) { 3995 extern int kernel_debug; 3996 if (kernel_debug & 1) { 3997 struct proc *p = curlwp->l_proc; 3998 printf("prefetch_abort: page is already " 3999 "mapped - pte=%p *pte=%08x\n", ptep, pte); 4000 printf("prefetch_abort: pc=%08lx proc=%p " 4001 "process=%s\n", va, p, p->p_comm); 4002 printf("prefetch_abort: far=%08x fs=%x\n", 4003 cpu_faultaddress(), cpu_faultstatus()); 4004 } 4005 #ifdef DDB 4006 if (kernel_debug & 2) 4007 Debugger(); 4008 #endif 4009 rv = 1; 4010 } 4011 } 4012 #endif /* CPU_SA110 */ 4013 4014 #ifdef DEBUG 4015 /* 4016 * If 'rv == 0' at this point, it generally indicates that there is a 4017 * stale TLB entry for the faulting address. This happens when two or 4018 * more processes are sharing an L1. Since we don't flush the TLB on 4019 * a context switch between such processes, we can take domain faults 4020 * for mappings which exist at the same VA in both processes. EVEN IF 4021 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4022 * example. 4023 * 4024 * This is extremely likely to happen if pmap_enter() updated the L1 4025 * entry for a recently entered mapping. In this case, the TLB is 4026 * flushed for the new mapping, but there may still be TLB entries for 4027 * other mappings belonging to other processes in the 1MB range 4028 * covered by the L1 entry. 4029 * 4030 * Since 'rv == 0', we know that the L1 already contains the correct 4031 * value, so the fault must be due to a stale TLB entry. 4032 * 4033 * Since we always need to flush the TLB anyway in the case where we 4034 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4035 * stale TLB entries dynamically. 4036 * 4037 * However, the above condition can ONLY happen if the current L1 is 4038 * being shared. If it happens when the L1 is unshared, it indicates 4039 * that other parts of the pmap are not doing their job WRT managing 4040 * the TLB. 4041 */ 4042 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4043 extern int last_fault_code; 4044 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4045 pm, va, ftype); 4046 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4047 l2, l2b, ptep, pl1pd); 4048 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4049 pte, l1pd, last_fault_code); 4050 #ifdef DDB 4051 Debugger(); 4052 #endif 4053 } 4054 #endif 4055 4056 cpu_tlb_flushID_SE(va); 4057 cpu_cpwait(); 4058 4059 rv = 1; 4060 4061 out: 4062 pmap_release_pmap_lock(pm); 4063 PMAP_MAP_TO_HEAD_UNLOCK(); 4064 4065 return (rv); 4066 } 4067 4068 /* 4069 * Routine: pmap_procwr 4070 * 4071 * Function: 4072 * Synchronize caches corresponding to [addr, addr+len) in p. 4073 * 4074 */ 4075 void 4076 pmap_procwr(struct proc *p, vaddr_t va, int len) 4077 { 4078 /* We only need to do anything if it is the current process. */ 4079 if (p == curproc) 4080 cpu_icache_sync_range(va, len); 4081 } 4082 4083 /* 4084 * Routine: pmap_unwire 4085 * Function: Clear the wired attribute for a map/virtual-address pair. 4086 * 4087 * In/out conditions: 4088 * The mapping must already exist in the pmap. 4089 */ 4090 void 4091 pmap_unwire(pmap_t pm, vaddr_t va) 4092 { 4093 struct l2_bucket *l2b; 4094 pt_entry_t *ptep, pte; 4095 struct vm_page *pg; 4096 paddr_t pa; 4097 4098 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4099 4100 PMAP_MAP_TO_HEAD_LOCK(); 4101 pmap_acquire_pmap_lock(pm); 4102 4103 l2b = pmap_get_l2_bucket(pm, va); 4104 KDASSERT(l2b != NULL); 4105 4106 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4107 pte = *ptep; 4108 4109 /* Extract the physical address of the page */ 4110 pa = l2pte_pa(pte); 4111 4112 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4113 /* Update the wired bit in the pv entry for this page. */ 4114 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4115 4116 simple_lock(&md->pvh_slock); 4117 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4118 simple_unlock(&md->pvh_slock); 4119 } 4120 4121 pmap_release_pmap_lock(pm); 4122 PMAP_MAP_TO_HEAD_UNLOCK(); 4123 } 4124 4125 void 4126 pmap_activate(struct lwp *l) 4127 { 4128 extern int block_userspace_access; 4129 pmap_t opm, npm, rpm; 4130 uint32_t odacr, ndacr; 4131 int oldirqstate; 4132 4133 /* 4134 * If activating a non-current lwp or the current lwp is 4135 * already active, just return. 4136 */ 4137 if (l != curlwp || 4138 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4139 return; 4140 4141 npm = l->l_proc->p_vmspace->vm_map.pmap; 4142 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4143 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4144 4145 /* 4146 * If TTB and DACR are unchanged, short-circuit all the 4147 * TLB/cache management stuff. 4148 */ 4149 if (pmap_previous_active_lwp != NULL) { 4150 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4151 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4152 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4153 4154 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4155 goto all_done; 4156 } else 4157 opm = NULL; 4158 4159 PMAPCOUNT(activations); 4160 block_userspace_access = 1; 4161 4162 /* 4163 * If switching to a user vmspace which is different to the 4164 * most recent one, and the most recent one is potentially 4165 * live in the cache, we must write-back and invalidate the 4166 * entire cache. 4167 */ 4168 rpm = pmap_recent_user; 4169 4170 /* 4171 * XXXSCW: There's a corner case here which can leave turds in the cache as 4172 * reported in kern/41058. They're probably left over during tear-down and 4173 * switching away from an exiting process. Until the root cause is identified 4174 * and fixed, zap the cache when switching pmaps. This will result in a few 4175 * unnecessary cache flushes, but that's better than silently corrupting data. 4176 */ 4177 #if 0 4178 if (npm != pmap_kernel() && rpm && npm != rpm && 4179 rpm->pm_cstate.cs_cache) { 4180 rpm->pm_cstate.cs_cache = 0; 4181 #ifdef PMAP_CACHE_VIVT 4182 cpu_idcache_wbinv_all(); 4183 #endif 4184 } 4185 #else 4186 if (rpm) { 4187 rpm->pm_cstate.cs_cache = 0; 4188 if (npm == pmap_kernel()) 4189 pmap_recent_user = NULL; 4190 #ifdef PMAP_CACHE_VIVT 4191 cpu_idcache_wbinv_all(); 4192 #endif 4193 } 4194 #endif 4195 4196 /* No interrupts while we frob the TTB/DACR */ 4197 oldirqstate = disable_interrupts(IF32_bits); 4198 4199 /* 4200 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4201 * entry corresponding to 'vector_page' in the incoming L1 table 4202 * before switching to it otherwise subsequent interrupts/exceptions 4203 * (including domain faults!) will jump into hyperspace. 4204 */ 4205 if (npm->pm_pl1vec != NULL) { 4206 cpu_tlb_flushID_SE((u_int)vector_page); 4207 cpu_cpwait(); 4208 *npm->pm_pl1vec = npm->pm_l1vec; 4209 PTE_SYNC(npm->pm_pl1vec); 4210 } 4211 4212 cpu_domains(ndacr); 4213 4214 if (npm == pmap_kernel() || npm == rpm) { 4215 /* 4216 * Switching to a kernel thread, or back to the 4217 * same user vmspace as before... Simply update 4218 * the TTB (no TLB flush required) 4219 */ 4220 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4221 "r"(npm->pm_l1->l1_physaddr)); 4222 cpu_cpwait(); 4223 } else { 4224 /* 4225 * Otherwise, update TTB and flush TLB 4226 */ 4227 cpu_context_switch(npm->pm_l1->l1_physaddr); 4228 if (rpm != NULL) 4229 rpm->pm_cstate.cs_tlb = 0; 4230 } 4231 4232 restore_interrupts(oldirqstate); 4233 4234 block_userspace_access = 0; 4235 4236 all_done: 4237 /* 4238 * The new pmap is resident. Make sure it's marked 4239 * as resident in the cache/TLB. 4240 */ 4241 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4242 if (npm != pmap_kernel()) 4243 pmap_recent_user = npm; 4244 4245 /* The old pmap is not longer active */ 4246 if (opm != NULL) 4247 opm->pm_activated = false; 4248 4249 /* But the new one is */ 4250 npm->pm_activated = true; 4251 } 4252 4253 void 4254 pmap_deactivate(struct lwp *l) 4255 { 4256 4257 /* 4258 * If the process is exiting, make sure pmap_activate() does 4259 * a full MMU context-switch and cache flush, which we might 4260 * otherwise skip. See PR port-arm/38950. 4261 */ 4262 if (l->l_proc->p_sflag & PS_WEXIT) 4263 pmap_previous_active_lwp = NULL; 4264 4265 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4266 } 4267 4268 void 4269 pmap_update(pmap_t pm) 4270 { 4271 4272 if (pm->pm_remove_all) { 4273 /* 4274 * Finish up the pmap_remove_all() optimisation by flushing 4275 * the TLB. 4276 */ 4277 pmap_tlb_flushID(pm); 4278 pm->pm_remove_all = false; 4279 } 4280 4281 if (pmap_is_current(pm)) { 4282 /* 4283 * If we're dealing with a current userland pmap, move its L1 4284 * to the end of the LRU. 4285 */ 4286 if (pm != pmap_kernel()) 4287 pmap_use_l1(pm); 4288 4289 /* 4290 * We can assume we're done with frobbing the cache/tlb for 4291 * now. Make sure any future pmap ops don't skip cache/tlb 4292 * flushes. 4293 */ 4294 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4295 } 4296 4297 PMAPCOUNT(updates); 4298 4299 /* 4300 * make sure TLB/cache operations have completed. 4301 */ 4302 cpu_cpwait(); 4303 } 4304 4305 void 4306 pmap_remove_all(pmap_t pm) 4307 { 4308 4309 /* 4310 * The vmspace described by this pmap is about to be torn down. 4311 * Until pmap_update() is called, UVM will only make calls 4312 * to pmap_remove(). We can make life much simpler by flushing 4313 * the cache now, and deferring TLB invalidation to pmap_update(). 4314 */ 4315 #ifdef PMAP_CACHE_VIVT 4316 pmap_idcache_wbinv_all(pm); 4317 #endif 4318 pm->pm_remove_all = true; 4319 } 4320 4321 /* 4322 * Retire the given physical map from service. 4323 * Should only be called if the map contains no valid mappings. 4324 */ 4325 void 4326 pmap_destroy(pmap_t pm) 4327 { 4328 u_int count; 4329 4330 if (pm == NULL) 4331 return; 4332 4333 if (pm->pm_remove_all) { 4334 pmap_tlb_flushID(pm); 4335 pm->pm_remove_all = false; 4336 } 4337 4338 /* 4339 * Drop reference count 4340 */ 4341 mutex_enter(&pm->pm_lock); 4342 count = --pm->pm_obj.uo_refs; 4343 mutex_exit(&pm->pm_lock); 4344 if (count > 0) { 4345 if (pmap_is_current(pm)) { 4346 if (pm != pmap_kernel()) 4347 pmap_use_l1(pm); 4348 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4349 } 4350 return; 4351 } 4352 4353 /* 4354 * reference count is zero, free pmap resources and then free pmap. 4355 */ 4356 4357 if (vector_page < KERNEL_BASE) { 4358 KDASSERT(!pmap_is_current(pm)); 4359 4360 /* Remove the vector page mapping */ 4361 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4362 pmap_update(pm); 4363 } 4364 4365 LIST_REMOVE(pm, pm_list); 4366 4367 pmap_free_l1(pm); 4368 4369 if (pmap_recent_user == pm) 4370 pmap_recent_user = NULL; 4371 4372 UVM_OBJ_DESTROY(&pm->pm_obj); 4373 4374 /* return the pmap to the pool */ 4375 pool_cache_put(&pmap_cache, pm); 4376 } 4377 4378 4379 /* 4380 * void pmap_reference(pmap_t pm) 4381 * 4382 * Add a reference to the specified pmap. 4383 */ 4384 void 4385 pmap_reference(pmap_t pm) 4386 { 4387 4388 if (pm == NULL) 4389 return; 4390 4391 pmap_use_l1(pm); 4392 4393 mutex_enter(&pm->pm_lock); 4394 pm->pm_obj.uo_refs++; 4395 mutex_exit(&pm->pm_lock); 4396 } 4397 4398 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4399 4400 static struct evcnt pmap_prefer_nochange_ev = 4401 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4402 static struct evcnt pmap_prefer_change_ev = 4403 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4404 4405 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4406 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4407 4408 void 4409 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4410 { 4411 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4412 vaddr_t va = *vap; 4413 vaddr_t diff = (hint - va) & mask; 4414 if (diff == 0) { 4415 pmap_prefer_nochange_ev.ev_count++; 4416 } else { 4417 pmap_prefer_change_ev.ev_count++; 4418 if (__predict_false(td)) 4419 va -= mask + 1; 4420 *vap = va + diff; 4421 } 4422 } 4423 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4424 4425 /* 4426 * pmap_zero_page() 4427 * 4428 * Zero a given physical page by mapping it at a page hook point. 4429 * In doing the zero page op, the page we zero is mapped cachable, as with 4430 * StrongARM accesses to non-cached pages are non-burst making writing 4431 * _any_ bulk data very slow. 4432 */ 4433 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4434 void 4435 pmap_zero_page_generic(paddr_t phys) 4436 { 4437 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4438 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4439 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4440 #endif 4441 #ifdef PMAP_CACHE_VIPT 4442 /* Choose the last page color it had, if any */ 4443 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4444 #else 4445 const vsize_t va_offset = 0; 4446 #endif 4447 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4448 4449 #ifdef DEBUG 4450 if (!SLIST_EMPTY(&md->pvh_list)) 4451 panic("pmap_zero_page: page has mappings"); 4452 #endif 4453 4454 KDASSERT((phys & PGOFSET) == 0); 4455 4456 /* 4457 * Hook in the page, zero it, and purge the cache for that 4458 * zeroed page. Invalidate the TLB as needed. 4459 */ 4460 *ptep = L2_S_PROTO | phys | 4461 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4462 PTE_SYNC(ptep); 4463 cpu_tlb_flushD_SE(cdstp + va_offset); 4464 cpu_cpwait(); 4465 bzero_page(cdstp + va_offset); 4466 /* 4467 * Unmap the page. 4468 */ 4469 *ptep = 0; 4470 PTE_SYNC(ptep); 4471 cpu_tlb_flushD_SE(cdstp + va_offset); 4472 #ifdef PMAP_CACHE_VIVT 4473 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4474 #endif 4475 #ifdef PMAP_CACHE_VIPT 4476 /* 4477 * This page is now cache resident so it now has a page color. 4478 * Any contents have been obliterated so clear the EXEC flag. 4479 */ 4480 if (!pmap_is_page_colored_p(md)) { 4481 PMAPCOUNT(vac_color_new); 4482 md->pvh_attrs |= PVF_COLORED; 4483 } 4484 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4485 md->pvh_attrs &= ~PVF_EXEC; 4486 PMAPCOUNT(exec_discarded_zero); 4487 } 4488 md->pvh_attrs |= PVF_DIRTY; 4489 #endif 4490 } 4491 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4492 4493 #if ARM_MMU_XSCALE == 1 4494 void 4495 pmap_zero_page_xscale(paddr_t phys) 4496 { 4497 #ifdef DEBUG 4498 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4499 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4500 4501 if (!SLIST_EMPTY(&md->pvh_list)) 4502 panic("pmap_zero_page: page has mappings"); 4503 #endif 4504 4505 KDASSERT((phys & PGOFSET) == 0); 4506 4507 /* 4508 * Hook in the page, zero it, and purge the cache for that 4509 * zeroed page. Invalidate the TLB as needed. 4510 */ 4511 *cdst_pte = L2_S_PROTO | phys | 4512 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4513 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4514 PTE_SYNC(cdst_pte); 4515 cpu_tlb_flushD_SE(cdstp); 4516 cpu_cpwait(); 4517 bzero_page(cdstp); 4518 xscale_cache_clean_minidata(); 4519 } 4520 #endif /* ARM_MMU_XSCALE == 1 */ 4521 4522 /* pmap_pageidlezero() 4523 * 4524 * The same as above, except that we assume that the page is not 4525 * mapped. This means we never have to flush the cache first. Called 4526 * from the idle loop. 4527 */ 4528 bool 4529 pmap_pageidlezero(paddr_t phys) 4530 { 4531 unsigned int i; 4532 int *ptr; 4533 bool rv = true; 4534 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4535 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4536 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4537 #endif 4538 #ifdef PMAP_CACHE_VIPT 4539 /* Choose the last page color it had, if any */ 4540 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4541 #else 4542 const vsize_t va_offset = 0; 4543 #endif 4544 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4545 4546 4547 #ifdef DEBUG 4548 if (!SLIST_EMPTY(&md->pvh_list)) 4549 panic("pmap_pageidlezero: page has mappings"); 4550 #endif 4551 4552 KDASSERT((phys & PGOFSET) == 0); 4553 4554 /* 4555 * Hook in the page, zero it, and purge the cache for that 4556 * zeroed page. Invalidate the TLB as needed. 4557 */ 4558 *ptep = L2_S_PROTO | phys | 4559 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4560 PTE_SYNC(ptep); 4561 cpu_tlb_flushD_SE(cdstp + va_offset); 4562 cpu_cpwait(); 4563 4564 for (i = 0, ptr = (int *)(cdstp + va_offset); 4565 i < (PAGE_SIZE / sizeof(int)); i++) { 4566 if (sched_curcpu_runnable_p() != 0) { 4567 /* 4568 * A process has become ready. Abort now, 4569 * so we don't keep it waiting while we 4570 * do slow memory access to finish this 4571 * page. 4572 */ 4573 rv = false; 4574 break; 4575 } 4576 *ptr++ = 0; 4577 } 4578 4579 #ifdef PMAP_CACHE_VIVT 4580 if (rv) 4581 /* 4582 * if we aborted we'll rezero this page again later so don't 4583 * purge it unless we finished it 4584 */ 4585 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4586 #elif defined(PMAP_CACHE_VIPT) 4587 /* 4588 * This page is now cache resident so it now has a page color. 4589 * Any contents have been obliterated so clear the EXEC flag. 4590 */ 4591 if (!pmap_is_page_colored_p(md)) { 4592 PMAPCOUNT(vac_color_new); 4593 md->pvh_attrs |= PVF_COLORED; 4594 } 4595 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4596 md->pvh_attrs &= ~PVF_EXEC; 4597 PMAPCOUNT(exec_discarded_zero); 4598 } 4599 #endif 4600 /* 4601 * Unmap the page. 4602 */ 4603 *ptep = 0; 4604 PTE_SYNC(ptep); 4605 cpu_tlb_flushD_SE(cdstp + va_offset); 4606 4607 return (rv); 4608 } 4609 4610 /* 4611 * pmap_copy_page() 4612 * 4613 * Copy one physical page into another, by mapping the pages into 4614 * hook points. The same comment regarding cachability as in 4615 * pmap_zero_page also applies here. 4616 */ 4617 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4618 void 4619 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4620 { 4621 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4622 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4623 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4624 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4625 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4626 #endif 4627 #ifdef PMAP_CACHE_VIPT 4628 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4629 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4630 #else 4631 const vsize_t src_va_offset = 0; 4632 const vsize_t dst_va_offset = 0; 4633 #endif 4634 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4635 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4636 4637 #ifdef DEBUG 4638 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4639 panic("pmap_copy_page: dst page has mappings"); 4640 #endif 4641 4642 #ifdef PMAP_CACHE_VIPT 4643 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4644 #endif 4645 KDASSERT((src & PGOFSET) == 0); 4646 KDASSERT((dst & PGOFSET) == 0); 4647 4648 /* 4649 * Clean the source page. Hold the source page's lock for 4650 * the duration of the copy so that no other mappings can 4651 * be created while we have a potentially aliased mapping. 4652 */ 4653 simple_lock(&src_md->pvh_slock); 4654 #ifdef PMAP_CACHE_VIVT 4655 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4656 #endif 4657 4658 /* 4659 * Map the pages into the page hook points, copy them, and purge 4660 * the cache for the appropriate page. Invalidate the TLB 4661 * as required. 4662 */ 4663 *src_ptep = L2_S_PROTO 4664 | src 4665 #ifdef PMAP_CACHE_VIPT 4666 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4667 #endif 4668 #ifdef PMAP_CACHE_VIVT 4669 | pte_l2_s_cache_mode 4670 #endif 4671 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4672 *dst_ptep = L2_S_PROTO | dst | 4673 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4674 PTE_SYNC(src_ptep); 4675 PTE_SYNC(dst_ptep); 4676 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4677 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4678 cpu_cpwait(); 4679 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4680 #ifdef PMAP_CACHE_VIVT 4681 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4682 #endif 4683 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4684 #ifdef PMAP_CACHE_VIVT 4685 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4686 #endif 4687 /* 4688 * Unmap the pages. 4689 */ 4690 *src_ptep = 0; 4691 *dst_ptep = 0; 4692 PTE_SYNC(src_ptep); 4693 PTE_SYNC(dst_ptep); 4694 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4695 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4696 #ifdef PMAP_CACHE_VIPT 4697 /* 4698 * Now that the destination page is in the cache, mark it as colored. 4699 * If this was an exec page, discard it. 4700 */ 4701 if (!pmap_is_page_colored_p(dst_md)) { 4702 PMAPCOUNT(vac_color_new); 4703 dst_md->pvh_attrs |= PVF_COLORED; 4704 } 4705 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4706 dst_md->pvh_attrs &= ~PVF_EXEC; 4707 PMAPCOUNT(exec_discarded_copy); 4708 } 4709 dst_md->pvh_attrs |= PVF_DIRTY; 4710 #endif 4711 } 4712 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4713 4714 #if ARM_MMU_XSCALE == 1 4715 void 4716 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4717 { 4718 struct vm_page_md *src_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(src)); 4719 #ifdef DEBUG 4720 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4721 4722 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4723 panic("pmap_copy_page: dst page has mappings"); 4724 #endif 4725 4726 KDASSERT((src & PGOFSET) == 0); 4727 KDASSERT((dst & PGOFSET) == 0); 4728 4729 /* 4730 * Clean the source page. Hold the source page's lock for 4731 * the duration of the copy so that no other mappings can 4732 * be created while we have a potentially aliased mapping. 4733 */ 4734 simple_lock(&src_md->pvh_slock); 4735 #ifdef PMAP_CACHE_VIVT 4736 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4737 #endif 4738 4739 /* 4740 * Map the pages into the page hook points, copy them, and purge 4741 * the cache for the appropriate page. Invalidate the TLB 4742 * as required. 4743 */ 4744 *csrc_pte = L2_S_PROTO | src | 4745 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4746 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4747 PTE_SYNC(csrc_pte); 4748 *cdst_pte = L2_S_PROTO | dst | 4749 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4750 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4751 PTE_SYNC(cdst_pte); 4752 cpu_tlb_flushD_SE(csrcp); 4753 cpu_tlb_flushD_SE(cdstp); 4754 cpu_cpwait(); 4755 bcopy_page(csrcp, cdstp); 4756 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4757 xscale_cache_clean_minidata(); 4758 } 4759 #endif /* ARM_MMU_XSCALE == 1 */ 4760 4761 /* 4762 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4763 * 4764 * Return the start and end addresses of the kernel's virtual space. 4765 * These values are setup in pmap_bootstrap and are updated as pages 4766 * are allocated. 4767 */ 4768 void 4769 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4770 { 4771 *start = virtual_avail; 4772 *end = virtual_end; 4773 } 4774 4775 /* 4776 * Helper function for pmap_grow_l2_bucket() 4777 */ 4778 static inline int 4779 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4780 { 4781 struct l2_bucket *l2b; 4782 pt_entry_t *ptep; 4783 paddr_t pa; 4784 4785 if (uvm.page_init_done == false) { 4786 #ifdef PMAP_STEAL_MEMORY 4787 pv_addr_t pv; 4788 pmap_boot_pagealloc(PAGE_SIZE, 4789 #ifdef PMAP_CACHE_VIPT 4790 arm_cache_prefer_mask, 4791 va & arm_cache_prefer_mask, 4792 #else 4793 0, 0, 4794 #endif 4795 &pv); 4796 pa = pv.pv_pa; 4797 #else 4798 if (uvm_page_physget(&pa) == false) 4799 return (1); 4800 #endif /* PMAP_STEAL_MEMORY */ 4801 } else { 4802 struct vm_page *pg; 4803 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4804 if (pg == NULL) 4805 return (1); 4806 pa = VM_PAGE_TO_PHYS(pg); 4807 #ifdef PMAP_CACHE_VIPT 4808 #ifdef DIAGNOSTIC 4809 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4810 #endif 4811 /* 4812 * This new page must not have any mappings. Enter it via 4813 * pmap_kenter_pa and let that routine do the hard work. 4814 */ 4815 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4816 pmap_kenter_pa(va, pa, 4817 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4818 #endif 4819 } 4820 4821 if (pap) 4822 *pap = pa; 4823 4824 PMAPCOUNT(pt_mappings); 4825 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4826 KDASSERT(l2b != NULL); 4827 4828 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4829 *ptep = L2_S_PROTO | pa | cache_mode | 4830 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4831 PTE_SYNC(ptep); 4832 memset((void *)va, 0, PAGE_SIZE); 4833 return (0); 4834 } 4835 4836 /* 4837 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4838 * used by pmap_growkernel(). 4839 */ 4840 static inline struct l2_bucket * 4841 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4842 { 4843 struct l2_dtable *l2; 4844 struct l2_bucket *l2b; 4845 u_short l1idx; 4846 vaddr_t nva; 4847 4848 l1idx = L1_IDX(va); 4849 4850 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4851 /* 4852 * No mapping at this address, as there is 4853 * no entry in the L1 table. 4854 * Need to allocate a new l2_dtable. 4855 */ 4856 nva = pmap_kernel_l2dtable_kva; 4857 if ((nva & PGOFSET) == 0) { 4858 /* 4859 * Need to allocate a backing page 4860 */ 4861 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4862 return (NULL); 4863 } 4864 4865 l2 = (struct l2_dtable *)nva; 4866 nva += sizeof(struct l2_dtable); 4867 4868 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4869 /* 4870 * The new l2_dtable straddles a page boundary. 4871 * Map in another page to cover it. 4872 */ 4873 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4874 return (NULL); 4875 } 4876 4877 pmap_kernel_l2dtable_kva = nva; 4878 4879 /* 4880 * Link it into the parent pmap 4881 */ 4882 pm->pm_l2[L2_IDX(l1idx)] = l2; 4883 } 4884 4885 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4886 4887 /* 4888 * Fetch pointer to the L2 page table associated with the address. 4889 */ 4890 if (l2b->l2b_kva == NULL) { 4891 pt_entry_t *ptep; 4892 4893 /* 4894 * No L2 page table has been allocated. Chances are, this 4895 * is because we just allocated the l2_dtable, above. 4896 */ 4897 nva = pmap_kernel_l2ptp_kva; 4898 ptep = (pt_entry_t *)nva; 4899 if ((nva & PGOFSET) == 0) { 4900 /* 4901 * Need to allocate a backing page 4902 */ 4903 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4904 &pmap_kernel_l2ptp_phys)) 4905 return (NULL); 4906 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4907 } 4908 4909 l2->l2_occupancy++; 4910 l2b->l2b_kva = ptep; 4911 l2b->l2b_l1idx = l1idx; 4912 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4913 4914 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4915 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4916 } 4917 4918 return (l2b); 4919 } 4920 4921 vaddr_t 4922 pmap_growkernel(vaddr_t maxkvaddr) 4923 { 4924 pmap_t kpm = pmap_kernel(); 4925 struct l1_ttable *l1; 4926 struct l2_bucket *l2b; 4927 pd_entry_t *pl1pd; 4928 int s; 4929 4930 if (maxkvaddr <= pmap_curmaxkvaddr) 4931 goto out; /* we are OK */ 4932 4933 NPDEBUG(PDB_GROWKERN, 4934 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4935 pmap_curmaxkvaddr, maxkvaddr)); 4936 4937 KDASSERT(maxkvaddr <= virtual_end); 4938 4939 /* 4940 * whoops! we need to add kernel PTPs 4941 */ 4942 4943 s = splhigh(); /* to be safe */ 4944 mutex_enter(&kpm->pm_lock); 4945 4946 /* Map 1MB at a time */ 4947 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4948 4949 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4950 KDASSERT(l2b != NULL); 4951 4952 /* Distribute new L1 entry to all other L1s */ 4953 SLIST_FOREACH(l1, &l1_list, l1_link) { 4954 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4955 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4956 L1_C_PROTO; 4957 PTE_SYNC(pl1pd); 4958 } 4959 } 4960 4961 /* 4962 * flush out the cache, expensive but growkernel will happen so 4963 * rarely 4964 */ 4965 cpu_dcache_wbinv_all(); 4966 cpu_tlb_flushD(); 4967 cpu_cpwait(); 4968 4969 mutex_exit(&kpm->pm_lock); 4970 splx(s); 4971 4972 out: 4973 return (pmap_curmaxkvaddr); 4974 } 4975 4976 /************************ Utility routines ****************************/ 4977 4978 /* 4979 * vector_page_setprot: 4980 * 4981 * Manipulate the protection of the vector page. 4982 */ 4983 void 4984 vector_page_setprot(int prot) 4985 { 4986 struct l2_bucket *l2b; 4987 pt_entry_t *ptep; 4988 4989 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4990 KDASSERT(l2b != NULL); 4991 4992 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4993 4994 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4995 PTE_SYNC(ptep); 4996 cpu_tlb_flushD_SE(vector_page); 4997 cpu_cpwait(); 4998 } 4999 5000 /* 5001 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5002 * Returns true if the mapping exists, else false. 5003 * 5004 * NOTE: This function is only used by a couple of arm-specific modules. 5005 * It is not safe to take any pmap locks here, since we could be right 5006 * in the middle of debugging the pmap anyway... 5007 * 5008 * It is possible for this routine to return false even though a valid 5009 * mapping does exist. This is because we don't lock, so the metadata 5010 * state may be inconsistent. 5011 * 5012 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5013 * a "section" mapping. 5014 */ 5015 bool 5016 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5017 { 5018 struct l2_dtable *l2; 5019 pd_entry_t *pl1pd, l1pd; 5020 pt_entry_t *ptep; 5021 u_short l1idx; 5022 5023 if (pm->pm_l1 == NULL) 5024 return false; 5025 5026 l1idx = L1_IDX(va); 5027 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5028 l1pd = *pl1pd; 5029 5030 if (l1pte_section_p(l1pd)) { 5031 *ptp = NULL; 5032 return true; 5033 } 5034 5035 if (pm->pm_l2 == NULL) 5036 return false; 5037 5038 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5039 5040 if (l2 == NULL || 5041 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5042 return false; 5043 } 5044 5045 *ptp = &ptep[l2pte_index(va)]; 5046 return true; 5047 } 5048 5049 bool 5050 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5051 { 5052 u_short l1idx; 5053 5054 if (pm->pm_l1 == NULL) 5055 return false; 5056 5057 l1idx = L1_IDX(va); 5058 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5059 5060 return true; 5061 } 5062 5063 /************************ Bootstrapping routines ****************************/ 5064 5065 static void 5066 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5067 { 5068 int i; 5069 5070 l1->l1_kva = l1pt; 5071 l1->l1_domain_use_count = 0; 5072 l1->l1_domain_first = 0; 5073 5074 for (i = 0; i < PMAP_DOMAINS; i++) 5075 l1->l1_domain_free[i] = i + 1; 5076 5077 /* 5078 * Copy the kernel's L1 entries to each new L1. 5079 */ 5080 if (pmap_initialized) 5081 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5082 5083 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5084 &l1->l1_physaddr) == false) 5085 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5086 5087 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5088 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5089 } 5090 5091 /* 5092 * pmap_bootstrap() is called from the board-specific initarm() routine 5093 * once the kernel L1/L2 descriptors tables have been set up. 5094 * 5095 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5096 * spread over a number of disparate files/functions. 5097 * 5098 * We are passed the following parameters 5099 * - kernel_l1pt 5100 * This is a pointer to the base of the kernel's L1 translation table. 5101 * - vstart 5102 * 1MB-aligned start of managed kernel virtual memory. 5103 * - vend 5104 * 1MB-aligned end of managed kernel virtual memory. 5105 * 5106 * We use the first parameter to build the metadata (struct l1_ttable and 5107 * struct l2_dtable) necessary to track kernel mappings. 5108 */ 5109 #define PMAP_STATIC_L2_SIZE 16 5110 void 5111 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5112 { 5113 static struct l1_ttable static_l1; 5114 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5115 struct l1_ttable *l1 = &static_l1; 5116 struct l2_dtable *l2; 5117 struct l2_bucket *l2b; 5118 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5119 pmap_t pm = pmap_kernel(); 5120 pd_entry_t pde; 5121 pt_entry_t *ptep; 5122 paddr_t pa; 5123 vaddr_t va; 5124 vsize_t size; 5125 int nptes, l1idx, l2idx, l2next = 0; 5126 5127 /* 5128 * Initialise the kernel pmap object 5129 */ 5130 pm->pm_l1 = l1; 5131 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5132 pm->pm_activated = true; 5133 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5134 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5135 5136 /* 5137 * Scan the L1 translation table created by initarm() and create 5138 * the required metadata for all valid mappings found in it. 5139 */ 5140 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5141 pde = l1pt[l1idx]; 5142 5143 /* 5144 * We're only interested in Coarse mappings. 5145 * pmap_extract() can deal with section mappings without 5146 * recourse to checking L2 metadata. 5147 */ 5148 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5149 continue; 5150 5151 /* 5152 * Lookup the KVA of this L2 descriptor table 5153 */ 5154 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5155 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5156 if (ptep == NULL) { 5157 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5158 (u_int)l1idx << L1_S_SHIFT, pa); 5159 } 5160 5161 /* 5162 * Fetch the associated L2 metadata structure. 5163 * Allocate a new one if necessary. 5164 */ 5165 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5166 if (l2next == PMAP_STATIC_L2_SIZE) 5167 panic("pmap_bootstrap: out of static L2s"); 5168 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5169 } 5170 5171 /* 5172 * One more L1 slot tracked... 5173 */ 5174 l2->l2_occupancy++; 5175 5176 /* 5177 * Fill in the details of the L2 descriptor in the 5178 * appropriate bucket. 5179 */ 5180 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5181 l2b->l2b_kva = ptep; 5182 l2b->l2b_phys = pa; 5183 l2b->l2b_l1idx = l1idx; 5184 5185 /* 5186 * Establish an initial occupancy count for this descriptor 5187 */ 5188 for (l2idx = 0; 5189 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5190 l2idx++) { 5191 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5192 l2b->l2b_occupancy++; 5193 } 5194 } 5195 5196 /* 5197 * Make sure the descriptor itself has the correct cache mode. 5198 * If not, fix it, but whine about the problem. Port-meisters 5199 * should consider this a clue to fix up their initarm() 5200 * function. :) 5201 */ 5202 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5203 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5204 "L2 pte @ %p\n", ptep); 5205 } 5206 } 5207 5208 /* 5209 * Ensure the primary (kernel) L1 has the correct cache mode for 5210 * a page table. Bitch if it is not correctly set. 5211 */ 5212 for (va = (vaddr_t)l1pt; 5213 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5214 if (pmap_set_pt_cache_mode(l1pt, va)) 5215 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5216 "primary L1 @ 0x%lx\n", va); 5217 } 5218 5219 cpu_dcache_wbinv_all(); 5220 cpu_tlb_flushID(); 5221 cpu_cpwait(); 5222 5223 /* 5224 * now we allocate the "special" VAs which are used for tmp mappings 5225 * by the pmap (and other modules). we allocate the VAs by advancing 5226 * virtual_avail (note that there are no pages mapped at these VAs). 5227 * 5228 * Managed KVM space start from wherever initarm() tells us. 5229 */ 5230 virtual_avail = vstart; 5231 virtual_end = vend; 5232 5233 #ifdef PMAP_CACHE_VIPT 5234 /* 5235 * If we have a VIPT cache, we need one page/pte per possible alias 5236 * page so we won't violate cache aliasing rules. 5237 */ 5238 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5239 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5240 #else 5241 nptes = 1; 5242 #endif 5243 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5244 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5245 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5246 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5247 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5248 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5249 (void *)&msgbufaddr, NULL); 5250 5251 /* 5252 * Allocate a range of kernel virtual address space to be used 5253 * for L2 descriptor tables and metadata allocation in 5254 * pmap_growkernel(). 5255 */ 5256 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5257 pmap_alloc_specials(&virtual_avail, 5258 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5259 &pmap_kernel_l2ptp_kva, NULL); 5260 5261 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5262 pmap_alloc_specials(&virtual_avail, 5263 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5264 &pmap_kernel_l2dtable_kva, NULL); 5265 5266 /* 5267 * init the static-global locks and global pmap list. 5268 */ 5269 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5270 5271 /* 5272 * We can now initialise the first L1's metadata. 5273 */ 5274 SLIST_INIT(&l1_list); 5275 TAILQ_INIT(&l1_lru_list); 5276 simple_lock_init(&l1_lru_lock); 5277 pmap_init_l1(l1, l1pt); 5278 5279 /* Set up vector page L1 details, if necessary */ 5280 if (vector_page < KERNEL_BASE) { 5281 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5282 l2b = pmap_get_l2_bucket(pm, vector_page); 5283 KDASSERT(l2b != NULL); 5284 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5285 L1_C_DOM(pm->pm_domain); 5286 } else 5287 pm->pm_pl1vec = NULL; 5288 5289 /* 5290 * Initialize the pmap cache 5291 */ 5292 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5293 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5294 LIST_INIT(&pmap_pmaps); 5295 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5296 5297 /* 5298 * Initialize the pv pool. 5299 */ 5300 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5301 &pmap_bootstrap_pv_allocator, IPL_NONE); 5302 5303 /* 5304 * Initialize the L2 dtable pool and cache. 5305 */ 5306 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5307 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5308 5309 /* 5310 * Initialise the L2 descriptor table pool and cache 5311 */ 5312 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5313 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5314 pmap_l2ptp_ctor, NULL, NULL); 5315 5316 cpu_dcache_wbinv_all(); 5317 } 5318 5319 static int 5320 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5321 { 5322 pd_entry_t *pdep, pde; 5323 pt_entry_t *ptep, pte; 5324 vaddr_t pa; 5325 int rv = 0; 5326 5327 /* 5328 * Make sure the descriptor itself has the correct cache mode 5329 */ 5330 pdep = &kl1[L1_IDX(va)]; 5331 pde = *pdep; 5332 5333 if (l1pte_section_p(pde)) { 5334 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5335 *pdep = (pde & ~L1_S_CACHE_MASK) | 5336 pte_l1_s_cache_mode_pt; 5337 PTE_SYNC(pdep); 5338 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5339 rv = 1; 5340 } 5341 } else { 5342 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5343 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5344 if (ptep == NULL) 5345 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5346 5347 ptep = &ptep[l2pte_index(va)]; 5348 pte = *ptep; 5349 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5350 *ptep = (pte & ~L2_S_CACHE_MASK) | 5351 pte_l2_s_cache_mode_pt; 5352 PTE_SYNC(ptep); 5353 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5354 rv = 1; 5355 } 5356 } 5357 5358 return (rv); 5359 } 5360 5361 static void 5362 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5363 { 5364 vaddr_t va = *availp; 5365 struct l2_bucket *l2b; 5366 5367 if (ptep) { 5368 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5369 if (l2b == NULL) 5370 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5371 5372 if (ptep) 5373 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5374 } 5375 5376 *vap = va; 5377 *availp = va + (PAGE_SIZE * pages); 5378 } 5379 5380 void 5381 pmap_init(void) 5382 { 5383 5384 /* 5385 * Set the available memory vars - These do not map to real memory 5386 * addresses and cannot as the physical memory is fragmented. 5387 * They are used by ps for %mem calculations. 5388 * One could argue whether this should be the entire memory or just 5389 * the memory that is useable in a user process. 5390 */ 5391 avail_start = ptoa(vm_physmem[0].start); 5392 avail_end = ptoa(vm_physmem[vm_nphysseg - 1].end); 5393 5394 /* 5395 * Now we need to free enough pv_entry structures to allow us to get 5396 * the kmem_map/kmem_object allocated and inited (done after this 5397 * function is finished). to do this we allocate one bootstrap page out 5398 * of kernel_map and use it to provide an initial pool of pv_entry 5399 * structures. we never free this page. 5400 */ 5401 pool_setlowat(&pmap_pv_pool, 5402 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5403 5404 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5405 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5406 UVM_KMF_WIRED|UVM_KMF_ZERO); 5407 5408 pmap_initialized = true; 5409 } 5410 5411 static vaddr_t last_bootstrap_page = 0; 5412 static void *free_bootstrap_pages = NULL; 5413 5414 static void * 5415 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5416 { 5417 extern void *pool_page_alloc(struct pool *, int); 5418 vaddr_t new_page; 5419 void *rv; 5420 5421 if (pmap_initialized) 5422 return (pool_page_alloc(pp, flags)); 5423 5424 if (free_bootstrap_pages) { 5425 rv = free_bootstrap_pages; 5426 free_bootstrap_pages = *((void **)rv); 5427 return (rv); 5428 } 5429 5430 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5431 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5432 5433 KASSERT(new_page > last_bootstrap_page); 5434 last_bootstrap_page = new_page; 5435 return ((void *)new_page); 5436 } 5437 5438 static void 5439 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5440 { 5441 extern void pool_page_free(struct pool *, void *); 5442 5443 if ((vaddr_t)v <= last_bootstrap_page) { 5444 *((void **)v) = free_bootstrap_pages; 5445 free_bootstrap_pages = v; 5446 return; 5447 } 5448 5449 if (pmap_initialized) { 5450 pool_page_free(pp, v); 5451 return; 5452 } 5453 } 5454 5455 /* 5456 * pmap_postinit() 5457 * 5458 * This routine is called after the vm and kmem subsystems have been 5459 * initialised. This allows the pmap code to perform any initialisation 5460 * that can only be done one the memory allocation is in place. 5461 */ 5462 void 5463 pmap_postinit(void) 5464 { 5465 extern paddr_t physical_start, physical_end; 5466 struct l2_bucket *l2b; 5467 struct l1_ttable *l1; 5468 struct pglist plist; 5469 struct vm_page *m; 5470 pd_entry_t *pl1pt; 5471 pt_entry_t *ptep, pte; 5472 vaddr_t va, eva; 5473 u_int loop, needed; 5474 int error; 5475 5476 pool_cache_setlowat(&pmap_l2ptp_cache, 5477 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5478 pool_cache_setlowat(&pmap_l2dtable_cache, 5479 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5480 5481 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5482 needed -= 1; 5483 5484 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5485 5486 for (loop = 0; loop < needed; loop++, l1++) { 5487 /* Allocate a L1 page table */ 5488 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5489 if (va == 0) 5490 panic("Cannot allocate L1 KVM"); 5491 5492 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5493 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5494 if (error) 5495 panic("Cannot allocate L1 physical pages"); 5496 5497 m = TAILQ_FIRST(&plist); 5498 eva = va + L1_TABLE_SIZE; 5499 pl1pt = (pd_entry_t *)va; 5500 5501 while (m && va < eva) { 5502 paddr_t pa = VM_PAGE_TO_PHYS(m); 5503 5504 pmap_kenter_pa(va, pa, 5505 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5506 5507 /* 5508 * Make sure the L1 descriptor table is mapped 5509 * with the cache-mode set to write-through. 5510 */ 5511 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5512 KDASSERT(l2b != NULL); 5513 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5514 pte = *ptep; 5515 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5516 *ptep = pte; 5517 PTE_SYNC(ptep); 5518 cpu_tlb_flushD_SE(va); 5519 5520 va += PAGE_SIZE; 5521 m = TAILQ_NEXT(m, pageq.queue); 5522 } 5523 5524 #ifdef DIAGNOSTIC 5525 if (m) 5526 panic("pmap_alloc_l1pt: pglist not empty"); 5527 #endif /* DIAGNOSTIC */ 5528 5529 pmap_init_l1(l1, pl1pt); 5530 } 5531 5532 #ifdef DEBUG 5533 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5534 needed); 5535 #endif 5536 } 5537 5538 /* 5539 * Note that the following routines are used by board-specific initialisation 5540 * code to configure the initial kernel page tables. 5541 * 5542 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5543 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5544 * behaviour of the old pmap, and provides an easy migration path for 5545 * initial bring-up of the new pmap on existing ports. Fortunately, 5546 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5547 * will be deprecated. 5548 * 5549 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5550 * tables. 5551 */ 5552 5553 /* 5554 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5555 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5556 * find them as necessary. 5557 * 5558 * Note that the data on this list MUST remain valid after initarm() returns, 5559 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5560 */ 5561 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5562 5563 static vaddr_t 5564 kernel_pt_lookup(paddr_t pa) 5565 { 5566 pv_addr_t *pv; 5567 5568 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5569 #ifndef ARM32_NEW_VM_LAYOUT 5570 if (pv->pv_pa == (pa & ~PGOFSET)) 5571 return (pv->pv_va | (pa & PGOFSET)); 5572 #else 5573 if (pv->pv_pa == pa) 5574 return (pv->pv_va); 5575 #endif 5576 } 5577 return (0); 5578 } 5579 5580 /* 5581 * pmap_map_section: 5582 * 5583 * Create a single section mapping. 5584 */ 5585 void 5586 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5587 { 5588 pd_entry_t *pde = (pd_entry_t *) l1pt; 5589 pd_entry_t fl; 5590 5591 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5592 5593 switch (cache) { 5594 case PTE_NOCACHE: 5595 default: 5596 fl = 0; 5597 break; 5598 5599 case PTE_CACHE: 5600 fl = pte_l1_s_cache_mode; 5601 break; 5602 5603 case PTE_PAGETABLE: 5604 fl = pte_l1_s_cache_mode_pt; 5605 break; 5606 } 5607 5608 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5609 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5610 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5611 } 5612 5613 /* 5614 * pmap_map_entry: 5615 * 5616 * Create a single page mapping. 5617 */ 5618 void 5619 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5620 { 5621 pd_entry_t *pde = (pd_entry_t *) l1pt; 5622 pt_entry_t fl; 5623 pt_entry_t *pte; 5624 5625 KASSERT(((va | pa) & PGOFSET) == 0); 5626 5627 switch (cache) { 5628 case PTE_NOCACHE: 5629 default: 5630 fl = 0; 5631 break; 5632 5633 case PTE_CACHE: 5634 fl = pte_l2_s_cache_mode; 5635 break; 5636 5637 case PTE_PAGETABLE: 5638 fl = pte_l2_s_cache_mode_pt; 5639 break; 5640 } 5641 5642 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5643 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5644 5645 #ifndef ARM32_NEW_VM_LAYOUT 5646 pte = (pt_entry_t *) 5647 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5648 #else 5649 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5650 #endif 5651 if (pte == NULL) 5652 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5653 5654 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5655 #ifndef ARM32_NEW_VM_LAYOUT 5656 pte += (va >> PGSHIFT) & 0x3ff; 5657 #else 5658 pte += l2pte_index(va); 5659 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5660 #endif 5661 *pte = fl; 5662 PTE_SYNC(pte); 5663 } 5664 5665 /* 5666 * pmap_link_l2pt: 5667 * 5668 * Link the L2 page table specified by "l2pv" into the L1 5669 * page table at the slot for "va". 5670 */ 5671 void 5672 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5673 { 5674 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5675 u_int slot = va >> L1_S_SHIFT; 5676 5677 #ifndef ARM32_NEW_VM_LAYOUT 5678 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5679 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5680 #endif 5681 5682 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5683 5684 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5685 #ifdef ARM32_NEW_VM_LAYOUT 5686 PTE_SYNC(&pde[slot]); 5687 #else 5688 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5689 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5690 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5691 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5692 #endif 5693 5694 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5695 } 5696 5697 /* 5698 * pmap_map_chunk: 5699 * 5700 * Map a chunk of memory using the most efficient mappings 5701 * possible (section, large page, small page) into the 5702 * provided L1 and L2 tables at the specified virtual address. 5703 */ 5704 vsize_t 5705 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5706 int prot, int cache) 5707 { 5708 pd_entry_t *pde = (pd_entry_t *) l1pt; 5709 pt_entry_t *pte, f1, f2s, f2l; 5710 vsize_t resid; 5711 int i; 5712 5713 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5714 5715 if (l1pt == 0) 5716 panic("pmap_map_chunk: no L1 table provided"); 5717 5718 #ifdef VERBOSE_INIT_ARM 5719 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5720 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5721 #endif 5722 5723 switch (cache) { 5724 case PTE_NOCACHE: 5725 default: 5726 f1 = 0; 5727 f2l = 0; 5728 f2s = 0; 5729 break; 5730 5731 case PTE_CACHE: 5732 f1 = pte_l1_s_cache_mode; 5733 f2l = pte_l2_l_cache_mode; 5734 f2s = pte_l2_s_cache_mode; 5735 break; 5736 5737 case PTE_PAGETABLE: 5738 f1 = pte_l1_s_cache_mode_pt; 5739 f2l = pte_l2_l_cache_mode_pt; 5740 f2s = pte_l2_s_cache_mode_pt; 5741 break; 5742 } 5743 5744 size = resid; 5745 5746 while (resid > 0) { 5747 /* See if we can use a section mapping. */ 5748 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5749 #ifdef VERBOSE_INIT_ARM 5750 printf("S"); 5751 #endif 5752 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5753 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5754 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5755 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5756 va += L1_S_SIZE; 5757 pa += L1_S_SIZE; 5758 resid -= L1_S_SIZE; 5759 continue; 5760 } 5761 5762 /* 5763 * Ok, we're going to use an L2 table. Make sure 5764 * one is actually in the corresponding L1 slot 5765 * for the current VA. 5766 */ 5767 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5768 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5769 5770 #ifndef ARM32_NEW_VM_LAYOUT 5771 pte = (pt_entry_t *) 5772 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5773 #else 5774 pte = (pt_entry_t *) kernel_pt_lookup( 5775 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5776 #endif 5777 if (pte == NULL) 5778 panic("pmap_map_chunk: can't find L2 table for VA" 5779 "0x%08lx", va); 5780 5781 /* See if we can use a L2 large page mapping. */ 5782 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5783 #ifdef VERBOSE_INIT_ARM 5784 printf("L"); 5785 #endif 5786 for (i = 0; i < 16; i++) { 5787 #ifndef ARM32_NEW_VM_LAYOUT 5788 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5789 L2_L_PROTO | pa | 5790 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5791 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5792 #else 5793 pte[l2pte_index(va) + i] = 5794 L2_L_PROTO | pa | 5795 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5796 PTE_SYNC(&pte[l2pte_index(va) + i]); 5797 #endif 5798 } 5799 va += L2_L_SIZE; 5800 pa += L2_L_SIZE; 5801 resid -= L2_L_SIZE; 5802 continue; 5803 } 5804 5805 /* Use a small page mapping. */ 5806 #ifdef VERBOSE_INIT_ARM 5807 printf("P"); 5808 #endif 5809 #ifndef ARM32_NEW_VM_LAYOUT 5810 pte[(va >> PGSHIFT) & 0x3ff] = 5811 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5812 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5813 #else 5814 pte[l2pte_index(va)] = 5815 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5816 PTE_SYNC(&pte[l2pte_index(va)]); 5817 #endif 5818 va += PAGE_SIZE; 5819 pa += PAGE_SIZE; 5820 resid -= PAGE_SIZE; 5821 } 5822 #ifdef VERBOSE_INIT_ARM 5823 printf("\n"); 5824 #endif 5825 return (size); 5826 } 5827 5828 /********************** Static device map routines ***************************/ 5829 5830 static const struct pmap_devmap *pmap_devmap_table; 5831 5832 /* 5833 * Register the devmap table. This is provided in case early console 5834 * initialization needs to register mappings created by bootstrap code 5835 * before pmap_devmap_bootstrap() is called. 5836 */ 5837 void 5838 pmap_devmap_register(const struct pmap_devmap *table) 5839 { 5840 5841 pmap_devmap_table = table; 5842 } 5843 5844 /* 5845 * Map all of the static regions in the devmap table, and remember 5846 * the devmap table so other parts of the kernel can look up entries 5847 * later. 5848 */ 5849 void 5850 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5851 { 5852 int i; 5853 5854 pmap_devmap_table = table; 5855 5856 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5857 #ifdef VERBOSE_INIT_ARM 5858 printf("devmap: %08lx -> %08lx @ %08lx\n", 5859 pmap_devmap_table[i].pd_pa, 5860 pmap_devmap_table[i].pd_pa + 5861 pmap_devmap_table[i].pd_size - 1, 5862 pmap_devmap_table[i].pd_va); 5863 #endif 5864 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5865 pmap_devmap_table[i].pd_pa, 5866 pmap_devmap_table[i].pd_size, 5867 pmap_devmap_table[i].pd_prot, 5868 pmap_devmap_table[i].pd_cache); 5869 } 5870 } 5871 5872 const struct pmap_devmap * 5873 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5874 { 5875 uint64_t endpa; 5876 int i; 5877 5878 if (pmap_devmap_table == NULL) 5879 return (NULL); 5880 5881 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5882 5883 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5884 if (pa >= pmap_devmap_table[i].pd_pa && 5885 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5886 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5887 return (&pmap_devmap_table[i]); 5888 } 5889 5890 return (NULL); 5891 } 5892 5893 const struct pmap_devmap * 5894 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5895 { 5896 int i; 5897 5898 if (pmap_devmap_table == NULL) 5899 return (NULL); 5900 5901 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5902 if (va >= pmap_devmap_table[i].pd_va && 5903 va + size - 1 <= pmap_devmap_table[i].pd_va + 5904 pmap_devmap_table[i].pd_size - 1) 5905 return (&pmap_devmap_table[i]); 5906 } 5907 5908 return (NULL); 5909 } 5910 5911 /********************** PTE initialization routines **************************/ 5912 5913 /* 5914 * These routines are called when the CPU type is identified to set up 5915 * the PTE prototypes, cache modes, etc. 5916 * 5917 * The variables are always here, just in case modules need to reference 5918 * them (though, they shouldn't). 5919 */ 5920 5921 pt_entry_t pte_l1_s_cache_mode; 5922 pt_entry_t pte_l1_s_cache_mode_pt; 5923 pt_entry_t pte_l1_s_cache_mask; 5924 5925 pt_entry_t pte_l2_l_cache_mode; 5926 pt_entry_t pte_l2_l_cache_mode_pt; 5927 pt_entry_t pte_l2_l_cache_mask; 5928 5929 pt_entry_t pte_l2_s_cache_mode; 5930 pt_entry_t pte_l2_s_cache_mode_pt; 5931 pt_entry_t pte_l2_s_cache_mask; 5932 5933 pt_entry_t pte_l1_s_prot_u; 5934 pt_entry_t pte_l1_s_prot_w; 5935 pt_entry_t pte_l1_s_prot_ro; 5936 pt_entry_t pte_l1_s_prot_mask; 5937 5938 pt_entry_t pte_l2_s_prot_u; 5939 pt_entry_t pte_l2_s_prot_w; 5940 pt_entry_t pte_l2_s_prot_ro; 5941 pt_entry_t pte_l2_s_prot_mask; 5942 5943 pt_entry_t pte_l2_l_prot_u; 5944 pt_entry_t pte_l2_l_prot_w; 5945 pt_entry_t pte_l2_l_prot_ro; 5946 pt_entry_t pte_l2_l_prot_mask; 5947 5948 pt_entry_t pte_l1_s_proto; 5949 pt_entry_t pte_l1_c_proto; 5950 pt_entry_t pte_l2_s_proto; 5951 5952 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5953 void (*pmap_zero_page_func)(paddr_t); 5954 5955 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5956 void 5957 pmap_pte_init_generic(void) 5958 { 5959 5960 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5961 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5962 5963 pte_l2_l_cache_mode = L2_B|L2_C; 5964 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5965 5966 pte_l2_s_cache_mode = L2_B|L2_C; 5967 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5968 5969 /* 5970 * If we have a write-through cache, set B and C. If 5971 * we have a write-back cache, then we assume setting 5972 * only C will make those pages write-through. 5973 */ 5974 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5975 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5976 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5977 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5978 } else { 5979 #if ARM_MMU_V6 > 1 5980 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5981 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5982 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5983 #else 5984 pte_l1_s_cache_mode_pt = L1_S_C; 5985 pte_l2_l_cache_mode_pt = L2_C; 5986 pte_l2_s_cache_mode_pt = L2_C; 5987 #endif 5988 } 5989 5990 pte_l1_s_prot_u = L1_S_PROT_U_generic; 5991 pte_l1_s_prot_w = L1_S_PROT_W_generic; 5992 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 5993 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 5994 5995 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5996 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5997 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 5998 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5999 6000 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6001 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6002 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6003 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6004 6005 pte_l1_s_proto = L1_S_PROTO_generic; 6006 pte_l1_c_proto = L1_C_PROTO_generic; 6007 pte_l2_s_proto = L2_S_PROTO_generic; 6008 6009 pmap_copy_page_func = pmap_copy_page_generic; 6010 pmap_zero_page_func = pmap_zero_page_generic; 6011 } 6012 6013 #if defined(CPU_ARM8) 6014 void 6015 pmap_pte_init_arm8(void) 6016 { 6017 6018 /* 6019 * ARM8 is compatible with generic, but we need to use 6020 * the page tables uncached. 6021 */ 6022 pmap_pte_init_generic(); 6023 6024 pte_l1_s_cache_mode_pt = 0; 6025 pte_l2_l_cache_mode_pt = 0; 6026 pte_l2_s_cache_mode_pt = 0; 6027 } 6028 #endif /* CPU_ARM8 */ 6029 6030 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6031 void 6032 pmap_pte_init_arm9(void) 6033 { 6034 6035 /* 6036 * ARM9 is compatible with generic, but we want to use 6037 * write-through caching for now. 6038 */ 6039 pmap_pte_init_generic(); 6040 6041 pte_l1_s_cache_mode = L1_S_C; 6042 pte_l2_l_cache_mode = L2_C; 6043 pte_l2_s_cache_mode = L2_C; 6044 6045 pte_l1_s_cache_mode_pt = L1_S_C; 6046 pte_l2_l_cache_mode_pt = L2_C; 6047 pte_l2_s_cache_mode_pt = L2_C; 6048 } 6049 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6050 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6051 6052 #if defined(CPU_ARM10) 6053 void 6054 pmap_pte_init_arm10(void) 6055 { 6056 6057 /* 6058 * ARM10 is compatible with generic, but we want to use 6059 * write-through caching for now. 6060 */ 6061 pmap_pte_init_generic(); 6062 6063 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6064 pte_l2_l_cache_mode = L2_B | L2_C; 6065 pte_l2_s_cache_mode = L2_B | L2_C; 6066 6067 pte_l1_s_cache_mode_pt = L1_S_C; 6068 pte_l2_l_cache_mode_pt = L2_C; 6069 pte_l2_s_cache_mode_pt = L2_C; 6070 6071 } 6072 #endif /* CPU_ARM10 */ 6073 6074 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6075 void 6076 pmap_pte_init_arm11(void) 6077 { 6078 6079 /* 6080 * ARM11 is compatible with generic, but we want to use 6081 * write-through caching for now. 6082 */ 6083 pmap_pte_init_generic(); 6084 6085 pte_l1_s_cache_mode = L1_S_C; 6086 pte_l2_l_cache_mode = L2_C; 6087 pte_l2_s_cache_mode = L2_C; 6088 6089 pte_l1_s_cache_mode_pt = L1_S_C; 6090 pte_l2_l_cache_mode_pt = L2_C; 6091 pte_l2_s_cache_mode_pt = L2_C; 6092 } 6093 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6094 6095 #if ARM_MMU_SA1 == 1 6096 void 6097 pmap_pte_init_sa1(void) 6098 { 6099 6100 /* 6101 * The StrongARM SA-1 cache does not have a write-through 6102 * mode. So, do the generic initialization, then reset 6103 * the page table cache mode to B=1,C=1, and note that 6104 * the PTEs need to be sync'd. 6105 */ 6106 pmap_pte_init_generic(); 6107 6108 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6109 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6110 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6111 6112 pmap_needs_pte_sync = 1; 6113 } 6114 #endif /* ARM_MMU_SA1 == 1*/ 6115 6116 #if ARM_MMU_XSCALE == 1 6117 #if (ARM_NMMUS > 1) 6118 static u_int xscale_use_minidata; 6119 #endif 6120 6121 void 6122 pmap_pte_init_xscale(void) 6123 { 6124 uint32_t auxctl; 6125 int write_through = 0; 6126 6127 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6128 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6129 6130 pte_l2_l_cache_mode = L2_B|L2_C; 6131 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6132 6133 pte_l2_s_cache_mode = L2_B|L2_C; 6134 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6135 6136 pte_l1_s_cache_mode_pt = L1_S_C; 6137 pte_l2_l_cache_mode_pt = L2_C; 6138 pte_l2_s_cache_mode_pt = L2_C; 6139 6140 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6141 /* 6142 * The XScale core has an enhanced mode where writes that 6143 * miss the cache cause a cache line to be allocated. This 6144 * is significantly faster than the traditional, write-through 6145 * behavior of this case. 6146 */ 6147 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6148 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6149 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6150 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6151 6152 #ifdef XSCALE_CACHE_WRITE_THROUGH 6153 /* 6154 * Some versions of the XScale core have various bugs in 6155 * their cache units, the work-around for which is to run 6156 * the cache in write-through mode. Unfortunately, this 6157 * has a major (negative) impact on performance. So, we 6158 * go ahead and run fast-and-loose, in the hopes that we 6159 * don't line up the planets in a way that will trip the 6160 * bugs. 6161 * 6162 * However, we give you the option to be slow-but-correct. 6163 */ 6164 write_through = 1; 6165 #elif defined(XSCALE_CACHE_WRITE_BACK) 6166 /* force write back cache mode */ 6167 write_through = 0; 6168 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6169 /* 6170 * Intel PXA2[15]0 processors are known to have a bug in 6171 * write-back cache on revision 4 and earlier (stepping 6172 * A[01] and B[012]). Fixed for C0 and later. 6173 */ 6174 { 6175 uint32_t id, type; 6176 6177 id = cpufunc_id(); 6178 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6179 6180 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6181 if ((id & CPU_ID_REVISION_MASK) < 5) { 6182 /* write through for stepping A0-1 and B0-2 */ 6183 write_through = 1; 6184 } 6185 } 6186 } 6187 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6188 6189 if (write_through) { 6190 pte_l1_s_cache_mode = L1_S_C; 6191 pte_l2_l_cache_mode = L2_C; 6192 pte_l2_s_cache_mode = L2_C; 6193 } 6194 6195 #if (ARM_NMMUS > 1) 6196 xscale_use_minidata = 1; 6197 #endif 6198 6199 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6200 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6201 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6202 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6203 6204 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6205 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6206 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6207 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6208 6209 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6210 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6211 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6212 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6213 6214 pte_l1_s_proto = L1_S_PROTO_xscale; 6215 pte_l1_c_proto = L1_C_PROTO_xscale; 6216 pte_l2_s_proto = L2_S_PROTO_xscale; 6217 6218 pmap_copy_page_func = pmap_copy_page_xscale; 6219 pmap_zero_page_func = pmap_zero_page_xscale; 6220 6221 /* 6222 * Disable ECC protection of page table access, for now. 6223 */ 6224 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6225 auxctl &= ~XSCALE_AUXCTL_P; 6226 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6227 } 6228 6229 /* 6230 * xscale_setup_minidata: 6231 * 6232 * Set up the mini-data cache clean area. We require the 6233 * caller to allocate the right amount of physically and 6234 * virtually contiguous space. 6235 */ 6236 void 6237 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6238 { 6239 extern vaddr_t xscale_minidata_clean_addr; 6240 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6241 pd_entry_t *pde = (pd_entry_t *) l1pt; 6242 pt_entry_t *pte; 6243 vsize_t size; 6244 uint32_t auxctl; 6245 6246 xscale_minidata_clean_addr = va; 6247 6248 /* Round it to page size. */ 6249 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6250 6251 for (; size != 0; 6252 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6253 #ifndef ARM32_NEW_VM_LAYOUT 6254 pte = (pt_entry_t *) 6255 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6256 #else 6257 pte = (pt_entry_t *) kernel_pt_lookup( 6258 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6259 #endif 6260 if (pte == NULL) 6261 panic("xscale_setup_minidata: can't find L2 table for " 6262 "VA 0x%08lx", va); 6263 #ifndef ARM32_NEW_VM_LAYOUT 6264 pte[(va >> PGSHIFT) & 0x3ff] = 6265 #else 6266 pte[l2pte_index(va)] = 6267 #endif 6268 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6269 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6270 } 6271 6272 /* 6273 * Configure the mini-data cache for write-back with 6274 * read/write-allocate. 6275 * 6276 * NOTE: In order to reconfigure the mini-data cache, we must 6277 * make sure it contains no valid data! In order to do that, 6278 * we must issue a global data cache invalidate command! 6279 * 6280 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6281 * THIS IS VERY IMPORTANT! 6282 */ 6283 6284 /* Invalidate data and mini-data. */ 6285 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6286 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6287 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6288 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6289 } 6290 6291 /* 6292 * Change the PTEs for the specified kernel mappings such that they 6293 * will use the mini data cache instead of the main data cache. 6294 */ 6295 void 6296 pmap_uarea(vaddr_t va) 6297 { 6298 struct l2_bucket *l2b; 6299 pt_entry_t *ptep, *sptep, pte; 6300 vaddr_t next_bucket, eva; 6301 6302 #if (ARM_NMMUS > 1) 6303 if (xscale_use_minidata == 0) 6304 return; 6305 #endif 6306 6307 eva = va + USPACE; 6308 6309 while (va < eva) { 6310 next_bucket = L2_NEXT_BUCKET(va); 6311 if (next_bucket > eva) 6312 next_bucket = eva; 6313 6314 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6315 KDASSERT(l2b != NULL); 6316 6317 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6318 6319 while (va < next_bucket) { 6320 pte = *ptep; 6321 if (!l2pte_minidata(pte)) { 6322 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6323 cpu_tlb_flushD_SE(va); 6324 *ptep = pte & ~L2_B; 6325 } 6326 ptep++; 6327 va += PAGE_SIZE; 6328 } 6329 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6330 } 6331 cpu_cpwait(); 6332 } 6333 #endif /* ARM_MMU_XSCALE == 1 */ 6334 6335 #if ARM_MMU_V7 == 1 6336 void 6337 pmap_pte_init_armv7(void) 6338 { 6339 /* 6340 * The ARMv7-A MMU is mostly compatible with generic. If the 6341 * AP field is zero, that now means "no access" rather than 6342 * read-only. The prototypes are a little different because of 6343 * the XN bit. 6344 */ 6345 pmap_pte_init_generic(); 6346 6347 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6348 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6349 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6350 6351 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6352 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6353 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6354 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6355 6356 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6357 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6358 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6359 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6360 6361 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6362 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6363 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6364 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6365 6366 pte_l1_s_proto = L1_S_PROTO_armv7; 6367 pte_l1_c_proto = L1_C_PROTO_armv7; 6368 pte_l2_s_proto = L2_S_PROTO_armv7; 6369 } 6370 #endif /* ARM_MMU_V7 */ 6371 6372 /* 6373 * return the PA of the current L1 table, for use when handling a crash dump 6374 */ 6375 uint32_t pmap_kernel_L1_addr(void) 6376 { 6377 return pmap_kernel()->pm_l1->l1_physaddr; 6378 } 6379 6380 #if defined(DDB) 6381 /* 6382 * A couple of ddb-callable functions for dumping pmaps 6383 */ 6384 void pmap_dump_all(void); 6385 void pmap_dump(pmap_t); 6386 6387 void 6388 pmap_dump_all(void) 6389 { 6390 pmap_t pm; 6391 6392 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6393 if (pm == pmap_kernel()) 6394 continue; 6395 pmap_dump(pm); 6396 printf("\n"); 6397 } 6398 } 6399 6400 static pt_entry_t ncptes[64]; 6401 static void pmap_dump_ncpg(pmap_t); 6402 6403 void 6404 pmap_dump(pmap_t pm) 6405 { 6406 struct l2_dtable *l2; 6407 struct l2_bucket *l2b; 6408 pt_entry_t *ptep, pte; 6409 vaddr_t l2_va, l2b_va, va; 6410 int i, j, k, occ, rows = 0; 6411 6412 if (pm == pmap_kernel()) 6413 printf("pmap_kernel (%p): ", pm); 6414 else 6415 printf("user pmap (%p): ", pm); 6416 6417 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6418 6419 l2_va = 0; 6420 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6421 l2 = pm->pm_l2[i]; 6422 6423 if (l2 == NULL || l2->l2_occupancy == 0) 6424 continue; 6425 6426 l2b_va = l2_va; 6427 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6428 l2b = &l2->l2_bucket[j]; 6429 6430 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6431 continue; 6432 6433 ptep = l2b->l2b_kva; 6434 6435 for (k = 0; k < 256 && ptep[k] == 0; k++) 6436 ; 6437 6438 k &= ~63; 6439 occ = l2b->l2b_occupancy; 6440 va = l2b_va + (k * 4096); 6441 for (; k < 256; k++, va += 0x1000) { 6442 char ch = ' '; 6443 if ((k % 64) == 0) { 6444 if ((rows % 8) == 0) { 6445 printf( 6446 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6447 } 6448 printf("%08lx: ", va); 6449 } 6450 6451 ncptes[k & 63] = 0; 6452 pte = ptep[k]; 6453 if (pte == 0) { 6454 ch = '.'; 6455 } else { 6456 occ--; 6457 switch (pte & 0x0c) { 6458 case 0x00: 6459 ch = 'D'; /* No cache No buff */ 6460 break; 6461 case 0x04: 6462 ch = 'B'; /* No cache buff */ 6463 break; 6464 case 0x08: 6465 if (pte & 0x40) 6466 ch = 'm'; 6467 else 6468 ch = 'C'; /* Cache No buff */ 6469 break; 6470 case 0x0c: 6471 ch = 'F'; /* Cache Buff */ 6472 break; 6473 } 6474 6475 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6476 ch += 0x20; 6477 6478 if ((pte & 0xc) == 0) 6479 ncptes[k & 63] = pte; 6480 } 6481 6482 if ((k % 64) == 63) { 6483 rows++; 6484 printf("%c\n", ch); 6485 pmap_dump_ncpg(pm); 6486 if (occ == 0) 6487 break; 6488 } else 6489 printf("%c", ch); 6490 } 6491 } 6492 } 6493 } 6494 6495 static void 6496 pmap_dump_ncpg(pmap_t pm) 6497 { 6498 struct vm_page *pg; 6499 struct vm_page_md *md; 6500 struct pv_entry *pv; 6501 int i; 6502 6503 for (i = 0; i < 63; i++) { 6504 if (ncptes[i] == 0) 6505 continue; 6506 6507 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6508 if (pg == NULL) 6509 continue; 6510 md = VM_PAGE_TO_MD(pg); 6511 6512 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6513 VM_PAGE_TO_PHYS(pg), 6514 md->krw_mappings, md->kro_mappings, 6515 md->urw_mappings, md->uro_mappings); 6516 6517 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6518 printf(" %c va 0x%08lx, flags 0x%x\n", 6519 (pm == pv->pv_pmap) ? '*' : ' ', 6520 pv->pv_va, pv->pv_flags); 6521 } 6522 } 6523 } 6524 #endif 6525 6526 #ifdef PMAP_STEAL_MEMORY 6527 void 6528 pmap_boot_pageadd(pv_addr_t *newpv) 6529 { 6530 pv_addr_t *pv, *npv; 6531 6532 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6533 if (newpv->pv_pa < pv->pv_va) { 6534 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6535 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6536 newpv->pv_size += pv->pv_size; 6537 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6538 } 6539 pv = NULL; 6540 } else { 6541 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6542 pv = npv) { 6543 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6544 KASSERT(pv->pv_pa < newpv->pv_pa); 6545 if (newpv->pv_pa > npv->pv_pa) 6546 continue; 6547 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6548 pv->pv_size += newpv->pv_size; 6549 return; 6550 } 6551 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6552 break; 6553 newpv->pv_size += npv->pv_size; 6554 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6555 SLIST_REMOVE_AFTER(newpv, pv_list); 6556 return; 6557 } 6558 } 6559 } 6560 6561 if (pv) { 6562 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6563 } else { 6564 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6565 } 6566 } 6567 6568 void 6569 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6570 pv_addr_t *rpv) 6571 { 6572 pv_addr_t *pv, **pvp; 6573 struct vm_physseg *ps; 6574 size_t i; 6575 6576 KASSERT(amount & PGOFSET); 6577 KASSERT((mask & PGOFSET) == 0); 6578 KASSERT((match & PGOFSET) == 0); 6579 KASSERT(amount != 0); 6580 6581 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6582 (pv = *pvp) != NULL; 6583 pvp = &SLIST_NEXT(pv, pv_list)) { 6584 pv_addr_t *newpv; 6585 psize_t off; 6586 /* 6587 * If this entry is too small to satify the request... 6588 */ 6589 KASSERT(pv->pv_size > 0); 6590 if (pv->pv_size < amount) 6591 continue; 6592 6593 for (off = 0; off <= mask; off += PAGE_SIZE) { 6594 if (((pv->pv_pa + off) & mask) == match 6595 && off + amount <= pv->pv_size) 6596 break; 6597 } 6598 if (off > mask) 6599 continue; 6600 6601 rpv->pv_va = pv->pv_va + off; 6602 rpv->pv_pa = pv->pv_pa + off; 6603 rpv->pv_size = amount; 6604 pv->pv_size -= amount; 6605 if (pv->pv_size == 0) { 6606 KASSERT(off == 0); 6607 KASSERT((vaddr_t) pv == rpv->pv_va); 6608 *pvp = SLIST_NEXT(pv, pv_list); 6609 } else if (off == 0) { 6610 KASSERT((vaddr_t) pv == rpv->pv_va); 6611 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6612 *newpv = *pv; 6613 newpv->pv_pa += amount; 6614 newpv->pv_va += amount; 6615 *pvp = newpv; 6616 } else if (off < pv->pv_size) { 6617 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6618 *newpv = *pv; 6619 newpv->pv_size -= off; 6620 newpv->pv_pa += off + amount; 6621 newpv->pv_va += off + amount; 6622 6623 SLIST_NEXT(pv, pv_list) = newpv; 6624 pv->pv_size = off; 6625 } else { 6626 KASSERT((vaddr_t) pv != rpv->pv_va); 6627 } 6628 memset((void *)rpv->pv_va, 0, amount); 6629 return; 6630 } 6631 6632 if (vm_nphysseg == 0) 6633 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6634 6635 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6636 (pv = *pvp) != NULL; 6637 pvp = &SLIST_NEXT(pv, pv_list)) { 6638 if (SLIST_NEXT(pv, pv_list) == NULL) 6639 break; 6640 } 6641 KASSERT(mask == 0); 6642 for (ps = vm_physmem, i = 0; i < vm_nphysseg; ps++, i++) { 6643 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6644 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6645 rpv->pv_va = pv->pv_va; 6646 rpv->pv_pa = pv->pv_pa; 6647 rpv->pv_size = amount; 6648 *pvp = NULL; 6649 pmap_map_chunk(kernel_l1pt.pv_va, 6650 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6651 ptoa(ps->avail_start), 6652 amount - pv->pv_size, 6653 VM_PROT_READ|VM_PROT_WRITE, 6654 PTE_CACHE); 6655 ps->avail_start += atop(amount - pv->pv_size); 6656 /* 6657 * If we consumed the entire physseg, remove it. 6658 */ 6659 if (ps->avail_start == ps->avail_end) { 6660 for (--vm_nphysseg; i < vm_nphysseg; i++, ps++) 6661 ps[0] = ps[1]; 6662 } 6663 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6664 return; 6665 } 6666 } 6667 6668 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6669 } 6670 6671 vaddr_t 6672 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6673 { 6674 pv_addr_t pv; 6675 6676 pmap_boot_pagealloc(size, 0, 0, &pv); 6677 6678 return pv.pv_va; 6679 } 6680 #endif /* PMAP_STEAL_MEMORY */ 6681 6682 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6683 { 6684 sysctl_createv(clog, 0, NULL, NULL, 6685 CTLFLAG_PERMANENT, 6686 CTLTYPE_NODE, "machdep", NULL, 6687 NULL, 0, NULL, 0, 6688 CTL_MACHDEP, CTL_EOL); 6689 6690 sysctl_createv(clog, 0, NULL, NULL, 6691 CTLFLAG_PERMANENT, 6692 CTLTYPE_INT, "kmpages", 6693 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6694 NULL, 0, &pmap_kmpages, 0, 6695 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6696 } 6697
Indexes created Mon Sep 29 18:09:42 GMT 2025