pmap.c revision 1.221
1 /* $NetBSD: pmap.c,v 1.221 2011/03/10 07:47:14 bsh Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/pool.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <machine/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.221 2011/03/10 07:47:14 bsh Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 static struct pmap kernel_pmap_store; 258 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 #ifdef PMAPCOUNTERS 308 #define PMAP_EVCNT_INITIALIZER(name) \ 309 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 310 311 #ifdef PMAP_CACHE_VIPT 312 static struct evcnt pmap_ev_vac_clean_one = 313 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 314 static struct evcnt pmap_ev_vac_flush_one = 315 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_lots = 317 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 318 static struct evcnt pmap_ev_vac_flush_lots2 = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 324 325 static struct evcnt pmap_ev_vac_color_new = 326 PMAP_EVCNT_INITIALIZER("new page color"); 327 static struct evcnt pmap_ev_vac_color_reuse = 328 PMAP_EVCNT_INITIALIZER("ok first page color"); 329 static struct evcnt pmap_ev_vac_color_ok = 330 PMAP_EVCNT_INITIALIZER("ok page color"); 331 static struct evcnt pmap_ev_vac_color_blind = 332 PMAP_EVCNT_INITIALIZER("blind page color"); 333 static struct evcnt pmap_ev_vac_color_change = 334 PMAP_EVCNT_INITIALIZER("change page color"); 335 static struct evcnt pmap_ev_vac_color_erase = 336 PMAP_EVCNT_INITIALIZER("erase page color"); 337 static struct evcnt pmap_ev_vac_color_none = 338 PMAP_EVCNT_INITIALIZER("no page color"); 339 static struct evcnt pmap_ev_vac_color_restore = 340 PMAP_EVCNT_INITIALIZER("restore page color"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 350 #endif 351 352 static struct evcnt pmap_ev_mappings = 353 PMAP_EVCNT_INITIALIZER("pages mapped"); 354 static struct evcnt pmap_ev_unmappings = 355 PMAP_EVCNT_INITIALIZER("pages unmapped"); 356 static struct evcnt pmap_ev_remappings = 357 PMAP_EVCNT_INITIALIZER("pages remapped"); 358 359 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 360 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 362 363 static struct evcnt pmap_ev_kernel_mappings = 364 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 365 static struct evcnt pmap_ev_kernel_unmappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 367 static struct evcnt pmap_ev_kernel_remappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 373 374 static struct evcnt pmap_ev_kenter_mappings = 375 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 376 static struct evcnt pmap_ev_kenter_unmappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 378 static struct evcnt pmap_ev_kenter_remappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 380 static struct evcnt pmap_ev_pt_mappings = 381 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 382 383 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 387 388 #ifdef PMAP_CACHE_VIPT 389 static struct evcnt pmap_ev_exec_mappings = 390 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 391 static struct evcnt pmap_ev_exec_cached = 392 PMAP_EVCNT_INITIALIZER("exec pages cached"); 393 394 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 396 397 static struct evcnt pmap_ev_exec_synced = 398 PMAP_EVCNT_INITIALIZER("exec pages synced"); 399 static struct evcnt pmap_ev_exec_synced_map = 400 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 401 static struct evcnt pmap_ev_exec_synced_unmap = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 403 static struct evcnt pmap_ev_exec_synced_remap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 405 static struct evcnt pmap_ev_exec_synced_clearbit = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 407 static struct evcnt pmap_ev_exec_synced_kremove = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 409 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 416 417 static struct evcnt pmap_ev_exec_discarded_unmap = 418 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 419 static struct evcnt pmap_ev_exec_discarded_zero = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 421 static struct evcnt pmap_ev_exec_discarded_copy = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 423 static struct evcnt pmap_ev_exec_discarded_page_protect = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 425 static struct evcnt pmap_ev_exec_discarded_clearbit = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 427 static struct evcnt pmap_ev_exec_discarded_kremove = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 429 430 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 436 #endif /* PMAP_CACHE_VIPT */ 437 438 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 439 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 440 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 441 442 EVCNT_ATTACH_STATIC(pmap_ev_updates); 443 EVCNT_ATTACH_STATIC(pmap_ev_collects); 444 EVCNT_ATTACH_STATIC(pmap_ev_activations); 445 446 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 447 #else 448 #define PMAPCOUNT(x) ((void)0) 449 #endif 450 451 /* 452 * pmap copy/zero page, and mem(5) hook point 453 */ 454 static pt_entry_t *csrc_pte, *cdst_pte; 455 static vaddr_t csrcp, cdstp; 456 vaddr_t memhook; /* used by mem.c */ 457 kmutex_t memlock; /* used by mem.c */ 458 void *zeropage; /* used by mem.c */ 459 extern void *msgbufaddr; 460 int pmap_kmpages; 461 /* 462 * Flag to indicate if pmap_init() has done its thing 463 */ 464 bool pmap_initialized; 465 466 /* 467 * Misc. locking data structures 468 */ 469 470 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 471 static struct lock pmap_main_lock; 472 473 #define PMAP_MAP_TO_HEAD_LOCK() \ 474 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 475 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 476 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 477 #define PMAP_HEAD_TO_MAP_LOCK() \ 478 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 479 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 480 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 481 #else 482 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 483 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 484 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 485 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 486 #endif 487 488 #define pmap_acquire_pmap_lock(pm) \ 489 do { \ 490 if ((pm) != pmap_kernel()) \ 491 mutex_enter(&(pm)->pm_lock); \ 492 } while (/*CONSTCOND*/0) 493 494 #define pmap_release_pmap_lock(pm) \ 495 do { \ 496 if ((pm) != pmap_kernel()) \ 497 mutex_exit(&(pm)->pm_lock); \ 498 } while (/*CONSTCOND*/0) 499 500 501 /* 502 * Metadata for L1 translation tables. 503 */ 504 struct l1_ttable { 505 /* Entry on the L1 Table list */ 506 SLIST_ENTRY(l1_ttable) l1_link; 507 508 /* Entry on the L1 Least Recently Used list */ 509 TAILQ_ENTRY(l1_ttable) l1_lru; 510 511 /* Track how many domains are allocated from this L1 */ 512 volatile u_int l1_domain_use_count; 513 514 /* 515 * A free-list of domain numbers for this L1. 516 * We avoid using ffs() and a bitmap to track domains since ffs() 517 * is slow on ARM. 518 */ 519 u_int8_t l1_domain_first; 520 u_int8_t l1_domain_free[PMAP_DOMAINS]; 521 522 /* Physical address of this L1 page table */ 523 paddr_t l1_physaddr; 524 525 /* KVA of this L1 page table */ 526 pd_entry_t *l1_kva; 527 }; 528 529 /* 530 * Convert a virtual address into its L1 table index. That is, the 531 * index used to locate the L2 descriptor table pointer in an L1 table. 532 * This is basically used to index l1->l1_kva[]. 533 * 534 * Each L2 descriptor table represents 1MB of VA space. 535 */ 536 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 537 538 /* 539 * L1 Page Tables are tracked using a Least Recently Used list. 540 * - New L1s are allocated from the HEAD. 541 * - Freed L1s are added to the TAIl. 542 * - Recently accessed L1s (where an 'access' is some change to one of 543 * the userland pmaps which owns this L1) are moved to the TAIL. 544 */ 545 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 546 static struct simplelock l1_lru_lock; 547 548 /* 549 * A list of all L1 tables 550 */ 551 static SLIST_HEAD(, l1_ttable) l1_list; 552 553 /* 554 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 555 * 556 * This is normally 16MB worth L2 page descriptors for any given pmap. 557 * Reference counts are maintained for L2 descriptors so they can be 558 * freed when empty. 559 */ 560 struct l2_dtable { 561 /* The number of L2 page descriptors allocated to this l2_dtable */ 562 u_int l2_occupancy; 563 564 /* List of L2 page descriptors */ 565 struct l2_bucket { 566 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 567 paddr_t l2b_phys; /* Physical address of same */ 568 u_short l2b_l1idx; /* This L2 table's L1 index */ 569 u_short l2b_occupancy; /* How many active descriptors */ 570 } l2_bucket[L2_BUCKET_SIZE]; 571 }; 572 573 /* 574 * Given an L1 table index, calculate the corresponding l2_dtable index 575 * and bucket index within the l2_dtable. 576 */ 577 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 578 (L2_SIZE - 1)) 579 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 580 581 /* 582 * Given a virtual address, this macro returns the 583 * virtual address required to drop into the next L2 bucket. 584 */ 585 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 586 587 /* 588 * L2 allocation. 589 */ 590 #define pmap_alloc_l2_dtable() \ 591 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 592 #define pmap_free_l2_dtable(l2) \ 593 pool_cache_put(&pmap_l2dtable_cache, (l2)) 594 #define pmap_alloc_l2_ptp(pap) \ 595 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 596 PR_NOWAIT, (pap))) 597 598 /* 599 * We try to map the page tables write-through, if possible. However, not 600 * all CPUs have a write-through cache mode, so on those we have to sync 601 * the cache when we frob page tables. 602 * 603 * We try to evaluate this at compile time, if possible. However, it's 604 * not always possible to do that, hence this run-time var. 605 */ 606 int pmap_needs_pte_sync; 607 608 /* 609 * Real definition of pv_entry. 610 */ 611 struct pv_entry { 612 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 613 pmap_t pv_pmap; /* pmap where mapping lies */ 614 vaddr_t pv_va; /* virtual address for mapping */ 615 u_int pv_flags; /* flags */ 616 }; 617 618 /* 619 * Macro to determine if a mapping might be resident in the 620 * instruction cache and/or TLB 621 */ 622 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 623 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 624 625 /* 626 * Macro to determine if a mapping might be resident in the 627 * data cache and/or TLB 628 */ 629 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 630 631 /* 632 * Local prototypes 633 */ 634 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 635 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 636 pt_entry_t **); 637 static bool pmap_is_current(pmap_t); 638 static bool pmap_is_cached(pmap_t); 639 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 640 pmap_t, vaddr_t, u_int); 641 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 642 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 643 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 644 u_int, u_int); 645 646 static void pmap_pinit(pmap_t); 647 static int pmap_pmap_ctor(void *, void *, int); 648 649 static void pmap_alloc_l1(pmap_t); 650 static void pmap_free_l1(pmap_t); 651 static void pmap_use_l1(pmap_t); 652 653 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 654 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 655 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 656 static int pmap_l2ptp_ctor(void *, void *, int); 657 static int pmap_l2dtable_ctor(void *, void *, int); 658 659 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 660 #ifdef PMAP_CACHE_VIVT 661 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 662 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 663 #endif 664 665 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 666 #ifdef PMAP_CACHE_VIVT 667 static int pmap_clean_page(struct pv_entry *, bool); 668 #endif 669 #ifdef PMAP_CACHE_VIPT 670 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 671 enum pmap_flush_op { 672 PMAP_FLUSH_PRIMARY, 673 PMAP_FLUSH_SECONDARY, 674 PMAP_CLEAN_PRIMARY 675 }; 676 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 677 #endif 678 static void pmap_page_remove(struct vm_page_md *, paddr_t); 679 680 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 681 static vaddr_t kernel_pt_lookup(paddr_t); 682 683 684 /* 685 * External function prototypes 686 */ 687 extern void bzero_page(vaddr_t); 688 extern void bcopy_page(vaddr_t, vaddr_t); 689 690 /* 691 * Misc variables 692 */ 693 vaddr_t virtual_avail; 694 vaddr_t virtual_end; 695 vaddr_t pmap_curmaxkvaddr; 696 697 paddr_t avail_start; 698 paddr_t avail_end; 699 700 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 701 pv_addr_t kernelpages; 702 pv_addr_t kernel_l1pt; 703 pv_addr_t systempage; 704 705 /* Function to set the debug level of the pmap code */ 706 707 #ifdef PMAP_DEBUG 708 void 709 pmap_debug(int level) 710 { 711 pmap_debug_level = level; 712 printf("pmap_debug: level=%d\n", pmap_debug_level); 713 } 714 #endif /* PMAP_DEBUG */ 715 716 /* 717 * A bunch of routines to conditionally flush the caches/TLB depending 718 * on whether the specified pmap actually needs to be flushed at any 719 * given time. 720 */ 721 static inline void 722 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 723 { 724 725 if (pm->pm_cstate.cs_tlb_id) 726 cpu_tlb_flushID_SE(va); 727 } 728 729 static inline void 730 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 731 { 732 733 if (pm->pm_cstate.cs_tlb_d) 734 cpu_tlb_flushD_SE(va); 735 } 736 737 static inline void 738 pmap_tlb_flushID(pmap_t pm) 739 { 740 741 if (pm->pm_cstate.cs_tlb_id) { 742 cpu_tlb_flushID(); 743 pm->pm_cstate.cs_tlb = 0; 744 } 745 } 746 747 static inline void 748 pmap_tlb_flushD(pmap_t pm) 749 { 750 751 if (pm->pm_cstate.cs_tlb_d) { 752 cpu_tlb_flushD(); 753 pm->pm_cstate.cs_tlb_d = 0; 754 } 755 } 756 757 #ifdef PMAP_CACHE_VIVT 758 static inline void 759 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 760 { 761 if (pm->pm_cstate.cs_cache_id) { 762 cpu_idcache_wbinv_range(va, len); 763 } 764 } 765 766 static inline void 767 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 768 bool do_inv, bool rd_only) 769 { 770 771 if (pm->pm_cstate.cs_cache_d) { 772 if (do_inv) { 773 if (rd_only) 774 cpu_dcache_inv_range(va, len); 775 else 776 cpu_dcache_wbinv_range(va, len); 777 } else 778 if (!rd_only) 779 cpu_dcache_wb_range(va, len); 780 } 781 } 782 783 static inline void 784 pmap_idcache_wbinv_all(pmap_t pm) 785 { 786 if (pm->pm_cstate.cs_cache_id) { 787 cpu_idcache_wbinv_all(); 788 pm->pm_cstate.cs_cache = 0; 789 } 790 } 791 792 static inline void 793 pmap_dcache_wbinv_all(pmap_t pm) 794 { 795 if (pm->pm_cstate.cs_cache_d) { 796 cpu_dcache_wbinv_all(); 797 pm->pm_cstate.cs_cache_d = 0; 798 } 799 } 800 #endif /* PMAP_CACHE_VIVT */ 801 802 static inline bool 803 pmap_is_current(pmap_t pm) 804 { 805 806 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 807 return true; 808 809 return false; 810 } 811 812 static inline bool 813 pmap_is_cached(pmap_t pm) 814 { 815 816 if (pm == pmap_kernel() || pmap_recent_user == NULL || 817 pmap_recent_user == pm) 818 return (true); 819 820 return false; 821 } 822 823 /* 824 * PTE_SYNC_CURRENT: 825 * 826 * Make sure the pte is written out to RAM. 827 * We need to do this for one of two cases: 828 * - We're dealing with the kernel pmap 829 * - There is no pmap active in the cache/tlb. 830 * - The specified pmap is 'active' in the cache/tlb. 831 */ 832 #ifdef PMAP_INCLUDE_PTE_SYNC 833 #define PTE_SYNC_CURRENT(pm, ptep) \ 834 do { \ 835 if (PMAP_NEEDS_PTE_SYNC && \ 836 pmap_is_cached(pm)) \ 837 PTE_SYNC(ptep); \ 838 } while (/*CONSTCOND*/0) 839 #else 840 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 841 #endif 842 843 /* 844 * main pv_entry manipulation functions: 845 * pmap_enter_pv: enter a mapping onto a vm_page list 846 * pmap_remove_pv: remove a mappiing from a vm_page list 847 * 848 * NOTE: pmap_enter_pv expects to lock the pvh itself 849 * pmap_remove_pv expects te caller to lock the pvh before calling 850 */ 851 852 /* 853 * pmap_enter_pv: enter a mapping onto a vm_page lst 854 * 855 * => caller should hold the proper lock on pmap_main_lock 856 * => caller should have pmap locked 857 * => we will gain the lock on the vm_page and allocate the new pv_entry 858 * => caller should adjust ptp's wire_count before calling 859 * => caller should not adjust pmap's wire_count 860 */ 861 static void 862 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 863 vaddr_t va, u_int flags) 864 { 865 struct pv_entry **pvp; 866 867 NPDEBUG(PDB_PVDUMP, 868 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 869 870 pv->pv_pmap = pm; 871 pv->pv_va = va; 872 pv->pv_flags = flags; 873 874 simple_lock(&md->pvh_slock); /* lock vm_page */ 875 pvp = &SLIST_FIRST(&md->pvh_list); 876 #ifdef PMAP_CACHE_VIPT 877 /* 878 * Insert unmanaged entries, writeable first, at the head of 879 * the pv list. 880 */ 881 if (__predict_true((flags & PVF_KENTRY) == 0)) { 882 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 883 pvp = &SLIST_NEXT(*pvp, pv_link); 884 } else if ((flags & PVF_WRITE) == 0) { 885 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 886 pvp = &SLIST_NEXT(*pvp, pv_link); 887 } 888 #endif 889 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 890 *pvp = pv; /* ... locked list */ 891 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 892 #ifdef PMAP_CACHE_VIPT 893 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 894 md->pvh_attrs |= PVF_KMOD; 895 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 896 md->pvh_attrs |= PVF_DIRTY; 897 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 898 #endif 899 if (pm == pmap_kernel()) { 900 PMAPCOUNT(kernel_mappings); 901 if (flags & PVF_WRITE) 902 md->krw_mappings++; 903 else 904 md->kro_mappings++; 905 } else { 906 if (flags & PVF_WRITE) 907 md->urw_mappings++; 908 else 909 md->uro_mappings++; 910 } 911 912 #ifdef PMAP_CACHE_VIPT 913 /* 914 * If this is an exec mapping and its the first exec mapping 915 * for this page, make sure to sync the I-cache. 916 */ 917 if (PV_IS_EXEC_P(flags)) { 918 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 919 pmap_syncicache_page(md, pa); 920 PMAPCOUNT(exec_synced_map); 921 } 922 PMAPCOUNT(exec_mappings); 923 } 924 #endif 925 926 PMAPCOUNT(mappings); 927 simple_unlock(&md->pvh_slock); /* unlock, done! */ 928 929 if (pv->pv_flags & PVF_WIRED) 930 ++pm->pm_stats.wired_count; 931 } 932 933 /* 934 * 935 * pmap_find_pv: Find a pv entry 936 * 937 * => caller should hold lock on vm_page 938 */ 939 static inline struct pv_entry * 940 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 941 { 942 struct pv_entry *pv; 943 944 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 945 if (pm == pv->pv_pmap && va == pv->pv_va) 946 break; 947 } 948 949 return (pv); 950 } 951 952 /* 953 * pmap_remove_pv: try to remove a mapping from a pv_list 954 * 955 * => caller should hold proper lock on pmap_main_lock 956 * => pmap should be locked 957 * => caller should hold lock on vm_page [so that attrs can be adjusted] 958 * => caller should adjust ptp's wire_count and free PTP if needed 959 * => caller should NOT adjust pmap's wire_count 960 * => we return the removed pv 961 */ 962 static struct pv_entry * 963 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 964 { 965 struct pv_entry *pv, **prevptr; 966 967 NPDEBUG(PDB_PVDUMP, 968 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 969 970 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 971 pv = *prevptr; 972 973 while (pv) { 974 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 975 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 976 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 977 if (pv->pv_flags & PVF_WIRED) { 978 --pm->pm_stats.wired_count; 979 } 980 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 981 if (pm == pmap_kernel()) { 982 PMAPCOUNT(kernel_unmappings); 983 if (pv->pv_flags & PVF_WRITE) 984 md->krw_mappings--; 985 else 986 md->kro_mappings--; 987 } else { 988 if (pv->pv_flags & PVF_WRITE) 989 md->urw_mappings--; 990 else 991 md->uro_mappings--; 992 } 993 994 PMAPCOUNT(unmappings); 995 #ifdef PMAP_CACHE_VIPT 996 if (!(pv->pv_flags & PVF_WRITE)) 997 break; 998 /* 999 * If this page has had an exec mapping, then if 1000 * this was the last mapping, discard the contents, 1001 * otherwise sync the i-cache for this page. 1002 */ 1003 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1004 if (SLIST_EMPTY(&md->pvh_list)) { 1005 md->pvh_attrs &= ~PVF_EXEC; 1006 PMAPCOUNT(exec_discarded_unmap); 1007 } else { 1008 pmap_syncicache_page(md, pa); 1009 PMAPCOUNT(exec_synced_unmap); 1010 } 1011 } 1012 #endif /* PMAP_CACHE_VIPT */ 1013 break; 1014 } 1015 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1016 pv = *prevptr; /* advance */ 1017 } 1018 1019 #ifdef PMAP_CACHE_VIPT 1020 /* 1021 * If we no longer have a WRITEABLE KENTRY at the head of list, 1022 * clear the KMOD attribute from the page. 1023 */ 1024 if (SLIST_FIRST(&md->pvh_list) == NULL 1025 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1026 md->pvh_attrs &= ~PVF_KMOD; 1027 1028 /* 1029 * If this was a writeable page and there are no more writeable 1030 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1031 * the contents to memory. 1032 */ 1033 if (md->krw_mappings + md->urw_mappings == 0) 1034 md->pvh_attrs &= ~PVF_WRITE; 1035 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1036 #endif /* PMAP_CACHE_VIPT */ 1037 1038 return(pv); /* return removed pv */ 1039 } 1040 1041 /* 1042 * 1043 * pmap_modify_pv: Update pv flags 1044 * 1045 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1046 * => caller should NOT adjust pmap's wire_count 1047 * => caller must call pmap_vac_me_harder() if writable status of a page 1048 * may have changed. 1049 * => we return the old flags 1050 * 1051 * Modify a physical-virtual mapping in the pv table 1052 */ 1053 static u_int 1054 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1055 u_int clr_mask, u_int set_mask) 1056 { 1057 struct pv_entry *npv; 1058 u_int flags, oflags; 1059 1060 KASSERT((clr_mask & PVF_KENTRY) == 0); 1061 KASSERT((set_mask & PVF_KENTRY) == 0); 1062 1063 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1064 return (0); 1065 1066 NPDEBUG(PDB_PVDUMP, 1067 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1068 1069 /* 1070 * There is at least one VA mapping this page. 1071 */ 1072 1073 if (clr_mask & (PVF_REF | PVF_MOD)) { 1074 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1075 #ifdef PMAP_CACHE_VIPT 1076 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1077 md->pvh_attrs |= PVF_DIRTY; 1078 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1079 #endif 1080 } 1081 1082 oflags = npv->pv_flags; 1083 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1084 1085 if ((flags ^ oflags) & PVF_WIRED) { 1086 if (flags & PVF_WIRED) 1087 ++pm->pm_stats.wired_count; 1088 else 1089 --pm->pm_stats.wired_count; 1090 } 1091 1092 if ((flags ^ oflags) & PVF_WRITE) { 1093 if (pm == pmap_kernel()) { 1094 if (flags & PVF_WRITE) { 1095 md->krw_mappings++; 1096 md->kro_mappings--; 1097 } else { 1098 md->kro_mappings++; 1099 md->krw_mappings--; 1100 } 1101 } else { 1102 if (flags & PVF_WRITE) { 1103 md->urw_mappings++; 1104 md->uro_mappings--; 1105 } else { 1106 md->uro_mappings++; 1107 md->urw_mappings--; 1108 } 1109 } 1110 } 1111 #ifdef PMAP_CACHE_VIPT 1112 if (md->urw_mappings + md->krw_mappings == 0) 1113 md->pvh_attrs &= ~PVF_WRITE; 1114 /* 1115 * We have two cases here: the first is from enter_pv (new exec 1116 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1117 * Since in latter, pmap_enter_pv won't do anything, we just have 1118 * to do what pmap_remove_pv would do. 1119 */ 1120 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1121 || (PV_IS_EXEC_P(md->pvh_attrs) 1122 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1123 pmap_syncicache_page(md, pa); 1124 PMAPCOUNT(exec_synced_remap); 1125 } 1126 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1127 #endif 1128 1129 PMAPCOUNT(remappings); 1130 1131 return (oflags); 1132 } 1133 1134 /* 1135 * Allocate an L1 translation table for the specified pmap. 1136 * This is called at pmap creation time. 1137 */ 1138 static void 1139 pmap_alloc_l1(pmap_t pm) 1140 { 1141 struct l1_ttable *l1; 1142 u_int8_t domain; 1143 1144 /* 1145 * Remove the L1 at the head of the LRU list 1146 */ 1147 simple_lock(&l1_lru_lock); 1148 l1 = TAILQ_FIRST(&l1_lru_list); 1149 KDASSERT(l1 != NULL); 1150 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1151 1152 /* 1153 * Pick the first available domain number, and update 1154 * the link to the next number. 1155 */ 1156 domain = l1->l1_domain_first; 1157 l1->l1_domain_first = l1->l1_domain_free[domain]; 1158 1159 /* 1160 * If there are still free domain numbers in this L1, 1161 * put it back on the TAIL of the LRU list. 1162 */ 1163 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1164 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1165 1166 simple_unlock(&l1_lru_lock); 1167 1168 /* 1169 * Fix up the relevant bits in the pmap structure 1170 */ 1171 pm->pm_l1 = l1; 1172 pm->pm_domain = domain; 1173 } 1174 1175 /* 1176 * Free an L1 translation table. 1177 * This is called at pmap destruction time. 1178 */ 1179 static void 1180 pmap_free_l1(pmap_t pm) 1181 { 1182 struct l1_ttable *l1 = pm->pm_l1; 1183 1184 simple_lock(&l1_lru_lock); 1185 1186 /* 1187 * If this L1 is currently on the LRU list, remove it. 1188 */ 1189 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1190 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1191 1192 /* 1193 * Free up the domain number which was allocated to the pmap 1194 */ 1195 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1196 l1->l1_domain_first = pm->pm_domain; 1197 l1->l1_domain_use_count--; 1198 1199 /* 1200 * The L1 now must have at least 1 free domain, so add 1201 * it back to the LRU list. If the use count is zero, 1202 * put it at the head of the list, otherwise it goes 1203 * to the tail. 1204 */ 1205 if (l1->l1_domain_use_count == 0) 1206 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1207 else 1208 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1209 1210 simple_unlock(&l1_lru_lock); 1211 } 1212 1213 static inline void 1214 pmap_use_l1(pmap_t pm) 1215 { 1216 struct l1_ttable *l1; 1217 1218 /* 1219 * Do nothing if we're in interrupt context. 1220 * Access to an L1 by the kernel pmap must not affect 1221 * the LRU list. 1222 */ 1223 if (cpu_intr_p() || pm == pmap_kernel()) 1224 return; 1225 1226 l1 = pm->pm_l1; 1227 1228 /* 1229 * If the L1 is not currently on the LRU list, just return 1230 */ 1231 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1232 return; 1233 1234 simple_lock(&l1_lru_lock); 1235 1236 /* 1237 * Check the use count again, now that we've acquired the lock 1238 */ 1239 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1240 simple_unlock(&l1_lru_lock); 1241 return; 1242 } 1243 1244 /* 1245 * Move the L1 to the back of the LRU list 1246 */ 1247 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1248 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1249 1250 simple_unlock(&l1_lru_lock); 1251 } 1252 1253 /* 1254 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1255 * 1256 * Free an L2 descriptor table. 1257 */ 1258 static inline void 1259 #ifndef PMAP_INCLUDE_PTE_SYNC 1260 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1261 #else 1262 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1263 #endif 1264 { 1265 #ifdef PMAP_INCLUDE_PTE_SYNC 1266 #ifdef PMAP_CACHE_VIVT 1267 /* 1268 * Note: With a write-back cache, we may need to sync this 1269 * L2 table before re-using it. 1270 * This is because it may have belonged to a non-current 1271 * pmap, in which case the cache syncs would have been 1272 * skipped for the pages that were being unmapped. If the 1273 * L2 table were then to be immediately re-allocated to 1274 * the *current* pmap, it may well contain stale mappings 1275 * which have not yet been cleared by a cache write-back 1276 * and so would still be visible to the mmu. 1277 */ 1278 if (need_sync) 1279 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1280 #endif /* PMAP_CACHE_VIVT */ 1281 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1282 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1283 } 1284 1285 /* 1286 * Returns a pointer to the L2 bucket associated with the specified pmap 1287 * and VA, or NULL if no L2 bucket exists for the address. 1288 */ 1289 static inline struct l2_bucket * 1290 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1291 { 1292 struct l2_dtable *l2; 1293 struct l2_bucket *l2b; 1294 u_short l1idx; 1295 1296 l1idx = L1_IDX(va); 1297 1298 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1299 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1300 return (NULL); 1301 1302 return (l2b); 1303 } 1304 1305 /* 1306 * Returns a pointer to the L2 bucket associated with the specified pmap 1307 * and VA. 1308 * 1309 * If no L2 bucket exists, perform the necessary allocations to put an L2 1310 * bucket/page table in place. 1311 * 1312 * Note that if a new L2 bucket/page was allocated, the caller *must* 1313 * increment the bucket occupancy counter appropriately *before* 1314 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1315 * the bucket/page in the meantime. 1316 */ 1317 static struct l2_bucket * 1318 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1319 { 1320 struct l2_dtable *l2; 1321 struct l2_bucket *l2b; 1322 u_short l1idx; 1323 1324 l1idx = L1_IDX(va); 1325 1326 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1327 /* 1328 * No mapping at this address, as there is 1329 * no entry in the L1 table. 1330 * Need to allocate a new l2_dtable. 1331 */ 1332 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1333 return (NULL); 1334 1335 /* 1336 * Link it into the parent pmap 1337 */ 1338 pm->pm_l2[L2_IDX(l1idx)] = l2; 1339 } 1340 1341 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1342 1343 /* 1344 * Fetch pointer to the L2 page table associated with the address. 1345 */ 1346 if (l2b->l2b_kva == NULL) { 1347 pt_entry_t *ptep; 1348 1349 /* 1350 * No L2 page table has been allocated. Chances are, this 1351 * is because we just allocated the l2_dtable, above. 1352 */ 1353 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1354 /* 1355 * Oops, no more L2 page tables available at this 1356 * time. We may need to deallocate the l2_dtable 1357 * if we allocated a new one above. 1358 */ 1359 if (l2->l2_occupancy == 0) { 1360 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1361 pmap_free_l2_dtable(l2); 1362 } 1363 return (NULL); 1364 } 1365 1366 l2->l2_occupancy++; 1367 l2b->l2b_kva = ptep; 1368 l2b->l2b_l1idx = l1idx; 1369 } 1370 1371 return (l2b); 1372 } 1373 1374 /* 1375 * One or more mappings in the specified L2 descriptor table have just been 1376 * invalidated. 1377 * 1378 * Garbage collect the metadata and descriptor table itself if necessary. 1379 * 1380 * The pmap lock must be acquired when this is called (not necessary 1381 * for the kernel pmap). 1382 */ 1383 static void 1384 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1385 { 1386 struct l2_dtable *l2; 1387 pd_entry_t *pl1pd, l1pd; 1388 pt_entry_t *ptep; 1389 u_short l1idx; 1390 1391 KDASSERT(count <= l2b->l2b_occupancy); 1392 1393 /* 1394 * Update the bucket's reference count according to how many 1395 * PTEs the caller has just invalidated. 1396 */ 1397 l2b->l2b_occupancy -= count; 1398 1399 /* 1400 * Note: 1401 * 1402 * Level 2 page tables allocated to the kernel pmap are never freed 1403 * as that would require checking all Level 1 page tables and 1404 * removing any references to the Level 2 page table. See also the 1405 * comment elsewhere about never freeing bootstrap L2 descriptors. 1406 * 1407 * We make do with just invalidating the mapping in the L2 table. 1408 * 1409 * This isn't really a big deal in practice and, in fact, leads 1410 * to a performance win over time as we don't need to continually 1411 * alloc/free. 1412 */ 1413 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1414 return; 1415 1416 /* 1417 * There are no more valid mappings in this level 2 page table. 1418 * Go ahead and NULL-out the pointer in the bucket, then 1419 * free the page table. 1420 */ 1421 l1idx = l2b->l2b_l1idx; 1422 ptep = l2b->l2b_kva; 1423 l2b->l2b_kva = NULL; 1424 1425 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1426 1427 /* 1428 * If the L1 slot matches the pmap's domain 1429 * number, then invalidate it. 1430 */ 1431 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1432 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1433 *pl1pd = 0; 1434 PTE_SYNC(pl1pd); 1435 } 1436 1437 /* 1438 * Release the L2 descriptor table back to the pool cache. 1439 */ 1440 #ifndef PMAP_INCLUDE_PTE_SYNC 1441 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1442 #else 1443 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1444 #endif 1445 1446 /* 1447 * Update the reference count in the associated l2_dtable 1448 */ 1449 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1450 if (--l2->l2_occupancy > 0) 1451 return; 1452 1453 /* 1454 * There are no more valid mappings in any of the Level 1 1455 * slots managed by this l2_dtable. Go ahead and NULL-out 1456 * the pointer in the parent pmap and free the l2_dtable. 1457 */ 1458 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1459 pmap_free_l2_dtable(l2); 1460 } 1461 1462 /* 1463 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1464 * structures. 1465 */ 1466 static int 1467 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1468 { 1469 #ifndef PMAP_INCLUDE_PTE_SYNC 1470 struct l2_bucket *l2b; 1471 pt_entry_t *ptep, pte; 1472 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1473 1474 /* 1475 * The mappings for these page tables were initially made using 1476 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1477 * mode will not be right for page table mappings. To avoid 1478 * polluting the pmap_kenter_pa() code with a special case for 1479 * page tables, we simply fix up the cache-mode here if it's not 1480 * correct. 1481 */ 1482 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1483 KDASSERT(l2b != NULL); 1484 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1485 pte = *ptep; 1486 1487 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1488 /* 1489 * Page tables must have the cache-mode set to Write-Thru. 1490 */ 1491 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1492 PTE_SYNC(ptep); 1493 cpu_tlb_flushD_SE(va); 1494 cpu_cpwait(); 1495 } 1496 #endif 1497 1498 memset(v, 0, L2_TABLE_SIZE_REAL); 1499 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1500 return (0); 1501 } 1502 1503 static int 1504 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1505 { 1506 1507 memset(v, 0, sizeof(struct l2_dtable)); 1508 return (0); 1509 } 1510 1511 static int 1512 pmap_pmap_ctor(void *arg, void *v, int flags) 1513 { 1514 1515 memset(v, 0, sizeof(struct pmap)); 1516 return (0); 1517 } 1518 1519 static void 1520 pmap_pinit(pmap_t pm) 1521 { 1522 struct l2_bucket *l2b; 1523 1524 if (vector_page < KERNEL_BASE) { 1525 /* 1526 * Map the vector page. 1527 */ 1528 pmap_enter(pm, vector_page, systempage.pv_pa, 1529 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1530 pmap_update(pm); 1531 1532 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1533 l2b = pmap_get_l2_bucket(pm, vector_page); 1534 KDASSERT(l2b != NULL); 1535 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1536 L1_C_DOM(pm->pm_domain); 1537 } else 1538 pm->pm_pl1vec = NULL; 1539 } 1540 1541 #ifdef PMAP_CACHE_VIVT 1542 /* 1543 * Since we have a virtually indexed cache, we may need to inhibit caching if 1544 * there is more than one mapping and at least one of them is writable. 1545 * Since we purge the cache on every context switch, we only need to check for 1546 * other mappings within the same pmap, or kernel_pmap. 1547 * This function is also called when a page is unmapped, to possibly reenable 1548 * caching on any remaining mappings. 1549 * 1550 * The code implements the following logic, where: 1551 * 1552 * KW = # of kernel read/write pages 1553 * KR = # of kernel read only pages 1554 * UW = # of user read/write pages 1555 * UR = # of user read only pages 1556 * 1557 * KC = kernel mapping is cacheable 1558 * UC = user mapping is cacheable 1559 * 1560 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1561 * +--------------------------------------------- 1562 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1563 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1564 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1565 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1566 */ 1567 1568 static const int pmap_vac_flags[4][4] = { 1569 {-1, 0, 0, PVF_KNC}, 1570 {0, 0, PVF_NC, PVF_NC}, 1571 {0, PVF_NC, PVF_NC, PVF_NC}, 1572 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1573 }; 1574 1575 static inline int 1576 pmap_get_vac_flags(const struct vm_page_md *md) 1577 { 1578 int kidx, uidx; 1579 1580 kidx = 0; 1581 if (md->kro_mappings || md->krw_mappings > 1) 1582 kidx |= 1; 1583 if (md->krw_mappings) 1584 kidx |= 2; 1585 1586 uidx = 0; 1587 if (md->uro_mappings || md->urw_mappings > 1) 1588 uidx |= 1; 1589 if (md->urw_mappings) 1590 uidx |= 2; 1591 1592 return (pmap_vac_flags[uidx][kidx]); 1593 } 1594 1595 static inline void 1596 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1597 { 1598 int nattr; 1599 1600 nattr = pmap_get_vac_flags(md); 1601 1602 if (nattr < 0) { 1603 md->pvh_attrs &= ~PVF_NC; 1604 return; 1605 } 1606 1607 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1608 return; 1609 1610 if (pm == pmap_kernel()) 1611 pmap_vac_me_kpmap(md, pa, pm, va); 1612 else 1613 pmap_vac_me_user(md, pa, pm, va); 1614 1615 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1616 } 1617 1618 static void 1619 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1620 { 1621 u_int u_cacheable, u_entries; 1622 struct pv_entry *pv; 1623 pmap_t last_pmap = pm; 1624 1625 /* 1626 * Pass one, see if there are both kernel and user pmaps for 1627 * this page. Calculate whether there are user-writable or 1628 * kernel-writable pages. 1629 */ 1630 u_cacheable = 0; 1631 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1632 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1633 u_cacheable++; 1634 } 1635 1636 u_entries = md->urw_mappings + md->uro_mappings; 1637 1638 /* 1639 * We know we have just been updating a kernel entry, so if 1640 * all user pages are already cacheable, then there is nothing 1641 * further to do. 1642 */ 1643 if (md->k_mappings == 0 && u_cacheable == u_entries) 1644 return; 1645 1646 if (u_entries) { 1647 /* 1648 * Scan over the list again, for each entry, if it 1649 * might not be set correctly, call pmap_vac_me_user 1650 * to recalculate the settings. 1651 */ 1652 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1653 /* 1654 * We know kernel mappings will get set 1655 * correctly in other calls. We also know 1656 * that if the pmap is the same as last_pmap 1657 * then we've just handled this entry. 1658 */ 1659 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1660 continue; 1661 1662 /* 1663 * If there are kernel entries and this page 1664 * is writable but non-cacheable, then we can 1665 * skip this entry also. 1666 */ 1667 if (md->k_mappings && 1668 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1669 (PVF_NC | PVF_WRITE)) 1670 continue; 1671 1672 /* 1673 * Similarly if there are no kernel-writable 1674 * entries and the page is already 1675 * read-only/cacheable. 1676 */ 1677 if (md->krw_mappings == 0 && 1678 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1679 continue; 1680 1681 /* 1682 * For some of the remaining cases, we know 1683 * that we must recalculate, but for others we 1684 * can't tell if they are correct or not, so 1685 * we recalculate anyway. 1686 */ 1687 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1688 } 1689 1690 if (md->k_mappings == 0) 1691 return; 1692 } 1693 1694 pmap_vac_me_user(md, pa, pm, va); 1695 } 1696 1697 static void 1698 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1699 { 1700 pmap_t kpmap = pmap_kernel(); 1701 struct pv_entry *pv, *npv = NULL; 1702 struct l2_bucket *l2b; 1703 pt_entry_t *ptep, pte; 1704 u_int entries = 0; 1705 u_int writable = 0; 1706 u_int cacheable_entries = 0; 1707 u_int kern_cacheable = 0; 1708 u_int other_writable = 0; 1709 1710 /* 1711 * Count mappings and writable mappings in this pmap. 1712 * Include kernel mappings as part of our own. 1713 * Keep a pointer to the first one. 1714 */ 1715 npv = NULL; 1716 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1717 /* Count mappings in the same pmap */ 1718 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1719 if (entries++ == 0) 1720 npv = pv; 1721 1722 /* Cacheable mappings */ 1723 if ((pv->pv_flags & PVF_NC) == 0) { 1724 cacheable_entries++; 1725 if (kpmap == pv->pv_pmap) 1726 kern_cacheable++; 1727 } 1728 1729 /* Writable mappings */ 1730 if (pv->pv_flags & PVF_WRITE) 1731 ++writable; 1732 } else 1733 if (pv->pv_flags & PVF_WRITE) 1734 other_writable = 1; 1735 } 1736 1737 /* 1738 * Enable or disable caching as necessary. 1739 * Note: the first entry might be part of the kernel pmap, 1740 * so we can't assume this is indicative of the state of the 1741 * other (maybe non-kpmap) entries. 1742 */ 1743 if ((entries > 1 && writable) || 1744 (entries > 0 && pm == kpmap && other_writable)) { 1745 if (cacheable_entries == 0) 1746 return; 1747 1748 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1749 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1750 (pv->pv_flags & PVF_NC)) 1751 continue; 1752 1753 pv->pv_flags |= PVF_NC; 1754 1755 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1756 KDASSERT(l2b != NULL); 1757 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1758 pte = *ptep & ~L2_S_CACHE_MASK; 1759 1760 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1761 l2pte_valid(pte)) { 1762 if (PV_BEEN_EXECD(pv->pv_flags)) { 1763 #ifdef PMAP_CACHE_VIVT 1764 pmap_idcache_wbinv_range(pv->pv_pmap, 1765 pv->pv_va, PAGE_SIZE); 1766 #endif 1767 pmap_tlb_flushID_SE(pv->pv_pmap, 1768 pv->pv_va); 1769 } else 1770 if (PV_BEEN_REFD(pv->pv_flags)) { 1771 #ifdef PMAP_CACHE_VIVT 1772 pmap_dcache_wb_range(pv->pv_pmap, 1773 pv->pv_va, PAGE_SIZE, true, 1774 (pv->pv_flags & PVF_WRITE) == 0); 1775 #endif 1776 pmap_tlb_flushD_SE(pv->pv_pmap, 1777 pv->pv_va); 1778 } 1779 } 1780 1781 *ptep = pte; 1782 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1783 } 1784 cpu_cpwait(); 1785 } else 1786 if (entries > cacheable_entries) { 1787 /* 1788 * Turn cacheing back on for some pages. If it is a kernel 1789 * page, only do so if there are no other writable pages. 1790 */ 1791 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1792 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1793 (kpmap != pv->pv_pmap || other_writable))) 1794 continue; 1795 1796 pv->pv_flags &= ~PVF_NC; 1797 1798 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1799 KDASSERT(l2b != NULL); 1800 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1801 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1802 1803 if (l2pte_valid(pte)) { 1804 if (PV_BEEN_EXECD(pv->pv_flags)) { 1805 pmap_tlb_flushID_SE(pv->pv_pmap, 1806 pv->pv_va); 1807 } else 1808 if (PV_BEEN_REFD(pv->pv_flags)) { 1809 pmap_tlb_flushD_SE(pv->pv_pmap, 1810 pv->pv_va); 1811 } 1812 } 1813 1814 *ptep = pte; 1815 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1816 } 1817 } 1818 } 1819 #endif 1820 1821 #ifdef PMAP_CACHE_VIPT 1822 static void 1823 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1824 { 1825 struct pv_entry *pv; 1826 vaddr_t tst_mask; 1827 bool bad_alias; 1828 struct l2_bucket *l2b; 1829 pt_entry_t *ptep, pte, opte; 1830 const u_int 1831 rw_mappings = md->urw_mappings + md->krw_mappings, 1832 ro_mappings = md->uro_mappings + md->kro_mappings; 1833 1834 /* do we need to do anything? */ 1835 if (arm_cache_prefer_mask == 0) 1836 return; 1837 1838 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1839 md, pm, va)); 1840 1841 KASSERT(!va || pm); 1842 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1843 1844 /* Already a conflict? */ 1845 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1846 /* just an add, things are already non-cached */ 1847 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1848 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1849 bad_alias = false; 1850 if (va) { 1851 PMAPCOUNT(vac_color_none); 1852 bad_alias = true; 1853 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1854 goto fixup; 1855 } 1856 pv = SLIST_FIRST(&md->pvh_list); 1857 /* the list can't be empty because it would be cachable */ 1858 if (md->pvh_attrs & PVF_KMPAGE) { 1859 tst_mask = md->pvh_attrs; 1860 } else { 1861 KASSERT(pv); 1862 tst_mask = pv->pv_va; 1863 pv = SLIST_NEXT(pv, pv_link); 1864 } 1865 /* 1866 * Only check for a bad alias if we have writable mappings. 1867 */ 1868 tst_mask &= arm_cache_prefer_mask; 1869 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1870 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1871 /* if there's a bad alias, stop checking. */ 1872 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1873 bad_alias = true; 1874 } 1875 md->pvh_attrs |= PVF_WRITE; 1876 if (!bad_alias) 1877 md->pvh_attrs |= PVF_DIRTY; 1878 } else { 1879 /* 1880 * We have only read-only mappings. Let's see if there 1881 * are multiple colors in use or if we mapped a KMPAGE. 1882 * If the latter, we have a bad alias. If the former, 1883 * we need to remember that. 1884 */ 1885 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1886 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1887 if (md->pvh_attrs & PVF_KMPAGE) 1888 bad_alias = true; 1889 break; 1890 } 1891 } 1892 md->pvh_attrs &= ~PVF_WRITE; 1893 /* 1894 * No KMPAGE and we exited early, so we must have 1895 * multiple color mappings. 1896 */ 1897 if (!bad_alias && pv != NULL) 1898 md->pvh_attrs |= PVF_MULTCLR; 1899 } 1900 1901 /* If no conflicting colors, set everything back to cached */ 1902 if (!bad_alias) { 1903 #ifdef DEBUG 1904 if ((md->pvh_attrs & PVF_WRITE) 1905 || ro_mappings < 2) { 1906 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1907 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1908 } 1909 #endif 1910 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1911 md->pvh_attrs |= tst_mask | PVF_COLORED; 1912 /* 1913 * Restore DIRTY bit if page is modified 1914 */ 1915 if (md->pvh_attrs & PVF_DMOD) 1916 md->pvh_attrs |= PVF_DIRTY; 1917 PMAPCOUNT(vac_color_restore); 1918 } else { 1919 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1920 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1921 } 1922 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1923 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1924 } else if (!va) { 1925 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1926 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1927 || (md->pvh_attrs & PVF_DIRTY)); 1928 if (rw_mappings == 0) { 1929 md->pvh_attrs &= ~PVF_WRITE; 1930 if (ro_mappings == 1 1931 && (md->pvh_attrs & PVF_MULTCLR)) { 1932 /* 1933 * If this is the last readonly mapping 1934 * but it doesn't match the current color 1935 * for the page, change the current color 1936 * to match this last readonly mapping. 1937 */ 1938 pv = SLIST_FIRST(&md->pvh_list); 1939 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1940 & arm_cache_prefer_mask; 1941 if (tst_mask) { 1942 md->pvh_attrs ^= tst_mask; 1943 PMAPCOUNT(vac_color_change); 1944 } 1945 } 1946 } 1947 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1948 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1949 return; 1950 } else if (!pmap_is_page_colored_p(md)) { 1951 /* not colored so we just use its color */ 1952 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1953 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1954 PMAPCOUNT(vac_color_new); 1955 md->pvh_attrs &= PAGE_SIZE - 1; 1956 md->pvh_attrs |= PVF_COLORED 1957 | (va & arm_cache_prefer_mask) 1958 | (rw_mappings > 0 ? PVF_WRITE : 0); 1959 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1960 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1961 return; 1962 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1963 bad_alias = false; 1964 if (rw_mappings > 0) { 1965 /* 1966 * We now have writeable mappings and if we have 1967 * readonly mappings in more than once color, we have 1968 * an aliasing problem. Regardless mark the page as 1969 * writeable. 1970 */ 1971 if (md->pvh_attrs & PVF_MULTCLR) { 1972 if (ro_mappings < 2) { 1973 /* 1974 * If we only have less than two 1975 * read-only mappings, just flush the 1976 * non-primary colors from the cache. 1977 */ 1978 pmap_flush_page(md, pa, 1979 PMAP_FLUSH_SECONDARY); 1980 } else { 1981 bad_alias = true; 1982 } 1983 } 1984 md->pvh_attrs |= PVF_WRITE; 1985 } 1986 /* If no conflicting colors, set everything back to cached */ 1987 if (!bad_alias) { 1988 #ifdef DEBUG 1989 if (rw_mappings > 0 1990 || (md->pvh_attrs & PMAP_KMPAGE)) { 1991 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1992 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1993 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1994 } 1995 #endif 1996 if (SLIST_EMPTY(&md->pvh_list)) 1997 PMAPCOUNT(vac_color_reuse); 1998 else 1999 PMAPCOUNT(vac_color_ok); 2000 2001 /* matching color, just return */ 2002 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2003 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2004 return; 2005 } 2006 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2007 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2008 2009 /* color conflict. evict from cache. */ 2010 2011 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2012 md->pvh_attrs &= ~PVF_COLORED; 2013 md->pvh_attrs |= PVF_NC; 2014 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2015 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2016 PMAPCOUNT(vac_color_erase); 2017 } else if (rw_mappings == 0 2018 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2019 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2020 2021 /* 2022 * If the page has dirty cache lines, clean it. 2023 */ 2024 if (md->pvh_attrs & PVF_DIRTY) 2025 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2026 2027 /* 2028 * If this is the first remapping (we know that there are no 2029 * writeable mappings), then this is a simple color change. 2030 * Otherwise this is a seconary r/o mapping, which means 2031 * we don't have to do anything. 2032 */ 2033 if (ro_mappings == 1) { 2034 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2035 md->pvh_attrs &= PAGE_SIZE - 1; 2036 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2037 PMAPCOUNT(vac_color_change); 2038 } else { 2039 PMAPCOUNT(vac_color_blind); 2040 } 2041 md->pvh_attrs |= PVF_MULTCLR; 2042 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2043 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2044 return; 2045 } else { 2046 if (rw_mappings > 0) 2047 md->pvh_attrs |= PVF_WRITE; 2048 2049 /* color conflict. evict from cache. */ 2050 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2051 2052 /* the list can't be empty because this was a enter/modify */ 2053 pv = SLIST_FIRST(&md->pvh_list); 2054 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2055 KASSERT(pv); 2056 /* 2057 * If there's only one mapped page, change color to the 2058 * page's new color and return. Restore the DIRTY bit 2059 * that was erased by pmap_flush_page. 2060 */ 2061 if (SLIST_NEXT(pv, pv_link) == NULL) { 2062 md->pvh_attrs &= PAGE_SIZE - 1; 2063 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2064 if (md->pvh_attrs & PVF_DMOD) 2065 md->pvh_attrs |= PVF_DIRTY; 2066 PMAPCOUNT(vac_color_change); 2067 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2068 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2069 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2070 return; 2071 } 2072 } 2073 bad_alias = true; 2074 md->pvh_attrs &= ~PVF_COLORED; 2075 md->pvh_attrs |= PVF_NC; 2076 PMAPCOUNT(vac_color_erase); 2077 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2078 } 2079 2080 fixup: 2081 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2082 2083 /* 2084 * Turn cacheing on/off for all pages. 2085 */ 2086 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2087 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2088 KDASSERT(l2b != NULL); 2089 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2090 opte = *ptep; 2091 pte = opte & ~L2_S_CACHE_MASK; 2092 if (bad_alias) { 2093 pv->pv_flags |= PVF_NC; 2094 } else { 2095 pv->pv_flags &= ~PVF_NC; 2096 pte |= pte_l2_s_cache_mode; 2097 } 2098 2099 if (opte == pte) /* only update is there's a change */ 2100 continue; 2101 2102 if (l2pte_valid(pte)) { 2103 if (PV_BEEN_EXECD(pv->pv_flags)) { 2104 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2105 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2106 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2107 } 2108 } 2109 2110 *ptep = pte; 2111 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2112 } 2113 } 2114 #endif /* PMAP_CACHE_VIPT */ 2115 2116 2117 /* 2118 * Modify pte bits for all ptes corresponding to the given physical address. 2119 * We use `maskbits' rather than `clearbits' because we're always passing 2120 * constants and the latter would require an extra inversion at run-time. 2121 */ 2122 static void 2123 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2124 { 2125 struct l2_bucket *l2b; 2126 struct pv_entry *pv; 2127 pt_entry_t *ptep, npte, opte; 2128 pmap_t pm; 2129 vaddr_t va; 2130 u_int oflags; 2131 #ifdef PMAP_CACHE_VIPT 2132 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2133 bool need_syncicache = false; 2134 bool did_syncicache = false; 2135 bool need_vac_me_harder = false; 2136 #endif 2137 2138 NPDEBUG(PDB_BITS, 2139 printf("pmap_clearbit: md %p mask 0x%x\n", 2140 md, maskbits)); 2141 2142 PMAP_HEAD_TO_MAP_LOCK(); 2143 simple_lock(&md->pvh_slock); 2144 2145 #ifdef PMAP_CACHE_VIPT 2146 /* 2147 * If we might want to sync the I-cache and we've modified it, 2148 * then we know we definitely need to sync or discard it. 2149 */ 2150 if (want_syncicache) 2151 need_syncicache = md->pvh_attrs & PVF_MOD; 2152 #endif 2153 /* 2154 * Clear saved attributes (modify, reference) 2155 */ 2156 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2157 2158 if (SLIST_EMPTY(&md->pvh_list)) { 2159 #ifdef PMAP_CACHE_VIPT 2160 if (need_syncicache) { 2161 /* 2162 * No one has it mapped, so just discard it. The next 2163 * exec remapping will cause it to be synced. 2164 */ 2165 md->pvh_attrs &= ~PVF_EXEC; 2166 PMAPCOUNT(exec_discarded_clearbit); 2167 } 2168 #endif 2169 simple_unlock(&md->pvh_slock); 2170 PMAP_HEAD_TO_MAP_UNLOCK(); 2171 return; 2172 } 2173 2174 /* 2175 * Loop over all current mappings setting/clearing as appropos 2176 */ 2177 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2178 va = pv->pv_va; 2179 pm = pv->pv_pmap; 2180 oflags = pv->pv_flags; 2181 /* 2182 * Kernel entries are unmanaged and as such not to be changed. 2183 */ 2184 if (oflags & PVF_KENTRY) 2185 continue; 2186 pv->pv_flags &= ~maskbits; 2187 2188 pmap_acquire_pmap_lock(pm); 2189 2190 l2b = pmap_get_l2_bucket(pm, va); 2191 KDASSERT(l2b != NULL); 2192 2193 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2194 npte = opte = *ptep; 2195 2196 NPDEBUG(PDB_BITS, 2197 printf( 2198 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2199 pv, pv->pv_pmap, pv->pv_va, oflags)); 2200 2201 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2202 #ifdef PMAP_CACHE_VIVT 2203 if ((pv->pv_flags & PVF_NC)) { 2204 /* 2205 * Entry is not cacheable: 2206 * 2207 * Don't turn caching on again if this is a 2208 * modified emulation. This would be 2209 * inconsitent with the settings created by 2210 * pmap_vac_me_harder(). Otherwise, it's safe 2211 * to re-enable cacheing. 2212 * 2213 * There's no need to call pmap_vac_me_harder() 2214 * here: all pages are losing their write 2215 * permission. 2216 */ 2217 if (maskbits & PVF_WRITE) { 2218 npte |= pte_l2_s_cache_mode; 2219 pv->pv_flags &= ~PVF_NC; 2220 } 2221 } else 2222 if (l2pte_writable_p(opte)) { 2223 /* 2224 * Entry is writable/cacheable: check if pmap 2225 * is current if it is flush it, otherwise it 2226 * won't be in the cache 2227 */ 2228 if (PV_BEEN_EXECD(oflags)) 2229 pmap_idcache_wbinv_range(pm, pv->pv_va, 2230 PAGE_SIZE); 2231 else 2232 if (PV_BEEN_REFD(oflags)) 2233 pmap_dcache_wb_range(pm, pv->pv_va, 2234 PAGE_SIZE, 2235 (maskbits & PVF_REF) != 0, false); 2236 } 2237 #endif 2238 2239 /* make the pte read only */ 2240 npte = l2pte_set_readonly(npte); 2241 2242 if (maskbits & oflags & PVF_WRITE) { 2243 /* 2244 * Keep alias accounting up to date 2245 */ 2246 if (pv->pv_pmap == pmap_kernel()) { 2247 md->krw_mappings--; 2248 md->kro_mappings++; 2249 } else { 2250 md->urw_mappings--; 2251 md->uro_mappings++; 2252 } 2253 #ifdef PMAP_CACHE_VIPT 2254 if (md->urw_mappings + md->krw_mappings == 0) 2255 md->pvh_attrs &= ~PVF_WRITE; 2256 if (want_syncicache) 2257 need_syncicache = true; 2258 need_vac_me_harder = true; 2259 #endif 2260 } 2261 } 2262 2263 if (maskbits & PVF_REF) { 2264 if ((pv->pv_flags & PVF_NC) == 0 && 2265 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2266 l2pte_valid(npte)) { 2267 #ifdef PMAP_CACHE_VIVT 2268 /* 2269 * Check npte here; we may have already 2270 * done the wbinv above, and the validity 2271 * of the PTE is the same for opte and 2272 * npte. 2273 */ 2274 /* XXXJRT need idcache_inv_range */ 2275 if (PV_BEEN_EXECD(oflags)) 2276 pmap_idcache_wbinv_range(pm, 2277 pv->pv_va, PAGE_SIZE); 2278 else 2279 if (PV_BEEN_REFD(oflags)) 2280 pmap_dcache_wb_range(pm, 2281 pv->pv_va, PAGE_SIZE, 2282 true, true); 2283 #endif 2284 } 2285 2286 /* 2287 * Make the PTE invalid so that we will take a 2288 * page fault the next time the mapping is 2289 * referenced. 2290 */ 2291 npte &= ~L2_TYPE_MASK; 2292 npte |= L2_TYPE_INV; 2293 } 2294 2295 if (npte != opte) { 2296 *ptep = npte; 2297 PTE_SYNC(ptep); 2298 /* Flush the TLB entry if a current pmap. */ 2299 if (PV_BEEN_EXECD(oflags)) 2300 pmap_tlb_flushID_SE(pm, pv->pv_va); 2301 else 2302 if (PV_BEEN_REFD(oflags)) 2303 pmap_tlb_flushD_SE(pm, pv->pv_va); 2304 } 2305 2306 pmap_release_pmap_lock(pm); 2307 2308 NPDEBUG(PDB_BITS, 2309 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2310 pm, va, opte, npte)); 2311 } 2312 2313 #ifdef PMAP_CACHE_VIPT 2314 /* 2315 * If we need to sync the I-cache and we haven't done it yet, do it. 2316 */ 2317 if (need_syncicache && !did_syncicache) { 2318 pmap_syncicache_page(md, pa); 2319 PMAPCOUNT(exec_synced_clearbit); 2320 } 2321 /* 2322 * If we are changing this to read-only, we need to call vac_me_harder 2323 * so we can change all the read-only pages to cacheable. We pretend 2324 * this as a page deletion. 2325 */ 2326 if (need_vac_me_harder) { 2327 if (md->pvh_attrs & PVF_NC) 2328 pmap_vac_me_harder(md, pa, NULL, 0); 2329 } 2330 #endif 2331 2332 simple_unlock(&md->pvh_slock); 2333 PMAP_HEAD_TO_MAP_UNLOCK(); 2334 } 2335 2336 /* 2337 * pmap_clean_page() 2338 * 2339 * This is a local function used to work out the best strategy to clean 2340 * a single page referenced by its entry in the PV table. It's used by 2341 * pmap_copy_page, pmap_zero page and maybe some others later on. 2342 * 2343 * Its policy is effectively: 2344 * o If there are no mappings, we don't bother doing anything with the cache. 2345 * o If there is one mapping, we clean just that page. 2346 * o If there are multiple mappings, we clean the entire cache. 2347 * 2348 * So that some functions can be further optimised, it returns 0 if it didn't 2349 * clean the entire cache, or 1 if it did. 2350 * 2351 * XXX One bug in this routine is that if the pv_entry has a single page 2352 * mapped at 0x00000000 a whole cache clean will be performed rather than 2353 * just the 1 page. Since this should not occur in everyday use and if it does 2354 * it will just result in not the most efficient clean for the page. 2355 */ 2356 #ifdef PMAP_CACHE_VIVT 2357 static int 2358 pmap_clean_page(struct pv_entry *pv, bool is_src) 2359 { 2360 pmap_t pm_to_clean = NULL; 2361 struct pv_entry *npv; 2362 u_int cache_needs_cleaning = 0; 2363 u_int flags = 0; 2364 vaddr_t page_to_clean = 0; 2365 2366 if (pv == NULL) { 2367 /* nothing mapped in so nothing to flush */ 2368 return (0); 2369 } 2370 2371 /* 2372 * Since we flush the cache each time we change to a different 2373 * user vmspace, we only need to flush the page if it is in the 2374 * current pmap. 2375 */ 2376 2377 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2378 if (pmap_is_current(npv->pv_pmap)) { 2379 flags |= npv->pv_flags; 2380 /* 2381 * The page is mapped non-cacheable in 2382 * this map. No need to flush the cache. 2383 */ 2384 if (npv->pv_flags & PVF_NC) { 2385 #ifdef DIAGNOSTIC 2386 if (cache_needs_cleaning) 2387 panic("pmap_clean_page: " 2388 "cache inconsistency"); 2389 #endif 2390 break; 2391 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2392 continue; 2393 if (cache_needs_cleaning) { 2394 page_to_clean = 0; 2395 break; 2396 } else { 2397 page_to_clean = npv->pv_va; 2398 pm_to_clean = npv->pv_pmap; 2399 } 2400 cache_needs_cleaning = 1; 2401 } 2402 } 2403 2404 if (page_to_clean) { 2405 if (PV_BEEN_EXECD(flags)) 2406 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2407 PAGE_SIZE); 2408 else 2409 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2410 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2411 } else if (cache_needs_cleaning) { 2412 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2413 2414 if (PV_BEEN_EXECD(flags)) 2415 pmap_idcache_wbinv_all(pm); 2416 else 2417 pmap_dcache_wbinv_all(pm); 2418 return (1); 2419 } 2420 return (0); 2421 } 2422 #endif 2423 2424 #ifdef PMAP_CACHE_VIPT 2425 /* 2426 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2427 * right cache alias to make sure we flush the right stuff. 2428 */ 2429 void 2430 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2431 { 2432 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2433 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2434 2435 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2436 md, md->pvh_attrs)); 2437 /* 2438 * No need to clean the page if it's non-cached. 2439 */ 2440 if (md->pvh_attrs & PVF_NC) 2441 return; 2442 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2443 2444 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2445 /* 2446 * Set up a PTE with the right coloring to flush existing cache lines. 2447 */ 2448 *ptep = L2_S_PROTO | 2449 pa 2450 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2451 | pte_l2_s_cache_mode; 2452 PTE_SYNC(ptep); 2453 2454 /* 2455 * Flush it. 2456 */ 2457 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2458 /* 2459 * Unmap the page. 2460 */ 2461 *ptep = 0; 2462 PTE_SYNC(ptep); 2463 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2464 2465 md->pvh_attrs |= PVF_EXEC; 2466 PMAPCOUNT(exec_synced); 2467 } 2468 2469 void 2470 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2471 { 2472 vsize_t va_offset, end_va; 2473 void (*cf)(vaddr_t, vsize_t); 2474 2475 if (arm_cache_prefer_mask == 0) 2476 return; 2477 2478 switch (flush) { 2479 case PMAP_FLUSH_PRIMARY: 2480 if (md->pvh_attrs & PVF_MULTCLR) { 2481 va_offset = 0; 2482 end_va = arm_cache_prefer_mask; 2483 md->pvh_attrs &= ~PVF_MULTCLR; 2484 PMAPCOUNT(vac_flush_lots); 2485 } else { 2486 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2487 end_va = va_offset; 2488 PMAPCOUNT(vac_flush_one); 2489 } 2490 /* 2491 * Mark that the page is no longer dirty. 2492 */ 2493 md->pvh_attrs &= ~PVF_DIRTY; 2494 cf = cpufuncs.cf_idcache_wbinv_range; 2495 break; 2496 case PMAP_FLUSH_SECONDARY: 2497 va_offset = 0; 2498 end_va = arm_cache_prefer_mask; 2499 cf = cpufuncs.cf_idcache_wbinv_range; 2500 md->pvh_attrs &= ~PVF_MULTCLR; 2501 PMAPCOUNT(vac_flush_lots); 2502 break; 2503 case PMAP_CLEAN_PRIMARY: 2504 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2505 end_va = va_offset; 2506 cf = cpufuncs.cf_dcache_wb_range; 2507 /* 2508 * Mark that the page is no longer dirty. 2509 */ 2510 if ((md->pvh_attrs & PVF_DMOD) == 0) 2511 md->pvh_attrs &= ~PVF_DIRTY; 2512 PMAPCOUNT(vac_clean_one); 2513 break; 2514 default: 2515 return; 2516 } 2517 2518 KASSERT(!(md->pvh_attrs & PVF_NC)); 2519 2520 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2521 md, md->pvh_attrs)); 2522 2523 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2524 const size_t pte_offset = va_offset >> PGSHIFT; 2525 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2526 const pt_entry_t oldpte = *ptep; 2527 2528 if (flush == PMAP_FLUSH_SECONDARY 2529 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2530 continue; 2531 2532 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2533 /* 2534 * Set up a PTE with the right coloring to flush 2535 * existing cache entries. 2536 */ 2537 *ptep = L2_S_PROTO 2538 | pa 2539 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2540 | pte_l2_s_cache_mode; 2541 PTE_SYNC(ptep); 2542 2543 /* 2544 * Flush it. 2545 */ 2546 (*cf)(cdstp + va_offset, PAGE_SIZE); 2547 2548 /* 2549 * Restore the page table entry since we might have interrupted 2550 * pmap_zero_page or pmap_copy_page which was already using 2551 * this pte. 2552 */ 2553 *ptep = oldpte; 2554 PTE_SYNC(ptep); 2555 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2556 } 2557 } 2558 #endif /* PMAP_CACHE_VIPT */ 2559 2560 /* 2561 * Routine: pmap_page_remove 2562 * Function: 2563 * Removes this physical page from 2564 * all physical maps in which it resides. 2565 * Reflects back modify bits to the pager. 2566 */ 2567 static void 2568 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2569 { 2570 struct l2_bucket *l2b; 2571 struct pv_entry *pv, *npv, **pvp; 2572 pmap_t pm; 2573 pt_entry_t *ptep; 2574 bool flush; 2575 u_int flags; 2576 2577 NPDEBUG(PDB_FOLLOW, 2578 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2579 pa)); 2580 2581 PMAP_HEAD_TO_MAP_LOCK(); 2582 simple_lock(&md->pvh_slock); 2583 2584 pv = SLIST_FIRST(&md->pvh_list); 2585 if (pv == NULL) { 2586 #ifdef PMAP_CACHE_VIPT 2587 /* 2588 * We *know* the page contents are about to be replaced. 2589 * Discard the exec contents 2590 */ 2591 if (PV_IS_EXEC_P(md->pvh_attrs)) 2592 PMAPCOUNT(exec_discarded_page_protect); 2593 md->pvh_attrs &= ~PVF_EXEC; 2594 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2595 #endif 2596 simple_unlock(&md->pvh_slock); 2597 PMAP_HEAD_TO_MAP_UNLOCK(); 2598 return; 2599 } 2600 #ifdef PMAP_CACHE_VIPT 2601 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2602 #endif 2603 2604 /* 2605 * Clear alias counts 2606 */ 2607 #ifdef PMAP_CACHE_VIVT 2608 md->k_mappings = 0; 2609 #endif 2610 md->urw_mappings = md->uro_mappings = 0; 2611 2612 flush = false; 2613 flags = 0; 2614 2615 #ifdef PMAP_CACHE_VIVT 2616 pmap_clean_page(pv, false); 2617 #endif 2618 2619 pvp = &SLIST_FIRST(&md->pvh_list); 2620 while (pv) { 2621 pm = pv->pv_pmap; 2622 npv = SLIST_NEXT(pv, pv_link); 2623 if (flush == false && pmap_is_current(pm)) 2624 flush = true; 2625 2626 if (pm == pmap_kernel()) { 2627 #ifdef PMAP_CACHE_VIPT 2628 /* 2629 * If this was unmanaged mapping, it must be preserved. 2630 * Move it back on the list and advance the end-of-list 2631 * pointer. 2632 */ 2633 if (pv->pv_flags & PVF_KENTRY) { 2634 *pvp = pv; 2635 pvp = &SLIST_NEXT(pv, pv_link); 2636 pv = npv; 2637 continue; 2638 } 2639 if (pv->pv_flags & PVF_WRITE) 2640 md->krw_mappings--; 2641 else 2642 md->kro_mappings--; 2643 #endif 2644 PMAPCOUNT(kernel_unmappings); 2645 } 2646 PMAPCOUNT(unmappings); 2647 2648 pmap_acquire_pmap_lock(pm); 2649 2650 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2651 KDASSERT(l2b != NULL); 2652 2653 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2654 2655 /* 2656 * Update statistics 2657 */ 2658 --pm->pm_stats.resident_count; 2659 2660 /* Wired bit */ 2661 if (pv->pv_flags & PVF_WIRED) 2662 --pm->pm_stats.wired_count; 2663 2664 flags |= pv->pv_flags; 2665 2666 /* 2667 * Invalidate the PTEs. 2668 */ 2669 *ptep = 0; 2670 PTE_SYNC_CURRENT(pm, ptep); 2671 pmap_free_l2_bucket(pm, l2b, 1); 2672 2673 pool_put(&pmap_pv_pool, pv); 2674 pv = npv; 2675 /* 2676 * if we reach the end of the list and there are still 2677 * mappings, they might be able to be cached now. 2678 */ 2679 if (pv == NULL) { 2680 *pvp = NULL; 2681 if (!SLIST_EMPTY(&md->pvh_list)) 2682 pmap_vac_me_harder(md, pa, pm, 0); 2683 } 2684 pmap_release_pmap_lock(pm); 2685 } 2686 #ifdef PMAP_CACHE_VIPT 2687 /* 2688 * Its EXEC cache is now gone. 2689 */ 2690 if (PV_IS_EXEC_P(md->pvh_attrs)) 2691 PMAPCOUNT(exec_discarded_page_protect); 2692 md->pvh_attrs &= ~PVF_EXEC; 2693 KASSERT(md->urw_mappings == 0); 2694 KASSERT(md->uro_mappings == 0); 2695 if (md->krw_mappings == 0) 2696 md->pvh_attrs &= ~PVF_WRITE; 2697 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2698 #endif 2699 simple_unlock(&md->pvh_slock); 2700 PMAP_HEAD_TO_MAP_UNLOCK(); 2701 2702 if (flush) { 2703 /* 2704 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2705 * would need a subsequent call to pmap_update() to ensure 2706 * curpm->pm_cstate.cs_all is reset. Our callers are not 2707 * required to do that (see pmap(9)), so we can't modify 2708 * the current pmap's state. 2709 */ 2710 if (PV_BEEN_EXECD(flags)) 2711 cpu_tlb_flushID(); 2712 else 2713 cpu_tlb_flushD(); 2714 } 2715 cpu_cpwait(); 2716 } 2717 2718 /* 2719 * pmap_t pmap_create(void) 2720 * 2721 * Create a new pmap structure from scratch. 2722 */ 2723 pmap_t 2724 pmap_create(void) 2725 { 2726 pmap_t pm; 2727 2728 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2729 2730 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2731 pm->pm_stats.wired_count = 0; 2732 pm->pm_stats.resident_count = 1; 2733 pm->pm_cstate.cs_all = 0; 2734 pmap_alloc_l1(pm); 2735 2736 /* 2737 * Note: The pool cache ensures that the pm_l2[] array is already 2738 * initialised to zero. 2739 */ 2740 2741 pmap_pinit(pm); 2742 2743 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2744 2745 return (pm); 2746 } 2747 2748 u_int 2749 arm32_mmap_flags(paddr_t pa) 2750 { 2751 /* 2752 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 2753 * and we're using the upper bits in page numbers to pass flags around 2754 * so we might as well use the same bits 2755 */ 2756 return (u_int)pa & PMAP_MD_MASK; 2757 } 2758 /* 2759 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2760 * u_int flags) 2761 * 2762 * Insert the given physical page (p) at 2763 * the specified virtual address (v) in the 2764 * target physical map with the protection requested. 2765 * 2766 * NB: This is the only routine which MAY NOT lazy-evaluate 2767 * or lose information. That is, this routine must actually 2768 * insert this page into the given map NOW. 2769 */ 2770 int 2771 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2772 { 2773 struct l2_bucket *l2b; 2774 struct vm_page *pg, *opg; 2775 struct pv_entry *pv; 2776 pt_entry_t *ptep, npte, opte; 2777 u_int nflags; 2778 u_int oflags; 2779 2780 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2781 2782 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2783 KDASSERT(((va | pa) & PGOFSET) == 0); 2784 2785 /* 2786 * Get a pointer to the page. Later on in this function, we 2787 * test for a managed page by checking pg != NULL. 2788 */ 2789 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2790 2791 nflags = 0; 2792 if (prot & VM_PROT_WRITE) 2793 nflags |= PVF_WRITE; 2794 if (prot & VM_PROT_EXECUTE) 2795 nflags |= PVF_EXEC; 2796 if (flags & PMAP_WIRED) 2797 nflags |= PVF_WIRED; 2798 2799 PMAP_MAP_TO_HEAD_LOCK(); 2800 pmap_acquire_pmap_lock(pm); 2801 2802 /* 2803 * Fetch the L2 bucket which maps this page, allocating one if 2804 * necessary for user pmaps. 2805 */ 2806 if (pm == pmap_kernel()) 2807 l2b = pmap_get_l2_bucket(pm, va); 2808 else 2809 l2b = pmap_alloc_l2_bucket(pm, va); 2810 if (l2b == NULL) { 2811 if (flags & PMAP_CANFAIL) { 2812 pmap_release_pmap_lock(pm); 2813 PMAP_MAP_TO_HEAD_UNLOCK(); 2814 return (ENOMEM); 2815 } 2816 panic("pmap_enter: failed to allocate L2 bucket"); 2817 } 2818 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2819 opte = *ptep; 2820 npte = pa; 2821 oflags = 0; 2822 2823 if (opte) { 2824 /* 2825 * There is already a mapping at this address. 2826 * If the physical address is different, lookup the 2827 * vm_page. 2828 */ 2829 if (l2pte_pa(opte) != pa) 2830 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2831 else 2832 opg = pg; 2833 } else 2834 opg = NULL; 2835 2836 if (pg) { 2837 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2838 2839 /* 2840 * This is to be a managed mapping. 2841 */ 2842 if ((flags & VM_PROT_ALL) || 2843 (md->pvh_attrs & PVF_REF)) { 2844 /* 2845 * - The access type indicates that we don't need 2846 * to do referenced emulation. 2847 * OR 2848 * - The physical page has already been referenced 2849 * so no need to re-do referenced emulation here. 2850 */ 2851 npte |= l2pte_set_readonly(L2_S_PROTO); 2852 2853 nflags |= PVF_REF; 2854 2855 if ((prot & VM_PROT_WRITE) != 0 && 2856 ((flags & VM_PROT_WRITE) != 0 || 2857 (md->pvh_attrs & PVF_MOD) != 0)) { 2858 /* 2859 * This is a writable mapping, and the 2860 * page's mod state indicates it has 2861 * already been modified. Make it 2862 * writable from the outset. 2863 */ 2864 npte = l2pte_set_writable(npte); 2865 nflags |= PVF_MOD; 2866 } 2867 } else { 2868 /* 2869 * Need to do page referenced emulation. 2870 */ 2871 npte |= L2_TYPE_INV; 2872 } 2873 2874 npte |= pte_l2_s_cache_mode; 2875 2876 if (pg == opg) { 2877 /* 2878 * We're changing the attrs of an existing mapping. 2879 */ 2880 simple_lock(&md->pvh_slock); 2881 oflags = pmap_modify_pv(md, pa, pm, va, 2882 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2883 PVF_MOD | PVF_REF, nflags); 2884 simple_unlock(&md->pvh_slock); 2885 2886 #ifdef PMAP_CACHE_VIVT 2887 /* 2888 * We may need to flush the cache if we're 2889 * doing rw-ro... 2890 */ 2891 if (pm->pm_cstate.cs_cache_d && 2892 (oflags & PVF_NC) == 0 && 2893 l2pte_writable_p(opte) && 2894 (prot & VM_PROT_WRITE) == 0) 2895 cpu_dcache_wb_range(va, PAGE_SIZE); 2896 #endif 2897 } else { 2898 /* 2899 * New mapping, or changing the backing page 2900 * of an existing mapping. 2901 */ 2902 if (opg) { 2903 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2904 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2905 2906 /* 2907 * Replacing an existing mapping with a new one. 2908 * It is part of our managed memory so we 2909 * must remove it from the PV list 2910 */ 2911 simple_lock(&omd->pvh_slock); 2912 pv = pmap_remove_pv(omd, opa, pm, va); 2913 pmap_vac_me_harder(omd, opa, pm, 0); 2914 simple_unlock(&omd->pvh_slock); 2915 oflags = pv->pv_flags; 2916 2917 #ifdef PMAP_CACHE_VIVT 2918 /* 2919 * If the old mapping was valid (ref/mod 2920 * emulation creates 'invalid' mappings 2921 * initially) then make sure to frob 2922 * the cache. 2923 */ 2924 if ((oflags & PVF_NC) == 0 && 2925 l2pte_valid(opte)) { 2926 if (PV_BEEN_EXECD(oflags)) { 2927 pmap_idcache_wbinv_range(pm, va, 2928 PAGE_SIZE); 2929 } else 2930 if (PV_BEEN_REFD(oflags)) { 2931 pmap_dcache_wb_range(pm, va, 2932 PAGE_SIZE, true, 2933 (oflags & PVF_WRITE) == 0); 2934 } 2935 } 2936 #endif 2937 } else 2938 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2939 if ((flags & PMAP_CANFAIL) == 0) 2940 panic("pmap_enter: no pv entries"); 2941 2942 if (pm != pmap_kernel()) 2943 pmap_free_l2_bucket(pm, l2b, 0); 2944 pmap_release_pmap_lock(pm); 2945 PMAP_MAP_TO_HEAD_UNLOCK(); 2946 NPDEBUG(PDB_ENTER, 2947 printf("pmap_enter: ENOMEM\n")); 2948 return (ENOMEM); 2949 } 2950 2951 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2952 } 2953 } else { 2954 /* 2955 * We're mapping an unmanaged page. 2956 * These are always readable, and possibly writable, from 2957 * the get go as we don't need to track ref/mod status. 2958 */ 2959 npte |= l2pte_set_readonly(L2_S_PROTO); 2960 if (prot & VM_PROT_WRITE) 2961 npte = l2pte_set_writable(npte); 2962 2963 /* 2964 * Make sure the vector table is mapped cacheable 2965 */ 2966 if ((pm != pmap_kernel() && va == vector_page) || 2967 (flags & ARM32_MMAP_CACHEABLE)) { 2968 npte |= pte_l2_s_cache_mode; 2969 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 2970 npte |= pte_l2_s_wc_mode; 2971 } 2972 if (opg) { 2973 /* 2974 * Looks like there's an existing 'managed' mapping 2975 * at this address. 2976 */ 2977 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2978 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2979 2980 simple_lock(&omd->pvh_slock); 2981 pv = pmap_remove_pv(omd, opa, pm, va); 2982 pmap_vac_me_harder(omd, opa, pm, 0); 2983 simple_unlock(&omd->pvh_slock); 2984 oflags = pv->pv_flags; 2985 2986 #ifdef PMAP_CACHE_VIVT 2987 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2988 if (PV_BEEN_EXECD(oflags)) 2989 pmap_idcache_wbinv_range(pm, va, 2990 PAGE_SIZE); 2991 else 2992 if (PV_BEEN_REFD(oflags)) 2993 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2994 true, (oflags & PVF_WRITE) == 0); 2995 } 2996 #endif 2997 pool_put(&pmap_pv_pool, pv); 2998 } 2999 } 3000 3001 /* 3002 * Make sure userland mappings get the right permissions 3003 */ 3004 if (pm != pmap_kernel() && va != vector_page) 3005 npte |= L2_S_PROT_U; 3006 3007 /* 3008 * Keep the stats up to date 3009 */ 3010 if (opte == 0) { 3011 l2b->l2b_occupancy++; 3012 pm->pm_stats.resident_count++; 3013 } 3014 3015 NPDEBUG(PDB_ENTER, 3016 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3017 3018 /* 3019 * If this is just a wiring change, the two PTEs will be 3020 * identical, so there's no need to update the page table. 3021 */ 3022 if (npte != opte) { 3023 bool is_cached = pmap_is_cached(pm); 3024 3025 *ptep = npte; 3026 if (is_cached) { 3027 /* 3028 * We only need to frob the cache/tlb if this pmap 3029 * is current 3030 */ 3031 PTE_SYNC(ptep); 3032 if (va != vector_page && l2pte_valid(npte)) { 3033 /* 3034 * This mapping is likely to be accessed as 3035 * soon as we return to userland. Fix up the 3036 * L1 entry to avoid taking another 3037 * page/domain fault. 3038 */ 3039 pd_entry_t *pl1pd, l1pd; 3040 3041 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3042 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3043 L1_C_PROTO; 3044 if (*pl1pd != l1pd) { 3045 *pl1pd = l1pd; 3046 PTE_SYNC(pl1pd); 3047 } 3048 } 3049 } 3050 3051 if (PV_BEEN_EXECD(oflags)) 3052 pmap_tlb_flushID_SE(pm, va); 3053 else 3054 if (PV_BEEN_REFD(oflags)) 3055 pmap_tlb_flushD_SE(pm, va); 3056 3057 NPDEBUG(PDB_ENTER, 3058 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3059 is_cached, pm->pm_cstate.cs_all)); 3060 3061 if (pg != NULL) { 3062 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3063 3064 simple_lock(&md->pvh_slock); 3065 pmap_vac_me_harder(md, pa, pm, va); 3066 simple_unlock(&md->pvh_slock); 3067 } 3068 } 3069 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3070 if (pg) { 3071 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3072 3073 simple_lock(&md->pvh_slock); 3074 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3075 KASSERT(((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0)); 3076 simple_unlock(&md->pvh_slock); 3077 } 3078 #endif 3079 3080 pmap_release_pmap_lock(pm); 3081 PMAP_MAP_TO_HEAD_UNLOCK(); 3082 3083 return (0); 3084 } 3085 3086 /* 3087 * pmap_remove() 3088 * 3089 * pmap_remove is responsible for nuking a number of mappings for a range 3090 * of virtual address space in the current pmap. To do this efficiently 3091 * is interesting, because in a number of cases a wide virtual address 3092 * range may be supplied that contains few actual mappings. So, the 3093 * optimisations are: 3094 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3095 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3096 * maybe do just a partial cache clean. This path of execution is 3097 * complicated by the fact that the cache must be flushed _before_ 3098 * the PTE is nuked, being a VAC :-) 3099 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3100 * all invalidations until pmap_update(), since pmap_remove_all() has 3101 * already flushed the cache. 3102 * 4. Maybe later fast-case a single page, but I don't think this is 3103 * going to make _that_ much difference overall. 3104 */ 3105 3106 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3107 3108 void 3109 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3110 { 3111 struct l2_bucket *l2b; 3112 vaddr_t next_bucket; 3113 pt_entry_t *ptep; 3114 u_int cleanlist_idx, total, cnt; 3115 struct { 3116 vaddr_t va; 3117 pt_entry_t *ptep; 3118 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3119 u_int mappings, is_exec, is_refd; 3120 3121 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3122 "eva=%08lx\n", pm, sva, eva)); 3123 3124 /* 3125 * we lock in the pmap => pv_head direction 3126 */ 3127 PMAP_MAP_TO_HEAD_LOCK(); 3128 pmap_acquire_pmap_lock(pm); 3129 3130 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3131 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3132 if (pm->pm_cstate.cs_tlb == 0) 3133 pm->pm_remove_all = true; 3134 } else 3135 cleanlist_idx = 0; 3136 3137 total = 0; 3138 3139 while (sva < eva) { 3140 /* 3141 * Do one L2 bucket's worth at a time. 3142 */ 3143 next_bucket = L2_NEXT_BUCKET(sva); 3144 if (next_bucket > eva) 3145 next_bucket = eva; 3146 3147 l2b = pmap_get_l2_bucket(pm, sva); 3148 if (l2b == NULL) { 3149 sva = next_bucket; 3150 continue; 3151 } 3152 3153 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3154 3155 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3156 struct vm_page *pg; 3157 pt_entry_t pte; 3158 paddr_t pa; 3159 3160 pte = *ptep; 3161 3162 if (pte == 0) { 3163 /* Nothing here, move along */ 3164 continue; 3165 } 3166 3167 pa = l2pte_pa(pte); 3168 is_exec = 0; 3169 is_refd = 1; 3170 3171 /* 3172 * Update flags. In a number of circumstances, 3173 * we could cluster a lot of these and do a 3174 * number of sequential pages in one go. 3175 */ 3176 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3177 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3178 struct pv_entry *pv; 3179 3180 simple_lock(&md->pvh_slock); 3181 pv = pmap_remove_pv(md, pa, pm, sva); 3182 pmap_vac_me_harder(md, pa, pm, 0); 3183 simple_unlock(&md->pvh_slock); 3184 if (pv != NULL) { 3185 if (pm->pm_remove_all == false) { 3186 is_exec = 3187 PV_BEEN_EXECD(pv->pv_flags); 3188 is_refd = 3189 PV_BEEN_REFD(pv->pv_flags); 3190 } 3191 pool_put(&pmap_pv_pool, pv); 3192 } 3193 } 3194 mappings++; 3195 3196 if (!l2pte_valid(pte)) { 3197 /* 3198 * Ref/Mod emulation is still active for this 3199 * mapping, therefore it is has not yet been 3200 * accessed. No need to frob the cache/tlb. 3201 */ 3202 *ptep = 0; 3203 PTE_SYNC_CURRENT(pm, ptep); 3204 continue; 3205 } 3206 3207 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3208 /* Add to the clean list. */ 3209 cleanlist[cleanlist_idx].ptep = ptep; 3210 cleanlist[cleanlist_idx].va = 3211 sva | (is_exec & 1); 3212 cleanlist_idx++; 3213 } else 3214 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3215 /* Nuke everything if needed. */ 3216 #ifdef PMAP_CACHE_VIVT 3217 pmap_idcache_wbinv_all(pm); 3218 #endif 3219 pmap_tlb_flushID(pm); 3220 3221 /* 3222 * Roll back the previous PTE list, 3223 * and zero out the current PTE. 3224 */ 3225 for (cnt = 0; 3226 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3227 *cleanlist[cnt].ptep = 0; 3228 PTE_SYNC(cleanlist[cnt].ptep); 3229 } 3230 *ptep = 0; 3231 PTE_SYNC(ptep); 3232 cleanlist_idx++; 3233 pm->pm_remove_all = true; 3234 } else { 3235 *ptep = 0; 3236 PTE_SYNC(ptep); 3237 if (pm->pm_remove_all == false) { 3238 if (is_exec) 3239 pmap_tlb_flushID_SE(pm, sva); 3240 else 3241 if (is_refd) 3242 pmap_tlb_flushD_SE(pm, sva); 3243 } 3244 } 3245 } 3246 3247 /* 3248 * Deal with any left overs 3249 */ 3250 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3251 total += cleanlist_idx; 3252 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3253 if (pm->pm_cstate.cs_all != 0) { 3254 vaddr_t clva = cleanlist[cnt].va & ~1; 3255 if (cleanlist[cnt].va & 1) { 3256 #ifdef PMAP_CACHE_VIVT 3257 pmap_idcache_wbinv_range(pm, 3258 clva, PAGE_SIZE); 3259 #endif 3260 pmap_tlb_flushID_SE(pm, clva); 3261 } else { 3262 #ifdef PMAP_CACHE_VIVT 3263 pmap_dcache_wb_range(pm, 3264 clva, PAGE_SIZE, true, 3265 false); 3266 #endif 3267 pmap_tlb_flushD_SE(pm, clva); 3268 } 3269 } 3270 *cleanlist[cnt].ptep = 0; 3271 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3272 } 3273 3274 /* 3275 * If it looks like we're removing a whole bunch 3276 * of mappings, it's faster to just write-back 3277 * the whole cache now and defer TLB flushes until 3278 * pmap_update() is called. 3279 */ 3280 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3281 cleanlist_idx = 0; 3282 else { 3283 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3284 #ifdef PMAP_CACHE_VIVT 3285 pmap_idcache_wbinv_all(pm); 3286 #endif 3287 pm->pm_remove_all = true; 3288 } 3289 } 3290 3291 pmap_free_l2_bucket(pm, l2b, mappings); 3292 pm->pm_stats.resident_count -= mappings; 3293 } 3294 3295 pmap_release_pmap_lock(pm); 3296 PMAP_MAP_TO_HEAD_UNLOCK(); 3297 } 3298 3299 #ifdef PMAP_CACHE_VIPT 3300 static struct pv_entry * 3301 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3302 { 3303 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3304 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3305 struct pv_entry *pv; 3306 3307 simple_lock(&md->pvh_slock); 3308 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3309 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3310 3311 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3312 KASSERT(pv); 3313 KASSERT(pv->pv_flags & PVF_KENTRY); 3314 3315 /* 3316 * If we are removing a writeable mapping to a cached exec page, 3317 * if it's the last mapping then clear it execness other sync 3318 * the page to the icache. 3319 */ 3320 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3321 && (pv->pv_flags & PVF_WRITE) != 0) { 3322 if (SLIST_EMPTY(&md->pvh_list)) { 3323 md->pvh_attrs &= ~PVF_EXEC; 3324 PMAPCOUNT(exec_discarded_kremove); 3325 } else { 3326 pmap_syncicache_page(md, pa); 3327 PMAPCOUNT(exec_synced_kremove); 3328 } 3329 } 3330 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3331 simple_unlock(&md->pvh_slock); 3332 3333 return pv; 3334 } 3335 #endif /* PMAP_CACHE_VIPT */ 3336 3337 /* 3338 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3339 * 3340 * We assume there is already sufficient KVM space available 3341 * to do this, as we can't allocate L2 descriptor tables/metadata 3342 * from here. 3343 */ 3344 void 3345 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3346 { 3347 struct l2_bucket *l2b; 3348 pt_entry_t *ptep, opte; 3349 #ifdef PMAP_CACHE_VIVT 3350 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3351 #endif 3352 #ifdef PMAP_CACHE_VIPT 3353 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3354 struct vm_page *opg; 3355 struct pv_entry *pv = NULL; 3356 #endif 3357 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3358 3359 NPDEBUG(PDB_KENTER, 3360 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3361 va, pa, prot)); 3362 3363 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3364 KDASSERT(l2b != NULL); 3365 3366 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3367 opte = *ptep; 3368 3369 if (opte == 0) { 3370 PMAPCOUNT(kenter_mappings); 3371 l2b->l2b_occupancy++; 3372 } else { 3373 PMAPCOUNT(kenter_remappings); 3374 #ifdef PMAP_CACHE_VIPT 3375 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3376 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3377 if (opg) { 3378 KASSERT(opg != pg); 3379 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3380 KASSERT((flags & PMAP_KMPAGE) == 0); 3381 simple_lock(&omd->pvh_slock); 3382 pv = pmap_kremove_pg(opg, va); 3383 simple_unlock(&omd->pvh_slock); 3384 } 3385 #endif 3386 if (l2pte_valid(opte)) { 3387 #ifdef PMAP_CACHE_VIVT 3388 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3389 #endif 3390 cpu_tlb_flushD_SE(va); 3391 cpu_cpwait(); 3392 } 3393 } 3394 3395 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3396 pte_l2_s_cache_mode; 3397 PTE_SYNC(ptep); 3398 3399 if (pg) { 3400 if (flags & PMAP_KMPAGE) { 3401 simple_lock(&md->pvh_slock); 3402 KASSERT(md->urw_mappings == 0); 3403 KASSERT(md->uro_mappings == 0); 3404 KASSERT(md->krw_mappings == 0); 3405 KASSERT(md->kro_mappings == 0); 3406 #ifdef PMAP_CACHE_VIPT 3407 KASSERT(pv == NULL); 3408 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3409 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3410 /* if there is a color conflict, evict from cache. */ 3411 if (pmap_is_page_colored_p(md) 3412 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3413 PMAPCOUNT(vac_color_change); 3414 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3415 } else if (md->pvh_attrs & PVF_MULTCLR) { 3416 /* 3417 * If this page has multiple colors, expunge 3418 * them. 3419 */ 3420 PMAPCOUNT(vac_flush_lots2); 3421 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3422 } 3423 md->pvh_attrs &= PAGE_SIZE - 1; 3424 md->pvh_attrs |= PVF_KMPAGE 3425 | PVF_COLORED | PVF_DIRTY 3426 | (va & arm_cache_prefer_mask); 3427 #endif 3428 #ifdef PMAP_CACHE_VIVT 3429 md->pvh_attrs |= PVF_KMPAGE; 3430 #endif 3431 pmap_kmpages++; 3432 simple_unlock(&md->pvh_slock); 3433 #ifdef PMAP_CACHE_VIPT 3434 } else { 3435 if (pv == NULL) { 3436 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3437 KASSERT(pv != NULL); 3438 } 3439 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3440 PVF_WIRED | PVF_KENTRY 3441 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3442 if ((prot & VM_PROT_WRITE) 3443 && !(md->pvh_attrs & PVF_NC)) 3444 md->pvh_attrs |= PVF_DIRTY; 3445 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3446 simple_lock(&md->pvh_slock); 3447 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3448 simple_unlock(&md->pvh_slock); 3449 #endif 3450 } 3451 #ifdef PMAP_CACHE_VIPT 3452 } else { 3453 if (pv != NULL) 3454 pool_put(&pmap_pv_pool, pv); 3455 #endif 3456 } 3457 } 3458 3459 void 3460 pmap_kremove(vaddr_t va, vsize_t len) 3461 { 3462 struct l2_bucket *l2b; 3463 pt_entry_t *ptep, *sptep, opte; 3464 vaddr_t next_bucket, eva; 3465 u_int mappings; 3466 struct vm_page *opg; 3467 3468 PMAPCOUNT(kenter_unmappings); 3469 3470 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3471 va, len)); 3472 3473 eva = va + len; 3474 3475 while (va < eva) { 3476 next_bucket = L2_NEXT_BUCKET(va); 3477 if (next_bucket > eva) 3478 next_bucket = eva; 3479 3480 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3481 KDASSERT(l2b != NULL); 3482 3483 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3484 mappings = 0; 3485 3486 while (va < next_bucket) { 3487 opte = *ptep; 3488 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3489 if (opg) { 3490 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3491 3492 if (omd->pvh_attrs & PVF_KMPAGE) { 3493 simple_lock(&omd->pvh_slock); 3494 KASSERT(omd->urw_mappings == 0); 3495 KASSERT(omd->uro_mappings == 0); 3496 KASSERT(omd->krw_mappings == 0); 3497 KASSERT(omd->kro_mappings == 0); 3498 omd->pvh_attrs &= ~PVF_KMPAGE; 3499 #ifdef PMAP_CACHE_VIPT 3500 omd->pvh_attrs &= ~PVF_WRITE; 3501 #endif 3502 pmap_kmpages--; 3503 simple_unlock(&omd->pvh_slock); 3504 #ifdef PMAP_CACHE_VIPT 3505 } else { 3506 pool_put(&pmap_pv_pool, 3507 pmap_kremove_pg(opg, va)); 3508 #endif 3509 } 3510 } 3511 if (l2pte_valid(opte)) { 3512 #ifdef PMAP_CACHE_VIVT 3513 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3514 #endif 3515 cpu_tlb_flushD_SE(va); 3516 } 3517 if (opte) { 3518 *ptep = 0; 3519 mappings++; 3520 } 3521 va += PAGE_SIZE; 3522 ptep++; 3523 } 3524 KDASSERT(mappings <= l2b->l2b_occupancy); 3525 l2b->l2b_occupancy -= mappings; 3526 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3527 } 3528 cpu_cpwait(); 3529 } 3530 3531 bool 3532 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3533 { 3534 struct l2_dtable *l2; 3535 pd_entry_t *pl1pd, l1pd; 3536 pt_entry_t *ptep, pte; 3537 paddr_t pa; 3538 u_int l1idx; 3539 3540 pmap_acquire_pmap_lock(pm); 3541 3542 l1idx = L1_IDX(va); 3543 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3544 l1pd = *pl1pd; 3545 3546 if (l1pte_section_p(l1pd)) { 3547 /* 3548 * These should only happen for pmap_kernel() 3549 */ 3550 KDASSERT(pm == pmap_kernel()); 3551 pmap_release_pmap_lock(pm); 3552 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3553 } else { 3554 /* 3555 * Note that we can't rely on the validity of the L1 3556 * descriptor as an indication that a mapping exists. 3557 * We have to look it up in the L2 dtable. 3558 */ 3559 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3560 3561 if (l2 == NULL || 3562 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3563 pmap_release_pmap_lock(pm); 3564 return false; 3565 } 3566 3567 ptep = &ptep[l2pte_index(va)]; 3568 pte = *ptep; 3569 pmap_release_pmap_lock(pm); 3570 3571 if (pte == 0) 3572 return false; 3573 3574 switch (pte & L2_TYPE_MASK) { 3575 case L2_TYPE_L: 3576 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3577 break; 3578 3579 default: 3580 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3581 break; 3582 } 3583 } 3584 3585 if (pap != NULL) 3586 *pap = pa; 3587 3588 return true; 3589 } 3590 3591 void 3592 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3593 { 3594 struct l2_bucket *l2b; 3595 pt_entry_t *ptep, pte; 3596 vaddr_t next_bucket; 3597 u_int flags; 3598 u_int clr_mask; 3599 int flush; 3600 3601 NPDEBUG(PDB_PROTECT, 3602 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3603 pm, sva, eva, prot)); 3604 3605 if ((prot & VM_PROT_READ) == 0) { 3606 pmap_remove(pm, sva, eva); 3607 return; 3608 } 3609 3610 if (prot & VM_PROT_WRITE) { 3611 /* 3612 * If this is a read->write transition, just ignore it and let 3613 * uvm_fault() take care of it later. 3614 */ 3615 return; 3616 } 3617 3618 PMAP_MAP_TO_HEAD_LOCK(); 3619 pmap_acquire_pmap_lock(pm); 3620 3621 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3622 flags = 0; 3623 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3624 3625 while (sva < eva) { 3626 next_bucket = L2_NEXT_BUCKET(sva); 3627 if (next_bucket > eva) 3628 next_bucket = eva; 3629 3630 l2b = pmap_get_l2_bucket(pm, sva); 3631 if (l2b == NULL) { 3632 sva = next_bucket; 3633 continue; 3634 } 3635 3636 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3637 3638 while (sva < next_bucket) { 3639 pte = *ptep; 3640 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3641 struct vm_page *pg; 3642 u_int f; 3643 3644 #ifdef PMAP_CACHE_VIVT 3645 /* 3646 * OK, at this point, we know we're doing 3647 * write-protect operation. If the pmap is 3648 * active, write-back the page. 3649 */ 3650 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3651 false, false); 3652 #endif 3653 3654 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3655 pte = l2pte_set_readonly(pte); 3656 *ptep = pte; 3657 PTE_SYNC(ptep); 3658 3659 if (pg != NULL) { 3660 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3661 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3662 3663 simple_lock(&md->pvh_slock); 3664 f = pmap_modify_pv(md, pa, pm, sva, 3665 clr_mask, 0); 3666 pmap_vac_me_harder(md, pa, pm, sva); 3667 simple_unlock(&md->pvh_slock); 3668 } else 3669 f = PVF_REF | PVF_EXEC; 3670 3671 if (flush >= 0) { 3672 flush++; 3673 flags |= f; 3674 } else 3675 if (PV_BEEN_EXECD(f)) 3676 pmap_tlb_flushID_SE(pm, sva); 3677 else 3678 if (PV_BEEN_REFD(f)) 3679 pmap_tlb_flushD_SE(pm, sva); 3680 } 3681 3682 sva += PAGE_SIZE; 3683 ptep++; 3684 } 3685 } 3686 3687 pmap_release_pmap_lock(pm); 3688 PMAP_MAP_TO_HEAD_UNLOCK(); 3689 3690 if (flush) { 3691 if (PV_BEEN_EXECD(flags)) 3692 pmap_tlb_flushID(pm); 3693 else 3694 if (PV_BEEN_REFD(flags)) 3695 pmap_tlb_flushD(pm); 3696 } 3697 } 3698 3699 void 3700 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3701 { 3702 struct l2_bucket *l2b; 3703 pt_entry_t *ptep; 3704 vaddr_t next_bucket; 3705 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3706 3707 NPDEBUG(PDB_EXEC, 3708 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3709 pm, sva, eva)); 3710 3711 PMAP_MAP_TO_HEAD_LOCK(); 3712 pmap_acquire_pmap_lock(pm); 3713 3714 while (sva < eva) { 3715 next_bucket = L2_NEXT_BUCKET(sva); 3716 if (next_bucket > eva) 3717 next_bucket = eva; 3718 3719 l2b = pmap_get_l2_bucket(pm, sva); 3720 if (l2b == NULL) { 3721 sva = next_bucket; 3722 continue; 3723 } 3724 3725 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3726 sva < next_bucket; 3727 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3728 if (l2pte_valid(*ptep)) { 3729 cpu_icache_sync_range(sva, 3730 min(page_size, eva - sva)); 3731 } 3732 } 3733 } 3734 3735 pmap_release_pmap_lock(pm); 3736 PMAP_MAP_TO_HEAD_UNLOCK(); 3737 } 3738 3739 void 3740 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3741 { 3742 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3743 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3744 3745 NPDEBUG(PDB_PROTECT, 3746 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3747 md, pa, prot)); 3748 3749 switch(prot) { 3750 case VM_PROT_READ|VM_PROT_WRITE: 3751 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3752 pmap_clearbit(md, pa, PVF_EXEC); 3753 break; 3754 #endif 3755 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3756 break; 3757 3758 case VM_PROT_READ: 3759 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3760 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3761 break; 3762 #endif 3763 case VM_PROT_READ|VM_PROT_EXECUTE: 3764 pmap_clearbit(md, pa, PVF_WRITE); 3765 break; 3766 3767 default: 3768 pmap_page_remove(md, pa); 3769 break; 3770 } 3771 } 3772 3773 /* 3774 * pmap_clear_modify: 3775 * 3776 * Clear the "modified" attribute for a page. 3777 */ 3778 bool 3779 pmap_clear_modify(struct vm_page *pg) 3780 { 3781 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3782 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3783 bool rv; 3784 3785 if (md->pvh_attrs & PVF_MOD) { 3786 rv = true; 3787 #ifdef PMAP_CACHE_VIPT 3788 /* 3789 * If we are going to clear the modified bit and there are 3790 * no other modified bits set, flush the page to memory and 3791 * mark it clean. 3792 */ 3793 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3794 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3795 #endif 3796 pmap_clearbit(md, pa, PVF_MOD); 3797 } else 3798 rv = false; 3799 3800 return (rv); 3801 } 3802 3803 /* 3804 * pmap_clear_reference: 3805 * 3806 * Clear the "referenced" attribute for a page. 3807 */ 3808 bool 3809 pmap_clear_reference(struct vm_page *pg) 3810 { 3811 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3812 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3813 bool rv; 3814 3815 if (md->pvh_attrs & PVF_REF) { 3816 rv = true; 3817 pmap_clearbit(md, pa, PVF_REF); 3818 } else 3819 rv = false; 3820 3821 return (rv); 3822 } 3823 3824 /* 3825 * pmap_is_modified: 3826 * 3827 * Test if a page has the "modified" attribute. 3828 */ 3829 /* See <arm/arm32/pmap.h> */ 3830 3831 /* 3832 * pmap_is_referenced: 3833 * 3834 * Test if a page has the "referenced" attribute. 3835 */ 3836 /* See <arm/arm32/pmap.h> */ 3837 3838 int 3839 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3840 { 3841 struct l2_dtable *l2; 3842 struct l2_bucket *l2b; 3843 pd_entry_t *pl1pd, l1pd; 3844 pt_entry_t *ptep, pte; 3845 paddr_t pa; 3846 u_int l1idx; 3847 int rv = 0; 3848 3849 PMAP_MAP_TO_HEAD_LOCK(); 3850 pmap_acquire_pmap_lock(pm); 3851 3852 l1idx = L1_IDX(va); 3853 3854 /* 3855 * If there is no l2_dtable for this address, then the process 3856 * has no business accessing it. 3857 * 3858 * Note: This will catch userland processes trying to access 3859 * kernel addresses. 3860 */ 3861 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3862 if (l2 == NULL) 3863 goto out; 3864 3865 /* 3866 * Likewise if there is no L2 descriptor table 3867 */ 3868 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3869 if (l2b->l2b_kva == NULL) 3870 goto out; 3871 3872 /* 3873 * Check the PTE itself. 3874 */ 3875 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3876 pte = *ptep; 3877 if (pte == 0) 3878 goto out; 3879 3880 /* 3881 * Catch a userland access to the vector page mapped at 0x0 3882 */ 3883 if (user && (pte & L2_S_PROT_U) == 0) 3884 goto out; 3885 3886 pa = l2pte_pa(pte); 3887 3888 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3889 /* 3890 * This looks like a good candidate for "page modified" 3891 * emulation... 3892 */ 3893 struct pv_entry *pv; 3894 struct vm_page *pg; 3895 3896 /* Extract the physical address of the page */ 3897 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3898 goto out; 3899 3900 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3901 3902 /* Get the current flags for this page. */ 3903 simple_lock(&md->pvh_slock); 3904 3905 pv = pmap_find_pv(md, pm, va); 3906 if (pv == NULL) { 3907 simple_unlock(&md->pvh_slock); 3908 goto out; 3909 } 3910 3911 /* 3912 * Do the flags say this page is writable? If not then it 3913 * is a genuine write fault. If yes then the write fault is 3914 * our fault as we did not reflect the write access in the 3915 * PTE. Now we know a write has occurred we can correct this 3916 * and also set the modified bit 3917 */ 3918 if ((pv->pv_flags & PVF_WRITE) == 0) { 3919 simple_unlock(&md->pvh_slock); 3920 goto out; 3921 } 3922 3923 NPDEBUG(PDB_FOLLOW, 3924 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3925 pm, va, pa)); 3926 3927 md->pvh_attrs |= PVF_REF | PVF_MOD; 3928 pv->pv_flags |= PVF_REF | PVF_MOD; 3929 #ifdef PMAP_CACHE_VIPT 3930 /* 3931 * If there are cacheable mappings for this page, mark it dirty. 3932 */ 3933 if ((md->pvh_attrs & PVF_NC) == 0) 3934 md->pvh_attrs |= PVF_DIRTY; 3935 #endif 3936 simple_unlock(&md->pvh_slock); 3937 3938 /* 3939 * Re-enable write permissions for the page. No need to call 3940 * pmap_vac_me_harder(), since this is just a 3941 * modified-emulation fault, and the PVF_WRITE bit isn't 3942 * changing. We've already set the cacheable bits based on 3943 * the assumption that we can write to this page. 3944 */ 3945 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3946 PTE_SYNC(ptep); 3947 rv = 1; 3948 } else 3949 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3950 /* 3951 * This looks like a good candidate for "page referenced" 3952 * emulation. 3953 */ 3954 struct pv_entry *pv; 3955 struct vm_page *pg; 3956 3957 /* Extract the physical address of the page */ 3958 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3959 goto out; 3960 3961 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3962 3963 /* Get the current flags for this page. */ 3964 simple_lock(&md->pvh_slock); 3965 3966 pv = pmap_find_pv(md, pm, va); 3967 if (pv == NULL) { 3968 simple_unlock(&md->pvh_slock); 3969 goto out; 3970 } 3971 3972 md->pvh_attrs |= PVF_REF; 3973 pv->pv_flags |= PVF_REF; 3974 simple_unlock(&md->pvh_slock); 3975 3976 NPDEBUG(PDB_FOLLOW, 3977 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3978 pm, va, pa)); 3979 3980 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3981 PTE_SYNC(ptep); 3982 rv = 1; 3983 } 3984 3985 /* 3986 * We know there is a valid mapping here, so simply 3987 * fix up the L1 if necessary. 3988 */ 3989 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3990 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3991 if (*pl1pd != l1pd) { 3992 *pl1pd = l1pd; 3993 PTE_SYNC(pl1pd); 3994 rv = 1; 3995 } 3996 3997 #ifdef CPU_SA110 3998 /* 3999 * There are bugs in the rev K SA110. This is a check for one 4000 * of them. 4001 */ 4002 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4003 curcpu()->ci_arm_cpurev < 3) { 4004 /* Always current pmap */ 4005 if (l2pte_valid(pte)) { 4006 extern int kernel_debug; 4007 if (kernel_debug & 1) { 4008 struct proc *p = curlwp->l_proc; 4009 printf("prefetch_abort: page is already " 4010 "mapped - pte=%p *pte=%08x\n", ptep, pte); 4011 printf("prefetch_abort: pc=%08lx proc=%p " 4012 "process=%s\n", va, p, p->p_comm); 4013 printf("prefetch_abort: far=%08x fs=%x\n", 4014 cpu_faultaddress(), cpu_faultstatus()); 4015 } 4016 #ifdef DDB 4017 if (kernel_debug & 2) 4018 Debugger(); 4019 #endif 4020 rv = 1; 4021 } 4022 } 4023 #endif /* CPU_SA110 */ 4024 4025 #ifdef DEBUG 4026 /* 4027 * If 'rv == 0' at this point, it generally indicates that there is a 4028 * stale TLB entry for the faulting address. This happens when two or 4029 * more processes are sharing an L1. Since we don't flush the TLB on 4030 * a context switch between such processes, we can take domain faults 4031 * for mappings which exist at the same VA in both processes. EVEN IF 4032 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4033 * example. 4034 * 4035 * This is extremely likely to happen if pmap_enter() updated the L1 4036 * entry for a recently entered mapping. In this case, the TLB is 4037 * flushed for the new mapping, but there may still be TLB entries for 4038 * other mappings belonging to other processes in the 1MB range 4039 * covered by the L1 entry. 4040 * 4041 * Since 'rv == 0', we know that the L1 already contains the correct 4042 * value, so the fault must be due to a stale TLB entry. 4043 * 4044 * Since we always need to flush the TLB anyway in the case where we 4045 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4046 * stale TLB entries dynamically. 4047 * 4048 * However, the above condition can ONLY happen if the current L1 is 4049 * being shared. If it happens when the L1 is unshared, it indicates 4050 * that other parts of the pmap are not doing their job WRT managing 4051 * the TLB. 4052 */ 4053 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4054 extern int last_fault_code; 4055 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4056 pm, va, ftype); 4057 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4058 l2, l2b, ptep, pl1pd); 4059 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4060 pte, l1pd, last_fault_code); 4061 #ifdef DDB 4062 Debugger(); 4063 #endif 4064 } 4065 #endif 4066 4067 cpu_tlb_flushID_SE(va); 4068 cpu_cpwait(); 4069 4070 rv = 1; 4071 4072 out: 4073 pmap_release_pmap_lock(pm); 4074 PMAP_MAP_TO_HEAD_UNLOCK(); 4075 4076 return (rv); 4077 } 4078 4079 /* 4080 * Routine: pmap_procwr 4081 * 4082 * Function: 4083 * Synchronize caches corresponding to [addr, addr+len) in p. 4084 * 4085 */ 4086 void 4087 pmap_procwr(struct proc *p, vaddr_t va, int len) 4088 { 4089 /* We only need to do anything if it is the current process. */ 4090 if (p == curproc) 4091 cpu_icache_sync_range(va, len); 4092 } 4093 4094 /* 4095 * Routine: pmap_unwire 4096 * Function: Clear the wired attribute for a map/virtual-address pair. 4097 * 4098 * In/out conditions: 4099 * The mapping must already exist in the pmap. 4100 */ 4101 void 4102 pmap_unwire(pmap_t pm, vaddr_t va) 4103 { 4104 struct l2_bucket *l2b; 4105 pt_entry_t *ptep, pte; 4106 struct vm_page *pg; 4107 paddr_t pa; 4108 4109 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4110 4111 PMAP_MAP_TO_HEAD_LOCK(); 4112 pmap_acquire_pmap_lock(pm); 4113 4114 l2b = pmap_get_l2_bucket(pm, va); 4115 KDASSERT(l2b != NULL); 4116 4117 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4118 pte = *ptep; 4119 4120 /* Extract the physical address of the page */ 4121 pa = l2pte_pa(pte); 4122 4123 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4124 /* Update the wired bit in the pv entry for this page. */ 4125 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4126 4127 simple_lock(&md->pvh_slock); 4128 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4129 simple_unlock(&md->pvh_slock); 4130 } 4131 4132 pmap_release_pmap_lock(pm); 4133 PMAP_MAP_TO_HEAD_UNLOCK(); 4134 } 4135 4136 void 4137 pmap_activate(struct lwp *l) 4138 { 4139 extern int block_userspace_access; 4140 pmap_t opm, npm, rpm; 4141 uint32_t odacr, ndacr; 4142 int oldirqstate; 4143 4144 /* 4145 * If activating a non-current lwp or the current lwp is 4146 * already active, just return. 4147 */ 4148 if (l != curlwp || 4149 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4150 return; 4151 4152 npm = l->l_proc->p_vmspace->vm_map.pmap; 4153 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4154 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4155 4156 /* 4157 * If TTB and DACR are unchanged, short-circuit all the 4158 * TLB/cache management stuff. 4159 */ 4160 if (pmap_previous_active_lwp != NULL) { 4161 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4162 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4163 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4164 4165 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4166 goto all_done; 4167 } else 4168 opm = NULL; 4169 4170 PMAPCOUNT(activations); 4171 block_userspace_access = 1; 4172 4173 /* 4174 * If switching to a user vmspace which is different to the 4175 * most recent one, and the most recent one is potentially 4176 * live in the cache, we must write-back and invalidate the 4177 * entire cache. 4178 */ 4179 rpm = pmap_recent_user; 4180 4181 /* 4182 * XXXSCW: There's a corner case here which can leave turds in the cache as 4183 * reported in kern/41058. They're probably left over during tear-down and 4184 * switching away from an exiting process. Until the root cause is identified 4185 * and fixed, zap the cache when switching pmaps. This will result in a few 4186 * unnecessary cache flushes, but that's better than silently corrupting data. 4187 */ 4188 #if 0 4189 if (npm != pmap_kernel() && rpm && npm != rpm && 4190 rpm->pm_cstate.cs_cache) { 4191 rpm->pm_cstate.cs_cache = 0; 4192 #ifdef PMAP_CACHE_VIVT 4193 cpu_idcache_wbinv_all(); 4194 #endif 4195 } 4196 #else 4197 if (rpm) { 4198 rpm->pm_cstate.cs_cache = 0; 4199 if (npm == pmap_kernel()) 4200 pmap_recent_user = NULL; 4201 #ifdef PMAP_CACHE_VIVT 4202 cpu_idcache_wbinv_all(); 4203 #endif 4204 } 4205 #endif 4206 4207 /* No interrupts while we frob the TTB/DACR */ 4208 oldirqstate = disable_interrupts(IF32_bits); 4209 4210 /* 4211 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4212 * entry corresponding to 'vector_page' in the incoming L1 table 4213 * before switching to it otherwise subsequent interrupts/exceptions 4214 * (including domain faults!) will jump into hyperspace. 4215 */ 4216 if (npm->pm_pl1vec != NULL) { 4217 cpu_tlb_flushID_SE((u_int)vector_page); 4218 cpu_cpwait(); 4219 *npm->pm_pl1vec = npm->pm_l1vec; 4220 PTE_SYNC(npm->pm_pl1vec); 4221 } 4222 4223 cpu_domains(ndacr); 4224 4225 if (npm == pmap_kernel() || npm == rpm) { 4226 /* 4227 * Switching to a kernel thread, or back to the 4228 * same user vmspace as before... Simply update 4229 * the TTB (no TLB flush required) 4230 */ 4231 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4232 "r"(npm->pm_l1->l1_physaddr)); 4233 cpu_cpwait(); 4234 } else { 4235 /* 4236 * Otherwise, update TTB and flush TLB 4237 */ 4238 cpu_context_switch(npm->pm_l1->l1_physaddr); 4239 if (rpm != NULL) 4240 rpm->pm_cstate.cs_tlb = 0; 4241 } 4242 4243 restore_interrupts(oldirqstate); 4244 4245 block_userspace_access = 0; 4246 4247 all_done: 4248 /* 4249 * The new pmap is resident. Make sure it's marked 4250 * as resident in the cache/TLB. 4251 */ 4252 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4253 if (npm != pmap_kernel()) 4254 pmap_recent_user = npm; 4255 4256 /* The old pmap is not longer active */ 4257 if (opm != NULL) 4258 opm->pm_activated = false; 4259 4260 /* But the new one is */ 4261 npm->pm_activated = true; 4262 } 4263 4264 void 4265 pmap_deactivate(struct lwp *l) 4266 { 4267 4268 /* 4269 * If the process is exiting, make sure pmap_activate() does 4270 * a full MMU context-switch and cache flush, which we might 4271 * otherwise skip. See PR port-arm/38950. 4272 */ 4273 if (l->l_proc->p_sflag & PS_WEXIT) 4274 pmap_previous_active_lwp = NULL; 4275 4276 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4277 } 4278 4279 void 4280 pmap_update(pmap_t pm) 4281 { 4282 4283 if (pm->pm_remove_all) { 4284 /* 4285 * Finish up the pmap_remove_all() optimisation by flushing 4286 * the TLB. 4287 */ 4288 pmap_tlb_flushID(pm); 4289 pm->pm_remove_all = false; 4290 } 4291 4292 if (pmap_is_current(pm)) { 4293 /* 4294 * If we're dealing with a current userland pmap, move its L1 4295 * to the end of the LRU. 4296 */ 4297 if (pm != pmap_kernel()) 4298 pmap_use_l1(pm); 4299 4300 /* 4301 * We can assume we're done with frobbing the cache/tlb for 4302 * now. Make sure any future pmap ops don't skip cache/tlb 4303 * flushes. 4304 */ 4305 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4306 } 4307 4308 PMAPCOUNT(updates); 4309 4310 /* 4311 * make sure TLB/cache operations have completed. 4312 */ 4313 cpu_cpwait(); 4314 } 4315 4316 void 4317 pmap_remove_all(pmap_t pm) 4318 { 4319 4320 /* 4321 * The vmspace described by this pmap is about to be torn down. 4322 * Until pmap_update() is called, UVM will only make calls 4323 * to pmap_remove(). We can make life much simpler by flushing 4324 * the cache now, and deferring TLB invalidation to pmap_update(). 4325 */ 4326 #ifdef PMAP_CACHE_VIVT 4327 pmap_idcache_wbinv_all(pm); 4328 #endif 4329 pm->pm_remove_all = true; 4330 } 4331 4332 /* 4333 * Retire the given physical map from service. 4334 * Should only be called if the map contains no valid mappings. 4335 */ 4336 void 4337 pmap_destroy(pmap_t pm) 4338 { 4339 u_int count; 4340 4341 if (pm == NULL) 4342 return; 4343 4344 if (pm->pm_remove_all) { 4345 pmap_tlb_flushID(pm); 4346 pm->pm_remove_all = false; 4347 } 4348 4349 /* 4350 * Drop reference count 4351 */ 4352 mutex_enter(&pm->pm_lock); 4353 count = --pm->pm_obj.uo_refs; 4354 mutex_exit(&pm->pm_lock); 4355 if (count > 0) { 4356 if (pmap_is_current(pm)) { 4357 if (pm != pmap_kernel()) 4358 pmap_use_l1(pm); 4359 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4360 } 4361 return; 4362 } 4363 4364 /* 4365 * reference count is zero, free pmap resources and then free pmap. 4366 */ 4367 4368 if (vector_page < KERNEL_BASE) { 4369 KDASSERT(!pmap_is_current(pm)); 4370 4371 /* Remove the vector page mapping */ 4372 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4373 pmap_update(pm); 4374 } 4375 4376 LIST_REMOVE(pm, pm_list); 4377 4378 pmap_free_l1(pm); 4379 4380 if (pmap_recent_user == pm) 4381 pmap_recent_user = NULL; 4382 4383 UVM_OBJ_DESTROY(&pm->pm_obj); 4384 4385 /* return the pmap to the pool */ 4386 pool_cache_put(&pmap_cache, pm); 4387 } 4388 4389 4390 /* 4391 * void pmap_reference(pmap_t pm) 4392 * 4393 * Add a reference to the specified pmap. 4394 */ 4395 void 4396 pmap_reference(pmap_t pm) 4397 { 4398 4399 if (pm == NULL) 4400 return; 4401 4402 pmap_use_l1(pm); 4403 4404 mutex_enter(&pm->pm_lock); 4405 pm->pm_obj.uo_refs++; 4406 mutex_exit(&pm->pm_lock); 4407 } 4408 4409 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4410 4411 static struct evcnt pmap_prefer_nochange_ev = 4412 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4413 static struct evcnt pmap_prefer_change_ev = 4414 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4415 4416 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4417 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4418 4419 void 4420 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4421 { 4422 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4423 vaddr_t va = *vap; 4424 vaddr_t diff = (hint - va) & mask; 4425 if (diff == 0) { 4426 pmap_prefer_nochange_ev.ev_count++; 4427 } else { 4428 pmap_prefer_change_ev.ev_count++; 4429 if (__predict_false(td)) 4430 va -= mask + 1; 4431 *vap = va + diff; 4432 } 4433 } 4434 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4435 4436 /* 4437 * pmap_zero_page() 4438 * 4439 * Zero a given physical page by mapping it at a page hook point. 4440 * In doing the zero page op, the page we zero is mapped cachable, as with 4441 * StrongARM accesses to non-cached pages are non-burst making writing 4442 * _any_ bulk data very slow. 4443 */ 4444 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4445 void 4446 pmap_zero_page_generic(paddr_t phys) 4447 { 4448 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4449 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4450 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4451 #endif 4452 #ifdef PMAP_CACHE_VIPT 4453 /* Choose the last page color it had, if any */ 4454 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4455 #else 4456 const vsize_t va_offset = 0; 4457 #endif 4458 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4459 4460 #ifdef DEBUG 4461 if (!SLIST_EMPTY(&md->pvh_list)) 4462 panic("pmap_zero_page: page has mappings"); 4463 #endif 4464 4465 KDASSERT((phys & PGOFSET) == 0); 4466 4467 /* 4468 * Hook in the page, zero it, and purge the cache for that 4469 * zeroed page. Invalidate the TLB as needed. 4470 */ 4471 *ptep = L2_S_PROTO | phys | 4472 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4473 PTE_SYNC(ptep); 4474 cpu_tlb_flushD_SE(cdstp + va_offset); 4475 cpu_cpwait(); 4476 bzero_page(cdstp + va_offset); 4477 /* 4478 * Unmap the page. 4479 */ 4480 *ptep = 0; 4481 PTE_SYNC(ptep); 4482 cpu_tlb_flushD_SE(cdstp + va_offset); 4483 #ifdef PMAP_CACHE_VIVT 4484 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4485 #endif 4486 #ifdef PMAP_CACHE_VIPT 4487 /* 4488 * This page is now cache resident so it now has a page color. 4489 * Any contents have been obliterated so clear the EXEC flag. 4490 */ 4491 if (!pmap_is_page_colored_p(md)) { 4492 PMAPCOUNT(vac_color_new); 4493 md->pvh_attrs |= PVF_COLORED; 4494 } 4495 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4496 md->pvh_attrs &= ~PVF_EXEC; 4497 PMAPCOUNT(exec_discarded_zero); 4498 } 4499 md->pvh_attrs |= PVF_DIRTY; 4500 #endif 4501 } 4502 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4503 4504 #if ARM_MMU_XSCALE == 1 4505 void 4506 pmap_zero_page_xscale(paddr_t phys) 4507 { 4508 #ifdef DEBUG 4509 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4510 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4511 4512 if (!SLIST_EMPTY(&md->pvh_list)) 4513 panic("pmap_zero_page: page has mappings"); 4514 #endif 4515 4516 KDASSERT((phys & PGOFSET) == 0); 4517 4518 /* 4519 * Hook in the page, zero it, and purge the cache for that 4520 * zeroed page. Invalidate the TLB as needed. 4521 */ 4522 *cdst_pte = L2_S_PROTO | phys | 4523 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4524 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4525 PTE_SYNC(cdst_pte); 4526 cpu_tlb_flushD_SE(cdstp); 4527 cpu_cpwait(); 4528 bzero_page(cdstp); 4529 xscale_cache_clean_minidata(); 4530 } 4531 #endif /* ARM_MMU_XSCALE == 1 */ 4532 4533 /* pmap_pageidlezero() 4534 * 4535 * The same as above, except that we assume that the page is not 4536 * mapped. This means we never have to flush the cache first. Called 4537 * from the idle loop. 4538 */ 4539 bool 4540 pmap_pageidlezero(paddr_t phys) 4541 { 4542 unsigned int i; 4543 int *ptr; 4544 bool rv = true; 4545 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4546 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4547 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4548 #endif 4549 #ifdef PMAP_CACHE_VIPT 4550 /* Choose the last page color it had, if any */ 4551 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4552 #else 4553 const vsize_t va_offset = 0; 4554 #endif 4555 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4556 4557 4558 #ifdef DEBUG 4559 if (!SLIST_EMPTY(&md->pvh_list)) 4560 panic("pmap_pageidlezero: page has mappings"); 4561 #endif 4562 4563 KDASSERT((phys & PGOFSET) == 0); 4564 4565 /* 4566 * Hook in the page, zero it, and purge the cache for that 4567 * zeroed page. Invalidate the TLB as needed. 4568 */ 4569 *ptep = L2_S_PROTO | phys | 4570 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4571 PTE_SYNC(ptep); 4572 cpu_tlb_flushD_SE(cdstp + va_offset); 4573 cpu_cpwait(); 4574 4575 for (i = 0, ptr = (int *)(cdstp + va_offset); 4576 i < (PAGE_SIZE / sizeof(int)); i++) { 4577 if (sched_curcpu_runnable_p() != 0) { 4578 /* 4579 * A process has become ready. Abort now, 4580 * so we don't keep it waiting while we 4581 * do slow memory access to finish this 4582 * page. 4583 */ 4584 rv = false; 4585 break; 4586 } 4587 *ptr++ = 0; 4588 } 4589 4590 #ifdef PMAP_CACHE_VIVT 4591 if (rv) 4592 /* 4593 * if we aborted we'll rezero this page again later so don't 4594 * purge it unless we finished it 4595 */ 4596 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4597 #elif defined(PMAP_CACHE_VIPT) 4598 /* 4599 * This page is now cache resident so it now has a page color. 4600 * Any contents have been obliterated so clear the EXEC flag. 4601 */ 4602 if (!pmap_is_page_colored_p(md)) { 4603 PMAPCOUNT(vac_color_new); 4604 md->pvh_attrs |= PVF_COLORED; 4605 } 4606 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4607 md->pvh_attrs &= ~PVF_EXEC; 4608 PMAPCOUNT(exec_discarded_zero); 4609 } 4610 #endif 4611 /* 4612 * Unmap the page. 4613 */ 4614 *ptep = 0; 4615 PTE_SYNC(ptep); 4616 cpu_tlb_flushD_SE(cdstp + va_offset); 4617 4618 return (rv); 4619 } 4620 4621 /* 4622 * pmap_copy_page() 4623 * 4624 * Copy one physical page into another, by mapping the pages into 4625 * hook points. The same comment regarding cachability as in 4626 * pmap_zero_page also applies here. 4627 */ 4628 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4629 void 4630 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4631 { 4632 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4633 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4634 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4635 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4636 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4637 #endif 4638 #ifdef PMAP_CACHE_VIPT 4639 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4640 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4641 #else 4642 const vsize_t src_va_offset = 0; 4643 const vsize_t dst_va_offset = 0; 4644 #endif 4645 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4646 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4647 4648 #ifdef DEBUG 4649 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4650 panic("pmap_copy_page: dst page has mappings"); 4651 #endif 4652 4653 #ifdef PMAP_CACHE_VIPT 4654 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4655 #endif 4656 KDASSERT((src & PGOFSET) == 0); 4657 KDASSERT((dst & PGOFSET) == 0); 4658 4659 /* 4660 * Clean the source page. Hold the source page's lock for 4661 * the duration of the copy so that no other mappings can 4662 * be created while we have a potentially aliased mapping. 4663 */ 4664 simple_lock(&src_md->pvh_slock); 4665 #ifdef PMAP_CACHE_VIVT 4666 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4667 #endif 4668 4669 /* 4670 * Map the pages into the page hook points, copy them, and purge 4671 * the cache for the appropriate page. Invalidate the TLB 4672 * as required. 4673 */ 4674 *src_ptep = L2_S_PROTO 4675 | src 4676 #ifdef PMAP_CACHE_VIPT 4677 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4678 #endif 4679 #ifdef PMAP_CACHE_VIVT 4680 | pte_l2_s_cache_mode 4681 #endif 4682 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4683 *dst_ptep = L2_S_PROTO | dst | 4684 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4685 PTE_SYNC(src_ptep); 4686 PTE_SYNC(dst_ptep); 4687 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4688 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4689 cpu_cpwait(); 4690 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4691 #ifdef PMAP_CACHE_VIVT 4692 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4693 #endif 4694 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4695 #ifdef PMAP_CACHE_VIVT 4696 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4697 #endif 4698 /* 4699 * Unmap the pages. 4700 */ 4701 *src_ptep = 0; 4702 *dst_ptep = 0; 4703 PTE_SYNC(src_ptep); 4704 PTE_SYNC(dst_ptep); 4705 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4706 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4707 #ifdef PMAP_CACHE_VIPT 4708 /* 4709 * Now that the destination page is in the cache, mark it as colored. 4710 * If this was an exec page, discard it. 4711 */ 4712 if (!pmap_is_page_colored_p(dst_md)) { 4713 PMAPCOUNT(vac_color_new); 4714 dst_md->pvh_attrs |= PVF_COLORED; 4715 } 4716 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4717 dst_md->pvh_attrs &= ~PVF_EXEC; 4718 PMAPCOUNT(exec_discarded_copy); 4719 } 4720 dst_md->pvh_attrs |= PVF_DIRTY; 4721 #endif 4722 } 4723 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4724 4725 #if ARM_MMU_XSCALE == 1 4726 void 4727 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4728 { 4729 struct vm_page_md *src_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(src)); 4730 #ifdef DEBUG 4731 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4732 4733 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4734 panic("pmap_copy_page: dst page has mappings"); 4735 #endif 4736 4737 KDASSERT((src & PGOFSET) == 0); 4738 KDASSERT((dst & PGOFSET) == 0); 4739 4740 /* 4741 * Clean the source page. Hold the source page's lock for 4742 * the duration of the copy so that no other mappings can 4743 * be created while we have a potentially aliased mapping. 4744 */ 4745 simple_lock(&src_md->pvh_slock); 4746 #ifdef PMAP_CACHE_VIVT 4747 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4748 #endif 4749 4750 /* 4751 * Map the pages into the page hook points, copy them, and purge 4752 * the cache for the appropriate page. Invalidate the TLB 4753 * as required. 4754 */ 4755 *csrc_pte = L2_S_PROTO | src | 4756 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4757 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4758 PTE_SYNC(csrc_pte); 4759 *cdst_pte = L2_S_PROTO | dst | 4760 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4761 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4762 PTE_SYNC(cdst_pte); 4763 cpu_tlb_flushD_SE(csrcp); 4764 cpu_tlb_flushD_SE(cdstp); 4765 cpu_cpwait(); 4766 bcopy_page(csrcp, cdstp); 4767 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4768 xscale_cache_clean_minidata(); 4769 } 4770 #endif /* ARM_MMU_XSCALE == 1 */ 4771 4772 /* 4773 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4774 * 4775 * Return the start and end addresses of the kernel's virtual space. 4776 * These values are setup in pmap_bootstrap and are updated as pages 4777 * are allocated. 4778 */ 4779 void 4780 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4781 { 4782 *start = virtual_avail; 4783 *end = virtual_end; 4784 } 4785 4786 /* 4787 * Helper function for pmap_grow_l2_bucket() 4788 */ 4789 static inline int 4790 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4791 { 4792 struct l2_bucket *l2b; 4793 pt_entry_t *ptep; 4794 paddr_t pa; 4795 4796 if (uvm.page_init_done == false) { 4797 #ifdef PMAP_STEAL_MEMORY 4798 pv_addr_t pv; 4799 pmap_boot_pagealloc(PAGE_SIZE, 4800 #ifdef PMAP_CACHE_VIPT 4801 arm_cache_prefer_mask, 4802 va & arm_cache_prefer_mask, 4803 #else 4804 0, 0, 4805 #endif 4806 &pv); 4807 pa = pv.pv_pa; 4808 #else 4809 if (uvm_page_physget(&pa) == false) 4810 return (1); 4811 #endif /* PMAP_STEAL_MEMORY */ 4812 } else { 4813 struct vm_page *pg; 4814 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4815 if (pg == NULL) 4816 return (1); 4817 pa = VM_PAGE_TO_PHYS(pg); 4818 #ifdef PMAP_CACHE_VIPT 4819 #ifdef DIAGNOSTIC 4820 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4821 #endif 4822 /* 4823 * This new page must not have any mappings. Enter it via 4824 * pmap_kenter_pa and let that routine do the hard work. 4825 */ 4826 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4827 pmap_kenter_pa(va, pa, 4828 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4829 #endif 4830 } 4831 4832 if (pap) 4833 *pap = pa; 4834 4835 PMAPCOUNT(pt_mappings); 4836 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4837 KDASSERT(l2b != NULL); 4838 4839 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4840 *ptep = L2_S_PROTO | pa | cache_mode | 4841 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4842 PTE_SYNC(ptep); 4843 memset((void *)va, 0, PAGE_SIZE); 4844 return (0); 4845 } 4846 4847 /* 4848 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4849 * used by pmap_growkernel(). 4850 */ 4851 static inline struct l2_bucket * 4852 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4853 { 4854 struct l2_dtable *l2; 4855 struct l2_bucket *l2b; 4856 u_short l1idx; 4857 vaddr_t nva; 4858 4859 l1idx = L1_IDX(va); 4860 4861 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4862 /* 4863 * No mapping at this address, as there is 4864 * no entry in the L1 table. 4865 * Need to allocate a new l2_dtable. 4866 */ 4867 nva = pmap_kernel_l2dtable_kva; 4868 if ((nva & PGOFSET) == 0) { 4869 /* 4870 * Need to allocate a backing page 4871 */ 4872 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4873 return (NULL); 4874 } 4875 4876 l2 = (struct l2_dtable *)nva; 4877 nva += sizeof(struct l2_dtable); 4878 4879 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4880 /* 4881 * The new l2_dtable straddles a page boundary. 4882 * Map in another page to cover it. 4883 */ 4884 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4885 return (NULL); 4886 } 4887 4888 pmap_kernel_l2dtable_kva = nva; 4889 4890 /* 4891 * Link it into the parent pmap 4892 */ 4893 pm->pm_l2[L2_IDX(l1idx)] = l2; 4894 } 4895 4896 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4897 4898 /* 4899 * Fetch pointer to the L2 page table associated with the address. 4900 */ 4901 if (l2b->l2b_kva == NULL) { 4902 pt_entry_t *ptep; 4903 4904 /* 4905 * No L2 page table has been allocated. Chances are, this 4906 * is because we just allocated the l2_dtable, above. 4907 */ 4908 nva = pmap_kernel_l2ptp_kva; 4909 ptep = (pt_entry_t *)nva; 4910 if ((nva & PGOFSET) == 0) { 4911 /* 4912 * Need to allocate a backing page 4913 */ 4914 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4915 &pmap_kernel_l2ptp_phys)) 4916 return (NULL); 4917 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4918 } 4919 4920 l2->l2_occupancy++; 4921 l2b->l2b_kva = ptep; 4922 l2b->l2b_l1idx = l1idx; 4923 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4924 4925 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4926 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4927 } 4928 4929 return (l2b); 4930 } 4931 4932 vaddr_t 4933 pmap_growkernel(vaddr_t maxkvaddr) 4934 { 4935 pmap_t kpm = pmap_kernel(); 4936 struct l1_ttable *l1; 4937 struct l2_bucket *l2b; 4938 pd_entry_t *pl1pd; 4939 int s; 4940 4941 if (maxkvaddr <= pmap_curmaxkvaddr) 4942 goto out; /* we are OK */ 4943 4944 NPDEBUG(PDB_GROWKERN, 4945 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4946 pmap_curmaxkvaddr, maxkvaddr)); 4947 4948 KDASSERT(maxkvaddr <= virtual_end); 4949 4950 /* 4951 * whoops! we need to add kernel PTPs 4952 */ 4953 4954 s = splhigh(); /* to be safe */ 4955 mutex_enter(&kpm->pm_lock); 4956 4957 /* Map 1MB at a time */ 4958 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4959 4960 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4961 KDASSERT(l2b != NULL); 4962 4963 /* Distribute new L1 entry to all other L1s */ 4964 SLIST_FOREACH(l1, &l1_list, l1_link) { 4965 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4966 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4967 L1_C_PROTO; 4968 PTE_SYNC(pl1pd); 4969 } 4970 } 4971 4972 /* 4973 * flush out the cache, expensive but growkernel will happen so 4974 * rarely 4975 */ 4976 cpu_dcache_wbinv_all(); 4977 cpu_tlb_flushD(); 4978 cpu_cpwait(); 4979 4980 mutex_exit(&kpm->pm_lock); 4981 splx(s); 4982 4983 out: 4984 return (pmap_curmaxkvaddr); 4985 } 4986 4987 /************************ Utility routines ****************************/ 4988 4989 /* 4990 * vector_page_setprot: 4991 * 4992 * Manipulate the protection of the vector page. 4993 */ 4994 void 4995 vector_page_setprot(int prot) 4996 { 4997 struct l2_bucket *l2b; 4998 pt_entry_t *ptep; 4999 5000 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5001 KDASSERT(l2b != NULL); 5002 5003 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5004 5005 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 5006 PTE_SYNC(ptep); 5007 cpu_tlb_flushD_SE(vector_page); 5008 cpu_cpwait(); 5009 } 5010 5011 /* 5012 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5013 * Returns true if the mapping exists, else false. 5014 * 5015 * NOTE: This function is only used by a couple of arm-specific modules. 5016 * It is not safe to take any pmap locks here, since we could be right 5017 * in the middle of debugging the pmap anyway... 5018 * 5019 * It is possible for this routine to return false even though a valid 5020 * mapping does exist. This is because we don't lock, so the metadata 5021 * state may be inconsistent. 5022 * 5023 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5024 * a "section" mapping. 5025 */ 5026 bool 5027 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5028 { 5029 struct l2_dtable *l2; 5030 pd_entry_t *pl1pd, l1pd; 5031 pt_entry_t *ptep; 5032 u_short l1idx; 5033 5034 if (pm->pm_l1 == NULL) 5035 return false; 5036 5037 l1idx = L1_IDX(va); 5038 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5039 l1pd = *pl1pd; 5040 5041 if (l1pte_section_p(l1pd)) { 5042 *ptp = NULL; 5043 return true; 5044 } 5045 5046 if (pm->pm_l2 == NULL) 5047 return false; 5048 5049 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5050 5051 if (l2 == NULL || 5052 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5053 return false; 5054 } 5055 5056 *ptp = &ptep[l2pte_index(va)]; 5057 return true; 5058 } 5059 5060 bool 5061 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5062 { 5063 u_short l1idx; 5064 5065 if (pm->pm_l1 == NULL) 5066 return false; 5067 5068 l1idx = L1_IDX(va); 5069 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5070 5071 return true; 5072 } 5073 5074 /************************ Bootstrapping routines ****************************/ 5075 5076 static void 5077 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5078 { 5079 int i; 5080 5081 l1->l1_kva = l1pt; 5082 l1->l1_domain_use_count = 0; 5083 l1->l1_domain_first = 0; 5084 5085 for (i = 0; i < PMAP_DOMAINS; i++) 5086 l1->l1_domain_free[i] = i + 1; 5087 5088 /* 5089 * Copy the kernel's L1 entries to each new L1. 5090 */ 5091 if (pmap_initialized) 5092 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5093 5094 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5095 &l1->l1_physaddr) == false) 5096 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5097 5098 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5099 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5100 } 5101 5102 /* 5103 * pmap_bootstrap() is called from the board-specific initarm() routine 5104 * once the kernel L1/L2 descriptors tables have been set up. 5105 * 5106 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5107 * spread over a number of disparate files/functions. 5108 * 5109 * We are passed the following parameters 5110 * - kernel_l1pt 5111 * This is a pointer to the base of the kernel's L1 translation table. 5112 * - vstart 5113 * 1MB-aligned start of managed kernel virtual memory. 5114 * - vend 5115 * 1MB-aligned end of managed kernel virtual memory. 5116 * 5117 * We use the first parameter to build the metadata (struct l1_ttable and 5118 * struct l2_dtable) necessary to track kernel mappings. 5119 */ 5120 #define PMAP_STATIC_L2_SIZE 16 5121 void 5122 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5123 { 5124 static struct l1_ttable static_l1; 5125 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5126 struct l1_ttable *l1 = &static_l1; 5127 struct l2_dtable *l2; 5128 struct l2_bucket *l2b; 5129 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5130 pmap_t pm = pmap_kernel(); 5131 pd_entry_t pde; 5132 pt_entry_t *ptep; 5133 paddr_t pa; 5134 vaddr_t va; 5135 vsize_t size; 5136 int nptes, l1idx, l2idx, l2next = 0; 5137 5138 /* 5139 * Initialise the kernel pmap object 5140 */ 5141 pm->pm_l1 = l1; 5142 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5143 pm->pm_activated = true; 5144 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5145 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5146 5147 /* 5148 * Scan the L1 translation table created by initarm() and create 5149 * the required metadata for all valid mappings found in it. 5150 */ 5151 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5152 pde = l1pt[l1idx]; 5153 5154 /* 5155 * We're only interested in Coarse mappings. 5156 * pmap_extract() can deal with section mappings without 5157 * recourse to checking L2 metadata. 5158 */ 5159 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5160 continue; 5161 5162 /* 5163 * Lookup the KVA of this L2 descriptor table 5164 */ 5165 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5166 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5167 if (ptep == NULL) { 5168 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5169 (u_int)l1idx << L1_S_SHIFT, pa); 5170 } 5171 5172 /* 5173 * Fetch the associated L2 metadata structure. 5174 * Allocate a new one if necessary. 5175 */ 5176 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5177 if (l2next == PMAP_STATIC_L2_SIZE) 5178 panic("pmap_bootstrap: out of static L2s"); 5179 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5180 } 5181 5182 /* 5183 * One more L1 slot tracked... 5184 */ 5185 l2->l2_occupancy++; 5186 5187 /* 5188 * Fill in the details of the L2 descriptor in the 5189 * appropriate bucket. 5190 */ 5191 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5192 l2b->l2b_kva = ptep; 5193 l2b->l2b_phys = pa; 5194 l2b->l2b_l1idx = l1idx; 5195 5196 /* 5197 * Establish an initial occupancy count for this descriptor 5198 */ 5199 for (l2idx = 0; 5200 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5201 l2idx++) { 5202 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5203 l2b->l2b_occupancy++; 5204 } 5205 } 5206 5207 /* 5208 * Make sure the descriptor itself has the correct cache mode. 5209 * If not, fix it, but whine about the problem. Port-meisters 5210 * should consider this a clue to fix up their initarm() 5211 * function. :) 5212 */ 5213 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5214 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5215 "L2 pte @ %p\n", ptep); 5216 } 5217 } 5218 5219 /* 5220 * Ensure the primary (kernel) L1 has the correct cache mode for 5221 * a page table. Bitch if it is not correctly set. 5222 */ 5223 for (va = (vaddr_t)l1pt; 5224 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5225 if (pmap_set_pt_cache_mode(l1pt, va)) 5226 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5227 "primary L1 @ 0x%lx\n", va); 5228 } 5229 5230 cpu_dcache_wbinv_all(); 5231 cpu_tlb_flushID(); 5232 cpu_cpwait(); 5233 5234 /* 5235 * now we allocate the "special" VAs which are used for tmp mappings 5236 * by the pmap (and other modules). we allocate the VAs by advancing 5237 * virtual_avail (note that there are no pages mapped at these VAs). 5238 * 5239 * Managed KVM space start from wherever initarm() tells us. 5240 */ 5241 virtual_avail = vstart; 5242 virtual_end = vend; 5243 5244 #ifdef PMAP_CACHE_VIPT 5245 /* 5246 * If we have a VIPT cache, we need one page/pte per possible alias 5247 * page so we won't violate cache aliasing rules. 5248 */ 5249 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5250 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5251 #else 5252 nptes = 1; 5253 #endif 5254 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5255 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5256 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5257 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5258 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5259 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5260 (void *)&msgbufaddr, NULL); 5261 5262 /* 5263 * Allocate a range of kernel virtual address space to be used 5264 * for L2 descriptor tables and metadata allocation in 5265 * pmap_growkernel(). 5266 */ 5267 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5268 pmap_alloc_specials(&virtual_avail, 5269 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5270 &pmap_kernel_l2ptp_kva, NULL); 5271 5272 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5273 pmap_alloc_specials(&virtual_avail, 5274 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5275 &pmap_kernel_l2dtable_kva, NULL); 5276 5277 /* 5278 * init the static-global locks and global pmap list. 5279 */ 5280 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5281 5282 /* 5283 * We can now initialise the first L1's metadata. 5284 */ 5285 SLIST_INIT(&l1_list); 5286 TAILQ_INIT(&l1_lru_list); 5287 simple_lock_init(&l1_lru_lock); 5288 pmap_init_l1(l1, l1pt); 5289 5290 /* Set up vector page L1 details, if necessary */ 5291 if (vector_page < KERNEL_BASE) { 5292 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5293 l2b = pmap_get_l2_bucket(pm, vector_page); 5294 KDASSERT(l2b != NULL); 5295 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5296 L1_C_DOM(pm->pm_domain); 5297 } else 5298 pm->pm_pl1vec = NULL; 5299 5300 /* 5301 * Initialize the pmap cache 5302 */ 5303 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5304 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5305 LIST_INIT(&pmap_pmaps); 5306 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5307 5308 /* 5309 * Initialize the pv pool. 5310 */ 5311 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5312 &pmap_bootstrap_pv_allocator, IPL_NONE); 5313 5314 /* 5315 * Initialize the L2 dtable pool and cache. 5316 */ 5317 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5318 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5319 5320 /* 5321 * Initialise the L2 descriptor table pool and cache 5322 */ 5323 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5324 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5325 pmap_l2ptp_ctor, NULL, NULL); 5326 5327 cpu_dcache_wbinv_all(); 5328 } 5329 5330 static int 5331 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5332 { 5333 pd_entry_t *pdep, pde; 5334 pt_entry_t *ptep, pte; 5335 vaddr_t pa; 5336 int rv = 0; 5337 5338 /* 5339 * Make sure the descriptor itself has the correct cache mode 5340 */ 5341 pdep = &kl1[L1_IDX(va)]; 5342 pde = *pdep; 5343 5344 if (l1pte_section_p(pde)) { 5345 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5346 *pdep = (pde & ~L1_S_CACHE_MASK) | 5347 pte_l1_s_cache_mode_pt; 5348 PTE_SYNC(pdep); 5349 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5350 rv = 1; 5351 } 5352 } else { 5353 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5354 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5355 if (ptep == NULL) 5356 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5357 5358 ptep = &ptep[l2pte_index(va)]; 5359 pte = *ptep; 5360 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5361 *ptep = (pte & ~L2_S_CACHE_MASK) | 5362 pte_l2_s_cache_mode_pt; 5363 PTE_SYNC(ptep); 5364 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5365 rv = 1; 5366 } 5367 } 5368 5369 return (rv); 5370 } 5371 5372 static void 5373 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5374 { 5375 vaddr_t va = *availp; 5376 struct l2_bucket *l2b; 5377 5378 if (ptep) { 5379 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5380 if (l2b == NULL) 5381 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5382 5383 if (ptep) 5384 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5385 } 5386 5387 *vap = va; 5388 *availp = va + (PAGE_SIZE * pages); 5389 } 5390 5391 void 5392 pmap_init(void) 5393 { 5394 5395 /* 5396 * Set the available memory vars - These do not map to real memory 5397 * addresses and cannot as the physical memory is fragmented. 5398 * They are used by ps for %mem calculations. 5399 * One could argue whether this should be the entire memory or just 5400 * the memory that is useable in a user process. 5401 */ 5402 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5403 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5404 5405 /* 5406 * Now we need to free enough pv_entry structures to allow us to get 5407 * the kmem_map/kmem_object allocated and inited (done after this 5408 * function is finished). to do this we allocate one bootstrap page out 5409 * of kernel_map and use it to provide an initial pool of pv_entry 5410 * structures. we never free this page. 5411 */ 5412 pool_setlowat(&pmap_pv_pool, 5413 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5414 5415 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5416 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5417 UVM_KMF_WIRED|UVM_KMF_ZERO); 5418 5419 pmap_initialized = true; 5420 } 5421 5422 static vaddr_t last_bootstrap_page = 0; 5423 static void *free_bootstrap_pages = NULL; 5424 5425 static void * 5426 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5427 { 5428 extern void *pool_page_alloc(struct pool *, int); 5429 vaddr_t new_page; 5430 void *rv; 5431 5432 if (pmap_initialized) 5433 return (pool_page_alloc(pp, flags)); 5434 5435 if (free_bootstrap_pages) { 5436 rv = free_bootstrap_pages; 5437 free_bootstrap_pages = *((void **)rv); 5438 return (rv); 5439 } 5440 5441 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5442 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5443 5444 KASSERT(new_page > last_bootstrap_page); 5445 last_bootstrap_page = new_page; 5446 return ((void *)new_page); 5447 } 5448 5449 static void 5450 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5451 { 5452 extern void pool_page_free(struct pool *, void *); 5453 5454 if ((vaddr_t)v <= last_bootstrap_page) { 5455 *((void **)v) = free_bootstrap_pages; 5456 free_bootstrap_pages = v; 5457 return; 5458 } 5459 5460 if (pmap_initialized) { 5461 pool_page_free(pp, v); 5462 return; 5463 } 5464 } 5465 5466 /* 5467 * pmap_postinit() 5468 * 5469 * This routine is called after the vm and kmem subsystems have been 5470 * initialised. This allows the pmap code to perform any initialisation 5471 * that can only be done one the memory allocation is in place. 5472 */ 5473 void 5474 pmap_postinit(void) 5475 { 5476 extern paddr_t physical_start, physical_end; 5477 struct l2_bucket *l2b; 5478 struct l1_ttable *l1; 5479 struct pglist plist; 5480 struct vm_page *m; 5481 pd_entry_t *pl1pt; 5482 pt_entry_t *ptep, pte; 5483 vaddr_t va, eva; 5484 u_int loop, needed; 5485 int error; 5486 5487 pool_cache_setlowat(&pmap_l2ptp_cache, 5488 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5489 pool_cache_setlowat(&pmap_l2dtable_cache, 5490 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5491 5492 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5493 needed -= 1; 5494 5495 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5496 5497 for (loop = 0; loop < needed; loop++, l1++) { 5498 /* Allocate a L1 page table */ 5499 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5500 if (va == 0) 5501 panic("Cannot allocate L1 KVM"); 5502 5503 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5504 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5505 if (error) 5506 panic("Cannot allocate L1 physical pages"); 5507 5508 m = TAILQ_FIRST(&plist); 5509 eva = va + L1_TABLE_SIZE; 5510 pl1pt = (pd_entry_t *)va; 5511 5512 while (m && va < eva) { 5513 paddr_t pa = VM_PAGE_TO_PHYS(m); 5514 5515 pmap_kenter_pa(va, pa, 5516 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5517 5518 /* 5519 * Make sure the L1 descriptor table is mapped 5520 * with the cache-mode set to write-through. 5521 */ 5522 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5523 KDASSERT(l2b != NULL); 5524 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5525 pte = *ptep; 5526 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5527 *ptep = pte; 5528 PTE_SYNC(ptep); 5529 cpu_tlb_flushD_SE(va); 5530 5531 va += PAGE_SIZE; 5532 m = TAILQ_NEXT(m, pageq.queue); 5533 } 5534 5535 #ifdef DIAGNOSTIC 5536 if (m) 5537 panic("pmap_alloc_l1pt: pglist not empty"); 5538 #endif /* DIAGNOSTIC */ 5539 5540 pmap_init_l1(l1, pl1pt); 5541 } 5542 5543 #ifdef DEBUG 5544 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5545 needed); 5546 #endif 5547 } 5548 5549 /* 5550 * Note that the following routines are used by board-specific initialisation 5551 * code to configure the initial kernel page tables. 5552 * 5553 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5554 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5555 * behaviour of the old pmap, and provides an easy migration path for 5556 * initial bring-up of the new pmap on existing ports. Fortunately, 5557 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5558 * will be deprecated. 5559 * 5560 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5561 * tables. 5562 */ 5563 5564 /* 5565 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5566 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5567 * find them as necessary. 5568 * 5569 * Note that the data on this list MUST remain valid after initarm() returns, 5570 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5571 */ 5572 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5573 5574 static vaddr_t 5575 kernel_pt_lookup(paddr_t pa) 5576 { 5577 pv_addr_t *pv; 5578 5579 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5580 #ifndef ARM32_NEW_VM_LAYOUT 5581 if (pv->pv_pa == (pa & ~PGOFSET)) 5582 return (pv->pv_va | (pa & PGOFSET)); 5583 #else 5584 if (pv->pv_pa == pa) 5585 return (pv->pv_va); 5586 #endif 5587 } 5588 return (0); 5589 } 5590 5591 /* 5592 * pmap_map_section: 5593 * 5594 * Create a single section mapping. 5595 */ 5596 void 5597 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5598 { 5599 pd_entry_t *pde = (pd_entry_t *) l1pt; 5600 pd_entry_t fl; 5601 5602 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5603 5604 switch (cache) { 5605 case PTE_NOCACHE: 5606 default: 5607 fl = 0; 5608 break; 5609 5610 case PTE_CACHE: 5611 fl = pte_l1_s_cache_mode; 5612 break; 5613 5614 case PTE_PAGETABLE: 5615 fl = pte_l1_s_cache_mode_pt; 5616 break; 5617 } 5618 5619 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5620 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5621 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5622 } 5623 5624 /* 5625 * pmap_map_entry: 5626 * 5627 * Create a single page mapping. 5628 */ 5629 void 5630 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5631 { 5632 pd_entry_t *pde = (pd_entry_t *) l1pt; 5633 pt_entry_t fl; 5634 pt_entry_t *pte; 5635 5636 KASSERT(((va | pa) & PGOFSET) == 0); 5637 5638 switch (cache) { 5639 case PTE_NOCACHE: 5640 default: 5641 fl = 0; 5642 break; 5643 5644 case PTE_CACHE: 5645 fl = pte_l2_s_cache_mode; 5646 break; 5647 5648 case PTE_PAGETABLE: 5649 fl = pte_l2_s_cache_mode_pt; 5650 break; 5651 } 5652 5653 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5654 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5655 5656 #ifndef ARM32_NEW_VM_LAYOUT 5657 pte = (pt_entry_t *) 5658 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5659 #else 5660 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5661 #endif 5662 if (pte == NULL) 5663 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5664 5665 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5666 #ifndef ARM32_NEW_VM_LAYOUT 5667 pte += (va >> PGSHIFT) & 0x3ff; 5668 #else 5669 pte += l2pte_index(va); 5670 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5671 #endif 5672 *pte = fl; 5673 PTE_SYNC(pte); 5674 } 5675 5676 /* 5677 * pmap_link_l2pt: 5678 * 5679 * Link the L2 page table specified by "l2pv" into the L1 5680 * page table at the slot for "va". 5681 */ 5682 void 5683 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5684 { 5685 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5686 u_int slot = va >> L1_S_SHIFT; 5687 5688 #ifndef ARM32_NEW_VM_LAYOUT 5689 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5690 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5691 #endif 5692 5693 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5694 5695 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5696 #ifdef ARM32_NEW_VM_LAYOUT 5697 PTE_SYNC(&pde[slot]); 5698 #else 5699 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5700 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5701 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5702 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5703 #endif 5704 5705 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5706 } 5707 5708 /* 5709 * pmap_map_chunk: 5710 * 5711 * Map a chunk of memory using the most efficient mappings 5712 * possible (section, large page, small page) into the 5713 * provided L1 and L2 tables at the specified virtual address. 5714 */ 5715 vsize_t 5716 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5717 int prot, int cache) 5718 { 5719 pd_entry_t *pde = (pd_entry_t *) l1pt; 5720 pt_entry_t *pte, f1, f2s, f2l; 5721 vsize_t resid; 5722 int i; 5723 5724 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5725 5726 if (l1pt == 0) 5727 panic("pmap_map_chunk: no L1 table provided"); 5728 5729 #ifdef VERBOSE_INIT_ARM 5730 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5731 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5732 #endif 5733 5734 switch (cache) { 5735 case PTE_NOCACHE: 5736 default: 5737 f1 = 0; 5738 f2l = 0; 5739 f2s = 0; 5740 break; 5741 5742 case PTE_CACHE: 5743 f1 = pte_l1_s_cache_mode; 5744 f2l = pte_l2_l_cache_mode; 5745 f2s = pte_l2_s_cache_mode; 5746 break; 5747 5748 case PTE_PAGETABLE: 5749 f1 = pte_l1_s_cache_mode_pt; 5750 f2l = pte_l2_l_cache_mode_pt; 5751 f2s = pte_l2_s_cache_mode_pt; 5752 break; 5753 } 5754 5755 size = resid; 5756 5757 while (resid > 0) { 5758 /* See if we can use a section mapping. */ 5759 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5760 #ifdef VERBOSE_INIT_ARM 5761 printf("S"); 5762 #endif 5763 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5764 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5765 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5766 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5767 va += L1_S_SIZE; 5768 pa += L1_S_SIZE; 5769 resid -= L1_S_SIZE; 5770 continue; 5771 } 5772 5773 /* 5774 * Ok, we're going to use an L2 table. Make sure 5775 * one is actually in the corresponding L1 slot 5776 * for the current VA. 5777 */ 5778 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5779 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5780 5781 #ifndef ARM32_NEW_VM_LAYOUT 5782 pte = (pt_entry_t *) 5783 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5784 #else 5785 pte = (pt_entry_t *) kernel_pt_lookup( 5786 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5787 #endif 5788 if (pte == NULL) 5789 panic("pmap_map_chunk: can't find L2 table for VA" 5790 "0x%08lx", va); 5791 5792 /* See if we can use a L2 large page mapping. */ 5793 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5794 #ifdef VERBOSE_INIT_ARM 5795 printf("L"); 5796 #endif 5797 for (i = 0; i < 16; i++) { 5798 #ifndef ARM32_NEW_VM_LAYOUT 5799 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5800 L2_L_PROTO | pa | 5801 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5802 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5803 #else 5804 pte[l2pte_index(va) + i] = 5805 L2_L_PROTO | pa | 5806 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5807 PTE_SYNC(&pte[l2pte_index(va) + i]); 5808 #endif 5809 } 5810 va += L2_L_SIZE; 5811 pa += L2_L_SIZE; 5812 resid -= L2_L_SIZE; 5813 continue; 5814 } 5815 5816 /* Use a small page mapping. */ 5817 #ifdef VERBOSE_INIT_ARM 5818 printf("P"); 5819 #endif 5820 #ifndef ARM32_NEW_VM_LAYOUT 5821 pte[(va >> PGSHIFT) & 0x3ff] = 5822 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5823 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5824 #else 5825 pte[l2pte_index(va)] = 5826 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5827 PTE_SYNC(&pte[l2pte_index(va)]); 5828 #endif 5829 va += PAGE_SIZE; 5830 pa += PAGE_SIZE; 5831 resid -= PAGE_SIZE; 5832 } 5833 #ifdef VERBOSE_INIT_ARM 5834 printf("\n"); 5835 #endif 5836 return (size); 5837 } 5838 5839 /********************** Static device map routines ***************************/ 5840 5841 static const struct pmap_devmap *pmap_devmap_table; 5842 5843 /* 5844 * Register the devmap table. This is provided in case early console 5845 * initialization needs to register mappings created by bootstrap code 5846 * before pmap_devmap_bootstrap() is called. 5847 */ 5848 void 5849 pmap_devmap_register(const struct pmap_devmap *table) 5850 { 5851 5852 pmap_devmap_table = table; 5853 } 5854 5855 /* 5856 * Map all of the static regions in the devmap table, and remember 5857 * the devmap table so other parts of the kernel can look up entries 5858 * later. 5859 */ 5860 void 5861 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5862 { 5863 int i; 5864 5865 pmap_devmap_table = table; 5866 5867 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5868 #ifdef VERBOSE_INIT_ARM 5869 printf("devmap: %08lx -> %08lx @ %08lx\n", 5870 pmap_devmap_table[i].pd_pa, 5871 pmap_devmap_table[i].pd_pa + 5872 pmap_devmap_table[i].pd_size - 1, 5873 pmap_devmap_table[i].pd_va); 5874 #endif 5875 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5876 pmap_devmap_table[i].pd_pa, 5877 pmap_devmap_table[i].pd_size, 5878 pmap_devmap_table[i].pd_prot, 5879 pmap_devmap_table[i].pd_cache); 5880 } 5881 } 5882 5883 const struct pmap_devmap * 5884 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5885 { 5886 uint64_t endpa; 5887 int i; 5888 5889 if (pmap_devmap_table == NULL) 5890 return (NULL); 5891 5892 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5893 5894 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5895 if (pa >= pmap_devmap_table[i].pd_pa && 5896 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5897 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5898 return (&pmap_devmap_table[i]); 5899 } 5900 5901 return (NULL); 5902 } 5903 5904 const struct pmap_devmap * 5905 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5906 { 5907 int i; 5908 5909 if (pmap_devmap_table == NULL) 5910 return (NULL); 5911 5912 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5913 if (va >= pmap_devmap_table[i].pd_va && 5914 va + size - 1 <= pmap_devmap_table[i].pd_va + 5915 pmap_devmap_table[i].pd_size - 1) 5916 return (&pmap_devmap_table[i]); 5917 } 5918 5919 return (NULL); 5920 } 5921 5922 /********************** PTE initialization routines **************************/ 5923 5924 /* 5925 * These routines are called when the CPU type is identified to set up 5926 * the PTE prototypes, cache modes, etc. 5927 * 5928 * The variables are always here, just in case modules need to reference 5929 * them (though, they shouldn't). 5930 */ 5931 5932 pt_entry_t pte_l1_s_cache_mode; 5933 pt_entry_t pte_l1_s_wc_mode; 5934 pt_entry_t pte_l1_s_cache_mode_pt; 5935 pt_entry_t pte_l1_s_cache_mask; 5936 5937 pt_entry_t pte_l2_l_cache_mode; 5938 pt_entry_t pte_l2_l_wc_mode; 5939 pt_entry_t pte_l2_l_cache_mode_pt; 5940 pt_entry_t pte_l2_l_cache_mask; 5941 5942 pt_entry_t pte_l2_s_cache_mode; 5943 pt_entry_t pte_l2_s_wc_mode; 5944 pt_entry_t pte_l2_s_cache_mode_pt; 5945 pt_entry_t pte_l2_s_cache_mask; 5946 5947 pt_entry_t pte_l1_s_prot_u; 5948 pt_entry_t pte_l1_s_prot_w; 5949 pt_entry_t pte_l1_s_prot_ro; 5950 pt_entry_t pte_l1_s_prot_mask; 5951 5952 pt_entry_t pte_l2_s_prot_u; 5953 pt_entry_t pte_l2_s_prot_w; 5954 pt_entry_t pte_l2_s_prot_ro; 5955 pt_entry_t pte_l2_s_prot_mask; 5956 5957 pt_entry_t pte_l2_l_prot_u; 5958 pt_entry_t pte_l2_l_prot_w; 5959 pt_entry_t pte_l2_l_prot_ro; 5960 pt_entry_t pte_l2_l_prot_mask; 5961 5962 pt_entry_t pte_l1_s_proto; 5963 pt_entry_t pte_l1_c_proto; 5964 pt_entry_t pte_l2_s_proto; 5965 5966 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5967 void (*pmap_zero_page_func)(paddr_t); 5968 5969 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5970 void 5971 pmap_pte_init_generic(void) 5972 { 5973 5974 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5975 pte_l1_s_wc_mode = L1_S_B; 5976 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5977 5978 pte_l2_l_cache_mode = L2_B|L2_C; 5979 pte_l2_l_wc_mode = L2_B; 5980 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5981 5982 pte_l2_s_cache_mode = L2_B|L2_C; 5983 pte_l2_s_wc_mode = L2_B; 5984 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5985 5986 /* 5987 * If we have a write-through cache, set B and C. If 5988 * we have a write-back cache, then we assume setting 5989 * only C will make those pages write-through. 5990 */ 5991 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5992 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5993 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5994 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5995 } else { 5996 #if ARM_MMU_V6 > 1 5997 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5998 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5999 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 6000 #else 6001 pte_l1_s_cache_mode_pt = L1_S_C; 6002 pte_l2_l_cache_mode_pt = L2_C; 6003 pte_l2_s_cache_mode_pt = L2_C; 6004 #endif 6005 } 6006 6007 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6008 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6009 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6010 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6011 6012 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6013 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6014 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6015 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6016 6017 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6018 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6019 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6020 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6021 6022 pte_l1_s_proto = L1_S_PROTO_generic; 6023 pte_l1_c_proto = L1_C_PROTO_generic; 6024 pte_l2_s_proto = L2_S_PROTO_generic; 6025 6026 pmap_copy_page_func = pmap_copy_page_generic; 6027 pmap_zero_page_func = pmap_zero_page_generic; 6028 } 6029 6030 #if defined(CPU_ARM8) 6031 void 6032 pmap_pte_init_arm8(void) 6033 { 6034 6035 /* 6036 * ARM8 is compatible with generic, but we need to use 6037 * the page tables uncached. 6038 */ 6039 pmap_pte_init_generic(); 6040 6041 pte_l1_s_cache_mode_pt = 0; 6042 pte_l2_l_cache_mode_pt = 0; 6043 pte_l2_s_cache_mode_pt = 0; 6044 } 6045 #endif /* CPU_ARM8 */ 6046 6047 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6048 void 6049 pmap_pte_init_arm9(void) 6050 { 6051 6052 /* 6053 * ARM9 is compatible with generic, but we want to use 6054 * write-through caching for now. 6055 */ 6056 pmap_pte_init_generic(); 6057 6058 pte_l1_s_cache_mode = L1_S_C; 6059 pte_l2_l_cache_mode = L2_C; 6060 pte_l2_s_cache_mode = L2_C; 6061 6062 pte_l1_s_wc_mode = L1_S_B; 6063 pte_l2_l_wc_mode = L2_B; 6064 pte_l2_s_wc_mode = L2_B; 6065 6066 pte_l1_s_cache_mode_pt = L1_S_C; 6067 pte_l2_l_cache_mode_pt = L2_C; 6068 pte_l2_s_cache_mode_pt = L2_C; 6069 } 6070 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6071 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6072 6073 #if defined(CPU_ARM10) 6074 void 6075 pmap_pte_init_arm10(void) 6076 { 6077 6078 /* 6079 * ARM10 is compatible with generic, but we want to use 6080 * write-through caching for now. 6081 */ 6082 pmap_pte_init_generic(); 6083 6084 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6085 pte_l2_l_cache_mode = L2_B | L2_C; 6086 pte_l2_s_cache_mode = L2_B | L2_C; 6087 6088 pte_l1_s_cache_mode = L1_S_B; 6089 pte_l2_l_cache_mode = L2_B; 6090 pte_l2_s_cache_mode = L2_B; 6091 6092 pte_l1_s_cache_mode_pt = L1_S_C; 6093 pte_l2_l_cache_mode_pt = L2_C; 6094 pte_l2_s_cache_mode_pt = L2_C; 6095 6096 } 6097 #endif /* CPU_ARM10 */ 6098 6099 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6100 void 6101 pmap_pte_init_arm11(void) 6102 { 6103 6104 /* 6105 * ARM11 is compatible with generic, but we want to use 6106 * write-through caching for now. 6107 */ 6108 pmap_pte_init_generic(); 6109 6110 pte_l1_s_cache_mode = L1_S_C; 6111 pte_l2_l_cache_mode = L2_C; 6112 pte_l2_s_cache_mode = L2_C; 6113 6114 pte_l1_s_wc_mode = L1_S_B; 6115 pte_l2_l_wc_mode = L2_B; 6116 pte_l2_s_wc_mode = L2_B; 6117 6118 pte_l1_s_cache_mode_pt = L1_S_C; 6119 pte_l2_l_cache_mode_pt = L2_C; 6120 pte_l2_s_cache_mode_pt = L2_C; 6121 } 6122 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6123 6124 #if ARM_MMU_SA1 == 1 6125 void 6126 pmap_pte_init_sa1(void) 6127 { 6128 6129 /* 6130 * The StrongARM SA-1 cache does not have a write-through 6131 * mode. So, do the generic initialization, then reset 6132 * the page table cache mode to B=1,C=1, and note that 6133 * the PTEs need to be sync'd. 6134 */ 6135 pmap_pte_init_generic(); 6136 6137 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6138 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6139 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6140 6141 pmap_needs_pte_sync = 1; 6142 } 6143 #endif /* ARM_MMU_SA1 == 1*/ 6144 6145 #if ARM_MMU_XSCALE == 1 6146 #if (ARM_NMMUS > 1) 6147 static u_int xscale_use_minidata; 6148 #endif 6149 6150 void 6151 pmap_pte_init_xscale(void) 6152 { 6153 uint32_t auxctl; 6154 int write_through = 0; 6155 6156 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6157 pte_l1_s_wc_mode = L1_S_B; 6158 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6159 6160 pte_l2_l_cache_mode = L2_B|L2_C; 6161 pte_l2_l_wc_mode = L2_B; 6162 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6163 6164 pte_l2_s_cache_mode = L2_B|L2_C; 6165 pte_l2_s_wc_mode = L2_B; 6166 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6167 6168 pte_l1_s_cache_mode_pt = L1_S_C; 6169 pte_l2_l_cache_mode_pt = L2_C; 6170 pte_l2_s_cache_mode_pt = L2_C; 6171 6172 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6173 /* 6174 * The XScale core has an enhanced mode where writes that 6175 * miss the cache cause a cache line to be allocated. This 6176 * is significantly faster than the traditional, write-through 6177 * behavior of this case. 6178 */ 6179 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6180 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6181 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6182 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6183 6184 #ifdef XSCALE_CACHE_WRITE_THROUGH 6185 /* 6186 * Some versions of the XScale core have various bugs in 6187 * their cache units, the work-around for which is to run 6188 * the cache in write-through mode. Unfortunately, this 6189 * has a major (negative) impact on performance. So, we 6190 * go ahead and run fast-and-loose, in the hopes that we 6191 * don't line up the planets in a way that will trip the 6192 * bugs. 6193 * 6194 * However, we give you the option to be slow-but-correct. 6195 */ 6196 write_through = 1; 6197 #elif defined(XSCALE_CACHE_WRITE_BACK) 6198 /* force write back cache mode */ 6199 write_through = 0; 6200 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6201 /* 6202 * Intel PXA2[15]0 processors are known to have a bug in 6203 * write-back cache on revision 4 and earlier (stepping 6204 * A[01] and B[012]). Fixed for C0 and later. 6205 */ 6206 { 6207 uint32_t id, type; 6208 6209 id = cpufunc_id(); 6210 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6211 6212 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6213 if ((id & CPU_ID_REVISION_MASK) < 5) { 6214 /* write through for stepping A0-1 and B0-2 */ 6215 write_through = 1; 6216 } 6217 } 6218 } 6219 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6220 6221 if (write_through) { 6222 pte_l1_s_cache_mode = L1_S_C; 6223 pte_l2_l_cache_mode = L2_C; 6224 pte_l2_s_cache_mode = L2_C; 6225 } 6226 6227 #if (ARM_NMMUS > 1) 6228 xscale_use_minidata = 1; 6229 #endif 6230 6231 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6232 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6233 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6234 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6235 6236 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6237 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6238 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6239 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6240 6241 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6242 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6243 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6244 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6245 6246 pte_l1_s_proto = L1_S_PROTO_xscale; 6247 pte_l1_c_proto = L1_C_PROTO_xscale; 6248 pte_l2_s_proto = L2_S_PROTO_xscale; 6249 6250 pmap_copy_page_func = pmap_copy_page_xscale; 6251 pmap_zero_page_func = pmap_zero_page_xscale; 6252 6253 /* 6254 * Disable ECC protection of page table access, for now. 6255 */ 6256 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6257 auxctl &= ~XSCALE_AUXCTL_P; 6258 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6259 } 6260 6261 /* 6262 * xscale_setup_minidata: 6263 * 6264 * Set up the mini-data cache clean area. We require the 6265 * caller to allocate the right amount of physically and 6266 * virtually contiguous space. 6267 */ 6268 void 6269 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6270 { 6271 extern vaddr_t xscale_minidata_clean_addr; 6272 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6273 pd_entry_t *pde = (pd_entry_t *) l1pt; 6274 pt_entry_t *pte; 6275 vsize_t size; 6276 uint32_t auxctl; 6277 6278 xscale_minidata_clean_addr = va; 6279 6280 /* Round it to page size. */ 6281 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6282 6283 for (; size != 0; 6284 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6285 #ifndef ARM32_NEW_VM_LAYOUT 6286 pte = (pt_entry_t *) 6287 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6288 #else 6289 pte = (pt_entry_t *) kernel_pt_lookup( 6290 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6291 #endif 6292 if (pte == NULL) 6293 panic("xscale_setup_minidata: can't find L2 table for " 6294 "VA 0x%08lx", va); 6295 #ifndef ARM32_NEW_VM_LAYOUT 6296 pte[(va >> PGSHIFT) & 0x3ff] = 6297 #else 6298 pte[l2pte_index(va)] = 6299 #endif 6300 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6301 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6302 } 6303 6304 /* 6305 * Configure the mini-data cache for write-back with 6306 * read/write-allocate. 6307 * 6308 * NOTE: In order to reconfigure the mini-data cache, we must 6309 * make sure it contains no valid data! In order to do that, 6310 * we must issue a global data cache invalidate command! 6311 * 6312 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6313 * THIS IS VERY IMPORTANT! 6314 */ 6315 6316 /* Invalidate data and mini-data. */ 6317 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6318 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6319 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6320 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6321 } 6322 6323 /* 6324 * Change the PTEs for the specified kernel mappings such that they 6325 * will use the mini data cache instead of the main data cache. 6326 */ 6327 void 6328 pmap_uarea(vaddr_t va) 6329 { 6330 struct l2_bucket *l2b; 6331 pt_entry_t *ptep, *sptep, pte; 6332 vaddr_t next_bucket, eva; 6333 6334 #if (ARM_NMMUS > 1) 6335 if (xscale_use_minidata == 0) 6336 return; 6337 #endif 6338 6339 eva = va + USPACE; 6340 6341 while (va < eva) { 6342 next_bucket = L2_NEXT_BUCKET(va); 6343 if (next_bucket > eva) 6344 next_bucket = eva; 6345 6346 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6347 KDASSERT(l2b != NULL); 6348 6349 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6350 6351 while (va < next_bucket) { 6352 pte = *ptep; 6353 if (!l2pte_minidata(pte)) { 6354 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6355 cpu_tlb_flushD_SE(va); 6356 *ptep = pte & ~L2_B; 6357 } 6358 ptep++; 6359 va += PAGE_SIZE; 6360 } 6361 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6362 } 6363 cpu_cpwait(); 6364 } 6365 #endif /* ARM_MMU_XSCALE == 1 */ 6366 6367 6368 #if defined(CPU_ARM11MPCORE) 6369 6370 void 6371 pmap_pte_init_arm11mpcore(void) 6372 { 6373 6374 /* cache mode is controlled by 5 bits (B, C, TEX) */ 6375 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 6376 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 6377 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6378 /* use extended small page (without APn, with TEX) */ 6379 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 6380 #else 6381 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 6382 #endif 6383 6384 /* write-back, write-allocate */ 6385 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6386 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 6387 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6388 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6389 #else 6390 /* no TEX. read-allocate */ 6391 pte_l2_s_cache_mode = L2_C | L2_B; 6392 #endif 6393 /* 6394 * write-back, write-allocate for page tables. 6395 */ 6396 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6397 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 6398 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6399 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6400 #else 6401 pte_l2_s_cache_mode_pt = L2_C | L2_B; 6402 #endif 6403 6404 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 6405 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 6406 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 6407 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 6408 6409 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6410 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 6411 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 6412 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 6413 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 6414 6415 #else 6416 /* with AP[0..3] */ 6417 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6418 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6419 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6420 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6421 #endif 6422 6423 #ifdef ARM11MPCORE_COMPAT_MMU 6424 /* with AP[0..3] */ 6425 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6426 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6427 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6428 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6429 6430 pte_l1_s_proto = L1_S_PROTO_armv6; 6431 pte_l1_c_proto = L1_C_PROTO_armv6; 6432 pte_l2_s_proto = L2_S_PROTO_armv6c; 6433 #else 6434 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 6435 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 6436 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 6437 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 6438 6439 pte_l1_s_proto = L1_S_PROTO_armv6; 6440 pte_l1_c_proto = L1_C_PROTO_armv6; 6441 pte_l2_s_proto = L2_S_PROTO_armv6n; 6442 #endif 6443 6444 pmap_copy_page_func = pmap_copy_page_generic; 6445 pmap_zero_page_func = pmap_zero_page_generic; 6446 pmap_needs_pte_sync = 1; 6447 } 6448 #endif /* CPU_ARM11MPCORE */ 6449 6450 6451 #if ARM_MMU_V7 == 1 6452 void 6453 pmap_pte_init_armv7(void) 6454 { 6455 /* 6456 * The ARMv7-A MMU is mostly compatible with generic. If the 6457 * AP field is zero, that now means "no access" rather than 6458 * read-only. The prototypes are a little different because of 6459 * the XN bit. 6460 */ 6461 pmap_pte_init_generic(); 6462 6463 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6464 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6465 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6466 6467 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6468 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6469 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6470 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6471 6472 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6473 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6474 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6475 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6476 6477 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6478 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6479 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6480 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6481 6482 pte_l1_s_proto = L1_S_PROTO_armv7; 6483 pte_l1_c_proto = L1_C_PROTO_armv7; 6484 pte_l2_s_proto = L2_S_PROTO_armv7; 6485 } 6486 #endif /* ARM_MMU_V7 */ 6487 6488 /* 6489 * return the PA of the current L1 table, for use when handling a crash dump 6490 */ 6491 uint32_t pmap_kernel_L1_addr(void) 6492 { 6493 return pmap_kernel()->pm_l1->l1_physaddr; 6494 } 6495 6496 #if defined(DDB) 6497 /* 6498 * A couple of ddb-callable functions for dumping pmaps 6499 */ 6500 void pmap_dump_all(void); 6501 void pmap_dump(pmap_t); 6502 6503 void 6504 pmap_dump_all(void) 6505 { 6506 pmap_t pm; 6507 6508 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6509 if (pm == pmap_kernel()) 6510 continue; 6511 pmap_dump(pm); 6512 printf("\n"); 6513 } 6514 } 6515 6516 static pt_entry_t ncptes[64]; 6517 static void pmap_dump_ncpg(pmap_t); 6518 6519 void 6520 pmap_dump(pmap_t pm) 6521 { 6522 struct l2_dtable *l2; 6523 struct l2_bucket *l2b; 6524 pt_entry_t *ptep, pte; 6525 vaddr_t l2_va, l2b_va, va; 6526 int i, j, k, occ, rows = 0; 6527 6528 if (pm == pmap_kernel()) 6529 printf("pmap_kernel (%p): ", pm); 6530 else 6531 printf("user pmap (%p): ", pm); 6532 6533 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6534 6535 l2_va = 0; 6536 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6537 l2 = pm->pm_l2[i]; 6538 6539 if (l2 == NULL || l2->l2_occupancy == 0) 6540 continue; 6541 6542 l2b_va = l2_va; 6543 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6544 l2b = &l2->l2_bucket[j]; 6545 6546 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6547 continue; 6548 6549 ptep = l2b->l2b_kva; 6550 6551 for (k = 0; k < 256 && ptep[k] == 0; k++) 6552 ; 6553 6554 k &= ~63; 6555 occ = l2b->l2b_occupancy; 6556 va = l2b_va + (k * 4096); 6557 for (; k < 256; k++, va += 0x1000) { 6558 char ch = ' '; 6559 if ((k % 64) == 0) { 6560 if ((rows % 8) == 0) { 6561 printf( 6562 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6563 } 6564 printf("%08lx: ", va); 6565 } 6566 6567 ncptes[k & 63] = 0; 6568 pte = ptep[k]; 6569 if (pte == 0) { 6570 ch = '.'; 6571 } else { 6572 occ--; 6573 switch (pte & 0x0c) { 6574 case 0x00: 6575 ch = 'D'; /* No cache No buff */ 6576 break; 6577 case 0x04: 6578 ch = 'B'; /* No cache buff */ 6579 break; 6580 case 0x08: 6581 if (pte & 0x40) 6582 ch = 'm'; 6583 else 6584 ch = 'C'; /* Cache No buff */ 6585 break; 6586 case 0x0c: 6587 ch = 'F'; /* Cache Buff */ 6588 break; 6589 } 6590 6591 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6592 ch += 0x20; 6593 6594 if ((pte & 0xc) == 0) 6595 ncptes[k & 63] = pte; 6596 } 6597 6598 if ((k % 64) == 63) { 6599 rows++; 6600 printf("%c\n", ch); 6601 pmap_dump_ncpg(pm); 6602 if (occ == 0) 6603 break; 6604 } else 6605 printf("%c", ch); 6606 } 6607 } 6608 } 6609 } 6610 6611 static void 6612 pmap_dump_ncpg(pmap_t pm) 6613 { 6614 struct vm_page *pg; 6615 struct vm_page_md *md; 6616 struct pv_entry *pv; 6617 int i; 6618 6619 for (i = 0; i < 63; i++) { 6620 if (ncptes[i] == 0) 6621 continue; 6622 6623 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6624 if (pg == NULL) 6625 continue; 6626 md = VM_PAGE_TO_MD(pg); 6627 6628 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6629 VM_PAGE_TO_PHYS(pg), 6630 md->krw_mappings, md->kro_mappings, 6631 md->urw_mappings, md->uro_mappings); 6632 6633 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6634 printf(" %c va 0x%08lx, flags 0x%x\n", 6635 (pm == pv->pv_pmap) ? '*' : ' ', 6636 pv->pv_va, pv->pv_flags); 6637 } 6638 } 6639 } 6640 #endif 6641 6642 #ifdef PMAP_STEAL_MEMORY 6643 void 6644 pmap_boot_pageadd(pv_addr_t *newpv) 6645 { 6646 pv_addr_t *pv, *npv; 6647 6648 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6649 if (newpv->pv_pa < pv->pv_va) { 6650 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6651 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6652 newpv->pv_size += pv->pv_size; 6653 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6654 } 6655 pv = NULL; 6656 } else { 6657 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6658 pv = npv) { 6659 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6660 KASSERT(pv->pv_pa < newpv->pv_pa); 6661 if (newpv->pv_pa > npv->pv_pa) 6662 continue; 6663 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6664 pv->pv_size += newpv->pv_size; 6665 return; 6666 } 6667 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6668 break; 6669 newpv->pv_size += npv->pv_size; 6670 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6671 SLIST_REMOVE_AFTER(newpv, pv_list); 6672 return; 6673 } 6674 } 6675 } 6676 6677 if (pv) { 6678 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6679 } else { 6680 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6681 } 6682 } 6683 6684 void 6685 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6686 pv_addr_t *rpv) 6687 { 6688 pv_addr_t *pv, **pvp; 6689 struct vm_physseg *ps; 6690 size_t i; 6691 6692 KASSERT(amount & PGOFSET); 6693 KASSERT((mask & PGOFSET) == 0); 6694 KASSERT((match & PGOFSET) == 0); 6695 KASSERT(amount != 0); 6696 6697 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6698 (pv = *pvp) != NULL; 6699 pvp = &SLIST_NEXT(pv, pv_list)) { 6700 pv_addr_t *newpv; 6701 psize_t off; 6702 /* 6703 * If this entry is too small to satify the request... 6704 */ 6705 KASSERT(pv->pv_size > 0); 6706 if (pv->pv_size < amount) 6707 continue; 6708 6709 for (off = 0; off <= mask; off += PAGE_SIZE) { 6710 if (((pv->pv_pa + off) & mask) == match 6711 && off + amount <= pv->pv_size) 6712 break; 6713 } 6714 if (off > mask) 6715 continue; 6716 6717 rpv->pv_va = pv->pv_va + off; 6718 rpv->pv_pa = pv->pv_pa + off; 6719 rpv->pv_size = amount; 6720 pv->pv_size -= amount; 6721 if (pv->pv_size == 0) { 6722 KASSERT(off == 0); 6723 KASSERT((vaddr_t) pv == rpv->pv_va); 6724 *pvp = SLIST_NEXT(pv, pv_list); 6725 } else if (off == 0) { 6726 KASSERT((vaddr_t) pv == rpv->pv_va); 6727 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6728 *newpv = *pv; 6729 newpv->pv_pa += amount; 6730 newpv->pv_va += amount; 6731 *pvp = newpv; 6732 } else if (off < pv->pv_size) { 6733 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6734 *newpv = *pv; 6735 newpv->pv_size -= off; 6736 newpv->pv_pa += off + amount; 6737 newpv->pv_va += off + amount; 6738 6739 SLIST_NEXT(pv, pv_list) = newpv; 6740 pv->pv_size = off; 6741 } else { 6742 KASSERT((vaddr_t) pv != rpv->pv_va); 6743 } 6744 memset((void *)rpv->pv_va, 0, amount); 6745 return; 6746 } 6747 6748 if (vm_nphysseg == 0) 6749 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6750 6751 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6752 (pv = *pvp) != NULL; 6753 pvp = &SLIST_NEXT(pv, pv_list)) { 6754 if (SLIST_NEXT(pv, pv_list) == NULL) 6755 break; 6756 } 6757 KASSERT(mask == 0); 6758 for (i = 0; i < vm_nphysseg; i++) { 6759 ps = VM_PHYSMEM_PTR(i); 6760 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6761 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6762 rpv->pv_va = pv->pv_va; 6763 rpv->pv_pa = pv->pv_pa; 6764 rpv->pv_size = amount; 6765 *pvp = NULL; 6766 pmap_map_chunk(kernel_l1pt.pv_va, 6767 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6768 ptoa(ps->avail_start), 6769 amount - pv->pv_size, 6770 VM_PROT_READ|VM_PROT_WRITE, 6771 PTE_CACHE); 6772 ps->avail_start += atop(amount - pv->pv_size); 6773 /* 6774 * If we consumed the entire physseg, remove it. 6775 */ 6776 if (ps->avail_start == ps->avail_end) { 6777 for (--vm_nphysseg; i < vm_nphysseg; i++) 6778 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6779 } 6780 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6781 return; 6782 } 6783 } 6784 6785 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6786 } 6787 6788 vaddr_t 6789 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6790 { 6791 pv_addr_t pv; 6792 6793 pmap_boot_pagealloc(size, 0, 0, &pv); 6794 6795 return pv.pv_va; 6796 } 6797 #endif /* PMAP_STEAL_MEMORY */ 6798 6799 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6800 { 6801 sysctl_createv(clog, 0, NULL, NULL, 6802 CTLFLAG_PERMANENT, 6803 CTLTYPE_NODE, "machdep", NULL, 6804 NULL, 0, NULL, 0, 6805 CTL_MACHDEP, CTL_EOL); 6806 6807 sysctl_createv(clog, 0, NULL, NULL, 6808 CTLFLAG_PERMANENT, 6809 CTLTYPE_INT, "kmpages", 6810 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6811 NULL, 0, &pmap_kmpages, 0, 6812 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6813 } 6814
Indexes created Thu Sep 25 16:09:42 GMT 2025