pmap.c revision 1.224.2.4
1 /* $NetBSD: pmap.c,v 1.224.2.4 2013/01/23 00:05:40 yamt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/pool.h> 201 #include <sys/kmem.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <sys/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/cpuconf.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.224.2.4 2013/01/23 00:05:40 yamt Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 #define PDB_EXEC 0x80000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 static struct pmap kernel_pmap_store; 259 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 260 #ifdef PMAP_NEED_ALLOC_POOLPAGE 261 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 262 #endif 263 264 /* 265 * Which pmap is currently 'live' in the cache 266 * 267 * XXXSCW: Fix for SMP ... 268 */ 269 static pmap_t pmap_recent_user; 270 271 /* 272 * Pointer to last active lwp, or NULL if it exited. 273 */ 274 struct lwp *pmap_previous_active_lwp; 275 276 /* 277 * Pool and cache that pmap structures are allocated from. 278 * We use a cache to avoid clearing the pm_l2[] array (1KB) 279 * in pmap_create(). 280 */ 281 static struct pool_cache pmap_cache; 282 static LIST_HEAD(, pmap) pmap_pmaps; 283 284 /* 285 * Pool of PV structures 286 */ 287 static struct pool pmap_pv_pool; 288 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 289 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 290 static struct pool_allocator pmap_bootstrap_pv_allocator = { 291 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 292 }; 293 294 /* 295 * Pool and cache of l2_dtable structures. 296 * We use a cache to avoid clearing the structures when they're 297 * allocated. (196 bytes) 298 */ 299 static struct pool_cache pmap_l2dtable_cache; 300 static vaddr_t pmap_kernel_l2dtable_kva; 301 302 /* 303 * Pool and cache of L2 page descriptors. 304 * We use a cache to avoid clearing the descriptor table 305 * when they're allocated. (1KB) 306 */ 307 static struct pool_cache pmap_l2ptp_cache; 308 static vaddr_t pmap_kernel_l2ptp_kva; 309 static paddr_t pmap_kernel_l2ptp_phys; 310 311 #ifdef PMAPCOUNTERS 312 #define PMAP_EVCNT_INITIALIZER(name) \ 313 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 314 315 #ifdef PMAP_CACHE_VIPT 316 static struct evcnt pmap_ev_vac_clean_one = 317 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_one = 319 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_lots = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 322 static struct evcnt pmap_ev_vac_flush_lots2 = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 328 329 static struct evcnt pmap_ev_vac_color_new = 330 PMAP_EVCNT_INITIALIZER("new page color"); 331 static struct evcnt pmap_ev_vac_color_reuse = 332 PMAP_EVCNT_INITIALIZER("ok first page color"); 333 static struct evcnt pmap_ev_vac_color_ok = 334 PMAP_EVCNT_INITIALIZER("ok page color"); 335 static struct evcnt pmap_ev_vac_color_blind = 336 PMAP_EVCNT_INITIALIZER("blind page color"); 337 static struct evcnt pmap_ev_vac_color_change = 338 PMAP_EVCNT_INITIALIZER("change page color"); 339 static struct evcnt pmap_ev_vac_color_erase = 340 PMAP_EVCNT_INITIALIZER("erase page color"); 341 static struct evcnt pmap_ev_vac_color_none = 342 PMAP_EVCNT_INITIALIZER("no page color"); 343 static struct evcnt pmap_ev_vac_color_restore = 344 PMAP_EVCNT_INITIALIZER("restore page color"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 354 #endif 355 356 static struct evcnt pmap_ev_mappings = 357 PMAP_EVCNT_INITIALIZER("pages mapped"); 358 static struct evcnt pmap_ev_unmappings = 359 PMAP_EVCNT_INITIALIZER("pages unmapped"); 360 static struct evcnt pmap_ev_remappings = 361 PMAP_EVCNT_INITIALIZER("pages remapped"); 362 363 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 364 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 366 367 static struct evcnt pmap_ev_kernel_mappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 369 static struct evcnt pmap_ev_kernel_unmappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 371 static struct evcnt pmap_ev_kernel_remappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 373 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 377 378 static struct evcnt pmap_ev_kenter_mappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 380 static struct evcnt pmap_ev_kenter_unmappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 382 static struct evcnt pmap_ev_kenter_remappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 384 static struct evcnt pmap_ev_pt_mappings = 385 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 391 392 #ifdef PMAP_CACHE_VIPT 393 static struct evcnt pmap_ev_exec_mappings = 394 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 395 static struct evcnt pmap_ev_exec_cached = 396 PMAP_EVCNT_INITIALIZER("exec pages cached"); 397 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 399 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 400 401 static struct evcnt pmap_ev_exec_synced = 402 PMAP_EVCNT_INITIALIZER("exec pages synced"); 403 static struct evcnt pmap_ev_exec_synced_map = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 405 static struct evcnt pmap_ev_exec_synced_unmap = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 407 static struct evcnt pmap_ev_exec_synced_remap = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 409 static struct evcnt pmap_ev_exec_synced_clearbit = 410 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 411 static struct evcnt pmap_ev_exec_synced_kremove = 412 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 413 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 420 421 static struct evcnt pmap_ev_exec_discarded_unmap = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 423 static struct evcnt pmap_ev_exec_discarded_zero = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 425 static struct evcnt pmap_ev_exec_discarded_copy = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 427 static struct evcnt pmap_ev_exec_discarded_page_protect = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 429 static struct evcnt pmap_ev_exec_discarded_clearbit = 430 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 431 static struct evcnt pmap_ev_exec_discarded_kremove = 432 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 433 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 440 #endif /* PMAP_CACHE_VIPT */ 441 442 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 443 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 444 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 445 446 EVCNT_ATTACH_STATIC(pmap_ev_updates); 447 EVCNT_ATTACH_STATIC(pmap_ev_collects); 448 EVCNT_ATTACH_STATIC(pmap_ev_activations); 449 450 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 451 #else 452 #define PMAPCOUNT(x) ((void)0) 453 #endif 454 455 /* 456 * pmap copy/zero page, and mem(5) hook point 457 */ 458 static pt_entry_t *csrc_pte, *cdst_pte; 459 static vaddr_t csrcp, cdstp; 460 vaddr_t memhook; /* used by mem.c */ 461 kmutex_t memlock; /* used by mem.c */ 462 void *zeropage; /* used by mem.c */ 463 extern void *msgbufaddr; 464 int pmap_kmpages; 465 /* 466 * Flag to indicate if pmap_init() has done its thing 467 */ 468 bool pmap_initialized; 469 470 /* 471 * Misc. locking data structures 472 */ 473 474 #define pmap_acquire_pmap_lock(pm) \ 475 do { \ 476 if ((pm) != pmap_kernel()) \ 477 mutex_enter((pm)->pm_lock); \ 478 } while (/*CONSTCOND*/0) 479 480 #define pmap_release_pmap_lock(pm) \ 481 do { \ 482 if ((pm) != pmap_kernel()) \ 483 mutex_exit((pm)->pm_lock); \ 484 } while (/*CONSTCOND*/0) 485 486 487 /* 488 * Metadata for L1 translation tables. 489 */ 490 struct l1_ttable { 491 /* Entry on the L1 Table list */ 492 SLIST_ENTRY(l1_ttable) l1_link; 493 494 /* Entry on the L1 Least Recently Used list */ 495 TAILQ_ENTRY(l1_ttable) l1_lru; 496 497 /* Track how many domains are allocated from this L1 */ 498 volatile u_int l1_domain_use_count; 499 500 /* 501 * A free-list of domain numbers for this L1. 502 * We avoid using ffs() and a bitmap to track domains since ffs() 503 * is slow on ARM. 504 */ 505 uint8_t l1_domain_first; 506 uint8_t l1_domain_free[PMAP_DOMAINS]; 507 508 /* Physical address of this L1 page table */ 509 paddr_t l1_physaddr; 510 511 /* KVA of this L1 page table */ 512 pd_entry_t *l1_kva; 513 }; 514 515 /* 516 * Convert a virtual address into its L1 table index. That is, the 517 * index used to locate the L2 descriptor table pointer in an L1 table. 518 * This is basically used to index l1->l1_kva[]. 519 * 520 * Each L2 descriptor table represents 1MB of VA space. 521 */ 522 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 523 524 /* 525 * L1 Page Tables are tracked using a Least Recently Used list. 526 * - New L1s are allocated from the HEAD. 527 * - Freed L1s are added to the TAIl. 528 * - Recently accessed L1s (where an 'access' is some change to one of 529 * the userland pmaps which owns this L1) are moved to the TAIL. 530 */ 531 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 532 static kmutex_t l1_lru_lock __cacheline_aligned; 533 534 /* 535 * A list of all L1 tables 536 */ 537 static SLIST_HEAD(, l1_ttable) l1_list; 538 539 /* 540 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 541 * 542 * This is normally 16MB worth L2 page descriptors for any given pmap. 543 * Reference counts are maintained for L2 descriptors so they can be 544 * freed when empty. 545 */ 546 struct l2_dtable { 547 /* The number of L2 page descriptors allocated to this l2_dtable */ 548 u_int l2_occupancy; 549 550 /* List of L2 page descriptors */ 551 struct l2_bucket { 552 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 553 paddr_t l2b_phys; /* Physical address of same */ 554 u_short l2b_l1idx; /* This L2 table's L1 index */ 555 u_short l2b_occupancy; /* How many active descriptors */ 556 } l2_bucket[L2_BUCKET_SIZE]; 557 }; 558 559 /* 560 * Given an L1 table index, calculate the corresponding l2_dtable index 561 * and bucket index within the l2_dtable. 562 */ 563 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 564 (L2_SIZE - 1)) 565 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 566 567 /* 568 * Given a virtual address, this macro returns the 569 * virtual address required to drop into the next L2 bucket. 570 */ 571 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 572 573 /* 574 * L2 allocation. 575 */ 576 #define pmap_alloc_l2_dtable() \ 577 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 578 #define pmap_free_l2_dtable(l2) \ 579 pool_cache_put(&pmap_l2dtable_cache, (l2)) 580 #define pmap_alloc_l2_ptp(pap) \ 581 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 582 PR_NOWAIT, (pap))) 583 584 /* 585 * We try to map the page tables write-through, if possible. However, not 586 * all CPUs have a write-through cache mode, so on those we have to sync 587 * the cache when we frob page tables. 588 * 589 * We try to evaluate this at compile time, if possible. However, it's 590 * not always possible to do that, hence this run-time var. 591 */ 592 int pmap_needs_pte_sync; 593 594 /* 595 * Real definition of pv_entry. 596 */ 597 struct pv_entry { 598 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 599 pmap_t pv_pmap; /* pmap where mapping lies */ 600 vaddr_t pv_va; /* virtual address for mapping */ 601 u_int pv_flags; /* flags */ 602 }; 603 604 /* 605 * Macro to determine if a mapping might be resident in the 606 * instruction cache and/or TLB 607 */ 608 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 609 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 610 611 /* 612 * Macro to determine if a mapping might be resident in the 613 * data cache and/or TLB 614 */ 615 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 616 617 /* 618 * Local prototypes 619 */ 620 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 621 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 622 pt_entry_t **); 623 static bool pmap_is_current(pmap_t); 624 static bool pmap_is_cached(pmap_t); 625 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 626 pmap_t, vaddr_t, u_int); 627 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 628 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 629 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 630 u_int, u_int); 631 632 static void pmap_pinit(pmap_t); 633 static int pmap_pmap_ctor(void *, void *, int); 634 635 static void pmap_alloc_l1(pmap_t); 636 static void pmap_free_l1(pmap_t); 637 static void pmap_use_l1(pmap_t); 638 639 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 640 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 641 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 642 static int pmap_l2ptp_ctor(void *, void *, int); 643 static int pmap_l2dtable_ctor(void *, void *, int); 644 645 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 646 #ifdef PMAP_CACHE_VIVT 647 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 648 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 649 #endif 650 651 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 652 #ifdef PMAP_CACHE_VIVT 653 static int pmap_clean_page(struct pv_entry *, bool); 654 #endif 655 #ifdef PMAP_CACHE_VIPT 656 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 657 enum pmap_flush_op { 658 PMAP_FLUSH_PRIMARY, 659 PMAP_FLUSH_SECONDARY, 660 PMAP_CLEAN_PRIMARY 661 }; 662 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 663 #endif 664 static void pmap_page_remove(struct vm_page_md *, paddr_t); 665 666 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 667 static vaddr_t kernel_pt_lookup(paddr_t); 668 669 670 /* 671 * Misc variables 672 */ 673 vaddr_t virtual_avail; 674 vaddr_t virtual_end; 675 vaddr_t pmap_curmaxkvaddr; 676 677 paddr_t avail_start; 678 paddr_t avail_end; 679 680 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 681 pv_addr_t kernelpages; 682 pv_addr_t kernel_l1pt; 683 pv_addr_t systempage; 684 685 /* Function to set the debug level of the pmap code */ 686 687 #ifdef PMAP_DEBUG 688 void 689 pmap_debug(int level) 690 { 691 pmap_debug_level = level; 692 printf("pmap_debug: level=%d\n", pmap_debug_level); 693 } 694 #endif /* PMAP_DEBUG */ 695 696 /* 697 * A bunch of routines to conditionally flush the caches/TLB depending 698 * on whether the specified pmap actually needs to be flushed at any 699 * given time. 700 */ 701 static inline void 702 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 703 { 704 705 if (pm->pm_cstate.cs_tlb_id) 706 cpu_tlb_flushID_SE(va); 707 } 708 709 static inline void 710 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 711 { 712 713 if (pm->pm_cstate.cs_tlb_d) 714 cpu_tlb_flushD_SE(va); 715 } 716 717 static inline void 718 pmap_tlb_flushID(pmap_t pm) 719 { 720 721 if (pm->pm_cstate.cs_tlb_id) { 722 cpu_tlb_flushID(); 723 pm->pm_cstate.cs_tlb = 0; 724 } 725 } 726 727 static inline void 728 pmap_tlb_flushD(pmap_t pm) 729 { 730 731 if (pm->pm_cstate.cs_tlb_d) { 732 cpu_tlb_flushD(); 733 pm->pm_cstate.cs_tlb_d = 0; 734 } 735 } 736 737 #ifdef PMAP_CACHE_VIVT 738 static inline void 739 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 740 { 741 if (pm->pm_cstate.cs_cache_id) { 742 cpu_idcache_wbinv_range(va, len); 743 } 744 } 745 746 static inline void 747 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 748 bool do_inv, bool rd_only) 749 { 750 751 if (pm->pm_cstate.cs_cache_d) { 752 if (do_inv) { 753 if (rd_only) 754 cpu_dcache_inv_range(va, len); 755 else 756 cpu_dcache_wbinv_range(va, len); 757 } else 758 if (!rd_only) 759 cpu_dcache_wb_range(va, len); 760 } 761 } 762 763 static inline void 764 pmap_idcache_wbinv_all(pmap_t pm) 765 { 766 if (pm->pm_cstate.cs_cache_id) { 767 cpu_idcache_wbinv_all(); 768 pm->pm_cstate.cs_cache = 0; 769 } 770 } 771 772 static inline void 773 pmap_dcache_wbinv_all(pmap_t pm) 774 { 775 if (pm->pm_cstate.cs_cache_d) { 776 cpu_dcache_wbinv_all(); 777 pm->pm_cstate.cs_cache_d = 0; 778 } 779 } 780 #endif /* PMAP_CACHE_VIVT */ 781 782 static inline bool 783 pmap_is_current(pmap_t pm) 784 { 785 786 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 787 return true; 788 789 return false; 790 } 791 792 static inline bool 793 pmap_is_cached(pmap_t pm) 794 { 795 796 if (pm == pmap_kernel() || pmap_recent_user == NULL || 797 pmap_recent_user == pm) 798 return (true); 799 800 return false; 801 } 802 803 /* 804 * PTE_SYNC_CURRENT: 805 * 806 * Make sure the pte is written out to RAM. 807 * We need to do this for one of two cases: 808 * - We're dealing with the kernel pmap 809 * - There is no pmap active in the cache/tlb. 810 * - The specified pmap is 'active' in the cache/tlb. 811 */ 812 #ifdef PMAP_INCLUDE_PTE_SYNC 813 #define PTE_SYNC_CURRENT(pm, ptep) \ 814 do { \ 815 if (PMAP_NEEDS_PTE_SYNC && \ 816 pmap_is_cached(pm)) \ 817 PTE_SYNC(ptep); \ 818 } while (/*CONSTCOND*/0) 819 #else 820 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 821 #endif 822 823 /* 824 * main pv_entry manipulation functions: 825 * pmap_enter_pv: enter a mapping onto a vm_page list 826 * pmap_remove_pv: remove a mappiing from a vm_page list 827 * 828 * NOTE: pmap_enter_pv expects to lock the pvh itself 829 * pmap_remove_pv expects te caller to lock the pvh before calling 830 */ 831 832 /* 833 * pmap_enter_pv: enter a mapping onto a vm_page lst 834 * 835 * => caller should hold the proper lock on pmap_main_lock 836 * => caller should have pmap locked 837 * => we will gain the lock on the vm_page and allocate the new pv_entry 838 * => caller should adjust ptp's wire_count before calling 839 * => caller should not adjust pmap's wire_count 840 */ 841 static void 842 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 843 vaddr_t va, u_int flags) 844 { 845 struct pv_entry **pvp; 846 847 NPDEBUG(PDB_PVDUMP, 848 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 849 850 pv->pv_pmap = pm; 851 pv->pv_va = va; 852 pv->pv_flags = flags; 853 854 pvp = &SLIST_FIRST(&md->pvh_list); 855 #ifdef PMAP_CACHE_VIPT 856 /* 857 * Insert unmanaged entries, writeable first, at the head of 858 * the pv list. 859 */ 860 if (__predict_true((flags & PVF_KENTRY) == 0)) { 861 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 862 pvp = &SLIST_NEXT(*pvp, pv_link); 863 } else if ((flags & PVF_WRITE) == 0) { 864 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 865 pvp = &SLIST_NEXT(*pvp, pv_link); 866 } 867 #endif 868 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 869 *pvp = pv; /* ... locked list */ 870 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 871 #ifdef PMAP_CACHE_VIPT 872 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 873 md->pvh_attrs |= PVF_KMOD; 874 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 875 md->pvh_attrs |= PVF_DIRTY; 876 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 877 #endif 878 if (pm == pmap_kernel()) { 879 PMAPCOUNT(kernel_mappings); 880 if (flags & PVF_WRITE) 881 md->krw_mappings++; 882 else 883 md->kro_mappings++; 884 } else { 885 if (flags & PVF_WRITE) 886 md->urw_mappings++; 887 else 888 md->uro_mappings++; 889 } 890 891 #ifdef PMAP_CACHE_VIPT 892 /* 893 * If this is an exec mapping and its the first exec mapping 894 * for this page, make sure to sync the I-cache. 895 */ 896 if (PV_IS_EXEC_P(flags)) { 897 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 898 pmap_syncicache_page(md, pa); 899 PMAPCOUNT(exec_synced_map); 900 } 901 PMAPCOUNT(exec_mappings); 902 } 903 #endif 904 905 PMAPCOUNT(mappings); 906 907 if (pv->pv_flags & PVF_WIRED) 908 ++pm->pm_stats.wired_count; 909 } 910 911 /* 912 * 913 * pmap_find_pv: Find a pv entry 914 * 915 * => caller should hold lock on vm_page 916 */ 917 static inline struct pv_entry * 918 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 919 { 920 struct pv_entry *pv; 921 922 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 923 if (pm == pv->pv_pmap && va == pv->pv_va) 924 break; 925 } 926 927 return (pv); 928 } 929 930 /* 931 * pmap_remove_pv: try to remove a mapping from a pv_list 932 * 933 * => caller should hold proper lock on pmap_main_lock 934 * => pmap should be locked 935 * => caller should hold lock on vm_page [so that attrs can be adjusted] 936 * => caller should adjust ptp's wire_count and free PTP if needed 937 * => caller should NOT adjust pmap's wire_count 938 * => we return the removed pv 939 */ 940 static struct pv_entry * 941 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 942 { 943 struct pv_entry *pv, **prevptr; 944 945 NPDEBUG(PDB_PVDUMP, 946 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 947 948 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 949 pv = *prevptr; 950 951 while (pv) { 952 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 953 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 954 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 955 if (pv->pv_flags & PVF_WIRED) { 956 --pm->pm_stats.wired_count; 957 } 958 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 959 if (pm == pmap_kernel()) { 960 PMAPCOUNT(kernel_unmappings); 961 if (pv->pv_flags & PVF_WRITE) 962 md->krw_mappings--; 963 else 964 md->kro_mappings--; 965 } else { 966 if (pv->pv_flags & PVF_WRITE) 967 md->urw_mappings--; 968 else 969 md->uro_mappings--; 970 } 971 972 PMAPCOUNT(unmappings); 973 #ifdef PMAP_CACHE_VIPT 974 if (!(pv->pv_flags & PVF_WRITE)) 975 break; 976 /* 977 * If this page has had an exec mapping, then if 978 * this was the last mapping, discard the contents, 979 * otherwise sync the i-cache for this page. 980 */ 981 if (PV_IS_EXEC_P(md->pvh_attrs)) { 982 if (SLIST_EMPTY(&md->pvh_list)) { 983 md->pvh_attrs &= ~PVF_EXEC; 984 PMAPCOUNT(exec_discarded_unmap); 985 } else { 986 pmap_syncicache_page(md, pa); 987 PMAPCOUNT(exec_synced_unmap); 988 } 989 } 990 #endif /* PMAP_CACHE_VIPT */ 991 break; 992 } 993 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 994 pv = *prevptr; /* advance */ 995 } 996 997 #ifdef PMAP_CACHE_VIPT 998 /* 999 * If we no longer have a WRITEABLE KENTRY at the head of list, 1000 * clear the KMOD attribute from the page. 1001 */ 1002 if (SLIST_FIRST(&md->pvh_list) == NULL 1003 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1004 md->pvh_attrs &= ~PVF_KMOD; 1005 1006 /* 1007 * If this was a writeable page and there are no more writeable 1008 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1009 * the contents to memory. 1010 */ 1011 if (md->krw_mappings + md->urw_mappings == 0) 1012 md->pvh_attrs &= ~PVF_WRITE; 1013 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1014 #endif /* PMAP_CACHE_VIPT */ 1015 1016 return(pv); /* return removed pv */ 1017 } 1018 1019 /* 1020 * 1021 * pmap_modify_pv: Update pv flags 1022 * 1023 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1024 * => caller should NOT adjust pmap's wire_count 1025 * => caller must call pmap_vac_me_harder() if writable status of a page 1026 * may have changed. 1027 * => we return the old flags 1028 * 1029 * Modify a physical-virtual mapping in the pv table 1030 */ 1031 static u_int 1032 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1033 u_int clr_mask, u_int set_mask) 1034 { 1035 struct pv_entry *npv; 1036 u_int flags, oflags; 1037 1038 KASSERT((clr_mask & PVF_KENTRY) == 0); 1039 KASSERT((set_mask & PVF_KENTRY) == 0); 1040 1041 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1042 return (0); 1043 1044 NPDEBUG(PDB_PVDUMP, 1045 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1046 1047 /* 1048 * There is at least one VA mapping this page. 1049 */ 1050 1051 if (clr_mask & (PVF_REF | PVF_MOD)) { 1052 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1053 #ifdef PMAP_CACHE_VIPT 1054 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1055 md->pvh_attrs |= PVF_DIRTY; 1056 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1057 #endif 1058 } 1059 1060 oflags = npv->pv_flags; 1061 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1062 1063 if ((flags ^ oflags) & PVF_WIRED) { 1064 if (flags & PVF_WIRED) 1065 ++pm->pm_stats.wired_count; 1066 else 1067 --pm->pm_stats.wired_count; 1068 } 1069 1070 if ((flags ^ oflags) & PVF_WRITE) { 1071 if (pm == pmap_kernel()) { 1072 if (flags & PVF_WRITE) { 1073 md->krw_mappings++; 1074 md->kro_mappings--; 1075 } else { 1076 md->kro_mappings++; 1077 md->krw_mappings--; 1078 } 1079 } else { 1080 if (flags & PVF_WRITE) { 1081 md->urw_mappings++; 1082 md->uro_mappings--; 1083 } else { 1084 md->uro_mappings++; 1085 md->urw_mappings--; 1086 } 1087 } 1088 } 1089 #ifdef PMAP_CACHE_VIPT 1090 if (md->urw_mappings + md->krw_mappings == 0) { 1091 md->pvh_attrs &= ~PVF_WRITE; 1092 } else { 1093 md->pvh_attrs |= PVF_WRITE; 1094 } 1095 /* 1096 * We have two cases here: the first is from enter_pv (new exec 1097 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1098 * Since in latter, pmap_enter_pv won't do anything, we just have 1099 * to do what pmap_remove_pv would do. 1100 */ 1101 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1102 || (PV_IS_EXEC_P(md->pvh_attrs) 1103 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1104 pmap_syncicache_page(md, pa); 1105 PMAPCOUNT(exec_synced_remap); 1106 } 1107 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1108 #endif 1109 1110 PMAPCOUNT(remappings); 1111 1112 return (oflags); 1113 } 1114 1115 /* 1116 * Allocate an L1 translation table for the specified pmap. 1117 * This is called at pmap creation time. 1118 */ 1119 static void 1120 pmap_alloc_l1(pmap_t pm) 1121 { 1122 struct l1_ttable *l1; 1123 uint8_t domain; 1124 1125 /* 1126 * Remove the L1 at the head of the LRU list 1127 */ 1128 mutex_spin_enter(&l1_lru_lock); 1129 l1 = TAILQ_FIRST(&l1_lru_list); 1130 KDASSERT(l1 != NULL); 1131 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1132 1133 /* 1134 * Pick the first available domain number, and update 1135 * the link to the next number. 1136 */ 1137 domain = l1->l1_domain_first; 1138 l1->l1_domain_first = l1->l1_domain_free[domain]; 1139 1140 /* 1141 * If there are still free domain numbers in this L1, 1142 * put it back on the TAIL of the LRU list. 1143 */ 1144 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1145 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1146 1147 mutex_spin_exit(&l1_lru_lock); 1148 1149 /* 1150 * Fix up the relevant bits in the pmap structure 1151 */ 1152 pm->pm_l1 = l1; 1153 pm->pm_domain = domain + 1; 1154 } 1155 1156 /* 1157 * Free an L1 translation table. 1158 * This is called at pmap destruction time. 1159 */ 1160 static void 1161 pmap_free_l1(pmap_t pm) 1162 { 1163 struct l1_ttable *l1 = pm->pm_l1; 1164 1165 mutex_spin_enter(&l1_lru_lock); 1166 1167 /* 1168 * If this L1 is currently on the LRU list, remove it. 1169 */ 1170 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1171 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1172 1173 /* 1174 * Free up the domain number which was allocated to the pmap 1175 */ 1176 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first; 1177 l1->l1_domain_first = pm->pm_domain - 1; 1178 l1->l1_domain_use_count--; 1179 1180 /* 1181 * The L1 now must have at least 1 free domain, so add 1182 * it back to the LRU list. If the use count is zero, 1183 * put it at the head of the list, otherwise it goes 1184 * to the tail. 1185 */ 1186 if (l1->l1_domain_use_count == 0) 1187 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1188 else 1189 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1190 1191 mutex_spin_exit(&l1_lru_lock); 1192 } 1193 1194 static inline void 1195 pmap_use_l1(pmap_t pm) 1196 { 1197 struct l1_ttable *l1; 1198 1199 /* 1200 * Do nothing if we're in interrupt context. 1201 * Access to an L1 by the kernel pmap must not affect 1202 * the LRU list. 1203 */ 1204 if (cpu_intr_p() || pm == pmap_kernel()) 1205 return; 1206 1207 l1 = pm->pm_l1; 1208 1209 /* 1210 * If the L1 is not currently on the LRU list, just return 1211 */ 1212 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1213 return; 1214 1215 mutex_spin_enter(&l1_lru_lock); 1216 1217 /* 1218 * Check the use count again, now that we've acquired the lock 1219 */ 1220 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1221 mutex_spin_exit(&l1_lru_lock); 1222 return; 1223 } 1224 1225 /* 1226 * Move the L1 to the back of the LRU list 1227 */ 1228 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1229 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1230 1231 mutex_spin_exit(&l1_lru_lock); 1232 } 1233 1234 /* 1235 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1236 * 1237 * Free an L2 descriptor table. 1238 */ 1239 static inline void 1240 #ifndef PMAP_INCLUDE_PTE_SYNC 1241 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1242 #else 1243 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1244 #endif 1245 { 1246 #ifdef PMAP_INCLUDE_PTE_SYNC 1247 #ifdef PMAP_CACHE_VIVT 1248 /* 1249 * Note: With a write-back cache, we may need to sync this 1250 * L2 table before re-using it. 1251 * This is because it may have belonged to a non-current 1252 * pmap, in which case the cache syncs would have been 1253 * skipped for the pages that were being unmapped. If the 1254 * L2 table were then to be immediately re-allocated to 1255 * the *current* pmap, it may well contain stale mappings 1256 * which have not yet been cleared by a cache write-back 1257 * and so would still be visible to the mmu. 1258 */ 1259 if (need_sync) 1260 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1261 #endif /* PMAP_CACHE_VIVT */ 1262 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1263 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1264 } 1265 1266 /* 1267 * Returns a pointer to the L2 bucket associated with the specified pmap 1268 * and VA, or NULL if no L2 bucket exists for the address. 1269 */ 1270 static inline struct l2_bucket * 1271 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1272 { 1273 struct l2_dtable *l2; 1274 struct l2_bucket *l2b; 1275 u_short l1idx; 1276 1277 l1idx = L1_IDX(va); 1278 1279 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1280 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1281 return (NULL); 1282 1283 return (l2b); 1284 } 1285 1286 /* 1287 * Returns a pointer to the L2 bucket associated with the specified pmap 1288 * and VA. 1289 * 1290 * If no L2 bucket exists, perform the necessary allocations to put an L2 1291 * bucket/page table in place. 1292 * 1293 * Note that if a new L2 bucket/page was allocated, the caller *must* 1294 * increment the bucket occupancy counter appropriately *before* 1295 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1296 * the bucket/page in the meantime. 1297 */ 1298 static struct l2_bucket * 1299 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1300 { 1301 struct l2_dtable *l2; 1302 struct l2_bucket *l2b; 1303 u_short l1idx; 1304 1305 l1idx = L1_IDX(va); 1306 1307 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1308 /* 1309 * No mapping at this address, as there is 1310 * no entry in the L1 table. 1311 * Need to allocate a new l2_dtable. 1312 */ 1313 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1314 return (NULL); 1315 1316 /* 1317 * Link it into the parent pmap 1318 */ 1319 pm->pm_l2[L2_IDX(l1idx)] = l2; 1320 } 1321 1322 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1323 1324 /* 1325 * Fetch pointer to the L2 page table associated with the address. 1326 */ 1327 if (l2b->l2b_kva == NULL) { 1328 pt_entry_t *ptep; 1329 1330 /* 1331 * No L2 page table has been allocated. Chances are, this 1332 * is because we just allocated the l2_dtable, above. 1333 */ 1334 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1335 /* 1336 * Oops, no more L2 page tables available at this 1337 * time. We may need to deallocate the l2_dtable 1338 * if we allocated a new one above. 1339 */ 1340 if (l2->l2_occupancy == 0) { 1341 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1342 pmap_free_l2_dtable(l2); 1343 } 1344 return (NULL); 1345 } 1346 1347 l2->l2_occupancy++; 1348 l2b->l2b_kva = ptep; 1349 l2b->l2b_l1idx = l1idx; 1350 } 1351 1352 return (l2b); 1353 } 1354 1355 /* 1356 * One or more mappings in the specified L2 descriptor table have just been 1357 * invalidated. 1358 * 1359 * Garbage collect the metadata and descriptor table itself if necessary. 1360 * 1361 * The pmap lock must be acquired when this is called (not necessary 1362 * for the kernel pmap). 1363 */ 1364 static void 1365 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1366 { 1367 struct l2_dtable *l2; 1368 pd_entry_t *pl1pd, l1pd; 1369 pt_entry_t *ptep; 1370 u_short l1idx; 1371 1372 KDASSERT(count <= l2b->l2b_occupancy); 1373 1374 /* 1375 * Update the bucket's reference count according to how many 1376 * PTEs the caller has just invalidated. 1377 */ 1378 l2b->l2b_occupancy -= count; 1379 1380 /* 1381 * Note: 1382 * 1383 * Level 2 page tables allocated to the kernel pmap are never freed 1384 * as that would require checking all Level 1 page tables and 1385 * removing any references to the Level 2 page table. See also the 1386 * comment elsewhere about never freeing bootstrap L2 descriptors. 1387 * 1388 * We make do with just invalidating the mapping in the L2 table. 1389 * 1390 * This isn't really a big deal in practice and, in fact, leads 1391 * to a performance win over time as we don't need to continually 1392 * alloc/free. 1393 */ 1394 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1395 return; 1396 1397 /* 1398 * There are no more valid mappings in this level 2 page table. 1399 * Go ahead and NULL-out the pointer in the bucket, then 1400 * free the page table. 1401 */ 1402 l1idx = l2b->l2b_l1idx; 1403 ptep = l2b->l2b_kva; 1404 l2b->l2b_kva = NULL; 1405 1406 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1407 1408 /* 1409 * If the L1 slot matches the pmap's domain 1410 * number, then invalidate it. 1411 */ 1412 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1413 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1414 *pl1pd = 0; 1415 PTE_SYNC(pl1pd); 1416 } 1417 1418 /* 1419 * Release the L2 descriptor table back to the pool cache. 1420 */ 1421 #ifndef PMAP_INCLUDE_PTE_SYNC 1422 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1423 #else 1424 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1425 #endif 1426 1427 /* 1428 * Update the reference count in the associated l2_dtable 1429 */ 1430 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1431 if (--l2->l2_occupancy > 0) 1432 return; 1433 1434 /* 1435 * There are no more valid mappings in any of the Level 1 1436 * slots managed by this l2_dtable. Go ahead and NULL-out 1437 * the pointer in the parent pmap and free the l2_dtable. 1438 */ 1439 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1440 pmap_free_l2_dtable(l2); 1441 } 1442 1443 /* 1444 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1445 * structures. 1446 */ 1447 static int 1448 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1449 { 1450 #ifndef PMAP_INCLUDE_PTE_SYNC 1451 struct l2_bucket *l2b; 1452 pt_entry_t *ptep, pte; 1453 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1454 1455 /* 1456 * The mappings for these page tables were initially made using 1457 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1458 * mode will not be right for page table mappings. To avoid 1459 * polluting the pmap_kenter_pa() code with a special case for 1460 * page tables, we simply fix up the cache-mode here if it's not 1461 * correct. 1462 */ 1463 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1464 KDASSERT(l2b != NULL); 1465 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1466 pte = *ptep; 1467 1468 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1469 /* 1470 * Page tables must have the cache-mode set to Write-Thru. 1471 */ 1472 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1473 PTE_SYNC(ptep); 1474 cpu_tlb_flushD_SE(va); 1475 cpu_cpwait(); 1476 } 1477 #endif 1478 1479 memset(v, 0, L2_TABLE_SIZE_REAL); 1480 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1481 return (0); 1482 } 1483 1484 static int 1485 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1486 { 1487 1488 memset(v, 0, sizeof(struct l2_dtable)); 1489 return (0); 1490 } 1491 1492 static int 1493 pmap_pmap_ctor(void *arg, void *v, int flags) 1494 { 1495 1496 memset(v, 0, sizeof(struct pmap)); 1497 return (0); 1498 } 1499 1500 static void 1501 pmap_pinit(pmap_t pm) 1502 { 1503 struct l2_bucket *l2b; 1504 1505 if (vector_page < KERNEL_BASE) { 1506 /* 1507 * Map the vector page. 1508 */ 1509 pmap_enter(pm, vector_page, systempage.pv_pa, 1510 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1511 pmap_update(pm); 1512 1513 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1514 l2b = pmap_get_l2_bucket(pm, vector_page); 1515 KDASSERT(l2b != NULL); 1516 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1517 L1_C_DOM(pm->pm_domain); 1518 } else 1519 pm->pm_pl1vec = NULL; 1520 } 1521 1522 #ifdef PMAP_CACHE_VIVT 1523 /* 1524 * Since we have a virtually indexed cache, we may need to inhibit caching if 1525 * there is more than one mapping and at least one of them is writable. 1526 * Since we purge the cache on every context switch, we only need to check for 1527 * other mappings within the same pmap, or kernel_pmap. 1528 * This function is also called when a page is unmapped, to possibly reenable 1529 * caching on any remaining mappings. 1530 * 1531 * The code implements the following logic, where: 1532 * 1533 * KW = # of kernel read/write pages 1534 * KR = # of kernel read only pages 1535 * UW = # of user read/write pages 1536 * UR = # of user read only pages 1537 * 1538 * KC = kernel mapping is cacheable 1539 * UC = user mapping is cacheable 1540 * 1541 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1542 * +--------------------------------------------- 1543 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1544 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1545 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1546 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1547 */ 1548 1549 static const int pmap_vac_flags[4][4] = { 1550 {-1, 0, 0, PVF_KNC}, 1551 {0, 0, PVF_NC, PVF_NC}, 1552 {0, PVF_NC, PVF_NC, PVF_NC}, 1553 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1554 }; 1555 1556 static inline int 1557 pmap_get_vac_flags(const struct vm_page_md *md) 1558 { 1559 int kidx, uidx; 1560 1561 kidx = 0; 1562 if (md->kro_mappings || md->krw_mappings > 1) 1563 kidx |= 1; 1564 if (md->krw_mappings) 1565 kidx |= 2; 1566 1567 uidx = 0; 1568 if (md->uro_mappings || md->urw_mappings > 1) 1569 uidx |= 1; 1570 if (md->urw_mappings) 1571 uidx |= 2; 1572 1573 return (pmap_vac_flags[uidx][kidx]); 1574 } 1575 1576 static inline void 1577 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1578 { 1579 int nattr; 1580 1581 nattr = pmap_get_vac_flags(md); 1582 1583 if (nattr < 0) { 1584 md->pvh_attrs &= ~PVF_NC; 1585 return; 1586 } 1587 1588 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1589 return; 1590 1591 if (pm == pmap_kernel()) 1592 pmap_vac_me_kpmap(md, pa, pm, va); 1593 else 1594 pmap_vac_me_user(md, pa, pm, va); 1595 1596 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1597 } 1598 1599 static void 1600 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1601 { 1602 u_int u_cacheable, u_entries; 1603 struct pv_entry *pv; 1604 pmap_t last_pmap = pm; 1605 1606 /* 1607 * Pass one, see if there are both kernel and user pmaps for 1608 * this page. Calculate whether there are user-writable or 1609 * kernel-writable pages. 1610 */ 1611 u_cacheable = 0; 1612 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1613 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1614 u_cacheable++; 1615 } 1616 1617 u_entries = md->urw_mappings + md->uro_mappings; 1618 1619 /* 1620 * We know we have just been updating a kernel entry, so if 1621 * all user pages are already cacheable, then there is nothing 1622 * further to do. 1623 */ 1624 if (md->k_mappings == 0 && u_cacheable == u_entries) 1625 return; 1626 1627 if (u_entries) { 1628 /* 1629 * Scan over the list again, for each entry, if it 1630 * might not be set correctly, call pmap_vac_me_user 1631 * to recalculate the settings. 1632 */ 1633 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1634 /* 1635 * We know kernel mappings will get set 1636 * correctly in other calls. We also know 1637 * that if the pmap is the same as last_pmap 1638 * then we've just handled this entry. 1639 */ 1640 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1641 continue; 1642 1643 /* 1644 * If there are kernel entries and this page 1645 * is writable but non-cacheable, then we can 1646 * skip this entry also. 1647 */ 1648 if (md->k_mappings && 1649 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1650 (PVF_NC | PVF_WRITE)) 1651 continue; 1652 1653 /* 1654 * Similarly if there are no kernel-writable 1655 * entries and the page is already 1656 * read-only/cacheable. 1657 */ 1658 if (md->krw_mappings == 0 && 1659 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1660 continue; 1661 1662 /* 1663 * For some of the remaining cases, we know 1664 * that we must recalculate, but for others we 1665 * can't tell if they are correct or not, so 1666 * we recalculate anyway. 1667 */ 1668 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1669 } 1670 1671 if (md->k_mappings == 0) 1672 return; 1673 } 1674 1675 pmap_vac_me_user(md, pa, pm, va); 1676 } 1677 1678 static void 1679 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1680 { 1681 pmap_t kpmap = pmap_kernel(); 1682 struct pv_entry *pv, *npv = NULL; 1683 struct l2_bucket *l2b; 1684 pt_entry_t *ptep, pte; 1685 u_int entries = 0; 1686 u_int writable = 0; 1687 u_int cacheable_entries = 0; 1688 u_int kern_cacheable = 0; 1689 u_int other_writable = 0; 1690 1691 /* 1692 * Count mappings and writable mappings in this pmap. 1693 * Include kernel mappings as part of our own. 1694 * Keep a pointer to the first one. 1695 */ 1696 npv = NULL; 1697 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1698 /* Count mappings in the same pmap */ 1699 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1700 if (entries++ == 0) 1701 npv = pv; 1702 1703 /* Cacheable mappings */ 1704 if ((pv->pv_flags & PVF_NC) == 0) { 1705 cacheable_entries++; 1706 if (kpmap == pv->pv_pmap) 1707 kern_cacheable++; 1708 } 1709 1710 /* Writable mappings */ 1711 if (pv->pv_flags & PVF_WRITE) 1712 ++writable; 1713 } else 1714 if (pv->pv_flags & PVF_WRITE) 1715 other_writable = 1; 1716 } 1717 1718 /* 1719 * Enable or disable caching as necessary. 1720 * Note: the first entry might be part of the kernel pmap, 1721 * so we can't assume this is indicative of the state of the 1722 * other (maybe non-kpmap) entries. 1723 */ 1724 if ((entries > 1 && writable) || 1725 (entries > 0 && pm == kpmap && other_writable)) { 1726 if (cacheable_entries == 0) 1727 return; 1728 1729 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1730 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1731 (pv->pv_flags & PVF_NC)) 1732 continue; 1733 1734 pv->pv_flags |= PVF_NC; 1735 1736 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1737 KDASSERT(l2b != NULL); 1738 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1739 pte = *ptep & ~L2_S_CACHE_MASK; 1740 1741 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1742 l2pte_valid(pte)) { 1743 if (PV_BEEN_EXECD(pv->pv_flags)) { 1744 #ifdef PMAP_CACHE_VIVT 1745 pmap_idcache_wbinv_range(pv->pv_pmap, 1746 pv->pv_va, PAGE_SIZE); 1747 #endif 1748 pmap_tlb_flushID_SE(pv->pv_pmap, 1749 pv->pv_va); 1750 } else 1751 if (PV_BEEN_REFD(pv->pv_flags)) { 1752 #ifdef PMAP_CACHE_VIVT 1753 pmap_dcache_wb_range(pv->pv_pmap, 1754 pv->pv_va, PAGE_SIZE, true, 1755 (pv->pv_flags & PVF_WRITE) == 0); 1756 #endif 1757 pmap_tlb_flushD_SE(pv->pv_pmap, 1758 pv->pv_va); 1759 } 1760 } 1761 1762 *ptep = pte; 1763 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1764 } 1765 cpu_cpwait(); 1766 } else 1767 if (entries > cacheable_entries) { 1768 /* 1769 * Turn cacheing back on for some pages. If it is a kernel 1770 * page, only do so if there are no other writable pages. 1771 */ 1772 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1773 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1774 (kpmap != pv->pv_pmap || other_writable))) 1775 continue; 1776 1777 pv->pv_flags &= ~PVF_NC; 1778 1779 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1780 KDASSERT(l2b != NULL); 1781 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1782 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1783 1784 if (l2pte_valid(pte)) { 1785 if (PV_BEEN_EXECD(pv->pv_flags)) { 1786 pmap_tlb_flushID_SE(pv->pv_pmap, 1787 pv->pv_va); 1788 } else 1789 if (PV_BEEN_REFD(pv->pv_flags)) { 1790 pmap_tlb_flushD_SE(pv->pv_pmap, 1791 pv->pv_va); 1792 } 1793 } 1794 1795 *ptep = pte; 1796 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1797 } 1798 } 1799 } 1800 #endif 1801 1802 #ifdef PMAP_CACHE_VIPT 1803 static void 1804 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1805 { 1806 struct pv_entry *pv; 1807 vaddr_t tst_mask; 1808 bool bad_alias; 1809 struct l2_bucket *l2b; 1810 pt_entry_t *ptep, pte, opte; 1811 const u_int 1812 rw_mappings = md->urw_mappings + md->krw_mappings, 1813 ro_mappings = md->uro_mappings + md->kro_mappings; 1814 1815 /* do we need to do anything? */ 1816 if (arm_cache_prefer_mask == 0) 1817 return; 1818 1819 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1820 md, pm, va)); 1821 1822 KASSERT(!va || pm); 1823 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1824 1825 /* Already a conflict? */ 1826 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1827 /* just an add, things are already non-cached */ 1828 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1829 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1830 bad_alias = false; 1831 if (va) { 1832 PMAPCOUNT(vac_color_none); 1833 bad_alias = true; 1834 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1835 goto fixup; 1836 } 1837 pv = SLIST_FIRST(&md->pvh_list); 1838 /* the list can't be empty because it would be cachable */ 1839 if (md->pvh_attrs & PVF_KMPAGE) { 1840 tst_mask = md->pvh_attrs; 1841 } else { 1842 KASSERT(pv); 1843 tst_mask = pv->pv_va; 1844 pv = SLIST_NEXT(pv, pv_link); 1845 } 1846 /* 1847 * Only check for a bad alias if we have writable mappings. 1848 */ 1849 tst_mask &= arm_cache_prefer_mask; 1850 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1851 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1852 /* if there's a bad alias, stop checking. */ 1853 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1854 bad_alias = true; 1855 } 1856 md->pvh_attrs |= PVF_WRITE; 1857 if (!bad_alias) 1858 md->pvh_attrs |= PVF_DIRTY; 1859 } else { 1860 /* 1861 * We have only read-only mappings. Let's see if there 1862 * are multiple colors in use or if we mapped a KMPAGE. 1863 * If the latter, we have a bad alias. If the former, 1864 * we need to remember that. 1865 */ 1866 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1867 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1868 if (md->pvh_attrs & PVF_KMPAGE) 1869 bad_alias = true; 1870 break; 1871 } 1872 } 1873 md->pvh_attrs &= ~PVF_WRITE; 1874 /* 1875 * No KMPAGE and we exited early, so we must have 1876 * multiple color mappings. 1877 */ 1878 if (!bad_alias && pv != NULL) 1879 md->pvh_attrs |= PVF_MULTCLR; 1880 } 1881 1882 /* If no conflicting colors, set everything back to cached */ 1883 if (!bad_alias) { 1884 #ifdef DEBUG 1885 if ((md->pvh_attrs & PVF_WRITE) 1886 || ro_mappings < 2) { 1887 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1888 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1889 } 1890 #endif 1891 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1892 md->pvh_attrs |= tst_mask | PVF_COLORED; 1893 /* 1894 * Restore DIRTY bit if page is modified 1895 */ 1896 if (md->pvh_attrs & PVF_DMOD) 1897 md->pvh_attrs |= PVF_DIRTY; 1898 PMAPCOUNT(vac_color_restore); 1899 } else { 1900 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1901 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1902 } 1903 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1904 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1905 } else if (!va) { 1906 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1907 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1908 || (md->pvh_attrs & PVF_DIRTY)); 1909 if (rw_mappings == 0) { 1910 md->pvh_attrs &= ~PVF_WRITE; 1911 if (ro_mappings == 1 1912 && (md->pvh_attrs & PVF_MULTCLR)) { 1913 /* 1914 * If this is the last readonly mapping 1915 * but it doesn't match the current color 1916 * for the page, change the current color 1917 * to match this last readonly mapping. 1918 */ 1919 pv = SLIST_FIRST(&md->pvh_list); 1920 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1921 & arm_cache_prefer_mask; 1922 if (tst_mask) { 1923 md->pvh_attrs ^= tst_mask; 1924 PMAPCOUNT(vac_color_change); 1925 } 1926 } 1927 } 1928 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1929 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1930 return; 1931 } else if (!pmap_is_page_colored_p(md)) { 1932 /* not colored so we just use its color */ 1933 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1934 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1935 PMAPCOUNT(vac_color_new); 1936 md->pvh_attrs &= PAGE_SIZE - 1; 1937 md->pvh_attrs |= PVF_COLORED 1938 | (va & arm_cache_prefer_mask) 1939 | (rw_mappings > 0 ? PVF_WRITE : 0); 1940 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1941 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1942 return; 1943 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1944 bad_alias = false; 1945 if (rw_mappings > 0) { 1946 /* 1947 * We now have writeable mappings and if we have 1948 * readonly mappings in more than once color, we have 1949 * an aliasing problem. Regardless mark the page as 1950 * writeable. 1951 */ 1952 if (md->pvh_attrs & PVF_MULTCLR) { 1953 if (ro_mappings < 2) { 1954 /* 1955 * If we only have less than two 1956 * read-only mappings, just flush the 1957 * non-primary colors from the cache. 1958 */ 1959 pmap_flush_page(md, pa, 1960 PMAP_FLUSH_SECONDARY); 1961 } else { 1962 bad_alias = true; 1963 } 1964 } 1965 md->pvh_attrs |= PVF_WRITE; 1966 } 1967 /* If no conflicting colors, set everything back to cached */ 1968 if (!bad_alias) { 1969 #ifdef DEBUG 1970 if (rw_mappings > 0 1971 || (md->pvh_attrs & PMAP_KMPAGE)) { 1972 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1973 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1974 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1975 } 1976 #endif 1977 if (SLIST_EMPTY(&md->pvh_list)) 1978 PMAPCOUNT(vac_color_reuse); 1979 else 1980 PMAPCOUNT(vac_color_ok); 1981 1982 /* matching color, just return */ 1983 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1984 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1985 return; 1986 } 1987 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1988 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1989 1990 /* color conflict. evict from cache. */ 1991 1992 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 1993 md->pvh_attrs &= ~PVF_COLORED; 1994 md->pvh_attrs |= PVF_NC; 1995 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1996 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1997 PMAPCOUNT(vac_color_erase); 1998 } else if (rw_mappings == 0 1999 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2000 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2001 2002 /* 2003 * If the page has dirty cache lines, clean it. 2004 */ 2005 if (md->pvh_attrs & PVF_DIRTY) 2006 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2007 2008 /* 2009 * If this is the first remapping (we know that there are no 2010 * writeable mappings), then this is a simple color change. 2011 * Otherwise this is a seconary r/o mapping, which means 2012 * we don't have to do anything. 2013 */ 2014 if (ro_mappings == 1) { 2015 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2016 md->pvh_attrs &= PAGE_SIZE - 1; 2017 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2018 PMAPCOUNT(vac_color_change); 2019 } else { 2020 PMAPCOUNT(vac_color_blind); 2021 } 2022 md->pvh_attrs |= PVF_MULTCLR; 2023 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2024 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2025 return; 2026 } else { 2027 if (rw_mappings > 0) 2028 md->pvh_attrs |= PVF_WRITE; 2029 2030 /* color conflict. evict from cache. */ 2031 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2032 2033 /* the list can't be empty because this was a enter/modify */ 2034 pv = SLIST_FIRST(&md->pvh_list); 2035 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2036 KASSERT(pv); 2037 /* 2038 * If there's only one mapped page, change color to the 2039 * page's new color and return. Restore the DIRTY bit 2040 * that was erased by pmap_flush_page. 2041 */ 2042 if (SLIST_NEXT(pv, pv_link) == NULL) { 2043 md->pvh_attrs &= PAGE_SIZE - 1; 2044 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2045 if (md->pvh_attrs & PVF_DMOD) 2046 md->pvh_attrs |= PVF_DIRTY; 2047 PMAPCOUNT(vac_color_change); 2048 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2049 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2050 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2051 return; 2052 } 2053 } 2054 bad_alias = true; 2055 md->pvh_attrs &= ~PVF_COLORED; 2056 md->pvh_attrs |= PVF_NC; 2057 PMAPCOUNT(vac_color_erase); 2058 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2059 } 2060 2061 fixup: 2062 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2063 2064 /* 2065 * Turn cacheing on/off for all pages. 2066 */ 2067 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2068 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2069 KDASSERT(l2b != NULL); 2070 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2071 opte = *ptep; 2072 pte = opte & ~L2_S_CACHE_MASK; 2073 if (bad_alias) { 2074 pv->pv_flags |= PVF_NC; 2075 } else { 2076 pv->pv_flags &= ~PVF_NC; 2077 pte |= pte_l2_s_cache_mode; 2078 } 2079 2080 if (opte == pte) /* only update is there's a change */ 2081 continue; 2082 2083 if (l2pte_valid(pte)) { 2084 if (PV_BEEN_EXECD(pv->pv_flags)) { 2085 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2086 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2087 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2088 } 2089 } 2090 2091 *ptep = pte; 2092 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2093 } 2094 } 2095 #endif /* PMAP_CACHE_VIPT */ 2096 2097 2098 /* 2099 * Modify pte bits for all ptes corresponding to the given physical address. 2100 * We use `maskbits' rather than `clearbits' because we're always passing 2101 * constants and the latter would require an extra inversion at run-time. 2102 */ 2103 static void 2104 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2105 { 2106 struct l2_bucket *l2b; 2107 struct pv_entry *pv; 2108 pt_entry_t *ptep, npte, opte; 2109 pmap_t pm; 2110 vaddr_t va; 2111 u_int oflags; 2112 #ifdef PMAP_CACHE_VIPT 2113 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2114 bool need_syncicache = false; 2115 bool did_syncicache = false; 2116 bool need_vac_me_harder = false; 2117 #endif 2118 2119 NPDEBUG(PDB_BITS, 2120 printf("pmap_clearbit: md %p mask 0x%x\n", 2121 md, maskbits)); 2122 2123 #ifdef PMAP_CACHE_VIPT 2124 /* 2125 * If we might want to sync the I-cache and we've modified it, 2126 * then we know we definitely need to sync or discard it. 2127 */ 2128 if (want_syncicache) 2129 need_syncicache = md->pvh_attrs & PVF_MOD; 2130 #endif 2131 /* 2132 * Clear saved attributes (modify, reference) 2133 */ 2134 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2135 2136 if (SLIST_EMPTY(&md->pvh_list)) { 2137 #ifdef PMAP_CACHE_VIPT 2138 if (need_syncicache) { 2139 /* 2140 * No one has it mapped, so just discard it. The next 2141 * exec remapping will cause it to be synced. 2142 */ 2143 md->pvh_attrs &= ~PVF_EXEC; 2144 PMAPCOUNT(exec_discarded_clearbit); 2145 } 2146 #endif 2147 return; 2148 } 2149 2150 /* 2151 * Loop over all current mappings setting/clearing as appropos 2152 */ 2153 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2154 va = pv->pv_va; 2155 pm = pv->pv_pmap; 2156 oflags = pv->pv_flags; 2157 /* 2158 * Kernel entries are unmanaged and as such not to be changed. 2159 */ 2160 if (oflags & PVF_KENTRY) 2161 continue; 2162 pv->pv_flags &= ~maskbits; 2163 2164 pmap_acquire_pmap_lock(pm); 2165 2166 l2b = pmap_get_l2_bucket(pm, va); 2167 KDASSERT(l2b != NULL); 2168 2169 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2170 npte = opte = *ptep; 2171 2172 NPDEBUG(PDB_BITS, 2173 printf( 2174 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2175 pv, pv->pv_pmap, pv->pv_va, oflags)); 2176 2177 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2178 #ifdef PMAP_CACHE_VIVT 2179 if ((pv->pv_flags & PVF_NC)) { 2180 /* 2181 * Entry is not cacheable: 2182 * 2183 * Don't turn caching on again if this is a 2184 * modified emulation. This would be 2185 * inconsitent with the settings created by 2186 * pmap_vac_me_harder(). Otherwise, it's safe 2187 * to re-enable cacheing. 2188 * 2189 * There's no need to call pmap_vac_me_harder() 2190 * here: all pages are losing their write 2191 * permission. 2192 */ 2193 if (maskbits & PVF_WRITE) { 2194 npte |= pte_l2_s_cache_mode; 2195 pv->pv_flags &= ~PVF_NC; 2196 } 2197 } else 2198 if (l2pte_writable_p(opte)) { 2199 /* 2200 * Entry is writable/cacheable: check if pmap 2201 * is current if it is flush it, otherwise it 2202 * won't be in the cache 2203 */ 2204 if (PV_BEEN_EXECD(oflags)) 2205 pmap_idcache_wbinv_range(pm, pv->pv_va, 2206 PAGE_SIZE); 2207 else 2208 if (PV_BEEN_REFD(oflags)) 2209 pmap_dcache_wb_range(pm, pv->pv_va, 2210 PAGE_SIZE, 2211 (maskbits & PVF_REF) != 0, false); 2212 } 2213 #endif 2214 2215 /* make the pte read only */ 2216 npte = l2pte_set_readonly(npte); 2217 2218 if (maskbits & oflags & PVF_WRITE) { 2219 /* 2220 * Keep alias accounting up to date 2221 */ 2222 if (pv->pv_pmap == pmap_kernel()) { 2223 md->krw_mappings--; 2224 md->kro_mappings++; 2225 } else { 2226 md->urw_mappings--; 2227 md->uro_mappings++; 2228 } 2229 #ifdef PMAP_CACHE_VIPT 2230 if (md->urw_mappings + md->krw_mappings == 0) { 2231 md->pvh_attrs &= ~PVF_WRITE; 2232 } else { 2233 KASSERT(md->pvh_attrs & PVF_WRITE); 2234 } 2235 if (want_syncicache) 2236 need_syncicache = true; 2237 need_vac_me_harder = true; 2238 #endif 2239 } 2240 } 2241 2242 if (maskbits & PVF_REF) { 2243 if ((pv->pv_flags & PVF_NC) == 0 && 2244 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2245 l2pte_valid(npte)) { 2246 #ifdef PMAP_CACHE_VIVT 2247 /* 2248 * Check npte here; we may have already 2249 * done the wbinv above, and the validity 2250 * of the PTE is the same for opte and 2251 * npte. 2252 */ 2253 /* XXXJRT need idcache_inv_range */ 2254 if (PV_BEEN_EXECD(oflags)) 2255 pmap_idcache_wbinv_range(pm, 2256 pv->pv_va, PAGE_SIZE); 2257 else 2258 if (PV_BEEN_REFD(oflags)) 2259 pmap_dcache_wb_range(pm, 2260 pv->pv_va, PAGE_SIZE, 2261 true, true); 2262 #endif 2263 } 2264 2265 /* 2266 * Make the PTE invalid so that we will take a 2267 * page fault the next time the mapping is 2268 * referenced. 2269 */ 2270 npte &= ~L2_TYPE_MASK; 2271 npte |= L2_TYPE_INV; 2272 } 2273 2274 if (npte != opte) { 2275 *ptep = npte; 2276 PTE_SYNC(ptep); 2277 /* Flush the TLB entry if a current pmap. */ 2278 if (PV_BEEN_EXECD(oflags)) 2279 pmap_tlb_flushID_SE(pm, pv->pv_va); 2280 else 2281 if (PV_BEEN_REFD(oflags)) 2282 pmap_tlb_flushD_SE(pm, pv->pv_va); 2283 } 2284 2285 pmap_release_pmap_lock(pm); 2286 2287 NPDEBUG(PDB_BITS, 2288 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2289 pm, va, opte, npte)); 2290 } 2291 2292 #ifdef PMAP_CACHE_VIPT 2293 /* 2294 * If we need to sync the I-cache and we haven't done it yet, do it. 2295 */ 2296 if (need_syncicache && !did_syncicache) { 2297 pmap_syncicache_page(md, pa); 2298 PMAPCOUNT(exec_synced_clearbit); 2299 } 2300 /* 2301 * If we are changing this to read-only, we need to call vac_me_harder 2302 * so we can change all the read-only pages to cacheable. We pretend 2303 * this as a page deletion. 2304 */ 2305 if (need_vac_me_harder) { 2306 if (md->pvh_attrs & PVF_NC) 2307 pmap_vac_me_harder(md, pa, NULL, 0); 2308 } 2309 #endif 2310 } 2311 2312 /* 2313 * pmap_clean_page() 2314 * 2315 * This is a local function used to work out the best strategy to clean 2316 * a single page referenced by its entry in the PV table. It's used by 2317 * pmap_copy_page, pmap_zero page and maybe some others later on. 2318 * 2319 * Its policy is effectively: 2320 * o If there are no mappings, we don't bother doing anything with the cache. 2321 * o If there is one mapping, we clean just that page. 2322 * o If there are multiple mappings, we clean the entire cache. 2323 * 2324 * So that some functions can be further optimised, it returns 0 if it didn't 2325 * clean the entire cache, or 1 if it did. 2326 * 2327 * XXX One bug in this routine is that if the pv_entry has a single page 2328 * mapped at 0x00000000 a whole cache clean will be performed rather than 2329 * just the 1 page. Since this should not occur in everyday use and if it does 2330 * it will just result in not the most efficient clean for the page. 2331 */ 2332 #ifdef PMAP_CACHE_VIVT 2333 static int 2334 pmap_clean_page(struct pv_entry *pv, bool is_src) 2335 { 2336 pmap_t pm_to_clean = NULL; 2337 struct pv_entry *npv; 2338 u_int cache_needs_cleaning = 0; 2339 u_int flags = 0; 2340 vaddr_t page_to_clean = 0; 2341 2342 if (pv == NULL) { 2343 /* nothing mapped in so nothing to flush */ 2344 return (0); 2345 } 2346 2347 /* 2348 * Since we flush the cache each time we change to a different 2349 * user vmspace, we only need to flush the page if it is in the 2350 * current pmap. 2351 */ 2352 2353 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2354 if (pmap_is_current(npv->pv_pmap)) { 2355 flags |= npv->pv_flags; 2356 /* 2357 * The page is mapped non-cacheable in 2358 * this map. No need to flush the cache. 2359 */ 2360 if (npv->pv_flags & PVF_NC) { 2361 #ifdef DIAGNOSTIC 2362 if (cache_needs_cleaning) 2363 panic("pmap_clean_page: " 2364 "cache inconsistency"); 2365 #endif 2366 break; 2367 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2368 continue; 2369 if (cache_needs_cleaning) { 2370 page_to_clean = 0; 2371 break; 2372 } else { 2373 page_to_clean = npv->pv_va; 2374 pm_to_clean = npv->pv_pmap; 2375 } 2376 cache_needs_cleaning = 1; 2377 } 2378 } 2379 2380 if (page_to_clean) { 2381 if (PV_BEEN_EXECD(flags)) 2382 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2383 PAGE_SIZE); 2384 else 2385 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2386 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2387 } else if (cache_needs_cleaning) { 2388 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2389 2390 if (PV_BEEN_EXECD(flags)) 2391 pmap_idcache_wbinv_all(pm); 2392 else 2393 pmap_dcache_wbinv_all(pm); 2394 return (1); 2395 } 2396 return (0); 2397 } 2398 #endif 2399 2400 #ifdef PMAP_CACHE_VIPT 2401 /* 2402 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2403 * right cache alias to make sure we flush the right stuff. 2404 */ 2405 void 2406 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2407 { 2408 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2409 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2410 2411 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2412 md, md->pvh_attrs)); 2413 /* 2414 * No need to clean the page if it's non-cached. 2415 */ 2416 if (md->pvh_attrs & PVF_NC) 2417 return; 2418 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2419 2420 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2421 /* 2422 * Set up a PTE with the right coloring to flush existing cache lines. 2423 */ 2424 *ptep = L2_S_PROTO | 2425 pa 2426 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2427 | pte_l2_s_cache_mode; 2428 PTE_SYNC(ptep); 2429 2430 /* 2431 * Flush it. 2432 */ 2433 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2434 /* 2435 * Unmap the page. 2436 */ 2437 *ptep = 0; 2438 PTE_SYNC(ptep); 2439 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2440 2441 md->pvh_attrs |= PVF_EXEC; 2442 PMAPCOUNT(exec_synced); 2443 } 2444 2445 void 2446 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2447 { 2448 vsize_t va_offset, end_va; 2449 void (*cf)(vaddr_t, vsize_t); 2450 2451 if (arm_cache_prefer_mask == 0) 2452 return; 2453 2454 switch (flush) { 2455 case PMAP_FLUSH_PRIMARY: 2456 if (md->pvh_attrs & PVF_MULTCLR) { 2457 va_offset = 0; 2458 end_va = arm_cache_prefer_mask; 2459 md->pvh_attrs &= ~PVF_MULTCLR; 2460 PMAPCOUNT(vac_flush_lots); 2461 } else { 2462 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2463 end_va = va_offset; 2464 PMAPCOUNT(vac_flush_one); 2465 } 2466 /* 2467 * Mark that the page is no longer dirty. 2468 */ 2469 md->pvh_attrs &= ~PVF_DIRTY; 2470 cf = cpufuncs.cf_idcache_wbinv_range; 2471 break; 2472 case PMAP_FLUSH_SECONDARY: 2473 va_offset = 0; 2474 end_va = arm_cache_prefer_mask; 2475 cf = cpufuncs.cf_idcache_wbinv_range; 2476 md->pvh_attrs &= ~PVF_MULTCLR; 2477 PMAPCOUNT(vac_flush_lots); 2478 break; 2479 case PMAP_CLEAN_PRIMARY: 2480 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2481 end_va = va_offset; 2482 cf = cpufuncs.cf_dcache_wb_range; 2483 /* 2484 * Mark that the page is no longer dirty. 2485 */ 2486 if ((md->pvh_attrs & PVF_DMOD) == 0) 2487 md->pvh_attrs &= ~PVF_DIRTY; 2488 PMAPCOUNT(vac_clean_one); 2489 break; 2490 default: 2491 return; 2492 } 2493 2494 KASSERT(!(md->pvh_attrs & PVF_NC)); 2495 2496 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2497 md, md->pvh_attrs)); 2498 2499 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2500 const size_t pte_offset = va_offset >> PGSHIFT; 2501 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2502 const pt_entry_t oldpte = *ptep; 2503 2504 if (flush == PMAP_FLUSH_SECONDARY 2505 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2506 continue; 2507 2508 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2509 /* 2510 * Set up a PTE with the right coloring to flush 2511 * existing cache entries. 2512 */ 2513 *ptep = L2_S_PROTO 2514 | pa 2515 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2516 | pte_l2_s_cache_mode; 2517 PTE_SYNC(ptep); 2518 2519 /* 2520 * Flush it. 2521 */ 2522 (*cf)(cdstp + va_offset, PAGE_SIZE); 2523 2524 /* 2525 * Restore the page table entry since we might have interrupted 2526 * pmap_zero_page or pmap_copy_page which was already using 2527 * this pte. 2528 */ 2529 *ptep = oldpte; 2530 PTE_SYNC(ptep); 2531 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2532 } 2533 } 2534 #endif /* PMAP_CACHE_VIPT */ 2535 2536 /* 2537 * Routine: pmap_page_remove 2538 * Function: 2539 * Removes this physical page from 2540 * all physical maps in which it resides. 2541 * Reflects back modify bits to the pager. 2542 */ 2543 static void 2544 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2545 { 2546 struct l2_bucket *l2b; 2547 struct pv_entry *pv, *npv, **pvp; 2548 pmap_t pm; 2549 pt_entry_t *ptep; 2550 bool flush; 2551 u_int flags; 2552 2553 NPDEBUG(PDB_FOLLOW, 2554 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2555 pa)); 2556 2557 pv = SLIST_FIRST(&md->pvh_list); 2558 if (pv == NULL) { 2559 #ifdef PMAP_CACHE_VIPT 2560 /* 2561 * We *know* the page contents are about to be replaced. 2562 * Discard the exec contents 2563 */ 2564 if (PV_IS_EXEC_P(md->pvh_attrs)) 2565 PMAPCOUNT(exec_discarded_page_protect); 2566 md->pvh_attrs &= ~PVF_EXEC; 2567 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2568 #endif 2569 return; 2570 } 2571 #ifdef PMAP_CACHE_VIPT 2572 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2573 #endif 2574 2575 /* 2576 * Clear alias counts 2577 */ 2578 #ifdef PMAP_CACHE_VIVT 2579 md->k_mappings = 0; 2580 #endif 2581 md->urw_mappings = md->uro_mappings = 0; 2582 2583 flush = false; 2584 flags = 0; 2585 2586 #ifdef PMAP_CACHE_VIVT 2587 pmap_clean_page(pv, false); 2588 #endif 2589 2590 pvp = &SLIST_FIRST(&md->pvh_list); 2591 while (pv) { 2592 pm = pv->pv_pmap; 2593 npv = SLIST_NEXT(pv, pv_link); 2594 if (flush == false && pmap_is_current(pm)) 2595 flush = true; 2596 2597 if (pm == pmap_kernel()) { 2598 #ifdef PMAP_CACHE_VIPT 2599 /* 2600 * If this was unmanaged mapping, it must be preserved. 2601 * Move it back on the list and advance the end-of-list 2602 * pointer. 2603 */ 2604 if (pv->pv_flags & PVF_KENTRY) { 2605 *pvp = pv; 2606 pvp = &SLIST_NEXT(pv, pv_link); 2607 pv = npv; 2608 continue; 2609 } 2610 if (pv->pv_flags & PVF_WRITE) 2611 md->krw_mappings--; 2612 else 2613 md->kro_mappings--; 2614 #endif 2615 PMAPCOUNT(kernel_unmappings); 2616 } 2617 PMAPCOUNT(unmappings); 2618 2619 pmap_acquire_pmap_lock(pm); 2620 2621 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2622 KDASSERT(l2b != NULL); 2623 2624 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2625 2626 /* 2627 * Update statistics 2628 */ 2629 --pm->pm_stats.resident_count; 2630 2631 /* Wired bit */ 2632 if (pv->pv_flags & PVF_WIRED) 2633 --pm->pm_stats.wired_count; 2634 2635 flags |= pv->pv_flags; 2636 2637 /* 2638 * Invalidate the PTEs. 2639 */ 2640 *ptep = 0; 2641 PTE_SYNC_CURRENT(pm, ptep); 2642 pmap_free_l2_bucket(pm, l2b, 1); 2643 2644 pool_put(&pmap_pv_pool, pv); 2645 pv = npv; 2646 /* 2647 * if we reach the end of the list and there are still 2648 * mappings, they might be able to be cached now. 2649 */ 2650 if (pv == NULL) { 2651 *pvp = NULL; 2652 if (!SLIST_EMPTY(&md->pvh_list)) 2653 pmap_vac_me_harder(md, pa, pm, 0); 2654 } 2655 pmap_release_pmap_lock(pm); 2656 } 2657 #ifdef PMAP_CACHE_VIPT 2658 /* 2659 * Its EXEC cache is now gone. 2660 */ 2661 if (PV_IS_EXEC_P(md->pvh_attrs)) 2662 PMAPCOUNT(exec_discarded_page_protect); 2663 md->pvh_attrs &= ~PVF_EXEC; 2664 KASSERT(md->urw_mappings == 0); 2665 KASSERT(md->uro_mappings == 0); 2666 if (md->krw_mappings == 0) 2667 md->pvh_attrs &= ~PVF_WRITE; 2668 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2669 #endif 2670 2671 if (flush) { 2672 /* 2673 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2674 * would need a subsequent call to pmap_update() to ensure 2675 * curpm->pm_cstate.cs_all is reset. Our callers are not 2676 * required to do that (see pmap(9)), so we can't modify 2677 * the current pmap's state. 2678 */ 2679 if (PV_BEEN_EXECD(flags)) 2680 cpu_tlb_flushID(); 2681 else 2682 cpu_tlb_flushD(); 2683 } 2684 cpu_cpwait(); 2685 } 2686 2687 /* 2688 * pmap_t pmap_create(void) 2689 * 2690 * Create a new pmap structure from scratch. 2691 */ 2692 pmap_t 2693 pmap_create(void) 2694 { 2695 pmap_t pm; 2696 2697 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2698 2699 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2700 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2701 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2702 2703 pm->pm_stats.wired_count = 0; 2704 pm->pm_stats.resident_count = 1; 2705 pm->pm_cstate.cs_all = 0; 2706 pmap_alloc_l1(pm); 2707 2708 /* 2709 * Note: The pool cache ensures that the pm_l2[] array is already 2710 * initialised to zero. 2711 */ 2712 2713 pmap_pinit(pm); 2714 2715 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2716 2717 return (pm); 2718 } 2719 2720 u_int 2721 arm32_mmap_flags(paddr_t pa) 2722 { 2723 /* 2724 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 2725 * and we're using the upper bits in page numbers to pass flags around 2726 * so we might as well use the same bits 2727 */ 2728 return (u_int)pa & PMAP_MD_MASK; 2729 } 2730 /* 2731 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2732 * u_int flags) 2733 * 2734 * Insert the given physical page (p) at 2735 * the specified virtual address (v) in the 2736 * target physical map with the protection requested. 2737 * 2738 * NB: This is the only routine which MAY NOT lazy-evaluate 2739 * or lose information. That is, this routine must actually 2740 * insert this page into the given map NOW. 2741 */ 2742 int 2743 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2744 { 2745 struct l2_bucket *l2b; 2746 struct vm_page *pg, *opg; 2747 struct pv_entry *pv; 2748 pt_entry_t *ptep, npte, opte; 2749 u_int nflags; 2750 u_int oflags; 2751 2752 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2753 2754 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2755 KDASSERT(((va | pa) & PGOFSET) == 0); 2756 2757 /* 2758 * Get a pointer to the page. Later on in this function, we 2759 * test for a managed page by checking pg != NULL. 2760 */ 2761 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2762 2763 nflags = 0; 2764 if (prot & VM_PROT_WRITE) 2765 nflags |= PVF_WRITE; 2766 if (prot & VM_PROT_EXECUTE) 2767 nflags |= PVF_EXEC; 2768 if (flags & PMAP_WIRED) 2769 nflags |= PVF_WIRED; 2770 2771 pmap_acquire_pmap_lock(pm); 2772 2773 /* 2774 * Fetch the L2 bucket which maps this page, allocating one if 2775 * necessary for user pmaps. 2776 */ 2777 if (pm == pmap_kernel()) 2778 l2b = pmap_get_l2_bucket(pm, va); 2779 else 2780 l2b = pmap_alloc_l2_bucket(pm, va); 2781 if (l2b == NULL) { 2782 if (flags & PMAP_CANFAIL) { 2783 pmap_release_pmap_lock(pm); 2784 return (ENOMEM); 2785 } 2786 panic("pmap_enter: failed to allocate L2 bucket"); 2787 } 2788 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2789 opte = *ptep; 2790 npte = pa; 2791 oflags = 0; 2792 2793 if (opte) { 2794 /* 2795 * There is already a mapping at this address. 2796 * If the physical address is different, lookup the 2797 * vm_page. 2798 */ 2799 if (l2pte_pa(opte) != pa) 2800 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2801 else 2802 opg = pg; 2803 } else 2804 opg = NULL; 2805 2806 if (pg) { 2807 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2808 2809 /* 2810 * This is to be a managed mapping. 2811 */ 2812 if ((flags & VM_PROT_ALL) || 2813 (md->pvh_attrs & PVF_REF)) { 2814 /* 2815 * - The access type indicates that we don't need 2816 * to do referenced emulation. 2817 * OR 2818 * - The physical page has already been referenced 2819 * so no need to re-do referenced emulation here. 2820 */ 2821 npte |= l2pte_set_readonly(L2_S_PROTO); 2822 2823 nflags |= PVF_REF; 2824 2825 if ((prot & VM_PROT_WRITE) != 0 && 2826 ((flags & VM_PROT_WRITE) != 0 || 2827 (md->pvh_attrs & PVF_MOD) != 0)) { 2828 /* 2829 * This is a writable mapping, and the 2830 * page's mod state indicates it has 2831 * already been modified. Make it 2832 * writable from the outset. 2833 */ 2834 npte = l2pte_set_writable(npte); 2835 nflags |= PVF_MOD; 2836 } 2837 } else { 2838 /* 2839 * Need to do page referenced emulation. 2840 */ 2841 npte |= L2_TYPE_INV; 2842 } 2843 2844 npte |= pte_l2_s_cache_mode; 2845 2846 if (pg == opg) { 2847 /* 2848 * We're changing the attrs of an existing mapping. 2849 */ 2850 #ifdef MULTIPROCESSOR 2851 KASSERT(uvm_page_locked_p(pg)); 2852 #endif 2853 oflags = pmap_modify_pv(md, pa, pm, va, 2854 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2855 PVF_MOD | PVF_REF, nflags); 2856 2857 #ifdef PMAP_CACHE_VIVT 2858 /* 2859 * We may need to flush the cache if we're 2860 * doing rw-ro... 2861 */ 2862 if (pm->pm_cstate.cs_cache_d && 2863 (oflags & PVF_NC) == 0 && 2864 l2pte_writable_p(opte) && 2865 (prot & VM_PROT_WRITE) == 0) 2866 cpu_dcache_wb_range(va, PAGE_SIZE); 2867 #endif 2868 } else { 2869 /* 2870 * New mapping, or changing the backing page 2871 * of an existing mapping. 2872 */ 2873 if (opg) { 2874 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2875 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2876 2877 /* 2878 * Replacing an existing mapping with a new one. 2879 * It is part of our managed memory so we 2880 * must remove it from the PV list 2881 */ 2882 #ifdef MULTIPROCESSOR 2883 KASSERT(uvm_page_locked_p(opg)); 2884 #endif 2885 pv = pmap_remove_pv(omd, opa, pm, va); 2886 pmap_vac_me_harder(omd, opa, pm, 0); 2887 oflags = pv->pv_flags; 2888 2889 #ifdef PMAP_CACHE_VIVT 2890 /* 2891 * If the old mapping was valid (ref/mod 2892 * emulation creates 'invalid' mappings 2893 * initially) then make sure to frob 2894 * the cache. 2895 */ 2896 if ((oflags & PVF_NC) == 0 && 2897 l2pte_valid(opte)) { 2898 if (PV_BEEN_EXECD(oflags)) { 2899 pmap_idcache_wbinv_range(pm, va, 2900 PAGE_SIZE); 2901 } else 2902 if (PV_BEEN_REFD(oflags)) { 2903 pmap_dcache_wb_range(pm, va, 2904 PAGE_SIZE, true, 2905 (oflags & PVF_WRITE) == 0); 2906 } 2907 } 2908 #endif 2909 } else 2910 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2911 if ((flags & PMAP_CANFAIL) == 0) 2912 panic("pmap_enter: no pv entries"); 2913 2914 if (pm != pmap_kernel()) 2915 pmap_free_l2_bucket(pm, l2b, 0); 2916 pmap_release_pmap_lock(pm); 2917 NPDEBUG(PDB_ENTER, 2918 printf("pmap_enter: ENOMEM\n")); 2919 return (ENOMEM); 2920 } 2921 2922 #ifdef MULTIPROCESSOR 2923 KASSERT(uvm_page_locked_p(pg)); 2924 #endif 2925 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2926 } 2927 } else { 2928 /* 2929 * We're mapping an unmanaged page. 2930 * These are always readable, and possibly writable, from 2931 * the get go as we don't need to track ref/mod status. 2932 */ 2933 npte |= l2pte_set_readonly(L2_S_PROTO); 2934 if (prot & VM_PROT_WRITE) 2935 npte = l2pte_set_writable(npte); 2936 2937 /* 2938 * Make sure the vector table is mapped cacheable 2939 */ 2940 if ((pm != pmap_kernel() && va == vector_page) || 2941 (flags & ARM32_MMAP_CACHEABLE)) { 2942 npte |= pte_l2_s_cache_mode; 2943 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 2944 npte |= pte_l2_s_wc_mode; 2945 } 2946 if (opg) { 2947 /* 2948 * Looks like there's an existing 'managed' mapping 2949 * at this address. 2950 */ 2951 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2952 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2953 2954 #ifdef MULTIPROCESSOR 2955 KASSERT(uvm_page_locked_p(opg)); 2956 #endif 2957 pv = pmap_remove_pv(omd, opa, pm, va); 2958 pmap_vac_me_harder(omd, opa, pm, 0); 2959 oflags = pv->pv_flags; 2960 2961 #ifdef PMAP_CACHE_VIVT 2962 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2963 if (PV_BEEN_EXECD(oflags)) 2964 pmap_idcache_wbinv_range(pm, va, 2965 PAGE_SIZE); 2966 else 2967 if (PV_BEEN_REFD(oflags)) 2968 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2969 true, (oflags & PVF_WRITE) == 0); 2970 } 2971 #endif 2972 pool_put(&pmap_pv_pool, pv); 2973 } 2974 } 2975 2976 /* 2977 * Make sure userland mappings get the right permissions 2978 */ 2979 if (pm != pmap_kernel() && va != vector_page) 2980 npte |= L2_S_PROT_U; 2981 2982 /* 2983 * Keep the stats up to date 2984 */ 2985 if (opte == 0) { 2986 l2b->l2b_occupancy++; 2987 pm->pm_stats.resident_count++; 2988 } 2989 2990 NPDEBUG(PDB_ENTER, 2991 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2992 2993 /* 2994 * If this is just a wiring change, the two PTEs will be 2995 * identical, so there's no need to update the page table. 2996 */ 2997 if (npte != opte) { 2998 bool is_cached = pmap_is_cached(pm); 2999 3000 *ptep = npte; 3001 PTE_SYNC(ptep); 3002 if (is_cached) { 3003 /* 3004 * We only need to frob the cache/tlb if this pmap 3005 * is current 3006 */ 3007 if (va != vector_page && l2pte_valid(npte)) { 3008 /* 3009 * This mapping is likely to be accessed as 3010 * soon as we return to userland. Fix up the 3011 * L1 entry to avoid taking another 3012 * page/domain fault. 3013 */ 3014 pd_entry_t *pl1pd, l1pd; 3015 3016 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3017 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3018 L1_C_PROTO; 3019 if (*pl1pd != l1pd) { 3020 *pl1pd = l1pd; 3021 PTE_SYNC(pl1pd); 3022 } 3023 } 3024 } 3025 3026 if (PV_BEEN_EXECD(oflags)) 3027 pmap_tlb_flushID_SE(pm, va); 3028 else 3029 if (PV_BEEN_REFD(oflags)) 3030 pmap_tlb_flushD_SE(pm, va); 3031 3032 NPDEBUG(PDB_ENTER, 3033 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3034 is_cached, pm->pm_cstate.cs_all)); 3035 3036 if (pg != NULL) { 3037 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3038 3039 #ifdef MULTIPROCESSOR 3040 KASSERT(uvm_page_locked_p(pg)); 3041 #endif 3042 pmap_vac_me_harder(md, pa, pm, va); 3043 } 3044 } 3045 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3046 if (pg) { 3047 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3048 3049 #ifdef MULTIPROCESSOR 3050 KASSERT(uvm_page_locked_p(pg)); 3051 #endif 3052 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3053 KASSERTMSG(arm_cache_prefer_mask == 0 || ((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0), 3054 "pg %p: attrs=%#x urw=%u krw=%u", pg, 3055 md->pvh_attrs, md->urw_mappings, md->krw_mappings); 3056 } 3057 #endif 3058 3059 pmap_release_pmap_lock(pm); 3060 3061 return (0); 3062 } 3063 3064 /* 3065 * pmap_remove() 3066 * 3067 * pmap_remove is responsible for nuking a number of mappings for a range 3068 * of virtual address space in the current pmap. To do this efficiently 3069 * is interesting, because in a number of cases a wide virtual address 3070 * range may be supplied that contains few actual mappings. So, the 3071 * optimisations are: 3072 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3073 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3074 * maybe do just a partial cache clean. This path of execution is 3075 * complicated by the fact that the cache must be flushed _before_ 3076 * the PTE is nuked, being a VAC :-) 3077 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3078 * all invalidations until pmap_update(), since pmap_remove_all() has 3079 * already flushed the cache. 3080 * 4. Maybe later fast-case a single page, but I don't think this is 3081 * going to make _that_ much difference overall. 3082 */ 3083 3084 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3085 3086 void 3087 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3088 { 3089 struct l2_bucket *l2b; 3090 vaddr_t next_bucket; 3091 pt_entry_t *ptep; 3092 u_int cleanlist_idx, total, cnt; 3093 struct { 3094 vaddr_t va; 3095 pt_entry_t *ptep; 3096 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3097 u_int mappings, is_exec, is_refd; 3098 3099 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3100 "eva=%08lx\n", pm, sva, eva)); 3101 3102 /* 3103 * we lock in the pmap => pv_head direction 3104 */ 3105 pmap_acquire_pmap_lock(pm); 3106 3107 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3108 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3109 if (pm->pm_cstate.cs_tlb == 0) 3110 pm->pm_remove_all = true; 3111 } else 3112 cleanlist_idx = 0; 3113 3114 total = 0; 3115 3116 while (sva < eva) { 3117 /* 3118 * Do one L2 bucket's worth at a time. 3119 */ 3120 next_bucket = L2_NEXT_BUCKET(sva); 3121 if (next_bucket > eva) 3122 next_bucket = eva; 3123 3124 l2b = pmap_get_l2_bucket(pm, sva); 3125 if (l2b == NULL) { 3126 sva = next_bucket; 3127 continue; 3128 } 3129 3130 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3131 3132 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3133 struct vm_page *pg; 3134 pt_entry_t pte; 3135 paddr_t pa; 3136 3137 pte = *ptep; 3138 3139 if (pte == 0) { 3140 /* Nothing here, move along */ 3141 continue; 3142 } 3143 3144 pa = l2pte_pa(pte); 3145 is_exec = 0; 3146 is_refd = 1; 3147 3148 /* 3149 * Update flags. In a number of circumstances, 3150 * we could cluster a lot of these and do a 3151 * number of sequential pages in one go. 3152 */ 3153 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3154 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3155 struct pv_entry *pv; 3156 3157 #ifdef MULTIPROCESSOR 3158 KASSERT(uvm_page_locked_p(pg)); 3159 #endif 3160 pv = pmap_remove_pv(md, pa, pm, sva); 3161 pmap_vac_me_harder(md, pa, pm, 0); 3162 if (pv != NULL) { 3163 if (pm->pm_remove_all == false) { 3164 is_exec = 3165 PV_BEEN_EXECD(pv->pv_flags); 3166 is_refd = 3167 PV_BEEN_REFD(pv->pv_flags); 3168 } 3169 pool_put(&pmap_pv_pool, pv); 3170 } 3171 } 3172 mappings++; 3173 3174 if (!l2pte_valid(pte)) { 3175 /* 3176 * Ref/Mod emulation is still active for this 3177 * mapping, therefore it is has not yet been 3178 * accessed. No need to frob the cache/tlb. 3179 */ 3180 *ptep = 0; 3181 PTE_SYNC_CURRENT(pm, ptep); 3182 continue; 3183 } 3184 3185 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3186 /* Add to the clean list. */ 3187 cleanlist[cleanlist_idx].ptep = ptep; 3188 cleanlist[cleanlist_idx].va = 3189 sva | (is_exec & 1); 3190 cleanlist_idx++; 3191 } else 3192 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3193 /* Nuke everything if needed. */ 3194 #ifdef PMAP_CACHE_VIVT 3195 pmap_idcache_wbinv_all(pm); 3196 #endif 3197 pmap_tlb_flushID(pm); 3198 3199 /* 3200 * Roll back the previous PTE list, 3201 * and zero out the current PTE. 3202 */ 3203 for (cnt = 0; 3204 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3205 *cleanlist[cnt].ptep = 0; 3206 PTE_SYNC(cleanlist[cnt].ptep); 3207 } 3208 *ptep = 0; 3209 PTE_SYNC(ptep); 3210 cleanlist_idx++; 3211 pm->pm_remove_all = true; 3212 } else { 3213 *ptep = 0; 3214 PTE_SYNC(ptep); 3215 if (pm->pm_remove_all == false) { 3216 if (is_exec) 3217 pmap_tlb_flushID_SE(pm, sva); 3218 else 3219 if (is_refd) 3220 pmap_tlb_flushD_SE(pm, sva); 3221 } 3222 } 3223 } 3224 3225 /* 3226 * Deal with any left overs 3227 */ 3228 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3229 total += cleanlist_idx; 3230 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3231 if (pm->pm_cstate.cs_all != 0) { 3232 vaddr_t clva = cleanlist[cnt].va & ~1; 3233 if (cleanlist[cnt].va & 1) { 3234 #ifdef PMAP_CACHE_VIVT 3235 pmap_idcache_wbinv_range(pm, 3236 clva, PAGE_SIZE); 3237 #endif 3238 pmap_tlb_flushID_SE(pm, clva); 3239 } else { 3240 #ifdef PMAP_CACHE_VIVT 3241 pmap_dcache_wb_range(pm, 3242 clva, PAGE_SIZE, true, 3243 false); 3244 #endif 3245 pmap_tlb_flushD_SE(pm, clva); 3246 } 3247 } 3248 *cleanlist[cnt].ptep = 0; 3249 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3250 } 3251 3252 /* 3253 * If it looks like we're removing a whole bunch 3254 * of mappings, it's faster to just write-back 3255 * the whole cache now and defer TLB flushes until 3256 * pmap_update() is called. 3257 */ 3258 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3259 cleanlist_idx = 0; 3260 else { 3261 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3262 #ifdef PMAP_CACHE_VIVT 3263 pmap_idcache_wbinv_all(pm); 3264 #endif 3265 pm->pm_remove_all = true; 3266 } 3267 } 3268 3269 pmap_free_l2_bucket(pm, l2b, mappings); 3270 pm->pm_stats.resident_count -= mappings; 3271 } 3272 3273 pmap_release_pmap_lock(pm); 3274 } 3275 3276 #ifdef PMAP_CACHE_VIPT 3277 static struct pv_entry * 3278 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3279 { 3280 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3281 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3282 struct pv_entry *pv; 3283 3284 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3285 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3286 3287 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3288 KASSERT(pv); 3289 KASSERT(pv->pv_flags & PVF_KENTRY); 3290 3291 /* 3292 * If we are removing a writeable mapping to a cached exec page, 3293 * if it's the last mapping then clear it execness other sync 3294 * the page to the icache. 3295 */ 3296 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3297 && (pv->pv_flags & PVF_WRITE) != 0) { 3298 if (SLIST_EMPTY(&md->pvh_list)) { 3299 md->pvh_attrs &= ~PVF_EXEC; 3300 PMAPCOUNT(exec_discarded_kremove); 3301 } else { 3302 pmap_syncicache_page(md, pa); 3303 PMAPCOUNT(exec_synced_kremove); 3304 } 3305 } 3306 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3307 3308 return pv; 3309 } 3310 #endif /* PMAP_CACHE_VIPT */ 3311 3312 /* 3313 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3314 * 3315 * We assume there is already sufficient KVM space available 3316 * to do this, as we can't allocate L2 descriptor tables/metadata 3317 * from here. 3318 */ 3319 void 3320 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3321 { 3322 struct l2_bucket *l2b; 3323 pt_entry_t *ptep, opte; 3324 #ifdef PMAP_CACHE_VIVT 3325 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3326 #endif 3327 #ifdef PMAP_CACHE_VIPT 3328 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3329 struct vm_page *opg; 3330 struct pv_entry *pv = NULL; 3331 #endif 3332 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3333 3334 NPDEBUG(PDB_KENTER, 3335 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3336 va, pa, prot)); 3337 3338 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3339 KDASSERT(l2b != NULL); 3340 3341 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3342 opte = *ptep; 3343 3344 if (opte == 0) { 3345 PMAPCOUNT(kenter_mappings); 3346 l2b->l2b_occupancy++; 3347 } else { 3348 PMAPCOUNT(kenter_remappings); 3349 #ifdef PMAP_CACHE_VIPT 3350 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3351 #ifdef DIAGNOSTIC 3352 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3353 #endif 3354 if (opg) { 3355 KASSERT(opg != pg); 3356 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3357 KASSERT((flags & PMAP_KMPAGE) == 0); 3358 pv = pmap_kremove_pg(opg, va); 3359 } 3360 #endif 3361 if (l2pte_valid(opte)) { 3362 #ifdef PMAP_CACHE_VIVT 3363 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3364 #endif 3365 cpu_tlb_flushD_SE(va); 3366 cpu_cpwait(); 3367 } 3368 } 3369 3370 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3371 | ((flags & PMAP_NOCACHE) ? 0 : pte_l2_s_cache_mode); 3372 PTE_SYNC(ptep); 3373 3374 if (pg) { 3375 #ifdef MULTIPROCESSOR 3376 KASSERT(uvm_page_locked_p(pg)); 3377 #endif 3378 if (flags & PMAP_KMPAGE) { 3379 KASSERT(md->urw_mappings == 0); 3380 KASSERT(md->uro_mappings == 0); 3381 KASSERT(md->krw_mappings == 0); 3382 KASSERT(md->kro_mappings == 0); 3383 #ifdef PMAP_CACHE_VIPT 3384 KASSERT(pv == NULL); 3385 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3386 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3387 /* if there is a color conflict, evict from cache. */ 3388 if (pmap_is_page_colored_p(md) 3389 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3390 PMAPCOUNT(vac_color_change); 3391 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3392 } else if (md->pvh_attrs & PVF_MULTCLR) { 3393 /* 3394 * If this page has multiple colors, expunge 3395 * them. 3396 */ 3397 PMAPCOUNT(vac_flush_lots2); 3398 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3399 } 3400 md->pvh_attrs &= PAGE_SIZE - 1; 3401 md->pvh_attrs |= PVF_KMPAGE 3402 | PVF_COLORED | PVF_DIRTY 3403 | (va & arm_cache_prefer_mask); 3404 #endif 3405 #ifdef PMAP_CACHE_VIVT 3406 md->pvh_attrs |= PVF_KMPAGE; 3407 #endif 3408 pmap_kmpages++; 3409 #ifdef PMAP_CACHE_VIPT 3410 } else { 3411 if (pv == NULL) { 3412 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3413 KASSERT(pv != NULL); 3414 } 3415 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3416 PVF_WIRED | PVF_KENTRY 3417 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3418 if ((prot & VM_PROT_WRITE) 3419 && !(md->pvh_attrs & PVF_NC)) 3420 md->pvh_attrs |= PVF_DIRTY; 3421 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3422 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3423 #endif 3424 } 3425 #ifdef PMAP_CACHE_VIPT 3426 } else { 3427 if (pv != NULL) 3428 pool_put(&pmap_pv_pool, pv); 3429 #endif 3430 } 3431 } 3432 3433 void 3434 pmap_kremove(vaddr_t va, vsize_t len) 3435 { 3436 struct l2_bucket *l2b; 3437 pt_entry_t *ptep, *sptep, opte; 3438 vaddr_t next_bucket, eva; 3439 u_int mappings; 3440 struct vm_page *opg; 3441 3442 PMAPCOUNT(kenter_unmappings); 3443 3444 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3445 va, len)); 3446 3447 eva = va + len; 3448 3449 while (va < eva) { 3450 next_bucket = L2_NEXT_BUCKET(va); 3451 if (next_bucket > eva) 3452 next_bucket = eva; 3453 3454 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3455 KDASSERT(l2b != NULL); 3456 3457 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3458 mappings = 0; 3459 3460 while (va < next_bucket) { 3461 opte = *ptep; 3462 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3463 if (opg) { 3464 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3465 3466 if (omd->pvh_attrs & PVF_KMPAGE) { 3467 KASSERT(omd->urw_mappings == 0); 3468 KASSERT(omd->uro_mappings == 0); 3469 KASSERT(omd->krw_mappings == 0); 3470 KASSERT(omd->kro_mappings == 0); 3471 omd->pvh_attrs &= ~PVF_KMPAGE; 3472 #ifdef PMAP_CACHE_VIPT 3473 omd->pvh_attrs &= ~PVF_WRITE; 3474 #endif 3475 pmap_kmpages--; 3476 #ifdef PMAP_CACHE_VIPT 3477 } else { 3478 pool_put(&pmap_pv_pool, 3479 pmap_kremove_pg(opg, va)); 3480 #endif 3481 } 3482 } 3483 if (l2pte_valid(opte)) { 3484 #ifdef PMAP_CACHE_VIVT 3485 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3486 #endif 3487 cpu_tlb_flushD_SE(va); 3488 } 3489 if (opte) { 3490 *ptep = 0; 3491 mappings++; 3492 } 3493 va += PAGE_SIZE; 3494 ptep++; 3495 } 3496 KDASSERT(mappings <= l2b->l2b_occupancy); 3497 l2b->l2b_occupancy -= mappings; 3498 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3499 } 3500 cpu_cpwait(); 3501 } 3502 3503 bool 3504 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3505 { 3506 struct l2_dtable *l2; 3507 pd_entry_t *pl1pd, l1pd; 3508 pt_entry_t *ptep, pte; 3509 paddr_t pa; 3510 u_int l1idx; 3511 3512 pmap_acquire_pmap_lock(pm); 3513 3514 l1idx = L1_IDX(va); 3515 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3516 l1pd = *pl1pd; 3517 3518 if (l1pte_section_p(l1pd)) { 3519 /* 3520 * These should only happen for pmap_kernel() 3521 */ 3522 KDASSERT(pm == pmap_kernel()); 3523 pmap_release_pmap_lock(pm); 3524 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3525 if (l1pte_supersection_p(l1pd)) { 3526 pa = (l1pd & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3527 } else 3528 #endif 3529 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3530 } else { 3531 /* 3532 * Note that we can't rely on the validity of the L1 3533 * descriptor as an indication that a mapping exists. 3534 * We have to look it up in the L2 dtable. 3535 */ 3536 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3537 3538 if (l2 == NULL || 3539 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3540 pmap_release_pmap_lock(pm); 3541 return false; 3542 } 3543 3544 ptep = &ptep[l2pte_index(va)]; 3545 pte = *ptep; 3546 pmap_release_pmap_lock(pm); 3547 3548 if (pte == 0) 3549 return false; 3550 3551 switch (pte & L2_TYPE_MASK) { 3552 case L2_TYPE_L: 3553 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3554 break; 3555 3556 default: 3557 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3558 break; 3559 } 3560 } 3561 3562 if (pap != NULL) 3563 *pap = pa; 3564 3565 return true; 3566 } 3567 3568 void 3569 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3570 { 3571 struct l2_bucket *l2b; 3572 pt_entry_t *ptep, pte; 3573 vaddr_t next_bucket; 3574 u_int flags; 3575 u_int clr_mask; 3576 int flush; 3577 3578 NPDEBUG(PDB_PROTECT, 3579 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3580 pm, sva, eva, prot)); 3581 3582 if ((prot & VM_PROT_READ) == 0) { 3583 pmap_remove(pm, sva, eva); 3584 return; 3585 } 3586 3587 if (prot & VM_PROT_WRITE) { 3588 /* 3589 * If this is a read->write transition, just ignore it and let 3590 * uvm_fault() take care of it later. 3591 */ 3592 return; 3593 } 3594 3595 pmap_acquire_pmap_lock(pm); 3596 3597 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3598 flags = 0; 3599 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3600 3601 while (sva < eva) { 3602 next_bucket = L2_NEXT_BUCKET(sva); 3603 if (next_bucket > eva) 3604 next_bucket = eva; 3605 3606 l2b = pmap_get_l2_bucket(pm, sva); 3607 if (l2b == NULL) { 3608 sva = next_bucket; 3609 continue; 3610 } 3611 3612 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3613 3614 while (sva < next_bucket) { 3615 pte = *ptep; 3616 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3617 struct vm_page *pg; 3618 u_int f; 3619 3620 #ifdef PMAP_CACHE_VIVT 3621 /* 3622 * OK, at this point, we know we're doing 3623 * write-protect operation. If the pmap is 3624 * active, write-back the page. 3625 */ 3626 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3627 false, false); 3628 #endif 3629 3630 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3631 pte = l2pte_set_readonly(pte); 3632 *ptep = pte; 3633 PTE_SYNC(ptep); 3634 3635 if (pg != NULL) { 3636 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3637 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3638 3639 #ifdef MULTIPROCESSOR 3640 KASSERT(uvm_page_locked_p(pg)); 3641 #endif 3642 f = pmap_modify_pv(md, pa, pm, sva, 3643 clr_mask, 0); 3644 pmap_vac_me_harder(md, pa, pm, sva); 3645 } else { 3646 f = PVF_REF | PVF_EXEC; 3647 } 3648 3649 if (flush >= 0) { 3650 flush++; 3651 flags |= f; 3652 } else 3653 if (PV_BEEN_EXECD(f)) 3654 pmap_tlb_flushID_SE(pm, sva); 3655 else 3656 if (PV_BEEN_REFD(f)) 3657 pmap_tlb_flushD_SE(pm, sva); 3658 } 3659 3660 sva += PAGE_SIZE; 3661 ptep++; 3662 } 3663 } 3664 3665 pmap_release_pmap_lock(pm); 3666 3667 if (flush) { 3668 if (PV_BEEN_EXECD(flags)) 3669 pmap_tlb_flushID(pm); 3670 else 3671 if (PV_BEEN_REFD(flags)) 3672 pmap_tlb_flushD(pm); 3673 } 3674 } 3675 3676 void 3677 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3678 { 3679 struct l2_bucket *l2b; 3680 pt_entry_t *ptep; 3681 vaddr_t next_bucket; 3682 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3683 3684 NPDEBUG(PDB_EXEC, 3685 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3686 pm, sva, eva)); 3687 3688 pmap_acquire_pmap_lock(pm); 3689 3690 while (sva < eva) { 3691 next_bucket = L2_NEXT_BUCKET(sva); 3692 if (next_bucket > eva) 3693 next_bucket = eva; 3694 3695 l2b = pmap_get_l2_bucket(pm, sva); 3696 if (l2b == NULL) { 3697 sva = next_bucket; 3698 continue; 3699 } 3700 3701 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3702 sva < next_bucket; 3703 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3704 if (l2pte_valid(*ptep)) { 3705 cpu_icache_sync_range(sva, 3706 min(page_size, eva - sva)); 3707 } 3708 } 3709 } 3710 3711 pmap_release_pmap_lock(pm); 3712 } 3713 3714 void 3715 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3716 { 3717 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3718 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3719 3720 NPDEBUG(PDB_PROTECT, 3721 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3722 md, pa, prot)); 3723 3724 #ifdef MULTIPROCESSOR 3725 KASSERT(uvm_page_locked_p(pg)); 3726 #endif 3727 3728 switch(prot) { 3729 case VM_PROT_READ|VM_PROT_WRITE: 3730 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3731 pmap_clearbit(md, pa, PVF_EXEC); 3732 break; 3733 #endif 3734 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3735 break; 3736 3737 case VM_PROT_READ: 3738 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3739 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3740 break; 3741 #endif 3742 case VM_PROT_READ|VM_PROT_EXECUTE: 3743 pmap_clearbit(md, pa, PVF_WRITE); 3744 break; 3745 3746 default: 3747 pmap_page_remove(md, pa); 3748 break; 3749 } 3750 } 3751 3752 /* 3753 * pmap_clear_modify: 3754 * 3755 * Clear the "modified" attribute for a page. 3756 */ 3757 bool 3758 pmap_clear_modify(struct vm_page *pg) 3759 { 3760 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3761 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3762 bool rv; 3763 3764 #ifdef MULTIPROCESSOR 3765 KASSERT(uvm_page_locked_p(pg)); 3766 #endif 3767 3768 if (md->pvh_attrs & PVF_MOD) { 3769 rv = true; 3770 #ifdef PMAP_CACHE_VIPT 3771 /* 3772 * If we are going to clear the modified bit and there are 3773 * no other modified bits set, flush the page to memory and 3774 * mark it clean. 3775 */ 3776 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3777 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3778 #endif 3779 pmap_clearbit(md, pa, PVF_MOD); 3780 } else 3781 rv = false; 3782 3783 return (rv); 3784 } 3785 3786 /* 3787 * pmap_clear_reference: 3788 * 3789 * Clear the "referenced" attribute for a page. 3790 */ 3791 bool 3792 pmap_clear_reference(struct vm_page *pg) 3793 { 3794 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3795 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3796 bool rv; 3797 3798 #ifdef MULTIPROCESSOR 3799 KASSERT(uvm_page_locked_p(pg)); 3800 #endif 3801 3802 if (md->pvh_attrs & PVF_REF) { 3803 rv = true; 3804 pmap_clearbit(md, pa, PVF_REF); 3805 } else 3806 rv = false; 3807 3808 return (rv); 3809 } 3810 3811 /* 3812 * pmap_is_modified: 3813 * 3814 * Test if a page has the "modified" attribute. 3815 */ 3816 /* See <arm/arm32/pmap.h> */ 3817 3818 /* 3819 * pmap_is_referenced: 3820 * 3821 * Test if a page has the "referenced" attribute. 3822 */ 3823 /* See <arm/arm32/pmap.h> */ 3824 3825 int 3826 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3827 { 3828 struct l2_dtable *l2; 3829 struct l2_bucket *l2b; 3830 pd_entry_t *pl1pd, l1pd; 3831 pt_entry_t *ptep, pte; 3832 paddr_t pa; 3833 u_int l1idx; 3834 int rv = 0; 3835 3836 pmap_acquire_pmap_lock(pm); 3837 3838 l1idx = L1_IDX(va); 3839 3840 /* 3841 * If there is no l2_dtable for this address, then the process 3842 * has no business accessing it. 3843 * 3844 * Note: This will catch userland processes trying to access 3845 * kernel addresses. 3846 */ 3847 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3848 if (l2 == NULL) 3849 goto out; 3850 3851 /* 3852 * Likewise if there is no L2 descriptor table 3853 */ 3854 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3855 if (l2b->l2b_kva == NULL) 3856 goto out; 3857 3858 /* 3859 * Check the PTE itself. 3860 */ 3861 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3862 pte = *ptep; 3863 if (pte == 0) 3864 goto out; 3865 3866 /* 3867 * Catch a userland access to the vector page mapped at 0x0 3868 */ 3869 if (user && (pte & L2_S_PROT_U) == 0) 3870 goto out; 3871 3872 pa = l2pte_pa(pte); 3873 3874 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3875 /* 3876 * This looks like a good candidate for "page modified" 3877 * emulation... 3878 */ 3879 struct pv_entry *pv; 3880 struct vm_page *pg; 3881 3882 /* Extract the physical address of the page */ 3883 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3884 goto out; 3885 3886 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3887 3888 /* Get the current flags for this page. */ 3889 #ifdef MULTIPROCESSOR 3890 KASSERT(uvm_page_locked_p(pg)); 3891 #endif 3892 3893 pv = pmap_find_pv(md, pm, va); 3894 if (pv == NULL) { 3895 goto out; 3896 } 3897 3898 /* 3899 * Do the flags say this page is writable? If not then it 3900 * is a genuine write fault. If yes then the write fault is 3901 * our fault as we did not reflect the write access in the 3902 * PTE. Now we know a write has occurred we can correct this 3903 * and also set the modified bit 3904 */ 3905 if ((pv->pv_flags & PVF_WRITE) == 0) { 3906 goto out; 3907 } 3908 3909 NPDEBUG(PDB_FOLLOW, 3910 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3911 pm, va, pa)); 3912 3913 md->pvh_attrs |= PVF_REF | PVF_MOD; 3914 pv->pv_flags |= PVF_REF | PVF_MOD; 3915 #ifdef PMAP_CACHE_VIPT 3916 /* 3917 * If there are cacheable mappings for this page, mark it dirty. 3918 */ 3919 if ((md->pvh_attrs & PVF_NC) == 0) 3920 md->pvh_attrs |= PVF_DIRTY; 3921 #endif 3922 3923 /* 3924 * Re-enable write permissions for the page. No need to call 3925 * pmap_vac_me_harder(), since this is just a 3926 * modified-emulation fault, and the PVF_WRITE bit isn't 3927 * changing. We've already set the cacheable bits based on 3928 * the assumption that we can write to this page. 3929 */ 3930 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3931 PTE_SYNC(ptep); 3932 rv = 1; 3933 } else 3934 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3935 /* 3936 * This looks like a good candidate for "page referenced" 3937 * emulation. 3938 */ 3939 struct pv_entry *pv; 3940 struct vm_page *pg; 3941 3942 /* Extract the physical address of the page */ 3943 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3944 goto out; 3945 3946 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3947 3948 /* Get the current flags for this page. */ 3949 #ifdef MULTIPROCESSOR 3950 KASSERT(uvm_page_locked_p(pg)); 3951 #endif 3952 3953 pv = pmap_find_pv(md, pm, va); 3954 if (pv == NULL) { 3955 goto out; 3956 } 3957 3958 md->pvh_attrs |= PVF_REF; 3959 pv->pv_flags |= PVF_REF; 3960 3961 NPDEBUG(PDB_FOLLOW, 3962 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3963 pm, va, pa)); 3964 3965 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3966 PTE_SYNC(ptep); 3967 rv = 1; 3968 } 3969 3970 /* 3971 * We know there is a valid mapping here, so simply 3972 * fix up the L1 if necessary. 3973 */ 3974 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3975 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3976 if (*pl1pd != l1pd) { 3977 *pl1pd = l1pd; 3978 PTE_SYNC(pl1pd); 3979 rv = 1; 3980 } 3981 3982 #ifdef CPU_SA110 3983 /* 3984 * There are bugs in the rev K SA110. This is a check for one 3985 * of them. 3986 */ 3987 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3988 curcpu()->ci_arm_cpurev < 3) { 3989 /* Always current pmap */ 3990 if (l2pte_valid(pte)) { 3991 extern int kernel_debug; 3992 if (kernel_debug & 1) { 3993 struct proc *p = curlwp->l_proc; 3994 printf("prefetch_abort: page is already " 3995 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3996 printf("prefetch_abort: pc=%08lx proc=%p " 3997 "process=%s\n", va, p, p->p_comm); 3998 printf("prefetch_abort: far=%08x fs=%x\n", 3999 cpu_faultaddress(), cpu_faultstatus()); 4000 } 4001 #ifdef DDB 4002 if (kernel_debug & 2) 4003 Debugger(); 4004 #endif 4005 rv = 1; 4006 } 4007 } 4008 #endif /* CPU_SA110 */ 4009 4010 /* 4011 * If 'rv == 0' at this point, it generally indicates that there is a 4012 * stale TLB entry for the faulting address. That might be due to a 4013 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4014 */ 4015 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1 4016 && pmap_needs_pte_sync == 0) { 4017 pmap_needs_pte_sync = 1; 4018 PTE_SYNC(ptep); 4019 rv = 1; 4020 } 4021 4022 #ifdef DEBUG 4023 /* 4024 * If 'rv == 0' at this point, it generally indicates that there is a 4025 * stale TLB entry for the faulting address. This happens when two or 4026 * more processes are sharing an L1. Since we don't flush the TLB on 4027 * a context switch between such processes, we can take domain faults 4028 * for mappings which exist at the same VA in both processes. EVEN IF 4029 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4030 * example. 4031 * 4032 * This is extremely likely to happen if pmap_enter() updated the L1 4033 * entry for a recently entered mapping. In this case, the TLB is 4034 * flushed for the new mapping, but there may still be TLB entries for 4035 * other mappings belonging to other processes in the 1MB range 4036 * covered by the L1 entry. 4037 * 4038 * Since 'rv == 0', we know that the L1 already contains the correct 4039 * value, so the fault must be due to a stale TLB entry. 4040 * 4041 * Since we always need to flush the TLB anyway in the case where we 4042 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4043 * stale TLB entries dynamically. 4044 * 4045 * However, the above condition can ONLY happen if the current L1 is 4046 * being shared. If it happens when the L1 is unshared, it indicates 4047 * that other parts of the pmap are not doing their job WRT managing 4048 * the TLB. 4049 */ 4050 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4051 extern int last_fault_code; 4052 extern int kernel_debug; 4053 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4054 pm, va, ftype); 4055 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4056 l2, l2b, ptep, pl1pd); 4057 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4058 pte, l1pd, last_fault_code); 4059 #ifdef DDB 4060 if (kernel_debug & 2) 4061 Debugger(); 4062 #endif 4063 } 4064 #endif 4065 4066 cpu_tlb_flushID_SE(va); 4067 cpu_cpwait(); 4068 4069 rv = 1; 4070 4071 out: 4072 pmap_release_pmap_lock(pm); 4073 4074 return (rv); 4075 } 4076 4077 /* 4078 * Routine: pmap_procwr 4079 * 4080 * Function: 4081 * Synchronize caches corresponding to [addr, addr+len) in p. 4082 * 4083 */ 4084 void 4085 pmap_procwr(struct proc *p, vaddr_t va, int len) 4086 { 4087 /* We only need to do anything if it is the current process. */ 4088 if (p == curproc) 4089 cpu_icache_sync_range(va, len); 4090 } 4091 4092 /* 4093 * Routine: pmap_unwire 4094 * Function: Clear the wired attribute for a map/virtual-address pair. 4095 * 4096 * In/out conditions: 4097 * The mapping must already exist in the pmap. 4098 */ 4099 void 4100 pmap_unwire(pmap_t pm, vaddr_t va) 4101 { 4102 struct l2_bucket *l2b; 4103 pt_entry_t *ptep, pte; 4104 struct vm_page *pg; 4105 paddr_t pa; 4106 4107 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4108 4109 pmap_acquire_pmap_lock(pm); 4110 4111 l2b = pmap_get_l2_bucket(pm, va); 4112 KDASSERT(l2b != NULL); 4113 4114 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4115 pte = *ptep; 4116 4117 /* Extract the physical address of the page */ 4118 pa = l2pte_pa(pte); 4119 4120 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4121 /* Update the wired bit in the pv entry for this page. */ 4122 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4123 4124 #ifdef MULTIPROCESSOR 4125 KASSERT(uvm_page_locked_p(pg)); 4126 #endif 4127 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4128 } 4129 4130 pmap_release_pmap_lock(pm); 4131 } 4132 4133 void 4134 pmap_activate(struct lwp *l) 4135 { 4136 extern int block_userspace_access; 4137 pmap_t opm, npm, rpm; 4138 uint32_t odacr, ndacr; 4139 int oldirqstate; 4140 4141 /* 4142 * If activating a non-current lwp or the current lwp is 4143 * already active, just return. 4144 */ 4145 if (l != curlwp || 4146 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4147 return; 4148 4149 npm = l->l_proc->p_vmspace->vm_map.pmap; 4150 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4151 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4152 4153 /* 4154 * If TTB and DACR are unchanged, short-circuit all the 4155 * TLB/cache management stuff. 4156 */ 4157 if (pmap_previous_active_lwp != NULL) { 4158 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4159 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4160 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4161 4162 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4163 goto all_done; 4164 } else 4165 opm = NULL; 4166 4167 PMAPCOUNT(activations); 4168 block_userspace_access = 1; 4169 4170 /* 4171 * If switching to a user vmspace which is different to the 4172 * most recent one, and the most recent one is potentially 4173 * live in the cache, we must write-back and invalidate the 4174 * entire cache. 4175 */ 4176 rpm = pmap_recent_user; 4177 4178 /* 4179 * XXXSCW: There's a corner case here which can leave turds in the cache as 4180 * reported in kern/41058. They're probably left over during tear-down and 4181 * switching away from an exiting process. Until the root cause is identified 4182 * and fixed, zap the cache when switching pmaps. This will result in a few 4183 * unnecessary cache flushes, but that's better than silently corrupting data. 4184 */ 4185 #if 0 4186 if (npm != pmap_kernel() && rpm && npm != rpm && 4187 rpm->pm_cstate.cs_cache) { 4188 rpm->pm_cstate.cs_cache = 0; 4189 #ifdef PMAP_CACHE_VIVT 4190 cpu_idcache_wbinv_all(); 4191 #endif 4192 } 4193 #else 4194 if (rpm) { 4195 rpm->pm_cstate.cs_cache = 0; 4196 if (npm == pmap_kernel()) 4197 pmap_recent_user = NULL; 4198 #ifdef PMAP_CACHE_VIVT 4199 cpu_idcache_wbinv_all(); 4200 #endif 4201 } 4202 #endif 4203 4204 /* No interrupts while we frob the TTB/DACR */ 4205 oldirqstate = disable_interrupts(IF32_bits); 4206 4207 /* 4208 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4209 * entry corresponding to 'vector_page' in the incoming L1 table 4210 * before switching to it otherwise subsequent interrupts/exceptions 4211 * (including domain faults!) will jump into hyperspace. 4212 */ 4213 if (npm->pm_pl1vec != NULL) { 4214 cpu_tlb_flushID_SE((u_int)vector_page); 4215 cpu_cpwait(); 4216 *npm->pm_pl1vec = npm->pm_l1vec; 4217 PTE_SYNC(npm->pm_pl1vec); 4218 } 4219 4220 cpu_domains(ndacr); 4221 4222 if (npm == pmap_kernel() || npm == rpm) { 4223 /* 4224 * Switching to a kernel thread, or back to the 4225 * same user vmspace as before... Simply update 4226 * the TTB (no TLB flush required) 4227 */ 4228 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4229 cpu_cpwait(); 4230 } else { 4231 /* 4232 * Otherwise, update TTB and flush TLB 4233 */ 4234 cpu_context_switch(npm->pm_l1->l1_physaddr); 4235 if (rpm != NULL) 4236 rpm->pm_cstate.cs_tlb = 0; 4237 } 4238 4239 restore_interrupts(oldirqstate); 4240 4241 block_userspace_access = 0; 4242 4243 all_done: 4244 /* 4245 * The new pmap is resident. Make sure it's marked 4246 * as resident in the cache/TLB. 4247 */ 4248 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4249 if (npm != pmap_kernel()) 4250 pmap_recent_user = npm; 4251 4252 /* The old pmap is not longer active */ 4253 if (opm != NULL) 4254 opm->pm_activated = false; 4255 4256 /* But the new one is */ 4257 npm->pm_activated = true; 4258 } 4259 4260 void 4261 pmap_deactivate(struct lwp *l) 4262 { 4263 4264 /* 4265 * If the process is exiting, make sure pmap_activate() does 4266 * a full MMU context-switch and cache flush, which we might 4267 * otherwise skip. See PR port-arm/38950. 4268 */ 4269 if (l->l_proc->p_sflag & PS_WEXIT) 4270 pmap_previous_active_lwp = NULL; 4271 4272 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4273 } 4274 4275 void 4276 pmap_update(pmap_t pm) 4277 { 4278 4279 if (pm->pm_remove_all) { 4280 /* 4281 * Finish up the pmap_remove_all() optimisation by flushing 4282 * the TLB. 4283 */ 4284 pmap_tlb_flushID(pm); 4285 pm->pm_remove_all = false; 4286 } 4287 4288 if (pmap_is_current(pm)) { 4289 /* 4290 * If we're dealing with a current userland pmap, move its L1 4291 * to the end of the LRU. 4292 */ 4293 if (pm != pmap_kernel()) 4294 pmap_use_l1(pm); 4295 4296 /* 4297 * We can assume we're done with frobbing the cache/tlb for 4298 * now. Make sure any future pmap ops don't skip cache/tlb 4299 * flushes. 4300 */ 4301 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4302 } 4303 4304 PMAPCOUNT(updates); 4305 4306 /* 4307 * make sure TLB/cache operations have completed. 4308 */ 4309 cpu_cpwait(); 4310 } 4311 4312 void 4313 pmap_remove_all(pmap_t pm) 4314 { 4315 4316 /* 4317 * The vmspace described by this pmap is about to be torn down. 4318 * Until pmap_update() is called, UVM will only make calls 4319 * to pmap_remove(). We can make life much simpler by flushing 4320 * the cache now, and deferring TLB invalidation to pmap_update(). 4321 */ 4322 #ifdef PMAP_CACHE_VIVT 4323 pmap_idcache_wbinv_all(pm); 4324 #endif 4325 pm->pm_remove_all = true; 4326 } 4327 4328 /* 4329 * Retire the given physical map from service. 4330 * Should only be called if the map contains no valid mappings. 4331 */ 4332 void 4333 pmap_destroy(pmap_t pm) 4334 { 4335 u_int count; 4336 4337 if (pm == NULL) 4338 return; 4339 4340 if (pm->pm_remove_all) { 4341 pmap_tlb_flushID(pm); 4342 pm->pm_remove_all = false; 4343 } 4344 4345 /* 4346 * Drop reference count 4347 */ 4348 mutex_enter(pm->pm_lock); 4349 count = --pm->pm_obj.uo_refs; 4350 mutex_exit(pm->pm_lock); 4351 if (count > 0) { 4352 if (pmap_is_current(pm)) { 4353 if (pm != pmap_kernel()) 4354 pmap_use_l1(pm); 4355 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4356 } 4357 return; 4358 } 4359 4360 /* 4361 * reference count is zero, free pmap resources and then free pmap. 4362 */ 4363 4364 if (vector_page < KERNEL_BASE) { 4365 KDASSERT(!pmap_is_current(pm)); 4366 4367 /* Remove the vector page mapping */ 4368 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4369 pmap_update(pm); 4370 } 4371 4372 LIST_REMOVE(pm, pm_list); 4373 4374 pmap_free_l1(pm); 4375 4376 if (pmap_recent_user == pm) 4377 pmap_recent_user = NULL; 4378 4379 uvm_obj_destroy(&pm->pm_obj, false); 4380 mutex_destroy(&pm->pm_obj_lock); 4381 pool_cache_put(&pmap_cache, pm); 4382 } 4383 4384 4385 /* 4386 * void pmap_reference(pmap_t pm) 4387 * 4388 * Add a reference to the specified pmap. 4389 */ 4390 void 4391 pmap_reference(pmap_t pm) 4392 { 4393 4394 if (pm == NULL) 4395 return; 4396 4397 pmap_use_l1(pm); 4398 4399 mutex_enter(pm->pm_lock); 4400 pm->pm_obj.uo_refs++; 4401 mutex_exit(pm->pm_lock); 4402 } 4403 4404 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4405 4406 static struct evcnt pmap_prefer_nochange_ev = 4407 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4408 static struct evcnt pmap_prefer_change_ev = 4409 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4410 4411 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4412 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4413 4414 void 4415 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4416 { 4417 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4418 vaddr_t va = *vap; 4419 vaddr_t diff = (hint - va) & mask; 4420 if (diff == 0) { 4421 pmap_prefer_nochange_ev.ev_count++; 4422 } else { 4423 pmap_prefer_change_ev.ev_count++; 4424 if (__predict_false(td)) 4425 va -= mask + 1; 4426 *vap = va + diff; 4427 } 4428 } 4429 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4430 4431 /* 4432 * pmap_zero_page() 4433 * 4434 * Zero a given physical page by mapping it at a page hook point. 4435 * In doing the zero page op, the page we zero is mapped cachable, as with 4436 * StrongARM accesses to non-cached pages are non-burst making writing 4437 * _any_ bulk data very slow. 4438 */ 4439 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4440 void 4441 pmap_zero_page_generic(paddr_t phys) 4442 { 4443 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4444 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4445 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4446 #endif 4447 #if defined(PMAP_CACHE_VIPT) 4448 /* Choose the last page color it had, if any */ 4449 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4450 #else 4451 const vsize_t va_offset = 0; 4452 #endif 4453 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 4454 /* 4455 * Is this page mapped at its natural color? 4456 * If we have all of memory mapped, then just convert PA to VA. 4457 */ 4458 const bool okcolor = va_offset == (phys & arm_cache_prefer_mask); 4459 const vaddr_t vdstp = KERNEL_BASE + (phys - physical_start); 4460 #else 4461 const bool okcolor = false; 4462 const vaddr_t vdstp = cdstp + va_offset; 4463 #endif 4464 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4465 4466 4467 #ifdef DEBUG 4468 if (!SLIST_EMPTY(&md->pvh_list)) 4469 panic("pmap_zero_page: page has mappings"); 4470 #endif 4471 4472 KDASSERT((phys & PGOFSET) == 0); 4473 4474 if (!okcolor) { 4475 /* 4476 * Hook in the page, zero it, and purge the cache for that 4477 * zeroed page. Invalidate the TLB as needed. 4478 */ 4479 *ptep = L2_S_PROTO | phys | 4480 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4481 PTE_SYNC(ptep); 4482 cpu_tlb_flushD_SE(cdstp + va_offset); 4483 cpu_cpwait(); 4484 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 4485 /* 4486 * If we are direct-mapped and our color isn't ok, then before 4487 * we bzero the page invalidate its contents from the cache and 4488 * reset the color to its natural color. 4489 */ 4490 cpu_dcache_inv_range(cdstp + va_offset, PAGE_SIZE); 4491 md->pvh_attrs &= ~arm_cache_prefer_mask; 4492 md->pvh_attrs |= (phys & arm_cache_prefer_mask); 4493 #endif 4494 } 4495 bzero_page(vdstp); 4496 if (!okcolor) { 4497 /* 4498 * Unmap the page. 4499 */ 4500 *ptep = 0; 4501 PTE_SYNC(ptep); 4502 cpu_tlb_flushD_SE(cdstp + va_offset); 4503 #ifdef PMAP_CACHE_VIVT 4504 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4505 #endif 4506 } 4507 #ifdef PMAP_CACHE_VIPT 4508 /* 4509 * This page is now cache resident so it now has a page color. 4510 * Any contents have been obliterated so clear the EXEC flag. 4511 */ 4512 if (!pmap_is_page_colored_p(md)) { 4513 PMAPCOUNT(vac_color_new); 4514 md->pvh_attrs |= PVF_COLORED; 4515 } 4516 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4517 md->pvh_attrs &= ~PVF_EXEC; 4518 PMAPCOUNT(exec_discarded_zero); 4519 } 4520 md->pvh_attrs |= PVF_DIRTY; 4521 #endif 4522 } 4523 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4524 4525 #if ARM_MMU_XSCALE == 1 4526 void 4527 pmap_zero_page_xscale(paddr_t phys) 4528 { 4529 #ifdef DEBUG 4530 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4531 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4532 4533 if (!SLIST_EMPTY(&md->pvh_list)) 4534 panic("pmap_zero_page: page has mappings"); 4535 #endif 4536 4537 KDASSERT((phys & PGOFSET) == 0); 4538 4539 /* 4540 * Hook in the page, zero it, and purge the cache for that 4541 * zeroed page. Invalidate the TLB as needed. 4542 */ 4543 *cdst_pte = L2_S_PROTO | phys | 4544 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4545 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4546 PTE_SYNC(cdst_pte); 4547 cpu_tlb_flushD_SE(cdstp); 4548 cpu_cpwait(); 4549 bzero_page(cdstp); 4550 xscale_cache_clean_minidata(); 4551 } 4552 #endif /* ARM_MMU_XSCALE == 1 */ 4553 4554 /* pmap_pageidlezero() 4555 * 4556 * The same as above, except that we assume that the page is not 4557 * mapped. This means we never have to flush the cache first. Called 4558 * from the idle loop. 4559 */ 4560 bool 4561 pmap_pageidlezero(paddr_t phys) 4562 { 4563 unsigned int i; 4564 int *ptr; 4565 bool rv = true; 4566 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4567 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4568 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4569 #endif 4570 #ifdef PMAP_CACHE_VIPT 4571 /* Choose the last page color it had, if any */ 4572 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4573 #else 4574 const vsize_t va_offset = 0; 4575 #endif 4576 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4577 4578 4579 #ifdef DEBUG 4580 if (!SLIST_EMPTY(&md->pvh_list)) 4581 panic("pmap_pageidlezero: page has mappings"); 4582 #endif 4583 4584 KDASSERT((phys & PGOFSET) == 0); 4585 4586 /* 4587 * Hook in the page, zero it, and purge the cache for that 4588 * zeroed page. Invalidate the TLB as needed. 4589 */ 4590 *ptep = L2_S_PROTO | phys | 4591 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4592 PTE_SYNC(ptep); 4593 cpu_tlb_flushD_SE(cdstp + va_offset); 4594 cpu_cpwait(); 4595 4596 for (i = 0, ptr = (int *)(cdstp + va_offset); 4597 i < (PAGE_SIZE / sizeof(int)); i++) { 4598 if (sched_curcpu_runnable_p() != 0) { 4599 /* 4600 * A process has become ready. Abort now, 4601 * so we don't keep it waiting while we 4602 * do slow memory access to finish this 4603 * page. 4604 */ 4605 rv = false; 4606 break; 4607 } 4608 *ptr++ = 0; 4609 } 4610 4611 #ifdef PMAP_CACHE_VIVT 4612 if (rv) 4613 /* 4614 * if we aborted we'll rezero this page again later so don't 4615 * purge it unless we finished it 4616 */ 4617 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4618 #elif defined(PMAP_CACHE_VIPT) 4619 /* 4620 * This page is now cache resident so it now has a page color. 4621 * Any contents have been obliterated so clear the EXEC flag. 4622 */ 4623 if (!pmap_is_page_colored_p(md)) { 4624 PMAPCOUNT(vac_color_new); 4625 md->pvh_attrs |= PVF_COLORED; 4626 } 4627 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4628 md->pvh_attrs &= ~PVF_EXEC; 4629 PMAPCOUNT(exec_discarded_zero); 4630 } 4631 #endif 4632 /* 4633 * Unmap the page. 4634 */ 4635 *ptep = 0; 4636 PTE_SYNC(ptep); 4637 cpu_tlb_flushD_SE(cdstp + va_offset); 4638 4639 return (rv); 4640 } 4641 4642 /* 4643 * pmap_copy_page() 4644 * 4645 * Copy one physical page into another, by mapping the pages into 4646 * hook points. The same comment regarding cachability as in 4647 * pmap_zero_page also applies here. 4648 */ 4649 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4650 void 4651 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4652 { 4653 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4654 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4655 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4656 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4657 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4658 #endif 4659 #ifdef PMAP_CACHE_VIPT 4660 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4661 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4662 #else 4663 const vsize_t src_va_offset = 0; 4664 const vsize_t dst_va_offset = 0; 4665 #endif 4666 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 4667 /* 4668 * Is this page mapped at its natural color? 4669 * If we have all of memory mapped, then just convert PA to VA. 4670 */ 4671 const bool src_okcolor = src_va_offset == (src & arm_cache_prefer_mask); 4672 const bool dst_okcolor = dst_va_offset == (dst & arm_cache_prefer_mask); 4673 const vaddr_t vsrcp = src_okcolor 4674 ? KERNEL_BASE + (src - physical_start) 4675 : csrcp + src_va_offset; 4676 const vaddr_t vdstp = KERNEL_BASE + (dst - physical_start); 4677 #else 4678 const bool src_okcolor = false; 4679 const bool dst_okcolor = false; 4680 const vaddr_t vsrcp = csrcp + src_va_offset; 4681 const vaddr_t vdstp = cdstp + dst_va_offset; 4682 #endif 4683 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4684 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4685 4686 #ifdef DEBUG 4687 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4688 panic("pmap_copy_page: dst page has mappings"); 4689 #endif 4690 4691 #ifdef PMAP_CACHE_VIPT 4692 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4693 #endif 4694 KDASSERT((src & PGOFSET) == 0); 4695 KDASSERT((dst & PGOFSET) == 0); 4696 4697 /* 4698 * Clean the source page. Hold the source page's lock for 4699 * the duration of the copy so that no other mappings can 4700 * be created while we have a potentially aliased mapping. 4701 */ 4702 #ifdef MULTIPROCESSOR 4703 KASSERT(uvm_page_locked_p(src_pg)); 4704 #endif 4705 #ifdef PMAP_CACHE_VIVT 4706 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4707 #endif 4708 4709 /* 4710 * Map the pages into the page hook points, copy them, and purge 4711 * the cache for the appropriate page. Invalidate the TLB 4712 * as required. 4713 */ 4714 if (!src_okcolor) { 4715 *src_ptep = L2_S_PROTO 4716 | src 4717 #ifdef PMAP_CACHE_VIPT 4718 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4719 #endif 4720 #ifdef PMAP_CACHE_VIVT 4721 | pte_l2_s_cache_mode 4722 #endif 4723 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4724 PTE_SYNC(src_ptep); 4725 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4726 cpu_cpwait(); 4727 } 4728 if (!dst_okcolor) { 4729 *dst_ptep = L2_S_PROTO | dst | 4730 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4731 PTE_SYNC(dst_ptep); 4732 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4733 cpu_cpwait(); 4734 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 4735 /* 4736 * If we are direct-mapped and our color isn't ok, then before 4737 * we bcopy to the new page invalidate its contents from the 4738 * cache and reset its color to its natural color. 4739 */ 4740 cpu_dcache_inv_range(cdstp + dst_va_offset, PAGE_SIZE); 4741 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 4742 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 4743 #endif 4744 } 4745 bcopy_page(vsrcp, vdstp); 4746 #ifdef PMAP_CACHE_VIVT 4747 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 4748 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 4749 #endif 4750 /* 4751 * Unmap the pages. 4752 */ 4753 if (!src_okcolor) { 4754 *src_ptep = 0; 4755 PTE_SYNC(src_ptep); 4756 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4757 cpu_cpwait(); 4758 } 4759 if (!dst_okcolor) { 4760 *dst_ptep = 0; 4761 PTE_SYNC(dst_ptep); 4762 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4763 cpu_cpwait(); 4764 } 4765 #ifdef PMAP_CACHE_VIPT 4766 /* 4767 * Now that the destination page is in the cache, mark it as colored. 4768 * If this was an exec page, discard it. 4769 */ 4770 if (!pmap_is_page_colored_p(dst_md)) { 4771 PMAPCOUNT(vac_color_new); 4772 dst_md->pvh_attrs |= PVF_COLORED; 4773 } 4774 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4775 dst_md->pvh_attrs &= ~PVF_EXEC; 4776 PMAPCOUNT(exec_discarded_copy); 4777 } 4778 dst_md->pvh_attrs |= PVF_DIRTY; 4779 #endif 4780 } 4781 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4782 4783 #if ARM_MMU_XSCALE == 1 4784 void 4785 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4786 { 4787 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4788 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4789 #ifdef DEBUG 4790 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4791 4792 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4793 panic("pmap_copy_page: dst page has mappings"); 4794 #endif 4795 4796 KDASSERT((src & PGOFSET) == 0); 4797 KDASSERT((dst & PGOFSET) == 0); 4798 4799 /* 4800 * Clean the source page. Hold the source page's lock for 4801 * the duration of the copy so that no other mappings can 4802 * be created while we have a potentially aliased mapping. 4803 */ 4804 #ifdef MULTIPROCESSOR 4805 KASSERT(uvm_page_locked_p(src_pg)); 4806 #endif 4807 #ifdef PMAP_CACHE_VIVT 4808 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4809 #endif 4810 4811 /* 4812 * Map the pages into the page hook points, copy them, and purge 4813 * the cache for the appropriate page. Invalidate the TLB 4814 * as required. 4815 */ 4816 *csrc_pte = L2_S_PROTO | src | 4817 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4818 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4819 PTE_SYNC(csrc_pte); 4820 *cdst_pte = L2_S_PROTO | dst | 4821 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4822 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4823 PTE_SYNC(cdst_pte); 4824 cpu_tlb_flushD_SE(csrcp); 4825 cpu_tlb_flushD_SE(cdstp); 4826 cpu_cpwait(); 4827 bcopy_page(csrcp, cdstp); 4828 xscale_cache_clean_minidata(); 4829 } 4830 #endif /* ARM_MMU_XSCALE == 1 */ 4831 4832 /* 4833 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4834 * 4835 * Return the start and end addresses of the kernel's virtual space. 4836 * These values are setup in pmap_bootstrap and are updated as pages 4837 * are allocated. 4838 */ 4839 void 4840 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4841 { 4842 *start = virtual_avail; 4843 *end = virtual_end; 4844 } 4845 4846 /* 4847 * Helper function for pmap_grow_l2_bucket() 4848 */ 4849 static inline int 4850 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4851 { 4852 struct l2_bucket *l2b; 4853 pt_entry_t *ptep; 4854 paddr_t pa; 4855 4856 if (uvm.page_init_done == false) { 4857 #ifdef PMAP_STEAL_MEMORY 4858 pv_addr_t pv; 4859 pmap_boot_pagealloc(PAGE_SIZE, 4860 #ifdef PMAP_CACHE_VIPT 4861 arm_cache_prefer_mask, 4862 va & arm_cache_prefer_mask, 4863 #else 4864 0, 0, 4865 #endif 4866 &pv); 4867 pa = pv.pv_pa; 4868 #else 4869 if (uvm_page_physget(&pa) == false) 4870 return (1); 4871 #endif /* PMAP_STEAL_MEMORY */ 4872 } else { 4873 struct vm_page *pg; 4874 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4875 if (pg == NULL) 4876 return (1); 4877 pa = VM_PAGE_TO_PHYS(pg); 4878 #ifdef PMAP_CACHE_VIPT 4879 #ifdef DIAGNOSTIC 4880 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4881 #endif 4882 /* 4883 * This new page must not have any mappings. Enter it via 4884 * pmap_kenter_pa and let that routine do the hard work. 4885 */ 4886 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4887 pmap_kenter_pa(va, pa, 4888 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4889 #endif 4890 } 4891 4892 if (pap) 4893 *pap = pa; 4894 4895 PMAPCOUNT(pt_mappings); 4896 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4897 KDASSERT(l2b != NULL); 4898 4899 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4900 *ptep = L2_S_PROTO | pa | cache_mode | 4901 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4902 PTE_SYNC(ptep); 4903 memset((void *)va, 0, PAGE_SIZE); 4904 return (0); 4905 } 4906 4907 /* 4908 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4909 * used by pmap_growkernel(). 4910 */ 4911 static inline struct l2_bucket * 4912 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4913 { 4914 struct l2_dtable *l2; 4915 struct l2_bucket *l2b; 4916 u_short l1idx; 4917 vaddr_t nva; 4918 4919 l1idx = L1_IDX(va); 4920 4921 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4922 /* 4923 * No mapping at this address, as there is 4924 * no entry in the L1 table. 4925 * Need to allocate a new l2_dtable. 4926 */ 4927 nva = pmap_kernel_l2dtable_kva; 4928 if ((nva & PGOFSET) == 0) { 4929 /* 4930 * Need to allocate a backing page 4931 */ 4932 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4933 return (NULL); 4934 } 4935 4936 l2 = (struct l2_dtable *)nva; 4937 nva += sizeof(struct l2_dtable); 4938 4939 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4940 /* 4941 * The new l2_dtable straddles a page boundary. 4942 * Map in another page to cover it. 4943 */ 4944 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4945 return (NULL); 4946 } 4947 4948 pmap_kernel_l2dtable_kva = nva; 4949 4950 /* 4951 * Link it into the parent pmap 4952 */ 4953 pm->pm_l2[L2_IDX(l1idx)] = l2; 4954 } 4955 4956 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4957 4958 /* 4959 * Fetch pointer to the L2 page table associated with the address. 4960 */ 4961 if (l2b->l2b_kva == NULL) { 4962 pt_entry_t *ptep; 4963 4964 /* 4965 * No L2 page table has been allocated. Chances are, this 4966 * is because we just allocated the l2_dtable, above. 4967 */ 4968 nva = pmap_kernel_l2ptp_kva; 4969 ptep = (pt_entry_t *)nva; 4970 if ((nva & PGOFSET) == 0) { 4971 /* 4972 * Need to allocate a backing page 4973 */ 4974 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4975 &pmap_kernel_l2ptp_phys)) 4976 return (NULL); 4977 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4978 } 4979 4980 l2->l2_occupancy++; 4981 l2b->l2b_kva = ptep; 4982 l2b->l2b_l1idx = l1idx; 4983 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4984 4985 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4986 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4987 } 4988 4989 return (l2b); 4990 } 4991 4992 vaddr_t 4993 pmap_growkernel(vaddr_t maxkvaddr) 4994 { 4995 pmap_t kpm = pmap_kernel(); 4996 struct l1_ttable *l1; 4997 struct l2_bucket *l2b; 4998 pd_entry_t *pl1pd; 4999 int s; 5000 5001 if (maxkvaddr <= pmap_curmaxkvaddr) 5002 goto out; /* we are OK */ 5003 5004 NPDEBUG(PDB_GROWKERN, 5005 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5006 pmap_curmaxkvaddr, maxkvaddr)); 5007 5008 KDASSERT(maxkvaddr <= virtual_end); 5009 5010 /* 5011 * whoops! we need to add kernel PTPs 5012 */ 5013 5014 s = splhigh(); /* to be safe */ 5015 mutex_enter(kpm->pm_lock); 5016 5017 /* Map 1MB at a time */ 5018 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 5019 5020 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5021 KDASSERT(l2b != NULL); 5022 5023 /* Distribute new L1 entry to all other L1s */ 5024 SLIST_FOREACH(l1, &l1_list, l1_link) { 5025 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 5026 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 5027 L1_C_PROTO; 5028 PTE_SYNC(pl1pd); 5029 } 5030 } 5031 5032 /* 5033 * flush out the cache, expensive but growkernel will happen so 5034 * rarely 5035 */ 5036 cpu_dcache_wbinv_all(); 5037 cpu_tlb_flushD(); 5038 cpu_cpwait(); 5039 5040 mutex_exit(kpm->pm_lock); 5041 splx(s); 5042 5043 out: 5044 return (pmap_curmaxkvaddr); 5045 } 5046 5047 /************************ Utility routines ****************************/ 5048 5049 /* 5050 * vector_page_setprot: 5051 * 5052 * Manipulate the protection of the vector page. 5053 */ 5054 void 5055 vector_page_setprot(int prot) 5056 { 5057 struct l2_bucket *l2b; 5058 pt_entry_t *ptep; 5059 5060 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5061 KDASSERT(l2b != NULL); 5062 5063 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5064 5065 *ptep = (*ptep & ~L2_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 5066 PTE_SYNC(ptep); 5067 cpu_tlb_flushD_SE(vector_page); 5068 cpu_cpwait(); 5069 } 5070 5071 /* 5072 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5073 * Returns true if the mapping exists, else false. 5074 * 5075 * NOTE: This function is only used by a couple of arm-specific modules. 5076 * It is not safe to take any pmap locks here, since we could be right 5077 * in the middle of debugging the pmap anyway... 5078 * 5079 * It is possible for this routine to return false even though a valid 5080 * mapping does exist. This is because we don't lock, so the metadata 5081 * state may be inconsistent. 5082 * 5083 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5084 * a "section" mapping. 5085 */ 5086 bool 5087 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5088 { 5089 struct l2_dtable *l2; 5090 pd_entry_t *pl1pd, l1pd; 5091 pt_entry_t *ptep; 5092 u_short l1idx; 5093 5094 if (pm->pm_l1 == NULL) 5095 return false; 5096 5097 l1idx = L1_IDX(va); 5098 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5099 l1pd = *pl1pd; 5100 5101 if (l1pte_section_p(l1pd)) { 5102 *ptp = NULL; 5103 return true; 5104 } 5105 5106 if (pm->pm_l2 == NULL) 5107 return false; 5108 5109 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5110 5111 if (l2 == NULL || 5112 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5113 return false; 5114 } 5115 5116 *ptp = &ptep[l2pte_index(va)]; 5117 return true; 5118 } 5119 5120 bool 5121 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5122 { 5123 u_short l1idx; 5124 5125 if (pm->pm_l1 == NULL) 5126 return false; 5127 5128 l1idx = L1_IDX(va); 5129 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5130 5131 return true; 5132 } 5133 5134 /************************ Bootstrapping routines ****************************/ 5135 5136 static void 5137 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5138 { 5139 int i; 5140 5141 l1->l1_kva = l1pt; 5142 l1->l1_domain_use_count = 0; 5143 l1->l1_domain_first = 0; 5144 5145 for (i = 0; i < PMAP_DOMAINS; i++) 5146 l1->l1_domain_free[i] = i + 1; 5147 5148 /* 5149 * Copy the kernel's L1 entries to each new L1. 5150 */ 5151 if (pmap_initialized) 5152 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5153 5154 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5155 &l1->l1_physaddr) == false) 5156 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5157 5158 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5159 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5160 } 5161 5162 /* 5163 * pmap_bootstrap() is called from the board-specific initarm() routine 5164 * once the kernel L1/L2 descriptors tables have been set up. 5165 * 5166 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5167 * spread over a number of disparate files/functions. 5168 * 5169 * We are passed the following parameters 5170 * - kernel_l1pt 5171 * This is a pointer to the base of the kernel's L1 translation table. 5172 * - vstart 5173 * 1MB-aligned start of managed kernel virtual memory. 5174 * - vend 5175 * 1MB-aligned end of managed kernel virtual memory. 5176 * 5177 * We use the first parameter to build the metadata (struct l1_ttable and 5178 * struct l2_dtable) necessary to track kernel mappings. 5179 */ 5180 #define PMAP_STATIC_L2_SIZE 16 5181 void 5182 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5183 { 5184 static struct l1_ttable static_l1; 5185 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5186 struct l1_ttable *l1 = &static_l1; 5187 struct l2_dtable *l2; 5188 struct l2_bucket *l2b; 5189 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5190 pmap_t pm = pmap_kernel(); 5191 pd_entry_t pde; 5192 pt_entry_t *ptep; 5193 paddr_t pa; 5194 vaddr_t va; 5195 vsize_t size; 5196 int nptes, l1idx, l2idx, l2next = 0; 5197 5198 /* 5199 * Initialise the kernel pmap object 5200 */ 5201 pm->pm_l1 = l1; 5202 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5203 pm->pm_activated = true; 5204 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5205 5206 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5207 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5208 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5209 5210 /* 5211 * Scan the L1 translation table created by initarm() and create 5212 * the required metadata for all valid mappings found in it. 5213 */ 5214 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5215 pde = l1pt[l1idx]; 5216 5217 /* 5218 * We're only interested in Coarse mappings. 5219 * pmap_extract() can deal with section mappings without 5220 * recourse to checking L2 metadata. 5221 */ 5222 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5223 continue; 5224 5225 /* 5226 * Lookup the KVA of this L2 descriptor table 5227 */ 5228 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5229 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5230 if (ptep == NULL) { 5231 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5232 (u_int)l1idx << L1_S_SHIFT, pa); 5233 } 5234 5235 /* 5236 * Fetch the associated L2 metadata structure. 5237 * Allocate a new one if necessary. 5238 */ 5239 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5240 if (l2next == PMAP_STATIC_L2_SIZE) 5241 panic("pmap_bootstrap: out of static L2s"); 5242 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5243 } 5244 5245 /* 5246 * One more L1 slot tracked... 5247 */ 5248 l2->l2_occupancy++; 5249 5250 /* 5251 * Fill in the details of the L2 descriptor in the 5252 * appropriate bucket. 5253 */ 5254 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5255 l2b->l2b_kva = ptep; 5256 l2b->l2b_phys = pa; 5257 l2b->l2b_l1idx = l1idx; 5258 5259 /* 5260 * Establish an initial occupancy count for this descriptor 5261 */ 5262 for (l2idx = 0; 5263 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5264 l2idx++) { 5265 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5266 l2b->l2b_occupancy++; 5267 } 5268 } 5269 5270 /* 5271 * Make sure the descriptor itself has the correct cache mode. 5272 * If not, fix it, but whine about the problem. Port-meisters 5273 * should consider this a clue to fix up their initarm() 5274 * function. :) 5275 */ 5276 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5277 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5278 "L2 pte @ %p\n", ptep); 5279 } 5280 } 5281 5282 /* 5283 * Ensure the primary (kernel) L1 has the correct cache mode for 5284 * a page table. Bitch if it is not correctly set. 5285 */ 5286 for (va = (vaddr_t)l1pt; 5287 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5288 if (pmap_set_pt_cache_mode(l1pt, va)) 5289 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5290 "primary L1 @ 0x%lx\n", va); 5291 } 5292 5293 cpu_dcache_wbinv_all(); 5294 cpu_tlb_flushID(); 5295 cpu_cpwait(); 5296 5297 /* 5298 * now we allocate the "special" VAs which are used for tmp mappings 5299 * by the pmap (and other modules). we allocate the VAs by advancing 5300 * virtual_avail (note that there are no pages mapped at these VAs). 5301 * 5302 * Managed KVM space start from wherever initarm() tells us. 5303 */ 5304 virtual_avail = vstart; 5305 virtual_end = vend; 5306 5307 #ifdef PMAP_CACHE_VIPT 5308 /* 5309 * If we have a VIPT cache, we need one page/pte per possible alias 5310 * page so we won't violate cache aliasing rules. 5311 */ 5312 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5313 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5314 #else 5315 nptes = 1; 5316 #endif 5317 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5318 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5319 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5320 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5321 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5322 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5323 (void *)&msgbufaddr, NULL); 5324 5325 /* 5326 * Allocate a range of kernel virtual address space to be used 5327 * for L2 descriptor tables and metadata allocation in 5328 * pmap_growkernel(). 5329 */ 5330 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5331 pmap_alloc_specials(&virtual_avail, 5332 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5333 &pmap_kernel_l2ptp_kva, NULL); 5334 5335 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5336 pmap_alloc_specials(&virtual_avail, 5337 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5338 &pmap_kernel_l2dtable_kva, NULL); 5339 5340 /* 5341 * init the static-global locks and global pmap list. 5342 */ 5343 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 5344 5345 /* 5346 * We can now initialise the first L1's metadata. 5347 */ 5348 SLIST_INIT(&l1_list); 5349 TAILQ_INIT(&l1_lru_list); 5350 pmap_init_l1(l1, l1pt); 5351 5352 /* Set up vector page L1 details, if necessary */ 5353 if (vector_page < KERNEL_BASE) { 5354 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5355 l2b = pmap_get_l2_bucket(pm, vector_page); 5356 KDASSERT(l2b != NULL); 5357 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5358 L1_C_DOM(pm->pm_domain); 5359 } else 5360 pm->pm_pl1vec = NULL; 5361 5362 /* 5363 * Initialize the pmap cache 5364 */ 5365 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5366 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5367 LIST_INIT(&pmap_pmaps); 5368 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5369 5370 /* 5371 * Initialize the pv pool. 5372 */ 5373 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5374 &pmap_bootstrap_pv_allocator, IPL_NONE); 5375 5376 /* 5377 * Initialize the L2 dtable pool and cache. 5378 */ 5379 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5380 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5381 5382 /* 5383 * Initialise the L2 descriptor table pool and cache 5384 */ 5385 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5386 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5387 pmap_l2ptp_ctor, NULL, NULL); 5388 5389 cpu_dcache_wbinv_all(); 5390 } 5391 5392 static int 5393 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5394 { 5395 pd_entry_t *pdep, pde; 5396 pt_entry_t *ptep, pte; 5397 vaddr_t pa; 5398 int rv = 0; 5399 5400 /* 5401 * Make sure the descriptor itself has the correct cache mode 5402 */ 5403 pdep = &kl1[L1_IDX(va)]; 5404 pde = *pdep; 5405 5406 if (l1pte_section_p(pde)) { 5407 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 5408 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5409 *pdep = (pde & ~L1_S_CACHE_MASK) | 5410 pte_l1_s_cache_mode_pt; 5411 PTE_SYNC(pdep); 5412 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5413 rv = 1; 5414 } 5415 } else { 5416 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5417 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5418 if (ptep == NULL) 5419 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5420 5421 ptep = &ptep[l2pte_index(va)]; 5422 pte = *ptep; 5423 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5424 *ptep = (pte & ~L2_S_CACHE_MASK) | 5425 pte_l2_s_cache_mode_pt; 5426 PTE_SYNC(ptep); 5427 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5428 rv = 1; 5429 } 5430 } 5431 5432 return (rv); 5433 } 5434 5435 static void 5436 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5437 { 5438 vaddr_t va = *availp; 5439 struct l2_bucket *l2b; 5440 5441 if (ptep) { 5442 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5443 if (l2b == NULL) 5444 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5445 5446 if (ptep) 5447 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5448 } 5449 5450 *vap = va; 5451 *availp = va + (PAGE_SIZE * pages); 5452 } 5453 5454 void 5455 pmap_init(void) 5456 { 5457 5458 /* 5459 * Set the available memory vars - These do not map to real memory 5460 * addresses and cannot as the physical memory is fragmented. 5461 * They are used by ps for %mem calculations. 5462 * One could argue whether this should be the entire memory or just 5463 * the memory that is useable in a user process. 5464 */ 5465 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5466 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5467 5468 /* 5469 * Now we need to free enough pv_entry structures to allow us to get 5470 * the kmem_map/kmem_object allocated and inited (done after this 5471 * function is finished). to do this we allocate one bootstrap page out 5472 * of kernel_map and use it to provide an initial pool of pv_entry 5473 * structures. we never free this page. 5474 */ 5475 pool_setlowat(&pmap_pv_pool, 5476 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5477 5478 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5479 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5480 UVM_KMF_WIRED|UVM_KMF_ZERO); 5481 5482 pmap_initialized = true; 5483 } 5484 5485 static vaddr_t last_bootstrap_page = 0; 5486 static void *free_bootstrap_pages = NULL; 5487 5488 static void * 5489 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5490 { 5491 extern void *pool_page_alloc(struct pool *, int); 5492 vaddr_t new_page; 5493 void *rv; 5494 5495 if (pmap_initialized) 5496 return (pool_page_alloc(pp, flags)); 5497 5498 if (free_bootstrap_pages) { 5499 rv = free_bootstrap_pages; 5500 free_bootstrap_pages = *((void **)rv); 5501 return (rv); 5502 } 5503 5504 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5505 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5506 5507 KASSERT(new_page > last_bootstrap_page); 5508 last_bootstrap_page = new_page; 5509 return ((void *)new_page); 5510 } 5511 5512 static void 5513 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5514 { 5515 extern void pool_page_free(struct pool *, void *); 5516 5517 if ((vaddr_t)v <= last_bootstrap_page) { 5518 *((void **)v) = free_bootstrap_pages; 5519 free_bootstrap_pages = v; 5520 return; 5521 } 5522 5523 if (pmap_initialized) { 5524 pool_page_free(pp, v); 5525 return; 5526 } 5527 } 5528 5529 /* 5530 * pmap_postinit() 5531 * 5532 * This routine is called after the vm and kmem subsystems have been 5533 * initialised. This allows the pmap code to perform any initialisation 5534 * that can only be done one the memory allocation is in place. 5535 */ 5536 void 5537 pmap_postinit(void) 5538 { 5539 extern paddr_t physical_start, physical_end; 5540 struct l2_bucket *l2b; 5541 struct l1_ttable *l1; 5542 struct pglist plist; 5543 struct vm_page *m; 5544 pd_entry_t *pl1pt; 5545 pt_entry_t *ptep, pte; 5546 vaddr_t va, eva; 5547 u_int loop, needed; 5548 int error; 5549 5550 pool_cache_setlowat(&pmap_l2ptp_cache, 5551 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5552 pool_cache_setlowat(&pmap_l2dtable_cache, 5553 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5554 5555 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5556 needed -= 1; 5557 5558 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 5559 5560 for (loop = 0; loop < needed; loop++, l1++) { 5561 /* Allocate a L1 page table */ 5562 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5563 if (va == 0) 5564 panic("Cannot allocate L1 KVM"); 5565 5566 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5567 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 5568 if (error) 5569 panic("Cannot allocate L1 physical pages"); 5570 5571 m = TAILQ_FIRST(&plist); 5572 eva = va + L1_TABLE_SIZE; 5573 pl1pt = (pd_entry_t *)va; 5574 5575 while (m && va < eva) { 5576 paddr_t pa = VM_PAGE_TO_PHYS(m); 5577 5578 pmap_kenter_pa(va, pa, 5579 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5580 5581 /* 5582 * Make sure the L1 descriptor table is mapped 5583 * with the cache-mode set to write-through. 5584 */ 5585 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5586 KDASSERT(l2b != NULL); 5587 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5588 pte = *ptep; 5589 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5590 *ptep = pte; 5591 PTE_SYNC(ptep); 5592 cpu_tlb_flushD_SE(va); 5593 5594 va += PAGE_SIZE; 5595 m = TAILQ_NEXT(m, pageq.queue); 5596 } 5597 5598 #ifdef DIAGNOSTIC 5599 if (m) 5600 panic("pmap_alloc_l1pt: pglist not empty"); 5601 #endif /* DIAGNOSTIC */ 5602 5603 pmap_init_l1(l1, pl1pt); 5604 } 5605 5606 #ifdef DEBUG 5607 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5608 needed); 5609 #endif 5610 } 5611 5612 /* 5613 * Note that the following routines are used by board-specific initialisation 5614 * code to configure the initial kernel page tables. 5615 * 5616 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5617 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5618 * behaviour of the old pmap, and provides an easy migration path for 5619 * initial bring-up of the new pmap on existing ports. Fortunately, 5620 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5621 * will be deprecated. 5622 * 5623 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5624 * tables. 5625 */ 5626 5627 /* 5628 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5629 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5630 * find them as necessary. 5631 * 5632 * Note that the data on this list MUST remain valid after initarm() returns, 5633 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5634 */ 5635 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5636 5637 static vaddr_t 5638 kernel_pt_lookup(paddr_t pa) 5639 { 5640 pv_addr_t *pv; 5641 5642 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5643 #ifndef ARM32_NEW_VM_LAYOUT 5644 if (pv->pv_pa == (pa & ~PGOFSET)) 5645 return (pv->pv_va | (pa & PGOFSET)); 5646 #else 5647 if (pv->pv_pa == pa) 5648 return (pv->pv_va); 5649 #endif 5650 } 5651 return (0); 5652 } 5653 5654 /* 5655 * pmap_map_section: 5656 * 5657 * Create a single section mapping. 5658 */ 5659 void 5660 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5661 { 5662 pd_entry_t *pde = (pd_entry_t *) l1pt; 5663 pd_entry_t fl; 5664 5665 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5666 5667 switch (cache) { 5668 case PTE_NOCACHE: 5669 default: 5670 fl = 0; 5671 break; 5672 5673 case PTE_CACHE: 5674 fl = pte_l1_s_cache_mode; 5675 break; 5676 5677 case PTE_PAGETABLE: 5678 fl = pte_l1_s_cache_mode_pt; 5679 break; 5680 } 5681 5682 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5683 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5684 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5685 } 5686 5687 /* 5688 * pmap_map_entry: 5689 * 5690 * Create a single page mapping. 5691 */ 5692 void 5693 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5694 { 5695 pd_entry_t *pde = (pd_entry_t *) l1pt; 5696 pt_entry_t fl; 5697 pt_entry_t *pte; 5698 5699 KASSERT(((va | pa) & PGOFSET) == 0); 5700 5701 switch (cache) { 5702 case PTE_NOCACHE: 5703 default: 5704 fl = 0; 5705 break; 5706 5707 case PTE_CACHE: 5708 fl = pte_l2_s_cache_mode; 5709 break; 5710 5711 case PTE_PAGETABLE: 5712 fl = pte_l2_s_cache_mode_pt; 5713 break; 5714 } 5715 5716 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5717 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5718 5719 #ifndef ARM32_NEW_VM_LAYOUT 5720 pte = (pt_entry_t *) 5721 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5722 #else 5723 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5724 #endif 5725 if (pte == NULL) 5726 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5727 5728 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5729 #ifndef ARM32_NEW_VM_LAYOUT 5730 pte += (va >> PGSHIFT) & 0x3ff; 5731 #else 5732 pte += l2pte_index(va); 5733 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5734 #endif 5735 *pte = fl; 5736 PTE_SYNC(pte); 5737 } 5738 5739 /* 5740 * pmap_link_l2pt: 5741 * 5742 * Link the L2 page table specified by "l2pv" into the L1 5743 * page table at the slot for "va". 5744 */ 5745 void 5746 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5747 { 5748 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5749 u_int slot = va >> L1_S_SHIFT; 5750 5751 #ifndef ARM32_NEW_VM_LAYOUT 5752 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5753 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5754 #endif 5755 5756 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5757 5758 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5759 #ifdef ARM32_NEW_VM_LAYOUT 5760 PTE_SYNC(&pde[slot]); 5761 #else 5762 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5763 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5764 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5765 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5766 #endif 5767 5768 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5769 } 5770 5771 /* 5772 * pmap_map_chunk: 5773 * 5774 * Map a chunk of memory using the most efficient mappings 5775 * possible (section, large page, small page) into the 5776 * provided L1 and L2 tables at the specified virtual address. 5777 */ 5778 vsize_t 5779 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5780 int prot, int cache) 5781 { 5782 pd_entry_t *pdep = (pd_entry_t *) l1pt; 5783 pt_entry_t *pte, f1, f2s, f2l; 5784 vsize_t resid; 5785 int i; 5786 5787 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5788 5789 if (l1pt == 0) 5790 panic("pmap_map_chunk: no L1 table provided"); 5791 5792 #ifdef VERBOSE_INIT_ARM 5793 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5794 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5795 #endif 5796 5797 switch (cache) { 5798 case PTE_NOCACHE: 5799 default: 5800 f1 = 0; 5801 f2l = 0; 5802 f2s = 0; 5803 break; 5804 5805 case PTE_CACHE: 5806 f1 = pte_l1_s_cache_mode; 5807 f2l = pte_l2_l_cache_mode; 5808 f2s = pte_l2_s_cache_mode; 5809 break; 5810 5811 case PTE_PAGETABLE: 5812 f1 = pte_l1_s_cache_mode_pt; 5813 f2l = pte_l2_l_cache_mode_pt; 5814 f2s = pte_l2_s_cache_mode_pt; 5815 break; 5816 } 5817 5818 size = resid; 5819 5820 while (resid > 0) { 5821 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5822 /* See if we can use a supersection mapping. */ 5823 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 5824 /* Supersection are always domain 0 */ 5825 pd_entry_t pde = L1_SS_PROTO | pa | 5826 L1_S_PROT(PTE_KERNEL, prot) | f1; 5827 #ifdef VERBOSE_INIT_ARM 5828 printf("sS"); 5829 #endif 5830 for (size_t s = va >> L1_S_SHIFT, 5831 e = s + L1_SS_SIZE / L1_S_SIZE; 5832 s < e; 5833 s++) { 5834 pdep[s] = pde; 5835 PTE_SYNC(&pdep[s]); 5836 } 5837 va += L1_SS_SIZE; 5838 pa += L1_SS_SIZE; 5839 resid -= L1_SS_SIZE; 5840 continue; 5841 } 5842 #endif 5843 /* See if we can use a section mapping. */ 5844 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5845 #ifdef VERBOSE_INIT_ARM 5846 printf("S"); 5847 #endif 5848 pdep[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5849 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5850 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5851 PTE_SYNC(&pdep[va >> L1_S_SHIFT]); 5852 va += L1_S_SIZE; 5853 pa += L1_S_SIZE; 5854 resid -= L1_S_SIZE; 5855 continue; 5856 } 5857 5858 /* 5859 * Ok, we're going to use an L2 table. Make sure 5860 * one is actually in the corresponding L1 slot 5861 * for the current VA. 5862 */ 5863 if ((pdep[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5864 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5865 5866 #ifndef ARM32_NEW_VM_LAYOUT 5867 pte = (pt_entry_t *) 5868 kernel_pt_lookup(pdep[va >> L1_S_SHIFT] & L2_S_FRAME); 5869 #else 5870 pte = (pt_entry_t *) kernel_pt_lookup( 5871 pdep[L1_IDX(va)] & L1_C_ADDR_MASK); 5872 #endif 5873 if (pte == NULL) 5874 panic("pmap_map_chunk: can't find L2 table for VA" 5875 "0x%08lx", va); 5876 5877 /* See if we can use a L2 large page mapping. */ 5878 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5879 #ifdef VERBOSE_INIT_ARM 5880 printf("L"); 5881 #endif 5882 for (i = 0; i < 16; i++) { 5883 #ifndef ARM32_NEW_VM_LAYOUT 5884 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5885 L2_L_PROTO | pa | 5886 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5887 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5888 #else 5889 pte[l2pte_index(va) + i] = 5890 L2_L_PROTO | pa | 5891 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5892 PTE_SYNC(&pte[l2pte_index(va) + i]); 5893 #endif 5894 } 5895 va += L2_L_SIZE; 5896 pa += L2_L_SIZE; 5897 resid -= L2_L_SIZE; 5898 continue; 5899 } 5900 5901 /* Use a small page mapping. */ 5902 #ifdef VERBOSE_INIT_ARM 5903 printf("P"); 5904 #endif 5905 #ifndef ARM32_NEW_VM_LAYOUT 5906 pte[(va >> PGSHIFT) & 0x3ff] = 5907 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5908 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5909 #else 5910 pte[l2pte_index(va)] = 5911 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5912 PTE_SYNC(&pte[l2pte_index(va)]); 5913 #endif 5914 va += PAGE_SIZE; 5915 pa += PAGE_SIZE; 5916 resid -= PAGE_SIZE; 5917 } 5918 #ifdef VERBOSE_INIT_ARM 5919 printf("\n"); 5920 #endif 5921 return (size); 5922 } 5923 5924 /********************** Static device map routines ***************************/ 5925 5926 static const struct pmap_devmap *pmap_devmap_table; 5927 5928 /* 5929 * Register the devmap table. This is provided in case early console 5930 * initialization needs to register mappings created by bootstrap code 5931 * before pmap_devmap_bootstrap() is called. 5932 */ 5933 void 5934 pmap_devmap_register(const struct pmap_devmap *table) 5935 { 5936 5937 pmap_devmap_table = table; 5938 } 5939 5940 /* 5941 * Map all of the static regions in the devmap table, and remember 5942 * the devmap table so other parts of the kernel can look up entries 5943 * later. 5944 */ 5945 void 5946 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5947 { 5948 int i; 5949 5950 pmap_devmap_table = table; 5951 5952 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5953 #ifdef VERBOSE_INIT_ARM 5954 printf("devmap: %08lx -> %08lx @ %08lx\n", 5955 pmap_devmap_table[i].pd_pa, 5956 pmap_devmap_table[i].pd_pa + 5957 pmap_devmap_table[i].pd_size - 1, 5958 pmap_devmap_table[i].pd_va); 5959 #endif 5960 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5961 pmap_devmap_table[i].pd_pa, 5962 pmap_devmap_table[i].pd_size, 5963 pmap_devmap_table[i].pd_prot, 5964 pmap_devmap_table[i].pd_cache); 5965 } 5966 } 5967 5968 const struct pmap_devmap * 5969 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5970 { 5971 uint64_t endpa; 5972 int i; 5973 5974 if (pmap_devmap_table == NULL) 5975 return (NULL); 5976 5977 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5978 5979 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5980 if (pa >= pmap_devmap_table[i].pd_pa && 5981 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5982 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5983 return (&pmap_devmap_table[i]); 5984 } 5985 5986 return (NULL); 5987 } 5988 5989 const struct pmap_devmap * 5990 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5991 { 5992 int i; 5993 5994 if (pmap_devmap_table == NULL) 5995 return (NULL); 5996 5997 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5998 if (va >= pmap_devmap_table[i].pd_va && 5999 va + size - 1 <= pmap_devmap_table[i].pd_va + 6000 pmap_devmap_table[i].pd_size - 1) 6001 return (&pmap_devmap_table[i]); 6002 } 6003 6004 return (NULL); 6005 } 6006 6007 /********************** PTE initialization routines **************************/ 6008 6009 /* 6010 * These routines are called when the CPU type is identified to set up 6011 * the PTE prototypes, cache modes, etc. 6012 * 6013 * The variables are always here, just in case modules need to reference 6014 * them (though, they shouldn't). 6015 */ 6016 6017 pt_entry_t pte_l1_s_cache_mode; 6018 pt_entry_t pte_l1_s_wc_mode; 6019 pt_entry_t pte_l1_s_cache_mode_pt; 6020 pt_entry_t pte_l1_s_cache_mask; 6021 6022 pt_entry_t pte_l2_l_cache_mode; 6023 pt_entry_t pte_l2_l_wc_mode; 6024 pt_entry_t pte_l2_l_cache_mode_pt; 6025 pt_entry_t pte_l2_l_cache_mask; 6026 6027 pt_entry_t pte_l2_s_cache_mode; 6028 pt_entry_t pte_l2_s_wc_mode; 6029 pt_entry_t pte_l2_s_cache_mode_pt; 6030 pt_entry_t pte_l2_s_cache_mask; 6031 6032 pt_entry_t pte_l1_s_prot_u; 6033 pt_entry_t pte_l1_s_prot_w; 6034 pt_entry_t pte_l1_s_prot_ro; 6035 pt_entry_t pte_l1_s_prot_mask; 6036 6037 pt_entry_t pte_l2_s_prot_u; 6038 pt_entry_t pte_l2_s_prot_w; 6039 pt_entry_t pte_l2_s_prot_ro; 6040 pt_entry_t pte_l2_s_prot_mask; 6041 6042 pt_entry_t pte_l2_l_prot_u; 6043 pt_entry_t pte_l2_l_prot_w; 6044 pt_entry_t pte_l2_l_prot_ro; 6045 pt_entry_t pte_l2_l_prot_mask; 6046 6047 pt_entry_t pte_l1_ss_proto; 6048 pt_entry_t pte_l1_s_proto; 6049 pt_entry_t pte_l1_c_proto; 6050 pt_entry_t pte_l2_s_proto; 6051 6052 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6053 void (*pmap_zero_page_func)(paddr_t); 6054 6055 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6056 void 6057 pmap_pte_init_generic(void) 6058 { 6059 6060 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6061 pte_l1_s_wc_mode = L1_S_B; 6062 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6063 6064 pte_l2_l_cache_mode = L2_B|L2_C; 6065 pte_l2_l_wc_mode = L2_B; 6066 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6067 6068 pte_l2_s_cache_mode = L2_B|L2_C; 6069 pte_l2_s_wc_mode = L2_B; 6070 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6071 6072 /* 6073 * If we have a write-through cache, set B and C. If 6074 * we have a write-back cache, then we assume setting 6075 * only C will make those pages write-through (except for those 6076 * Cortex CPUs which can read the L1 caches). 6077 */ 6078 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6079 #if ARM_MMU_V7 > 0 6080 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6081 #endif 6082 #if ARM_MMU_V6 > 0 6083 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6084 #endif 6085 || false) { 6086 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6087 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6088 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6089 } else { 6090 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6091 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6092 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6093 } 6094 6095 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6096 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6097 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6098 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6099 6100 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6101 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6102 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6103 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6104 6105 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6106 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6107 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6108 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6109 6110 pte_l1_ss_proto = L1_SS_PROTO_generic; 6111 pte_l1_s_proto = L1_S_PROTO_generic; 6112 pte_l1_c_proto = L1_C_PROTO_generic; 6113 pte_l2_s_proto = L2_S_PROTO_generic; 6114 6115 pmap_copy_page_func = pmap_copy_page_generic; 6116 pmap_zero_page_func = pmap_zero_page_generic; 6117 } 6118 6119 #if defined(CPU_ARM8) 6120 void 6121 pmap_pte_init_arm8(void) 6122 { 6123 6124 /* 6125 * ARM8 is compatible with generic, but we need to use 6126 * the page tables uncached. 6127 */ 6128 pmap_pte_init_generic(); 6129 6130 pte_l1_s_cache_mode_pt = 0; 6131 pte_l2_l_cache_mode_pt = 0; 6132 pte_l2_s_cache_mode_pt = 0; 6133 } 6134 #endif /* CPU_ARM8 */ 6135 6136 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6137 void 6138 pmap_pte_init_arm9(void) 6139 { 6140 6141 /* 6142 * ARM9 is compatible with generic, but we want to use 6143 * write-through caching for now. 6144 */ 6145 pmap_pte_init_generic(); 6146 6147 pte_l1_s_cache_mode = L1_S_C; 6148 pte_l2_l_cache_mode = L2_C; 6149 pte_l2_s_cache_mode = L2_C; 6150 6151 pte_l1_s_wc_mode = L1_S_B; 6152 pte_l2_l_wc_mode = L2_B; 6153 pte_l2_s_wc_mode = L2_B; 6154 6155 pte_l1_s_cache_mode_pt = L1_S_C; 6156 pte_l2_l_cache_mode_pt = L2_C; 6157 pte_l2_s_cache_mode_pt = L2_C; 6158 } 6159 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6160 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6161 6162 #if defined(CPU_ARM10) 6163 void 6164 pmap_pte_init_arm10(void) 6165 { 6166 6167 /* 6168 * ARM10 is compatible with generic, but we want to use 6169 * write-through caching for now. 6170 */ 6171 pmap_pte_init_generic(); 6172 6173 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6174 pte_l2_l_cache_mode = L2_B | L2_C; 6175 pte_l2_s_cache_mode = L2_B | L2_C; 6176 6177 pte_l1_s_cache_mode = L1_S_B; 6178 pte_l2_l_cache_mode = L2_B; 6179 pte_l2_s_cache_mode = L2_B; 6180 6181 pte_l1_s_cache_mode_pt = L1_S_C; 6182 pte_l2_l_cache_mode_pt = L2_C; 6183 pte_l2_s_cache_mode_pt = L2_C; 6184 6185 } 6186 #endif /* CPU_ARM10 */ 6187 6188 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6189 void 6190 pmap_pte_init_arm11(void) 6191 { 6192 6193 /* 6194 * ARM11 is compatible with generic, but we want to use 6195 * write-through caching for now. 6196 */ 6197 pmap_pte_init_generic(); 6198 6199 pte_l1_s_cache_mode = L1_S_C; 6200 pte_l2_l_cache_mode = L2_C; 6201 pte_l2_s_cache_mode = L2_C; 6202 6203 pte_l1_s_wc_mode = L1_S_B; 6204 pte_l2_l_wc_mode = L2_B; 6205 pte_l2_s_wc_mode = L2_B; 6206 6207 pte_l1_s_cache_mode_pt = L1_S_C; 6208 pte_l2_l_cache_mode_pt = L2_C; 6209 pte_l2_s_cache_mode_pt = L2_C; 6210 } 6211 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6212 6213 #if ARM_MMU_SA1 == 1 6214 void 6215 pmap_pte_init_sa1(void) 6216 { 6217 6218 /* 6219 * The StrongARM SA-1 cache does not have a write-through 6220 * mode. So, do the generic initialization, then reset 6221 * the page table cache mode to B=1,C=1, and note that 6222 * the PTEs need to be sync'd. 6223 */ 6224 pmap_pte_init_generic(); 6225 6226 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6227 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6228 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6229 6230 pmap_needs_pte_sync = 1; 6231 } 6232 #endif /* ARM_MMU_SA1 == 1*/ 6233 6234 #if ARM_MMU_XSCALE == 1 6235 #if (ARM_NMMUS > 1) 6236 static u_int xscale_use_minidata; 6237 #endif 6238 6239 void 6240 pmap_pte_init_xscale(void) 6241 { 6242 uint32_t auxctl; 6243 int write_through = 0; 6244 6245 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6246 pte_l1_s_wc_mode = L1_S_B; 6247 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6248 6249 pte_l2_l_cache_mode = L2_B|L2_C; 6250 pte_l2_l_wc_mode = L2_B; 6251 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6252 6253 pte_l2_s_cache_mode = L2_B|L2_C; 6254 pte_l2_s_wc_mode = L2_B; 6255 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6256 6257 pte_l1_s_cache_mode_pt = L1_S_C; 6258 pte_l2_l_cache_mode_pt = L2_C; 6259 pte_l2_s_cache_mode_pt = L2_C; 6260 6261 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6262 /* 6263 * The XScale core has an enhanced mode where writes that 6264 * miss the cache cause a cache line to be allocated. This 6265 * is significantly faster than the traditional, write-through 6266 * behavior of this case. 6267 */ 6268 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6269 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6270 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6271 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6272 6273 #ifdef XSCALE_CACHE_WRITE_THROUGH 6274 /* 6275 * Some versions of the XScale core have various bugs in 6276 * their cache units, the work-around for which is to run 6277 * the cache in write-through mode. Unfortunately, this 6278 * has a major (negative) impact on performance. So, we 6279 * go ahead and run fast-and-loose, in the hopes that we 6280 * don't line up the planets in a way that will trip the 6281 * bugs. 6282 * 6283 * However, we give you the option to be slow-but-correct. 6284 */ 6285 write_through = 1; 6286 #elif defined(XSCALE_CACHE_WRITE_BACK) 6287 /* force write back cache mode */ 6288 write_through = 0; 6289 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6290 /* 6291 * Intel PXA2[15]0 processors are known to have a bug in 6292 * write-back cache on revision 4 and earlier (stepping 6293 * A[01] and B[012]). Fixed for C0 and later. 6294 */ 6295 { 6296 uint32_t id, type; 6297 6298 id = cpufunc_id(); 6299 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6300 6301 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6302 if ((id & CPU_ID_REVISION_MASK) < 5) { 6303 /* write through for stepping A0-1 and B0-2 */ 6304 write_through = 1; 6305 } 6306 } 6307 } 6308 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6309 6310 if (write_through) { 6311 pte_l1_s_cache_mode = L1_S_C; 6312 pte_l2_l_cache_mode = L2_C; 6313 pte_l2_s_cache_mode = L2_C; 6314 } 6315 6316 #if (ARM_NMMUS > 1) 6317 xscale_use_minidata = 1; 6318 #endif 6319 6320 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6321 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6322 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6323 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6324 6325 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6326 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6327 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6328 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6329 6330 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6331 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6332 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6333 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6334 6335 pte_l1_ss_proto = L1_SS_PROTO_xscale; 6336 pte_l1_s_proto = L1_S_PROTO_xscale; 6337 pte_l1_c_proto = L1_C_PROTO_xscale; 6338 pte_l2_s_proto = L2_S_PROTO_xscale; 6339 6340 pmap_copy_page_func = pmap_copy_page_xscale; 6341 pmap_zero_page_func = pmap_zero_page_xscale; 6342 6343 /* 6344 * Disable ECC protection of page table access, for now. 6345 */ 6346 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6347 auxctl &= ~XSCALE_AUXCTL_P; 6348 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6349 } 6350 6351 /* 6352 * xscale_setup_minidata: 6353 * 6354 * Set up the mini-data cache clean area. We require the 6355 * caller to allocate the right amount of physically and 6356 * virtually contiguous space. 6357 */ 6358 void 6359 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6360 { 6361 extern vaddr_t xscale_minidata_clean_addr; 6362 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6363 pd_entry_t *pde = (pd_entry_t *) l1pt; 6364 pt_entry_t *pte; 6365 vsize_t size; 6366 uint32_t auxctl; 6367 6368 xscale_minidata_clean_addr = va; 6369 6370 /* Round it to page size. */ 6371 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6372 6373 for (; size != 0; 6374 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6375 #ifndef ARM32_NEW_VM_LAYOUT 6376 pte = (pt_entry_t *) 6377 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6378 #else 6379 pte = (pt_entry_t *) kernel_pt_lookup( 6380 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6381 #endif 6382 if (pte == NULL) 6383 panic("xscale_setup_minidata: can't find L2 table for " 6384 "VA 0x%08lx", va); 6385 #ifndef ARM32_NEW_VM_LAYOUT 6386 pte[(va >> PGSHIFT) & 0x3ff] = 6387 #else 6388 pte[l2pte_index(va)] = 6389 #endif 6390 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6391 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6392 } 6393 6394 /* 6395 * Configure the mini-data cache for write-back with 6396 * read/write-allocate. 6397 * 6398 * NOTE: In order to reconfigure the mini-data cache, we must 6399 * make sure it contains no valid data! In order to do that, 6400 * we must issue a global data cache invalidate command! 6401 * 6402 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6403 * THIS IS VERY IMPORTANT! 6404 */ 6405 6406 /* Invalidate data and mini-data. */ 6407 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6408 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6409 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6410 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6411 } 6412 6413 /* 6414 * Change the PTEs for the specified kernel mappings such that they 6415 * will use the mini data cache instead of the main data cache. 6416 */ 6417 void 6418 pmap_uarea(vaddr_t va) 6419 { 6420 struct l2_bucket *l2b; 6421 pt_entry_t *ptep, *sptep, pte; 6422 vaddr_t next_bucket, eva; 6423 6424 #if (ARM_NMMUS > 1) 6425 if (xscale_use_minidata == 0) 6426 return; 6427 #endif 6428 6429 eva = va + USPACE; 6430 6431 while (va < eva) { 6432 next_bucket = L2_NEXT_BUCKET(va); 6433 if (next_bucket > eva) 6434 next_bucket = eva; 6435 6436 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6437 KDASSERT(l2b != NULL); 6438 6439 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6440 6441 while (va < next_bucket) { 6442 pte = *ptep; 6443 if (!l2pte_minidata(pte)) { 6444 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6445 cpu_tlb_flushD_SE(va); 6446 *ptep = pte & ~L2_B; 6447 } 6448 ptep++; 6449 va += PAGE_SIZE; 6450 } 6451 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6452 } 6453 cpu_cpwait(); 6454 } 6455 #endif /* ARM_MMU_XSCALE == 1 */ 6456 6457 6458 #if defined(CPU_ARM11MPCORE) 6459 6460 void 6461 pmap_pte_init_arm11mpcore(void) 6462 { 6463 6464 /* cache mode is controlled by 5 bits (B, C, TEX) */ 6465 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 6466 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 6467 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6468 /* use extended small page (without APn, with TEX) */ 6469 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 6470 #else 6471 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 6472 #endif 6473 6474 /* write-back, write-allocate */ 6475 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6476 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 6477 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6478 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6479 #else 6480 /* no TEX. read-allocate */ 6481 pte_l2_s_cache_mode = L2_C | L2_B; 6482 #endif 6483 /* 6484 * write-back, write-allocate for page tables. 6485 */ 6486 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6487 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 6488 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6489 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6490 #else 6491 pte_l2_s_cache_mode_pt = L2_C | L2_B; 6492 #endif 6493 6494 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 6495 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 6496 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 6497 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 6498 6499 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6500 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 6501 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 6502 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 6503 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 6504 6505 #else 6506 /* with AP[0..3] */ 6507 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6508 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6509 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6510 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6511 #endif 6512 6513 #ifdef ARM11MPCORE_COMPAT_MMU 6514 /* with AP[0..3] */ 6515 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6516 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6517 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6518 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6519 6520 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6521 pte_l1_s_proto = L1_S_PROTO_armv6; 6522 pte_l1_c_proto = L1_C_PROTO_armv6; 6523 pte_l2_s_proto = L2_S_PROTO_armv6c; 6524 #else 6525 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 6526 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 6527 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 6528 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 6529 6530 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6531 pte_l1_s_proto = L1_S_PROTO_armv6; 6532 pte_l1_c_proto = L1_C_PROTO_armv6; 6533 pte_l2_s_proto = L2_S_PROTO_armv6n; 6534 #endif 6535 6536 pmap_copy_page_func = pmap_copy_page_generic; 6537 pmap_zero_page_func = pmap_zero_page_generic; 6538 pmap_needs_pte_sync = 1; 6539 } 6540 #endif /* CPU_ARM11MPCORE */ 6541 6542 6543 #if ARM_MMU_V7 == 1 6544 void 6545 pmap_pte_init_armv7(void) 6546 { 6547 /* 6548 * The ARMv7-A MMU is mostly compatible with generic. If the 6549 * AP field is zero, that now means "no access" rather than 6550 * read-only. The prototypes are a little different because of 6551 * the XN bit. 6552 */ 6553 pmap_pte_init_generic(); 6554 6555 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6556 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6557 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6558 6559 if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) { 6560 /* 6561 * write-back, no write-allocate, shareable for normal pages. 6562 */ 6563 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_S; 6564 pte_l2_l_cache_mode = L2_C | L2_B | L2_XS_S; 6565 pte_l2_s_cache_mode = L2_C | L2_B | L2_XS_S; 6566 6567 /* 6568 * write-back, no write-allocate, shareable for page tables. 6569 */ 6570 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_S; 6571 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6572 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6573 } 6574 6575 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6576 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6577 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6578 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6579 6580 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6581 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6582 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6583 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6584 6585 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6586 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6587 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6588 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6589 6590 pte_l1_ss_proto = L1_SS_PROTO_armv7; 6591 pte_l1_s_proto = L1_S_PROTO_armv7; 6592 pte_l1_c_proto = L1_C_PROTO_armv7; 6593 pte_l2_s_proto = L2_S_PROTO_armv7; 6594 6595 pmap_needs_pte_sync = 1; 6596 } 6597 #endif /* ARM_MMU_V7 */ 6598 6599 /* 6600 * return the PA of the current L1 table, for use when handling a crash dump 6601 */ 6602 uint32_t pmap_kernel_L1_addr(void) 6603 { 6604 return pmap_kernel()->pm_l1->l1_physaddr; 6605 } 6606 6607 #if defined(DDB) 6608 /* 6609 * A couple of ddb-callable functions for dumping pmaps 6610 */ 6611 void pmap_dump_all(void); 6612 void pmap_dump(pmap_t); 6613 6614 void 6615 pmap_dump_all(void) 6616 { 6617 pmap_t pm; 6618 6619 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6620 if (pm == pmap_kernel()) 6621 continue; 6622 pmap_dump(pm); 6623 printf("\n"); 6624 } 6625 } 6626 6627 static pt_entry_t ncptes[64]; 6628 static void pmap_dump_ncpg(pmap_t); 6629 6630 void 6631 pmap_dump(pmap_t pm) 6632 { 6633 struct l2_dtable *l2; 6634 struct l2_bucket *l2b; 6635 pt_entry_t *ptep, pte; 6636 vaddr_t l2_va, l2b_va, va; 6637 int i, j, k, occ, rows = 0; 6638 6639 if (pm == pmap_kernel()) 6640 printf("pmap_kernel (%p): ", pm); 6641 else 6642 printf("user pmap (%p): ", pm); 6643 6644 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6645 6646 l2_va = 0; 6647 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6648 l2 = pm->pm_l2[i]; 6649 6650 if (l2 == NULL || l2->l2_occupancy == 0) 6651 continue; 6652 6653 l2b_va = l2_va; 6654 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6655 l2b = &l2->l2_bucket[j]; 6656 6657 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6658 continue; 6659 6660 ptep = l2b->l2b_kva; 6661 6662 for (k = 0; k < 256 && ptep[k] == 0; k++) 6663 ; 6664 6665 k &= ~63; 6666 occ = l2b->l2b_occupancy; 6667 va = l2b_va + (k * 4096); 6668 for (; k < 256; k++, va += 0x1000) { 6669 char ch = ' '; 6670 if ((k % 64) == 0) { 6671 if ((rows % 8) == 0) { 6672 printf( 6673 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6674 } 6675 printf("%08lx: ", va); 6676 } 6677 6678 ncptes[k & 63] = 0; 6679 pte = ptep[k]; 6680 if (pte == 0) { 6681 ch = '.'; 6682 } else { 6683 occ--; 6684 switch (pte & 0x0c) { 6685 case 0x00: 6686 ch = 'D'; /* No cache No buff */ 6687 break; 6688 case 0x04: 6689 ch = 'B'; /* No cache buff */ 6690 break; 6691 case 0x08: 6692 if (pte & 0x40) 6693 ch = 'm'; 6694 else 6695 ch = 'C'; /* Cache No buff */ 6696 break; 6697 case 0x0c: 6698 ch = 'F'; /* Cache Buff */ 6699 break; 6700 } 6701 6702 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6703 ch += 0x20; 6704 6705 if ((pte & 0xc) == 0) 6706 ncptes[k & 63] = pte; 6707 } 6708 6709 if ((k % 64) == 63) { 6710 rows++; 6711 printf("%c\n", ch); 6712 pmap_dump_ncpg(pm); 6713 if (occ == 0) 6714 break; 6715 } else 6716 printf("%c", ch); 6717 } 6718 } 6719 } 6720 } 6721 6722 static void 6723 pmap_dump_ncpg(pmap_t pm) 6724 { 6725 struct vm_page *pg; 6726 struct vm_page_md *md; 6727 struct pv_entry *pv; 6728 int i; 6729 6730 for (i = 0; i < 63; i++) { 6731 if (ncptes[i] == 0) 6732 continue; 6733 6734 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6735 if (pg == NULL) 6736 continue; 6737 md = VM_PAGE_TO_MD(pg); 6738 6739 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6740 VM_PAGE_TO_PHYS(pg), 6741 md->krw_mappings, md->kro_mappings, 6742 md->urw_mappings, md->uro_mappings); 6743 6744 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6745 printf(" %c va 0x%08lx, flags 0x%x\n", 6746 (pm == pv->pv_pmap) ? '*' : ' ', 6747 pv->pv_va, pv->pv_flags); 6748 } 6749 } 6750 } 6751 #endif 6752 6753 #ifdef PMAP_STEAL_MEMORY 6754 void 6755 pmap_boot_pageadd(pv_addr_t *newpv) 6756 { 6757 pv_addr_t *pv, *npv; 6758 6759 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6760 if (newpv->pv_pa < pv->pv_va) { 6761 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6762 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6763 newpv->pv_size += pv->pv_size; 6764 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6765 } 6766 pv = NULL; 6767 } else { 6768 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6769 pv = npv) { 6770 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6771 KASSERT(pv->pv_pa < newpv->pv_pa); 6772 if (newpv->pv_pa > npv->pv_pa) 6773 continue; 6774 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6775 pv->pv_size += newpv->pv_size; 6776 return; 6777 } 6778 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6779 break; 6780 newpv->pv_size += npv->pv_size; 6781 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6782 SLIST_REMOVE_AFTER(newpv, pv_list); 6783 return; 6784 } 6785 } 6786 } 6787 6788 if (pv) { 6789 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6790 } else { 6791 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6792 } 6793 } 6794 6795 void 6796 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6797 pv_addr_t *rpv) 6798 { 6799 pv_addr_t *pv, **pvp; 6800 struct vm_physseg *ps; 6801 size_t i; 6802 6803 KASSERT(amount & PGOFSET); 6804 KASSERT((mask & PGOFSET) == 0); 6805 KASSERT((match & PGOFSET) == 0); 6806 KASSERT(amount != 0); 6807 6808 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6809 (pv = *pvp) != NULL; 6810 pvp = &SLIST_NEXT(pv, pv_list)) { 6811 pv_addr_t *newpv; 6812 psize_t off; 6813 /* 6814 * If this entry is too small to satify the request... 6815 */ 6816 KASSERT(pv->pv_size > 0); 6817 if (pv->pv_size < amount) 6818 continue; 6819 6820 for (off = 0; off <= mask; off += PAGE_SIZE) { 6821 if (((pv->pv_pa + off) & mask) == match 6822 && off + amount <= pv->pv_size) 6823 break; 6824 } 6825 if (off > mask) 6826 continue; 6827 6828 rpv->pv_va = pv->pv_va + off; 6829 rpv->pv_pa = pv->pv_pa + off; 6830 rpv->pv_size = amount; 6831 pv->pv_size -= amount; 6832 if (pv->pv_size == 0) { 6833 KASSERT(off == 0); 6834 KASSERT((vaddr_t) pv == rpv->pv_va); 6835 *pvp = SLIST_NEXT(pv, pv_list); 6836 } else if (off == 0) { 6837 KASSERT((vaddr_t) pv == rpv->pv_va); 6838 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6839 *newpv = *pv; 6840 newpv->pv_pa += amount; 6841 newpv->pv_va += amount; 6842 *pvp = newpv; 6843 } else if (off < pv->pv_size) { 6844 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6845 *newpv = *pv; 6846 newpv->pv_size -= off; 6847 newpv->pv_pa += off + amount; 6848 newpv->pv_va += off + amount; 6849 6850 SLIST_NEXT(pv, pv_list) = newpv; 6851 pv->pv_size = off; 6852 } else { 6853 KASSERT((vaddr_t) pv != rpv->pv_va); 6854 } 6855 memset((void *)rpv->pv_va, 0, amount); 6856 return; 6857 } 6858 6859 if (vm_nphysseg == 0) 6860 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6861 6862 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6863 (pv = *pvp) != NULL; 6864 pvp = &SLIST_NEXT(pv, pv_list)) { 6865 if (SLIST_NEXT(pv, pv_list) == NULL) 6866 break; 6867 } 6868 KASSERT(mask == 0); 6869 for (i = 0; i < vm_nphysseg; i++) { 6870 ps = VM_PHYSMEM_PTR(i); 6871 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6872 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6873 rpv->pv_va = pv->pv_va; 6874 rpv->pv_pa = pv->pv_pa; 6875 rpv->pv_size = amount; 6876 *pvp = NULL; 6877 pmap_map_chunk(kernel_l1pt.pv_va, 6878 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6879 ptoa(ps->avail_start), 6880 amount - pv->pv_size, 6881 VM_PROT_READ|VM_PROT_WRITE, 6882 PTE_CACHE); 6883 ps->avail_start += atop(amount - pv->pv_size); 6884 /* 6885 * If we consumed the entire physseg, remove it. 6886 */ 6887 if (ps->avail_start == ps->avail_end) { 6888 for (--vm_nphysseg; i < vm_nphysseg; i++) 6889 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6890 } 6891 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6892 return; 6893 } 6894 } 6895 6896 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6897 } 6898 6899 vaddr_t 6900 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6901 { 6902 pv_addr_t pv; 6903 6904 pmap_boot_pagealloc(size, 0, 0, &pv); 6905 6906 return pv.pv_va; 6907 } 6908 #endif /* PMAP_STEAL_MEMORY */ 6909 6910 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6911 { 6912 sysctl_createv(clog, 0, NULL, NULL, 6913 CTLFLAG_PERMANENT, 6914 CTLTYPE_NODE, "machdep", NULL, 6915 NULL, 0, NULL, 0, 6916 CTL_MACHDEP, CTL_EOL); 6917 6918 sysctl_createv(clog, 0, NULL, NULL, 6919 CTLFLAG_PERMANENT, 6920 CTLTYPE_INT, "kmpages", 6921 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6922 NULL, 0, &pmap_kmpages, 0, 6923 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6924 } 6925 6926 #ifdef PMAP_NEED_ALLOC_POOLPAGE 6927 struct vm_page * 6928 arm_pmap_alloc_poolpage(int flags) 6929 { 6930 /* 6931 * On some systems, only some pages may be "coherent" for dma and we 6932 * want to prefer those for pool pages (think mbufs) but fallback to 6933 * any page if none is available. 6934 */ 6935 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 6936 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 6937 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 6938 } 6939 6940 return uvm_pagealloc(NULL, 0, NULL, flags); 6941 } 6942 #endif 6943
Indexes created Mon Oct 27 15:09:58 GMT 2025