pmap.c revision 1.225
1 /* $NetBSD: pmap.c,v 1.225 2012/01/27 19:48:38 para Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/pool.h> 201 #include <sys/kmem.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <sys/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.225 2012/01/27 19:48:38 para Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 static struct pmap kernel_pmap_store; 258 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 #ifdef PMAPCOUNTERS 308 #define PMAP_EVCNT_INITIALIZER(name) \ 309 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 310 311 #ifdef PMAP_CACHE_VIPT 312 static struct evcnt pmap_ev_vac_clean_one = 313 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 314 static struct evcnt pmap_ev_vac_flush_one = 315 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_lots = 317 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 318 static struct evcnt pmap_ev_vac_flush_lots2 = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 324 325 static struct evcnt pmap_ev_vac_color_new = 326 PMAP_EVCNT_INITIALIZER("new page color"); 327 static struct evcnt pmap_ev_vac_color_reuse = 328 PMAP_EVCNT_INITIALIZER("ok first page color"); 329 static struct evcnt pmap_ev_vac_color_ok = 330 PMAP_EVCNT_INITIALIZER("ok page color"); 331 static struct evcnt pmap_ev_vac_color_blind = 332 PMAP_EVCNT_INITIALIZER("blind page color"); 333 static struct evcnt pmap_ev_vac_color_change = 334 PMAP_EVCNT_INITIALIZER("change page color"); 335 static struct evcnt pmap_ev_vac_color_erase = 336 PMAP_EVCNT_INITIALIZER("erase page color"); 337 static struct evcnt pmap_ev_vac_color_none = 338 PMAP_EVCNT_INITIALIZER("no page color"); 339 static struct evcnt pmap_ev_vac_color_restore = 340 PMAP_EVCNT_INITIALIZER("restore page color"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 350 #endif 351 352 static struct evcnt pmap_ev_mappings = 353 PMAP_EVCNT_INITIALIZER("pages mapped"); 354 static struct evcnt pmap_ev_unmappings = 355 PMAP_EVCNT_INITIALIZER("pages unmapped"); 356 static struct evcnt pmap_ev_remappings = 357 PMAP_EVCNT_INITIALIZER("pages remapped"); 358 359 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 360 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 362 363 static struct evcnt pmap_ev_kernel_mappings = 364 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 365 static struct evcnt pmap_ev_kernel_unmappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 367 static struct evcnt pmap_ev_kernel_remappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 373 374 static struct evcnt pmap_ev_kenter_mappings = 375 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 376 static struct evcnt pmap_ev_kenter_unmappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 378 static struct evcnt pmap_ev_kenter_remappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 380 static struct evcnt pmap_ev_pt_mappings = 381 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 382 383 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 387 388 #ifdef PMAP_CACHE_VIPT 389 static struct evcnt pmap_ev_exec_mappings = 390 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 391 static struct evcnt pmap_ev_exec_cached = 392 PMAP_EVCNT_INITIALIZER("exec pages cached"); 393 394 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 396 397 static struct evcnt pmap_ev_exec_synced = 398 PMAP_EVCNT_INITIALIZER("exec pages synced"); 399 static struct evcnt pmap_ev_exec_synced_map = 400 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 401 static struct evcnt pmap_ev_exec_synced_unmap = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 403 static struct evcnt pmap_ev_exec_synced_remap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 405 static struct evcnt pmap_ev_exec_synced_clearbit = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 407 static struct evcnt pmap_ev_exec_synced_kremove = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 409 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 416 417 static struct evcnt pmap_ev_exec_discarded_unmap = 418 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 419 static struct evcnt pmap_ev_exec_discarded_zero = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 421 static struct evcnt pmap_ev_exec_discarded_copy = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 423 static struct evcnt pmap_ev_exec_discarded_page_protect = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 425 static struct evcnt pmap_ev_exec_discarded_clearbit = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 427 static struct evcnt pmap_ev_exec_discarded_kremove = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 429 430 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 436 #endif /* PMAP_CACHE_VIPT */ 437 438 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 439 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 440 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 441 442 EVCNT_ATTACH_STATIC(pmap_ev_updates); 443 EVCNT_ATTACH_STATIC(pmap_ev_collects); 444 EVCNT_ATTACH_STATIC(pmap_ev_activations); 445 446 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 447 #else 448 #define PMAPCOUNT(x) ((void)0) 449 #endif 450 451 /* 452 * pmap copy/zero page, and mem(5) hook point 453 */ 454 static pt_entry_t *csrc_pte, *cdst_pte; 455 static vaddr_t csrcp, cdstp; 456 vaddr_t memhook; /* used by mem.c */ 457 kmutex_t memlock; /* used by mem.c */ 458 void *zeropage; /* used by mem.c */ 459 extern void *msgbufaddr; 460 int pmap_kmpages; 461 /* 462 * Flag to indicate if pmap_init() has done its thing 463 */ 464 bool pmap_initialized; 465 466 /* 467 * Misc. locking data structures 468 */ 469 470 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 471 static struct lock pmap_main_lock; 472 473 #define PMAP_MAP_TO_HEAD_LOCK() \ 474 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 475 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 476 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 477 #define PMAP_HEAD_TO_MAP_LOCK() \ 478 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 479 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 480 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 481 #else 482 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 483 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 484 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 485 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 486 #endif 487 488 #define pmap_acquire_pmap_lock(pm) \ 489 do { \ 490 if ((pm) != pmap_kernel()) \ 491 mutex_enter((pm)->pm_lock); \ 492 } while (/*CONSTCOND*/0) 493 494 #define pmap_release_pmap_lock(pm) \ 495 do { \ 496 if ((pm) != pmap_kernel()) \ 497 mutex_exit((pm)->pm_lock); \ 498 } while (/*CONSTCOND*/0) 499 500 501 /* 502 * Metadata for L1 translation tables. 503 */ 504 struct l1_ttable { 505 /* Entry on the L1 Table list */ 506 SLIST_ENTRY(l1_ttable) l1_link; 507 508 /* Entry on the L1 Least Recently Used list */ 509 TAILQ_ENTRY(l1_ttable) l1_lru; 510 511 /* Track how many domains are allocated from this L1 */ 512 volatile u_int l1_domain_use_count; 513 514 /* 515 * A free-list of domain numbers for this L1. 516 * We avoid using ffs() and a bitmap to track domains since ffs() 517 * is slow on ARM. 518 */ 519 u_int8_t l1_domain_first; 520 u_int8_t l1_domain_free[PMAP_DOMAINS]; 521 522 /* Physical address of this L1 page table */ 523 paddr_t l1_physaddr; 524 525 /* KVA of this L1 page table */ 526 pd_entry_t *l1_kva; 527 }; 528 529 /* 530 * Convert a virtual address into its L1 table index. That is, the 531 * index used to locate the L2 descriptor table pointer in an L1 table. 532 * This is basically used to index l1->l1_kva[]. 533 * 534 * Each L2 descriptor table represents 1MB of VA space. 535 */ 536 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 537 538 /* 539 * L1 Page Tables are tracked using a Least Recently Used list. 540 * - New L1s are allocated from the HEAD. 541 * - Freed L1s are added to the TAIl. 542 * - Recently accessed L1s (where an 'access' is some change to one of 543 * the userland pmaps which owns this L1) are moved to the TAIL. 544 */ 545 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 546 static struct simplelock l1_lru_lock; 547 548 /* 549 * A list of all L1 tables 550 */ 551 static SLIST_HEAD(, l1_ttable) l1_list; 552 553 /* 554 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 555 * 556 * This is normally 16MB worth L2 page descriptors for any given pmap. 557 * Reference counts are maintained for L2 descriptors so they can be 558 * freed when empty. 559 */ 560 struct l2_dtable { 561 /* The number of L2 page descriptors allocated to this l2_dtable */ 562 u_int l2_occupancy; 563 564 /* List of L2 page descriptors */ 565 struct l2_bucket { 566 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 567 paddr_t l2b_phys; /* Physical address of same */ 568 u_short l2b_l1idx; /* This L2 table's L1 index */ 569 u_short l2b_occupancy; /* How many active descriptors */ 570 } l2_bucket[L2_BUCKET_SIZE]; 571 }; 572 573 /* 574 * Given an L1 table index, calculate the corresponding l2_dtable index 575 * and bucket index within the l2_dtable. 576 */ 577 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 578 (L2_SIZE - 1)) 579 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 580 581 /* 582 * Given a virtual address, this macro returns the 583 * virtual address required to drop into the next L2 bucket. 584 */ 585 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 586 587 /* 588 * L2 allocation. 589 */ 590 #define pmap_alloc_l2_dtable() \ 591 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 592 #define pmap_free_l2_dtable(l2) \ 593 pool_cache_put(&pmap_l2dtable_cache, (l2)) 594 #define pmap_alloc_l2_ptp(pap) \ 595 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 596 PR_NOWAIT, (pap))) 597 598 /* 599 * We try to map the page tables write-through, if possible. However, not 600 * all CPUs have a write-through cache mode, so on those we have to sync 601 * the cache when we frob page tables. 602 * 603 * We try to evaluate this at compile time, if possible. However, it's 604 * not always possible to do that, hence this run-time var. 605 */ 606 int pmap_needs_pte_sync; 607 608 /* 609 * Real definition of pv_entry. 610 */ 611 struct pv_entry { 612 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 613 pmap_t pv_pmap; /* pmap where mapping lies */ 614 vaddr_t pv_va; /* virtual address for mapping */ 615 u_int pv_flags; /* flags */ 616 }; 617 618 /* 619 * Macro to determine if a mapping might be resident in the 620 * instruction cache and/or TLB 621 */ 622 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 623 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 624 625 /* 626 * Macro to determine if a mapping might be resident in the 627 * data cache and/or TLB 628 */ 629 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 630 631 /* 632 * Local prototypes 633 */ 634 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 635 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 636 pt_entry_t **); 637 static bool pmap_is_current(pmap_t); 638 static bool pmap_is_cached(pmap_t); 639 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 640 pmap_t, vaddr_t, u_int); 641 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 642 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 643 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 644 u_int, u_int); 645 646 static void pmap_pinit(pmap_t); 647 static int pmap_pmap_ctor(void *, void *, int); 648 649 static void pmap_alloc_l1(pmap_t); 650 static void pmap_free_l1(pmap_t); 651 static void pmap_use_l1(pmap_t); 652 653 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 654 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 655 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 656 static int pmap_l2ptp_ctor(void *, void *, int); 657 static int pmap_l2dtable_ctor(void *, void *, int); 658 659 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 660 #ifdef PMAP_CACHE_VIVT 661 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 662 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 663 #endif 664 665 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 666 #ifdef PMAP_CACHE_VIVT 667 static int pmap_clean_page(struct pv_entry *, bool); 668 #endif 669 #ifdef PMAP_CACHE_VIPT 670 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 671 enum pmap_flush_op { 672 PMAP_FLUSH_PRIMARY, 673 PMAP_FLUSH_SECONDARY, 674 PMAP_CLEAN_PRIMARY 675 }; 676 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 677 #endif 678 static void pmap_page_remove(struct vm_page_md *, paddr_t); 679 680 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 681 static vaddr_t kernel_pt_lookup(paddr_t); 682 683 684 /* 685 * External function prototypes 686 */ 687 extern void bzero_page(vaddr_t); 688 extern void bcopy_page(vaddr_t, vaddr_t); 689 690 /* 691 * Misc variables 692 */ 693 vaddr_t virtual_avail; 694 vaddr_t virtual_end; 695 vaddr_t pmap_curmaxkvaddr; 696 697 paddr_t avail_start; 698 paddr_t avail_end; 699 700 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 701 pv_addr_t kernelpages; 702 pv_addr_t kernel_l1pt; 703 pv_addr_t systempage; 704 705 /* Function to set the debug level of the pmap code */ 706 707 #ifdef PMAP_DEBUG 708 void 709 pmap_debug(int level) 710 { 711 pmap_debug_level = level; 712 printf("pmap_debug: level=%d\n", pmap_debug_level); 713 } 714 #endif /* PMAP_DEBUG */ 715 716 /* 717 * A bunch of routines to conditionally flush the caches/TLB depending 718 * on whether the specified pmap actually needs to be flushed at any 719 * given time. 720 */ 721 static inline void 722 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 723 { 724 725 if (pm->pm_cstate.cs_tlb_id) 726 cpu_tlb_flushID_SE(va); 727 } 728 729 static inline void 730 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 731 { 732 733 if (pm->pm_cstate.cs_tlb_d) 734 cpu_tlb_flushD_SE(va); 735 } 736 737 static inline void 738 pmap_tlb_flushID(pmap_t pm) 739 { 740 741 if (pm->pm_cstate.cs_tlb_id) { 742 cpu_tlb_flushID(); 743 pm->pm_cstate.cs_tlb = 0; 744 } 745 } 746 747 static inline void 748 pmap_tlb_flushD(pmap_t pm) 749 { 750 751 if (pm->pm_cstate.cs_tlb_d) { 752 cpu_tlb_flushD(); 753 pm->pm_cstate.cs_tlb_d = 0; 754 } 755 } 756 757 #ifdef PMAP_CACHE_VIVT 758 static inline void 759 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 760 { 761 if (pm->pm_cstate.cs_cache_id) { 762 cpu_idcache_wbinv_range(va, len); 763 } 764 } 765 766 static inline void 767 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 768 bool do_inv, bool rd_only) 769 { 770 771 if (pm->pm_cstate.cs_cache_d) { 772 if (do_inv) { 773 if (rd_only) 774 cpu_dcache_inv_range(va, len); 775 else 776 cpu_dcache_wbinv_range(va, len); 777 } else 778 if (!rd_only) 779 cpu_dcache_wb_range(va, len); 780 } 781 } 782 783 static inline void 784 pmap_idcache_wbinv_all(pmap_t pm) 785 { 786 if (pm->pm_cstate.cs_cache_id) { 787 cpu_idcache_wbinv_all(); 788 pm->pm_cstate.cs_cache = 0; 789 } 790 } 791 792 static inline void 793 pmap_dcache_wbinv_all(pmap_t pm) 794 { 795 if (pm->pm_cstate.cs_cache_d) { 796 cpu_dcache_wbinv_all(); 797 pm->pm_cstate.cs_cache_d = 0; 798 } 799 } 800 #endif /* PMAP_CACHE_VIVT */ 801 802 static inline bool 803 pmap_is_current(pmap_t pm) 804 { 805 806 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 807 return true; 808 809 return false; 810 } 811 812 static inline bool 813 pmap_is_cached(pmap_t pm) 814 { 815 816 if (pm == pmap_kernel() || pmap_recent_user == NULL || 817 pmap_recent_user == pm) 818 return (true); 819 820 return false; 821 } 822 823 /* 824 * PTE_SYNC_CURRENT: 825 * 826 * Make sure the pte is written out to RAM. 827 * We need to do this for one of two cases: 828 * - We're dealing with the kernel pmap 829 * - There is no pmap active in the cache/tlb. 830 * - The specified pmap is 'active' in the cache/tlb. 831 */ 832 #ifdef PMAP_INCLUDE_PTE_SYNC 833 #define PTE_SYNC_CURRENT(pm, ptep) \ 834 do { \ 835 if (PMAP_NEEDS_PTE_SYNC && \ 836 pmap_is_cached(pm)) \ 837 PTE_SYNC(ptep); \ 838 } while (/*CONSTCOND*/0) 839 #else 840 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 841 #endif 842 843 /* 844 * main pv_entry manipulation functions: 845 * pmap_enter_pv: enter a mapping onto a vm_page list 846 * pmap_remove_pv: remove a mappiing from a vm_page list 847 * 848 * NOTE: pmap_enter_pv expects to lock the pvh itself 849 * pmap_remove_pv expects te caller to lock the pvh before calling 850 */ 851 852 /* 853 * pmap_enter_pv: enter a mapping onto a vm_page lst 854 * 855 * => caller should hold the proper lock on pmap_main_lock 856 * => caller should have pmap locked 857 * => we will gain the lock on the vm_page and allocate the new pv_entry 858 * => caller should adjust ptp's wire_count before calling 859 * => caller should not adjust pmap's wire_count 860 */ 861 static void 862 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 863 vaddr_t va, u_int flags) 864 { 865 struct pv_entry **pvp; 866 867 NPDEBUG(PDB_PVDUMP, 868 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 869 870 pv->pv_pmap = pm; 871 pv->pv_va = va; 872 pv->pv_flags = flags; 873 874 simple_lock(&md->pvh_slock); /* lock vm_page */ 875 pvp = &SLIST_FIRST(&md->pvh_list); 876 #ifdef PMAP_CACHE_VIPT 877 /* 878 * Insert unmanaged entries, writeable first, at the head of 879 * the pv list. 880 */ 881 if (__predict_true((flags & PVF_KENTRY) == 0)) { 882 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 883 pvp = &SLIST_NEXT(*pvp, pv_link); 884 } else if ((flags & PVF_WRITE) == 0) { 885 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 886 pvp = &SLIST_NEXT(*pvp, pv_link); 887 } 888 #endif 889 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 890 *pvp = pv; /* ... locked list */ 891 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 892 #ifdef PMAP_CACHE_VIPT 893 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 894 md->pvh_attrs |= PVF_KMOD; 895 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 896 md->pvh_attrs |= PVF_DIRTY; 897 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 898 #endif 899 if (pm == pmap_kernel()) { 900 PMAPCOUNT(kernel_mappings); 901 if (flags & PVF_WRITE) 902 md->krw_mappings++; 903 else 904 md->kro_mappings++; 905 } else { 906 if (flags & PVF_WRITE) 907 md->urw_mappings++; 908 else 909 md->uro_mappings++; 910 } 911 912 #ifdef PMAP_CACHE_VIPT 913 /* 914 * If this is an exec mapping and its the first exec mapping 915 * for this page, make sure to sync the I-cache. 916 */ 917 if (PV_IS_EXEC_P(flags)) { 918 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 919 pmap_syncicache_page(md, pa); 920 PMAPCOUNT(exec_synced_map); 921 } 922 PMAPCOUNT(exec_mappings); 923 } 924 #endif 925 926 PMAPCOUNT(mappings); 927 simple_unlock(&md->pvh_slock); /* unlock, done! */ 928 929 if (pv->pv_flags & PVF_WIRED) 930 ++pm->pm_stats.wired_count; 931 } 932 933 /* 934 * 935 * pmap_find_pv: Find a pv entry 936 * 937 * => caller should hold lock on vm_page 938 */ 939 static inline struct pv_entry * 940 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 941 { 942 struct pv_entry *pv; 943 944 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 945 if (pm == pv->pv_pmap && va == pv->pv_va) 946 break; 947 } 948 949 return (pv); 950 } 951 952 /* 953 * pmap_remove_pv: try to remove a mapping from a pv_list 954 * 955 * => caller should hold proper lock on pmap_main_lock 956 * => pmap should be locked 957 * => caller should hold lock on vm_page [so that attrs can be adjusted] 958 * => caller should adjust ptp's wire_count and free PTP if needed 959 * => caller should NOT adjust pmap's wire_count 960 * => we return the removed pv 961 */ 962 static struct pv_entry * 963 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 964 { 965 struct pv_entry *pv, **prevptr; 966 967 NPDEBUG(PDB_PVDUMP, 968 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 969 970 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 971 pv = *prevptr; 972 973 while (pv) { 974 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 975 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 976 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 977 if (pv->pv_flags & PVF_WIRED) { 978 --pm->pm_stats.wired_count; 979 } 980 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 981 if (pm == pmap_kernel()) { 982 PMAPCOUNT(kernel_unmappings); 983 if (pv->pv_flags & PVF_WRITE) 984 md->krw_mappings--; 985 else 986 md->kro_mappings--; 987 } else { 988 if (pv->pv_flags & PVF_WRITE) 989 md->urw_mappings--; 990 else 991 md->uro_mappings--; 992 } 993 994 PMAPCOUNT(unmappings); 995 #ifdef PMAP_CACHE_VIPT 996 if (!(pv->pv_flags & PVF_WRITE)) 997 break; 998 /* 999 * If this page has had an exec mapping, then if 1000 * this was the last mapping, discard the contents, 1001 * otherwise sync the i-cache for this page. 1002 */ 1003 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1004 if (SLIST_EMPTY(&md->pvh_list)) { 1005 md->pvh_attrs &= ~PVF_EXEC; 1006 PMAPCOUNT(exec_discarded_unmap); 1007 } else { 1008 pmap_syncicache_page(md, pa); 1009 PMAPCOUNT(exec_synced_unmap); 1010 } 1011 } 1012 #endif /* PMAP_CACHE_VIPT */ 1013 break; 1014 } 1015 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1016 pv = *prevptr; /* advance */ 1017 } 1018 1019 #ifdef PMAP_CACHE_VIPT 1020 /* 1021 * If we no longer have a WRITEABLE KENTRY at the head of list, 1022 * clear the KMOD attribute from the page. 1023 */ 1024 if (SLIST_FIRST(&md->pvh_list) == NULL 1025 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1026 md->pvh_attrs &= ~PVF_KMOD; 1027 1028 /* 1029 * If this was a writeable page and there are no more writeable 1030 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1031 * the contents to memory. 1032 */ 1033 if (md->krw_mappings + md->urw_mappings == 0) 1034 md->pvh_attrs &= ~PVF_WRITE; 1035 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1036 #endif /* PMAP_CACHE_VIPT */ 1037 1038 return(pv); /* return removed pv */ 1039 } 1040 1041 /* 1042 * 1043 * pmap_modify_pv: Update pv flags 1044 * 1045 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1046 * => caller should NOT adjust pmap's wire_count 1047 * => caller must call pmap_vac_me_harder() if writable status of a page 1048 * may have changed. 1049 * => we return the old flags 1050 * 1051 * Modify a physical-virtual mapping in the pv table 1052 */ 1053 static u_int 1054 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1055 u_int clr_mask, u_int set_mask) 1056 { 1057 struct pv_entry *npv; 1058 u_int flags, oflags; 1059 1060 KASSERT((clr_mask & PVF_KENTRY) == 0); 1061 KASSERT((set_mask & PVF_KENTRY) == 0); 1062 1063 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1064 return (0); 1065 1066 NPDEBUG(PDB_PVDUMP, 1067 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1068 1069 /* 1070 * There is at least one VA mapping this page. 1071 */ 1072 1073 if (clr_mask & (PVF_REF | PVF_MOD)) { 1074 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1075 #ifdef PMAP_CACHE_VIPT 1076 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1077 md->pvh_attrs |= PVF_DIRTY; 1078 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1079 #endif 1080 } 1081 1082 oflags = npv->pv_flags; 1083 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1084 1085 if ((flags ^ oflags) & PVF_WIRED) { 1086 if (flags & PVF_WIRED) 1087 ++pm->pm_stats.wired_count; 1088 else 1089 --pm->pm_stats.wired_count; 1090 } 1091 1092 if ((flags ^ oflags) & PVF_WRITE) { 1093 if (pm == pmap_kernel()) { 1094 if (flags & PVF_WRITE) { 1095 md->krw_mappings++; 1096 md->kro_mappings--; 1097 } else { 1098 md->kro_mappings++; 1099 md->krw_mappings--; 1100 } 1101 } else { 1102 if (flags & PVF_WRITE) { 1103 md->urw_mappings++; 1104 md->uro_mappings--; 1105 } else { 1106 md->uro_mappings++; 1107 md->urw_mappings--; 1108 } 1109 } 1110 } 1111 #ifdef PMAP_CACHE_VIPT 1112 if (md->urw_mappings + md->krw_mappings == 0) 1113 md->pvh_attrs &= ~PVF_WRITE; 1114 /* 1115 * We have two cases here: the first is from enter_pv (new exec 1116 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1117 * Since in latter, pmap_enter_pv won't do anything, we just have 1118 * to do what pmap_remove_pv would do. 1119 */ 1120 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1121 || (PV_IS_EXEC_P(md->pvh_attrs) 1122 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1123 pmap_syncicache_page(md, pa); 1124 PMAPCOUNT(exec_synced_remap); 1125 } 1126 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1127 #endif 1128 1129 PMAPCOUNT(remappings); 1130 1131 return (oflags); 1132 } 1133 1134 /* 1135 * Allocate an L1 translation table for the specified pmap. 1136 * This is called at pmap creation time. 1137 */ 1138 static void 1139 pmap_alloc_l1(pmap_t pm) 1140 { 1141 struct l1_ttable *l1; 1142 u_int8_t domain; 1143 1144 /* 1145 * Remove the L1 at the head of the LRU list 1146 */ 1147 simple_lock(&l1_lru_lock); 1148 l1 = TAILQ_FIRST(&l1_lru_list); 1149 KDASSERT(l1 != NULL); 1150 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1151 1152 /* 1153 * Pick the first available domain number, and update 1154 * the link to the next number. 1155 */ 1156 domain = l1->l1_domain_first; 1157 l1->l1_domain_first = l1->l1_domain_free[domain]; 1158 1159 /* 1160 * If there are still free domain numbers in this L1, 1161 * put it back on the TAIL of the LRU list. 1162 */ 1163 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1164 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1165 1166 simple_unlock(&l1_lru_lock); 1167 1168 /* 1169 * Fix up the relevant bits in the pmap structure 1170 */ 1171 pm->pm_l1 = l1; 1172 pm->pm_domain = domain; 1173 } 1174 1175 /* 1176 * Free an L1 translation table. 1177 * This is called at pmap destruction time. 1178 */ 1179 static void 1180 pmap_free_l1(pmap_t pm) 1181 { 1182 struct l1_ttable *l1 = pm->pm_l1; 1183 1184 simple_lock(&l1_lru_lock); 1185 1186 /* 1187 * If this L1 is currently on the LRU list, remove it. 1188 */ 1189 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1190 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1191 1192 /* 1193 * Free up the domain number which was allocated to the pmap 1194 */ 1195 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1196 l1->l1_domain_first = pm->pm_domain; 1197 l1->l1_domain_use_count--; 1198 1199 /* 1200 * The L1 now must have at least 1 free domain, so add 1201 * it back to the LRU list. If the use count is zero, 1202 * put it at the head of the list, otherwise it goes 1203 * to the tail. 1204 */ 1205 if (l1->l1_domain_use_count == 0) 1206 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1207 else 1208 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1209 1210 simple_unlock(&l1_lru_lock); 1211 } 1212 1213 static inline void 1214 pmap_use_l1(pmap_t pm) 1215 { 1216 struct l1_ttable *l1; 1217 1218 /* 1219 * Do nothing if we're in interrupt context. 1220 * Access to an L1 by the kernel pmap must not affect 1221 * the LRU list. 1222 */ 1223 if (cpu_intr_p() || pm == pmap_kernel()) 1224 return; 1225 1226 l1 = pm->pm_l1; 1227 1228 /* 1229 * If the L1 is not currently on the LRU list, just return 1230 */ 1231 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1232 return; 1233 1234 simple_lock(&l1_lru_lock); 1235 1236 /* 1237 * Check the use count again, now that we've acquired the lock 1238 */ 1239 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1240 simple_unlock(&l1_lru_lock); 1241 return; 1242 } 1243 1244 /* 1245 * Move the L1 to the back of the LRU list 1246 */ 1247 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1248 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1249 1250 simple_unlock(&l1_lru_lock); 1251 } 1252 1253 /* 1254 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1255 * 1256 * Free an L2 descriptor table. 1257 */ 1258 static inline void 1259 #ifndef PMAP_INCLUDE_PTE_SYNC 1260 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1261 #else 1262 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1263 #endif 1264 { 1265 #ifdef PMAP_INCLUDE_PTE_SYNC 1266 #ifdef PMAP_CACHE_VIVT 1267 /* 1268 * Note: With a write-back cache, we may need to sync this 1269 * L2 table before re-using it. 1270 * This is because it may have belonged to a non-current 1271 * pmap, in which case the cache syncs would have been 1272 * skipped for the pages that were being unmapped. If the 1273 * L2 table were then to be immediately re-allocated to 1274 * the *current* pmap, it may well contain stale mappings 1275 * which have not yet been cleared by a cache write-back 1276 * and so would still be visible to the mmu. 1277 */ 1278 if (need_sync) 1279 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1280 #endif /* PMAP_CACHE_VIVT */ 1281 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1282 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1283 } 1284 1285 /* 1286 * Returns a pointer to the L2 bucket associated with the specified pmap 1287 * and VA, or NULL if no L2 bucket exists for the address. 1288 */ 1289 static inline struct l2_bucket * 1290 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1291 { 1292 struct l2_dtable *l2; 1293 struct l2_bucket *l2b; 1294 u_short l1idx; 1295 1296 l1idx = L1_IDX(va); 1297 1298 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1299 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1300 return (NULL); 1301 1302 return (l2b); 1303 } 1304 1305 /* 1306 * Returns a pointer to the L2 bucket associated with the specified pmap 1307 * and VA. 1308 * 1309 * If no L2 bucket exists, perform the necessary allocations to put an L2 1310 * bucket/page table in place. 1311 * 1312 * Note that if a new L2 bucket/page was allocated, the caller *must* 1313 * increment the bucket occupancy counter appropriately *before* 1314 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1315 * the bucket/page in the meantime. 1316 */ 1317 static struct l2_bucket * 1318 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1319 { 1320 struct l2_dtable *l2; 1321 struct l2_bucket *l2b; 1322 u_short l1idx; 1323 1324 l1idx = L1_IDX(va); 1325 1326 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1327 /* 1328 * No mapping at this address, as there is 1329 * no entry in the L1 table. 1330 * Need to allocate a new l2_dtable. 1331 */ 1332 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1333 return (NULL); 1334 1335 /* 1336 * Link it into the parent pmap 1337 */ 1338 pm->pm_l2[L2_IDX(l1idx)] = l2; 1339 } 1340 1341 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1342 1343 /* 1344 * Fetch pointer to the L2 page table associated with the address. 1345 */ 1346 if (l2b->l2b_kva == NULL) { 1347 pt_entry_t *ptep; 1348 1349 /* 1350 * No L2 page table has been allocated. Chances are, this 1351 * is because we just allocated the l2_dtable, above. 1352 */ 1353 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1354 /* 1355 * Oops, no more L2 page tables available at this 1356 * time. We may need to deallocate the l2_dtable 1357 * if we allocated a new one above. 1358 */ 1359 if (l2->l2_occupancy == 0) { 1360 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1361 pmap_free_l2_dtable(l2); 1362 } 1363 return (NULL); 1364 } 1365 1366 l2->l2_occupancy++; 1367 l2b->l2b_kva = ptep; 1368 l2b->l2b_l1idx = l1idx; 1369 } 1370 1371 return (l2b); 1372 } 1373 1374 /* 1375 * One or more mappings in the specified L2 descriptor table have just been 1376 * invalidated. 1377 * 1378 * Garbage collect the metadata and descriptor table itself if necessary. 1379 * 1380 * The pmap lock must be acquired when this is called (not necessary 1381 * for the kernel pmap). 1382 */ 1383 static void 1384 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1385 { 1386 struct l2_dtable *l2; 1387 pd_entry_t *pl1pd, l1pd; 1388 pt_entry_t *ptep; 1389 u_short l1idx; 1390 1391 KDASSERT(count <= l2b->l2b_occupancy); 1392 1393 /* 1394 * Update the bucket's reference count according to how many 1395 * PTEs the caller has just invalidated. 1396 */ 1397 l2b->l2b_occupancy -= count; 1398 1399 /* 1400 * Note: 1401 * 1402 * Level 2 page tables allocated to the kernel pmap are never freed 1403 * as that would require checking all Level 1 page tables and 1404 * removing any references to the Level 2 page table. See also the 1405 * comment elsewhere about never freeing bootstrap L2 descriptors. 1406 * 1407 * We make do with just invalidating the mapping in the L2 table. 1408 * 1409 * This isn't really a big deal in practice and, in fact, leads 1410 * to a performance win over time as we don't need to continually 1411 * alloc/free. 1412 */ 1413 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1414 return; 1415 1416 /* 1417 * There are no more valid mappings in this level 2 page table. 1418 * Go ahead and NULL-out the pointer in the bucket, then 1419 * free the page table. 1420 */ 1421 l1idx = l2b->l2b_l1idx; 1422 ptep = l2b->l2b_kva; 1423 l2b->l2b_kva = NULL; 1424 1425 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1426 1427 /* 1428 * If the L1 slot matches the pmap's domain 1429 * number, then invalidate it. 1430 */ 1431 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1432 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1433 *pl1pd = 0; 1434 PTE_SYNC(pl1pd); 1435 } 1436 1437 /* 1438 * Release the L2 descriptor table back to the pool cache. 1439 */ 1440 #ifndef PMAP_INCLUDE_PTE_SYNC 1441 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1442 #else 1443 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1444 #endif 1445 1446 /* 1447 * Update the reference count in the associated l2_dtable 1448 */ 1449 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1450 if (--l2->l2_occupancy > 0) 1451 return; 1452 1453 /* 1454 * There are no more valid mappings in any of the Level 1 1455 * slots managed by this l2_dtable. Go ahead and NULL-out 1456 * the pointer in the parent pmap and free the l2_dtable. 1457 */ 1458 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1459 pmap_free_l2_dtable(l2); 1460 } 1461 1462 /* 1463 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1464 * structures. 1465 */ 1466 static int 1467 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1468 { 1469 #ifndef PMAP_INCLUDE_PTE_SYNC 1470 struct l2_bucket *l2b; 1471 pt_entry_t *ptep, pte; 1472 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1473 1474 /* 1475 * The mappings for these page tables were initially made using 1476 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1477 * mode will not be right for page table mappings. To avoid 1478 * polluting the pmap_kenter_pa() code with a special case for 1479 * page tables, we simply fix up the cache-mode here if it's not 1480 * correct. 1481 */ 1482 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1483 KDASSERT(l2b != NULL); 1484 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1485 pte = *ptep; 1486 1487 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1488 /* 1489 * Page tables must have the cache-mode set to Write-Thru. 1490 */ 1491 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1492 PTE_SYNC(ptep); 1493 cpu_tlb_flushD_SE(va); 1494 cpu_cpwait(); 1495 } 1496 #endif 1497 1498 memset(v, 0, L2_TABLE_SIZE_REAL); 1499 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1500 return (0); 1501 } 1502 1503 static int 1504 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1505 { 1506 1507 memset(v, 0, sizeof(struct l2_dtable)); 1508 return (0); 1509 } 1510 1511 static int 1512 pmap_pmap_ctor(void *arg, void *v, int flags) 1513 { 1514 1515 memset(v, 0, sizeof(struct pmap)); 1516 return (0); 1517 } 1518 1519 static void 1520 pmap_pinit(pmap_t pm) 1521 { 1522 struct l2_bucket *l2b; 1523 1524 if (vector_page < KERNEL_BASE) { 1525 /* 1526 * Map the vector page. 1527 */ 1528 pmap_enter(pm, vector_page, systempage.pv_pa, 1529 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1530 pmap_update(pm); 1531 1532 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1533 l2b = pmap_get_l2_bucket(pm, vector_page); 1534 KDASSERT(l2b != NULL); 1535 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1536 L1_C_DOM(pm->pm_domain); 1537 } else 1538 pm->pm_pl1vec = NULL; 1539 } 1540 1541 #ifdef PMAP_CACHE_VIVT 1542 /* 1543 * Since we have a virtually indexed cache, we may need to inhibit caching if 1544 * there is more than one mapping and at least one of them is writable. 1545 * Since we purge the cache on every context switch, we only need to check for 1546 * other mappings within the same pmap, or kernel_pmap. 1547 * This function is also called when a page is unmapped, to possibly reenable 1548 * caching on any remaining mappings. 1549 * 1550 * The code implements the following logic, where: 1551 * 1552 * KW = # of kernel read/write pages 1553 * KR = # of kernel read only pages 1554 * UW = # of user read/write pages 1555 * UR = # of user read only pages 1556 * 1557 * KC = kernel mapping is cacheable 1558 * UC = user mapping is cacheable 1559 * 1560 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1561 * +--------------------------------------------- 1562 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1563 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1564 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1565 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1566 */ 1567 1568 static const int pmap_vac_flags[4][4] = { 1569 {-1, 0, 0, PVF_KNC}, 1570 {0, 0, PVF_NC, PVF_NC}, 1571 {0, PVF_NC, PVF_NC, PVF_NC}, 1572 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1573 }; 1574 1575 static inline int 1576 pmap_get_vac_flags(const struct vm_page_md *md) 1577 { 1578 int kidx, uidx; 1579 1580 kidx = 0; 1581 if (md->kro_mappings || md->krw_mappings > 1) 1582 kidx |= 1; 1583 if (md->krw_mappings) 1584 kidx |= 2; 1585 1586 uidx = 0; 1587 if (md->uro_mappings || md->urw_mappings > 1) 1588 uidx |= 1; 1589 if (md->urw_mappings) 1590 uidx |= 2; 1591 1592 return (pmap_vac_flags[uidx][kidx]); 1593 } 1594 1595 static inline void 1596 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1597 { 1598 int nattr; 1599 1600 nattr = pmap_get_vac_flags(md); 1601 1602 if (nattr < 0) { 1603 md->pvh_attrs &= ~PVF_NC; 1604 return; 1605 } 1606 1607 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1608 return; 1609 1610 if (pm == pmap_kernel()) 1611 pmap_vac_me_kpmap(md, pa, pm, va); 1612 else 1613 pmap_vac_me_user(md, pa, pm, va); 1614 1615 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1616 } 1617 1618 static void 1619 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1620 { 1621 u_int u_cacheable, u_entries; 1622 struct pv_entry *pv; 1623 pmap_t last_pmap = pm; 1624 1625 /* 1626 * Pass one, see if there are both kernel and user pmaps for 1627 * this page. Calculate whether there are user-writable or 1628 * kernel-writable pages. 1629 */ 1630 u_cacheable = 0; 1631 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1632 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1633 u_cacheable++; 1634 } 1635 1636 u_entries = md->urw_mappings + md->uro_mappings; 1637 1638 /* 1639 * We know we have just been updating a kernel entry, so if 1640 * all user pages are already cacheable, then there is nothing 1641 * further to do. 1642 */ 1643 if (md->k_mappings == 0 && u_cacheable == u_entries) 1644 return; 1645 1646 if (u_entries) { 1647 /* 1648 * Scan over the list again, for each entry, if it 1649 * might not be set correctly, call pmap_vac_me_user 1650 * to recalculate the settings. 1651 */ 1652 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1653 /* 1654 * We know kernel mappings will get set 1655 * correctly in other calls. We also know 1656 * that if the pmap is the same as last_pmap 1657 * then we've just handled this entry. 1658 */ 1659 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1660 continue; 1661 1662 /* 1663 * If there are kernel entries and this page 1664 * is writable but non-cacheable, then we can 1665 * skip this entry also. 1666 */ 1667 if (md->k_mappings && 1668 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1669 (PVF_NC | PVF_WRITE)) 1670 continue; 1671 1672 /* 1673 * Similarly if there are no kernel-writable 1674 * entries and the page is already 1675 * read-only/cacheable. 1676 */ 1677 if (md->krw_mappings == 0 && 1678 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1679 continue; 1680 1681 /* 1682 * For some of the remaining cases, we know 1683 * that we must recalculate, but for others we 1684 * can't tell if they are correct or not, so 1685 * we recalculate anyway. 1686 */ 1687 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1688 } 1689 1690 if (md->k_mappings == 0) 1691 return; 1692 } 1693 1694 pmap_vac_me_user(md, pa, pm, va); 1695 } 1696 1697 static void 1698 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1699 { 1700 pmap_t kpmap = pmap_kernel(); 1701 struct pv_entry *pv, *npv = NULL; 1702 struct l2_bucket *l2b; 1703 pt_entry_t *ptep, pte; 1704 u_int entries = 0; 1705 u_int writable = 0; 1706 u_int cacheable_entries = 0; 1707 u_int kern_cacheable = 0; 1708 u_int other_writable = 0; 1709 1710 /* 1711 * Count mappings and writable mappings in this pmap. 1712 * Include kernel mappings as part of our own. 1713 * Keep a pointer to the first one. 1714 */ 1715 npv = NULL; 1716 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1717 /* Count mappings in the same pmap */ 1718 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1719 if (entries++ == 0) 1720 npv = pv; 1721 1722 /* Cacheable mappings */ 1723 if ((pv->pv_flags & PVF_NC) == 0) { 1724 cacheable_entries++; 1725 if (kpmap == pv->pv_pmap) 1726 kern_cacheable++; 1727 } 1728 1729 /* Writable mappings */ 1730 if (pv->pv_flags & PVF_WRITE) 1731 ++writable; 1732 } else 1733 if (pv->pv_flags & PVF_WRITE) 1734 other_writable = 1; 1735 } 1736 1737 /* 1738 * Enable or disable caching as necessary. 1739 * Note: the first entry might be part of the kernel pmap, 1740 * so we can't assume this is indicative of the state of the 1741 * other (maybe non-kpmap) entries. 1742 */ 1743 if ((entries > 1 && writable) || 1744 (entries > 0 && pm == kpmap && other_writable)) { 1745 if (cacheable_entries == 0) 1746 return; 1747 1748 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1749 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1750 (pv->pv_flags & PVF_NC)) 1751 continue; 1752 1753 pv->pv_flags |= PVF_NC; 1754 1755 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1756 KDASSERT(l2b != NULL); 1757 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1758 pte = *ptep & ~L2_S_CACHE_MASK; 1759 1760 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1761 l2pte_valid(pte)) { 1762 if (PV_BEEN_EXECD(pv->pv_flags)) { 1763 #ifdef PMAP_CACHE_VIVT 1764 pmap_idcache_wbinv_range(pv->pv_pmap, 1765 pv->pv_va, PAGE_SIZE); 1766 #endif 1767 pmap_tlb_flushID_SE(pv->pv_pmap, 1768 pv->pv_va); 1769 } else 1770 if (PV_BEEN_REFD(pv->pv_flags)) { 1771 #ifdef PMAP_CACHE_VIVT 1772 pmap_dcache_wb_range(pv->pv_pmap, 1773 pv->pv_va, PAGE_SIZE, true, 1774 (pv->pv_flags & PVF_WRITE) == 0); 1775 #endif 1776 pmap_tlb_flushD_SE(pv->pv_pmap, 1777 pv->pv_va); 1778 } 1779 } 1780 1781 *ptep = pte; 1782 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1783 } 1784 cpu_cpwait(); 1785 } else 1786 if (entries > cacheable_entries) { 1787 /* 1788 * Turn cacheing back on for some pages. If it is a kernel 1789 * page, only do so if there are no other writable pages. 1790 */ 1791 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1792 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1793 (kpmap != pv->pv_pmap || other_writable))) 1794 continue; 1795 1796 pv->pv_flags &= ~PVF_NC; 1797 1798 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1799 KDASSERT(l2b != NULL); 1800 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1801 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1802 1803 if (l2pte_valid(pte)) { 1804 if (PV_BEEN_EXECD(pv->pv_flags)) { 1805 pmap_tlb_flushID_SE(pv->pv_pmap, 1806 pv->pv_va); 1807 } else 1808 if (PV_BEEN_REFD(pv->pv_flags)) { 1809 pmap_tlb_flushD_SE(pv->pv_pmap, 1810 pv->pv_va); 1811 } 1812 } 1813 1814 *ptep = pte; 1815 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1816 } 1817 } 1818 } 1819 #endif 1820 1821 #ifdef PMAP_CACHE_VIPT 1822 static void 1823 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1824 { 1825 struct pv_entry *pv; 1826 vaddr_t tst_mask; 1827 bool bad_alias; 1828 struct l2_bucket *l2b; 1829 pt_entry_t *ptep, pte, opte; 1830 const u_int 1831 rw_mappings = md->urw_mappings + md->krw_mappings, 1832 ro_mappings = md->uro_mappings + md->kro_mappings; 1833 1834 /* do we need to do anything? */ 1835 if (arm_cache_prefer_mask == 0) 1836 return; 1837 1838 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1839 md, pm, va)); 1840 1841 KASSERT(!va || pm); 1842 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1843 1844 /* Already a conflict? */ 1845 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1846 /* just an add, things are already non-cached */ 1847 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1848 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1849 bad_alias = false; 1850 if (va) { 1851 PMAPCOUNT(vac_color_none); 1852 bad_alias = true; 1853 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1854 goto fixup; 1855 } 1856 pv = SLIST_FIRST(&md->pvh_list); 1857 /* the list can't be empty because it would be cachable */ 1858 if (md->pvh_attrs & PVF_KMPAGE) { 1859 tst_mask = md->pvh_attrs; 1860 } else { 1861 KASSERT(pv); 1862 tst_mask = pv->pv_va; 1863 pv = SLIST_NEXT(pv, pv_link); 1864 } 1865 /* 1866 * Only check for a bad alias if we have writable mappings. 1867 */ 1868 tst_mask &= arm_cache_prefer_mask; 1869 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1870 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1871 /* if there's a bad alias, stop checking. */ 1872 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1873 bad_alias = true; 1874 } 1875 md->pvh_attrs |= PVF_WRITE; 1876 if (!bad_alias) 1877 md->pvh_attrs |= PVF_DIRTY; 1878 } else { 1879 /* 1880 * We have only read-only mappings. Let's see if there 1881 * are multiple colors in use or if we mapped a KMPAGE. 1882 * If the latter, we have a bad alias. If the former, 1883 * we need to remember that. 1884 */ 1885 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1886 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1887 if (md->pvh_attrs & PVF_KMPAGE) 1888 bad_alias = true; 1889 break; 1890 } 1891 } 1892 md->pvh_attrs &= ~PVF_WRITE; 1893 /* 1894 * No KMPAGE and we exited early, so we must have 1895 * multiple color mappings. 1896 */ 1897 if (!bad_alias && pv != NULL) 1898 md->pvh_attrs |= PVF_MULTCLR; 1899 } 1900 1901 /* If no conflicting colors, set everything back to cached */ 1902 if (!bad_alias) { 1903 #ifdef DEBUG 1904 if ((md->pvh_attrs & PVF_WRITE) 1905 || ro_mappings < 2) { 1906 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1907 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1908 } 1909 #endif 1910 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1911 md->pvh_attrs |= tst_mask | PVF_COLORED; 1912 /* 1913 * Restore DIRTY bit if page is modified 1914 */ 1915 if (md->pvh_attrs & PVF_DMOD) 1916 md->pvh_attrs |= PVF_DIRTY; 1917 PMAPCOUNT(vac_color_restore); 1918 } else { 1919 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1920 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1921 } 1922 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1923 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1924 } else if (!va) { 1925 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1926 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1927 || (md->pvh_attrs & PVF_DIRTY)); 1928 if (rw_mappings == 0) { 1929 md->pvh_attrs &= ~PVF_WRITE; 1930 if (ro_mappings == 1 1931 && (md->pvh_attrs & PVF_MULTCLR)) { 1932 /* 1933 * If this is the last readonly mapping 1934 * but it doesn't match the current color 1935 * for the page, change the current color 1936 * to match this last readonly mapping. 1937 */ 1938 pv = SLIST_FIRST(&md->pvh_list); 1939 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1940 & arm_cache_prefer_mask; 1941 if (tst_mask) { 1942 md->pvh_attrs ^= tst_mask; 1943 PMAPCOUNT(vac_color_change); 1944 } 1945 } 1946 } 1947 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1948 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1949 return; 1950 } else if (!pmap_is_page_colored_p(md)) { 1951 /* not colored so we just use its color */ 1952 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1953 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1954 PMAPCOUNT(vac_color_new); 1955 md->pvh_attrs &= PAGE_SIZE - 1; 1956 md->pvh_attrs |= PVF_COLORED 1957 | (va & arm_cache_prefer_mask) 1958 | (rw_mappings > 0 ? PVF_WRITE : 0); 1959 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1960 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1961 return; 1962 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1963 bad_alias = false; 1964 if (rw_mappings > 0) { 1965 /* 1966 * We now have writeable mappings and if we have 1967 * readonly mappings in more than once color, we have 1968 * an aliasing problem. Regardless mark the page as 1969 * writeable. 1970 */ 1971 if (md->pvh_attrs & PVF_MULTCLR) { 1972 if (ro_mappings < 2) { 1973 /* 1974 * If we only have less than two 1975 * read-only mappings, just flush the 1976 * non-primary colors from the cache. 1977 */ 1978 pmap_flush_page(md, pa, 1979 PMAP_FLUSH_SECONDARY); 1980 } else { 1981 bad_alias = true; 1982 } 1983 } 1984 md->pvh_attrs |= PVF_WRITE; 1985 } 1986 /* If no conflicting colors, set everything back to cached */ 1987 if (!bad_alias) { 1988 #ifdef DEBUG 1989 if (rw_mappings > 0 1990 || (md->pvh_attrs & PMAP_KMPAGE)) { 1991 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1992 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1993 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1994 } 1995 #endif 1996 if (SLIST_EMPTY(&md->pvh_list)) 1997 PMAPCOUNT(vac_color_reuse); 1998 else 1999 PMAPCOUNT(vac_color_ok); 2000 2001 /* matching color, just return */ 2002 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2003 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2004 return; 2005 } 2006 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2007 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2008 2009 /* color conflict. evict from cache. */ 2010 2011 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2012 md->pvh_attrs &= ~PVF_COLORED; 2013 md->pvh_attrs |= PVF_NC; 2014 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2015 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2016 PMAPCOUNT(vac_color_erase); 2017 } else if (rw_mappings == 0 2018 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2019 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2020 2021 /* 2022 * If the page has dirty cache lines, clean it. 2023 */ 2024 if (md->pvh_attrs & PVF_DIRTY) 2025 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2026 2027 /* 2028 * If this is the first remapping (we know that there are no 2029 * writeable mappings), then this is a simple color change. 2030 * Otherwise this is a seconary r/o mapping, which means 2031 * we don't have to do anything. 2032 */ 2033 if (ro_mappings == 1) { 2034 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2035 md->pvh_attrs &= PAGE_SIZE - 1; 2036 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2037 PMAPCOUNT(vac_color_change); 2038 } else { 2039 PMAPCOUNT(vac_color_blind); 2040 } 2041 md->pvh_attrs |= PVF_MULTCLR; 2042 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2043 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2044 return; 2045 } else { 2046 if (rw_mappings > 0) 2047 md->pvh_attrs |= PVF_WRITE; 2048 2049 /* color conflict. evict from cache. */ 2050 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2051 2052 /* the list can't be empty because this was a enter/modify */ 2053 pv = SLIST_FIRST(&md->pvh_list); 2054 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2055 KASSERT(pv); 2056 /* 2057 * If there's only one mapped page, change color to the 2058 * page's new color and return. Restore the DIRTY bit 2059 * that was erased by pmap_flush_page. 2060 */ 2061 if (SLIST_NEXT(pv, pv_link) == NULL) { 2062 md->pvh_attrs &= PAGE_SIZE - 1; 2063 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2064 if (md->pvh_attrs & PVF_DMOD) 2065 md->pvh_attrs |= PVF_DIRTY; 2066 PMAPCOUNT(vac_color_change); 2067 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2068 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2069 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2070 return; 2071 } 2072 } 2073 bad_alias = true; 2074 md->pvh_attrs &= ~PVF_COLORED; 2075 md->pvh_attrs |= PVF_NC; 2076 PMAPCOUNT(vac_color_erase); 2077 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2078 } 2079 2080 fixup: 2081 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2082 2083 /* 2084 * Turn cacheing on/off for all pages. 2085 */ 2086 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2087 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2088 KDASSERT(l2b != NULL); 2089 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2090 opte = *ptep; 2091 pte = opte & ~L2_S_CACHE_MASK; 2092 if (bad_alias) { 2093 pv->pv_flags |= PVF_NC; 2094 } else { 2095 pv->pv_flags &= ~PVF_NC; 2096 pte |= pte_l2_s_cache_mode; 2097 } 2098 2099 if (opte == pte) /* only update is there's a change */ 2100 continue; 2101 2102 if (l2pte_valid(pte)) { 2103 if (PV_BEEN_EXECD(pv->pv_flags)) { 2104 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2105 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2106 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2107 } 2108 } 2109 2110 *ptep = pte; 2111 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2112 } 2113 } 2114 #endif /* PMAP_CACHE_VIPT */ 2115 2116 2117 /* 2118 * Modify pte bits for all ptes corresponding to the given physical address. 2119 * We use `maskbits' rather than `clearbits' because we're always passing 2120 * constants and the latter would require an extra inversion at run-time. 2121 */ 2122 static void 2123 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2124 { 2125 struct l2_bucket *l2b; 2126 struct pv_entry *pv; 2127 pt_entry_t *ptep, npte, opte; 2128 pmap_t pm; 2129 vaddr_t va; 2130 u_int oflags; 2131 #ifdef PMAP_CACHE_VIPT 2132 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2133 bool need_syncicache = false; 2134 bool did_syncicache = false; 2135 bool need_vac_me_harder = false; 2136 #endif 2137 2138 NPDEBUG(PDB_BITS, 2139 printf("pmap_clearbit: md %p mask 0x%x\n", 2140 md, maskbits)); 2141 2142 PMAP_HEAD_TO_MAP_LOCK(); 2143 simple_lock(&md->pvh_slock); 2144 2145 #ifdef PMAP_CACHE_VIPT 2146 /* 2147 * If we might want to sync the I-cache and we've modified it, 2148 * then we know we definitely need to sync or discard it. 2149 */ 2150 if (want_syncicache) 2151 need_syncicache = md->pvh_attrs & PVF_MOD; 2152 #endif 2153 /* 2154 * Clear saved attributes (modify, reference) 2155 */ 2156 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2157 2158 if (SLIST_EMPTY(&md->pvh_list)) { 2159 #ifdef PMAP_CACHE_VIPT 2160 if (need_syncicache) { 2161 /* 2162 * No one has it mapped, so just discard it. The next 2163 * exec remapping will cause it to be synced. 2164 */ 2165 md->pvh_attrs &= ~PVF_EXEC; 2166 PMAPCOUNT(exec_discarded_clearbit); 2167 } 2168 #endif 2169 simple_unlock(&md->pvh_slock); 2170 PMAP_HEAD_TO_MAP_UNLOCK(); 2171 return; 2172 } 2173 2174 /* 2175 * Loop over all current mappings setting/clearing as appropos 2176 */ 2177 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2178 va = pv->pv_va; 2179 pm = pv->pv_pmap; 2180 oflags = pv->pv_flags; 2181 /* 2182 * Kernel entries are unmanaged and as such not to be changed. 2183 */ 2184 if (oflags & PVF_KENTRY) 2185 continue; 2186 pv->pv_flags &= ~maskbits; 2187 2188 pmap_acquire_pmap_lock(pm); 2189 2190 l2b = pmap_get_l2_bucket(pm, va); 2191 KDASSERT(l2b != NULL); 2192 2193 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2194 npte = opte = *ptep; 2195 2196 NPDEBUG(PDB_BITS, 2197 printf( 2198 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2199 pv, pv->pv_pmap, pv->pv_va, oflags)); 2200 2201 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2202 #ifdef PMAP_CACHE_VIVT 2203 if ((pv->pv_flags & PVF_NC)) { 2204 /* 2205 * Entry is not cacheable: 2206 * 2207 * Don't turn caching on again if this is a 2208 * modified emulation. This would be 2209 * inconsitent with the settings created by 2210 * pmap_vac_me_harder(). Otherwise, it's safe 2211 * to re-enable cacheing. 2212 * 2213 * There's no need to call pmap_vac_me_harder() 2214 * here: all pages are losing their write 2215 * permission. 2216 */ 2217 if (maskbits & PVF_WRITE) { 2218 npte |= pte_l2_s_cache_mode; 2219 pv->pv_flags &= ~PVF_NC; 2220 } 2221 } else 2222 if (l2pte_writable_p(opte)) { 2223 /* 2224 * Entry is writable/cacheable: check if pmap 2225 * is current if it is flush it, otherwise it 2226 * won't be in the cache 2227 */ 2228 if (PV_BEEN_EXECD(oflags)) 2229 pmap_idcache_wbinv_range(pm, pv->pv_va, 2230 PAGE_SIZE); 2231 else 2232 if (PV_BEEN_REFD(oflags)) 2233 pmap_dcache_wb_range(pm, pv->pv_va, 2234 PAGE_SIZE, 2235 (maskbits & PVF_REF) != 0, false); 2236 } 2237 #endif 2238 2239 /* make the pte read only */ 2240 npte = l2pte_set_readonly(npte); 2241 2242 if (maskbits & oflags & PVF_WRITE) { 2243 /* 2244 * Keep alias accounting up to date 2245 */ 2246 if (pv->pv_pmap == pmap_kernel()) { 2247 md->krw_mappings--; 2248 md->kro_mappings++; 2249 } else { 2250 md->urw_mappings--; 2251 md->uro_mappings++; 2252 } 2253 #ifdef PMAP_CACHE_VIPT 2254 if (md->urw_mappings + md->krw_mappings == 0) 2255 md->pvh_attrs &= ~PVF_WRITE; 2256 if (want_syncicache) 2257 need_syncicache = true; 2258 need_vac_me_harder = true; 2259 #endif 2260 } 2261 } 2262 2263 if (maskbits & PVF_REF) { 2264 if ((pv->pv_flags & PVF_NC) == 0 && 2265 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2266 l2pte_valid(npte)) { 2267 #ifdef PMAP_CACHE_VIVT 2268 /* 2269 * Check npte here; we may have already 2270 * done the wbinv above, and the validity 2271 * of the PTE is the same for opte and 2272 * npte. 2273 */ 2274 /* XXXJRT need idcache_inv_range */ 2275 if (PV_BEEN_EXECD(oflags)) 2276 pmap_idcache_wbinv_range(pm, 2277 pv->pv_va, PAGE_SIZE); 2278 else 2279 if (PV_BEEN_REFD(oflags)) 2280 pmap_dcache_wb_range(pm, 2281 pv->pv_va, PAGE_SIZE, 2282 true, true); 2283 #endif 2284 } 2285 2286 /* 2287 * Make the PTE invalid so that we will take a 2288 * page fault the next time the mapping is 2289 * referenced. 2290 */ 2291 npte &= ~L2_TYPE_MASK; 2292 npte |= L2_TYPE_INV; 2293 } 2294 2295 if (npte != opte) { 2296 *ptep = npte; 2297 PTE_SYNC(ptep); 2298 /* Flush the TLB entry if a current pmap. */ 2299 if (PV_BEEN_EXECD(oflags)) 2300 pmap_tlb_flushID_SE(pm, pv->pv_va); 2301 else 2302 if (PV_BEEN_REFD(oflags)) 2303 pmap_tlb_flushD_SE(pm, pv->pv_va); 2304 } 2305 2306 pmap_release_pmap_lock(pm); 2307 2308 NPDEBUG(PDB_BITS, 2309 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2310 pm, va, opte, npte)); 2311 } 2312 2313 #ifdef PMAP_CACHE_VIPT 2314 /* 2315 * If we need to sync the I-cache and we haven't done it yet, do it. 2316 */ 2317 if (need_syncicache && !did_syncicache) { 2318 pmap_syncicache_page(md, pa); 2319 PMAPCOUNT(exec_synced_clearbit); 2320 } 2321 /* 2322 * If we are changing this to read-only, we need to call vac_me_harder 2323 * so we can change all the read-only pages to cacheable. We pretend 2324 * this as a page deletion. 2325 */ 2326 if (need_vac_me_harder) { 2327 if (md->pvh_attrs & PVF_NC) 2328 pmap_vac_me_harder(md, pa, NULL, 0); 2329 } 2330 #endif 2331 2332 simple_unlock(&md->pvh_slock); 2333 PMAP_HEAD_TO_MAP_UNLOCK(); 2334 } 2335 2336 /* 2337 * pmap_clean_page() 2338 * 2339 * This is a local function used to work out the best strategy to clean 2340 * a single page referenced by its entry in the PV table. It's used by 2341 * pmap_copy_page, pmap_zero page and maybe some others later on. 2342 * 2343 * Its policy is effectively: 2344 * o If there are no mappings, we don't bother doing anything with the cache. 2345 * o If there is one mapping, we clean just that page. 2346 * o If there are multiple mappings, we clean the entire cache. 2347 * 2348 * So that some functions can be further optimised, it returns 0 if it didn't 2349 * clean the entire cache, or 1 if it did. 2350 * 2351 * XXX One bug in this routine is that if the pv_entry has a single page 2352 * mapped at 0x00000000 a whole cache clean will be performed rather than 2353 * just the 1 page. Since this should not occur in everyday use and if it does 2354 * it will just result in not the most efficient clean for the page. 2355 */ 2356 #ifdef PMAP_CACHE_VIVT 2357 static int 2358 pmap_clean_page(struct pv_entry *pv, bool is_src) 2359 { 2360 pmap_t pm_to_clean = NULL; 2361 struct pv_entry *npv; 2362 u_int cache_needs_cleaning = 0; 2363 u_int flags = 0; 2364 vaddr_t page_to_clean = 0; 2365 2366 if (pv == NULL) { 2367 /* nothing mapped in so nothing to flush */ 2368 return (0); 2369 } 2370 2371 /* 2372 * Since we flush the cache each time we change to a different 2373 * user vmspace, we only need to flush the page if it is in the 2374 * current pmap. 2375 */ 2376 2377 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2378 if (pmap_is_current(npv->pv_pmap)) { 2379 flags |= npv->pv_flags; 2380 /* 2381 * The page is mapped non-cacheable in 2382 * this map. No need to flush the cache. 2383 */ 2384 if (npv->pv_flags & PVF_NC) { 2385 #ifdef DIAGNOSTIC 2386 if (cache_needs_cleaning) 2387 panic("pmap_clean_page: " 2388 "cache inconsistency"); 2389 #endif 2390 break; 2391 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2392 continue; 2393 if (cache_needs_cleaning) { 2394 page_to_clean = 0; 2395 break; 2396 } else { 2397 page_to_clean = npv->pv_va; 2398 pm_to_clean = npv->pv_pmap; 2399 } 2400 cache_needs_cleaning = 1; 2401 } 2402 } 2403 2404 if (page_to_clean) { 2405 if (PV_BEEN_EXECD(flags)) 2406 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2407 PAGE_SIZE); 2408 else 2409 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2410 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2411 } else if (cache_needs_cleaning) { 2412 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2413 2414 if (PV_BEEN_EXECD(flags)) 2415 pmap_idcache_wbinv_all(pm); 2416 else 2417 pmap_dcache_wbinv_all(pm); 2418 return (1); 2419 } 2420 return (0); 2421 } 2422 #endif 2423 2424 #ifdef PMAP_CACHE_VIPT 2425 /* 2426 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2427 * right cache alias to make sure we flush the right stuff. 2428 */ 2429 void 2430 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2431 { 2432 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2433 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2434 2435 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2436 md, md->pvh_attrs)); 2437 /* 2438 * No need to clean the page if it's non-cached. 2439 */ 2440 if (md->pvh_attrs & PVF_NC) 2441 return; 2442 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2443 2444 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2445 /* 2446 * Set up a PTE with the right coloring to flush existing cache lines. 2447 */ 2448 *ptep = L2_S_PROTO | 2449 pa 2450 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2451 | pte_l2_s_cache_mode; 2452 PTE_SYNC(ptep); 2453 2454 /* 2455 * Flush it. 2456 */ 2457 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2458 /* 2459 * Unmap the page. 2460 */ 2461 *ptep = 0; 2462 PTE_SYNC(ptep); 2463 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2464 2465 md->pvh_attrs |= PVF_EXEC; 2466 PMAPCOUNT(exec_synced); 2467 } 2468 2469 void 2470 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2471 { 2472 vsize_t va_offset, end_va; 2473 void (*cf)(vaddr_t, vsize_t); 2474 2475 if (arm_cache_prefer_mask == 0) 2476 return; 2477 2478 switch (flush) { 2479 case PMAP_FLUSH_PRIMARY: 2480 if (md->pvh_attrs & PVF_MULTCLR) { 2481 va_offset = 0; 2482 end_va = arm_cache_prefer_mask; 2483 md->pvh_attrs &= ~PVF_MULTCLR; 2484 PMAPCOUNT(vac_flush_lots); 2485 } else { 2486 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2487 end_va = va_offset; 2488 PMAPCOUNT(vac_flush_one); 2489 } 2490 /* 2491 * Mark that the page is no longer dirty. 2492 */ 2493 md->pvh_attrs &= ~PVF_DIRTY; 2494 cf = cpufuncs.cf_idcache_wbinv_range; 2495 break; 2496 case PMAP_FLUSH_SECONDARY: 2497 va_offset = 0; 2498 end_va = arm_cache_prefer_mask; 2499 cf = cpufuncs.cf_idcache_wbinv_range; 2500 md->pvh_attrs &= ~PVF_MULTCLR; 2501 PMAPCOUNT(vac_flush_lots); 2502 break; 2503 case PMAP_CLEAN_PRIMARY: 2504 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2505 end_va = va_offset; 2506 cf = cpufuncs.cf_dcache_wb_range; 2507 /* 2508 * Mark that the page is no longer dirty. 2509 */ 2510 if ((md->pvh_attrs & PVF_DMOD) == 0) 2511 md->pvh_attrs &= ~PVF_DIRTY; 2512 PMAPCOUNT(vac_clean_one); 2513 break; 2514 default: 2515 return; 2516 } 2517 2518 KASSERT(!(md->pvh_attrs & PVF_NC)); 2519 2520 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2521 md, md->pvh_attrs)); 2522 2523 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2524 const size_t pte_offset = va_offset >> PGSHIFT; 2525 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2526 const pt_entry_t oldpte = *ptep; 2527 2528 if (flush == PMAP_FLUSH_SECONDARY 2529 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2530 continue; 2531 2532 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2533 /* 2534 * Set up a PTE with the right coloring to flush 2535 * existing cache entries. 2536 */ 2537 *ptep = L2_S_PROTO 2538 | pa 2539 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2540 | pte_l2_s_cache_mode; 2541 PTE_SYNC(ptep); 2542 2543 /* 2544 * Flush it. 2545 */ 2546 (*cf)(cdstp + va_offset, PAGE_SIZE); 2547 2548 /* 2549 * Restore the page table entry since we might have interrupted 2550 * pmap_zero_page or pmap_copy_page which was already using 2551 * this pte. 2552 */ 2553 *ptep = oldpte; 2554 PTE_SYNC(ptep); 2555 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2556 } 2557 } 2558 #endif /* PMAP_CACHE_VIPT */ 2559 2560 /* 2561 * Routine: pmap_page_remove 2562 * Function: 2563 * Removes this physical page from 2564 * all physical maps in which it resides. 2565 * Reflects back modify bits to the pager. 2566 */ 2567 static void 2568 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2569 { 2570 struct l2_bucket *l2b; 2571 struct pv_entry *pv, *npv, **pvp; 2572 pmap_t pm; 2573 pt_entry_t *ptep; 2574 bool flush; 2575 u_int flags; 2576 2577 NPDEBUG(PDB_FOLLOW, 2578 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2579 pa)); 2580 2581 PMAP_HEAD_TO_MAP_LOCK(); 2582 simple_lock(&md->pvh_slock); 2583 2584 pv = SLIST_FIRST(&md->pvh_list); 2585 if (pv == NULL) { 2586 #ifdef PMAP_CACHE_VIPT 2587 /* 2588 * We *know* the page contents are about to be replaced. 2589 * Discard the exec contents 2590 */ 2591 if (PV_IS_EXEC_P(md->pvh_attrs)) 2592 PMAPCOUNT(exec_discarded_page_protect); 2593 md->pvh_attrs &= ~PVF_EXEC; 2594 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2595 #endif 2596 simple_unlock(&md->pvh_slock); 2597 PMAP_HEAD_TO_MAP_UNLOCK(); 2598 return; 2599 } 2600 #ifdef PMAP_CACHE_VIPT 2601 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2602 #endif 2603 2604 /* 2605 * Clear alias counts 2606 */ 2607 #ifdef PMAP_CACHE_VIVT 2608 md->k_mappings = 0; 2609 #endif 2610 md->urw_mappings = md->uro_mappings = 0; 2611 2612 flush = false; 2613 flags = 0; 2614 2615 #ifdef PMAP_CACHE_VIVT 2616 pmap_clean_page(pv, false); 2617 #endif 2618 2619 pvp = &SLIST_FIRST(&md->pvh_list); 2620 while (pv) { 2621 pm = pv->pv_pmap; 2622 npv = SLIST_NEXT(pv, pv_link); 2623 if (flush == false && pmap_is_current(pm)) 2624 flush = true; 2625 2626 if (pm == pmap_kernel()) { 2627 #ifdef PMAP_CACHE_VIPT 2628 /* 2629 * If this was unmanaged mapping, it must be preserved. 2630 * Move it back on the list and advance the end-of-list 2631 * pointer. 2632 */ 2633 if (pv->pv_flags & PVF_KENTRY) { 2634 *pvp = pv; 2635 pvp = &SLIST_NEXT(pv, pv_link); 2636 pv = npv; 2637 continue; 2638 } 2639 if (pv->pv_flags & PVF_WRITE) 2640 md->krw_mappings--; 2641 else 2642 md->kro_mappings--; 2643 #endif 2644 PMAPCOUNT(kernel_unmappings); 2645 } 2646 PMAPCOUNT(unmappings); 2647 2648 pmap_acquire_pmap_lock(pm); 2649 2650 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2651 KDASSERT(l2b != NULL); 2652 2653 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2654 2655 /* 2656 * Update statistics 2657 */ 2658 --pm->pm_stats.resident_count; 2659 2660 /* Wired bit */ 2661 if (pv->pv_flags & PVF_WIRED) 2662 --pm->pm_stats.wired_count; 2663 2664 flags |= pv->pv_flags; 2665 2666 /* 2667 * Invalidate the PTEs. 2668 */ 2669 *ptep = 0; 2670 PTE_SYNC_CURRENT(pm, ptep); 2671 pmap_free_l2_bucket(pm, l2b, 1); 2672 2673 pool_put(&pmap_pv_pool, pv); 2674 pv = npv; 2675 /* 2676 * if we reach the end of the list and there are still 2677 * mappings, they might be able to be cached now. 2678 */ 2679 if (pv == NULL) { 2680 *pvp = NULL; 2681 if (!SLIST_EMPTY(&md->pvh_list)) 2682 pmap_vac_me_harder(md, pa, pm, 0); 2683 } 2684 pmap_release_pmap_lock(pm); 2685 } 2686 #ifdef PMAP_CACHE_VIPT 2687 /* 2688 * Its EXEC cache is now gone. 2689 */ 2690 if (PV_IS_EXEC_P(md->pvh_attrs)) 2691 PMAPCOUNT(exec_discarded_page_protect); 2692 md->pvh_attrs &= ~PVF_EXEC; 2693 KASSERT(md->urw_mappings == 0); 2694 KASSERT(md->uro_mappings == 0); 2695 if (md->krw_mappings == 0) 2696 md->pvh_attrs &= ~PVF_WRITE; 2697 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2698 #endif 2699 simple_unlock(&md->pvh_slock); 2700 PMAP_HEAD_TO_MAP_UNLOCK(); 2701 2702 if (flush) { 2703 /* 2704 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2705 * would need a subsequent call to pmap_update() to ensure 2706 * curpm->pm_cstate.cs_all is reset. Our callers are not 2707 * required to do that (see pmap(9)), so we can't modify 2708 * the current pmap's state. 2709 */ 2710 if (PV_BEEN_EXECD(flags)) 2711 cpu_tlb_flushID(); 2712 else 2713 cpu_tlb_flushD(); 2714 } 2715 cpu_cpwait(); 2716 } 2717 2718 /* 2719 * pmap_t pmap_create(void) 2720 * 2721 * Create a new pmap structure from scratch. 2722 */ 2723 pmap_t 2724 pmap_create(void) 2725 { 2726 pmap_t pm; 2727 2728 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2729 2730 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2731 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2732 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2733 2734 pm->pm_stats.wired_count = 0; 2735 pm->pm_stats.resident_count = 1; 2736 pm->pm_cstate.cs_all = 0; 2737 pmap_alloc_l1(pm); 2738 2739 /* 2740 * Note: The pool cache ensures that the pm_l2[] array is already 2741 * initialised to zero. 2742 */ 2743 2744 pmap_pinit(pm); 2745 2746 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2747 2748 return (pm); 2749 } 2750 2751 u_int 2752 arm32_mmap_flags(paddr_t pa) 2753 { 2754 /* 2755 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 2756 * and we're using the upper bits in page numbers to pass flags around 2757 * so we might as well use the same bits 2758 */ 2759 return (u_int)pa & PMAP_MD_MASK; 2760 } 2761 /* 2762 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2763 * u_int flags) 2764 * 2765 * Insert the given physical page (p) at 2766 * the specified virtual address (v) in the 2767 * target physical map with the protection requested. 2768 * 2769 * NB: This is the only routine which MAY NOT lazy-evaluate 2770 * or lose information. That is, this routine must actually 2771 * insert this page into the given map NOW. 2772 */ 2773 int 2774 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2775 { 2776 struct l2_bucket *l2b; 2777 struct vm_page *pg, *opg; 2778 struct pv_entry *pv; 2779 pt_entry_t *ptep, npte, opte; 2780 u_int nflags; 2781 u_int oflags; 2782 2783 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2784 2785 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2786 KDASSERT(((va | pa) & PGOFSET) == 0); 2787 2788 /* 2789 * Get a pointer to the page. Later on in this function, we 2790 * test for a managed page by checking pg != NULL. 2791 */ 2792 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2793 2794 nflags = 0; 2795 if (prot & VM_PROT_WRITE) 2796 nflags |= PVF_WRITE; 2797 if (prot & VM_PROT_EXECUTE) 2798 nflags |= PVF_EXEC; 2799 if (flags & PMAP_WIRED) 2800 nflags |= PVF_WIRED; 2801 2802 PMAP_MAP_TO_HEAD_LOCK(); 2803 pmap_acquire_pmap_lock(pm); 2804 2805 /* 2806 * Fetch the L2 bucket which maps this page, allocating one if 2807 * necessary for user pmaps. 2808 */ 2809 if (pm == pmap_kernel()) 2810 l2b = pmap_get_l2_bucket(pm, va); 2811 else 2812 l2b = pmap_alloc_l2_bucket(pm, va); 2813 if (l2b == NULL) { 2814 if (flags & PMAP_CANFAIL) { 2815 pmap_release_pmap_lock(pm); 2816 PMAP_MAP_TO_HEAD_UNLOCK(); 2817 return (ENOMEM); 2818 } 2819 panic("pmap_enter: failed to allocate L2 bucket"); 2820 } 2821 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2822 opte = *ptep; 2823 npte = pa; 2824 oflags = 0; 2825 2826 if (opte) { 2827 /* 2828 * There is already a mapping at this address. 2829 * If the physical address is different, lookup the 2830 * vm_page. 2831 */ 2832 if (l2pte_pa(opte) != pa) 2833 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2834 else 2835 opg = pg; 2836 } else 2837 opg = NULL; 2838 2839 if (pg) { 2840 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2841 2842 /* 2843 * This is to be a managed mapping. 2844 */ 2845 if ((flags & VM_PROT_ALL) || 2846 (md->pvh_attrs & PVF_REF)) { 2847 /* 2848 * - The access type indicates that we don't need 2849 * to do referenced emulation. 2850 * OR 2851 * - The physical page has already been referenced 2852 * so no need to re-do referenced emulation here. 2853 */ 2854 npte |= l2pte_set_readonly(L2_S_PROTO); 2855 2856 nflags |= PVF_REF; 2857 2858 if ((prot & VM_PROT_WRITE) != 0 && 2859 ((flags & VM_PROT_WRITE) != 0 || 2860 (md->pvh_attrs & PVF_MOD) != 0)) { 2861 /* 2862 * This is a writable mapping, and the 2863 * page's mod state indicates it has 2864 * already been modified. Make it 2865 * writable from the outset. 2866 */ 2867 npte = l2pte_set_writable(npte); 2868 nflags |= PVF_MOD; 2869 } 2870 } else { 2871 /* 2872 * Need to do page referenced emulation. 2873 */ 2874 npte |= L2_TYPE_INV; 2875 } 2876 2877 npte |= pte_l2_s_cache_mode; 2878 2879 if (pg == opg) { 2880 /* 2881 * We're changing the attrs of an existing mapping. 2882 */ 2883 simple_lock(&md->pvh_slock); 2884 oflags = pmap_modify_pv(md, pa, pm, va, 2885 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2886 PVF_MOD | PVF_REF, nflags); 2887 simple_unlock(&md->pvh_slock); 2888 2889 #ifdef PMAP_CACHE_VIVT 2890 /* 2891 * We may need to flush the cache if we're 2892 * doing rw-ro... 2893 */ 2894 if (pm->pm_cstate.cs_cache_d && 2895 (oflags & PVF_NC) == 0 && 2896 l2pte_writable_p(opte) && 2897 (prot & VM_PROT_WRITE) == 0) 2898 cpu_dcache_wb_range(va, PAGE_SIZE); 2899 #endif 2900 } else { 2901 /* 2902 * New mapping, or changing the backing page 2903 * of an existing mapping. 2904 */ 2905 if (opg) { 2906 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2907 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2908 2909 /* 2910 * Replacing an existing mapping with a new one. 2911 * It is part of our managed memory so we 2912 * must remove it from the PV list 2913 */ 2914 simple_lock(&omd->pvh_slock); 2915 pv = pmap_remove_pv(omd, opa, pm, va); 2916 pmap_vac_me_harder(omd, opa, pm, 0); 2917 simple_unlock(&omd->pvh_slock); 2918 oflags = pv->pv_flags; 2919 2920 #ifdef PMAP_CACHE_VIVT 2921 /* 2922 * If the old mapping was valid (ref/mod 2923 * emulation creates 'invalid' mappings 2924 * initially) then make sure to frob 2925 * the cache. 2926 */ 2927 if ((oflags & PVF_NC) == 0 && 2928 l2pte_valid(opte)) { 2929 if (PV_BEEN_EXECD(oflags)) { 2930 pmap_idcache_wbinv_range(pm, va, 2931 PAGE_SIZE); 2932 } else 2933 if (PV_BEEN_REFD(oflags)) { 2934 pmap_dcache_wb_range(pm, va, 2935 PAGE_SIZE, true, 2936 (oflags & PVF_WRITE) == 0); 2937 } 2938 } 2939 #endif 2940 } else 2941 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2942 if ((flags & PMAP_CANFAIL) == 0) 2943 panic("pmap_enter: no pv entries"); 2944 2945 if (pm != pmap_kernel()) 2946 pmap_free_l2_bucket(pm, l2b, 0); 2947 pmap_release_pmap_lock(pm); 2948 PMAP_MAP_TO_HEAD_UNLOCK(); 2949 NPDEBUG(PDB_ENTER, 2950 printf("pmap_enter: ENOMEM\n")); 2951 return (ENOMEM); 2952 } 2953 2954 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2955 } 2956 } else { 2957 /* 2958 * We're mapping an unmanaged page. 2959 * These are always readable, and possibly writable, from 2960 * the get go as we don't need to track ref/mod status. 2961 */ 2962 npte |= l2pte_set_readonly(L2_S_PROTO); 2963 if (prot & VM_PROT_WRITE) 2964 npte = l2pte_set_writable(npte); 2965 2966 /* 2967 * Make sure the vector table is mapped cacheable 2968 */ 2969 if ((pm != pmap_kernel() && va == vector_page) || 2970 (flags & ARM32_MMAP_CACHEABLE)) { 2971 npte |= pte_l2_s_cache_mode; 2972 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 2973 npte |= pte_l2_s_wc_mode; 2974 } 2975 if (opg) { 2976 /* 2977 * Looks like there's an existing 'managed' mapping 2978 * at this address. 2979 */ 2980 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2981 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2982 2983 simple_lock(&omd->pvh_slock); 2984 pv = pmap_remove_pv(omd, opa, pm, va); 2985 pmap_vac_me_harder(omd, opa, pm, 0); 2986 simple_unlock(&omd->pvh_slock); 2987 oflags = pv->pv_flags; 2988 2989 #ifdef PMAP_CACHE_VIVT 2990 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2991 if (PV_BEEN_EXECD(oflags)) 2992 pmap_idcache_wbinv_range(pm, va, 2993 PAGE_SIZE); 2994 else 2995 if (PV_BEEN_REFD(oflags)) 2996 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2997 true, (oflags & PVF_WRITE) == 0); 2998 } 2999 #endif 3000 pool_put(&pmap_pv_pool, pv); 3001 } 3002 } 3003 3004 /* 3005 * Make sure userland mappings get the right permissions 3006 */ 3007 if (pm != pmap_kernel() && va != vector_page) 3008 npte |= L2_S_PROT_U; 3009 3010 /* 3011 * Keep the stats up to date 3012 */ 3013 if (opte == 0) { 3014 l2b->l2b_occupancy++; 3015 pm->pm_stats.resident_count++; 3016 } 3017 3018 NPDEBUG(PDB_ENTER, 3019 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3020 3021 /* 3022 * If this is just a wiring change, the two PTEs will be 3023 * identical, so there's no need to update the page table. 3024 */ 3025 if (npte != opte) { 3026 bool is_cached = pmap_is_cached(pm); 3027 3028 *ptep = npte; 3029 if (is_cached) { 3030 /* 3031 * We only need to frob the cache/tlb if this pmap 3032 * is current 3033 */ 3034 PTE_SYNC(ptep); 3035 if (va != vector_page && l2pte_valid(npte)) { 3036 /* 3037 * This mapping is likely to be accessed as 3038 * soon as we return to userland. Fix up the 3039 * L1 entry to avoid taking another 3040 * page/domain fault. 3041 */ 3042 pd_entry_t *pl1pd, l1pd; 3043 3044 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3045 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3046 L1_C_PROTO; 3047 if (*pl1pd != l1pd) { 3048 *pl1pd = l1pd; 3049 PTE_SYNC(pl1pd); 3050 } 3051 } 3052 } 3053 3054 if (PV_BEEN_EXECD(oflags)) 3055 pmap_tlb_flushID_SE(pm, va); 3056 else 3057 if (PV_BEEN_REFD(oflags)) 3058 pmap_tlb_flushD_SE(pm, va); 3059 3060 NPDEBUG(PDB_ENTER, 3061 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3062 is_cached, pm->pm_cstate.cs_all)); 3063 3064 if (pg != NULL) { 3065 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3066 3067 simple_lock(&md->pvh_slock); 3068 pmap_vac_me_harder(md, pa, pm, va); 3069 simple_unlock(&md->pvh_slock); 3070 } 3071 } 3072 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3073 if (pg) { 3074 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3075 3076 simple_lock(&md->pvh_slock); 3077 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3078 KASSERT(((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0)); 3079 simple_unlock(&md->pvh_slock); 3080 } 3081 #endif 3082 3083 pmap_release_pmap_lock(pm); 3084 PMAP_MAP_TO_HEAD_UNLOCK(); 3085 3086 return (0); 3087 } 3088 3089 /* 3090 * pmap_remove() 3091 * 3092 * pmap_remove is responsible for nuking a number of mappings for a range 3093 * of virtual address space in the current pmap. To do this efficiently 3094 * is interesting, because in a number of cases a wide virtual address 3095 * range may be supplied that contains few actual mappings. So, the 3096 * optimisations are: 3097 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3098 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3099 * maybe do just a partial cache clean. This path of execution is 3100 * complicated by the fact that the cache must be flushed _before_ 3101 * the PTE is nuked, being a VAC :-) 3102 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3103 * all invalidations until pmap_update(), since pmap_remove_all() has 3104 * already flushed the cache. 3105 * 4. Maybe later fast-case a single page, but I don't think this is 3106 * going to make _that_ much difference overall. 3107 */ 3108 3109 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3110 3111 void 3112 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3113 { 3114 struct l2_bucket *l2b; 3115 vaddr_t next_bucket; 3116 pt_entry_t *ptep; 3117 u_int cleanlist_idx, total, cnt; 3118 struct { 3119 vaddr_t va; 3120 pt_entry_t *ptep; 3121 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3122 u_int mappings, is_exec, is_refd; 3123 3124 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3125 "eva=%08lx\n", pm, sva, eva)); 3126 3127 /* 3128 * we lock in the pmap => pv_head direction 3129 */ 3130 PMAP_MAP_TO_HEAD_LOCK(); 3131 pmap_acquire_pmap_lock(pm); 3132 3133 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3134 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3135 if (pm->pm_cstate.cs_tlb == 0) 3136 pm->pm_remove_all = true; 3137 } else 3138 cleanlist_idx = 0; 3139 3140 total = 0; 3141 3142 while (sva < eva) { 3143 /* 3144 * Do one L2 bucket's worth at a time. 3145 */ 3146 next_bucket = L2_NEXT_BUCKET(sva); 3147 if (next_bucket > eva) 3148 next_bucket = eva; 3149 3150 l2b = pmap_get_l2_bucket(pm, sva); 3151 if (l2b == NULL) { 3152 sva = next_bucket; 3153 continue; 3154 } 3155 3156 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3157 3158 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3159 struct vm_page *pg; 3160 pt_entry_t pte; 3161 paddr_t pa; 3162 3163 pte = *ptep; 3164 3165 if (pte == 0) { 3166 /* Nothing here, move along */ 3167 continue; 3168 } 3169 3170 pa = l2pte_pa(pte); 3171 is_exec = 0; 3172 is_refd = 1; 3173 3174 /* 3175 * Update flags. In a number of circumstances, 3176 * we could cluster a lot of these and do a 3177 * number of sequential pages in one go. 3178 */ 3179 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3180 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3181 struct pv_entry *pv; 3182 3183 simple_lock(&md->pvh_slock); 3184 pv = pmap_remove_pv(md, pa, pm, sva); 3185 pmap_vac_me_harder(md, pa, pm, 0); 3186 simple_unlock(&md->pvh_slock); 3187 if (pv != NULL) { 3188 if (pm->pm_remove_all == false) { 3189 is_exec = 3190 PV_BEEN_EXECD(pv->pv_flags); 3191 is_refd = 3192 PV_BEEN_REFD(pv->pv_flags); 3193 } 3194 pool_put(&pmap_pv_pool, pv); 3195 } 3196 } 3197 mappings++; 3198 3199 if (!l2pte_valid(pte)) { 3200 /* 3201 * Ref/Mod emulation is still active for this 3202 * mapping, therefore it is has not yet been 3203 * accessed. No need to frob the cache/tlb. 3204 */ 3205 *ptep = 0; 3206 PTE_SYNC_CURRENT(pm, ptep); 3207 continue; 3208 } 3209 3210 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3211 /* Add to the clean list. */ 3212 cleanlist[cleanlist_idx].ptep = ptep; 3213 cleanlist[cleanlist_idx].va = 3214 sva | (is_exec & 1); 3215 cleanlist_idx++; 3216 } else 3217 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3218 /* Nuke everything if needed. */ 3219 #ifdef PMAP_CACHE_VIVT 3220 pmap_idcache_wbinv_all(pm); 3221 #endif 3222 pmap_tlb_flushID(pm); 3223 3224 /* 3225 * Roll back the previous PTE list, 3226 * and zero out the current PTE. 3227 */ 3228 for (cnt = 0; 3229 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3230 *cleanlist[cnt].ptep = 0; 3231 PTE_SYNC(cleanlist[cnt].ptep); 3232 } 3233 *ptep = 0; 3234 PTE_SYNC(ptep); 3235 cleanlist_idx++; 3236 pm->pm_remove_all = true; 3237 } else { 3238 *ptep = 0; 3239 PTE_SYNC(ptep); 3240 if (pm->pm_remove_all == false) { 3241 if (is_exec) 3242 pmap_tlb_flushID_SE(pm, sva); 3243 else 3244 if (is_refd) 3245 pmap_tlb_flushD_SE(pm, sva); 3246 } 3247 } 3248 } 3249 3250 /* 3251 * Deal with any left overs 3252 */ 3253 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3254 total += cleanlist_idx; 3255 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3256 if (pm->pm_cstate.cs_all != 0) { 3257 vaddr_t clva = cleanlist[cnt].va & ~1; 3258 if (cleanlist[cnt].va & 1) { 3259 #ifdef PMAP_CACHE_VIVT 3260 pmap_idcache_wbinv_range(pm, 3261 clva, PAGE_SIZE); 3262 #endif 3263 pmap_tlb_flushID_SE(pm, clva); 3264 } else { 3265 #ifdef PMAP_CACHE_VIVT 3266 pmap_dcache_wb_range(pm, 3267 clva, PAGE_SIZE, true, 3268 false); 3269 #endif 3270 pmap_tlb_flushD_SE(pm, clva); 3271 } 3272 } 3273 *cleanlist[cnt].ptep = 0; 3274 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3275 } 3276 3277 /* 3278 * If it looks like we're removing a whole bunch 3279 * of mappings, it's faster to just write-back 3280 * the whole cache now and defer TLB flushes until 3281 * pmap_update() is called. 3282 */ 3283 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3284 cleanlist_idx = 0; 3285 else { 3286 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3287 #ifdef PMAP_CACHE_VIVT 3288 pmap_idcache_wbinv_all(pm); 3289 #endif 3290 pm->pm_remove_all = true; 3291 } 3292 } 3293 3294 pmap_free_l2_bucket(pm, l2b, mappings); 3295 pm->pm_stats.resident_count -= mappings; 3296 } 3297 3298 pmap_release_pmap_lock(pm); 3299 PMAP_MAP_TO_HEAD_UNLOCK(); 3300 } 3301 3302 #ifdef PMAP_CACHE_VIPT 3303 static struct pv_entry * 3304 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3305 { 3306 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3307 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3308 struct pv_entry *pv; 3309 3310 simple_lock(&md->pvh_slock); 3311 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3312 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3313 3314 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3315 KASSERT(pv); 3316 KASSERT(pv->pv_flags & PVF_KENTRY); 3317 3318 /* 3319 * If we are removing a writeable mapping to a cached exec page, 3320 * if it's the last mapping then clear it execness other sync 3321 * the page to the icache. 3322 */ 3323 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3324 && (pv->pv_flags & PVF_WRITE) != 0) { 3325 if (SLIST_EMPTY(&md->pvh_list)) { 3326 md->pvh_attrs &= ~PVF_EXEC; 3327 PMAPCOUNT(exec_discarded_kremove); 3328 } else { 3329 pmap_syncicache_page(md, pa); 3330 PMAPCOUNT(exec_synced_kremove); 3331 } 3332 } 3333 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3334 simple_unlock(&md->pvh_slock); 3335 3336 return pv; 3337 } 3338 #endif /* PMAP_CACHE_VIPT */ 3339 3340 /* 3341 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3342 * 3343 * We assume there is already sufficient KVM space available 3344 * to do this, as we can't allocate L2 descriptor tables/metadata 3345 * from here. 3346 */ 3347 void 3348 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3349 { 3350 struct l2_bucket *l2b; 3351 pt_entry_t *ptep, opte; 3352 #ifdef PMAP_CACHE_VIVT 3353 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3354 #endif 3355 #ifdef PMAP_CACHE_VIPT 3356 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3357 struct vm_page *opg; 3358 struct pv_entry *pv = NULL; 3359 #endif 3360 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3361 3362 NPDEBUG(PDB_KENTER, 3363 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3364 va, pa, prot)); 3365 3366 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3367 KDASSERT(l2b != NULL); 3368 3369 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3370 opte = *ptep; 3371 3372 if (opte == 0) { 3373 PMAPCOUNT(kenter_mappings); 3374 l2b->l2b_occupancy++; 3375 } else { 3376 PMAPCOUNT(kenter_remappings); 3377 #ifdef PMAP_CACHE_VIPT 3378 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3379 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3380 if (opg) { 3381 KASSERT(opg != pg); 3382 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3383 KASSERT((flags & PMAP_KMPAGE) == 0); 3384 simple_lock(&omd->pvh_slock); 3385 pv = pmap_kremove_pg(opg, va); 3386 simple_unlock(&omd->pvh_slock); 3387 } 3388 #endif 3389 if (l2pte_valid(opte)) { 3390 #ifdef PMAP_CACHE_VIVT 3391 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3392 #endif 3393 cpu_tlb_flushD_SE(va); 3394 cpu_cpwait(); 3395 } 3396 } 3397 3398 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3399 pte_l2_s_cache_mode; 3400 PTE_SYNC(ptep); 3401 3402 if (pg) { 3403 if (flags & PMAP_KMPAGE) { 3404 simple_lock(&md->pvh_slock); 3405 KASSERT(md->urw_mappings == 0); 3406 KASSERT(md->uro_mappings == 0); 3407 KASSERT(md->krw_mappings == 0); 3408 KASSERT(md->kro_mappings == 0); 3409 #ifdef PMAP_CACHE_VIPT 3410 KASSERT(pv == NULL); 3411 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3412 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3413 /* if there is a color conflict, evict from cache. */ 3414 if (pmap_is_page_colored_p(md) 3415 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3416 PMAPCOUNT(vac_color_change); 3417 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3418 } else if (md->pvh_attrs & PVF_MULTCLR) { 3419 /* 3420 * If this page has multiple colors, expunge 3421 * them. 3422 */ 3423 PMAPCOUNT(vac_flush_lots2); 3424 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3425 } 3426 md->pvh_attrs &= PAGE_SIZE - 1; 3427 md->pvh_attrs |= PVF_KMPAGE 3428 | PVF_COLORED | PVF_DIRTY 3429 | (va & arm_cache_prefer_mask); 3430 #endif 3431 #ifdef PMAP_CACHE_VIVT 3432 md->pvh_attrs |= PVF_KMPAGE; 3433 #endif 3434 pmap_kmpages++; 3435 simple_unlock(&md->pvh_slock); 3436 #ifdef PMAP_CACHE_VIPT 3437 } else { 3438 if (pv == NULL) { 3439 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3440 KASSERT(pv != NULL); 3441 } 3442 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3443 PVF_WIRED | PVF_KENTRY 3444 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3445 if ((prot & VM_PROT_WRITE) 3446 && !(md->pvh_attrs & PVF_NC)) 3447 md->pvh_attrs |= PVF_DIRTY; 3448 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3449 simple_lock(&md->pvh_slock); 3450 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3451 simple_unlock(&md->pvh_slock); 3452 #endif 3453 } 3454 #ifdef PMAP_CACHE_VIPT 3455 } else { 3456 if (pv != NULL) 3457 pool_put(&pmap_pv_pool, pv); 3458 #endif 3459 } 3460 } 3461 3462 void 3463 pmap_kremove(vaddr_t va, vsize_t len) 3464 { 3465 struct l2_bucket *l2b; 3466 pt_entry_t *ptep, *sptep, opte; 3467 vaddr_t next_bucket, eva; 3468 u_int mappings; 3469 struct vm_page *opg; 3470 3471 PMAPCOUNT(kenter_unmappings); 3472 3473 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3474 va, len)); 3475 3476 eva = va + len; 3477 3478 while (va < eva) { 3479 next_bucket = L2_NEXT_BUCKET(va); 3480 if (next_bucket > eva) 3481 next_bucket = eva; 3482 3483 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3484 KDASSERT(l2b != NULL); 3485 3486 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3487 mappings = 0; 3488 3489 while (va < next_bucket) { 3490 opte = *ptep; 3491 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3492 if (opg) { 3493 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3494 3495 if (omd->pvh_attrs & PVF_KMPAGE) { 3496 simple_lock(&omd->pvh_slock); 3497 KASSERT(omd->urw_mappings == 0); 3498 KASSERT(omd->uro_mappings == 0); 3499 KASSERT(omd->krw_mappings == 0); 3500 KASSERT(omd->kro_mappings == 0); 3501 omd->pvh_attrs &= ~PVF_KMPAGE; 3502 #ifdef PMAP_CACHE_VIPT 3503 omd->pvh_attrs &= ~PVF_WRITE; 3504 #endif 3505 pmap_kmpages--; 3506 simple_unlock(&omd->pvh_slock); 3507 #ifdef PMAP_CACHE_VIPT 3508 } else { 3509 pool_put(&pmap_pv_pool, 3510 pmap_kremove_pg(opg, va)); 3511 #endif 3512 } 3513 } 3514 if (l2pte_valid(opte)) { 3515 #ifdef PMAP_CACHE_VIVT 3516 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3517 #endif 3518 cpu_tlb_flushD_SE(va); 3519 } 3520 if (opte) { 3521 *ptep = 0; 3522 mappings++; 3523 } 3524 va += PAGE_SIZE; 3525 ptep++; 3526 } 3527 KDASSERT(mappings <= l2b->l2b_occupancy); 3528 l2b->l2b_occupancy -= mappings; 3529 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3530 } 3531 cpu_cpwait(); 3532 } 3533 3534 bool 3535 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3536 { 3537 struct l2_dtable *l2; 3538 pd_entry_t *pl1pd, l1pd; 3539 pt_entry_t *ptep, pte; 3540 paddr_t pa; 3541 u_int l1idx; 3542 3543 pmap_acquire_pmap_lock(pm); 3544 3545 l1idx = L1_IDX(va); 3546 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3547 l1pd = *pl1pd; 3548 3549 if (l1pte_section_p(l1pd)) { 3550 /* 3551 * These should only happen for pmap_kernel() 3552 */ 3553 KDASSERT(pm == pmap_kernel()); 3554 pmap_release_pmap_lock(pm); 3555 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3556 } else { 3557 /* 3558 * Note that we can't rely on the validity of the L1 3559 * descriptor as an indication that a mapping exists. 3560 * We have to look it up in the L2 dtable. 3561 */ 3562 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3563 3564 if (l2 == NULL || 3565 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3566 pmap_release_pmap_lock(pm); 3567 return false; 3568 } 3569 3570 ptep = &ptep[l2pte_index(va)]; 3571 pte = *ptep; 3572 pmap_release_pmap_lock(pm); 3573 3574 if (pte == 0) 3575 return false; 3576 3577 switch (pte & L2_TYPE_MASK) { 3578 case L2_TYPE_L: 3579 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3580 break; 3581 3582 default: 3583 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3584 break; 3585 } 3586 } 3587 3588 if (pap != NULL) 3589 *pap = pa; 3590 3591 return true; 3592 } 3593 3594 void 3595 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3596 { 3597 struct l2_bucket *l2b; 3598 pt_entry_t *ptep, pte; 3599 vaddr_t next_bucket; 3600 u_int flags; 3601 u_int clr_mask; 3602 int flush; 3603 3604 NPDEBUG(PDB_PROTECT, 3605 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3606 pm, sva, eva, prot)); 3607 3608 if ((prot & VM_PROT_READ) == 0) { 3609 pmap_remove(pm, sva, eva); 3610 return; 3611 } 3612 3613 if (prot & VM_PROT_WRITE) { 3614 /* 3615 * If this is a read->write transition, just ignore it and let 3616 * uvm_fault() take care of it later. 3617 */ 3618 return; 3619 } 3620 3621 PMAP_MAP_TO_HEAD_LOCK(); 3622 pmap_acquire_pmap_lock(pm); 3623 3624 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3625 flags = 0; 3626 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3627 3628 while (sva < eva) { 3629 next_bucket = L2_NEXT_BUCKET(sva); 3630 if (next_bucket > eva) 3631 next_bucket = eva; 3632 3633 l2b = pmap_get_l2_bucket(pm, sva); 3634 if (l2b == NULL) { 3635 sva = next_bucket; 3636 continue; 3637 } 3638 3639 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3640 3641 while (sva < next_bucket) { 3642 pte = *ptep; 3643 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3644 struct vm_page *pg; 3645 u_int f; 3646 3647 #ifdef PMAP_CACHE_VIVT 3648 /* 3649 * OK, at this point, we know we're doing 3650 * write-protect operation. If the pmap is 3651 * active, write-back the page. 3652 */ 3653 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3654 false, false); 3655 #endif 3656 3657 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3658 pte = l2pte_set_readonly(pte); 3659 *ptep = pte; 3660 PTE_SYNC(ptep); 3661 3662 if (pg != NULL) { 3663 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3664 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3665 3666 simple_lock(&md->pvh_slock); 3667 f = pmap_modify_pv(md, pa, pm, sva, 3668 clr_mask, 0); 3669 pmap_vac_me_harder(md, pa, pm, sva); 3670 simple_unlock(&md->pvh_slock); 3671 } else 3672 f = PVF_REF | PVF_EXEC; 3673 3674 if (flush >= 0) { 3675 flush++; 3676 flags |= f; 3677 } else 3678 if (PV_BEEN_EXECD(f)) 3679 pmap_tlb_flushID_SE(pm, sva); 3680 else 3681 if (PV_BEEN_REFD(f)) 3682 pmap_tlb_flushD_SE(pm, sva); 3683 } 3684 3685 sva += PAGE_SIZE; 3686 ptep++; 3687 } 3688 } 3689 3690 pmap_release_pmap_lock(pm); 3691 PMAP_MAP_TO_HEAD_UNLOCK(); 3692 3693 if (flush) { 3694 if (PV_BEEN_EXECD(flags)) 3695 pmap_tlb_flushID(pm); 3696 else 3697 if (PV_BEEN_REFD(flags)) 3698 pmap_tlb_flushD(pm); 3699 } 3700 } 3701 3702 void 3703 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3704 { 3705 struct l2_bucket *l2b; 3706 pt_entry_t *ptep; 3707 vaddr_t next_bucket; 3708 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3709 3710 NPDEBUG(PDB_EXEC, 3711 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3712 pm, sva, eva)); 3713 3714 PMAP_MAP_TO_HEAD_LOCK(); 3715 pmap_acquire_pmap_lock(pm); 3716 3717 while (sva < eva) { 3718 next_bucket = L2_NEXT_BUCKET(sva); 3719 if (next_bucket > eva) 3720 next_bucket = eva; 3721 3722 l2b = pmap_get_l2_bucket(pm, sva); 3723 if (l2b == NULL) { 3724 sva = next_bucket; 3725 continue; 3726 } 3727 3728 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3729 sva < next_bucket; 3730 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3731 if (l2pte_valid(*ptep)) { 3732 cpu_icache_sync_range(sva, 3733 min(page_size, eva - sva)); 3734 } 3735 } 3736 } 3737 3738 pmap_release_pmap_lock(pm); 3739 PMAP_MAP_TO_HEAD_UNLOCK(); 3740 } 3741 3742 void 3743 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3744 { 3745 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3746 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3747 3748 NPDEBUG(PDB_PROTECT, 3749 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3750 md, pa, prot)); 3751 3752 switch(prot) { 3753 case VM_PROT_READ|VM_PROT_WRITE: 3754 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3755 pmap_clearbit(md, pa, PVF_EXEC); 3756 break; 3757 #endif 3758 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3759 break; 3760 3761 case VM_PROT_READ: 3762 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3763 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3764 break; 3765 #endif 3766 case VM_PROT_READ|VM_PROT_EXECUTE: 3767 pmap_clearbit(md, pa, PVF_WRITE); 3768 break; 3769 3770 default: 3771 pmap_page_remove(md, pa); 3772 break; 3773 } 3774 } 3775 3776 /* 3777 * pmap_clear_modify: 3778 * 3779 * Clear the "modified" attribute for a page. 3780 */ 3781 bool 3782 pmap_clear_modify(struct vm_page *pg) 3783 { 3784 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3785 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3786 bool rv; 3787 3788 if (md->pvh_attrs & PVF_MOD) { 3789 rv = true; 3790 #ifdef PMAP_CACHE_VIPT 3791 /* 3792 * If we are going to clear the modified bit and there are 3793 * no other modified bits set, flush the page to memory and 3794 * mark it clean. 3795 */ 3796 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3797 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3798 #endif 3799 pmap_clearbit(md, pa, PVF_MOD); 3800 } else 3801 rv = false; 3802 3803 return (rv); 3804 } 3805 3806 /* 3807 * pmap_clear_reference: 3808 * 3809 * Clear the "referenced" attribute for a page. 3810 */ 3811 bool 3812 pmap_clear_reference(struct vm_page *pg) 3813 { 3814 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3815 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3816 bool rv; 3817 3818 if (md->pvh_attrs & PVF_REF) { 3819 rv = true; 3820 pmap_clearbit(md, pa, PVF_REF); 3821 } else 3822 rv = false; 3823 3824 return (rv); 3825 } 3826 3827 /* 3828 * pmap_is_modified: 3829 * 3830 * Test if a page has the "modified" attribute. 3831 */ 3832 /* See <arm/arm32/pmap.h> */ 3833 3834 /* 3835 * pmap_is_referenced: 3836 * 3837 * Test if a page has the "referenced" attribute. 3838 */ 3839 /* See <arm/arm32/pmap.h> */ 3840 3841 int 3842 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3843 { 3844 struct l2_dtable *l2; 3845 struct l2_bucket *l2b; 3846 pd_entry_t *pl1pd, l1pd; 3847 pt_entry_t *ptep, pte; 3848 paddr_t pa; 3849 u_int l1idx; 3850 int rv = 0; 3851 3852 PMAP_MAP_TO_HEAD_LOCK(); 3853 pmap_acquire_pmap_lock(pm); 3854 3855 l1idx = L1_IDX(va); 3856 3857 /* 3858 * If there is no l2_dtable for this address, then the process 3859 * has no business accessing it. 3860 * 3861 * Note: This will catch userland processes trying to access 3862 * kernel addresses. 3863 */ 3864 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3865 if (l2 == NULL) 3866 goto out; 3867 3868 /* 3869 * Likewise if there is no L2 descriptor table 3870 */ 3871 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3872 if (l2b->l2b_kva == NULL) 3873 goto out; 3874 3875 /* 3876 * Check the PTE itself. 3877 */ 3878 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3879 pte = *ptep; 3880 if (pte == 0) 3881 goto out; 3882 3883 /* 3884 * Catch a userland access to the vector page mapped at 0x0 3885 */ 3886 if (user && (pte & L2_S_PROT_U) == 0) 3887 goto out; 3888 3889 pa = l2pte_pa(pte); 3890 3891 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3892 /* 3893 * This looks like a good candidate for "page modified" 3894 * emulation... 3895 */ 3896 struct pv_entry *pv; 3897 struct vm_page *pg; 3898 3899 /* Extract the physical address of the page */ 3900 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3901 goto out; 3902 3903 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3904 3905 /* Get the current flags for this page. */ 3906 simple_lock(&md->pvh_slock); 3907 3908 pv = pmap_find_pv(md, pm, va); 3909 if (pv == NULL) { 3910 simple_unlock(&md->pvh_slock); 3911 goto out; 3912 } 3913 3914 /* 3915 * Do the flags say this page is writable? If not then it 3916 * is a genuine write fault. If yes then the write fault is 3917 * our fault as we did not reflect the write access in the 3918 * PTE. Now we know a write has occurred we can correct this 3919 * and also set the modified bit 3920 */ 3921 if ((pv->pv_flags & PVF_WRITE) == 0) { 3922 simple_unlock(&md->pvh_slock); 3923 goto out; 3924 } 3925 3926 NPDEBUG(PDB_FOLLOW, 3927 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3928 pm, va, pa)); 3929 3930 md->pvh_attrs |= PVF_REF | PVF_MOD; 3931 pv->pv_flags |= PVF_REF | PVF_MOD; 3932 #ifdef PMAP_CACHE_VIPT 3933 /* 3934 * If there are cacheable mappings for this page, mark it dirty. 3935 */ 3936 if ((md->pvh_attrs & PVF_NC) == 0) 3937 md->pvh_attrs |= PVF_DIRTY; 3938 #endif 3939 simple_unlock(&md->pvh_slock); 3940 3941 /* 3942 * Re-enable write permissions for the page. No need to call 3943 * pmap_vac_me_harder(), since this is just a 3944 * modified-emulation fault, and the PVF_WRITE bit isn't 3945 * changing. We've already set the cacheable bits based on 3946 * the assumption that we can write to this page. 3947 */ 3948 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3949 PTE_SYNC(ptep); 3950 rv = 1; 3951 } else 3952 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3953 /* 3954 * This looks like a good candidate for "page referenced" 3955 * emulation. 3956 */ 3957 struct pv_entry *pv; 3958 struct vm_page *pg; 3959 3960 /* Extract the physical address of the page */ 3961 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3962 goto out; 3963 3964 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3965 3966 /* Get the current flags for this page. */ 3967 simple_lock(&md->pvh_slock); 3968 3969 pv = pmap_find_pv(md, pm, va); 3970 if (pv == NULL) { 3971 simple_unlock(&md->pvh_slock); 3972 goto out; 3973 } 3974 3975 md->pvh_attrs |= PVF_REF; 3976 pv->pv_flags |= PVF_REF; 3977 simple_unlock(&md->pvh_slock); 3978 3979 NPDEBUG(PDB_FOLLOW, 3980 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3981 pm, va, pa)); 3982 3983 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3984 PTE_SYNC(ptep); 3985 rv = 1; 3986 } 3987 3988 /* 3989 * We know there is a valid mapping here, so simply 3990 * fix up the L1 if necessary. 3991 */ 3992 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3993 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3994 if (*pl1pd != l1pd) { 3995 *pl1pd = l1pd; 3996 PTE_SYNC(pl1pd); 3997 rv = 1; 3998 } 3999 4000 #ifdef CPU_SA110 4001 /* 4002 * There are bugs in the rev K SA110. This is a check for one 4003 * of them. 4004 */ 4005 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4006 curcpu()->ci_arm_cpurev < 3) { 4007 /* Always current pmap */ 4008 if (l2pte_valid(pte)) { 4009 extern int kernel_debug; 4010 if (kernel_debug & 1) { 4011 struct proc *p = curlwp->l_proc; 4012 printf("prefetch_abort: page is already " 4013 "mapped - pte=%p *pte=%08x\n", ptep, pte); 4014 printf("prefetch_abort: pc=%08lx proc=%p " 4015 "process=%s\n", va, p, p->p_comm); 4016 printf("prefetch_abort: far=%08x fs=%x\n", 4017 cpu_faultaddress(), cpu_faultstatus()); 4018 } 4019 #ifdef DDB 4020 if (kernel_debug & 2) 4021 Debugger(); 4022 #endif 4023 rv = 1; 4024 } 4025 } 4026 #endif /* CPU_SA110 */ 4027 4028 #ifdef DEBUG 4029 /* 4030 * If 'rv == 0' at this point, it generally indicates that there is a 4031 * stale TLB entry for the faulting address. This happens when two or 4032 * more processes are sharing an L1. Since we don't flush the TLB on 4033 * a context switch between such processes, we can take domain faults 4034 * for mappings which exist at the same VA in both processes. EVEN IF 4035 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4036 * example. 4037 * 4038 * This is extremely likely to happen if pmap_enter() updated the L1 4039 * entry for a recently entered mapping. In this case, the TLB is 4040 * flushed for the new mapping, but there may still be TLB entries for 4041 * other mappings belonging to other processes in the 1MB range 4042 * covered by the L1 entry. 4043 * 4044 * Since 'rv == 0', we know that the L1 already contains the correct 4045 * value, so the fault must be due to a stale TLB entry. 4046 * 4047 * Since we always need to flush the TLB anyway in the case where we 4048 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4049 * stale TLB entries dynamically. 4050 * 4051 * However, the above condition can ONLY happen if the current L1 is 4052 * being shared. If it happens when the L1 is unshared, it indicates 4053 * that other parts of the pmap are not doing their job WRT managing 4054 * the TLB. 4055 */ 4056 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4057 extern int last_fault_code; 4058 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4059 pm, va, ftype); 4060 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4061 l2, l2b, ptep, pl1pd); 4062 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4063 pte, l1pd, last_fault_code); 4064 #ifdef DDB 4065 Debugger(); 4066 #endif 4067 } 4068 #endif 4069 4070 cpu_tlb_flushID_SE(va); 4071 cpu_cpwait(); 4072 4073 rv = 1; 4074 4075 out: 4076 pmap_release_pmap_lock(pm); 4077 PMAP_MAP_TO_HEAD_UNLOCK(); 4078 4079 return (rv); 4080 } 4081 4082 /* 4083 * Routine: pmap_procwr 4084 * 4085 * Function: 4086 * Synchronize caches corresponding to [addr, addr+len) in p. 4087 * 4088 */ 4089 void 4090 pmap_procwr(struct proc *p, vaddr_t va, int len) 4091 { 4092 /* We only need to do anything if it is the current process. */ 4093 if (p == curproc) 4094 cpu_icache_sync_range(va, len); 4095 } 4096 4097 /* 4098 * Routine: pmap_unwire 4099 * Function: Clear the wired attribute for a map/virtual-address pair. 4100 * 4101 * In/out conditions: 4102 * The mapping must already exist in the pmap. 4103 */ 4104 void 4105 pmap_unwire(pmap_t pm, vaddr_t va) 4106 { 4107 struct l2_bucket *l2b; 4108 pt_entry_t *ptep, pte; 4109 struct vm_page *pg; 4110 paddr_t pa; 4111 4112 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4113 4114 PMAP_MAP_TO_HEAD_LOCK(); 4115 pmap_acquire_pmap_lock(pm); 4116 4117 l2b = pmap_get_l2_bucket(pm, va); 4118 KDASSERT(l2b != NULL); 4119 4120 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4121 pte = *ptep; 4122 4123 /* Extract the physical address of the page */ 4124 pa = l2pte_pa(pte); 4125 4126 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4127 /* Update the wired bit in the pv entry for this page. */ 4128 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4129 4130 simple_lock(&md->pvh_slock); 4131 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4132 simple_unlock(&md->pvh_slock); 4133 } 4134 4135 pmap_release_pmap_lock(pm); 4136 PMAP_MAP_TO_HEAD_UNLOCK(); 4137 } 4138 4139 void 4140 pmap_activate(struct lwp *l) 4141 { 4142 extern int block_userspace_access; 4143 pmap_t opm, npm, rpm; 4144 uint32_t odacr, ndacr; 4145 int oldirqstate; 4146 4147 /* 4148 * If activating a non-current lwp or the current lwp is 4149 * already active, just return. 4150 */ 4151 if (l != curlwp || 4152 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4153 return; 4154 4155 npm = l->l_proc->p_vmspace->vm_map.pmap; 4156 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4157 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4158 4159 /* 4160 * If TTB and DACR are unchanged, short-circuit all the 4161 * TLB/cache management stuff. 4162 */ 4163 if (pmap_previous_active_lwp != NULL) { 4164 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4165 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4166 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4167 4168 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4169 goto all_done; 4170 } else 4171 opm = NULL; 4172 4173 PMAPCOUNT(activations); 4174 block_userspace_access = 1; 4175 4176 /* 4177 * If switching to a user vmspace which is different to the 4178 * most recent one, and the most recent one is potentially 4179 * live in the cache, we must write-back and invalidate the 4180 * entire cache. 4181 */ 4182 rpm = pmap_recent_user; 4183 4184 /* 4185 * XXXSCW: There's a corner case here which can leave turds in the cache as 4186 * reported in kern/41058. They're probably left over during tear-down and 4187 * switching away from an exiting process. Until the root cause is identified 4188 * and fixed, zap the cache when switching pmaps. This will result in a few 4189 * unnecessary cache flushes, but that's better than silently corrupting data. 4190 */ 4191 #if 0 4192 if (npm != pmap_kernel() && rpm && npm != rpm && 4193 rpm->pm_cstate.cs_cache) { 4194 rpm->pm_cstate.cs_cache = 0; 4195 #ifdef PMAP_CACHE_VIVT 4196 cpu_idcache_wbinv_all(); 4197 #endif 4198 } 4199 #else 4200 if (rpm) { 4201 rpm->pm_cstate.cs_cache = 0; 4202 if (npm == pmap_kernel()) 4203 pmap_recent_user = NULL; 4204 #ifdef PMAP_CACHE_VIVT 4205 cpu_idcache_wbinv_all(); 4206 #endif 4207 } 4208 #endif 4209 4210 /* No interrupts while we frob the TTB/DACR */ 4211 oldirqstate = disable_interrupts(IF32_bits); 4212 4213 /* 4214 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4215 * entry corresponding to 'vector_page' in the incoming L1 table 4216 * before switching to it otherwise subsequent interrupts/exceptions 4217 * (including domain faults!) will jump into hyperspace. 4218 */ 4219 if (npm->pm_pl1vec != NULL) { 4220 cpu_tlb_flushID_SE((u_int)vector_page); 4221 cpu_cpwait(); 4222 *npm->pm_pl1vec = npm->pm_l1vec; 4223 PTE_SYNC(npm->pm_pl1vec); 4224 } 4225 4226 cpu_domains(ndacr); 4227 4228 if (npm == pmap_kernel() || npm == rpm) { 4229 /* 4230 * Switching to a kernel thread, or back to the 4231 * same user vmspace as before... Simply update 4232 * the TTB (no TLB flush required) 4233 */ 4234 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4235 "r"(npm->pm_l1->l1_physaddr)); 4236 cpu_cpwait(); 4237 } else { 4238 /* 4239 * Otherwise, update TTB and flush TLB 4240 */ 4241 cpu_context_switch(npm->pm_l1->l1_physaddr); 4242 if (rpm != NULL) 4243 rpm->pm_cstate.cs_tlb = 0; 4244 } 4245 4246 restore_interrupts(oldirqstate); 4247 4248 block_userspace_access = 0; 4249 4250 all_done: 4251 /* 4252 * The new pmap is resident. Make sure it's marked 4253 * as resident in the cache/TLB. 4254 */ 4255 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4256 if (npm != pmap_kernel()) 4257 pmap_recent_user = npm; 4258 4259 /* The old pmap is not longer active */ 4260 if (opm != NULL) 4261 opm->pm_activated = false; 4262 4263 /* But the new one is */ 4264 npm->pm_activated = true; 4265 } 4266 4267 void 4268 pmap_deactivate(struct lwp *l) 4269 { 4270 4271 /* 4272 * If the process is exiting, make sure pmap_activate() does 4273 * a full MMU context-switch and cache flush, which we might 4274 * otherwise skip. See PR port-arm/38950. 4275 */ 4276 if (l->l_proc->p_sflag & PS_WEXIT) 4277 pmap_previous_active_lwp = NULL; 4278 4279 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4280 } 4281 4282 void 4283 pmap_update(pmap_t pm) 4284 { 4285 4286 if (pm->pm_remove_all) { 4287 /* 4288 * Finish up the pmap_remove_all() optimisation by flushing 4289 * the TLB. 4290 */ 4291 pmap_tlb_flushID(pm); 4292 pm->pm_remove_all = false; 4293 } 4294 4295 if (pmap_is_current(pm)) { 4296 /* 4297 * If we're dealing with a current userland pmap, move its L1 4298 * to the end of the LRU. 4299 */ 4300 if (pm != pmap_kernel()) 4301 pmap_use_l1(pm); 4302 4303 /* 4304 * We can assume we're done with frobbing the cache/tlb for 4305 * now. Make sure any future pmap ops don't skip cache/tlb 4306 * flushes. 4307 */ 4308 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4309 } 4310 4311 PMAPCOUNT(updates); 4312 4313 /* 4314 * make sure TLB/cache operations have completed. 4315 */ 4316 cpu_cpwait(); 4317 } 4318 4319 void 4320 pmap_remove_all(pmap_t pm) 4321 { 4322 4323 /* 4324 * The vmspace described by this pmap is about to be torn down. 4325 * Until pmap_update() is called, UVM will only make calls 4326 * to pmap_remove(). We can make life much simpler by flushing 4327 * the cache now, and deferring TLB invalidation to pmap_update(). 4328 */ 4329 #ifdef PMAP_CACHE_VIVT 4330 pmap_idcache_wbinv_all(pm); 4331 #endif 4332 pm->pm_remove_all = true; 4333 } 4334 4335 /* 4336 * Retire the given physical map from service. 4337 * Should only be called if the map contains no valid mappings. 4338 */ 4339 void 4340 pmap_destroy(pmap_t pm) 4341 { 4342 u_int count; 4343 4344 if (pm == NULL) 4345 return; 4346 4347 if (pm->pm_remove_all) { 4348 pmap_tlb_flushID(pm); 4349 pm->pm_remove_all = false; 4350 } 4351 4352 /* 4353 * Drop reference count 4354 */ 4355 mutex_enter(pm->pm_lock); 4356 count = --pm->pm_obj.uo_refs; 4357 mutex_exit(pm->pm_lock); 4358 if (count > 0) { 4359 if (pmap_is_current(pm)) { 4360 if (pm != pmap_kernel()) 4361 pmap_use_l1(pm); 4362 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4363 } 4364 return; 4365 } 4366 4367 /* 4368 * reference count is zero, free pmap resources and then free pmap. 4369 */ 4370 4371 if (vector_page < KERNEL_BASE) { 4372 KDASSERT(!pmap_is_current(pm)); 4373 4374 /* Remove the vector page mapping */ 4375 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4376 pmap_update(pm); 4377 } 4378 4379 LIST_REMOVE(pm, pm_list); 4380 4381 pmap_free_l1(pm); 4382 4383 if (pmap_recent_user == pm) 4384 pmap_recent_user = NULL; 4385 4386 uvm_obj_destroy(&pm->pm_obj, false); 4387 mutex_destroy(&pm->pm_obj_lock); 4388 pool_cache_put(&pmap_cache, pm); 4389 } 4390 4391 4392 /* 4393 * void pmap_reference(pmap_t pm) 4394 * 4395 * Add a reference to the specified pmap. 4396 */ 4397 void 4398 pmap_reference(pmap_t pm) 4399 { 4400 4401 if (pm == NULL) 4402 return; 4403 4404 pmap_use_l1(pm); 4405 4406 mutex_enter(pm->pm_lock); 4407 pm->pm_obj.uo_refs++; 4408 mutex_exit(pm->pm_lock); 4409 } 4410 4411 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4412 4413 static struct evcnt pmap_prefer_nochange_ev = 4414 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4415 static struct evcnt pmap_prefer_change_ev = 4416 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4417 4418 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4419 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4420 4421 void 4422 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4423 { 4424 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4425 vaddr_t va = *vap; 4426 vaddr_t diff = (hint - va) & mask; 4427 if (diff == 0) { 4428 pmap_prefer_nochange_ev.ev_count++; 4429 } else { 4430 pmap_prefer_change_ev.ev_count++; 4431 if (__predict_false(td)) 4432 va -= mask + 1; 4433 *vap = va + diff; 4434 } 4435 } 4436 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4437 4438 /* 4439 * pmap_zero_page() 4440 * 4441 * Zero a given physical page by mapping it at a page hook point. 4442 * In doing the zero page op, the page we zero is mapped cachable, as with 4443 * StrongARM accesses to non-cached pages are non-burst making writing 4444 * _any_ bulk data very slow. 4445 */ 4446 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4447 void 4448 pmap_zero_page_generic(paddr_t phys) 4449 { 4450 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4451 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4452 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4453 #endif 4454 #ifdef PMAP_CACHE_VIPT 4455 /* Choose the last page color it had, if any */ 4456 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4457 #else 4458 const vsize_t va_offset = 0; 4459 #endif 4460 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4461 4462 #ifdef DEBUG 4463 if (!SLIST_EMPTY(&md->pvh_list)) 4464 panic("pmap_zero_page: page has mappings"); 4465 #endif 4466 4467 KDASSERT((phys & PGOFSET) == 0); 4468 4469 /* 4470 * Hook in the page, zero it, and purge the cache for that 4471 * zeroed page. Invalidate the TLB as needed. 4472 */ 4473 *ptep = L2_S_PROTO | phys | 4474 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4475 PTE_SYNC(ptep); 4476 cpu_tlb_flushD_SE(cdstp + va_offset); 4477 cpu_cpwait(); 4478 bzero_page(cdstp + va_offset); 4479 /* 4480 * Unmap the page. 4481 */ 4482 *ptep = 0; 4483 PTE_SYNC(ptep); 4484 cpu_tlb_flushD_SE(cdstp + va_offset); 4485 #ifdef PMAP_CACHE_VIVT 4486 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4487 #endif 4488 #ifdef PMAP_CACHE_VIPT 4489 /* 4490 * This page is now cache resident so it now has a page color. 4491 * Any contents have been obliterated so clear the EXEC flag. 4492 */ 4493 if (!pmap_is_page_colored_p(md)) { 4494 PMAPCOUNT(vac_color_new); 4495 md->pvh_attrs |= PVF_COLORED; 4496 } 4497 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4498 md->pvh_attrs &= ~PVF_EXEC; 4499 PMAPCOUNT(exec_discarded_zero); 4500 } 4501 md->pvh_attrs |= PVF_DIRTY; 4502 #endif 4503 } 4504 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4505 4506 #if ARM_MMU_XSCALE == 1 4507 void 4508 pmap_zero_page_xscale(paddr_t phys) 4509 { 4510 #ifdef DEBUG 4511 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4512 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4513 4514 if (!SLIST_EMPTY(&md->pvh_list)) 4515 panic("pmap_zero_page: page has mappings"); 4516 #endif 4517 4518 KDASSERT((phys & PGOFSET) == 0); 4519 4520 /* 4521 * Hook in the page, zero it, and purge the cache for that 4522 * zeroed page. Invalidate the TLB as needed. 4523 */ 4524 *cdst_pte = L2_S_PROTO | phys | 4525 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4526 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4527 PTE_SYNC(cdst_pte); 4528 cpu_tlb_flushD_SE(cdstp); 4529 cpu_cpwait(); 4530 bzero_page(cdstp); 4531 xscale_cache_clean_minidata(); 4532 } 4533 #endif /* ARM_MMU_XSCALE == 1 */ 4534 4535 /* pmap_pageidlezero() 4536 * 4537 * The same as above, except that we assume that the page is not 4538 * mapped. This means we never have to flush the cache first. Called 4539 * from the idle loop. 4540 */ 4541 bool 4542 pmap_pageidlezero(paddr_t phys) 4543 { 4544 unsigned int i; 4545 int *ptr; 4546 bool rv = true; 4547 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4548 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4549 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4550 #endif 4551 #ifdef PMAP_CACHE_VIPT 4552 /* Choose the last page color it had, if any */ 4553 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4554 #else 4555 const vsize_t va_offset = 0; 4556 #endif 4557 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4558 4559 4560 #ifdef DEBUG 4561 if (!SLIST_EMPTY(&md->pvh_list)) 4562 panic("pmap_pageidlezero: page has mappings"); 4563 #endif 4564 4565 KDASSERT((phys & PGOFSET) == 0); 4566 4567 /* 4568 * Hook in the page, zero it, and purge the cache for that 4569 * zeroed page. Invalidate the TLB as needed. 4570 */ 4571 *ptep = L2_S_PROTO | phys | 4572 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4573 PTE_SYNC(ptep); 4574 cpu_tlb_flushD_SE(cdstp + va_offset); 4575 cpu_cpwait(); 4576 4577 for (i = 0, ptr = (int *)(cdstp + va_offset); 4578 i < (PAGE_SIZE / sizeof(int)); i++) { 4579 if (sched_curcpu_runnable_p() != 0) { 4580 /* 4581 * A process has become ready. Abort now, 4582 * so we don't keep it waiting while we 4583 * do slow memory access to finish this 4584 * page. 4585 */ 4586 rv = false; 4587 break; 4588 } 4589 *ptr++ = 0; 4590 } 4591 4592 #ifdef PMAP_CACHE_VIVT 4593 if (rv) 4594 /* 4595 * if we aborted we'll rezero this page again later so don't 4596 * purge it unless we finished it 4597 */ 4598 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4599 #elif defined(PMAP_CACHE_VIPT) 4600 /* 4601 * This page is now cache resident so it now has a page color. 4602 * Any contents have been obliterated so clear the EXEC flag. 4603 */ 4604 if (!pmap_is_page_colored_p(md)) { 4605 PMAPCOUNT(vac_color_new); 4606 md->pvh_attrs |= PVF_COLORED; 4607 } 4608 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4609 md->pvh_attrs &= ~PVF_EXEC; 4610 PMAPCOUNT(exec_discarded_zero); 4611 } 4612 #endif 4613 /* 4614 * Unmap the page. 4615 */ 4616 *ptep = 0; 4617 PTE_SYNC(ptep); 4618 cpu_tlb_flushD_SE(cdstp + va_offset); 4619 4620 return (rv); 4621 } 4622 4623 /* 4624 * pmap_copy_page() 4625 * 4626 * Copy one physical page into another, by mapping the pages into 4627 * hook points. The same comment regarding cachability as in 4628 * pmap_zero_page also applies here. 4629 */ 4630 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4631 void 4632 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4633 { 4634 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4635 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4636 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4637 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4638 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4639 #endif 4640 #ifdef PMAP_CACHE_VIPT 4641 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4642 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4643 #else 4644 const vsize_t src_va_offset = 0; 4645 const vsize_t dst_va_offset = 0; 4646 #endif 4647 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4648 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4649 4650 #ifdef DEBUG 4651 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4652 panic("pmap_copy_page: dst page has mappings"); 4653 #endif 4654 4655 #ifdef PMAP_CACHE_VIPT 4656 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4657 #endif 4658 KDASSERT((src & PGOFSET) == 0); 4659 KDASSERT((dst & PGOFSET) == 0); 4660 4661 /* 4662 * Clean the source page. Hold the source page's lock for 4663 * the duration of the copy so that no other mappings can 4664 * be created while we have a potentially aliased mapping. 4665 */ 4666 simple_lock(&src_md->pvh_slock); 4667 #ifdef PMAP_CACHE_VIVT 4668 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4669 #endif 4670 4671 /* 4672 * Map the pages into the page hook points, copy them, and purge 4673 * the cache for the appropriate page. Invalidate the TLB 4674 * as required. 4675 */ 4676 *src_ptep = L2_S_PROTO 4677 | src 4678 #ifdef PMAP_CACHE_VIPT 4679 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4680 #endif 4681 #ifdef PMAP_CACHE_VIVT 4682 | pte_l2_s_cache_mode 4683 #endif 4684 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4685 *dst_ptep = L2_S_PROTO | dst | 4686 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4687 PTE_SYNC(src_ptep); 4688 PTE_SYNC(dst_ptep); 4689 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4690 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4691 cpu_cpwait(); 4692 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4693 #ifdef PMAP_CACHE_VIVT 4694 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4695 #endif 4696 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4697 #ifdef PMAP_CACHE_VIVT 4698 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4699 #endif 4700 /* 4701 * Unmap the pages. 4702 */ 4703 *src_ptep = 0; 4704 *dst_ptep = 0; 4705 PTE_SYNC(src_ptep); 4706 PTE_SYNC(dst_ptep); 4707 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4708 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4709 #ifdef PMAP_CACHE_VIPT 4710 /* 4711 * Now that the destination page is in the cache, mark it as colored. 4712 * If this was an exec page, discard it. 4713 */ 4714 if (!pmap_is_page_colored_p(dst_md)) { 4715 PMAPCOUNT(vac_color_new); 4716 dst_md->pvh_attrs |= PVF_COLORED; 4717 } 4718 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4719 dst_md->pvh_attrs &= ~PVF_EXEC; 4720 PMAPCOUNT(exec_discarded_copy); 4721 } 4722 dst_md->pvh_attrs |= PVF_DIRTY; 4723 #endif 4724 } 4725 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4726 4727 #if ARM_MMU_XSCALE == 1 4728 void 4729 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4730 { 4731 struct vm_page_md *src_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(src)); 4732 #ifdef DEBUG 4733 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4734 4735 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4736 panic("pmap_copy_page: dst page has mappings"); 4737 #endif 4738 4739 KDASSERT((src & PGOFSET) == 0); 4740 KDASSERT((dst & PGOFSET) == 0); 4741 4742 /* 4743 * Clean the source page. Hold the source page's lock for 4744 * the duration of the copy so that no other mappings can 4745 * be created while we have a potentially aliased mapping. 4746 */ 4747 simple_lock(&src_md->pvh_slock); 4748 #ifdef PMAP_CACHE_VIVT 4749 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4750 #endif 4751 4752 /* 4753 * Map the pages into the page hook points, copy them, and purge 4754 * the cache for the appropriate page. Invalidate the TLB 4755 * as required. 4756 */ 4757 *csrc_pte = L2_S_PROTO | src | 4758 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4759 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4760 PTE_SYNC(csrc_pte); 4761 *cdst_pte = L2_S_PROTO | dst | 4762 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4763 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4764 PTE_SYNC(cdst_pte); 4765 cpu_tlb_flushD_SE(csrcp); 4766 cpu_tlb_flushD_SE(cdstp); 4767 cpu_cpwait(); 4768 bcopy_page(csrcp, cdstp); 4769 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4770 xscale_cache_clean_minidata(); 4771 } 4772 #endif /* ARM_MMU_XSCALE == 1 */ 4773 4774 /* 4775 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4776 * 4777 * Return the start and end addresses of the kernel's virtual space. 4778 * These values are setup in pmap_bootstrap and are updated as pages 4779 * are allocated. 4780 */ 4781 void 4782 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4783 { 4784 *start = virtual_avail; 4785 *end = virtual_end; 4786 } 4787 4788 /* 4789 * Helper function for pmap_grow_l2_bucket() 4790 */ 4791 static inline int 4792 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4793 { 4794 struct l2_bucket *l2b; 4795 pt_entry_t *ptep; 4796 paddr_t pa; 4797 4798 if (uvm.page_init_done == false) { 4799 #ifdef PMAP_STEAL_MEMORY 4800 pv_addr_t pv; 4801 pmap_boot_pagealloc(PAGE_SIZE, 4802 #ifdef PMAP_CACHE_VIPT 4803 arm_cache_prefer_mask, 4804 va & arm_cache_prefer_mask, 4805 #else 4806 0, 0, 4807 #endif 4808 &pv); 4809 pa = pv.pv_pa; 4810 #else 4811 if (uvm_page_physget(&pa) == false) 4812 return (1); 4813 #endif /* PMAP_STEAL_MEMORY */ 4814 } else { 4815 struct vm_page *pg; 4816 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4817 if (pg == NULL) 4818 return (1); 4819 pa = VM_PAGE_TO_PHYS(pg); 4820 #ifdef PMAP_CACHE_VIPT 4821 #ifdef DIAGNOSTIC 4822 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4823 #endif 4824 /* 4825 * This new page must not have any mappings. Enter it via 4826 * pmap_kenter_pa and let that routine do the hard work. 4827 */ 4828 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4829 pmap_kenter_pa(va, pa, 4830 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4831 #endif 4832 } 4833 4834 if (pap) 4835 *pap = pa; 4836 4837 PMAPCOUNT(pt_mappings); 4838 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4839 KDASSERT(l2b != NULL); 4840 4841 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4842 *ptep = L2_S_PROTO | pa | cache_mode | 4843 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4844 PTE_SYNC(ptep); 4845 memset((void *)va, 0, PAGE_SIZE); 4846 return (0); 4847 } 4848 4849 /* 4850 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4851 * used by pmap_growkernel(). 4852 */ 4853 static inline struct l2_bucket * 4854 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4855 { 4856 struct l2_dtable *l2; 4857 struct l2_bucket *l2b; 4858 u_short l1idx; 4859 vaddr_t nva; 4860 4861 l1idx = L1_IDX(va); 4862 4863 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4864 /* 4865 * No mapping at this address, as there is 4866 * no entry in the L1 table. 4867 * Need to allocate a new l2_dtable. 4868 */ 4869 nva = pmap_kernel_l2dtable_kva; 4870 if ((nva & PGOFSET) == 0) { 4871 /* 4872 * Need to allocate a backing page 4873 */ 4874 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4875 return (NULL); 4876 } 4877 4878 l2 = (struct l2_dtable *)nva; 4879 nva += sizeof(struct l2_dtable); 4880 4881 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4882 /* 4883 * The new l2_dtable straddles a page boundary. 4884 * Map in another page to cover it. 4885 */ 4886 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4887 return (NULL); 4888 } 4889 4890 pmap_kernel_l2dtable_kva = nva; 4891 4892 /* 4893 * Link it into the parent pmap 4894 */ 4895 pm->pm_l2[L2_IDX(l1idx)] = l2; 4896 } 4897 4898 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4899 4900 /* 4901 * Fetch pointer to the L2 page table associated with the address. 4902 */ 4903 if (l2b->l2b_kva == NULL) { 4904 pt_entry_t *ptep; 4905 4906 /* 4907 * No L2 page table has been allocated. Chances are, this 4908 * is because we just allocated the l2_dtable, above. 4909 */ 4910 nva = pmap_kernel_l2ptp_kva; 4911 ptep = (pt_entry_t *)nva; 4912 if ((nva & PGOFSET) == 0) { 4913 /* 4914 * Need to allocate a backing page 4915 */ 4916 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4917 &pmap_kernel_l2ptp_phys)) 4918 return (NULL); 4919 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4920 } 4921 4922 l2->l2_occupancy++; 4923 l2b->l2b_kva = ptep; 4924 l2b->l2b_l1idx = l1idx; 4925 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4926 4927 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4928 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4929 } 4930 4931 return (l2b); 4932 } 4933 4934 vaddr_t 4935 pmap_growkernel(vaddr_t maxkvaddr) 4936 { 4937 pmap_t kpm = pmap_kernel(); 4938 struct l1_ttable *l1; 4939 struct l2_bucket *l2b; 4940 pd_entry_t *pl1pd; 4941 int s; 4942 4943 if (maxkvaddr <= pmap_curmaxkvaddr) 4944 goto out; /* we are OK */ 4945 4946 NPDEBUG(PDB_GROWKERN, 4947 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4948 pmap_curmaxkvaddr, maxkvaddr)); 4949 4950 KDASSERT(maxkvaddr <= virtual_end); 4951 4952 /* 4953 * whoops! we need to add kernel PTPs 4954 */ 4955 4956 s = splhigh(); /* to be safe */ 4957 mutex_enter(kpm->pm_lock); 4958 4959 /* Map 1MB at a time */ 4960 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4961 4962 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4963 KDASSERT(l2b != NULL); 4964 4965 /* Distribute new L1 entry to all other L1s */ 4966 SLIST_FOREACH(l1, &l1_list, l1_link) { 4967 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4968 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4969 L1_C_PROTO; 4970 PTE_SYNC(pl1pd); 4971 } 4972 } 4973 4974 /* 4975 * flush out the cache, expensive but growkernel will happen so 4976 * rarely 4977 */ 4978 cpu_dcache_wbinv_all(); 4979 cpu_tlb_flushD(); 4980 cpu_cpwait(); 4981 4982 mutex_exit(kpm->pm_lock); 4983 splx(s); 4984 4985 out: 4986 return (pmap_curmaxkvaddr); 4987 } 4988 4989 /************************ Utility routines ****************************/ 4990 4991 /* 4992 * vector_page_setprot: 4993 * 4994 * Manipulate the protection of the vector page. 4995 */ 4996 void 4997 vector_page_setprot(int prot) 4998 { 4999 struct l2_bucket *l2b; 5000 pt_entry_t *ptep; 5001 5002 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5003 KDASSERT(l2b != NULL); 5004 5005 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5006 5007 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 5008 PTE_SYNC(ptep); 5009 cpu_tlb_flushD_SE(vector_page); 5010 cpu_cpwait(); 5011 } 5012 5013 /* 5014 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5015 * Returns true if the mapping exists, else false. 5016 * 5017 * NOTE: This function is only used by a couple of arm-specific modules. 5018 * It is not safe to take any pmap locks here, since we could be right 5019 * in the middle of debugging the pmap anyway... 5020 * 5021 * It is possible for this routine to return false even though a valid 5022 * mapping does exist. This is because we don't lock, so the metadata 5023 * state may be inconsistent. 5024 * 5025 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5026 * a "section" mapping. 5027 */ 5028 bool 5029 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5030 { 5031 struct l2_dtable *l2; 5032 pd_entry_t *pl1pd, l1pd; 5033 pt_entry_t *ptep; 5034 u_short l1idx; 5035 5036 if (pm->pm_l1 == NULL) 5037 return false; 5038 5039 l1idx = L1_IDX(va); 5040 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5041 l1pd = *pl1pd; 5042 5043 if (l1pte_section_p(l1pd)) { 5044 *ptp = NULL; 5045 return true; 5046 } 5047 5048 if (pm->pm_l2 == NULL) 5049 return false; 5050 5051 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5052 5053 if (l2 == NULL || 5054 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5055 return false; 5056 } 5057 5058 *ptp = &ptep[l2pte_index(va)]; 5059 return true; 5060 } 5061 5062 bool 5063 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5064 { 5065 u_short l1idx; 5066 5067 if (pm->pm_l1 == NULL) 5068 return false; 5069 5070 l1idx = L1_IDX(va); 5071 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5072 5073 return true; 5074 } 5075 5076 /************************ Bootstrapping routines ****************************/ 5077 5078 static void 5079 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5080 { 5081 int i; 5082 5083 l1->l1_kva = l1pt; 5084 l1->l1_domain_use_count = 0; 5085 l1->l1_domain_first = 0; 5086 5087 for (i = 0; i < PMAP_DOMAINS; i++) 5088 l1->l1_domain_free[i] = i + 1; 5089 5090 /* 5091 * Copy the kernel's L1 entries to each new L1. 5092 */ 5093 if (pmap_initialized) 5094 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5095 5096 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5097 &l1->l1_physaddr) == false) 5098 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5099 5100 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5101 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5102 } 5103 5104 /* 5105 * pmap_bootstrap() is called from the board-specific initarm() routine 5106 * once the kernel L1/L2 descriptors tables have been set up. 5107 * 5108 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5109 * spread over a number of disparate files/functions. 5110 * 5111 * We are passed the following parameters 5112 * - kernel_l1pt 5113 * This is a pointer to the base of the kernel's L1 translation table. 5114 * - vstart 5115 * 1MB-aligned start of managed kernel virtual memory. 5116 * - vend 5117 * 1MB-aligned end of managed kernel virtual memory. 5118 * 5119 * We use the first parameter to build the metadata (struct l1_ttable and 5120 * struct l2_dtable) necessary to track kernel mappings. 5121 */ 5122 #define PMAP_STATIC_L2_SIZE 16 5123 void 5124 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5125 { 5126 static struct l1_ttable static_l1; 5127 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5128 struct l1_ttable *l1 = &static_l1; 5129 struct l2_dtable *l2; 5130 struct l2_bucket *l2b; 5131 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5132 pmap_t pm = pmap_kernel(); 5133 pd_entry_t pde; 5134 pt_entry_t *ptep; 5135 paddr_t pa; 5136 vaddr_t va; 5137 vsize_t size; 5138 int nptes, l1idx, l2idx, l2next = 0; 5139 5140 /* 5141 * Initialise the kernel pmap object 5142 */ 5143 pm->pm_l1 = l1; 5144 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5145 pm->pm_activated = true; 5146 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5147 5148 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5149 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5150 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5151 5152 /* 5153 * Scan the L1 translation table created by initarm() and create 5154 * the required metadata for all valid mappings found in it. 5155 */ 5156 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5157 pde = l1pt[l1idx]; 5158 5159 /* 5160 * We're only interested in Coarse mappings. 5161 * pmap_extract() can deal with section mappings without 5162 * recourse to checking L2 metadata. 5163 */ 5164 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5165 continue; 5166 5167 /* 5168 * Lookup the KVA of this L2 descriptor table 5169 */ 5170 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5171 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5172 if (ptep == NULL) { 5173 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5174 (u_int)l1idx << L1_S_SHIFT, pa); 5175 } 5176 5177 /* 5178 * Fetch the associated L2 metadata structure. 5179 * Allocate a new one if necessary. 5180 */ 5181 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5182 if (l2next == PMAP_STATIC_L2_SIZE) 5183 panic("pmap_bootstrap: out of static L2s"); 5184 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5185 } 5186 5187 /* 5188 * One more L1 slot tracked... 5189 */ 5190 l2->l2_occupancy++; 5191 5192 /* 5193 * Fill in the details of the L2 descriptor in the 5194 * appropriate bucket. 5195 */ 5196 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5197 l2b->l2b_kva = ptep; 5198 l2b->l2b_phys = pa; 5199 l2b->l2b_l1idx = l1idx; 5200 5201 /* 5202 * Establish an initial occupancy count for this descriptor 5203 */ 5204 for (l2idx = 0; 5205 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5206 l2idx++) { 5207 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5208 l2b->l2b_occupancy++; 5209 } 5210 } 5211 5212 /* 5213 * Make sure the descriptor itself has the correct cache mode. 5214 * If not, fix it, but whine about the problem. Port-meisters 5215 * should consider this a clue to fix up their initarm() 5216 * function. :) 5217 */ 5218 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5219 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5220 "L2 pte @ %p\n", ptep); 5221 } 5222 } 5223 5224 /* 5225 * Ensure the primary (kernel) L1 has the correct cache mode for 5226 * a page table. Bitch if it is not correctly set. 5227 */ 5228 for (va = (vaddr_t)l1pt; 5229 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5230 if (pmap_set_pt_cache_mode(l1pt, va)) 5231 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5232 "primary L1 @ 0x%lx\n", va); 5233 } 5234 5235 cpu_dcache_wbinv_all(); 5236 cpu_tlb_flushID(); 5237 cpu_cpwait(); 5238 5239 /* 5240 * now we allocate the "special" VAs which are used for tmp mappings 5241 * by the pmap (and other modules). we allocate the VAs by advancing 5242 * virtual_avail (note that there are no pages mapped at these VAs). 5243 * 5244 * Managed KVM space start from wherever initarm() tells us. 5245 */ 5246 virtual_avail = vstart; 5247 virtual_end = vend; 5248 5249 #ifdef PMAP_CACHE_VIPT 5250 /* 5251 * If we have a VIPT cache, we need one page/pte per possible alias 5252 * page so we won't violate cache aliasing rules. 5253 */ 5254 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5255 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5256 #else 5257 nptes = 1; 5258 #endif 5259 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5260 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5261 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5262 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5263 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5264 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5265 (void *)&msgbufaddr, NULL); 5266 5267 /* 5268 * Allocate a range of kernel virtual address space to be used 5269 * for L2 descriptor tables and metadata allocation in 5270 * pmap_growkernel(). 5271 */ 5272 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5273 pmap_alloc_specials(&virtual_avail, 5274 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5275 &pmap_kernel_l2ptp_kva, NULL); 5276 5277 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5278 pmap_alloc_specials(&virtual_avail, 5279 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5280 &pmap_kernel_l2dtable_kva, NULL); 5281 5282 /* 5283 * init the static-global locks and global pmap list. 5284 */ 5285 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5286 5287 /* 5288 * We can now initialise the first L1's metadata. 5289 */ 5290 SLIST_INIT(&l1_list); 5291 TAILQ_INIT(&l1_lru_list); 5292 simple_lock_init(&l1_lru_lock); 5293 pmap_init_l1(l1, l1pt); 5294 5295 /* Set up vector page L1 details, if necessary */ 5296 if (vector_page < KERNEL_BASE) { 5297 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5298 l2b = pmap_get_l2_bucket(pm, vector_page); 5299 KDASSERT(l2b != NULL); 5300 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5301 L1_C_DOM(pm->pm_domain); 5302 } else 5303 pm->pm_pl1vec = NULL; 5304 5305 /* 5306 * Initialize the pmap cache 5307 */ 5308 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5309 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5310 LIST_INIT(&pmap_pmaps); 5311 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5312 5313 /* 5314 * Initialize the pv pool. 5315 */ 5316 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5317 &pmap_bootstrap_pv_allocator, IPL_NONE); 5318 5319 /* 5320 * Initialize the L2 dtable pool and cache. 5321 */ 5322 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5323 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5324 5325 /* 5326 * Initialise the L2 descriptor table pool and cache 5327 */ 5328 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5329 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5330 pmap_l2ptp_ctor, NULL, NULL); 5331 5332 cpu_dcache_wbinv_all(); 5333 } 5334 5335 static int 5336 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5337 { 5338 pd_entry_t *pdep, pde; 5339 pt_entry_t *ptep, pte; 5340 vaddr_t pa; 5341 int rv = 0; 5342 5343 /* 5344 * Make sure the descriptor itself has the correct cache mode 5345 */ 5346 pdep = &kl1[L1_IDX(va)]; 5347 pde = *pdep; 5348 5349 if (l1pte_section_p(pde)) { 5350 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5351 *pdep = (pde & ~L1_S_CACHE_MASK) | 5352 pte_l1_s_cache_mode_pt; 5353 PTE_SYNC(pdep); 5354 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5355 rv = 1; 5356 } 5357 } else { 5358 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5359 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5360 if (ptep == NULL) 5361 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5362 5363 ptep = &ptep[l2pte_index(va)]; 5364 pte = *ptep; 5365 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5366 *ptep = (pte & ~L2_S_CACHE_MASK) | 5367 pte_l2_s_cache_mode_pt; 5368 PTE_SYNC(ptep); 5369 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5370 rv = 1; 5371 } 5372 } 5373 5374 return (rv); 5375 } 5376 5377 static void 5378 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5379 { 5380 vaddr_t va = *availp; 5381 struct l2_bucket *l2b; 5382 5383 if (ptep) { 5384 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5385 if (l2b == NULL) 5386 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5387 5388 if (ptep) 5389 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5390 } 5391 5392 *vap = va; 5393 *availp = va + (PAGE_SIZE * pages); 5394 } 5395 5396 void 5397 pmap_init(void) 5398 { 5399 5400 /* 5401 * Set the available memory vars - These do not map to real memory 5402 * addresses and cannot as the physical memory is fragmented. 5403 * They are used by ps for %mem calculations. 5404 * One could argue whether this should be the entire memory or just 5405 * the memory that is useable in a user process. 5406 */ 5407 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5408 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5409 5410 /* 5411 * Now we need to free enough pv_entry structures to allow us to get 5412 * the kmem_map/kmem_object allocated and inited (done after this 5413 * function is finished). to do this we allocate one bootstrap page out 5414 * of kernel_map and use it to provide an initial pool of pv_entry 5415 * structures. we never free this page. 5416 */ 5417 pool_setlowat(&pmap_pv_pool, 5418 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5419 5420 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5421 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5422 UVM_KMF_WIRED|UVM_KMF_ZERO); 5423 5424 pmap_initialized = true; 5425 } 5426 5427 static vaddr_t last_bootstrap_page = 0; 5428 static void *free_bootstrap_pages = NULL; 5429 5430 static void * 5431 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5432 { 5433 extern void *pool_page_alloc(struct pool *, int); 5434 vaddr_t new_page; 5435 void *rv; 5436 5437 if (pmap_initialized) 5438 return (pool_page_alloc(pp, flags)); 5439 5440 if (free_bootstrap_pages) { 5441 rv = free_bootstrap_pages; 5442 free_bootstrap_pages = *((void **)rv); 5443 return (rv); 5444 } 5445 5446 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5447 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5448 5449 KASSERT(new_page > last_bootstrap_page); 5450 last_bootstrap_page = new_page; 5451 return ((void *)new_page); 5452 } 5453 5454 static void 5455 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5456 { 5457 extern void pool_page_free(struct pool *, void *); 5458 5459 if ((vaddr_t)v <= last_bootstrap_page) { 5460 *((void **)v) = free_bootstrap_pages; 5461 free_bootstrap_pages = v; 5462 return; 5463 } 5464 5465 if (pmap_initialized) { 5466 pool_page_free(pp, v); 5467 return; 5468 } 5469 } 5470 5471 /* 5472 * pmap_postinit() 5473 * 5474 * This routine is called after the vm and kmem subsystems have been 5475 * initialised. This allows the pmap code to perform any initialisation 5476 * that can only be done one the memory allocation is in place. 5477 */ 5478 void 5479 pmap_postinit(void) 5480 { 5481 extern paddr_t physical_start, physical_end; 5482 struct l2_bucket *l2b; 5483 struct l1_ttable *l1; 5484 struct pglist plist; 5485 struct vm_page *m; 5486 pd_entry_t *pl1pt; 5487 pt_entry_t *ptep, pte; 5488 vaddr_t va, eva; 5489 u_int loop, needed; 5490 int error; 5491 5492 pool_cache_setlowat(&pmap_l2ptp_cache, 5493 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5494 pool_cache_setlowat(&pmap_l2dtable_cache, 5495 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5496 5497 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5498 needed -= 1; 5499 5500 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 5501 5502 for (loop = 0; loop < needed; loop++, l1++) { 5503 /* Allocate a L1 page table */ 5504 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5505 if (va == 0) 5506 panic("Cannot allocate L1 KVM"); 5507 5508 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5509 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 5510 if (error) 5511 panic("Cannot allocate L1 physical pages"); 5512 5513 m = TAILQ_FIRST(&plist); 5514 eva = va + L1_TABLE_SIZE; 5515 pl1pt = (pd_entry_t *)va; 5516 5517 while (m && va < eva) { 5518 paddr_t pa = VM_PAGE_TO_PHYS(m); 5519 5520 pmap_kenter_pa(va, pa, 5521 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5522 5523 /* 5524 * Make sure the L1 descriptor table is mapped 5525 * with the cache-mode set to write-through. 5526 */ 5527 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5528 KDASSERT(l2b != NULL); 5529 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5530 pte = *ptep; 5531 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5532 *ptep = pte; 5533 PTE_SYNC(ptep); 5534 cpu_tlb_flushD_SE(va); 5535 5536 va += PAGE_SIZE; 5537 m = TAILQ_NEXT(m, pageq.queue); 5538 } 5539 5540 #ifdef DIAGNOSTIC 5541 if (m) 5542 panic("pmap_alloc_l1pt: pglist not empty"); 5543 #endif /* DIAGNOSTIC */ 5544 5545 pmap_init_l1(l1, pl1pt); 5546 } 5547 5548 #ifdef DEBUG 5549 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5550 needed); 5551 #endif 5552 } 5553 5554 /* 5555 * Note that the following routines are used by board-specific initialisation 5556 * code to configure the initial kernel page tables. 5557 * 5558 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5559 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5560 * behaviour of the old pmap, and provides an easy migration path for 5561 * initial bring-up of the new pmap on existing ports. Fortunately, 5562 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5563 * will be deprecated. 5564 * 5565 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5566 * tables. 5567 */ 5568 5569 /* 5570 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5571 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5572 * find them as necessary. 5573 * 5574 * Note that the data on this list MUST remain valid after initarm() returns, 5575 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5576 */ 5577 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5578 5579 static vaddr_t 5580 kernel_pt_lookup(paddr_t pa) 5581 { 5582 pv_addr_t *pv; 5583 5584 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5585 #ifndef ARM32_NEW_VM_LAYOUT 5586 if (pv->pv_pa == (pa & ~PGOFSET)) 5587 return (pv->pv_va | (pa & PGOFSET)); 5588 #else 5589 if (pv->pv_pa == pa) 5590 return (pv->pv_va); 5591 #endif 5592 } 5593 return (0); 5594 } 5595 5596 /* 5597 * pmap_map_section: 5598 * 5599 * Create a single section mapping. 5600 */ 5601 void 5602 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5603 { 5604 pd_entry_t *pde = (pd_entry_t *) l1pt; 5605 pd_entry_t fl; 5606 5607 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5608 5609 switch (cache) { 5610 case PTE_NOCACHE: 5611 default: 5612 fl = 0; 5613 break; 5614 5615 case PTE_CACHE: 5616 fl = pte_l1_s_cache_mode; 5617 break; 5618 5619 case PTE_PAGETABLE: 5620 fl = pte_l1_s_cache_mode_pt; 5621 break; 5622 } 5623 5624 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5625 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5626 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5627 } 5628 5629 /* 5630 * pmap_map_entry: 5631 * 5632 * Create a single page mapping. 5633 */ 5634 void 5635 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5636 { 5637 pd_entry_t *pde = (pd_entry_t *) l1pt; 5638 pt_entry_t fl; 5639 pt_entry_t *pte; 5640 5641 KASSERT(((va | pa) & PGOFSET) == 0); 5642 5643 switch (cache) { 5644 case PTE_NOCACHE: 5645 default: 5646 fl = 0; 5647 break; 5648 5649 case PTE_CACHE: 5650 fl = pte_l2_s_cache_mode; 5651 break; 5652 5653 case PTE_PAGETABLE: 5654 fl = pte_l2_s_cache_mode_pt; 5655 break; 5656 } 5657 5658 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5659 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5660 5661 #ifndef ARM32_NEW_VM_LAYOUT 5662 pte = (pt_entry_t *) 5663 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5664 #else 5665 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5666 #endif 5667 if (pte == NULL) 5668 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5669 5670 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5671 #ifndef ARM32_NEW_VM_LAYOUT 5672 pte += (va >> PGSHIFT) & 0x3ff; 5673 #else 5674 pte += l2pte_index(va); 5675 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5676 #endif 5677 *pte = fl; 5678 PTE_SYNC(pte); 5679 } 5680 5681 /* 5682 * pmap_link_l2pt: 5683 * 5684 * Link the L2 page table specified by "l2pv" into the L1 5685 * page table at the slot for "va". 5686 */ 5687 void 5688 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5689 { 5690 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5691 u_int slot = va >> L1_S_SHIFT; 5692 5693 #ifndef ARM32_NEW_VM_LAYOUT 5694 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5695 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5696 #endif 5697 5698 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5699 5700 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5701 #ifdef ARM32_NEW_VM_LAYOUT 5702 PTE_SYNC(&pde[slot]); 5703 #else 5704 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5705 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5706 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5707 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5708 #endif 5709 5710 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5711 } 5712 5713 /* 5714 * pmap_map_chunk: 5715 * 5716 * Map a chunk of memory using the most efficient mappings 5717 * possible (section, large page, small page) into the 5718 * provided L1 and L2 tables at the specified virtual address. 5719 */ 5720 vsize_t 5721 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5722 int prot, int cache) 5723 { 5724 pd_entry_t *pde = (pd_entry_t *) l1pt; 5725 pt_entry_t *pte, f1, f2s, f2l; 5726 vsize_t resid; 5727 int i; 5728 5729 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5730 5731 if (l1pt == 0) 5732 panic("pmap_map_chunk: no L1 table provided"); 5733 5734 #ifdef VERBOSE_INIT_ARM 5735 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5736 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5737 #endif 5738 5739 switch (cache) { 5740 case PTE_NOCACHE: 5741 default: 5742 f1 = 0; 5743 f2l = 0; 5744 f2s = 0; 5745 break; 5746 5747 case PTE_CACHE: 5748 f1 = pte_l1_s_cache_mode; 5749 f2l = pte_l2_l_cache_mode; 5750 f2s = pte_l2_s_cache_mode; 5751 break; 5752 5753 case PTE_PAGETABLE: 5754 f1 = pte_l1_s_cache_mode_pt; 5755 f2l = pte_l2_l_cache_mode_pt; 5756 f2s = pte_l2_s_cache_mode_pt; 5757 break; 5758 } 5759 5760 size = resid; 5761 5762 while (resid > 0) { 5763 /* See if we can use a section mapping. */ 5764 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5765 #ifdef VERBOSE_INIT_ARM 5766 printf("S"); 5767 #endif 5768 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5769 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5770 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5771 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5772 va += L1_S_SIZE; 5773 pa += L1_S_SIZE; 5774 resid -= L1_S_SIZE; 5775 continue; 5776 } 5777 5778 /* 5779 * Ok, we're going to use an L2 table. Make sure 5780 * one is actually in the corresponding L1 slot 5781 * for the current VA. 5782 */ 5783 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5784 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5785 5786 #ifndef ARM32_NEW_VM_LAYOUT 5787 pte = (pt_entry_t *) 5788 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5789 #else 5790 pte = (pt_entry_t *) kernel_pt_lookup( 5791 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5792 #endif 5793 if (pte == NULL) 5794 panic("pmap_map_chunk: can't find L2 table for VA" 5795 "0x%08lx", va); 5796 5797 /* See if we can use a L2 large page mapping. */ 5798 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5799 #ifdef VERBOSE_INIT_ARM 5800 printf("L"); 5801 #endif 5802 for (i = 0; i < 16; i++) { 5803 #ifndef ARM32_NEW_VM_LAYOUT 5804 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5805 L2_L_PROTO | pa | 5806 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5807 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5808 #else 5809 pte[l2pte_index(va) + i] = 5810 L2_L_PROTO | pa | 5811 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5812 PTE_SYNC(&pte[l2pte_index(va) + i]); 5813 #endif 5814 } 5815 va += L2_L_SIZE; 5816 pa += L2_L_SIZE; 5817 resid -= L2_L_SIZE; 5818 continue; 5819 } 5820 5821 /* Use a small page mapping. */ 5822 #ifdef VERBOSE_INIT_ARM 5823 printf("P"); 5824 #endif 5825 #ifndef ARM32_NEW_VM_LAYOUT 5826 pte[(va >> PGSHIFT) & 0x3ff] = 5827 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5828 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5829 #else 5830 pte[l2pte_index(va)] = 5831 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5832 PTE_SYNC(&pte[l2pte_index(va)]); 5833 #endif 5834 va += PAGE_SIZE; 5835 pa += PAGE_SIZE; 5836 resid -= PAGE_SIZE; 5837 } 5838 #ifdef VERBOSE_INIT_ARM 5839 printf("\n"); 5840 #endif 5841 return (size); 5842 } 5843 5844 /********************** Static device map routines ***************************/ 5845 5846 static const struct pmap_devmap *pmap_devmap_table; 5847 5848 /* 5849 * Register the devmap table. This is provided in case early console 5850 * initialization needs to register mappings created by bootstrap code 5851 * before pmap_devmap_bootstrap() is called. 5852 */ 5853 void 5854 pmap_devmap_register(const struct pmap_devmap *table) 5855 { 5856 5857 pmap_devmap_table = table; 5858 } 5859 5860 /* 5861 * Map all of the static regions in the devmap table, and remember 5862 * the devmap table so other parts of the kernel can look up entries 5863 * later. 5864 */ 5865 void 5866 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5867 { 5868 int i; 5869 5870 pmap_devmap_table = table; 5871 5872 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5873 #ifdef VERBOSE_INIT_ARM 5874 printf("devmap: %08lx -> %08lx @ %08lx\n", 5875 pmap_devmap_table[i].pd_pa, 5876 pmap_devmap_table[i].pd_pa + 5877 pmap_devmap_table[i].pd_size - 1, 5878 pmap_devmap_table[i].pd_va); 5879 #endif 5880 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5881 pmap_devmap_table[i].pd_pa, 5882 pmap_devmap_table[i].pd_size, 5883 pmap_devmap_table[i].pd_prot, 5884 pmap_devmap_table[i].pd_cache); 5885 } 5886 } 5887 5888 const struct pmap_devmap * 5889 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5890 { 5891 uint64_t endpa; 5892 int i; 5893 5894 if (pmap_devmap_table == NULL) 5895 return (NULL); 5896 5897 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5898 5899 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5900 if (pa >= pmap_devmap_table[i].pd_pa && 5901 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5902 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5903 return (&pmap_devmap_table[i]); 5904 } 5905 5906 return (NULL); 5907 } 5908 5909 const struct pmap_devmap * 5910 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5911 { 5912 int i; 5913 5914 if (pmap_devmap_table == NULL) 5915 return (NULL); 5916 5917 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5918 if (va >= pmap_devmap_table[i].pd_va && 5919 va + size - 1 <= pmap_devmap_table[i].pd_va + 5920 pmap_devmap_table[i].pd_size - 1) 5921 return (&pmap_devmap_table[i]); 5922 } 5923 5924 return (NULL); 5925 } 5926 5927 /********************** PTE initialization routines **************************/ 5928 5929 /* 5930 * These routines are called when the CPU type is identified to set up 5931 * the PTE prototypes, cache modes, etc. 5932 * 5933 * The variables are always here, just in case modules need to reference 5934 * them (though, they shouldn't). 5935 */ 5936 5937 pt_entry_t pte_l1_s_cache_mode; 5938 pt_entry_t pte_l1_s_wc_mode; 5939 pt_entry_t pte_l1_s_cache_mode_pt; 5940 pt_entry_t pte_l1_s_cache_mask; 5941 5942 pt_entry_t pte_l2_l_cache_mode; 5943 pt_entry_t pte_l2_l_wc_mode; 5944 pt_entry_t pte_l2_l_cache_mode_pt; 5945 pt_entry_t pte_l2_l_cache_mask; 5946 5947 pt_entry_t pte_l2_s_cache_mode; 5948 pt_entry_t pte_l2_s_wc_mode; 5949 pt_entry_t pte_l2_s_cache_mode_pt; 5950 pt_entry_t pte_l2_s_cache_mask; 5951 5952 pt_entry_t pte_l1_s_prot_u; 5953 pt_entry_t pte_l1_s_prot_w; 5954 pt_entry_t pte_l1_s_prot_ro; 5955 pt_entry_t pte_l1_s_prot_mask; 5956 5957 pt_entry_t pte_l2_s_prot_u; 5958 pt_entry_t pte_l2_s_prot_w; 5959 pt_entry_t pte_l2_s_prot_ro; 5960 pt_entry_t pte_l2_s_prot_mask; 5961 5962 pt_entry_t pte_l2_l_prot_u; 5963 pt_entry_t pte_l2_l_prot_w; 5964 pt_entry_t pte_l2_l_prot_ro; 5965 pt_entry_t pte_l2_l_prot_mask; 5966 5967 pt_entry_t pte_l1_s_proto; 5968 pt_entry_t pte_l1_c_proto; 5969 pt_entry_t pte_l2_s_proto; 5970 5971 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5972 void (*pmap_zero_page_func)(paddr_t); 5973 5974 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5975 void 5976 pmap_pte_init_generic(void) 5977 { 5978 5979 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5980 pte_l1_s_wc_mode = L1_S_B; 5981 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5982 5983 pte_l2_l_cache_mode = L2_B|L2_C; 5984 pte_l2_l_wc_mode = L2_B; 5985 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5986 5987 pte_l2_s_cache_mode = L2_B|L2_C; 5988 pte_l2_s_wc_mode = L2_B; 5989 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5990 5991 /* 5992 * If we have a write-through cache, set B and C. If 5993 * we have a write-back cache, then we assume setting 5994 * only C will make those pages write-through. 5995 */ 5996 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5997 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5998 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5999 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6000 } else { 6001 #if ARM_MMU_V6 > 1 6002 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 6003 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 6004 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 6005 #else 6006 pte_l1_s_cache_mode_pt = L1_S_C; 6007 pte_l2_l_cache_mode_pt = L2_C; 6008 pte_l2_s_cache_mode_pt = L2_C; 6009 #endif 6010 } 6011 6012 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6013 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6014 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6015 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6016 6017 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6018 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6019 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6020 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6021 6022 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6023 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6024 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6025 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6026 6027 pte_l1_s_proto = L1_S_PROTO_generic; 6028 pte_l1_c_proto = L1_C_PROTO_generic; 6029 pte_l2_s_proto = L2_S_PROTO_generic; 6030 6031 pmap_copy_page_func = pmap_copy_page_generic; 6032 pmap_zero_page_func = pmap_zero_page_generic; 6033 } 6034 6035 #if defined(CPU_ARM8) 6036 void 6037 pmap_pte_init_arm8(void) 6038 { 6039 6040 /* 6041 * ARM8 is compatible with generic, but we need to use 6042 * the page tables uncached. 6043 */ 6044 pmap_pte_init_generic(); 6045 6046 pte_l1_s_cache_mode_pt = 0; 6047 pte_l2_l_cache_mode_pt = 0; 6048 pte_l2_s_cache_mode_pt = 0; 6049 } 6050 #endif /* CPU_ARM8 */ 6051 6052 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6053 void 6054 pmap_pte_init_arm9(void) 6055 { 6056 6057 /* 6058 * ARM9 is compatible with generic, but we want to use 6059 * write-through caching for now. 6060 */ 6061 pmap_pte_init_generic(); 6062 6063 pte_l1_s_cache_mode = L1_S_C; 6064 pte_l2_l_cache_mode = L2_C; 6065 pte_l2_s_cache_mode = L2_C; 6066 6067 pte_l1_s_wc_mode = L1_S_B; 6068 pte_l2_l_wc_mode = L2_B; 6069 pte_l2_s_wc_mode = L2_B; 6070 6071 pte_l1_s_cache_mode_pt = L1_S_C; 6072 pte_l2_l_cache_mode_pt = L2_C; 6073 pte_l2_s_cache_mode_pt = L2_C; 6074 } 6075 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6076 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6077 6078 #if defined(CPU_ARM10) 6079 void 6080 pmap_pte_init_arm10(void) 6081 { 6082 6083 /* 6084 * ARM10 is compatible with generic, but we want to use 6085 * write-through caching for now. 6086 */ 6087 pmap_pte_init_generic(); 6088 6089 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6090 pte_l2_l_cache_mode = L2_B | L2_C; 6091 pte_l2_s_cache_mode = L2_B | L2_C; 6092 6093 pte_l1_s_cache_mode = L1_S_B; 6094 pte_l2_l_cache_mode = L2_B; 6095 pte_l2_s_cache_mode = L2_B; 6096 6097 pte_l1_s_cache_mode_pt = L1_S_C; 6098 pte_l2_l_cache_mode_pt = L2_C; 6099 pte_l2_s_cache_mode_pt = L2_C; 6100 6101 } 6102 #endif /* CPU_ARM10 */ 6103 6104 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6105 void 6106 pmap_pte_init_arm11(void) 6107 { 6108 6109 /* 6110 * ARM11 is compatible with generic, but we want to use 6111 * write-through caching for now. 6112 */ 6113 pmap_pte_init_generic(); 6114 6115 pte_l1_s_cache_mode = L1_S_C; 6116 pte_l2_l_cache_mode = L2_C; 6117 pte_l2_s_cache_mode = L2_C; 6118 6119 pte_l1_s_wc_mode = L1_S_B; 6120 pte_l2_l_wc_mode = L2_B; 6121 pte_l2_s_wc_mode = L2_B; 6122 6123 pte_l1_s_cache_mode_pt = L1_S_C; 6124 pte_l2_l_cache_mode_pt = L2_C; 6125 pte_l2_s_cache_mode_pt = L2_C; 6126 } 6127 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6128 6129 #if ARM_MMU_SA1 == 1 6130 void 6131 pmap_pte_init_sa1(void) 6132 { 6133 6134 /* 6135 * The StrongARM SA-1 cache does not have a write-through 6136 * mode. So, do the generic initialization, then reset 6137 * the page table cache mode to B=1,C=1, and note that 6138 * the PTEs need to be sync'd. 6139 */ 6140 pmap_pte_init_generic(); 6141 6142 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6143 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6144 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6145 6146 pmap_needs_pte_sync = 1; 6147 } 6148 #endif /* ARM_MMU_SA1 == 1*/ 6149 6150 #if ARM_MMU_XSCALE == 1 6151 #if (ARM_NMMUS > 1) 6152 static u_int xscale_use_minidata; 6153 #endif 6154 6155 void 6156 pmap_pte_init_xscale(void) 6157 { 6158 uint32_t auxctl; 6159 int write_through = 0; 6160 6161 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6162 pte_l1_s_wc_mode = L1_S_B; 6163 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6164 6165 pte_l2_l_cache_mode = L2_B|L2_C; 6166 pte_l2_l_wc_mode = L2_B; 6167 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6168 6169 pte_l2_s_cache_mode = L2_B|L2_C; 6170 pte_l2_s_wc_mode = L2_B; 6171 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6172 6173 pte_l1_s_cache_mode_pt = L1_S_C; 6174 pte_l2_l_cache_mode_pt = L2_C; 6175 pte_l2_s_cache_mode_pt = L2_C; 6176 6177 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6178 /* 6179 * The XScale core has an enhanced mode where writes that 6180 * miss the cache cause a cache line to be allocated. This 6181 * is significantly faster than the traditional, write-through 6182 * behavior of this case. 6183 */ 6184 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6185 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6186 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6187 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6188 6189 #ifdef XSCALE_CACHE_WRITE_THROUGH 6190 /* 6191 * Some versions of the XScale core have various bugs in 6192 * their cache units, the work-around for which is to run 6193 * the cache in write-through mode. Unfortunately, this 6194 * has a major (negative) impact on performance. So, we 6195 * go ahead and run fast-and-loose, in the hopes that we 6196 * don't line up the planets in a way that will trip the 6197 * bugs. 6198 * 6199 * However, we give you the option to be slow-but-correct. 6200 */ 6201 write_through = 1; 6202 #elif defined(XSCALE_CACHE_WRITE_BACK) 6203 /* force write back cache mode */ 6204 write_through = 0; 6205 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6206 /* 6207 * Intel PXA2[15]0 processors are known to have a bug in 6208 * write-back cache on revision 4 and earlier (stepping 6209 * A[01] and B[012]). Fixed for C0 and later. 6210 */ 6211 { 6212 uint32_t id, type; 6213 6214 id = cpufunc_id(); 6215 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6216 6217 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6218 if ((id & CPU_ID_REVISION_MASK) < 5) { 6219 /* write through for stepping A0-1 and B0-2 */ 6220 write_through = 1; 6221 } 6222 } 6223 } 6224 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6225 6226 if (write_through) { 6227 pte_l1_s_cache_mode = L1_S_C; 6228 pte_l2_l_cache_mode = L2_C; 6229 pte_l2_s_cache_mode = L2_C; 6230 } 6231 6232 #if (ARM_NMMUS > 1) 6233 xscale_use_minidata = 1; 6234 #endif 6235 6236 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6237 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6238 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6239 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6240 6241 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6242 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6243 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6244 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6245 6246 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6247 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6248 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6249 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6250 6251 pte_l1_s_proto = L1_S_PROTO_xscale; 6252 pte_l1_c_proto = L1_C_PROTO_xscale; 6253 pte_l2_s_proto = L2_S_PROTO_xscale; 6254 6255 pmap_copy_page_func = pmap_copy_page_xscale; 6256 pmap_zero_page_func = pmap_zero_page_xscale; 6257 6258 /* 6259 * Disable ECC protection of page table access, for now. 6260 */ 6261 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6262 auxctl &= ~XSCALE_AUXCTL_P; 6263 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6264 } 6265 6266 /* 6267 * xscale_setup_minidata: 6268 * 6269 * Set up the mini-data cache clean area. We require the 6270 * caller to allocate the right amount of physically and 6271 * virtually contiguous space. 6272 */ 6273 void 6274 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6275 { 6276 extern vaddr_t xscale_minidata_clean_addr; 6277 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6278 pd_entry_t *pde = (pd_entry_t *) l1pt; 6279 pt_entry_t *pte; 6280 vsize_t size; 6281 uint32_t auxctl; 6282 6283 xscale_minidata_clean_addr = va; 6284 6285 /* Round it to page size. */ 6286 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6287 6288 for (; size != 0; 6289 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6290 #ifndef ARM32_NEW_VM_LAYOUT 6291 pte = (pt_entry_t *) 6292 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6293 #else 6294 pte = (pt_entry_t *) kernel_pt_lookup( 6295 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6296 #endif 6297 if (pte == NULL) 6298 panic("xscale_setup_minidata: can't find L2 table for " 6299 "VA 0x%08lx", va); 6300 #ifndef ARM32_NEW_VM_LAYOUT 6301 pte[(va >> PGSHIFT) & 0x3ff] = 6302 #else 6303 pte[l2pte_index(va)] = 6304 #endif 6305 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6306 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6307 } 6308 6309 /* 6310 * Configure the mini-data cache for write-back with 6311 * read/write-allocate. 6312 * 6313 * NOTE: In order to reconfigure the mini-data cache, we must 6314 * make sure it contains no valid data! In order to do that, 6315 * we must issue a global data cache invalidate command! 6316 * 6317 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6318 * THIS IS VERY IMPORTANT! 6319 */ 6320 6321 /* Invalidate data and mini-data. */ 6322 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6323 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6324 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6325 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6326 } 6327 6328 /* 6329 * Change the PTEs for the specified kernel mappings such that they 6330 * will use the mini data cache instead of the main data cache. 6331 */ 6332 void 6333 pmap_uarea(vaddr_t va) 6334 { 6335 struct l2_bucket *l2b; 6336 pt_entry_t *ptep, *sptep, pte; 6337 vaddr_t next_bucket, eva; 6338 6339 #if (ARM_NMMUS > 1) 6340 if (xscale_use_minidata == 0) 6341 return; 6342 #endif 6343 6344 eva = va + USPACE; 6345 6346 while (va < eva) { 6347 next_bucket = L2_NEXT_BUCKET(va); 6348 if (next_bucket > eva) 6349 next_bucket = eva; 6350 6351 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6352 KDASSERT(l2b != NULL); 6353 6354 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6355 6356 while (va < next_bucket) { 6357 pte = *ptep; 6358 if (!l2pte_minidata(pte)) { 6359 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6360 cpu_tlb_flushD_SE(va); 6361 *ptep = pte & ~L2_B; 6362 } 6363 ptep++; 6364 va += PAGE_SIZE; 6365 } 6366 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6367 } 6368 cpu_cpwait(); 6369 } 6370 #endif /* ARM_MMU_XSCALE == 1 */ 6371 6372 6373 #if defined(CPU_ARM11MPCORE) 6374 6375 void 6376 pmap_pte_init_arm11mpcore(void) 6377 { 6378 6379 /* cache mode is controlled by 5 bits (B, C, TEX) */ 6380 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 6381 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 6382 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6383 /* use extended small page (without APn, with TEX) */ 6384 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 6385 #else 6386 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 6387 #endif 6388 6389 /* write-back, write-allocate */ 6390 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6391 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 6392 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6393 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6394 #else 6395 /* no TEX. read-allocate */ 6396 pte_l2_s_cache_mode = L2_C | L2_B; 6397 #endif 6398 /* 6399 * write-back, write-allocate for page tables. 6400 */ 6401 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6402 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 6403 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6404 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6405 #else 6406 pte_l2_s_cache_mode_pt = L2_C | L2_B; 6407 #endif 6408 6409 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 6410 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 6411 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 6412 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 6413 6414 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6415 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 6416 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 6417 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 6418 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 6419 6420 #else 6421 /* with AP[0..3] */ 6422 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6423 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6424 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6425 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6426 #endif 6427 6428 #ifdef ARM11MPCORE_COMPAT_MMU 6429 /* with AP[0..3] */ 6430 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6431 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6432 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6433 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6434 6435 pte_l1_s_proto = L1_S_PROTO_armv6; 6436 pte_l1_c_proto = L1_C_PROTO_armv6; 6437 pte_l2_s_proto = L2_S_PROTO_armv6c; 6438 #else 6439 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 6440 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 6441 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 6442 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 6443 6444 pte_l1_s_proto = L1_S_PROTO_armv6; 6445 pte_l1_c_proto = L1_C_PROTO_armv6; 6446 pte_l2_s_proto = L2_S_PROTO_armv6n; 6447 #endif 6448 6449 pmap_copy_page_func = pmap_copy_page_generic; 6450 pmap_zero_page_func = pmap_zero_page_generic; 6451 pmap_needs_pte_sync = 1; 6452 } 6453 #endif /* CPU_ARM11MPCORE */ 6454 6455 6456 #if ARM_MMU_V7 == 1 6457 void 6458 pmap_pte_init_armv7(void) 6459 { 6460 /* 6461 * The ARMv7-A MMU is mostly compatible with generic. If the 6462 * AP field is zero, that now means "no access" rather than 6463 * read-only. The prototypes are a little different because of 6464 * the XN bit. 6465 */ 6466 pmap_pte_init_generic(); 6467 6468 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6469 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6470 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6471 6472 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6473 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6474 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6475 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6476 6477 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6478 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6479 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6480 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6481 6482 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6483 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6484 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6485 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6486 6487 pte_l1_s_proto = L1_S_PROTO_armv7; 6488 pte_l1_c_proto = L1_C_PROTO_armv7; 6489 pte_l2_s_proto = L2_S_PROTO_armv7; 6490 } 6491 #endif /* ARM_MMU_V7 */ 6492 6493 /* 6494 * return the PA of the current L1 table, for use when handling a crash dump 6495 */ 6496 uint32_t pmap_kernel_L1_addr(void) 6497 { 6498 return pmap_kernel()->pm_l1->l1_physaddr; 6499 } 6500 6501 #if defined(DDB) 6502 /* 6503 * A couple of ddb-callable functions for dumping pmaps 6504 */ 6505 void pmap_dump_all(void); 6506 void pmap_dump(pmap_t); 6507 6508 void 6509 pmap_dump_all(void) 6510 { 6511 pmap_t pm; 6512 6513 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6514 if (pm == pmap_kernel()) 6515 continue; 6516 pmap_dump(pm); 6517 printf("\n"); 6518 } 6519 } 6520 6521 static pt_entry_t ncptes[64]; 6522 static void pmap_dump_ncpg(pmap_t); 6523 6524 void 6525 pmap_dump(pmap_t pm) 6526 { 6527 struct l2_dtable *l2; 6528 struct l2_bucket *l2b; 6529 pt_entry_t *ptep, pte; 6530 vaddr_t l2_va, l2b_va, va; 6531 int i, j, k, occ, rows = 0; 6532 6533 if (pm == pmap_kernel()) 6534 printf("pmap_kernel (%p): ", pm); 6535 else 6536 printf("user pmap (%p): ", pm); 6537 6538 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6539 6540 l2_va = 0; 6541 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6542 l2 = pm->pm_l2[i]; 6543 6544 if (l2 == NULL || l2->l2_occupancy == 0) 6545 continue; 6546 6547 l2b_va = l2_va; 6548 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6549 l2b = &l2->l2_bucket[j]; 6550 6551 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6552 continue; 6553 6554 ptep = l2b->l2b_kva; 6555 6556 for (k = 0; k < 256 && ptep[k] == 0; k++) 6557 ; 6558 6559 k &= ~63; 6560 occ = l2b->l2b_occupancy; 6561 va = l2b_va + (k * 4096); 6562 for (; k < 256; k++, va += 0x1000) { 6563 char ch = ' '; 6564 if ((k % 64) == 0) { 6565 if ((rows % 8) == 0) { 6566 printf( 6567 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6568 } 6569 printf("%08lx: ", va); 6570 } 6571 6572 ncptes[k & 63] = 0; 6573 pte = ptep[k]; 6574 if (pte == 0) { 6575 ch = '.'; 6576 } else { 6577 occ--; 6578 switch (pte & 0x0c) { 6579 case 0x00: 6580 ch = 'D'; /* No cache No buff */ 6581 break; 6582 case 0x04: 6583 ch = 'B'; /* No cache buff */ 6584 break; 6585 case 0x08: 6586 if (pte & 0x40) 6587 ch = 'm'; 6588 else 6589 ch = 'C'; /* Cache No buff */ 6590 break; 6591 case 0x0c: 6592 ch = 'F'; /* Cache Buff */ 6593 break; 6594 } 6595 6596 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6597 ch += 0x20; 6598 6599 if ((pte & 0xc) == 0) 6600 ncptes[k & 63] = pte; 6601 } 6602 6603 if ((k % 64) == 63) { 6604 rows++; 6605 printf("%c\n", ch); 6606 pmap_dump_ncpg(pm); 6607 if (occ == 0) 6608 break; 6609 } else 6610 printf("%c", ch); 6611 } 6612 } 6613 } 6614 } 6615 6616 static void 6617 pmap_dump_ncpg(pmap_t pm) 6618 { 6619 struct vm_page *pg; 6620 struct vm_page_md *md; 6621 struct pv_entry *pv; 6622 int i; 6623 6624 for (i = 0; i < 63; i++) { 6625 if (ncptes[i] == 0) 6626 continue; 6627 6628 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6629 if (pg == NULL) 6630 continue; 6631 md = VM_PAGE_TO_MD(pg); 6632 6633 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6634 VM_PAGE_TO_PHYS(pg), 6635 md->krw_mappings, md->kro_mappings, 6636 md->urw_mappings, md->uro_mappings); 6637 6638 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6639 printf(" %c va 0x%08lx, flags 0x%x\n", 6640 (pm == pv->pv_pmap) ? '*' : ' ', 6641 pv->pv_va, pv->pv_flags); 6642 } 6643 } 6644 } 6645 #endif 6646 6647 #ifdef PMAP_STEAL_MEMORY 6648 void 6649 pmap_boot_pageadd(pv_addr_t *newpv) 6650 { 6651 pv_addr_t *pv, *npv; 6652 6653 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6654 if (newpv->pv_pa < pv->pv_va) { 6655 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6656 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6657 newpv->pv_size += pv->pv_size; 6658 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6659 } 6660 pv = NULL; 6661 } else { 6662 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6663 pv = npv) { 6664 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6665 KASSERT(pv->pv_pa < newpv->pv_pa); 6666 if (newpv->pv_pa > npv->pv_pa) 6667 continue; 6668 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6669 pv->pv_size += newpv->pv_size; 6670 return; 6671 } 6672 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6673 break; 6674 newpv->pv_size += npv->pv_size; 6675 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6676 SLIST_REMOVE_AFTER(newpv, pv_list); 6677 return; 6678 } 6679 } 6680 } 6681 6682 if (pv) { 6683 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6684 } else { 6685 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6686 } 6687 } 6688 6689 void 6690 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6691 pv_addr_t *rpv) 6692 { 6693 pv_addr_t *pv, **pvp; 6694 struct vm_physseg *ps; 6695 size_t i; 6696 6697 KASSERT(amount & PGOFSET); 6698 KASSERT((mask & PGOFSET) == 0); 6699 KASSERT((match & PGOFSET) == 0); 6700 KASSERT(amount != 0); 6701 6702 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6703 (pv = *pvp) != NULL; 6704 pvp = &SLIST_NEXT(pv, pv_list)) { 6705 pv_addr_t *newpv; 6706 psize_t off; 6707 /* 6708 * If this entry is too small to satify the request... 6709 */ 6710 KASSERT(pv->pv_size > 0); 6711 if (pv->pv_size < amount) 6712 continue; 6713 6714 for (off = 0; off <= mask; off += PAGE_SIZE) { 6715 if (((pv->pv_pa + off) & mask) == match 6716 && off + amount <= pv->pv_size) 6717 break; 6718 } 6719 if (off > mask) 6720 continue; 6721 6722 rpv->pv_va = pv->pv_va + off; 6723 rpv->pv_pa = pv->pv_pa + off; 6724 rpv->pv_size = amount; 6725 pv->pv_size -= amount; 6726 if (pv->pv_size == 0) { 6727 KASSERT(off == 0); 6728 KASSERT((vaddr_t) pv == rpv->pv_va); 6729 *pvp = SLIST_NEXT(pv, pv_list); 6730 } else if (off == 0) { 6731 KASSERT((vaddr_t) pv == rpv->pv_va); 6732 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6733 *newpv = *pv; 6734 newpv->pv_pa += amount; 6735 newpv->pv_va += amount; 6736 *pvp = newpv; 6737 } else if (off < pv->pv_size) { 6738 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6739 *newpv = *pv; 6740 newpv->pv_size -= off; 6741 newpv->pv_pa += off + amount; 6742 newpv->pv_va += off + amount; 6743 6744 SLIST_NEXT(pv, pv_list) = newpv; 6745 pv->pv_size = off; 6746 } else { 6747 KASSERT((vaddr_t) pv != rpv->pv_va); 6748 } 6749 memset((void *)rpv->pv_va, 0, amount); 6750 return; 6751 } 6752 6753 if (vm_nphysseg == 0) 6754 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6755 6756 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6757 (pv = *pvp) != NULL; 6758 pvp = &SLIST_NEXT(pv, pv_list)) { 6759 if (SLIST_NEXT(pv, pv_list) == NULL) 6760 break; 6761 } 6762 KASSERT(mask == 0); 6763 for (i = 0; i < vm_nphysseg; i++) { 6764 ps = VM_PHYSMEM_PTR(i); 6765 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6766 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6767 rpv->pv_va = pv->pv_va; 6768 rpv->pv_pa = pv->pv_pa; 6769 rpv->pv_size = amount; 6770 *pvp = NULL; 6771 pmap_map_chunk(kernel_l1pt.pv_va, 6772 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6773 ptoa(ps->avail_start), 6774 amount - pv->pv_size, 6775 VM_PROT_READ|VM_PROT_WRITE, 6776 PTE_CACHE); 6777 ps->avail_start += atop(amount - pv->pv_size); 6778 /* 6779 * If we consumed the entire physseg, remove it. 6780 */ 6781 if (ps->avail_start == ps->avail_end) { 6782 for (--vm_nphysseg; i < vm_nphysseg; i++) 6783 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6784 } 6785 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6786 return; 6787 } 6788 } 6789 6790 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6791 } 6792 6793 vaddr_t 6794 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6795 { 6796 pv_addr_t pv; 6797 6798 pmap_boot_pagealloc(size, 0, 0, &pv); 6799 6800 return pv.pv_va; 6801 } 6802 #endif /* PMAP_STEAL_MEMORY */ 6803 6804 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6805 { 6806 sysctl_createv(clog, 0, NULL, NULL, 6807 CTLFLAG_PERMANENT, 6808 CTLTYPE_NODE, "machdep", NULL, 6809 NULL, 0, NULL, 0, 6810 CTL_MACHDEP, CTL_EOL); 6811 6812 sysctl_createv(clog, 0, NULL, NULL, 6813 CTLFLAG_PERMANENT, 6814 CTLTYPE_INT, "kmpages", 6815 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6816 NULL, 0, &pmap_kmpages, 0, 6817 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6818 } 6819
Indexes created Fri Sep 26 20:09:58 GMT 2025