pmap.c revision 1.227
1 /* $NetBSD: pmap.c,v 1.227 2012/01/28 16:16:41 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/pool.h> 201 #include <sys/kmem.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <sys/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.227 2012/01/28 16:16:41 matt Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 static struct pmap kernel_pmap_store; 258 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 #ifdef PMAPCOUNTERS 308 #define PMAP_EVCNT_INITIALIZER(name) \ 309 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 310 311 #ifdef PMAP_CACHE_VIPT 312 static struct evcnt pmap_ev_vac_clean_one = 313 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 314 static struct evcnt pmap_ev_vac_flush_one = 315 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_lots = 317 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 318 static struct evcnt pmap_ev_vac_flush_lots2 = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 324 325 static struct evcnt pmap_ev_vac_color_new = 326 PMAP_EVCNT_INITIALIZER("new page color"); 327 static struct evcnt pmap_ev_vac_color_reuse = 328 PMAP_EVCNT_INITIALIZER("ok first page color"); 329 static struct evcnt pmap_ev_vac_color_ok = 330 PMAP_EVCNT_INITIALIZER("ok page color"); 331 static struct evcnt pmap_ev_vac_color_blind = 332 PMAP_EVCNT_INITIALIZER("blind page color"); 333 static struct evcnt pmap_ev_vac_color_change = 334 PMAP_EVCNT_INITIALIZER("change page color"); 335 static struct evcnt pmap_ev_vac_color_erase = 336 PMAP_EVCNT_INITIALIZER("erase page color"); 337 static struct evcnt pmap_ev_vac_color_none = 338 PMAP_EVCNT_INITIALIZER("no page color"); 339 static struct evcnt pmap_ev_vac_color_restore = 340 PMAP_EVCNT_INITIALIZER("restore page color"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 350 #endif 351 352 static struct evcnt pmap_ev_mappings = 353 PMAP_EVCNT_INITIALIZER("pages mapped"); 354 static struct evcnt pmap_ev_unmappings = 355 PMAP_EVCNT_INITIALIZER("pages unmapped"); 356 static struct evcnt pmap_ev_remappings = 357 PMAP_EVCNT_INITIALIZER("pages remapped"); 358 359 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 360 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 362 363 static struct evcnt pmap_ev_kernel_mappings = 364 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 365 static struct evcnt pmap_ev_kernel_unmappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 367 static struct evcnt pmap_ev_kernel_remappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 373 374 static struct evcnt pmap_ev_kenter_mappings = 375 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 376 static struct evcnt pmap_ev_kenter_unmappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 378 static struct evcnt pmap_ev_kenter_remappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 380 static struct evcnt pmap_ev_pt_mappings = 381 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 382 383 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 387 388 #ifdef PMAP_CACHE_VIPT 389 static struct evcnt pmap_ev_exec_mappings = 390 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 391 static struct evcnt pmap_ev_exec_cached = 392 PMAP_EVCNT_INITIALIZER("exec pages cached"); 393 394 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 396 397 static struct evcnt pmap_ev_exec_synced = 398 PMAP_EVCNT_INITIALIZER("exec pages synced"); 399 static struct evcnt pmap_ev_exec_synced_map = 400 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 401 static struct evcnt pmap_ev_exec_synced_unmap = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 403 static struct evcnt pmap_ev_exec_synced_remap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 405 static struct evcnt pmap_ev_exec_synced_clearbit = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 407 static struct evcnt pmap_ev_exec_synced_kremove = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 409 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 416 417 static struct evcnt pmap_ev_exec_discarded_unmap = 418 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 419 static struct evcnt pmap_ev_exec_discarded_zero = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 421 static struct evcnt pmap_ev_exec_discarded_copy = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 423 static struct evcnt pmap_ev_exec_discarded_page_protect = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 425 static struct evcnt pmap_ev_exec_discarded_clearbit = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 427 static struct evcnt pmap_ev_exec_discarded_kremove = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 429 430 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 436 #endif /* PMAP_CACHE_VIPT */ 437 438 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 439 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 440 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 441 442 EVCNT_ATTACH_STATIC(pmap_ev_updates); 443 EVCNT_ATTACH_STATIC(pmap_ev_collects); 444 EVCNT_ATTACH_STATIC(pmap_ev_activations); 445 446 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 447 #else 448 #define PMAPCOUNT(x) ((void)0) 449 #endif 450 451 /* 452 * pmap copy/zero page, and mem(5) hook point 453 */ 454 static pt_entry_t *csrc_pte, *cdst_pte; 455 static vaddr_t csrcp, cdstp; 456 vaddr_t memhook; /* used by mem.c */ 457 kmutex_t memlock; /* used by mem.c */ 458 void *zeropage; /* used by mem.c */ 459 extern void *msgbufaddr; 460 int pmap_kmpages; 461 /* 462 * Flag to indicate if pmap_init() has done its thing 463 */ 464 bool pmap_initialized; 465 466 /* 467 * Misc. locking data structures 468 */ 469 470 #define pmap_acquire_pmap_lock(pm) \ 471 do { \ 472 if ((pm) != pmap_kernel()) \ 473 mutex_enter((pm)->pm_lock); \ 474 } while (/*CONSTCOND*/0) 475 476 #define pmap_release_pmap_lock(pm) \ 477 do { \ 478 if ((pm) != pmap_kernel()) \ 479 mutex_exit((pm)->pm_lock); \ 480 } while (/*CONSTCOND*/0) 481 482 483 /* 484 * Metadata for L1 translation tables. 485 */ 486 struct l1_ttable { 487 /* Entry on the L1 Table list */ 488 SLIST_ENTRY(l1_ttable) l1_link; 489 490 /* Entry on the L1 Least Recently Used list */ 491 TAILQ_ENTRY(l1_ttable) l1_lru; 492 493 /* Track how many domains are allocated from this L1 */ 494 volatile u_int l1_domain_use_count; 495 496 /* 497 * A free-list of domain numbers for this L1. 498 * We avoid using ffs() and a bitmap to track domains since ffs() 499 * is slow on ARM. 500 */ 501 u_int8_t l1_domain_first; 502 u_int8_t l1_domain_free[PMAP_DOMAINS]; 503 504 /* Physical address of this L1 page table */ 505 paddr_t l1_physaddr; 506 507 /* KVA of this L1 page table */ 508 pd_entry_t *l1_kva; 509 }; 510 511 /* 512 * Convert a virtual address into its L1 table index. That is, the 513 * index used to locate the L2 descriptor table pointer in an L1 table. 514 * This is basically used to index l1->l1_kva[]. 515 * 516 * Each L2 descriptor table represents 1MB of VA space. 517 */ 518 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 519 520 /* 521 * L1 Page Tables are tracked using a Least Recently Used list. 522 * - New L1s are allocated from the HEAD. 523 * - Freed L1s are added to the TAIl. 524 * - Recently accessed L1s (where an 'access' is some change to one of 525 * the userland pmaps which owns this L1) are moved to the TAIL. 526 */ 527 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 528 static kmutex_t l1_lru_lock __cacheline_aligned; 529 530 /* 531 * A list of all L1 tables 532 */ 533 static SLIST_HEAD(, l1_ttable) l1_list; 534 535 /* 536 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 537 * 538 * This is normally 16MB worth L2 page descriptors for any given pmap. 539 * Reference counts are maintained for L2 descriptors so they can be 540 * freed when empty. 541 */ 542 struct l2_dtable { 543 /* The number of L2 page descriptors allocated to this l2_dtable */ 544 u_int l2_occupancy; 545 546 /* List of L2 page descriptors */ 547 struct l2_bucket { 548 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 549 paddr_t l2b_phys; /* Physical address of same */ 550 u_short l2b_l1idx; /* This L2 table's L1 index */ 551 u_short l2b_occupancy; /* How many active descriptors */ 552 } l2_bucket[L2_BUCKET_SIZE]; 553 }; 554 555 /* 556 * Given an L1 table index, calculate the corresponding l2_dtable index 557 * and bucket index within the l2_dtable. 558 */ 559 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 560 (L2_SIZE - 1)) 561 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 562 563 /* 564 * Given a virtual address, this macro returns the 565 * virtual address required to drop into the next L2 bucket. 566 */ 567 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 568 569 /* 570 * L2 allocation. 571 */ 572 #define pmap_alloc_l2_dtable() \ 573 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 574 #define pmap_free_l2_dtable(l2) \ 575 pool_cache_put(&pmap_l2dtable_cache, (l2)) 576 #define pmap_alloc_l2_ptp(pap) \ 577 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 578 PR_NOWAIT, (pap))) 579 580 /* 581 * We try to map the page tables write-through, if possible. However, not 582 * all CPUs have a write-through cache mode, so on those we have to sync 583 * the cache when we frob page tables. 584 * 585 * We try to evaluate this at compile time, if possible. However, it's 586 * not always possible to do that, hence this run-time var. 587 */ 588 int pmap_needs_pte_sync; 589 590 /* 591 * Real definition of pv_entry. 592 */ 593 struct pv_entry { 594 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 595 pmap_t pv_pmap; /* pmap where mapping lies */ 596 vaddr_t pv_va; /* virtual address for mapping */ 597 u_int pv_flags; /* flags */ 598 }; 599 600 /* 601 * Macro to determine if a mapping might be resident in the 602 * instruction cache and/or TLB 603 */ 604 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 605 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 606 607 /* 608 * Macro to determine if a mapping might be resident in the 609 * data cache and/or TLB 610 */ 611 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 612 613 /* 614 * Local prototypes 615 */ 616 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 617 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 618 pt_entry_t **); 619 static bool pmap_is_current(pmap_t); 620 static bool pmap_is_cached(pmap_t); 621 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 622 pmap_t, vaddr_t, u_int); 623 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 624 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 625 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 626 u_int, u_int); 627 628 static void pmap_pinit(pmap_t); 629 static int pmap_pmap_ctor(void *, void *, int); 630 631 static void pmap_alloc_l1(pmap_t); 632 static void pmap_free_l1(pmap_t); 633 static void pmap_use_l1(pmap_t); 634 635 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 636 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 637 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 638 static int pmap_l2ptp_ctor(void *, void *, int); 639 static int pmap_l2dtable_ctor(void *, void *, int); 640 641 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 642 #ifdef PMAP_CACHE_VIVT 643 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 644 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 645 #endif 646 647 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 648 #ifdef PMAP_CACHE_VIVT 649 static int pmap_clean_page(struct pv_entry *, bool); 650 #endif 651 #ifdef PMAP_CACHE_VIPT 652 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 653 enum pmap_flush_op { 654 PMAP_FLUSH_PRIMARY, 655 PMAP_FLUSH_SECONDARY, 656 PMAP_CLEAN_PRIMARY 657 }; 658 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 659 #endif 660 static void pmap_page_remove(struct vm_page_md *, paddr_t); 661 662 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 663 static vaddr_t kernel_pt_lookup(paddr_t); 664 665 666 /* 667 * External function prototypes 668 */ 669 extern void bzero_page(vaddr_t); 670 extern void bcopy_page(vaddr_t, vaddr_t); 671 672 /* 673 * Misc variables 674 */ 675 vaddr_t virtual_avail; 676 vaddr_t virtual_end; 677 vaddr_t pmap_curmaxkvaddr; 678 679 paddr_t avail_start; 680 paddr_t avail_end; 681 682 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 683 pv_addr_t kernelpages; 684 pv_addr_t kernel_l1pt; 685 pv_addr_t systempage; 686 687 /* Function to set the debug level of the pmap code */ 688 689 #ifdef PMAP_DEBUG 690 void 691 pmap_debug(int level) 692 { 693 pmap_debug_level = level; 694 printf("pmap_debug: level=%d\n", pmap_debug_level); 695 } 696 #endif /* PMAP_DEBUG */ 697 698 /* 699 * A bunch of routines to conditionally flush the caches/TLB depending 700 * on whether the specified pmap actually needs to be flushed at any 701 * given time. 702 */ 703 static inline void 704 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 705 { 706 707 if (pm->pm_cstate.cs_tlb_id) 708 cpu_tlb_flushID_SE(va); 709 } 710 711 static inline void 712 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 713 { 714 715 if (pm->pm_cstate.cs_tlb_d) 716 cpu_tlb_flushD_SE(va); 717 } 718 719 static inline void 720 pmap_tlb_flushID(pmap_t pm) 721 { 722 723 if (pm->pm_cstate.cs_tlb_id) { 724 cpu_tlb_flushID(); 725 pm->pm_cstate.cs_tlb = 0; 726 } 727 } 728 729 static inline void 730 pmap_tlb_flushD(pmap_t pm) 731 { 732 733 if (pm->pm_cstate.cs_tlb_d) { 734 cpu_tlb_flushD(); 735 pm->pm_cstate.cs_tlb_d = 0; 736 } 737 } 738 739 #ifdef PMAP_CACHE_VIVT 740 static inline void 741 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 742 { 743 if (pm->pm_cstate.cs_cache_id) { 744 cpu_idcache_wbinv_range(va, len); 745 } 746 } 747 748 static inline void 749 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 750 bool do_inv, bool rd_only) 751 { 752 753 if (pm->pm_cstate.cs_cache_d) { 754 if (do_inv) { 755 if (rd_only) 756 cpu_dcache_inv_range(va, len); 757 else 758 cpu_dcache_wbinv_range(va, len); 759 } else 760 if (!rd_only) 761 cpu_dcache_wb_range(va, len); 762 } 763 } 764 765 static inline void 766 pmap_idcache_wbinv_all(pmap_t pm) 767 { 768 if (pm->pm_cstate.cs_cache_id) { 769 cpu_idcache_wbinv_all(); 770 pm->pm_cstate.cs_cache = 0; 771 } 772 } 773 774 static inline void 775 pmap_dcache_wbinv_all(pmap_t pm) 776 { 777 if (pm->pm_cstate.cs_cache_d) { 778 cpu_dcache_wbinv_all(); 779 pm->pm_cstate.cs_cache_d = 0; 780 } 781 } 782 #endif /* PMAP_CACHE_VIVT */ 783 784 static inline bool 785 pmap_is_current(pmap_t pm) 786 { 787 788 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 789 return true; 790 791 return false; 792 } 793 794 static inline bool 795 pmap_is_cached(pmap_t pm) 796 { 797 798 if (pm == pmap_kernel() || pmap_recent_user == NULL || 799 pmap_recent_user == pm) 800 return (true); 801 802 return false; 803 } 804 805 /* 806 * PTE_SYNC_CURRENT: 807 * 808 * Make sure the pte is written out to RAM. 809 * We need to do this for one of two cases: 810 * - We're dealing with the kernel pmap 811 * - There is no pmap active in the cache/tlb. 812 * - The specified pmap is 'active' in the cache/tlb. 813 */ 814 #ifdef PMAP_INCLUDE_PTE_SYNC 815 #define PTE_SYNC_CURRENT(pm, ptep) \ 816 do { \ 817 if (PMAP_NEEDS_PTE_SYNC && \ 818 pmap_is_cached(pm)) \ 819 PTE_SYNC(ptep); \ 820 } while (/*CONSTCOND*/0) 821 #else 822 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 823 #endif 824 825 /* 826 * main pv_entry manipulation functions: 827 * pmap_enter_pv: enter a mapping onto a vm_page list 828 * pmap_remove_pv: remove a mappiing from a vm_page list 829 * 830 * NOTE: pmap_enter_pv expects to lock the pvh itself 831 * pmap_remove_pv expects te caller to lock the pvh before calling 832 */ 833 834 /* 835 * pmap_enter_pv: enter a mapping onto a vm_page lst 836 * 837 * => caller should hold the proper lock on pmap_main_lock 838 * => caller should have pmap locked 839 * => we will gain the lock on the vm_page and allocate the new pv_entry 840 * => caller should adjust ptp's wire_count before calling 841 * => caller should not adjust pmap's wire_count 842 */ 843 static void 844 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 845 vaddr_t va, u_int flags) 846 { 847 struct pv_entry **pvp; 848 849 NPDEBUG(PDB_PVDUMP, 850 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 851 852 pv->pv_pmap = pm; 853 pv->pv_va = va; 854 pv->pv_flags = flags; 855 856 pvp = &SLIST_FIRST(&md->pvh_list); 857 #ifdef PMAP_CACHE_VIPT 858 /* 859 * Insert unmanaged entries, writeable first, at the head of 860 * the pv list. 861 */ 862 if (__predict_true((flags & PVF_KENTRY) == 0)) { 863 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 864 pvp = &SLIST_NEXT(*pvp, pv_link); 865 } else if ((flags & PVF_WRITE) == 0) { 866 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 867 pvp = &SLIST_NEXT(*pvp, pv_link); 868 } 869 #endif 870 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 871 *pvp = pv; /* ... locked list */ 872 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 873 #ifdef PMAP_CACHE_VIPT 874 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 875 md->pvh_attrs |= PVF_KMOD; 876 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 877 md->pvh_attrs |= PVF_DIRTY; 878 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 879 #endif 880 if (pm == pmap_kernel()) { 881 PMAPCOUNT(kernel_mappings); 882 if (flags & PVF_WRITE) 883 md->krw_mappings++; 884 else 885 md->kro_mappings++; 886 } else { 887 if (flags & PVF_WRITE) 888 md->urw_mappings++; 889 else 890 md->uro_mappings++; 891 } 892 893 #ifdef PMAP_CACHE_VIPT 894 /* 895 * If this is an exec mapping and its the first exec mapping 896 * for this page, make sure to sync the I-cache. 897 */ 898 if (PV_IS_EXEC_P(flags)) { 899 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 900 pmap_syncicache_page(md, pa); 901 PMAPCOUNT(exec_synced_map); 902 } 903 PMAPCOUNT(exec_mappings); 904 } 905 #endif 906 907 PMAPCOUNT(mappings); 908 909 if (pv->pv_flags & PVF_WIRED) 910 ++pm->pm_stats.wired_count; 911 } 912 913 /* 914 * 915 * pmap_find_pv: Find a pv entry 916 * 917 * => caller should hold lock on vm_page 918 */ 919 static inline struct pv_entry * 920 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 921 { 922 struct pv_entry *pv; 923 924 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 925 if (pm == pv->pv_pmap && va == pv->pv_va) 926 break; 927 } 928 929 return (pv); 930 } 931 932 /* 933 * pmap_remove_pv: try to remove a mapping from a pv_list 934 * 935 * => caller should hold proper lock on pmap_main_lock 936 * => pmap should be locked 937 * => caller should hold lock on vm_page [so that attrs can be adjusted] 938 * => caller should adjust ptp's wire_count and free PTP if needed 939 * => caller should NOT adjust pmap's wire_count 940 * => we return the removed pv 941 */ 942 static struct pv_entry * 943 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 944 { 945 struct pv_entry *pv, **prevptr; 946 947 NPDEBUG(PDB_PVDUMP, 948 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 949 950 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 951 pv = *prevptr; 952 953 while (pv) { 954 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 955 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 956 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 957 if (pv->pv_flags & PVF_WIRED) { 958 --pm->pm_stats.wired_count; 959 } 960 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 961 if (pm == pmap_kernel()) { 962 PMAPCOUNT(kernel_unmappings); 963 if (pv->pv_flags & PVF_WRITE) 964 md->krw_mappings--; 965 else 966 md->kro_mappings--; 967 } else { 968 if (pv->pv_flags & PVF_WRITE) 969 md->urw_mappings--; 970 else 971 md->uro_mappings--; 972 } 973 974 PMAPCOUNT(unmappings); 975 #ifdef PMAP_CACHE_VIPT 976 if (!(pv->pv_flags & PVF_WRITE)) 977 break; 978 /* 979 * If this page has had an exec mapping, then if 980 * this was the last mapping, discard the contents, 981 * otherwise sync the i-cache for this page. 982 */ 983 if (PV_IS_EXEC_P(md->pvh_attrs)) { 984 if (SLIST_EMPTY(&md->pvh_list)) { 985 md->pvh_attrs &= ~PVF_EXEC; 986 PMAPCOUNT(exec_discarded_unmap); 987 } else { 988 pmap_syncicache_page(md, pa); 989 PMAPCOUNT(exec_synced_unmap); 990 } 991 } 992 #endif /* PMAP_CACHE_VIPT */ 993 break; 994 } 995 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 996 pv = *prevptr; /* advance */ 997 } 998 999 #ifdef PMAP_CACHE_VIPT 1000 /* 1001 * If we no longer have a WRITEABLE KENTRY at the head of list, 1002 * clear the KMOD attribute from the page. 1003 */ 1004 if (SLIST_FIRST(&md->pvh_list) == NULL 1005 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1006 md->pvh_attrs &= ~PVF_KMOD; 1007 1008 /* 1009 * If this was a writeable page and there are no more writeable 1010 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1011 * the contents to memory. 1012 */ 1013 if (md->krw_mappings + md->urw_mappings == 0) 1014 md->pvh_attrs &= ~PVF_WRITE; 1015 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1016 #endif /* PMAP_CACHE_VIPT */ 1017 1018 return(pv); /* return removed pv */ 1019 } 1020 1021 /* 1022 * 1023 * pmap_modify_pv: Update pv flags 1024 * 1025 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1026 * => caller should NOT adjust pmap's wire_count 1027 * => caller must call pmap_vac_me_harder() if writable status of a page 1028 * may have changed. 1029 * => we return the old flags 1030 * 1031 * Modify a physical-virtual mapping in the pv table 1032 */ 1033 static u_int 1034 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1035 u_int clr_mask, u_int set_mask) 1036 { 1037 struct pv_entry *npv; 1038 u_int flags, oflags; 1039 1040 KASSERT((clr_mask & PVF_KENTRY) == 0); 1041 KASSERT((set_mask & PVF_KENTRY) == 0); 1042 1043 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1044 return (0); 1045 1046 NPDEBUG(PDB_PVDUMP, 1047 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1048 1049 /* 1050 * There is at least one VA mapping this page. 1051 */ 1052 1053 if (clr_mask & (PVF_REF | PVF_MOD)) { 1054 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1055 #ifdef PMAP_CACHE_VIPT 1056 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1057 md->pvh_attrs |= PVF_DIRTY; 1058 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1059 #endif 1060 } 1061 1062 oflags = npv->pv_flags; 1063 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1064 1065 if ((flags ^ oflags) & PVF_WIRED) { 1066 if (flags & PVF_WIRED) 1067 ++pm->pm_stats.wired_count; 1068 else 1069 --pm->pm_stats.wired_count; 1070 } 1071 1072 if ((flags ^ oflags) & PVF_WRITE) { 1073 if (pm == pmap_kernel()) { 1074 if (flags & PVF_WRITE) { 1075 md->krw_mappings++; 1076 md->kro_mappings--; 1077 } else { 1078 md->kro_mappings++; 1079 md->krw_mappings--; 1080 } 1081 } else { 1082 if (flags & PVF_WRITE) { 1083 md->urw_mappings++; 1084 md->uro_mappings--; 1085 } else { 1086 md->uro_mappings++; 1087 md->urw_mappings--; 1088 } 1089 } 1090 } 1091 #ifdef PMAP_CACHE_VIPT 1092 if (md->urw_mappings + md->krw_mappings == 0) 1093 md->pvh_attrs &= ~PVF_WRITE; 1094 /* 1095 * We have two cases here: the first is from enter_pv (new exec 1096 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1097 * Since in latter, pmap_enter_pv won't do anything, we just have 1098 * to do what pmap_remove_pv would do. 1099 */ 1100 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1101 || (PV_IS_EXEC_P(md->pvh_attrs) 1102 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1103 pmap_syncicache_page(md, pa); 1104 PMAPCOUNT(exec_synced_remap); 1105 } 1106 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1107 #endif 1108 1109 PMAPCOUNT(remappings); 1110 1111 return (oflags); 1112 } 1113 1114 /* 1115 * Allocate an L1 translation table for the specified pmap. 1116 * This is called at pmap creation time. 1117 */ 1118 static void 1119 pmap_alloc_l1(pmap_t pm) 1120 { 1121 struct l1_ttable *l1; 1122 u_int8_t domain; 1123 1124 /* 1125 * Remove the L1 at the head of the LRU list 1126 */ 1127 mutex_spin_enter(&l1_lru_lock); 1128 l1 = TAILQ_FIRST(&l1_lru_list); 1129 KDASSERT(l1 != NULL); 1130 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1131 1132 /* 1133 * Pick the first available domain number, and update 1134 * the link to the next number. 1135 */ 1136 domain = l1->l1_domain_first; 1137 l1->l1_domain_first = l1->l1_domain_free[domain]; 1138 1139 /* 1140 * If there are still free domain numbers in this L1, 1141 * put it back on the TAIL of the LRU list. 1142 */ 1143 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1144 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1145 1146 mutex_spin_exit(&l1_lru_lock); 1147 1148 /* 1149 * Fix up the relevant bits in the pmap structure 1150 */ 1151 pm->pm_l1 = l1; 1152 pm->pm_domain = domain; 1153 } 1154 1155 /* 1156 * Free an L1 translation table. 1157 * This is called at pmap destruction time. 1158 */ 1159 static void 1160 pmap_free_l1(pmap_t pm) 1161 { 1162 struct l1_ttable *l1 = pm->pm_l1; 1163 1164 mutex_spin_enter(&l1_lru_lock); 1165 1166 /* 1167 * If this L1 is currently on the LRU list, remove it. 1168 */ 1169 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1170 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1171 1172 /* 1173 * Free up the domain number which was allocated to the pmap 1174 */ 1175 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1176 l1->l1_domain_first = pm->pm_domain; 1177 l1->l1_domain_use_count--; 1178 1179 /* 1180 * The L1 now must have at least 1 free domain, so add 1181 * it back to the LRU list. If the use count is zero, 1182 * put it at the head of the list, otherwise it goes 1183 * to the tail. 1184 */ 1185 if (l1->l1_domain_use_count == 0) 1186 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1187 else 1188 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1189 1190 mutex_spin_exit(&l1_lru_lock); 1191 } 1192 1193 static inline void 1194 pmap_use_l1(pmap_t pm) 1195 { 1196 struct l1_ttable *l1; 1197 1198 /* 1199 * Do nothing if we're in interrupt context. 1200 * Access to an L1 by the kernel pmap must not affect 1201 * the LRU list. 1202 */ 1203 if (cpu_intr_p() || pm == pmap_kernel()) 1204 return; 1205 1206 l1 = pm->pm_l1; 1207 1208 /* 1209 * If the L1 is not currently on the LRU list, just return 1210 */ 1211 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1212 return; 1213 1214 mutex_spin_enter(&l1_lru_lock); 1215 1216 /* 1217 * Check the use count again, now that we've acquired the lock 1218 */ 1219 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1220 mutex_spin_exit(&l1_lru_lock); 1221 return; 1222 } 1223 1224 /* 1225 * Move the L1 to the back of the LRU list 1226 */ 1227 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1228 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1229 1230 mutex_spin_exit(&l1_lru_lock); 1231 } 1232 1233 /* 1234 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1235 * 1236 * Free an L2 descriptor table. 1237 */ 1238 static inline void 1239 #ifndef PMAP_INCLUDE_PTE_SYNC 1240 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1241 #else 1242 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1243 #endif 1244 { 1245 #ifdef PMAP_INCLUDE_PTE_SYNC 1246 #ifdef PMAP_CACHE_VIVT 1247 /* 1248 * Note: With a write-back cache, we may need to sync this 1249 * L2 table before re-using it. 1250 * This is because it may have belonged to a non-current 1251 * pmap, in which case the cache syncs would have been 1252 * skipped for the pages that were being unmapped. If the 1253 * L2 table were then to be immediately re-allocated to 1254 * the *current* pmap, it may well contain stale mappings 1255 * which have not yet been cleared by a cache write-back 1256 * and so would still be visible to the mmu. 1257 */ 1258 if (need_sync) 1259 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1260 #endif /* PMAP_CACHE_VIVT */ 1261 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1262 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1263 } 1264 1265 /* 1266 * Returns a pointer to the L2 bucket associated with the specified pmap 1267 * and VA, or NULL if no L2 bucket exists for the address. 1268 */ 1269 static inline struct l2_bucket * 1270 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1271 { 1272 struct l2_dtable *l2; 1273 struct l2_bucket *l2b; 1274 u_short l1idx; 1275 1276 l1idx = L1_IDX(va); 1277 1278 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1279 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1280 return (NULL); 1281 1282 return (l2b); 1283 } 1284 1285 /* 1286 * Returns a pointer to the L2 bucket associated with the specified pmap 1287 * and VA. 1288 * 1289 * If no L2 bucket exists, perform the necessary allocations to put an L2 1290 * bucket/page table in place. 1291 * 1292 * Note that if a new L2 bucket/page was allocated, the caller *must* 1293 * increment the bucket occupancy counter appropriately *before* 1294 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1295 * the bucket/page in the meantime. 1296 */ 1297 static struct l2_bucket * 1298 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1299 { 1300 struct l2_dtable *l2; 1301 struct l2_bucket *l2b; 1302 u_short l1idx; 1303 1304 l1idx = L1_IDX(va); 1305 1306 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1307 /* 1308 * No mapping at this address, as there is 1309 * no entry in the L1 table. 1310 * Need to allocate a new l2_dtable. 1311 */ 1312 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1313 return (NULL); 1314 1315 /* 1316 * Link it into the parent pmap 1317 */ 1318 pm->pm_l2[L2_IDX(l1idx)] = l2; 1319 } 1320 1321 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1322 1323 /* 1324 * Fetch pointer to the L2 page table associated with the address. 1325 */ 1326 if (l2b->l2b_kva == NULL) { 1327 pt_entry_t *ptep; 1328 1329 /* 1330 * No L2 page table has been allocated. Chances are, this 1331 * is because we just allocated the l2_dtable, above. 1332 */ 1333 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1334 /* 1335 * Oops, no more L2 page tables available at this 1336 * time. We may need to deallocate the l2_dtable 1337 * if we allocated a new one above. 1338 */ 1339 if (l2->l2_occupancy == 0) { 1340 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1341 pmap_free_l2_dtable(l2); 1342 } 1343 return (NULL); 1344 } 1345 1346 l2->l2_occupancy++; 1347 l2b->l2b_kva = ptep; 1348 l2b->l2b_l1idx = l1idx; 1349 } 1350 1351 return (l2b); 1352 } 1353 1354 /* 1355 * One or more mappings in the specified L2 descriptor table have just been 1356 * invalidated. 1357 * 1358 * Garbage collect the metadata and descriptor table itself if necessary. 1359 * 1360 * The pmap lock must be acquired when this is called (not necessary 1361 * for the kernel pmap). 1362 */ 1363 static void 1364 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1365 { 1366 struct l2_dtable *l2; 1367 pd_entry_t *pl1pd, l1pd; 1368 pt_entry_t *ptep; 1369 u_short l1idx; 1370 1371 KDASSERT(count <= l2b->l2b_occupancy); 1372 1373 /* 1374 * Update the bucket's reference count according to how many 1375 * PTEs the caller has just invalidated. 1376 */ 1377 l2b->l2b_occupancy -= count; 1378 1379 /* 1380 * Note: 1381 * 1382 * Level 2 page tables allocated to the kernel pmap are never freed 1383 * as that would require checking all Level 1 page tables and 1384 * removing any references to the Level 2 page table. See also the 1385 * comment elsewhere about never freeing bootstrap L2 descriptors. 1386 * 1387 * We make do with just invalidating the mapping in the L2 table. 1388 * 1389 * This isn't really a big deal in practice and, in fact, leads 1390 * to a performance win over time as we don't need to continually 1391 * alloc/free. 1392 */ 1393 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1394 return; 1395 1396 /* 1397 * There are no more valid mappings in this level 2 page table. 1398 * Go ahead and NULL-out the pointer in the bucket, then 1399 * free the page table. 1400 */ 1401 l1idx = l2b->l2b_l1idx; 1402 ptep = l2b->l2b_kva; 1403 l2b->l2b_kva = NULL; 1404 1405 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1406 1407 /* 1408 * If the L1 slot matches the pmap's domain 1409 * number, then invalidate it. 1410 */ 1411 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1412 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1413 *pl1pd = 0; 1414 PTE_SYNC(pl1pd); 1415 } 1416 1417 /* 1418 * Release the L2 descriptor table back to the pool cache. 1419 */ 1420 #ifndef PMAP_INCLUDE_PTE_SYNC 1421 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1422 #else 1423 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1424 #endif 1425 1426 /* 1427 * Update the reference count in the associated l2_dtable 1428 */ 1429 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1430 if (--l2->l2_occupancy > 0) 1431 return; 1432 1433 /* 1434 * There are no more valid mappings in any of the Level 1 1435 * slots managed by this l2_dtable. Go ahead and NULL-out 1436 * the pointer in the parent pmap and free the l2_dtable. 1437 */ 1438 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1439 pmap_free_l2_dtable(l2); 1440 } 1441 1442 /* 1443 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1444 * structures. 1445 */ 1446 static int 1447 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1448 { 1449 #ifndef PMAP_INCLUDE_PTE_SYNC 1450 struct l2_bucket *l2b; 1451 pt_entry_t *ptep, pte; 1452 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1453 1454 /* 1455 * The mappings for these page tables were initially made using 1456 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1457 * mode will not be right for page table mappings. To avoid 1458 * polluting the pmap_kenter_pa() code with a special case for 1459 * page tables, we simply fix up the cache-mode here if it's not 1460 * correct. 1461 */ 1462 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1463 KDASSERT(l2b != NULL); 1464 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1465 pte = *ptep; 1466 1467 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1468 /* 1469 * Page tables must have the cache-mode set to Write-Thru. 1470 */ 1471 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1472 PTE_SYNC(ptep); 1473 cpu_tlb_flushD_SE(va); 1474 cpu_cpwait(); 1475 } 1476 #endif 1477 1478 memset(v, 0, L2_TABLE_SIZE_REAL); 1479 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1480 return (0); 1481 } 1482 1483 static int 1484 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1485 { 1486 1487 memset(v, 0, sizeof(struct l2_dtable)); 1488 return (0); 1489 } 1490 1491 static int 1492 pmap_pmap_ctor(void *arg, void *v, int flags) 1493 { 1494 1495 memset(v, 0, sizeof(struct pmap)); 1496 return (0); 1497 } 1498 1499 static void 1500 pmap_pinit(pmap_t pm) 1501 { 1502 struct l2_bucket *l2b; 1503 1504 if (vector_page < KERNEL_BASE) { 1505 /* 1506 * Map the vector page. 1507 */ 1508 pmap_enter(pm, vector_page, systempage.pv_pa, 1509 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1510 pmap_update(pm); 1511 1512 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1513 l2b = pmap_get_l2_bucket(pm, vector_page); 1514 KDASSERT(l2b != NULL); 1515 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1516 L1_C_DOM(pm->pm_domain); 1517 } else 1518 pm->pm_pl1vec = NULL; 1519 } 1520 1521 #ifdef PMAP_CACHE_VIVT 1522 /* 1523 * Since we have a virtually indexed cache, we may need to inhibit caching if 1524 * there is more than one mapping and at least one of them is writable. 1525 * Since we purge the cache on every context switch, we only need to check for 1526 * other mappings within the same pmap, or kernel_pmap. 1527 * This function is also called when a page is unmapped, to possibly reenable 1528 * caching on any remaining mappings. 1529 * 1530 * The code implements the following logic, where: 1531 * 1532 * KW = # of kernel read/write pages 1533 * KR = # of kernel read only pages 1534 * UW = # of user read/write pages 1535 * UR = # of user read only pages 1536 * 1537 * KC = kernel mapping is cacheable 1538 * UC = user mapping is cacheable 1539 * 1540 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1541 * +--------------------------------------------- 1542 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1543 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1544 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1545 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1546 */ 1547 1548 static const int pmap_vac_flags[4][4] = { 1549 {-1, 0, 0, PVF_KNC}, 1550 {0, 0, PVF_NC, PVF_NC}, 1551 {0, PVF_NC, PVF_NC, PVF_NC}, 1552 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1553 }; 1554 1555 static inline int 1556 pmap_get_vac_flags(const struct vm_page_md *md) 1557 { 1558 int kidx, uidx; 1559 1560 kidx = 0; 1561 if (md->kro_mappings || md->krw_mappings > 1) 1562 kidx |= 1; 1563 if (md->krw_mappings) 1564 kidx |= 2; 1565 1566 uidx = 0; 1567 if (md->uro_mappings || md->urw_mappings > 1) 1568 uidx |= 1; 1569 if (md->urw_mappings) 1570 uidx |= 2; 1571 1572 return (pmap_vac_flags[uidx][kidx]); 1573 } 1574 1575 static inline void 1576 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1577 { 1578 int nattr; 1579 1580 nattr = pmap_get_vac_flags(md); 1581 1582 if (nattr < 0) { 1583 md->pvh_attrs &= ~PVF_NC; 1584 return; 1585 } 1586 1587 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1588 return; 1589 1590 if (pm == pmap_kernel()) 1591 pmap_vac_me_kpmap(md, pa, pm, va); 1592 else 1593 pmap_vac_me_user(md, pa, pm, va); 1594 1595 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1596 } 1597 1598 static void 1599 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1600 { 1601 u_int u_cacheable, u_entries; 1602 struct pv_entry *pv; 1603 pmap_t last_pmap = pm; 1604 1605 /* 1606 * Pass one, see if there are both kernel and user pmaps for 1607 * this page. Calculate whether there are user-writable or 1608 * kernel-writable pages. 1609 */ 1610 u_cacheable = 0; 1611 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1612 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1613 u_cacheable++; 1614 } 1615 1616 u_entries = md->urw_mappings + md->uro_mappings; 1617 1618 /* 1619 * We know we have just been updating a kernel entry, so if 1620 * all user pages are already cacheable, then there is nothing 1621 * further to do. 1622 */ 1623 if (md->k_mappings == 0 && u_cacheable == u_entries) 1624 return; 1625 1626 if (u_entries) { 1627 /* 1628 * Scan over the list again, for each entry, if it 1629 * might not be set correctly, call pmap_vac_me_user 1630 * to recalculate the settings. 1631 */ 1632 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1633 /* 1634 * We know kernel mappings will get set 1635 * correctly in other calls. We also know 1636 * that if the pmap is the same as last_pmap 1637 * then we've just handled this entry. 1638 */ 1639 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1640 continue; 1641 1642 /* 1643 * If there are kernel entries and this page 1644 * is writable but non-cacheable, then we can 1645 * skip this entry also. 1646 */ 1647 if (md->k_mappings && 1648 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1649 (PVF_NC | PVF_WRITE)) 1650 continue; 1651 1652 /* 1653 * Similarly if there are no kernel-writable 1654 * entries and the page is already 1655 * read-only/cacheable. 1656 */ 1657 if (md->krw_mappings == 0 && 1658 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1659 continue; 1660 1661 /* 1662 * For some of the remaining cases, we know 1663 * that we must recalculate, but for others we 1664 * can't tell if they are correct or not, so 1665 * we recalculate anyway. 1666 */ 1667 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1668 } 1669 1670 if (md->k_mappings == 0) 1671 return; 1672 } 1673 1674 pmap_vac_me_user(md, pa, pm, va); 1675 } 1676 1677 static void 1678 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1679 { 1680 pmap_t kpmap = pmap_kernel(); 1681 struct pv_entry *pv, *npv = NULL; 1682 struct l2_bucket *l2b; 1683 pt_entry_t *ptep, pte; 1684 u_int entries = 0; 1685 u_int writable = 0; 1686 u_int cacheable_entries = 0; 1687 u_int kern_cacheable = 0; 1688 u_int other_writable = 0; 1689 1690 /* 1691 * Count mappings and writable mappings in this pmap. 1692 * Include kernel mappings as part of our own. 1693 * Keep a pointer to the first one. 1694 */ 1695 npv = NULL; 1696 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1697 /* Count mappings in the same pmap */ 1698 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1699 if (entries++ == 0) 1700 npv = pv; 1701 1702 /* Cacheable mappings */ 1703 if ((pv->pv_flags & PVF_NC) == 0) { 1704 cacheable_entries++; 1705 if (kpmap == pv->pv_pmap) 1706 kern_cacheable++; 1707 } 1708 1709 /* Writable mappings */ 1710 if (pv->pv_flags & PVF_WRITE) 1711 ++writable; 1712 } else 1713 if (pv->pv_flags & PVF_WRITE) 1714 other_writable = 1; 1715 } 1716 1717 /* 1718 * Enable or disable caching as necessary. 1719 * Note: the first entry might be part of the kernel pmap, 1720 * so we can't assume this is indicative of the state of the 1721 * other (maybe non-kpmap) entries. 1722 */ 1723 if ((entries > 1 && writable) || 1724 (entries > 0 && pm == kpmap && other_writable)) { 1725 if (cacheable_entries == 0) 1726 return; 1727 1728 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1729 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1730 (pv->pv_flags & PVF_NC)) 1731 continue; 1732 1733 pv->pv_flags |= PVF_NC; 1734 1735 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1736 KDASSERT(l2b != NULL); 1737 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1738 pte = *ptep & ~L2_S_CACHE_MASK; 1739 1740 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1741 l2pte_valid(pte)) { 1742 if (PV_BEEN_EXECD(pv->pv_flags)) { 1743 #ifdef PMAP_CACHE_VIVT 1744 pmap_idcache_wbinv_range(pv->pv_pmap, 1745 pv->pv_va, PAGE_SIZE); 1746 #endif 1747 pmap_tlb_flushID_SE(pv->pv_pmap, 1748 pv->pv_va); 1749 } else 1750 if (PV_BEEN_REFD(pv->pv_flags)) { 1751 #ifdef PMAP_CACHE_VIVT 1752 pmap_dcache_wb_range(pv->pv_pmap, 1753 pv->pv_va, PAGE_SIZE, true, 1754 (pv->pv_flags & PVF_WRITE) == 0); 1755 #endif 1756 pmap_tlb_flushD_SE(pv->pv_pmap, 1757 pv->pv_va); 1758 } 1759 } 1760 1761 *ptep = pte; 1762 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1763 } 1764 cpu_cpwait(); 1765 } else 1766 if (entries > cacheable_entries) { 1767 /* 1768 * Turn cacheing back on for some pages. If it is a kernel 1769 * page, only do so if there are no other writable pages. 1770 */ 1771 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1772 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1773 (kpmap != pv->pv_pmap || other_writable))) 1774 continue; 1775 1776 pv->pv_flags &= ~PVF_NC; 1777 1778 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1779 KDASSERT(l2b != NULL); 1780 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1781 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1782 1783 if (l2pte_valid(pte)) { 1784 if (PV_BEEN_EXECD(pv->pv_flags)) { 1785 pmap_tlb_flushID_SE(pv->pv_pmap, 1786 pv->pv_va); 1787 } else 1788 if (PV_BEEN_REFD(pv->pv_flags)) { 1789 pmap_tlb_flushD_SE(pv->pv_pmap, 1790 pv->pv_va); 1791 } 1792 } 1793 1794 *ptep = pte; 1795 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1796 } 1797 } 1798 } 1799 #endif 1800 1801 #ifdef PMAP_CACHE_VIPT 1802 static void 1803 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1804 { 1805 struct pv_entry *pv; 1806 vaddr_t tst_mask; 1807 bool bad_alias; 1808 struct l2_bucket *l2b; 1809 pt_entry_t *ptep, pte, opte; 1810 const u_int 1811 rw_mappings = md->urw_mappings + md->krw_mappings, 1812 ro_mappings = md->uro_mappings + md->kro_mappings; 1813 1814 /* do we need to do anything? */ 1815 if (arm_cache_prefer_mask == 0) 1816 return; 1817 1818 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1819 md, pm, va)); 1820 1821 KASSERT(!va || pm); 1822 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1823 1824 /* Already a conflict? */ 1825 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1826 /* just an add, things are already non-cached */ 1827 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1828 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1829 bad_alias = false; 1830 if (va) { 1831 PMAPCOUNT(vac_color_none); 1832 bad_alias = true; 1833 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1834 goto fixup; 1835 } 1836 pv = SLIST_FIRST(&md->pvh_list); 1837 /* the list can't be empty because it would be cachable */ 1838 if (md->pvh_attrs & PVF_KMPAGE) { 1839 tst_mask = md->pvh_attrs; 1840 } else { 1841 KASSERT(pv); 1842 tst_mask = pv->pv_va; 1843 pv = SLIST_NEXT(pv, pv_link); 1844 } 1845 /* 1846 * Only check for a bad alias if we have writable mappings. 1847 */ 1848 tst_mask &= arm_cache_prefer_mask; 1849 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1850 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1851 /* if there's a bad alias, stop checking. */ 1852 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1853 bad_alias = true; 1854 } 1855 md->pvh_attrs |= PVF_WRITE; 1856 if (!bad_alias) 1857 md->pvh_attrs |= PVF_DIRTY; 1858 } else { 1859 /* 1860 * We have only read-only mappings. Let's see if there 1861 * are multiple colors in use or if we mapped a KMPAGE. 1862 * If the latter, we have a bad alias. If the former, 1863 * we need to remember that. 1864 */ 1865 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1866 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1867 if (md->pvh_attrs & PVF_KMPAGE) 1868 bad_alias = true; 1869 break; 1870 } 1871 } 1872 md->pvh_attrs &= ~PVF_WRITE; 1873 /* 1874 * No KMPAGE and we exited early, so we must have 1875 * multiple color mappings. 1876 */ 1877 if (!bad_alias && pv != NULL) 1878 md->pvh_attrs |= PVF_MULTCLR; 1879 } 1880 1881 /* If no conflicting colors, set everything back to cached */ 1882 if (!bad_alias) { 1883 #ifdef DEBUG 1884 if ((md->pvh_attrs & PVF_WRITE) 1885 || ro_mappings < 2) { 1886 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1887 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1888 } 1889 #endif 1890 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1891 md->pvh_attrs |= tst_mask | PVF_COLORED; 1892 /* 1893 * Restore DIRTY bit if page is modified 1894 */ 1895 if (md->pvh_attrs & PVF_DMOD) 1896 md->pvh_attrs |= PVF_DIRTY; 1897 PMAPCOUNT(vac_color_restore); 1898 } else { 1899 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1900 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1901 } 1902 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1903 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1904 } else if (!va) { 1905 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1906 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1907 || (md->pvh_attrs & PVF_DIRTY)); 1908 if (rw_mappings == 0) { 1909 md->pvh_attrs &= ~PVF_WRITE; 1910 if (ro_mappings == 1 1911 && (md->pvh_attrs & PVF_MULTCLR)) { 1912 /* 1913 * If this is the last readonly mapping 1914 * but it doesn't match the current color 1915 * for the page, change the current color 1916 * to match this last readonly mapping. 1917 */ 1918 pv = SLIST_FIRST(&md->pvh_list); 1919 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1920 & arm_cache_prefer_mask; 1921 if (tst_mask) { 1922 md->pvh_attrs ^= tst_mask; 1923 PMAPCOUNT(vac_color_change); 1924 } 1925 } 1926 } 1927 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1928 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1929 return; 1930 } else if (!pmap_is_page_colored_p(md)) { 1931 /* not colored so we just use its color */ 1932 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1933 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1934 PMAPCOUNT(vac_color_new); 1935 md->pvh_attrs &= PAGE_SIZE - 1; 1936 md->pvh_attrs |= PVF_COLORED 1937 | (va & arm_cache_prefer_mask) 1938 | (rw_mappings > 0 ? PVF_WRITE : 0); 1939 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1940 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1941 return; 1942 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1943 bad_alias = false; 1944 if (rw_mappings > 0) { 1945 /* 1946 * We now have writeable mappings and if we have 1947 * readonly mappings in more than once color, we have 1948 * an aliasing problem. Regardless mark the page as 1949 * writeable. 1950 */ 1951 if (md->pvh_attrs & PVF_MULTCLR) { 1952 if (ro_mappings < 2) { 1953 /* 1954 * If we only have less than two 1955 * read-only mappings, just flush the 1956 * non-primary colors from the cache. 1957 */ 1958 pmap_flush_page(md, pa, 1959 PMAP_FLUSH_SECONDARY); 1960 } else { 1961 bad_alias = true; 1962 } 1963 } 1964 md->pvh_attrs |= PVF_WRITE; 1965 } 1966 /* If no conflicting colors, set everything back to cached */ 1967 if (!bad_alias) { 1968 #ifdef DEBUG 1969 if (rw_mappings > 0 1970 || (md->pvh_attrs & PMAP_KMPAGE)) { 1971 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1972 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1973 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1974 } 1975 #endif 1976 if (SLIST_EMPTY(&md->pvh_list)) 1977 PMAPCOUNT(vac_color_reuse); 1978 else 1979 PMAPCOUNT(vac_color_ok); 1980 1981 /* matching color, just return */ 1982 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1983 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1984 return; 1985 } 1986 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1987 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1988 1989 /* color conflict. evict from cache. */ 1990 1991 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 1992 md->pvh_attrs &= ~PVF_COLORED; 1993 md->pvh_attrs |= PVF_NC; 1994 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1995 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1996 PMAPCOUNT(vac_color_erase); 1997 } else if (rw_mappings == 0 1998 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 1999 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2000 2001 /* 2002 * If the page has dirty cache lines, clean it. 2003 */ 2004 if (md->pvh_attrs & PVF_DIRTY) 2005 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2006 2007 /* 2008 * If this is the first remapping (we know that there are no 2009 * writeable mappings), then this is a simple color change. 2010 * Otherwise this is a seconary r/o mapping, which means 2011 * we don't have to do anything. 2012 */ 2013 if (ro_mappings == 1) { 2014 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2015 md->pvh_attrs &= PAGE_SIZE - 1; 2016 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2017 PMAPCOUNT(vac_color_change); 2018 } else { 2019 PMAPCOUNT(vac_color_blind); 2020 } 2021 md->pvh_attrs |= PVF_MULTCLR; 2022 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2023 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2024 return; 2025 } else { 2026 if (rw_mappings > 0) 2027 md->pvh_attrs |= PVF_WRITE; 2028 2029 /* color conflict. evict from cache. */ 2030 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2031 2032 /* the list can't be empty because this was a enter/modify */ 2033 pv = SLIST_FIRST(&md->pvh_list); 2034 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2035 KASSERT(pv); 2036 /* 2037 * If there's only one mapped page, change color to the 2038 * page's new color and return. Restore the DIRTY bit 2039 * that was erased by pmap_flush_page. 2040 */ 2041 if (SLIST_NEXT(pv, pv_link) == NULL) { 2042 md->pvh_attrs &= PAGE_SIZE - 1; 2043 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2044 if (md->pvh_attrs & PVF_DMOD) 2045 md->pvh_attrs |= PVF_DIRTY; 2046 PMAPCOUNT(vac_color_change); 2047 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2048 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2049 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2050 return; 2051 } 2052 } 2053 bad_alias = true; 2054 md->pvh_attrs &= ~PVF_COLORED; 2055 md->pvh_attrs |= PVF_NC; 2056 PMAPCOUNT(vac_color_erase); 2057 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2058 } 2059 2060 fixup: 2061 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2062 2063 /* 2064 * Turn cacheing on/off for all pages. 2065 */ 2066 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2067 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2068 KDASSERT(l2b != NULL); 2069 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2070 opte = *ptep; 2071 pte = opte & ~L2_S_CACHE_MASK; 2072 if (bad_alias) { 2073 pv->pv_flags |= PVF_NC; 2074 } else { 2075 pv->pv_flags &= ~PVF_NC; 2076 pte |= pte_l2_s_cache_mode; 2077 } 2078 2079 if (opte == pte) /* only update is there's a change */ 2080 continue; 2081 2082 if (l2pte_valid(pte)) { 2083 if (PV_BEEN_EXECD(pv->pv_flags)) { 2084 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2085 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2086 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2087 } 2088 } 2089 2090 *ptep = pte; 2091 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2092 } 2093 } 2094 #endif /* PMAP_CACHE_VIPT */ 2095 2096 2097 /* 2098 * Modify pte bits for all ptes corresponding to the given physical address. 2099 * We use `maskbits' rather than `clearbits' because we're always passing 2100 * constants and the latter would require an extra inversion at run-time. 2101 */ 2102 static void 2103 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2104 { 2105 struct l2_bucket *l2b; 2106 struct pv_entry *pv; 2107 pt_entry_t *ptep, npte, opte; 2108 pmap_t pm; 2109 vaddr_t va; 2110 u_int oflags; 2111 #ifdef PMAP_CACHE_VIPT 2112 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2113 bool need_syncicache = false; 2114 bool did_syncicache = false; 2115 bool need_vac_me_harder = false; 2116 #endif 2117 2118 NPDEBUG(PDB_BITS, 2119 printf("pmap_clearbit: md %p mask 0x%x\n", 2120 md, maskbits)); 2121 2122 #ifdef PMAP_CACHE_VIPT 2123 /* 2124 * If we might want to sync the I-cache and we've modified it, 2125 * then we know we definitely need to sync or discard it. 2126 */ 2127 if (want_syncicache) 2128 need_syncicache = md->pvh_attrs & PVF_MOD; 2129 #endif 2130 /* 2131 * Clear saved attributes (modify, reference) 2132 */ 2133 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2134 2135 if (SLIST_EMPTY(&md->pvh_list)) { 2136 #ifdef PMAP_CACHE_VIPT 2137 if (need_syncicache) { 2138 /* 2139 * No one has it mapped, so just discard it. The next 2140 * exec remapping will cause it to be synced. 2141 */ 2142 md->pvh_attrs &= ~PVF_EXEC; 2143 PMAPCOUNT(exec_discarded_clearbit); 2144 } 2145 #endif 2146 return; 2147 } 2148 2149 /* 2150 * Loop over all current mappings setting/clearing as appropos 2151 */ 2152 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2153 va = pv->pv_va; 2154 pm = pv->pv_pmap; 2155 oflags = pv->pv_flags; 2156 /* 2157 * Kernel entries are unmanaged and as such not to be changed. 2158 */ 2159 if (oflags & PVF_KENTRY) 2160 continue; 2161 pv->pv_flags &= ~maskbits; 2162 2163 pmap_acquire_pmap_lock(pm); 2164 2165 l2b = pmap_get_l2_bucket(pm, va); 2166 KDASSERT(l2b != NULL); 2167 2168 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2169 npte = opte = *ptep; 2170 2171 NPDEBUG(PDB_BITS, 2172 printf( 2173 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2174 pv, pv->pv_pmap, pv->pv_va, oflags)); 2175 2176 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2177 #ifdef PMAP_CACHE_VIVT 2178 if ((pv->pv_flags & PVF_NC)) { 2179 /* 2180 * Entry is not cacheable: 2181 * 2182 * Don't turn caching on again if this is a 2183 * modified emulation. This would be 2184 * inconsitent with the settings created by 2185 * pmap_vac_me_harder(). Otherwise, it's safe 2186 * to re-enable cacheing. 2187 * 2188 * There's no need to call pmap_vac_me_harder() 2189 * here: all pages are losing their write 2190 * permission. 2191 */ 2192 if (maskbits & PVF_WRITE) { 2193 npte |= pte_l2_s_cache_mode; 2194 pv->pv_flags &= ~PVF_NC; 2195 } 2196 } else 2197 if (l2pte_writable_p(opte)) { 2198 /* 2199 * Entry is writable/cacheable: check if pmap 2200 * is current if it is flush it, otherwise it 2201 * won't be in the cache 2202 */ 2203 if (PV_BEEN_EXECD(oflags)) 2204 pmap_idcache_wbinv_range(pm, pv->pv_va, 2205 PAGE_SIZE); 2206 else 2207 if (PV_BEEN_REFD(oflags)) 2208 pmap_dcache_wb_range(pm, pv->pv_va, 2209 PAGE_SIZE, 2210 (maskbits & PVF_REF) != 0, false); 2211 } 2212 #endif 2213 2214 /* make the pte read only */ 2215 npte = l2pte_set_readonly(npte); 2216 2217 if (maskbits & oflags & PVF_WRITE) { 2218 /* 2219 * Keep alias accounting up to date 2220 */ 2221 if (pv->pv_pmap == pmap_kernel()) { 2222 md->krw_mappings--; 2223 md->kro_mappings++; 2224 } else { 2225 md->urw_mappings--; 2226 md->uro_mappings++; 2227 } 2228 #ifdef PMAP_CACHE_VIPT 2229 if (md->urw_mappings + md->krw_mappings == 0) 2230 md->pvh_attrs &= ~PVF_WRITE; 2231 if (want_syncicache) 2232 need_syncicache = true; 2233 need_vac_me_harder = true; 2234 #endif 2235 } 2236 } 2237 2238 if (maskbits & PVF_REF) { 2239 if ((pv->pv_flags & PVF_NC) == 0 && 2240 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2241 l2pte_valid(npte)) { 2242 #ifdef PMAP_CACHE_VIVT 2243 /* 2244 * Check npte here; we may have already 2245 * done the wbinv above, and the validity 2246 * of the PTE is the same for opte and 2247 * npte. 2248 */ 2249 /* XXXJRT need idcache_inv_range */ 2250 if (PV_BEEN_EXECD(oflags)) 2251 pmap_idcache_wbinv_range(pm, 2252 pv->pv_va, PAGE_SIZE); 2253 else 2254 if (PV_BEEN_REFD(oflags)) 2255 pmap_dcache_wb_range(pm, 2256 pv->pv_va, PAGE_SIZE, 2257 true, true); 2258 #endif 2259 } 2260 2261 /* 2262 * Make the PTE invalid so that we will take a 2263 * page fault the next time the mapping is 2264 * referenced. 2265 */ 2266 npte &= ~L2_TYPE_MASK; 2267 npte |= L2_TYPE_INV; 2268 } 2269 2270 if (npte != opte) { 2271 *ptep = npte; 2272 PTE_SYNC(ptep); 2273 /* Flush the TLB entry if a current pmap. */ 2274 if (PV_BEEN_EXECD(oflags)) 2275 pmap_tlb_flushID_SE(pm, pv->pv_va); 2276 else 2277 if (PV_BEEN_REFD(oflags)) 2278 pmap_tlb_flushD_SE(pm, pv->pv_va); 2279 } 2280 2281 pmap_release_pmap_lock(pm); 2282 2283 NPDEBUG(PDB_BITS, 2284 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2285 pm, va, opte, npte)); 2286 } 2287 2288 #ifdef PMAP_CACHE_VIPT 2289 /* 2290 * If we need to sync the I-cache and we haven't done it yet, do it. 2291 */ 2292 if (need_syncicache && !did_syncicache) { 2293 pmap_syncicache_page(md, pa); 2294 PMAPCOUNT(exec_synced_clearbit); 2295 } 2296 /* 2297 * If we are changing this to read-only, we need to call vac_me_harder 2298 * so we can change all the read-only pages to cacheable. We pretend 2299 * this as a page deletion. 2300 */ 2301 if (need_vac_me_harder) { 2302 if (md->pvh_attrs & PVF_NC) 2303 pmap_vac_me_harder(md, pa, NULL, 0); 2304 } 2305 #endif 2306 } 2307 2308 /* 2309 * pmap_clean_page() 2310 * 2311 * This is a local function used to work out the best strategy to clean 2312 * a single page referenced by its entry in the PV table. It's used by 2313 * pmap_copy_page, pmap_zero page and maybe some others later on. 2314 * 2315 * Its policy is effectively: 2316 * o If there are no mappings, we don't bother doing anything with the cache. 2317 * o If there is one mapping, we clean just that page. 2318 * o If there are multiple mappings, we clean the entire cache. 2319 * 2320 * So that some functions can be further optimised, it returns 0 if it didn't 2321 * clean the entire cache, or 1 if it did. 2322 * 2323 * XXX One bug in this routine is that if the pv_entry has a single page 2324 * mapped at 0x00000000 a whole cache clean will be performed rather than 2325 * just the 1 page. Since this should not occur in everyday use and if it does 2326 * it will just result in not the most efficient clean for the page. 2327 */ 2328 #ifdef PMAP_CACHE_VIVT 2329 static int 2330 pmap_clean_page(struct pv_entry *pv, bool is_src) 2331 { 2332 pmap_t pm_to_clean = NULL; 2333 struct pv_entry *npv; 2334 u_int cache_needs_cleaning = 0; 2335 u_int flags = 0; 2336 vaddr_t page_to_clean = 0; 2337 2338 if (pv == NULL) { 2339 /* nothing mapped in so nothing to flush */ 2340 return (0); 2341 } 2342 2343 /* 2344 * Since we flush the cache each time we change to a different 2345 * user vmspace, we only need to flush the page if it is in the 2346 * current pmap. 2347 */ 2348 2349 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2350 if (pmap_is_current(npv->pv_pmap)) { 2351 flags |= npv->pv_flags; 2352 /* 2353 * The page is mapped non-cacheable in 2354 * this map. No need to flush the cache. 2355 */ 2356 if (npv->pv_flags & PVF_NC) { 2357 #ifdef DIAGNOSTIC 2358 if (cache_needs_cleaning) 2359 panic("pmap_clean_page: " 2360 "cache inconsistency"); 2361 #endif 2362 break; 2363 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2364 continue; 2365 if (cache_needs_cleaning) { 2366 page_to_clean = 0; 2367 break; 2368 } else { 2369 page_to_clean = npv->pv_va; 2370 pm_to_clean = npv->pv_pmap; 2371 } 2372 cache_needs_cleaning = 1; 2373 } 2374 } 2375 2376 if (page_to_clean) { 2377 if (PV_BEEN_EXECD(flags)) 2378 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2379 PAGE_SIZE); 2380 else 2381 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2382 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2383 } else if (cache_needs_cleaning) { 2384 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2385 2386 if (PV_BEEN_EXECD(flags)) 2387 pmap_idcache_wbinv_all(pm); 2388 else 2389 pmap_dcache_wbinv_all(pm); 2390 return (1); 2391 } 2392 return (0); 2393 } 2394 #endif 2395 2396 #ifdef PMAP_CACHE_VIPT 2397 /* 2398 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2399 * right cache alias to make sure we flush the right stuff. 2400 */ 2401 void 2402 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2403 { 2404 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2405 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2406 2407 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2408 md, md->pvh_attrs)); 2409 /* 2410 * No need to clean the page if it's non-cached. 2411 */ 2412 if (md->pvh_attrs & PVF_NC) 2413 return; 2414 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2415 2416 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2417 /* 2418 * Set up a PTE with the right coloring to flush existing cache lines. 2419 */ 2420 *ptep = L2_S_PROTO | 2421 pa 2422 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2423 | pte_l2_s_cache_mode; 2424 PTE_SYNC(ptep); 2425 2426 /* 2427 * Flush it. 2428 */ 2429 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2430 /* 2431 * Unmap the page. 2432 */ 2433 *ptep = 0; 2434 PTE_SYNC(ptep); 2435 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2436 2437 md->pvh_attrs |= PVF_EXEC; 2438 PMAPCOUNT(exec_synced); 2439 } 2440 2441 void 2442 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2443 { 2444 vsize_t va_offset, end_va; 2445 void (*cf)(vaddr_t, vsize_t); 2446 2447 if (arm_cache_prefer_mask == 0) 2448 return; 2449 2450 switch (flush) { 2451 case PMAP_FLUSH_PRIMARY: 2452 if (md->pvh_attrs & PVF_MULTCLR) { 2453 va_offset = 0; 2454 end_va = arm_cache_prefer_mask; 2455 md->pvh_attrs &= ~PVF_MULTCLR; 2456 PMAPCOUNT(vac_flush_lots); 2457 } else { 2458 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2459 end_va = va_offset; 2460 PMAPCOUNT(vac_flush_one); 2461 } 2462 /* 2463 * Mark that the page is no longer dirty. 2464 */ 2465 md->pvh_attrs &= ~PVF_DIRTY; 2466 cf = cpufuncs.cf_idcache_wbinv_range; 2467 break; 2468 case PMAP_FLUSH_SECONDARY: 2469 va_offset = 0; 2470 end_va = arm_cache_prefer_mask; 2471 cf = cpufuncs.cf_idcache_wbinv_range; 2472 md->pvh_attrs &= ~PVF_MULTCLR; 2473 PMAPCOUNT(vac_flush_lots); 2474 break; 2475 case PMAP_CLEAN_PRIMARY: 2476 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2477 end_va = va_offset; 2478 cf = cpufuncs.cf_dcache_wb_range; 2479 /* 2480 * Mark that the page is no longer dirty. 2481 */ 2482 if ((md->pvh_attrs & PVF_DMOD) == 0) 2483 md->pvh_attrs &= ~PVF_DIRTY; 2484 PMAPCOUNT(vac_clean_one); 2485 break; 2486 default: 2487 return; 2488 } 2489 2490 KASSERT(!(md->pvh_attrs & PVF_NC)); 2491 2492 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2493 md, md->pvh_attrs)); 2494 2495 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2496 const size_t pte_offset = va_offset >> PGSHIFT; 2497 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2498 const pt_entry_t oldpte = *ptep; 2499 2500 if (flush == PMAP_FLUSH_SECONDARY 2501 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2502 continue; 2503 2504 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2505 /* 2506 * Set up a PTE with the right coloring to flush 2507 * existing cache entries. 2508 */ 2509 *ptep = L2_S_PROTO 2510 | pa 2511 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2512 | pte_l2_s_cache_mode; 2513 PTE_SYNC(ptep); 2514 2515 /* 2516 * Flush it. 2517 */ 2518 (*cf)(cdstp + va_offset, PAGE_SIZE); 2519 2520 /* 2521 * Restore the page table entry since we might have interrupted 2522 * pmap_zero_page or pmap_copy_page which was already using 2523 * this pte. 2524 */ 2525 *ptep = oldpte; 2526 PTE_SYNC(ptep); 2527 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2528 } 2529 } 2530 #endif /* PMAP_CACHE_VIPT */ 2531 2532 /* 2533 * Routine: pmap_page_remove 2534 * Function: 2535 * Removes this physical page from 2536 * all physical maps in which it resides. 2537 * Reflects back modify bits to the pager. 2538 */ 2539 static void 2540 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2541 { 2542 struct l2_bucket *l2b; 2543 struct pv_entry *pv, *npv, **pvp; 2544 pmap_t pm; 2545 pt_entry_t *ptep; 2546 bool flush; 2547 u_int flags; 2548 2549 NPDEBUG(PDB_FOLLOW, 2550 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2551 pa)); 2552 2553 pv = SLIST_FIRST(&md->pvh_list); 2554 if (pv == NULL) { 2555 #ifdef PMAP_CACHE_VIPT 2556 /* 2557 * We *know* the page contents are about to be replaced. 2558 * Discard the exec contents 2559 */ 2560 if (PV_IS_EXEC_P(md->pvh_attrs)) 2561 PMAPCOUNT(exec_discarded_page_protect); 2562 md->pvh_attrs &= ~PVF_EXEC; 2563 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2564 #endif 2565 return; 2566 } 2567 #ifdef PMAP_CACHE_VIPT 2568 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2569 #endif 2570 2571 /* 2572 * Clear alias counts 2573 */ 2574 #ifdef PMAP_CACHE_VIVT 2575 md->k_mappings = 0; 2576 #endif 2577 md->urw_mappings = md->uro_mappings = 0; 2578 2579 flush = false; 2580 flags = 0; 2581 2582 #ifdef PMAP_CACHE_VIVT 2583 pmap_clean_page(pv, false); 2584 #endif 2585 2586 pvp = &SLIST_FIRST(&md->pvh_list); 2587 while (pv) { 2588 pm = pv->pv_pmap; 2589 npv = SLIST_NEXT(pv, pv_link); 2590 if (flush == false && pmap_is_current(pm)) 2591 flush = true; 2592 2593 if (pm == pmap_kernel()) { 2594 #ifdef PMAP_CACHE_VIPT 2595 /* 2596 * If this was unmanaged mapping, it must be preserved. 2597 * Move it back on the list and advance the end-of-list 2598 * pointer. 2599 */ 2600 if (pv->pv_flags & PVF_KENTRY) { 2601 *pvp = pv; 2602 pvp = &SLIST_NEXT(pv, pv_link); 2603 pv = npv; 2604 continue; 2605 } 2606 if (pv->pv_flags & PVF_WRITE) 2607 md->krw_mappings--; 2608 else 2609 md->kro_mappings--; 2610 #endif 2611 PMAPCOUNT(kernel_unmappings); 2612 } 2613 PMAPCOUNT(unmappings); 2614 2615 pmap_acquire_pmap_lock(pm); 2616 2617 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2618 KDASSERT(l2b != NULL); 2619 2620 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2621 2622 /* 2623 * Update statistics 2624 */ 2625 --pm->pm_stats.resident_count; 2626 2627 /* Wired bit */ 2628 if (pv->pv_flags & PVF_WIRED) 2629 --pm->pm_stats.wired_count; 2630 2631 flags |= pv->pv_flags; 2632 2633 /* 2634 * Invalidate the PTEs. 2635 */ 2636 *ptep = 0; 2637 PTE_SYNC_CURRENT(pm, ptep); 2638 pmap_free_l2_bucket(pm, l2b, 1); 2639 2640 pool_put(&pmap_pv_pool, pv); 2641 pv = npv; 2642 /* 2643 * if we reach the end of the list and there are still 2644 * mappings, they might be able to be cached now. 2645 */ 2646 if (pv == NULL) { 2647 *pvp = NULL; 2648 if (!SLIST_EMPTY(&md->pvh_list)) 2649 pmap_vac_me_harder(md, pa, pm, 0); 2650 } 2651 pmap_release_pmap_lock(pm); 2652 } 2653 #ifdef PMAP_CACHE_VIPT 2654 /* 2655 * Its EXEC cache is now gone. 2656 */ 2657 if (PV_IS_EXEC_P(md->pvh_attrs)) 2658 PMAPCOUNT(exec_discarded_page_protect); 2659 md->pvh_attrs &= ~PVF_EXEC; 2660 KASSERT(md->urw_mappings == 0); 2661 KASSERT(md->uro_mappings == 0); 2662 if (md->krw_mappings == 0) 2663 md->pvh_attrs &= ~PVF_WRITE; 2664 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2665 #endif 2666 2667 if (flush) { 2668 /* 2669 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2670 * would need a subsequent call to pmap_update() to ensure 2671 * curpm->pm_cstate.cs_all is reset. Our callers are not 2672 * required to do that (see pmap(9)), so we can't modify 2673 * the current pmap's state. 2674 */ 2675 if (PV_BEEN_EXECD(flags)) 2676 cpu_tlb_flushID(); 2677 else 2678 cpu_tlb_flushD(); 2679 } 2680 cpu_cpwait(); 2681 } 2682 2683 /* 2684 * pmap_t pmap_create(void) 2685 * 2686 * Create a new pmap structure from scratch. 2687 */ 2688 pmap_t 2689 pmap_create(void) 2690 { 2691 pmap_t pm; 2692 2693 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2694 2695 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2696 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2697 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2698 2699 pm->pm_stats.wired_count = 0; 2700 pm->pm_stats.resident_count = 1; 2701 pm->pm_cstate.cs_all = 0; 2702 pmap_alloc_l1(pm); 2703 2704 /* 2705 * Note: The pool cache ensures that the pm_l2[] array is already 2706 * initialised to zero. 2707 */ 2708 2709 pmap_pinit(pm); 2710 2711 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2712 2713 return (pm); 2714 } 2715 2716 u_int 2717 arm32_mmap_flags(paddr_t pa) 2718 { 2719 /* 2720 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 2721 * and we're using the upper bits in page numbers to pass flags around 2722 * so we might as well use the same bits 2723 */ 2724 return (u_int)pa & PMAP_MD_MASK; 2725 } 2726 /* 2727 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2728 * u_int flags) 2729 * 2730 * Insert the given physical page (p) at 2731 * the specified virtual address (v) in the 2732 * target physical map with the protection requested. 2733 * 2734 * NB: This is the only routine which MAY NOT lazy-evaluate 2735 * or lose information. That is, this routine must actually 2736 * insert this page into the given map NOW. 2737 */ 2738 int 2739 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2740 { 2741 struct l2_bucket *l2b; 2742 struct vm_page *pg, *opg; 2743 struct pv_entry *pv; 2744 pt_entry_t *ptep, npte, opte; 2745 u_int nflags; 2746 u_int oflags; 2747 2748 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2749 2750 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2751 KDASSERT(((va | pa) & PGOFSET) == 0); 2752 2753 /* 2754 * Get a pointer to the page. Later on in this function, we 2755 * test for a managed page by checking pg != NULL. 2756 */ 2757 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2758 2759 nflags = 0; 2760 if (prot & VM_PROT_WRITE) 2761 nflags |= PVF_WRITE; 2762 if (prot & VM_PROT_EXECUTE) 2763 nflags |= PVF_EXEC; 2764 if (flags & PMAP_WIRED) 2765 nflags |= PVF_WIRED; 2766 2767 pmap_acquire_pmap_lock(pm); 2768 2769 /* 2770 * Fetch the L2 bucket which maps this page, allocating one if 2771 * necessary for user pmaps. 2772 */ 2773 if (pm == pmap_kernel()) 2774 l2b = pmap_get_l2_bucket(pm, va); 2775 else 2776 l2b = pmap_alloc_l2_bucket(pm, va); 2777 if (l2b == NULL) { 2778 if (flags & PMAP_CANFAIL) { 2779 pmap_release_pmap_lock(pm); 2780 return (ENOMEM); 2781 } 2782 panic("pmap_enter: failed to allocate L2 bucket"); 2783 } 2784 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2785 opte = *ptep; 2786 npte = pa; 2787 oflags = 0; 2788 2789 if (opte) { 2790 /* 2791 * There is already a mapping at this address. 2792 * If the physical address is different, lookup the 2793 * vm_page. 2794 */ 2795 if (l2pte_pa(opte) != pa) 2796 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2797 else 2798 opg = pg; 2799 } else 2800 opg = NULL; 2801 2802 if (pg) { 2803 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2804 2805 /* 2806 * This is to be a managed mapping. 2807 */ 2808 if ((flags & VM_PROT_ALL) || 2809 (md->pvh_attrs & PVF_REF)) { 2810 /* 2811 * - The access type indicates that we don't need 2812 * to do referenced emulation. 2813 * OR 2814 * - The physical page has already been referenced 2815 * so no need to re-do referenced emulation here. 2816 */ 2817 npte |= l2pte_set_readonly(L2_S_PROTO); 2818 2819 nflags |= PVF_REF; 2820 2821 if ((prot & VM_PROT_WRITE) != 0 && 2822 ((flags & VM_PROT_WRITE) != 0 || 2823 (md->pvh_attrs & PVF_MOD) != 0)) { 2824 /* 2825 * This is a writable mapping, and the 2826 * page's mod state indicates it has 2827 * already been modified. Make it 2828 * writable from the outset. 2829 */ 2830 npte = l2pte_set_writable(npte); 2831 nflags |= PVF_MOD; 2832 } 2833 } else { 2834 /* 2835 * Need to do page referenced emulation. 2836 */ 2837 npte |= L2_TYPE_INV; 2838 } 2839 2840 npte |= pte_l2_s_cache_mode; 2841 2842 if (pg == opg) { 2843 /* 2844 * We're changing the attrs of an existing mapping. 2845 */ 2846 #ifdef MULTIPROCESSOR 2847 KASSERT(uvm_page_locked_p(pg)); 2848 #endif 2849 oflags = pmap_modify_pv(md, pa, pm, va, 2850 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2851 PVF_MOD | PVF_REF, nflags); 2852 2853 #ifdef PMAP_CACHE_VIVT 2854 /* 2855 * We may need to flush the cache if we're 2856 * doing rw-ro... 2857 */ 2858 if (pm->pm_cstate.cs_cache_d && 2859 (oflags & PVF_NC) == 0 && 2860 l2pte_writable_p(opte) && 2861 (prot & VM_PROT_WRITE) == 0) 2862 cpu_dcache_wb_range(va, PAGE_SIZE); 2863 #endif 2864 } else { 2865 /* 2866 * New mapping, or changing the backing page 2867 * of an existing mapping. 2868 */ 2869 if (opg) { 2870 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2871 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2872 2873 /* 2874 * Replacing an existing mapping with a new one. 2875 * It is part of our managed memory so we 2876 * must remove it from the PV list 2877 */ 2878 #ifdef MULTIPROCESSOR 2879 KASSERT(uvm_page_locked_p(opg)); 2880 #endif 2881 pv = pmap_remove_pv(omd, opa, pm, va); 2882 pmap_vac_me_harder(omd, opa, pm, 0); 2883 oflags = pv->pv_flags; 2884 2885 #ifdef PMAP_CACHE_VIVT 2886 /* 2887 * If the old mapping was valid (ref/mod 2888 * emulation creates 'invalid' mappings 2889 * initially) then make sure to frob 2890 * the cache. 2891 */ 2892 if ((oflags & PVF_NC) == 0 && 2893 l2pte_valid(opte)) { 2894 if (PV_BEEN_EXECD(oflags)) { 2895 pmap_idcache_wbinv_range(pm, va, 2896 PAGE_SIZE); 2897 } else 2898 if (PV_BEEN_REFD(oflags)) { 2899 pmap_dcache_wb_range(pm, va, 2900 PAGE_SIZE, true, 2901 (oflags & PVF_WRITE) == 0); 2902 } 2903 } 2904 #endif 2905 } else 2906 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2907 if ((flags & PMAP_CANFAIL) == 0) 2908 panic("pmap_enter: no pv entries"); 2909 2910 if (pm != pmap_kernel()) 2911 pmap_free_l2_bucket(pm, l2b, 0); 2912 pmap_release_pmap_lock(pm); 2913 NPDEBUG(PDB_ENTER, 2914 printf("pmap_enter: ENOMEM\n")); 2915 return (ENOMEM); 2916 } 2917 2918 #ifdef MULTIPROCESSOR 2919 KASSERT(uvm_page_locked_p(pg)); 2920 #endif 2921 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2922 } 2923 } else { 2924 /* 2925 * We're mapping an unmanaged page. 2926 * These are always readable, and possibly writable, from 2927 * the get go as we don't need to track ref/mod status. 2928 */ 2929 npte |= l2pte_set_readonly(L2_S_PROTO); 2930 if (prot & VM_PROT_WRITE) 2931 npte = l2pte_set_writable(npte); 2932 2933 /* 2934 * Make sure the vector table is mapped cacheable 2935 */ 2936 if ((pm != pmap_kernel() && va == vector_page) || 2937 (flags & ARM32_MMAP_CACHEABLE)) { 2938 npte |= pte_l2_s_cache_mode; 2939 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 2940 npte |= pte_l2_s_wc_mode; 2941 } 2942 if (opg) { 2943 /* 2944 * Looks like there's an existing 'managed' mapping 2945 * at this address. 2946 */ 2947 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2948 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2949 2950 #ifdef MULTIPROCESSOR 2951 KASSERT(uvm_page_locked_p(opg)); 2952 #endif 2953 pv = pmap_remove_pv(omd, opa, pm, va); 2954 pmap_vac_me_harder(omd, opa, pm, 0); 2955 oflags = pv->pv_flags; 2956 2957 #ifdef PMAP_CACHE_VIVT 2958 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2959 if (PV_BEEN_EXECD(oflags)) 2960 pmap_idcache_wbinv_range(pm, va, 2961 PAGE_SIZE); 2962 else 2963 if (PV_BEEN_REFD(oflags)) 2964 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2965 true, (oflags & PVF_WRITE) == 0); 2966 } 2967 #endif 2968 pool_put(&pmap_pv_pool, pv); 2969 } 2970 } 2971 2972 /* 2973 * Make sure userland mappings get the right permissions 2974 */ 2975 if (pm != pmap_kernel() && va != vector_page) 2976 npte |= L2_S_PROT_U; 2977 2978 /* 2979 * Keep the stats up to date 2980 */ 2981 if (opte == 0) { 2982 l2b->l2b_occupancy++; 2983 pm->pm_stats.resident_count++; 2984 } 2985 2986 NPDEBUG(PDB_ENTER, 2987 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2988 2989 /* 2990 * If this is just a wiring change, the two PTEs will be 2991 * identical, so there's no need to update the page table. 2992 */ 2993 if (npte != opte) { 2994 bool is_cached = pmap_is_cached(pm); 2995 2996 *ptep = npte; 2997 if (is_cached) { 2998 /* 2999 * We only need to frob the cache/tlb if this pmap 3000 * is current 3001 */ 3002 PTE_SYNC(ptep); 3003 if (va != vector_page && l2pte_valid(npte)) { 3004 /* 3005 * This mapping is likely to be accessed as 3006 * soon as we return to userland. Fix up the 3007 * L1 entry to avoid taking another 3008 * page/domain fault. 3009 */ 3010 pd_entry_t *pl1pd, l1pd; 3011 3012 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3013 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3014 L1_C_PROTO; 3015 if (*pl1pd != l1pd) { 3016 *pl1pd = l1pd; 3017 PTE_SYNC(pl1pd); 3018 } 3019 } 3020 } 3021 3022 if (PV_BEEN_EXECD(oflags)) 3023 pmap_tlb_flushID_SE(pm, va); 3024 else 3025 if (PV_BEEN_REFD(oflags)) 3026 pmap_tlb_flushD_SE(pm, va); 3027 3028 NPDEBUG(PDB_ENTER, 3029 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3030 is_cached, pm->pm_cstate.cs_all)); 3031 3032 if (pg != NULL) { 3033 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3034 3035 #ifdef MULTIPROCESSOR 3036 KASSERT(uvm_page_locked_p(pg)); 3037 #endif 3038 pmap_vac_me_harder(md, pa, pm, va); 3039 } 3040 } 3041 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3042 if (pg) { 3043 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3044 3045 #ifdef MULTIPROCESSOR 3046 KASSERT(uvm_page_locked_p(pg)); 3047 #endif 3048 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3049 KASSERT(((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0)); 3050 } 3051 #endif 3052 3053 pmap_release_pmap_lock(pm); 3054 3055 return (0); 3056 } 3057 3058 /* 3059 * pmap_remove() 3060 * 3061 * pmap_remove is responsible for nuking a number of mappings for a range 3062 * of virtual address space in the current pmap. To do this efficiently 3063 * is interesting, because in a number of cases a wide virtual address 3064 * range may be supplied that contains few actual mappings. So, the 3065 * optimisations are: 3066 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3067 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3068 * maybe do just a partial cache clean. This path of execution is 3069 * complicated by the fact that the cache must be flushed _before_ 3070 * the PTE is nuked, being a VAC :-) 3071 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3072 * all invalidations until pmap_update(), since pmap_remove_all() has 3073 * already flushed the cache. 3074 * 4. Maybe later fast-case a single page, but I don't think this is 3075 * going to make _that_ much difference overall. 3076 */ 3077 3078 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3079 3080 void 3081 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3082 { 3083 struct l2_bucket *l2b; 3084 vaddr_t next_bucket; 3085 pt_entry_t *ptep; 3086 u_int cleanlist_idx, total, cnt; 3087 struct { 3088 vaddr_t va; 3089 pt_entry_t *ptep; 3090 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3091 u_int mappings, is_exec, is_refd; 3092 3093 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3094 "eva=%08lx\n", pm, sva, eva)); 3095 3096 /* 3097 * we lock in the pmap => pv_head direction 3098 */ 3099 pmap_acquire_pmap_lock(pm); 3100 3101 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3102 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3103 if (pm->pm_cstate.cs_tlb == 0) 3104 pm->pm_remove_all = true; 3105 } else 3106 cleanlist_idx = 0; 3107 3108 total = 0; 3109 3110 while (sva < eva) { 3111 /* 3112 * Do one L2 bucket's worth at a time. 3113 */ 3114 next_bucket = L2_NEXT_BUCKET(sva); 3115 if (next_bucket > eva) 3116 next_bucket = eva; 3117 3118 l2b = pmap_get_l2_bucket(pm, sva); 3119 if (l2b == NULL) { 3120 sva = next_bucket; 3121 continue; 3122 } 3123 3124 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3125 3126 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3127 struct vm_page *pg; 3128 pt_entry_t pte; 3129 paddr_t pa; 3130 3131 pte = *ptep; 3132 3133 if (pte == 0) { 3134 /* Nothing here, move along */ 3135 continue; 3136 } 3137 3138 pa = l2pte_pa(pte); 3139 is_exec = 0; 3140 is_refd = 1; 3141 3142 /* 3143 * Update flags. In a number of circumstances, 3144 * we could cluster a lot of these and do a 3145 * number of sequential pages in one go. 3146 */ 3147 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3148 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3149 struct pv_entry *pv; 3150 3151 #ifdef MULTIPROCESSOR 3152 KASSERT(uvm_page_locked_p(pg)); 3153 #endif 3154 pv = pmap_remove_pv(md, pa, pm, sva); 3155 pmap_vac_me_harder(md, pa, pm, 0); 3156 if (pv != NULL) { 3157 if (pm->pm_remove_all == false) { 3158 is_exec = 3159 PV_BEEN_EXECD(pv->pv_flags); 3160 is_refd = 3161 PV_BEEN_REFD(pv->pv_flags); 3162 } 3163 pool_put(&pmap_pv_pool, pv); 3164 } 3165 } 3166 mappings++; 3167 3168 if (!l2pte_valid(pte)) { 3169 /* 3170 * Ref/Mod emulation is still active for this 3171 * mapping, therefore it is has not yet been 3172 * accessed. No need to frob the cache/tlb. 3173 */ 3174 *ptep = 0; 3175 PTE_SYNC_CURRENT(pm, ptep); 3176 continue; 3177 } 3178 3179 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3180 /* Add to the clean list. */ 3181 cleanlist[cleanlist_idx].ptep = ptep; 3182 cleanlist[cleanlist_idx].va = 3183 sva | (is_exec & 1); 3184 cleanlist_idx++; 3185 } else 3186 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3187 /* Nuke everything if needed. */ 3188 #ifdef PMAP_CACHE_VIVT 3189 pmap_idcache_wbinv_all(pm); 3190 #endif 3191 pmap_tlb_flushID(pm); 3192 3193 /* 3194 * Roll back the previous PTE list, 3195 * and zero out the current PTE. 3196 */ 3197 for (cnt = 0; 3198 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3199 *cleanlist[cnt].ptep = 0; 3200 PTE_SYNC(cleanlist[cnt].ptep); 3201 } 3202 *ptep = 0; 3203 PTE_SYNC(ptep); 3204 cleanlist_idx++; 3205 pm->pm_remove_all = true; 3206 } else { 3207 *ptep = 0; 3208 PTE_SYNC(ptep); 3209 if (pm->pm_remove_all == false) { 3210 if (is_exec) 3211 pmap_tlb_flushID_SE(pm, sva); 3212 else 3213 if (is_refd) 3214 pmap_tlb_flushD_SE(pm, sva); 3215 } 3216 } 3217 } 3218 3219 /* 3220 * Deal with any left overs 3221 */ 3222 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3223 total += cleanlist_idx; 3224 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3225 if (pm->pm_cstate.cs_all != 0) { 3226 vaddr_t clva = cleanlist[cnt].va & ~1; 3227 if (cleanlist[cnt].va & 1) { 3228 #ifdef PMAP_CACHE_VIVT 3229 pmap_idcache_wbinv_range(pm, 3230 clva, PAGE_SIZE); 3231 #endif 3232 pmap_tlb_flushID_SE(pm, clva); 3233 } else { 3234 #ifdef PMAP_CACHE_VIVT 3235 pmap_dcache_wb_range(pm, 3236 clva, PAGE_SIZE, true, 3237 false); 3238 #endif 3239 pmap_tlb_flushD_SE(pm, clva); 3240 } 3241 } 3242 *cleanlist[cnt].ptep = 0; 3243 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3244 } 3245 3246 /* 3247 * If it looks like we're removing a whole bunch 3248 * of mappings, it's faster to just write-back 3249 * the whole cache now and defer TLB flushes until 3250 * pmap_update() is called. 3251 */ 3252 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3253 cleanlist_idx = 0; 3254 else { 3255 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3256 #ifdef PMAP_CACHE_VIVT 3257 pmap_idcache_wbinv_all(pm); 3258 #endif 3259 pm->pm_remove_all = true; 3260 } 3261 } 3262 3263 pmap_free_l2_bucket(pm, l2b, mappings); 3264 pm->pm_stats.resident_count -= mappings; 3265 } 3266 3267 pmap_release_pmap_lock(pm); 3268 } 3269 3270 #ifdef PMAP_CACHE_VIPT 3271 static struct pv_entry * 3272 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3273 { 3274 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3275 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3276 struct pv_entry *pv; 3277 3278 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3279 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3280 3281 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3282 KASSERT(pv); 3283 KASSERT(pv->pv_flags & PVF_KENTRY); 3284 3285 /* 3286 * If we are removing a writeable mapping to a cached exec page, 3287 * if it's the last mapping then clear it execness other sync 3288 * the page to the icache. 3289 */ 3290 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3291 && (pv->pv_flags & PVF_WRITE) != 0) { 3292 if (SLIST_EMPTY(&md->pvh_list)) { 3293 md->pvh_attrs &= ~PVF_EXEC; 3294 PMAPCOUNT(exec_discarded_kremove); 3295 } else { 3296 pmap_syncicache_page(md, pa); 3297 PMAPCOUNT(exec_synced_kremove); 3298 } 3299 } 3300 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3301 3302 return pv; 3303 } 3304 #endif /* PMAP_CACHE_VIPT */ 3305 3306 /* 3307 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3308 * 3309 * We assume there is already sufficient KVM space available 3310 * to do this, as we can't allocate L2 descriptor tables/metadata 3311 * from here. 3312 */ 3313 void 3314 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3315 { 3316 struct l2_bucket *l2b; 3317 pt_entry_t *ptep, opte; 3318 #ifdef PMAP_CACHE_VIVT 3319 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3320 #endif 3321 #ifdef PMAP_CACHE_VIPT 3322 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3323 struct vm_page *opg; 3324 struct pv_entry *pv = NULL; 3325 #endif 3326 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3327 3328 NPDEBUG(PDB_KENTER, 3329 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3330 va, pa, prot)); 3331 3332 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3333 KDASSERT(l2b != NULL); 3334 3335 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3336 opte = *ptep; 3337 3338 if (opte == 0) { 3339 PMAPCOUNT(kenter_mappings); 3340 l2b->l2b_occupancy++; 3341 } else { 3342 PMAPCOUNT(kenter_remappings); 3343 #ifdef PMAP_CACHE_VIPT 3344 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3345 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3346 if (opg) { 3347 KASSERT(opg != pg); 3348 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3349 KASSERT((flags & PMAP_KMPAGE) == 0); 3350 pv = pmap_kremove_pg(opg, va); 3351 } 3352 #endif 3353 if (l2pte_valid(opte)) { 3354 #ifdef PMAP_CACHE_VIVT 3355 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3356 #endif 3357 cpu_tlb_flushD_SE(va); 3358 cpu_cpwait(); 3359 } 3360 } 3361 3362 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3363 pte_l2_s_cache_mode; 3364 PTE_SYNC(ptep); 3365 3366 if (pg) { 3367 #ifdef MULTIPROCESSOR 3368 KASSERT(uvm_page_locked_p(pg)); 3369 #endif 3370 if (flags & PMAP_KMPAGE) { 3371 KASSERT(md->urw_mappings == 0); 3372 KASSERT(md->uro_mappings == 0); 3373 KASSERT(md->krw_mappings == 0); 3374 KASSERT(md->kro_mappings == 0); 3375 #ifdef PMAP_CACHE_VIPT 3376 KASSERT(pv == NULL); 3377 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3378 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3379 /* if there is a color conflict, evict from cache. */ 3380 if (pmap_is_page_colored_p(md) 3381 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3382 PMAPCOUNT(vac_color_change); 3383 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3384 } else if (md->pvh_attrs & PVF_MULTCLR) { 3385 /* 3386 * If this page has multiple colors, expunge 3387 * them. 3388 */ 3389 PMAPCOUNT(vac_flush_lots2); 3390 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3391 } 3392 md->pvh_attrs &= PAGE_SIZE - 1; 3393 md->pvh_attrs |= PVF_KMPAGE 3394 | PVF_COLORED | PVF_DIRTY 3395 | (va & arm_cache_prefer_mask); 3396 #endif 3397 #ifdef PMAP_CACHE_VIVT 3398 md->pvh_attrs |= PVF_KMPAGE; 3399 #endif 3400 pmap_kmpages++; 3401 #ifdef PMAP_CACHE_VIPT 3402 } else { 3403 if (pv == NULL) { 3404 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3405 KASSERT(pv != NULL); 3406 } 3407 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3408 PVF_WIRED | PVF_KENTRY 3409 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3410 if ((prot & VM_PROT_WRITE) 3411 && !(md->pvh_attrs & PVF_NC)) 3412 md->pvh_attrs |= PVF_DIRTY; 3413 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3414 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3415 #endif 3416 } 3417 #ifdef PMAP_CACHE_VIPT 3418 } else { 3419 if (pv != NULL) 3420 pool_put(&pmap_pv_pool, pv); 3421 #endif 3422 } 3423 } 3424 3425 void 3426 pmap_kremove(vaddr_t va, vsize_t len) 3427 { 3428 struct l2_bucket *l2b; 3429 pt_entry_t *ptep, *sptep, opte; 3430 vaddr_t next_bucket, eva; 3431 u_int mappings; 3432 struct vm_page *opg; 3433 3434 PMAPCOUNT(kenter_unmappings); 3435 3436 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3437 va, len)); 3438 3439 eva = va + len; 3440 3441 while (va < eva) { 3442 next_bucket = L2_NEXT_BUCKET(va); 3443 if (next_bucket > eva) 3444 next_bucket = eva; 3445 3446 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3447 KDASSERT(l2b != NULL); 3448 3449 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3450 mappings = 0; 3451 3452 while (va < next_bucket) { 3453 opte = *ptep; 3454 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3455 if (opg) { 3456 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3457 3458 if (omd->pvh_attrs & PVF_KMPAGE) { 3459 KASSERT(omd->urw_mappings == 0); 3460 KASSERT(omd->uro_mappings == 0); 3461 KASSERT(omd->krw_mappings == 0); 3462 KASSERT(omd->kro_mappings == 0); 3463 omd->pvh_attrs &= ~PVF_KMPAGE; 3464 #ifdef PMAP_CACHE_VIPT 3465 omd->pvh_attrs &= ~PVF_WRITE; 3466 #endif 3467 pmap_kmpages--; 3468 #ifdef PMAP_CACHE_VIPT 3469 } else { 3470 pool_put(&pmap_pv_pool, 3471 pmap_kremove_pg(opg, va)); 3472 #endif 3473 } 3474 } 3475 if (l2pte_valid(opte)) { 3476 #ifdef PMAP_CACHE_VIVT 3477 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3478 #endif 3479 cpu_tlb_flushD_SE(va); 3480 } 3481 if (opte) { 3482 *ptep = 0; 3483 mappings++; 3484 } 3485 va += PAGE_SIZE; 3486 ptep++; 3487 } 3488 KDASSERT(mappings <= l2b->l2b_occupancy); 3489 l2b->l2b_occupancy -= mappings; 3490 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3491 } 3492 cpu_cpwait(); 3493 } 3494 3495 bool 3496 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3497 { 3498 struct l2_dtable *l2; 3499 pd_entry_t *pl1pd, l1pd; 3500 pt_entry_t *ptep, pte; 3501 paddr_t pa; 3502 u_int l1idx; 3503 3504 pmap_acquire_pmap_lock(pm); 3505 3506 l1idx = L1_IDX(va); 3507 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3508 l1pd = *pl1pd; 3509 3510 if (l1pte_section_p(l1pd)) { 3511 /* 3512 * These should only happen for pmap_kernel() 3513 */ 3514 KDASSERT(pm == pmap_kernel()); 3515 pmap_release_pmap_lock(pm); 3516 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3517 } else { 3518 /* 3519 * Note that we can't rely on the validity of the L1 3520 * descriptor as an indication that a mapping exists. 3521 * We have to look it up in the L2 dtable. 3522 */ 3523 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3524 3525 if (l2 == NULL || 3526 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3527 pmap_release_pmap_lock(pm); 3528 return false; 3529 } 3530 3531 ptep = &ptep[l2pte_index(va)]; 3532 pte = *ptep; 3533 pmap_release_pmap_lock(pm); 3534 3535 if (pte == 0) 3536 return false; 3537 3538 switch (pte & L2_TYPE_MASK) { 3539 case L2_TYPE_L: 3540 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3541 break; 3542 3543 default: 3544 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3545 break; 3546 } 3547 } 3548 3549 if (pap != NULL) 3550 *pap = pa; 3551 3552 return true; 3553 } 3554 3555 void 3556 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3557 { 3558 struct l2_bucket *l2b; 3559 pt_entry_t *ptep, pte; 3560 vaddr_t next_bucket; 3561 u_int flags; 3562 u_int clr_mask; 3563 int flush; 3564 3565 NPDEBUG(PDB_PROTECT, 3566 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3567 pm, sva, eva, prot)); 3568 3569 if ((prot & VM_PROT_READ) == 0) { 3570 pmap_remove(pm, sva, eva); 3571 return; 3572 } 3573 3574 if (prot & VM_PROT_WRITE) { 3575 /* 3576 * If this is a read->write transition, just ignore it and let 3577 * uvm_fault() take care of it later. 3578 */ 3579 return; 3580 } 3581 3582 pmap_acquire_pmap_lock(pm); 3583 3584 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3585 flags = 0; 3586 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3587 3588 while (sva < eva) { 3589 next_bucket = L2_NEXT_BUCKET(sva); 3590 if (next_bucket > eva) 3591 next_bucket = eva; 3592 3593 l2b = pmap_get_l2_bucket(pm, sva); 3594 if (l2b == NULL) { 3595 sva = next_bucket; 3596 continue; 3597 } 3598 3599 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3600 3601 while (sva < next_bucket) { 3602 pte = *ptep; 3603 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3604 struct vm_page *pg; 3605 u_int f; 3606 3607 #ifdef PMAP_CACHE_VIVT 3608 /* 3609 * OK, at this point, we know we're doing 3610 * write-protect operation. If the pmap is 3611 * active, write-back the page. 3612 */ 3613 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3614 false, false); 3615 #endif 3616 3617 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3618 pte = l2pte_set_readonly(pte); 3619 *ptep = pte; 3620 PTE_SYNC(ptep); 3621 3622 if (pg != NULL) { 3623 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3624 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3625 3626 #ifdef MULTIPROCESSOR 3627 KASSERT(uvm_page_locked_p(pg)); 3628 #endif 3629 f = pmap_modify_pv(md, pa, pm, sva, 3630 clr_mask, 0); 3631 pmap_vac_me_harder(md, pa, pm, sva); 3632 } else { 3633 f = PVF_REF | PVF_EXEC; 3634 } 3635 3636 if (flush >= 0) { 3637 flush++; 3638 flags |= f; 3639 } else 3640 if (PV_BEEN_EXECD(f)) 3641 pmap_tlb_flushID_SE(pm, sva); 3642 else 3643 if (PV_BEEN_REFD(f)) 3644 pmap_tlb_flushD_SE(pm, sva); 3645 } 3646 3647 sva += PAGE_SIZE; 3648 ptep++; 3649 } 3650 } 3651 3652 pmap_release_pmap_lock(pm); 3653 3654 if (flush) { 3655 if (PV_BEEN_EXECD(flags)) 3656 pmap_tlb_flushID(pm); 3657 else 3658 if (PV_BEEN_REFD(flags)) 3659 pmap_tlb_flushD(pm); 3660 } 3661 } 3662 3663 void 3664 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3665 { 3666 struct l2_bucket *l2b; 3667 pt_entry_t *ptep; 3668 vaddr_t next_bucket; 3669 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3670 3671 NPDEBUG(PDB_EXEC, 3672 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3673 pm, sva, eva)); 3674 3675 pmap_acquire_pmap_lock(pm); 3676 3677 while (sva < eva) { 3678 next_bucket = L2_NEXT_BUCKET(sva); 3679 if (next_bucket > eva) 3680 next_bucket = eva; 3681 3682 l2b = pmap_get_l2_bucket(pm, sva); 3683 if (l2b == NULL) { 3684 sva = next_bucket; 3685 continue; 3686 } 3687 3688 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3689 sva < next_bucket; 3690 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3691 if (l2pte_valid(*ptep)) { 3692 cpu_icache_sync_range(sva, 3693 min(page_size, eva - sva)); 3694 } 3695 } 3696 } 3697 3698 pmap_release_pmap_lock(pm); 3699 } 3700 3701 void 3702 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3703 { 3704 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3705 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3706 3707 NPDEBUG(PDB_PROTECT, 3708 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3709 md, pa, prot)); 3710 3711 #ifdef MULTIPROCESSOR 3712 KASSERT(uvm_page_locked_p(pg)); 3713 #endif 3714 3715 switch(prot) { 3716 case VM_PROT_READ|VM_PROT_WRITE: 3717 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3718 pmap_clearbit(md, pa, PVF_EXEC); 3719 break; 3720 #endif 3721 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3722 break; 3723 3724 case VM_PROT_READ: 3725 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3726 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3727 break; 3728 #endif 3729 case VM_PROT_READ|VM_PROT_EXECUTE: 3730 pmap_clearbit(md, pa, PVF_WRITE); 3731 break; 3732 3733 default: 3734 pmap_page_remove(md, pa); 3735 break; 3736 } 3737 } 3738 3739 /* 3740 * pmap_clear_modify: 3741 * 3742 * Clear the "modified" attribute for a page. 3743 */ 3744 bool 3745 pmap_clear_modify(struct vm_page *pg) 3746 { 3747 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3748 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3749 bool rv; 3750 3751 #ifdef MULTIPROCESSOR 3752 KASSERT(uvm_page_locked_p(pg)); 3753 #endif 3754 3755 if (md->pvh_attrs & PVF_MOD) { 3756 rv = true; 3757 #ifdef PMAP_CACHE_VIPT 3758 /* 3759 * If we are going to clear the modified bit and there are 3760 * no other modified bits set, flush the page to memory and 3761 * mark it clean. 3762 */ 3763 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3764 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3765 #endif 3766 pmap_clearbit(md, pa, PVF_MOD); 3767 } else 3768 rv = false; 3769 3770 return (rv); 3771 } 3772 3773 /* 3774 * pmap_clear_reference: 3775 * 3776 * Clear the "referenced" attribute for a page. 3777 */ 3778 bool 3779 pmap_clear_reference(struct vm_page *pg) 3780 { 3781 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3782 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3783 bool rv; 3784 3785 #ifdef MULTIPROCESSOR 3786 KASSERT(uvm_page_locked_p(pg)); 3787 #endif 3788 3789 if (md->pvh_attrs & PVF_REF) { 3790 rv = true; 3791 pmap_clearbit(md, pa, PVF_REF); 3792 } else 3793 rv = false; 3794 3795 return (rv); 3796 } 3797 3798 /* 3799 * pmap_is_modified: 3800 * 3801 * Test if a page has the "modified" attribute. 3802 */ 3803 /* See <arm/arm32/pmap.h> */ 3804 3805 /* 3806 * pmap_is_referenced: 3807 * 3808 * Test if a page has the "referenced" attribute. 3809 */ 3810 /* See <arm/arm32/pmap.h> */ 3811 3812 int 3813 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3814 { 3815 struct l2_dtable *l2; 3816 struct l2_bucket *l2b; 3817 pd_entry_t *pl1pd, l1pd; 3818 pt_entry_t *ptep, pte; 3819 paddr_t pa; 3820 u_int l1idx; 3821 int rv = 0; 3822 3823 pmap_acquire_pmap_lock(pm); 3824 3825 l1idx = L1_IDX(va); 3826 3827 /* 3828 * If there is no l2_dtable for this address, then the process 3829 * has no business accessing it. 3830 * 3831 * Note: This will catch userland processes trying to access 3832 * kernel addresses. 3833 */ 3834 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3835 if (l2 == NULL) 3836 goto out; 3837 3838 /* 3839 * Likewise if there is no L2 descriptor table 3840 */ 3841 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3842 if (l2b->l2b_kva == NULL) 3843 goto out; 3844 3845 /* 3846 * Check the PTE itself. 3847 */ 3848 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3849 pte = *ptep; 3850 if (pte == 0) 3851 goto out; 3852 3853 /* 3854 * Catch a userland access to the vector page mapped at 0x0 3855 */ 3856 if (user && (pte & L2_S_PROT_U) == 0) 3857 goto out; 3858 3859 pa = l2pte_pa(pte); 3860 3861 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3862 /* 3863 * This looks like a good candidate for "page modified" 3864 * emulation... 3865 */ 3866 struct pv_entry *pv; 3867 struct vm_page *pg; 3868 3869 /* Extract the physical address of the page */ 3870 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3871 goto out; 3872 3873 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3874 3875 /* Get the current flags for this page. */ 3876 #ifdef MULTIPROCESSOR 3877 KASSERT(uvm_page_locked_p(pg)); 3878 #endif 3879 3880 pv = pmap_find_pv(md, pm, va); 3881 if (pv == NULL) { 3882 goto out; 3883 } 3884 3885 /* 3886 * Do the flags say this page is writable? If not then it 3887 * is a genuine write fault. If yes then the write fault is 3888 * our fault as we did not reflect the write access in the 3889 * PTE. Now we know a write has occurred we can correct this 3890 * and also set the modified bit 3891 */ 3892 if ((pv->pv_flags & PVF_WRITE) == 0) { 3893 goto out; 3894 } 3895 3896 NPDEBUG(PDB_FOLLOW, 3897 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3898 pm, va, pa)); 3899 3900 md->pvh_attrs |= PVF_REF | PVF_MOD; 3901 pv->pv_flags |= PVF_REF | PVF_MOD; 3902 #ifdef PMAP_CACHE_VIPT 3903 /* 3904 * If there are cacheable mappings for this page, mark it dirty. 3905 */ 3906 if ((md->pvh_attrs & PVF_NC) == 0) 3907 md->pvh_attrs |= PVF_DIRTY; 3908 #endif 3909 3910 /* 3911 * Re-enable write permissions for the page. No need to call 3912 * pmap_vac_me_harder(), since this is just a 3913 * modified-emulation fault, and the PVF_WRITE bit isn't 3914 * changing. We've already set the cacheable bits based on 3915 * the assumption that we can write to this page. 3916 */ 3917 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3918 PTE_SYNC(ptep); 3919 rv = 1; 3920 } else 3921 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3922 /* 3923 * This looks like a good candidate for "page referenced" 3924 * emulation. 3925 */ 3926 struct pv_entry *pv; 3927 struct vm_page *pg; 3928 3929 /* Extract the physical address of the page */ 3930 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3931 goto out; 3932 3933 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3934 3935 /* Get the current flags for this page. */ 3936 #ifdef MULTIPROCESSOR 3937 KASSERT(uvm_page_locked_p(pg)); 3938 #endif 3939 3940 pv = pmap_find_pv(md, pm, va); 3941 if (pv == NULL) { 3942 goto out; 3943 } 3944 3945 md->pvh_attrs |= PVF_REF; 3946 pv->pv_flags |= PVF_REF; 3947 3948 NPDEBUG(PDB_FOLLOW, 3949 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3950 pm, va, pa)); 3951 3952 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3953 PTE_SYNC(ptep); 3954 rv = 1; 3955 } 3956 3957 /* 3958 * We know there is a valid mapping here, so simply 3959 * fix up the L1 if necessary. 3960 */ 3961 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3962 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3963 if (*pl1pd != l1pd) { 3964 *pl1pd = l1pd; 3965 PTE_SYNC(pl1pd); 3966 rv = 1; 3967 } 3968 3969 #ifdef CPU_SA110 3970 /* 3971 * There are bugs in the rev K SA110. This is a check for one 3972 * of them. 3973 */ 3974 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3975 curcpu()->ci_arm_cpurev < 3) { 3976 /* Always current pmap */ 3977 if (l2pte_valid(pte)) { 3978 extern int kernel_debug; 3979 if (kernel_debug & 1) { 3980 struct proc *p = curlwp->l_proc; 3981 printf("prefetch_abort: page is already " 3982 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3983 printf("prefetch_abort: pc=%08lx proc=%p " 3984 "process=%s\n", va, p, p->p_comm); 3985 printf("prefetch_abort: far=%08x fs=%x\n", 3986 cpu_faultaddress(), cpu_faultstatus()); 3987 } 3988 #ifdef DDB 3989 if (kernel_debug & 2) 3990 Debugger(); 3991 #endif 3992 rv = 1; 3993 } 3994 } 3995 #endif /* CPU_SA110 */ 3996 3997 #ifdef DEBUG 3998 /* 3999 * If 'rv == 0' at this point, it generally indicates that there is a 4000 * stale TLB entry for the faulting address. This happens when two or 4001 * more processes are sharing an L1. Since we don't flush the TLB on 4002 * a context switch between such processes, we can take domain faults 4003 * for mappings which exist at the same VA in both processes. EVEN IF 4004 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4005 * example. 4006 * 4007 * This is extremely likely to happen if pmap_enter() updated the L1 4008 * entry for a recently entered mapping. In this case, the TLB is 4009 * flushed for the new mapping, but there may still be TLB entries for 4010 * other mappings belonging to other processes in the 1MB range 4011 * covered by the L1 entry. 4012 * 4013 * Since 'rv == 0', we know that the L1 already contains the correct 4014 * value, so the fault must be due to a stale TLB entry. 4015 * 4016 * Since we always need to flush the TLB anyway in the case where we 4017 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4018 * stale TLB entries dynamically. 4019 * 4020 * However, the above condition can ONLY happen if the current L1 is 4021 * being shared. If it happens when the L1 is unshared, it indicates 4022 * that other parts of the pmap are not doing their job WRT managing 4023 * the TLB. 4024 */ 4025 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4026 extern int last_fault_code; 4027 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4028 pm, va, ftype); 4029 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4030 l2, l2b, ptep, pl1pd); 4031 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4032 pte, l1pd, last_fault_code); 4033 #ifdef DDB 4034 Debugger(); 4035 #endif 4036 } 4037 #endif 4038 4039 cpu_tlb_flushID_SE(va); 4040 cpu_cpwait(); 4041 4042 rv = 1; 4043 4044 out: 4045 pmap_release_pmap_lock(pm); 4046 4047 return (rv); 4048 } 4049 4050 /* 4051 * Routine: pmap_procwr 4052 * 4053 * Function: 4054 * Synchronize caches corresponding to [addr, addr+len) in p. 4055 * 4056 */ 4057 void 4058 pmap_procwr(struct proc *p, vaddr_t va, int len) 4059 { 4060 /* We only need to do anything if it is the current process. */ 4061 if (p == curproc) 4062 cpu_icache_sync_range(va, len); 4063 } 4064 4065 /* 4066 * Routine: pmap_unwire 4067 * Function: Clear the wired attribute for a map/virtual-address pair. 4068 * 4069 * In/out conditions: 4070 * The mapping must already exist in the pmap. 4071 */ 4072 void 4073 pmap_unwire(pmap_t pm, vaddr_t va) 4074 { 4075 struct l2_bucket *l2b; 4076 pt_entry_t *ptep, pte; 4077 struct vm_page *pg; 4078 paddr_t pa; 4079 4080 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4081 4082 pmap_acquire_pmap_lock(pm); 4083 4084 l2b = pmap_get_l2_bucket(pm, va); 4085 KDASSERT(l2b != NULL); 4086 4087 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4088 pte = *ptep; 4089 4090 /* Extract the physical address of the page */ 4091 pa = l2pte_pa(pte); 4092 4093 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4094 /* Update the wired bit in the pv entry for this page. */ 4095 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4096 4097 #ifdef MULTIPROCESSOR 4098 KASSERT(uvm_page_locked_p(pg)); 4099 #endif 4100 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4101 } 4102 4103 pmap_release_pmap_lock(pm); 4104 } 4105 4106 void 4107 pmap_activate(struct lwp *l) 4108 { 4109 extern int block_userspace_access; 4110 pmap_t opm, npm, rpm; 4111 uint32_t odacr, ndacr; 4112 int oldirqstate; 4113 4114 /* 4115 * If activating a non-current lwp or the current lwp is 4116 * already active, just return. 4117 */ 4118 if (l != curlwp || 4119 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4120 return; 4121 4122 npm = l->l_proc->p_vmspace->vm_map.pmap; 4123 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4124 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4125 4126 /* 4127 * If TTB and DACR are unchanged, short-circuit all the 4128 * TLB/cache management stuff. 4129 */ 4130 if (pmap_previous_active_lwp != NULL) { 4131 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4132 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4133 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4134 4135 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4136 goto all_done; 4137 } else 4138 opm = NULL; 4139 4140 PMAPCOUNT(activations); 4141 block_userspace_access = 1; 4142 4143 /* 4144 * If switching to a user vmspace which is different to the 4145 * most recent one, and the most recent one is potentially 4146 * live in the cache, we must write-back and invalidate the 4147 * entire cache. 4148 */ 4149 rpm = pmap_recent_user; 4150 4151 /* 4152 * XXXSCW: There's a corner case here which can leave turds in the cache as 4153 * reported in kern/41058. They're probably left over during tear-down and 4154 * switching away from an exiting process. Until the root cause is identified 4155 * and fixed, zap the cache when switching pmaps. This will result in a few 4156 * unnecessary cache flushes, but that's better than silently corrupting data. 4157 */ 4158 #if 0 4159 if (npm != pmap_kernel() && rpm && npm != rpm && 4160 rpm->pm_cstate.cs_cache) { 4161 rpm->pm_cstate.cs_cache = 0; 4162 #ifdef PMAP_CACHE_VIVT 4163 cpu_idcache_wbinv_all(); 4164 #endif 4165 } 4166 #else 4167 if (rpm) { 4168 rpm->pm_cstate.cs_cache = 0; 4169 if (npm == pmap_kernel()) 4170 pmap_recent_user = NULL; 4171 #ifdef PMAP_CACHE_VIVT 4172 cpu_idcache_wbinv_all(); 4173 #endif 4174 } 4175 #endif 4176 4177 /* No interrupts while we frob the TTB/DACR */ 4178 oldirqstate = disable_interrupts(IF32_bits); 4179 4180 /* 4181 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4182 * entry corresponding to 'vector_page' in the incoming L1 table 4183 * before switching to it otherwise subsequent interrupts/exceptions 4184 * (including domain faults!) will jump into hyperspace. 4185 */ 4186 if (npm->pm_pl1vec != NULL) { 4187 cpu_tlb_flushID_SE((u_int)vector_page); 4188 cpu_cpwait(); 4189 *npm->pm_pl1vec = npm->pm_l1vec; 4190 PTE_SYNC(npm->pm_pl1vec); 4191 } 4192 4193 cpu_domains(ndacr); 4194 4195 if (npm == pmap_kernel() || npm == rpm) { 4196 /* 4197 * Switching to a kernel thread, or back to the 4198 * same user vmspace as before... Simply update 4199 * the TTB (no TLB flush required) 4200 */ 4201 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4202 "r"(npm->pm_l1->l1_physaddr)); 4203 cpu_cpwait(); 4204 } else { 4205 /* 4206 * Otherwise, update TTB and flush TLB 4207 */ 4208 cpu_context_switch(npm->pm_l1->l1_physaddr); 4209 if (rpm != NULL) 4210 rpm->pm_cstate.cs_tlb = 0; 4211 } 4212 4213 restore_interrupts(oldirqstate); 4214 4215 block_userspace_access = 0; 4216 4217 all_done: 4218 /* 4219 * The new pmap is resident. Make sure it's marked 4220 * as resident in the cache/TLB. 4221 */ 4222 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4223 if (npm != pmap_kernel()) 4224 pmap_recent_user = npm; 4225 4226 /* The old pmap is not longer active */ 4227 if (opm != NULL) 4228 opm->pm_activated = false; 4229 4230 /* But the new one is */ 4231 npm->pm_activated = true; 4232 } 4233 4234 void 4235 pmap_deactivate(struct lwp *l) 4236 { 4237 4238 /* 4239 * If the process is exiting, make sure pmap_activate() does 4240 * a full MMU context-switch and cache flush, which we might 4241 * otherwise skip. See PR port-arm/38950. 4242 */ 4243 if (l->l_proc->p_sflag & PS_WEXIT) 4244 pmap_previous_active_lwp = NULL; 4245 4246 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4247 } 4248 4249 void 4250 pmap_update(pmap_t pm) 4251 { 4252 4253 if (pm->pm_remove_all) { 4254 /* 4255 * Finish up the pmap_remove_all() optimisation by flushing 4256 * the TLB. 4257 */ 4258 pmap_tlb_flushID(pm); 4259 pm->pm_remove_all = false; 4260 } 4261 4262 if (pmap_is_current(pm)) { 4263 /* 4264 * If we're dealing with a current userland pmap, move its L1 4265 * to the end of the LRU. 4266 */ 4267 if (pm != pmap_kernel()) 4268 pmap_use_l1(pm); 4269 4270 /* 4271 * We can assume we're done with frobbing the cache/tlb for 4272 * now. Make sure any future pmap ops don't skip cache/tlb 4273 * flushes. 4274 */ 4275 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4276 } 4277 4278 PMAPCOUNT(updates); 4279 4280 /* 4281 * make sure TLB/cache operations have completed. 4282 */ 4283 cpu_cpwait(); 4284 } 4285 4286 void 4287 pmap_remove_all(pmap_t pm) 4288 { 4289 4290 /* 4291 * The vmspace described by this pmap is about to be torn down. 4292 * Until pmap_update() is called, UVM will only make calls 4293 * to pmap_remove(). We can make life much simpler by flushing 4294 * the cache now, and deferring TLB invalidation to pmap_update(). 4295 */ 4296 #ifdef PMAP_CACHE_VIVT 4297 pmap_idcache_wbinv_all(pm); 4298 #endif 4299 pm->pm_remove_all = true; 4300 } 4301 4302 /* 4303 * Retire the given physical map from service. 4304 * Should only be called if the map contains no valid mappings. 4305 */ 4306 void 4307 pmap_destroy(pmap_t pm) 4308 { 4309 u_int count; 4310 4311 if (pm == NULL) 4312 return; 4313 4314 if (pm->pm_remove_all) { 4315 pmap_tlb_flushID(pm); 4316 pm->pm_remove_all = false; 4317 } 4318 4319 /* 4320 * Drop reference count 4321 */ 4322 mutex_enter(pm->pm_lock); 4323 count = --pm->pm_obj.uo_refs; 4324 mutex_exit(pm->pm_lock); 4325 if (count > 0) { 4326 if (pmap_is_current(pm)) { 4327 if (pm != pmap_kernel()) 4328 pmap_use_l1(pm); 4329 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4330 } 4331 return; 4332 } 4333 4334 /* 4335 * reference count is zero, free pmap resources and then free pmap. 4336 */ 4337 4338 if (vector_page < KERNEL_BASE) { 4339 KDASSERT(!pmap_is_current(pm)); 4340 4341 /* Remove the vector page mapping */ 4342 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4343 pmap_update(pm); 4344 } 4345 4346 LIST_REMOVE(pm, pm_list); 4347 4348 pmap_free_l1(pm); 4349 4350 if (pmap_recent_user == pm) 4351 pmap_recent_user = NULL; 4352 4353 uvm_obj_destroy(&pm->pm_obj, false); 4354 mutex_destroy(&pm->pm_obj_lock); 4355 pool_cache_put(&pmap_cache, pm); 4356 } 4357 4358 4359 /* 4360 * void pmap_reference(pmap_t pm) 4361 * 4362 * Add a reference to the specified pmap. 4363 */ 4364 void 4365 pmap_reference(pmap_t pm) 4366 { 4367 4368 if (pm == NULL) 4369 return; 4370 4371 pmap_use_l1(pm); 4372 4373 mutex_enter(pm->pm_lock); 4374 pm->pm_obj.uo_refs++; 4375 mutex_exit(pm->pm_lock); 4376 } 4377 4378 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4379 4380 static struct evcnt pmap_prefer_nochange_ev = 4381 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4382 static struct evcnt pmap_prefer_change_ev = 4383 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4384 4385 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4386 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4387 4388 void 4389 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4390 { 4391 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4392 vaddr_t va = *vap; 4393 vaddr_t diff = (hint - va) & mask; 4394 if (diff == 0) { 4395 pmap_prefer_nochange_ev.ev_count++; 4396 } else { 4397 pmap_prefer_change_ev.ev_count++; 4398 if (__predict_false(td)) 4399 va -= mask + 1; 4400 *vap = va + diff; 4401 } 4402 } 4403 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4404 4405 /* 4406 * pmap_zero_page() 4407 * 4408 * Zero a given physical page by mapping it at a page hook point. 4409 * In doing the zero page op, the page we zero is mapped cachable, as with 4410 * StrongARM accesses to non-cached pages are non-burst making writing 4411 * _any_ bulk data very slow. 4412 */ 4413 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4414 void 4415 pmap_zero_page_generic(paddr_t phys) 4416 { 4417 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4418 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4419 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4420 #endif 4421 #ifdef PMAP_CACHE_VIPT 4422 /* Choose the last page color it had, if any */ 4423 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4424 #else 4425 const vsize_t va_offset = 0; 4426 #endif 4427 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4428 4429 #ifdef DEBUG 4430 if (!SLIST_EMPTY(&md->pvh_list)) 4431 panic("pmap_zero_page: page has mappings"); 4432 #endif 4433 4434 KDASSERT((phys & PGOFSET) == 0); 4435 4436 /* 4437 * Hook in the page, zero it, and purge the cache for that 4438 * zeroed page. Invalidate the TLB as needed. 4439 */ 4440 *ptep = L2_S_PROTO | phys | 4441 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4442 PTE_SYNC(ptep); 4443 cpu_tlb_flushD_SE(cdstp + va_offset); 4444 cpu_cpwait(); 4445 bzero_page(cdstp + va_offset); 4446 /* 4447 * Unmap the page. 4448 */ 4449 *ptep = 0; 4450 PTE_SYNC(ptep); 4451 cpu_tlb_flushD_SE(cdstp + va_offset); 4452 #ifdef PMAP_CACHE_VIVT 4453 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4454 #endif 4455 #ifdef PMAP_CACHE_VIPT 4456 /* 4457 * This page is now cache resident so it now has a page color. 4458 * Any contents have been obliterated so clear the EXEC flag. 4459 */ 4460 if (!pmap_is_page_colored_p(md)) { 4461 PMAPCOUNT(vac_color_new); 4462 md->pvh_attrs |= PVF_COLORED; 4463 } 4464 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4465 md->pvh_attrs &= ~PVF_EXEC; 4466 PMAPCOUNT(exec_discarded_zero); 4467 } 4468 md->pvh_attrs |= PVF_DIRTY; 4469 #endif 4470 } 4471 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4472 4473 #if ARM_MMU_XSCALE == 1 4474 void 4475 pmap_zero_page_xscale(paddr_t phys) 4476 { 4477 #ifdef DEBUG 4478 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4479 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4480 4481 if (!SLIST_EMPTY(&md->pvh_list)) 4482 panic("pmap_zero_page: page has mappings"); 4483 #endif 4484 4485 KDASSERT((phys & PGOFSET) == 0); 4486 4487 /* 4488 * Hook in the page, zero it, and purge the cache for that 4489 * zeroed page. Invalidate the TLB as needed. 4490 */ 4491 *cdst_pte = L2_S_PROTO | phys | 4492 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4493 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4494 PTE_SYNC(cdst_pte); 4495 cpu_tlb_flushD_SE(cdstp); 4496 cpu_cpwait(); 4497 bzero_page(cdstp); 4498 xscale_cache_clean_minidata(); 4499 } 4500 #endif /* ARM_MMU_XSCALE == 1 */ 4501 4502 /* pmap_pageidlezero() 4503 * 4504 * The same as above, except that we assume that the page is not 4505 * mapped. This means we never have to flush the cache first. Called 4506 * from the idle loop. 4507 */ 4508 bool 4509 pmap_pageidlezero(paddr_t phys) 4510 { 4511 unsigned int i; 4512 int *ptr; 4513 bool rv = true; 4514 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4515 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4516 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4517 #endif 4518 #ifdef PMAP_CACHE_VIPT 4519 /* Choose the last page color it had, if any */ 4520 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4521 #else 4522 const vsize_t va_offset = 0; 4523 #endif 4524 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4525 4526 4527 #ifdef DEBUG 4528 if (!SLIST_EMPTY(&md->pvh_list)) 4529 panic("pmap_pageidlezero: page has mappings"); 4530 #endif 4531 4532 KDASSERT((phys & PGOFSET) == 0); 4533 4534 /* 4535 * Hook in the page, zero it, and purge the cache for that 4536 * zeroed page. Invalidate the TLB as needed. 4537 */ 4538 *ptep = L2_S_PROTO | phys | 4539 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4540 PTE_SYNC(ptep); 4541 cpu_tlb_flushD_SE(cdstp + va_offset); 4542 cpu_cpwait(); 4543 4544 for (i = 0, ptr = (int *)(cdstp + va_offset); 4545 i < (PAGE_SIZE / sizeof(int)); i++) { 4546 if (sched_curcpu_runnable_p() != 0) { 4547 /* 4548 * A process has become ready. Abort now, 4549 * so we don't keep it waiting while we 4550 * do slow memory access to finish this 4551 * page. 4552 */ 4553 rv = false; 4554 break; 4555 } 4556 *ptr++ = 0; 4557 } 4558 4559 #ifdef PMAP_CACHE_VIVT 4560 if (rv) 4561 /* 4562 * if we aborted we'll rezero this page again later so don't 4563 * purge it unless we finished it 4564 */ 4565 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4566 #elif defined(PMAP_CACHE_VIPT) 4567 /* 4568 * This page is now cache resident so it now has a page color. 4569 * Any contents have been obliterated so clear the EXEC flag. 4570 */ 4571 if (!pmap_is_page_colored_p(md)) { 4572 PMAPCOUNT(vac_color_new); 4573 md->pvh_attrs |= PVF_COLORED; 4574 } 4575 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4576 md->pvh_attrs &= ~PVF_EXEC; 4577 PMAPCOUNT(exec_discarded_zero); 4578 } 4579 #endif 4580 /* 4581 * Unmap the page. 4582 */ 4583 *ptep = 0; 4584 PTE_SYNC(ptep); 4585 cpu_tlb_flushD_SE(cdstp + va_offset); 4586 4587 return (rv); 4588 } 4589 4590 /* 4591 * pmap_copy_page() 4592 * 4593 * Copy one physical page into another, by mapping the pages into 4594 * hook points. The same comment regarding cachability as in 4595 * pmap_zero_page also applies here. 4596 */ 4597 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4598 void 4599 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4600 { 4601 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4602 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4603 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4604 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4605 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4606 #endif 4607 #ifdef PMAP_CACHE_VIPT 4608 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4609 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4610 #else 4611 const vsize_t src_va_offset = 0; 4612 const vsize_t dst_va_offset = 0; 4613 #endif 4614 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4615 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4616 4617 #ifdef DEBUG 4618 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4619 panic("pmap_copy_page: dst page has mappings"); 4620 #endif 4621 4622 #ifdef PMAP_CACHE_VIPT 4623 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4624 #endif 4625 KDASSERT((src & PGOFSET) == 0); 4626 KDASSERT((dst & PGOFSET) == 0); 4627 4628 /* 4629 * Clean the source page. Hold the source page's lock for 4630 * the duration of the copy so that no other mappings can 4631 * be created while we have a potentially aliased mapping. 4632 */ 4633 #ifdef MULTIPROCESSOR 4634 KASSERT(uvm_page_locked_p(src_pg)); 4635 #endif 4636 #ifdef PMAP_CACHE_VIVT 4637 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4638 #endif 4639 4640 /* 4641 * Map the pages into the page hook points, copy them, and purge 4642 * the cache for the appropriate page. Invalidate the TLB 4643 * as required. 4644 */ 4645 *src_ptep = L2_S_PROTO 4646 | src 4647 #ifdef PMAP_CACHE_VIPT 4648 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4649 #endif 4650 #ifdef PMAP_CACHE_VIVT 4651 | pte_l2_s_cache_mode 4652 #endif 4653 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4654 *dst_ptep = L2_S_PROTO | dst | 4655 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4656 PTE_SYNC(src_ptep); 4657 PTE_SYNC(dst_ptep); 4658 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4659 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4660 cpu_cpwait(); 4661 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4662 #ifdef PMAP_CACHE_VIVT 4663 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4664 #endif 4665 #ifdef PMAP_CACHE_VIVT 4666 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4667 #endif 4668 /* 4669 * Unmap the pages. 4670 */ 4671 *src_ptep = 0; 4672 *dst_ptep = 0; 4673 PTE_SYNC(src_ptep); 4674 PTE_SYNC(dst_ptep); 4675 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4676 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4677 #ifdef PMAP_CACHE_VIPT 4678 /* 4679 * Now that the destination page is in the cache, mark it as colored. 4680 * If this was an exec page, discard it. 4681 */ 4682 if (!pmap_is_page_colored_p(dst_md)) { 4683 PMAPCOUNT(vac_color_new); 4684 dst_md->pvh_attrs |= PVF_COLORED; 4685 } 4686 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4687 dst_md->pvh_attrs &= ~PVF_EXEC; 4688 PMAPCOUNT(exec_discarded_copy); 4689 } 4690 dst_md->pvh_attrs |= PVF_DIRTY; 4691 #endif 4692 } 4693 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4694 4695 #if ARM_MMU_XSCALE == 1 4696 void 4697 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4698 { 4699 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4700 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4701 #ifdef DEBUG 4702 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4703 4704 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4705 panic("pmap_copy_page: dst page has mappings"); 4706 #endif 4707 4708 KDASSERT((src & PGOFSET) == 0); 4709 KDASSERT((dst & PGOFSET) == 0); 4710 4711 /* 4712 * Clean the source page. Hold the source page's lock for 4713 * the duration of the copy so that no other mappings can 4714 * be created while we have a potentially aliased mapping. 4715 */ 4716 #ifdef MULTIPROCESSOR 4717 KASSERT(uvm_page_locked_p(src_pg)); 4718 #endif 4719 #ifdef PMAP_CACHE_VIVT 4720 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4721 #endif 4722 4723 /* 4724 * Map the pages into the page hook points, copy them, and purge 4725 * the cache for the appropriate page. Invalidate the TLB 4726 * as required. 4727 */ 4728 *csrc_pte = L2_S_PROTO | src | 4729 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4730 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4731 PTE_SYNC(csrc_pte); 4732 *cdst_pte = L2_S_PROTO | dst | 4733 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4734 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4735 PTE_SYNC(cdst_pte); 4736 cpu_tlb_flushD_SE(csrcp); 4737 cpu_tlb_flushD_SE(cdstp); 4738 cpu_cpwait(); 4739 bcopy_page(csrcp, cdstp); 4740 xscale_cache_clean_minidata(); 4741 } 4742 #endif /* ARM_MMU_XSCALE == 1 */ 4743 4744 /* 4745 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4746 * 4747 * Return the start and end addresses of the kernel's virtual space. 4748 * These values are setup in pmap_bootstrap and are updated as pages 4749 * are allocated. 4750 */ 4751 void 4752 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4753 { 4754 *start = virtual_avail; 4755 *end = virtual_end; 4756 } 4757 4758 /* 4759 * Helper function for pmap_grow_l2_bucket() 4760 */ 4761 static inline int 4762 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4763 { 4764 struct l2_bucket *l2b; 4765 pt_entry_t *ptep; 4766 paddr_t pa; 4767 4768 if (uvm.page_init_done == false) { 4769 #ifdef PMAP_STEAL_MEMORY 4770 pv_addr_t pv; 4771 pmap_boot_pagealloc(PAGE_SIZE, 4772 #ifdef PMAP_CACHE_VIPT 4773 arm_cache_prefer_mask, 4774 va & arm_cache_prefer_mask, 4775 #else 4776 0, 0, 4777 #endif 4778 &pv); 4779 pa = pv.pv_pa; 4780 #else 4781 if (uvm_page_physget(&pa) == false) 4782 return (1); 4783 #endif /* PMAP_STEAL_MEMORY */ 4784 } else { 4785 struct vm_page *pg; 4786 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4787 if (pg == NULL) 4788 return (1); 4789 pa = VM_PAGE_TO_PHYS(pg); 4790 #ifdef PMAP_CACHE_VIPT 4791 #ifdef DIAGNOSTIC 4792 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4793 #endif 4794 /* 4795 * This new page must not have any mappings. Enter it via 4796 * pmap_kenter_pa and let that routine do the hard work. 4797 */ 4798 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4799 pmap_kenter_pa(va, pa, 4800 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4801 #endif 4802 } 4803 4804 if (pap) 4805 *pap = pa; 4806 4807 PMAPCOUNT(pt_mappings); 4808 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4809 KDASSERT(l2b != NULL); 4810 4811 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4812 *ptep = L2_S_PROTO | pa | cache_mode | 4813 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4814 PTE_SYNC(ptep); 4815 memset((void *)va, 0, PAGE_SIZE); 4816 return (0); 4817 } 4818 4819 /* 4820 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4821 * used by pmap_growkernel(). 4822 */ 4823 static inline struct l2_bucket * 4824 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4825 { 4826 struct l2_dtable *l2; 4827 struct l2_bucket *l2b; 4828 u_short l1idx; 4829 vaddr_t nva; 4830 4831 l1idx = L1_IDX(va); 4832 4833 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4834 /* 4835 * No mapping at this address, as there is 4836 * no entry in the L1 table. 4837 * Need to allocate a new l2_dtable. 4838 */ 4839 nva = pmap_kernel_l2dtable_kva; 4840 if ((nva & PGOFSET) == 0) { 4841 /* 4842 * Need to allocate a backing page 4843 */ 4844 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4845 return (NULL); 4846 } 4847 4848 l2 = (struct l2_dtable *)nva; 4849 nva += sizeof(struct l2_dtable); 4850 4851 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4852 /* 4853 * The new l2_dtable straddles a page boundary. 4854 * Map in another page to cover it. 4855 */ 4856 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4857 return (NULL); 4858 } 4859 4860 pmap_kernel_l2dtable_kva = nva; 4861 4862 /* 4863 * Link it into the parent pmap 4864 */ 4865 pm->pm_l2[L2_IDX(l1idx)] = l2; 4866 } 4867 4868 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4869 4870 /* 4871 * Fetch pointer to the L2 page table associated with the address. 4872 */ 4873 if (l2b->l2b_kva == NULL) { 4874 pt_entry_t *ptep; 4875 4876 /* 4877 * No L2 page table has been allocated. Chances are, this 4878 * is because we just allocated the l2_dtable, above. 4879 */ 4880 nva = pmap_kernel_l2ptp_kva; 4881 ptep = (pt_entry_t *)nva; 4882 if ((nva & PGOFSET) == 0) { 4883 /* 4884 * Need to allocate a backing page 4885 */ 4886 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4887 &pmap_kernel_l2ptp_phys)) 4888 return (NULL); 4889 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4890 } 4891 4892 l2->l2_occupancy++; 4893 l2b->l2b_kva = ptep; 4894 l2b->l2b_l1idx = l1idx; 4895 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4896 4897 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4898 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4899 } 4900 4901 return (l2b); 4902 } 4903 4904 vaddr_t 4905 pmap_growkernel(vaddr_t maxkvaddr) 4906 { 4907 pmap_t kpm = pmap_kernel(); 4908 struct l1_ttable *l1; 4909 struct l2_bucket *l2b; 4910 pd_entry_t *pl1pd; 4911 int s; 4912 4913 if (maxkvaddr <= pmap_curmaxkvaddr) 4914 goto out; /* we are OK */ 4915 4916 NPDEBUG(PDB_GROWKERN, 4917 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4918 pmap_curmaxkvaddr, maxkvaddr)); 4919 4920 KDASSERT(maxkvaddr <= virtual_end); 4921 4922 /* 4923 * whoops! we need to add kernel PTPs 4924 */ 4925 4926 s = splhigh(); /* to be safe */ 4927 mutex_enter(kpm->pm_lock); 4928 4929 /* Map 1MB at a time */ 4930 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4931 4932 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4933 KDASSERT(l2b != NULL); 4934 4935 /* Distribute new L1 entry to all other L1s */ 4936 SLIST_FOREACH(l1, &l1_list, l1_link) { 4937 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4938 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4939 L1_C_PROTO; 4940 PTE_SYNC(pl1pd); 4941 } 4942 } 4943 4944 /* 4945 * flush out the cache, expensive but growkernel will happen so 4946 * rarely 4947 */ 4948 cpu_dcache_wbinv_all(); 4949 cpu_tlb_flushD(); 4950 cpu_cpwait(); 4951 4952 mutex_exit(kpm->pm_lock); 4953 splx(s); 4954 4955 out: 4956 return (pmap_curmaxkvaddr); 4957 } 4958 4959 /************************ Utility routines ****************************/ 4960 4961 /* 4962 * vector_page_setprot: 4963 * 4964 * Manipulate the protection of the vector page. 4965 */ 4966 void 4967 vector_page_setprot(int prot) 4968 { 4969 struct l2_bucket *l2b; 4970 pt_entry_t *ptep; 4971 4972 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4973 KDASSERT(l2b != NULL); 4974 4975 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4976 4977 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4978 PTE_SYNC(ptep); 4979 cpu_tlb_flushD_SE(vector_page); 4980 cpu_cpwait(); 4981 } 4982 4983 /* 4984 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4985 * Returns true if the mapping exists, else false. 4986 * 4987 * NOTE: This function is only used by a couple of arm-specific modules. 4988 * It is not safe to take any pmap locks here, since we could be right 4989 * in the middle of debugging the pmap anyway... 4990 * 4991 * It is possible for this routine to return false even though a valid 4992 * mapping does exist. This is because we don't lock, so the metadata 4993 * state may be inconsistent. 4994 * 4995 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4996 * a "section" mapping. 4997 */ 4998 bool 4999 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5000 { 5001 struct l2_dtable *l2; 5002 pd_entry_t *pl1pd, l1pd; 5003 pt_entry_t *ptep; 5004 u_short l1idx; 5005 5006 if (pm->pm_l1 == NULL) 5007 return false; 5008 5009 l1idx = L1_IDX(va); 5010 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5011 l1pd = *pl1pd; 5012 5013 if (l1pte_section_p(l1pd)) { 5014 *ptp = NULL; 5015 return true; 5016 } 5017 5018 if (pm->pm_l2 == NULL) 5019 return false; 5020 5021 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5022 5023 if (l2 == NULL || 5024 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5025 return false; 5026 } 5027 5028 *ptp = &ptep[l2pte_index(va)]; 5029 return true; 5030 } 5031 5032 bool 5033 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5034 { 5035 u_short l1idx; 5036 5037 if (pm->pm_l1 == NULL) 5038 return false; 5039 5040 l1idx = L1_IDX(va); 5041 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5042 5043 return true; 5044 } 5045 5046 /************************ Bootstrapping routines ****************************/ 5047 5048 static void 5049 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5050 { 5051 int i; 5052 5053 l1->l1_kva = l1pt; 5054 l1->l1_domain_use_count = 0; 5055 l1->l1_domain_first = 0; 5056 5057 for (i = 0; i < PMAP_DOMAINS; i++) 5058 l1->l1_domain_free[i] = i + 1; 5059 5060 /* 5061 * Copy the kernel's L1 entries to each new L1. 5062 */ 5063 if (pmap_initialized) 5064 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5065 5066 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5067 &l1->l1_physaddr) == false) 5068 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5069 5070 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5071 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5072 } 5073 5074 /* 5075 * pmap_bootstrap() is called from the board-specific initarm() routine 5076 * once the kernel L1/L2 descriptors tables have been set up. 5077 * 5078 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5079 * spread over a number of disparate files/functions. 5080 * 5081 * We are passed the following parameters 5082 * - kernel_l1pt 5083 * This is a pointer to the base of the kernel's L1 translation table. 5084 * - vstart 5085 * 1MB-aligned start of managed kernel virtual memory. 5086 * - vend 5087 * 1MB-aligned end of managed kernel virtual memory. 5088 * 5089 * We use the first parameter to build the metadata (struct l1_ttable and 5090 * struct l2_dtable) necessary to track kernel mappings. 5091 */ 5092 #define PMAP_STATIC_L2_SIZE 16 5093 void 5094 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5095 { 5096 static struct l1_ttable static_l1; 5097 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5098 struct l1_ttable *l1 = &static_l1; 5099 struct l2_dtable *l2; 5100 struct l2_bucket *l2b; 5101 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5102 pmap_t pm = pmap_kernel(); 5103 pd_entry_t pde; 5104 pt_entry_t *ptep; 5105 paddr_t pa; 5106 vaddr_t va; 5107 vsize_t size; 5108 int nptes, l1idx, l2idx, l2next = 0; 5109 5110 /* 5111 * Initialise the kernel pmap object 5112 */ 5113 pm->pm_l1 = l1; 5114 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5115 pm->pm_activated = true; 5116 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5117 5118 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5119 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5120 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5121 5122 /* 5123 * Scan the L1 translation table created by initarm() and create 5124 * the required metadata for all valid mappings found in it. 5125 */ 5126 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5127 pde = l1pt[l1idx]; 5128 5129 /* 5130 * We're only interested in Coarse mappings. 5131 * pmap_extract() can deal with section mappings without 5132 * recourse to checking L2 metadata. 5133 */ 5134 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5135 continue; 5136 5137 /* 5138 * Lookup the KVA of this L2 descriptor table 5139 */ 5140 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5141 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5142 if (ptep == NULL) { 5143 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5144 (u_int)l1idx << L1_S_SHIFT, pa); 5145 } 5146 5147 /* 5148 * Fetch the associated L2 metadata structure. 5149 * Allocate a new one if necessary. 5150 */ 5151 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5152 if (l2next == PMAP_STATIC_L2_SIZE) 5153 panic("pmap_bootstrap: out of static L2s"); 5154 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5155 } 5156 5157 /* 5158 * One more L1 slot tracked... 5159 */ 5160 l2->l2_occupancy++; 5161 5162 /* 5163 * Fill in the details of the L2 descriptor in the 5164 * appropriate bucket. 5165 */ 5166 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5167 l2b->l2b_kva = ptep; 5168 l2b->l2b_phys = pa; 5169 l2b->l2b_l1idx = l1idx; 5170 5171 /* 5172 * Establish an initial occupancy count for this descriptor 5173 */ 5174 for (l2idx = 0; 5175 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5176 l2idx++) { 5177 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5178 l2b->l2b_occupancy++; 5179 } 5180 } 5181 5182 /* 5183 * Make sure the descriptor itself has the correct cache mode. 5184 * If not, fix it, but whine about the problem. Port-meisters 5185 * should consider this a clue to fix up their initarm() 5186 * function. :) 5187 */ 5188 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5189 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5190 "L2 pte @ %p\n", ptep); 5191 } 5192 } 5193 5194 /* 5195 * Ensure the primary (kernel) L1 has the correct cache mode for 5196 * a page table. Bitch if it is not correctly set. 5197 */ 5198 for (va = (vaddr_t)l1pt; 5199 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5200 if (pmap_set_pt_cache_mode(l1pt, va)) 5201 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5202 "primary L1 @ 0x%lx\n", va); 5203 } 5204 5205 cpu_dcache_wbinv_all(); 5206 cpu_tlb_flushID(); 5207 cpu_cpwait(); 5208 5209 /* 5210 * now we allocate the "special" VAs which are used for tmp mappings 5211 * by the pmap (and other modules). we allocate the VAs by advancing 5212 * virtual_avail (note that there are no pages mapped at these VAs). 5213 * 5214 * Managed KVM space start from wherever initarm() tells us. 5215 */ 5216 virtual_avail = vstart; 5217 virtual_end = vend; 5218 5219 #ifdef PMAP_CACHE_VIPT 5220 /* 5221 * If we have a VIPT cache, we need one page/pte per possible alias 5222 * page so we won't violate cache aliasing rules. 5223 */ 5224 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5225 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5226 #else 5227 nptes = 1; 5228 #endif 5229 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5230 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5231 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5232 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5233 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5234 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5235 (void *)&msgbufaddr, NULL); 5236 5237 /* 5238 * Allocate a range of kernel virtual address space to be used 5239 * for L2 descriptor tables and metadata allocation in 5240 * pmap_growkernel(). 5241 */ 5242 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5243 pmap_alloc_specials(&virtual_avail, 5244 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5245 &pmap_kernel_l2ptp_kva, NULL); 5246 5247 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5248 pmap_alloc_specials(&virtual_avail, 5249 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5250 &pmap_kernel_l2dtable_kva, NULL); 5251 5252 /* 5253 * init the static-global locks and global pmap list. 5254 */ 5255 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 5256 5257 /* 5258 * We can now initialise the first L1's metadata. 5259 */ 5260 SLIST_INIT(&l1_list); 5261 TAILQ_INIT(&l1_lru_list); 5262 pmap_init_l1(l1, l1pt); 5263 5264 /* Set up vector page L1 details, if necessary */ 5265 if (vector_page < KERNEL_BASE) { 5266 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5267 l2b = pmap_get_l2_bucket(pm, vector_page); 5268 KDASSERT(l2b != NULL); 5269 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5270 L1_C_DOM(pm->pm_domain); 5271 } else 5272 pm->pm_pl1vec = NULL; 5273 5274 /* 5275 * Initialize the pmap cache 5276 */ 5277 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5278 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5279 LIST_INIT(&pmap_pmaps); 5280 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5281 5282 /* 5283 * Initialize the pv pool. 5284 */ 5285 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5286 &pmap_bootstrap_pv_allocator, IPL_NONE); 5287 5288 /* 5289 * Initialize the L2 dtable pool and cache. 5290 */ 5291 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5292 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5293 5294 /* 5295 * Initialise the L2 descriptor table pool and cache 5296 */ 5297 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5298 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5299 pmap_l2ptp_ctor, NULL, NULL); 5300 5301 cpu_dcache_wbinv_all(); 5302 } 5303 5304 static int 5305 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5306 { 5307 pd_entry_t *pdep, pde; 5308 pt_entry_t *ptep, pte; 5309 vaddr_t pa; 5310 int rv = 0; 5311 5312 /* 5313 * Make sure the descriptor itself has the correct cache mode 5314 */ 5315 pdep = &kl1[L1_IDX(va)]; 5316 pde = *pdep; 5317 5318 if (l1pte_section_p(pde)) { 5319 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5320 *pdep = (pde & ~L1_S_CACHE_MASK) | 5321 pte_l1_s_cache_mode_pt; 5322 PTE_SYNC(pdep); 5323 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5324 rv = 1; 5325 } 5326 } else { 5327 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5328 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5329 if (ptep == NULL) 5330 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5331 5332 ptep = &ptep[l2pte_index(va)]; 5333 pte = *ptep; 5334 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5335 *ptep = (pte & ~L2_S_CACHE_MASK) | 5336 pte_l2_s_cache_mode_pt; 5337 PTE_SYNC(ptep); 5338 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5339 rv = 1; 5340 } 5341 } 5342 5343 return (rv); 5344 } 5345 5346 static void 5347 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5348 { 5349 vaddr_t va = *availp; 5350 struct l2_bucket *l2b; 5351 5352 if (ptep) { 5353 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5354 if (l2b == NULL) 5355 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5356 5357 if (ptep) 5358 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5359 } 5360 5361 *vap = va; 5362 *availp = va + (PAGE_SIZE * pages); 5363 } 5364 5365 void 5366 pmap_init(void) 5367 { 5368 5369 /* 5370 * Set the available memory vars - These do not map to real memory 5371 * addresses and cannot as the physical memory is fragmented. 5372 * They are used by ps for %mem calculations. 5373 * One could argue whether this should be the entire memory or just 5374 * the memory that is useable in a user process. 5375 */ 5376 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5377 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5378 5379 /* 5380 * Now we need to free enough pv_entry structures to allow us to get 5381 * the kmem_map/kmem_object allocated and inited (done after this 5382 * function is finished). to do this we allocate one bootstrap page out 5383 * of kernel_map and use it to provide an initial pool of pv_entry 5384 * structures. we never free this page. 5385 */ 5386 pool_setlowat(&pmap_pv_pool, 5387 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5388 5389 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5390 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5391 UVM_KMF_WIRED|UVM_KMF_ZERO); 5392 5393 pmap_initialized = true; 5394 } 5395 5396 static vaddr_t last_bootstrap_page = 0; 5397 static void *free_bootstrap_pages = NULL; 5398 5399 static void * 5400 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5401 { 5402 extern void *pool_page_alloc(struct pool *, int); 5403 vaddr_t new_page; 5404 void *rv; 5405 5406 if (pmap_initialized) 5407 return (pool_page_alloc(pp, flags)); 5408 5409 if (free_bootstrap_pages) { 5410 rv = free_bootstrap_pages; 5411 free_bootstrap_pages = *((void **)rv); 5412 return (rv); 5413 } 5414 5415 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5416 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5417 5418 KASSERT(new_page > last_bootstrap_page); 5419 last_bootstrap_page = new_page; 5420 return ((void *)new_page); 5421 } 5422 5423 static void 5424 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5425 { 5426 extern void pool_page_free(struct pool *, void *); 5427 5428 if ((vaddr_t)v <= last_bootstrap_page) { 5429 *((void **)v) = free_bootstrap_pages; 5430 free_bootstrap_pages = v; 5431 return; 5432 } 5433 5434 if (pmap_initialized) { 5435 pool_page_free(pp, v); 5436 return; 5437 } 5438 } 5439 5440 /* 5441 * pmap_postinit() 5442 * 5443 * This routine is called after the vm and kmem subsystems have been 5444 * initialised. This allows the pmap code to perform any initialisation 5445 * that can only be done one the memory allocation is in place. 5446 */ 5447 void 5448 pmap_postinit(void) 5449 { 5450 extern paddr_t physical_start, physical_end; 5451 struct l2_bucket *l2b; 5452 struct l1_ttable *l1; 5453 struct pglist plist; 5454 struct vm_page *m; 5455 pd_entry_t *pl1pt; 5456 pt_entry_t *ptep, pte; 5457 vaddr_t va, eva; 5458 u_int loop, needed; 5459 int error; 5460 5461 pool_cache_setlowat(&pmap_l2ptp_cache, 5462 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5463 pool_cache_setlowat(&pmap_l2dtable_cache, 5464 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5465 5466 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5467 needed -= 1; 5468 5469 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 5470 5471 for (loop = 0; loop < needed; loop++, l1++) { 5472 /* Allocate a L1 page table */ 5473 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5474 if (va == 0) 5475 panic("Cannot allocate L1 KVM"); 5476 5477 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5478 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 5479 if (error) 5480 panic("Cannot allocate L1 physical pages"); 5481 5482 m = TAILQ_FIRST(&plist); 5483 eva = va + L1_TABLE_SIZE; 5484 pl1pt = (pd_entry_t *)va; 5485 5486 while (m && va < eva) { 5487 paddr_t pa = VM_PAGE_TO_PHYS(m); 5488 5489 pmap_kenter_pa(va, pa, 5490 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5491 5492 /* 5493 * Make sure the L1 descriptor table is mapped 5494 * with the cache-mode set to write-through. 5495 */ 5496 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5497 KDASSERT(l2b != NULL); 5498 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5499 pte = *ptep; 5500 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5501 *ptep = pte; 5502 PTE_SYNC(ptep); 5503 cpu_tlb_flushD_SE(va); 5504 5505 va += PAGE_SIZE; 5506 m = TAILQ_NEXT(m, pageq.queue); 5507 } 5508 5509 #ifdef DIAGNOSTIC 5510 if (m) 5511 panic("pmap_alloc_l1pt: pglist not empty"); 5512 #endif /* DIAGNOSTIC */ 5513 5514 pmap_init_l1(l1, pl1pt); 5515 } 5516 5517 #ifdef DEBUG 5518 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5519 needed); 5520 #endif 5521 } 5522 5523 /* 5524 * Note that the following routines are used by board-specific initialisation 5525 * code to configure the initial kernel page tables. 5526 * 5527 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5528 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5529 * behaviour of the old pmap, and provides an easy migration path for 5530 * initial bring-up of the new pmap on existing ports. Fortunately, 5531 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5532 * will be deprecated. 5533 * 5534 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5535 * tables. 5536 */ 5537 5538 /* 5539 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5540 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5541 * find them as necessary. 5542 * 5543 * Note that the data on this list MUST remain valid after initarm() returns, 5544 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5545 */ 5546 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5547 5548 static vaddr_t 5549 kernel_pt_lookup(paddr_t pa) 5550 { 5551 pv_addr_t *pv; 5552 5553 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5554 #ifndef ARM32_NEW_VM_LAYOUT 5555 if (pv->pv_pa == (pa & ~PGOFSET)) 5556 return (pv->pv_va | (pa & PGOFSET)); 5557 #else 5558 if (pv->pv_pa == pa) 5559 return (pv->pv_va); 5560 #endif 5561 } 5562 return (0); 5563 } 5564 5565 /* 5566 * pmap_map_section: 5567 * 5568 * Create a single section mapping. 5569 */ 5570 void 5571 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5572 { 5573 pd_entry_t *pde = (pd_entry_t *) l1pt; 5574 pd_entry_t fl; 5575 5576 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5577 5578 switch (cache) { 5579 case PTE_NOCACHE: 5580 default: 5581 fl = 0; 5582 break; 5583 5584 case PTE_CACHE: 5585 fl = pte_l1_s_cache_mode; 5586 break; 5587 5588 case PTE_PAGETABLE: 5589 fl = pte_l1_s_cache_mode_pt; 5590 break; 5591 } 5592 5593 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5594 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5595 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5596 } 5597 5598 /* 5599 * pmap_map_entry: 5600 * 5601 * Create a single page mapping. 5602 */ 5603 void 5604 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5605 { 5606 pd_entry_t *pde = (pd_entry_t *) l1pt; 5607 pt_entry_t fl; 5608 pt_entry_t *pte; 5609 5610 KASSERT(((va | pa) & PGOFSET) == 0); 5611 5612 switch (cache) { 5613 case PTE_NOCACHE: 5614 default: 5615 fl = 0; 5616 break; 5617 5618 case PTE_CACHE: 5619 fl = pte_l2_s_cache_mode; 5620 break; 5621 5622 case PTE_PAGETABLE: 5623 fl = pte_l2_s_cache_mode_pt; 5624 break; 5625 } 5626 5627 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5628 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5629 5630 #ifndef ARM32_NEW_VM_LAYOUT 5631 pte = (pt_entry_t *) 5632 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5633 #else 5634 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5635 #endif 5636 if (pte == NULL) 5637 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5638 5639 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5640 #ifndef ARM32_NEW_VM_LAYOUT 5641 pte += (va >> PGSHIFT) & 0x3ff; 5642 #else 5643 pte += l2pte_index(va); 5644 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5645 #endif 5646 *pte = fl; 5647 PTE_SYNC(pte); 5648 } 5649 5650 /* 5651 * pmap_link_l2pt: 5652 * 5653 * Link the L2 page table specified by "l2pv" into the L1 5654 * page table at the slot for "va". 5655 */ 5656 void 5657 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5658 { 5659 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5660 u_int slot = va >> L1_S_SHIFT; 5661 5662 #ifndef ARM32_NEW_VM_LAYOUT 5663 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5664 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5665 #endif 5666 5667 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5668 5669 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5670 #ifdef ARM32_NEW_VM_LAYOUT 5671 PTE_SYNC(&pde[slot]); 5672 #else 5673 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5674 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5675 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5676 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5677 #endif 5678 5679 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5680 } 5681 5682 /* 5683 * pmap_map_chunk: 5684 * 5685 * Map a chunk of memory using the most efficient mappings 5686 * possible (section, large page, small page) into the 5687 * provided L1 and L2 tables at the specified virtual address. 5688 */ 5689 vsize_t 5690 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5691 int prot, int cache) 5692 { 5693 pd_entry_t *pde = (pd_entry_t *) l1pt; 5694 pt_entry_t *pte, f1, f2s, f2l; 5695 vsize_t resid; 5696 int i; 5697 5698 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5699 5700 if (l1pt == 0) 5701 panic("pmap_map_chunk: no L1 table provided"); 5702 5703 #ifdef VERBOSE_INIT_ARM 5704 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5705 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5706 #endif 5707 5708 switch (cache) { 5709 case PTE_NOCACHE: 5710 default: 5711 f1 = 0; 5712 f2l = 0; 5713 f2s = 0; 5714 break; 5715 5716 case PTE_CACHE: 5717 f1 = pte_l1_s_cache_mode; 5718 f2l = pte_l2_l_cache_mode; 5719 f2s = pte_l2_s_cache_mode; 5720 break; 5721 5722 case PTE_PAGETABLE: 5723 f1 = pte_l1_s_cache_mode_pt; 5724 f2l = pte_l2_l_cache_mode_pt; 5725 f2s = pte_l2_s_cache_mode_pt; 5726 break; 5727 } 5728 5729 size = resid; 5730 5731 while (resid > 0) { 5732 /* See if we can use a section mapping. */ 5733 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5734 #ifdef VERBOSE_INIT_ARM 5735 printf("S"); 5736 #endif 5737 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5738 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5739 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5740 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5741 va += L1_S_SIZE; 5742 pa += L1_S_SIZE; 5743 resid -= L1_S_SIZE; 5744 continue; 5745 } 5746 5747 /* 5748 * Ok, we're going to use an L2 table. Make sure 5749 * one is actually in the corresponding L1 slot 5750 * for the current VA. 5751 */ 5752 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5753 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5754 5755 #ifndef ARM32_NEW_VM_LAYOUT 5756 pte = (pt_entry_t *) 5757 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5758 #else 5759 pte = (pt_entry_t *) kernel_pt_lookup( 5760 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5761 #endif 5762 if (pte == NULL) 5763 panic("pmap_map_chunk: can't find L2 table for VA" 5764 "0x%08lx", va); 5765 5766 /* See if we can use a L2 large page mapping. */ 5767 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5768 #ifdef VERBOSE_INIT_ARM 5769 printf("L"); 5770 #endif 5771 for (i = 0; i < 16; i++) { 5772 #ifndef ARM32_NEW_VM_LAYOUT 5773 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5774 L2_L_PROTO | pa | 5775 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5776 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5777 #else 5778 pte[l2pte_index(va) + i] = 5779 L2_L_PROTO | pa | 5780 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5781 PTE_SYNC(&pte[l2pte_index(va) + i]); 5782 #endif 5783 } 5784 va += L2_L_SIZE; 5785 pa += L2_L_SIZE; 5786 resid -= L2_L_SIZE; 5787 continue; 5788 } 5789 5790 /* Use a small page mapping. */ 5791 #ifdef VERBOSE_INIT_ARM 5792 printf("P"); 5793 #endif 5794 #ifndef ARM32_NEW_VM_LAYOUT 5795 pte[(va >> PGSHIFT) & 0x3ff] = 5796 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5797 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5798 #else 5799 pte[l2pte_index(va)] = 5800 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5801 PTE_SYNC(&pte[l2pte_index(va)]); 5802 #endif 5803 va += PAGE_SIZE; 5804 pa += PAGE_SIZE; 5805 resid -= PAGE_SIZE; 5806 } 5807 #ifdef VERBOSE_INIT_ARM 5808 printf("\n"); 5809 #endif 5810 return (size); 5811 } 5812 5813 /********************** Static device map routines ***************************/ 5814 5815 static const struct pmap_devmap *pmap_devmap_table; 5816 5817 /* 5818 * Register the devmap table. This is provided in case early console 5819 * initialization needs to register mappings created by bootstrap code 5820 * before pmap_devmap_bootstrap() is called. 5821 */ 5822 void 5823 pmap_devmap_register(const struct pmap_devmap *table) 5824 { 5825 5826 pmap_devmap_table = table; 5827 } 5828 5829 /* 5830 * Map all of the static regions in the devmap table, and remember 5831 * the devmap table so other parts of the kernel can look up entries 5832 * later. 5833 */ 5834 void 5835 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5836 { 5837 int i; 5838 5839 pmap_devmap_table = table; 5840 5841 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5842 #ifdef VERBOSE_INIT_ARM 5843 printf("devmap: %08lx -> %08lx @ %08lx\n", 5844 pmap_devmap_table[i].pd_pa, 5845 pmap_devmap_table[i].pd_pa + 5846 pmap_devmap_table[i].pd_size - 1, 5847 pmap_devmap_table[i].pd_va); 5848 #endif 5849 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5850 pmap_devmap_table[i].pd_pa, 5851 pmap_devmap_table[i].pd_size, 5852 pmap_devmap_table[i].pd_prot, 5853 pmap_devmap_table[i].pd_cache); 5854 } 5855 } 5856 5857 const struct pmap_devmap * 5858 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5859 { 5860 uint64_t endpa; 5861 int i; 5862 5863 if (pmap_devmap_table == NULL) 5864 return (NULL); 5865 5866 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5867 5868 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5869 if (pa >= pmap_devmap_table[i].pd_pa && 5870 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5871 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5872 return (&pmap_devmap_table[i]); 5873 } 5874 5875 return (NULL); 5876 } 5877 5878 const struct pmap_devmap * 5879 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5880 { 5881 int i; 5882 5883 if (pmap_devmap_table == NULL) 5884 return (NULL); 5885 5886 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5887 if (va >= pmap_devmap_table[i].pd_va && 5888 va + size - 1 <= pmap_devmap_table[i].pd_va + 5889 pmap_devmap_table[i].pd_size - 1) 5890 return (&pmap_devmap_table[i]); 5891 } 5892 5893 return (NULL); 5894 } 5895 5896 /********************** PTE initialization routines **************************/ 5897 5898 /* 5899 * These routines are called when the CPU type is identified to set up 5900 * the PTE prototypes, cache modes, etc. 5901 * 5902 * The variables are always here, just in case modules need to reference 5903 * them (though, they shouldn't). 5904 */ 5905 5906 pt_entry_t pte_l1_s_cache_mode; 5907 pt_entry_t pte_l1_s_wc_mode; 5908 pt_entry_t pte_l1_s_cache_mode_pt; 5909 pt_entry_t pte_l1_s_cache_mask; 5910 5911 pt_entry_t pte_l2_l_cache_mode; 5912 pt_entry_t pte_l2_l_wc_mode; 5913 pt_entry_t pte_l2_l_cache_mode_pt; 5914 pt_entry_t pte_l2_l_cache_mask; 5915 5916 pt_entry_t pte_l2_s_cache_mode; 5917 pt_entry_t pte_l2_s_wc_mode; 5918 pt_entry_t pte_l2_s_cache_mode_pt; 5919 pt_entry_t pte_l2_s_cache_mask; 5920 5921 pt_entry_t pte_l1_s_prot_u; 5922 pt_entry_t pte_l1_s_prot_w; 5923 pt_entry_t pte_l1_s_prot_ro; 5924 pt_entry_t pte_l1_s_prot_mask; 5925 5926 pt_entry_t pte_l2_s_prot_u; 5927 pt_entry_t pte_l2_s_prot_w; 5928 pt_entry_t pte_l2_s_prot_ro; 5929 pt_entry_t pte_l2_s_prot_mask; 5930 5931 pt_entry_t pte_l2_l_prot_u; 5932 pt_entry_t pte_l2_l_prot_w; 5933 pt_entry_t pte_l2_l_prot_ro; 5934 pt_entry_t pte_l2_l_prot_mask; 5935 5936 pt_entry_t pte_l1_s_proto; 5937 pt_entry_t pte_l1_c_proto; 5938 pt_entry_t pte_l2_s_proto; 5939 5940 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5941 void (*pmap_zero_page_func)(paddr_t); 5942 5943 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5944 void 5945 pmap_pte_init_generic(void) 5946 { 5947 5948 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5949 pte_l1_s_wc_mode = L1_S_B; 5950 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5951 5952 pte_l2_l_cache_mode = L2_B|L2_C; 5953 pte_l2_l_wc_mode = L2_B; 5954 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5955 5956 pte_l2_s_cache_mode = L2_B|L2_C; 5957 pte_l2_s_wc_mode = L2_B; 5958 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5959 5960 /* 5961 * If we have a write-through cache, set B and C. If 5962 * we have a write-back cache, then we assume setting 5963 * only C will make those pages write-through. 5964 */ 5965 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5966 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5967 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5968 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5969 } else { 5970 #if ARM_MMU_V6 > 1 5971 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5972 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5973 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5974 #else 5975 pte_l1_s_cache_mode_pt = L1_S_C; 5976 pte_l2_l_cache_mode_pt = L2_C; 5977 pte_l2_s_cache_mode_pt = L2_C; 5978 #endif 5979 } 5980 5981 pte_l1_s_prot_u = L1_S_PROT_U_generic; 5982 pte_l1_s_prot_w = L1_S_PROT_W_generic; 5983 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 5984 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 5985 5986 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5987 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5988 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 5989 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5990 5991 pte_l2_l_prot_u = L2_L_PROT_U_generic; 5992 pte_l2_l_prot_w = L2_L_PROT_W_generic; 5993 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 5994 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 5995 5996 pte_l1_s_proto = L1_S_PROTO_generic; 5997 pte_l1_c_proto = L1_C_PROTO_generic; 5998 pte_l2_s_proto = L2_S_PROTO_generic; 5999 6000 pmap_copy_page_func = pmap_copy_page_generic; 6001 pmap_zero_page_func = pmap_zero_page_generic; 6002 } 6003 6004 #if defined(CPU_ARM8) 6005 void 6006 pmap_pte_init_arm8(void) 6007 { 6008 6009 /* 6010 * ARM8 is compatible with generic, but we need to use 6011 * the page tables uncached. 6012 */ 6013 pmap_pte_init_generic(); 6014 6015 pte_l1_s_cache_mode_pt = 0; 6016 pte_l2_l_cache_mode_pt = 0; 6017 pte_l2_s_cache_mode_pt = 0; 6018 } 6019 #endif /* CPU_ARM8 */ 6020 6021 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6022 void 6023 pmap_pte_init_arm9(void) 6024 { 6025 6026 /* 6027 * ARM9 is compatible with generic, but we want to use 6028 * write-through caching for now. 6029 */ 6030 pmap_pte_init_generic(); 6031 6032 pte_l1_s_cache_mode = L1_S_C; 6033 pte_l2_l_cache_mode = L2_C; 6034 pte_l2_s_cache_mode = L2_C; 6035 6036 pte_l1_s_wc_mode = L1_S_B; 6037 pte_l2_l_wc_mode = L2_B; 6038 pte_l2_s_wc_mode = L2_B; 6039 6040 pte_l1_s_cache_mode_pt = L1_S_C; 6041 pte_l2_l_cache_mode_pt = L2_C; 6042 pte_l2_s_cache_mode_pt = L2_C; 6043 } 6044 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6045 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6046 6047 #if defined(CPU_ARM10) 6048 void 6049 pmap_pte_init_arm10(void) 6050 { 6051 6052 /* 6053 * ARM10 is compatible with generic, but we want to use 6054 * write-through caching for now. 6055 */ 6056 pmap_pte_init_generic(); 6057 6058 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6059 pte_l2_l_cache_mode = L2_B | L2_C; 6060 pte_l2_s_cache_mode = L2_B | L2_C; 6061 6062 pte_l1_s_cache_mode = L1_S_B; 6063 pte_l2_l_cache_mode = L2_B; 6064 pte_l2_s_cache_mode = L2_B; 6065 6066 pte_l1_s_cache_mode_pt = L1_S_C; 6067 pte_l2_l_cache_mode_pt = L2_C; 6068 pte_l2_s_cache_mode_pt = L2_C; 6069 6070 } 6071 #endif /* CPU_ARM10 */ 6072 6073 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6074 void 6075 pmap_pte_init_arm11(void) 6076 { 6077 6078 /* 6079 * ARM11 is compatible with generic, but we want to use 6080 * write-through caching for now. 6081 */ 6082 pmap_pte_init_generic(); 6083 6084 pte_l1_s_cache_mode = L1_S_C; 6085 pte_l2_l_cache_mode = L2_C; 6086 pte_l2_s_cache_mode = L2_C; 6087 6088 pte_l1_s_wc_mode = L1_S_B; 6089 pte_l2_l_wc_mode = L2_B; 6090 pte_l2_s_wc_mode = L2_B; 6091 6092 pte_l1_s_cache_mode_pt = L1_S_C; 6093 pte_l2_l_cache_mode_pt = L2_C; 6094 pte_l2_s_cache_mode_pt = L2_C; 6095 } 6096 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6097 6098 #if ARM_MMU_SA1 == 1 6099 void 6100 pmap_pte_init_sa1(void) 6101 { 6102 6103 /* 6104 * The StrongARM SA-1 cache does not have a write-through 6105 * mode. So, do the generic initialization, then reset 6106 * the page table cache mode to B=1,C=1, and note that 6107 * the PTEs need to be sync'd. 6108 */ 6109 pmap_pte_init_generic(); 6110 6111 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6112 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6113 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6114 6115 pmap_needs_pte_sync = 1; 6116 } 6117 #endif /* ARM_MMU_SA1 == 1*/ 6118 6119 #if ARM_MMU_XSCALE == 1 6120 #if (ARM_NMMUS > 1) 6121 static u_int xscale_use_minidata; 6122 #endif 6123 6124 void 6125 pmap_pte_init_xscale(void) 6126 { 6127 uint32_t auxctl; 6128 int write_through = 0; 6129 6130 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6131 pte_l1_s_wc_mode = L1_S_B; 6132 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6133 6134 pte_l2_l_cache_mode = L2_B|L2_C; 6135 pte_l2_l_wc_mode = L2_B; 6136 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6137 6138 pte_l2_s_cache_mode = L2_B|L2_C; 6139 pte_l2_s_wc_mode = L2_B; 6140 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6141 6142 pte_l1_s_cache_mode_pt = L1_S_C; 6143 pte_l2_l_cache_mode_pt = L2_C; 6144 pte_l2_s_cache_mode_pt = L2_C; 6145 6146 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6147 /* 6148 * The XScale core has an enhanced mode where writes that 6149 * miss the cache cause a cache line to be allocated. This 6150 * is significantly faster than the traditional, write-through 6151 * behavior of this case. 6152 */ 6153 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6154 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6155 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6156 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6157 6158 #ifdef XSCALE_CACHE_WRITE_THROUGH 6159 /* 6160 * Some versions of the XScale core have various bugs in 6161 * their cache units, the work-around for which is to run 6162 * the cache in write-through mode. Unfortunately, this 6163 * has a major (negative) impact on performance. So, we 6164 * go ahead and run fast-and-loose, in the hopes that we 6165 * don't line up the planets in a way that will trip the 6166 * bugs. 6167 * 6168 * However, we give you the option to be slow-but-correct. 6169 */ 6170 write_through = 1; 6171 #elif defined(XSCALE_CACHE_WRITE_BACK) 6172 /* force write back cache mode */ 6173 write_through = 0; 6174 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6175 /* 6176 * Intel PXA2[15]0 processors are known to have a bug in 6177 * write-back cache on revision 4 and earlier (stepping 6178 * A[01] and B[012]). Fixed for C0 and later. 6179 */ 6180 { 6181 uint32_t id, type; 6182 6183 id = cpufunc_id(); 6184 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6185 6186 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6187 if ((id & CPU_ID_REVISION_MASK) < 5) { 6188 /* write through for stepping A0-1 and B0-2 */ 6189 write_through = 1; 6190 } 6191 } 6192 } 6193 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6194 6195 if (write_through) { 6196 pte_l1_s_cache_mode = L1_S_C; 6197 pte_l2_l_cache_mode = L2_C; 6198 pte_l2_s_cache_mode = L2_C; 6199 } 6200 6201 #if (ARM_NMMUS > 1) 6202 xscale_use_minidata = 1; 6203 #endif 6204 6205 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6206 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6207 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6208 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6209 6210 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6211 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6212 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6213 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6214 6215 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6216 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6217 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6218 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6219 6220 pte_l1_s_proto = L1_S_PROTO_xscale; 6221 pte_l1_c_proto = L1_C_PROTO_xscale; 6222 pte_l2_s_proto = L2_S_PROTO_xscale; 6223 6224 pmap_copy_page_func = pmap_copy_page_xscale; 6225 pmap_zero_page_func = pmap_zero_page_xscale; 6226 6227 /* 6228 * Disable ECC protection of page table access, for now. 6229 */ 6230 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6231 auxctl &= ~XSCALE_AUXCTL_P; 6232 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6233 } 6234 6235 /* 6236 * xscale_setup_minidata: 6237 * 6238 * Set up the mini-data cache clean area. We require the 6239 * caller to allocate the right amount of physically and 6240 * virtually contiguous space. 6241 */ 6242 void 6243 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6244 { 6245 extern vaddr_t xscale_minidata_clean_addr; 6246 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6247 pd_entry_t *pde = (pd_entry_t *) l1pt; 6248 pt_entry_t *pte; 6249 vsize_t size; 6250 uint32_t auxctl; 6251 6252 xscale_minidata_clean_addr = va; 6253 6254 /* Round it to page size. */ 6255 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6256 6257 for (; size != 0; 6258 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6259 #ifndef ARM32_NEW_VM_LAYOUT 6260 pte = (pt_entry_t *) 6261 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6262 #else 6263 pte = (pt_entry_t *) kernel_pt_lookup( 6264 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6265 #endif 6266 if (pte == NULL) 6267 panic("xscale_setup_minidata: can't find L2 table for " 6268 "VA 0x%08lx", va); 6269 #ifndef ARM32_NEW_VM_LAYOUT 6270 pte[(va >> PGSHIFT) & 0x3ff] = 6271 #else 6272 pte[l2pte_index(va)] = 6273 #endif 6274 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6275 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6276 } 6277 6278 /* 6279 * Configure the mini-data cache for write-back with 6280 * read/write-allocate. 6281 * 6282 * NOTE: In order to reconfigure the mini-data cache, we must 6283 * make sure it contains no valid data! In order to do that, 6284 * we must issue a global data cache invalidate command! 6285 * 6286 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6287 * THIS IS VERY IMPORTANT! 6288 */ 6289 6290 /* Invalidate data and mini-data. */ 6291 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6292 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6293 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6294 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6295 } 6296 6297 /* 6298 * Change the PTEs for the specified kernel mappings such that they 6299 * will use the mini data cache instead of the main data cache. 6300 */ 6301 void 6302 pmap_uarea(vaddr_t va) 6303 { 6304 struct l2_bucket *l2b; 6305 pt_entry_t *ptep, *sptep, pte; 6306 vaddr_t next_bucket, eva; 6307 6308 #if (ARM_NMMUS > 1) 6309 if (xscale_use_minidata == 0) 6310 return; 6311 #endif 6312 6313 eva = va + USPACE; 6314 6315 while (va < eva) { 6316 next_bucket = L2_NEXT_BUCKET(va); 6317 if (next_bucket > eva) 6318 next_bucket = eva; 6319 6320 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6321 KDASSERT(l2b != NULL); 6322 6323 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6324 6325 while (va < next_bucket) { 6326 pte = *ptep; 6327 if (!l2pte_minidata(pte)) { 6328 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6329 cpu_tlb_flushD_SE(va); 6330 *ptep = pte & ~L2_B; 6331 } 6332 ptep++; 6333 va += PAGE_SIZE; 6334 } 6335 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6336 } 6337 cpu_cpwait(); 6338 } 6339 #endif /* ARM_MMU_XSCALE == 1 */ 6340 6341 6342 #if defined(CPU_ARM11MPCORE) 6343 6344 void 6345 pmap_pte_init_arm11mpcore(void) 6346 { 6347 6348 /* cache mode is controlled by 5 bits (B, C, TEX) */ 6349 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 6350 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 6351 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6352 /* use extended small page (without APn, with TEX) */ 6353 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 6354 #else 6355 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 6356 #endif 6357 6358 /* write-back, write-allocate */ 6359 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6360 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 6361 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6362 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6363 #else 6364 /* no TEX. read-allocate */ 6365 pte_l2_s_cache_mode = L2_C | L2_B; 6366 #endif 6367 /* 6368 * write-back, write-allocate for page tables. 6369 */ 6370 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6371 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 6372 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6373 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6374 #else 6375 pte_l2_s_cache_mode_pt = L2_C | L2_B; 6376 #endif 6377 6378 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 6379 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 6380 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 6381 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 6382 6383 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6384 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 6385 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 6386 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 6387 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 6388 6389 #else 6390 /* with AP[0..3] */ 6391 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6392 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6393 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6394 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6395 #endif 6396 6397 #ifdef ARM11MPCORE_COMPAT_MMU 6398 /* with AP[0..3] */ 6399 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6400 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6401 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6402 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6403 6404 pte_l1_s_proto = L1_S_PROTO_armv6; 6405 pte_l1_c_proto = L1_C_PROTO_armv6; 6406 pte_l2_s_proto = L2_S_PROTO_armv6c; 6407 #else 6408 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 6409 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 6410 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 6411 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 6412 6413 pte_l1_s_proto = L1_S_PROTO_armv6; 6414 pte_l1_c_proto = L1_C_PROTO_armv6; 6415 pte_l2_s_proto = L2_S_PROTO_armv6n; 6416 #endif 6417 6418 pmap_copy_page_func = pmap_copy_page_generic; 6419 pmap_zero_page_func = pmap_zero_page_generic; 6420 pmap_needs_pte_sync = 1; 6421 } 6422 #endif /* CPU_ARM11MPCORE */ 6423 6424 6425 #if ARM_MMU_V7 == 1 6426 void 6427 pmap_pte_init_armv7(void) 6428 { 6429 /* 6430 * The ARMv7-A MMU is mostly compatible with generic. If the 6431 * AP field is zero, that now means "no access" rather than 6432 * read-only. The prototypes are a little different because of 6433 * the XN bit. 6434 */ 6435 pmap_pte_init_generic(); 6436 6437 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6438 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6439 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6440 6441 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6442 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6443 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6444 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6445 6446 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6447 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6448 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6449 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6450 6451 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6452 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6453 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6454 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6455 6456 pte_l1_s_proto = L1_S_PROTO_armv7; 6457 pte_l1_c_proto = L1_C_PROTO_armv7; 6458 pte_l2_s_proto = L2_S_PROTO_armv7; 6459 } 6460 #endif /* ARM_MMU_V7 */ 6461 6462 /* 6463 * return the PA of the current L1 table, for use when handling a crash dump 6464 */ 6465 uint32_t pmap_kernel_L1_addr(void) 6466 { 6467 return pmap_kernel()->pm_l1->l1_physaddr; 6468 } 6469 6470 #if defined(DDB) 6471 /* 6472 * A couple of ddb-callable functions for dumping pmaps 6473 */ 6474 void pmap_dump_all(void); 6475 void pmap_dump(pmap_t); 6476 6477 void 6478 pmap_dump_all(void) 6479 { 6480 pmap_t pm; 6481 6482 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6483 if (pm == pmap_kernel()) 6484 continue; 6485 pmap_dump(pm); 6486 printf("\n"); 6487 } 6488 } 6489 6490 static pt_entry_t ncptes[64]; 6491 static void pmap_dump_ncpg(pmap_t); 6492 6493 void 6494 pmap_dump(pmap_t pm) 6495 { 6496 struct l2_dtable *l2; 6497 struct l2_bucket *l2b; 6498 pt_entry_t *ptep, pte; 6499 vaddr_t l2_va, l2b_va, va; 6500 int i, j, k, occ, rows = 0; 6501 6502 if (pm == pmap_kernel()) 6503 printf("pmap_kernel (%p): ", pm); 6504 else 6505 printf("user pmap (%p): ", pm); 6506 6507 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6508 6509 l2_va = 0; 6510 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6511 l2 = pm->pm_l2[i]; 6512 6513 if (l2 == NULL || l2->l2_occupancy == 0) 6514 continue; 6515 6516 l2b_va = l2_va; 6517 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6518 l2b = &l2->l2_bucket[j]; 6519 6520 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6521 continue; 6522 6523 ptep = l2b->l2b_kva; 6524 6525 for (k = 0; k < 256 && ptep[k] == 0; k++) 6526 ; 6527 6528 k &= ~63; 6529 occ = l2b->l2b_occupancy; 6530 va = l2b_va + (k * 4096); 6531 for (; k < 256; k++, va += 0x1000) { 6532 char ch = ' '; 6533 if ((k % 64) == 0) { 6534 if ((rows % 8) == 0) { 6535 printf( 6536 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6537 } 6538 printf("%08lx: ", va); 6539 } 6540 6541 ncptes[k & 63] = 0; 6542 pte = ptep[k]; 6543 if (pte == 0) { 6544 ch = '.'; 6545 } else { 6546 occ--; 6547 switch (pte & 0x0c) { 6548 case 0x00: 6549 ch = 'D'; /* No cache No buff */ 6550 break; 6551 case 0x04: 6552 ch = 'B'; /* No cache buff */ 6553 break; 6554 case 0x08: 6555 if (pte & 0x40) 6556 ch = 'm'; 6557 else 6558 ch = 'C'; /* Cache No buff */ 6559 break; 6560 case 0x0c: 6561 ch = 'F'; /* Cache Buff */ 6562 break; 6563 } 6564 6565 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6566 ch += 0x20; 6567 6568 if ((pte & 0xc) == 0) 6569 ncptes[k & 63] = pte; 6570 } 6571 6572 if ((k % 64) == 63) { 6573 rows++; 6574 printf("%c\n", ch); 6575 pmap_dump_ncpg(pm); 6576 if (occ == 0) 6577 break; 6578 } else 6579 printf("%c", ch); 6580 } 6581 } 6582 } 6583 } 6584 6585 static void 6586 pmap_dump_ncpg(pmap_t pm) 6587 { 6588 struct vm_page *pg; 6589 struct vm_page_md *md; 6590 struct pv_entry *pv; 6591 int i; 6592 6593 for (i = 0; i < 63; i++) { 6594 if (ncptes[i] == 0) 6595 continue; 6596 6597 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6598 if (pg == NULL) 6599 continue; 6600 md = VM_PAGE_TO_MD(pg); 6601 6602 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6603 VM_PAGE_TO_PHYS(pg), 6604 md->krw_mappings, md->kro_mappings, 6605 md->urw_mappings, md->uro_mappings); 6606 6607 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6608 printf(" %c va 0x%08lx, flags 0x%x\n", 6609 (pm == pv->pv_pmap) ? '*' : ' ', 6610 pv->pv_va, pv->pv_flags); 6611 } 6612 } 6613 } 6614 #endif 6615 6616 #ifdef PMAP_STEAL_MEMORY 6617 void 6618 pmap_boot_pageadd(pv_addr_t *newpv) 6619 { 6620 pv_addr_t *pv, *npv; 6621 6622 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6623 if (newpv->pv_pa < pv->pv_va) { 6624 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6625 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6626 newpv->pv_size += pv->pv_size; 6627 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6628 } 6629 pv = NULL; 6630 } else { 6631 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6632 pv = npv) { 6633 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6634 KASSERT(pv->pv_pa < newpv->pv_pa); 6635 if (newpv->pv_pa > npv->pv_pa) 6636 continue; 6637 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6638 pv->pv_size += newpv->pv_size; 6639 return; 6640 } 6641 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6642 break; 6643 newpv->pv_size += npv->pv_size; 6644 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6645 SLIST_REMOVE_AFTER(newpv, pv_list); 6646 return; 6647 } 6648 } 6649 } 6650 6651 if (pv) { 6652 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6653 } else { 6654 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6655 } 6656 } 6657 6658 void 6659 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6660 pv_addr_t *rpv) 6661 { 6662 pv_addr_t *pv, **pvp; 6663 struct vm_physseg *ps; 6664 size_t i; 6665 6666 KASSERT(amount & PGOFSET); 6667 KASSERT((mask & PGOFSET) == 0); 6668 KASSERT((match & PGOFSET) == 0); 6669 KASSERT(amount != 0); 6670 6671 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6672 (pv = *pvp) != NULL; 6673 pvp = &SLIST_NEXT(pv, pv_list)) { 6674 pv_addr_t *newpv; 6675 psize_t off; 6676 /* 6677 * If this entry is too small to satify the request... 6678 */ 6679 KASSERT(pv->pv_size > 0); 6680 if (pv->pv_size < amount) 6681 continue; 6682 6683 for (off = 0; off <= mask; off += PAGE_SIZE) { 6684 if (((pv->pv_pa + off) & mask) == match 6685 && off + amount <= pv->pv_size) 6686 break; 6687 } 6688 if (off > mask) 6689 continue; 6690 6691 rpv->pv_va = pv->pv_va + off; 6692 rpv->pv_pa = pv->pv_pa + off; 6693 rpv->pv_size = amount; 6694 pv->pv_size -= amount; 6695 if (pv->pv_size == 0) { 6696 KASSERT(off == 0); 6697 KASSERT((vaddr_t) pv == rpv->pv_va); 6698 *pvp = SLIST_NEXT(pv, pv_list); 6699 } else if (off == 0) { 6700 KASSERT((vaddr_t) pv == rpv->pv_va); 6701 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6702 *newpv = *pv; 6703 newpv->pv_pa += amount; 6704 newpv->pv_va += amount; 6705 *pvp = newpv; 6706 } else if (off < pv->pv_size) { 6707 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6708 *newpv = *pv; 6709 newpv->pv_size -= off; 6710 newpv->pv_pa += off + amount; 6711 newpv->pv_va += off + amount; 6712 6713 SLIST_NEXT(pv, pv_list) = newpv; 6714 pv->pv_size = off; 6715 } else { 6716 KASSERT((vaddr_t) pv != rpv->pv_va); 6717 } 6718 memset((void *)rpv->pv_va, 0, amount); 6719 return; 6720 } 6721 6722 if (vm_nphysseg == 0) 6723 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6724 6725 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6726 (pv = *pvp) != NULL; 6727 pvp = &SLIST_NEXT(pv, pv_list)) { 6728 if (SLIST_NEXT(pv, pv_list) == NULL) 6729 break; 6730 } 6731 KASSERT(mask == 0); 6732 for (i = 0; i < vm_nphysseg; i++) { 6733 ps = VM_PHYSMEM_PTR(i); 6734 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6735 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6736 rpv->pv_va = pv->pv_va; 6737 rpv->pv_pa = pv->pv_pa; 6738 rpv->pv_size = amount; 6739 *pvp = NULL; 6740 pmap_map_chunk(kernel_l1pt.pv_va, 6741 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6742 ptoa(ps->avail_start), 6743 amount - pv->pv_size, 6744 VM_PROT_READ|VM_PROT_WRITE, 6745 PTE_CACHE); 6746 ps->avail_start += atop(amount - pv->pv_size); 6747 /* 6748 * If we consumed the entire physseg, remove it. 6749 */ 6750 if (ps->avail_start == ps->avail_end) { 6751 for (--vm_nphysseg; i < vm_nphysseg; i++) 6752 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6753 } 6754 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6755 return; 6756 } 6757 } 6758 6759 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6760 } 6761 6762 vaddr_t 6763 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6764 { 6765 pv_addr_t pv; 6766 6767 pmap_boot_pagealloc(size, 0, 0, &pv); 6768 6769 return pv.pv_va; 6770 } 6771 #endif /* PMAP_STEAL_MEMORY */ 6772 6773 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6774 { 6775 sysctl_createv(clog, 0, NULL, NULL, 6776 CTLFLAG_PERMANENT, 6777 CTLTYPE_NODE, "machdep", NULL, 6778 NULL, 0, NULL, 0, 6779 CTL_MACHDEP, CTL_EOL); 6780 6781 sysctl_createv(clog, 0, NULL, NULL, 6782 CTLFLAG_PERMANENT, 6783 CTLTYPE_INT, "kmpages", 6784 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6785 NULL, 0, &pmap_kmpages, 0, 6786 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6787 } 6788
Indexes created Tue Sep 30 07:10:03 GMT 2025