pmap.c revision 1.233
1 /* $NetBSD: pmap.c,v 1.233 2012/08/29 17:08:41 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/pool.h> 201 #include <sys/kmem.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <sys/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.233 2012/08/29 17:08:41 matt Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 static struct pmap kernel_pmap_store; 258 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 #ifdef PMAPCOUNTERS 308 #define PMAP_EVCNT_INITIALIZER(name) \ 309 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 310 311 #ifdef PMAP_CACHE_VIPT 312 static struct evcnt pmap_ev_vac_clean_one = 313 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 314 static struct evcnt pmap_ev_vac_flush_one = 315 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_lots = 317 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 318 static struct evcnt pmap_ev_vac_flush_lots2 = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 324 325 static struct evcnt pmap_ev_vac_color_new = 326 PMAP_EVCNT_INITIALIZER("new page color"); 327 static struct evcnt pmap_ev_vac_color_reuse = 328 PMAP_EVCNT_INITIALIZER("ok first page color"); 329 static struct evcnt pmap_ev_vac_color_ok = 330 PMAP_EVCNT_INITIALIZER("ok page color"); 331 static struct evcnt pmap_ev_vac_color_blind = 332 PMAP_EVCNT_INITIALIZER("blind page color"); 333 static struct evcnt pmap_ev_vac_color_change = 334 PMAP_EVCNT_INITIALIZER("change page color"); 335 static struct evcnt pmap_ev_vac_color_erase = 336 PMAP_EVCNT_INITIALIZER("erase page color"); 337 static struct evcnt pmap_ev_vac_color_none = 338 PMAP_EVCNT_INITIALIZER("no page color"); 339 static struct evcnt pmap_ev_vac_color_restore = 340 PMAP_EVCNT_INITIALIZER("restore page color"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 350 #endif 351 352 static struct evcnt pmap_ev_mappings = 353 PMAP_EVCNT_INITIALIZER("pages mapped"); 354 static struct evcnt pmap_ev_unmappings = 355 PMAP_EVCNT_INITIALIZER("pages unmapped"); 356 static struct evcnt pmap_ev_remappings = 357 PMAP_EVCNT_INITIALIZER("pages remapped"); 358 359 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 360 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 362 363 static struct evcnt pmap_ev_kernel_mappings = 364 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 365 static struct evcnt pmap_ev_kernel_unmappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 367 static struct evcnt pmap_ev_kernel_remappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 373 374 static struct evcnt pmap_ev_kenter_mappings = 375 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 376 static struct evcnt pmap_ev_kenter_unmappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 378 static struct evcnt pmap_ev_kenter_remappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 380 static struct evcnt pmap_ev_pt_mappings = 381 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 382 383 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 387 388 #ifdef PMAP_CACHE_VIPT 389 static struct evcnt pmap_ev_exec_mappings = 390 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 391 static struct evcnt pmap_ev_exec_cached = 392 PMAP_EVCNT_INITIALIZER("exec pages cached"); 393 394 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 396 397 static struct evcnt pmap_ev_exec_synced = 398 PMAP_EVCNT_INITIALIZER("exec pages synced"); 399 static struct evcnt pmap_ev_exec_synced_map = 400 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 401 static struct evcnt pmap_ev_exec_synced_unmap = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 403 static struct evcnt pmap_ev_exec_synced_remap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 405 static struct evcnt pmap_ev_exec_synced_clearbit = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 407 static struct evcnt pmap_ev_exec_synced_kremove = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 409 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 416 417 static struct evcnt pmap_ev_exec_discarded_unmap = 418 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 419 static struct evcnt pmap_ev_exec_discarded_zero = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 421 static struct evcnt pmap_ev_exec_discarded_copy = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 423 static struct evcnt pmap_ev_exec_discarded_page_protect = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 425 static struct evcnt pmap_ev_exec_discarded_clearbit = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 427 static struct evcnt pmap_ev_exec_discarded_kremove = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 429 430 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 436 #endif /* PMAP_CACHE_VIPT */ 437 438 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 439 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 440 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 441 442 EVCNT_ATTACH_STATIC(pmap_ev_updates); 443 EVCNT_ATTACH_STATIC(pmap_ev_collects); 444 EVCNT_ATTACH_STATIC(pmap_ev_activations); 445 446 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 447 #else 448 #define PMAPCOUNT(x) ((void)0) 449 #endif 450 451 /* 452 * pmap copy/zero page, and mem(5) hook point 453 */ 454 static pt_entry_t *csrc_pte, *cdst_pte; 455 static vaddr_t csrcp, cdstp; 456 vaddr_t memhook; /* used by mem.c */ 457 kmutex_t memlock; /* used by mem.c */ 458 void *zeropage; /* used by mem.c */ 459 extern void *msgbufaddr; 460 int pmap_kmpages; 461 /* 462 * Flag to indicate if pmap_init() has done its thing 463 */ 464 bool pmap_initialized; 465 466 /* 467 * Misc. locking data structures 468 */ 469 470 #define pmap_acquire_pmap_lock(pm) \ 471 do { \ 472 if ((pm) != pmap_kernel()) \ 473 mutex_enter((pm)->pm_lock); \ 474 } while (/*CONSTCOND*/0) 475 476 #define pmap_release_pmap_lock(pm) \ 477 do { \ 478 if ((pm) != pmap_kernel()) \ 479 mutex_exit((pm)->pm_lock); \ 480 } while (/*CONSTCOND*/0) 481 482 483 /* 484 * Metadata for L1 translation tables. 485 */ 486 struct l1_ttable { 487 /* Entry on the L1 Table list */ 488 SLIST_ENTRY(l1_ttable) l1_link; 489 490 /* Entry on the L1 Least Recently Used list */ 491 TAILQ_ENTRY(l1_ttable) l1_lru; 492 493 /* Track how many domains are allocated from this L1 */ 494 volatile u_int l1_domain_use_count; 495 496 /* 497 * A free-list of domain numbers for this L1. 498 * We avoid using ffs() and a bitmap to track domains since ffs() 499 * is slow on ARM. 500 */ 501 u_int8_t l1_domain_first; 502 u_int8_t l1_domain_free[PMAP_DOMAINS]; 503 504 /* Physical address of this L1 page table */ 505 paddr_t l1_physaddr; 506 507 /* KVA of this L1 page table */ 508 pd_entry_t *l1_kva; 509 }; 510 511 /* 512 * Convert a virtual address into its L1 table index. That is, the 513 * index used to locate the L2 descriptor table pointer in an L1 table. 514 * This is basically used to index l1->l1_kva[]. 515 * 516 * Each L2 descriptor table represents 1MB of VA space. 517 */ 518 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 519 520 /* 521 * L1 Page Tables are tracked using a Least Recently Used list. 522 * - New L1s are allocated from the HEAD. 523 * - Freed L1s are added to the TAIl. 524 * - Recently accessed L1s (where an 'access' is some change to one of 525 * the userland pmaps which owns this L1) are moved to the TAIL. 526 */ 527 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 528 static kmutex_t l1_lru_lock __cacheline_aligned; 529 530 /* 531 * A list of all L1 tables 532 */ 533 static SLIST_HEAD(, l1_ttable) l1_list; 534 535 /* 536 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 537 * 538 * This is normally 16MB worth L2 page descriptors for any given pmap. 539 * Reference counts are maintained for L2 descriptors so they can be 540 * freed when empty. 541 */ 542 struct l2_dtable { 543 /* The number of L2 page descriptors allocated to this l2_dtable */ 544 u_int l2_occupancy; 545 546 /* List of L2 page descriptors */ 547 struct l2_bucket { 548 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 549 paddr_t l2b_phys; /* Physical address of same */ 550 u_short l2b_l1idx; /* This L2 table's L1 index */ 551 u_short l2b_occupancy; /* How many active descriptors */ 552 } l2_bucket[L2_BUCKET_SIZE]; 553 }; 554 555 /* 556 * Given an L1 table index, calculate the corresponding l2_dtable index 557 * and bucket index within the l2_dtable. 558 */ 559 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 560 (L2_SIZE - 1)) 561 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 562 563 /* 564 * Given a virtual address, this macro returns the 565 * virtual address required to drop into the next L2 bucket. 566 */ 567 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 568 569 /* 570 * L2 allocation. 571 */ 572 #define pmap_alloc_l2_dtable() \ 573 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 574 #define pmap_free_l2_dtable(l2) \ 575 pool_cache_put(&pmap_l2dtable_cache, (l2)) 576 #define pmap_alloc_l2_ptp(pap) \ 577 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 578 PR_NOWAIT, (pap))) 579 580 /* 581 * We try to map the page tables write-through, if possible. However, not 582 * all CPUs have a write-through cache mode, so on those we have to sync 583 * the cache when we frob page tables. 584 * 585 * We try to evaluate this at compile time, if possible. However, it's 586 * not always possible to do that, hence this run-time var. 587 */ 588 int pmap_needs_pte_sync; 589 590 /* 591 * Real definition of pv_entry. 592 */ 593 struct pv_entry { 594 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 595 pmap_t pv_pmap; /* pmap where mapping lies */ 596 vaddr_t pv_va; /* virtual address for mapping */ 597 u_int pv_flags; /* flags */ 598 }; 599 600 /* 601 * Macro to determine if a mapping might be resident in the 602 * instruction cache and/or TLB 603 */ 604 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 605 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 606 607 /* 608 * Macro to determine if a mapping might be resident in the 609 * data cache and/or TLB 610 */ 611 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 612 613 /* 614 * Local prototypes 615 */ 616 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 617 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 618 pt_entry_t **); 619 static bool pmap_is_current(pmap_t); 620 static bool pmap_is_cached(pmap_t); 621 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 622 pmap_t, vaddr_t, u_int); 623 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 624 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 625 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 626 u_int, u_int); 627 628 static void pmap_pinit(pmap_t); 629 static int pmap_pmap_ctor(void *, void *, int); 630 631 static void pmap_alloc_l1(pmap_t); 632 static void pmap_free_l1(pmap_t); 633 static void pmap_use_l1(pmap_t); 634 635 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 636 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 637 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 638 static int pmap_l2ptp_ctor(void *, void *, int); 639 static int pmap_l2dtable_ctor(void *, void *, int); 640 641 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 642 #ifdef PMAP_CACHE_VIVT 643 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 644 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 645 #endif 646 647 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 648 #ifdef PMAP_CACHE_VIVT 649 static int pmap_clean_page(struct pv_entry *, bool); 650 #endif 651 #ifdef PMAP_CACHE_VIPT 652 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 653 enum pmap_flush_op { 654 PMAP_FLUSH_PRIMARY, 655 PMAP_FLUSH_SECONDARY, 656 PMAP_CLEAN_PRIMARY 657 }; 658 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 659 #endif 660 static void pmap_page_remove(struct vm_page_md *, paddr_t); 661 662 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 663 static vaddr_t kernel_pt_lookup(paddr_t); 664 665 666 /* 667 * External function prototypes 668 */ 669 extern void bzero_page(vaddr_t); 670 extern void bcopy_page(vaddr_t, vaddr_t); 671 672 /* 673 * Misc variables 674 */ 675 vaddr_t virtual_avail; 676 vaddr_t virtual_end; 677 vaddr_t pmap_curmaxkvaddr; 678 679 paddr_t avail_start; 680 paddr_t avail_end; 681 682 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 683 pv_addr_t kernelpages; 684 pv_addr_t kernel_l1pt; 685 pv_addr_t systempage; 686 687 /* Function to set the debug level of the pmap code */ 688 689 #ifdef PMAP_DEBUG 690 void 691 pmap_debug(int level) 692 { 693 pmap_debug_level = level; 694 printf("pmap_debug: level=%d\n", pmap_debug_level); 695 } 696 #endif /* PMAP_DEBUG */ 697 698 /* 699 * A bunch of routines to conditionally flush the caches/TLB depending 700 * on whether the specified pmap actually needs to be flushed at any 701 * given time. 702 */ 703 static inline void 704 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 705 { 706 707 if (pm->pm_cstate.cs_tlb_id) 708 cpu_tlb_flushID_SE(va); 709 } 710 711 static inline void 712 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 713 { 714 715 if (pm->pm_cstate.cs_tlb_d) 716 cpu_tlb_flushD_SE(va); 717 } 718 719 static inline void 720 pmap_tlb_flushID(pmap_t pm) 721 { 722 723 if (pm->pm_cstate.cs_tlb_id) { 724 cpu_tlb_flushID(); 725 pm->pm_cstate.cs_tlb = 0; 726 } 727 } 728 729 static inline void 730 pmap_tlb_flushD(pmap_t pm) 731 { 732 733 if (pm->pm_cstate.cs_tlb_d) { 734 cpu_tlb_flushD(); 735 pm->pm_cstate.cs_tlb_d = 0; 736 } 737 } 738 739 #ifdef PMAP_CACHE_VIVT 740 static inline void 741 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 742 { 743 if (pm->pm_cstate.cs_cache_id) { 744 cpu_idcache_wbinv_range(va, len); 745 } 746 } 747 748 static inline void 749 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 750 bool do_inv, bool rd_only) 751 { 752 753 if (pm->pm_cstate.cs_cache_d) { 754 if (do_inv) { 755 if (rd_only) 756 cpu_dcache_inv_range(va, len); 757 else 758 cpu_dcache_wbinv_range(va, len); 759 } else 760 if (!rd_only) 761 cpu_dcache_wb_range(va, len); 762 } 763 } 764 765 static inline void 766 pmap_idcache_wbinv_all(pmap_t pm) 767 { 768 if (pm->pm_cstate.cs_cache_id) { 769 cpu_idcache_wbinv_all(); 770 pm->pm_cstate.cs_cache = 0; 771 } 772 } 773 774 static inline void 775 pmap_dcache_wbinv_all(pmap_t pm) 776 { 777 if (pm->pm_cstate.cs_cache_d) { 778 cpu_dcache_wbinv_all(); 779 pm->pm_cstate.cs_cache_d = 0; 780 } 781 } 782 #endif /* PMAP_CACHE_VIVT */ 783 784 static inline bool 785 pmap_is_current(pmap_t pm) 786 { 787 788 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 789 return true; 790 791 return false; 792 } 793 794 static inline bool 795 pmap_is_cached(pmap_t pm) 796 { 797 798 if (pm == pmap_kernel() || pmap_recent_user == NULL || 799 pmap_recent_user == pm) 800 return (true); 801 802 return false; 803 } 804 805 /* 806 * PTE_SYNC_CURRENT: 807 * 808 * Make sure the pte is written out to RAM. 809 * We need to do this for one of two cases: 810 * - We're dealing with the kernel pmap 811 * - There is no pmap active in the cache/tlb. 812 * - The specified pmap is 'active' in the cache/tlb. 813 */ 814 #ifdef PMAP_INCLUDE_PTE_SYNC 815 #define PTE_SYNC_CURRENT(pm, ptep) \ 816 do { \ 817 if (PMAP_NEEDS_PTE_SYNC && \ 818 pmap_is_cached(pm)) \ 819 PTE_SYNC(ptep); \ 820 } while (/*CONSTCOND*/0) 821 #else 822 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 823 #endif 824 825 /* 826 * main pv_entry manipulation functions: 827 * pmap_enter_pv: enter a mapping onto a vm_page list 828 * pmap_remove_pv: remove a mappiing from a vm_page list 829 * 830 * NOTE: pmap_enter_pv expects to lock the pvh itself 831 * pmap_remove_pv expects te caller to lock the pvh before calling 832 */ 833 834 /* 835 * pmap_enter_pv: enter a mapping onto a vm_page lst 836 * 837 * => caller should hold the proper lock on pmap_main_lock 838 * => caller should have pmap locked 839 * => we will gain the lock on the vm_page and allocate the new pv_entry 840 * => caller should adjust ptp's wire_count before calling 841 * => caller should not adjust pmap's wire_count 842 */ 843 static void 844 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 845 vaddr_t va, u_int flags) 846 { 847 struct pv_entry **pvp; 848 849 NPDEBUG(PDB_PVDUMP, 850 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 851 852 pv->pv_pmap = pm; 853 pv->pv_va = va; 854 pv->pv_flags = flags; 855 856 pvp = &SLIST_FIRST(&md->pvh_list); 857 #ifdef PMAP_CACHE_VIPT 858 /* 859 * Insert unmanaged entries, writeable first, at the head of 860 * the pv list. 861 */ 862 if (__predict_true((flags & PVF_KENTRY) == 0)) { 863 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 864 pvp = &SLIST_NEXT(*pvp, pv_link); 865 } else if ((flags & PVF_WRITE) == 0) { 866 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 867 pvp = &SLIST_NEXT(*pvp, pv_link); 868 } 869 #endif 870 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 871 *pvp = pv; /* ... locked list */ 872 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 873 #ifdef PMAP_CACHE_VIPT 874 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 875 md->pvh_attrs |= PVF_KMOD; 876 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 877 md->pvh_attrs |= PVF_DIRTY; 878 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 879 #endif 880 if (pm == pmap_kernel()) { 881 PMAPCOUNT(kernel_mappings); 882 if (flags & PVF_WRITE) 883 md->krw_mappings++; 884 else 885 md->kro_mappings++; 886 } else { 887 if (flags & PVF_WRITE) 888 md->urw_mappings++; 889 else 890 md->uro_mappings++; 891 } 892 893 #ifdef PMAP_CACHE_VIPT 894 /* 895 * If this is an exec mapping and its the first exec mapping 896 * for this page, make sure to sync the I-cache. 897 */ 898 if (PV_IS_EXEC_P(flags)) { 899 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 900 pmap_syncicache_page(md, pa); 901 PMAPCOUNT(exec_synced_map); 902 } 903 PMAPCOUNT(exec_mappings); 904 } 905 #endif 906 907 PMAPCOUNT(mappings); 908 909 if (pv->pv_flags & PVF_WIRED) 910 ++pm->pm_stats.wired_count; 911 } 912 913 /* 914 * 915 * pmap_find_pv: Find a pv entry 916 * 917 * => caller should hold lock on vm_page 918 */ 919 static inline struct pv_entry * 920 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 921 { 922 struct pv_entry *pv; 923 924 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 925 if (pm == pv->pv_pmap && va == pv->pv_va) 926 break; 927 } 928 929 return (pv); 930 } 931 932 /* 933 * pmap_remove_pv: try to remove a mapping from a pv_list 934 * 935 * => caller should hold proper lock on pmap_main_lock 936 * => pmap should be locked 937 * => caller should hold lock on vm_page [so that attrs can be adjusted] 938 * => caller should adjust ptp's wire_count and free PTP if needed 939 * => caller should NOT adjust pmap's wire_count 940 * => we return the removed pv 941 */ 942 static struct pv_entry * 943 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 944 { 945 struct pv_entry *pv, **prevptr; 946 947 NPDEBUG(PDB_PVDUMP, 948 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 949 950 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 951 pv = *prevptr; 952 953 while (pv) { 954 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 955 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 956 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 957 if (pv->pv_flags & PVF_WIRED) { 958 --pm->pm_stats.wired_count; 959 } 960 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 961 if (pm == pmap_kernel()) { 962 PMAPCOUNT(kernel_unmappings); 963 if (pv->pv_flags & PVF_WRITE) 964 md->krw_mappings--; 965 else 966 md->kro_mappings--; 967 } else { 968 if (pv->pv_flags & PVF_WRITE) 969 md->urw_mappings--; 970 else 971 md->uro_mappings--; 972 } 973 974 PMAPCOUNT(unmappings); 975 #ifdef PMAP_CACHE_VIPT 976 if (!(pv->pv_flags & PVF_WRITE)) 977 break; 978 /* 979 * If this page has had an exec mapping, then if 980 * this was the last mapping, discard the contents, 981 * otherwise sync the i-cache for this page. 982 */ 983 if (PV_IS_EXEC_P(md->pvh_attrs)) { 984 if (SLIST_EMPTY(&md->pvh_list)) { 985 md->pvh_attrs &= ~PVF_EXEC; 986 PMAPCOUNT(exec_discarded_unmap); 987 } else { 988 pmap_syncicache_page(md, pa); 989 PMAPCOUNT(exec_synced_unmap); 990 } 991 } 992 #endif /* PMAP_CACHE_VIPT */ 993 break; 994 } 995 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 996 pv = *prevptr; /* advance */ 997 } 998 999 #ifdef PMAP_CACHE_VIPT 1000 /* 1001 * If we no longer have a WRITEABLE KENTRY at the head of list, 1002 * clear the KMOD attribute from the page. 1003 */ 1004 if (SLIST_FIRST(&md->pvh_list) == NULL 1005 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1006 md->pvh_attrs &= ~PVF_KMOD; 1007 1008 /* 1009 * If this was a writeable page and there are no more writeable 1010 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1011 * the contents to memory. 1012 */ 1013 if (md->krw_mappings + md->urw_mappings == 0) 1014 md->pvh_attrs &= ~PVF_WRITE; 1015 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1016 #endif /* PMAP_CACHE_VIPT */ 1017 1018 return(pv); /* return removed pv */ 1019 } 1020 1021 /* 1022 * 1023 * pmap_modify_pv: Update pv flags 1024 * 1025 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1026 * => caller should NOT adjust pmap's wire_count 1027 * => caller must call pmap_vac_me_harder() if writable status of a page 1028 * may have changed. 1029 * => we return the old flags 1030 * 1031 * Modify a physical-virtual mapping in the pv table 1032 */ 1033 static u_int 1034 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1035 u_int clr_mask, u_int set_mask) 1036 { 1037 struct pv_entry *npv; 1038 u_int flags, oflags; 1039 1040 KASSERT((clr_mask & PVF_KENTRY) == 0); 1041 KASSERT((set_mask & PVF_KENTRY) == 0); 1042 1043 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1044 return (0); 1045 1046 NPDEBUG(PDB_PVDUMP, 1047 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1048 1049 /* 1050 * There is at least one VA mapping this page. 1051 */ 1052 1053 if (clr_mask & (PVF_REF | PVF_MOD)) { 1054 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1055 #ifdef PMAP_CACHE_VIPT 1056 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1057 md->pvh_attrs |= PVF_DIRTY; 1058 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1059 #endif 1060 } 1061 1062 oflags = npv->pv_flags; 1063 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1064 1065 if ((flags ^ oflags) & PVF_WIRED) { 1066 if (flags & PVF_WIRED) 1067 ++pm->pm_stats.wired_count; 1068 else 1069 --pm->pm_stats.wired_count; 1070 } 1071 1072 if ((flags ^ oflags) & PVF_WRITE) { 1073 if (pm == pmap_kernel()) { 1074 if (flags & PVF_WRITE) { 1075 md->krw_mappings++; 1076 md->kro_mappings--; 1077 } else { 1078 md->kro_mappings++; 1079 md->krw_mappings--; 1080 } 1081 } else { 1082 if (flags & PVF_WRITE) { 1083 md->urw_mappings++; 1084 md->uro_mappings--; 1085 } else { 1086 md->uro_mappings++; 1087 md->urw_mappings--; 1088 } 1089 } 1090 } 1091 #ifdef PMAP_CACHE_VIPT 1092 if (md->urw_mappings + md->krw_mappings == 0) 1093 md->pvh_attrs &= ~PVF_WRITE; 1094 /* 1095 * We have two cases here: the first is from enter_pv (new exec 1096 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1097 * Since in latter, pmap_enter_pv won't do anything, we just have 1098 * to do what pmap_remove_pv would do. 1099 */ 1100 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1101 || (PV_IS_EXEC_P(md->pvh_attrs) 1102 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1103 pmap_syncicache_page(md, pa); 1104 PMAPCOUNT(exec_synced_remap); 1105 } 1106 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1107 #endif 1108 1109 PMAPCOUNT(remappings); 1110 1111 return (oflags); 1112 } 1113 1114 /* 1115 * Allocate an L1 translation table for the specified pmap. 1116 * This is called at pmap creation time. 1117 */ 1118 static void 1119 pmap_alloc_l1(pmap_t pm) 1120 { 1121 struct l1_ttable *l1; 1122 u_int8_t domain; 1123 1124 /* 1125 * Remove the L1 at the head of the LRU list 1126 */ 1127 mutex_spin_enter(&l1_lru_lock); 1128 l1 = TAILQ_FIRST(&l1_lru_list); 1129 KDASSERT(l1 != NULL); 1130 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1131 1132 /* 1133 * Pick the first available domain number, and update 1134 * the link to the next number. 1135 */ 1136 domain = l1->l1_domain_first; 1137 l1->l1_domain_first = l1->l1_domain_free[domain]; 1138 1139 /* 1140 * If there are still free domain numbers in this L1, 1141 * put it back on the TAIL of the LRU list. 1142 */ 1143 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1144 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1145 1146 mutex_spin_exit(&l1_lru_lock); 1147 1148 /* 1149 * Fix up the relevant bits in the pmap structure 1150 */ 1151 pm->pm_l1 = l1; 1152 pm->pm_domain = domain + 1; 1153 } 1154 1155 /* 1156 * Free an L1 translation table. 1157 * This is called at pmap destruction time. 1158 */ 1159 static void 1160 pmap_free_l1(pmap_t pm) 1161 { 1162 struct l1_ttable *l1 = pm->pm_l1; 1163 1164 mutex_spin_enter(&l1_lru_lock); 1165 1166 /* 1167 * If this L1 is currently on the LRU list, remove it. 1168 */ 1169 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1170 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1171 1172 /* 1173 * Free up the domain number which was allocated to the pmap 1174 */ 1175 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first; 1176 l1->l1_domain_first = pm->pm_domain - 1; 1177 l1->l1_domain_use_count--; 1178 1179 /* 1180 * The L1 now must have at least 1 free domain, so add 1181 * it back to the LRU list. If the use count is zero, 1182 * put it at the head of the list, otherwise it goes 1183 * to the tail. 1184 */ 1185 if (l1->l1_domain_use_count == 0) 1186 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1187 else 1188 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1189 1190 mutex_spin_exit(&l1_lru_lock); 1191 } 1192 1193 static inline void 1194 pmap_use_l1(pmap_t pm) 1195 { 1196 struct l1_ttable *l1; 1197 1198 /* 1199 * Do nothing if we're in interrupt context. 1200 * Access to an L1 by the kernel pmap must not affect 1201 * the LRU list. 1202 */ 1203 if (cpu_intr_p() || pm == pmap_kernel()) 1204 return; 1205 1206 l1 = pm->pm_l1; 1207 1208 /* 1209 * If the L1 is not currently on the LRU list, just return 1210 */ 1211 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1212 return; 1213 1214 mutex_spin_enter(&l1_lru_lock); 1215 1216 /* 1217 * Check the use count again, now that we've acquired the lock 1218 */ 1219 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1220 mutex_spin_exit(&l1_lru_lock); 1221 return; 1222 } 1223 1224 /* 1225 * Move the L1 to the back of the LRU list 1226 */ 1227 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1228 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1229 1230 mutex_spin_exit(&l1_lru_lock); 1231 } 1232 1233 /* 1234 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1235 * 1236 * Free an L2 descriptor table. 1237 */ 1238 static inline void 1239 #ifndef PMAP_INCLUDE_PTE_SYNC 1240 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1241 #else 1242 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1243 #endif 1244 { 1245 #ifdef PMAP_INCLUDE_PTE_SYNC 1246 #ifdef PMAP_CACHE_VIVT 1247 /* 1248 * Note: With a write-back cache, we may need to sync this 1249 * L2 table before re-using it. 1250 * This is because it may have belonged to a non-current 1251 * pmap, in which case the cache syncs would have been 1252 * skipped for the pages that were being unmapped. If the 1253 * L2 table were then to be immediately re-allocated to 1254 * the *current* pmap, it may well contain stale mappings 1255 * which have not yet been cleared by a cache write-back 1256 * and so would still be visible to the mmu. 1257 */ 1258 if (need_sync) 1259 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1260 #endif /* PMAP_CACHE_VIVT */ 1261 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1262 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1263 } 1264 1265 /* 1266 * Returns a pointer to the L2 bucket associated with the specified pmap 1267 * and VA, or NULL if no L2 bucket exists for the address. 1268 */ 1269 static inline struct l2_bucket * 1270 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1271 { 1272 struct l2_dtable *l2; 1273 struct l2_bucket *l2b; 1274 u_short l1idx; 1275 1276 l1idx = L1_IDX(va); 1277 1278 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1279 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1280 return (NULL); 1281 1282 return (l2b); 1283 } 1284 1285 /* 1286 * Returns a pointer to the L2 bucket associated with the specified pmap 1287 * and VA. 1288 * 1289 * If no L2 bucket exists, perform the necessary allocations to put an L2 1290 * bucket/page table in place. 1291 * 1292 * Note that if a new L2 bucket/page was allocated, the caller *must* 1293 * increment the bucket occupancy counter appropriately *before* 1294 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1295 * the bucket/page in the meantime. 1296 */ 1297 static struct l2_bucket * 1298 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1299 { 1300 struct l2_dtable *l2; 1301 struct l2_bucket *l2b; 1302 u_short l1idx; 1303 1304 l1idx = L1_IDX(va); 1305 1306 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1307 /* 1308 * No mapping at this address, as there is 1309 * no entry in the L1 table. 1310 * Need to allocate a new l2_dtable. 1311 */ 1312 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1313 return (NULL); 1314 1315 /* 1316 * Link it into the parent pmap 1317 */ 1318 pm->pm_l2[L2_IDX(l1idx)] = l2; 1319 } 1320 1321 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1322 1323 /* 1324 * Fetch pointer to the L2 page table associated with the address. 1325 */ 1326 if (l2b->l2b_kva == NULL) { 1327 pt_entry_t *ptep; 1328 1329 /* 1330 * No L2 page table has been allocated. Chances are, this 1331 * is because we just allocated the l2_dtable, above. 1332 */ 1333 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1334 /* 1335 * Oops, no more L2 page tables available at this 1336 * time. We may need to deallocate the l2_dtable 1337 * if we allocated a new one above. 1338 */ 1339 if (l2->l2_occupancy == 0) { 1340 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1341 pmap_free_l2_dtable(l2); 1342 } 1343 return (NULL); 1344 } 1345 1346 l2->l2_occupancy++; 1347 l2b->l2b_kva = ptep; 1348 l2b->l2b_l1idx = l1idx; 1349 } 1350 1351 return (l2b); 1352 } 1353 1354 /* 1355 * One or more mappings in the specified L2 descriptor table have just been 1356 * invalidated. 1357 * 1358 * Garbage collect the metadata and descriptor table itself if necessary. 1359 * 1360 * The pmap lock must be acquired when this is called (not necessary 1361 * for the kernel pmap). 1362 */ 1363 static void 1364 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1365 { 1366 struct l2_dtable *l2; 1367 pd_entry_t *pl1pd, l1pd; 1368 pt_entry_t *ptep; 1369 u_short l1idx; 1370 1371 KDASSERT(count <= l2b->l2b_occupancy); 1372 1373 /* 1374 * Update the bucket's reference count according to how many 1375 * PTEs the caller has just invalidated. 1376 */ 1377 l2b->l2b_occupancy -= count; 1378 1379 /* 1380 * Note: 1381 * 1382 * Level 2 page tables allocated to the kernel pmap are never freed 1383 * as that would require checking all Level 1 page tables and 1384 * removing any references to the Level 2 page table. See also the 1385 * comment elsewhere about never freeing bootstrap L2 descriptors. 1386 * 1387 * We make do with just invalidating the mapping in the L2 table. 1388 * 1389 * This isn't really a big deal in practice and, in fact, leads 1390 * to a performance win over time as we don't need to continually 1391 * alloc/free. 1392 */ 1393 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1394 return; 1395 1396 /* 1397 * There are no more valid mappings in this level 2 page table. 1398 * Go ahead and NULL-out the pointer in the bucket, then 1399 * free the page table. 1400 */ 1401 l1idx = l2b->l2b_l1idx; 1402 ptep = l2b->l2b_kva; 1403 l2b->l2b_kva = NULL; 1404 1405 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1406 1407 /* 1408 * If the L1 slot matches the pmap's domain 1409 * number, then invalidate it. 1410 */ 1411 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1412 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1413 *pl1pd = 0; 1414 PTE_SYNC(pl1pd); 1415 } 1416 1417 /* 1418 * Release the L2 descriptor table back to the pool cache. 1419 */ 1420 #ifndef PMAP_INCLUDE_PTE_SYNC 1421 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1422 #else 1423 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1424 #endif 1425 1426 /* 1427 * Update the reference count in the associated l2_dtable 1428 */ 1429 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1430 if (--l2->l2_occupancy > 0) 1431 return; 1432 1433 /* 1434 * There are no more valid mappings in any of the Level 1 1435 * slots managed by this l2_dtable. Go ahead and NULL-out 1436 * the pointer in the parent pmap and free the l2_dtable. 1437 */ 1438 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1439 pmap_free_l2_dtable(l2); 1440 } 1441 1442 /* 1443 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1444 * structures. 1445 */ 1446 static int 1447 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1448 { 1449 #ifndef PMAP_INCLUDE_PTE_SYNC 1450 struct l2_bucket *l2b; 1451 pt_entry_t *ptep, pte; 1452 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1453 1454 /* 1455 * The mappings for these page tables were initially made using 1456 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1457 * mode will not be right for page table mappings. To avoid 1458 * polluting the pmap_kenter_pa() code with a special case for 1459 * page tables, we simply fix up the cache-mode here if it's not 1460 * correct. 1461 */ 1462 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1463 KDASSERT(l2b != NULL); 1464 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1465 pte = *ptep; 1466 1467 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1468 /* 1469 * Page tables must have the cache-mode set to Write-Thru. 1470 */ 1471 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1472 PTE_SYNC(ptep); 1473 cpu_tlb_flushD_SE(va); 1474 cpu_cpwait(); 1475 } 1476 #endif 1477 1478 memset(v, 0, L2_TABLE_SIZE_REAL); 1479 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1480 return (0); 1481 } 1482 1483 static int 1484 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1485 { 1486 1487 memset(v, 0, sizeof(struct l2_dtable)); 1488 return (0); 1489 } 1490 1491 static int 1492 pmap_pmap_ctor(void *arg, void *v, int flags) 1493 { 1494 1495 memset(v, 0, sizeof(struct pmap)); 1496 return (0); 1497 } 1498 1499 static void 1500 pmap_pinit(pmap_t pm) 1501 { 1502 struct l2_bucket *l2b; 1503 1504 if (vector_page < KERNEL_BASE) { 1505 /* 1506 * Map the vector page. 1507 */ 1508 pmap_enter(pm, vector_page, systempage.pv_pa, 1509 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1510 pmap_update(pm); 1511 1512 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1513 l2b = pmap_get_l2_bucket(pm, vector_page); 1514 KDASSERT(l2b != NULL); 1515 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1516 L1_C_DOM(pm->pm_domain); 1517 } else 1518 pm->pm_pl1vec = NULL; 1519 } 1520 1521 #ifdef PMAP_CACHE_VIVT 1522 /* 1523 * Since we have a virtually indexed cache, we may need to inhibit caching if 1524 * there is more than one mapping and at least one of them is writable. 1525 * Since we purge the cache on every context switch, we only need to check for 1526 * other mappings within the same pmap, or kernel_pmap. 1527 * This function is also called when a page is unmapped, to possibly reenable 1528 * caching on any remaining mappings. 1529 * 1530 * The code implements the following logic, where: 1531 * 1532 * KW = # of kernel read/write pages 1533 * KR = # of kernel read only pages 1534 * UW = # of user read/write pages 1535 * UR = # of user read only pages 1536 * 1537 * KC = kernel mapping is cacheable 1538 * UC = user mapping is cacheable 1539 * 1540 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1541 * +--------------------------------------------- 1542 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1543 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1544 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1545 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1546 */ 1547 1548 static const int pmap_vac_flags[4][4] = { 1549 {-1, 0, 0, PVF_KNC}, 1550 {0, 0, PVF_NC, PVF_NC}, 1551 {0, PVF_NC, PVF_NC, PVF_NC}, 1552 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1553 }; 1554 1555 static inline int 1556 pmap_get_vac_flags(const struct vm_page_md *md) 1557 { 1558 int kidx, uidx; 1559 1560 kidx = 0; 1561 if (md->kro_mappings || md->krw_mappings > 1) 1562 kidx |= 1; 1563 if (md->krw_mappings) 1564 kidx |= 2; 1565 1566 uidx = 0; 1567 if (md->uro_mappings || md->urw_mappings > 1) 1568 uidx |= 1; 1569 if (md->urw_mappings) 1570 uidx |= 2; 1571 1572 return (pmap_vac_flags[uidx][kidx]); 1573 } 1574 1575 static inline void 1576 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1577 { 1578 int nattr; 1579 1580 nattr = pmap_get_vac_flags(md); 1581 1582 if (nattr < 0) { 1583 md->pvh_attrs &= ~PVF_NC; 1584 return; 1585 } 1586 1587 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1588 return; 1589 1590 if (pm == pmap_kernel()) 1591 pmap_vac_me_kpmap(md, pa, pm, va); 1592 else 1593 pmap_vac_me_user(md, pa, pm, va); 1594 1595 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1596 } 1597 1598 static void 1599 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1600 { 1601 u_int u_cacheable, u_entries; 1602 struct pv_entry *pv; 1603 pmap_t last_pmap = pm; 1604 1605 /* 1606 * Pass one, see if there are both kernel and user pmaps for 1607 * this page. Calculate whether there are user-writable or 1608 * kernel-writable pages. 1609 */ 1610 u_cacheable = 0; 1611 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1612 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1613 u_cacheable++; 1614 } 1615 1616 u_entries = md->urw_mappings + md->uro_mappings; 1617 1618 /* 1619 * We know we have just been updating a kernel entry, so if 1620 * all user pages are already cacheable, then there is nothing 1621 * further to do. 1622 */ 1623 if (md->k_mappings == 0 && u_cacheable == u_entries) 1624 return; 1625 1626 if (u_entries) { 1627 /* 1628 * Scan over the list again, for each entry, if it 1629 * might not be set correctly, call pmap_vac_me_user 1630 * to recalculate the settings. 1631 */ 1632 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1633 /* 1634 * We know kernel mappings will get set 1635 * correctly in other calls. We also know 1636 * that if the pmap is the same as last_pmap 1637 * then we've just handled this entry. 1638 */ 1639 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1640 continue; 1641 1642 /* 1643 * If there are kernel entries and this page 1644 * is writable but non-cacheable, then we can 1645 * skip this entry also. 1646 */ 1647 if (md->k_mappings && 1648 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1649 (PVF_NC | PVF_WRITE)) 1650 continue; 1651 1652 /* 1653 * Similarly if there are no kernel-writable 1654 * entries and the page is already 1655 * read-only/cacheable. 1656 */ 1657 if (md->krw_mappings == 0 && 1658 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1659 continue; 1660 1661 /* 1662 * For some of the remaining cases, we know 1663 * that we must recalculate, but for others we 1664 * can't tell if they are correct or not, so 1665 * we recalculate anyway. 1666 */ 1667 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1668 } 1669 1670 if (md->k_mappings == 0) 1671 return; 1672 } 1673 1674 pmap_vac_me_user(md, pa, pm, va); 1675 } 1676 1677 static void 1678 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1679 { 1680 pmap_t kpmap = pmap_kernel(); 1681 struct pv_entry *pv, *npv = NULL; 1682 struct l2_bucket *l2b; 1683 pt_entry_t *ptep, pte; 1684 u_int entries = 0; 1685 u_int writable = 0; 1686 u_int cacheable_entries = 0; 1687 u_int kern_cacheable = 0; 1688 u_int other_writable = 0; 1689 1690 /* 1691 * Count mappings and writable mappings in this pmap. 1692 * Include kernel mappings as part of our own. 1693 * Keep a pointer to the first one. 1694 */ 1695 npv = NULL; 1696 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1697 /* Count mappings in the same pmap */ 1698 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1699 if (entries++ == 0) 1700 npv = pv; 1701 1702 /* Cacheable mappings */ 1703 if ((pv->pv_flags & PVF_NC) == 0) { 1704 cacheable_entries++; 1705 if (kpmap == pv->pv_pmap) 1706 kern_cacheable++; 1707 } 1708 1709 /* Writable mappings */ 1710 if (pv->pv_flags & PVF_WRITE) 1711 ++writable; 1712 } else 1713 if (pv->pv_flags & PVF_WRITE) 1714 other_writable = 1; 1715 } 1716 1717 /* 1718 * Enable or disable caching as necessary. 1719 * Note: the first entry might be part of the kernel pmap, 1720 * so we can't assume this is indicative of the state of the 1721 * other (maybe non-kpmap) entries. 1722 */ 1723 if ((entries > 1 && writable) || 1724 (entries > 0 && pm == kpmap && other_writable)) { 1725 if (cacheable_entries == 0) 1726 return; 1727 1728 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1729 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1730 (pv->pv_flags & PVF_NC)) 1731 continue; 1732 1733 pv->pv_flags |= PVF_NC; 1734 1735 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1736 KDASSERT(l2b != NULL); 1737 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1738 pte = *ptep & ~L2_S_CACHE_MASK; 1739 1740 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1741 l2pte_valid(pte)) { 1742 if (PV_BEEN_EXECD(pv->pv_flags)) { 1743 #ifdef PMAP_CACHE_VIVT 1744 pmap_idcache_wbinv_range(pv->pv_pmap, 1745 pv->pv_va, PAGE_SIZE); 1746 #endif 1747 pmap_tlb_flushID_SE(pv->pv_pmap, 1748 pv->pv_va); 1749 } else 1750 if (PV_BEEN_REFD(pv->pv_flags)) { 1751 #ifdef PMAP_CACHE_VIVT 1752 pmap_dcache_wb_range(pv->pv_pmap, 1753 pv->pv_va, PAGE_SIZE, true, 1754 (pv->pv_flags & PVF_WRITE) == 0); 1755 #endif 1756 pmap_tlb_flushD_SE(pv->pv_pmap, 1757 pv->pv_va); 1758 } 1759 } 1760 1761 *ptep = pte; 1762 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1763 } 1764 cpu_cpwait(); 1765 } else 1766 if (entries > cacheable_entries) { 1767 /* 1768 * Turn cacheing back on for some pages. If it is a kernel 1769 * page, only do so if there are no other writable pages. 1770 */ 1771 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1772 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1773 (kpmap != pv->pv_pmap || other_writable))) 1774 continue; 1775 1776 pv->pv_flags &= ~PVF_NC; 1777 1778 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1779 KDASSERT(l2b != NULL); 1780 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1781 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1782 1783 if (l2pte_valid(pte)) { 1784 if (PV_BEEN_EXECD(pv->pv_flags)) { 1785 pmap_tlb_flushID_SE(pv->pv_pmap, 1786 pv->pv_va); 1787 } else 1788 if (PV_BEEN_REFD(pv->pv_flags)) { 1789 pmap_tlb_flushD_SE(pv->pv_pmap, 1790 pv->pv_va); 1791 } 1792 } 1793 1794 *ptep = pte; 1795 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1796 } 1797 } 1798 } 1799 #endif 1800 1801 #ifdef PMAP_CACHE_VIPT 1802 static void 1803 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1804 { 1805 struct pv_entry *pv; 1806 vaddr_t tst_mask; 1807 bool bad_alias; 1808 struct l2_bucket *l2b; 1809 pt_entry_t *ptep, pte, opte; 1810 const u_int 1811 rw_mappings = md->urw_mappings + md->krw_mappings, 1812 ro_mappings = md->uro_mappings + md->kro_mappings; 1813 1814 /* do we need to do anything? */ 1815 if (arm_cache_prefer_mask == 0) 1816 return; 1817 1818 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1819 md, pm, va)); 1820 1821 KASSERT(!va || pm); 1822 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1823 1824 /* Already a conflict? */ 1825 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1826 /* just an add, things are already non-cached */ 1827 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1828 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1829 bad_alias = false; 1830 if (va) { 1831 PMAPCOUNT(vac_color_none); 1832 bad_alias = true; 1833 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1834 goto fixup; 1835 } 1836 pv = SLIST_FIRST(&md->pvh_list); 1837 /* the list can't be empty because it would be cachable */ 1838 if (md->pvh_attrs & PVF_KMPAGE) { 1839 tst_mask = md->pvh_attrs; 1840 } else { 1841 KASSERT(pv); 1842 tst_mask = pv->pv_va; 1843 pv = SLIST_NEXT(pv, pv_link); 1844 } 1845 /* 1846 * Only check for a bad alias if we have writable mappings. 1847 */ 1848 tst_mask &= arm_cache_prefer_mask; 1849 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1850 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1851 /* if there's a bad alias, stop checking. */ 1852 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1853 bad_alias = true; 1854 } 1855 md->pvh_attrs |= PVF_WRITE; 1856 if (!bad_alias) 1857 md->pvh_attrs |= PVF_DIRTY; 1858 } else { 1859 /* 1860 * We have only read-only mappings. Let's see if there 1861 * are multiple colors in use or if we mapped a KMPAGE. 1862 * If the latter, we have a bad alias. If the former, 1863 * we need to remember that. 1864 */ 1865 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1866 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1867 if (md->pvh_attrs & PVF_KMPAGE) 1868 bad_alias = true; 1869 break; 1870 } 1871 } 1872 md->pvh_attrs &= ~PVF_WRITE; 1873 /* 1874 * No KMPAGE and we exited early, so we must have 1875 * multiple color mappings. 1876 */ 1877 if (!bad_alias && pv != NULL) 1878 md->pvh_attrs |= PVF_MULTCLR; 1879 } 1880 1881 /* If no conflicting colors, set everything back to cached */ 1882 if (!bad_alias) { 1883 #ifdef DEBUG 1884 if ((md->pvh_attrs & PVF_WRITE) 1885 || ro_mappings < 2) { 1886 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1887 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1888 } 1889 #endif 1890 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1891 md->pvh_attrs |= tst_mask | PVF_COLORED; 1892 /* 1893 * Restore DIRTY bit if page is modified 1894 */ 1895 if (md->pvh_attrs & PVF_DMOD) 1896 md->pvh_attrs |= PVF_DIRTY; 1897 PMAPCOUNT(vac_color_restore); 1898 } else { 1899 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1900 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1901 } 1902 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1903 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1904 } else if (!va) { 1905 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1906 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1907 || (md->pvh_attrs & PVF_DIRTY)); 1908 if (rw_mappings == 0) { 1909 md->pvh_attrs &= ~PVF_WRITE; 1910 if (ro_mappings == 1 1911 && (md->pvh_attrs & PVF_MULTCLR)) { 1912 /* 1913 * If this is the last readonly mapping 1914 * but it doesn't match the current color 1915 * for the page, change the current color 1916 * to match this last readonly mapping. 1917 */ 1918 pv = SLIST_FIRST(&md->pvh_list); 1919 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1920 & arm_cache_prefer_mask; 1921 if (tst_mask) { 1922 md->pvh_attrs ^= tst_mask; 1923 PMAPCOUNT(vac_color_change); 1924 } 1925 } 1926 } 1927 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1928 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1929 return; 1930 } else if (!pmap_is_page_colored_p(md)) { 1931 /* not colored so we just use its color */ 1932 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1933 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1934 PMAPCOUNT(vac_color_new); 1935 md->pvh_attrs &= PAGE_SIZE - 1; 1936 md->pvh_attrs |= PVF_COLORED 1937 | (va & arm_cache_prefer_mask) 1938 | (rw_mappings > 0 ? PVF_WRITE : 0); 1939 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1940 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1941 return; 1942 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1943 bad_alias = false; 1944 if (rw_mappings > 0) { 1945 /* 1946 * We now have writeable mappings and if we have 1947 * readonly mappings in more than once color, we have 1948 * an aliasing problem. Regardless mark the page as 1949 * writeable. 1950 */ 1951 if (md->pvh_attrs & PVF_MULTCLR) { 1952 if (ro_mappings < 2) { 1953 /* 1954 * If we only have less than two 1955 * read-only mappings, just flush the 1956 * non-primary colors from the cache. 1957 */ 1958 pmap_flush_page(md, pa, 1959 PMAP_FLUSH_SECONDARY); 1960 } else { 1961 bad_alias = true; 1962 } 1963 } 1964 md->pvh_attrs |= PVF_WRITE; 1965 } 1966 /* If no conflicting colors, set everything back to cached */ 1967 if (!bad_alias) { 1968 #ifdef DEBUG 1969 if (rw_mappings > 0 1970 || (md->pvh_attrs & PMAP_KMPAGE)) { 1971 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1972 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1973 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1974 } 1975 #endif 1976 if (SLIST_EMPTY(&md->pvh_list)) 1977 PMAPCOUNT(vac_color_reuse); 1978 else 1979 PMAPCOUNT(vac_color_ok); 1980 1981 /* matching color, just return */ 1982 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1983 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1984 return; 1985 } 1986 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1987 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1988 1989 /* color conflict. evict from cache. */ 1990 1991 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 1992 md->pvh_attrs &= ~PVF_COLORED; 1993 md->pvh_attrs |= PVF_NC; 1994 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1995 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1996 PMAPCOUNT(vac_color_erase); 1997 } else if (rw_mappings == 0 1998 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 1999 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2000 2001 /* 2002 * If the page has dirty cache lines, clean it. 2003 */ 2004 if (md->pvh_attrs & PVF_DIRTY) 2005 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2006 2007 /* 2008 * If this is the first remapping (we know that there are no 2009 * writeable mappings), then this is a simple color change. 2010 * Otherwise this is a seconary r/o mapping, which means 2011 * we don't have to do anything. 2012 */ 2013 if (ro_mappings == 1) { 2014 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2015 md->pvh_attrs &= PAGE_SIZE - 1; 2016 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2017 PMAPCOUNT(vac_color_change); 2018 } else { 2019 PMAPCOUNT(vac_color_blind); 2020 } 2021 md->pvh_attrs |= PVF_MULTCLR; 2022 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2023 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2024 return; 2025 } else { 2026 if (rw_mappings > 0) 2027 md->pvh_attrs |= PVF_WRITE; 2028 2029 /* color conflict. evict from cache. */ 2030 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2031 2032 /* the list can't be empty because this was a enter/modify */ 2033 pv = SLIST_FIRST(&md->pvh_list); 2034 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2035 KASSERT(pv); 2036 /* 2037 * If there's only one mapped page, change color to the 2038 * page's new color and return. Restore the DIRTY bit 2039 * that was erased by pmap_flush_page. 2040 */ 2041 if (SLIST_NEXT(pv, pv_link) == NULL) { 2042 md->pvh_attrs &= PAGE_SIZE - 1; 2043 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2044 if (md->pvh_attrs & PVF_DMOD) 2045 md->pvh_attrs |= PVF_DIRTY; 2046 PMAPCOUNT(vac_color_change); 2047 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2048 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2049 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2050 return; 2051 } 2052 } 2053 bad_alias = true; 2054 md->pvh_attrs &= ~PVF_COLORED; 2055 md->pvh_attrs |= PVF_NC; 2056 PMAPCOUNT(vac_color_erase); 2057 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2058 } 2059 2060 fixup: 2061 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2062 2063 /* 2064 * Turn cacheing on/off for all pages. 2065 */ 2066 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2067 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2068 KDASSERT(l2b != NULL); 2069 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2070 opte = *ptep; 2071 pte = opte & ~L2_S_CACHE_MASK; 2072 if (bad_alias) { 2073 pv->pv_flags |= PVF_NC; 2074 } else { 2075 pv->pv_flags &= ~PVF_NC; 2076 pte |= pte_l2_s_cache_mode; 2077 } 2078 2079 if (opte == pte) /* only update is there's a change */ 2080 continue; 2081 2082 if (l2pte_valid(pte)) { 2083 if (PV_BEEN_EXECD(pv->pv_flags)) { 2084 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2085 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2086 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2087 } 2088 } 2089 2090 *ptep = pte; 2091 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2092 } 2093 } 2094 #endif /* PMAP_CACHE_VIPT */ 2095 2096 2097 /* 2098 * Modify pte bits for all ptes corresponding to the given physical address. 2099 * We use `maskbits' rather than `clearbits' because we're always passing 2100 * constants and the latter would require an extra inversion at run-time. 2101 */ 2102 static void 2103 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2104 { 2105 struct l2_bucket *l2b; 2106 struct pv_entry *pv; 2107 pt_entry_t *ptep, npte, opte; 2108 pmap_t pm; 2109 vaddr_t va; 2110 u_int oflags; 2111 #ifdef PMAP_CACHE_VIPT 2112 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2113 bool need_syncicache = false; 2114 bool did_syncicache = false; 2115 bool need_vac_me_harder = false; 2116 #endif 2117 2118 NPDEBUG(PDB_BITS, 2119 printf("pmap_clearbit: md %p mask 0x%x\n", 2120 md, maskbits)); 2121 2122 #ifdef PMAP_CACHE_VIPT 2123 /* 2124 * If we might want to sync the I-cache and we've modified it, 2125 * then we know we definitely need to sync or discard it. 2126 */ 2127 if (want_syncicache) 2128 need_syncicache = md->pvh_attrs & PVF_MOD; 2129 #endif 2130 /* 2131 * Clear saved attributes (modify, reference) 2132 */ 2133 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2134 2135 if (SLIST_EMPTY(&md->pvh_list)) { 2136 #ifdef PMAP_CACHE_VIPT 2137 if (need_syncicache) { 2138 /* 2139 * No one has it mapped, so just discard it. The next 2140 * exec remapping will cause it to be synced. 2141 */ 2142 md->pvh_attrs &= ~PVF_EXEC; 2143 PMAPCOUNT(exec_discarded_clearbit); 2144 } 2145 #endif 2146 return; 2147 } 2148 2149 /* 2150 * Loop over all current mappings setting/clearing as appropos 2151 */ 2152 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2153 va = pv->pv_va; 2154 pm = pv->pv_pmap; 2155 oflags = pv->pv_flags; 2156 /* 2157 * Kernel entries are unmanaged and as such not to be changed. 2158 */ 2159 if (oflags & PVF_KENTRY) 2160 continue; 2161 pv->pv_flags &= ~maskbits; 2162 2163 pmap_acquire_pmap_lock(pm); 2164 2165 l2b = pmap_get_l2_bucket(pm, va); 2166 KDASSERT(l2b != NULL); 2167 2168 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2169 npte = opte = *ptep; 2170 2171 NPDEBUG(PDB_BITS, 2172 printf( 2173 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2174 pv, pv->pv_pmap, pv->pv_va, oflags)); 2175 2176 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2177 #ifdef PMAP_CACHE_VIVT 2178 if ((pv->pv_flags & PVF_NC)) { 2179 /* 2180 * Entry is not cacheable: 2181 * 2182 * Don't turn caching on again if this is a 2183 * modified emulation. This would be 2184 * inconsitent with the settings created by 2185 * pmap_vac_me_harder(). Otherwise, it's safe 2186 * to re-enable cacheing. 2187 * 2188 * There's no need to call pmap_vac_me_harder() 2189 * here: all pages are losing their write 2190 * permission. 2191 */ 2192 if (maskbits & PVF_WRITE) { 2193 npte |= pte_l2_s_cache_mode; 2194 pv->pv_flags &= ~PVF_NC; 2195 } 2196 } else 2197 if (l2pte_writable_p(opte)) { 2198 /* 2199 * Entry is writable/cacheable: check if pmap 2200 * is current if it is flush it, otherwise it 2201 * won't be in the cache 2202 */ 2203 if (PV_BEEN_EXECD(oflags)) 2204 pmap_idcache_wbinv_range(pm, pv->pv_va, 2205 PAGE_SIZE); 2206 else 2207 if (PV_BEEN_REFD(oflags)) 2208 pmap_dcache_wb_range(pm, pv->pv_va, 2209 PAGE_SIZE, 2210 (maskbits & PVF_REF) != 0, false); 2211 } 2212 #endif 2213 2214 /* make the pte read only */ 2215 npte = l2pte_set_readonly(npte); 2216 2217 if (maskbits & oflags & PVF_WRITE) { 2218 /* 2219 * Keep alias accounting up to date 2220 */ 2221 if (pv->pv_pmap == pmap_kernel()) { 2222 md->krw_mappings--; 2223 md->kro_mappings++; 2224 } else { 2225 md->urw_mappings--; 2226 md->uro_mappings++; 2227 } 2228 #ifdef PMAP_CACHE_VIPT 2229 if (md->urw_mappings + md->krw_mappings == 0) 2230 md->pvh_attrs &= ~PVF_WRITE; 2231 if (want_syncicache) 2232 need_syncicache = true; 2233 need_vac_me_harder = true; 2234 #endif 2235 } 2236 } 2237 2238 if (maskbits & PVF_REF) { 2239 if ((pv->pv_flags & PVF_NC) == 0 && 2240 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2241 l2pte_valid(npte)) { 2242 #ifdef PMAP_CACHE_VIVT 2243 /* 2244 * Check npte here; we may have already 2245 * done the wbinv above, and the validity 2246 * of the PTE is the same for opte and 2247 * npte. 2248 */ 2249 /* XXXJRT need idcache_inv_range */ 2250 if (PV_BEEN_EXECD(oflags)) 2251 pmap_idcache_wbinv_range(pm, 2252 pv->pv_va, PAGE_SIZE); 2253 else 2254 if (PV_BEEN_REFD(oflags)) 2255 pmap_dcache_wb_range(pm, 2256 pv->pv_va, PAGE_SIZE, 2257 true, true); 2258 #endif 2259 } 2260 2261 /* 2262 * Make the PTE invalid so that we will take a 2263 * page fault the next time the mapping is 2264 * referenced. 2265 */ 2266 npte &= ~L2_TYPE_MASK; 2267 npte |= L2_TYPE_INV; 2268 } 2269 2270 if (npte != opte) { 2271 *ptep = npte; 2272 PTE_SYNC(ptep); 2273 /* Flush the TLB entry if a current pmap. */ 2274 if (PV_BEEN_EXECD(oflags)) 2275 pmap_tlb_flushID_SE(pm, pv->pv_va); 2276 else 2277 if (PV_BEEN_REFD(oflags)) 2278 pmap_tlb_flushD_SE(pm, pv->pv_va); 2279 } 2280 2281 pmap_release_pmap_lock(pm); 2282 2283 NPDEBUG(PDB_BITS, 2284 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2285 pm, va, opte, npte)); 2286 } 2287 2288 #ifdef PMAP_CACHE_VIPT 2289 /* 2290 * If we need to sync the I-cache and we haven't done it yet, do it. 2291 */ 2292 if (need_syncicache && !did_syncicache) { 2293 pmap_syncicache_page(md, pa); 2294 PMAPCOUNT(exec_synced_clearbit); 2295 } 2296 /* 2297 * If we are changing this to read-only, we need to call vac_me_harder 2298 * so we can change all the read-only pages to cacheable. We pretend 2299 * this as a page deletion. 2300 */ 2301 if (need_vac_me_harder) { 2302 if (md->pvh_attrs & PVF_NC) 2303 pmap_vac_me_harder(md, pa, NULL, 0); 2304 } 2305 #endif 2306 } 2307 2308 /* 2309 * pmap_clean_page() 2310 * 2311 * This is a local function used to work out the best strategy to clean 2312 * a single page referenced by its entry in the PV table. It's used by 2313 * pmap_copy_page, pmap_zero page and maybe some others later on. 2314 * 2315 * Its policy is effectively: 2316 * o If there are no mappings, we don't bother doing anything with the cache. 2317 * o If there is one mapping, we clean just that page. 2318 * o If there are multiple mappings, we clean the entire cache. 2319 * 2320 * So that some functions can be further optimised, it returns 0 if it didn't 2321 * clean the entire cache, or 1 if it did. 2322 * 2323 * XXX One bug in this routine is that if the pv_entry has a single page 2324 * mapped at 0x00000000 a whole cache clean will be performed rather than 2325 * just the 1 page. Since this should not occur in everyday use and if it does 2326 * it will just result in not the most efficient clean for the page. 2327 */ 2328 #ifdef PMAP_CACHE_VIVT 2329 static int 2330 pmap_clean_page(struct pv_entry *pv, bool is_src) 2331 { 2332 pmap_t pm_to_clean = NULL; 2333 struct pv_entry *npv; 2334 u_int cache_needs_cleaning = 0; 2335 u_int flags = 0; 2336 vaddr_t page_to_clean = 0; 2337 2338 if (pv == NULL) { 2339 /* nothing mapped in so nothing to flush */ 2340 return (0); 2341 } 2342 2343 /* 2344 * Since we flush the cache each time we change to a different 2345 * user vmspace, we only need to flush the page if it is in the 2346 * current pmap. 2347 */ 2348 2349 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2350 if (pmap_is_current(npv->pv_pmap)) { 2351 flags |= npv->pv_flags; 2352 /* 2353 * The page is mapped non-cacheable in 2354 * this map. No need to flush the cache. 2355 */ 2356 if (npv->pv_flags & PVF_NC) { 2357 #ifdef DIAGNOSTIC 2358 if (cache_needs_cleaning) 2359 panic("pmap_clean_page: " 2360 "cache inconsistency"); 2361 #endif 2362 break; 2363 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2364 continue; 2365 if (cache_needs_cleaning) { 2366 page_to_clean = 0; 2367 break; 2368 } else { 2369 page_to_clean = npv->pv_va; 2370 pm_to_clean = npv->pv_pmap; 2371 } 2372 cache_needs_cleaning = 1; 2373 } 2374 } 2375 2376 if (page_to_clean) { 2377 if (PV_BEEN_EXECD(flags)) 2378 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2379 PAGE_SIZE); 2380 else 2381 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2382 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2383 } else if (cache_needs_cleaning) { 2384 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2385 2386 if (PV_BEEN_EXECD(flags)) 2387 pmap_idcache_wbinv_all(pm); 2388 else 2389 pmap_dcache_wbinv_all(pm); 2390 return (1); 2391 } 2392 return (0); 2393 } 2394 #endif 2395 2396 #ifdef PMAP_CACHE_VIPT 2397 /* 2398 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2399 * right cache alias to make sure we flush the right stuff. 2400 */ 2401 void 2402 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2403 { 2404 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2405 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2406 2407 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2408 md, md->pvh_attrs)); 2409 /* 2410 * No need to clean the page if it's non-cached. 2411 */ 2412 if (md->pvh_attrs & PVF_NC) 2413 return; 2414 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2415 2416 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2417 /* 2418 * Set up a PTE with the right coloring to flush existing cache lines. 2419 */ 2420 *ptep = L2_S_PROTO | 2421 pa 2422 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2423 | pte_l2_s_cache_mode; 2424 PTE_SYNC(ptep); 2425 2426 /* 2427 * Flush it. 2428 */ 2429 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2430 /* 2431 * Unmap the page. 2432 */ 2433 *ptep = 0; 2434 PTE_SYNC(ptep); 2435 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2436 2437 md->pvh_attrs |= PVF_EXEC; 2438 PMAPCOUNT(exec_synced); 2439 } 2440 2441 void 2442 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2443 { 2444 vsize_t va_offset, end_va; 2445 void (*cf)(vaddr_t, vsize_t); 2446 2447 if (arm_cache_prefer_mask == 0) 2448 return; 2449 2450 switch (flush) { 2451 case PMAP_FLUSH_PRIMARY: 2452 if (md->pvh_attrs & PVF_MULTCLR) { 2453 va_offset = 0; 2454 end_va = arm_cache_prefer_mask; 2455 md->pvh_attrs &= ~PVF_MULTCLR; 2456 PMAPCOUNT(vac_flush_lots); 2457 } else { 2458 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2459 end_va = va_offset; 2460 PMAPCOUNT(vac_flush_one); 2461 } 2462 /* 2463 * Mark that the page is no longer dirty. 2464 */ 2465 md->pvh_attrs &= ~PVF_DIRTY; 2466 cf = cpufuncs.cf_idcache_wbinv_range; 2467 break; 2468 case PMAP_FLUSH_SECONDARY: 2469 va_offset = 0; 2470 end_va = arm_cache_prefer_mask; 2471 cf = cpufuncs.cf_idcache_wbinv_range; 2472 md->pvh_attrs &= ~PVF_MULTCLR; 2473 PMAPCOUNT(vac_flush_lots); 2474 break; 2475 case PMAP_CLEAN_PRIMARY: 2476 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2477 end_va = va_offset; 2478 cf = cpufuncs.cf_dcache_wb_range; 2479 /* 2480 * Mark that the page is no longer dirty. 2481 */ 2482 if ((md->pvh_attrs & PVF_DMOD) == 0) 2483 md->pvh_attrs &= ~PVF_DIRTY; 2484 PMAPCOUNT(vac_clean_one); 2485 break; 2486 default: 2487 return; 2488 } 2489 2490 KASSERT(!(md->pvh_attrs & PVF_NC)); 2491 2492 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2493 md, md->pvh_attrs)); 2494 2495 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2496 const size_t pte_offset = va_offset >> PGSHIFT; 2497 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2498 const pt_entry_t oldpte = *ptep; 2499 2500 if (flush == PMAP_FLUSH_SECONDARY 2501 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2502 continue; 2503 2504 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2505 /* 2506 * Set up a PTE with the right coloring to flush 2507 * existing cache entries. 2508 */ 2509 *ptep = L2_S_PROTO 2510 | pa 2511 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2512 | pte_l2_s_cache_mode; 2513 PTE_SYNC(ptep); 2514 2515 /* 2516 * Flush it. 2517 */ 2518 (*cf)(cdstp + va_offset, PAGE_SIZE); 2519 2520 /* 2521 * Restore the page table entry since we might have interrupted 2522 * pmap_zero_page or pmap_copy_page which was already using 2523 * this pte. 2524 */ 2525 *ptep = oldpte; 2526 PTE_SYNC(ptep); 2527 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2528 } 2529 } 2530 #endif /* PMAP_CACHE_VIPT */ 2531 2532 /* 2533 * Routine: pmap_page_remove 2534 * Function: 2535 * Removes this physical page from 2536 * all physical maps in which it resides. 2537 * Reflects back modify bits to the pager. 2538 */ 2539 static void 2540 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2541 { 2542 struct l2_bucket *l2b; 2543 struct pv_entry *pv, *npv, **pvp; 2544 pmap_t pm; 2545 pt_entry_t *ptep; 2546 bool flush; 2547 u_int flags; 2548 2549 NPDEBUG(PDB_FOLLOW, 2550 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2551 pa)); 2552 2553 pv = SLIST_FIRST(&md->pvh_list); 2554 if (pv == NULL) { 2555 #ifdef PMAP_CACHE_VIPT 2556 /* 2557 * We *know* the page contents are about to be replaced. 2558 * Discard the exec contents 2559 */ 2560 if (PV_IS_EXEC_P(md->pvh_attrs)) 2561 PMAPCOUNT(exec_discarded_page_protect); 2562 md->pvh_attrs &= ~PVF_EXEC; 2563 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2564 #endif 2565 return; 2566 } 2567 #ifdef PMAP_CACHE_VIPT 2568 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2569 #endif 2570 2571 /* 2572 * Clear alias counts 2573 */ 2574 #ifdef PMAP_CACHE_VIVT 2575 md->k_mappings = 0; 2576 #endif 2577 md->urw_mappings = md->uro_mappings = 0; 2578 2579 flush = false; 2580 flags = 0; 2581 2582 #ifdef PMAP_CACHE_VIVT 2583 pmap_clean_page(pv, false); 2584 #endif 2585 2586 pvp = &SLIST_FIRST(&md->pvh_list); 2587 while (pv) { 2588 pm = pv->pv_pmap; 2589 npv = SLIST_NEXT(pv, pv_link); 2590 if (flush == false && pmap_is_current(pm)) 2591 flush = true; 2592 2593 if (pm == pmap_kernel()) { 2594 #ifdef PMAP_CACHE_VIPT 2595 /* 2596 * If this was unmanaged mapping, it must be preserved. 2597 * Move it back on the list and advance the end-of-list 2598 * pointer. 2599 */ 2600 if (pv->pv_flags & PVF_KENTRY) { 2601 *pvp = pv; 2602 pvp = &SLIST_NEXT(pv, pv_link); 2603 pv = npv; 2604 continue; 2605 } 2606 if (pv->pv_flags & PVF_WRITE) 2607 md->krw_mappings--; 2608 else 2609 md->kro_mappings--; 2610 #endif 2611 PMAPCOUNT(kernel_unmappings); 2612 } 2613 PMAPCOUNT(unmappings); 2614 2615 pmap_acquire_pmap_lock(pm); 2616 2617 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2618 KDASSERT(l2b != NULL); 2619 2620 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2621 2622 /* 2623 * Update statistics 2624 */ 2625 --pm->pm_stats.resident_count; 2626 2627 /* Wired bit */ 2628 if (pv->pv_flags & PVF_WIRED) 2629 --pm->pm_stats.wired_count; 2630 2631 flags |= pv->pv_flags; 2632 2633 /* 2634 * Invalidate the PTEs. 2635 */ 2636 *ptep = 0; 2637 PTE_SYNC_CURRENT(pm, ptep); 2638 pmap_free_l2_bucket(pm, l2b, 1); 2639 2640 pool_put(&pmap_pv_pool, pv); 2641 pv = npv; 2642 /* 2643 * if we reach the end of the list and there are still 2644 * mappings, they might be able to be cached now. 2645 */ 2646 if (pv == NULL) { 2647 *pvp = NULL; 2648 if (!SLIST_EMPTY(&md->pvh_list)) 2649 pmap_vac_me_harder(md, pa, pm, 0); 2650 } 2651 pmap_release_pmap_lock(pm); 2652 } 2653 #ifdef PMAP_CACHE_VIPT 2654 /* 2655 * Its EXEC cache is now gone. 2656 */ 2657 if (PV_IS_EXEC_P(md->pvh_attrs)) 2658 PMAPCOUNT(exec_discarded_page_protect); 2659 md->pvh_attrs &= ~PVF_EXEC; 2660 KASSERT(md->urw_mappings == 0); 2661 KASSERT(md->uro_mappings == 0); 2662 if (md->krw_mappings == 0) 2663 md->pvh_attrs &= ~PVF_WRITE; 2664 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2665 #endif 2666 2667 if (flush) { 2668 /* 2669 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2670 * would need a subsequent call to pmap_update() to ensure 2671 * curpm->pm_cstate.cs_all is reset. Our callers are not 2672 * required to do that (see pmap(9)), so we can't modify 2673 * the current pmap's state. 2674 */ 2675 if (PV_BEEN_EXECD(flags)) 2676 cpu_tlb_flushID(); 2677 else 2678 cpu_tlb_flushD(); 2679 } 2680 cpu_cpwait(); 2681 } 2682 2683 /* 2684 * pmap_t pmap_create(void) 2685 * 2686 * Create a new pmap structure from scratch. 2687 */ 2688 pmap_t 2689 pmap_create(void) 2690 { 2691 pmap_t pm; 2692 2693 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2694 2695 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2696 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2697 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2698 2699 pm->pm_stats.wired_count = 0; 2700 pm->pm_stats.resident_count = 1; 2701 pm->pm_cstate.cs_all = 0; 2702 pmap_alloc_l1(pm); 2703 2704 /* 2705 * Note: The pool cache ensures that the pm_l2[] array is already 2706 * initialised to zero. 2707 */ 2708 2709 pmap_pinit(pm); 2710 2711 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2712 2713 return (pm); 2714 } 2715 2716 u_int 2717 arm32_mmap_flags(paddr_t pa) 2718 { 2719 /* 2720 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 2721 * and we're using the upper bits in page numbers to pass flags around 2722 * so we might as well use the same bits 2723 */ 2724 return (u_int)pa & PMAP_MD_MASK; 2725 } 2726 /* 2727 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2728 * u_int flags) 2729 * 2730 * Insert the given physical page (p) at 2731 * the specified virtual address (v) in the 2732 * target physical map with the protection requested. 2733 * 2734 * NB: This is the only routine which MAY NOT lazy-evaluate 2735 * or lose information. That is, this routine must actually 2736 * insert this page into the given map NOW. 2737 */ 2738 int 2739 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2740 { 2741 struct l2_bucket *l2b; 2742 struct vm_page *pg, *opg; 2743 struct pv_entry *pv; 2744 pt_entry_t *ptep, npte, opte; 2745 u_int nflags; 2746 u_int oflags; 2747 2748 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2749 2750 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2751 KDASSERT(((va | pa) & PGOFSET) == 0); 2752 2753 /* 2754 * Get a pointer to the page. Later on in this function, we 2755 * test for a managed page by checking pg != NULL. 2756 */ 2757 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2758 2759 nflags = 0; 2760 if (prot & VM_PROT_WRITE) 2761 nflags |= PVF_WRITE; 2762 if (prot & VM_PROT_EXECUTE) 2763 nflags |= PVF_EXEC; 2764 if (flags & PMAP_WIRED) 2765 nflags |= PVF_WIRED; 2766 2767 pmap_acquire_pmap_lock(pm); 2768 2769 /* 2770 * Fetch the L2 bucket which maps this page, allocating one if 2771 * necessary for user pmaps. 2772 */ 2773 if (pm == pmap_kernel()) 2774 l2b = pmap_get_l2_bucket(pm, va); 2775 else 2776 l2b = pmap_alloc_l2_bucket(pm, va); 2777 if (l2b == NULL) { 2778 if (flags & PMAP_CANFAIL) { 2779 pmap_release_pmap_lock(pm); 2780 return (ENOMEM); 2781 } 2782 panic("pmap_enter: failed to allocate L2 bucket"); 2783 } 2784 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2785 opte = *ptep; 2786 npte = pa; 2787 oflags = 0; 2788 2789 if (opte) { 2790 /* 2791 * There is already a mapping at this address. 2792 * If the physical address is different, lookup the 2793 * vm_page. 2794 */ 2795 if (l2pte_pa(opte) != pa) 2796 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2797 else 2798 opg = pg; 2799 } else 2800 opg = NULL; 2801 2802 if (pg) { 2803 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2804 2805 /* 2806 * This is to be a managed mapping. 2807 */ 2808 if ((flags & VM_PROT_ALL) || 2809 (md->pvh_attrs & PVF_REF)) { 2810 /* 2811 * - The access type indicates that we don't need 2812 * to do referenced emulation. 2813 * OR 2814 * - The physical page has already been referenced 2815 * so no need to re-do referenced emulation here. 2816 */ 2817 npte |= l2pte_set_readonly(L2_S_PROTO); 2818 2819 nflags |= PVF_REF; 2820 2821 if ((prot & VM_PROT_WRITE) != 0 && 2822 ((flags & VM_PROT_WRITE) != 0 || 2823 (md->pvh_attrs & PVF_MOD) != 0)) { 2824 /* 2825 * This is a writable mapping, and the 2826 * page's mod state indicates it has 2827 * already been modified. Make it 2828 * writable from the outset. 2829 */ 2830 npte = l2pte_set_writable(npte); 2831 nflags |= PVF_MOD; 2832 } 2833 } else { 2834 /* 2835 * Need to do page referenced emulation. 2836 */ 2837 npte |= L2_TYPE_INV; 2838 } 2839 2840 npte |= pte_l2_s_cache_mode; 2841 2842 if (pg == opg) { 2843 /* 2844 * We're changing the attrs of an existing mapping. 2845 */ 2846 #ifdef MULTIPROCESSOR 2847 KASSERT(uvm_page_locked_p(pg)); 2848 #endif 2849 oflags = pmap_modify_pv(md, pa, pm, va, 2850 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2851 PVF_MOD | PVF_REF, nflags); 2852 2853 #ifdef PMAP_CACHE_VIVT 2854 /* 2855 * We may need to flush the cache if we're 2856 * doing rw-ro... 2857 */ 2858 if (pm->pm_cstate.cs_cache_d && 2859 (oflags & PVF_NC) == 0 && 2860 l2pte_writable_p(opte) && 2861 (prot & VM_PROT_WRITE) == 0) 2862 cpu_dcache_wb_range(va, PAGE_SIZE); 2863 #endif 2864 } else { 2865 /* 2866 * New mapping, or changing the backing page 2867 * of an existing mapping. 2868 */ 2869 if (opg) { 2870 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2871 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2872 2873 /* 2874 * Replacing an existing mapping with a new one. 2875 * It is part of our managed memory so we 2876 * must remove it from the PV list 2877 */ 2878 #ifdef MULTIPROCESSOR 2879 KASSERT(uvm_page_locked_p(opg)); 2880 #endif 2881 pv = pmap_remove_pv(omd, opa, pm, va); 2882 pmap_vac_me_harder(omd, opa, pm, 0); 2883 oflags = pv->pv_flags; 2884 2885 #ifdef PMAP_CACHE_VIVT 2886 /* 2887 * If the old mapping was valid (ref/mod 2888 * emulation creates 'invalid' mappings 2889 * initially) then make sure to frob 2890 * the cache. 2891 */ 2892 if ((oflags & PVF_NC) == 0 && 2893 l2pte_valid(opte)) { 2894 if (PV_BEEN_EXECD(oflags)) { 2895 pmap_idcache_wbinv_range(pm, va, 2896 PAGE_SIZE); 2897 } else 2898 if (PV_BEEN_REFD(oflags)) { 2899 pmap_dcache_wb_range(pm, va, 2900 PAGE_SIZE, true, 2901 (oflags & PVF_WRITE) == 0); 2902 } 2903 } 2904 #endif 2905 } else 2906 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2907 if ((flags & PMAP_CANFAIL) == 0) 2908 panic("pmap_enter: no pv entries"); 2909 2910 if (pm != pmap_kernel()) 2911 pmap_free_l2_bucket(pm, l2b, 0); 2912 pmap_release_pmap_lock(pm); 2913 NPDEBUG(PDB_ENTER, 2914 printf("pmap_enter: ENOMEM\n")); 2915 return (ENOMEM); 2916 } 2917 2918 #ifdef MULTIPROCESSOR 2919 KASSERT(uvm_page_locked_p(pg)); 2920 #endif 2921 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2922 } 2923 } else { 2924 /* 2925 * We're mapping an unmanaged page. 2926 * These are always readable, and possibly writable, from 2927 * the get go as we don't need to track ref/mod status. 2928 */ 2929 npte |= l2pte_set_readonly(L2_S_PROTO); 2930 if (prot & VM_PROT_WRITE) 2931 npte = l2pte_set_writable(npte); 2932 2933 /* 2934 * Make sure the vector table is mapped cacheable 2935 */ 2936 if ((pm != pmap_kernel() && va == vector_page) || 2937 (flags & ARM32_MMAP_CACHEABLE)) { 2938 npte |= pte_l2_s_cache_mode; 2939 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 2940 npte |= pte_l2_s_wc_mode; 2941 } 2942 if (opg) { 2943 /* 2944 * Looks like there's an existing 'managed' mapping 2945 * at this address. 2946 */ 2947 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2948 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2949 2950 #ifdef MULTIPROCESSOR 2951 KASSERT(uvm_page_locked_p(opg)); 2952 #endif 2953 pv = pmap_remove_pv(omd, opa, pm, va); 2954 pmap_vac_me_harder(omd, opa, pm, 0); 2955 oflags = pv->pv_flags; 2956 2957 #ifdef PMAP_CACHE_VIVT 2958 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2959 if (PV_BEEN_EXECD(oflags)) 2960 pmap_idcache_wbinv_range(pm, va, 2961 PAGE_SIZE); 2962 else 2963 if (PV_BEEN_REFD(oflags)) 2964 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2965 true, (oflags & PVF_WRITE) == 0); 2966 } 2967 #endif 2968 pool_put(&pmap_pv_pool, pv); 2969 } 2970 } 2971 2972 /* 2973 * Make sure userland mappings get the right permissions 2974 */ 2975 if (pm != pmap_kernel() && va != vector_page) 2976 npte |= L2_S_PROT_U; 2977 2978 /* 2979 * Keep the stats up to date 2980 */ 2981 if (opte == 0) { 2982 l2b->l2b_occupancy++; 2983 pm->pm_stats.resident_count++; 2984 } 2985 2986 NPDEBUG(PDB_ENTER, 2987 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2988 2989 /* 2990 * If this is just a wiring change, the two PTEs will be 2991 * identical, so there's no need to update the page table. 2992 */ 2993 if (npte != opte) { 2994 bool is_cached = pmap_is_cached(pm); 2995 2996 *ptep = npte; 2997 if (is_cached) { 2998 /* 2999 * We only need to frob the cache/tlb if this pmap 3000 * is current 3001 */ 3002 PTE_SYNC(ptep); 3003 if (va != vector_page && l2pte_valid(npte)) { 3004 /* 3005 * This mapping is likely to be accessed as 3006 * soon as we return to userland. Fix up the 3007 * L1 entry to avoid taking another 3008 * page/domain fault. 3009 */ 3010 pd_entry_t *pl1pd, l1pd; 3011 3012 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3013 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3014 L1_C_PROTO; 3015 if (*pl1pd != l1pd) { 3016 *pl1pd = l1pd; 3017 PTE_SYNC(pl1pd); 3018 } 3019 } 3020 } 3021 3022 if (PV_BEEN_EXECD(oflags)) 3023 pmap_tlb_flushID_SE(pm, va); 3024 else 3025 if (PV_BEEN_REFD(oflags)) 3026 pmap_tlb_flushD_SE(pm, va); 3027 3028 NPDEBUG(PDB_ENTER, 3029 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3030 is_cached, pm->pm_cstate.cs_all)); 3031 3032 if (pg != NULL) { 3033 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3034 3035 #ifdef MULTIPROCESSOR 3036 KASSERT(uvm_page_locked_p(pg)); 3037 #endif 3038 pmap_vac_me_harder(md, pa, pm, va); 3039 } 3040 } 3041 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3042 if (pg) { 3043 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3044 3045 #ifdef MULTIPROCESSOR 3046 KASSERT(uvm_page_locked_p(pg)); 3047 #endif 3048 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3049 KASSERT(arm_cache_prefer_mask == 0 || ((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0)); 3050 } 3051 #endif 3052 3053 pmap_release_pmap_lock(pm); 3054 3055 return (0); 3056 } 3057 3058 /* 3059 * pmap_remove() 3060 * 3061 * pmap_remove is responsible for nuking a number of mappings for a range 3062 * of virtual address space in the current pmap. To do this efficiently 3063 * is interesting, because in a number of cases a wide virtual address 3064 * range may be supplied that contains few actual mappings. So, the 3065 * optimisations are: 3066 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3067 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3068 * maybe do just a partial cache clean. This path of execution is 3069 * complicated by the fact that the cache must be flushed _before_ 3070 * the PTE is nuked, being a VAC :-) 3071 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3072 * all invalidations until pmap_update(), since pmap_remove_all() has 3073 * already flushed the cache. 3074 * 4. Maybe later fast-case a single page, but I don't think this is 3075 * going to make _that_ much difference overall. 3076 */ 3077 3078 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3079 3080 void 3081 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3082 { 3083 struct l2_bucket *l2b; 3084 vaddr_t next_bucket; 3085 pt_entry_t *ptep; 3086 u_int cleanlist_idx, total, cnt; 3087 struct { 3088 vaddr_t va; 3089 pt_entry_t *ptep; 3090 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3091 u_int mappings, is_exec, is_refd; 3092 3093 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3094 "eva=%08lx\n", pm, sva, eva)); 3095 3096 /* 3097 * we lock in the pmap => pv_head direction 3098 */ 3099 pmap_acquire_pmap_lock(pm); 3100 3101 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3102 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3103 if (pm->pm_cstate.cs_tlb == 0) 3104 pm->pm_remove_all = true; 3105 } else 3106 cleanlist_idx = 0; 3107 3108 total = 0; 3109 3110 while (sva < eva) { 3111 /* 3112 * Do one L2 bucket's worth at a time. 3113 */ 3114 next_bucket = L2_NEXT_BUCKET(sva); 3115 if (next_bucket > eva) 3116 next_bucket = eva; 3117 3118 l2b = pmap_get_l2_bucket(pm, sva); 3119 if (l2b == NULL) { 3120 sva = next_bucket; 3121 continue; 3122 } 3123 3124 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3125 3126 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3127 struct vm_page *pg; 3128 pt_entry_t pte; 3129 paddr_t pa; 3130 3131 pte = *ptep; 3132 3133 if (pte == 0) { 3134 /* Nothing here, move along */ 3135 continue; 3136 } 3137 3138 pa = l2pte_pa(pte); 3139 is_exec = 0; 3140 is_refd = 1; 3141 3142 /* 3143 * Update flags. In a number of circumstances, 3144 * we could cluster a lot of these and do a 3145 * number of sequential pages in one go. 3146 */ 3147 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3148 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3149 struct pv_entry *pv; 3150 3151 #ifdef MULTIPROCESSOR 3152 KASSERT(uvm_page_locked_p(pg)); 3153 #endif 3154 pv = pmap_remove_pv(md, pa, pm, sva); 3155 pmap_vac_me_harder(md, pa, pm, 0); 3156 if (pv != NULL) { 3157 if (pm->pm_remove_all == false) { 3158 is_exec = 3159 PV_BEEN_EXECD(pv->pv_flags); 3160 is_refd = 3161 PV_BEEN_REFD(pv->pv_flags); 3162 } 3163 pool_put(&pmap_pv_pool, pv); 3164 } 3165 } 3166 mappings++; 3167 3168 if (!l2pte_valid(pte)) { 3169 /* 3170 * Ref/Mod emulation is still active for this 3171 * mapping, therefore it is has not yet been 3172 * accessed. No need to frob the cache/tlb. 3173 */ 3174 *ptep = 0; 3175 PTE_SYNC_CURRENT(pm, ptep); 3176 continue; 3177 } 3178 3179 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3180 /* Add to the clean list. */ 3181 cleanlist[cleanlist_idx].ptep = ptep; 3182 cleanlist[cleanlist_idx].va = 3183 sva | (is_exec & 1); 3184 cleanlist_idx++; 3185 } else 3186 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3187 /* Nuke everything if needed. */ 3188 #ifdef PMAP_CACHE_VIVT 3189 pmap_idcache_wbinv_all(pm); 3190 #endif 3191 pmap_tlb_flushID(pm); 3192 3193 /* 3194 * Roll back the previous PTE list, 3195 * and zero out the current PTE. 3196 */ 3197 for (cnt = 0; 3198 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3199 *cleanlist[cnt].ptep = 0; 3200 PTE_SYNC(cleanlist[cnt].ptep); 3201 } 3202 *ptep = 0; 3203 PTE_SYNC(ptep); 3204 cleanlist_idx++; 3205 pm->pm_remove_all = true; 3206 } else { 3207 *ptep = 0; 3208 PTE_SYNC(ptep); 3209 if (pm->pm_remove_all == false) { 3210 if (is_exec) 3211 pmap_tlb_flushID_SE(pm, sva); 3212 else 3213 if (is_refd) 3214 pmap_tlb_flushD_SE(pm, sva); 3215 } 3216 } 3217 } 3218 3219 /* 3220 * Deal with any left overs 3221 */ 3222 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3223 total += cleanlist_idx; 3224 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3225 if (pm->pm_cstate.cs_all != 0) { 3226 vaddr_t clva = cleanlist[cnt].va & ~1; 3227 if (cleanlist[cnt].va & 1) { 3228 #ifdef PMAP_CACHE_VIVT 3229 pmap_idcache_wbinv_range(pm, 3230 clva, PAGE_SIZE); 3231 #endif 3232 pmap_tlb_flushID_SE(pm, clva); 3233 } else { 3234 #ifdef PMAP_CACHE_VIVT 3235 pmap_dcache_wb_range(pm, 3236 clva, PAGE_SIZE, true, 3237 false); 3238 #endif 3239 pmap_tlb_flushD_SE(pm, clva); 3240 } 3241 } 3242 *cleanlist[cnt].ptep = 0; 3243 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3244 } 3245 3246 /* 3247 * If it looks like we're removing a whole bunch 3248 * of mappings, it's faster to just write-back 3249 * the whole cache now and defer TLB flushes until 3250 * pmap_update() is called. 3251 */ 3252 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3253 cleanlist_idx = 0; 3254 else { 3255 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3256 #ifdef PMAP_CACHE_VIVT 3257 pmap_idcache_wbinv_all(pm); 3258 #endif 3259 pm->pm_remove_all = true; 3260 } 3261 } 3262 3263 pmap_free_l2_bucket(pm, l2b, mappings); 3264 pm->pm_stats.resident_count -= mappings; 3265 } 3266 3267 pmap_release_pmap_lock(pm); 3268 } 3269 3270 #ifdef PMAP_CACHE_VIPT 3271 static struct pv_entry * 3272 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3273 { 3274 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3275 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3276 struct pv_entry *pv; 3277 3278 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3279 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3280 3281 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3282 KASSERT(pv); 3283 KASSERT(pv->pv_flags & PVF_KENTRY); 3284 3285 /* 3286 * If we are removing a writeable mapping to a cached exec page, 3287 * if it's the last mapping then clear it execness other sync 3288 * the page to the icache. 3289 */ 3290 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3291 && (pv->pv_flags & PVF_WRITE) != 0) { 3292 if (SLIST_EMPTY(&md->pvh_list)) { 3293 md->pvh_attrs &= ~PVF_EXEC; 3294 PMAPCOUNT(exec_discarded_kremove); 3295 } else { 3296 pmap_syncicache_page(md, pa); 3297 PMAPCOUNT(exec_synced_kremove); 3298 } 3299 } 3300 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3301 3302 return pv; 3303 } 3304 #endif /* PMAP_CACHE_VIPT */ 3305 3306 /* 3307 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3308 * 3309 * We assume there is already sufficient KVM space available 3310 * to do this, as we can't allocate L2 descriptor tables/metadata 3311 * from here. 3312 */ 3313 void 3314 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3315 { 3316 struct l2_bucket *l2b; 3317 pt_entry_t *ptep, opte; 3318 #ifdef PMAP_CACHE_VIVT 3319 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3320 #endif 3321 #ifdef PMAP_CACHE_VIPT 3322 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3323 struct vm_page *opg; 3324 struct pv_entry *pv = NULL; 3325 #endif 3326 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3327 3328 NPDEBUG(PDB_KENTER, 3329 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3330 va, pa, prot)); 3331 3332 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3333 KDASSERT(l2b != NULL); 3334 3335 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3336 opte = *ptep; 3337 3338 if (opte == 0) { 3339 PMAPCOUNT(kenter_mappings); 3340 l2b->l2b_occupancy++; 3341 } else { 3342 PMAPCOUNT(kenter_remappings); 3343 #ifdef PMAP_CACHE_VIPT 3344 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3345 #ifdef DIAGNOSTIC 3346 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3347 #endif 3348 if (opg) { 3349 KASSERT(opg != pg); 3350 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3351 KASSERT((flags & PMAP_KMPAGE) == 0); 3352 pv = pmap_kremove_pg(opg, va); 3353 } 3354 #endif 3355 if (l2pte_valid(opte)) { 3356 #ifdef PMAP_CACHE_VIVT 3357 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3358 #endif 3359 cpu_tlb_flushD_SE(va); 3360 cpu_cpwait(); 3361 } 3362 } 3363 3364 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3365 | ((flags & PMAP_NOCACHE) ? 0 : pte_l2_s_cache_mode); 3366 PTE_SYNC(ptep); 3367 3368 if (pg) { 3369 #ifdef MULTIPROCESSOR 3370 KASSERT(uvm_page_locked_p(pg)); 3371 #endif 3372 if (flags & PMAP_KMPAGE) { 3373 KASSERT(md->urw_mappings == 0); 3374 KASSERT(md->uro_mappings == 0); 3375 KASSERT(md->krw_mappings == 0); 3376 KASSERT(md->kro_mappings == 0); 3377 #ifdef PMAP_CACHE_VIPT 3378 KASSERT(pv == NULL); 3379 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3380 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3381 /* if there is a color conflict, evict from cache. */ 3382 if (pmap_is_page_colored_p(md) 3383 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3384 PMAPCOUNT(vac_color_change); 3385 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3386 } else if (md->pvh_attrs & PVF_MULTCLR) { 3387 /* 3388 * If this page has multiple colors, expunge 3389 * them. 3390 */ 3391 PMAPCOUNT(vac_flush_lots2); 3392 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3393 } 3394 md->pvh_attrs &= PAGE_SIZE - 1; 3395 md->pvh_attrs |= PVF_KMPAGE 3396 | PVF_COLORED | PVF_DIRTY 3397 | (va & arm_cache_prefer_mask); 3398 #endif 3399 #ifdef PMAP_CACHE_VIVT 3400 md->pvh_attrs |= PVF_KMPAGE; 3401 #endif 3402 pmap_kmpages++; 3403 #ifdef PMAP_CACHE_VIPT 3404 } else { 3405 if (pv == NULL) { 3406 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3407 KASSERT(pv != NULL); 3408 } 3409 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3410 PVF_WIRED | PVF_KENTRY 3411 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3412 if ((prot & VM_PROT_WRITE) 3413 && !(md->pvh_attrs & PVF_NC)) 3414 md->pvh_attrs |= PVF_DIRTY; 3415 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3416 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3417 #endif 3418 } 3419 #ifdef PMAP_CACHE_VIPT 3420 } else { 3421 if (pv != NULL) 3422 pool_put(&pmap_pv_pool, pv); 3423 #endif 3424 } 3425 } 3426 3427 void 3428 pmap_kremove(vaddr_t va, vsize_t len) 3429 { 3430 struct l2_bucket *l2b; 3431 pt_entry_t *ptep, *sptep, opte; 3432 vaddr_t next_bucket, eva; 3433 u_int mappings; 3434 struct vm_page *opg; 3435 3436 PMAPCOUNT(kenter_unmappings); 3437 3438 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3439 va, len)); 3440 3441 eva = va + len; 3442 3443 while (va < eva) { 3444 next_bucket = L2_NEXT_BUCKET(va); 3445 if (next_bucket > eva) 3446 next_bucket = eva; 3447 3448 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3449 KDASSERT(l2b != NULL); 3450 3451 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3452 mappings = 0; 3453 3454 while (va < next_bucket) { 3455 opte = *ptep; 3456 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3457 if (opg) { 3458 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3459 3460 if (omd->pvh_attrs & PVF_KMPAGE) { 3461 KASSERT(omd->urw_mappings == 0); 3462 KASSERT(omd->uro_mappings == 0); 3463 KASSERT(omd->krw_mappings == 0); 3464 KASSERT(omd->kro_mappings == 0); 3465 omd->pvh_attrs &= ~PVF_KMPAGE; 3466 #ifdef PMAP_CACHE_VIPT 3467 omd->pvh_attrs &= ~PVF_WRITE; 3468 #endif 3469 pmap_kmpages--; 3470 #ifdef PMAP_CACHE_VIPT 3471 } else { 3472 pool_put(&pmap_pv_pool, 3473 pmap_kremove_pg(opg, va)); 3474 #endif 3475 } 3476 } 3477 if (l2pte_valid(opte)) { 3478 #ifdef PMAP_CACHE_VIVT 3479 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3480 #endif 3481 cpu_tlb_flushD_SE(va); 3482 } 3483 if (opte) { 3484 *ptep = 0; 3485 mappings++; 3486 } 3487 va += PAGE_SIZE; 3488 ptep++; 3489 } 3490 KDASSERT(mappings <= l2b->l2b_occupancy); 3491 l2b->l2b_occupancy -= mappings; 3492 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3493 } 3494 cpu_cpwait(); 3495 } 3496 3497 bool 3498 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3499 { 3500 struct l2_dtable *l2; 3501 pd_entry_t *pl1pd, l1pd; 3502 pt_entry_t *ptep, pte; 3503 paddr_t pa; 3504 u_int l1idx; 3505 3506 pmap_acquire_pmap_lock(pm); 3507 3508 l1idx = L1_IDX(va); 3509 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3510 l1pd = *pl1pd; 3511 3512 if (l1pte_section_p(l1pd)) { 3513 /* 3514 * These should only happen for pmap_kernel() 3515 */ 3516 KDASSERT(pm == pmap_kernel()); 3517 pmap_release_pmap_lock(pm); 3518 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3519 } else { 3520 /* 3521 * Note that we can't rely on the validity of the L1 3522 * descriptor as an indication that a mapping exists. 3523 * We have to look it up in the L2 dtable. 3524 */ 3525 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3526 3527 if (l2 == NULL || 3528 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3529 pmap_release_pmap_lock(pm); 3530 return false; 3531 } 3532 3533 ptep = &ptep[l2pte_index(va)]; 3534 pte = *ptep; 3535 pmap_release_pmap_lock(pm); 3536 3537 if (pte == 0) 3538 return false; 3539 3540 switch (pte & L2_TYPE_MASK) { 3541 case L2_TYPE_L: 3542 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3543 break; 3544 3545 default: 3546 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3547 break; 3548 } 3549 } 3550 3551 if (pap != NULL) 3552 *pap = pa; 3553 3554 return true; 3555 } 3556 3557 void 3558 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3559 { 3560 struct l2_bucket *l2b; 3561 pt_entry_t *ptep, pte; 3562 vaddr_t next_bucket; 3563 u_int flags; 3564 u_int clr_mask; 3565 int flush; 3566 3567 NPDEBUG(PDB_PROTECT, 3568 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3569 pm, sva, eva, prot)); 3570 3571 if ((prot & VM_PROT_READ) == 0) { 3572 pmap_remove(pm, sva, eva); 3573 return; 3574 } 3575 3576 if (prot & VM_PROT_WRITE) { 3577 /* 3578 * If this is a read->write transition, just ignore it and let 3579 * uvm_fault() take care of it later. 3580 */ 3581 return; 3582 } 3583 3584 pmap_acquire_pmap_lock(pm); 3585 3586 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3587 flags = 0; 3588 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3589 3590 while (sva < eva) { 3591 next_bucket = L2_NEXT_BUCKET(sva); 3592 if (next_bucket > eva) 3593 next_bucket = eva; 3594 3595 l2b = pmap_get_l2_bucket(pm, sva); 3596 if (l2b == NULL) { 3597 sva = next_bucket; 3598 continue; 3599 } 3600 3601 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3602 3603 while (sva < next_bucket) { 3604 pte = *ptep; 3605 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3606 struct vm_page *pg; 3607 u_int f; 3608 3609 #ifdef PMAP_CACHE_VIVT 3610 /* 3611 * OK, at this point, we know we're doing 3612 * write-protect operation. If the pmap is 3613 * active, write-back the page. 3614 */ 3615 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3616 false, false); 3617 #endif 3618 3619 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3620 pte = l2pte_set_readonly(pte); 3621 *ptep = pte; 3622 PTE_SYNC(ptep); 3623 3624 if (pg != NULL) { 3625 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3626 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3627 3628 #ifdef MULTIPROCESSOR 3629 KASSERT(uvm_page_locked_p(pg)); 3630 #endif 3631 f = pmap_modify_pv(md, pa, pm, sva, 3632 clr_mask, 0); 3633 pmap_vac_me_harder(md, pa, pm, sva); 3634 } else { 3635 f = PVF_REF | PVF_EXEC; 3636 } 3637 3638 if (flush >= 0) { 3639 flush++; 3640 flags |= f; 3641 } else 3642 if (PV_BEEN_EXECD(f)) 3643 pmap_tlb_flushID_SE(pm, sva); 3644 else 3645 if (PV_BEEN_REFD(f)) 3646 pmap_tlb_flushD_SE(pm, sva); 3647 } 3648 3649 sva += PAGE_SIZE; 3650 ptep++; 3651 } 3652 } 3653 3654 pmap_release_pmap_lock(pm); 3655 3656 if (flush) { 3657 if (PV_BEEN_EXECD(flags)) 3658 pmap_tlb_flushID(pm); 3659 else 3660 if (PV_BEEN_REFD(flags)) 3661 pmap_tlb_flushD(pm); 3662 } 3663 } 3664 3665 void 3666 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3667 { 3668 struct l2_bucket *l2b; 3669 pt_entry_t *ptep; 3670 vaddr_t next_bucket; 3671 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3672 3673 NPDEBUG(PDB_EXEC, 3674 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3675 pm, sva, eva)); 3676 3677 pmap_acquire_pmap_lock(pm); 3678 3679 while (sva < eva) { 3680 next_bucket = L2_NEXT_BUCKET(sva); 3681 if (next_bucket > eva) 3682 next_bucket = eva; 3683 3684 l2b = pmap_get_l2_bucket(pm, sva); 3685 if (l2b == NULL) { 3686 sva = next_bucket; 3687 continue; 3688 } 3689 3690 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3691 sva < next_bucket; 3692 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3693 if (l2pte_valid(*ptep)) { 3694 cpu_icache_sync_range(sva, 3695 min(page_size, eva - sva)); 3696 } 3697 } 3698 } 3699 3700 pmap_release_pmap_lock(pm); 3701 } 3702 3703 void 3704 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3705 { 3706 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3707 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3708 3709 NPDEBUG(PDB_PROTECT, 3710 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3711 md, pa, prot)); 3712 3713 #ifdef MULTIPROCESSOR 3714 KASSERT(uvm_page_locked_p(pg)); 3715 #endif 3716 3717 switch(prot) { 3718 case VM_PROT_READ|VM_PROT_WRITE: 3719 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3720 pmap_clearbit(md, pa, PVF_EXEC); 3721 break; 3722 #endif 3723 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3724 break; 3725 3726 case VM_PROT_READ: 3727 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3728 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3729 break; 3730 #endif 3731 case VM_PROT_READ|VM_PROT_EXECUTE: 3732 pmap_clearbit(md, pa, PVF_WRITE); 3733 break; 3734 3735 default: 3736 pmap_page_remove(md, pa); 3737 break; 3738 } 3739 } 3740 3741 /* 3742 * pmap_clear_modify: 3743 * 3744 * Clear the "modified" attribute for a page. 3745 */ 3746 bool 3747 pmap_clear_modify(struct vm_page *pg) 3748 { 3749 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3750 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3751 bool rv; 3752 3753 #ifdef MULTIPROCESSOR 3754 KASSERT(uvm_page_locked_p(pg)); 3755 #endif 3756 3757 if (md->pvh_attrs & PVF_MOD) { 3758 rv = true; 3759 #ifdef PMAP_CACHE_VIPT 3760 /* 3761 * If we are going to clear the modified bit and there are 3762 * no other modified bits set, flush the page to memory and 3763 * mark it clean. 3764 */ 3765 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3766 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3767 #endif 3768 pmap_clearbit(md, pa, PVF_MOD); 3769 } else 3770 rv = false; 3771 3772 return (rv); 3773 } 3774 3775 /* 3776 * pmap_clear_reference: 3777 * 3778 * Clear the "referenced" attribute for a page. 3779 */ 3780 bool 3781 pmap_clear_reference(struct vm_page *pg) 3782 { 3783 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3784 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3785 bool rv; 3786 3787 #ifdef MULTIPROCESSOR 3788 KASSERT(uvm_page_locked_p(pg)); 3789 #endif 3790 3791 if (md->pvh_attrs & PVF_REF) { 3792 rv = true; 3793 pmap_clearbit(md, pa, PVF_REF); 3794 } else 3795 rv = false; 3796 3797 return (rv); 3798 } 3799 3800 /* 3801 * pmap_is_modified: 3802 * 3803 * Test if a page has the "modified" attribute. 3804 */ 3805 /* See <arm/arm32/pmap.h> */ 3806 3807 /* 3808 * pmap_is_referenced: 3809 * 3810 * Test if a page has the "referenced" attribute. 3811 */ 3812 /* See <arm/arm32/pmap.h> */ 3813 3814 int 3815 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3816 { 3817 struct l2_dtable *l2; 3818 struct l2_bucket *l2b; 3819 pd_entry_t *pl1pd, l1pd; 3820 pt_entry_t *ptep, pte; 3821 paddr_t pa; 3822 u_int l1idx; 3823 int rv = 0; 3824 3825 pmap_acquire_pmap_lock(pm); 3826 3827 l1idx = L1_IDX(va); 3828 3829 /* 3830 * If there is no l2_dtable for this address, then the process 3831 * has no business accessing it. 3832 * 3833 * Note: This will catch userland processes trying to access 3834 * kernel addresses. 3835 */ 3836 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3837 if (l2 == NULL) 3838 goto out; 3839 3840 /* 3841 * Likewise if there is no L2 descriptor table 3842 */ 3843 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3844 if (l2b->l2b_kva == NULL) 3845 goto out; 3846 3847 /* 3848 * Check the PTE itself. 3849 */ 3850 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3851 pte = *ptep; 3852 if (pte == 0) 3853 goto out; 3854 3855 /* 3856 * Catch a userland access to the vector page mapped at 0x0 3857 */ 3858 if (user && (pte & L2_S_PROT_U) == 0) 3859 goto out; 3860 3861 pa = l2pte_pa(pte); 3862 3863 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3864 /* 3865 * This looks like a good candidate for "page modified" 3866 * emulation... 3867 */ 3868 struct pv_entry *pv; 3869 struct vm_page *pg; 3870 3871 /* Extract the physical address of the page */ 3872 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3873 goto out; 3874 3875 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3876 3877 /* Get the current flags for this page. */ 3878 #ifdef MULTIPROCESSOR 3879 KASSERT(uvm_page_locked_p(pg)); 3880 #endif 3881 3882 pv = pmap_find_pv(md, pm, va); 3883 if (pv == NULL) { 3884 goto out; 3885 } 3886 3887 /* 3888 * Do the flags say this page is writable? If not then it 3889 * is a genuine write fault. If yes then the write fault is 3890 * our fault as we did not reflect the write access in the 3891 * PTE. Now we know a write has occurred we can correct this 3892 * and also set the modified bit 3893 */ 3894 if ((pv->pv_flags & PVF_WRITE) == 0) { 3895 goto out; 3896 } 3897 3898 NPDEBUG(PDB_FOLLOW, 3899 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3900 pm, va, pa)); 3901 3902 md->pvh_attrs |= PVF_REF | PVF_MOD; 3903 pv->pv_flags |= PVF_REF | PVF_MOD; 3904 #ifdef PMAP_CACHE_VIPT 3905 /* 3906 * If there are cacheable mappings for this page, mark it dirty. 3907 */ 3908 if ((md->pvh_attrs & PVF_NC) == 0) 3909 md->pvh_attrs |= PVF_DIRTY; 3910 #endif 3911 3912 /* 3913 * Re-enable write permissions for the page. No need to call 3914 * pmap_vac_me_harder(), since this is just a 3915 * modified-emulation fault, and the PVF_WRITE bit isn't 3916 * changing. We've already set the cacheable bits based on 3917 * the assumption that we can write to this page. 3918 */ 3919 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3920 PTE_SYNC(ptep); 3921 rv = 1; 3922 } else 3923 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3924 /* 3925 * This looks like a good candidate for "page referenced" 3926 * emulation. 3927 */ 3928 struct pv_entry *pv; 3929 struct vm_page *pg; 3930 3931 /* Extract the physical address of the page */ 3932 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3933 goto out; 3934 3935 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3936 3937 /* Get the current flags for this page. */ 3938 #ifdef MULTIPROCESSOR 3939 KASSERT(uvm_page_locked_p(pg)); 3940 #endif 3941 3942 pv = pmap_find_pv(md, pm, va); 3943 if (pv == NULL) { 3944 goto out; 3945 } 3946 3947 md->pvh_attrs |= PVF_REF; 3948 pv->pv_flags |= PVF_REF; 3949 3950 NPDEBUG(PDB_FOLLOW, 3951 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3952 pm, va, pa)); 3953 3954 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3955 PTE_SYNC(ptep); 3956 rv = 1; 3957 } 3958 3959 /* 3960 * We know there is a valid mapping here, so simply 3961 * fix up the L1 if necessary. 3962 */ 3963 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3964 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3965 if (*pl1pd != l1pd) { 3966 *pl1pd = l1pd; 3967 PTE_SYNC(pl1pd); 3968 rv = 1; 3969 } 3970 3971 #ifdef CPU_SA110 3972 /* 3973 * There are bugs in the rev K SA110. This is a check for one 3974 * of them. 3975 */ 3976 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3977 curcpu()->ci_arm_cpurev < 3) { 3978 /* Always current pmap */ 3979 if (l2pte_valid(pte)) { 3980 extern int kernel_debug; 3981 if (kernel_debug & 1) { 3982 struct proc *p = curlwp->l_proc; 3983 printf("prefetch_abort: page is already " 3984 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3985 printf("prefetch_abort: pc=%08lx proc=%p " 3986 "process=%s\n", va, p, p->p_comm); 3987 printf("prefetch_abort: far=%08x fs=%x\n", 3988 cpu_faultaddress(), cpu_faultstatus()); 3989 } 3990 #ifdef DDB 3991 if (kernel_debug & 2) 3992 Debugger(); 3993 #endif 3994 rv = 1; 3995 } 3996 } 3997 #endif /* CPU_SA110 */ 3998 3999 #ifdef DEBUG 4000 /* 4001 * If 'rv == 0' at this point, it generally indicates that there is a 4002 * stale TLB entry for the faulting address. This happens when two or 4003 * more processes are sharing an L1. Since we don't flush the TLB on 4004 * a context switch between such processes, we can take domain faults 4005 * for mappings which exist at the same VA in both processes. EVEN IF 4006 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4007 * example. 4008 * 4009 * This is extremely likely to happen if pmap_enter() updated the L1 4010 * entry for a recently entered mapping. In this case, the TLB is 4011 * flushed for the new mapping, but there may still be TLB entries for 4012 * other mappings belonging to other processes in the 1MB range 4013 * covered by the L1 entry. 4014 * 4015 * Since 'rv == 0', we know that the L1 already contains the correct 4016 * value, so the fault must be due to a stale TLB entry. 4017 * 4018 * Since we always need to flush the TLB anyway in the case where we 4019 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4020 * stale TLB entries dynamically. 4021 * 4022 * However, the above condition can ONLY happen if the current L1 is 4023 * being shared. If it happens when the L1 is unshared, it indicates 4024 * that other parts of the pmap are not doing their job WRT managing 4025 * the TLB. 4026 */ 4027 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4028 extern int last_fault_code; 4029 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4030 pm, va, ftype); 4031 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4032 l2, l2b, ptep, pl1pd); 4033 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4034 pte, l1pd, last_fault_code); 4035 #ifdef DDB 4036 Debugger(); 4037 #endif 4038 } 4039 #endif 4040 4041 cpu_tlb_flushID_SE(va); 4042 cpu_cpwait(); 4043 4044 rv = 1; 4045 4046 out: 4047 pmap_release_pmap_lock(pm); 4048 4049 return (rv); 4050 } 4051 4052 /* 4053 * Routine: pmap_procwr 4054 * 4055 * Function: 4056 * Synchronize caches corresponding to [addr, addr+len) in p. 4057 * 4058 */ 4059 void 4060 pmap_procwr(struct proc *p, vaddr_t va, int len) 4061 { 4062 /* We only need to do anything if it is the current process. */ 4063 if (p == curproc) 4064 cpu_icache_sync_range(va, len); 4065 } 4066 4067 /* 4068 * Routine: pmap_unwire 4069 * Function: Clear the wired attribute for a map/virtual-address pair. 4070 * 4071 * In/out conditions: 4072 * The mapping must already exist in the pmap. 4073 */ 4074 void 4075 pmap_unwire(pmap_t pm, vaddr_t va) 4076 { 4077 struct l2_bucket *l2b; 4078 pt_entry_t *ptep, pte; 4079 struct vm_page *pg; 4080 paddr_t pa; 4081 4082 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4083 4084 pmap_acquire_pmap_lock(pm); 4085 4086 l2b = pmap_get_l2_bucket(pm, va); 4087 KDASSERT(l2b != NULL); 4088 4089 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4090 pte = *ptep; 4091 4092 /* Extract the physical address of the page */ 4093 pa = l2pte_pa(pte); 4094 4095 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4096 /* Update the wired bit in the pv entry for this page. */ 4097 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4098 4099 #ifdef MULTIPROCESSOR 4100 KASSERT(uvm_page_locked_p(pg)); 4101 #endif 4102 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4103 } 4104 4105 pmap_release_pmap_lock(pm); 4106 } 4107 4108 void 4109 pmap_activate(struct lwp *l) 4110 { 4111 extern int block_userspace_access; 4112 pmap_t opm, npm, rpm; 4113 uint32_t odacr, ndacr; 4114 int oldirqstate; 4115 4116 /* 4117 * If activating a non-current lwp or the current lwp is 4118 * already active, just return. 4119 */ 4120 if (l != curlwp || 4121 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4122 return; 4123 4124 npm = l->l_proc->p_vmspace->vm_map.pmap; 4125 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4126 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4127 4128 /* 4129 * If TTB and DACR are unchanged, short-circuit all the 4130 * TLB/cache management stuff. 4131 */ 4132 if (pmap_previous_active_lwp != NULL) { 4133 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4134 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4135 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4136 4137 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4138 goto all_done; 4139 } else 4140 opm = NULL; 4141 4142 PMAPCOUNT(activations); 4143 block_userspace_access = 1; 4144 4145 /* 4146 * If switching to a user vmspace which is different to the 4147 * most recent one, and the most recent one is potentially 4148 * live in the cache, we must write-back and invalidate the 4149 * entire cache. 4150 */ 4151 rpm = pmap_recent_user; 4152 4153 /* 4154 * XXXSCW: There's a corner case here which can leave turds in the cache as 4155 * reported in kern/41058. They're probably left over during tear-down and 4156 * switching away from an exiting process. Until the root cause is identified 4157 * and fixed, zap the cache when switching pmaps. This will result in a few 4158 * unnecessary cache flushes, but that's better than silently corrupting data. 4159 */ 4160 #if 0 4161 if (npm != pmap_kernel() && rpm && npm != rpm && 4162 rpm->pm_cstate.cs_cache) { 4163 rpm->pm_cstate.cs_cache = 0; 4164 #ifdef PMAP_CACHE_VIVT 4165 cpu_idcache_wbinv_all(); 4166 #endif 4167 } 4168 #else 4169 if (rpm) { 4170 rpm->pm_cstate.cs_cache = 0; 4171 if (npm == pmap_kernel()) 4172 pmap_recent_user = NULL; 4173 #ifdef PMAP_CACHE_VIVT 4174 cpu_idcache_wbinv_all(); 4175 #endif 4176 } 4177 #endif 4178 4179 /* No interrupts while we frob the TTB/DACR */ 4180 oldirqstate = disable_interrupts(IF32_bits); 4181 4182 /* 4183 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4184 * entry corresponding to 'vector_page' in the incoming L1 table 4185 * before switching to it otherwise subsequent interrupts/exceptions 4186 * (including domain faults!) will jump into hyperspace. 4187 */ 4188 if (npm->pm_pl1vec != NULL) { 4189 cpu_tlb_flushID_SE((u_int)vector_page); 4190 cpu_cpwait(); 4191 *npm->pm_pl1vec = npm->pm_l1vec; 4192 PTE_SYNC(npm->pm_pl1vec); 4193 } 4194 4195 cpu_domains(ndacr); 4196 4197 if (npm == pmap_kernel() || npm == rpm) { 4198 /* 4199 * Switching to a kernel thread, or back to the 4200 * same user vmspace as before... Simply update 4201 * the TTB (no TLB flush required) 4202 */ 4203 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4204 "r"(npm->pm_l1->l1_physaddr)); 4205 cpu_cpwait(); 4206 } else { 4207 /* 4208 * Otherwise, update TTB and flush TLB 4209 */ 4210 cpu_context_switch(npm->pm_l1->l1_physaddr); 4211 if (rpm != NULL) 4212 rpm->pm_cstate.cs_tlb = 0; 4213 } 4214 4215 restore_interrupts(oldirqstate); 4216 4217 block_userspace_access = 0; 4218 4219 all_done: 4220 /* 4221 * The new pmap is resident. Make sure it's marked 4222 * as resident in the cache/TLB. 4223 */ 4224 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4225 if (npm != pmap_kernel()) 4226 pmap_recent_user = npm; 4227 4228 /* The old pmap is not longer active */ 4229 if (opm != NULL) 4230 opm->pm_activated = false; 4231 4232 /* But the new one is */ 4233 npm->pm_activated = true; 4234 } 4235 4236 void 4237 pmap_deactivate(struct lwp *l) 4238 { 4239 4240 /* 4241 * If the process is exiting, make sure pmap_activate() does 4242 * a full MMU context-switch and cache flush, which we might 4243 * otherwise skip. See PR port-arm/38950. 4244 */ 4245 if (l->l_proc->p_sflag & PS_WEXIT) 4246 pmap_previous_active_lwp = NULL; 4247 4248 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4249 } 4250 4251 void 4252 pmap_update(pmap_t pm) 4253 { 4254 4255 if (pm->pm_remove_all) { 4256 /* 4257 * Finish up the pmap_remove_all() optimisation by flushing 4258 * the TLB. 4259 */ 4260 pmap_tlb_flushID(pm); 4261 pm->pm_remove_all = false; 4262 } 4263 4264 if (pmap_is_current(pm)) { 4265 /* 4266 * If we're dealing with a current userland pmap, move its L1 4267 * to the end of the LRU. 4268 */ 4269 if (pm != pmap_kernel()) 4270 pmap_use_l1(pm); 4271 4272 /* 4273 * We can assume we're done with frobbing the cache/tlb for 4274 * now. Make sure any future pmap ops don't skip cache/tlb 4275 * flushes. 4276 */ 4277 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4278 } 4279 4280 PMAPCOUNT(updates); 4281 4282 /* 4283 * make sure TLB/cache operations have completed. 4284 */ 4285 cpu_cpwait(); 4286 } 4287 4288 void 4289 pmap_remove_all(pmap_t pm) 4290 { 4291 4292 /* 4293 * The vmspace described by this pmap is about to be torn down. 4294 * Until pmap_update() is called, UVM will only make calls 4295 * to pmap_remove(). We can make life much simpler by flushing 4296 * the cache now, and deferring TLB invalidation to pmap_update(). 4297 */ 4298 #ifdef PMAP_CACHE_VIVT 4299 pmap_idcache_wbinv_all(pm); 4300 #endif 4301 pm->pm_remove_all = true; 4302 } 4303 4304 /* 4305 * Retire the given physical map from service. 4306 * Should only be called if the map contains no valid mappings. 4307 */ 4308 void 4309 pmap_destroy(pmap_t pm) 4310 { 4311 u_int count; 4312 4313 if (pm == NULL) 4314 return; 4315 4316 if (pm->pm_remove_all) { 4317 pmap_tlb_flushID(pm); 4318 pm->pm_remove_all = false; 4319 } 4320 4321 /* 4322 * Drop reference count 4323 */ 4324 mutex_enter(pm->pm_lock); 4325 count = --pm->pm_obj.uo_refs; 4326 mutex_exit(pm->pm_lock); 4327 if (count > 0) { 4328 if (pmap_is_current(pm)) { 4329 if (pm != pmap_kernel()) 4330 pmap_use_l1(pm); 4331 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4332 } 4333 return; 4334 } 4335 4336 /* 4337 * reference count is zero, free pmap resources and then free pmap. 4338 */ 4339 4340 if (vector_page < KERNEL_BASE) { 4341 KDASSERT(!pmap_is_current(pm)); 4342 4343 /* Remove the vector page mapping */ 4344 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4345 pmap_update(pm); 4346 } 4347 4348 LIST_REMOVE(pm, pm_list); 4349 4350 pmap_free_l1(pm); 4351 4352 if (pmap_recent_user == pm) 4353 pmap_recent_user = NULL; 4354 4355 uvm_obj_destroy(&pm->pm_obj, false); 4356 mutex_destroy(&pm->pm_obj_lock); 4357 pool_cache_put(&pmap_cache, pm); 4358 } 4359 4360 4361 /* 4362 * void pmap_reference(pmap_t pm) 4363 * 4364 * Add a reference to the specified pmap. 4365 */ 4366 void 4367 pmap_reference(pmap_t pm) 4368 { 4369 4370 if (pm == NULL) 4371 return; 4372 4373 pmap_use_l1(pm); 4374 4375 mutex_enter(pm->pm_lock); 4376 pm->pm_obj.uo_refs++; 4377 mutex_exit(pm->pm_lock); 4378 } 4379 4380 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4381 4382 static struct evcnt pmap_prefer_nochange_ev = 4383 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4384 static struct evcnt pmap_prefer_change_ev = 4385 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4386 4387 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4388 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4389 4390 void 4391 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4392 { 4393 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4394 vaddr_t va = *vap; 4395 vaddr_t diff = (hint - va) & mask; 4396 if (diff == 0) { 4397 pmap_prefer_nochange_ev.ev_count++; 4398 } else { 4399 pmap_prefer_change_ev.ev_count++; 4400 if (__predict_false(td)) 4401 va -= mask + 1; 4402 *vap = va + diff; 4403 } 4404 } 4405 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4406 4407 /* 4408 * pmap_zero_page() 4409 * 4410 * Zero a given physical page by mapping it at a page hook point. 4411 * In doing the zero page op, the page we zero is mapped cachable, as with 4412 * StrongARM accesses to non-cached pages are non-burst making writing 4413 * _any_ bulk data very slow. 4414 */ 4415 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4416 void 4417 pmap_zero_page_generic(paddr_t phys) 4418 { 4419 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4420 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4421 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4422 #endif 4423 #ifdef PMAP_CACHE_VIPT 4424 /* Choose the last page color it had, if any */ 4425 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4426 #else 4427 const vsize_t va_offset = 0; 4428 #endif 4429 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4430 4431 #ifdef DEBUG 4432 if (!SLIST_EMPTY(&md->pvh_list)) 4433 panic("pmap_zero_page: page has mappings"); 4434 #endif 4435 4436 KDASSERT((phys & PGOFSET) == 0); 4437 4438 /* 4439 * Hook in the page, zero it, and purge the cache for that 4440 * zeroed page. Invalidate the TLB as needed. 4441 */ 4442 *ptep = L2_S_PROTO | phys | 4443 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4444 PTE_SYNC(ptep); 4445 cpu_tlb_flushD_SE(cdstp + va_offset); 4446 cpu_cpwait(); 4447 bzero_page(cdstp + va_offset); 4448 /* 4449 * Unmap the page. 4450 */ 4451 *ptep = 0; 4452 PTE_SYNC(ptep); 4453 cpu_tlb_flushD_SE(cdstp + va_offset); 4454 #ifdef PMAP_CACHE_VIVT 4455 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4456 #endif 4457 #ifdef PMAP_CACHE_VIPT 4458 /* 4459 * This page is now cache resident so it now has a page color. 4460 * Any contents have been obliterated so clear the EXEC flag. 4461 */ 4462 if (!pmap_is_page_colored_p(md)) { 4463 PMAPCOUNT(vac_color_new); 4464 md->pvh_attrs |= PVF_COLORED; 4465 } 4466 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4467 md->pvh_attrs &= ~PVF_EXEC; 4468 PMAPCOUNT(exec_discarded_zero); 4469 } 4470 md->pvh_attrs |= PVF_DIRTY; 4471 #endif 4472 } 4473 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4474 4475 #if ARM_MMU_XSCALE == 1 4476 void 4477 pmap_zero_page_xscale(paddr_t phys) 4478 { 4479 #ifdef DEBUG 4480 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4481 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4482 4483 if (!SLIST_EMPTY(&md->pvh_list)) 4484 panic("pmap_zero_page: page has mappings"); 4485 #endif 4486 4487 KDASSERT((phys & PGOFSET) == 0); 4488 4489 /* 4490 * Hook in the page, zero it, and purge the cache for that 4491 * zeroed page. Invalidate the TLB as needed. 4492 */ 4493 *cdst_pte = L2_S_PROTO | phys | 4494 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4495 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4496 PTE_SYNC(cdst_pte); 4497 cpu_tlb_flushD_SE(cdstp); 4498 cpu_cpwait(); 4499 bzero_page(cdstp); 4500 xscale_cache_clean_minidata(); 4501 } 4502 #endif /* ARM_MMU_XSCALE == 1 */ 4503 4504 /* pmap_pageidlezero() 4505 * 4506 * The same as above, except that we assume that the page is not 4507 * mapped. This means we never have to flush the cache first. Called 4508 * from the idle loop. 4509 */ 4510 bool 4511 pmap_pageidlezero(paddr_t phys) 4512 { 4513 unsigned int i; 4514 int *ptr; 4515 bool rv = true; 4516 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4517 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4518 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4519 #endif 4520 #ifdef PMAP_CACHE_VIPT 4521 /* Choose the last page color it had, if any */ 4522 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4523 #else 4524 const vsize_t va_offset = 0; 4525 #endif 4526 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4527 4528 4529 #ifdef DEBUG 4530 if (!SLIST_EMPTY(&md->pvh_list)) 4531 panic("pmap_pageidlezero: page has mappings"); 4532 #endif 4533 4534 KDASSERT((phys & PGOFSET) == 0); 4535 4536 /* 4537 * Hook in the page, zero it, and purge the cache for that 4538 * zeroed page. Invalidate the TLB as needed. 4539 */ 4540 *ptep = L2_S_PROTO | phys | 4541 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4542 PTE_SYNC(ptep); 4543 cpu_tlb_flushD_SE(cdstp + va_offset); 4544 cpu_cpwait(); 4545 4546 for (i = 0, ptr = (int *)(cdstp + va_offset); 4547 i < (PAGE_SIZE / sizeof(int)); i++) { 4548 if (sched_curcpu_runnable_p() != 0) { 4549 /* 4550 * A process has become ready. Abort now, 4551 * so we don't keep it waiting while we 4552 * do slow memory access to finish this 4553 * page. 4554 */ 4555 rv = false; 4556 break; 4557 } 4558 *ptr++ = 0; 4559 } 4560 4561 #ifdef PMAP_CACHE_VIVT 4562 if (rv) 4563 /* 4564 * if we aborted we'll rezero this page again later so don't 4565 * purge it unless we finished it 4566 */ 4567 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4568 #elif defined(PMAP_CACHE_VIPT) 4569 /* 4570 * This page is now cache resident so it now has a page color. 4571 * Any contents have been obliterated so clear the EXEC flag. 4572 */ 4573 if (!pmap_is_page_colored_p(md)) { 4574 PMAPCOUNT(vac_color_new); 4575 md->pvh_attrs |= PVF_COLORED; 4576 } 4577 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4578 md->pvh_attrs &= ~PVF_EXEC; 4579 PMAPCOUNT(exec_discarded_zero); 4580 } 4581 #endif 4582 /* 4583 * Unmap the page. 4584 */ 4585 *ptep = 0; 4586 PTE_SYNC(ptep); 4587 cpu_tlb_flushD_SE(cdstp + va_offset); 4588 4589 return (rv); 4590 } 4591 4592 /* 4593 * pmap_copy_page() 4594 * 4595 * Copy one physical page into another, by mapping the pages into 4596 * hook points. The same comment regarding cachability as in 4597 * pmap_zero_page also applies here. 4598 */ 4599 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4600 void 4601 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4602 { 4603 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4604 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4605 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4606 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4607 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4608 #endif 4609 #ifdef PMAP_CACHE_VIPT 4610 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4611 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4612 #else 4613 const vsize_t src_va_offset = 0; 4614 const vsize_t dst_va_offset = 0; 4615 #endif 4616 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4617 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4618 4619 #ifdef DEBUG 4620 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4621 panic("pmap_copy_page: dst page has mappings"); 4622 #endif 4623 4624 #ifdef PMAP_CACHE_VIPT 4625 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4626 #endif 4627 KDASSERT((src & PGOFSET) == 0); 4628 KDASSERT((dst & PGOFSET) == 0); 4629 4630 /* 4631 * Clean the source page. Hold the source page's lock for 4632 * the duration of the copy so that no other mappings can 4633 * be created while we have a potentially aliased mapping. 4634 */ 4635 #ifdef MULTIPROCESSOR 4636 KASSERT(uvm_page_locked_p(src_pg)); 4637 #endif 4638 #ifdef PMAP_CACHE_VIVT 4639 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4640 #endif 4641 4642 /* 4643 * Map the pages into the page hook points, copy them, and purge 4644 * the cache for the appropriate page. Invalidate the TLB 4645 * as required. 4646 */ 4647 *src_ptep = L2_S_PROTO 4648 | src 4649 #ifdef PMAP_CACHE_VIPT 4650 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4651 #endif 4652 #ifdef PMAP_CACHE_VIVT 4653 | pte_l2_s_cache_mode 4654 #endif 4655 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4656 *dst_ptep = L2_S_PROTO | dst | 4657 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4658 PTE_SYNC(src_ptep); 4659 PTE_SYNC(dst_ptep); 4660 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4661 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4662 cpu_cpwait(); 4663 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4664 #ifdef PMAP_CACHE_VIVT 4665 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4666 #endif 4667 #ifdef PMAP_CACHE_VIVT 4668 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4669 #endif 4670 /* 4671 * Unmap the pages. 4672 */ 4673 *src_ptep = 0; 4674 *dst_ptep = 0; 4675 PTE_SYNC(src_ptep); 4676 PTE_SYNC(dst_ptep); 4677 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4678 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4679 #ifdef PMAP_CACHE_VIPT 4680 /* 4681 * Now that the destination page is in the cache, mark it as colored. 4682 * If this was an exec page, discard it. 4683 */ 4684 if (!pmap_is_page_colored_p(dst_md)) { 4685 PMAPCOUNT(vac_color_new); 4686 dst_md->pvh_attrs |= PVF_COLORED; 4687 } 4688 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4689 dst_md->pvh_attrs &= ~PVF_EXEC; 4690 PMAPCOUNT(exec_discarded_copy); 4691 } 4692 dst_md->pvh_attrs |= PVF_DIRTY; 4693 #endif 4694 } 4695 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4696 4697 #if ARM_MMU_XSCALE == 1 4698 void 4699 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4700 { 4701 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4702 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4703 #ifdef DEBUG 4704 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4705 4706 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4707 panic("pmap_copy_page: dst page has mappings"); 4708 #endif 4709 4710 KDASSERT((src & PGOFSET) == 0); 4711 KDASSERT((dst & PGOFSET) == 0); 4712 4713 /* 4714 * Clean the source page. Hold the source page's lock for 4715 * the duration of the copy so that no other mappings can 4716 * be created while we have a potentially aliased mapping. 4717 */ 4718 #ifdef MULTIPROCESSOR 4719 KASSERT(uvm_page_locked_p(src_pg)); 4720 #endif 4721 #ifdef PMAP_CACHE_VIVT 4722 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4723 #endif 4724 4725 /* 4726 * Map the pages into the page hook points, copy them, and purge 4727 * the cache for the appropriate page. Invalidate the TLB 4728 * as required. 4729 */ 4730 *csrc_pte = L2_S_PROTO | src | 4731 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4732 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4733 PTE_SYNC(csrc_pte); 4734 *cdst_pte = L2_S_PROTO | dst | 4735 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4736 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4737 PTE_SYNC(cdst_pte); 4738 cpu_tlb_flushD_SE(csrcp); 4739 cpu_tlb_flushD_SE(cdstp); 4740 cpu_cpwait(); 4741 bcopy_page(csrcp, cdstp); 4742 xscale_cache_clean_minidata(); 4743 } 4744 #endif /* ARM_MMU_XSCALE == 1 */ 4745 4746 /* 4747 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4748 * 4749 * Return the start and end addresses of the kernel's virtual space. 4750 * These values are setup in pmap_bootstrap and are updated as pages 4751 * are allocated. 4752 */ 4753 void 4754 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4755 { 4756 *start = virtual_avail; 4757 *end = virtual_end; 4758 } 4759 4760 /* 4761 * Helper function for pmap_grow_l2_bucket() 4762 */ 4763 static inline int 4764 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4765 { 4766 struct l2_bucket *l2b; 4767 pt_entry_t *ptep; 4768 paddr_t pa; 4769 4770 if (uvm.page_init_done == false) { 4771 #ifdef PMAP_STEAL_MEMORY 4772 pv_addr_t pv; 4773 pmap_boot_pagealloc(PAGE_SIZE, 4774 #ifdef PMAP_CACHE_VIPT 4775 arm_cache_prefer_mask, 4776 va & arm_cache_prefer_mask, 4777 #else 4778 0, 0, 4779 #endif 4780 &pv); 4781 pa = pv.pv_pa; 4782 #else 4783 if (uvm_page_physget(&pa) == false) 4784 return (1); 4785 #endif /* PMAP_STEAL_MEMORY */ 4786 } else { 4787 struct vm_page *pg; 4788 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4789 if (pg == NULL) 4790 return (1); 4791 pa = VM_PAGE_TO_PHYS(pg); 4792 #ifdef PMAP_CACHE_VIPT 4793 #ifdef DIAGNOSTIC 4794 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4795 #endif 4796 /* 4797 * This new page must not have any mappings. Enter it via 4798 * pmap_kenter_pa and let that routine do the hard work. 4799 */ 4800 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4801 pmap_kenter_pa(va, pa, 4802 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4803 #endif 4804 } 4805 4806 if (pap) 4807 *pap = pa; 4808 4809 PMAPCOUNT(pt_mappings); 4810 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4811 KDASSERT(l2b != NULL); 4812 4813 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4814 *ptep = L2_S_PROTO | pa | cache_mode | 4815 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4816 PTE_SYNC(ptep); 4817 memset((void *)va, 0, PAGE_SIZE); 4818 return (0); 4819 } 4820 4821 /* 4822 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4823 * used by pmap_growkernel(). 4824 */ 4825 static inline struct l2_bucket * 4826 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4827 { 4828 struct l2_dtable *l2; 4829 struct l2_bucket *l2b; 4830 u_short l1idx; 4831 vaddr_t nva; 4832 4833 l1idx = L1_IDX(va); 4834 4835 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4836 /* 4837 * No mapping at this address, as there is 4838 * no entry in the L1 table. 4839 * Need to allocate a new l2_dtable. 4840 */ 4841 nva = pmap_kernel_l2dtable_kva; 4842 if ((nva & PGOFSET) == 0) { 4843 /* 4844 * Need to allocate a backing page 4845 */ 4846 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4847 return (NULL); 4848 } 4849 4850 l2 = (struct l2_dtable *)nva; 4851 nva += sizeof(struct l2_dtable); 4852 4853 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4854 /* 4855 * The new l2_dtable straddles a page boundary. 4856 * Map in another page to cover it. 4857 */ 4858 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4859 return (NULL); 4860 } 4861 4862 pmap_kernel_l2dtable_kva = nva; 4863 4864 /* 4865 * Link it into the parent pmap 4866 */ 4867 pm->pm_l2[L2_IDX(l1idx)] = l2; 4868 } 4869 4870 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4871 4872 /* 4873 * Fetch pointer to the L2 page table associated with the address. 4874 */ 4875 if (l2b->l2b_kva == NULL) { 4876 pt_entry_t *ptep; 4877 4878 /* 4879 * No L2 page table has been allocated. Chances are, this 4880 * is because we just allocated the l2_dtable, above. 4881 */ 4882 nva = pmap_kernel_l2ptp_kva; 4883 ptep = (pt_entry_t *)nva; 4884 if ((nva & PGOFSET) == 0) { 4885 /* 4886 * Need to allocate a backing page 4887 */ 4888 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4889 &pmap_kernel_l2ptp_phys)) 4890 return (NULL); 4891 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4892 } 4893 4894 l2->l2_occupancy++; 4895 l2b->l2b_kva = ptep; 4896 l2b->l2b_l1idx = l1idx; 4897 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4898 4899 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4900 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4901 } 4902 4903 return (l2b); 4904 } 4905 4906 vaddr_t 4907 pmap_growkernel(vaddr_t maxkvaddr) 4908 { 4909 pmap_t kpm = pmap_kernel(); 4910 struct l1_ttable *l1; 4911 struct l2_bucket *l2b; 4912 pd_entry_t *pl1pd; 4913 int s; 4914 4915 if (maxkvaddr <= pmap_curmaxkvaddr) 4916 goto out; /* we are OK */ 4917 4918 NPDEBUG(PDB_GROWKERN, 4919 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4920 pmap_curmaxkvaddr, maxkvaddr)); 4921 4922 KDASSERT(maxkvaddr <= virtual_end); 4923 4924 /* 4925 * whoops! we need to add kernel PTPs 4926 */ 4927 4928 s = splhigh(); /* to be safe */ 4929 mutex_enter(kpm->pm_lock); 4930 4931 /* Map 1MB at a time */ 4932 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4933 4934 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4935 KDASSERT(l2b != NULL); 4936 4937 /* Distribute new L1 entry to all other L1s */ 4938 SLIST_FOREACH(l1, &l1_list, l1_link) { 4939 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4940 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4941 L1_C_PROTO; 4942 PTE_SYNC(pl1pd); 4943 } 4944 } 4945 4946 /* 4947 * flush out the cache, expensive but growkernel will happen so 4948 * rarely 4949 */ 4950 cpu_dcache_wbinv_all(); 4951 cpu_tlb_flushD(); 4952 cpu_cpwait(); 4953 4954 mutex_exit(kpm->pm_lock); 4955 splx(s); 4956 4957 out: 4958 return (pmap_curmaxkvaddr); 4959 } 4960 4961 /************************ Utility routines ****************************/ 4962 4963 /* 4964 * vector_page_setprot: 4965 * 4966 * Manipulate the protection of the vector page. 4967 */ 4968 void 4969 vector_page_setprot(int prot) 4970 { 4971 struct l2_bucket *l2b; 4972 pt_entry_t *ptep; 4973 4974 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4975 KDASSERT(l2b != NULL); 4976 4977 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4978 4979 *ptep = (*ptep & ~L2_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4980 PTE_SYNC(ptep); 4981 cpu_tlb_flushD_SE(vector_page); 4982 cpu_cpwait(); 4983 } 4984 4985 /* 4986 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 4987 * Returns true if the mapping exists, else false. 4988 * 4989 * NOTE: This function is only used by a couple of arm-specific modules. 4990 * It is not safe to take any pmap locks here, since we could be right 4991 * in the middle of debugging the pmap anyway... 4992 * 4993 * It is possible for this routine to return false even though a valid 4994 * mapping does exist. This is because we don't lock, so the metadata 4995 * state may be inconsistent. 4996 * 4997 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 4998 * a "section" mapping. 4999 */ 5000 bool 5001 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5002 { 5003 struct l2_dtable *l2; 5004 pd_entry_t *pl1pd, l1pd; 5005 pt_entry_t *ptep; 5006 u_short l1idx; 5007 5008 if (pm->pm_l1 == NULL) 5009 return false; 5010 5011 l1idx = L1_IDX(va); 5012 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5013 l1pd = *pl1pd; 5014 5015 if (l1pte_section_p(l1pd)) { 5016 *ptp = NULL; 5017 return true; 5018 } 5019 5020 if (pm->pm_l2 == NULL) 5021 return false; 5022 5023 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5024 5025 if (l2 == NULL || 5026 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5027 return false; 5028 } 5029 5030 *ptp = &ptep[l2pte_index(va)]; 5031 return true; 5032 } 5033 5034 bool 5035 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5036 { 5037 u_short l1idx; 5038 5039 if (pm->pm_l1 == NULL) 5040 return false; 5041 5042 l1idx = L1_IDX(va); 5043 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5044 5045 return true; 5046 } 5047 5048 /************************ Bootstrapping routines ****************************/ 5049 5050 static void 5051 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5052 { 5053 int i; 5054 5055 l1->l1_kva = l1pt; 5056 l1->l1_domain_use_count = 0; 5057 l1->l1_domain_first = 0; 5058 5059 for (i = 0; i < PMAP_DOMAINS; i++) 5060 l1->l1_domain_free[i] = i + 1; 5061 5062 /* 5063 * Copy the kernel's L1 entries to each new L1. 5064 */ 5065 if (pmap_initialized) 5066 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5067 5068 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5069 &l1->l1_physaddr) == false) 5070 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5071 5072 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5073 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5074 } 5075 5076 /* 5077 * pmap_bootstrap() is called from the board-specific initarm() routine 5078 * once the kernel L1/L2 descriptors tables have been set up. 5079 * 5080 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5081 * spread over a number of disparate files/functions. 5082 * 5083 * We are passed the following parameters 5084 * - kernel_l1pt 5085 * This is a pointer to the base of the kernel's L1 translation table. 5086 * - vstart 5087 * 1MB-aligned start of managed kernel virtual memory. 5088 * - vend 5089 * 1MB-aligned end of managed kernel virtual memory. 5090 * 5091 * We use the first parameter to build the metadata (struct l1_ttable and 5092 * struct l2_dtable) necessary to track kernel mappings. 5093 */ 5094 #define PMAP_STATIC_L2_SIZE 16 5095 void 5096 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5097 { 5098 static struct l1_ttable static_l1; 5099 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5100 struct l1_ttable *l1 = &static_l1; 5101 struct l2_dtable *l2; 5102 struct l2_bucket *l2b; 5103 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5104 pmap_t pm = pmap_kernel(); 5105 pd_entry_t pde; 5106 pt_entry_t *ptep; 5107 paddr_t pa; 5108 vaddr_t va; 5109 vsize_t size; 5110 int nptes, l1idx, l2idx, l2next = 0; 5111 5112 /* 5113 * Initialise the kernel pmap object 5114 */ 5115 pm->pm_l1 = l1; 5116 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5117 pm->pm_activated = true; 5118 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5119 5120 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5121 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5122 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5123 5124 /* 5125 * Scan the L1 translation table created by initarm() and create 5126 * the required metadata for all valid mappings found in it. 5127 */ 5128 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5129 pde = l1pt[l1idx]; 5130 5131 /* 5132 * We're only interested in Coarse mappings. 5133 * pmap_extract() can deal with section mappings without 5134 * recourse to checking L2 metadata. 5135 */ 5136 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5137 continue; 5138 5139 /* 5140 * Lookup the KVA of this L2 descriptor table 5141 */ 5142 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5143 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5144 if (ptep == NULL) { 5145 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5146 (u_int)l1idx << L1_S_SHIFT, pa); 5147 } 5148 5149 /* 5150 * Fetch the associated L2 metadata structure. 5151 * Allocate a new one if necessary. 5152 */ 5153 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5154 if (l2next == PMAP_STATIC_L2_SIZE) 5155 panic("pmap_bootstrap: out of static L2s"); 5156 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5157 } 5158 5159 /* 5160 * One more L1 slot tracked... 5161 */ 5162 l2->l2_occupancy++; 5163 5164 /* 5165 * Fill in the details of the L2 descriptor in the 5166 * appropriate bucket. 5167 */ 5168 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5169 l2b->l2b_kva = ptep; 5170 l2b->l2b_phys = pa; 5171 l2b->l2b_l1idx = l1idx; 5172 5173 /* 5174 * Establish an initial occupancy count for this descriptor 5175 */ 5176 for (l2idx = 0; 5177 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5178 l2idx++) { 5179 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5180 l2b->l2b_occupancy++; 5181 } 5182 } 5183 5184 /* 5185 * Make sure the descriptor itself has the correct cache mode. 5186 * If not, fix it, but whine about the problem. Port-meisters 5187 * should consider this a clue to fix up their initarm() 5188 * function. :) 5189 */ 5190 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5191 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5192 "L2 pte @ %p\n", ptep); 5193 } 5194 } 5195 5196 /* 5197 * Ensure the primary (kernel) L1 has the correct cache mode for 5198 * a page table. Bitch if it is not correctly set. 5199 */ 5200 for (va = (vaddr_t)l1pt; 5201 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5202 if (pmap_set_pt_cache_mode(l1pt, va)) 5203 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5204 "primary L1 @ 0x%lx\n", va); 5205 } 5206 5207 cpu_dcache_wbinv_all(); 5208 cpu_tlb_flushID(); 5209 cpu_cpwait(); 5210 5211 /* 5212 * now we allocate the "special" VAs which are used for tmp mappings 5213 * by the pmap (and other modules). we allocate the VAs by advancing 5214 * virtual_avail (note that there are no pages mapped at these VAs). 5215 * 5216 * Managed KVM space start from wherever initarm() tells us. 5217 */ 5218 virtual_avail = vstart; 5219 virtual_end = vend; 5220 5221 #ifdef PMAP_CACHE_VIPT 5222 /* 5223 * If we have a VIPT cache, we need one page/pte per possible alias 5224 * page so we won't violate cache aliasing rules. 5225 */ 5226 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5227 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5228 #else 5229 nptes = 1; 5230 #endif 5231 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5232 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5233 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5234 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5235 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5236 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5237 (void *)&msgbufaddr, NULL); 5238 5239 /* 5240 * Allocate a range of kernel virtual address space to be used 5241 * for L2 descriptor tables and metadata allocation in 5242 * pmap_growkernel(). 5243 */ 5244 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5245 pmap_alloc_specials(&virtual_avail, 5246 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5247 &pmap_kernel_l2ptp_kva, NULL); 5248 5249 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5250 pmap_alloc_specials(&virtual_avail, 5251 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5252 &pmap_kernel_l2dtable_kva, NULL); 5253 5254 /* 5255 * init the static-global locks and global pmap list. 5256 */ 5257 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 5258 5259 /* 5260 * We can now initialise the first L1's metadata. 5261 */ 5262 SLIST_INIT(&l1_list); 5263 TAILQ_INIT(&l1_lru_list); 5264 pmap_init_l1(l1, l1pt); 5265 5266 /* Set up vector page L1 details, if necessary */ 5267 if (vector_page < KERNEL_BASE) { 5268 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5269 l2b = pmap_get_l2_bucket(pm, vector_page); 5270 KDASSERT(l2b != NULL); 5271 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5272 L1_C_DOM(pm->pm_domain); 5273 } else 5274 pm->pm_pl1vec = NULL; 5275 5276 /* 5277 * Initialize the pmap cache 5278 */ 5279 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5280 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5281 LIST_INIT(&pmap_pmaps); 5282 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5283 5284 /* 5285 * Initialize the pv pool. 5286 */ 5287 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5288 &pmap_bootstrap_pv_allocator, IPL_NONE); 5289 5290 /* 5291 * Initialize the L2 dtable pool and cache. 5292 */ 5293 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5294 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5295 5296 /* 5297 * Initialise the L2 descriptor table pool and cache 5298 */ 5299 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5300 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5301 pmap_l2ptp_ctor, NULL, NULL); 5302 5303 cpu_dcache_wbinv_all(); 5304 } 5305 5306 static int 5307 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5308 { 5309 pd_entry_t *pdep, pde; 5310 pt_entry_t *ptep, pte; 5311 vaddr_t pa; 5312 int rv = 0; 5313 5314 /* 5315 * Make sure the descriptor itself has the correct cache mode 5316 */ 5317 pdep = &kl1[L1_IDX(va)]; 5318 pde = *pdep; 5319 5320 if (l1pte_section_p(pde)) { 5321 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5322 *pdep = (pde & ~L1_S_CACHE_MASK) | 5323 pte_l1_s_cache_mode_pt; 5324 PTE_SYNC(pdep); 5325 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5326 rv = 1; 5327 } 5328 } else { 5329 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5330 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5331 if (ptep == NULL) 5332 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5333 5334 ptep = &ptep[l2pte_index(va)]; 5335 pte = *ptep; 5336 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5337 *ptep = (pte & ~L2_S_CACHE_MASK) | 5338 pte_l2_s_cache_mode_pt; 5339 PTE_SYNC(ptep); 5340 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5341 rv = 1; 5342 } 5343 } 5344 5345 return (rv); 5346 } 5347 5348 static void 5349 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5350 { 5351 vaddr_t va = *availp; 5352 struct l2_bucket *l2b; 5353 5354 if (ptep) { 5355 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5356 if (l2b == NULL) 5357 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5358 5359 if (ptep) 5360 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5361 } 5362 5363 *vap = va; 5364 *availp = va + (PAGE_SIZE * pages); 5365 } 5366 5367 void 5368 pmap_init(void) 5369 { 5370 5371 /* 5372 * Set the available memory vars - These do not map to real memory 5373 * addresses and cannot as the physical memory is fragmented. 5374 * They are used by ps for %mem calculations. 5375 * One could argue whether this should be the entire memory or just 5376 * the memory that is useable in a user process. 5377 */ 5378 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5379 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5380 5381 /* 5382 * Now we need to free enough pv_entry structures to allow us to get 5383 * the kmem_map/kmem_object allocated and inited (done after this 5384 * function is finished). to do this we allocate one bootstrap page out 5385 * of kernel_map and use it to provide an initial pool of pv_entry 5386 * structures. we never free this page. 5387 */ 5388 pool_setlowat(&pmap_pv_pool, 5389 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5390 5391 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5392 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5393 UVM_KMF_WIRED|UVM_KMF_ZERO); 5394 5395 pmap_initialized = true; 5396 } 5397 5398 static vaddr_t last_bootstrap_page = 0; 5399 static void *free_bootstrap_pages = NULL; 5400 5401 static void * 5402 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5403 { 5404 extern void *pool_page_alloc(struct pool *, int); 5405 vaddr_t new_page; 5406 void *rv; 5407 5408 if (pmap_initialized) 5409 return (pool_page_alloc(pp, flags)); 5410 5411 if (free_bootstrap_pages) { 5412 rv = free_bootstrap_pages; 5413 free_bootstrap_pages = *((void **)rv); 5414 return (rv); 5415 } 5416 5417 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5418 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5419 5420 KASSERT(new_page > last_bootstrap_page); 5421 last_bootstrap_page = new_page; 5422 return ((void *)new_page); 5423 } 5424 5425 static void 5426 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5427 { 5428 extern void pool_page_free(struct pool *, void *); 5429 5430 if ((vaddr_t)v <= last_bootstrap_page) { 5431 *((void **)v) = free_bootstrap_pages; 5432 free_bootstrap_pages = v; 5433 return; 5434 } 5435 5436 if (pmap_initialized) { 5437 pool_page_free(pp, v); 5438 return; 5439 } 5440 } 5441 5442 /* 5443 * pmap_postinit() 5444 * 5445 * This routine is called after the vm and kmem subsystems have been 5446 * initialised. This allows the pmap code to perform any initialisation 5447 * that can only be done one the memory allocation is in place. 5448 */ 5449 void 5450 pmap_postinit(void) 5451 { 5452 extern paddr_t physical_start, physical_end; 5453 struct l2_bucket *l2b; 5454 struct l1_ttable *l1; 5455 struct pglist plist; 5456 struct vm_page *m; 5457 pd_entry_t *pl1pt; 5458 pt_entry_t *ptep, pte; 5459 vaddr_t va, eva; 5460 u_int loop, needed; 5461 int error; 5462 5463 pool_cache_setlowat(&pmap_l2ptp_cache, 5464 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5465 pool_cache_setlowat(&pmap_l2dtable_cache, 5466 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5467 5468 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5469 needed -= 1; 5470 5471 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 5472 5473 for (loop = 0; loop < needed; loop++, l1++) { 5474 /* Allocate a L1 page table */ 5475 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5476 if (va == 0) 5477 panic("Cannot allocate L1 KVM"); 5478 5479 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5480 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 5481 if (error) 5482 panic("Cannot allocate L1 physical pages"); 5483 5484 m = TAILQ_FIRST(&plist); 5485 eva = va + L1_TABLE_SIZE; 5486 pl1pt = (pd_entry_t *)va; 5487 5488 while (m && va < eva) { 5489 paddr_t pa = VM_PAGE_TO_PHYS(m); 5490 5491 pmap_kenter_pa(va, pa, 5492 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5493 5494 /* 5495 * Make sure the L1 descriptor table is mapped 5496 * with the cache-mode set to write-through. 5497 */ 5498 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5499 KDASSERT(l2b != NULL); 5500 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5501 pte = *ptep; 5502 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5503 *ptep = pte; 5504 PTE_SYNC(ptep); 5505 cpu_tlb_flushD_SE(va); 5506 5507 va += PAGE_SIZE; 5508 m = TAILQ_NEXT(m, pageq.queue); 5509 } 5510 5511 #ifdef DIAGNOSTIC 5512 if (m) 5513 panic("pmap_alloc_l1pt: pglist not empty"); 5514 #endif /* DIAGNOSTIC */ 5515 5516 pmap_init_l1(l1, pl1pt); 5517 } 5518 5519 #ifdef DEBUG 5520 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5521 needed); 5522 #endif 5523 } 5524 5525 /* 5526 * Note that the following routines are used by board-specific initialisation 5527 * code to configure the initial kernel page tables. 5528 * 5529 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5530 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5531 * behaviour of the old pmap, and provides an easy migration path for 5532 * initial bring-up of the new pmap on existing ports. Fortunately, 5533 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5534 * will be deprecated. 5535 * 5536 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5537 * tables. 5538 */ 5539 5540 /* 5541 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5542 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5543 * find them as necessary. 5544 * 5545 * Note that the data on this list MUST remain valid after initarm() returns, 5546 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5547 */ 5548 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5549 5550 static vaddr_t 5551 kernel_pt_lookup(paddr_t pa) 5552 { 5553 pv_addr_t *pv; 5554 5555 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5556 #ifndef ARM32_NEW_VM_LAYOUT 5557 if (pv->pv_pa == (pa & ~PGOFSET)) 5558 return (pv->pv_va | (pa & PGOFSET)); 5559 #else 5560 if (pv->pv_pa == pa) 5561 return (pv->pv_va); 5562 #endif 5563 } 5564 return (0); 5565 } 5566 5567 /* 5568 * pmap_map_section: 5569 * 5570 * Create a single section mapping. 5571 */ 5572 void 5573 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5574 { 5575 pd_entry_t *pde = (pd_entry_t *) l1pt; 5576 pd_entry_t fl; 5577 5578 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5579 5580 switch (cache) { 5581 case PTE_NOCACHE: 5582 default: 5583 fl = 0; 5584 break; 5585 5586 case PTE_CACHE: 5587 fl = pte_l1_s_cache_mode; 5588 break; 5589 5590 case PTE_PAGETABLE: 5591 fl = pte_l1_s_cache_mode_pt; 5592 break; 5593 } 5594 5595 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5596 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5597 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5598 } 5599 5600 /* 5601 * pmap_map_entry: 5602 * 5603 * Create a single page mapping. 5604 */ 5605 void 5606 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5607 { 5608 pd_entry_t *pde = (pd_entry_t *) l1pt; 5609 pt_entry_t fl; 5610 pt_entry_t *pte; 5611 5612 KASSERT(((va | pa) & PGOFSET) == 0); 5613 5614 switch (cache) { 5615 case PTE_NOCACHE: 5616 default: 5617 fl = 0; 5618 break; 5619 5620 case PTE_CACHE: 5621 fl = pte_l2_s_cache_mode; 5622 break; 5623 5624 case PTE_PAGETABLE: 5625 fl = pte_l2_s_cache_mode_pt; 5626 break; 5627 } 5628 5629 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5630 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5631 5632 #ifndef ARM32_NEW_VM_LAYOUT 5633 pte = (pt_entry_t *) 5634 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5635 #else 5636 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5637 #endif 5638 if (pte == NULL) 5639 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5640 5641 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5642 #ifndef ARM32_NEW_VM_LAYOUT 5643 pte += (va >> PGSHIFT) & 0x3ff; 5644 #else 5645 pte += l2pte_index(va); 5646 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5647 #endif 5648 *pte = fl; 5649 PTE_SYNC(pte); 5650 } 5651 5652 /* 5653 * pmap_link_l2pt: 5654 * 5655 * Link the L2 page table specified by "l2pv" into the L1 5656 * page table at the slot for "va". 5657 */ 5658 void 5659 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5660 { 5661 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5662 u_int slot = va >> L1_S_SHIFT; 5663 5664 #ifndef ARM32_NEW_VM_LAYOUT 5665 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5666 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5667 #endif 5668 5669 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5670 5671 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5672 #ifdef ARM32_NEW_VM_LAYOUT 5673 PTE_SYNC(&pde[slot]); 5674 #else 5675 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5676 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5677 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5678 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5679 #endif 5680 5681 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5682 } 5683 5684 /* 5685 * pmap_map_chunk: 5686 * 5687 * Map a chunk of memory using the most efficient mappings 5688 * possible (section, large page, small page) into the 5689 * provided L1 and L2 tables at the specified virtual address. 5690 */ 5691 vsize_t 5692 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5693 int prot, int cache) 5694 { 5695 pd_entry_t *pdep = (pd_entry_t *) l1pt; 5696 pt_entry_t *pte, f1, f2s, f2l; 5697 vsize_t resid; 5698 int i; 5699 5700 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5701 5702 if (l1pt == 0) 5703 panic("pmap_map_chunk: no L1 table provided"); 5704 5705 #ifdef VERBOSE_INIT_ARM 5706 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5707 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5708 #endif 5709 5710 switch (cache) { 5711 case PTE_NOCACHE: 5712 default: 5713 f1 = 0; 5714 f2l = 0; 5715 f2s = 0; 5716 break; 5717 5718 case PTE_CACHE: 5719 f1 = pte_l1_s_cache_mode; 5720 f2l = pte_l2_l_cache_mode; 5721 f2s = pte_l2_s_cache_mode; 5722 break; 5723 5724 case PTE_PAGETABLE: 5725 f1 = pte_l1_s_cache_mode_pt; 5726 f2l = pte_l2_l_cache_mode_pt; 5727 f2s = pte_l2_s_cache_mode_pt; 5728 break; 5729 } 5730 5731 size = resid; 5732 5733 while (resid > 0) { 5734 #ifdef _ARM_ARCH_6 5735 /* See if we can use a supersection mapping. */ 5736 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 5737 /* Supersection are always domain 0 */ 5738 pd_entry_t pde = L1_SS_PROTO | pa | 5739 L1_S_PROT(PTE_KERNEL, prot) | f1; 5740 #ifdef VERBOSE_INIT_ARM 5741 printf("sS"); 5742 #endif 5743 for (size_t s = va >> L1_S_SHIFT, 5744 e = s + L1_SS_SIZE / L1_S_SIZE; 5745 s < e; 5746 s++) { 5747 pdep[s] = pde; 5748 PTE_SYNC(&pdep[s]); 5749 } 5750 va += L1_SS_SIZE; 5751 pa += L1_SS_SIZE; 5752 resid -= L1_SS_SIZE; 5753 continue; 5754 } 5755 #endif 5756 /* See if we can use a section mapping. */ 5757 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5758 #ifdef VERBOSE_INIT_ARM 5759 printf("S"); 5760 #endif 5761 pdep[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5762 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5763 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5764 PTE_SYNC(&pdep[va >> L1_S_SHIFT]); 5765 va += L1_S_SIZE; 5766 pa += L1_S_SIZE; 5767 resid -= L1_S_SIZE; 5768 continue; 5769 } 5770 5771 /* 5772 * Ok, we're going to use an L2 table. Make sure 5773 * one is actually in the corresponding L1 slot 5774 * for the current VA. 5775 */ 5776 if ((pdep[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5777 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5778 5779 #ifndef ARM32_NEW_VM_LAYOUT 5780 pte = (pt_entry_t *) 5781 kernel_pt_lookup(pdep[va >> L1_S_SHIFT] & L2_S_FRAME); 5782 #else 5783 pte = (pt_entry_t *) kernel_pt_lookup( 5784 pdep[L1_IDX(va)] & L1_C_ADDR_MASK); 5785 #endif 5786 if (pte == NULL) 5787 panic("pmap_map_chunk: can't find L2 table for VA" 5788 "0x%08lx", va); 5789 5790 /* See if we can use a L2 large page mapping. */ 5791 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5792 #ifdef VERBOSE_INIT_ARM 5793 printf("L"); 5794 #endif 5795 for (i = 0; i < 16; i++) { 5796 #ifndef ARM32_NEW_VM_LAYOUT 5797 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5798 L2_L_PROTO | pa | 5799 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5800 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5801 #else 5802 pte[l2pte_index(va) + i] = 5803 L2_L_PROTO | pa | 5804 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5805 PTE_SYNC(&pte[l2pte_index(va) + i]); 5806 #endif 5807 } 5808 va += L2_L_SIZE; 5809 pa += L2_L_SIZE; 5810 resid -= L2_L_SIZE; 5811 continue; 5812 } 5813 5814 /* Use a small page mapping. */ 5815 #ifdef VERBOSE_INIT_ARM 5816 printf("P"); 5817 #endif 5818 #ifndef ARM32_NEW_VM_LAYOUT 5819 pte[(va >> PGSHIFT) & 0x3ff] = 5820 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5821 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5822 #else 5823 pte[l2pte_index(va)] = 5824 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5825 PTE_SYNC(&pte[l2pte_index(va)]); 5826 #endif 5827 va += PAGE_SIZE; 5828 pa += PAGE_SIZE; 5829 resid -= PAGE_SIZE; 5830 } 5831 #ifdef VERBOSE_INIT_ARM 5832 printf("\n"); 5833 #endif 5834 return (size); 5835 } 5836 5837 /********************** Static device map routines ***************************/ 5838 5839 static const struct pmap_devmap *pmap_devmap_table; 5840 5841 /* 5842 * Register the devmap table. This is provided in case early console 5843 * initialization needs to register mappings created by bootstrap code 5844 * before pmap_devmap_bootstrap() is called. 5845 */ 5846 void 5847 pmap_devmap_register(const struct pmap_devmap *table) 5848 { 5849 5850 pmap_devmap_table = table; 5851 } 5852 5853 /* 5854 * Map all of the static regions in the devmap table, and remember 5855 * the devmap table so other parts of the kernel can look up entries 5856 * later. 5857 */ 5858 void 5859 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5860 { 5861 int i; 5862 5863 pmap_devmap_table = table; 5864 5865 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5866 #ifdef VERBOSE_INIT_ARM 5867 printf("devmap: %08lx -> %08lx @ %08lx\n", 5868 pmap_devmap_table[i].pd_pa, 5869 pmap_devmap_table[i].pd_pa + 5870 pmap_devmap_table[i].pd_size - 1, 5871 pmap_devmap_table[i].pd_va); 5872 #endif 5873 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5874 pmap_devmap_table[i].pd_pa, 5875 pmap_devmap_table[i].pd_size, 5876 pmap_devmap_table[i].pd_prot, 5877 pmap_devmap_table[i].pd_cache); 5878 } 5879 } 5880 5881 const struct pmap_devmap * 5882 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5883 { 5884 uint64_t endpa; 5885 int i; 5886 5887 if (pmap_devmap_table == NULL) 5888 return (NULL); 5889 5890 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5891 5892 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5893 if (pa >= pmap_devmap_table[i].pd_pa && 5894 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5895 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5896 return (&pmap_devmap_table[i]); 5897 } 5898 5899 return (NULL); 5900 } 5901 5902 const struct pmap_devmap * 5903 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5904 { 5905 int i; 5906 5907 if (pmap_devmap_table == NULL) 5908 return (NULL); 5909 5910 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5911 if (va >= pmap_devmap_table[i].pd_va && 5912 va + size - 1 <= pmap_devmap_table[i].pd_va + 5913 pmap_devmap_table[i].pd_size - 1) 5914 return (&pmap_devmap_table[i]); 5915 } 5916 5917 return (NULL); 5918 } 5919 5920 /********************** PTE initialization routines **************************/ 5921 5922 /* 5923 * These routines are called when the CPU type is identified to set up 5924 * the PTE prototypes, cache modes, etc. 5925 * 5926 * The variables are always here, just in case modules need to reference 5927 * them (though, they shouldn't). 5928 */ 5929 5930 pt_entry_t pte_l1_s_cache_mode; 5931 pt_entry_t pte_l1_s_wc_mode; 5932 pt_entry_t pte_l1_s_cache_mode_pt; 5933 pt_entry_t pte_l1_s_cache_mask; 5934 5935 pt_entry_t pte_l2_l_cache_mode; 5936 pt_entry_t pte_l2_l_wc_mode; 5937 pt_entry_t pte_l2_l_cache_mode_pt; 5938 pt_entry_t pte_l2_l_cache_mask; 5939 5940 pt_entry_t pte_l2_s_cache_mode; 5941 pt_entry_t pte_l2_s_wc_mode; 5942 pt_entry_t pte_l2_s_cache_mode_pt; 5943 pt_entry_t pte_l2_s_cache_mask; 5944 5945 pt_entry_t pte_l1_s_prot_u; 5946 pt_entry_t pte_l1_s_prot_w; 5947 pt_entry_t pte_l1_s_prot_ro; 5948 pt_entry_t pte_l1_s_prot_mask; 5949 5950 pt_entry_t pte_l2_s_prot_u; 5951 pt_entry_t pte_l2_s_prot_w; 5952 pt_entry_t pte_l2_s_prot_ro; 5953 pt_entry_t pte_l2_s_prot_mask; 5954 5955 pt_entry_t pte_l2_l_prot_u; 5956 pt_entry_t pte_l2_l_prot_w; 5957 pt_entry_t pte_l2_l_prot_ro; 5958 pt_entry_t pte_l2_l_prot_mask; 5959 5960 pt_entry_t pte_l1_ss_proto; 5961 pt_entry_t pte_l1_s_proto; 5962 pt_entry_t pte_l1_c_proto; 5963 pt_entry_t pte_l2_s_proto; 5964 5965 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5966 void (*pmap_zero_page_func)(paddr_t); 5967 5968 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5969 void 5970 pmap_pte_init_generic(void) 5971 { 5972 5973 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5974 pte_l1_s_wc_mode = L1_S_B; 5975 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5976 5977 pte_l2_l_cache_mode = L2_B|L2_C; 5978 pte_l2_l_wc_mode = L2_B; 5979 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5980 5981 pte_l2_s_cache_mode = L2_B|L2_C; 5982 pte_l2_s_wc_mode = L2_B; 5983 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5984 5985 /* 5986 * If we have a write-through cache, set B and C. If 5987 * we have a write-back cache, then we assume setting 5988 * only C will make those pages write-through (except for those 5989 * Cortex CPUs which can read the L1 caches). 5990 */ 5991 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 5992 #if ARM_MMU_V7 > 1 5993 || (CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 5994 && !CPU_ID_CORTEX_A8_P(curcpu()->ci_arm_cpuid)) 5995 #endif 5996 || false) { 5997 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5998 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5999 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6000 #if ARM_MMU_V6 > 1 6001 } else if (CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid)) { 6002 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 6003 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 6004 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 6005 #endif 6006 } else { 6007 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6008 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6009 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6010 } 6011 6012 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6013 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6014 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6015 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6016 6017 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6018 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6019 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6020 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6021 6022 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6023 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6024 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6025 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6026 6027 pte_l1_ss_proto = L1_SS_PROTO_generic; 6028 pte_l1_s_proto = L1_S_PROTO_generic; 6029 pte_l1_c_proto = L1_C_PROTO_generic; 6030 pte_l2_s_proto = L2_S_PROTO_generic; 6031 6032 pmap_copy_page_func = pmap_copy_page_generic; 6033 pmap_zero_page_func = pmap_zero_page_generic; 6034 } 6035 6036 #if defined(CPU_ARM8) 6037 void 6038 pmap_pte_init_arm8(void) 6039 { 6040 6041 /* 6042 * ARM8 is compatible with generic, but we need to use 6043 * the page tables uncached. 6044 */ 6045 pmap_pte_init_generic(); 6046 6047 pte_l1_s_cache_mode_pt = 0; 6048 pte_l2_l_cache_mode_pt = 0; 6049 pte_l2_s_cache_mode_pt = 0; 6050 } 6051 #endif /* CPU_ARM8 */ 6052 6053 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6054 void 6055 pmap_pte_init_arm9(void) 6056 { 6057 6058 /* 6059 * ARM9 is compatible with generic, but we want to use 6060 * write-through caching for now. 6061 */ 6062 pmap_pte_init_generic(); 6063 6064 pte_l1_s_cache_mode = L1_S_C; 6065 pte_l2_l_cache_mode = L2_C; 6066 pte_l2_s_cache_mode = L2_C; 6067 6068 pte_l1_s_wc_mode = L1_S_B; 6069 pte_l2_l_wc_mode = L2_B; 6070 pte_l2_s_wc_mode = L2_B; 6071 6072 pte_l1_s_cache_mode_pt = L1_S_C; 6073 pte_l2_l_cache_mode_pt = L2_C; 6074 pte_l2_s_cache_mode_pt = L2_C; 6075 } 6076 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6077 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6078 6079 #if defined(CPU_ARM10) 6080 void 6081 pmap_pte_init_arm10(void) 6082 { 6083 6084 /* 6085 * ARM10 is compatible with generic, but we want to use 6086 * write-through caching for now. 6087 */ 6088 pmap_pte_init_generic(); 6089 6090 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6091 pte_l2_l_cache_mode = L2_B | L2_C; 6092 pte_l2_s_cache_mode = L2_B | L2_C; 6093 6094 pte_l1_s_cache_mode = L1_S_B; 6095 pte_l2_l_cache_mode = L2_B; 6096 pte_l2_s_cache_mode = L2_B; 6097 6098 pte_l1_s_cache_mode_pt = L1_S_C; 6099 pte_l2_l_cache_mode_pt = L2_C; 6100 pte_l2_s_cache_mode_pt = L2_C; 6101 6102 } 6103 #endif /* CPU_ARM10 */ 6104 6105 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6106 void 6107 pmap_pte_init_arm11(void) 6108 { 6109 6110 /* 6111 * ARM11 is compatible with generic, but we want to use 6112 * write-through caching for now. 6113 */ 6114 pmap_pte_init_generic(); 6115 6116 pte_l1_s_cache_mode = L1_S_C; 6117 pte_l2_l_cache_mode = L2_C; 6118 pte_l2_s_cache_mode = L2_C; 6119 6120 pte_l1_s_wc_mode = L1_S_B; 6121 pte_l2_l_wc_mode = L2_B; 6122 pte_l2_s_wc_mode = L2_B; 6123 6124 pte_l1_s_cache_mode_pt = L1_S_C; 6125 pte_l2_l_cache_mode_pt = L2_C; 6126 pte_l2_s_cache_mode_pt = L2_C; 6127 } 6128 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6129 6130 #if ARM_MMU_SA1 == 1 6131 void 6132 pmap_pte_init_sa1(void) 6133 { 6134 6135 /* 6136 * The StrongARM SA-1 cache does not have a write-through 6137 * mode. So, do the generic initialization, then reset 6138 * the page table cache mode to B=1,C=1, and note that 6139 * the PTEs need to be sync'd. 6140 */ 6141 pmap_pte_init_generic(); 6142 6143 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6144 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6145 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6146 6147 pmap_needs_pte_sync = 1; 6148 } 6149 #endif /* ARM_MMU_SA1 == 1*/ 6150 6151 #if ARM_MMU_XSCALE == 1 6152 #if (ARM_NMMUS > 1) 6153 static u_int xscale_use_minidata; 6154 #endif 6155 6156 void 6157 pmap_pte_init_xscale(void) 6158 { 6159 uint32_t auxctl; 6160 int write_through = 0; 6161 6162 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6163 pte_l1_s_wc_mode = L1_S_B; 6164 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6165 6166 pte_l2_l_cache_mode = L2_B|L2_C; 6167 pte_l2_l_wc_mode = L2_B; 6168 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6169 6170 pte_l2_s_cache_mode = L2_B|L2_C; 6171 pte_l2_s_wc_mode = L2_B; 6172 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6173 6174 pte_l1_s_cache_mode_pt = L1_S_C; 6175 pte_l2_l_cache_mode_pt = L2_C; 6176 pte_l2_s_cache_mode_pt = L2_C; 6177 6178 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6179 /* 6180 * The XScale core has an enhanced mode where writes that 6181 * miss the cache cause a cache line to be allocated. This 6182 * is significantly faster than the traditional, write-through 6183 * behavior of this case. 6184 */ 6185 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6186 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6187 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6188 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6189 6190 #ifdef XSCALE_CACHE_WRITE_THROUGH 6191 /* 6192 * Some versions of the XScale core have various bugs in 6193 * their cache units, the work-around for which is to run 6194 * the cache in write-through mode. Unfortunately, this 6195 * has a major (negative) impact on performance. So, we 6196 * go ahead and run fast-and-loose, in the hopes that we 6197 * don't line up the planets in a way that will trip the 6198 * bugs. 6199 * 6200 * However, we give you the option to be slow-but-correct. 6201 */ 6202 write_through = 1; 6203 #elif defined(XSCALE_CACHE_WRITE_BACK) 6204 /* force write back cache mode */ 6205 write_through = 0; 6206 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6207 /* 6208 * Intel PXA2[15]0 processors are known to have a bug in 6209 * write-back cache on revision 4 and earlier (stepping 6210 * A[01] and B[012]). Fixed for C0 and later. 6211 */ 6212 { 6213 uint32_t id, type; 6214 6215 id = cpufunc_id(); 6216 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6217 6218 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6219 if ((id & CPU_ID_REVISION_MASK) < 5) { 6220 /* write through for stepping A0-1 and B0-2 */ 6221 write_through = 1; 6222 } 6223 } 6224 } 6225 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6226 6227 if (write_through) { 6228 pte_l1_s_cache_mode = L1_S_C; 6229 pte_l2_l_cache_mode = L2_C; 6230 pte_l2_s_cache_mode = L2_C; 6231 } 6232 6233 #if (ARM_NMMUS > 1) 6234 xscale_use_minidata = 1; 6235 #endif 6236 6237 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6238 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6239 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6240 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6241 6242 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6243 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6244 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6245 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6246 6247 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6248 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6249 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6250 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6251 6252 pte_l1_ss_proto = L1_SS_PROTO_xscale; 6253 pte_l1_s_proto = L1_S_PROTO_xscale; 6254 pte_l1_c_proto = L1_C_PROTO_xscale; 6255 pte_l2_s_proto = L2_S_PROTO_xscale; 6256 6257 pmap_copy_page_func = pmap_copy_page_xscale; 6258 pmap_zero_page_func = pmap_zero_page_xscale; 6259 6260 /* 6261 * Disable ECC protection of page table access, for now. 6262 */ 6263 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6264 auxctl &= ~XSCALE_AUXCTL_P; 6265 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6266 } 6267 6268 /* 6269 * xscale_setup_minidata: 6270 * 6271 * Set up the mini-data cache clean area. We require the 6272 * caller to allocate the right amount of physically and 6273 * virtually contiguous space. 6274 */ 6275 void 6276 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6277 { 6278 extern vaddr_t xscale_minidata_clean_addr; 6279 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6280 pd_entry_t *pde = (pd_entry_t *) l1pt; 6281 pt_entry_t *pte; 6282 vsize_t size; 6283 uint32_t auxctl; 6284 6285 xscale_minidata_clean_addr = va; 6286 6287 /* Round it to page size. */ 6288 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6289 6290 for (; size != 0; 6291 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6292 #ifndef ARM32_NEW_VM_LAYOUT 6293 pte = (pt_entry_t *) 6294 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6295 #else 6296 pte = (pt_entry_t *) kernel_pt_lookup( 6297 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6298 #endif 6299 if (pte == NULL) 6300 panic("xscale_setup_minidata: can't find L2 table for " 6301 "VA 0x%08lx", va); 6302 #ifndef ARM32_NEW_VM_LAYOUT 6303 pte[(va >> PGSHIFT) & 0x3ff] = 6304 #else 6305 pte[l2pte_index(va)] = 6306 #endif 6307 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6308 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6309 } 6310 6311 /* 6312 * Configure the mini-data cache for write-back with 6313 * read/write-allocate. 6314 * 6315 * NOTE: In order to reconfigure the mini-data cache, we must 6316 * make sure it contains no valid data! In order to do that, 6317 * we must issue a global data cache invalidate command! 6318 * 6319 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6320 * THIS IS VERY IMPORTANT! 6321 */ 6322 6323 /* Invalidate data and mini-data. */ 6324 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6325 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6326 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6327 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6328 } 6329 6330 /* 6331 * Change the PTEs for the specified kernel mappings such that they 6332 * will use the mini data cache instead of the main data cache. 6333 */ 6334 void 6335 pmap_uarea(vaddr_t va) 6336 { 6337 struct l2_bucket *l2b; 6338 pt_entry_t *ptep, *sptep, pte; 6339 vaddr_t next_bucket, eva; 6340 6341 #if (ARM_NMMUS > 1) 6342 if (xscale_use_minidata == 0) 6343 return; 6344 #endif 6345 6346 eva = va + USPACE; 6347 6348 while (va < eva) { 6349 next_bucket = L2_NEXT_BUCKET(va); 6350 if (next_bucket > eva) 6351 next_bucket = eva; 6352 6353 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6354 KDASSERT(l2b != NULL); 6355 6356 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6357 6358 while (va < next_bucket) { 6359 pte = *ptep; 6360 if (!l2pte_minidata(pte)) { 6361 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6362 cpu_tlb_flushD_SE(va); 6363 *ptep = pte & ~L2_B; 6364 } 6365 ptep++; 6366 va += PAGE_SIZE; 6367 } 6368 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6369 } 6370 cpu_cpwait(); 6371 } 6372 #endif /* ARM_MMU_XSCALE == 1 */ 6373 6374 6375 #if defined(CPU_ARM11MPCORE) 6376 6377 void 6378 pmap_pte_init_arm11mpcore(void) 6379 { 6380 6381 /* cache mode is controlled by 5 bits (B, C, TEX) */ 6382 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 6383 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 6384 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6385 /* use extended small page (without APn, with TEX) */ 6386 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 6387 #else 6388 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 6389 #endif 6390 6391 /* write-back, write-allocate */ 6392 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6393 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 6394 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6395 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6396 #else 6397 /* no TEX. read-allocate */ 6398 pte_l2_s_cache_mode = L2_C | L2_B; 6399 #endif 6400 /* 6401 * write-back, write-allocate for page tables. 6402 */ 6403 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6404 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 6405 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6406 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6407 #else 6408 pte_l2_s_cache_mode_pt = L2_C | L2_B; 6409 #endif 6410 6411 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 6412 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 6413 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 6414 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 6415 6416 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6417 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 6418 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 6419 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 6420 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 6421 6422 #else 6423 /* with AP[0..3] */ 6424 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6425 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6426 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6427 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6428 #endif 6429 6430 #ifdef ARM11MPCORE_COMPAT_MMU 6431 /* with AP[0..3] */ 6432 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6433 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6434 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6435 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6436 6437 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6438 pte_l1_s_proto = L1_S_PROTO_armv6; 6439 pte_l1_c_proto = L1_C_PROTO_armv6; 6440 pte_l2_s_proto = L2_S_PROTO_armv6c; 6441 #else 6442 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 6443 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 6444 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 6445 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 6446 6447 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6448 pte_l1_s_proto = L1_S_PROTO_armv6; 6449 pte_l1_c_proto = L1_C_PROTO_armv6; 6450 pte_l2_s_proto = L2_S_PROTO_armv6n; 6451 #endif 6452 6453 pmap_copy_page_func = pmap_copy_page_generic; 6454 pmap_zero_page_func = pmap_zero_page_generic; 6455 pmap_needs_pte_sync = 1; 6456 } 6457 #endif /* CPU_ARM11MPCORE */ 6458 6459 6460 #if ARM_MMU_V7 == 1 6461 void 6462 pmap_pte_init_armv7(void) 6463 { 6464 /* 6465 * The ARMv7-A MMU is mostly compatible with generic. If the 6466 * AP field is zero, that now means "no access" rather than 6467 * read-only. The prototypes are a little different because of 6468 * the XN bit. 6469 */ 6470 pmap_pte_init_generic(); 6471 6472 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6473 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6474 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6475 6476 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6477 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6478 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6479 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6480 6481 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6482 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6483 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6484 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6485 6486 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6487 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6488 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6489 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6490 6491 pte_l1_ss_proto = L1_SS_PROTO_armv7; 6492 pte_l1_s_proto = L1_S_PROTO_armv7; 6493 pte_l1_c_proto = L1_C_PROTO_armv7; 6494 pte_l2_s_proto = L2_S_PROTO_armv7; 6495 } 6496 #endif /* ARM_MMU_V7 */ 6497 6498 /* 6499 * return the PA of the current L1 table, for use when handling a crash dump 6500 */ 6501 uint32_t pmap_kernel_L1_addr(void) 6502 { 6503 return pmap_kernel()->pm_l1->l1_physaddr; 6504 } 6505 6506 #if defined(DDB) 6507 /* 6508 * A couple of ddb-callable functions for dumping pmaps 6509 */ 6510 void pmap_dump_all(void); 6511 void pmap_dump(pmap_t); 6512 6513 void 6514 pmap_dump_all(void) 6515 { 6516 pmap_t pm; 6517 6518 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6519 if (pm == pmap_kernel()) 6520 continue; 6521 pmap_dump(pm); 6522 printf("\n"); 6523 } 6524 } 6525 6526 static pt_entry_t ncptes[64]; 6527 static void pmap_dump_ncpg(pmap_t); 6528 6529 void 6530 pmap_dump(pmap_t pm) 6531 { 6532 struct l2_dtable *l2; 6533 struct l2_bucket *l2b; 6534 pt_entry_t *ptep, pte; 6535 vaddr_t l2_va, l2b_va, va; 6536 int i, j, k, occ, rows = 0; 6537 6538 if (pm == pmap_kernel()) 6539 printf("pmap_kernel (%p): ", pm); 6540 else 6541 printf("user pmap (%p): ", pm); 6542 6543 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6544 6545 l2_va = 0; 6546 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6547 l2 = pm->pm_l2[i]; 6548 6549 if (l2 == NULL || l2->l2_occupancy == 0) 6550 continue; 6551 6552 l2b_va = l2_va; 6553 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6554 l2b = &l2->l2_bucket[j]; 6555 6556 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6557 continue; 6558 6559 ptep = l2b->l2b_kva; 6560 6561 for (k = 0; k < 256 && ptep[k] == 0; k++) 6562 ; 6563 6564 k &= ~63; 6565 occ = l2b->l2b_occupancy; 6566 va = l2b_va + (k * 4096); 6567 for (; k < 256; k++, va += 0x1000) { 6568 char ch = ' '; 6569 if ((k % 64) == 0) { 6570 if ((rows % 8) == 0) { 6571 printf( 6572 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6573 } 6574 printf("%08lx: ", va); 6575 } 6576 6577 ncptes[k & 63] = 0; 6578 pte = ptep[k]; 6579 if (pte == 0) { 6580 ch = '.'; 6581 } else { 6582 occ--; 6583 switch (pte & 0x0c) { 6584 case 0x00: 6585 ch = 'D'; /* No cache No buff */ 6586 break; 6587 case 0x04: 6588 ch = 'B'; /* No cache buff */ 6589 break; 6590 case 0x08: 6591 if (pte & 0x40) 6592 ch = 'm'; 6593 else 6594 ch = 'C'; /* Cache No buff */ 6595 break; 6596 case 0x0c: 6597 ch = 'F'; /* Cache Buff */ 6598 break; 6599 } 6600 6601 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6602 ch += 0x20; 6603 6604 if ((pte & 0xc) == 0) 6605 ncptes[k & 63] = pte; 6606 } 6607 6608 if ((k % 64) == 63) { 6609 rows++; 6610 printf("%c\n", ch); 6611 pmap_dump_ncpg(pm); 6612 if (occ == 0) 6613 break; 6614 } else 6615 printf("%c", ch); 6616 } 6617 } 6618 } 6619 } 6620 6621 static void 6622 pmap_dump_ncpg(pmap_t pm) 6623 { 6624 struct vm_page *pg; 6625 struct vm_page_md *md; 6626 struct pv_entry *pv; 6627 int i; 6628 6629 for (i = 0; i < 63; i++) { 6630 if (ncptes[i] == 0) 6631 continue; 6632 6633 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6634 if (pg == NULL) 6635 continue; 6636 md = VM_PAGE_TO_MD(pg); 6637 6638 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6639 VM_PAGE_TO_PHYS(pg), 6640 md->krw_mappings, md->kro_mappings, 6641 md->urw_mappings, md->uro_mappings); 6642 6643 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6644 printf(" %c va 0x%08lx, flags 0x%x\n", 6645 (pm == pv->pv_pmap) ? '*' : ' ', 6646 pv->pv_va, pv->pv_flags); 6647 } 6648 } 6649 } 6650 #endif 6651 6652 #ifdef PMAP_STEAL_MEMORY 6653 void 6654 pmap_boot_pageadd(pv_addr_t *newpv) 6655 { 6656 pv_addr_t *pv, *npv; 6657 6658 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6659 if (newpv->pv_pa < pv->pv_va) { 6660 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6661 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6662 newpv->pv_size += pv->pv_size; 6663 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6664 } 6665 pv = NULL; 6666 } else { 6667 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6668 pv = npv) { 6669 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6670 KASSERT(pv->pv_pa < newpv->pv_pa); 6671 if (newpv->pv_pa > npv->pv_pa) 6672 continue; 6673 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6674 pv->pv_size += newpv->pv_size; 6675 return; 6676 } 6677 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6678 break; 6679 newpv->pv_size += npv->pv_size; 6680 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6681 SLIST_REMOVE_AFTER(newpv, pv_list); 6682 return; 6683 } 6684 } 6685 } 6686 6687 if (pv) { 6688 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6689 } else { 6690 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6691 } 6692 } 6693 6694 void 6695 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6696 pv_addr_t *rpv) 6697 { 6698 pv_addr_t *pv, **pvp; 6699 struct vm_physseg *ps; 6700 size_t i; 6701 6702 KASSERT(amount & PGOFSET); 6703 KASSERT((mask & PGOFSET) == 0); 6704 KASSERT((match & PGOFSET) == 0); 6705 KASSERT(amount != 0); 6706 6707 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6708 (pv = *pvp) != NULL; 6709 pvp = &SLIST_NEXT(pv, pv_list)) { 6710 pv_addr_t *newpv; 6711 psize_t off; 6712 /* 6713 * If this entry is too small to satify the request... 6714 */ 6715 KASSERT(pv->pv_size > 0); 6716 if (pv->pv_size < amount) 6717 continue; 6718 6719 for (off = 0; off <= mask; off += PAGE_SIZE) { 6720 if (((pv->pv_pa + off) & mask) == match 6721 && off + amount <= pv->pv_size) 6722 break; 6723 } 6724 if (off > mask) 6725 continue; 6726 6727 rpv->pv_va = pv->pv_va + off; 6728 rpv->pv_pa = pv->pv_pa + off; 6729 rpv->pv_size = amount; 6730 pv->pv_size -= amount; 6731 if (pv->pv_size == 0) { 6732 KASSERT(off == 0); 6733 KASSERT((vaddr_t) pv == rpv->pv_va); 6734 *pvp = SLIST_NEXT(pv, pv_list); 6735 } else if (off == 0) { 6736 KASSERT((vaddr_t) pv == rpv->pv_va); 6737 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6738 *newpv = *pv; 6739 newpv->pv_pa += amount; 6740 newpv->pv_va += amount; 6741 *pvp = newpv; 6742 } else if (off < pv->pv_size) { 6743 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6744 *newpv = *pv; 6745 newpv->pv_size -= off; 6746 newpv->pv_pa += off + amount; 6747 newpv->pv_va += off + amount; 6748 6749 SLIST_NEXT(pv, pv_list) = newpv; 6750 pv->pv_size = off; 6751 } else { 6752 KASSERT((vaddr_t) pv != rpv->pv_va); 6753 } 6754 memset((void *)rpv->pv_va, 0, amount); 6755 return; 6756 } 6757 6758 if (vm_nphysseg == 0) 6759 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6760 6761 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6762 (pv = *pvp) != NULL; 6763 pvp = &SLIST_NEXT(pv, pv_list)) { 6764 if (SLIST_NEXT(pv, pv_list) == NULL) 6765 break; 6766 } 6767 KASSERT(mask == 0); 6768 for (i = 0; i < vm_nphysseg; i++) { 6769 ps = VM_PHYSMEM_PTR(i); 6770 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6771 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6772 rpv->pv_va = pv->pv_va; 6773 rpv->pv_pa = pv->pv_pa; 6774 rpv->pv_size = amount; 6775 *pvp = NULL; 6776 pmap_map_chunk(kernel_l1pt.pv_va, 6777 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6778 ptoa(ps->avail_start), 6779 amount - pv->pv_size, 6780 VM_PROT_READ|VM_PROT_WRITE, 6781 PTE_CACHE); 6782 ps->avail_start += atop(amount - pv->pv_size); 6783 /* 6784 * If we consumed the entire physseg, remove it. 6785 */ 6786 if (ps->avail_start == ps->avail_end) { 6787 for (--vm_nphysseg; i < vm_nphysseg; i++) 6788 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6789 } 6790 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6791 return; 6792 } 6793 } 6794 6795 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6796 } 6797 6798 vaddr_t 6799 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6800 { 6801 pv_addr_t pv; 6802 6803 pmap_boot_pagealloc(size, 0, 0, &pv); 6804 6805 return pv.pv_va; 6806 } 6807 #endif /* PMAP_STEAL_MEMORY */ 6808 6809 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6810 { 6811 sysctl_createv(clog, 0, NULL, NULL, 6812 CTLFLAG_PERMANENT, 6813 CTLTYPE_NODE, "machdep", NULL, 6814 NULL, 0, NULL, 0, 6815 CTL_MACHDEP, CTL_EOL); 6816 6817 sysctl_createv(clog, 0, NULL, NULL, 6818 CTLFLAG_PERMANENT, 6819 CTLTYPE_INT, "kmpages", 6820 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6821 NULL, 0, &pmap_kmpages, 0, 6822 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6823 } 6824
Indexes created Mon Sep 29 21:09:56 GMT 2025