pmap.c revision 1.243
1 /* $NetBSD: pmap.c,v 1.243 2012/12/10 06:54:23 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/pool.h> 201 #include <sys/kmem.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <sys/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/cpuconf.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.243 2012/12/10 06:54:23 matt Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 #define PDB_EXEC 0x80000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 static struct pmap kernel_pmap_store; 259 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 260 #ifdef PMAP_NEED_ALLOC_POOLPAGE 261 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 262 #endif 263 264 /* 265 * Which pmap is currently 'live' in the cache 266 * 267 * XXXSCW: Fix for SMP ... 268 */ 269 static pmap_t pmap_recent_user; 270 271 /* 272 * Pointer to last active lwp, or NULL if it exited. 273 */ 274 struct lwp *pmap_previous_active_lwp; 275 276 /* 277 * Pool and cache that pmap structures are allocated from. 278 * We use a cache to avoid clearing the pm_l2[] array (1KB) 279 * in pmap_create(). 280 */ 281 static struct pool_cache pmap_cache; 282 static LIST_HEAD(, pmap) pmap_pmaps; 283 284 /* 285 * Pool of PV structures 286 */ 287 static struct pool pmap_pv_pool; 288 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 289 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 290 static struct pool_allocator pmap_bootstrap_pv_allocator = { 291 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 292 }; 293 294 /* 295 * Pool and cache of l2_dtable structures. 296 * We use a cache to avoid clearing the structures when they're 297 * allocated. (196 bytes) 298 */ 299 static struct pool_cache pmap_l2dtable_cache; 300 static vaddr_t pmap_kernel_l2dtable_kva; 301 302 /* 303 * Pool and cache of L2 page descriptors. 304 * We use a cache to avoid clearing the descriptor table 305 * when they're allocated. (1KB) 306 */ 307 static struct pool_cache pmap_l2ptp_cache; 308 static vaddr_t pmap_kernel_l2ptp_kva; 309 static paddr_t pmap_kernel_l2ptp_phys; 310 311 #ifdef PMAPCOUNTERS 312 #define PMAP_EVCNT_INITIALIZER(name) \ 313 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 314 315 #ifdef PMAP_CACHE_VIPT 316 static struct evcnt pmap_ev_vac_clean_one = 317 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_one = 319 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_lots = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 322 static struct evcnt pmap_ev_vac_flush_lots2 = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 328 329 static struct evcnt pmap_ev_vac_color_new = 330 PMAP_EVCNT_INITIALIZER("new page color"); 331 static struct evcnt pmap_ev_vac_color_reuse = 332 PMAP_EVCNT_INITIALIZER("ok first page color"); 333 static struct evcnt pmap_ev_vac_color_ok = 334 PMAP_EVCNT_INITIALIZER("ok page color"); 335 static struct evcnt pmap_ev_vac_color_blind = 336 PMAP_EVCNT_INITIALIZER("blind page color"); 337 static struct evcnt pmap_ev_vac_color_change = 338 PMAP_EVCNT_INITIALIZER("change page color"); 339 static struct evcnt pmap_ev_vac_color_erase = 340 PMAP_EVCNT_INITIALIZER("erase page color"); 341 static struct evcnt pmap_ev_vac_color_none = 342 PMAP_EVCNT_INITIALIZER("no page color"); 343 static struct evcnt pmap_ev_vac_color_restore = 344 PMAP_EVCNT_INITIALIZER("restore page color"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 354 #endif 355 356 static struct evcnt pmap_ev_mappings = 357 PMAP_EVCNT_INITIALIZER("pages mapped"); 358 static struct evcnt pmap_ev_unmappings = 359 PMAP_EVCNT_INITIALIZER("pages unmapped"); 360 static struct evcnt pmap_ev_remappings = 361 PMAP_EVCNT_INITIALIZER("pages remapped"); 362 363 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 364 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 366 367 static struct evcnt pmap_ev_kernel_mappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 369 static struct evcnt pmap_ev_kernel_unmappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 371 static struct evcnt pmap_ev_kernel_remappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 373 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 377 378 static struct evcnt pmap_ev_kenter_mappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 380 static struct evcnt pmap_ev_kenter_unmappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 382 static struct evcnt pmap_ev_kenter_remappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 384 static struct evcnt pmap_ev_pt_mappings = 385 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 391 392 #ifdef PMAP_CACHE_VIPT 393 static struct evcnt pmap_ev_exec_mappings = 394 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 395 static struct evcnt pmap_ev_exec_cached = 396 PMAP_EVCNT_INITIALIZER("exec pages cached"); 397 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 399 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 400 401 static struct evcnt pmap_ev_exec_synced = 402 PMAP_EVCNT_INITIALIZER("exec pages synced"); 403 static struct evcnt pmap_ev_exec_synced_map = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 405 static struct evcnt pmap_ev_exec_synced_unmap = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 407 static struct evcnt pmap_ev_exec_synced_remap = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 409 static struct evcnt pmap_ev_exec_synced_clearbit = 410 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 411 static struct evcnt pmap_ev_exec_synced_kremove = 412 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 413 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 420 421 static struct evcnt pmap_ev_exec_discarded_unmap = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 423 static struct evcnt pmap_ev_exec_discarded_zero = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 425 static struct evcnt pmap_ev_exec_discarded_copy = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 427 static struct evcnt pmap_ev_exec_discarded_page_protect = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 429 static struct evcnt pmap_ev_exec_discarded_clearbit = 430 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 431 static struct evcnt pmap_ev_exec_discarded_kremove = 432 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 433 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 440 #endif /* PMAP_CACHE_VIPT */ 441 442 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 443 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 444 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 445 446 EVCNT_ATTACH_STATIC(pmap_ev_updates); 447 EVCNT_ATTACH_STATIC(pmap_ev_collects); 448 EVCNT_ATTACH_STATIC(pmap_ev_activations); 449 450 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 451 #else 452 #define PMAPCOUNT(x) ((void)0) 453 #endif 454 455 /* 456 * pmap copy/zero page, and mem(5) hook point 457 */ 458 static pt_entry_t *csrc_pte, *cdst_pte; 459 static vaddr_t csrcp, cdstp; 460 vaddr_t memhook; /* used by mem.c */ 461 kmutex_t memlock; /* used by mem.c */ 462 void *zeropage; /* used by mem.c */ 463 extern void *msgbufaddr; 464 int pmap_kmpages; 465 /* 466 * Flag to indicate if pmap_init() has done its thing 467 */ 468 bool pmap_initialized; 469 470 /* 471 * Misc. locking data structures 472 */ 473 474 #define pmap_acquire_pmap_lock(pm) \ 475 do { \ 476 if ((pm) != pmap_kernel()) \ 477 mutex_enter((pm)->pm_lock); \ 478 } while (/*CONSTCOND*/0) 479 480 #define pmap_release_pmap_lock(pm) \ 481 do { \ 482 if ((pm) != pmap_kernel()) \ 483 mutex_exit((pm)->pm_lock); \ 484 } while (/*CONSTCOND*/0) 485 486 487 /* 488 * Metadata for L1 translation tables. 489 */ 490 struct l1_ttable { 491 /* Entry on the L1 Table list */ 492 SLIST_ENTRY(l1_ttable) l1_link; 493 494 /* Entry on the L1 Least Recently Used list */ 495 TAILQ_ENTRY(l1_ttable) l1_lru; 496 497 /* Track how many domains are allocated from this L1 */ 498 volatile u_int l1_domain_use_count; 499 500 /* 501 * A free-list of domain numbers for this L1. 502 * We avoid using ffs() and a bitmap to track domains since ffs() 503 * is slow on ARM. 504 */ 505 uint8_t l1_domain_first; 506 uint8_t l1_domain_free[PMAP_DOMAINS]; 507 508 /* Physical address of this L1 page table */ 509 paddr_t l1_physaddr; 510 511 /* KVA of this L1 page table */ 512 pd_entry_t *l1_kva; 513 }; 514 515 /* 516 * Convert a virtual address into its L1 table index. That is, the 517 * index used to locate the L2 descriptor table pointer in an L1 table. 518 * This is basically used to index l1->l1_kva[]. 519 * 520 * Each L2 descriptor table represents 1MB of VA space. 521 */ 522 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 523 524 /* 525 * L1 Page Tables are tracked using a Least Recently Used list. 526 * - New L1s are allocated from the HEAD. 527 * - Freed L1s are added to the TAIl. 528 * - Recently accessed L1s (where an 'access' is some change to one of 529 * the userland pmaps which owns this L1) are moved to the TAIL. 530 */ 531 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 532 static kmutex_t l1_lru_lock __cacheline_aligned; 533 534 /* 535 * A list of all L1 tables 536 */ 537 static SLIST_HEAD(, l1_ttable) l1_list; 538 539 /* 540 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 541 * 542 * This is normally 16MB worth L2 page descriptors for any given pmap. 543 * Reference counts are maintained for L2 descriptors so they can be 544 * freed when empty. 545 */ 546 struct l2_dtable { 547 /* The number of L2 page descriptors allocated to this l2_dtable */ 548 u_int l2_occupancy; 549 550 /* List of L2 page descriptors */ 551 struct l2_bucket { 552 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 553 paddr_t l2b_phys; /* Physical address of same */ 554 u_short l2b_l1idx; /* This L2 table's L1 index */ 555 u_short l2b_occupancy; /* How many active descriptors */ 556 } l2_bucket[L2_BUCKET_SIZE]; 557 }; 558 559 /* 560 * Given an L1 table index, calculate the corresponding l2_dtable index 561 * and bucket index within the l2_dtable. 562 */ 563 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 564 (L2_SIZE - 1)) 565 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 566 567 /* 568 * Given a virtual address, this macro returns the 569 * virtual address required to drop into the next L2 bucket. 570 */ 571 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 572 573 /* 574 * L2 allocation. 575 */ 576 #define pmap_alloc_l2_dtable() \ 577 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 578 #define pmap_free_l2_dtable(l2) \ 579 pool_cache_put(&pmap_l2dtable_cache, (l2)) 580 #define pmap_alloc_l2_ptp(pap) \ 581 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 582 PR_NOWAIT, (pap))) 583 584 /* 585 * We try to map the page tables write-through, if possible. However, not 586 * all CPUs have a write-through cache mode, so on those we have to sync 587 * the cache when we frob page tables. 588 * 589 * We try to evaluate this at compile time, if possible. However, it's 590 * not always possible to do that, hence this run-time var. 591 */ 592 int pmap_needs_pte_sync; 593 594 /* 595 * Real definition of pv_entry. 596 */ 597 struct pv_entry { 598 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 599 pmap_t pv_pmap; /* pmap where mapping lies */ 600 vaddr_t pv_va; /* virtual address for mapping */ 601 u_int pv_flags; /* flags */ 602 }; 603 604 /* 605 * Macro to determine if a mapping might be resident in the 606 * instruction cache and/or TLB 607 */ 608 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 609 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 610 611 /* 612 * Macro to determine if a mapping might be resident in the 613 * data cache and/or TLB 614 */ 615 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 616 617 /* 618 * Local prototypes 619 */ 620 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 621 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 622 pt_entry_t **); 623 static bool pmap_is_current(pmap_t); 624 static bool pmap_is_cached(pmap_t); 625 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 626 pmap_t, vaddr_t, u_int); 627 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 628 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 629 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 630 u_int, u_int); 631 632 static void pmap_pinit(pmap_t); 633 static int pmap_pmap_ctor(void *, void *, int); 634 635 static void pmap_alloc_l1(pmap_t); 636 static void pmap_free_l1(pmap_t); 637 static void pmap_use_l1(pmap_t); 638 639 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 640 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 641 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 642 static int pmap_l2ptp_ctor(void *, void *, int); 643 static int pmap_l2dtable_ctor(void *, void *, int); 644 645 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 646 #ifdef PMAP_CACHE_VIVT 647 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 648 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 649 #endif 650 651 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 652 #ifdef PMAP_CACHE_VIVT 653 static int pmap_clean_page(struct pv_entry *, bool); 654 #endif 655 #ifdef PMAP_CACHE_VIPT 656 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 657 enum pmap_flush_op { 658 PMAP_FLUSH_PRIMARY, 659 PMAP_FLUSH_SECONDARY, 660 PMAP_CLEAN_PRIMARY 661 }; 662 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 663 #endif 664 static void pmap_page_remove(struct vm_page_md *, paddr_t); 665 666 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 667 static vaddr_t kernel_pt_lookup(paddr_t); 668 669 670 /* 671 * External function prototypes 672 */ 673 extern void bzero_page(vaddr_t); 674 extern void bcopy_page(vaddr_t, vaddr_t); 675 676 /* 677 * Misc variables 678 */ 679 vaddr_t virtual_avail; 680 vaddr_t virtual_end; 681 vaddr_t pmap_curmaxkvaddr; 682 683 paddr_t avail_start; 684 paddr_t avail_end; 685 686 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 687 pv_addr_t kernelpages; 688 pv_addr_t kernel_l1pt; 689 pv_addr_t systempage; 690 691 /* Function to set the debug level of the pmap code */ 692 693 #ifdef PMAP_DEBUG 694 void 695 pmap_debug(int level) 696 { 697 pmap_debug_level = level; 698 printf("pmap_debug: level=%d\n", pmap_debug_level); 699 } 700 #endif /* PMAP_DEBUG */ 701 702 /* 703 * A bunch of routines to conditionally flush the caches/TLB depending 704 * on whether the specified pmap actually needs to be flushed at any 705 * given time. 706 */ 707 static inline void 708 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 709 { 710 711 if (pm->pm_cstate.cs_tlb_id) 712 cpu_tlb_flushID_SE(va); 713 } 714 715 static inline void 716 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 717 { 718 719 if (pm->pm_cstate.cs_tlb_d) 720 cpu_tlb_flushD_SE(va); 721 } 722 723 static inline void 724 pmap_tlb_flushID(pmap_t pm) 725 { 726 727 if (pm->pm_cstate.cs_tlb_id) { 728 cpu_tlb_flushID(); 729 pm->pm_cstate.cs_tlb = 0; 730 } 731 } 732 733 static inline void 734 pmap_tlb_flushD(pmap_t pm) 735 { 736 737 if (pm->pm_cstate.cs_tlb_d) { 738 cpu_tlb_flushD(); 739 pm->pm_cstate.cs_tlb_d = 0; 740 } 741 } 742 743 #ifdef PMAP_CACHE_VIVT 744 static inline void 745 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 746 { 747 if (pm->pm_cstate.cs_cache_id) { 748 cpu_idcache_wbinv_range(va, len); 749 } 750 } 751 752 static inline void 753 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 754 bool do_inv, bool rd_only) 755 { 756 757 if (pm->pm_cstate.cs_cache_d) { 758 if (do_inv) { 759 if (rd_only) 760 cpu_dcache_inv_range(va, len); 761 else 762 cpu_dcache_wbinv_range(va, len); 763 } else 764 if (!rd_only) 765 cpu_dcache_wb_range(va, len); 766 } 767 } 768 769 static inline void 770 pmap_idcache_wbinv_all(pmap_t pm) 771 { 772 if (pm->pm_cstate.cs_cache_id) { 773 cpu_idcache_wbinv_all(); 774 pm->pm_cstate.cs_cache = 0; 775 } 776 } 777 778 static inline void 779 pmap_dcache_wbinv_all(pmap_t pm) 780 { 781 if (pm->pm_cstate.cs_cache_d) { 782 cpu_dcache_wbinv_all(); 783 pm->pm_cstate.cs_cache_d = 0; 784 } 785 } 786 #endif /* PMAP_CACHE_VIVT */ 787 788 static inline bool 789 pmap_is_current(pmap_t pm) 790 { 791 792 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 793 return true; 794 795 return false; 796 } 797 798 static inline bool 799 pmap_is_cached(pmap_t pm) 800 { 801 802 if (pm == pmap_kernel() || pmap_recent_user == NULL || 803 pmap_recent_user == pm) 804 return (true); 805 806 return false; 807 } 808 809 /* 810 * PTE_SYNC_CURRENT: 811 * 812 * Make sure the pte is written out to RAM. 813 * We need to do this for one of two cases: 814 * - We're dealing with the kernel pmap 815 * - There is no pmap active in the cache/tlb. 816 * - The specified pmap is 'active' in the cache/tlb. 817 */ 818 #ifdef PMAP_INCLUDE_PTE_SYNC 819 #define PTE_SYNC_CURRENT(pm, ptep) \ 820 do { \ 821 if (PMAP_NEEDS_PTE_SYNC && \ 822 pmap_is_cached(pm)) \ 823 PTE_SYNC(ptep); \ 824 } while (/*CONSTCOND*/0) 825 #else 826 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 827 #endif 828 829 /* 830 * main pv_entry manipulation functions: 831 * pmap_enter_pv: enter a mapping onto a vm_page list 832 * pmap_remove_pv: remove a mappiing from a vm_page list 833 * 834 * NOTE: pmap_enter_pv expects to lock the pvh itself 835 * pmap_remove_pv expects te caller to lock the pvh before calling 836 */ 837 838 /* 839 * pmap_enter_pv: enter a mapping onto a vm_page lst 840 * 841 * => caller should hold the proper lock on pmap_main_lock 842 * => caller should have pmap locked 843 * => we will gain the lock on the vm_page and allocate the new pv_entry 844 * => caller should adjust ptp's wire_count before calling 845 * => caller should not adjust pmap's wire_count 846 */ 847 static void 848 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 849 vaddr_t va, u_int flags) 850 { 851 struct pv_entry **pvp; 852 853 NPDEBUG(PDB_PVDUMP, 854 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 855 856 pv->pv_pmap = pm; 857 pv->pv_va = va; 858 pv->pv_flags = flags; 859 860 pvp = &SLIST_FIRST(&md->pvh_list); 861 #ifdef PMAP_CACHE_VIPT 862 /* 863 * Insert unmanaged entries, writeable first, at the head of 864 * the pv list. 865 */ 866 if (__predict_true((flags & PVF_KENTRY) == 0)) { 867 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 868 pvp = &SLIST_NEXT(*pvp, pv_link); 869 } else if ((flags & PVF_WRITE) == 0) { 870 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 871 pvp = &SLIST_NEXT(*pvp, pv_link); 872 } 873 #endif 874 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 875 *pvp = pv; /* ... locked list */ 876 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 877 #ifdef PMAP_CACHE_VIPT 878 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 879 md->pvh_attrs |= PVF_KMOD; 880 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 881 md->pvh_attrs |= PVF_DIRTY; 882 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 883 #endif 884 if (pm == pmap_kernel()) { 885 PMAPCOUNT(kernel_mappings); 886 if (flags & PVF_WRITE) 887 md->krw_mappings++; 888 else 889 md->kro_mappings++; 890 } else { 891 if (flags & PVF_WRITE) 892 md->urw_mappings++; 893 else 894 md->uro_mappings++; 895 } 896 897 #ifdef PMAP_CACHE_VIPT 898 /* 899 * If this is an exec mapping and its the first exec mapping 900 * for this page, make sure to sync the I-cache. 901 */ 902 if (PV_IS_EXEC_P(flags)) { 903 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 904 pmap_syncicache_page(md, pa); 905 PMAPCOUNT(exec_synced_map); 906 } 907 PMAPCOUNT(exec_mappings); 908 } 909 #endif 910 911 PMAPCOUNT(mappings); 912 913 if (pv->pv_flags & PVF_WIRED) 914 ++pm->pm_stats.wired_count; 915 } 916 917 /* 918 * 919 * pmap_find_pv: Find a pv entry 920 * 921 * => caller should hold lock on vm_page 922 */ 923 static inline struct pv_entry * 924 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 925 { 926 struct pv_entry *pv; 927 928 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 929 if (pm == pv->pv_pmap && va == pv->pv_va) 930 break; 931 } 932 933 return (pv); 934 } 935 936 /* 937 * pmap_remove_pv: try to remove a mapping from a pv_list 938 * 939 * => caller should hold proper lock on pmap_main_lock 940 * => pmap should be locked 941 * => caller should hold lock on vm_page [so that attrs can be adjusted] 942 * => caller should adjust ptp's wire_count and free PTP if needed 943 * => caller should NOT adjust pmap's wire_count 944 * => we return the removed pv 945 */ 946 static struct pv_entry * 947 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 948 { 949 struct pv_entry *pv, **prevptr; 950 951 NPDEBUG(PDB_PVDUMP, 952 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 953 954 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 955 pv = *prevptr; 956 957 while (pv) { 958 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 959 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 960 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 961 if (pv->pv_flags & PVF_WIRED) { 962 --pm->pm_stats.wired_count; 963 } 964 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 965 if (pm == pmap_kernel()) { 966 PMAPCOUNT(kernel_unmappings); 967 if (pv->pv_flags & PVF_WRITE) 968 md->krw_mappings--; 969 else 970 md->kro_mappings--; 971 } else { 972 if (pv->pv_flags & PVF_WRITE) 973 md->urw_mappings--; 974 else 975 md->uro_mappings--; 976 } 977 978 PMAPCOUNT(unmappings); 979 #ifdef PMAP_CACHE_VIPT 980 if (!(pv->pv_flags & PVF_WRITE)) 981 break; 982 /* 983 * If this page has had an exec mapping, then if 984 * this was the last mapping, discard the contents, 985 * otherwise sync the i-cache for this page. 986 */ 987 if (PV_IS_EXEC_P(md->pvh_attrs)) { 988 if (SLIST_EMPTY(&md->pvh_list)) { 989 md->pvh_attrs &= ~PVF_EXEC; 990 PMAPCOUNT(exec_discarded_unmap); 991 } else { 992 pmap_syncicache_page(md, pa); 993 PMAPCOUNT(exec_synced_unmap); 994 } 995 } 996 #endif /* PMAP_CACHE_VIPT */ 997 break; 998 } 999 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1000 pv = *prevptr; /* advance */ 1001 } 1002 1003 #ifdef PMAP_CACHE_VIPT 1004 /* 1005 * If we no longer have a WRITEABLE KENTRY at the head of list, 1006 * clear the KMOD attribute from the page. 1007 */ 1008 if (SLIST_FIRST(&md->pvh_list) == NULL 1009 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1010 md->pvh_attrs &= ~PVF_KMOD; 1011 1012 /* 1013 * If this was a writeable page and there are no more writeable 1014 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1015 * the contents to memory. 1016 */ 1017 if (md->krw_mappings + md->urw_mappings == 0) 1018 md->pvh_attrs &= ~PVF_WRITE; 1019 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1020 #endif /* PMAP_CACHE_VIPT */ 1021 1022 return(pv); /* return removed pv */ 1023 } 1024 1025 /* 1026 * 1027 * pmap_modify_pv: Update pv flags 1028 * 1029 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1030 * => caller should NOT adjust pmap's wire_count 1031 * => caller must call pmap_vac_me_harder() if writable status of a page 1032 * may have changed. 1033 * => we return the old flags 1034 * 1035 * Modify a physical-virtual mapping in the pv table 1036 */ 1037 static u_int 1038 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1039 u_int clr_mask, u_int set_mask) 1040 { 1041 struct pv_entry *npv; 1042 u_int flags, oflags; 1043 1044 KASSERT((clr_mask & PVF_KENTRY) == 0); 1045 KASSERT((set_mask & PVF_KENTRY) == 0); 1046 1047 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1048 return (0); 1049 1050 NPDEBUG(PDB_PVDUMP, 1051 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1052 1053 /* 1054 * There is at least one VA mapping this page. 1055 */ 1056 1057 if (clr_mask & (PVF_REF | PVF_MOD)) { 1058 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1059 #ifdef PMAP_CACHE_VIPT 1060 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1061 md->pvh_attrs |= PVF_DIRTY; 1062 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1063 #endif 1064 } 1065 1066 oflags = npv->pv_flags; 1067 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1068 1069 if ((flags ^ oflags) & PVF_WIRED) { 1070 if (flags & PVF_WIRED) 1071 ++pm->pm_stats.wired_count; 1072 else 1073 --pm->pm_stats.wired_count; 1074 } 1075 1076 if ((flags ^ oflags) & PVF_WRITE) { 1077 if (pm == pmap_kernel()) { 1078 if (flags & PVF_WRITE) { 1079 md->krw_mappings++; 1080 md->kro_mappings--; 1081 } else { 1082 md->kro_mappings++; 1083 md->krw_mappings--; 1084 } 1085 } else { 1086 if (flags & PVF_WRITE) { 1087 md->urw_mappings++; 1088 md->uro_mappings--; 1089 } else { 1090 md->uro_mappings++; 1091 md->urw_mappings--; 1092 } 1093 } 1094 } 1095 #ifdef PMAP_CACHE_VIPT 1096 if (md->urw_mappings + md->krw_mappings == 0) 1097 md->pvh_attrs &= ~PVF_WRITE; 1098 /* 1099 * We have two cases here: the first is from enter_pv (new exec 1100 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1101 * Since in latter, pmap_enter_pv won't do anything, we just have 1102 * to do what pmap_remove_pv would do. 1103 */ 1104 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1105 || (PV_IS_EXEC_P(md->pvh_attrs) 1106 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1107 pmap_syncicache_page(md, pa); 1108 PMAPCOUNT(exec_synced_remap); 1109 } 1110 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1111 #endif 1112 1113 PMAPCOUNT(remappings); 1114 1115 return (oflags); 1116 } 1117 1118 /* 1119 * Allocate an L1 translation table for the specified pmap. 1120 * This is called at pmap creation time. 1121 */ 1122 static void 1123 pmap_alloc_l1(pmap_t pm) 1124 { 1125 struct l1_ttable *l1; 1126 uint8_t domain; 1127 1128 /* 1129 * Remove the L1 at the head of the LRU list 1130 */ 1131 mutex_spin_enter(&l1_lru_lock); 1132 l1 = TAILQ_FIRST(&l1_lru_list); 1133 KDASSERT(l1 != NULL); 1134 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1135 1136 /* 1137 * Pick the first available domain number, and update 1138 * the link to the next number. 1139 */ 1140 domain = l1->l1_domain_first; 1141 l1->l1_domain_first = l1->l1_domain_free[domain]; 1142 1143 /* 1144 * If there are still free domain numbers in this L1, 1145 * put it back on the TAIL of the LRU list. 1146 */ 1147 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1148 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1149 1150 mutex_spin_exit(&l1_lru_lock); 1151 1152 /* 1153 * Fix up the relevant bits in the pmap structure 1154 */ 1155 pm->pm_l1 = l1; 1156 pm->pm_domain = domain + 1; 1157 } 1158 1159 /* 1160 * Free an L1 translation table. 1161 * This is called at pmap destruction time. 1162 */ 1163 static void 1164 pmap_free_l1(pmap_t pm) 1165 { 1166 struct l1_ttable *l1 = pm->pm_l1; 1167 1168 mutex_spin_enter(&l1_lru_lock); 1169 1170 /* 1171 * If this L1 is currently on the LRU list, remove it. 1172 */ 1173 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1174 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1175 1176 /* 1177 * Free up the domain number which was allocated to the pmap 1178 */ 1179 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first; 1180 l1->l1_domain_first = pm->pm_domain - 1; 1181 l1->l1_domain_use_count--; 1182 1183 /* 1184 * The L1 now must have at least 1 free domain, so add 1185 * it back to the LRU list. If the use count is zero, 1186 * put it at the head of the list, otherwise it goes 1187 * to the tail. 1188 */ 1189 if (l1->l1_domain_use_count == 0) 1190 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1191 else 1192 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1193 1194 mutex_spin_exit(&l1_lru_lock); 1195 } 1196 1197 static inline void 1198 pmap_use_l1(pmap_t pm) 1199 { 1200 struct l1_ttable *l1; 1201 1202 /* 1203 * Do nothing if we're in interrupt context. 1204 * Access to an L1 by the kernel pmap must not affect 1205 * the LRU list. 1206 */ 1207 if (cpu_intr_p() || pm == pmap_kernel()) 1208 return; 1209 1210 l1 = pm->pm_l1; 1211 1212 /* 1213 * If the L1 is not currently on the LRU list, just return 1214 */ 1215 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1216 return; 1217 1218 mutex_spin_enter(&l1_lru_lock); 1219 1220 /* 1221 * Check the use count again, now that we've acquired the lock 1222 */ 1223 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1224 mutex_spin_exit(&l1_lru_lock); 1225 return; 1226 } 1227 1228 /* 1229 * Move the L1 to the back of the LRU list 1230 */ 1231 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1232 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1233 1234 mutex_spin_exit(&l1_lru_lock); 1235 } 1236 1237 /* 1238 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1239 * 1240 * Free an L2 descriptor table. 1241 */ 1242 static inline void 1243 #ifndef PMAP_INCLUDE_PTE_SYNC 1244 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1245 #else 1246 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1247 #endif 1248 { 1249 #ifdef PMAP_INCLUDE_PTE_SYNC 1250 #ifdef PMAP_CACHE_VIVT 1251 /* 1252 * Note: With a write-back cache, we may need to sync this 1253 * L2 table before re-using it. 1254 * This is because it may have belonged to a non-current 1255 * pmap, in which case the cache syncs would have been 1256 * skipped for the pages that were being unmapped. If the 1257 * L2 table were then to be immediately re-allocated to 1258 * the *current* pmap, it may well contain stale mappings 1259 * which have not yet been cleared by a cache write-back 1260 * and so would still be visible to the mmu. 1261 */ 1262 if (need_sync) 1263 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1264 #endif /* PMAP_CACHE_VIVT */ 1265 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1266 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1267 } 1268 1269 /* 1270 * Returns a pointer to the L2 bucket associated with the specified pmap 1271 * and VA, or NULL if no L2 bucket exists for the address. 1272 */ 1273 static inline struct l2_bucket * 1274 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1275 { 1276 struct l2_dtable *l2; 1277 struct l2_bucket *l2b; 1278 u_short l1idx; 1279 1280 l1idx = L1_IDX(va); 1281 1282 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1283 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1284 return (NULL); 1285 1286 return (l2b); 1287 } 1288 1289 /* 1290 * Returns a pointer to the L2 bucket associated with the specified pmap 1291 * and VA. 1292 * 1293 * If no L2 bucket exists, perform the necessary allocations to put an L2 1294 * bucket/page table in place. 1295 * 1296 * Note that if a new L2 bucket/page was allocated, the caller *must* 1297 * increment the bucket occupancy counter appropriately *before* 1298 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1299 * the bucket/page in the meantime. 1300 */ 1301 static struct l2_bucket * 1302 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1303 { 1304 struct l2_dtable *l2; 1305 struct l2_bucket *l2b; 1306 u_short l1idx; 1307 1308 l1idx = L1_IDX(va); 1309 1310 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1311 /* 1312 * No mapping at this address, as there is 1313 * no entry in the L1 table. 1314 * Need to allocate a new l2_dtable. 1315 */ 1316 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1317 return (NULL); 1318 1319 /* 1320 * Link it into the parent pmap 1321 */ 1322 pm->pm_l2[L2_IDX(l1idx)] = l2; 1323 } 1324 1325 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1326 1327 /* 1328 * Fetch pointer to the L2 page table associated with the address. 1329 */ 1330 if (l2b->l2b_kva == NULL) { 1331 pt_entry_t *ptep; 1332 1333 /* 1334 * No L2 page table has been allocated. Chances are, this 1335 * is because we just allocated the l2_dtable, above. 1336 */ 1337 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1338 /* 1339 * Oops, no more L2 page tables available at this 1340 * time. We may need to deallocate the l2_dtable 1341 * if we allocated a new one above. 1342 */ 1343 if (l2->l2_occupancy == 0) { 1344 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1345 pmap_free_l2_dtable(l2); 1346 } 1347 return (NULL); 1348 } 1349 1350 l2->l2_occupancy++; 1351 l2b->l2b_kva = ptep; 1352 l2b->l2b_l1idx = l1idx; 1353 } 1354 1355 return (l2b); 1356 } 1357 1358 /* 1359 * One or more mappings in the specified L2 descriptor table have just been 1360 * invalidated. 1361 * 1362 * Garbage collect the metadata and descriptor table itself if necessary. 1363 * 1364 * The pmap lock must be acquired when this is called (not necessary 1365 * for the kernel pmap). 1366 */ 1367 static void 1368 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1369 { 1370 struct l2_dtable *l2; 1371 pd_entry_t *pl1pd, l1pd; 1372 pt_entry_t *ptep; 1373 u_short l1idx; 1374 1375 KDASSERT(count <= l2b->l2b_occupancy); 1376 1377 /* 1378 * Update the bucket's reference count according to how many 1379 * PTEs the caller has just invalidated. 1380 */ 1381 l2b->l2b_occupancy -= count; 1382 1383 /* 1384 * Note: 1385 * 1386 * Level 2 page tables allocated to the kernel pmap are never freed 1387 * as that would require checking all Level 1 page tables and 1388 * removing any references to the Level 2 page table. See also the 1389 * comment elsewhere about never freeing bootstrap L2 descriptors. 1390 * 1391 * We make do with just invalidating the mapping in the L2 table. 1392 * 1393 * This isn't really a big deal in practice and, in fact, leads 1394 * to a performance win over time as we don't need to continually 1395 * alloc/free. 1396 */ 1397 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1398 return; 1399 1400 /* 1401 * There are no more valid mappings in this level 2 page table. 1402 * Go ahead and NULL-out the pointer in the bucket, then 1403 * free the page table. 1404 */ 1405 l1idx = l2b->l2b_l1idx; 1406 ptep = l2b->l2b_kva; 1407 l2b->l2b_kva = NULL; 1408 1409 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1410 1411 /* 1412 * If the L1 slot matches the pmap's domain 1413 * number, then invalidate it. 1414 */ 1415 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1416 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1417 *pl1pd = 0; 1418 PTE_SYNC(pl1pd); 1419 } 1420 1421 /* 1422 * Release the L2 descriptor table back to the pool cache. 1423 */ 1424 #ifndef PMAP_INCLUDE_PTE_SYNC 1425 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1426 #else 1427 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1428 #endif 1429 1430 /* 1431 * Update the reference count in the associated l2_dtable 1432 */ 1433 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1434 if (--l2->l2_occupancy > 0) 1435 return; 1436 1437 /* 1438 * There are no more valid mappings in any of the Level 1 1439 * slots managed by this l2_dtable. Go ahead and NULL-out 1440 * the pointer in the parent pmap and free the l2_dtable. 1441 */ 1442 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1443 pmap_free_l2_dtable(l2); 1444 } 1445 1446 /* 1447 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1448 * structures. 1449 */ 1450 static int 1451 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1452 { 1453 #ifndef PMAP_INCLUDE_PTE_SYNC 1454 struct l2_bucket *l2b; 1455 pt_entry_t *ptep, pte; 1456 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1457 1458 /* 1459 * The mappings for these page tables were initially made using 1460 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1461 * mode will not be right for page table mappings. To avoid 1462 * polluting the pmap_kenter_pa() code with a special case for 1463 * page tables, we simply fix up the cache-mode here if it's not 1464 * correct. 1465 */ 1466 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1467 KDASSERT(l2b != NULL); 1468 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1469 pte = *ptep; 1470 1471 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1472 /* 1473 * Page tables must have the cache-mode set to Write-Thru. 1474 */ 1475 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1476 PTE_SYNC(ptep); 1477 cpu_tlb_flushD_SE(va); 1478 cpu_cpwait(); 1479 } 1480 #endif 1481 1482 memset(v, 0, L2_TABLE_SIZE_REAL); 1483 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1484 return (0); 1485 } 1486 1487 static int 1488 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1489 { 1490 1491 memset(v, 0, sizeof(struct l2_dtable)); 1492 return (0); 1493 } 1494 1495 static int 1496 pmap_pmap_ctor(void *arg, void *v, int flags) 1497 { 1498 1499 memset(v, 0, sizeof(struct pmap)); 1500 return (0); 1501 } 1502 1503 static void 1504 pmap_pinit(pmap_t pm) 1505 { 1506 struct l2_bucket *l2b; 1507 1508 if (vector_page < KERNEL_BASE) { 1509 /* 1510 * Map the vector page. 1511 */ 1512 pmap_enter(pm, vector_page, systempage.pv_pa, 1513 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1514 pmap_update(pm); 1515 1516 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1517 l2b = pmap_get_l2_bucket(pm, vector_page); 1518 KDASSERT(l2b != NULL); 1519 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1520 L1_C_DOM(pm->pm_domain); 1521 } else 1522 pm->pm_pl1vec = NULL; 1523 } 1524 1525 #ifdef PMAP_CACHE_VIVT 1526 /* 1527 * Since we have a virtually indexed cache, we may need to inhibit caching if 1528 * there is more than one mapping and at least one of them is writable. 1529 * Since we purge the cache on every context switch, we only need to check for 1530 * other mappings within the same pmap, or kernel_pmap. 1531 * This function is also called when a page is unmapped, to possibly reenable 1532 * caching on any remaining mappings. 1533 * 1534 * The code implements the following logic, where: 1535 * 1536 * KW = # of kernel read/write pages 1537 * KR = # of kernel read only pages 1538 * UW = # of user read/write pages 1539 * UR = # of user read only pages 1540 * 1541 * KC = kernel mapping is cacheable 1542 * UC = user mapping is cacheable 1543 * 1544 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1545 * +--------------------------------------------- 1546 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1547 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1548 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1549 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1550 */ 1551 1552 static const int pmap_vac_flags[4][4] = { 1553 {-1, 0, 0, PVF_KNC}, 1554 {0, 0, PVF_NC, PVF_NC}, 1555 {0, PVF_NC, PVF_NC, PVF_NC}, 1556 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1557 }; 1558 1559 static inline int 1560 pmap_get_vac_flags(const struct vm_page_md *md) 1561 { 1562 int kidx, uidx; 1563 1564 kidx = 0; 1565 if (md->kro_mappings || md->krw_mappings > 1) 1566 kidx |= 1; 1567 if (md->krw_mappings) 1568 kidx |= 2; 1569 1570 uidx = 0; 1571 if (md->uro_mappings || md->urw_mappings > 1) 1572 uidx |= 1; 1573 if (md->urw_mappings) 1574 uidx |= 2; 1575 1576 return (pmap_vac_flags[uidx][kidx]); 1577 } 1578 1579 static inline void 1580 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1581 { 1582 int nattr; 1583 1584 nattr = pmap_get_vac_flags(md); 1585 1586 if (nattr < 0) { 1587 md->pvh_attrs &= ~PVF_NC; 1588 return; 1589 } 1590 1591 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1592 return; 1593 1594 if (pm == pmap_kernel()) 1595 pmap_vac_me_kpmap(md, pa, pm, va); 1596 else 1597 pmap_vac_me_user(md, pa, pm, va); 1598 1599 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1600 } 1601 1602 static void 1603 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1604 { 1605 u_int u_cacheable, u_entries; 1606 struct pv_entry *pv; 1607 pmap_t last_pmap = pm; 1608 1609 /* 1610 * Pass one, see if there are both kernel and user pmaps for 1611 * this page. Calculate whether there are user-writable or 1612 * kernel-writable pages. 1613 */ 1614 u_cacheable = 0; 1615 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1616 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1617 u_cacheable++; 1618 } 1619 1620 u_entries = md->urw_mappings + md->uro_mappings; 1621 1622 /* 1623 * We know we have just been updating a kernel entry, so if 1624 * all user pages are already cacheable, then there is nothing 1625 * further to do. 1626 */ 1627 if (md->k_mappings == 0 && u_cacheable == u_entries) 1628 return; 1629 1630 if (u_entries) { 1631 /* 1632 * Scan over the list again, for each entry, if it 1633 * might not be set correctly, call pmap_vac_me_user 1634 * to recalculate the settings. 1635 */ 1636 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1637 /* 1638 * We know kernel mappings will get set 1639 * correctly in other calls. We also know 1640 * that if the pmap is the same as last_pmap 1641 * then we've just handled this entry. 1642 */ 1643 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1644 continue; 1645 1646 /* 1647 * If there are kernel entries and this page 1648 * is writable but non-cacheable, then we can 1649 * skip this entry also. 1650 */ 1651 if (md->k_mappings && 1652 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1653 (PVF_NC | PVF_WRITE)) 1654 continue; 1655 1656 /* 1657 * Similarly if there are no kernel-writable 1658 * entries and the page is already 1659 * read-only/cacheable. 1660 */ 1661 if (md->krw_mappings == 0 && 1662 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1663 continue; 1664 1665 /* 1666 * For some of the remaining cases, we know 1667 * that we must recalculate, but for others we 1668 * can't tell if they are correct or not, so 1669 * we recalculate anyway. 1670 */ 1671 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1672 } 1673 1674 if (md->k_mappings == 0) 1675 return; 1676 } 1677 1678 pmap_vac_me_user(md, pa, pm, va); 1679 } 1680 1681 static void 1682 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1683 { 1684 pmap_t kpmap = pmap_kernel(); 1685 struct pv_entry *pv, *npv = NULL; 1686 struct l2_bucket *l2b; 1687 pt_entry_t *ptep, pte; 1688 u_int entries = 0; 1689 u_int writable = 0; 1690 u_int cacheable_entries = 0; 1691 u_int kern_cacheable = 0; 1692 u_int other_writable = 0; 1693 1694 /* 1695 * Count mappings and writable mappings in this pmap. 1696 * Include kernel mappings as part of our own. 1697 * Keep a pointer to the first one. 1698 */ 1699 npv = NULL; 1700 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1701 /* Count mappings in the same pmap */ 1702 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1703 if (entries++ == 0) 1704 npv = pv; 1705 1706 /* Cacheable mappings */ 1707 if ((pv->pv_flags & PVF_NC) == 0) { 1708 cacheable_entries++; 1709 if (kpmap == pv->pv_pmap) 1710 kern_cacheable++; 1711 } 1712 1713 /* Writable mappings */ 1714 if (pv->pv_flags & PVF_WRITE) 1715 ++writable; 1716 } else 1717 if (pv->pv_flags & PVF_WRITE) 1718 other_writable = 1; 1719 } 1720 1721 /* 1722 * Enable or disable caching as necessary. 1723 * Note: the first entry might be part of the kernel pmap, 1724 * so we can't assume this is indicative of the state of the 1725 * other (maybe non-kpmap) entries. 1726 */ 1727 if ((entries > 1 && writable) || 1728 (entries > 0 && pm == kpmap && other_writable)) { 1729 if (cacheable_entries == 0) 1730 return; 1731 1732 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1733 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1734 (pv->pv_flags & PVF_NC)) 1735 continue; 1736 1737 pv->pv_flags |= PVF_NC; 1738 1739 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1740 KDASSERT(l2b != NULL); 1741 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1742 pte = *ptep & ~L2_S_CACHE_MASK; 1743 1744 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1745 l2pte_valid(pte)) { 1746 if (PV_BEEN_EXECD(pv->pv_flags)) { 1747 #ifdef PMAP_CACHE_VIVT 1748 pmap_idcache_wbinv_range(pv->pv_pmap, 1749 pv->pv_va, PAGE_SIZE); 1750 #endif 1751 pmap_tlb_flushID_SE(pv->pv_pmap, 1752 pv->pv_va); 1753 } else 1754 if (PV_BEEN_REFD(pv->pv_flags)) { 1755 #ifdef PMAP_CACHE_VIVT 1756 pmap_dcache_wb_range(pv->pv_pmap, 1757 pv->pv_va, PAGE_SIZE, true, 1758 (pv->pv_flags & PVF_WRITE) == 0); 1759 #endif 1760 pmap_tlb_flushD_SE(pv->pv_pmap, 1761 pv->pv_va); 1762 } 1763 } 1764 1765 *ptep = pte; 1766 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1767 } 1768 cpu_cpwait(); 1769 } else 1770 if (entries > cacheable_entries) { 1771 /* 1772 * Turn cacheing back on for some pages. If it is a kernel 1773 * page, only do so if there are no other writable pages. 1774 */ 1775 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1776 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1777 (kpmap != pv->pv_pmap || other_writable))) 1778 continue; 1779 1780 pv->pv_flags &= ~PVF_NC; 1781 1782 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1783 KDASSERT(l2b != NULL); 1784 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1785 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1786 1787 if (l2pte_valid(pte)) { 1788 if (PV_BEEN_EXECD(pv->pv_flags)) { 1789 pmap_tlb_flushID_SE(pv->pv_pmap, 1790 pv->pv_va); 1791 } else 1792 if (PV_BEEN_REFD(pv->pv_flags)) { 1793 pmap_tlb_flushD_SE(pv->pv_pmap, 1794 pv->pv_va); 1795 } 1796 } 1797 1798 *ptep = pte; 1799 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1800 } 1801 } 1802 } 1803 #endif 1804 1805 #ifdef PMAP_CACHE_VIPT 1806 static void 1807 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1808 { 1809 struct pv_entry *pv; 1810 vaddr_t tst_mask; 1811 bool bad_alias; 1812 struct l2_bucket *l2b; 1813 pt_entry_t *ptep, pte, opte; 1814 const u_int 1815 rw_mappings = md->urw_mappings + md->krw_mappings, 1816 ro_mappings = md->uro_mappings + md->kro_mappings; 1817 1818 /* do we need to do anything? */ 1819 if (arm_cache_prefer_mask == 0) 1820 return; 1821 1822 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1823 md, pm, va)); 1824 1825 KASSERT(!va || pm); 1826 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1827 1828 /* Already a conflict? */ 1829 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1830 /* just an add, things are already non-cached */ 1831 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1832 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1833 bad_alias = false; 1834 if (va) { 1835 PMAPCOUNT(vac_color_none); 1836 bad_alias = true; 1837 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1838 goto fixup; 1839 } 1840 pv = SLIST_FIRST(&md->pvh_list); 1841 /* the list can't be empty because it would be cachable */ 1842 if (md->pvh_attrs & PVF_KMPAGE) { 1843 tst_mask = md->pvh_attrs; 1844 } else { 1845 KASSERT(pv); 1846 tst_mask = pv->pv_va; 1847 pv = SLIST_NEXT(pv, pv_link); 1848 } 1849 /* 1850 * Only check for a bad alias if we have writable mappings. 1851 */ 1852 tst_mask &= arm_cache_prefer_mask; 1853 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1854 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1855 /* if there's a bad alias, stop checking. */ 1856 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1857 bad_alias = true; 1858 } 1859 md->pvh_attrs |= PVF_WRITE; 1860 if (!bad_alias) 1861 md->pvh_attrs |= PVF_DIRTY; 1862 } else { 1863 /* 1864 * We have only read-only mappings. Let's see if there 1865 * are multiple colors in use or if we mapped a KMPAGE. 1866 * If the latter, we have a bad alias. If the former, 1867 * we need to remember that. 1868 */ 1869 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1870 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1871 if (md->pvh_attrs & PVF_KMPAGE) 1872 bad_alias = true; 1873 break; 1874 } 1875 } 1876 md->pvh_attrs &= ~PVF_WRITE; 1877 /* 1878 * No KMPAGE and we exited early, so we must have 1879 * multiple color mappings. 1880 */ 1881 if (!bad_alias && pv != NULL) 1882 md->pvh_attrs |= PVF_MULTCLR; 1883 } 1884 1885 /* If no conflicting colors, set everything back to cached */ 1886 if (!bad_alias) { 1887 #ifdef DEBUG 1888 if ((md->pvh_attrs & PVF_WRITE) 1889 || ro_mappings < 2) { 1890 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1891 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1892 } 1893 #endif 1894 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1895 md->pvh_attrs |= tst_mask | PVF_COLORED; 1896 /* 1897 * Restore DIRTY bit if page is modified 1898 */ 1899 if (md->pvh_attrs & PVF_DMOD) 1900 md->pvh_attrs |= PVF_DIRTY; 1901 PMAPCOUNT(vac_color_restore); 1902 } else { 1903 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1904 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1905 } 1906 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1907 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1908 } else if (!va) { 1909 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1910 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1911 || (md->pvh_attrs & PVF_DIRTY)); 1912 if (rw_mappings == 0) { 1913 md->pvh_attrs &= ~PVF_WRITE; 1914 if (ro_mappings == 1 1915 && (md->pvh_attrs & PVF_MULTCLR)) { 1916 /* 1917 * If this is the last readonly mapping 1918 * but it doesn't match the current color 1919 * for the page, change the current color 1920 * to match this last readonly mapping. 1921 */ 1922 pv = SLIST_FIRST(&md->pvh_list); 1923 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1924 & arm_cache_prefer_mask; 1925 if (tst_mask) { 1926 md->pvh_attrs ^= tst_mask; 1927 PMAPCOUNT(vac_color_change); 1928 } 1929 } 1930 } 1931 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1932 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1933 return; 1934 } else if (!pmap_is_page_colored_p(md)) { 1935 /* not colored so we just use its color */ 1936 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1937 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1938 PMAPCOUNT(vac_color_new); 1939 md->pvh_attrs &= PAGE_SIZE - 1; 1940 md->pvh_attrs |= PVF_COLORED 1941 | (va & arm_cache_prefer_mask) 1942 | (rw_mappings > 0 ? PVF_WRITE : 0); 1943 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1944 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1945 return; 1946 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1947 bad_alias = false; 1948 if (rw_mappings > 0) { 1949 /* 1950 * We now have writeable mappings and if we have 1951 * readonly mappings in more than once color, we have 1952 * an aliasing problem. Regardless mark the page as 1953 * writeable. 1954 */ 1955 if (md->pvh_attrs & PVF_MULTCLR) { 1956 if (ro_mappings < 2) { 1957 /* 1958 * If we only have less than two 1959 * read-only mappings, just flush the 1960 * non-primary colors from the cache. 1961 */ 1962 pmap_flush_page(md, pa, 1963 PMAP_FLUSH_SECONDARY); 1964 } else { 1965 bad_alias = true; 1966 } 1967 } 1968 md->pvh_attrs |= PVF_WRITE; 1969 } 1970 /* If no conflicting colors, set everything back to cached */ 1971 if (!bad_alias) { 1972 #ifdef DEBUG 1973 if (rw_mappings > 0 1974 || (md->pvh_attrs & PMAP_KMPAGE)) { 1975 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1976 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1977 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1978 } 1979 #endif 1980 if (SLIST_EMPTY(&md->pvh_list)) 1981 PMAPCOUNT(vac_color_reuse); 1982 else 1983 PMAPCOUNT(vac_color_ok); 1984 1985 /* matching color, just return */ 1986 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1987 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1988 return; 1989 } 1990 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1991 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1992 1993 /* color conflict. evict from cache. */ 1994 1995 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 1996 md->pvh_attrs &= ~PVF_COLORED; 1997 md->pvh_attrs |= PVF_NC; 1998 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1999 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2000 PMAPCOUNT(vac_color_erase); 2001 } else if (rw_mappings == 0 2002 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2003 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2004 2005 /* 2006 * If the page has dirty cache lines, clean it. 2007 */ 2008 if (md->pvh_attrs & PVF_DIRTY) 2009 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2010 2011 /* 2012 * If this is the first remapping (we know that there are no 2013 * writeable mappings), then this is a simple color change. 2014 * Otherwise this is a seconary r/o mapping, which means 2015 * we don't have to do anything. 2016 */ 2017 if (ro_mappings == 1) { 2018 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2019 md->pvh_attrs &= PAGE_SIZE - 1; 2020 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2021 PMAPCOUNT(vac_color_change); 2022 } else { 2023 PMAPCOUNT(vac_color_blind); 2024 } 2025 md->pvh_attrs |= PVF_MULTCLR; 2026 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2027 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2028 return; 2029 } else { 2030 if (rw_mappings > 0) 2031 md->pvh_attrs |= PVF_WRITE; 2032 2033 /* color conflict. evict from cache. */ 2034 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2035 2036 /* the list can't be empty because this was a enter/modify */ 2037 pv = SLIST_FIRST(&md->pvh_list); 2038 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2039 KASSERT(pv); 2040 /* 2041 * If there's only one mapped page, change color to the 2042 * page's new color and return. Restore the DIRTY bit 2043 * that was erased by pmap_flush_page. 2044 */ 2045 if (SLIST_NEXT(pv, pv_link) == NULL) { 2046 md->pvh_attrs &= PAGE_SIZE - 1; 2047 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2048 if (md->pvh_attrs & PVF_DMOD) 2049 md->pvh_attrs |= PVF_DIRTY; 2050 PMAPCOUNT(vac_color_change); 2051 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2052 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2053 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2054 return; 2055 } 2056 } 2057 bad_alias = true; 2058 md->pvh_attrs &= ~PVF_COLORED; 2059 md->pvh_attrs |= PVF_NC; 2060 PMAPCOUNT(vac_color_erase); 2061 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2062 } 2063 2064 fixup: 2065 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2066 2067 /* 2068 * Turn cacheing on/off for all pages. 2069 */ 2070 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2071 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2072 KDASSERT(l2b != NULL); 2073 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2074 opte = *ptep; 2075 pte = opte & ~L2_S_CACHE_MASK; 2076 if (bad_alias) { 2077 pv->pv_flags |= PVF_NC; 2078 } else { 2079 pv->pv_flags &= ~PVF_NC; 2080 pte |= pte_l2_s_cache_mode; 2081 } 2082 2083 if (opte == pte) /* only update is there's a change */ 2084 continue; 2085 2086 if (l2pte_valid(pte)) { 2087 if (PV_BEEN_EXECD(pv->pv_flags)) { 2088 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2089 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2090 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2091 } 2092 } 2093 2094 *ptep = pte; 2095 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2096 } 2097 } 2098 #endif /* PMAP_CACHE_VIPT */ 2099 2100 2101 /* 2102 * Modify pte bits for all ptes corresponding to the given physical address. 2103 * We use `maskbits' rather than `clearbits' because we're always passing 2104 * constants and the latter would require an extra inversion at run-time. 2105 */ 2106 static void 2107 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2108 { 2109 struct l2_bucket *l2b; 2110 struct pv_entry *pv; 2111 pt_entry_t *ptep, npte, opte; 2112 pmap_t pm; 2113 vaddr_t va; 2114 u_int oflags; 2115 #ifdef PMAP_CACHE_VIPT 2116 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2117 bool need_syncicache = false; 2118 bool did_syncicache = false; 2119 bool need_vac_me_harder = false; 2120 #endif 2121 2122 NPDEBUG(PDB_BITS, 2123 printf("pmap_clearbit: md %p mask 0x%x\n", 2124 md, maskbits)); 2125 2126 #ifdef PMAP_CACHE_VIPT 2127 /* 2128 * If we might want to sync the I-cache and we've modified it, 2129 * then we know we definitely need to sync or discard it. 2130 */ 2131 if (want_syncicache) 2132 need_syncicache = md->pvh_attrs & PVF_MOD; 2133 #endif 2134 /* 2135 * Clear saved attributes (modify, reference) 2136 */ 2137 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2138 2139 if (SLIST_EMPTY(&md->pvh_list)) { 2140 #ifdef PMAP_CACHE_VIPT 2141 if (need_syncicache) { 2142 /* 2143 * No one has it mapped, so just discard it. The next 2144 * exec remapping will cause it to be synced. 2145 */ 2146 md->pvh_attrs &= ~PVF_EXEC; 2147 PMAPCOUNT(exec_discarded_clearbit); 2148 } 2149 #endif 2150 return; 2151 } 2152 2153 /* 2154 * Loop over all current mappings setting/clearing as appropos 2155 */ 2156 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2157 va = pv->pv_va; 2158 pm = pv->pv_pmap; 2159 oflags = pv->pv_flags; 2160 /* 2161 * Kernel entries are unmanaged and as such not to be changed. 2162 */ 2163 if (oflags & PVF_KENTRY) 2164 continue; 2165 pv->pv_flags &= ~maskbits; 2166 2167 pmap_acquire_pmap_lock(pm); 2168 2169 l2b = pmap_get_l2_bucket(pm, va); 2170 KDASSERT(l2b != NULL); 2171 2172 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2173 npte = opte = *ptep; 2174 2175 NPDEBUG(PDB_BITS, 2176 printf( 2177 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2178 pv, pv->pv_pmap, pv->pv_va, oflags)); 2179 2180 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2181 #ifdef PMAP_CACHE_VIVT 2182 if ((pv->pv_flags & PVF_NC)) { 2183 /* 2184 * Entry is not cacheable: 2185 * 2186 * Don't turn caching on again if this is a 2187 * modified emulation. This would be 2188 * inconsitent with the settings created by 2189 * pmap_vac_me_harder(). Otherwise, it's safe 2190 * to re-enable cacheing. 2191 * 2192 * There's no need to call pmap_vac_me_harder() 2193 * here: all pages are losing their write 2194 * permission. 2195 */ 2196 if (maskbits & PVF_WRITE) { 2197 npte |= pte_l2_s_cache_mode; 2198 pv->pv_flags &= ~PVF_NC; 2199 } 2200 } else 2201 if (l2pte_writable_p(opte)) { 2202 /* 2203 * Entry is writable/cacheable: check if pmap 2204 * is current if it is flush it, otherwise it 2205 * won't be in the cache 2206 */ 2207 if (PV_BEEN_EXECD(oflags)) 2208 pmap_idcache_wbinv_range(pm, pv->pv_va, 2209 PAGE_SIZE); 2210 else 2211 if (PV_BEEN_REFD(oflags)) 2212 pmap_dcache_wb_range(pm, pv->pv_va, 2213 PAGE_SIZE, 2214 (maskbits & PVF_REF) != 0, false); 2215 } 2216 #endif 2217 2218 /* make the pte read only */ 2219 npte = l2pte_set_readonly(npte); 2220 2221 if (maskbits & oflags & PVF_WRITE) { 2222 /* 2223 * Keep alias accounting up to date 2224 */ 2225 if (pv->pv_pmap == pmap_kernel()) { 2226 md->krw_mappings--; 2227 md->kro_mappings++; 2228 } else { 2229 md->urw_mappings--; 2230 md->uro_mappings++; 2231 } 2232 #ifdef PMAP_CACHE_VIPT 2233 if (md->urw_mappings + md->krw_mappings == 0) 2234 md->pvh_attrs &= ~PVF_WRITE; 2235 if (want_syncicache) 2236 need_syncicache = true; 2237 need_vac_me_harder = true; 2238 #endif 2239 } 2240 } 2241 2242 if (maskbits & PVF_REF) { 2243 if ((pv->pv_flags & PVF_NC) == 0 && 2244 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2245 l2pte_valid(npte)) { 2246 #ifdef PMAP_CACHE_VIVT 2247 /* 2248 * Check npte here; we may have already 2249 * done the wbinv above, and the validity 2250 * of the PTE is the same for opte and 2251 * npte. 2252 */ 2253 /* XXXJRT need idcache_inv_range */ 2254 if (PV_BEEN_EXECD(oflags)) 2255 pmap_idcache_wbinv_range(pm, 2256 pv->pv_va, PAGE_SIZE); 2257 else 2258 if (PV_BEEN_REFD(oflags)) 2259 pmap_dcache_wb_range(pm, 2260 pv->pv_va, PAGE_SIZE, 2261 true, true); 2262 #endif 2263 } 2264 2265 /* 2266 * Make the PTE invalid so that we will take a 2267 * page fault the next time the mapping is 2268 * referenced. 2269 */ 2270 npte &= ~L2_TYPE_MASK; 2271 npte |= L2_TYPE_INV; 2272 } 2273 2274 if (npte != opte) { 2275 *ptep = npte; 2276 PTE_SYNC(ptep); 2277 /* Flush the TLB entry if a current pmap. */ 2278 if (PV_BEEN_EXECD(oflags)) 2279 pmap_tlb_flushID_SE(pm, pv->pv_va); 2280 else 2281 if (PV_BEEN_REFD(oflags)) 2282 pmap_tlb_flushD_SE(pm, pv->pv_va); 2283 } 2284 2285 pmap_release_pmap_lock(pm); 2286 2287 NPDEBUG(PDB_BITS, 2288 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2289 pm, va, opte, npte)); 2290 } 2291 2292 #ifdef PMAP_CACHE_VIPT 2293 /* 2294 * If we need to sync the I-cache and we haven't done it yet, do it. 2295 */ 2296 if (need_syncicache && !did_syncicache) { 2297 pmap_syncicache_page(md, pa); 2298 PMAPCOUNT(exec_synced_clearbit); 2299 } 2300 /* 2301 * If we are changing this to read-only, we need to call vac_me_harder 2302 * so we can change all the read-only pages to cacheable. We pretend 2303 * this as a page deletion. 2304 */ 2305 if (need_vac_me_harder) { 2306 if (md->pvh_attrs & PVF_NC) 2307 pmap_vac_me_harder(md, pa, NULL, 0); 2308 } 2309 #endif 2310 } 2311 2312 /* 2313 * pmap_clean_page() 2314 * 2315 * This is a local function used to work out the best strategy to clean 2316 * a single page referenced by its entry in the PV table. It's used by 2317 * pmap_copy_page, pmap_zero page and maybe some others later on. 2318 * 2319 * Its policy is effectively: 2320 * o If there are no mappings, we don't bother doing anything with the cache. 2321 * o If there is one mapping, we clean just that page. 2322 * o If there are multiple mappings, we clean the entire cache. 2323 * 2324 * So that some functions can be further optimised, it returns 0 if it didn't 2325 * clean the entire cache, or 1 if it did. 2326 * 2327 * XXX One bug in this routine is that if the pv_entry has a single page 2328 * mapped at 0x00000000 a whole cache clean will be performed rather than 2329 * just the 1 page. Since this should not occur in everyday use and if it does 2330 * it will just result in not the most efficient clean for the page. 2331 */ 2332 #ifdef PMAP_CACHE_VIVT 2333 static int 2334 pmap_clean_page(struct pv_entry *pv, bool is_src) 2335 { 2336 pmap_t pm_to_clean = NULL; 2337 struct pv_entry *npv; 2338 u_int cache_needs_cleaning = 0; 2339 u_int flags = 0; 2340 vaddr_t page_to_clean = 0; 2341 2342 if (pv == NULL) { 2343 /* nothing mapped in so nothing to flush */ 2344 return (0); 2345 } 2346 2347 /* 2348 * Since we flush the cache each time we change to a different 2349 * user vmspace, we only need to flush the page if it is in the 2350 * current pmap. 2351 */ 2352 2353 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2354 if (pmap_is_current(npv->pv_pmap)) { 2355 flags |= npv->pv_flags; 2356 /* 2357 * The page is mapped non-cacheable in 2358 * this map. No need to flush the cache. 2359 */ 2360 if (npv->pv_flags & PVF_NC) { 2361 #ifdef DIAGNOSTIC 2362 if (cache_needs_cleaning) 2363 panic("pmap_clean_page: " 2364 "cache inconsistency"); 2365 #endif 2366 break; 2367 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2368 continue; 2369 if (cache_needs_cleaning) { 2370 page_to_clean = 0; 2371 break; 2372 } else { 2373 page_to_clean = npv->pv_va; 2374 pm_to_clean = npv->pv_pmap; 2375 } 2376 cache_needs_cleaning = 1; 2377 } 2378 } 2379 2380 if (page_to_clean) { 2381 if (PV_BEEN_EXECD(flags)) 2382 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2383 PAGE_SIZE); 2384 else 2385 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2386 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2387 } else if (cache_needs_cleaning) { 2388 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2389 2390 if (PV_BEEN_EXECD(flags)) 2391 pmap_idcache_wbinv_all(pm); 2392 else 2393 pmap_dcache_wbinv_all(pm); 2394 return (1); 2395 } 2396 return (0); 2397 } 2398 #endif 2399 2400 #ifdef PMAP_CACHE_VIPT 2401 /* 2402 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2403 * right cache alias to make sure we flush the right stuff. 2404 */ 2405 void 2406 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2407 { 2408 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2409 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2410 2411 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2412 md, md->pvh_attrs)); 2413 /* 2414 * No need to clean the page if it's non-cached. 2415 */ 2416 if (md->pvh_attrs & PVF_NC) 2417 return; 2418 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2419 2420 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2421 /* 2422 * Set up a PTE with the right coloring to flush existing cache lines. 2423 */ 2424 *ptep = L2_S_PROTO | 2425 pa 2426 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2427 | pte_l2_s_cache_mode; 2428 PTE_SYNC(ptep); 2429 2430 /* 2431 * Flush it. 2432 */ 2433 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2434 /* 2435 * Unmap the page. 2436 */ 2437 *ptep = 0; 2438 PTE_SYNC(ptep); 2439 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2440 2441 md->pvh_attrs |= PVF_EXEC; 2442 PMAPCOUNT(exec_synced); 2443 } 2444 2445 void 2446 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2447 { 2448 vsize_t va_offset, end_va; 2449 void (*cf)(vaddr_t, vsize_t); 2450 2451 if (arm_cache_prefer_mask == 0) 2452 return; 2453 2454 switch (flush) { 2455 case PMAP_FLUSH_PRIMARY: 2456 if (md->pvh_attrs & PVF_MULTCLR) { 2457 va_offset = 0; 2458 end_va = arm_cache_prefer_mask; 2459 md->pvh_attrs &= ~PVF_MULTCLR; 2460 PMAPCOUNT(vac_flush_lots); 2461 } else { 2462 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2463 end_va = va_offset; 2464 PMAPCOUNT(vac_flush_one); 2465 } 2466 /* 2467 * Mark that the page is no longer dirty. 2468 */ 2469 md->pvh_attrs &= ~PVF_DIRTY; 2470 cf = cpufuncs.cf_idcache_wbinv_range; 2471 break; 2472 case PMAP_FLUSH_SECONDARY: 2473 va_offset = 0; 2474 end_va = arm_cache_prefer_mask; 2475 cf = cpufuncs.cf_idcache_wbinv_range; 2476 md->pvh_attrs &= ~PVF_MULTCLR; 2477 PMAPCOUNT(vac_flush_lots); 2478 break; 2479 case PMAP_CLEAN_PRIMARY: 2480 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2481 end_va = va_offset; 2482 cf = cpufuncs.cf_dcache_wb_range; 2483 /* 2484 * Mark that the page is no longer dirty. 2485 */ 2486 if ((md->pvh_attrs & PVF_DMOD) == 0) 2487 md->pvh_attrs &= ~PVF_DIRTY; 2488 PMAPCOUNT(vac_clean_one); 2489 break; 2490 default: 2491 return; 2492 } 2493 2494 KASSERT(!(md->pvh_attrs & PVF_NC)); 2495 2496 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2497 md, md->pvh_attrs)); 2498 2499 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2500 const size_t pte_offset = va_offset >> PGSHIFT; 2501 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2502 const pt_entry_t oldpte = *ptep; 2503 2504 if (flush == PMAP_FLUSH_SECONDARY 2505 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2506 continue; 2507 2508 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2509 /* 2510 * Set up a PTE with the right coloring to flush 2511 * existing cache entries. 2512 */ 2513 *ptep = L2_S_PROTO 2514 | pa 2515 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2516 | pte_l2_s_cache_mode; 2517 PTE_SYNC(ptep); 2518 2519 /* 2520 * Flush it. 2521 */ 2522 (*cf)(cdstp + va_offset, PAGE_SIZE); 2523 2524 /* 2525 * Restore the page table entry since we might have interrupted 2526 * pmap_zero_page or pmap_copy_page which was already using 2527 * this pte. 2528 */ 2529 *ptep = oldpte; 2530 PTE_SYNC(ptep); 2531 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2532 } 2533 } 2534 #endif /* PMAP_CACHE_VIPT */ 2535 2536 /* 2537 * Routine: pmap_page_remove 2538 * Function: 2539 * Removes this physical page from 2540 * all physical maps in which it resides. 2541 * Reflects back modify bits to the pager. 2542 */ 2543 static void 2544 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2545 { 2546 struct l2_bucket *l2b; 2547 struct pv_entry *pv, *npv, **pvp; 2548 pmap_t pm; 2549 pt_entry_t *ptep; 2550 bool flush; 2551 u_int flags; 2552 2553 NPDEBUG(PDB_FOLLOW, 2554 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2555 pa)); 2556 2557 pv = SLIST_FIRST(&md->pvh_list); 2558 if (pv == NULL) { 2559 #ifdef PMAP_CACHE_VIPT 2560 /* 2561 * We *know* the page contents are about to be replaced. 2562 * Discard the exec contents 2563 */ 2564 if (PV_IS_EXEC_P(md->pvh_attrs)) 2565 PMAPCOUNT(exec_discarded_page_protect); 2566 md->pvh_attrs &= ~PVF_EXEC; 2567 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2568 #endif 2569 return; 2570 } 2571 #ifdef PMAP_CACHE_VIPT 2572 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2573 #endif 2574 2575 /* 2576 * Clear alias counts 2577 */ 2578 #ifdef PMAP_CACHE_VIVT 2579 md->k_mappings = 0; 2580 #endif 2581 md->urw_mappings = md->uro_mappings = 0; 2582 2583 flush = false; 2584 flags = 0; 2585 2586 #ifdef PMAP_CACHE_VIVT 2587 pmap_clean_page(pv, false); 2588 #endif 2589 2590 pvp = &SLIST_FIRST(&md->pvh_list); 2591 while (pv) { 2592 pm = pv->pv_pmap; 2593 npv = SLIST_NEXT(pv, pv_link); 2594 if (flush == false && pmap_is_current(pm)) 2595 flush = true; 2596 2597 if (pm == pmap_kernel()) { 2598 #ifdef PMAP_CACHE_VIPT 2599 /* 2600 * If this was unmanaged mapping, it must be preserved. 2601 * Move it back on the list and advance the end-of-list 2602 * pointer. 2603 */ 2604 if (pv->pv_flags & PVF_KENTRY) { 2605 *pvp = pv; 2606 pvp = &SLIST_NEXT(pv, pv_link); 2607 pv = npv; 2608 continue; 2609 } 2610 if (pv->pv_flags & PVF_WRITE) 2611 md->krw_mappings--; 2612 else 2613 md->kro_mappings--; 2614 #endif 2615 PMAPCOUNT(kernel_unmappings); 2616 } 2617 PMAPCOUNT(unmappings); 2618 2619 pmap_acquire_pmap_lock(pm); 2620 2621 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2622 KDASSERT(l2b != NULL); 2623 2624 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2625 2626 /* 2627 * Update statistics 2628 */ 2629 --pm->pm_stats.resident_count; 2630 2631 /* Wired bit */ 2632 if (pv->pv_flags & PVF_WIRED) 2633 --pm->pm_stats.wired_count; 2634 2635 flags |= pv->pv_flags; 2636 2637 /* 2638 * Invalidate the PTEs. 2639 */ 2640 *ptep = 0; 2641 PTE_SYNC_CURRENT(pm, ptep); 2642 pmap_free_l2_bucket(pm, l2b, 1); 2643 2644 pool_put(&pmap_pv_pool, pv); 2645 pv = npv; 2646 /* 2647 * if we reach the end of the list and there are still 2648 * mappings, they might be able to be cached now. 2649 */ 2650 if (pv == NULL) { 2651 *pvp = NULL; 2652 if (!SLIST_EMPTY(&md->pvh_list)) 2653 pmap_vac_me_harder(md, pa, pm, 0); 2654 } 2655 pmap_release_pmap_lock(pm); 2656 } 2657 #ifdef PMAP_CACHE_VIPT 2658 /* 2659 * Its EXEC cache is now gone. 2660 */ 2661 if (PV_IS_EXEC_P(md->pvh_attrs)) 2662 PMAPCOUNT(exec_discarded_page_protect); 2663 md->pvh_attrs &= ~PVF_EXEC; 2664 KASSERT(md->urw_mappings == 0); 2665 KASSERT(md->uro_mappings == 0); 2666 if (md->krw_mappings == 0) 2667 md->pvh_attrs &= ~PVF_WRITE; 2668 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2669 #endif 2670 2671 if (flush) { 2672 /* 2673 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2674 * would need a subsequent call to pmap_update() to ensure 2675 * curpm->pm_cstate.cs_all is reset. Our callers are not 2676 * required to do that (see pmap(9)), so we can't modify 2677 * the current pmap's state. 2678 */ 2679 if (PV_BEEN_EXECD(flags)) 2680 cpu_tlb_flushID(); 2681 else 2682 cpu_tlb_flushD(); 2683 } 2684 cpu_cpwait(); 2685 } 2686 2687 /* 2688 * pmap_t pmap_create(void) 2689 * 2690 * Create a new pmap structure from scratch. 2691 */ 2692 pmap_t 2693 pmap_create(void) 2694 { 2695 pmap_t pm; 2696 2697 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2698 2699 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2700 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2701 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2702 2703 pm->pm_stats.wired_count = 0; 2704 pm->pm_stats.resident_count = 1; 2705 pm->pm_cstate.cs_all = 0; 2706 pmap_alloc_l1(pm); 2707 2708 /* 2709 * Note: The pool cache ensures that the pm_l2[] array is already 2710 * initialised to zero. 2711 */ 2712 2713 pmap_pinit(pm); 2714 2715 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2716 2717 return (pm); 2718 } 2719 2720 u_int 2721 arm32_mmap_flags(paddr_t pa) 2722 { 2723 /* 2724 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 2725 * and we're using the upper bits in page numbers to pass flags around 2726 * so we might as well use the same bits 2727 */ 2728 return (u_int)pa & PMAP_MD_MASK; 2729 } 2730 /* 2731 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2732 * u_int flags) 2733 * 2734 * Insert the given physical page (p) at 2735 * the specified virtual address (v) in the 2736 * target physical map with the protection requested. 2737 * 2738 * NB: This is the only routine which MAY NOT lazy-evaluate 2739 * or lose information. That is, this routine must actually 2740 * insert this page into the given map NOW. 2741 */ 2742 int 2743 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2744 { 2745 struct l2_bucket *l2b; 2746 struct vm_page *pg, *opg; 2747 struct pv_entry *pv; 2748 pt_entry_t *ptep, npte, opte; 2749 u_int nflags; 2750 u_int oflags; 2751 2752 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2753 2754 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2755 KDASSERT(((va | pa) & PGOFSET) == 0); 2756 2757 /* 2758 * Get a pointer to the page. Later on in this function, we 2759 * test for a managed page by checking pg != NULL. 2760 */ 2761 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2762 2763 nflags = 0; 2764 if (prot & VM_PROT_WRITE) 2765 nflags |= PVF_WRITE; 2766 if (prot & VM_PROT_EXECUTE) 2767 nflags |= PVF_EXEC; 2768 if (flags & PMAP_WIRED) 2769 nflags |= PVF_WIRED; 2770 2771 pmap_acquire_pmap_lock(pm); 2772 2773 /* 2774 * Fetch the L2 bucket which maps this page, allocating one if 2775 * necessary for user pmaps. 2776 */ 2777 if (pm == pmap_kernel()) 2778 l2b = pmap_get_l2_bucket(pm, va); 2779 else 2780 l2b = pmap_alloc_l2_bucket(pm, va); 2781 if (l2b == NULL) { 2782 if (flags & PMAP_CANFAIL) { 2783 pmap_release_pmap_lock(pm); 2784 return (ENOMEM); 2785 } 2786 panic("pmap_enter: failed to allocate L2 bucket"); 2787 } 2788 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2789 opte = *ptep; 2790 npte = pa; 2791 oflags = 0; 2792 2793 if (opte) { 2794 /* 2795 * There is already a mapping at this address. 2796 * If the physical address is different, lookup the 2797 * vm_page. 2798 */ 2799 if (l2pte_pa(opte) != pa) 2800 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2801 else 2802 opg = pg; 2803 } else 2804 opg = NULL; 2805 2806 if (pg) { 2807 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2808 2809 /* 2810 * This is to be a managed mapping. 2811 */ 2812 if ((flags & VM_PROT_ALL) || 2813 (md->pvh_attrs & PVF_REF)) { 2814 /* 2815 * - The access type indicates that we don't need 2816 * to do referenced emulation. 2817 * OR 2818 * - The physical page has already been referenced 2819 * so no need to re-do referenced emulation here. 2820 */ 2821 npte |= l2pte_set_readonly(L2_S_PROTO); 2822 2823 nflags |= PVF_REF; 2824 2825 if ((prot & VM_PROT_WRITE) != 0 && 2826 ((flags & VM_PROT_WRITE) != 0 || 2827 (md->pvh_attrs & PVF_MOD) != 0)) { 2828 /* 2829 * This is a writable mapping, and the 2830 * page's mod state indicates it has 2831 * already been modified. Make it 2832 * writable from the outset. 2833 */ 2834 npte = l2pte_set_writable(npte); 2835 nflags |= PVF_MOD; 2836 } 2837 } else { 2838 /* 2839 * Need to do page referenced emulation. 2840 */ 2841 npte |= L2_TYPE_INV; 2842 } 2843 2844 npte |= pte_l2_s_cache_mode; 2845 2846 if (pg == opg) { 2847 /* 2848 * We're changing the attrs of an existing mapping. 2849 */ 2850 #ifdef MULTIPROCESSOR 2851 KASSERT(uvm_page_locked_p(pg)); 2852 #endif 2853 oflags = pmap_modify_pv(md, pa, pm, va, 2854 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2855 PVF_MOD | PVF_REF, nflags); 2856 2857 #ifdef PMAP_CACHE_VIVT 2858 /* 2859 * We may need to flush the cache if we're 2860 * doing rw-ro... 2861 */ 2862 if (pm->pm_cstate.cs_cache_d && 2863 (oflags & PVF_NC) == 0 && 2864 l2pte_writable_p(opte) && 2865 (prot & VM_PROT_WRITE) == 0) 2866 cpu_dcache_wb_range(va, PAGE_SIZE); 2867 #endif 2868 } else { 2869 /* 2870 * New mapping, or changing the backing page 2871 * of an existing mapping. 2872 */ 2873 if (opg) { 2874 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2875 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2876 2877 /* 2878 * Replacing an existing mapping with a new one. 2879 * It is part of our managed memory so we 2880 * must remove it from the PV list 2881 */ 2882 #ifdef MULTIPROCESSOR 2883 KASSERT(uvm_page_locked_p(opg)); 2884 #endif 2885 pv = pmap_remove_pv(omd, opa, pm, va); 2886 pmap_vac_me_harder(omd, opa, pm, 0); 2887 oflags = pv->pv_flags; 2888 2889 #ifdef PMAP_CACHE_VIVT 2890 /* 2891 * If the old mapping was valid (ref/mod 2892 * emulation creates 'invalid' mappings 2893 * initially) then make sure to frob 2894 * the cache. 2895 */ 2896 if ((oflags & PVF_NC) == 0 && 2897 l2pte_valid(opte)) { 2898 if (PV_BEEN_EXECD(oflags)) { 2899 pmap_idcache_wbinv_range(pm, va, 2900 PAGE_SIZE); 2901 } else 2902 if (PV_BEEN_REFD(oflags)) { 2903 pmap_dcache_wb_range(pm, va, 2904 PAGE_SIZE, true, 2905 (oflags & PVF_WRITE) == 0); 2906 } 2907 } 2908 #endif 2909 } else 2910 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2911 if ((flags & PMAP_CANFAIL) == 0) 2912 panic("pmap_enter: no pv entries"); 2913 2914 if (pm != pmap_kernel()) 2915 pmap_free_l2_bucket(pm, l2b, 0); 2916 pmap_release_pmap_lock(pm); 2917 NPDEBUG(PDB_ENTER, 2918 printf("pmap_enter: ENOMEM\n")); 2919 return (ENOMEM); 2920 } 2921 2922 #ifdef MULTIPROCESSOR 2923 KASSERT(uvm_page_locked_p(pg)); 2924 #endif 2925 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2926 } 2927 } else { 2928 /* 2929 * We're mapping an unmanaged page. 2930 * These are always readable, and possibly writable, from 2931 * the get go as we don't need to track ref/mod status. 2932 */ 2933 npte |= l2pte_set_readonly(L2_S_PROTO); 2934 if (prot & VM_PROT_WRITE) 2935 npte = l2pte_set_writable(npte); 2936 2937 /* 2938 * Make sure the vector table is mapped cacheable 2939 */ 2940 if ((pm != pmap_kernel() && va == vector_page) || 2941 (flags & ARM32_MMAP_CACHEABLE)) { 2942 npte |= pte_l2_s_cache_mode; 2943 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 2944 npte |= pte_l2_s_wc_mode; 2945 } 2946 if (opg) { 2947 /* 2948 * Looks like there's an existing 'managed' mapping 2949 * at this address. 2950 */ 2951 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2952 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2953 2954 #ifdef MULTIPROCESSOR 2955 KASSERT(uvm_page_locked_p(opg)); 2956 #endif 2957 pv = pmap_remove_pv(omd, opa, pm, va); 2958 pmap_vac_me_harder(omd, opa, pm, 0); 2959 oflags = pv->pv_flags; 2960 2961 #ifdef PMAP_CACHE_VIVT 2962 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2963 if (PV_BEEN_EXECD(oflags)) 2964 pmap_idcache_wbinv_range(pm, va, 2965 PAGE_SIZE); 2966 else 2967 if (PV_BEEN_REFD(oflags)) 2968 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2969 true, (oflags & PVF_WRITE) == 0); 2970 } 2971 #endif 2972 pool_put(&pmap_pv_pool, pv); 2973 } 2974 } 2975 2976 /* 2977 * Make sure userland mappings get the right permissions 2978 */ 2979 if (pm != pmap_kernel() && va != vector_page) 2980 npte |= L2_S_PROT_U; 2981 2982 /* 2983 * Keep the stats up to date 2984 */ 2985 if (opte == 0) { 2986 l2b->l2b_occupancy++; 2987 pm->pm_stats.resident_count++; 2988 } 2989 2990 NPDEBUG(PDB_ENTER, 2991 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2992 2993 /* 2994 * If this is just a wiring change, the two PTEs will be 2995 * identical, so there's no need to update the page table. 2996 */ 2997 if (npte != opte) { 2998 bool is_cached = pmap_is_cached(pm); 2999 3000 *ptep = npte; 3001 PTE_SYNC(ptep); 3002 if (is_cached) { 3003 /* 3004 * We only need to frob the cache/tlb if this pmap 3005 * is current 3006 */ 3007 if (va != vector_page && l2pte_valid(npte)) { 3008 /* 3009 * This mapping is likely to be accessed as 3010 * soon as we return to userland. Fix up the 3011 * L1 entry to avoid taking another 3012 * page/domain fault. 3013 */ 3014 pd_entry_t *pl1pd, l1pd; 3015 3016 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3017 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3018 L1_C_PROTO; 3019 if (*pl1pd != l1pd) { 3020 *pl1pd = l1pd; 3021 PTE_SYNC(pl1pd); 3022 } 3023 } 3024 } 3025 3026 if (PV_BEEN_EXECD(oflags)) 3027 pmap_tlb_flushID_SE(pm, va); 3028 else 3029 if (PV_BEEN_REFD(oflags)) 3030 pmap_tlb_flushD_SE(pm, va); 3031 3032 NPDEBUG(PDB_ENTER, 3033 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3034 is_cached, pm->pm_cstate.cs_all)); 3035 3036 if (pg != NULL) { 3037 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3038 3039 #ifdef MULTIPROCESSOR 3040 KASSERT(uvm_page_locked_p(pg)); 3041 #endif 3042 pmap_vac_me_harder(md, pa, pm, va); 3043 } 3044 } 3045 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3046 if (pg) { 3047 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3048 3049 #ifdef MULTIPROCESSOR 3050 KASSERT(uvm_page_locked_p(pg)); 3051 #endif 3052 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3053 KASSERTMSG(arm_cache_prefer_mask == 0 || ((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0), 3054 "pg %p: attrs=%#x urw=%u krw=%u", pg, 3055 md->pvh_attrs, md->urw_mappings, md->krw_mappings); 3056 } 3057 #endif 3058 3059 pmap_release_pmap_lock(pm); 3060 3061 return (0); 3062 } 3063 3064 /* 3065 * pmap_remove() 3066 * 3067 * pmap_remove is responsible for nuking a number of mappings for a range 3068 * of virtual address space in the current pmap. To do this efficiently 3069 * is interesting, because in a number of cases a wide virtual address 3070 * range may be supplied that contains few actual mappings. So, the 3071 * optimisations are: 3072 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3073 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3074 * maybe do just a partial cache clean. This path of execution is 3075 * complicated by the fact that the cache must be flushed _before_ 3076 * the PTE is nuked, being a VAC :-) 3077 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3078 * all invalidations until pmap_update(), since pmap_remove_all() has 3079 * already flushed the cache. 3080 * 4. Maybe later fast-case a single page, but I don't think this is 3081 * going to make _that_ much difference overall. 3082 */ 3083 3084 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3085 3086 void 3087 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3088 { 3089 struct l2_bucket *l2b; 3090 vaddr_t next_bucket; 3091 pt_entry_t *ptep; 3092 u_int cleanlist_idx, total, cnt; 3093 struct { 3094 vaddr_t va; 3095 pt_entry_t *ptep; 3096 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3097 u_int mappings, is_exec, is_refd; 3098 3099 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3100 "eva=%08lx\n", pm, sva, eva)); 3101 3102 /* 3103 * we lock in the pmap => pv_head direction 3104 */ 3105 pmap_acquire_pmap_lock(pm); 3106 3107 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3108 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3109 if (pm->pm_cstate.cs_tlb == 0) 3110 pm->pm_remove_all = true; 3111 } else 3112 cleanlist_idx = 0; 3113 3114 total = 0; 3115 3116 while (sva < eva) { 3117 /* 3118 * Do one L2 bucket's worth at a time. 3119 */ 3120 next_bucket = L2_NEXT_BUCKET(sva); 3121 if (next_bucket > eva) 3122 next_bucket = eva; 3123 3124 l2b = pmap_get_l2_bucket(pm, sva); 3125 if (l2b == NULL) { 3126 sva = next_bucket; 3127 continue; 3128 } 3129 3130 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3131 3132 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3133 struct vm_page *pg; 3134 pt_entry_t pte; 3135 paddr_t pa; 3136 3137 pte = *ptep; 3138 3139 if (pte == 0) { 3140 /* Nothing here, move along */ 3141 continue; 3142 } 3143 3144 pa = l2pte_pa(pte); 3145 is_exec = 0; 3146 is_refd = 1; 3147 3148 /* 3149 * Update flags. In a number of circumstances, 3150 * we could cluster a lot of these and do a 3151 * number of sequential pages in one go. 3152 */ 3153 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3154 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3155 struct pv_entry *pv; 3156 3157 #ifdef MULTIPROCESSOR 3158 KASSERT(uvm_page_locked_p(pg)); 3159 #endif 3160 pv = pmap_remove_pv(md, pa, pm, sva); 3161 pmap_vac_me_harder(md, pa, pm, 0); 3162 if (pv != NULL) { 3163 if (pm->pm_remove_all == false) { 3164 is_exec = 3165 PV_BEEN_EXECD(pv->pv_flags); 3166 is_refd = 3167 PV_BEEN_REFD(pv->pv_flags); 3168 } 3169 pool_put(&pmap_pv_pool, pv); 3170 } 3171 } 3172 mappings++; 3173 3174 if (!l2pte_valid(pte)) { 3175 /* 3176 * Ref/Mod emulation is still active for this 3177 * mapping, therefore it is has not yet been 3178 * accessed. No need to frob the cache/tlb. 3179 */ 3180 *ptep = 0; 3181 PTE_SYNC_CURRENT(pm, ptep); 3182 continue; 3183 } 3184 3185 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3186 /* Add to the clean list. */ 3187 cleanlist[cleanlist_idx].ptep = ptep; 3188 cleanlist[cleanlist_idx].va = 3189 sva | (is_exec & 1); 3190 cleanlist_idx++; 3191 } else 3192 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3193 /* Nuke everything if needed. */ 3194 #ifdef PMAP_CACHE_VIVT 3195 pmap_idcache_wbinv_all(pm); 3196 #endif 3197 pmap_tlb_flushID(pm); 3198 3199 /* 3200 * Roll back the previous PTE list, 3201 * and zero out the current PTE. 3202 */ 3203 for (cnt = 0; 3204 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3205 *cleanlist[cnt].ptep = 0; 3206 PTE_SYNC(cleanlist[cnt].ptep); 3207 } 3208 *ptep = 0; 3209 PTE_SYNC(ptep); 3210 cleanlist_idx++; 3211 pm->pm_remove_all = true; 3212 } else { 3213 *ptep = 0; 3214 PTE_SYNC(ptep); 3215 if (pm->pm_remove_all == false) { 3216 if (is_exec) 3217 pmap_tlb_flushID_SE(pm, sva); 3218 else 3219 if (is_refd) 3220 pmap_tlb_flushD_SE(pm, sva); 3221 } 3222 } 3223 } 3224 3225 /* 3226 * Deal with any left overs 3227 */ 3228 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3229 total += cleanlist_idx; 3230 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3231 if (pm->pm_cstate.cs_all != 0) { 3232 vaddr_t clva = cleanlist[cnt].va & ~1; 3233 if (cleanlist[cnt].va & 1) { 3234 #ifdef PMAP_CACHE_VIVT 3235 pmap_idcache_wbinv_range(pm, 3236 clva, PAGE_SIZE); 3237 #endif 3238 pmap_tlb_flushID_SE(pm, clva); 3239 } else { 3240 #ifdef PMAP_CACHE_VIVT 3241 pmap_dcache_wb_range(pm, 3242 clva, PAGE_SIZE, true, 3243 false); 3244 #endif 3245 pmap_tlb_flushD_SE(pm, clva); 3246 } 3247 } 3248 *cleanlist[cnt].ptep = 0; 3249 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3250 } 3251 3252 /* 3253 * If it looks like we're removing a whole bunch 3254 * of mappings, it's faster to just write-back 3255 * the whole cache now and defer TLB flushes until 3256 * pmap_update() is called. 3257 */ 3258 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3259 cleanlist_idx = 0; 3260 else { 3261 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3262 #ifdef PMAP_CACHE_VIVT 3263 pmap_idcache_wbinv_all(pm); 3264 #endif 3265 pm->pm_remove_all = true; 3266 } 3267 } 3268 3269 pmap_free_l2_bucket(pm, l2b, mappings); 3270 pm->pm_stats.resident_count -= mappings; 3271 } 3272 3273 pmap_release_pmap_lock(pm); 3274 } 3275 3276 #ifdef PMAP_CACHE_VIPT 3277 static struct pv_entry * 3278 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3279 { 3280 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3281 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3282 struct pv_entry *pv; 3283 3284 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3285 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3286 3287 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3288 KASSERT(pv); 3289 KASSERT(pv->pv_flags & PVF_KENTRY); 3290 3291 /* 3292 * If we are removing a writeable mapping to a cached exec page, 3293 * if it's the last mapping then clear it execness other sync 3294 * the page to the icache. 3295 */ 3296 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3297 && (pv->pv_flags & PVF_WRITE) != 0) { 3298 if (SLIST_EMPTY(&md->pvh_list)) { 3299 md->pvh_attrs &= ~PVF_EXEC; 3300 PMAPCOUNT(exec_discarded_kremove); 3301 } else { 3302 pmap_syncicache_page(md, pa); 3303 PMAPCOUNT(exec_synced_kremove); 3304 } 3305 } 3306 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3307 3308 return pv; 3309 } 3310 #endif /* PMAP_CACHE_VIPT */ 3311 3312 /* 3313 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3314 * 3315 * We assume there is already sufficient KVM space available 3316 * to do this, as we can't allocate L2 descriptor tables/metadata 3317 * from here. 3318 */ 3319 void 3320 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3321 { 3322 struct l2_bucket *l2b; 3323 pt_entry_t *ptep, opte; 3324 #ifdef PMAP_CACHE_VIVT 3325 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3326 #endif 3327 #ifdef PMAP_CACHE_VIPT 3328 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3329 struct vm_page *opg; 3330 struct pv_entry *pv = NULL; 3331 #endif 3332 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3333 3334 NPDEBUG(PDB_KENTER, 3335 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3336 va, pa, prot)); 3337 3338 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3339 KDASSERT(l2b != NULL); 3340 3341 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3342 opte = *ptep; 3343 3344 if (opte == 0) { 3345 PMAPCOUNT(kenter_mappings); 3346 l2b->l2b_occupancy++; 3347 } else { 3348 PMAPCOUNT(kenter_remappings); 3349 #ifdef PMAP_CACHE_VIPT 3350 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3351 #ifdef DIAGNOSTIC 3352 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3353 #endif 3354 if (opg) { 3355 KASSERT(opg != pg); 3356 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3357 KASSERT((flags & PMAP_KMPAGE) == 0); 3358 pv = pmap_kremove_pg(opg, va); 3359 } 3360 #endif 3361 if (l2pte_valid(opte)) { 3362 #ifdef PMAP_CACHE_VIVT 3363 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3364 #endif 3365 cpu_tlb_flushD_SE(va); 3366 cpu_cpwait(); 3367 } 3368 } 3369 3370 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3371 | ((flags & PMAP_NOCACHE) ? 0 : pte_l2_s_cache_mode); 3372 PTE_SYNC(ptep); 3373 3374 if (pg) { 3375 #ifdef MULTIPROCESSOR 3376 KASSERT(uvm_page_locked_p(pg)); 3377 #endif 3378 if (flags & PMAP_KMPAGE) { 3379 KASSERT(md->urw_mappings == 0); 3380 KASSERT(md->uro_mappings == 0); 3381 KASSERT(md->krw_mappings == 0); 3382 KASSERT(md->kro_mappings == 0); 3383 #ifdef PMAP_CACHE_VIPT 3384 KASSERT(pv == NULL); 3385 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3386 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3387 /* if there is a color conflict, evict from cache. */ 3388 if (pmap_is_page_colored_p(md) 3389 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3390 PMAPCOUNT(vac_color_change); 3391 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3392 } else if (md->pvh_attrs & PVF_MULTCLR) { 3393 /* 3394 * If this page has multiple colors, expunge 3395 * them. 3396 */ 3397 PMAPCOUNT(vac_flush_lots2); 3398 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3399 } 3400 md->pvh_attrs &= PAGE_SIZE - 1; 3401 md->pvh_attrs |= PVF_KMPAGE 3402 | PVF_COLORED | PVF_DIRTY 3403 | (va & arm_cache_prefer_mask); 3404 #endif 3405 #ifdef PMAP_CACHE_VIVT 3406 md->pvh_attrs |= PVF_KMPAGE; 3407 #endif 3408 pmap_kmpages++; 3409 #ifdef PMAP_CACHE_VIPT 3410 } else { 3411 if (pv == NULL) { 3412 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3413 KASSERT(pv != NULL); 3414 } 3415 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3416 PVF_WIRED | PVF_KENTRY 3417 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3418 if ((prot & VM_PROT_WRITE) 3419 && !(md->pvh_attrs & PVF_NC)) 3420 md->pvh_attrs |= PVF_DIRTY; 3421 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3422 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3423 #endif 3424 } 3425 #ifdef PMAP_CACHE_VIPT 3426 } else { 3427 if (pv != NULL) 3428 pool_put(&pmap_pv_pool, pv); 3429 #endif 3430 } 3431 } 3432 3433 void 3434 pmap_kremove(vaddr_t va, vsize_t len) 3435 { 3436 struct l2_bucket *l2b; 3437 pt_entry_t *ptep, *sptep, opte; 3438 vaddr_t next_bucket, eva; 3439 u_int mappings; 3440 struct vm_page *opg; 3441 3442 PMAPCOUNT(kenter_unmappings); 3443 3444 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3445 va, len)); 3446 3447 eva = va + len; 3448 3449 while (va < eva) { 3450 next_bucket = L2_NEXT_BUCKET(va); 3451 if (next_bucket > eva) 3452 next_bucket = eva; 3453 3454 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3455 KDASSERT(l2b != NULL); 3456 3457 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3458 mappings = 0; 3459 3460 while (va < next_bucket) { 3461 opte = *ptep; 3462 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3463 if (opg) { 3464 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3465 3466 if (omd->pvh_attrs & PVF_KMPAGE) { 3467 KASSERT(omd->urw_mappings == 0); 3468 KASSERT(omd->uro_mappings == 0); 3469 KASSERT(omd->krw_mappings == 0); 3470 KASSERT(omd->kro_mappings == 0); 3471 omd->pvh_attrs &= ~PVF_KMPAGE; 3472 #ifdef PMAP_CACHE_VIPT 3473 omd->pvh_attrs &= ~PVF_WRITE; 3474 #endif 3475 pmap_kmpages--; 3476 #ifdef PMAP_CACHE_VIPT 3477 } else { 3478 pool_put(&pmap_pv_pool, 3479 pmap_kremove_pg(opg, va)); 3480 #endif 3481 } 3482 } 3483 if (l2pte_valid(opte)) { 3484 #ifdef PMAP_CACHE_VIVT 3485 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3486 #endif 3487 cpu_tlb_flushD_SE(va); 3488 } 3489 if (opte) { 3490 *ptep = 0; 3491 mappings++; 3492 } 3493 va += PAGE_SIZE; 3494 ptep++; 3495 } 3496 KDASSERT(mappings <= l2b->l2b_occupancy); 3497 l2b->l2b_occupancy -= mappings; 3498 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3499 } 3500 cpu_cpwait(); 3501 } 3502 3503 bool 3504 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3505 { 3506 struct l2_dtable *l2; 3507 pd_entry_t *pl1pd, l1pd; 3508 pt_entry_t *ptep, pte; 3509 paddr_t pa; 3510 u_int l1idx; 3511 3512 pmap_acquire_pmap_lock(pm); 3513 3514 l1idx = L1_IDX(va); 3515 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3516 l1pd = *pl1pd; 3517 3518 if (l1pte_section_p(l1pd)) { 3519 /* 3520 * These should only happen for pmap_kernel() 3521 */ 3522 KDASSERT(pm == pmap_kernel()); 3523 pmap_release_pmap_lock(pm); 3524 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3525 if (l1pte_supersection_p(l1pd)) { 3526 pa = (l1pd & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3527 } else 3528 #endif 3529 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3530 } else { 3531 /* 3532 * Note that we can't rely on the validity of the L1 3533 * descriptor as an indication that a mapping exists. 3534 * We have to look it up in the L2 dtable. 3535 */ 3536 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3537 3538 if (l2 == NULL || 3539 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3540 pmap_release_pmap_lock(pm); 3541 return false; 3542 } 3543 3544 ptep = &ptep[l2pte_index(va)]; 3545 pte = *ptep; 3546 pmap_release_pmap_lock(pm); 3547 3548 if (pte == 0) 3549 return false; 3550 3551 switch (pte & L2_TYPE_MASK) { 3552 case L2_TYPE_L: 3553 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3554 break; 3555 3556 default: 3557 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3558 break; 3559 } 3560 } 3561 3562 if (pap != NULL) 3563 *pap = pa; 3564 3565 return true; 3566 } 3567 3568 void 3569 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3570 { 3571 struct l2_bucket *l2b; 3572 pt_entry_t *ptep, pte; 3573 vaddr_t next_bucket; 3574 u_int flags; 3575 u_int clr_mask; 3576 int flush; 3577 3578 NPDEBUG(PDB_PROTECT, 3579 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3580 pm, sva, eva, prot)); 3581 3582 if ((prot & VM_PROT_READ) == 0) { 3583 pmap_remove(pm, sva, eva); 3584 return; 3585 } 3586 3587 if (prot & VM_PROT_WRITE) { 3588 /* 3589 * If this is a read->write transition, just ignore it and let 3590 * uvm_fault() take care of it later. 3591 */ 3592 return; 3593 } 3594 3595 pmap_acquire_pmap_lock(pm); 3596 3597 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3598 flags = 0; 3599 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3600 3601 while (sva < eva) { 3602 next_bucket = L2_NEXT_BUCKET(sva); 3603 if (next_bucket > eva) 3604 next_bucket = eva; 3605 3606 l2b = pmap_get_l2_bucket(pm, sva); 3607 if (l2b == NULL) { 3608 sva = next_bucket; 3609 continue; 3610 } 3611 3612 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3613 3614 while (sva < next_bucket) { 3615 pte = *ptep; 3616 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3617 struct vm_page *pg; 3618 u_int f; 3619 3620 #ifdef PMAP_CACHE_VIVT 3621 /* 3622 * OK, at this point, we know we're doing 3623 * write-protect operation. If the pmap is 3624 * active, write-back the page. 3625 */ 3626 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3627 false, false); 3628 #endif 3629 3630 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3631 pte = l2pte_set_readonly(pte); 3632 *ptep = pte; 3633 PTE_SYNC(ptep); 3634 3635 if (pg != NULL) { 3636 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3637 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3638 3639 #ifdef MULTIPROCESSOR 3640 KASSERT(uvm_page_locked_p(pg)); 3641 #endif 3642 f = pmap_modify_pv(md, pa, pm, sva, 3643 clr_mask, 0); 3644 pmap_vac_me_harder(md, pa, pm, sva); 3645 } else { 3646 f = PVF_REF | PVF_EXEC; 3647 } 3648 3649 if (flush >= 0) { 3650 flush++; 3651 flags |= f; 3652 } else 3653 if (PV_BEEN_EXECD(f)) 3654 pmap_tlb_flushID_SE(pm, sva); 3655 else 3656 if (PV_BEEN_REFD(f)) 3657 pmap_tlb_flushD_SE(pm, sva); 3658 } 3659 3660 sva += PAGE_SIZE; 3661 ptep++; 3662 } 3663 } 3664 3665 pmap_release_pmap_lock(pm); 3666 3667 if (flush) { 3668 if (PV_BEEN_EXECD(flags)) 3669 pmap_tlb_flushID(pm); 3670 else 3671 if (PV_BEEN_REFD(flags)) 3672 pmap_tlb_flushD(pm); 3673 } 3674 } 3675 3676 void 3677 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3678 { 3679 struct l2_bucket *l2b; 3680 pt_entry_t *ptep; 3681 vaddr_t next_bucket; 3682 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3683 3684 NPDEBUG(PDB_EXEC, 3685 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3686 pm, sva, eva)); 3687 3688 pmap_acquire_pmap_lock(pm); 3689 3690 while (sva < eva) { 3691 next_bucket = L2_NEXT_BUCKET(sva); 3692 if (next_bucket > eva) 3693 next_bucket = eva; 3694 3695 l2b = pmap_get_l2_bucket(pm, sva); 3696 if (l2b == NULL) { 3697 sva = next_bucket; 3698 continue; 3699 } 3700 3701 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3702 sva < next_bucket; 3703 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3704 if (l2pte_valid(*ptep)) { 3705 cpu_icache_sync_range(sva, 3706 min(page_size, eva - sva)); 3707 } 3708 } 3709 } 3710 3711 pmap_release_pmap_lock(pm); 3712 } 3713 3714 void 3715 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3716 { 3717 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3718 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3719 3720 NPDEBUG(PDB_PROTECT, 3721 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3722 md, pa, prot)); 3723 3724 #ifdef MULTIPROCESSOR 3725 KASSERT(uvm_page_locked_p(pg)); 3726 #endif 3727 3728 switch(prot) { 3729 case VM_PROT_READ|VM_PROT_WRITE: 3730 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3731 pmap_clearbit(md, pa, PVF_EXEC); 3732 break; 3733 #endif 3734 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3735 break; 3736 3737 case VM_PROT_READ: 3738 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3739 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3740 break; 3741 #endif 3742 case VM_PROT_READ|VM_PROT_EXECUTE: 3743 pmap_clearbit(md, pa, PVF_WRITE); 3744 break; 3745 3746 default: 3747 pmap_page_remove(md, pa); 3748 break; 3749 } 3750 } 3751 3752 /* 3753 * pmap_clear_modify: 3754 * 3755 * Clear the "modified" attribute for a page. 3756 */ 3757 bool 3758 pmap_clear_modify(struct vm_page *pg) 3759 { 3760 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3761 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3762 bool rv; 3763 3764 #ifdef MULTIPROCESSOR 3765 KASSERT(uvm_page_locked_p(pg)); 3766 #endif 3767 3768 if (md->pvh_attrs & PVF_MOD) { 3769 rv = true; 3770 #ifdef PMAP_CACHE_VIPT 3771 /* 3772 * If we are going to clear the modified bit and there are 3773 * no other modified bits set, flush the page to memory and 3774 * mark it clean. 3775 */ 3776 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3777 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3778 #endif 3779 pmap_clearbit(md, pa, PVF_MOD); 3780 } else 3781 rv = false; 3782 3783 return (rv); 3784 } 3785 3786 /* 3787 * pmap_clear_reference: 3788 * 3789 * Clear the "referenced" attribute for a page. 3790 */ 3791 bool 3792 pmap_clear_reference(struct vm_page *pg) 3793 { 3794 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3795 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3796 bool rv; 3797 3798 #ifdef MULTIPROCESSOR 3799 KASSERT(uvm_page_locked_p(pg)); 3800 #endif 3801 3802 if (md->pvh_attrs & PVF_REF) { 3803 rv = true; 3804 pmap_clearbit(md, pa, PVF_REF); 3805 } else 3806 rv = false; 3807 3808 return (rv); 3809 } 3810 3811 /* 3812 * pmap_is_modified: 3813 * 3814 * Test if a page has the "modified" attribute. 3815 */ 3816 /* See <arm/arm32/pmap.h> */ 3817 3818 /* 3819 * pmap_is_referenced: 3820 * 3821 * Test if a page has the "referenced" attribute. 3822 */ 3823 /* See <arm/arm32/pmap.h> */ 3824 3825 int 3826 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3827 { 3828 struct l2_dtable *l2; 3829 struct l2_bucket *l2b; 3830 pd_entry_t *pl1pd, l1pd; 3831 pt_entry_t *ptep, pte; 3832 paddr_t pa; 3833 u_int l1idx; 3834 int rv = 0; 3835 3836 pmap_acquire_pmap_lock(pm); 3837 3838 l1idx = L1_IDX(va); 3839 3840 /* 3841 * If there is no l2_dtable for this address, then the process 3842 * has no business accessing it. 3843 * 3844 * Note: This will catch userland processes trying to access 3845 * kernel addresses. 3846 */ 3847 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3848 if (l2 == NULL) 3849 goto out; 3850 3851 /* 3852 * Likewise if there is no L2 descriptor table 3853 */ 3854 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3855 if (l2b->l2b_kva == NULL) 3856 goto out; 3857 3858 /* 3859 * Check the PTE itself. 3860 */ 3861 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3862 pte = *ptep; 3863 if (pte == 0) 3864 goto out; 3865 3866 /* 3867 * Catch a userland access to the vector page mapped at 0x0 3868 */ 3869 if (user && (pte & L2_S_PROT_U) == 0) 3870 goto out; 3871 3872 pa = l2pte_pa(pte); 3873 3874 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3875 /* 3876 * This looks like a good candidate for "page modified" 3877 * emulation... 3878 */ 3879 struct pv_entry *pv; 3880 struct vm_page *pg; 3881 3882 /* Extract the physical address of the page */ 3883 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3884 goto out; 3885 3886 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3887 3888 /* Get the current flags for this page. */ 3889 #ifdef MULTIPROCESSOR 3890 KASSERT(uvm_page_locked_p(pg)); 3891 #endif 3892 3893 pv = pmap_find_pv(md, pm, va); 3894 if (pv == NULL) { 3895 goto out; 3896 } 3897 3898 /* 3899 * Do the flags say this page is writable? If not then it 3900 * is a genuine write fault. If yes then the write fault is 3901 * our fault as we did not reflect the write access in the 3902 * PTE. Now we know a write has occurred we can correct this 3903 * and also set the modified bit 3904 */ 3905 if ((pv->pv_flags & PVF_WRITE) == 0) { 3906 goto out; 3907 } 3908 3909 NPDEBUG(PDB_FOLLOW, 3910 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3911 pm, va, pa)); 3912 3913 md->pvh_attrs |= PVF_REF | PVF_MOD; 3914 pv->pv_flags |= PVF_REF | PVF_MOD; 3915 #ifdef PMAP_CACHE_VIPT 3916 /* 3917 * If there are cacheable mappings for this page, mark it dirty. 3918 */ 3919 if ((md->pvh_attrs & PVF_NC) == 0) 3920 md->pvh_attrs |= PVF_DIRTY; 3921 #endif 3922 3923 /* 3924 * Re-enable write permissions for the page. No need to call 3925 * pmap_vac_me_harder(), since this is just a 3926 * modified-emulation fault, and the PVF_WRITE bit isn't 3927 * changing. We've already set the cacheable bits based on 3928 * the assumption that we can write to this page. 3929 */ 3930 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3931 PTE_SYNC(ptep); 3932 rv = 1; 3933 } else 3934 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3935 /* 3936 * This looks like a good candidate for "page referenced" 3937 * emulation. 3938 */ 3939 struct pv_entry *pv; 3940 struct vm_page *pg; 3941 3942 /* Extract the physical address of the page */ 3943 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3944 goto out; 3945 3946 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3947 3948 /* Get the current flags for this page. */ 3949 #ifdef MULTIPROCESSOR 3950 KASSERT(uvm_page_locked_p(pg)); 3951 #endif 3952 3953 pv = pmap_find_pv(md, pm, va); 3954 if (pv == NULL) { 3955 goto out; 3956 } 3957 3958 md->pvh_attrs |= PVF_REF; 3959 pv->pv_flags |= PVF_REF; 3960 3961 NPDEBUG(PDB_FOLLOW, 3962 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3963 pm, va, pa)); 3964 3965 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3966 PTE_SYNC(ptep); 3967 rv = 1; 3968 } 3969 3970 /* 3971 * We know there is a valid mapping here, so simply 3972 * fix up the L1 if necessary. 3973 */ 3974 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3975 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3976 if (*pl1pd != l1pd) { 3977 *pl1pd = l1pd; 3978 PTE_SYNC(pl1pd); 3979 rv = 1; 3980 } 3981 3982 #ifdef CPU_SA110 3983 /* 3984 * There are bugs in the rev K SA110. This is a check for one 3985 * of them. 3986 */ 3987 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3988 curcpu()->ci_arm_cpurev < 3) { 3989 /* Always current pmap */ 3990 if (l2pte_valid(pte)) { 3991 extern int kernel_debug; 3992 if (kernel_debug & 1) { 3993 struct proc *p = curlwp->l_proc; 3994 printf("prefetch_abort: page is already " 3995 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3996 printf("prefetch_abort: pc=%08lx proc=%p " 3997 "process=%s\n", va, p, p->p_comm); 3998 printf("prefetch_abort: far=%08x fs=%x\n", 3999 cpu_faultaddress(), cpu_faultstatus()); 4000 } 4001 #ifdef DDB 4002 if (kernel_debug & 2) 4003 Debugger(); 4004 #endif 4005 rv = 1; 4006 } 4007 } 4008 #endif /* CPU_SA110 */ 4009 4010 /* 4011 * If 'rv == 0' at this point, it generally indicates that there is a 4012 * stale TLB entry for the faulting address. That might be due to a 4013 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4014 */ 4015 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1 4016 && pmap_needs_pte_sync == 0) { 4017 pmap_needs_pte_sync = 1; 4018 PTE_SYNC(ptep); 4019 rv = 1; 4020 } 4021 4022 #ifdef DEBUG 4023 /* 4024 * If 'rv == 0' at this point, it generally indicates that there is a 4025 * stale TLB entry for the faulting address. This happens when two or 4026 * more processes are sharing an L1. Since we don't flush the TLB on 4027 * a context switch between such processes, we can take domain faults 4028 * for mappings which exist at the same VA in both processes. EVEN IF 4029 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4030 * example. 4031 * 4032 * This is extremely likely to happen if pmap_enter() updated the L1 4033 * entry for a recently entered mapping. In this case, the TLB is 4034 * flushed for the new mapping, but there may still be TLB entries for 4035 * other mappings belonging to other processes in the 1MB range 4036 * covered by the L1 entry. 4037 * 4038 * Since 'rv == 0', we know that the L1 already contains the correct 4039 * value, so the fault must be due to a stale TLB entry. 4040 * 4041 * Since we always need to flush the TLB anyway in the case where we 4042 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4043 * stale TLB entries dynamically. 4044 * 4045 * However, the above condition can ONLY happen if the current L1 is 4046 * being shared. If it happens when the L1 is unshared, it indicates 4047 * that other parts of the pmap are not doing their job WRT managing 4048 * the TLB. 4049 */ 4050 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4051 extern int last_fault_code; 4052 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4053 pm, va, ftype); 4054 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4055 l2, l2b, ptep, pl1pd); 4056 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4057 pte, l1pd, last_fault_code); 4058 #ifdef DDB 4059 Debugger(); 4060 #endif 4061 } 4062 #endif 4063 4064 cpu_tlb_flushID_SE(va); 4065 cpu_cpwait(); 4066 4067 rv = 1; 4068 4069 out: 4070 pmap_release_pmap_lock(pm); 4071 4072 return (rv); 4073 } 4074 4075 /* 4076 * Routine: pmap_procwr 4077 * 4078 * Function: 4079 * Synchronize caches corresponding to [addr, addr+len) in p. 4080 * 4081 */ 4082 void 4083 pmap_procwr(struct proc *p, vaddr_t va, int len) 4084 { 4085 /* We only need to do anything if it is the current process. */ 4086 if (p == curproc) 4087 cpu_icache_sync_range(va, len); 4088 } 4089 4090 /* 4091 * Routine: pmap_unwire 4092 * Function: Clear the wired attribute for a map/virtual-address pair. 4093 * 4094 * In/out conditions: 4095 * The mapping must already exist in the pmap. 4096 */ 4097 void 4098 pmap_unwire(pmap_t pm, vaddr_t va) 4099 { 4100 struct l2_bucket *l2b; 4101 pt_entry_t *ptep, pte; 4102 struct vm_page *pg; 4103 paddr_t pa; 4104 4105 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4106 4107 pmap_acquire_pmap_lock(pm); 4108 4109 l2b = pmap_get_l2_bucket(pm, va); 4110 KDASSERT(l2b != NULL); 4111 4112 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4113 pte = *ptep; 4114 4115 /* Extract the physical address of the page */ 4116 pa = l2pte_pa(pte); 4117 4118 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4119 /* Update the wired bit in the pv entry for this page. */ 4120 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4121 4122 #ifdef MULTIPROCESSOR 4123 KASSERT(uvm_page_locked_p(pg)); 4124 #endif 4125 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4126 } 4127 4128 pmap_release_pmap_lock(pm); 4129 } 4130 4131 void 4132 pmap_activate(struct lwp *l) 4133 { 4134 extern int block_userspace_access; 4135 pmap_t opm, npm, rpm; 4136 uint32_t odacr, ndacr; 4137 int oldirqstate; 4138 4139 /* 4140 * If activating a non-current lwp or the current lwp is 4141 * already active, just return. 4142 */ 4143 if (l != curlwp || 4144 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4145 return; 4146 4147 npm = l->l_proc->p_vmspace->vm_map.pmap; 4148 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4149 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4150 4151 /* 4152 * If TTB and DACR are unchanged, short-circuit all the 4153 * TLB/cache management stuff. 4154 */ 4155 if (pmap_previous_active_lwp != NULL) { 4156 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4157 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4158 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4159 4160 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4161 goto all_done; 4162 } else 4163 opm = NULL; 4164 4165 PMAPCOUNT(activations); 4166 block_userspace_access = 1; 4167 4168 /* 4169 * If switching to a user vmspace which is different to the 4170 * most recent one, and the most recent one is potentially 4171 * live in the cache, we must write-back and invalidate the 4172 * entire cache. 4173 */ 4174 rpm = pmap_recent_user; 4175 4176 /* 4177 * XXXSCW: There's a corner case here which can leave turds in the cache as 4178 * reported in kern/41058. They're probably left over during tear-down and 4179 * switching away from an exiting process. Until the root cause is identified 4180 * and fixed, zap the cache when switching pmaps. This will result in a few 4181 * unnecessary cache flushes, but that's better than silently corrupting data. 4182 */ 4183 #if 0 4184 if (npm != pmap_kernel() && rpm && npm != rpm && 4185 rpm->pm_cstate.cs_cache) { 4186 rpm->pm_cstate.cs_cache = 0; 4187 #ifdef PMAP_CACHE_VIVT 4188 cpu_idcache_wbinv_all(); 4189 #endif 4190 } 4191 #else 4192 if (rpm) { 4193 rpm->pm_cstate.cs_cache = 0; 4194 if (npm == pmap_kernel()) 4195 pmap_recent_user = NULL; 4196 #ifdef PMAP_CACHE_VIVT 4197 cpu_idcache_wbinv_all(); 4198 #endif 4199 } 4200 #endif 4201 4202 /* No interrupts while we frob the TTB/DACR */ 4203 oldirqstate = disable_interrupts(IF32_bits); 4204 4205 /* 4206 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4207 * entry corresponding to 'vector_page' in the incoming L1 table 4208 * before switching to it otherwise subsequent interrupts/exceptions 4209 * (including domain faults!) will jump into hyperspace. 4210 */ 4211 if (npm->pm_pl1vec != NULL) { 4212 cpu_tlb_flushID_SE((u_int)vector_page); 4213 cpu_cpwait(); 4214 *npm->pm_pl1vec = npm->pm_l1vec; 4215 PTE_SYNC(npm->pm_pl1vec); 4216 } 4217 4218 cpu_domains(ndacr); 4219 4220 if (npm == pmap_kernel() || npm == rpm) { 4221 /* 4222 * Switching to a kernel thread, or back to the 4223 * same user vmspace as before... Simply update 4224 * the TTB (no TLB flush required) 4225 */ 4226 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4227 cpu_cpwait(); 4228 } else { 4229 /* 4230 * Otherwise, update TTB and flush TLB 4231 */ 4232 cpu_context_switch(npm->pm_l1->l1_physaddr); 4233 if (rpm != NULL) 4234 rpm->pm_cstate.cs_tlb = 0; 4235 } 4236 4237 restore_interrupts(oldirqstate); 4238 4239 block_userspace_access = 0; 4240 4241 all_done: 4242 /* 4243 * The new pmap is resident. Make sure it's marked 4244 * as resident in the cache/TLB. 4245 */ 4246 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4247 if (npm != pmap_kernel()) 4248 pmap_recent_user = npm; 4249 4250 /* The old pmap is not longer active */ 4251 if (opm != NULL) 4252 opm->pm_activated = false; 4253 4254 /* But the new one is */ 4255 npm->pm_activated = true; 4256 } 4257 4258 void 4259 pmap_deactivate(struct lwp *l) 4260 { 4261 4262 /* 4263 * If the process is exiting, make sure pmap_activate() does 4264 * a full MMU context-switch and cache flush, which we might 4265 * otherwise skip. See PR port-arm/38950. 4266 */ 4267 if (l->l_proc->p_sflag & PS_WEXIT) 4268 pmap_previous_active_lwp = NULL; 4269 4270 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4271 } 4272 4273 void 4274 pmap_update(pmap_t pm) 4275 { 4276 4277 if (pm->pm_remove_all) { 4278 /* 4279 * Finish up the pmap_remove_all() optimisation by flushing 4280 * the TLB. 4281 */ 4282 pmap_tlb_flushID(pm); 4283 pm->pm_remove_all = false; 4284 } 4285 4286 if (pmap_is_current(pm)) { 4287 /* 4288 * If we're dealing with a current userland pmap, move its L1 4289 * to the end of the LRU. 4290 */ 4291 if (pm != pmap_kernel()) 4292 pmap_use_l1(pm); 4293 4294 /* 4295 * We can assume we're done with frobbing the cache/tlb for 4296 * now. Make sure any future pmap ops don't skip cache/tlb 4297 * flushes. 4298 */ 4299 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4300 } 4301 4302 PMAPCOUNT(updates); 4303 4304 /* 4305 * make sure TLB/cache operations have completed. 4306 */ 4307 cpu_cpwait(); 4308 } 4309 4310 void 4311 pmap_remove_all(pmap_t pm) 4312 { 4313 4314 /* 4315 * The vmspace described by this pmap is about to be torn down. 4316 * Until pmap_update() is called, UVM will only make calls 4317 * to pmap_remove(). We can make life much simpler by flushing 4318 * the cache now, and deferring TLB invalidation to pmap_update(). 4319 */ 4320 #ifdef PMAP_CACHE_VIVT 4321 pmap_idcache_wbinv_all(pm); 4322 #endif 4323 pm->pm_remove_all = true; 4324 } 4325 4326 /* 4327 * Retire the given physical map from service. 4328 * Should only be called if the map contains no valid mappings. 4329 */ 4330 void 4331 pmap_destroy(pmap_t pm) 4332 { 4333 u_int count; 4334 4335 if (pm == NULL) 4336 return; 4337 4338 if (pm->pm_remove_all) { 4339 pmap_tlb_flushID(pm); 4340 pm->pm_remove_all = false; 4341 } 4342 4343 /* 4344 * Drop reference count 4345 */ 4346 mutex_enter(pm->pm_lock); 4347 count = --pm->pm_obj.uo_refs; 4348 mutex_exit(pm->pm_lock); 4349 if (count > 0) { 4350 if (pmap_is_current(pm)) { 4351 if (pm != pmap_kernel()) 4352 pmap_use_l1(pm); 4353 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4354 } 4355 return; 4356 } 4357 4358 /* 4359 * reference count is zero, free pmap resources and then free pmap. 4360 */ 4361 4362 if (vector_page < KERNEL_BASE) { 4363 KDASSERT(!pmap_is_current(pm)); 4364 4365 /* Remove the vector page mapping */ 4366 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4367 pmap_update(pm); 4368 } 4369 4370 LIST_REMOVE(pm, pm_list); 4371 4372 pmap_free_l1(pm); 4373 4374 if (pmap_recent_user == pm) 4375 pmap_recent_user = NULL; 4376 4377 uvm_obj_destroy(&pm->pm_obj, false); 4378 mutex_destroy(&pm->pm_obj_lock); 4379 pool_cache_put(&pmap_cache, pm); 4380 } 4381 4382 4383 /* 4384 * void pmap_reference(pmap_t pm) 4385 * 4386 * Add a reference to the specified pmap. 4387 */ 4388 void 4389 pmap_reference(pmap_t pm) 4390 { 4391 4392 if (pm == NULL) 4393 return; 4394 4395 pmap_use_l1(pm); 4396 4397 mutex_enter(pm->pm_lock); 4398 pm->pm_obj.uo_refs++; 4399 mutex_exit(pm->pm_lock); 4400 } 4401 4402 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4403 4404 static struct evcnt pmap_prefer_nochange_ev = 4405 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4406 static struct evcnt pmap_prefer_change_ev = 4407 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4408 4409 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4410 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4411 4412 void 4413 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4414 { 4415 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4416 vaddr_t va = *vap; 4417 vaddr_t diff = (hint - va) & mask; 4418 if (diff == 0) { 4419 pmap_prefer_nochange_ev.ev_count++; 4420 } else { 4421 pmap_prefer_change_ev.ev_count++; 4422 if (__predict_false(td)) 4423 va -= mask + 1; 4424 *vap = va + diff; 4425 } 4426 } 4427 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4428 4429 /* 4430 * pmap_zero_page() 4431 * 4432 * Zero a given physical page by mapping it at a page hook point. 4433 * In doing the zero page op, the page we zero is mapped cachable, as with 4434 * StrongARM accesses to non-cached pages are non-burst making writing 4435 * _any_ bulk data very slow. 4436 */ 4437 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4438 void 4439 pmap_zero_page_generic(paddr_t phys) 4440 { 4441 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4442 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4443 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4444 #endif 4445 #ifdef PMAP_CACHE_VIPT 4446 /* Choose the last page color it had, if any */ 4447 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4448 #else 4449 const vsize_t va_offset = 0; 4450 #endif 4451 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4452 4453 #ifdef DEBUG 4454 if (!SLIST_EMPTY(&md->pvh_list)) 4455 panic("pmap_zero_page: page has mappings"); 4456 #endif 4457 4458 KDASSERT((phys & PGOFSET) == 0); 4459 4460 /* 4461 * Hook in the page, zero it, and purge the cache for that 4462 * zeroed page. Invalidate the TLB as needed. 4463 */ 4464 *ptep = L2_S_PROTO | phys | 4465 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4466 PTE_SYNC(ptep); 4467 cpu_tlb_flushD_SE(cdstp + va_offset); 4468 cpu_cpwait(); 4469 bzero_page(cdstp + va_offset); 4470 /* 4471 * Unmap the page. 4472 */ 4473 *ptep = 0; 4474 PTE_SYNC(ptep); 4475 cpu_tlb_flushD_SE(cdstp + va_offset); 4476 #ifdef PMAP_CACHE_VIVT 4477 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4478 #endif 4479 #ifdef PMAP_CACHE_VIPT 4480 /* 4481 * This page is now cache resident so it now has a page color. 4482 * Any contents have been obliterated so clear the EXEC flag. 4483 */ 4484 if (!pmap_is_page_colored_p(md)) { 4485 PMAPCOUNT(vac_color_new); 4486 md->pvh_attrs |= PVF_COLORED; 4487 } 4488 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4489 md->pvh_attrs &= ~PVF_EXEC; 4490 PMAPCOUNT(exec_discarded_zero); 4491 } 4492 md->pvh_attrs |= PVF_DIRTY; 4493 #endif 4494 } 4495 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4496 4497 #if ARM_MMU_XSCALE == 1 4498 void 4499 pmap_zero_page_xscale(paddr_t phys) 4500 { 4501 #ifdef DEBUG 4502 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4503 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4504 4505 if (!SLIST_EMPTY(&md->pvh_list)) 4506 panic("pmap_zero_page: page has mappings"); 4507 #endif 4508 4509 KDASSERT((phys & PGOFSET) == 0); 4510 4511 /* 4512 * Hook in the page, zero it, and purge the cache for that 4513 * zeroed page. Invalidate the TLB as needed. 4514 */ 4515 *cdst_pte = L2_S_PROTO | phys | 4516 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4517 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4518 PTE_SYNC(cdst_pte); 4519 cpu_tlb_flushD_SE(cdstp); 4520 cpu_cpwait(); 4521 bzero_page(cdstp); 4522 xscale_cache_clean_minidata(); 4523 } 4524 #endif /* ARM_MMU_XSCALE == 1 */ 4525 4526 /* pmap_pageidlezero() 4527 * 4528 * The same as above, except that we assume that the page is not 4529 * mapped. This means we never have to flush the cache first. Called 4530 * from the idle loop. 4531 */ 4532 bool 4533 pmap_pageidlezero(paddr_t phys) 4534 { 4535 unsigned int i; 4536 int *ptr; 4537 bool rv = true; 4538 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4539 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4540 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4541 #endif 4542 #ifdef PMAP_CACHE_VIPT 4543 /* Choose the last page color it had, if any */ 4544 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4545 #else 4546 const vsize_t va_offset = 0; 4547 #endif 4548 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4549 4550 4551 #ifdef DEBUG 4552 if (!SLIST_EMPTY(&md->pvh_list)) 4553 panic("pmap_pageidlezero: page has mappings"); 4554 #endif 4555 4556 KDASSERT((phys & PGOFSET) == 0); 4557 4558 /* 4559 * Hook in the page, zero it, and purge the cache for that 4560 * zeroed page. Invalidate the TLB as needed. 4561 */ 4562 *ptep = L2_S_PROTO | phys | 4563 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4564 PTE_SYNC(ptep); 4565 cpu_tlb_flushD_SE(cdstp + va_offset); 4566 cpu_cpwait(); 4567 4568 for (i = 0, ptr = (int *)(cdstp + va_offset); 4569 i < (PAGE_SIZE / sizeof(int)); i++) { 4570 if (sched_curcpu_runnable_p() != 0) { 4571 /* 4572 * A process has become ready. Abort now, 4573 * so we don't keep it waiting while we 4574 * do slow memory access to finish this 4575 * page. 4576 */ 4577 rv = false; 4578 break; 4579 } 4580 *ptr++ = 0; 4581 } 4582 4583 #ifdef PMAP_CACHE_VIVT 4584 if (rv) 4585 /* 4586 * if we aborted we'll rezero this page again later so don't 4587 * purge it unless we finished it 4588 */ 4589 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4590 #elif defined(PMAP_CACHE_VIPT) 4591 /* 4592 * This page is now cache resident so it now has a page color. 4593 * Any contents have been obliterated so clear the EXEC flag. 4594 */ 4595 if (!pmap_is_page_colored_p(md)) { 4596 PMAPCOUNT(vac_color_new); 4597 md->pvh_attrs |= PVF_COLORED; 4598 } 4599 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4600 md->pvh_attrs &= ~PVF_EXEC; 4601 PMAPCOUNT(exec_discarded_zero); 4602 } 4603 #endif 4604 /* 4605 * Unmap the page. 4606 */ 4607 *ptep = 0; 4608 PTE_SYNC(ptep); 4609 cpu_tlb_flushD_SE(cdstp + va_offset); 4610 4611 return (rv); 4612 } 4613 4614 /* 4615 * pmap_copy_page() 4616 * 4617 * Copy one physical page into another, by mapping the pages into 4618 * hook points. The same comment regarding cachability as in 4619 * pmap_zero_page also applies here. 4620 */ 4621 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4622 void 4623 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4624 { 4625 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4626 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4627 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4628 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4629 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4630 #endif 4631 #ifdef PMAP_CACHE_VIPT 4632 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4633 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4634 #else 4635 const vsize_t src_va_offset = 0; 4636 const vsize_t dst_va_offset = 0; 4637 #endif 4638 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4639 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4640 4641 #ifdef DEBUG 4642 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4643 panic("pmap_copy_page: dst page has mappings"); 4644 #endif 4645 4646 #ifdef PMAP_CACHE_VIPT 4647 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4648 #endif 4649 KDASSERT((src & PGOFSET) == 0); 4650 KDASSERT((dst & PGOFSET) == 0); 4651 4652 /* 4653 * Clean the source page. Hold the source page's lock for 4654 * the duration of the copy so that no other mappings can 4655 * be created while we have a potentially aliased mapping. 4656 */ 4657 #ifdef MULTIPROCESSOR 4658 KASSERT(uvm_page_locked_p(src_pg)); 4659 #endif 4660 #ifdef PMAP_CACHE_VIVT 4661 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4662 #endif 4663 4664 /* 4665 * Map the pages into the page hook points, copy them, and purge 4666 * the cache for the appropriate page. Invalidate the TLB 4667 * as required. 4668 */ 4669 *src_ptep = L2_S_PROTO 4670 | src 4671 #ifdef PMAP_CACHE_VIPT 4672 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4673 #endif 4674 #ifdef PMAP_CACHE_VIVT 4675 | pte_l2_s_cache_mode 4676 #endif 4677 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4678 *dst_ptep = L2_S_PROTO | dst | 4679 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4680 PTE_SYNC(src_ptep); 4681 PTE_SYNC(dst_ptep); 4682 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4683 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4684 cpu_cpwait(); 4685 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4686 #ifdef PMAP_CACHE_VIVT 4687 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4688 #endif 4689 #ifdef PMAP_CACHE_VIVT 4690 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4691 #endif 4692 /* 4693 * Unmap the pages. 4694 */ 4695 *src_ptep = 0; 4696 *dst_ptep = 0; 4697 PTE_SYNC(src_ptep); 4698 PTE_SYNC(dst_ptep); 4699 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4700 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4701 #ifdef PMAP_CACHE_VIPT 4702 /* 4703 * Now that the destination page is in the cache, mark it as colored. 4704 * If this was an exec page, discard it. 4705 */ 4706 if (!pmap_is_page_colored_p(dst_md)) { 4707 PMAPCOUNT(vac_color_new); 4708 dst_md->pvh_attrs |= PVF_COLORED; 4709 } 4710 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4711 dst_md->pvh_attrs &= ~PVF_EXEC; 4712 PMAPCOUNT(exec_discarded_copy); 4713 } 4714 dst_md->pvh_attrs |= PVF_DIRTY; 4715 #endif 4716 } 4717 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4718 4719 #if ARM_MMU_XSCALE == 1 4720 void 4721 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4722 { 4723 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4724 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4725 #ifdef DEBUG 4726 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4727 4728 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4729 panic("pmap_copy_page: dst page has mappings"); 4730 #endif 4731 4732 KDASSERT((src & PGOFSET) == 0); 4733 KDASSERT((dst & PGOFSET) == 0); 4734 4735 /* 4736 * Clean the source page. Hold the source page's lock for 4737 * the duration of the copy so that no other mappings can 4738 * be created while we have a potentially aliased mapping. 4739 */ 4740 #ifdef MULTIPROCESSOR 4741 KASSERT(uvm_page_locked_p(src_pg)); 4742 #endif 4743 #ifdef PMAP_CACHE_VIVT 4744 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4745 #endif 4746 4747 /* 4748 * Map the pages into the page hook points, copy them, and purge 4749 * the cache for the appropriate page. Invalidate the TLB 4750 * as required. 4751 */ 4752 *csrc_pte = L2_S_PROTO | src | 4753 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4754 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4755 PTE_SYNC(csrc_pte); 4756 *cdst_pte = L2_S_PROTO | dst | 4757 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4758 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4759 PTE_SYNC(cdst_pte); 4760 cpu_tlb_flushD_SE(csrcp); 4761 cpu_tlb_flushD_SE(cdstp); 4762 cpu_cpwait(); 4763 bcopy_page(csrcp, cdstp); 4764 xscale_cache_clean_minidata(); 4765 } 4766 #endif /* ARM_MMU_XSCALE == 1 */ 4767 4768 /* 4769 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4770 * 4771 * Return the start and end addresses of the kernel's virtual space. 4772 * These values are setup in pmap_bootstrap and are updated as pages 4773 * are allocated. 4774 */ 4775 void 4776 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4777 { 4778 *start = virtual_avail; 4779 *end = virtual_end; 4780 } 4781 4782 /* 4783 * Helper function for pmap_grow_l2_bucket() 4784 */ 4785 static inline int 4786 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4787 { 4788 struct l2_bucket *l2b; 4789 pt_entry_t *ptep; 4790 paddr_t pa; 4791 4792 if (uvm.page_init_done == false) { 4793 #ifdef PMAP_STEAL_MEMORY 4794 pv_addr_t pv; 4795 pmap_boot_pagealloc(PAGE_SIZE, 4796 #ifdef PMAP_CACHE_VIPT 4797 arm_cache_prefer_mask, 4798 va & arm_cache_prefer_mask, 4799 #else 4800 0, 0, 4801 #endif 4802 &pv); 4803 pa = pv.pv_pa; 4804 #else 4805 if (uvm_page_physget(&pa) == false) 4806 return (1); 4807 #endif /* PMAP_STEAL_MEMORY */ 4808 } else { 4809 struct vm_page *pg; 4810 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4811 if (pg == NULL) 4812 return (1); 4813 pa = VM_PAGE_TO_PHYS(pg); 4814 #ifdef PMAP_CACHE_VIPT 4815 #ifdef DIAGNOSTIC 4816 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4817 #endif 4818 /* 4819 * This new page must not have any mappings. Enter it via 4820 * pmap_kenter_pa and let that routine do the hard work. 4821 */ 4822 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4823 pmap_kenter_pa(va, pa, 4824 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4825 #endif 4826 } 4827 4828 if (pap) 4829 *pap = pa; 4830 4831 PMAPCOUNT(pt_mappings); 4832 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4833 KDASSERT(l2b != NULL); 4834 4835 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4836 *ptep = L2_S_PROTO | pa | cache_mode | 4837 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4838 PTE_SYNC(ptep); 4839 memset((void *)va, 0, PAGE_SIZE); 4840 return (0); 4841 } 4842 4843 /* 4844 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4845 * used by pmap_growkernel(). 4846 */ 4847 static inline struct l2_bucket * 4848 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4849 { 4850 struct l2_dtable *l2; 4851 struct l2_bucket *l2b; 4852 u_short l1idx; 4853 vaddr_t nva; 4854 4855 l1idx = L1_IDX(va); 4856 4857 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4858 /* 4859 * No mapping at this address, as there is 4860 * no entry in the L1 table. 4861 * Need to allocate a new l2_dtable. 4862 */ 4863 nva = pmap_kernel_l2dtable_kva; 4864 if ((nva & PGOFSET) == 0) { 4865 /* 4866 * Need to allocate a backing page 4867 */ 4868 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4869 return (NULL); 4870 } 4871 4872 l2 = (struct l2_dtable *)nva; 4873 nva += sizeof(struct l2_dtable); 4874 4875 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4876 /* 4877 * The new l2_dtable straddles a page boundary. 4878 * Map in another page to cover it. 4879 */ 4880 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4881 return (NULL); 4882 } 4883 4884 pmap_kernel_l2dtable_kva = nva; 4885 4886 /* 4887 * Link it into the parent pmap 4888 */ 4889 pm->pm_l2[L2_IDX(l1idx)] = l2; 4890 } 4891 4892 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4893 4894 /* 4895 * Fetch pointer to the L2 page table associated with the address. 4896 */ 4897 if (l2b->l2b_kva == NULL) { 4898 pt_entry_t *ptep; 4899 4900 /* 4901 * No L2 page table has been allocated. Chances are, this 4902 * is because we just allocated the l2_dtable, above. 4903 */ 4904 nva = pmap_kernel_l2ptp_kva; 4905 ptep = (pt_entry_t *)nva; 4906 if ((nva & PGOFSET) == 0) { 4907 /* 4908 * Need to allocate a backing page 4909 */ 4910 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4911 &pmap_kernel_l2ptp_phys)) 4912 return (NULL); 4913 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4914 } 4915 4916 l2->l2_occupancy++; 4917 l2b->l2b_kva = ptep; 4918 l2b->l2b_l1idx = l1idx; 4919 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4920 4921 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4922 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4923 } 4924 4925 return (l2b); 4926 } 4927 4928 vaddr_t 4929 pmap_growkernel(vaddr_t maxkvaddr) 4930 { 4931 pmap_t kpm = pmap_kernel(); 4932 struct l1_ttable *l1; 4933 struct l2_bucket *l2b; 4934 pd_entry_t *pl1pd; 4935 int s; 4936 4937 if (maxkvaddr <= pmap_curmaxkvaddr) 4938 goto out; /* we are OK */ 4939 4940 NPDEBUG(PDB_GROWKERN, 4941 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4942 pmap_curmaxkvaddr, maxkvaddr)); 4943 4944 KDASSERT(maxkvaddr <= virtual_end); 4945 4946 /* 4947 * whoops! we need to add kernel PTPs 4948 */ 4949 4950 s = splhigh(); /* to be safe */ 4951 mutex_enter(kpm->pm_lock); 4952 4953 /* Map 1MB at a time */ 4954 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4955 4956 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4957 KDASSERT(l2b != NULL); 4958 4959 /* Distribute new L1 entry to all other L1s */ 4960 SLIST_FOREACH(l1, &l1_list, l1_link) { 4961 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4962 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4963 L1_C_PROTO; 4964 PTE_SYNC(pl1pd); 4965 } 4966 } 4967 4968 /* 4969 * flush out the cache, expensive but growkernel will happen so 4970 * rarely 4971 */ 4972 cpu_dcache_wbinv_all(); 4973 cpu_tlb_flushD(); 4974 cpu_cpwait(); 4975 4976 mutex_exit(kpm->pm_lock); 4977 splx(s); 4978 4979 out: 4980 return (pmap_curmaxkvaddr); 4981 } 4982 4983 /************************ Utility routines ****************************/ 4984 4985 /* 4986 * vector_page_setprot: 4987 * 4988 * Manipulate the protection of the vector page. 4989 */ 4990 void 4991 vector_page_setprot(int prot) 4992 { 4993 struct l2_bucket *l2b; 4994 pt_entry_t *ptep; 4995 4996 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4997 KDASSERT(l2b != NULL); 4998 4999 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5000 5001 *ptep = (*ptep & ~L2_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 5002 PTE_SYNC(ptep); 5003 cpu_tlb_flushD_SE(vector_page); 5004 cpu_cpwait(); 5005 } 5006 5007 /* 5008 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5009 * Returns true if the mapping exists, else false. 5010 * 5011 * NOTE: This function is only used by a couple of arm-specific modules. 5012 * It is not safe to take any pmap locks here, since we could be right 5013 * in the middle of debugging the pmap anyway... 5014 * 5015 * It is possible for this routine to return false even though a valid 5016 * mapping does exist. This is because we don't lock, so the metadata 5017 * state may be inconsistent. 5018 * 5019 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5020 * a "section" mapping. 5021 */ 5022 bool 5023 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5024 { 5025 struct l2_dtable *l2; 5026 pd_entry_t *pl1pd, l1pd; 5027 pt_entry_t *ptep; 5028 u_short l1idx; 5029 5030 if (pm->pm_l1 == NULL) 5031 return false; 5032 5033 l1idx = L1_IDX(va); 5034 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5035 l1pd = *pl1pd; 5036 5037 if (l1pte_section_p(l1pd)) { 5038 *ptp = NULL; 5039 return true; 5040 } 5041 5042 if (pm->pm_l2 == NULL) 5043 return false; 5044 5045 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5046 5047 if (l2 == NULL || 5048 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5049 return false; 5050 } 5051 5052 *ptp = &ptep[l2pte_index(va)]; 5053 return true; 5054 } 5055 5056 bool 5057 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5058 { 5059 u_short l1idx; 5060 5061 if (pm->pm_l1 == NULL) 5062 return false; 5063 5064 l1idx = L1_IDX(va); 5065 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5066 5067 return true; 5068 } 5069 5070 /************************ Bootstrapping routines ****************************/ 5071 5072 static void 5073 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5074 { 5075 int i; 5076 5077 l1->l1_kva = l1pt; 5078 l1->l1_domain_use_count = 0; 5079 l1->l1_domain_first = 0; 5080 5081 for (i = 0; i < PMAP_DOMAINS; i++) 5082 l1->l1_domain_free[i] = i + 1; 5083 5084 /* 5085 * Copy the kernel's L1 entries to each new L1. 5086 */ 5087 if (pmap_initialized) 5088 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5089 5090 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5091 &l1->l1_physaddr) == false) 5092 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5093 5094 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5095 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5096 } 5097 5098 /* 5099 * pmap_bootstrap() is called from the board-specific initarm() routine 5100 * once the kernel L1/L2 descriptors tables have been set up. 5101 * 5102 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5103 * spread over a number of disparate files/functions. 5104 * 5105 * We are passed the following parameters 5106 * - kernel_l1pt 5107 * This is a pointer to the base of the kernel's L1 translation table. 5108 * - vstart 5109 * 1MB-aligned start of managed kernel virtual memory. 5110 * - vend 5111 * 1MB-aligned end of managed kernel virtual memory. 5112 * 5113 * We use the first parameter to build the metadata (struct l1_ttable and 5114 * struct l2_dtable) necessary to track kernel mappings. 5115 */ 5116 #define PMAP_STATIC_L2_SIZE 16 5117 void 5118 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5119 { 5120 static struct l1_ttable static_l1; 5121 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5122 struct l1_ttable *l1 = &static_l1; 5123 struct l2_dtable *l2; 5124 struct l2_bucket *l2b; 5125 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5126 pmap_t pm = pmap_kernel(); 5127 pd_entry_t pde; 5128 pt_entry_t *ptep; 5129 paddr_t pa; 5130 vaddr_t va; 5131 vsize_t size; 5132 int nptes, l1idx, l2idx, l2next = 0; 5133 5134 /* 5135 * Initialise the kernel pmap object 5136 */ 5137 pm->pm_l1 = l1; 5138 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5139 pm->pm_activated = true; 5140 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5141 5142 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5143 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5144 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5145 5146 /* 5147 * Scan the L1 translation table created by initarm() and create 5148 * the required metadata for all valid mappings found in it. 5149 */ 5150 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5151 pde = l1pt[l1idx]; 5152 5153 /* 5154 * We're only interested in Coarse mappings. 5155 * pmap_extract() can deal with section mappings without 5156 * recourse to checking L2 metadata. 5157 */ 5158 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5159 continue; 5160 5161 /* 5162 * Lookup the KVA of this L2 descriptor table 5163 */ 5164 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5165 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5166 if (ptep == NULL) { 5167 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5168 (u_int)l1idx << L1_S_SHIFT, pa); 5169 } 5170 5171 /* 5172 * Fetch the associated L2 metadata structure. 5173 * Allocate a new one if necessary. 5174 */ 5175 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5176 if (l2next == PMAP_STATIC_L2_SIZE) 5177 panic("pmap_bootstrap: out of static L2s"); 5178 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5179 } 5180 5181 /* 5182 * One more L1 slot tracked... 5183 */ 5184 l2->l2_occupancy++; 5185 5186 /* 5187 * Fill in the details of the L2 descriptor in the 5188 * appropriate bucket. 5189 */ 5190 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5191 l2b->l2b_kva = ptep; 5192 l2b->l2b_phys = pa; 5193 l2b->l2b_l1idx = l1idx; 5194 5195 /* 5196 * Establish an initial occupancy count for this descriptor 5197 */ 5198 for (l2idx = 0; 5199 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5200 l2idx++) { 5201 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5202 l2b->l2b_occupancy++; 5203 } 5204 } 5205 5206 /* 5207 * Make sure the descriptor itself has the correct cache mode. 5208 * If not, fix it, but whine about the problem. Port-meisters 5209 * should consider this a clue to fix up their initarm() 5210 * function. :) 5211 */ 5212 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5213 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5214 "L2 pte @ %p\n", ptep); 5215 } 5216 } 5217 5218 /* 5219 * Ensure the primary (kernel) L1 has the correct cache mode for 5220 * a page table. Bitch if it is not correctly set. 5221 */ 5222 for (va = (vaddr_t)l1pt; 5223 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5224 if (pmap_set_pt_cache_mode(l1pt, va)) 5225 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5226 "primary L1 @ 0x%lx\n", va); 5227 } 5228 5229 cpu_dcache_wbinv_all(); 5230 cpu_tlb_flushID(); 5231 cpu_cpwait(); 5232 5233 /* 5234 * now we allocate the "special" VAs which are used for tmp mappings 5235 * by the pmap (and other modules). we allocate the VAs by advancing 5236 * virtual_avail (note that there are no pages mapped at these VAs). 5237 * 5238 * Managed KVM space start from wherever initarm() tells us. 5239 */ 5240 virtual_avail = vstart; 5241 virtual_end = vend; 5242 5243 #ifdef PMAP_CACHE_VIPT 5244 /* 5245 * If we have a VIPT cache, we need one page/pte per possible alias 5246 * page so we won't violate cache aliasing rules. 5247 */ 5248 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5249 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5250 #else 5251 nptes = 1; 5252 #endif 5253 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5254 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5255 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5256 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5257 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5258 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5259 (void *)&msgbufaddr, NULL); 5260 5261 /* 5262 * Allocate a range of kernel virtual address space to be used 5263 * for L2 descriptor tables and metadata allocation in 5264 * pmap_growkernel(). 5265 */ 5266 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5267 pmap_alloc_specials(&virtual_avail, 5268 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5269 &pmap_kernel_l2ptp_kva, NULL); 5270 5271 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5272 pmap_alloc_specials(&virtual_avail, 5273 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5274 &pmap_kernel_l2dtable_kva, NULL); 5275 5276 /* 5277 * init the static-global locks and global pmap list. 5278 */ 5279 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 5280 5281 /* 5282 * We can now initialise the first L1's metadata. 5283 */ 5284 SLIST_INIT(&l1_list); 5285 TAILQ_INIT(&l1_lru_list); 5286 pmap_init_l1(l1, l1pt); 5287 5288 /* Set up vector page L1 details, if necessary */ 5289 if (vector_page < KERNEL_BASE) { 5290 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5291 l2b = pmap_get_l2_bucket(pm, vector_page); 5292 KDASSERT(l2b != NULL); 5293 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5294 L1_C_DOM(pm->pm_domain); 5295 } else 5296 pm->pm_pl1vec = NULL; 5297 5298 /* 5299 * Initialize the pmap cache 5300 */ 5301 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5302 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5303 LIST_INIT(&pmap_pmaps); 5304 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5305 5306 /* 5307 * Initialize the pv pool. 5308 */ 5309 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5310 &pmap_bootstrap_pv_allocator, IPL_NONE); 5311 5312 /* 5313 * Initialize the L2 dtable pool and cache. 5314 */ 5315 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5316 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5317 5318 /* 5319 * Initialise the L2 descriptor table pool and cache 5320 */ 5321 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5322 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5323 pmap_l2ptp_ctor, NULL, NULL); 5324 5325 cpu_dcache_wbinv_all(); 5326 } 5327 5328 static int 5329 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5330 { 5331 pd_entry_t *pdep, pde; 5332 pt_entry_t *ptep, pte; 5333 vaddr_t pa; 5334 int rv = 0; 5335 5336 /* 5337 * Make sure the descriptor itself has the correct cache mode 5338 */ 5339 pdep = &kl1[L1_IDX(va)]; 5340 pde = *pdep; 5341 5342 if (l1pte_section_p(pde)) { 5343 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 5344 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5345 *pdep = (pde & ~L1_S_CACHE_MASK) | 5346 pte_l1_s_cache_mode_pt; 5347 PTE_SYNC(pdep); 5348 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5349 rv = 1; 5350 } 5351 } else { 5352 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5353 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5354 if (ptep == NULL) 5355 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5356 5357 ptep = &ptep[l2pte_index(va)]; 5358 pte = *ptep; 5359 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5360 *ptep = (pte & ~L2_S_CACHE_MASK) | 5361 pte_l2_s_cache_mode_pt; 5362 PTE_SYNC(ptep); 5363 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5364 rv = 1; 5365 } 5366 } 5367 5368 return (rv); 5369 } 5370 5371 static void 5372 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5373 { 5374 vaddr_t va = *availp; 5375 struct l2_bucket *l2b; 5376 5377 if (ptep) { 5378 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5379 if (l2b == NULL) 5380 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5381 5382 if (ptep) 5383 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5384 } 5385 5386 *vap = va; 5387 *availp = va + (PAGE_SIZE * pages); 5388 } 5389 5390 void 5391 pmap_init(void) 5392 { 5393 5394 /* 5395 * Set the available memory vars - These do not map to real memory 5396 * addresses and cannot as the physical memory is fragmented. 5397 * They are used by ps for %mem calculations. 5398 * One could argue whether this should be the entire memory or just 5399 * the memory that is useable in a user process. 5400 */ 5401 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5402 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5403 5404 /* 5405 * Now we need to free enough pv_entry structures to allow us to get 5406 * the kmem_map/kmem_object allocated and inited (done after this 5407 * function is finished). to do this we allocate one bootstrap page out 5408 * of kernel_map and use it to provide an initial pool of pv_entry 5409 * structures. we never free this page. 5410 */ 5411 pool_setlowat(&pmap_pv_pool, 5412 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5413 5414 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5415 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5416 UVM_KMF_WIRED|UVM_KMF_ZERO); 5417 5418 pmap_initialized = true; 5419 } 5420 5421 static vaddr_t last_bootstrap_page = 0; 5422 static void *free_bootstrap_pages = NULL; 5423 5424 static void * 5425 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5426 { 5427 extern void *pool_page_alloc(struct pool *, int); 5428 vaddr_t new_page; 5429 void *rv; 5430 5431 if (pmap_initialized) 5432 return (pool_page_alloc(pp, flags)); 5433 5434 if (free_bootstrap_pages) { 5435 rv = free_bootstrap_pages; 5436 free_bootstrap_pages = *((void **)rv); 5437 return (rv); 5438 } 5439 5440 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5441 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5442 5443 KASSERT(new_page > last_bootstrap_page); 5444 last_bootstrap_page = new_page; 5445 return ((void *)new_page); 5446 } 5447 5448 static void 5449 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5450 { 5451 extern void pool_page_free(struct pool *, void *); 5452 5453 if ((vaddr_t)v <= last_bootstrap_page) { 5454 *((void **)v) = free_bootstrap_pages; 5455 free_bootstrap_pages = v; 5456 return; 5457 } 5458 5459 if (pmap_initialized) { 5460 pool_page_free(pp, v); 5461 return; 5462 } 5463 } 5464 5465 /* 5466 * pmap_postinit() 5467 * 5468 * This routine is called after the vm and kmem subsystems have been 5469 * initialised. This allows the pmap code to perform any initialisation 5470 * that can only be done one the memory allocation is in place. 5471 */ 5472 void 5473 pmap_postinit(void) 5474 { 5475 extern paddr_t physical_start, physical_end; 5476 struct l2_bucket *l2b; 5477 struct l1_ttable *l1; 5478 struct pglist plist; 5479 struct vm_page *m; 5480 pd_entry_t *pl1pt; 5481 pt_entry_t *ptep, pte; 5482 vaddr_t va, eva; 5483 u_int loop, needed; 5484 int error; 5485 5486 pool_cache_setlowat(&pmap_l2ptp_cache, 5487 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5488 pool_cache_setlowat(&pmap_l2dtable_cache, 5489 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5490 5491 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5492 needed -= 1; 5493 5494 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 5495 5496 for (loop = 0; loop < needed; loop++, l1++) { 5497 /* Allocate a L1 page table */ 5498 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5499 if (va == 0) 5500 panic("Cannot allocate L1 KVM"); 5501 5502 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5503 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 5504 if (error) 5505 panic("Cannot allocate L1 physical pages"); 5506 5507 m = TAILQ_FIRST(&plist); 5508 eva = va + L1_TABLE_SIZE; 5509 pl1pt = (pd_entry_t *)va; 5510 5511 while (m && va < eva) { 5512 paddr_t pa = VM_PAGE_TO_PHYS(m); 5513 5514 pmap_kenter_pa(va, pa, 5515 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5516 5517 /* 5518 * Make sure the L1 descriptor table is mapped 5519 * with the cache-mode set to write-through. 5520 */ 5521 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5522 KDASSERT(l2b != NULL); 5523 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5524 pte = *ptep; 5525 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5526 *ptep = pte; 5527 PTE_SYNC(ptep); 5528 cpu_tlb_flushD_SE(va); 5529 5530 va += PAGE_SIZE; 5531 m = TAILQ_NEXT(m, pageq.queue); 5532 } 5533 5534 #ifdef DIAGNOSTIC 5535 if (m) 5536 panic("pmap_alloc_l1pt: pglist not empty"); 5537 #endif /* DIAGNOSTIC */ 5538 5539 pmap_init_l1(l1, pl1pt); 5540 } 5541 5542 #ifdef DEBUG 5543 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5544 needed); 5545 #endif 5546 } 5547 5548 /* 5549 * Note that the following routines are used by board-specific initialisation 5550 * code to configure the initial kernel page tables. 5551 * 5552 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5553 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5554 * behaviour of the old pmap, and provides an easy migration path for 5555 * initial bring-up of the new pmap on existing ports. Fortunately, 5556 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5557 * will be deprecated. 5558 * 5559 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5560 * tables. 5561 */ 5562 5563 /* 5564 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5565 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5566 * find them as necessary. 5567 * 5568 * Note that the data on this list MUST remain valid after initarm() returns, 5569 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5570 */ 5571 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5572 5573 static vaddr_t 5574 kernel_pt_lookup(paddr_t pa) 5575 { 5576 pv_addr_t *pv; 5577 5578 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5579 #ifndef ARM32_NEW_VM_LAYOUT 5580 if (pv->pv_pa == (pa & ~PGOFSET)) 5581 return (pv->pv_va | (pa & PGOFSET)); 5582 #else 5583 if (pv->pv_pa == pa) 5584 return (pv->pv_va); 5585 #endif 5586 } 5587 return (0); 5588 } 5589 5590 /* 5591 * pmap_map_section: 5592 * 5593 * Create a single section mapping. 5594 */ 5595 void 5596 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5597 { 5598 pd_entry_t *pde = (pd_entry_t *) l1pt; 5599 pd_entry_t fl; 5600 5601 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5602 5603 switch (cache) { 5604 case PTE_NOCACHE: 5605 default: 5606 fl = 0; 5607 break; 5608 5609 case PTE_CACHE: 5610 fl = pte_l1_s_cache_mode; 5611 break; 5612 5613 case PTE_PAGETABLE: 5614 fl = pte_l1_s_cache_mode_pt; 5615 break; 5616 } 5617 5618 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5619 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5620 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5621 } 5622 5623 /* 5624 * pmap_map_entry: 5625 * 5626 * Create a single page mapping. 5627 */ 5628 void 5629 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5630 { 5631 pd_entry_t *pde = (pd_entry_t *) l1pt; 5632 pt_entry_t fl; 5633 pt_entry_t *pte; 5634 5635 KASSERT(((va | pa) & PGOFSET) == 0); 5636 5637 switch (cache) { 5638 case PTE_NOCACHE: 5639 default: 5640 fl = 0; 5641 break; 5642 5643 case PTE_CACHE: 5644 fl = pte_l2_s_cache_mode; 5645 break; 5646 5647 case PTE_PAGETABLE: 5648 fl = pte_l2_s_cache_mode_pt; 5649 break; 5650 } 5651 5652 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5653 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5654 5655 #ifndef ARM32_NEW_VM_LAYOUT 5656 pte = (pt_entry_t *) 5657 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5658 #else 5659 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5660 #endif 5661 if (pte == NULL) 5662 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5663 5664 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5665 #ifndef ARM32_NEW_VM_LAYOUT 5666 pte += (va >> PGSHIFT) & 0x3ff; 5667 #else 5668 pte += l2pte_index(va); 5669 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5670 #endif 5671 *pte = fl; 5672 PTE_SYNC(pte); 5673 } 5674 5675 /* 5676 * pmap_link_l2pt: 5677 * 5678 * Link the L2 page table specified by "l2pv" into the L1 5679 * page table at the slot for "va". 5680 */ 5681 void 5682 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5683 { 5684 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5685 u_int slot = va >> L1_S_SHIFT; 5686 5687 #ifndef ARM32_NEW_VM_LAYOUT 5688 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5689 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5690 #endif 5691 5692 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5693 5694 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5695 #ifdef ARM32_NEW_VM_LAYOUT 5696 PTE_SYNC(&pde[slot]); 5697 #else 5698 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5699 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5700 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5701 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5702 #endif 5703 5704 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5705 } 5706 5707 /* 5708 * pmap_map_chunk: 5709 * 5710 * Map a chunk of memory using the most efficient mappings 5711 * possible (section, large page, small page) into the 5712 * provided L1 and L2 tables at the specified virtual address. 5713 */ 5714 vsize_t 5715 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5716 int prot, int cache) 5717 { 5718 pd_entry_t *pdep = (pd_entry_t *) l1pt; 5719 pt_entry_t *pte, f1, f2s, f2l; 5720 vsize_t resid; 5721 int i; 5722 5723 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5724 5725 if (l1pt == 0) 5726 panic("pmap_map_chunk: no L1 table provided"); 5727 5728 #ifdef VERBOSE_INIT_ARM 5729 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5730 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5731 #endif 5732 5733 switch (cache) { 5734 case PTE_NOCACHE: 5735 default: 5736 f1 = 0; 5737 f2l = 0; 5738 f2s = 0; 5739 break; 5740 5741 case PTE_CACHE: 5742 f1 = pte_l1_s_cache_mode; 5743 f2l = pte_l2_l_cache_mode; 5744 f2s = pte_l2_s_cache_mode; 5745 break; 5746 5747 case PTE_PAGETABLE: 5748 f1 = pte_l1_s_cache_mode_pt; 5749 f2l = pte_l2_l_cache_mode_pt; 5750 f2s = pte_l2_s_cache_mode_pt; 5751 break; 5752 } 5753 5754 size = resid; 5755 5756 while (resid > 0) { 5757 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5758 /* See if we can use a supersection mapping. */ 5759 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 5760 /* Supersection are always domain 0 */ 5761 pd_entry_t pde = L1_SS_PROTO | pa | 5762 L1_S_PROT(PTE_KERNEL, prot) | f1; 5763 #ifdef VERBOSE_INIT_ARM 5764 printf("sS"); 5765 #endif 5766 for (size_t s = va >> L1_S_SHIFT, 5767 e = s + L1_SS_SIZE / L1_S_SIZE; 5768 s < e; 5769 s++) { 5770 pdep[s] = pde; 5771 PTE_SYNC(&pdep[s]); 5772 } 5773 va += L1_SS_SIZE; 5774 pa += L1_SS_SIZE; 5775 resid -= L1_SS_SIZE; 5776 continue; 5777 } 5778 #endif 5779 /* See if we can use a section mapping. */ 5780 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5781 #ifdef VERBOSE_INIT_ARM 5782 printf("S"); 5783 #endif 5784 pdep[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5785 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5786 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5787 PTE_SYNC(&pdep[va >> L1_S_SHIFT]); 5788 va += L1_S_SIZE; 5789 pa += L1_S_SIZE; 5790 resid -= L1_S_SIZE; 5791 continue; 5792 } 5793 5794 /* 5795 * Ok, we're going to use an L2 table. Make sure 5796 * one is actually in the corresponding L1 slot 5797 * for the current VA. 5798 */ 5799 if ((pdep[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5800 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5801 5802 #ifndef ARM32_NEW_VM_LAYOUT 5803 pte = (pt_entry_t *) 5804 kernel_pt_lookup(pdep[va >> L1_S_SHIFT] & L2_S_FRAME); 5805 #else 5806 pte = (pt_entry_t *) kernel_pt_lookup( 5807 pdep[L1_IDX(va)] & L1_C_ADDR_MASK); 5808 #endif 5809 if (pte == NULL) 5810 panic("pmap_map_chunk: can't find L2 table for VA" 5811 "0x%08lx", va); 5812 5813 /* See if we can use a L2 large page mapping. */ 5814 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5815 #ifdef VERBOSE_INIT_ARM 5816 printf("L"); 5817 #endif 5818 for (i = 0; i < 16; i++) { 5819 #ifndef ARM32_NEW_VM_LAYOUT 5820 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5821 L2_L_PROTO | pa | 5822 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5823 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5824 #else 5825 pte[l2pte_index(va) + i] = 5826 L2_L_PROTO | pa | 5827 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5828 PTE_SYNC(&pte[l2pte_index(va) + i]); 5829 #endif 5830 } 5831 va += L2_L_SIZE; 5832 pa += L2_L_SIZE; 5833 resid -= L2_L_SIZE; 5834 continue; 5835 } 5836 5837 /* Use a small page mapping. */ 5838 #ifdef VERBOSE_INIT_ARM 5839 printf("P"); 5840 #endif 5841 #ifndef ARM32_NEW_VM_LAYOUT 5842 pte[(va >> PGSHIFT) & 0x3ff] = 5843 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5844 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5845 #else 5846 pte[l2pte_index(va)] = 5847 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5848 PTE_SYNC(&pte[l2pte_index(va)]); 5849 #endif 5850 va += PAGE_SIZE; 5851 pa += PAGE_SIZE; 5852 resid -= PAGE_SIZE; 5853 } 5854 #ifdef VERBOSE_INIT_ARM 5855 printf("\n"); 5856 #endif 5857 return (size); 5858 } 5859 5860 /********************** Static device map routines ***************************/ 5861 5862 static const struct pmap_devmap *pmap_devmap_table; 5863 5864 /* 5865 * Register the devmap table. This is provided in case early console 5866 * initialization needs to register mappings created by bootstrap code 5867 * before pmap_devmap_bootstrap() is called. 5868 */ 5869 void 5870 pmap_devmap_register(const struct pmap_devmap *table) 5871 { 5872 5873 pmap_devmap_table = table; 5874 } 5875 5876 /* 5877 * Map all of the static regions in the devmap table, and remember 5878 * the devmap table so other parts of the kernel can look up entries 5879 * later. 5880 */ 5881 void 5882 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5883 { 5884 int i; 5885 5886 pmap_devmap_table = table; 5887 5888 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5889 #ifdef VERBOSE_INIT_ARM 5890 printf("devmap: %08lx -> %08lx @ %08lx\n", 5891 pmap_devmap_table[i].pd_pa, 5892 pmap_devmap_table[i].pd_pa + 5893 pmap_devmap_table[i].pd_size - 1, 5894 pmap_devmap_table[i].pd_va); 5895 #endif 5896 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5897 pmap_devmap_table[i].pd_pa, 5898 pmap_devmap_table[i].pd_size, 5899 pmap_devmap_table[i].pd_prot, 5900 pmap_devmap_table[i].pd_cache); 5901 } 5902 } 5903 5904 const struct pmap_devmap * 5905 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5906 { 5907 uint64_t endpa; 5908 int i; 5909 5910 if (pmap_devmap_table == NULL) 5911 return (NULL); 5912 5913 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5914 5915 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5916 if (pa >= pmap_devmap_table[i].pd_pa && 5917 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5918 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5919 return (&pmap_devmap_table[i]); 5920 } 5921 5922 return (NULL); 5923 } 5924 5925 const struct pmap_devmap * 5926 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5927 { 5928 int i; 5929 5930 if (pmap_devmap_table == NULL) 5931 return (NULL); 5932 5933 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5934 if (va >= pmap_devmap_table[i].pd_va && 5935 va + size - 1 <= pmap_devmap_table[i].pd_va + 5936 pmap_devmap_table[i].pd_size - 1) 5937 return (&pmap_devmap_table[i]); 5938 } 5939 5940 return (NULL); 5941 } 5942 5943 /********************** PTE initialization routines **************************/ 5944 5945 /* 5946 * These routines are called when the CPU type is identified to set up 5947 * the PTE prototypes, cache modes, etc. 5948 * 5949 * The variables are always here, just in case modules need to reference 5950 * them (though, they shouldn't). 5951 */ 5952 5953 pt_entry_t pte_l1_s_cache_mode; 5954 pt_entry_t pte_l1_s_wc_mode; 5955 pt_entry_t pte_l1_s_cache_mode_pt; 5956 pt_entry_t pte_l1_s_cache_mask; 5957 5958 pt_entry_t pte_l2_l_cache_mode; 5959 pt_entry_t pte_l2_l_wc_mode; 5960 pt_entry_t pte_l2_l_cache_mode_pt; 5961 pt_entry_t pte_l2_l_cache_mask; 5962 5963 pt_entry_t pte_l2_s_cache_mode; 5964 pt_entry_t pte_l2_s_wc_mode; 5965 pt_entry_t pte_l2_s_cache_mode_pt; 5966 pt_entry_t pte_l2_s_cache_mask; 5967 5968 pt_entry_t pte_l1_s_prot_u; 5969 pt_entry_t pte_l1_s_prot_w; 5970 pt_entry_t pte_l1_s_prot_ro; 5971 pt_entry_t pte_l1_s_prot_mask; 5972 5973 pt_entry_t pte_l2_s_prot_u; 5974 pt_entry_t pte_l2_s_prot_w; 5975 pt_entry_t pte_l2_s_prot_ro; 5976 pt_entry_t pte_l2_s_prot_mask; 5977 5978 pt_entry_t pte_l2_l_prot_u; 5979 pt_entry_t pte_l2_l_prot_w; 5980 pt_entry_t pte_l2_l_prot_ro; 5981 pt_entry_t pte_l2_l_prot_mask; 5982 5983 pt_entry_t pte_l1_ss_proto; 5984 pt_entry_t pte_l1_s_proto; 5985 pt_entry_t pte_l1_c_proto; 5986 pt_entry_t pte_l2_s_proto; 5987 5988 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5989 void (*pmap_zero_page_func)(paddr_t); 5990 5991 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5992 void 5993 pmap_pte_init_generic(void) 5994 { 5995 5996 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5997 pte_l1_s_wc_mode = L1_S_B; 5998 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5999 6000 pte_l2_l_cache_mode = L2_B|L2_C; 6001 pte_l2_l_wc_mode = L2_B; 6002 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6003 6004 pte_l2_s_cache_mode = L2_B|L2_C; 6005 pte_l2_s_wc_mode = L2_B; 6006 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6007 6008 /* 6009 * If we have a write-through cache, set B and C. If 6010 * we have a write-back cache, then we assume setting 6011 * only C will make those pages write-through (except for those 6012 * Cortex CPUs which can read the L1 caches). 6013 */ 6014 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6015 #if ARM_MMU_V7 > 0 6016 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6017 #endif 6018 #if ARM_MMU_V6 > 0 6019 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6020 #endif 6021 || false) { 6022 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6023 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6024 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6025 } else { 6026 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6027 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6028 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6029 } 6030 6031 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6032 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6033 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6034 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6035 6036 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6037 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6038 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6039 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6040 6041 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6042 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6043 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6044 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6045 6046 pte_l1_ss_proto = L1_SS_PROTO_generic; 6047 pte_l1_s_proto = L1_S_PROTO_generic; 6048 pte_l1_c_proto = L1_C_PROTO_generic; 6049 pte_l2_s_proto = L2_S_PROTO_generic; 6050 6051 pmap_copy_page_func = pmap_copy_page_generic; 6052 pmap_zero_page_func = pmap_zero_page_generic; 6053 } 6054 6055 #if defined(CPU_ARM8) 6056 void 6057 pmap_pte_init_arm8(void) 6058 { 6059 6060 /* 6061 * ARM8 is compatible with generic, but we need to use 6062 * the page tables uncached. 6063 */ 6064 pmap_pte_init_generic(); 6065 6066 pte_l1_s_cache_mode_pt = 0; 6067 pte_l2_l_cache_mode_pt = 0; 6068 pte_l2_s_cache_mode_pt = 0; 6069 } 6070 #endif /* CPU_ARM8 */ 6071 6072 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6073 void 6074 pmap_pte_init_arm9(void) 6075 { 6076 6077 /* 6078 * ARM9 is compatible with generic, but we want to use 6079 * write-through caching for now. 6080 */ 6081 pmap_pte_init_generic(); 6082 6083 pte_l1_s_cache_mode = L1_S_C; 6084 pte_l2_l_cache_mode = L2_C; 6085 pte_l2_s_cache_mode = L2_C; 6086 6087 pte_l1_s_wc_mode = L1_S_B; 6088 pte_l2_l_wc_mode = L2_B; 6089 pte_l2_s_wc_mode = L2_B; 6090 6091 pte_l1_s_cache_mode_pt = L1_S_C; 6092 pte_l2_l_cache_mode_pt = L2_C; 6093 pte_l2_s_cache_mode_pt = L2_C; 6094 } 6095 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6096 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6097 6098 #if defined(CPU_ARM10) 6099 void 6100 pmap_pte_init_arm10(void) 6101 { 6102 6103 /* 6104 * ARM10 is compatible with generic, but we want to use 6105 * write-through caching for now. 6106 */ 6107 pmap_pte_init_generic(); 6108 6109 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6110 pte_l2_l_cache_mode = L2_B | L2_C; 6111 pte_l2_s_cache_mode = L2_B | L2_C; 6112 6113 pte_l1_s_cache_mode = L1_S_B; 6114 pte_l2_l_cache_mode = L2_B; 6115 pte_l2_s_cache_mode = L2_B; 6116 6117 pte_l1_s_cache_mode_pt = L1_S_C; 6118 pte_l2_l_cache_mode_pt = L2_C; 6119 pte_l2_s_cache_mode_pt = L2_C; 6120 6121 } 6122 #endif /* CPU_ARM10 */ 6123 6124 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6125 void 6126 pmap_pte_init_arm11(void) 6127 { 6128 6129 /* 6130 * ARM11 is compatible with generic, but we want to use 6131 * write-through caching for now. 6132 */ 6133 pmap_pte_init_generic(); 6134 6135 pte_l1_s_cache_mode = L1_S_C; 6136 pte_l2_l_cache_mode = L2_C; 6137 pte_l2_s_cache_mode = L2_C; 6138 6139 pte_l1_s_wc_mode = L1_S_B; 6140 pte_l2_l_wc_mode = L2_B; 6141 pte_l2_s_wc_mode = L2_B; 6142 6143 pte_l1_s_cache_mode_pt = L1_S_C; 6144 pte_l2_l_cache_mode_pt = L2_C; 6145 pte_l2_s_cache_mode_pt = L2_C; 6146 } 6147 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6148 6149 #if ARM_MMU_SA1 == 1 6150 void 6151 pmap_pte_init_sa1(void) 6152 { 6153 6154 /* 6155 * The StrongARM SA-1 cache does not have a write-through 6156 * mode. So, do the generic initialization, then reset 6157 * the page table cache mode to B=1,C=1, and note that 6158 * the PTEs need to be sync'd. 6159 */ 6160 pmap_pte_init_generic(); 6161 6162 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6163 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6164 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6165 6166 pmap_needs_pte_sync = 1; 6167 } 6168 #endif /* ARM_MMU_SA1 == 1*/ 6169 6170 #if ARM_MMU_XSCALE == 1 6171 #if (ARM_NMMUS > 1) 6172 static u_int xscale_use_minidata; 6173 #endif 6174 6175 void 6176 pmap_pte_init_xscale(void) 6177 { 6178 uint32_t auxctl; 6179 int write_through = 0; 6180 6181 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6182 pte_l1_s_wc_mode = L1_S_B; 6183 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6184 6185 pte_l2_l_cache_mode = L2_B|L2_C; 6186 pte_l2_l_wc_mode = L2_B; 6187 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6188 6189 pte_l2_s_cache_mode = L2_B|L2_C; 6190 pte_l2_s_wc_mode = L2_B; 6191 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6192 6193 pte_l1_s_cache_mode_pt = L1_S_C; 6194 pte_l2_l_cache_mode_pt = L2_C; 6195 pte_l2_s_cache_mode_pt = L2_C; 6196 6197 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6198 /* 6199 * The XScale core has an enhanced mode where writes that 6200 * miss the cache cause a cache line to be allocated. This 6201 * is significantly faster than the traditional, write-through 6202 * behavior of this case. 6203 */ 6204 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6205 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6206 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6207 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6208 6209 #ifdef XSCALE_CACHE_WRITE_THROUGH 6210 /* 6211 * Some versions of the XScale core have various bugs in 6212 * their cache units, the work-around for which is to run 6213 * the cache in write-through mode. Unfortunately, this 6214 * has a major (negative) impact on performance. So, we 6215 * go ahead and run fast-and-loose, in the hopes that we 6216 * don't line up the planets in a way that will trip the 6217 * bugs. 6218 * 6219 * However, we give you the option to be slow-but-correct. 6220 */ 6221 write_through = 1; 6222 #elif defined(XSCALE_CACHE_WRITE_BACK) 6223 /* force write back cache mode */ 6224 write_through = 0; 6225 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6226 /* 6227 * Intel PXA2[15]0 processors are known to have a bug in 6228 * write-back cache on revision 4 and earlier (stepping 6229 * A[01] and B[012]). Fixed for C0 and later. 6230 */ 6231 { 6232 uint32_t id, type; 6233 6234 id = cpufunc_id(); 6235 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6236 6237 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6238 if ((id & CPU_ID_REVISION_MASK) < 5) { 6239 /* write through for stepping A0-1 and B0-2 */ 6240 write_through = 1; 6241 } 6242 } 6243 } 6244 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6245 6246 if (write_through) { 6247 pte_l1_s_cache_mode = L1_S_C; 6248 pte_l2_l_cache_mode = L2_C; 6249 pte_l2_s_cache_mode = L2_C; 6250 } 6251 6252 #if (ARM_NMMUS > 1) 6253 xscale_use_minidata = 1; 6254 #endif 6255 6256 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6257 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6258 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6259 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6260 6261 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6262 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6263 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6264 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6265 6266 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6267 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6268 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6269 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6270 6271 pte_l1_ss_proto = L1_SS_PROTO_xscale; 6272 pte_l1_s_proto = L1_S_PROTO_xscale; 6273 pte_l1_c_proto = L1_C_PROTO_xscale; 6274 pte_l2_s_proto = L2_S_PROTO_xscale; 6275 6276 pmap_copy_page_func = pmap_copy_page_xscale; 6277 pmap_zero_page_func = pmap_zero_page_xscale; 6278 6279 /* 6280 * Disable ECC protection of page table access, for now. 6281 */ 6282 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6283 auxctl &= ~XSCALE_AUXCTL_P; 6284 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6285 } 6286 6287 /* 6288 * xscale_setup_minidata: 6289 * 6290 * Set up the mini-data cache clean area. We require the 6291 * caller to allocate the right amount of physically and 6292 * virtually contiguous space. 6293 */ 6294 void 6295 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6296 { 6297 extern vaddr_t xscale_minidata_clean_addr; 6298 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6299 pd_entry_t *pde = (pd_entry_t *) l1pt; 6300 pt_entry_t *pte; 6301 vsize_t size; 6302 uint32_t auxctl; 6303 6304 xscale_minidata_clean_addr = va; 6305 6306 /* Round it to page size. */ 6307 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6308 6309 for (; size != 0; 6310 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6311 #ifndef ARM32_NEW_VM_LAYOUT 6312 pte = (pt_entry_t *) 6313 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6314 #else 6315 pte = (pt_entry_t *) kernel_pt_lookup( 6316 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6317 #endif 6318 if (pte == NULL) 6319 panic("xscale_setup_minidata: can't find L2 table for " 6320 "VA 0x%08lx", va); 6321 #ifndef ARM32_NEW_VM_LAYOUT 6322 pte[(va >> PGSHIFT) & 0x3ff] = 6323 #else 6324 pte[l2pte_index(va)] = 6325 #endif 6326 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6327 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6328 } 6329 6330 /* 6331 * Configure the mini-data cache for write-back with 6332 * read/write-allocate. 6333 * 6334 * NOTE: In order to reconfigure the mini-data cache, we must 6335 * make sure it contains no valid data! In order to do that, 6336 * we must issue a global data cache invalidate command! 6337 * 6338 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6339 * THIS IS VERY IMPORTANT! 6340 */ 6341 6342 /* Invalidate data and mini-data. */ 6343 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6344 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6345 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6346 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6347 } 6348 6349 /* 6350 * Change the PTEs for the specified kernel mappings such that they 6351 * will use the mini data cache instead of the main data cache. 6352 */ 6353 void 6354 pmap_uarea(vaddr_t va) 6355 { 6356 struct l2_bucket *l2b; 6357 pt_entry_t *ptep, *sptep, pte; 6358 vaddr_t next_bucket, eva; 6359 6360 #if (ARM_NMMUS > 1) 6361 if (xscale_use_minidata == 0) 6362 return; 6363 #endif 6364 6365 eva = va + USPACE; 6366 6367 while (va < eva) { 6368 next_bucket = L2_NEXT_BUCKET(va); 6369 if (next_bucket > eva) 6370 next_bucket = eva; 6371 6372 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6373 KDASSERT(l2b != NULL); 6374 6375 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6376 6377 while (va < next_bucket) { 6378 pte = *ptep; 6379 if (!l2pte_minidata(pte)) { 6380 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6381 cpu_tlb_flushD_SE(va); 6382 *ptep = pte & ~L2_B; 6383 } 6384 ptep++; 6385 va += PAGE_SIZE; 6386 } 6387 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6388 } 6389 cpu_cpwait(); 6390 } 6391 #endif /* ARM_MMU_XSCALE == 1 */ 6392 6393 6394 #if defined(CPU_ARM11MPCORE) 6395 6396 void 6397 pmap_pte_init_arm11mpcore(void) 6398 { 6399 6400 /* cache mode is controlled by 5 bits (B, C, TEX) */ 6401 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 6402 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 6403 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6404 /* use extended small page (without APn, with TEX) */ 6405 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 6406 #else 6407 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 6408 #endif 6409 6410 /* write-back, write-allocate */ 6411 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6412 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 6413 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6414 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6415 #else 6416 /* no TEX. read-allocate */ 6417 pte_l2_s_cache_mode = L2_C | L2_B; 6418 #endif 6419 /* 6420 * write-back, write-allocate for page tables. 6421 */ 6422 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6423 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 6424 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6425 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6426 #else 6427 pte_l2_s_cache_mode_pt = L2_C | L2_B; 6428 #endif 6429 6430 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 6431 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 6432 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 6433 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 6434 6435 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6436 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 6437 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 6438 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 6439 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 6440 6441 #else 6442 /* with AP[0..3] */ 6443 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6444 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6445 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6446 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6447 #endif 6448 6449 #ifdef ARM11MPCORE_COMPAT_MMU 6450 /* with AP[0..3] */ 6451 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6452 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6453 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6454 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6455 6456 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6457 pte_l1_s_proto = L1_S_PROTO_armv6; 6458 pte_l1_c_proto = L1_C_PROTO_armv6; 6459 pte_l2_s_proto = L2_S_PROTO_armv6c; 6460 #else 6461 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 6462 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 6463 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 6464 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 6465 6466 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6467 pte_l1_s_proto = L1_S_PROTO_armv6; 6468 pte_l1_c_proto = L1_C_PROTO_armv6; 6469 pte_l2_s_proto = L2_S_PROTO_armv6n; 6470 #endif 6471 6472 pmap_copy_page_func = pmap_copy_page_generic; 6473 pmap_zero_page_func = pmap_zero_page_generic; 6474 pmap_needs_pte_sync = 1; 6475 } 6476 #endif /* CPU_ARM11MPCORE */ 6477 6478 6479 #if ARM_MMU_V7 == 1 6480 void 6481 pmap_pte_init_armv7(void) 6482 { 6483 /* 6484 * The ARMv7-A MMU is mostly compatible with generic. If the 6485 * AP field is zero, that now means "no access" rather than 6486 * read-only. The prototypes are a little different because of 6487 * the XN bit. 6488 */ 6489 pmap_pte_init_generic(); 6490 6491 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6492 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6493 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6494 6495 if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) { 6496 /* 6497 * write-back, no write-allocate, shareable for normal pages. 6498 */ 6499 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_S; 6500 pte_l2_l_cache_mode = L2_C | L2_B | L2_XS_S; 6501 pte_l2_s_cache_mode = L2_C | L2_B | L2_XS_S; 6502 6503 /* 6504 * write-back, no write-allocate, shareable for page tables. 6505 */ 6506 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_S; 6507 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6508 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6509 } 6510 6511 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6512 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6513 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6514 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6515 6516 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6517 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6518 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6519 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6520 6521 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6522 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6523 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6524 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6525 6526 pte_l1_ss_proto = L1_SS_PROTO_armv7; 6527 pte_l1_s_proto = L1_S_PROTO_armv7; 6528 pte_l1_c_proto = L1_C_PROTO_armv7; 6529 pte_l2_s_proto = L2_S_PROTO_armv7; 6530 6531 pmap_needs_pte_sync = 1; 6532 } 6533 #endif /* ARM_MMU_V7 */ 6534 6535 /* 6536 * return the PA of the current L1 table, for use when handling a crash dump 6537 */ 6538 uint32_t pmap_kernel_L1_addr(void) 6539 { 6540 return pmap_kernel()->pm_l1->l1_physaddr; 6541 } 6542 6543 #if defined(DDB) 6544 /* 6545 * A couple of ddb-callable functions for dumping pmaps 6546 */ 6547 void pmap_dump_all(void); 6548 void pmap_dump(pmap_t); 6549 6550 void 6551 pmap_dump_all(void) 6552 { 6553 pmap_t pm; 6554 6555 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6556 if (pm == pmap_kernel()) 6557 continue; 6558 pmap_dump(pm); 6559 printf("\n"); 6560 } 6561 } 6562 6563 static pt_entry_t ncptes[64]; 6564 static void pmap_dump_ncpg(pmap_t); 6565 6566 void 6567 pmap_dump(pmap_t pm) 6568 { 6569 struct l2_dtable *l2; 6570 struct l2_bucket *l2b; 6571 pt_entry_t *ptep, pte; 6572 vaddr_t l2_va, l2b_va, va; 6573 int i, j, k, occ, rows = 0; 6574 6575 if (pm == pmap_kernel()) 6576 printf("pmap_kernel (%p): ", pm); 6577 else 6578 printf("user pmap (%p): ", pm); 6579 6580 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6581 6582 l2_va = 0; 6583 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6584 l2 = pm->pm_l2[i]; 6585 6586 if (l2 == NULL || l2->l2_occupancy == 0) 6587 continue; 6588 6589 l2b_va = l2_va; 6590 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6591 l2b = &l2->l2_bucket[j]; 6592 6593 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6594 continue; 6595 6596 ptep = l2b->l2b_kva; 6597 6598 for (k = 0; k < 256 && ptep[k] == 0; k++) 6599 ; 6600 6601 k &= ~63; 6602 occ = l2b->l2b_occupancy; 6603 va = l2b_va + (k * 4096); 6604 for (; k < 256; k++, va += 0x1000) { 6605 char ch = ' '; 6606 if ((k % 64) == 0) { 6607 if ((rows % 8) == 0) { 6608 printf( 6609 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6610 } 6611 printf("%08lx: ", va); 6612 } 6613 6614 ncptes[k & 63] = 0; 6615 pte = ptep[k]; 6616 if (pte == 0) { 6617 ch = '.'; 6618 } else { 6619 occ--; 6620 switch (pte & 0x0c) { 6621 case 0x00: 6622 ch = 'D'; /* No cache No buff */ 6623 break; 6624 case 0x04: 6625 ch = 'B'; /* No cache buff */ 6626 break; 6627 case 0x08: 6628 if (pte & 0x40) 6629 ch = 'm'; 6630 else 6631 ch = 'C'; /* Cache No buff */ 6632 break; 6633 case 0x0c: 6634 ch = 'F'; /* Cache Buff */ 6635 break; 6636 } 6637 6638 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6639 ch += 0x20; 6640 6641 if ((pte & 0xc) == 0) 6642 ncptes[k & 63] = pte; 6643 } 6644 6645 if ((k % 64) == 63) { 6646 rows++; 6647 printf("%c\n", ch); 6648 pmap_dump_ncpg(pm); 6649 if (occ == 0) 6650 break; 6651 } else 6652 printf("%c", ch); 6653 } 6654 } 6655 } 6656 } 6657 6658 static void 6659 pmap_dump_ncpg(pmap_t pm) 6660 { 6661 struct vm_page *pg; 6662 struct vm_page_md *md; 6663 struct pv_entry *pv; 6664 int i; 6665 6666 for (i = 0; i < 63; i++) { 6667 if (ncptes[i] == 0) 6668 continue; 6669 6670 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6671 if (pg == NULL) 6672 continue; 6673 md = VM_PAGE_TO_MD(pg); 6674 6675 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6676 VM_PAGE_TO_PHYS(pg), 6677 md->krw_mappings, md->kro_mappings, 6678 md->urw_mappings, md->uro_mappings); 6679 6680 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6681 printf(" %c va 0x%08lx, flags 0x%x\n", 6682 (pm == pv->pv_pmap) ? '*' : ' ', 6683 pv->pv_va, pv->pv_flags); 6684 } 6685 } 6686 } 6687 #endif 6688 6689 #ifdef PMAP_STEAL_MEMORY 6690 void 6691 pmap_boot_pageadd(pv_addr_t *newpv) 6692 { 6693 pv_addr_t *pv, *npv; 6694 6695 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6696 if (newpv->pv_pa < pv->pv_va) { 6697 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6698 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6699 newpv->pv_size += pv->pv_size; 6700 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6701 } 6702 pv = NULL; 6703 } else { 6704 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6705 pv = npv) { 6706 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6707 KASSERT(pv->pv_pa < newpv->pv_pa); 6708 if (newpv->pv_pa > npv->pv_pa) 6709 continue; 6710 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6711 pv->pv_size += newpv->pv_size; 6712 return; 6713 } 6714 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6715 break; 6716 newpv->pv_size += npv->pv_size; 6717 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6718 SLIST_REMOVE_AFTER(newpv, pv_list); 6719 return; 6720 } 6721 } 6722 } 6723 6724 if (pv) { 6725 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6726 } else { 6727 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6728 } 6729 } 6730 6731 void 6732 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6733 pv_addr_t *rpv) 6734 { 6735 pv_addr_t *pv, **pvp; 6736 struct vm_physseg *ps; 6737 size_t i; 6738 6739 KASSERT(amount & PGOFSET); 6740 KASSERT((mask & PGOFSET) == 0); 6741 KASSERT((match & PGOFSET) == 0); 6742 KASSERT(amount != 0); 6743 6744 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6745 (pv = *pvp) != NULL; 6746 pvp = &SLIST_NEXT(pv, pv_list)) { 6747 pv_addr_t *newpv; 6748 psize_t off; 6749 /* 6750 * If this entry is too small to satify the request... 6751 */ 6752 KASSERT(pv->pv_size > 0); 6753 if (pv->pv_size < amount) 6754 continue; 6755 6756 for (off = 0; off <= mask; off += PAGE_SIZE) { 6757 if (((pv->pv_pa + off) & mask) == match 6758 && off + amount <= pv->pv_size) 6759 break; 6760 } 6761 if (off > mask) 6762 continue; 6763 6764 rpv->pv_va = pv->pv_va + off; 6765 rpv->pv_pa = pv->pv_pa + off; 6766 rpv->pv_size = amount; 6767 pv->pv_size -= amount; 6768 if (pv->pv_size == 0) { 6769 KASSERT(off == 0); 6770 KASSERT((vaddr_t) pv == rpv->pv_va); 6771 *pvp = SLIST_NEXT(pv, pv_list); 6772 } else if (off == 0) { 6773 KASSERT((vaddr_t) pv == rpv->pv_va); 6774 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6775 *newpv = *pv; 6776 newpv->pv_pa += amount; 6777 newpv->pv_va += amount; 6778 *pvp = newpv; 6779 } else if (off < pv->pv_size) { 6780 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6781 *newpv = *pv; 6782 newpv->pv_size -= off; 6783 newpv->pv_pa += off + amount; 6784 newpv->pv_va += off + amount; 6785 6786 SLIST_NEXT(pv, pv_list) = newpv; 6787 pv->pv_size = off; 6788 } else { 6789 KASSERT((vaddr_t) pv != rpv->pv_va); 6790 } 6791 memset((void *)rpv->pv_va, 0, amount); 6792 return; 6793 } 6794 6795 if (vm_nphysseg == 0) 6796 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6797 6798 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6799 (pv = *pvp) != NULL; 6800 pvp = &SLIST_NEXT(pv, pv_list)) { 6801 if (SLIST_NEXT(pv, pv_list) == NULL) 6802 break; 6803 } 6804 KASSERT(mask == 0); 6805 for (i = 0; i < vm_nphysseg; i++) { 6806 ps = VM_PHYSMEM_PTR(i); 6807 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6808 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6809 rpv->pv_va = pv->pv_va; 6810 rpv->pv_pa = pv->pv_pa; 6811 rpv->pv_size = amount; 6812 *pvp = NULL; 6813 pmap_map_chunk(kernel_l1pt.pv_va, 6814 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6815 ptoa(ps->avail_start), 6816 amount - pv->pv_size, 6817 VM_PROT_READ|VM_PROT_WRITE, 6818 PTE_CACHE); 6819 ps->avail_start += atop(amount - pv->pv_size); 6820 /* 6821 * If we consumed the entire physseg, remove it. 6822 */ 6823 if (ps->avail_start == ps->avail_end) { 6824 for (--vm_nphysseg; i < vm_nphysseg; i++) 6825 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6826 } 6827 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6828 return; 6829 } 6830 } 6831 6832 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6833 } 6834 6835 vaddr_t 6836 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6837 { 6838 pv_addr_t pv; 6839 6840 pmap_boot_pagealloc(size, 0, 0, &pv); 6841 6842 return pv.pv_va; 6843 } 6844 #endif /* PMAP_STEAL_MEMORY */ 6845 6846 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6847 { 6848 sysctl_createv(clog, 0, NULL, NULL, 6849 CTLFLAG_PERMANENT, 6850 CTLTYPE_NODE, "machdep", NULL, 6851 NULL, 0, NULL, 0, 6852 CTL_MACHDEP, CTL_EOL); 6853 6854 sysctl_createv(clog, 0, NULL, NULL, 6855 CTLFLAG_PERMANENT, 6856 CTLTYPE_INT, "kmpages", 6857 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6858 NULL, 0, &pmap_kmpages, 0, 6859 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6860 } 6861 6862 #ifdef PMAP_NEED_ALLOC_POOLPAGE 6863 struct vm_page * 6864 arm_pmap_alloc_poolpage(int flags) 6865 { 6866 /* 6867 * On some systems, only some pages may be "coherent" for dma and we 6868 * want to use those for pool pages (think mbufs). 6869 */ 6870 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) 6871 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 6872 UVM_PGA_STRAT_ONLY, arm_poolpage_vmfreelist); 6873 6874 return uvm_pagealloc(NULL, 0, NULL, flags); 6875 } 6876 #endif 6877
Indexes created Mon Sep 29 18:09:42 GMT 2025