pmap.c revision 1.244
1 /* $NetBSD: pmap.c,v 1.244 2012/12/11 01:16:10 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/pool.h> 201 #include <sys/kmem.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <sys/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/cpuconf.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.244 2012/12/11 01:16:10 matt Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 #define PDB_EXEC 0x80000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 static struct pmap kernel_pmap_store; 259 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 260 #ifdef PMAP_NEED_ALLOC_POOLPAGE 261 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 262 #endif 263 264 /* 265 * Which pmap is currently 'live' in the cache 266 * 267 * XXXSCW: Fix for SMP ... 268 */ 269 static pmap_t pmap_recent_user; 270 271 /* 272 * Pointer to last active lwp, or NULL if it exited. 273 */ 274 struct lwp *pmap_previous_active_lwp; 275 276 /* 277 * Pool and cache that pmap structures are allocated from. 278 * We use a cache to avoid clearing the pm_l2[] array (1KB) 279 * in pmap_create(). 280 */ 281 static struct pool_cache pmap_cache; 282 static LIST_HEAD(, pmap) pmap_pmaps; 283 284 /* 285 * Pool of PV structures 286 */ 287 static struct pool pmap_pv_pool; 288 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 289 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 290 static struct pool_allocator pmap_bootstrap_pv_allocator = { 291 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 292 }; 293 294 /* 295 * Pool and cache of l2_dtable structures. 296 * We use a cache to avoid clearing the structures when they're 297 * allocated. (196 bytes) 298 */ 299 static struct pool_cache pmap_l2dtable_cache; 300 static vaddr_t pmap_kernel_l2dtable_kva; 301 302 /* 303 * Pool and cache of L2 page descriptors. 304 * We use a cache to avoid clearing the descriptor table 305 * when they're allocated. (1KB) 306 */ 307 static struct pool_cache pmap_l2ptp_cache; 308 static vaddr_t pmap_kernel_l2ptp_kva; 309 static paddr_t pmap_kernel_l2ptp_phys; 310 311 #ifdef PMAPCOUNTERS 312 #define PMAP_EVCNT_INITIALIZER(name) \ 313 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 314 315 #ifdef PMAP_CACHE_VIPT 316 static struct evcnt pmap_ev_vac_clean_one = 317 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_one = 319 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_lots = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 322 static struct evcnt pmap_ev_vac_flush_lots2 = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 328 329 static struct evcnt pmap_ev_vac_color_new = 330 PMAP_EVCNT_INITIALIZER("new page color"); 331 static struct evcnt pmap_ev_vac_color_reuse = 332 PMAP_EVCNT_INITIALIZER("ok first page color"); 333 static struct evcnt pmap_ev_vac_color_ok = 334 PMAP_EVCNT_INITIALIZER("ok page color"); 335 static struct evcnt pmap_ev_vac_color_blind = 336 PMAP_EVCNT_INITIALIZER("blind page color"); 337 static struct evcnt pmap_ev_vac_color_change = 338 PMAP_EVCNT_INITIALIZER("change page color"); 339 static struct evcnt pmap_ev_vac_color_erase = 340 PMAP_EVCNT_INITIALIZER("erase page color"); 341 static struct evcnt pmap_ev_vac_color_none = 342 PMAP_EVCNT_INITIALIZER("no page color"); 343 static struct evcnt pmap_ev_vac_color_restore = 344 PMAP_EVCNT_INITIALIZER("restore page color"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 354 #endif 355 356 static struct evcnt pmap_ev_mappings = 357 PMAP_EVCNT_INITIALIZER("pages mapped"); 358 static struct evcnt pmap_ev_unmappings = 359 PMAP_EVCNT_INITIALIZER("pages unmapped"); 360 static struct evcnt pmap_ev_remappings = 361 PMAP_EVCNT_INITIALIZER("pages remapped"); 362 363 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 364 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 366 367 static struct evcnt pmap_ev_kernel_mappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 369 static struct evcnt pmap_ev_kernel_unmappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 371 static struct evcnt pmap_ev_kernel_remappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 373 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 377 378 static struct evcnt pmap_ev_kenter_mappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 380 static struct evcnt pmap_ev_kenter_unmappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 382 static struct evcnt pmap_ev_kenter_remappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 384 static struct evcnt pmap_ev_pt_mappings = 385 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 391 392 #ifdef PMAP_CACHE_VIPT 393 static struct evcnt pmap_ev_exec_mappings = 394 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 395 static struct evcnt pmap_ev_exec_cached = 396 PMAP_EVCNT_INITIALIZER("exec pages cached"); 397 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 399 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 400 401 static struct evcnt pmap_ev_exec_synced = 402 PMAP_EVCNT_INITIALIZER("exec pages synced"); 403 static struct evcnt pmap_ev_exec_synced_map = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 405 static struct evcnt pmap_ev_exec_synced_unmap = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 407 static struct evcnt pmap_ev_exec_synced_remap = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 409 static struct evcnt pmap_ev_exec_synced_clearbit = 410 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 411 static struct evcnt pmap_ev_exec_synced_kremove = 412 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 413 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 420 421 static struct evcnt pmap_ev_exec_discarded_unmap = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 423 static struct evcnt pmap_ev_exec_discarded_zero = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 425 static struct evcnt pmap_ev_exec_discarded_copy = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 427 static struct evcnt pmap_ev_exec_discarded_page_protect = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 429 static struct evcnt pmap_ev_exec_discarded_clearbit = 430 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 431 static struct evcnt pmap_ev_exec_discarded_kremove = 432 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 433 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 440 #endif /* PMAP_CACHE_VIPT */ 441 442 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 443 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 444 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 445 446 EVCNT_ATTACH_STATIC(pmap_ev_updates); 447 EVCNT_ATTACH_STATIC(pmap_ev_collects); 448 EVCNT_ATTACH_STATIC(pmap_ev_activations); 449 450 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 451 #else 452 #define PMAPCOUNT(x) ((void)0) 453 #endif 454 455 /* 456 * pmap copy/zero page, and mem(5) hook point 457 */ 458 static pt_entry_t *csrc_pte, *cdst_pte; 459 static vaddr_t csrcp, cdstp; 460 vaddr_t memhook; /* used by mem.c */ 461 kmutex_t memlock; /* used by mem.c */ 462 void *zeropage; /* used by mem.c */ 463 extern void *msgbufaddr; 464 int pmap_kmpages; 465 /* 466 * Flag to indicate if pmap_init() has done its thing 467 */ 468 bool pmap_initialized; 469 470 /* 471 * Misc. locking data structures 472 */ 473 474 #define pmap_acquire_pmap_lock(pm) \ 475 do { \ 476 if ((pm) != pmap_kernel()) \ 477 mutex_enter((pm)->pm_lock); \ 478 } while (/*CONSTCOND*/0) 479 480 #define pmap_release_pmap_lock(pm) \ 481 do { \ 482 if ((pm) != pmap_kernel()) \ 483 mutex_exit((pm)->pm_lock); \ 484 } while (/*CONSTCOND*/0) 485 486 487 /* 488 * Metadata for L1 translation tables. 489 */ 490 struct l1_ttable { 491 /* Entry on the L1 Table list */ 492 SLIST_ENTRY(l1_ttable) l1_link; 493 494 /* Entry on the L1 Least Recently Used list */ 495 TAILQ_ENTRY(l1_ttable) l1_lru; 496 497 /* Track how many domains are allocated from this L1 */ 498 volatile u_int l1_domain_use_count; 499 500 /* 501 * A free-list of domain numbers for this L1. 502 * We avoid using ffs() and a bitmap to track domains since ffs() 503 * is slow on ARM. 504 */ 505 uint8_t l1_domain_first; 506 uint8_t l1_domain_free[PMAP_DOMAINS]; 507 508 /* Physical address of this L1 page table */ 509 paddr_t l1_physaddr; 510 511 /* KVA of this L1 page table */ 512 pd_entry_t *l1_kva; 513 }; 514 515 /* 516 * Convert a virtual address into its L1 table index. That is, the 517 * index used to locate the L2 descriptor table pointer in an L1 table. 518 * This is basically used to index l1->l1_kva[]. 519 * 520 * Each L2 descriptor table represents 1MB of VA space. 521 */ 522 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 523 524 /* 525 * L1 Page Tables are tracked using a Least Recently Used list. 526 * - New L1s are allocated from the HEAD. 527 * - Freed L1s are added to the TAIl. 528 * - Recently accessed L1s (where an 'access' is some change to one of 529 * the userland pmaps which owns this L1) are moved to the TAIL. 530 */ 531 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 532 static kmutex_t l1_lru_lock __cacheline_aligned; 533 534 /* 535 * A list of all L1 tables 536 */ 537 static SLIST_HEAD(, l1_ttable) l1_list; 538 539 /* 540 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 541 * 542 * This is normally 16MB worth L2 page descriptors for any given pmap. 543 * Reference counts are maintained for L2 descriptors so they can be 544 * freed when empty. 545 */ 546 struct l2_dtable { 547 /* The number of L2 page descriptors allocated to this l2_dtable */ 548 u_int l2_occupancy; 549 550 /* List of L2 page descriptors */ 551 struct l2_bucket { 552 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 553 paddr_t l2b_phys; /* Physical address of same */ 554 u_short l2b_l1idx; /* This L2 table's L1 index */ 555 u_short l2b_occupancy; /* How many active descriptors */ 556 } l2_bucket[L2_BUCKET_SIZE]; 557 }; 558 559 /* 560 * Given an L1 table index, calculate the corresponding l2_dtable index 561 * and bucket index within the l2_dtable. 562 */ 563 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 564 (L2_SIZE - 1)) 565 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 566 567 /* 568 * Given a virtual address, this macro returns the 569 * virtual address required to drop into the next L2 bucket. 570 */ 571 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 572 573 /* 574 * L2 allocation. 575 */ 576 #define pmap_alloc_l2_dtable() \ 577 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 578 #define pmap_free_l2_dtable(l2) \ 579 pool_cache_put(&pmap_l2dtable_cache, (l2)) 580 #define pmap_alloc_l2_ptp(pap) \ 581 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 582 PR_NOWAIT, (pap))) 583 584 /* 585 * We try to map the page tables write-through, if possible. However, not 586 * all CPUs have a write-through cache mode, so on those we have to sync 587 * the cache when we frob page tables. 588 * 589 * We try to evaluate this at compile time, if possible. However, it's 590 * not always possible to do that, hence this run-time var. 591 */ 592 int pmap_needs_pte_sync; 593 594 /* 595 * Real definition of pv_entry. 596 */ 597 struct pv_entry { 598 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 599 pmap_t pv_pmap; /* pmap where mapping lies */ 600 vaddr_t pv_va; /* virtual address for mapping */ 601 u_int pv_flags; /* flags */ 602 }; 603 604 /* 605 * Macro to determine if a mapping might be resident in the 606 * instruction cache and/or TLB 607 */ 608 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 609 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 610 611 /* 612 * Macro to determine if a mapping might be resident in the 613 * data cache and/or TLB 614 */ 615 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 616 617 /* 618 * Local prototypes 619 */ 620 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 621 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 622 pt_entry_t **); 623 static bool pmap_is_current(pmap_t); 624 static bool pmap_is_cached(pmap_t); 625 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 626 pmap_t, vaddr_t, u_int); 627 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 628 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 629 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 630 u_int, u_int); 631 632 static void pmap_pinit(pmap_t); 633 static int pmap_pmap_ctor(void *, void *, int); 634 635 static void pmap_alloc_l1(pmap_t); 636 static void pmap_free_l1(pmap_t); 637 static void pmap_use_l1(pmap_t); 638 639 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 640 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 641 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 642 static int pmap_l2ptp_ctor(void *, void *, int); 643 static int pmap_l2dtable_ctor(void *, void *, int); 644 645 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 646 #ifdef PMAP_CACHE_VIVT 647 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 648 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 649 #endif 650 651 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 652 #ifdef PMAP_CACHE_VIVT 653 static int pmap_clean_page(struct pv_entry *, bool); 654 #endif 655 #ifdef PMAP_CACHE_VIPT 656 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 657 enum pmap_flush_op { 658 PMAP_FLUSH_PRIMARY, 659 PMAP_FLUSH_SECONDARY, 660 PMAP_CLEAN_PRIMARY 661 }; 662 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 663 #endif 664 static void pmap_page_remove(struct vm_page_md *, paddr_t); 665 666 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 667 static vaddr_t kernel_pt_lookup(paddr_t); 668 669 670 /* 671 * Misc variables 672 */ 673 vaddr_t virtual_avail; 674 vaddr_t virtual_end; 675 vaddr_t pmap_curmaxkvaddr; 676 677 paddr_t avail_start; 678 paddr_t avail_end; 679 680 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 681 pv_addr_t kernelpages; 682 pv_addr_t kernel_l1pt; 683 pv_addr_t systempage; 684 685 /* Function to set the debug level of the pmap code */ 686 687 #ifdef PMAP_DEBUG 688 void 689 pmap_debug(int level) 690 { 691 pmap_debug_level = level; 692 printf("pmap_debug: level=%d\n", pmap_debug_level); 693 } 694 #endif /* PMAP_DEBUG */ 695 696 /* 697 * A bunch of routines to conditionally flush the caches/TLB depending 698 * on whether the specified pmap actually needs to be flushed at any 699 * given time. 700 */ 701 static inline void 702 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 703 { 704 705 if (pm->pm_cstate.cs_tlb_id) 706 cpu_tlb_flushID_SE(va); 707 } 708 709 static inline void 710 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 711 { 712 713 if (pm->pm_cstate.cs_tlb_d) 714 cpu_tlb_flushD_SE(va); 715 } 716 717 static inline void 718 pmap_tlb_flushID(pmap_t pm) 719 { 720 721 if (pm->pm_cstate.cs_tlb_id) { 722 cpu_tlb_flushID(); 723 pm->pm_cstate.cs_tlb = 0; 724 } 725 } 726 727 static inline void 728 pmap_tlb_flushD(pmap_t pm) 729 { 730 731 if (pm->pm_cstate.cs_tlb_d) { 732 cpu_tlb_flushD(); 733 pm->pm_cstate.cs_tlb_d = 0; 734 } 735 } 736 737 #ifdef PMAP_CACHE_VIVT 738 static inline void 739 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 740 { 741 if (pm->pm_cstate.cs_cache_id) { 742 cpu_idcache_wbinv_range(va, len); 743 } 744 } 745 746 static inline void 747 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 748 bool do_inv, bool rd_only) 749 { 750 751 if (pm->pm_cstate.cs_cache_d) { 752 if (do_inv) { 753 if (rd_only) 754 cpu_dcache_inv_range(va, len); 755 else 756 cpu_dcache_wbinv_range(va, len); 757 } else 758 if (!rd_only) 759 cpu_dcache_wb_range(va, len); 760 } 761 } 762 763 static inline void 764 pmap_idcache_wbinv_all(pmap_t pm) 765 { 766 if (pm->pm_cstate.cs_cache_id) { 767 cpu_idcache_wbinv_all(); 768 pm->pm_cstate.cs_cache = 0; 769 } 770 } 771 772 static inline void 773 pmap_dcache_wbinv_all(pmap_t pm) 774 { 775 if (pm->pm_cstate.cs_cache_d) { 776 cpu_dcache_wbinv_all(); 777 pm->pm_cstate.cs_cache_d = 0; 778 } 779 } 780 #endif /* PMAP_CACHE_VIVT */ 781 782 static inline bool 783 pmap_is_current(pmap_t pm) 784 { 785 786 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 787 return true; 788 789 return false; 790 } 791 792 static inline bool 793 pmap_is_cached(pmap_t pm) 794 { 795 796 if (pm == pmap_kernel() || pmap_recent_user == NULL || 797 pmap_recent_user == pm) 798 return (true); 799 800 return false; 801 } 802 803 /* 804 * PTE_SYNC_CURRENT: 805 * 806 * Make sure the pte is written out to RAM. 807 * We need to do this for one of two cases: 808 * - We're dealing with the kernel pmap 809 * - There is no pmap active in the cache/tlb. 810 * - The specified pmap is 'active' in the cache/tlb. 811 */ 812 #ifdef PMAP_INCLUDE_PTE_SYNC 813 #define PTE_SYNC_CURRENT(pm, ptep) \ 814 do { \ 815 if (PMAP_NEEDS_PTE_SYNC && \ 816 pmap_is_cached(pm)) \ 817 PTE_SYNC(ptep); \ 818 } while (/*CONSTCOND*/0) 819 #else 820 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 821 #endif 822 823 /* 824 * main pv_entry manipulation functions: 825 * pmap_enter_pv: enter a mapping onto a vm_page list 826 * pmap_remove_pv: remove a mappiing from a vm_page list 827 * 828 * NOTE: pmap_enter_pv expects to lock the pvh itself 829 * pmap_remove_pv expects te caller to lock the pvh before calling 830 */ 831 832 /* 833 * pmap_enter_pv: enter a mapping onto a vm_page lst 834 * 835 * => caller should hold the proper lock on pmap_main_lock 836 * => caller should have pmap locked 837 * => we will gain the lock on the vm_page and allocate the new pv_entry 838 * => caller should adjust ptp's wire_count before calling 839 * => caller should not adjust pmap's wire_count 840 */ 841 static void 842 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 843 vaddr_t va, u_int flags) 844 { 845 struct pv_entry **pvp; 846 847 NPDEBUG(PDB_PVDUMP, 848 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 849 850 pv->pv_pmap = pm; 851 pv->pv_va = va; 852 pv->pv_flags = flags; 853 854 pvp = &SLIST_FIRST(&md->pvh_list); 855 #ifdef PMAP_CACHE_VIPT 856 /* 857 * Insert unmanaged entries, writeable first, at the head of 858 * the pv list. 859 */ 860 if (__predict_true((flags & PVF_KENTRY) == 0)) { 861 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 862 pvp = &SLIST_NEXT(*pvp, pv_link); 863 } else if ((flags & PVF_WRITE) == 0) { 864 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 865 pvp = &SLIST_NEXT(*pvp, pv_link); 866 } 867 #endif 868 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 869 *pvp = pv; /* ... locked list */ 870 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 871 #ifdef PMAP_CACHE_VIPT 872 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 873 md->pvh_attrs |= PVF_KMOD; 874 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 875 md->pvh_attrs |= PVF_DIRTY; 876 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 877 #endif 878 if (pm == pmap_kernel()) { 879 PMAPCOUNT(kernel_mappings); 880 if (flags & PVF_WRITE) 881 md->krw_mappings++; 882 else 883 md->kro_mappings++; 884 } else { 885 if (flags & PVF_WRITE) 886 md->urw_mappings++; 887 else 888 md->uro_mappings++; 889 } 890 891 #ifdef PMAP_CACHE_VIPT 892 /* 893 * If this is an exec mapping and its the first exec mapping 894 * for this page, make sure to sync the I-cache. 895 */ 896 if (PV_IS_EXEC_P(flags)) { 897 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 898 pmap_syncicache_page(md, pa); 899 PMAPCOUNT(exec_synced_map); 900 } 901 PMAPCOUNT(exec_mappings); 902 } 903 #endif 904 905 PMAPCOUNT(mappings); 906 907 if (pv->pv_flags & PVF_WIRED) 908 ++pm->pm_stats.wired_count; 909 } 910 911 /* 912 * 913 * pmap_find_pv: Find a pv entry 914 * 915 * => caller should hold lock on vm_page 916 */ 917 static inline struct pv_entry * 918 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 919 { 920 struct pv_entry *pv; 921 922 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 923 if (pm == pv->pv_pmap && va == pv->pv_va) 924 break; 925 } 926 927 return (pv); 928 } 929 930 /* 931 * pmap_remove_pv: try to remove a mapping from a pv_list 932 * 933 * => caller should hold proper lock on pmap_main_lock 934 * => pmap should be locked 935 * => caller should hold lock on vm_page [so that attrs can be adjusted] 936 * => caller should adjust ptp's wire_count and free PTP if needed 937 * => caller should NOT adjust pmap's wire_count 938 * => we return the removed pv 939 */ 940 static struct pv_entry * 941 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 942 { 943 struct pv_entry *pv, **prevptr; 944 945 NPDEBUG(PDB_PVDUMP, 946 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 947 948 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 949 pv = *prevptr; 950 951 while (pv) { 952 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 953 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 954 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 955 if (pv->pv_flags & PVF_WIRED) { 956 --pm->pm_stats.wired_count; 957 } 958 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 959 if (pm == pmap_kernel()) { 960 PMAPCOUNT(kernel_unmappings); 961 if (pv->pv_flags & PVF_WRITE) 962 md->krw_mappings--; 963 else 964 md->kro_mappings--; 965 } else { 966 if (pv->pv_flags & PVF_WRITE) 967 md->urw_mappings--; 968 else 969 md->uro_mappings--; 970 } 971 972 PMAPCOUNT(unmappings); 973 #ifdef PMAP_CACHE_VIPT 974 if (!(pv->pv_flags & PVF_WRITE)) 975 break; 976 /* 977 * If this page has had an exec mapping, then if 978 * this was the last mapping, discard the contents, 979 * otherwise sync the i-cache for this page. 980 */ 981 if (PV_IS_EXEC_P(md->pvh_attrs)) { 982 if (SLIST_EMPTY(&md->pvh_list)) { 983 md->pvh_attrs &= ~PVF_EXEC; 984 PMAPCOUNT(exec_discarded_unmap); 985 } else { 986 pmap_syncicache_page(md, pa); 987 PMAPCOUNT(exec_synced_unmap); 988 } 989 } 990 #endif /* PMAP_CACHE_VIPT */ 991 break; 992 } 993 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 994 pv = *prevptr; /* advance */ 995 } 996 997 #ifdef PMAP_CACHE_VIPT 998 /* 999 * If we no longer have a WRITEABLE KENTRY at the head of list, 1000 * clear the KMOD attribute from the page. 1001 */ 1002 if (SLIST_FIRST(&md->pvh_list) == NULL 1003 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1004 md->pvh_attrs &= ~PVF_KMOD; 1005 1006 /* 1007 * If this was a writeable page and there are no more writeable 1008 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1009 * the contents to memory. 1010 */ 1011 if (md->krw_mappings + md->urw_mappings == 0) 1012 md->pvh_attrs &= ~PVF_WRITE; 1013 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1014 #endif /* PMAP_CACHE_VIPT */ 1015 1016 return(pv); /* return removed pv */ 1017 } 1018 1019 /* 1020 * 1021 * pmap_modify_pv: Update pv flags 1022 * 1023 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1024 * => caller should NOT adjust pmap's wire_count 1025 * => caller must call pmap_vac_me_harder() if writable status of a page 1026 * may have changed. 1027 * => we return the old flags 1028 * 1029 * Modify a physical-virtual mapping in the pv table 1030 */ 1031 static u_int 1032 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1033 u_int clr_mask, u_int set_mask) 1034 { 1035 struct pv_entry *npv; 1036 u_int flags, oflags; 1037 1038 KASSERT((clr_mask & PVF_KENTRY) == 0); 1039 KASSERT((set_mask & PVF_KENTRY) == 0); 1040 1041 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1042 return (0); 1043 1044 NPDEBUG(PDB_PVDUMP, 1045 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1046 1047 /* 1048 * There is at least one VA mapping this page. 1049 */ 1050 1051 if (clr_mask & (PVF_REF | PVF_MOD)) { 1052 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1053 #ifdef PMAP_CACHE_VIPT 1054 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1055 md->pvh_attrs |= PVF_DIRTY; 1056 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1057 #endif 1058 } 1059 1060 oflags = npv->pv_flags; 1061 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1062 1063 if ((flags ^ oflags) & PVF_WIRED) { 1064 if (flags & PVF_WIRED) 1065 ++pm->pm_stats.wired_count; 1066 else 1067 --pm->pm_stats.wired_count; 1068 } 1069 1070 if ((flags ^ oflags) & PVF_WRITE) { 1071 if (pm == pmap_kernel()) { 1072 if (flags & PVF_WRITE) { 1073 md->krw_mappings++; 1074 md->kro_mappings--; 1075 } else { 1076 md->kro_mappings++; 1077 md->krw_mappings--; 1078 } 1079 } else { 1080 if (flags & PVF_WRITE) { 1081 md->urw_mappings++; 1082 md->uro_mappings--; 1083 } else { 1084 md->uro_mappings++; 1085 md->urw_mappings--; 1086 } 1087 } 1088 } 1089 #ifdef PMAP_CACHE_VIPT 1090 if (md->urw_mappings + md->krw_mappings == 0) 1091 md->pvh_attrs &= ~PVF_WRITE; 1092 /* 1093 * We have two cases here: the first is from enter_pv (new exec 1094 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1095 * Since in latter, pmap_enter_pv won't do anything, we just have 1096 * to do what pmap_remove_pv would do. 1097 */ 1098 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1099 || (PV_IS_EXEC_P(md->pvh_attrs) 1100 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1101 pmap_syncicache_page(md, pa); 1102 PMAPCOUNT(exec_synced_remap); 1103 } 1104 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1105 #endif 1106 1107 PMAPCOUNT(remappings); 1108 1109 return (oflags); 1110 } 1111 1112 /* 1113 * Allocate an L1 translation table for the specified pmap. 1114 * This is called at pmap creation time. 1115 */ 1116 static void 1117 pmap_alloc_l1(pmap_t pm) 1118 { 1119 struct l1_ttable *l1; 1120 uint8_t domain; 1121 1122 /* 1123 * Remove the L1 at the head of the LRU list 1124 */ 1125 mutex_spin_enter(&l1_lru_lock); 1126 l1 = TAILQ_FIRST(&l1_lru_list); 1127 KDASSERT(l1 != NULL); 1128 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1129 1130 /* 1131 * Pick the first available domain number, and update 1132 * the link to the next number. 1133 */ 1134 domain = l1->l1_domain_first; 1135 l1->l1_domain_first = l1->l1_domain_free[domain]; 1136 1137 /* 1138 * If there are still free domain numbers in this L1, 1139 * put it back on the TAIL of the LRU list. 1140 */ 1141 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1142 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1143 1144 mutex_spin_exit(&l1_lru_lock); 1145 1146 /* 1147 * Fix up the relevant bits in the pmap structure 1148 */ 1149 pm->pm_l1 = l1; 1150 pm->pm_domain = domain + 1; 1151 } 1152 1153 /* 1154 * Free an L1 translation table. 1155 * This is called at pmap destruction time. 1156 */ 1157 static void 1158 pmap_free_l1(pmap_t pm) 1159 { 1160 struct l1_ttable *l1 = pm->pm_l1; 1161 1162 mutex_spin_enter(&l1_lru_lock); 1163 1164 /* 1165 * If this L1 is currently on the LRU list, remove it. 1166 */ 1167 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1168 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1169 1170 /* 1171 * Free up the domain number which was allocated to the pmap 1172 */ 1173 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first; 1174 l1->l1_domain_first = pm->pm_domain - 1; 1175 l1->l1_domain_use_count--; 1176 1177 /* 1178 * The L1 now must have at least 1 free domain, so add 1179 * it back to the LRU list. If the use count is zero, 1180 * put it at the head of the list, otherwise it goes 1181 * to the tail. 1182 */ 1183 if (l1->l1_domain_use_count == 0) 1184 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1185 else 1186 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1187 1188 mutex_spin_exit(&l1_lru_lock); 1189 } 1190 1191 static inline void 1192 pmap_use_l1(pmap_t pm) 1193 { 1194 struct l1_ttable *l1; 1195 1196 /* 1197 * Do nothing if we're in interrupt context. 1198 * Access to an L1 by the kernel pmap must not affect 1199 * the LRU list. 1200 */ 1201 if (cpu_intr_p() || pm == pmap_kernel()) 1202 return; 1203 1204 l1 = pm->pm_l1; 1205 1206 /* 1207 * If the L1 is not currently on the LRU list, just return 1208 */ 1209 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1210 return; 1211 1212 mutex_spin_enter(&l1_lru_lock); 1213 1214 /* 1215 * Check the use count again, now that we've acquired the lock 1216 */ 1217 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1218 mutex_spin_exit(&l1_lru_lock); 1219 return; 1220 } 1221 1222 /* 1223 * Move the L1 to the back of the LRU list 1224 */ 1225 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1226 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1227 1228 mutex_spin_exit(&l1_lru_lock); 1229 } 1230 1231 /* 1232 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1233 * 1234 * Free an L2 descriptor table. 1235 */ 1236 static inline void 1237 #ifndef PMAP_INCLUDE_PTE_SYNC 1238 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1239 #else 1240 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1241 #endif 1242 { 1243 #ifdef PMAP_INCLUDE_PTE_SYNC 1244 #ifdef PMAP_CACHE_VIVT 1245 /* 1246 * Note: With a write-back cache, we may need to sync this 1247 * L2 table before re-using it. 1248 * This is because it may have belonged to a non-current 1249 * pmap, in which case the cache syncs would have been 1250 * skipped for the pages that were being unmapped. If the 1251 * L2 table were then to be immediately re-allocated to 1252 * the *current* pmap, it may well contain stale mappings 1253 * which have not yet been cleared by a cache write-back 1254 * and so would still be visible to the mmu. 1255 */ 1256 if (need_sync) 1257 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1258 #endif /* PMAP_CACHE_VIVT */ 1259 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1260 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1261 } 1262 1263 /* 1264 * Returns a pointer to the L2 bucket associated with the specified pmap 1265 * and VA, or NULL if no L2 bucket exists for the address. 1266 */ 1267 static inline struct l2_bucket * 1268 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1269 { 1270 struct l2_dtable *l2; 1271 struct l2_bucket *l2b; 1272 u_short l1idx; 1273 1274 l1idx = L1_IDX(va); 1275 1276 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1277 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1278 return (NULL); 1279 1280 return (l2b); 1281 } 1282 1283 /* 1284 * Returns a pointer to the L2 bucket associated with the specified pmap 1285 * and VA. 1286 * 1287 * If no L2 bucket exists, perform the necessary allocations to put an L2 1288 * bucket/page table in place. 1289 * 1290 * Note that if a new L2 bucket/page was allocated, the caller *must* 1291 * increment the bucket occupancy counter appropriately *before* 1292 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1293 * the bucket/page in the meantime. 1294 */ 1295 static struct l2_bucket * 1296 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1297 { 1298 struct l2_dtable *l2; 1299 struct l2_bucket *l2b; 1300 u_short l1idx; 1301 1302 l1idx = L1_IDX(va); 1303 1304 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1305 /* 1306 * No mapping at this address, as there is 1307 * no entry in the L1 table. 1308 * Need to allocate a new l2_dtable. 1309 */ 1310 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1311 return (NULL); 1312 1313 /* 1314 * Link it into the parent pmap 1315 */ 1316 pm->pm_l2[L2_IDX(l1idx)] = l2; 1317 } 1318 1319 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1320 1321 /* 1322 * Fetch pointer to the L2 page table associated with the address. 1323 */ 1324 if (l2b->l2b_kva == NULL) { 1325 pt_entry_t *ptep; 1326 1327 /* 1328 * No L2 page table has been allocated. Chances are, this 1329 * is because we just allocated the l2_dtable, above. 1330 */ 1331 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1332 /* 1333 * Oops, no more L2 page tables available at this 1334 * time. We may need to deallocate the l2_dtable 1335 * if we allocated a new one above. 1336 */ 1337 if (l2->l2_occupancy == 0) { 1338 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1339 pmap_free_l2_dtable(l2); 1340 } 1341 return (NULL); 1342 } 1343 1344 l2->l2_occupancy++; 1345 l2b->l2b_kva = ptep; 1346 l2b->l2b_l1idx = l1idx; 1347 } 1348 1349 return (l2b); 1350 } 1351 1352 /* 1353 * One or more mappings in the specified L2 descriptor table have just been 1354 * invalidated. 1355 * 1356 * Garbage collect the metadata and descriptor table itself if necessary. 1357 * 1358 * The pmap lock must be acquired when this is called (not necessary 1359 * for the kernel pmap). 1360 */ 1361 static void 1362 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1363 { 1364 struct l2_dtable *l2; 1365 pd_entry_t *pl1pd, l1pd; 1366 pt_entry_t *ptep; 1367 u_short l1idx; 1368 1369 KDASSERT(count <= l2b->l2b_occupancy); 1370 1371 /* 1372 * Update the bucket's reference count according to how many 1373 * PTEs the caller has just invalidated. 1374 */ 1375 l2b->l2b_occupancy -= count; 1376 1377 /* 1378 * Note: 1379 * 1380 * Level 2 page tables allocated to the kernel pmap are never freed 1381 * as that would require checking all Level 1 page tables and 1382 * removing any references to the Level 2 page table. See also the 1383 * comment elsewhere about never freeing bootstrap L2 descriptors. 1384 * 1385 * We make do with just invalidating the mapping in the L2 table. 1386 * 1387 * This isn't really a big deal in practice and, in fact, leads 1388 * to a performance win over time as we don't need to continually 1389 * alloc/free. 1390 */ 1391 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1392 return; 1393 1394 /* 1395 * There are no more valid mappings in this level 2 page table. 1396 * Go ahead and NULL-out the pointer in the bucket, then 1397 * free the page table. 1398 */ 1399 l1idx = l2b->l2b_l1idx; 1400 ptep = l2b->l2b_kva; 1401 l2b->l2b_kva = NULL; 1402 1403 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1404 1405 /* 1406 * If the L1 slot matches the pmap's domain 1407 * number, then invalidate it. 1408 */ 1409 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1410 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1411 *pl1pd = 0; 1412 PTE_SYNC(pl1pd); 1413 } 1414 1415 /* 1416 * Release the L2 descriptor table back to the pool cache. 1417 */ 1418 #ifndef PMAP_INCLUDE_PTE_SYNC 1419 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1420 #else 1421 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1422 #endif 1423 1424 /* 1425 * Update the reference count in the associated l2_dtable 1426 */ 1427 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1428 if (--l2->l2_occupancy > 0) 1429 return; 1430 1431 /* 1432 * There are no more valid mappings in any of the Level 1 1433 * slots managed by this l2_dtable. Go ahead and NULL-out 1434 * the pointer in the parent pmap and free the l2_dtable. 1435 */ 1436 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1437 pmap_free_l2_dtable(l2); 1438 } 1439 1440 /* 1441 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1442 * structures. 1443 */ 1444 static int 1445 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1446 { 1447 #ifndef PMAP_INCLUDE_PTE_SYNC 1448 struct l2_bucket *l2b; 1449 pt_entry_t *ptep, pte; 1450 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1451 1452 /* 1453 * The mappings for these page tables were initially made using 1454 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1455 * mode will not be right for page table mappings. To avoid 1456 * polluting the pmap_kenter_pa() code with a special case for 1457 * page tables, we simply fix up the cache-mode here if it's not 1458 * correct. 1459 */ 1460 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1461 KDASSERT(l2b != NULL); 1462 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1463 pte = *ptep; 1464 1465 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1466 /* 1467 * Page tables must have the cache-mode set to Write-Thru. 1468 */ 1469 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1470 PTE_SYNC(ptep); 1471 cpu_tlb_flushD_SE(va); 1472 cpu_cpwait(); 1473 } 1474 #endif 1475 1476 memset(v, 0, L2_TABLE_SIZE_REAL); 1477 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1478 return (0); 1479 } 1480 1481 static int 1482 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1483 { 1484 1485 memset(v, 0, sizeof(struct l2_dtable)); 1486 return (0); 1487 } 1488 1489 static int 1490 pmap_pmap_ctor(void *arg, void *v, int flags) 1491 { 1492 1493 memset(v, 0, sizeof(struct pmap)); 1494 return (0); 1495 } 1496 1497 static void 1498 pmap_pinit(pmap_t pm) 1499 { 1500 struct l2_bucket *l2b; 1501 1502 if (vector_page < KERNEL_BASE) { 1503 /* 1504 * Map the vector page. 1505 */ 1506 pmap_enter(pm, vector_page, systempage.pv_pa, 1507 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1508 pmap_update(pm); 1509 1510 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1511 l2b = pmap_get_l2_bucket(pm, vector_page); 1512 KDASSERT(l2b != NULL); 1513 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1514 L1_C_DOM(pm->pm_domain); 1515 } else 1516 pm->pm_pl1vec = NULL; 1517 } 1518 1519 #ifdef PMAP_CACHE_VIVT 1520 /* 1521 * Since we have a virtually indexed cache, we may need to inhibit caching if 1522 * there is more than one mapping and at least one of them is writable. 1523 * Since we purge the cache on every context switch, we only need to check for 1524 * other mappings within the same pmap, or kernel_pmap. 1525 * This function is also called when a page is unmapped, to possibly reenable 1526 * caching on any remaining mappings. 1527 * 1528 * The code implements the following logic, where: 1529 * 1530 * KW = # of kernel read/write pages 1531 * KR = # of kernel read only pages 1532 * UW = # of user read/write pages 1533 * UR = # of user read only pages 1534 * 1535 * KC = kernel mapping is cacheable 1536 * UC = user mapping is cacheable 1537 * 1538 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1539 * +--------------------------------------------- 1540 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1541 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1542 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1543 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1544 */ 1545 1546 static const int pmap_vac_flags[4][4] = { 1547 {-1, 0, 0, PVF_KNC}, 1548 {0, 0, PVF_NC, PVF_NC}, 1549 {0, PVF_NC, PVF_NC, PVF_NC}, 1550 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1551 }; 1552 1553 static inline int 1554 pmap_get_vac_flags(const struct vm_page_md *md) 1555 { 1556 int kidx, uidx; 1557 1558 kidx = 0; 1559 if (md->kro_mappings || md->krw_mappings > 1) 1560 kidx |= 1; 1561 if (md->krw_mappings) 1562 kidx |= 2; 1563 1564 uidx = 0; 1565 if (md->uro_mappings || md->urw_mappings > 1) 1566 uidx |= 1; 1567 if (md->urw_mappings) 1568 uidx |= 2; 1569 1570 return (pmap_vac_flags[uidx][kidx]); 1571 } 1572 1573 static inline void 1574 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1575 { 1576 int nattr; 1577 1578 nattr = pmap_get_vac_flags(md); 1579 1580 if (nattr < 0) { 1581 md->pvh_attrs &= ~PVF_NC; 1582 return; 1583 } 1584 1585 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1586 return; 1587 1588 if (pm == pmap_kernel()) 1589 pmap_vac_me_kpmap(md, pa, pm, va); 1590 else 1591 pmap_vac_me_user(md, pa, pm, va); 1592 1593 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1594 } 1595 1596 static void 1597 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1598 { 1599 u_int u_cacheable, u_entries; 1600 struct pv_entry *pv; 1601 pmap_t last_pmap = pm; 1602 1603 /* 1604 * Pass one, see if there are both kernel and user pmaps for 1605 * this page. Calculate whether there are user-writable or 1606 * kernel-writable pages. 1607 */ 1608 u_cacheable = 0; 1609 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1610 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1611 u_cacheable++; 1612 } 1613 1614 u_entries = md->urw_mappings + md->uro_mappings; 1615 1616 /* 1617 * We know we have just been updating a kernel entry, so if 1618 * all user pages are already cacheable, then there is nothing 1619 * further to do. 1620 */ 1621 if (md->k_mappings == 0 && u_cacheable == u_entries) 1622 return; 1623 1624 if (u_entries) { 1625 /* 1626 * Scan over the list again, for each entry, if it 1627 * might not be set correctly, call pmap_vac_me_user 1628 * to recalculate the settings. 1629 */ 1630 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1631 /* 1632 * We know kernel mappings will get set 1633 * correctly in other calls. We also know 1634 * that if the pmap is the same as last_pmap 1635 * then we've just handled this entry. 1636 */ 1637 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1638 continue; 1639 1640 /* 1641 * If there are kernel entries and this page 1642 * is writable but non-cacheable, then we can 1643 * skip this entry also. 1644 */ 1645 if (md->k_mappings && 1646 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1647 (PVF_NC | PVF_WRITE)) 1648 continue; 1649 1650 /* 1651 * Similarly if there are no kernel-writable 1652 * entries and the page is already 1653 * read-only/cacheable. 1654 */ 1655 if (md->krw_mappings == 0 && 1656 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1657 continue; 1658 1659 /* 1660 * For some of the remaining cases, we know 1661 * that we must recalculate, but for others we 1662 * can't tell if they are correct or not, so 1663 * we recalculate anyway. 1664 */ 1665 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1666 } 1667 1668 if (md->k_mappings == 0) 1669 return; 1670 } 1671 1672 pmap_vac_me_user(md, pa, pm, va); 1673 } 1674 1675 static void 1676 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1677 { 1678 pmap_t kpmap = pmap_kernel(); 1679 struct pv_entry *pv, *npv = NULL; 1680 struct l2_bucket *l2b; 1681 pt_entry_t *ptep, pte; 1682 u_int entries = 0; 1683 u_int writable = 0; 1684 u_int cacheable_entries = 0; 1685 u_int kern_cacheable = 0; 1686 u_int other_writable = 0; 1687 1688 /* 1689 * Count mappings and writable mappings in this pmap. 1690 * Include kernel mappings as part of our own. 1691 * Keep a pointer to the first one. 1692 */ 1693 npv = NULL; 1694 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1695 /* Count mappings in the same pmap */ 1696 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1697 if (entries++ == 0) 1698 npv = pv; 1699 1700 /* Cacheable mappings */ 1701 if ((pv->pv_flags & PVF_NC) == 0) { 1702 cacheable_entries++; 1703 if (kpmap == pv->pv_pmap) 1704 kern_cacheable++; 1705 } 1706 1707 /* Writable mappings */ 1708 if (pv->pv_flags & PVF_WRITE) 1709 ++writable; 1710 } else 1711 if (pv->pv_flags & PVF_WRITE) 1712 other_writable = 1; 1713 } 1714 1715 /* 1716 * Enable or disable caching as necessary. 1717 * Note: the first entry might be part of the kernel pmap, 1718 * so we can't assume this is indicative of the state of the 1719 * other (maybe non-kpmap) entries. 1720 */ 1721 if ((entries > 1 && writable) || 1722 (entries > 0 && pm == kpmap && other_writable)) { 1723 if (cacheable_entries == 0) 1724 return; 1725 1726 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1727 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1728 (pv->pv_flags & PVF_NC)) 1729 continue; 1730 1731 pv->pv_flags |= PVF_NC; 1732 1733 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1734 KDASSERT(l2b != NULL); 1735 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1736 pte = *ptep & ~L2_S_CACHE_MASK; 1737 1738 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1739 l2pte_valid(pte)) { 1740 if (PV_BEEN_EXECD(pv->pv_flags)) { 1741 #ifdef PMAP_CACHE_VIVT 1742 pmap_idcache_wbinv_range(pv->pv_pmap, 1743 pv->pv_va, PAGE_SIZE); 1744 #endif 1745 pmap_tlb_flushID_SE(pv->pv_pmap, 1746 pv->pv_va); 1747 } else 1748 if (PV_BEEN_REFD(pv->pv_flags)) { 1749 #ifdef PMAP_CACHE_VIVT 1750 pmap_dcache_wb_range(pv->pv_pmap, 1751 pv->pv_va, PAGE_SIZE, true, 1752 (pv->pv_flags & PVF_WRITE) == 0); 1753 #endif 1754 pmap_tlb_flushD_SE(pv->pv_pmap, 1755 pv->pv_va); 1756 } 1757 } 1758 1759 *ptep = pte; 1760 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1761 } 1762 cpu_cpwait(); 1763 } else 1764 if (entries > cacheable_entries) { 1765 /* 1766 * Turn cacheing back on for some pages. If it is a kernel 1767 * page, only do so if there are no other writable pages. 1768 */ 1769 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1770 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1771 (kpmap != pv->pv_pmap || other_writable))) 1772 continue; 1773 1774 pv->pv_flags &= ~PVF_NC; 1775 1776 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1777 KDASSERT(l2b != NULL); 1778 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1779 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1780 1781 if (l2pte_valid(pte)) { 1782 if (PV_BEEN_EXECD(pv->pv_flags)) { 1783 pmap_tlb_flushID_SE(pv->pv_pmap, 1784 pv->pv_va); 1785 } else 1786 if (PV_BEEN_REFD(pv->pv_flags)) { 1787 pmap_tlb_flushD_SE(pv->pv_pmap, 1788 pv->pv_va); 1789 } 1790 } 1791 1792 *ptep = pte; 1793 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1794 } 1795 } 1796 } 1797 #endif 1798 1799 #ifdef PMAP_CACHE_VIPT 1800 static void 1801 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1802 { 1803 struct pv_entry *pv; 1804 vaddr_t tst_mask; 1805 bool bad_alias; 1806 struct l2_bucket *l2b; 1807 pt_entry_t *ptep, pte, opte; 1808 const u_int 1809 rw_mappings = md->urw_mappings + md->krw_mappings, 1810 ro_mappings = md->uro_mappings + md->kro_mappings; 1811 1812 /* do we need to do anything? */ 1813 if (arm_cache_prefer_mask == 0) 1814 return; 1815 1816 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1817 md, pm, va)); 1818 1819 KASSERT(!va || pm); 1820 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1821 1822 /* Already a conflict? */ 1823 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1824 /* just an add, things are already non-cached */ 1825 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1826 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1827 bad_alias = false; 1828 if (va) { 1829 PMAPCOUNT(vac_color_none); 1830 bad_alias = true; 1831 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1832 goto fixup; 1833 } 1834 pv = SLIST_FIRST(&md->pvh_list); 1835 /* the list can't be empty because it would be cachable */ 1836 if (md->pvh_attrs & PVF_KMPAGE) { 1837 tst_mask = md->pvh_attrs; 1838 } else { 1839 KASSERT(pv); 1840 tst_mask = pv->pv_va; 1841 pv = SLIST_NEXT(pv, pv_link); 1842 } 1843 /* 1844 * Only check for a bad alias if we have writable mappings. 1845 */ 1846 tst_mask &= arm_cache_prefer_mask; 1847 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1848 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1849 /* if there's a bad alias, stop checking. */ 1850 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1851 bad_alias = true; 1852 } 1853 md->pvh_attrs |= PVF_WRITE; 1854 if (!bad_alias) 1855 md->pvh_attrs |= PVF_DIRTY; 1856 } else { 1857 /* 1858 * We have only read-only mappings. Let's see if there 1859 * are multiple colors in use or if we mapped a KMPAGE. 1860 * If the latter, we have a bad alias. If the former, 1861 * we need to remember that. 1862 */ 1863 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1864 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1865 if (md->pvh_attrs & PVF_KMPAGE) 1866 bad_alias = true; 1867 break; 1868 } 1869 } 1870 md->pvh_attrs &= ~PVF_WRITE; 1871 /* 1872 * No KMPAGE and we exited early, so we must have 1873 * multiple color mappings. 1874 */ 1875 if (!bad_alias && pv != NULL) 1876 md->pvh_attrs |= PVF_MULTCLR; 1877 } 1878 1879 /* If no conflicting colors, set everything back to cached */ 1880 if (!bad_alias) { 1881 #ifdef DEBUG 1882 if ((md->pvh_attrs & PVF_WRITE) 1883 || ro_mappings < 2) { 1884 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1885 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1886 } 1887 #endif 1888 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1889 md->pvh_attrs |= tst_mask | PVF_COLORED; 1890 /* 1891 * Restore DIRTY bit if page is modified 1892 */ 1893 if (md->pvh_attrs & PVF_DMOD) 1894 md->pvh_attrs |= PVF_DIRTY; 1895 PMAPCOUNT(vac_color_restore); 1896 } else { 1897 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1898 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1899 } 1900 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1901 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1902 } else if (!va) { 1903 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1904 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1905 || (md->pvh_attrs & PVF_DIRTY)); 1906 if (rw_mappings == 0) { 1907 md->pvh_attrs &= ~PVF_WRITE; 1908 if (ro_mappings == 1 1909 && (md->pvh_attrs & PVF_MULTCLR)) { 1910 /* 1911 * If this is the last readonly mapping 1912 * but it doesn't match the current color 1913 * for the page, change the current color 1914 * to match this last readonly mapping. 1915 */ 1916 pv = SLIST_FIRST(&md->pvh_list); 1917 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1918 & arm_cache_prefer_mask; 1919 if (tst_mask) { 1920 md->pvh_attrs ^= tst_mask; 1921 PMAPCOUNT(vac_color_change); 1922 } 1923 } 1924 } 1925 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1926 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1927 return; 1928 } else if (!pmap_is_page_colored_p(md)) { 1929 /* not colored so we just use its color */ 1930 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1931 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1932 PMAPCOUNT(vac_color_new); 1933 md->pvh_attrs &= PAGE_SIZE - 1; 1934 md->pvh_attrs |= PVF_COLORED 1935 | (va & arm_cache_prefer_mask) 1936 | (rw_mappings > 0 ? PVF_WRITE : 0); 1937 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1938 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1939 return; 1940 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1941 bad_alias = false; 1942 if (rw_mappings > 0) { 1943 /* 1944 * We now have writeable mappings and if we have 1945 * readonly mappings in more than once color, we have 1946 * an aliasing problem. Regardless mark the page as 1947 * writeable. 1948 */ 1949 if (md->pvh_attrs & PVF_MULTCLR) { 1950 if (ro_mappings < 2) { 1951 /* 1952 * If we only have less than two 1953 * read-only mappings, just flush the 1954 * non-primary colors from the cache. 1955 */ 1956 pmap_flush_page(md, pa, 1957 PMAP_FLUSH_SECONDARY); 1958 } else { 1959 bad_alias = true; 1960 } 1961 } 1962 md->pvh_attrs |= PVF_WRITE; 1963 } 1964 /* If no conflicting colors, set everything back to cached */ 1965 if (!bad_alias) { 1966 #ifdef DEBUG 1967 if (rw_mappings > 0 1968 || (md->pvh_attrs & PMAP_KMPAGE)) { 1969 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1970 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1971 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1972 } 1973 #endif 1974 if (SLIST_EMPTY(&md->pvh_list)) 1975 PMAPCOUNT(vac_color_reuse); 1976 else 1977 PMAPCOUNT(vac_color_ok); 1978 1979 /* matching color, just return */ 1980 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1981 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1982 return; 1983 } 1984 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1985 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1986 1987 /* color conflict. evict from cache. */ 1988 1989 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 1990 md->pvh_attrs &= ~PVF_COLORED; 1991 md->pvh_attrs |= PVF_NC; 1992 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1993 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1994 PMAPCOUNT(vac_color_erase); 1995 } else if (rw_mappings == 0 1996 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 1997 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 1998 1999 /* 2000 * If the page has dirty cache lines, clean it. 2001 */ 2002 if (md->pvh_attrs & PVF_DIRTY) 2003 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2004 2005 /* 2006 * If this is the first remapping (we know that there are no 2007 * writeable mappings), then this is a simple color change. 2008 * Otherwise this is a seconary r/o mapping, which means 2009 * we don't have to do anything. 2010 */ 2011 if (ro_mappings == 1) { 2012 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2013 md->pvh_attrs &= PAGE_SIZE - 1; 2014 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2015 PMAPCOUNT(vac_color_change); 2016 } else { 2017 PMAPCOUNT(vac_color_blind); 2018 } 2019 md->pvh_attrs |= PVF_MULTCLR; 2020 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2021 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2022 return; 2023 } else { 2024 if (rw_mappings > 0) 2025 md->pvh_attrs |= PVF_WRITE; 2026 2027 /* color conflict. evict from cache. */ 2028 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2029 2030 /* the list can't be empty because this was a enter/modify */ 2031 pv = SLIST_FIRST(&md->pvh_list); 2032 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2033 KASSERT(pv); 2034 /* 2035 * If there's only one mapped page, change color to the 2036 * page's new color and return. Restore the DIRTY bit 2037 * that was erased by pmap_flush_page. 2038 */ 2039 if (SLIST_NEXT(pv, pv_link) == NULL) { 2040 md->pvh_attrs &= PAGE_SIZE - 1; 2041 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2042 if (md->pvh_attrs & PVF_DMOD) 2043 md->pvh_attrs |= PVF_DIRTY; 2044 PMAPCOUNT(vac_color_change); 2045 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2046 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2047 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2048 return; 2049 } 2050 } 2051 bad_alias = true; 2052 md->pvh_attrs &= ~PVF_COLORED; 2053 md->pvh_attrs |= PVF_NC; 2054 PMAPCOUNT(vac_color_erase); 2055 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2056 } 2057 2058 fixup: 2059 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2060 2061 /* 2062 * Turn cacheing on/off for all pages. 2063 */ 2064 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2065 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2066 KDASSERT(l2b != NULL); 2067 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2068 opte = *ptep; 2069 pte = opte & ~L2_S_CACHE_MASK; 2070 if (bad_alias) { 2071 pv->pv_flags |= PVF_NC; 2072 } else { 2073 pv->pv_flags &= ~PVF_NC; 2074 pte |= pte_l2_s_cache_mode; 2075 } 2076 2077 if (opte == pte) /* only update is there's a change */ 2078 continue; 2079 2080 if (l2pte_valid(pte)) { 2081 if (PV_BEEN_EXECD(pv->pv_flags)) { 2082 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2083 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2084 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2085 } 2086 } 2087 2088 *ptep = pte; 2089 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2090 } 2091 } 2092 #endif /* PMAP_CACHE_VIPT */ 2093 2094 2095 /* 2096 * Modify pte bits for all ptes corresponding to the given physical address. 2097 * We use `maskbits' rather than `clearbits' because we're always passing 2098 * constants and the latter would require an extra inversion at run-time. 2099 */ 2100 static void 2101 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2102 { 2103 struct l2_bucket *l2b; 2104 struct pv_entry *pv; 2105 pt_entry_t *ptep, npte, opte; 2106 pmap_t pm; 2107 vaddr_t va; 2108 u_int oflags; 2109 #ifdef PMAP_CACHE_VIPT 2110 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2111 bool need_syncicache = false; 2112 bool did_syncicache = false; 2113 bool need_vac_me_harder = false; 2114 #endif 2115 2116 NPDEBUG(PDB_BITS, 2117 printf("pmap_clearbit: md %p mask 0x%x\n", 2118 md, maskbits)); 2119 2120 #ifdef PMAP_CACHE_VIPT 2121 /* 2122 * If we might want to sync the I-cache and we've modified it, 2123 * then we know we definitely need to sync or discard it. 2124 */ 2125 if (want_syncicache) 2126 need_syncicache = md->pvh_attrs & PVF_MOD; 2127 #endif 2128 /* 2129 * Clear saved attributes (modify, reference) 2130 */ 2131 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2132 2133 if (SLIST_EMPTY(&md->pvh_list)) { 2134 #ifdef PMAP_CACHE_VIPT 2135 if (need_syncicache) { 2136 /* 2137 * No one has it mapped, so just discard it. The next 2138 * exec remapping will cause it to be synced. 2139 */ 2140 md->pvh_attrs &= ~PVF_EXEC; 2141 PMAPCOUNT(exec_discarded_clearbit); 2142 } 2143 #endif 2144 return; 2145 } 2146 2147 /* 2148 * Loop over all current mappings setting/clearing as appropos 2149 */ 2150 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2151 va = pv->pv_va; 2152 pm = pv->pv_pmap; 2153 oflags = pv->pv_flags; 2154 /* 2155 * Kernel entries are unmanaged and as such not to be changed. 2156 */ 2157 if (oflags & PVF_KENTRY) 2158 continue; 2159 pv->pv_flags &= ~maskbits; 2160 2161 pmap_acquire_pmap_lock(pm); 2162 2163 l2b = pmap_get_l2_bucket(pm, va); 2164 KDASSERT(l2b != NULL); 2165 2166 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2167 npte = opte = *ptep; 2168 2169 NPDEBUG(PDB_BITS, 2170 printf( 2171 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2172 pv, pv->pv_pmap, pv->pv_va, oflags)); 2173 2174 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2175 #ifdef PMAP_CACHE_VIVT 2176 if ((pv->pv_flags & PVF_NC)) { 2177 /* 2178 * Entry is not cacheable: 2179 * 2180 * Don't turn caching on again if this is a 2181 * modified emulation. This would be 2182 * inconsitent with the settings created by 2183 * pmap_vac_me_harder(). Otherwise, it's safe 2184 * to re-enable cacheing. 2185 * 2186 * There's no need to call pmap_vac_me_harder() 2187 * here: all pages are losing their write 2188 * permission. 2189 */ 2190 if (maskbits & PVF_WRITE) { 2191 npte |= pte_l2_s_cache_mode; 2192 pv->pv_flags &= ~PVF_NC; 2193 } 2194 } else 2195 if (l2pte_writable_p(opte)) { 2196 /* 2197 * Entry is writable/cacheable: check if pmap 2198 * is current if it is flush it, otherwise it 2199 * won't be in the cache 2200 */ 2201 if (PV_BEEN_EXECD(oflags)) 2202 pmap_idcache_wbinv_range(pm, pv->pv_va, 2203 PAGE_SIZE); 2204 else 2205 if (PV_BEEN_REFD(oflags)) 2206 pmap_dcache_wb_range(pm, pv->pv_va, 2207 PAGE_SIZE, 2208 (maskbits & PVF_REF) != 0, false); 2209 } 2210 #endif 2211 2212 /* make the pte read only */ 2213 npte = l2pte_set_readonly(npte); 2214 2215 if (maskbits & oflags & PVF_WRITE) { 2216 /* 2217 * Keep alias accounting up to date 2218 */ 2219 if (pv->pv_pmap == pmap_kernel()) { 2220 md->krw_mappings--; 2221 md->kro_mappings++; 2222 } else { 2223 md->urw_mappings--; 2224 md->uro_mappings++; 2225 } 2226 #ifdef PMAP_CACHE_VIPT 2227 if (md->urw_mappings + md->krw_mappings == 0) 2228 md->pvh_attrs &= ~PVF_WRITE; 2229 if (want_syncicache) 2230 need_syncicache = true; 2231 need_vac_me_harder = true; 2232 #endif 2233 } 2234 } 2235 2236 if (maskbits & PVF_REF) { 2237 if ((pv->pv_flags & PVF_NC) == 0 && 2238 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2239 l2pte_valid(npte)) { 2240 #ifdef PMAP_CACHE_VIVT 2241 /* 2242 * Check npte here; we may have already 2243 * done the wbinv above, and the validity 2244 * of the PTE is the same for opte and 2245 * npte. 2246 */ 2247 /* XXXJRT need idcache_inv_range */ 2248 if (PV_BEEN_EXECD(oflags)) 2249 pmap_idcache_wbinv_range(pm, 2250 pv->pv_va, PAGE_SIZE); 2251 else 2252 if (PV_BEEN_REFD(oflags)) 2253 pmap_dcache_wb_range(pm, 2254 pv->pv_va, PAGE_SIZE, 2255 true, true); 2256 #endif 2257 } 2258 2259 /* 2260 * Make the PTE invalid so that we will take a 2261 * page fault the next time the mapping is 2262 * referenced. 2263 */ 2264 npte &= ~L2_TYPE_MASK; 2265 npte |= L2_TYPE_INV; 2266 } 2267 2268 if (npte != opte) { 2269 *ptep = npte; 2270 PTE_SYNC(ptep); 2271 /* Flush the TLB entry if a current pmap. */ 2272 if (PV_BEEN_EXECD(oflags)) 2273 pmap_tlb_flushID_SE(pm, pv->pv_va); 2274 else 2275 if (PV_BEEN_REFD(oflags)) 2276 pmap_tlb_flushD_SE(pm, pv->pv_va); 2277 } 2278 2279 pmap_release_pmap_lock(pm); 2280 2281 NPDEBUG(PDB_BITS, 2282 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2283 pm, va, opte, npte)); 2284 } 2285 2286 #ifdef PMAP_CACHE_VIPT 2287 /* 2288 * If we need to sync the I-cache and we haven't done it yet, do it. 2289 */ 2290 if (need_syncicache && !did_syncicache) { 2291 pmap_syncicache_page(md, pa); 2292 PMAPCOUNT(exec_synced_clearbit); 2293 } 2294 /* 2295 * If we are changing this to read-only, we need to call vac_me_harder 2296 * so we can change all the read-only pages to cacheable. We pretend 2297 * this as a page deletion. 2298 */ 2299 if (need_vac_me_harder) { 2300 if (md->pvh_attrs & PVF_NC) 2301 pmap_vac_me_harder(md, pa, NULL, 0); 2302 } 2303 #endif 2304 } 2305 2306 /* 2307 * pmap_clean_page() 2308 * 2309 * This is a local function used to work out the best strategy to clean 2310 * a single page referenced by its entry in the PV table. It's used by 2311 * pmap_copy_page, pmap_zero page and maybe some others later on. 2312 * 2313 * Its policy is effectively: 2314 * o If there are no mappings, we don't bother doing anything with the cache. 2315 * o If there is one mapping, we clean just that page. 2316 * o If there are multiple mappings, we clean the entire cache. 2317 * 2318 * So that some functions can be further optimised, it returns 0 if it didn't 2319 * clean the entire cache, or 1 if it did. 2320 * 2321 * XXX One bug in this routine is that if the pv_entry has a single page 2322 * mapped at 0x00000000 a whole cache clean will be performed rather than 2323 * just the 1 page. Since this should not occur in everyday use and if it does 2324 * it will just result in not the most efficient clean for the page. 2325 */ 2326 #ifdef PMAP_CACHE_VIVT 2327 static int 2328 pmap_clean_page(struct pv_entry *pv, bool is_src) 2329 { 2330 pmap_t pm_to_clean = NULL; 2331 struct pv_entry *npv; 2332 u_int cache_needs_cleaning = 0; 2333 u_int flags = 0; 2334 vaddr_t page_to_clean = 0; 2335 2336 if (pv == NULL) { 2337 /* nothing mapped in so nothing to flush */ 2338 return (0); 2339 } 2340 2341 /* 2342 * Since we flush the cache each time we change to a different 2343 * user vmspace, we only need to flush the page if it is in the 2344 * current pmap. 2345 */ 2346 2347 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2348 if (pmap_is_current(npv->pv_pmap)) { 2349 flags |= npv->pv_flags; 2350 /* 2351 * The page is mapped non-cacheable in 2352 * this map. No need to flush the cache. 2353 */ 2354 if (npv->pv_flags & PVF_NC) { 2355 #ifdef DIAGNOSTIC 2356 if (cache_needs_cleaning) 2357 panic("pmap_clean_page: " 2358 "cache inconsistency"); 2359 #endif 2360 break; 2361 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2362 continue; 2363 if (cache_needs_cleaning) { 2364 page_to_clean = 0; 2365 break; 2366 } else { 2367 page_to_clean = npv->pv_va; 2368 pm_to_clean = npv->pv_pmap; 2369 } 2370 cache_needs_cleaning = 1; 2371 } 2372 } 2373 2374 if (page_to_clean) { 2375 if (PV_BEEN_EXECD(flags)) 2376 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2377 PAGE_SIZE); 2378 else 2379 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2380 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2381 } else if (cache_needs_cleaning) { 2382 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2383 2384 if (PV_BEEN_EXECD(flags)) 2385 pmap_idcache_wbinv_all(pm); 2386 else 2387 pmap_dcache_wbinv_all(pm); 2388 return (1); 2389 } 2390 return (0); 2391 } 2392 #endif 2393 2394 #ifdef PMAP_CACHE_VIPT 2395 /* 2396 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2397 * right cache alias to make sure we flush the right stuff. 2398 */ 2399 void 2400 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2401 { 2402 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2403 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2404 2405 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2406 md, md->pvh_attrs)); 2407 /* 2408 * No need to clean the page if it's non-cached. 2409 */ 2410 if (md->pvh_attrs & PVF_NC) 2411 return; 2412 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2413 2414 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2415 /* 2416 * Set up a PTE with the right coloring to flush existing cache lines. 2417 */ 2418 *ptep = L2_S_PROTO | 2419 pa 2420 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2421 | pte_l2_s_cache_mode; 2422 PTE_SYNC(ptep); 2423 2424 /* 2425 * Flush it. 2426 */ 2427 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2428 /* 2429 * Unmap the page. 2430 */ 2431 *ptep = 0; 2432 PTE_SYNC(ptep); 2433 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2434 2435 md->pvh_attrs |= PVF_EXEC; 2436 PMAPCOUNT(exec_synced); 2437 } 2438 2439 void 2440 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2441 { 2442 vsize_t va_offset, end_va; 2443 void (*cf)(vaddr_t, vsize_t); 2444 2445 if (arm_cache_prefer_mask == 0) 2446 return; 2447 2448 switch (flush) { 2449 case PMAP_FLUSH_PRIMARY: 2450 if (md->pvh_attrs & PVF_MULTCLR) { 2451 va_offset = 0; 2452 end_va = arm_cache_prefer_mask; 2453 md->pvh_attrs &= ~PVF_MULTCLR; 2454 PMAPCOUNT(vac_flush_lots); 2455 } else { 2456 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2457 end_va = va_offset; 2458 PMAPCOUNT(vac_flush_one); 2459 } 2460 /* 2461 * Mark that the page is no longer dirty. 2462 */ 2463 md->pvh_attrs &= ~PVF_DIRTY; 2464 cf = cpufuncs.cf_idcache_wbinv_range; 2465 break; 2466 case PMAP_FLUSH_SECONDARY: 2467 va_offset = 0; 2468 end_va = arm_cache_prefer_mask; 2469 cf = cpufuncs.cf_idcache_wbinv_range; 2470 md->pvh_attrs &= ~PVF_MULTCLR; 2471 PMAPCOUNT(vac_flush_lots); 2472 break; 2473 case PMAP_CLEAN_PRIMARY: 2474 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2475 end_va = va_offset; 2476 cf = cpufuncs.cf_dcache_wb_range; 2477 /* 2478 * Mark that the page is no longer dirty. 2479 */ 2480 if ((md->pvh_attrs & PVF_DMOD) == 0) 2481 md->pvh_attrs &= ~PVF_DIRTY; 2482 PMAPCOUNT(vac_clean_one); 2483 break; 2484 default: 2485 return; 2486 } 2487 2488 KASSERT(!(md->pvh_attrs & PVF_NC)); 2489 2490 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2491 md, md->pvh_attrs)); 2492 2493 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2494 const size_t pte_offset = va_offset >> PGSHIFT; 2495 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2496 const pt_entry_t oldpte = *ptep; 2497 2498 if (flush == PMAP_FLUSH_SECONDARY 2499 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2500 continue; 2501 2502 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2503 /* 2504 * Set up a PTE with the right coloring to flush 2505 * existing cache entries. 2506 */ 2507 *ptep = L2_S_PROTO 2508 | pa 2509 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2510 | pte_l2_s_cache_mode; 2511 PTE_SYNC(ptep); 2512 2513 /* 2514 * Flush it. 2515 */ 2516 (*cf)(cdstp + va_offset, PAGE_SIZE); 2517 2518 /* 2519 * Restore the page table entry since we might have interrupted 2520 * pmap_zero_page or pmap_copy_page which was already using 2521 * this pte. 2522 */ 2523 *ptep = oldpte; 2524 PTE_SYNC(ptep); 2525 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2526 } 2527 } 2528 #endif /* PMAP_CACHE_VIPT */ 2529 2530 /* 2531 * Routine: pmap_page_remove 2532 * Function: 2533 * Removes this physical page from 2534 * all physical maps in which it resides. 2535 * Reflects back modify bits to the pager. 2536 */ 2537 static void 2538 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2539 { 2540 struct l2_bucket *l2b; 2541 struct pv_entry *pv, *npv, **pvp; 2542 pmap_t pm; 2543 pt_entry_t *ptep; 2544 bool flush; 2545 u_int flags; 2546 2547 NPDEBUG(PDB_FOLLOW, 2548 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2549 pa)); 2550 2551 pv = SLIST_FIRST(&md->pvh_list); 2552 if (pv == NULL) { 2553 #ifdef PMAP_CACHE_VIPT 2554 /* 2555 * We *know* the page contents are about to be replaced. 2556 * Discard the exec contents 2557 */ 2558 if (PV_IS_EXEC_P(md->pvh_attrs)) 2559 PMAPCOUNT(exec_discarded_page_protect); 2560 md->pvh_attrs &= ~PVF_EXEC; 2561 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2562 #endif 2563 return; 2564 } 2565 #ifdef PMAP_CACHE_VIPT 2566 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2567 #endif 2568 2569 /* 2570 * Clear alias counts 2571 */ 2572 #ifdef PMAP_CACHE_VIVT 2573 md->k_mappings = 0; 2574 #endif 2575 md->urw_mappings = md->uro_mappings = 0; 2576 2577 flush = false; 2578 flags = 0; 2579 2580 #ifdef PMAP_CACHE_VIVT 2581 pmap_clean_page(pv, false); 2582 #endif 2583 2584 pvp = &SLIST_FIRST(&md->pvh_list); 2585 while (pv) { 2586 pm = pv->pv_pmap; 2587 npv = SLIST_NEXT(pv, pv_link); 2588 if (flush == false && pmap_is_current(pm)) 2589 flush = true; 2590 2591 if (pm == pmap_kernel()) { 2592 #ifdef PMAP_CACHE_VIPT 2593 /* 2594 * If this was unmanaged mapping, it must be preserved. 2595 * Move it back on the list and advance the end-of-list 2596 * pointer. 2597 */ 2598 if (pv->pv_flags & PVF_KENTRY) { 2599 *pvp = pv; 2600 pvp = &SLIST_NEXT(pv, pv_link); 2601 pv = npv; 2602 continue; 2603 } 2604 if (pv->pv_flags & PVF_WRITE) 2605 md->krw_mappings--; 2606 else 2607 md->kro_mappings--; 2608 #endif 2609 PMAPCOUNT(kernel_unmappings); 2610 } 2611 PMAPCOUNT(unmappings); 2612 2613 pmap_acquire_pmap_lock(pm); 2614 2615 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2616 KDASSERT(l2b != NULL); 2617 2618 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2619 2620 /* 2621 * Update statistics 2622 */ 2623 --pm->pm_stats.resident_count; 2624 2625 /* Wired bit */ 2626 if (pv->pv_flags & PVF_WIRED) 2627 --pm->pm_stats.wired_count; 2628 2629 flags |= pv->pv_flags; 2630 2631 /* 2632 * Invalidate the PTEs. 2633 */ 2634 *ptep = 0; 2635 PTE_SYNC_CURRENT(pm, ptep); 2636 pmap_free_l2_bucket(pm, l2b, 1); 2637 2638 pool_put(&pmap_pv_pool, pv); 2639 pv = npv; 2640 /* 2641 * if we reach the end of the list and there are still 2642 * mappings, they might be able to be cached now. 2643 */ 2644 if (pv == NULL) { 2645 *pvp = NULL; 2646 if (!SLIST_EMPTY(&md->pvh_list)) 2647 pmap_vac_me_harder(md, pa, pm, 0); 2648 } 2649 pmap_release_pmap_lock(pm); 2650 } 2651 #ifdef PMAP_CACHE_VIPT 2652 /* 2653 * Its EXEC cache is now gone. 2654 */ 2655 if (PV_IS_EXEC_P(md->pvh_attrs)) 2656 PMAPCOUNT(exec_discarded_page_protect); 2657 md->pvh_attrs &= ~PVF_EXEC; 2658 KASSERT(md->urw_mappings == 0); 2659 KASSERT(md->uro_mappings == 0); 2660 if (md->krw_mappings == 0) 2661 md->pvh_attrs &= ~PVF_WRITE; 2662 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2663 #endif 2664 2665 if (flush) { 2666 /* 2667 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2668 * would need a subsequent call to pmap_update() to ensure 2669 * curpm->pm_cstate.cs_all is reset. Our callers are not 2670 * required to do that (see pmap(9)), so we can't modify 2671 * the current pmap's state. 2672 */ 2673 if (PV_BEEN_EXECD(flags)) 2674 cpu_tlb_flushID(); 2675 else 2676 cpu_tlb_flushD(); 2677 } 2678 cpu_cpwait(); 2679 } 2680 2681 /* 2682 * pmap_t pmap_create(void) 2683 * 2684 * Create a new pmap structure from scratch. 2685 */ 2686 pmap_t 2687 pmap_create(void) 2688 { 2689 pmap_t pm; 2690 2691 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2692 2693 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2694 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2695 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2696 2697 pm->pm_stats.wired_count = 0; 2698 pm->pm_stats.resident_count = 1; 2699 pm->pm_cstate.cs_all = 0; 2700 pmap_alloc_l1(pm); 2701 2702 /* 2703 * Note: The pool cache ensures that the pm_l2[] array is already 2704 * initialised to zero. 2705 */ 2706 2707 pmap_pinit(pm); 2708 2709 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2710 2711 return (pm); 2712 } 2713 2714 u_int 2715 arm32_mmap_flags(paddr_t pa) 2716 { 2717 /* 2718 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 2719 * and we're using the upper bits in page numbers to pass flags around 2720 * so we might as well use the same bits 2721 */ 2722 return (u_int)pa & PMAP_MD_MASK; 2723 } 2724 /* 2725 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2726 * u_int flags) 2727 * 2728 * Insert the given physical page (p) at 2729 * the specified virtual address (v) in the 2730 * target physical map with the protection requested. 2731 * 2732 * NB: This is the only routine which MAY NOT lazy-evaluate 2733 * or lose information. That is, this routine must actually 2734 * insert this page into the given map NOW. 2735 */ 2736 int 2737 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2738 { 2739 struct l2_bucket *l2b; 2740 struct vm_page *pg, *opg; 2741 struct pv_entry *pv; 2742 pt_entry_t *ptep, npte, opte; 2743 u_int nflags; 2744 u_int oflags; 2745 2746 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2747 2748 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2749 KDASSERT(((va | pa) & PGOFSET) == 0); 2750 2751 /* 2752 * Get a pointer to the page. Later on in this function, we 2753 * test for a managed page by checking pg != NULL. 2754 */ 2755 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2756 2757 nflags = 0; 2758 if (prot & VM_PROT_WRITE) 2759 nflags |= PVF_WRITE; 2760 if (prot & VM_PROT_EXECUTE) 2761 nflags |= PVF_EXEC; 2762 if (flags & PMAP_WIRED) 2763 nflags |= PVF_WIRED; 2764 2765 pmap_acquire_pmap_lock(pm); 2766 2767 /* 2768 * Fetch the L2 bucket which maps this page, allocating one if 2769 * necessary for user pmaps. 2770 */ 2771 if (pm == pmap_kernel()) 2772 l2b = pmap_get_l2_bucket(pm, va); 2773 else 2774 l2b = pmap_alloc_l2_bucket(pm, va); 2775 if (l2b == NULL) { 2776 if (flags & PMAP_CANFAIL) { 2777 pmap_release_pmap_lock(pm); 2778 return (ENOMEM); 2779 } 2780 panic("pmap_enter: failed to allocate L2 bucket"); 2781 } 2782 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2783 opte = *ptep; 2784 npte = pa; 2785 oflags = 0; 2786 2787 if (opte) { 2788 /* 2789 * There is already a mapping at this address. 2790 * If the physical address is different, lookup the 2791 * vm_page. 2792 */ 2793 if (l2pte_pa(opte) != pa) 2794 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2795 else 2796 opg = pg; 2797 } else 2798 opg = NULL; 2799 2800 if (pg) { 2801 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2802 2803 /* 2804 * This is to be a managed mapping. 2805 */ 2806 if ((flags & VM_PROT_ALL) || 2807 (md->pvh_attrs & PVF_REF)) { 2808 /* 2809 * - The access type indicates that we don't need 2810 * to do referenced emulation. 2811 * OR 2812 * - The physical page has already been referenced 2813 * so no need to re-do referenced emulation here. 2814 */ 2815 npte |= l2pte_set_readonly(L2_S_PROTO); 2816 2817 nflags |= PVF_REF; 2818 2819 if ((prot & VM_PROT_WRITE) != 0 && 2820 ((flags & VM_PROT_WRITE) != 0 || 2821 (md->pvh_attrs & PVF_MOD) != 0)) { 2822 /* 2823 * This is a writable mapping, and the 2824 * page's mod state indicates it has 2825 * already been modified. Make it 2826 * writable from the outset. 2827 */ 2828 npte = l2pte_set_writable(npte); 2829 nflags |= PVF_MOD; 2830 } 2831 } else { 2832 /* 2833 * Need to do page referenced emulation. 2834 */ 2835 npte |= L2_TYPE_INV; 2836 } 2837 2838 npte |= pte_l2_s_cache_mode; 2839 2840 if (pg == opg) { 2841 /* 2842 * We're changing the attrs of an existing mapping. 2843 */ 2844 #ifdef MULTIPROCESSOR 2845 KASSERT(uvm_page_locked_p(pg)); 2846 #endif 2847 oflags = pmap_modify_pv(md, pa, pm, va, 2848 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2849 PVF_MOD | PVF_REF, nflags); 2850 2851 #ifdef PMAP_CACHE_VIVT 2852 /* 2853 * We may need to flush the cache if we're 2854 * doing rw-ro... 2855 */ 2856 if (pm->pm_cstate.cs_cache_d && 2857 (oflags & PVF_NC) == 0 && 2858 l2pte_writable_p(opte) && 2859 (prot & VM_PROT_WRITE) == 0) 2860 cpu_dcache_wb_range(va, PAGE_SIZE); 2861 #endif 2862 } else { 2863 /* 2864 * New mapping, or changing the backing page 2865 * of an existing mapping. 2866 */ 2867 if (opg) { 2868 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2869 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2870 2871 /* 2872 * Replacing an existing mapping with a new one. 2873 * It is part of our managed memory so we 2874 * must remove it from the PV list 2875 */ 2876 #ifdef MULTIPROCESSOR 2877 KASSERT(uvm_page_locked_p(opg)); 2878 #endif 2879 pv = pmap_remove_pv(omd, opa, pm, va); 2880 pmap_vac_me_harder(omd, opa, pm, 0); 2881 oflags = pv->pv_flags; 2882 2883 #ifdef PMAP_CACHE_VIVT 2884 /* 2885 * If the old mapping was valid (ref/mod 2886 * emulation creates 'invalid' mappings 2887 * initially) then make sure to frob 2888 * the cache. 2889 */ 2890 if ((oflags & PVF_NC) == 0 && 2891 l2pte_valid(opte)) { 2892 if (PV_BEEN_EXECD(oflags)) { 2893 pmap_idcache_wbinv_range(pm, va, 2894 PAGE_SIZE); 2895 } else 2896 if (PV_BEEN_REFD(oflags)) { 2897 pmap_dcache_wb_range(pm, va, 2898 PAGE_SIZE, true, 2899 (oflags & PVF_WRITE) == 0); 2900 } 2901 } 2902 #endif 2903 } else 2904 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2905 if ((flags & PMAP_CANFAIL) == 0) 2906 panic("pmap_enter: no pv entries"); 2907 2908 if (pm != pmap_kernel()) 2909 pmap_free_l2_bucket(pm, l2b, 0); 2910 pmap_release_pmap_lock(pm); 2911 NPDEBUG(PDB_ENTER, 2912 printf("pmap_enter: ENOMEM\n")); 2913 return (ENOMEM); 2914 } 2915 2916 #ifdef MULTIPROCESSOR 2917 KASSERT(uvm_page_locked_p(pg)); 2918 #endif 2919 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2920 } 2921 } else { 2922 /* 2923 * We're mapping an unmanaged page. 2924 * These are always readable, and possibly writable, from 2925 * the get go as we don't need to track ref/mod status. 2926 */ 2927 npte |= l2pte_set_readonly(L2_S_PROTO); 2928 if (prot & VM_PROT_WRITE) 2929 npte = l2pte_set_writable(npte); 2930 2931 /* 2932 * Make sure the vector table is mapped cacheable 2933 */ 2934 if ((pm != pmap_kernel() && va == vector_page) || 2935 (flags & ARM32_MMAP_CACHEABLE)) { 2936 npte |= pte_l2_s_cache_mode; 2937 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 2938 npte |= pte_l2_s_wc_mode; 2939 } 2940 if (opg) { 2941 /* 2942 * Looks like there's an existing 'managed' mapping 2943 * at this address. 2944 */ 2945 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2946 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2947 2948 #ifdef MULTIPROCESSOR 2949 KASSERT(uvm_page_locked_p(opg)); 2950 #endif 2951 pv = pmap_remove_pv(omd, opa, pm, va); 2952 pmap_vac_me_harder(omd, opa, pm, 0); 2953 oflags = pv->pv_flags; 2954 2955 #ifdef PMAP_CACHE_VIVT 2956 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2957 if (PV_BEEN_EXECD(oflags)) 2958 pmap_idcache_wbinv_range(pm, va, 2959 PAGE_SIZE); 2960 else 2961 if (PV_BEEN_REFD(oflags)) 2962 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2963 true, (oflags & PVF_WRITE) == 0); 2964 } 2965 #endif 2966 pool_put(&pmap_pv_pool, pv); 2967 } 2968 } 2969 2970 /* 2971 * Make sure userland mappings get the right permissions 2972 */ 2973 if (pm != pmap_kernel() && va != vector_page) 2974 npte |= L2_S_PROT_U; 2975 2976 /* 2977 * Keep the stats up to date 2978 */ 2979 if (opte == 0) { 2980 l2b->l2b_occupancy++; 2981 pm->pm_stats.resident_count++; 2982 } 2983 2984 NPDEBUG(PDB_ENTER, 2985 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2986 2987 /* 2988 * If this is just a wiring change, the two PTEs will be 2989 * identical, so there's no need to update the page table. 2990 */ 2991 if (npte != opte) { 2992 bool is_cached = pmap_is_cached(pm); 2993 2994 *ptep = npte; 2995 PTE_SYNC(ptep); 2996 if (is_cached) { 2997 /* 2998 * We only need to frob the cache/tlb if this pmap 2999 * is current 3000 */ 3001 if (va != vector_page && l2pte_valid(npte)) { 3002 /* 3003 * This mapping is likely to be accessed as 3004 * soon as we return to userland. Fix up the 3005 * L1 entry to avoid taking another 3006 * page/domain fault. 3007 */ 3008 pd_entry_t *pl1pd, l1pd; 3009 3010 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3011 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3012 L1_C_PROTO; 3013 if (*pl1pd != l1pd) { 3014 *pl1pd = l1pd; 3015 PTE_SYNC(pl1pd); 3016 } 3017 } 3018 } 3019 3020 if (PV_BEEN_EXECD(oflags)) 3021 pmap_tlb_flushID_SE(pm, va); 3022 else 3023 if (PV_BEEN_REFD(oflags)) 3024 pmap_tlb_flushD_SE(pm, va); 3025 3026 NPDEBUG(PDB_ENTER, 3027 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3028 is_cached, pm->pm_cstate.cs_all)); 3029 3030 if (pg != NULL) { 3031 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3032 3033 #ifdef MULTIPROCESSOR 3034 KASSERT(uvm_page_locked_p(pg)); 3035 #endif 3036 pmap_vac_me_harder(md, pa, pm, va); 3037 } 3038 } 3039 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3040 if (pg) { 3041 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3042 3043 #ifdef MULTIPROCESSOR 3044 KASSERT(uvm_page_locked_p(pg)); 3045 #endif 3046 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3047 KASSERTMSG(arm_cache_prefer_mask == 0 || ((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0), 3048 "pg %p: attrs=%#x urw=%u krw=%u", pg, 3049 md->pvh_attrs, md->urw_mappings, md->krw_mappings); 3050 } 3051 #endif 3052 3053 pmap_release_pmap_lock(pm); 3054 3055 return (0); 3056 } 3057 3058 /* 3059 * pmap_remove() 3060 * 3061 * pmap_remove is responsible for nuking a number of mappings for a range 3062 * of virtual address space in the current pmap. To do this efficiently 3063 * is interesting, because in a number of cases a wide virtual address 3064 * range may be supplied that contains few actual mappings. So, the 3065 * optimisations are: 3066 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3067 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3068 * maybe do just a partial cache clean. This path of execution is 3069 * complicated by the fact that the cache must be flushed _before_ 3070 * the PTE is nuked, being a VAC :-) 3071 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3072 * all invalidations until pmap_update(), since pmap_remove_all() has 3073 * already flushed the cache. 3074 * 4. Maybe later fast-case a single page, but I don't think this is 3075 * going to make _that_ much difference overall. 3076 */ 3077 3078 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3079 3080 void 3081 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3082 { 3083 struct l2_bucket *l2b; 3084 vaddr_t next_bucket; 3085 pt_entry_t *ptep; 3086 u_int cleanlist_idx, total, cnt; 3087 struct { 3088 vaddr_t va; 3089 pt_entry_t *ptep; 3090 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3091 u_int mappings, is_exec, is_refd; 3092 3093 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3094 "eva=%08lx\n", pm, sva, eva)); 3095 3096 /* 3097 * we lock in the pmap => pv_head direction 3098 */ 3099 pmap_acquire_pmap_lock(pm); 3100 3101 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3102 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3103 if (pm->pm_cstate.cs_tlb == 0) 3104 pm->pm_remove_all = true; 3105 } else 3106 cleanlist_idx = 0; 3107 3108 total = 0; 3109 3110 while (sva < eva) { 3111 /* 3112 * Do one L2 bucket's worth at a time. 3113 */ 3114 next_bucket = L2_NEXT_BUCKET(sva); 3115 if (next_bucket > eva) 3116 next_bucket = eva; 3117 3118 l2b = pmap_get_l2_bucket(pm, sva); 3119 if (l2b == NULL) { 3120 sva = next_bucket; 3121 continue; 3122 } 3123 3124 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3125 3126 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3127 struct vm_page *pg; 3128 pt_entry_t pte; 3129 paddr_t pa; 3130 3131 pte = *ptep; 3132 3133 if (pte == 0) { 3134 /* Nothing here, move along */ 3135 continue; 3136 } 3137 3138 pa = l2pte_pa(pte); 3139 is_exec = 0; 3140 is_refd = 1; 3141 3142 /* 3143 * Update flags. In a number of circumstances, 3144 * we could cluster a lot of these and do a 3145 * number of sequential pages in one go. 3146 */ 3147 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3148 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3149 struct pv_entry *pv; 3150 3151 #ifdef MULTIPROCESSOR 3152 KASSERT(uvm_page_locked_p(pg)); 3153 #endif 3154 pv = pmap_remove_pv(md, pa, pm, sva); 3155 pmap_vac_me_harder(md, pa, pm, 0); 3156 if (pv != NULL) { 3157 if (pm->pm_remove_all == false) { 3158 is_exec = 3159 PV_BEEN_EXECD(pv->pv_flags); 3160 is_refd = 3161 PV_BEEN_REFD(pv->pv_flags); 3162 } 3163 pool_put(&pmap_pv_pool, pv); 3164 } 3165 } 3166 mappings++; 3167 3168 if (!l2pte_valid(pte)) { 3169 /* 3170 * Ref/Mod emulation is still active for this 3171 * mapping, therefore it is has not yet been 3172 * accessed. No need to frob the cache/tlb. 3173 */ 3174 *ptep = 0; 3175 PTE_SYNC_CURRENT(pm, ptep); 3176 continue; 3177 } 3178 3179 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3180 /* Add to the clean list. */ 3181 cleanlist[cleanlist_idx].ptep = ptep; 3182 cleanlist[cleanlist_idx].va = 3183 sva | (is_exec & 1); 3184 cleanlist_idx++; 3185 } else 3186 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3187 /* Nuke everything if needed. */ 3188 #ifdef PMAP_CACHE_VIVT 3189 pmap_idcache_wbinv_all(pm); 3190 #endif 3191 pmap_tlb_flushID(pm); 3192 3193 /* 3194 * Roll back the previous PTE list, 3195 * and zero out the current PTE. 3196 */ 3197 for (cnt = 0; 3198 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3199 *cleanlist[cnt].ptep = 0; 3200 PTE_SYNC(cleanlist[cnt].ptep); 3201 } 3202 *ptep = 0; 3203 PTE_SYNC(ptep); 3204 cleanlist_idx++; 3205 pm->pm_remove_all = true; 3206 } else { 3207 *ptep = 0; 3208 PTE_SYNC(ptep); 3209 if (pm->pm_remove_all == false) { 3210 if (is_exec) 3211 pmap_tlb_flushID_SE(pm, sva); 3212 else 3213 if (is_refd) 3214 pmap_tlb_flushD_SE(pm, sva); 3215 } 3216 } 3217 } 3218 3219 /* 3220 * Deal with any left overs 3221 */ 3222 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3223 total += cleanlist_idx; 3224 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3225 if (pm->pm_cstate.cs_all != 0) { 3226 vaddr_t clva = cleanlist[cnt].va & ~1; 3227 if (cleanlist[cnt].va & 1) { 3228 #ifdef PMAP_CACHE_VIVT 3229 pmap_idcache_wbinv_range(pm, 3230 clva, PAGE_SIZE); 3231 #endif 3232 pmap_tlb_flushID_SE(pm, clva); 3233 } else { 3234 #ifdef PMAP_CACHE_VIVT 3235 pmap_dcache_wb_range(pm, 3236 clva, PAGE_SIZE, true, 3237 false); 3238 #endif 3239 pmap_tlb_flushD_SE(pm, clva); 3240 } 3241 } 3242 *cleanlist[cnt].ptep = 0; 3243 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3244 } 3245 3246 /* 3247 * If it looks like we're removing a whole bunch 3248 * of mappings, it's faster to just write-back 3249 * the whole cache now and defer TLB flushes until 3250 * pmap_update() is called. 3251 */ 3252 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3253 cleanlist_idx = 0; 3254 else { 3255 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3256 #ifdef PMAP_CACHE_VIVT 3257 pmap_idcache_wbinv_all(pm); 3258 #endif 3259 pm->pm_remove_all = true; 3260 } 3261 } 3262 3263 pmap_free_l2_bucket(pm, l2b, mappings); 3264 pm->pm_stats.resident_count -= mappings; 3265 } 3266 3267 pmap_release_pmap_lock(pm); 3268 } 3269 3270 #ifdef PMAP_CACHE_VIPT 3271 static struct pv_entry * 3272 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3273 { 3274 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3275 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3276 struct pv_entry *pv; 3277 3278 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3279 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3280 3281 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3282 KASSERT(pv); 3283 KASSERT(pv->pv_flags & PVF_KENTRY); 3284 3285 /* 3286 * If we are removing a writeable mapping to a cached exec page, 3287 * if it's the last mapping then clear it execness other sync 3288 * the page to the icache. 3289 */ 3290 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3291 && (pv->pv_flags & PVF_WRITE) != 0) { 3292 if (SLIST_EMPTY(&md->pvh_list)) { 3293 md->pvh_attrs &= ~PVF_EXEC; 3294 PMAPCOUNT(exec_discarded_kremove); 3295 } else { 3296 pmap_syncicache_page(md, pa); 3297 PMAPCOUNT(exec_synced_kremove); 3298 } 3299 } 3300 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3301 3302 return pv; 3303 } 3304 #endif /* PMAP_CACHE_VIPT */ 3305 3306 /* 3307 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3308 * 3309 * We assume there is already sufficient KVM space available 3310 * to do this, as we can't allocate L2 descriptor tables/metadata 3311 * from here. 3312 */ 3313 void 3314 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3315 { 3316 struct l2_bucket *l2b; 3317 pt_entry_t *ptep, opte; 3318 #ifdef PMAP_CACHE_VIVT 3319 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3320 #endif 3321 #ifdef PMAP_CACHE_VIPT 3322 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3323 struct vm_page *opg; 3324 struct pv_entry *pv = NULL; 3325 #endif 3326 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3327 3328 NPDEBUG(PDB_KENTER, 3329 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3330 va, pa, prot)); 3331 3332 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3333 KDASSERT(l2b != NULL); 3334 3335 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3336 opte = *ptep; 3337 3338 if (opte == 0) { 3339 PMAPCOUNT(kenter_mappings); 3340 l2b->l2b_occupancy++; 3341 } else { 3342 PMAPCOUNT(kenter_remappings); 3343 #ifdef PMAP_CACHE_VIPT 3344 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3345 #ifdef DIAGNOSTIC 3346 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3347 #endif 3348 if (opg) { 3349 KASSERT(opg != pg); 3350 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3351 KASSERT((flags & PMAP_KMPAGE) == 0); 3352 pv = pmap_kremove_pg(opg, va); 3353 } 3354 #endif 3355 if (l2pte_valid(opte)) { 3356 #ifdef PMAP_CACHE_VIVT 3357 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3358 #endif 3359 cpu_tlb_flushD_SE(va); 3360 cpu_cpwait(); 3361 } 3362 } 3363 3364 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3365 | ((flags & PMAP_NOCACHE) ? 0 : pte_l2_s_cache_mode); 3366 PTE_SYNC(ptep); 3367 3368 if (pg) { 3369 #ifdef MULTIPROCESSOR 3370 KASSERT(uvm_page_locked_p(pg)); 3371 #endif 3372 if (flags & PMAP_KMPAGE) { 3373 KASSERT(md->urw_mappings == 0); 3374 KASSERT(md->uro_mappings == 0); 3375 KASSERT(md->krw_mappings == 0); 3376 KASSERT(md->kro_mappings == 0); 3377 #ifdef PMAP_CACHE_VIPT 3378 KASSERT(pv == NULL); 3379 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3380 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3381 /* if there is a color conflict, evict from cache. */ 3382 if (pmap_is_page_colored_p(md) 3383 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3384 PMAPCOUNT(vac_color_change); 3385 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3386 } else if (md->pvh_attrs & PVF_MULTCLR) { 3387 /* 3388 * If this page has multiple colors, expunge 3389 * them. 3390 */ 3391 PMAPCOUNT(vac_flush_lots2); 3392 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3393 } 3394 md->pvh_attrs &= PAGE_SIZE - 1; 3395 md->pvh_attrs |= PVF_KMPAGE 3396 | PVF_COLORED | PVF_DIRTY 3397 | (va & arm_cache_prefer_mask); 3398 #endif 3399 #ifdef PMAP_CACHE_VIVT 3400 md->pvh_attrs |= PVF_KMPAGE; 3401 #endif 3402 pmap_kmpages++; 3403 #ifdef PMAP_CACHE_VIPT 3404 } else { 3405 if (pv == NULL) { 3406 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3407 KASSERT(pv != NULL); 3408 } 3409 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3410 PVF_WIRED | PVF_KENTRY 3411 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3412 if ((prot & VM_PROT_WRITE) 3413 && !(md->pvh_attrs & PVF_NC)) 3414 md->pvh_attrs |= PVF_DIRTY; 3415 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3416 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3417 #endif 3418 } 3419 #ifdef PMAP_CACHE_VIPT 3420 } else { 3421 if (pv != NULL) 3422 pool_put(&pmap_pv_pool, pv); 3423 #endif 3424 } 3425 } 3426 3427 void 3428 pmap_kremove(vaddr_t va, vsize_t len) 3429 { 3430 struct l2_bucket *l2b; 3431 pt_entry_t *ptep, *sptep, opte; 3432 vaddr_t next_bucket, eva; 3433 u_int mappings; 3434 struct vm_page *opg; 3435 3436 PMAPCOUNT(kenter_unmappings); 3437 3438 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3439 va, len)); 3440 3441 eva = va + len; 3442 3443 while (va < eva) { 3444 next_bucket = L2_NEXT_BUCKET(va); 3445 if (next_bucket > eva) 3446 next_bucket = eva; 3447 3448 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3449 KDASSERT(l2b != NULL); 3450 3451 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3452 mappings = 0; 3453 3454 while (va < next_bucket) { 3455 opte = *ptep; 3456 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3457 if (opg) { 3458 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3459 3460 if (omd->pvh_attrs & PVF_KMPAGE) { 3461 KASSERT(omd->urw_mappings == 0); 3462 KASSERT(omd->uro_mappings == 0); 3463 KASSERT(omd->krw_mappings == 0); 3464 KASSERT(omd->kro_mappings == 0); 3465 omd->pvh_attrs &= ~PVF_KMPAGE; 3466 #ifdef PMAP_CACHE_VIPT 3467 omd->pvh_attrs &= ~PVF_WRITE; 3468 #endif 3469 pmap_kmpages--; 3470 #ifdef PMAP_CACHE_VIPT 3471 } else { 3472 pool_put(&pmap_pv_pool, 3473 pmap_kremove_pg(opg, va)); 3474 #endif 3475 } 3476 } 3477 if (l2pte_valid(opte)) { 3478 #ifdef PMAP_CACHE_VIVT 3479 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3480 #endif 3481 cpu_tlb_flushD_SE(va); 3482 } 3483 if (opte) { 3484 *ptep = 0; 3485 mappings++; 3486 } 3487 va += PAGE_SIZE; 3488 ptep++; 3489 } 3490 KDASSERT(mappings <= l2b->l2b_occupancy); 3491 l2b->l2b_occupancy -= mappings; 3492 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3493 } 3494 cpu_cpwait(); 3495 } 3496 3497 bool 3498 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3499 { 3500 struct l2_dtable *l2; 3501 pd_entry_t *pl1pd, l1pd; 3502 pt_entry_t *ptep, pte; 3503 paddr_t pa; 3504 u_int l1idx; 3505 3506 pmap_acquire_pmap_lock(pm); 3507 3508 l1idx = L1_IDX(va); 3509 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3510 l1pd = *pl1pd; 3511 3512 if (l1pte_section_p(l1pd)) { 3513 /* 3514 * These should only happen for pmap_kernel() 3515 */ 3516 KDASSERT(pm == pmap_kernel()); 3517 pmap_release_pmap_lock(pm); 3518 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3519 if (l1pte_supersection_p(l1pd)) { 3520 pa = (l1pd & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3521 } else 3522 #endif 3523 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3524 } else { 3525 /* 3526 * Note that we can't rely on the validity of the L1 3527 * descriptor as an indication that a mapping exists. 3528 * We have to look it up in the L2 dtable. 3529 */ 3530 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3531 3532 if (l2 == NULL || 3533 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3534 pmap_release_pmap_lock(pm); 3535 return false; 3536 } 3537 3538 ptep = &ptep[l2pte_index(va)]; 3539 pte = *ptep; 3540 pmap_release_pmap_lock(pm); 3541 3542 if (pte == 0) 3543 return false; 3544 3545 switch (pte & L2_TYPE_MASK) { 3546 case L2_TYPE_L: 3547 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3548 break; 3549 3550 default: 3551 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3552 break; 3553 } 3554 } 3555 3556 if (pap != NULL) 3557 *pap = pa; 3558 3559 return true; 3560 } 3561 3562 void 3563 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3564 { 3565 struct l2_bucket *l2b; 3566 pt_entry_t *ptep, pte; 3567 vaddr_t next_bucket; 3568 u_int flags; 3569 u_int clr_mask; 3570 int flush; 3571 3572 NPDEBUG(PDB_PROTECT, 3573 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3574 pm, sva, eva, prot)); 3575 3576 if ((prot & VM_PROT_READ) == 0) { 3577 pmap_remove(pm, sva, eva); 3578 return; 3579 } 3580 3581 if (prot & VM_PROT_WRITE) { 3582 /* 3583 * If this is a read->write transition, just ignore it and let 3584 * uvm_fault() take care of it later. 3585 */ 3586 return; 3587 } 3588 3589 pmap_acquire_pmap_lock(pm); 3590 3591 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3592 flags = 0; 3593 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3594 3595 while (sva < eva) { 3596 next_bucket = L2_NEXT_BUCKET(sva); 3597 if (next_bucket > eva) 3598 next_bucket = eva; 3599 3600 l2b = pmap_get_l2_bucket(pm, sva); 3601 if (l2b == NULL) { 3602 sva = next_bucket; 3603 continue; 3604 } 3605 3606 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3607 3608 while (sva < next_bucket) { 3609 pte = *ptep; 3610 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3611 struct vm_page *pg; 3612 u_int f; 3613 3614 #ifdef PMAP_CACHE_VIVT 3615 /* 3616 * OK, at this point, we know we're doing 3617 * write-protect operation. If the pmap is 3618 * active, write-back the page. 3619 */ 3620 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3621 false, false); 3622 #endif 3623 3624 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3625 pte = l2pte_set_readonly(pte); 3626 *ptep = pte; 3627 PTE_SYNC(ptep); 3628 3629 if (pg != NULL) { 3630 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3631 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3632 3633 #ifdef MULTIPROCESSOR 3634 KASSERT(uvm_page_locked_p(pg)); 3635 #endif 3636 f = pmap_modify_pv(md, pa, pm, sva, 3637 clr_mask, 0); 3638 pmap_vac_me_harder(md, pa, pm, sva); 3639 } else { 3640 f = PVF_REF | PVF_EXEC; 3641 } 3642 3643 if (flush >= 0) { 3644 flush++; 3645 flags |= f; 3646 } else 3647 if (PV_BEEN_EXECD(f)) 3648 pmap_tlb_flushID_SE(pm, sva); 3649 else 3650 if (PV_BEEN_REFD(f)) 3651 pmap_tlb_flushD_SE(pm, sva); 3652 } 3653 3654 sva += PAGE_SIZE; 3655 ptep++; 3656 } 3657 } 3658 3659 pmap_release_pmap_lock(pm); 3660 3661 if (flush) { 3662 if (PV_BEEN_EXECD(flags)) 3663 pmap_tlb_flushID(pm); 3664 else 3665 if (PV_BEEN_REFD(flags)) 3666 pmap_tlb_flushD(pm); 3667 } 3668 } 3669 3670 void 3671 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3672 { 3673 struct l2_bucket *l2b; 3674 pt_entry_t *ptep; 3675 vaddr_t next_bucket; 3676 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3677 3678 NPDEBUG(PDB_EXEC, 3679 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3680 pm, sva, eva)); 3681 3682 pmap_acquire_pmap_lock(pm); 3683 3684 while (sva < eva) { 3685 next_bucket = L2_NEXT_BUCKET(sva); 3686 if (next_bucket > eva) 3687 next_bucket = eva; 3688 3689 l2b = pmap_get_l2_bucket(pm, sva); 3690 if (l2b == NULL) { 3691 sva = next_bucket; 3692 continue; 3693 } 3694 3695 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3696 sva < next_bucket; 3697 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3698 if (l2pte_valid(*ptep)) { 3699 cpu_icache_sync_range(sva, 3700 min(page_size, eva - sva)); 3701 } 3702 } 3703 } 3704 3705 pmap_release_pmap_lock(pm); 3706 } 3707 3708 void 3709 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3710 { 3711 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3712 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3713 3714 NPDEBUG(PDB_PROTECT, 3715 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3716 md, pa, prot)); 3717 3718 #ifdef MULTIPROCESSOR 3719 KASSERT(uvm_page_locked_p(pg)); 3720 #endif 3721 3722 switch(prot) { 3723 case VM_PROT_READ|VM_PROT_WRITE: 3724 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3725 pmap_clearbit(md, pa, PVF_EXEC); 3726 break; 3727 #endif 3728 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3729 break; 3730 3731 case VM_PROT_READ: 3732 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3733 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3734 break; 3735 #endif 3736 case VM_PROT_READ|VM_PROT_EXECUTE: 3737 pmap_clearbit(md, pa, PVF_WRITE); 3738 break; 3739 3740 default: 3741 pmap_page_remove(md, pa); 3742 break; 3743 } 3744 } 3745 3746 /* 3747 * pmap_clear_modify: 3748 * 3749 * Clear the "modified" attribute for a page. 3750 */ 3751 bool 3752 pmap_clear_modify(struct vm_page *pg) 3753 { 3754 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3755 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3756 bool rv; 3757 3758 #ifdef MULTIPROCESSOR 3759 KASSERT(uvm_page_locked_p(pg)); 3760 #endif 3761 3762 if (md->pvh_attrs & PVF_MOD) { 3763 rv = true; 3764 #ifdef PMAP_CACHE_VIPT 3765 /* 3766 * If we are going to clear the modified bit and there are 3767 * no other modified bits set, flush the page to memory and 3768 * mark it clean. 3769 */ 3770 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3771 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3772 #endif 3773 pmap_clearbit(md, pa, PVF_MOD); 3774 } else 3775 rv = false; 3776 3777 return (rv); 3778 } 3779 3780 /* 3781 * pmap_clear_reference: 3782 * 3783 * Clear the "referenced" attribute for a page. 3784 */ 3785 bool 3786 pmap_clear_reference(struct vm_page *pg) 3787 { 3788 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3789 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3790 bool rv; 3791 3792 #ifdef MULTIPROCESSOR 3793 KASSERT(uvm_page_locked_p(pg)); 3794 #endif 3795 3796 if (md->pvh_attrs & PVF_REF) { 3797 rv = true; 3798 pmap_clearbit(md, pa, PVF_REF); 3799 } else 3800 rv = false; 3801 3802 return (rv); 3803 } 3804 3805 /* 3806 * pmap_is_modified: 3807 * 3808 * Test if a page has the "modified" attribute. 3809 */ 3810 /* See <arm/arm32/pmap.h> */ 3811 3812 /* 3813 * pmap_is_referenced: 3814 * 3815 * Test if a page has the "referenced" attribute. 3816 */ 3817 /* See <arm/arm32/pmap.h> */ 3818 3819 int 3820 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3821 { 3822 struct l2_dtable *l2; 3823 struct l2_bucket *l2b; 3824 pd_entry_t *pl1pd, l1pd; 3825 pt_entry_t *ptep, pte; 3826 paddr_t pa; 3827 u_int l1idx; 3828 int rv = 0; 3829 3830 pmap_acquire_pmap_lock(pm); 3831 3832 l1idx = L1_IDX(va); 3833 3834 /* 3835 * If there is no l2_dtable for this address, then the process 3836 * has no business accessing it. 3837 * 3838 * Note: This will catch userland processes trying to access 3839 * kernel addresses. 3840 */ 3841 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3842 if (l2 == NULL) 3843 goto out; 3844 3845 /* 3846 * Likewise if there is no L2 descriptor table 3847 */ 3848 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3849 if (l2b->l2b_kva == NULL) 3850 goto out; 3851 3852 /* 3853 * Check the PTE itself. 3854 */ 3855 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3856 pte = *ptep; 3857 if (pte == 0) 3858 goto out; 3859 3860 /* 3861 * Catch a userland access to the vector page mapped at 0x0 3862 */ 3863 if (user && (pte & L2_S_PROT_U) == 0) 3864 goto out; 3865 3866 pa = l2pte_pa(pte); 3867 3868 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3869 /* 3870 * This looks like a good candidate for "page modified" 3871 * emulation... 3872 */ 3873 struct pv_entry *pv; 3874 struct vm_page *pg; 3875 3876 /* Extract the physical address of the page */ 3877 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3878 goto out; 3879 3880 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3881 3882 /* Get the current flags for this page. */ 3883 #ifdef MULTIPROCESSOR 3884 KASSERT(uvm_page_locked_p(pg)); 3885 #endif 3886 3887 pv = pmap_find_pv(md, pm, va); 3888 if (pv == NULL) { 3889 goto out; 3890 } 3891 3892 /* 3893 * Do the flags say this page is writable? If not then it 3894 * is a genuine write fault. If yes then the write fault is 3895 * our fault as we did not reflect the write access in the 3896 * PTE. Now we know a write has occurred we can correct this 3897 * and also set the modified bit 3898 */ 3899 if ((pv->pv_flags & PVF_WRITE) == 0) { 3900 goto out; 3901 } 3902 3903 NPDEBUG(PDB_FOLLOW, 3904 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3905 pm, va, pa)); 3906 3907 md->pvh_attrs |= PVF_REF | PVF_MOD; 3908 pv->pv_flags |= PVF_REF | PVF_MOD; 3909 #ifdef PMAP_CACHE_VIPT 3910 /* 3911 * If there are cacheable mappings for this page, mark it dirty. 3912 */ 3913 if ((md->pvh_attrs & PVF_NC) == 0) 3914 md->pvh_attrs |= PVF_DIRTY; 3915 #endif 3916 3917 /* 3918 * Re-enable write permissions for the page. No need to call 3919 * pmap_vac_me_harder(), since this is just a 3920 * modified-emulation fault, and the PVF_WRITE bit isn't 3921 * changing. We've already set the cacheable bits based on 3922 * the assumption that we can write to this page. 3923 */ 3924 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3925 PTE_SYNC(ptep); 3926 rv = 1; 3927 } else 3928 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3929 /* 3930 * This looks like a good candidate for "page referenced" 3931 * emulation. 3932 */ 3933 struct pv_entry *pv; 3934 struct vm_page *pg; 3935 3936 /* Extract the physical address of the page */ 3937 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3938 goto out; 3939 3940 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3941 3942 /* Get the current flags for this page. */ 3943 #ifdef MULTIPROCESSOR 3944 KASSERT(uvm_page_locked_p(pg)); 3945 #endif 3946 3947 pv = pmap_find_pv(md, pm, va); 3948 if (pv == NULL) { 3949 goto out; 3950 } 3951 3952 md->pvh_attrs |= PVF_REF; 3953 pv->pv_flags |= PVF_REF; 3954 3955 NPDEBUG(PDB_FOLLOW, 3956 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3957 pm, va, pa)); 3958 3959 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3960 PTE_SYNC(ptep); 3961 rv = 1; 3962 } 3963 3964 /* 3965 * We know there is a valid mapping here, so simply 3966 * fix up the L1 if necessary. 3967 */ 3968 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3969 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3970 if (*pl1pd != l1pd) { 3971 *pl1pd = l1pd; 3972 PTE_SYNC(pl1pd); 3973 rv = 1; 3974 } 3975 3976 #ifdef CPU_SA110 3977 /* 3978 * There are bugs in the rev K SA110. This is a check for one 3979 * of them. 3980 */ 3981 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3982 curcpu()->ci_arm_cpurev < 3) { 3983 /* Always current pmap */ 3984 if (l2pte_valid(pte)) { 3985 extern int kernel_debug; 3986 if (kernel_debug & 1) { 3987 struct proc *p = curlwp->l_proc; 3988 printf("prefetch_abort: page is already " 3989 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3990 printf("prefetch_abort: pc=%08lx proc=%p " 3991 "process=%s\n", va, p, p->p_comm); 3992 printf("prefetch_abort: far=%08x fs=%x\n", 3993 cpu_faultaddress(), cpu_faultstatus()); 3994 } 3995 #ifdef DDB 3996 if (kernel_debug & 2) 3997 Debugger(); 3998 #endif 3999 rv = 1; 4000 } 4001 } 4002 #endif /* CPU_SA110 */ 4003 4004 /* 4005 * If 'rv == 0' at this point, it generally indicates that there is a 4006 * stale TLB entry for the faulting address. That might be due to a 4007 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4008 */ 4009 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1 4010 && pmap_needs_pte_sync == 0) { 4011 pmap_needs_pte_sync = 1; 4012 PTE_SYNC(ptep); 4013 rv = 1; 4014 } 4015 4016 #ifdef DEBUG 4017 /* 4018 * If 'rv == 0' at this point, it generally indicates that there is a 4019 * stale TLB entry for the faulting address. This happens when two or 4020 * more processes are sharing an L1. Since we don't flush the TLB on 4021 * a context switch between such processes, we can take domain faults 4022 * for mappings which exist at the same VA in both processes. EVEN IF 4023 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4024 * example. 4025 * 4026 * This is extremely likely to happen if pmap_enter() updated the L1 4027 * entry for a recently entered mapping. In this case, the TLB is 4028 * flushed for the new mapping, but there may still be TLB entries for 4029 * other mappings belonging to other processes in the 1MB range 4030 * covered by the L1 entry. 4031 * 4032 * Since 'rv == 0', we know that the L1 already contains the correct 4033 * value, so the fault must be due to a stale TLB entry. 4034 * 4035 * Since we always need to flush the TLB anyway in the case where we 4036 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4037 * stale TLB entries dynamically. 4038 * 4039 * However, the above condition can ONLY happen if the current L1 is 4040 * being shared. If it happens when the L1 is unshared, it indicates 4041 * that other parts of the pmap are not doing their job WRT managing 4042 * the TLB. 4043 */ 4044 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4045 extern int last_fault_code; 4046 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4047 pm, va, ftype); 4048 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4049 l2, l2b, ptep, pl1pd); 4050 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4051 pte, l1pd, last_fault_code); 4052 #ifdef DDB 4053 Debugger(); 4054 #endif 4055 } 4056 #endif 4057 4058 cpu_tlb_flushID_SE(va); 4059 cpu_cpwait(); 4060 4061 rv = 1; 4062 4063 out: 4064 pmap_release_pmap_lock(pm); 4065 4066 return (rv); 4067 } 4068 4069 /* 4070 * Routine: pmap_procwr 4071 * 4072 * Function: 4073 * Synchronize caches corresponding to [addr, addr+len) in p. 4074 * 4075 */ 4076 void 4077 pmap_procwr(struct proc *p, vaddr_t va, int len) 4078 { 4079 /* We only need to do anything if it is the current process. */ 4080 if (p == curproc) 4081 cpu_icache_sync_range(va, len); 4082 } 4083 4084 /* 4085 * Routine: pmap_unwire 4086 * Function: Clear the wired attribute for a map/virtual-address pair. 4087 * 4088 * In/out conditions: 4089 * The mapping must already exist in the pmap. 4090 */ 4091 void 4092 pmap_unwire(pmap_t pm, vaddr_t va) 4093 { 4094 struct l2_bucket *l2b; 4095 pt_entry_t *ptep, pte; 4096 struct vm_page *pg; 4097 paddr_t pa; 4098 4099 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4100 4101 pmap_acquire_pmap_lock(pm); 4102 4103 l2b = pmap_get_l2_bucket(pm, va); 4104 KDASSERT(l2b != NULL); 4105 4106 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4107 pte = *ptep; 4108 4109 /* Extract the physical address of the page */ 4110 pa = l2pte_pa(pte); 4111 4112 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4113 /* Update the wired bit in the pv entry for this page. */ 4114 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4115 4116 #ifdef MULTIPROCESSOR 4117 KASSERT(uvm_page_locked_p(pg)); 4118 #endif 4119 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4120 } 4121 4122 pmap_release_pmap_lock(pm); 4123 } 4124 4125 void 4126 pmap_activate(struct lwp *l) 4127 { 4128 extern int block_userspace_access; 4129 pmap_t opm, npm, rpm; 4130 uint32_t odacr, ndacr; 4131 int oldirqstate; 4132 4133 /* 4134 * If activating a non-current lwp or the current lwp is 4135 * already active, just return. 4136 */ 4137 if (l != curlwp || 4138 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4139 return; 4140 4141 npm = l->l_proc->p_vmspace->vm_map.pmap; 4142 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4143 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4144 4145 /* 4146 * If TTB and DACR are unchanged, short-circuit all the 4147 * TLB/cache management stuff. 4148 */ 4149 if (pmap_previous_active_lwp != NULL) { 4150 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4151 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4152 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4153 4154 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4155 goto all_done; 4156 } else 4157 opm = NULL; 4158 4159 PMAPCOUNT(activations); 4160 block_userspace_access = 1; 4161 4162 /* 4163 * If switching to a user vmspace which is different to the 4164 * most recent one, and the most recent one is potentially 4165 * live in the cache, we must write-back and invalidate the 4166 * entire cache. 4167 */ 4168 rpm = pmap_recent_user; 4169 4170 /* 4171 * XXXSCW: There's a corner case here which can leave turds in the cache as 4172 * reported in kern/41058. They're probably left over during tear-down and 4173 * switching away from an exiting process. Until the root cause is identified 4174 * and fixed, zap the cache when switching pmaps. This will result in a few 4175 * unnecessary cache flushes, but that's better than silently corrupting data. 4176 */ 4177 #if 0 4178 if (npm != pmap_kernel() && rpm && npm != rpm && 4179 rpm->pm_cstate.cs_cache) { 4180 rpm->pm_cstate.cs_cache = 0; 4181 #ifdef PMAP_CACHE_VIVT 4182 cpu_idcache_wbinv_all(); 4183 #endif 4184 } 4185 #else 4186 if (rpm) { 4187 rpm->pm_cstate.cs_cache = 0; 4188 if (npm == pmap_kernel()) 4189 pmap_recent_user = NULL; 4190 #ifdef PMAP_CACHE_VIVT 4191 cpu_idcache_wbinv_all(); 4192 #endif 4193 } 4194 #endif 4195 4196 /* No interrupts while we frob the TTB/DACR */ 4197 oldirqstate = disable_interrupts(IF32_bits); 4198 4199 /* 4200 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4201 * entry corresponding to 'vector_page' in the incoming L1 table 4202 * before switching to it otherwise subsequent interrupts/exceptions 4203 * (including domain faults!) will jump into hyperspace. 4204 */ 4205 if (npm->pm_pl1vec != NULL) { 4206 cpu_tlb_flushID_SE((u_int)vector_page); 4207 cpu_cpwait(); 4208 *npm->pm_pl1vec = npm->pm_l1vec; 4209 PTE_SYNC(npm->pm_pl1vec); 4210 } 4211 4212 cpu_domains(ndacr); 4213 4214 if (npm == pmap_kernel() || npm == rpm) { 4215 /* 4216 * Switching to a kernel thread, or back to the 4217 * same user vmspace as before... Simply update 4218 * the TTB (no TLB flush required) 4219 */ 4220 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4221 cpu_cpwait(); 4222 } else { 4223 /* 4224 * Otherwise, update TTB and flush TLB 4225 */ 4226 cpu_context_switch(npm->pm_l1->l1_physaddr); 4227 if (rpm != NULL) 4228 rpm->pm_cstate.cs_tlb = 0; 4229 } 4230 4231 restore_interrupts(oldirqstate); 4232 4233 block_userspace_access = 0; 4234 4235 all_done: 4236 /* 4237 * The new pmap is resident. Make sure it's marked 4238 * as resident in the cache/TLB. 4239 */ 4240 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4241 if (npm != pmap_kernel()) 4242 pmap_recent_user = npm; 4243 4244 /* The old pmap is not longer active */ 4245 if (opm != NULL) 4246 opm->pm_activated = false; 4247 4248 /* But the new one is */ 4249 npm->pm_activated = true; 4250 } 4251 4252 void 4253 pmap_deactivate(struct lwp *l) 4254 { 4255 4256 /* 4257 * If the process is exiting, make sure pmap_activate() does 4258 * a full MMU context-switch and cache flush, which we might 4259 * otherwise skip. See PR port-arm/38950. 4260 */ 4261 if (l->l_proc->p_sflag & PS_WEXIT) 4262 pmap_previous_active_lwp = NULL; 4263 4264 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4265 } 4266 4267 void 4268 pmap_update(pmap_t pm) 4269 { 4270 4271 if (pm->pm_remove_all) { 4272 /* 4273 * Finish up the pmap_remove_all() optimisation by flushing 4274 * the TLB. 4275 */ 4276 pmap_tlb_flushID(pm); 4277 pm->pm_remove_all = false; 4278 } 4279 4280 if (pmap_is_current(pm)) { 4281 /* 4282 * If we're dealing with a current userland pmap, move its L1 4283 * to the end of the LRU. 4284 */ 4285 if (pm != pmap_kernel()) 4286 pmap_use_l1(pm); 4287 4288 /* 4289 * We can assume we're done with frobbing the cache/tlb for 4290 * now. Make sure any future pmap ops don't skip cache/tlb 4291 * flushes. 4292 */ 4293 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4294 } 4295 4296 PMAPCOUNT(updates); 4297 4298 /* 4299 * make sure TLB/cache operations have completed. 4300 */ 4301 cpu_cpwait(); 4302 } 4303 4304 void 4305 pmap_remove_all(pmap_t pm) 4306 { 4307 4308 /* 4309 * The vmspace described by this pmap is about to be torn down. 4310 * Until pmap_update() is called, UVM will only make calls 4311 * to pmap_remove(). We can make life much simpler by flushing 4312 * the cache now, and deferring TLB invalidation to pmap_update(). 4313 */ 4314 #ifdef PMAP_CACHE_VIVT 4315 pmap_idcache_wbinv_all(pm); 4316 #endif 4317 pm->pm_remove_all = true; 4318 } 4319 4320 /* 4321 * Retire the given physical map from service. 4322 * Should only be called if the map contains no valid mappings. 4323 */ 4324 void 4325 pmap_destroy(pmap_t pm) 4326 { 4327 u_int count; 4328 4329 if (pm == NULL) 4330 return; 4331 4332 if (pm->pm_remove_all) { 4333 pmap_tlb_flushID(pm); 4334 pm->pm_remove_all = false; 4335 } 4336 4337 /* 4338 * Drop reference count 4339 */ 4340 mutex_enter(pm->pm_lock); 4341 count = --pm->pm_obj.uo_refs; 4342 mutex_exit(pm->pm_lock); 4343 if (count > 0) { 4344 if (pmap_is_current(pm)) { 4345 if (pm != pmap_kernel()) 4346 pmap_use_l1(pm); 4347 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4348 } 4349 return; 4350 } 4351 4352 /* 4353 * reference count is zero, free pmap resources and then free pmap. 4354 */ 4355 4356 if (vector_page < KERNEL_BASE) { 4357 KDASSERT(!pmap_is_current(pm)); 4358 4359 /* Remove the vector page mapping */ 4360 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4361 pmap_update(pm); 4362 } 4363 4364 LIST_REMOVE(pm, pm_list); 4365 4366 pmap_free_l1(pm); 4367 4368 if (pmap_recent_user == pm) 4369 pmap_recent_user = NULL; 4370 4371 uvm_obj_destroy(&pm->pm_obj, false); 4372 mutex_destroy(&pm->pm_obj_lock); 4373 pool_cache_put(&pmap_cache, pm); 4374 } 4375 4376 4377 /* 4378 * void pmap_reference(pmap_t pm) 4379 * 4380 * Add a reference to the specified pmap. 4381 */ 4382 void 4383 pmap_reference(pmap_t pm) 4384 { 4385 4386 if (pm == NULL) 4387 return; 4388 4389 pmap_use_l1(pm); 4390 4391 mutex_enter(pm->pm_lock); 4392 pm->pm_obj.uo_refs++; 4393 mutex_exit(pm->pm_lock); 4394 } 4395 4396 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4397 4398 static struct evcnt pmap_prefer_nochange_ev = 4399 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4400 static struct evcnt pmap_prefer_change_ev = 4401 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4402 4403 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4404 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4405 4406 void 4407 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4408 { 4409 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4410 vaddr_t va = *vap; 4411 vaddr_t diff = (hint - va) & mask; 4412 if (diff == 0) { 4413 pmap_prefer_nochange_ev.ev_count++; 4414 } else { 4415 pmap_prefer_change_ev.ev_count++; 4416 if (__predict_false(td)) 4417 va -= mask + 1; 4418 *vap = va + diff; 4419 } 4420 } 4421 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4422 4423 /* 4424 * pmap_zero_page() 4425 * 4426 * Zero a given physical page by mapping it at a page hook point. 4427 * In doing the zero page op, the page we zero is mapped cachable, as with 4428 * StrongARM accesses to non-cached pages are non-burst making writing 4429 * _any_ bulk data very slow. 4430 */ 4431 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4432 void 4433 pmap_zero_page_generic(paddr_t phys) 4434 { 4435 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4436 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4437 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4438 #endif 4439 #if defined(PMAP_CACHE_VIPT) 4440 /* Choose the last page color it had, if any */ 4441 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4442 #else 4443 const vsize_t va_offset = 0; 4444 #endif 4445 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 4446 /* 4447 * Is this page mapped at its natural color? 4448 * If we have all of memory mapped, then just convert PA to VA. 4449 */ 4450 const bool okcolor = va_offset == (phys & arm_cache_prefer_mask); 4451 const vaddr_t vdstp = KERNEL_BASE + (phys - physical_start); 4452 #else 4453 const bool okcolor = false; 4454 const vaddr_t vdstp = cdstp + va_offset; 4455 #endif 4456 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4457 4458 4459 #ifdef DEBUG 4460 if (!SLIST_EMPTY(&md->pvh_list)) 4461 panic("pmap_zero_page: page has mappings"); 4462 #endif 4463 4464 KDASSERT((phys & PGOFSET) == 0); 4465 4466 if (!okcolor) { 4467 /* 4468 * Hook in the page, zero it, and purge the cache for that 4469 * zeroed page. Invalidate the TLB as needed. 4470 */ 4471 *ptep = L2_S_PROTO | phys | 4472 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4473 PTE_SYNC(ptep); 4474 cpu_tlb_flushD_SE(cdstp + va_offset); 4475 cpu_cpwait(); 4476 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 4477 /* 4478 * If we are direct-mapped and our color isn't ok, then before 4479 * we bzero the page invalidate its contents from the cache and 4480 * reset the color to its natural color. 4481 */ 4482 cpu_dcache_inv_range(cdstp + va_offset, PAGE_SIZE); 4483 md->pvh_attrs &= ~arm_cache_prefer_mask; 4484 md->pvh_attrs |= (phys & arm_cache_prefer_mask); 4485 #endif 4486 } 4487 bzero_page(vdstp); 4488 if (!okcolor) { 4489 /* 4490 * Unmap the page. 4491 */ 4492 *ptep = 0; 4493 PTE_SYNC(ptep); 4494 cpu_tlb_flushD_SE(cdstp + va_offset); 4495 #ifdef PMAP_CACHE_VIVT 4496 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4497 #endif 4498 } 4499 #ifdef PMAP_CACHE_VIPT 4500 /* 4501 * This page is now cache resident so it now has a page color. 4502 * Any contents have been obliterated so clear the EXEC flag. 4503 */ 4504 if (!pmap_is_page_colored_p(md)) { 4505 PMAPCOUNT(vac_color_new); 4506 md->pvh_attrs |= PVF_COLORED; 4507 } 4508 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4509 md->pvh_attrs &= ~PVF_EXEC; 4510 PMAPCOUNT(exec_discarded_zero); 4511 } 4512 md->pvh_attrs |= PVF_DIRTY; 4513 #endif 4514 } 4515 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4516 4517 #if ARM_MMU_XSCALE == 1 4518 void 4519 pmap_zero_page_xscale(paddr_t phys) 4520 { 4521 #ifdef DEBUG 4522 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4523 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4524 4525 if (!SLIST_EMPTY(&md->pvh_list)) 4526 panic("pmap_zero_page: page has mappings"); 4527 #endif 4528 4529 KDASSERT((phys & PGOFSET) == 0); 4530 4531 /* 4532 * Hook in the page, zero it, and purge the cache for that 4533 * zeroed page. Invalidate the TLB as needed. 4534 */ 4535 *cdst_pte = L2_S_PROTO | phys | 4536 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4537 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4538 PTE_SYNC(cdst_pte); 4539 cpu_tlb_flushD_SE(cdstp); 4540 cpu_cpwait(); 4541 bzero_page(cdstp); 4542 xscale_cache_clean_minidata(); 4543 } 4544 #endif /* ARM_MMU_XSCALE == 1 */ 4545 4546 /* pmap_pageidlezero() 4547 * 4548 * The same as above, except that we assume that the page is not 4549 * mapped. This means we never have to flush the cache first. Called 4550 * from the idle loop. 4551 */ 4552 bool 4553 pmap_pageidlezero(paddr_t phys) 4554 { 4555 unsigned int i; 4556 int *ptr; 4557 bool rv = true; 4558 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4559 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4560 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4561 #endif 4562 #ifdef PMAP_CACHE_VIPT 4563 /* Choose the last page color it had, if any */ 4564 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4565 #else 4566 const vsize_t va_offset = 0; 4567 #endif 4568 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4569 4570 4571 #ifdef DEBUG 4572 if (!SLIST_EMPTY(&md->pvh_list)) 4573 panic("pmap_pageidlezero: page has mappings"); 4574 #endif 4575 4576 KDASSERT((phys & PGOFSET) == 0); 4577 4578 /* 4579 * Hook in the page, zero it, and purge the cache for that 4580 * zeroed page. Invalidate the TLB as needed. 4581 */ 4582 *ptep = L2_S_PROTO | phys | 4583 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4584 PTE_SYNC(ptep); 4585 cpu_tlb_flushD_SE(cdstp + va_offset); 4586 cpu_cpwait(); 4587 4588 for (i = 0, ptr = (int *)(cdstp + va_offset); 4589 i < (PAGE_SIZE / sizeof(int)); i++) { 4590 if (sched_curcpu_runnable_p() != 0) { 4591 /* 4592 * A process has become ready. Abort now, 4593 * so we don't keep it waiting while we 4594 * do slow memory access to finish this 4595 * page. 4596 */ 4597 rv = false; 4598 break; 4599 } 4600 *ptr++ = 0; 4601 } 4602 4603 #ifdef PMAP_CACHE_VIVT 4604 if (rv) 4605 /* 4606 * if we aborted we'll rezero this page again later so don't 4607 * purge it unless we finished it 4608 */ 4609 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4610 #elif defined(PMAP_CACHE_VIPT) 4611 /* 4612 * This page is now cache resident so it now has a page color. 4613 * Any contents have been obliterated so clear the EXEC flag. 4614 */ 4615 if (!pmap_is_page_colored_p(md)) { 4616 PMAPCOUNT(vac_color_new); 4617 md->pvh_attrs |= PVF_COLORED; 4618 } 4619 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4620 md->pvh_attrs &= ~PVF_EXEC; 4621 PMAPCOUNT(exec_discarded_zero); 4622 } 4623 #endif 4624 /* 4625 * Unmap the page. 4626 */ 4627 *ptep = 0; 4628 PTE_SYNC(ptep); 4629 cpu_tlb_flushD_SE(cdstp + va_offset); 4630 4631 return (rv); 4632 } 4633 4634 /* 4635 * pmap_copy_page() 4636 * 4637 * Copy one physical page into another, by mapping the pages into 4638 * hook points. The same comment regarding cachability as in 4639 * pmap_zero_page also applies here. 4640 */ 4641 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4642 void 4643 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4644 { 4645 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4646 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4647 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4648 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4649 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4650 #endif 4651 #ifdef PMAP_CACHE_VIPT 4652 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4653 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4654 #else 4655 const vsize_t src_va_offset = 0; 4656 const vsize_t dst_va_offset = 0; 4657 #endif 4658 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 4659 /* 4660 * Is this page mapped at its natural color? 4661 * If we have all of memory mapped, then just convert PA to VA. 4662 */ 4663 const bool src_okcolor = src_va_offset == (src & arm_cache_prefer_mask); 4664 const bool dst_okcolor = dst_va_offset == (dst & arm_cache_prefer_mask); 4665 const vaddr_t vsrcp = src_okcolor 4666 ? KERNEL_BASE + (src - physical_start) 4667 : csrcp + src_va_offset; 4668 const vaddr_t vdstp = KERNEL_BASE + (dst - physical_start); 4669 #else 4670 const bool src_okcolor = false; 4671 const bool dst_okcolor = false; 4672 const vaddr_t vsrcp = csrcp + va_offset; 4673 const vaddr_t vdstp = cdstp + va_offset; 4674 #endif 4675 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4676 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4677 4678 #ifdef DEBUG 4679 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4680 panic("pmap_copy_page: dst page has mappings"); 4681 #endif 4682 4683 #ifdef PMAP_CACHE_VIPT 4684 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4685 #endif 4686 KDASSERT((src & PGOFSET) == 0); 4687 KDASSERT((dst & PGOFSET) == 0); 4688 4689 /* 4690 * Clean the source page. Hold the source page's lock for 4691 * the duration of the copy so that no other mappings can 4692 * be created while we have a potentially aliased mapping. 4693 */ 4694 #ifdef MULTIPROCESSOR 4695 KASSERT(uvm_page_locked_p(src_pg)); 4696 #endif 4697 #ifdef PMAP_CACHE_VIVT 4698 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4699 #endif 4700 4701 /* 4702 * Map the pages into the page hook points, copy them, and purge 4703 * the cache for the appropriate page. Invalidate the TLB 4704 * as required. 4705 */ 4706 if (!src_okcolor) { 4707 *src_ptep = L2_S_PROTO 4708 | src 4709 #ifdef PMAP_CACHE_VIPT 4710 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4711 #endif 4712 #ifdef PMAP_CACHE_VIVT 4713 | pte_l2_s_cache_mode 4714 #endif 4715 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4716 PTE_SYNC(src_ptep); 4717 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4718 cpu_cpwait(); 4719 } 4720 if (!dst_okcolor) { 4721 *dst_ptep = L2_S_PROTO | dst | 4722 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4723 PTE_SYNC(dst_ptep); 4724 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4725 cpu_cpwait(); 4726 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 4727 /* 4728 * If we are direct-mapped and our color isn't ok, then before 4729 * we bcopy to the new page invalidate its contents from the 4730 * cache and reset its color to its natural color. 4731 */ 4732 cpu_dcache_inv_range(cdstp + dst_va_offset, PAGE_SIZE); 4733 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 4734 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 4735 #endif 4736 } 4737 bcopy_page(vsrcp, vdstp); 4738 #ifdef PMAP_CACHE_VIVT 4739 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 4740 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 4741 #endif 4742 /* 4743 * Unmap the pages. 4744 */ 4745 if (!src_okcolor) { 4746 *src_ptep = 0; 4747 PTE_SYNC(src_ptep); 4748 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4749 cpu_cpwait(); 4750 } 4751 if (!dst_okcolor) { 4752 *dst_ptep = 0; 4753 PTE_SYNC(dst_ptep); 4754 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4755 cpu_cpwait(); 4756 } 4757 #ifdef PMAP_CACHE_VIPT 4758 /* 4759 * Now that the destination page is in the cache, mark it as colored. 4760 * If this was an exec page, discard it. 4761 */ 4762 if (!pmap_is_page_colored_p(dst_md)) { 4763 PMAPCOUNT(vac_color_new); 4764 dst_md->pvh_attrs |= PVF_COLORED; 4765 } 4766 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4767 dst_md->pvh_attrs &= ~PVF_EXEC; 4768 PMAPCOUNT(exec_discarded_copy); 4769 } 4770 dst_md->pvh_attrs |= PVF_DIRTY; 4771 #endif 4772 } 4773 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4774 4775 #if ARM_MMU_XSCALE == 1 4776 void 4777 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4778 { 4779 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4780 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4781 #ifdef DEBUG 4782 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4783 4784 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4785 panic("pmap_copy_page: dst page has mappings"); 4786 #endif 4787 4788 KDASSERT((src & PGOFSET) == 0); 4789 KDASSERT((dst & PGOFSET) == 0); 4790 4791 /* 4792 * Clean the source page. Hold the source page's lock for 4793 * the duration of the copy so that no other mappings can 4794 * be created while we have a potentially aliased mapping. 4795 */ 4796 #ifdef MULTIPROCESSOR 4797 KASSERT(uvm_page_locked_p(src_pg)); 4798 #endif 4799 #ifdef PMAP_CACHE_VIVT 4800 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4801 #endif 4802 4803 /* 4804 * Map the pages into the page hook points, copy them, and purge 4805 * the cache for the appropriate page. Invalidate the TLB 4806 * as required. 4807 */ 4808 *csrc_pte = L2_S_PROTO | src | 4809 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4810 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4811 PTE_SYNC(csrc_pte); 4812 *cdst_pte = L2_S_PROTO | dst | 4813 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4814 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4815 PTE_SYNC(cdst_pte); 4816 cpu_tlb_flushD_SE(csrcp); 4817 cpu_tlb_flushD_SE(cdstp); 4818 cpu_cpwait(); 4819 bcopy_page(csrcp, cdstp); 4820 xscale_cache_clean_minidata(); 4821 } 4822 #endif /* ARM_MMU_XSCALE == 1 */ 4823 4824 /* 4825 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4826 * 4827 * Return the start and end addresses of the kernel's virtual space. 4828 * These values are setup in pmap_bootstrap and are updated as pages 4829 * are allocated. 4830 */ 4831 void 4832 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4833 { 4834 *start = virtual_avail; 4835 *end = virtual_end; 4836 } 4837 4838 /* 4839 * Helper function for pmap_grow_l2_bucket() 4840 */ 4841 static inline int 4842 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4843 { 4844 struct l2_bucket *l2b; 4845 pt_entry_t *ptep; 4846 paddr_t pa; 4847 4848 if (uvm.page_init_done == false) { 4849 #ifdef PMAP_STEAL_MEMORY 4850 pv_addr_t pv; 4851 pmap_boot_pagealloc(PAGE_SIZE, 4852 #ifdef PMAP_CACHE_VIPT 4853 arm_cache_prefer_mask, 4854 va & arm_cache_prefer_mask, 4855 #else 4856 0, 0, 4857 #endif 4858 &pv); 4859 pa = pv.pv_pa; 4860 #else 4861 if (uvm_page_physget(&pa) == false) 4862 return (1); 4863 #endif /* PMAP_STEAL_MEMORY */ 4864 } else { 4865 struct vm_page *pg; 4866 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4867 if (pg == NULL) 4868 return (1); 4869 pa = VM_PAGE_TO_PHYS(pg); 4870 #ifdef PMAP_CACHE_VIPT 4871 #ifdef DIAGNOSTIC 4872 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4873 #endif 4874 /* 4875 * This new page must not have any mappings. Enter it via 4876 * pmap_kenter_pa and let that routine do the hard work. 4877 */ 4878 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4879 pmap_kenter_pa(va, pa, 4880 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4881 #endif 4882 } 4883 4884 if (pap) 4885 *pap = pa; 4886 4887 PMAPCOUNT(pt_mappings); 4888 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4889 KDASSERT(l2b != NULL); 4890 4891 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4892 *ptep = L2_S_PROTO | pa | cache_mode | 4893 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4894 PTE_SYNC(ptep); 4895 memset((void *)va, 0, PAGE_SIZE); 4896 return (0); 4897 } 4898 4899 /* 4900 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4901 * used by pmap_growkernel(). 4902 */ 4903 static inline struct l2_bucket * 4904 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4905 { 4906 struct l2_dtable *l2; 4907 struct l2_bucket *l2b; 4908 u_short l1idx; 4909 vaddr_t nva; 4910 4911 l1idx = L1_IDX(va); 4912 4913 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4914 /* 4915 * No mapping at this address, as there is 4916 * no entry in the L1 table. 4917 * Need to allocate a new l2_dtable. 4918 */ 4919 nva = pmap_kernel_l2dtable_kva; 4920 if ((nva & PGOFSET) == 0) { 4921 /* 4922 * Need to allocate a backing page 4923 */ 4924 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4925 return (NULL); 4926 } 4927 4928 l2 = (struct l2_dtable *)nva; 4929 nva += sizeof(struct l2_dtable); 4930 4931 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4932 /* 4933 * The new l2_dtable straddles a page boundary. 4934 * Map in another page to cover it. 4935 */ 4936 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4937 return (NULL); 4938 } 4939 4940 pmap_kernel_l2dtable_kva = nva; 4941 4942 /* 4943 * Link it into the parent pmap 4944 */ 4945 pm->pm_l2[L2_IDX(l1idx)] = l2; 4946 } 4947 4948 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4949 4950 /* 4951 * Fetch pointer to the L2 page table associated with the address. 4952 */ 4953 if (l2b->l2b_kva == NULL) { 4954 pt_entry_t *ptep; 4955 4956 /* 4957 * No L2 page table has been allocated. Chances are, this 4958 * is because we just allocated the l2_dtable, above. 4959 */ 4960 nva = pmap_kernel_l2ptp_kva; 4961 ptep = (pt_entry_t *)nva; 4962 if ((nva & PGOFSET) == 0) { 4963 /* 4964 * Need to allocate a backing page 4965 */ 4966 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4967 &pmap_kernel_l2ptp_phys)) 4968 return (NULL); 4969 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4970 } 4971 4972 l2->l2_occupancy++; 4973 l2b->l2b_kva = ptep; 4974 l2b->l2b_l1idx = l1idx; 4975 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4976 4977 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4978 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4979 } 4980 4981 return (l2b); 4982 } 4983 4984 vaddr_t 4985 pmap_growkernel(vaddr_t maxkvaddr) 4986 { 4987 pmap_t kpm = pmap_kernel(); 4988 struct l1_ttable *l1; 4989 struct l2_bucket *l2b; 4990 pd_entry_t *pl1pd; 4991 int s; 4992 4993 if (maxkvaddr <= pmap_curmaxkvaddr) 4994 goto out; /* we are OK */ 4995 4996 NPDEBUG(PDB_GROWKERN, 4997 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4998 pmap_curmaxkvaddr, maxkvaddr)); 4999 5000 KDASSERT(maxkvaddr <= virtual_end); 5001 5002 /* 5003 * whoops! we need to add kernel PTPs 5004 */ 5005 5006 s = splhigh(); /* to be safe */ 5007 mutex_enter(kpm->pm_lock); 5008 5009 /* Map 1MB at a time */ 5010 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 5011 5012 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5013 KDASSERT(l2b != NULL); 5014 5015 /* Distribute new L1 entry to all other L1s */ 5016 SLIST_FOREACH(l1, &l1_list, l1_link) { 5017 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 5018 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 5019 L1_C_PROTO; 5020 PTE_SYNC(pl1pd); 5021 } 5022 } 5023 5024 /* 5025 * flush out the cache, expensive but growkernel will happen so 5026 * rarely 5027 */ 5028 cpu_dcache_wbinv_all(); 5029 cpu_tlb_flushD(); 5030 cpu_cpwait(); 5031 5032 mutex_exit(kpm->pm_lock); 5033 splx(s); 5034 5035 out: 5036 return (pmap_curmaxkvaddr); 5037 } 5038 5039 /************************ Utility routines ****************************/ 5040 5041 /* 5042 * vector_page_setprot: 5043 * 5044 * Manipulate the protection of the vector page. 5045 */ 5046 void 5047 vector_page_setprot(int prot) 5048 { 5049 struct l2_bucket *l2b; 5050 pt_entry_t *ptep; 5051 5052 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5053 KDASSERT(l2b != NULL); 5054 5055 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5056 5057 *ptep = (*ptep & ~L2_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 5058 PTE_SYNC(ptep); 5059 cpu_tlb_flushD_SE(vector_page); 5060 cpu_cpwait(); 5061 } 5062 5063 /* 5064 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5065 * Returns true if the mapping exists, else false. 5066 * 5067 * NOTE: This function is only used by a couple of arm-specific modules. 5068 * It is not safe to take any pmap locks here, since we could be right 5069 * in the middle of debugging the pmap anyway... 5070 * 5071 * It is possible for this routine to return false even though a valid 5072 * mapping does exist. This is because we don't lock, so the metadata 5073 * state may be inconsistent. 5074 * 5075 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5076 * a "section" mapping. 5077 */ 5078 bool 5079 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5080 { 5081 struct l2_dtable *l2; 5082 pd_entry_t *pl1pd, l1pd; 5083 pt_entry_t *ptep; 5084 u_short l1idx; 5085 5086 if (pm->pm_l1 == NULL) 5087 return false; 5088 5089 l1idx = L1_IDX(va); 5090 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5091 l1pd = *pl1pd; 5092 5093 if (l1pte_section_p(l1pd)) { 5094 *ptp = NULL; 5095 return true; 5096 } 5097 5098 if (pm->pm_l2 == NULL) 5099 return false; 5100 5101 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5102 5103 if (l2 == NULL || 5104 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5105 return false; 5106 } 5107 5108 *ptp = &ptep[l2pte_index(va)]; 5109 return true; 5110 } 5111 5112 bool 5113 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5114 { 5115 u_short l1idx; 5116 5117 if (pm->pm_l1 == NULL) 5118 return false; 5119 5120 l1idx = L1_IDX(va); 5121 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5122 5123 return true; 5124 } 5125 5126 /************************ Bootstrapping routines ****************************/ 5127 5128 static void 5129 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5130 { 5131 int i; 5132 5133 l1->l1_kva = l1pt; 5134 l1->l1_domain_use_count = 0; 5135 l1->l1_domain_first = 0; 5136 5137 for (i = 0; i < PMAP_DOMAINS; i++) 5138 l1->l1_domain_free[i] = i + 1; 5139 5140 /* 5141 * Copy the kernel's L1 entries to each new L1. 5142 */ 5143 if (pmap_initialized) 5144 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5145 5146 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5147 &l1->l1_physaddr) == false) 5148 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5149 5150 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5151 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5152 } 5153 5154 /* 5155 * pmap_bootstrap() is called from the board-specific initarm() routine 5156 * once the kernel L1/L2 descriptors tables have been set up. 5157 * 5158 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5159 * spread over a number of disparate files/functions. 5160 * 5161 * We are passed the following parameters 5162 * - kernel_l1pt 5163 * This is a pointer to the base of the kernel's L1 translation table. 5164 * - vstart 5165 * 1MB-aligned start of managed kernel virtual memory. 5166 * - vend 5167 * 1MB-aligned end of managed kernel virtual memory. 5168 * 5169 * We use the first parameter to build the metadata (struct l1_ttable and 5170 * struct l2_dtable) necessary to track kernel mappings. 5171 */ 5172 #define PMAP_STATIC_L2_SIZE 16 5173 void 5174 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5175 { 5176 static struct l1_ttable static_l1; 5177 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5178 struct l1_ttable *l1 = &static_l1; 5179 struct l2_dtable *l2; 5180 struct l2_bucket *l2b; 5181 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5182 pmap_t pm = pmap_kernel(); 5183 pd_entry_t pde; 5184 pt_entry_t *ptep; 5185 paddr_t pa; 5186 vaddr_t va; 5187 vsize_t size; 5188 int nptes, l1idx, l2idx, l2next = 0; 5189 5190 /* 5191 * Initialise the kernel pmap object 5192 */ 5193 pm->pm_l1 = l1; 5194 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5195 pm->pm_activated = true; 5196 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5197 5198 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5199 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5200 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5201 5202 /* 5203 * Scan the L1 translation table created by initarm() and create 5204 * the required metadata for all valid mappings found in it. 5205 */ 5206 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5207 pde = l1pt[l1idx]; 5208 5209 /* 5210 * We're only interested in Coarse mappings. 5211 * pmap_extract() can deal with section mappings without 5212 * recourse to checking L2 metadata. 5213 */ 5214 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5215 continue; 5216 5217 /* 5218 * Lookup the KVA of this L2 descriptor table 5219 */ 5220 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5221 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5222 if (ptep == NULL) { 5223 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5224 (u_int)l1idx << L1_S_SHIFT, pa); 5225 } 5226 5227 /* 5228 * Fetch the associated L2 metadata structure. 5229 * Allocate a new one if necessary. 5230 */ 5231 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5232 if (l2next == PMAP_STATIC_L2_SIZE) 5233 panic("pmap_bootstrap: out of static L2s"); 5234 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5235 } 5236 5237 /* 5238 * One more L1 slot tracked... 5239 */ 5240 l2->l2_occupancy++; 5241 5242 /* 5243 * Fill in the details of the L2 descriptor in the 5244 * appropriate bucket. 5245 */ 5246 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5247 l2b->l2b_kva = ptep; 5248 l2b->l2b_phys = pa; 5249 l2b->l2b_l1idx = l1idx; 5250 5251 /* 5252 * Establish an initial occupancy count for this descriptor 5253 */ 5254 for (l2idx = 0; 5255 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5256 l2idx++) { 5257 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5258 l2b->l2b_occupancy++; 5259 } 5260 } 5261 5262 /* 5263 * Make sure the descriptor itself has the correct cache mode. 5264 * If not, fix it, but whine about the problem. Port-meisters 5265 * should consider this a clue to fix up their initarm() 5266 * function. :) 5267 */ 5268 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5269 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5270 "L2 pte @ %p\n", ptep); 5271 } 5272 } 5273 5274 /* 5275 * Ensure the primary (kernel) L1 has the correct cache mode for 5276 * a page table. Bitch if it is not correctly set. 5277 */ 5278 for (va = (vaddr_t)l1pt; 5279 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5280 if (pmap_set_pt_cache_mode(l1pt, va)) 5281 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5282 "primary L1 @ 0x%lx\n", va); 5283 } 5284 5285 cpu_dcache_wbinv_all(); 5286 cpu_tlb_flushID(); 5287 cpu_cpwait(); 5288 5289 /* 5290 * now we allocate the "special" VAs which are used for tmp mappings 5291 * by the pmap (and other modules). we allocate the VAs by advancing 5292 * virtual_avail (note that there are no pages mapped at these VAs). 5293 * 5294 * Managed KVM space start from wherever initarm() tells us. 5295 */ 5296 virtual_avail = vstart; 5297 virtual_end = vend; 5298 5299 #ifdef PMAP_CACHE_VIPT 5300 /* 5301 * If we have a VIPT cache, we need one page/pte per possible alias 5302 * page so we won't violate cache aliasing rules. 5303 */ 5304 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5305 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5306 #else 5307 nptes = 1; 5308 #endif 5309 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5310 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5311 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5312 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5313 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5314 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5315 (void *)&msgbufaddr, NULL); 5316 5317 /* 5318 * Allocate a range of kernel virtual address space to be used 5319 * for L2 descriptor tables and metadata allocation in 5320 * pmap_growkernel(). 5321 */ 5322 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5323 pmap_alloc_specials(&virtual_avail, 5324 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5325 &pmap_kernel_l2ptp_kva, NULL); 5326 5327 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5328 pmap_alloc_specials(&virtual_avail, 5329 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5330 &pmap_kernel_l2dtable_kva, NULL); 5331 5332 /* 5333 * init the static-global locks and global pmap list. 5334 */ 5335 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 5336 5337 /* 5338 * We can now initialise the first L1's metadata. 5339 */ 5340 SLIST_INIT(&l1_list); 5341 TAILQ_INIT(&l1_lru_list); 5342 pmap_init_l1(l1, l1pt); 5343 5344 /* Set up vector page L1 details, if necessary */ 5345 if (vector_page < KERNEL_BASE) { 5346 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5347 l2b = pmap_get_l2_bucket(pm, vector_page); 5348 KDASSERT(l2b != NULL); 5349 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5350 L1_C_DOM(pm->pm_domain); 5351 } else 5352 pm->pm_pl1vec = NULL; 5353 5354 /* 5355 * Initialize the pmap cache 5356 */ 5357 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5358 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5359 LIST_INIT(&pmap_pmaps); 5360 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5361 5362 /* 5363 * Initialize the pv pool. 5364 */ 5365 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5366 &pmap_bootstrap_pv_allocator, IPL_NONE); 5367 5368 /* 5369 * Initialize the L2 dtable pool and cache. 5370 */ 5371 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5372 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5373 5374 /* 5375 * Initialise the L2 descriptor table pool and cache 5376 */ 5377 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5378 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5379 pmap_l2ptp_ctor, NULL, NULL); 5380 5381 cpu_dcache_wbinv_all(); 5382 } 5383 5384 static int 5385 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5386 { 5387 pd_entry_t *pdep, pde; 5388 pt_entry_t *ptep, pte; 5389 vaddr_t pa; 5390 int rv = 0; 5391 5392 /* 5393 * Make sure the descriptor itself has the correct cache mode 5394 */ 5395 pdep = &kl1[L1_IDX(va)]; 5396 pde = *pdep; 5397 5398 if (l1pte_section_p(pde)) { 5399 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 5400 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5401 *pdep = (pde & ~L1_S_CACHE_MASK) | 5402 pte_l1_s_cache_mode_pt; 5403 PTE_SYNC(pdep); 5404 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5405 rv = 1; 5406 } 5407 } else { 5408 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5409 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5410 if (ptep == NULL) 5411 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5412 5413 ptep = &ptep[l2pte_index(va)]; 5414 pte = *ptep; 5415 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5416 *ptep = (pte & ~L2_S_CACHE_MASK) | 5417 pte_l2_s_cache_mode_pt; 5418 PTE_SYNC(ptep); 5419 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5420 rv = 1; 5421 } 5422 } 5423 5424 return (rv); 5425 } 5426 5427 static void 5428 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5429 { 5430 vaddr_t va = *availp; 5431 struct l2_bucket *l2b; 5432 5433 if (ptep) { 5434 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5435 if (l2b == NULL) 5436 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5437 5438 if (ptep) 5439 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5440 } 5441 5442 *vap = va; 5443 *availp = va + (PAGE_SIZE * pages); 5444 } 5445 5446 void 5447 pmap_init(void) 5448 { 5449 5450 /* 5451 * Set the available memory vars - These do not map to real memory 5452 * addresses and cannot as the physical memory is fragmented. 5453 * They are used by ps for %mem calculations. 5454 * One could argue whether this should be the entire memory or just 5455 * the memory that is useable in a user process. 5456 */ 5457 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5458 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5459 5460 /* 5461 * Now we need to free enough pv_entry structures to allow us to get 5462 * the kmem_map/kmem_object allocated and inited (done after this 5463 * function is finished). to do this we allocate one bootstrap page out 5464 * of kernel_map and use it to provide an initial pool of pv_entry 5465 * structures. we never free this page. 5466 */ 5467 pool_setlowat(&pmap_pv_pool, 5468 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5469 5470 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5471 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5472 UVM_KMF_WIRED|UVM_KMF_ZERO); 5473 5474 pmap_initialized = true; 5475 } 5476 5477 static vaddr_t last_bootstrap_page = 0; 5478 static void *free_bootstrap_pages = NULL; 5479 5480 static void * 5481 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5482 { 5483 extern void *pool_page_alloc(struct pool *, int); 5484 vaddr_t new_page; 5485 void *rv; 5486 5487 if (pmap_initialized) 5488 return (pool_page_alloc(pp, flags)); 5489 5490 if (free_bootstrap_pages) { 5491 rv = free_bootstrap_pages; 5492 free_bootstrap_pages = *((void **)rv); 5493 return (rv); 5494 } 5495 5496 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5497 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5498 5499 KASSERT(new_page > last_bootstrap_page); 5500 last_bootstrap_page = new_page; 5501 return ((void *)new_page); 5502 } 5503 5504 static void 5505 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5506 { 5507 extern void pool_page_free(struct pool *, void *); 5508 5509 if ((vaddr_t)v <= last_bootstrap_page) { 5510 *((void **)v) = free_bootstrap_pages; 5511 free_bootstrap_pages = v; 5512 return; 5513 } 5514 5515 if (pmap_initialized) { 5516 pool_page_free(pp, v); 5517 return; 5518 } 5519 } 5520 5521 /* 5522 * pmap_postinit() 5523 * 5524 * This routine is called after the vm and kmem subsystems have been 5525 * initialised. This allows the pmap code to perform any initialisation 5526 * that can only be done one the memory allocation is in place. 5527 */ 5528 void 5529 pmap_postinit(void) 5530 { 5531 extern paddr_t physical_start, physical_end; 5532 struct l2_bucket *l2b; 5533 struct l1_ttable *l1; 5534 struct pglist plist; 5535 struct vm_page *m; 5536 pd_entry_t *pl1pt; 5537 pt_entry_t *ptep, pte; 5538 vaddr_t va, eva; 5539 u_int loop, needed; 5540 int error; 5541 5542 pool_cache_setlowat(&pmap_l2ptp_cache, 5543 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5544 pool_cache_setlowat(&pmap_l2dtable_cache, 5545 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5546 5547 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5548 needed -= 1; 5549 5550 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 5551 5552 for (loop = 0; loop < needed; loop++, l1++) { 5553 /* Allocate a L1 page table */ 5554 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5555 if (va == 0) 5556 panic("Cannot allocate L1 KVM"); 5557 5558 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5559 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 5560 if (error) 5561 panic("Cannot allocate L1 physical pages"); 5562 5563 m = TAILQ_FIRST(&plist); 5564 eva = va + L1_TABLE_SIZE; 5565 pl1pt = (pd_entry_t *)va; 5566 5567 while (m && va < eva) { 5568 paddr_t pa = VM_PAGE_TO_PHYS(m); 5569 5570 pmap_kenter_pa(va, pa, 5571 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5572 5573 /* 5574 * Make sure the L1 descriptor table is mapped 5575 * with the cache-mode set to write-through. 5576 */ 5577 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5578 KDASSERT(l2b != NULL); 5579 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5580 pte = *ptep; 5581 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5582 *ptep = pte; 5583 PTE_SYNC(ptep); 5584 cpu_tlb_flushD_SE(va); 5585 5586 va += PAGE_SIZE; 5587 m = TAILQ_NEXT(m, pageq.queue); 5588 } 5589 5590 #ifdef DIAGNOSTIC 5591 if (m) 5592 panic("pmap_alloc_l1pt: pglist not empty"); 5593 #endif /* DIAGNOSTIC */ 5594 5595 pmap_init_l1(l1, pl1pt); 5596 } 5597 5598 #ifdef DEBUG 5599 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5600 needed); 5601 #endif 5602 } 5603 5604 /* 5605 * Note that the following routines are used by board-specific initialisation 5606 * code to configure the initial kernel page tables. 5607 * 5608 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5609 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5610 * behaviour of the old pmap, and provides an easy migration path for 5611 * initial bring-up of the new pmap on existing ports. Fortunately, 5612 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5613 * will be deprecated. 5614 * 5615 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5616 * tables. 5617 */ 5618 5619 /* 5620 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5621 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5622 * find them as necessary. 5623 * 5624 * Note that the data on this list MUST remain valid after initarm() returns, 5625 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5626 */ 5627 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5628 5629 static vaddr_t 5630 kernel_pt_lookup(paddr_t pa) 5631 { 5632 pv_addr_t *pv; 5633 5634 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5635 #ifndef ARM32_NEW_VM_LAYOUT 5636 if (pv->pv_pa == (pa & ~PGOFSET)) 5637 return (pv->pv_va | (pa & PGOFSET)); 5638 #else 5639 if (pv->pv_pa == pa) 5640 return (pv->pv_va); 5641 #endif 5642 } 5643 return (0); 5644 } 5645 5646 /* 5647 * pmap_map_section: 5648 * 5649 * Create a single section mapping. 5650 */ 5651 void 5652 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5653 { 5654 pd_entry_t *pde = (pd_entry_t *) l1pt; 5655 pd_entry_t fl; 5656 5657 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5658 5659 switch (cache) { 5660 case PTE_NOCACHE: 5661 default: 5662 fl = 0; 5663 break; 5664 5665 case PTE_CACHE: 5666 fl = pte_l1_s_cache_mode; 5667 break; 5668 5669 case PTE_PAGETABLE: 5670 fl = pte_l1_s_cache_mode_pt; 5671 break; 5672 } 5673 5674 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5675 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5676 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5677 } 5678 5679 /* 5680 * pmap_map_entry: 5681 * 5682 * Create a single page mapping. 5683 */ 5684 void 5685 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5686 { 5687 pd_entry_t *pde = (pd_entry_t *) l1pt; 5688 pt_entry_t fl; 5689 pt_entry_t *pte; 5690 5691 KASSERT(((va | pa) & PGOFSET) == 0); 5692 5693 switch (cache) { 5694 case PTE_NOCACHE: 5695 default: 5696 fl = 0; 5697 break; 5698 5699 case PTE_CACHE: 5700 fl = pte_l2_s_cache_mode; 5701 break; 5702 5703 case PTE_PAGETABLE: 5704 fl = pte_l2_s_cache_mode_pt; 5705 break; 5706 } 5707 5708 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5709 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5710 5711 #ifndef ARM32_NEW_VM_LAYOUT 5712 pte = (pt_entry_t *) 5713 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5714 #else 5715 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5716 #endif 5717 if (pte == NULL) 5718 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5719 5720 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5721 #ifndef ARM32_NEW_VM_LAYOUT 5722 pte += (va >> PGSHIFT) & 0x3ff; 5723 #else 5724 pte += l2pte_index(va); 5725 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5726 #endif 5727 *pte = fl; 5728 PTE_SYNC(pte); 5729 } 5730 5731 /* 5732 * pmap_link_l2pt: 5733 * 5734 * Link the L2 page table specified by "l2pv" into the L1 5735 * page table at the slot for "va". 5736 */ 5737 void 5738 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5739 { 5740 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5741 u_int slot = va >> L1_S_SHIFT; 5742 5743 #ifndef ARM32_NEW_VM_LAYOUT 5744 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5745 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5746 #endif 5747 5748 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5749 5750 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5751 #ifdef ARM32_NEW_VM_LAYOUT 5752 PTE_SYNC(&pde[slot]); 5753 #else 5754 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5755 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5756 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5757 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5758 #endif 5759 5760 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5761 } 5762 5763 /* 5764 * pmap_map_chunk: 5765 * 5766 * Map a chunk of memory using the most efficient mappings 5767 * possible (section, large page, small page) into the 5768 * provided L1 and L2 tables at the specified virtual address. 5769 */ 5770 vsize_t 5771 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5772 int prot, int cache) 5773 { 5774 pd_entry_t *pdep = (pd_entry_t *) l1pt; 5775 pt_entry_t *pte, f1, f2s, f2l; 5776 vsize_t resid; 5777 int i; 5778 5779 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5780 5781 if (l1pt == 0) 5782 panic("pmap_map_chunk: no L1 table provided"); 5783 5784 #ifdef VERBOSE_INIT_ARM 5785 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5786 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5787 #endif 5788 5789 switch (cache) { 5790 case PTE_NOCACHE: 5791 default: 5792 f1 = 0; 5793 f2l = 0; 5794 f2s = 0; 5795 break; 5796 5797 case PTE_CACHE: 5798 f1 = pte_l1_s_cache_mode; 5799 f2l = pte_l2_l_cache_mode; 5800 f2s = pte_l2_s_cache_mode; 5801 break; 5802 5803 case PTE_PAGETABLE: 5804 f1 = pte_l1_s_cache_mode_pt; 5805 f2l = pte_l2_l_cache_mode_pt; 5806 f2s = pte_l2_s_cache_mode_pt; 5807 break; 5808 } 5809 5810 size = resid; 5811 5812 while (resid > 0) { 5813 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5814 /* See if we can use a supersection mapping. */ 5815 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 5816 /* Supersection are always domain 0 */ 5817 pd_entry_t pde = L1_SS_PROTO | pa | 5818 L1_S_PROT(PTE_KERNEL, prot) | f1; 5819 #ifdef VERBOSE_INIT_ARM 5820 printf("sS"); 5821 #endif 5822 for (size_t s = va >> L1_S_SHIFT, 5823 e = s + L1_SS_SIZE / L1_S_SIZE; 5824 s < e; 5825 s++) { 5826 pdep[s] = pde; 5827 PTE_SYNC(&pdep[s]); 5828 } 5829 va += L1_SS_SIZE; 5830 pa += L1_SS_SIZE; 5831 resid -= L1_SS_SIZE; 5832 continue; 5833 } 5834 #endif 5835 /* See if we can use a section mapping. */ 5836 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5837 #ifdef VERBOSE_INIT_ARM 5838 printf("S"); 5839 #endif 5840 pdep[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5841 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5842 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5843 PTE_SYNC(&pdep[va >> L1_S_SHIFT]); 5844 va += L1_S_SIZE; 5845 pa += L1_S_SIZE; 5846 resid -= L1_S_SIZE; 5847 continue; 5848 } 5849 5850 /* 5851 * Ok, we're going to use an L2 table. Make sure 5852 * one is actually in the corresponding L1 slot 5853 * for the current VA. 5854 */ 5855 if ((pdep[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5856 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5857 5858 #ifndef ARM32_NEW_VM_LAYOUT 5859 pte = (pt_entry_t *) 5860 kernel_pt_lookup(pdep[va >> L1_S_SHIFT] & L2_S_FRAME); 5861 #else 5862 pte = (pt_entry_t *) kernel_pt_lookup( 5863 pdep[L1_IDX(va)] & L1_C_ADDR_MASK); 5864 #endif 5865 if (pte == NULL) 5866 panic("pmap_map_chunk: can't find L2 table for VA" 5867 "0x%08lx", va); 5868 5869 /* See if we can use a L2 large page mapping. */ 5870 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5871 #ifdef VERBOSE_INIT_ARM 5872 printf("L"); 5873 #endif 5874 for (i = 0; i < 16; i++) { 5875 #ifndef ARM32_NEW_VM_LAYOUT 5876 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5877 L2_L_PROTO | pa | 5878 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5879 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5880 #else 5881 pte[l2pte_index(va) + i] = 5882 L2_L_PROTO | pa | 5883 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5884 PTE_SYNC(&pte[l2pte_index(va) + i]); 5885 #endif 5886 } 5887 va += L2_L_SIZE; 5888 pa += L2_L_SIZE; 5889 resid -= L2_L_SIZE; 5890 continue; 5891 } 5892 5893 /* Use a small page mapping. */ 5894 #ifdef VERBOSE_INIT_ARM 5895 printf("P"); 5896 #endif 5897 #ifndef ARM32_NEW_VM_LAYOUT 5898 pte[(va >> PGSHIFT) & 0x3ff] = 5899 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5900 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5901 #else 5902 pte[l2pte_index(va)] = 5903 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5904 PTE_SYNC(&pte[l2pte_index(va)]); 5905 #endif 5906 va += PAGE_SIZE; 5907 pa += PAGE_SIZE; 5908 resid -= PAGE_SIZE; 5909 } 5910 #ifdef VERBOSE_INIT_ARM 5911 printf("\n"); 5912 #endif 5913 return (size); 5914 } 5915 5916 /********************** Static device map routines ***************************/ 5917 5918 static const struct pmap_devmap *pmap_devmap_table; 5919 5920 /* 5921 * Register the devmap table. This is provided in case early console 5922 * initialization needs to register mappings created by bootstrap code 5923 * before pmap_devmap_bootstrap() is called. 5924 */ 5925 void 5926 pmap_devmap_register(const struct pmap_devmap *table) 5927 { 5928 5929 pmap_devmap_table = table; 5930 } 5931 5932 /* 5933 * Map all of the static regions in the devmap table, and remember 5934 * the devmap table so other parts of the kernel can look up entries 5935 * later. 5936 */ 5937 void 5938 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5939 { 5940 int i; 5941 5942 pmap_devmap_table = table; 5943 5944 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5945 #ifdef VERBOSE_INIT_ARM 5946 printf("devmap: %08lx -> %08lx @ %08lx\n", 5947 pmap_devmap_table[i].pd_pa, 5948 pmap_devmap_table[i].pd_pa + 5949 pmap_devmap_table[i].pd_size - 1, 5950 pmap_devmap_table[i].pd_va); 5951 #endif 5952 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5953 pmap_devmap_table[i].pd_pa, 5954 pmap_devmap_table[i].pd_size, 5955 pmap_devmap_table[i].pd_prot, 5956 pmap_devmap_table[i].pd_cache); 5957 } 5958 } 5959 5960 const struct pmap_devmap * 5961 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5962 { 5963 uint64_t endpa; 5964 int i; 5965 5966 if (pmap_devmap_table == NULL) 5967 return (NULL); 5968 5969 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5970 5971 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5972 if (pa >= pmap_devmap_table[i].pd_pa && 5973 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5974 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5975 return (&pmap_devmap_table[i]); 5976 } 5977 5978 return (NULL); 5979 } 5980 5981 const struct pmap_devmap * 5982 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5983 { 5984 int i; 5985 5986 if (pmap_devmap_table == NULL) 5987 return (NULL); 5988 5989 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5990 if (va >= pmap_devmap_table[i].pd_va && 5991 va + size - 1 <= pmap_devmap_table[i].pd_va + 5992 pmap_devmap_table[i].pd_size - 1) 5993 return (&pmap_devmap_table[i]); 5994 } 5995 5996 return (NULL); 5997 } 5998 5999 /********************** PTE initialization routines **************************/ 6000 6001 /* 6002 * These routines are called when the CPU type is identified to set up 6003 * the PTE prototypes, cache modes, etc. 6004 * 6005 * The variables are always here, just in case modules need to reference 6006 * them (though, they shouldn't). 6007 */ 6008 6009 pt_entry_t pte_l1_s_cache_mode; 6010 pt_entry_t pte_l1_s_wc_mode; 6011 pt_entry_t pte_l1_s_cache_mode_pt; 6012 pt_entry_t pte_l1_s_cache_mask; 6013 6014 pt_entry_t pte_l2_l_cache_mode; 6015 pt_entry_t pte_l2_l_wc_mode; 6016 pt_entry_t pte_l2_l_cache_mode_pt; 6017 pt_entry_t pte_l2_l_cache_mask; 6018 6019 pt_entry_t pte_l2_s_cache_mode; 6020 pt_entry_t pte_l2_s_wc_mode; 6021 pt_entry_t pte_l2_s_cache_mode_pt; 6022 pt_entry_t pte_l2_s_cache_mask; 6023 6024 pt_entry_t pte_l1_s_prot_u; 6025 pt_entry_t pte_l1_s_prot_w; 6026 pt_entry_t pte_l1_s_prot_ro; 6027 pt_entry_t pte_l1_s_prot_mask; 6028 6029 pt_entry_t pte_l2_s_prot_u; 6030 pt_entry_t pte_l2_s_prot_w; 6031 pt_entry_t pte_l2_s_prot_ro; 6032 pt_entry_t pte_l2_s_prot_mask; 6033 6034 pt_entry_t pte_l2_l_prot_u; 6035 pt_entry_t pte_l2_l_prot_w; 6036 pt_entry_t pte_l2_l_prot_ro; 6037 pt_entry_t pte_l2_l_prot_mask; 6038 6039 pt_entry_t pte_l1_ss_proto; 6040 pt_entry_t pte_l1_s_proto; 6041 pt_entry_t pte_l1_c_proto; 6042 pt_entry_t pte_l2_s_proto; 6043 6044 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6045 void (*pmap_zero_page_func)(paddr_t); 6046 6047 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6048 void 6049 pmap_pte_init_generic(void) 6050 { 6051 6052 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6053 pte_l1_s_wc_mode = L1_S_B; 6054 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6055 6056 pte_l2_l_cache_mode = L2_B|L2_C; 6057 pte_l2_l_wc_mode = L2_B; 6058 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6059 6060 pte_l2_s_cache_mode = L2_B|L2_C; 6061 pte_l2_s_wc_mode = L2_B; 6062 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6063 6064 /* 6065 * If we have a write-through cache, set B and C. If 6066 * we have a write-back cache, then we assume setting 6067 * only C will make those pages write-through (except for those 6068 * Cortex CPUs which can read the L1 caches). 6069 */ 6070 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6071 #if ARM_MMU_V7 > 0 6072 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6073 #endif 6074 #if ARM_MMU_V6 > 0 6075 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6076 #endif 6077 || false) { 6078 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6079 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6080 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6081 } else { 6082 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6083 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6084 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6085 } 6086 6087 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6088 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6089 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6090 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6091 6092 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6093 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6094 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6095 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6096 6097 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6098 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6099 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6100 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6101 6102 pte_l1_ss_proto = L1_SS_PROTO_generic; 6103 pte_l1_s_proto = L1_S_PROTO_generic; 6104 pte_l1_c_proto = L1_C_PROTO_generic; 6105 pte_l2_s_proto = L2_S_PROTO_generic; 6106 6107 pmap_copy_page_func = pmap_copy_page_generic; 6108 pmap_zero_page_func = pmap_zero_page_generic; 6109 } 6110 6111 #if defined(CPU_ARM8) 6112 void 6113 pmap_pte_init_arm8(void) 6114 { 6115 6116 /* 6117 * ARM8 is compatible with generic, but we need to use 6118 * the page tables uncached. 6119 */ 6120 pmap_pte_init_generic(); 6121 6122 pte_l1_s_cache_mode_pt = 0; 6123 pte_l2_l_cache_mode_pt = 0; 6124 pte_l2_s_cache_mode_pt = 0; 6125 } 6126 #endif /* CPU_ARM8 */ 6127 6128 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6129 void 6130 pmap_pte_init_arm9(void) 6131 { 6132 6133 /* 6134 * ARM9 is compatible with generic, but we want to use 6135 * write-through caching for now. 6136 */ 6137 pmap_pte_init_generic(); 6138 6139 pte_l1_s_cache_mode = L1_S_C; 6140 pte_l2_l_cache_mode = L2_C; 6141 pte_l2_s_cache_mode = L2_C; 6142 6143 pte_l1_s_wc_mode = L1_S_B; 6144 pte_l2_l_wc_mode = L2_B; 6145 pte_l2_s_wc_mode = L2_B; 6146 6147 pte_l1_s_cache_mode_pt = L1_S_C; 6148 pte_l2_l_cache_mode_pt = L2_C; 6149 pte_l2_s_cache_mode_pt = L2_C; 6150 } 6151 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6152 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6153 6154 #if defined(CPU_ARM10) 6155 void 6156 pmap_pte_init_arm10(void) 6157 { 6158 6159 /* 6160 * ARM10 is compatible with generic, but we want to use 6161 * write-through caching for now. 6162 */ 6163 pmap_pte_init_generic(); 6164 6165 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6166 pte_l2_l_cache_mode = L2_B | L2_C; 6167 pte_l2_s_cache_mode = L2_B | L2_C; 6168 6169 pte_l1_s_cache_mode = L1_S_B; 6170 pte_l2_l_cache_mode = L2_B; 6171 pte_l2_s_cache_mode = L2_B; 6172 6173 pte_l1_s_cache_mode_pt = L1_S_C; 6174 pte_l2_l_cache_mode_pt = L2_C; 6175 pte_l2_s_cache_mode_pt = L2_C; 6176 6177 } 6178 #endif /* CPU_ARM10 */ 6179 6180 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6181 void 6182 pmap_pte_init_arm11(void) 6183 { 6184 6185 /* 6186 * ARM11 is compatible with generic, but we want to use 6187 * write-through caching for now. 6188 */ 6189 pmap_pte_init_generic(); 6190 6191 pte_l1_s_cache_mode = L1_S_C; 6192 pte_l2_l_cache_mode = L2_C; 6193 pte_l2_s_cache_mode = L2_C; 6194 6195 pte_l1_s_wc_mode = L1_S_B; 6196 pte_l2_l_wc_mode = L2_B; 6197 pte_l2_s_wc_mode = L2_B; 6198 6199 pte_l1_s_cache_mode_pt = L1_S_C; 6200 pte_l2_l_cache_mode_pt = L2_C; 6201 pte_l2_s_cache_mode_pt = L2_C; 6202 } 6203 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6204 6205 #if ARM_MMU_SA1 == 1 6206 void 6207 pmap_pte_init_sa1(void) 6208 { 6209 6210 /* 6211 * The StrongARM SA-1 cache does not have a write-through 6212 * mode. So, do the generic initialization, then reset 6213 * the page table cache mode to B=1,C=1, and note that 6214 * the PTEs need to be sync'd. 6215 */ 6216 pmap_pte_init_generic(); 6217 6218 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6219 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6220 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6221 6222 pmap_needs_pte_sync = 1; 6223 } 6224 #endif /* ARM_MMU_SA1 == 1*/ 6225 6226 #if ARM_MMU_XSCALE == 1 6227 #if (ARM_NMMUS > 1) 6228 static u_int xscale_use_minidata; 6229 #endif 6230 6231 void 6232 pmap_pte_init_xscale(void) 6233 { 6234 uint32_t auxctl; 6235 int write_through = 0; 6236 6237 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6238 pte_l1_s_wc_mode = L1_S_B; 6239 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6240 6241 pte_l2_l_cache_mode = L2_B|L2_C; 6242 pte_l2_l_wc_mode = L2_B; 6243 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6244 6245 pte_l2_s_cache_mode = L2_B|L2_C; 6246 pte_l2_s_wc_mode = L2_B; 6247 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6248 6249 pte_l1_s_cache_mode_pt = L1_S_C; 6250 pte_l2_l_cache_mode_pt = L2_C; 6251 pte_l2_s_cache_mode_pt = L2_C; 6252 6253 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6254 /* 6255 * The XScale core has an enhanced mode where writes that 6256 * miss the cache cause a cache line to be allocated. This 6257 * is significantly faster than the traditional, write-through 6258 * behavior of this case. 6259 */ 6260 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6261 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6262 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6263 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6264 6265 #ifdef XSCALE_CACHE_WRITE_THROUGH 6266 /* 6267 * Some versions of the XScale core have various bugs in 6268 * their cache units, the work-around for which is to run 6269 * the cache in write-through mode. Unfortunately, this 6270 * has a major (negative) impact on performance. So, we 6271 * go ahead and run fast-and-loose, in the hopes that we 6272 * don't line up the planets in a way that will trip the 6273 * bugs. 6274 * 6275 * However, we give you the option to be slow-but-correct. 6276 */ 6277 write_through = 1; 6278 #elif defined(XSCALE_CACHE_WRITE_BACK) 6279 /* force write back cache mode */ 6280 write_through = 0; 6281 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6282 /* 6283 * Intel PXA2[15]0 processors are known to have a bug in 6284 * write-back cache on revision 4 and earlier (stepping 6285 * A[01] and B[012]). Fixed for C0 and later. 6286 */ 6287 { 6288 uint32_t id, type; 6289 6290 id = cpufunc_id(); 6291 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6292 6293 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6294 if ((id & CPU_ID_REVISION_MASK) < 5) { 6295 /* write through for stepping A0-1 and B0-2 */ 6296 write_through = 1; 6297 } 6298 } 6299 } 6300 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6301 6302 if (write_through) { 6303 pte_l1_s_cache_mode = L1_S_C; 6304 pte_l2_l_cache_mode = L2_C; 6305 pte_l2_s_cache_mode = L2_C; 6306 } 6307 6308 #if (ARM_NMMUS > 1) 6309 xscale_use_minidata = 1; 6310 #endif 6311 6312 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6313 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6314 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6315 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6316 6317 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6318 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6319 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6320 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6321 6322 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6323 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6324 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6325 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6326 6327 pte_l1_ss_proto = L1_SS_PROTO_xscale; 6328 pte_l1_s_proto = L1_S_PROTO_xscale; 6329 pte_l1_c_proto = L1_C_PROTO_xscale; 6330 pte_l2_s_proto = L2_S_PROTO_xscale; 6331 6332 pmap_copy_page_func = pmap_copy_page_xscale; 6333 pmap_zero_page_func = pmap_zero_page_xscale; 6334 6335 /* 6336 * Disable ECC protection of page table access, for now. 6337 */ 6338 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6339 auxctl &= ~XSCALE_AUXCTL_P; 6340 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6341 } 6342 6343 /* 6344 * xscale_setup_minidata: 6345 * 6346 * Set up the mini-data cache clean area. We require the 6347 * caller to allocate the right amount of physically and 6348 * virtually contiguous space. 6349 */ 6350 void 6351 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6352 { 6353 extern vaddr_t xscale_minidata_clean_addr; 6354 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6355 pd_entry_t *pde = (pd_entry_t *) l1pt; 6356 pt_entry_t *pte; 6357 vsize_t size; 6358 uint32_t auxctl; 6359 6360 xscale_minidata_clean_addr = va; 6361 6362 /* Round it to page size. */ 6363 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6364 6365 for (; size != 0; 6366 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6367 #ifndef ARM32_NEW_VM_LAYOUT 6368 pte = (pt_entry_t *) 6369 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6370 #else 6371 pte = (pt_entry_t *) kernel_pt_lookup( 6372 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6373 #endif 6374 if (pte == NULL) 6375 panic("xscale_setup_minidata: can't find L2 table for " 6376 "VA 0x%08lx", va); 6377 #ifndef ARM32_NEW_VM_LAYOUT 6378 pte[(va >> PGSHIFT) & 0x3ff] = 6379 #else 6380 pte[l2pte_index(va)] = 6381 #endif 6382 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6383 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6384 } 6385 6386 /* 6387 * Configure the mini-data cache for write-back with 6388 * read/write-allocate. 6389 * 6390 * NOTE: In order to reconfigure the mini-data cache, we must 6391 * make sure it contains no valid data! In order to do that, 6392 * we must issue a global data cache invalidate command! 6393 * 6394 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6395 * THIS IS VERY IMPORTANT! 6396 */ 6397 6398 /* Invalidate data and mini-data. */ 6399 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6400 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6401 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6402 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6403 } 6404 6405 /* 6406 * Change the PTEs for the specified kernel mappings such that they 6407 * will use the mini data cache instead of the main data cache. 6408 */ 6409 void 6410 pmap_uarea(vaddr_t va) 6411 { 6412 struct l2_bucket *l2b; 6413 pt_entry_t *ptep, *sptep, pte; 6414 vaddr_t next_bucket, eva; 6415 6416 #if (ARM_NMMUS > 1) 6417 if (xscale_use_minidata == 0) 6418 return; 6419 #endif 6420 6421 eva = va + USPACE; 6422 6423 while (va < eva) { 6424 next_bucket = L2_NEXT_BUCKET(va); 6425 if (next_bucket > eva) 6426 next_bucket = eva; 6427 6428 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6429 KDASSERT(l2b != NULL); 6430 6431 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6432 6433 while (va < next_bucket) { 6434 pte = *ptep; 6435 if (!l2pte_minidata(pte)) { 6436 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6437 cpu_tlb_flushD_SE(va); 6438 *ptep = pte & ~L2_B; 6439 } 6440 ptep++; 6441 va += PAGE_SIZE; 6442 } 6443 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6444 } 6445 cpu_cpwait(); 6446 } 6447 #endif /* ARM_MMU_XSCALE == 1 */ 6448 6449 6450 #if defined(CPU_ARM11MPCORE) 6451 6452 void 6453 pmap_pte_init_arm11mpcore(void) 6454 { 6455 6456 /* cache mode is controlled by 5 bits (B, C, TEX) */ 6457 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 6458 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 6459 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6460 /* use extended small page (without APn, with TEX) */ 6461 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 6462 #else 6463 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 6464 #endif 6465 6466 /* write-back, write-allocate */ 6467 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6468 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 6469 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6470 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6471 #else 6472 /* no TEX. read-allocate */ 6473 pte_l2_s_cache_mode = L2_C | L2_B; 6474 #endif 6475 /* 6476 * write-back, write-allocate for page tables. 6477 */ 6478 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6479 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 6480 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6481 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6482 #else 6483 pte_l2_s_cache_mode_pt = L2_C | L2_B; 6484 #endif 6485 6486 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 6487 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 6488 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 6489 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 6490 6491 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6492 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 6493 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 6494 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 6495 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 6496 6497 #else 6498 /* with AP[0..3] */ 6499 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6500 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6501 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6502 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6503 #endif 6504 6505 #ifdef ARM11MPCORE_COMPAT_MMU 6506 /* with AP[0..3] */ 6507 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6508 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6509 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6510 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6511 6512 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6513 pte_l1_s_proto = L1_S_PROTO_armv6; 6514 pte_l1_c_proto = L1_C_PROTO_armv6; 6515 pte_l2_s_proto = L2_S_PROTO_armv6c; 6516 #else 6517 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 6518 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 6519 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 6520 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 6521 6522 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6523 pte_l1_s_proto = L1_S_PROTO_armv6; 6524 pte_l1_c_proto = L1_C_PROTO_armv6; 6525 pte_l2_s_proto = L2_S_PROTO_armv6n; 6526 #endif 6527 6528 pmap_copy_page_func = pmap_copy_page_generic; 6529 pmap_zero_page_func = pmap_zero_page_generic; 6530 pmap_needs_pte_sync = 1; 6531 } 6532 #endif /* CPU_ARM11MPCORE */ 6533 6534 6535 #if ARM_MMU_V7 == 1 6536 void 6537 pmap_pte_init_armv7(void) 6538 { 6539 /* 6540 * The ARMv7-A MMU is mostly compatible with generic. If the 6541 * AP field is zero, that now means "no access" rather than 6542 * read-only. The prototypes are a little different because of 6543 * the XN bit. 6544 */ 6545 pmap_pte_init_generic(); 6546 6547 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6548 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6549 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6550 6551 if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) { 6552 /* 6553 * write-back, no write-allocate, shareable for normal pages. 6554 */ 6555 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_S; 6556 pte_l2_l_cache_mode = L2_C | L2_B | L2_XS_S; 6557 pte_l2_s_cache_mode = L2_C | L2_B | L2_XS_S; 6558 6559 /* 6560 * write-back, no write-allocate, shareable for page tables. 6561 */ 6562 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_S; 6563 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6564 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6565 } 6566 6567 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6568 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6569 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6570 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6571 6572 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6573 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6574 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6575 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6576 6577 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6578 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6579 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6580 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6581 6582 pte_l1_ss_proto = L1_SS_PROTO_armv7; 6583 pte_l1_s_proto = L1_S_PROTO_armv7; 6584 pte_l1_c_proto = L1_C_PROTO_armv7; 6585 pte_l2_s_proto = L2_S_PROTO_armv7; 6586 6587 pmap_needs_pte_sync = 1; 6588 } 6589 #endif /* ARM_MMU_V7 */ 6590 6591 /* 6592 * return the PA of the current L1 table, for use when handling a crash dump 6593 */ 6594 uint32_t pmap_kernel_L1_addr(void) 6595 { 6596 return pmap_kernel()->pm_l1->l1_physaddr; 6597 } 6598 6599 #if defined(DDB) 6600 /* 6601 * A couple of ddb-callable functions for dumping pmaps 6602 */ 6603 void pmap_dump_all(void); 6604 void pmap_dump(pmap_t); 6605 6606 void 6607 pmap_dump_all(void) 6608 { 6609 pmap_t pm; 6610 6611 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6612 if (pm == pmap_kernel()) 6613 continue; 6614 pmap_dump(pm); 6615 printf("\n"); 6616 } 6617 } 6618 6619 static pt_entry_t ncptes[64]; 6620 static void pmap_dump_ncpg(pmap_t); 6621 6622 void 6623 pmap_dump(pmap_t pm) 6624 { 6625 struct l2_dtable *l2; 6626 struct l2_bucket *l2b; 6627 pt_entry_t *ptep, pte; 6628 vaddr_t l2_va, l2b_va, va; 6629 int i, j, k, occ, rows = 0; 6630 6631 if (pm == pmap_kernel()) 6632 printf("pmap_kernel (%p): ", pm); 6633 else 6634 printf("user pmap (%p): ", pm); 6635 6636 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6637 6638 l2_va = 0; 6639 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6640 l2 = pm->pm_l2[i]; 6641 6642 if (l2 == NULL || l2->l2_occupancy == 0) 6643 continue; 6644 6645 l2b_va = l2_va; 6646 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6647 l2b = &l2->l2_bucket[j]; 6648 6649 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6650 continue; 6651 6652 ptep = l2b->l2b_kva; 6653 6654 for (k = 0; k < 256 && ptep[k] == 0; k++) 6655 ; 6656 6657 k &= ~63; 6658 occ = l2b->l2b_occupancy; 6659 va = l2b_va + (k * 4096); 6660 for (; k < 256; k++, va += 0x1000) { 6661 char ch = ' '; 6662 if ((k % 64) == 0) { 6663 if ((rows % 8) == 0) { 6664 printf( 6665 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6666 } 6667 printf("%08lx: ", va); 6668 } 6669 6670 ncptes[k & 63] = 0; 6671 pte = ptep[k]; 6672 if (pte == 0) { 6673 ch = '.'; 6674 } else { 6675 occ--; 6676 switch (pte & 0x0c) { 6677 case 0x00: 6678 ch = 'D'; /* No cache No buff */ 6679 break; 6680 case 0x04: 6681 ch = 'B'; /* No cache buff */ 6682 break; 6683 case 0x08: 6684 if (pte & 0x40) 6685 ch = 'm'; 6686 else 6687 ch = 'C'; /* Cache No buff */ 6688 break; 6689 case 0x0c: 6690 ch = 'F'; /* Cache Buff */ 6691 break; 6692 } 6693 6694 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6695 ch += 0x20; 6696 6697 if ((pte & 0xc) == 0) 6698 ncptes[k & 63] = pte; 6699 } 6700 6701 if ((k % 64) == 63) { 6702 rows++; 6703 printf("%c\n", ch); 6704 pmap_dump_ncpg(pm); 6705 if (occ == 0) 6706 break; 6707 } else 6708 printf("%c", ch); 6709 } 6710 } 6711 } 6712 } 6713 6714 static void 6715 pmap_dump_ncpg(pmap_t pm) 6716 { 6717 struct vm_page *pg; 6718 struct vm_page_md *md; 6719 struct pv_entry *pv; 6720 int i; 6721 6722 for (i = 0; i < 63; i++) { 6723 if (ncptes[i] == 0) 6724 continue; 6725 6726 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6727 if (pg == NULL) 6728 continue; 6729 md = VM_PAGE_TO_MD(pg); 6730 6731 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6732 VM_PAGE_TO_PHYS(pg), 6733 md->krw_mappings, md->kro_mappings, 6734 md->urw_mappings, md->uro_mappings); 6735 6736 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6737 printf(" %c va 0x%08lx, flags 0x%x\n", 6738 (pm == pv->pv_pmap) ? '*' : ' ', 6739 pv->pv_va, pv->pv_flags); 6740 } 6741 } 6742 } 6743 #endif 6744 6745 #ifdef PMAP_STEAL_MEMORY 6746 void 6747 pmap_boot_pageadd(pv_addr_t *newpv) 6748 { 6749 pv_addr_t *pv, *npv; 6750 6751 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6752 if (newpv->pv_pa < pv->pv_va) { 6753 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6754 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6755 newpv->pv_size += pv->pv_size; 6756 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6757 } 6758 pv = NULL; 6759 } else { 6760 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6761 pv = npv) { 6762 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6763 KASSERT(pv->pv_pa < newpv->pv_pa); 6764 if (newpv->pv_pa > npv->pv_pa) 6765 continue; 6766 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6767 pv->pv_size += newpv->pv_size; 6768 return; 6769 } 6770 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6771 break; 6772 newpv->pv_size += npv->pv_size; 6773 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6774 SLIST_REMOVE_AFTER(newpv, pv_list); 6775 return; 6776 } 6777 } 6778 } 6779 6780 if (pv) { 6781 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6782 } else { 6783 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6784 } 6785 } 6786 6787 void 6788 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6789 pv_addr_t *rpv) 6790 { 6791 pv_addr_t *pv, **pvp; 6792 struct vm_physseg *ps; 6793 size_t i; 6794 6795 KASSERT(amount & PGOFSET); 6796 KASSERT((mask & PGOFSET) == 0); 6797 KASSERT((match & PGOFSET) == 0); 6798 KASSERT(amount != 0); 6799 6800 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6801 (pv = *pvp) != NULL; 6802 pvp = &SLIST_NEXT(pv, pv_list)) { 6803 pv_addr_t *newpv; 6804 psize_t off; 6805 /* 6806 * If this entry is too small to satify the request... 6807 */ 6808 KASSERT(pv->pv_size > 0); 6809 if (pv->pv_size < amount) 6810 continue; 6811 6812 for (off = 0; off <= mask; off += PAGE_SIZE) { 6813 if (((pv->pv_pa + off) & mask) == match 6814 && off + amount <= pv->pv_size) 6815 break; 6816 } 6817 if (off > mask) 6818 continue; 6819 6820 rpv->pv_va = pv->pv_va + off; 6821 rpv->pv_pa = pv->pv_pa + off; 6822 rpv->pv_size = amount; 6823 pv->pv_size -= amount; 6824 if (pv->pv_size == 0) { 6825 KASSERT(off == 0); 6826 KASSERT((vaddr_t) pv == rpv->pv_va); 6827 *pvp = SLIST_NEXT(pv, pv_list); 6828 } else if (off == 0) { 6829 KASSERT((vaddr_t) pv == rpv->pv_va); 6830 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6831 *newpv = *pv; 6832 newpv->pv_pa += amount; 6833 newpv->pv_va += amount; 6834 *pvp = newpv; 6835 } else if (off < pv->pv_size) { 6836 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6837 *newpv = *pv; 6838 newpv->pv_size -= off; 6839 newpv->pv_pa += off + amount; 6840 newpv->pv_va += off + amount; 6841 6842 SLIST_NEXT(pv, pv_list) = newpv; 6843 pv->pv_size = off; 6844 } else { 6845 KASSERT((vaddr_t) pv != rpv->pv_va); 6846 } 6847 memset((void *)rpv->pv_va, 0, amount); 6848 return; 6849 } 6850 6851 if (vm_nphysseg == 0) 6852 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6853 6854 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6855 (pv = *pvp) != NULL; 6856 pvp = &SLIST_NEXT(pv, pv_list)) { 6857 if (SLIST_NEXT(pv, pv_list) == NULL) 6858 break; 6859 } 6860 KASSERT(mask == 0); 6861 for (i = 0; i < vm_nphysseg; i++) { 6862 ps = VM_PHYSMEM_PTR(i); 6863 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6864 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6865 rpv->pv_va = pv->pv_va; 6866 rpv->pv_pa = pv->pv_pa; 6867 rpv->pv_size = amount; 6868 *pvp = NULL; 6869 pmap_map_chunk(kernel_l1pt.pv_va, 6870 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6871 ptoa(ps->avail_start), 6872 amount - pv->pv_size, 6873 VM_PROT_READ|VM_PROT_WRITE, 6874 PTE_CACHE); 6875 ps->avail_start += atop(amount - pv->pv_size); 6876 /* 6877 * If we consumed the entire physseg, remove it. 6878 */ 6879 if (ps->avail_start == ps->avail_end) { 6880 for (--vm_nphysseg; i < vm_nphysseg; i++) 6881 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6882 } 6883 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6884 return; 6885 } 6886 } 6887 6888 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6889 } 6890 6891 vaddr_t 6892 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6893 { 6894 pv_addr_t pv; 6895 6896 pmap_boot_pagealloc(size, 0, 0, &pv); 6897 6898 return pv.pv_va; 6899 } 6900 #endif /* PMAP_STEAL_MEMORY */ 6901 6902 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6903 { 6904 sysctl_createv(clog, 0, NULL, NULL, 6905 CTLFLAG_PERMANENT, 6906 CTLTYPE_NODE, "machdep", NULL, 6907 NULL, 0, NULL, 0, 6908 CTL_MACHDEP, CTL_EOL); 6909 6910 sysctl_createv(clog, 0, NULL, NULL, 6911 CTLFLAG_PERMANENT, 6912 CTLTYPE_INT, "kmpages", 6913 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6914 NULL, 0, &pmap_kmpages, 0, 6915 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6916 } 6917 6918 #ifdef PMAP_NEED_ALLOC_POOLPAGE 6919 struct vm_page * 6920 arm_pmap_alloc_poolpage(int flags) 6921 { 6922 /* 6923 * On some systems, only some pages may be "coherent" for dma and we 6924 * want to use those for pool pages (think mbufs). 6925 */ 6926 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) 6927 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 6928 UVM_PGA_STRAT_ONLY, arm_poolpage_vmfreelist); 6929 6930 return uvm_pagealloc(NULL, 0, NULL, flags); 6931 } 6932 #endif 6933
Indexes created Wed Sep 24 05:09:52 GMT 2025