pmap.c revision 1.259
1 /* $NetBSD: pmap.c,v 1.259 2013/07/03 15:24:35 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/pool.h> 201 #include <sys/kmem.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <sys/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/cpuconf.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.259 2013/07/03 15:24:35 matt Exp $"); 216 217 #ifdef PMAP_DEBUG 218 219 /* XXX need to get rid of all refs to this */ 220 int pmap_debug_level = 0; 221 222 /* 223 * for switching to potentially finer grained debugging 224 */ 225 #define PDB_FOLLOW 0x0001 226 #define PDB_INIT 0x0002 227 #define PDB_ENTER 0x0004 228 #define PDB_REMOVE 0x0008 229 #define PDB_CREATE 0x0010 230 #define PDB_PTPAGE 0x0020 231 #define PDB_GROWKERN 0x0040 232 #define PDB_BITS 0x0080 233 #define PDB_COLLECT 0x0100 234 #define PDB_PROTECT 0x0200 235 #define PDB_MAP_L1 0x0400 236 #define PDB_BOOTSTRAP 0x1000 237 #define PDB_PARANOIA 0x2000 238 #define PDB_WIRING 0x4000 239 #define PDB_PVDUMP 0x8000 240 #define PDB_VAC 0x10000 241 #define PDB_KENTER 0x20000 242 #define PDB_KREMOVE 0x40000 243 #define PDB_EXEC 0x80000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 253 #endif /* PMAP_DEBUG */ 254 255 /* 256 * pmap_kernel() points here 257 */ 258 static struct pmap kernel_pmap_store; 259 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 260 #ifdef PMAP_NEED_ALLOC_POOLPAGE 261 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 262 #endif 263 264 /* 265 * Which pmap is currently 'live' in the cache 266 * 267 * XXXSCW: Fix for SMP ... 268 */ 269 static pmap_t pmap_recent_user; 270 271 /* 272 * Pointer to last active lwp, or NULL if it exited. 273 */ 274 struct lwp *pmap_previous_active_lwp; 275 276 /* 277 * Pool and cache that pmap structures are allocated from. 278 * We use a cache to avoid clearing the pm_l2[] array (1KB) 279 * in pmap_create(). 280 */ 281 static struct pool_cache pmap_cache; 282 static LIST_HEAD(, pmap) pmap_pmaps; 283 284 /* 285 * Pool of PV structures 286 */ 287 static struct pool pmap_pv_pool; 288 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 289 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 290 static struct pool_allocator pmap_bootstrap_pv_allocator = { 291 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 292 }; 293 294 /* 295 * Pool and cache of l2_dtable structures. 296 * We use a cache to avoid clearing the structures when they're 297 * allocated. (196 bytes) 298 */ 299 static struct pool_cache pmap_l2dtable_cache; 300 static vaddr_t pmap_kernel_l2dtable_kva; 301 302 /* 303 * Pool and cache of L2 page descriptors. 304 * We use a cache to avoid clearing the descriptor table 305 * when they're allocated. (1KB) 306 */ 307 static struct pool_cache pmap_l2ptp_cache; 308 static vaddr_t pmap_kernel_l2ptp_kva; 309 static paddr_t pmap_kernel_l2ptp_phys; 310 311 #ifdef PMAPCOUNTERS 312 #define PMAP_EVCNT_INITIALIZER(name) \ 313 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 314 315 #ifdef PMAP_CACHE_VIPT 316 static struct evcnt pmap_ev_vac_clean_one = 317 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_one = 319 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_lots = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 322 static struct evcnt pmap_ev_vac_flush_lots2 = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 328 329 static struct evcnt pmap_ev_vac_color_new = 330 PMAP_EVCNT_INITIALIZER("new page color"); 331 static struct evcnt pmap_ev_vac_color_reuse = 332 PMAP_EVCNT_INITIALIZER("ok first page color"); 333 static struct evcnt pmap_ev_vac_color_ok = 334 PMAP_EVCNT_INITIALIZER("ok page color"); 335 static struct evcnt pmap_ev_vac_color_blind = 336 PMAP_EVCNT_INITIALIZER("blind page color"); 337 static struct evcnt pmap_ev_vac_color_change = 338 PMAP_EVCNT_INITIALIZER("change page color"); 339 static struct evcnt pmap_ev_vac_color_erase = 340 PMAP_EVCNT_INITIALIZER("erase page color"); 341 static struct evcnt pmap_ev_vac_color_none = 342 PMAP_EVCNT_INITIALIZER("no page color"); 343 static struct evcnt pmap_ev_vac_color_restore = 344 PMAP_EVCNT_INITIALIZER("restore page color"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 354 #endif 355 356 static struct evcnt pmap_ev_mappings = 357 PMAP_EVCNT_INITIALIZER("pages mapped"); 358 static struct evcnt pmap_ev_unmappings = 359 PMAP_EVCNT_INITIALIZER("pages unmapped"); 360 static struct evcnt pmap_ev_remappings = 361 PMAP_EVCNT_INITIALIZER("pages remapped"); 362 363 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 364 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 366 367 static struct evcnt pmap_ev_kernel_mappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 369 static struct evcnt pmap_ev_kernel_unmappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 371 static struct evcnt pmap_ev_kernel_remappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 373 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 377 378 static struct evcnt pmap_ev_kenter_mappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 380 static struct evcnt pmap_ev_kenter_unmappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 382 static struct evcnt pmap_ev_kenter_remappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 384 static struct evcnt pmap_ev_pt_mappings = 385 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 391 392 #ifdef PMAP_CACHE_VIPT 393 static struct evcnt pmap_ev_exec_mappings = 394 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 395 static struct evcnt pmap_ev_exec_cached = 396 PMAP_EVCNT_INITIALIZER("exec pages cached"); 397 398 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 399 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 400 401 static struct evcnt pmap_ev_exec_synced = 402 PMAP_EVCNT_INITIALIZER("exec pages synced"); 403 static struct evcnt pmap_ev_exec_synced_map = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 405 static struct evcnt pmap_ev_exec_synced_unmap = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 407 static struct evcnt pmap_ev_exec_synced_remap = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 409 static struct evcnt pmap_ev_exec_synced_clearbit = 410 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 411 static struct evcnt pmap_ev_exec_synced_kremove = 412 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 413 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 417 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 418 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 420 421 static struct evcnt pmap_ev_exec_discarded_unmap = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 423 static struct evcnt pmap_ev_exec_discarded_zero = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 425 static struct evcnt pmap_ev_exec_discarded_copy = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 427 static struct evcnt pmap_ev_exec_discarded_page_protect = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 429 static struct evcnt pmap_ev_exec_discarded_clearbit = 430 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 431 static struct evcnt pmap_ev_exec_discarded_kremove = 432 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 433 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 440 #endif /* PMAP_CACHE_VIPT */ 441 442 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 443 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 444 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 445 446 EVCNT_ATTACH_STATIC(pmap_ev_updates); 447 EVCNT_ATTACH_STATIC(pmap_ev_collects); 448 EVCNT_ATTACH_STATIC(pmap_ev_activations); 449 450 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 451 #else 452 #define PMAPCOUNT(x) ((void)0) 453 #endif 454 455 /* 456 * pmap copy/zero page, and mem(5) hook point 457 */ 458 static pt_entry_t *csrc_pte, *cdst_pte; 459 static vaddr_t csrcp, cdstp; 460 vaddr_t memhook; /* used by mem.c */ 461 kmutex_t memlock; /* used by mem.c */ 462 void *zeropage; /* used by mem.c */ 463 extern void *msgbufaddr; 464 int pmap_kmpages; 465 /* 466 * Flag to indicate if pmap_init() has done its thing 467 */ 468 bool pmap_initialized; 469 470 /* 471 * Misc. locking data structures 472 */ 473 474 #define pmap_acquire_pmap_lock(pm) \ 475 do { \ 476 if ((pm) != pmap_kernel()) \ 477 mutex_enter((pm)->pm_lock); \ 478 } while (/*CONSTCOND*/0) 479 480 #define pmap_release_pmap_lock(pm) \ 481 do { \ 482 if ((pm) != pmap_kernel()) \ 483 mutex_exit((pm)->pm_lock); \ 484 } while (/*CONSTCOND*/0) 485 486 487 /* 488 * Metadata for L1 translation tables. 489 */ 490 struct l1_ttable { 491 /* Entry on the L1 Table list */ 492 SLIST_ENTRY(l1_ttable) l1_link; 493 494 /* Entry on the L1 Least Recently Used list */ 495 TAILQ_ENTRY(l1_ttable) l1_lru; 496 497 /* Track how many domains are allocated from this L1 */ 498 volatile u_int l1_domain_use_count; 499 500 /* 501 * A free-list of domain numbers for this L1. 502 * We avoid using ffs() and a bitmap to track domains since ffs() 503 * is slow on ARM. 504 */ 505 uint8_t l1_domain_first; 506 uint8_t l1_domain_free[PMAP_DOMAINS]; 507 508 /* Physical address of this L1 page table */ 509 paddr_t l1_physaddr; 510 511 /* KVA of this L1 page table */ 512 pd_entry_t *l1_kva; 513 }; 514 515 /* 516 * Convert a virtual address into its L1 table index. That is, the 517 * index used to locate the L2 descriptor table pointer in an L1 table. 518 * This is basically used to index l1->l1_kva[]. 519 * 520 * Each L2 descriptor table represents 1MB of VA space. 521 */ 522 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 523 524 /* 525 * L1 Page Tables are tracked using a Least Recently Used list. 526 * - New L1s are allocated from the HEAD. 527 * - Freed L1s are added to the TAIl. 528 * - Recently accessed L1s (where an 'access' is some change to one of 529 * the userland pmaps which owns this L1) are moved to the TAIL. 530 */ 531 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 532 static kmutex_t l1_lru_lock __cacheline_aligned; 533 534 /* 535 * A list of all L1 tables 536 */ 537 static SLIST_HEAD(, l1_ttable) l1_list; 538 539 /* 540 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 541 * 542 * This is normally 16MB worth L2 page descriptors for any given pmap. 543 * Reference counts are maintained for L2 descriptors so they can be 544 * freed when empty. 545 */ 546 struct l2_dtable { 547 /* The number of L2 page descriptors allocated to this l2_dtable */ 548 u_int l2_occupancy; 549 550 /* List of L2 page descriptors */ 551 struct l2_bucket { 552 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 553 paddr_t l2b_phys; /* Physical address of same */ 554 u_short l2b_l1idx; /* This L2 table's L1 index */ 555 u_short l2b_occupancy; /* How many active descriptors */ 556 } l2_bucket[L2_BUCKET_SIZE]; 557 }; 558 559 /* 560 * Given an L1 table index, calculate the corresponding l2_dtable index 561 * and bucket index within the l2_dtable. 562 */ 563 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 564 (L2_SIZE - 1)) 565 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 566 567 /* 568 * Given a virtual address, this macro returns the 569 * virtual address required to drop into the next L2 bucket. 570 */ 571 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 572 573 /* 574 * L2 allocation. 575 */ 576 #define pmap_alloc_l2_dtable() \ 577 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 578 #define pmap_free_l2_dtable(l2) \ 579 pool_cache_put(&pmap_l2dtable_cache, (l2)) 580 #define pmap_alloc_l2_ptp(pap) \ 581 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 582 PR_NOWAIT, (pap))) 583 584 /* 585 * We try to map the page tables write-through, if possible. However, not 586 * all CPUs have a write-through cache mode, so on those we have to sync 587 * the cache when we frob page tables. 588 * 589 * We try to evaluate this at compile time, if possible. However, it's 590 * not always possible to do that, hence this run-time var. 591 */ 592 int pmap_needs_pte_sync; 593 594 /* 595 * Real definition of pv_entry. 596 */ 597 struct pv_entry { 598 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 599 pmap_t pv_pmap; /* pmap where mapping lies */ 600 vaddr_t pv_va; /* virtual address for mapping */ 601 u_int pv_flags; /* flags */ 602 }; 603 604 /* 605 * Macro to determine if a mapping might be resident in the 606 * instruction cache and/or TLB 607 */ 608 #if ARM_MMU_V7 > 0 609 /* 610 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 611 * there are no explicit accesses, so there may be always be TLB entries to 612 * flush. If we used ASIDs then this would not be a problem. 613 */ 614 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 615 #else 616 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 617 #endif 618 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 619 620 /* 621 * Macro to determine if a mapping might be resident in the 622 * data cache and/or TLB 623 */ 624 #if ARM_MMU_V7 > 0 625 /* 626 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 627 * there are no explicit accesses, so there may be always be TLB entries to 628 * flush. If we used ASIDs then this would not be a problem. 629 */ 630 #define PV_BEEN_REFD(f) (1) 631 #else 632 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 633 #endif 634 635 /* 636 * Local prototypes 637 */ 638 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 639 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 640 pt_entry_t **); 641 static bool pmap_is_current(pmap_t); 642 static bool pmap_is_cached(pmap_t); 643 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 644 pmap_t, vaddr_t, u_int); 645 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 646 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 647 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 648 u_int, u_int); 649 650 static void pmap_pinit(pmap_t); 651 static int pmap_pmap_ctor(void *, void *, int); 652 653 static void pmap_alloc_l1(pmap_t); 654 static void pmap_free_l1(pmap_t); 655 static void pmap_use_l1(pmap_t); 656 657 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 658 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 659 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 660 static int pmap_l2ptp_ctor(void *, void *, int); 661 static int pmap_l2dtable_ctor(void *, void *, int); 662 663 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 664 #ifdef PMAP_CACHE_VIVT 665 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 666 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 667 #endif 668 669 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 670 #ifdef PMAP_CACHE_VIVT 671 static int pmap_clean_page(struct pv_entry *, bool); 672 #endif 673 #ifdef PMAP_CACHE_VIPT 674 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 675 enum pmap_flush_op { 676 PMAP_FLUSH_PRIMARY, 677 PMAP_FLUSH_SECONDARY, 678 PMAP_CLEAN_PRIMARY 679 }; 680 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 681 #endif 682 static void pmap_page_remove(struct vm_page_md *, paddr_t); 683 684 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 685 static vaddr_t kernel_pt_lookup(paddr_t); 686 687 688 /* 689 * Misc variables 690 */ 691 vaddr_t virtual_avail; 692 vaddr_t virtual_end; 693 vaddr_t pmap_curmaxkvaddr; 694 695 paddr_t avail_start; 696 paddr_t avail_end; 697 698 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 699 pv_addr_t kernelpages; 700 pv_addr_t kernel_l1pt; 701 pv_addr_t systempage; 702 703 /* Function to set the debug level of the pmap code */ 704 705 #ifdef PMAP_DEBUG 706 void 707 pmap_debug(int level) 708 { 709 pmap_debug_level = level; 710 printf("pmap_debug: level=%d\n", pmap_debug_level); 711 } 712 #endif /* PMAP_DEBUG */ 713 714 #ifdef PMAP_CACHE_VIPT 715 #define PMAP_VALIDATE_MD_PAGE(md) \ 716 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 717 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 718 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 719 #endif /* PMAP_CACHE_VIPT */ 720 /* 721 * A bunch of routines to conditionally flush the caches/TLB depending 722 * on whether the specified pmap actually needs to be flushed at any 723 * given time. 724 */ 725 static inline void 726 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 727 { 728 if (pm->pm_cstate.cs_tlb_id != 0) { 729 if (PV_BEEN_EXECD(flags)) { 730 cpu_tlb_flushID_SE(va); 731 } else if (PV_BEEN_REFD(flags)) { 732 cpu_tlb_flushD_SE(va); 733 } 734 } 735 } 736 737 static inline void 738 pmap_tlb_flushID(pmap_t pm) 739 { 740 if (pm->pm_cstate.cs_tlb_id) { 741 cpu_tlb_flushID(); 742 #if ARM_MMU_V7 == 0 743 /* 744 * Speculative loads by Cortex cores can cause TLB entries to 745 * be filled even if there are no explicit accesses, so there 746 * may be always be TLB entries to flush. If we used ASIDs 747 * then it would not be a problem. 748 * This is not true for other CPUs. 749 */ 750 pm->pm_cstate.cs_tlb = 0; 751 #endif /* ARM_MMU_V7 */ 752 } 753 } 754 755 static inline void 756 pmap_tlb_flushD(pmap_t pm) 757 { 758 if (pm->pm_cstate.cs_tlb_d) { 759 cpu_tlb_flushD(); 760 #if ARM_MMU_V7 == 0 761 /* 762 * Speculative loads by Cortex cores can cause TLB entries to 763 * be filled even if there are no explicit accesses, so there 764 * may be always be TLB entries to flush. If we used ASIDs 765 * then it would not be a problem. 766 * This is not true for other CPUs. 767 */ 768 pm->pm_cstate.cs_tlb_d = 0; 769 } 770 #endif /* ARM_MMU_V7 */ 771 } 772 773 #ifdef PMAP_CACHE_VIVT 774 static inline void 775 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 776 { 777 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 778 cpu_idcache_wbinv_range(va, PAGE_SIZE); 779 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 780 if (do_inv) { 781 if (flags & PVF_WRITE) 782 cpu_dcache_wbinv_range(va, PAGE_SIZE); 783 else 784 cpu_dcache_inv_range(va, PAGE_SIZE); 785 } else if (flags & PVF_WRITE) { 786 cpu_dcache_wb_range(va, PAGE_SIZE); 787 } 788 } 789 } 790 791 static inline void 792 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 793 { 794 if (PV_BEEN_EXECD(flags)) { 795 if (pm->pm_cstate.cs_cache_id) { 796 cpu_idcache_wbinv_all(); 797 pm->pm_cstate.cs_cache = 0; 798 } 799 } else if (pm->pm_cstate.cs_cache_d) { 800 cpu_dcache_wbinv_all(); 801 pm->pm_cstate.cs_cache_d = 0; 802 } 803 } 804 #endif /* PMAP_CACHE_VIVT */ 805 806 static inline uint8_t 807 pmap_domain(pmap_t pm) 808 { 809 return pm->pm_domain; 810 } 811 812 static inline pd_entry_t * 813 pmap_l1_kva(pmap_t pm) 814 { 815 return pm->pm_l1->l1_kva; 816 } 817 818 static inline bool 819 pmap_is_current(pmap_t pm) 820 { 821 822 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 823 return true; 824 825 return false; 826 } 827 828 static inline bool 829 pmap_is_cached(pmap_t pm) 830 { 831 832 if (pm == pmap_kernel() || pmap_recent_user == NULL || 833 pmap_recent_user == pm) 834 return (true); 835 836 return false; 837 } 838 839 /* 840 * PTE_SYNC_CURRENT: 841 * 842 * Make sure the pte is written out to RAM. 843 * We need to do this for one of two cases: 844 * - We're dealing with the kernel pmap 845 * - There is no pmap active in the cache/tlb. 846 * - The specified pmap is 'active' in the cache/tlb. 847 */ 848 #ifdef PMAP_INCLUDE_PTE_SYNC 849 #define PTE_SYNC_CURRENT(pm, ptep) \ 850 do { \ 851 if (PMAP_NEEDS_PTE_SYNC && \ 852 pmap_is_cached(pm)) \ 853 PTE_SYNC(ptep); \ 854 } while (/*CONSTCOND*/0) 855 #else 856 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 857 #endif 858 859 /* 860 * main pv_entry manipulation functions: 861 * pmap_enter_pv: enter a mapping onto a vm_page list 862 * pmap_remove_pv: remove a mapping from a vm_page list 863 * 864 * NOTE: pmap_enter_pv expects to lock the pvh itself 865 * pmap_remove_pv expects the caller to lock the pvh before calling 866 */ 867 868 /* 869 * pmap_enter_pv: enter a mapping onto a vm_page lst 870 * 871 * => caller should hold the proper lock on pmap_main_lock 872 * => caller should have pmap locked 873 * => we will gain the lock on the vm_page and allocate the new pv_entry 874 * => caller should adjust ptp's wire_count before calling 875 * => caller should not adjust pmap's wire_count 876 */ 877 static void 878 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 879 vaddr_t va, u_int flags) 880 { 881 struct pv_entry **pvp; 882 883 NPDEBUG(PDB_PVDUMP, 884 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 885 886 pv->pv_pmap = pm; 887 pv->pv_va = va; 888 pv->pv_flags = flags; 889 890 pvp = &SLIST_FIRST(&md->pvh_list); 891 #ifdef PMAP_CACHE_VIPT 892 /* 893 * Insert unmanaged entries, writeable first, at the head of 894 * the pv list. 895 */ 896 if (__predict_true((flags & PVF_KENTRY) == 0)) { 897 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 898 pvp = &SLIST_NEXT(*pvp, pv_link); 899 } else if ((flags & PVF_WRITE) == 0) { 900 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 901 pvp = &SLIST_NEXT(*pvp, pv_link); 902 } 903 #endif 904 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 905 *pvp = pv; /* ... locked list */ 906 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 907 #ifdef PMAP_CACHE_VIPT 908 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 909 md->pvh_attrs |= PVF_KMOD; 910 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 911 md->pvh_attrs |= PVF_DIRTY; 912 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 913 #endif 914 if (pm == pmap_kernel()) { 915 PMAPCOUNT(kernel_mappings); 916 if (flags & PVF_WRITE) 917 md->krw_mappings++; 918 else 919 md->kro_mappings++; 920 } else { 921 if (flags & PVF_WRITE) 922 md->urw_mappings++; 923 else 924 md->uro_mappings++; 925 } 926 927 #ifdef PMAP_CACHE_VIPT 928 /* 929 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 930 * do it here as well to keep the mappings & KVF_WRITE consistent. 931 */ 932 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 933 md->pvh_attrs |= PVF_WRITE; 934 } 935 /* 936 * If this is an exec mapping and its the first exec mapping 937 * for this page, make sure to sync the I-cache. 938 */ 939 if (PV_IS_EXEC_P(flags)) { 940 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 941 pmap_syncicache_page(md, pa); 942 PMAPCOUNT(exec_synced_map); 943 } 944 PMAPCOUNT(exec_mappings); 945 } 946 #endif 947 948 PMAPCOUNT(mappings); 949 950 if (pv->pv_flags & PVF_WIRED) 951 ++pm->pm_stats.wired_count; 952 } 953 954 /* 955 * 956 * pmap_find_pv: Find a pv entry 957 * 958 * => caller should hold lock on vm_page 959 */ 960 static inline struct pv_entry * 961 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 962 { 963 struct pv_entry *pv; 964 965 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 966 if (pm == pv->pv_pmap && va == pv->pv_va) 967 break; 968 } 969 970 return (pv); 971 } 972 973 /* 974 * pmap_remove_pv: try to remove a mapping from a pv_list 975 * 976 * => caller should hold proper lock on pmap_main_lock 977 * => pmap should be locked 978 * => caller should hold lock on vm_page [so that attrs can be adjusted] 979 * => caller should adjust ptp's wire_count and free PTP if needed 980 * => caller should NOT adjust pmap's wire_count 981 * => we return the removed pv 982 */ 983 static struct pv_entry * 984 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 985 { 986 struct pv_entry *pv, **prevptr; 987 988 NPDEBUG(PDB_PVDUMP, 989 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 990 991 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 992 pv = *prevptr; 993 994 while (pv) { 995 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 996 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 997 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 998 if (pv->pv_flags & PVF_WIRED) { 999 --pm->pm_stats.wired_count; 1000 } 1001 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1002 if (pm == pmap_kernel()) { 1003 PMAPCOUNT(kernel_unmappings); 1004 if (pv->pv_flags & PVF_WRITE) 1005 md->krw_mappings--; 1006 else 1007 md->kro_mappings--; 1008 } else { 1009 if (pv->pv_flags & PVF_WRITE) 1010 md->urw_mappings--; 1011 else 1012 md->uro_mappings--; 1013 } 1014 1015 PMAPCOUNT(unmappings); 1016 #ifdef PMAP_CACHE_VIPT 1017 if (!(pv->pv_flags & PVF_WRITE)) 1018 break; 1019 /* 1020 * If this page has had an exec mapping, then if 1021 * this was the last mapping, discard the contents, 1022 * otherwise sync the i-cache for this page. 1023 */ 1024 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1025 if (SLIST_EMPTY(&md->pvh_list)) { 1026 md->pvh_attrs &= ~PVF_EXEC; 1027 PMAPCOUNT(exec_discarded_unmap); 1028 } else { 1029 pmap_syncicache_page(md, pa); 1030 PMAPCOUNT(exec_synced_unmap); 1031 } 1032 } 1033 #endif /* PMAP_CACHE_VIPT */ 1034 break; 1035 } 1036 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1037 pv = *prevptr; /* advance */ 1038 } 1039 1040 #ifdef PMAP_CACHE_VIPT 1041 /* 1042 * If we no longer have a WRITEABLE KENTRY at the head of list, 1043 * clear the KMOD attribute from the page. 1044 */ 1045 if (SLIST_FIRST(&md->pvh_list) == NULL 1046 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1047 md->pvh_attrs &= ~PVF_KMOD; 1048 1049 /* 1050 * If this was a writeable page and there are no more writeable 1051 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1052 * the contents to memory. 1053 */ 1054 if (arm_cache_prefer_mask != 0) { 1055 if (md->krw_mappings + md->urw_mappings == 0) 1056 md->pvh_attrs &= ~PVF_WRITE; 1057 PMAP_VALIDATE_MD_PAGE(md); 1058 } 1059 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1060 #endif /* PMAP_CACHE_VIPT */ 1061 1062 return(pv); /* return removed pv */ 1063 } 1064 1065 /* 1066 * 1067 * pmap_modify_pv: Update pv flags 1068 * 1069 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1070 * => caller should NOT adjust pmap's wire_count 1071 * => caller must call pmap_vac_me_harder() if writable status of a page 1072 * may have changed. 1073 * => we return the old flags 1074 * 1075 * Modify a physical-virtual mapping in the pv table 1076 */ 1077 static u_int 1078 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1079 u_int clr_mask, u_int set_mask) 1080 { 1081 struct pv_entry *npv; 1082 u_int flags, oflags; 1083 1084 KASSERT((clr_mask & PVF_KENTRY) == 0); 1085 KASSERT((set_mask & PVF_KENTRY) == 0); 1086 1087 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1088 return (0); 1089 1090 NPDEBUG(PDB_PVDUMP, 1091 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1092 1093 /* 1094 * There is at least one VA mapping this page. 1095 */ 1096 1097 if (clr_mask & (PVF_REF | PVF_MOD)) { 1098 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1099 #ifdef PMAP_CACHE_VIPT 1100 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1101 md->pvh_attrs |= PVF_DIRTY; 1102 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1103 #endif 1104 } 1105 1106 oflags = npv->pv_flags; 1107 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1108 1109 if ((flags ^ oflags) & PVF_WIRED) { 1110 if (flags & PVF_WIRED) 1111 ++pm->pm_stats.wired_count; 1112 else 1113 --pm->pm_stats.wired_count; 1114 } 1115 1116 if ((flags ^ oflags) & PVF_WRITE) { 1117 if (pm == pmap_kernel()) { 1118 if (flags & PVF_WRITE) { 1119 md->krw_mappings++; 1120 md->kro_mappings--; 1121 } else { 1122 md->kro_mappings++; 1123 md->krw_mappings--; 1124 } 1125 } else { 1126 if (flags & PVF_WRITE) { 1127 md->urw_mappings++; 1128 md->uro_mappings--; 1129 } else { 1130 md->uro_mappings++; 1131 md->urw_mappings--; 1132 } 1133 } 1134 } 1135 #ifdef PMAP_CACHE_VIPT 1136 if (arm_cache_prefer_mask != 0) { 1137 if (md->urw_mappings + md->krw_mappings == 0) { 1138 md->pvh_attrs &= ~PVF_WRITE; 1139 } else { 1140 md->pvh_attrs |= PVF_WRITE; 1141 } 1142 } 1143 /* 1144 * We have two cases here: the first is from enter_pv (new exec 1145 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1146 * Since in latter, pmap_enter_pv won't do anything, we just have 1147 * to do what pmap_remove_pv would do. 1148 */ 1149 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1150 || (PV_IS_EXEC_P(md->pvh_attrs) 1151 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1152 pmap_syncicache_page(md, pa); 1153 PMAPCOUNT(exec_synced_remap); 1154 } 1155 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1156 #endif 1157 1158 PMAPCOUNT(remappings); 1159 1160 return (oflags); 1161 } 1162 1163 /* 1164 * Allocate an L1 translation table for the specified pmap. 1165 * This is called at pmap creation time. 1166 */ 1167 static void 1168 pmap_alloc_l1(pmap_t pm) 1169 { 1170 struct l1_ttable *l1; 1171 uint8_t domain; 1172 1173 /* 1174 * Remove the L1 at the head of the LRU list 1175 */ 1176 mutex_spin_enter(&l1_lru_lock); 1177 l1 = TAILQ_FIRST(&l1_lru_list); 1178 KDASSERT(l1 != NULL); 1179 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1180 1181 /* 1182 * Pick the first available domain number, and update 1183 * the link to the next number. 1184 */ 1185 domain = l1->l1_domain_first; 1186 l1->l1_domain_first = l1->l1_domain_free[domain]; 1187 1188 /* 1189 * If there are still free domain numbers in this L1, 1190 * put it back on the TAIL of the LRU list. 1191 */ 1192 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1193 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1194 1195 mutex_spin_exit(&l1_lru_lock); 1196 1197 /* 1198 * Fix up the relevant bits in the pmap structure 1199 */ 1200 pm->pm_l1 = l1; 1201 pm->pm_domain = domain + 1; 1202 } 1203 1204 /* 1205 * Free an L1 translation table. 1206 * This is called at pmap destruction time. 1207 */ 1208 static void 1209 pmap_free_l1(pmap_t pm) 1210 { 1211 struct l1_ttable *l1 = pm->pm_l1; 1212 1213 mutex_spin_enter(&l1_lru_lock); 1214 1215 /* 1216 * If this L1 is currently on the LRU list, remove it. 1217 */ 1218 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1219 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1220 1221 /* 1222 * Free up the domain number which was allocated to the pmap 1223 */ 1224 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1225 l1->l1_domain_first = pmap_domain(pm) - 1; 1226 l1->l1_domain_use_count--; 1227 1228 /* 1229 * The L1 now must have at least 1 free domain, so add 1230 * it back to the LRU list. If the use count is zero, 1231 * put it at the head of the list, otherwise it goes 1232 * to the tail. 1233 */ 1234 if (l1->l1_domain_use_count == 0) 1235 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1236 else 1237 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1238 1239 mutex_spin_exit(&l1_lru_lock); 1240 } 1241 1242 static inline void 1243 pmap_use_l1(pmap_t pm) 1244 { 1245 struct l1_ttable *l1; 1246 1247 /* 1248 * Do nothing if we're in interrupt context. 1249 * Access to an L1 by the kernel pmap must not affect 1250 * the LRU list. 1251 */ 1252 if (cpu_intr_p() || pm == pmap_kernel()) 1253 return; 1254 1255 l1 = pm->pm_l1; 1256 1257 /* 1258 * If the L1 is not currently on the LRU list, just return 1259 */ 1260 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1261 return; 1262 1263 mutex_spin_enter(&l1_lru_lock); 1264 1265 /* 1266 * Check the use count again, now that we've acquired the lock 1267 */ 1268 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1269 mutex_spin_exit(&l1_lru_lock); 1270 return; 1271 } 1272 1273 /* 1274 * Move the L1 to the back of the LRU list 1275 */ 1276 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1277 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1278 1279 mutex_spin_exit(&l1_lru_lock); 1280 } 1281 1282 /* 1283 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1284 * 1285 * Free an L2 descriptor table. 1286 */ 1287 static inline void 1288 #ifndef PMAP_INCLUDE_PTE_SYNC 1289 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1290 #else 1291 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1292 #endif 1293 { 1294 #ifdef PMAP_INCLUDE_PTE_SYNC 1295 #ifdef PMAP_CACHE_VIVT 1296 /* 1297 * Note: With a write-back cache, we may need to sync this 1298 * L2 table before re-using it. 1299 * This is because it may have belonged to a non-current 1300 * pmap, in which case the cache syncs would have been 1301 * skipped for the pages that were being unmapped. If the 1302 * L2 table were then to be immediately re-allocated to 1303 * the *current* pmap, it may well contain stale mappings 1304 * which have not yet been cleared by a cache write-back 1305 * and so would still be visible to the mmu. 1306 */ 1307 if (need_sync) 1308 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1309 #endif /* PMAP_CACHE_VIVT */ 1310 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1311 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1312 } 1313 1314 /* 1315 * Returns a pointer to the L2 bucket associated with the specified pmap 1316 * and VA, or NULL if no L2 bucket exists for the address. 1317 */ 1318 static inline struct l2_bucket * 1319 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1320 { 1321 struct l2_dtable *l2; 1322 struct l2_bucket *l2b; 1323 u_short l1idx; 1324 1325 l1idx = L1_IDX(va); 1326 1327 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1328 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1329 return (NULL); 1330 1331 return (l2b); 1332 } 1333 1334 /* 1335 * Returns a pointer to the L2 bucket associated with the specified pmap 1336 * and VA. 1337 * 1338 * If no L2 bucket exists, perform the necessary allocations to put an L2 1339 * bucket/page table in place. 1340 * 1341 * Note that if a new L2 bucket/page was allocated, the caller *must* 1342 * increment the bucket occupancy counter appropriately *before* 1343 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1344 * the bucket/page in the meantime. 1345 */ 1346 static struct l2_bucket * 1347 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1348 { 1349 struct l2_dtable *l2; 1350 struct l2_bucket *l2b; 1351 u_short l1idx; 1352 1353 l1idx = L1_IDX(va); 1354 1355 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1356 /* 1357 * No mapping at this address, as there is 1358 * no entry in the L1 table. 1359 * Need to allocate a new l2_dtable. 1360 */ 1361 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1362 return (NULL); 1363 1364 /* 1365 * Link it into the parent pmap 1366 */ 1367 pm->pm_l2[L2_IDX(l1idx)] = l2; 1368 } 1369 1370 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1371 1372 /* 1373 * Fetch pointer to the L2 page table associated with the address. 1374 */ 1375 if (l2b->l2b_kva == NULL) { 1376 pt_entry_t *ptep; 1377 1378 /* 1379 * No L2 page table has been allocated. Chances are, this 1380 * is because we just allocated the l2_dtable, above. 1381 */ 1382 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1383 /* 1384 * Oops, no more L2 page tables available at this 1385 * time. We may need to deallocate the l2_dtable 1386 * if we allocated a new one above. 1387 */ 1388 if (l2->l2_occupancy == 0) { 1389 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1390 pmap_free_l2_dtable(l2); 1391 } 1392 return (NULL); 1393 } 1394 1395 l2->l2_occupancy++; 1396 l2b->l2b_kva = ptep; 1397 l2b->l2b_l1idx = l1idx; 1398 } 1399 1400 return (l2b); 1401 } 1402 1403 /* 1404 * One or more mappings in the specified L2 descriptor table have just been 1405 * invalidated. 1406 * 1407 * Garbage collect the metadata and descriptor table itself if necessary. 1408 * 1409 * The pmap lock must be acquired when this is called (not necessary 1410 * for the kernel pmap). 1411 */ 1412 static void 1413 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1414 { 1415 struct l2_dtable *l2; 1416 pd_entry_t *pl1pd, l1pd; 1417 pt_entry_t *ptep; 1418 u_short l1idx; 1419 1420 KDASSERT(count <= l2b->l2b_occupancy); 1421 1422 /* 1423 * Update the bucket's reference count according to how many 1424 * PTEs the caller has just invalidated. 1425 */ 1426 l2b->l2b_occupancy -= count; 1427 1428 /* 1429 * Note: 1430 * 1431 * Level 2 page tables allocated to the kernel pmap are never freed 1432 * as that would require checking all Level 1 page tables and 1433 * removing any references to the Level 2 page table. See also the 1434 * comment elsewhere about never freeing bootstrap L2 descriptors. 1435 * 1436 * We make do with just invalidating the mapping in the L2 table. 1437 * 1438 * This isn't really a big deal in practice and, in fact, leads 1439 * to a performance win over time as we don't need to continually 1440 * alloc/free. 1441 */ 1442 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1443 return; 1444 1445 /* 1446 * There are no more valid mappings in this level 2 page table. 1447 * Go ahead and NULL-out the pointer in the bucket, then 1448 * free the page table. 1449 */ 1450 l1idx = l2b->l2b_l1idx; 1451 ptep = l2b->l2b_kva; 1452 l2b->l2b_kva = NULL; 1453 1454 pl1pd = pmap_l1_kva(pm) + l1idx; 1455 1456 /* 1457 * If the L1 slot matches the pmap's domain 1458 * number, then invalidate it. 1459 */ 1460 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1461 if (l1pd == (L1_C_DOM(pmap_domain(pm)) | L1_TYPE_C)) { 1462 *pl1pd = 0; 1463 PTE_SYNC(pl1pd); 1464 } 1465 1466 /* 1467 * Release the L2 descriptor table back to the pool cache. 1468 */ 1469 #ifndef PMAP_INCLUDE_PTE_SYNC 1470 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1471 #else 1472 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1473 #endif 1474 1475 /* 1476 * Update the reference count in the associated l2_dtable 1477 */ 1478 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1479 if (--l2->l2_occupancy > 0) 1480 return; 1481 1482 /* 1483 * There are no more valid mappings in any of the Level 1 1484 * slots managed by this l2_dtable. Go ahead and NULL-out 1485 * the pointer in the parent pmap and free the l2_dtable. 1486 */ 1487 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1488 pmap_free_l2_dtable(l2); 1489 } 1490 1491 /* 1492 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1493 * structures. 1494 */ 1495 static int 1496 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1497 { 1498 #ifndef PMAP_INCLUDE_PTE_SYNC 1499 struct l2_bucket *l2b; 1500 pt_entry_t *ptep, pte; 1501 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1502 1503 /* 1504 * The mappings for these page tables were initially made using 1505 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1506 * mode will not be right for page table mappings. To avoid 1507 * polluting the pmap_kenter_pa() code with a special case for 1508 * page tables, we simply fix up the cache-mode here if it's not 1509 * correct. 1510 */ 1511 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1512 KDASSERT(l2b != NULL); 1513 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1514 pte = *ptep; 1515 1516 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1517 /* 1518 * Page tables must have the cache-mode set to Write-Thru. 1519 */ 1520 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1521 PTE_SYNC(ptep); 1522 cpu_tlb_flushD_SE(va); 1523 cpu_cpwait(); 1524 } 1525 #endif 1526 1527 memset(v, 0, L2_TABLE_SIZE_REAL); 1528 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1529 return (0); 1530 } 1531 1532 static int 1533 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1534 { 1535 1536 memset(v, 0, sizeof(struct l2_dtable)); 1537 return (0); 1538 } 1539 1540 static int 1541 pmap_pmap_ctor(void *arg, void *v, int flags) 1542 { 1543 1544 memset(v, 0, sizeof(struct pmap)); 1545 return (0); 1546 } 1547 1548 static void 1549 pmap_pinit(pmap_t pm) 1550 { 1551 #ifndef ARM_HAS_VBAR 1552 struct l2_bucket *l2b; 1553 1554 if (vector_page < KERNEL_BASE) { 1555 /* 1556 * Map the vector page. 1557 */ 1558 pmap_enter(pm, vector_page, systempage.pv_pa, 1559 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1560 pmap_update(pm); 1561 1562 pm->pm_pl1vec = pmap_l1_kva(pm) + L1_IDX(vector_page); 1563 l2b = pmap_get_l2_bucket(pm, vector_page); 1564 KDASSERT(l2b != NULL); 1565 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1566 L1_C_DOM(pmap_domain(pm)); 1567 } else 1568 pm->pm_pl1vec = NULL; 1569 #endif 1570 } 1571 1572 #ifdef PMAP_CACHE_VIVT 1573 /* 1574 * Since we have a virtually indexed cache, we may need to inhibit caching if 1575 * there is more than one mapping and at least one of them is writable. 1576 * Since we purge the cache on every context switch, we only need to check for 1577 * other mappings within the same pmap, or kernel_pmap. 1578 * This function is also called when a page is unmapped, to possibly reenable 1579 * caching on any remaining mappings. 1580 * 1581 * The code implements the following logic, where: 1582 * 1583 * KW = # of kernel read/write pages 1584 * KR = # of kernel read only pages 1585 * UW = # of user read/write pages 1586 * UR = # of user read only pages 1587 * 1588 * KC = kernel mapping is cacheable 1589 * UC = user mapping is cacheable 1590 * 1591 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1592 * +--------------------------------------------- 1593 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1594 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1595 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1596 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1597 */ 1598 1599 static const int pmap_vac_flags[4][4] = { 1600 {-1, 0, 0, PVF_KNC}, 1601 {0, 0, PVF_NC, PVF_NC}, 1602 {0, PVF_NC, PVF_NC, PVF_NC}, 1603 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1604 }; 1605 1606 static inline int 1607 pmap_get_vac_flags(const struct vm_page_md *md) 1608 { 1609 int kidx, uidx; 1610 1611 kidx = 0; 1612 if (md->kro_mappings || md->krw_mappings > 1) 1613 kidx |= 1; 1614 if (md->krw_mappings) 1615 kidx |= 2; 1616 1617 uidx = 0; 1618 if (md->uro_mappings || md->urw_mappings > 1) 1619 uidx |= 1; 1620 if (md->urw_mappings) 1621 uidx |= 2; 1622 1623 return (pmap_vac_flags[uidx][kidx]); 1624 } 1625 1626 static inline void 1627 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1628 { 1629 int nattr; 1630 1631 nattr = pmap_get_vac_flags(md); 1632 1633 if (nattr < 0) { 1634 md->pvh_attrs &= ~PVF_NC; 1635 return; 1636 } 1637 1638 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1639 return; 1640 1641 if (pm == pmap_kernel()) 1642 pmap_vac_me_kpmap(md, pa, pm, va); 1643 else 1644 pmap_vac_me_user(md, pa, pm, va); 1645 1646 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1647 } 1648 1649 static void 1650 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1651 { 1652 u_int u_cacheable, u_entries; 1653 struct pv_entry *pv; 1654 pmap_t last_pmap = pm; 1655 1656 /* 1657 * Pass one, see if there are both kernel and user pmaps for 1658 * this page. Calculate whether there are user-writable or 1659 * kernel-writable pages. 1660 */ 1661 u_cacheable = 0; 1662 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1663 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1664 u_cacheable++; 1665 } 1666 1667 u_entries = md->urw_mappings + md->uro_mappings; 1668 1669 /* 1670 * We know we have just been updating a kernel entry, so if 1671 * all user pages are already cacheable, then there is nothing 1672 * further to do. 1673 */ 1674 if (md->k_mappings == 0 && u_cacheable == u_entries) 1675 return; 1676 1677 if (u_entries) { 1678 /* 1679 * Scan over the list again, for each entry, if it 1680 * might not be set correctly, call pmap_vac_me_user 1681 * to recalculate the settings. 1682 */ 1683 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1684 /* 1685 * We know kernel mappings will get set 1686 * correctly in other calls. We also know 1687 * that if the pmap is the same as last_pmap 1688 * then we've just handled this entry. 1689 */ 1690 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1691 continue; 1692 1693 /* 1694 * If there are kernel entries and this page 1695 * is writable but non-cacheable, then we can 1696 * skip this entry also. 1697 */ 1698 if (md->k_mappings && 1699 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1700 (PVF_NC | PVF_WRITE)) 1701 continue; 1702 1703 /* 1704 * Similarly if there are no kernel-writable 1705 * entries and the page is already 1706 * read-only/cacheable. 1707 */ 1708 if (md->krw_mappings == 0 && 1709 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1710 continue; 1711 1712 /* 1713 * For some of the remaining cases, we know 1714 * that we must recalculate, but for others we 1715 * can't tell if they are correct or not, so 1716 * we recalculate anyway. 1717 */ 1718 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1719 } 1720 1721 if (md->k_mappings == 0) 1722 return; 1723 } 1724 1725 pmap_vac_me_user(md, pa, pm, va); 1726 } 1727 1728 static void 1729 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1730 { 1731 pmap_t kpmap = pmap_kernel(); 1732 struct pv_entry *pv, *npv = NULL; 1733 struct l2_bucket *l2b; 1734 pt_entry_t *ptep, pte; 1735 u_int entries = 0; 1736 u_int writable = 0; 1737 u_int cacheable_entries = 0; 1738 u_int kern_cacheable = 0; 1739 u_int other_writable = 0; 1740 1741 /* 1742 * Count mappings and writable mappings in this pmap. 1743 * Include kernel mappings as part of our own. 1744 * Keep a pointer to the first one. 1745 */ 1746 npv = NULL; 1747 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1748 /* Count mappings in the same pmap */ 1749 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1750 if (entries++ == 0) 1751 npv = pv; 1752 1753 /* Cacheable mappings */ 1754 if ((pv->pv_flags & PVF_NC) == 0) { 1755 cacheable_entries++; 1756 if (kpmap == pv->pv_pmap) 1757 kern_cacheable++; 1758 } 1759 1760 /* Writable mappings */ 1761 if (pv->pv_flags & PVF_WRITE) 1762 ++writable; 1763 } else 1764 if (pv->pv_flags & PVF_WRITE) 1765 other_writable = 1; 1766 } 1767 1768 /* 1769 * Enable or disable caching as necessary. 1770 * Note: the first entry might be part of the kernel pmap, 1771 * so we can't assume this is indicative of the state of the 1772 * other (maybe non-kpmap) entries. 1773 */ 1774 if ((entries > 1 && writable) || 1775 (entries > 0 && pm == kpmap && other_writable)) { 1776 if (cacheable_entries == 0) 1777 return; 1778 1779 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1780 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1781 (pv->pv_flags & PVF_NC)) 1782 continue; 1783 1784 pv->pv_flags |= PVF_NC; 1785 1786 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1787 KDASSERT(l2b != NULL); 1788 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1789 pte = *ptep & ~L2_S_CACHE_MASK; 1790 1791 if ((va != pv->pv_va || pm != pv->pv_pmap) 1792 && l2pte_valid(pte)) { 1793 #ifdef PMAP_CACHE_VIVT 1794 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1795 true, pv->pv_flags); 1796 #endif 1797 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1798 pv->pv_flags); 1799 } 1800 1801 *ptep = pte; 1802 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1803 } 1804 cpu_cpwait(); 1805 } else 1806 if (entries > cacheable_entries) { 1807 /* 1808 * Turn cacheing back on for some pages. If it is a kernel 1809 * page, only do so if there are no other writable pages. 1810 */ 1811 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1812 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1813 (kpmap != pv->pv_pmap || other_writable))) 1814 continue; 1815 1816 pv->pv_flags &= ~PVF_NC; 1817 1818 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1819 KDASSERT(l2b != NULL); 1820 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1821 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1822 1823 if (l2pte_valid(pte)) { 1824 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1825 pv->pv_flags); 1826 } 1827 1828 *ptep = pte; 1829 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1830 } 1831 } 1832 } 1833 #endif 1834 1835 #ifdef PMAP_CACHE_VIPT 1836 static void 1837 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1838 { 1839 struct pv_entry *pv; 1840 vaddr_t tst_mask; 1841 bool bad_alias; 1842 struct l2_bucket *l2b; 1843 pt_entry_t *ptep, pte, opte; 1844 const u_int 1845 rw_mappings = md->urw_mappings + md->krw_mappings, 1846 ro_mappings = md->uro_mappings + md->kro_mappings; 1847 1848 /* do we need to do anything? */ 1849 if (arm_cache_prefer_mask == 0) 1850 return; 1851 1852 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1853 md, pm, va)); 1854 1855 KASSERT(!va || pm); 1856 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1857 1858 /* Already a conflict? */ 1859 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1860 /* just an add, things are already non-cached */ 1861 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1862 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1863 bad_alias = false; 1864 if (va) { 1865 PMAPCOUNT(vac_color_none); 1866 bad_alias = true; 1867 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1868 goto fixup; 1869 } 1870 pv = SLIST_FIRST(&md->pvh_list); 1871 /* the list can't be empty because it would be cachable */ 1872 if (md->pvh_attrs & PVF_KMPAGE) { 1873 tst_mask = md->pvh_attrs; 1874 } else { 1875 KASSERT(pv); 1876 tst_mask = pv->pv_va; 1877 pv = SLIST_NEXT(pv, pv_link); 1878 } 1879 /* 1880 * Only check for a bad alias if we have writable mappings. 1881 */ 1882 tst_mask &= arm_cache_prefer_mask; 1883 if (rw_mappings > 0) { 1884 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1885 /* if there's a bad alias, stop checking. */ 1886 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1887 bad_alias = true; 1888 } 1889 md->pvh_attrs |= PVF_WRITE; 1890 if (!bad_alias) 1891 md->pvh_attrs |= PVF_DIRTY; 1892 } else { 1893 /* 1894 * We have only read-only mappings. Let's see if there 1895 * are multiple colors in use or if we mapped a KMPAGE. 1896 * If the latter, we have a bad alias. If the former, 1897 * we need to remember that. 1898 */ 1899 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1900 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1901 if (md->pvh_attrs & PVF_KMPAGE) 1902 bad_alias = true; 1903 break; 1904 } 1905 } 1906 md->pvh_attrs &= ~PVF_WRITE; 1907 /* 1908 * No KMPAGE and we exited early, so we must have 1909 * multiple color mappings. 1910 */ 1911 if (!bad_alias && pv != NULL) 1912 md->pvh_attrs |= PVF_MULTCLR; 1913 } 1914 1915 /* If no conflicting colors, set everything back to cached */ 1916 if (!bad_alias) { 1917 #ifdef DEBUG 1918 if ((md->pvh_attrs & PVF_WRITE) 1919 || ro_mappings < 2) { 1920 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1921 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1922 } 1923 #endif 1924 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1925 md->pvh_attrs |= tst_mask | PVF_COLORED; 1926 /* 1927 * Restore DIRTY bit if page is modified 1928 */ 1929 if (md->pvh_attrs & PVF_DMOD) 1930 md->pvh_attrs |= PVF_DIRTY; 1931 PMAPCOUNT(vac_color_restore); 1932 } else { 1933 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1934 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1935 } 1936 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1937 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1938 } else if (!va) { 1939 KASSERT(pmap_is_page_colored_p(md)); 1940 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1941 || (md->pvh_attrs & PVF_DIRTY)); 1942 if (rw_mappings == 0) { 1943 md->pvh_attrs &= ~PVF_WRITE; 1944 if (ro_mappings == 1 1945 && (md->pvh_attrs & PVF_MULTCLR)) { 1946 /* 1947 * If this is the last readonly mapping 1948 * but it doesn't match the current color 1949 * for the page, change the current color 1950 * to match this last readonly mapping. 1951 */ 1952 pv = SLIST_FIRST(&md->pvh_list); 1953 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1954 & arm_cache_prefer_mask; 1955 if (tst_mask) { 1956 md->pvh_attrs ^= tst_mask; 1957 PMAPCOUNT(vac_color_change); 1958 } 1959 } 1960 } 1961 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1962 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1963 return; 1964 } else if (!pmap_is_page_colored_p(md)) { 1965 /* not colored so we just use its color */ 1966 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1967 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1968 PMAPCOUNT(vac_color_new); 1969 md->pvh_attrs &= PAGE_SIZE - 1; 1970 md->pvh_attrs |= PVF_COLORED 1971 | (va & arm_cache_prefer_mask) 1972 | (rw_mappings > 0 ? PVF_WRITE : 0); 1973 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1974 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1975 return; 1976 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1977 bad_alias = false; 1978 if (rw_mappings > 0) { 1979 /* 1980 * We now have writeable mappings and if we have 1981 * readonly mappings in more than once color, we have 1982 * an aliasing problem. Regardless mark the page as 1983 * writeable. 1984 */ 1985 if (md->pvh_attrs & PVF_MULTCLR) { 1986 if (ro_mappings < 2) { 1987 /* 1988 * If we only have less than two 1989 * read-only mappings, just flush the 1990 * non-primary colors from the cache. 1991 */ 1992 pmap_flush_page(md, pa, 1993 PMAP_FLUSH_SECONDARY); 1994 } else { 1995 bad_alias = true; 1996 } 1997 } 1998 md->pvh_attrs |= PVF_WRITE; 1999 } 2000 /* If no conflicting colors, set everything back to cached */ 2001 if (!bad_alias) { 2002 #ifdef DEBUG 2003 if (rw_mappings > 0 2004 || (md->pvh_attrs & PMAP_KMPAGE)) { 2005 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2006 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2007 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2008 } 2009 #endif 2010 if (SLIST_EMPTY(&md->pvh_list)) 2011 PMAPCOUNT(vac_color_reuse); 2012 else 2013 PMAPCOUNT(vac_color_ok); 2014 2015 /* matching color, just return */ 2016 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2017 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2018 return; 2019 } 2020 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2021 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2022 2023 /* color conflict. evict from cache. */ 2024 2025 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2026 md->pvh_attrs &= ~PVF_COLORED; 2027 md->pvh_attrs |= PVF_NC; 2028 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2029 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2030 PMAPCOUNT(vac_color_erase); 2031 } else if (rw_mappings == 0 2032 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2033 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2034 2035 /* 2036 * If the page has dirty cache lines, clean it. 2037 */ 2038 if (md->pvh_attrs & PVF_DIRTY) 2039 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2040 2041 /* 2042 * If this is the first remapping (we know that there are no 2043 * writeable mappings), then this is a simple color change. 2044 * Otherwise this is a seconary r/o mapping, which means 2045 * we don't have to do anything. 2046 */ 2047 if (ro_mappings == 1) { 2048 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2049 md->pvh_attrs &= PAGE_SIZE - 1; 2050 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2051 PMAPCOUNT(vac_color_change); 2052 } else { 2053 PMAPCOUNT(vac_color_blind); 2054 } 2055 md->pvh_attrs |= PVF_MULTCLR; 2056 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2057 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2058 return; 2059 } else { 2060 if (rw_mappings > 0) 2061 md->pvh_attrs |= PVF_WRITE; 2062 2063 /* color conflict. evict from cache. */ 2064 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2065 2066 /* the list can't be empty because this was a enter/modify */ 2067 pv = SLIST_FIRST(&md->pvh_list); 2068 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2069 KASSERT(pv); 2070 /* 2071 * If there's only one mapped page, change color to the 2072 * page's new color and return. Restore the DIRTY bit 2073 * that was erased by pmap_flush_page. 2074 */ 2075 if (SLIST_NEXT(pv, pv_link) == NULL) { 2076 md->pvh_attrs &= PAGE_SIZE - 1; 2077 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2078 if (md->pvh_attrs & PVF_DMOD) 2079 md->pvh_attrs |= PVF_DIRTY; 2080 PMAPCOUNT(vac_color_change); 2081 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2082 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2083 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2084 return; 2085 } 2086 } 2087 bad_alias = true; 2088 md->pvh_attrs &= ~PVF_COLORED; 2089 md->pvh_attrs |= PVF_NC; 2090 PMAPCOUNT(vac_color_erase); 2091 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2092 } 2093 2094 fixup: 2095 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2096 2097 /* 2098 * Turn cacheing on/off for all pages. 2099 */ 2100 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2101 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2102 KDASSERT(l2b != NULL); 2103 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2104 opte = *ptep; 2105 pte = opte & ~L2_S_CACHE_MASK; 2106 if (bad_alias) { 2107 pv->pv_flags |= PVF_NC; 2108 } else { 2109 pv->pv_flags &= ~PVF_NC; 2110 pte |= pte_l2_s_cache_mode; 2111 } 2112 2113 if (opte == pte) /* only update is there's a change */ 2114 continue; 2115 2116 if (l2pte_valid(pte)) { 2117 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2118 pv->pv_flags); 2119 } 2120 2121 *ptep = pte; 2122 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2123 } 2124 } 2125 #endif /* PMAP_CACHE_VIPT */ 2126 2127 2128 /* 2129 * Modify pte bits for all ptes corresponding to the given physical address. 2130 * We use `maskbits' rather than `clearbits' because we're always passing 2131 * constants and the latter would require an extra inversion at run-time. 2132 */ 2133 static void 2134 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2135 { 2136 struct l2_bucket *l2b; 2137 struct pv_entry *pv; 2138 pt_entry_t *ptep, npte, opte; 2139 pmap_t pm; 2140 vaddr_t va; 2141 u_int oflags; 2142 #ifdef PMAP_CACHE_VIPT 2143 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2144 bool need_syncicache = false; 2145 bool did_syncicache = false; 2146 bool need_vac_me_harder = false; 2147 #endif 2148 2149 NPDEBUG(PDB_BITS, 2150 printf("pmap_clearbit: md %p mask 0x%x\n", 2151 md, maskbits)); 2152 2153 #ifdef PMAP_CACHE_VIPT 2154 /* 2155 * If we might want to sync the I-cache and we've modified it, 2156 * then we know we definitely need to sync or discard it. 2157 */ 2158 if (want_syncicache) 2159 need_syncicache = md->pvh_attrs & PVF_MOD; 2160 #endif 2161 /* 2162 * Clear saved attributes (modify, reference) 2163 */ 2164 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2165 2166 if (SLIST_EMPTY(&md->pvh_list)) { 2167 #ifdef PMAP_CACHE_VIPT 2168 if (need_syncicache) { 2169 /* 2170 * No one has it mapped, so just discard it. The next 2171 * exec remapping will cause it to be synced. 2172 */ 2173 md->pvh_attrs &= ~PVF_EXEC; 2174 PMAPCOUNT(exec_discarded_clearbit); 2175 } 2176 #endif 2177 return; 2178 } 2179 2180 /* 2181 * Loop over all current mappings setting/clearing as appropos 2182 */ 2183 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2184 va = pv->pv_va; 2185 pm = pv->pv_pmap; 2186 oflags = pv->pv_flags; 2187 /* 2188 * Kernel entries are unmanaged and as such not to be changed. 2189 */ 2190 if (oflags & PVF_KENTRY) 2191 continue; 2192 pv->pv_flags &= ~maskbits; 2193 2194 pmap_acquire_pmap_lock(pm); 2195 2196 l2b = pmap_get_l2_bucket(pm, va); 2197 KDASSERT(l2b != NULL); 2198 2199 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2200 npte = opte = *ptep; 2201 2202 NPDEBUG(PDB_BITS, 2203 printf( 2204 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2205 pv, pv->pv_pmap, pv->pv_va, oflags)); 2206 2207 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2208 #ifdef PMAP_CACHE_VIVT 2209 if ((pv->pv_flags & PVF_NC)) { 2210 /* 2211 * Entry is not cacheable: 2212 * 2213 * Don't turn caching on again if this is a 2214 * modified emulation. This would be 2215 * inconsitent with the settings created by 2216 * pmap_vac_me_harder(). Otherwise, it's safe 2217 * to re-enable cacheing. 2218 * 2219 * There's no need to call pmap_vac_me_harder() 2220 * here: all pages are losing their write 2221 * permission. 2222 */ 2223 if (maskbits & PVF_WRITE) { 2224 npte |= pte_l2_s_cache_mode; 2225 pv->pv_flags &= ~PVF_NC; 2226 } 2227 } else 2228 if (l2pte_writable_p(opte)) { 2229 /* 2230 * Entry is writable/cacheable: check if pmap 2231 * is current if it is flush it, otherwise it 2232 * won't be in the cache 2233 */ 2234 pmap_cache_wbinv_page(pm, pv->pv_va, 2235 (maskbits & PVF_REF) != 0, 2236 oflags|PVF_WRITE); 2237 } 2238 #endif 2239 2240 /* make the pte read only */ 2241 npte = l2pte_set_readonly(npte); 2242 2243 if (maskbits & oflags & PVF_WRITE) { 2244 /* 2245 * Keep alias accounting up to date 2246 */ 2247 if (pv->pv_pmap == pmap_kernel()) { 2248 md->krw_mappings--; 2249 md->kro_mappings++; 2250 } else { 2251 md->urw_mappings--; 2252 md->uro_mappings++; 2253 } 2254 #ifdef PMAP_CACHE_VIPT 2255 if (arm_cache_prefer_mask != 0) { 2256 if (md->urw_mappings + md->krw_mappings == 0) { 2257 md->pvh_attrs &= ~PVF_WRITE; 2258 } else { 2259 PMAP_VALIDATE_MD_PAGE(md); 2260 } 2261 } 2262 if (want_syncicache) 2263 need_syncicache = true; 2264 need_vac_me_harder = true; 2265 #endif 2266 } 2267 } 2268 2269 if (maskbits & PVF_REF) { 2270 if ((pv->pv_flags & PVF_NC) == 0 2271 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2272 && l2pte_valid(npte)) { 2273 #ifdef PMAP_CACHE_VIVT 2274 /* 2275 * Check npte here; we may have already 2276 * done the wbinv above, and the validity 2277 * of the PTE is the same for opte and 2278 * npte. 2279 */ 2280 pmap_cache_wbinv_page(pm, pv->pv_va, true, 2281 oflags); 2282 #endif 2283 } 2284 2285 /* 2286 * Make the PTE invalid so that we will take a 2287 * page fault the next time the mapping is 2288 * referenced. 2289 */ 2290 npte &= ~L2_TYPE_MASK; 2291 npte |= L2_TYPE_INV; 2292 } 2293 2294 if (npte != opte) { 2295 *ptep = npte; 2296 PTE_SYNC(ptep); 2297 /* Flush the TLB entry if a current pmap. */ 2298 pmap_tlb_flush_SE(pm, pv->pv_va, oflags); 2299 } 2300 2301 pmap_release_pmap_lock(pm); 2302 2303 NPDEBUG(PDB_BITS, 2304 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2305 pm, va, opte, npte)); 2306 } 2307 2308 #ifdef PMAP_CACHE_VIPT 2309 /* 2310 * If we need to sync the I-cache and we haven't done it yet, do it. 2311 */ 2312 if (need_syncicache && !did_syncicache) { 2313 pmap_syncicache_page(md, pa); 2314 PMAPCOUNT(exec_synced_clearbit); 2315 } 2316 /* 2317 * If we are changing this to read-only, we need to call vac_me_harder 2318 * so we can change all the read-only pages to cacheable. We pretend 2319 * this as a page deletion. 2320 */ 2321 if (need_vac_me_harder) { 2322 if (md->pvh_attrs & PVF_NC) 2323 pmap_vac_me_harder(md, pa, NULL, 0); 2324 } 2325 #endif 2326 } 2327 2328 /* 2329 * pmap_clean_page() 2330 * 2331 * This is a local function used to work out the best strategy to clean 2332 * a single page referenced by its entry in the PV table. It's used by 2333 * pmap_copy_page, pmap_zero page and maybe some others later on. 2334 * 2335 * Its policy is effectively: 2336 * o If there are no mappings, we don't bother doing anything with the cache. 2337 * o If there is one mapping, we clean just that page. 2338 * o If there are multiple mappings, we clean the entire cache. 2339 * 2340 * So that some functions can be further optimised, it returns 0 if it didn't 2341 * clean the entire cache, or 1 if it did. 2342 * 2343 * XXX One bug in this routine is that if the pv_entry has a single page 2344 * mapped at 0x00000000 a whole cache clean will be performed rather than 2345 * just the 1 page. Since this should not occur in everyday use and if it does 2346 * it will just result in not the most efficient clean for the page. 2347 */ 2348 #ifdef PMAP_CACHE_VIVT 2349 static int 2350 pmap_clean_page(struct pv_entry *pv, bool is_src) 2351 { 2352 pmap_t pm_to_clean = NULL; 2353 struct pv_entry *npv; 2354 u_int cache_needs_cleaning = 0; 2355 u_int flags = 0; 2356 vaddr_t page_to_clean = 0; 2357 2358 if (pv == NULL) { 2359 /* nothing mapped in so nothing to flush */ 2360 return (0); 2361 } 2362 2363 /* 2364 * Since we flush the cache each time we change to a different 2365 * user vmspace, we only need to flush the page if it is in the 2366 * current pmap. 2367 */ 2368 2369 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2370 if (pmap_is_current(npv->pv_pmap)) { 2371 flags |= npv->pv_flags; 2372 /* 2373 * The page is mapped non-cacheable in 2374 * this map. No need to flush the cache. 2375 */ 2376 if (npv->pv_flags & PVF_NC) { 2377 #ifdef DIAGNOSTIC 2378 if (cache_needs_cleaning) 2379 panic("pmap_clean_page: " 2380 "cache inconsistency"); 2381 #endif 2382 break; 2383 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2384 continue; 2385 if (cache_needs_cleaning) { 2386 page_to_clean = 0; 2387 break; 2388 } else { 2389 page_to_clean = npv->pv_va; 2390 pm_to_clean = npv->pv_pmap; 2391 } 2392 cache_needs_cleaning = 1; 2393 } 2394 } 2395 2396 if (page_to_clean) { 2397 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2398 !is_src, flags | PVF_REF); 2399 } else if (cache_needs_cleaning) { 2400 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2401 2402 pmap_cache_wbinv_all(pm, flags); 2403 return (1); 2404 } 2405 return (0); 2406 } 2407 #endif 2408 2409 #ifdef PMAP_CACHE_VIPT 2410 /* 2411 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2412 * right cache alias to make sure we flush the right stuff. 2413 */ 2414 void 2415 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2416 { 2417 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2418 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2419 2420 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2421 md, md->pvh_attrs)); 2422 /* 2423 * No need to clean the page if it's non-cached. 2424 */ 2425 if (md->pvh_attrs & PVF_NC) 2426 return; 2427 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2428 2429 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, PVF_REF | PVF_EXEC); 2430 /* 2431 * Set up a PTE with the right coloring to flush existing cache lines. 2432 */ 2433 *ptep = L2_S_PROTO | 2434 pa 2435 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2436 | pte_l2_s_cache_mode; 2437 PTE_SYNC(ptep); 2438 2439 /* 2440 * Flush it. 2441 */ 2442 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2443 /* 2444 * Unmap the page. 2445 */ 2446 *ptep = 0; 2447 PTE_SYNC(ptep); 2448 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, PVF_REF | PVF_EXEC); 2449 2450 md->pvh_attrs |= PVF_EXEC; 2451 PMAPCOUNT(exec_synced); 2452 } 2453 2454 void 2455 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2456 { 2457 vsize_t va_offset, end_va; 2458 bool wbinv_p; 2459 2460 if (arm_cache_prefer_mask == 0) 2461 return; 2462 2463 switch (flush) { 2464 case PMAP_FLUSH_PRIMARY: 2465 if (md->pvh_attrs & PVF_MULTCLR) { 2466 va_offset = 0; 2467 end_va = arm_cache_prefer_mask; 2468 md->pvh_attrs &= ~PVF_MULTCLR; 2469 PMAPCOUNT(vac_flush_lots); 2470 } else { 2471 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2472 end_va = va_offset; 2473 PMAPCOUNT(vac_flush_one); 2474 } 2475 /* 2476 * Mark that the page is no longer dirty. 2477 */ 2478 md->pvh_attrs &= ~PVF_DIRTY; 2479 wbinv_p = true; 2480 break; 2481 case PMAP_FLUSH_SECONDARY: 2482 va_offset = 0; 2483 end_va = arm_cache_prefer_mask; 2484 wbinv_p = true; 2485 md->pvh_attrs &= ~PVF_MULTCLR; 2486 PMAPCOUNT(vac_flush_lots); 2487 break; 2488 case PMAP_CLEAN_PRIMARY: 2489 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2490 end_va = va_offset; 2491 wbinv_p = false; 2492 /* 2493 * Mark that the page is no longer dirty. 2494 */ 2495 if ((md->pvh_attrs & PVF_DMOD) == 0) 2496 md->pvh_attrs &= ~PVF_DIRTY; 2497 PMAPCOUNT(vac_clean_one); 2498 break; 2499 default: 2500 return; 2501 } 2502 2503 KASSERT(!(md->pvh_attrs & PVF_NC)); 2504 2505 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2506 md, md->pvh_attrs)); 2507 2508 const size_t scache_line_size = arm_scache.dcache_line_size; 2509 2510 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2511 const size_t pte_offset = va_offset >> PGSHIFT; 2512 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2513 const pt_entry_t oldpte = *ptep; 2514 2515 if (flush == PMAP_FLUSH_SECONDARY 2516 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2517 continue; 2518 2519 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, 2520 PVF_REF | PVF_EXEC); 2521 /* 2522 * Set up a PTE with the right coloring to flush 2523 * existing cache entries. 2524 */ 2525 *ptep = L2_S_PROTO 2526 | pa 2527 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2528 | pte_l2_s_cache_mode; 2529 PTE_SYNC(ptep); 2530 2531 /* 2532 * Flush it. 2533 */ 2534 vaddr_t va = cdstp + va_offset; 2535 if (scache_line_size != 0) { 2536 cpu_dcache_wb_range(va, PAGE_SIZE); 2537 if (wbinv_p) { 2538 cpu_sdcache_wbinv_range(va, pa, PAGE_SIZE); 2539 cpu_dcache_inv_range(va, PAGE_SIZE); 2540 } else { 2541 cpu_sdcache_wb_range(va, pa, PAGE_SIZE); 2542 } 2543 } else { 2544 if (wbinv_p) { 2545 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2546 } else { 2547 cpu_dcache_wb_range(va, PAGE_SIZE); 2548 } 2549 } 2550 2551 /* 2552 * Restore the page table entry since we might have interrupted 2553 * pmap_zero_page or pmap_copy_page which was already using 2554 * this pte. 2555 */ 2556 *ptep = oldpte; 2557 PTE_SYNC(ptep); 2558 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, 2559 PVF_REF | PVF_EXEC); 2560 } 2561 } 2562 #endif /* PMAP_CACHE_VIPT */ 2563 2564 /* 2565 * Routine: pmap_page_remove 2566 * Function: 2567 * Removes this physical page from 2568 * all physical maps in which it resides. 2569 * Reflects back modify bits to the pager. 2570 */ 2571 static void 2572 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2573 { 2574 struct l2_bucket *l2b; 2575 struct pv_entry *pv, *npv, **pvp; 2576 pmap_t pm; 2577 pt_entry_t *ptep; 2578 bool flush; 2579 u_int flags; 2580 2581 NPDEBUG(PDB_FOLLOW, 2582 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2583 pa)); 2584 2585 pv = SLIST_FIRST(&md->pvh_list); 2586 if (pv == NULL) { 2587 #ifdef PMAP_CACHE_VIPT 2588 /* 2589 * We *know* the page contents are about to be replaced. 2590 * Discard the exec contents 2591 */ 2592 if (PV_IS_EXEC_P(md->pvh_attrs)) 2593 PMAPCOUNT(exec_discarded_page_protect); 2594 md->pvh_attrs &= ~PVF_EXEC; 2595 PMAP_VALIDATE_MD_PAGE(md); 2596 #endif 2597 return; 2598 } 2599 #ifdef PMAP_CACHE_VIPT 2600 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2601 #endif 2602 2603 /* 2604 * Clear alias counts 2605 */ 2606 #ifdef PMAP_CACHE_VIVT 2607 md->k_mappings = 0; 2608 #endif 2609 md->urw_mappings = md->uro_mappings = 0; 2610 2611 flush = false; 2612 flags = 0; 2613 2614 #ifdef PMAP_CACHE_VIVT 2615 pmap_clean_page(pv, false); 2616 #endif 2617 2618 pvp = &SLIST_FIRST(&md->pvh_list); 2619 while (pv) { 2620 pm = pv->pv_pmap; 2621 npv = SLIST_NEXT(pv, pv_link); 2622 if (flush == false && pmap_is_current(pm)) 2623 flush = true; 2624 2625 if (pm == pmap_kernel()) { 2626 #ifdef PMAP_CACHE_VIPT 2627 /* 2628 * If this was unmanaged mapping, it must be preserved. 2629 * Move it back on the list and advance the end-of-list 2630 * pointer. 2631 */ 2632 if (pv->pv_flags & PVF_KENTRY) { 2633 *pvp = pv; 2634 pvp = &SLIST_NEXT(pv, pv_link); 2635 pv = npv; 2636 continue; 2637 } 2638 if (pv->pv_flags & PVF_WRITE) 2639 md->krw_mappings--; 2640 else 2641 md->kro_mappings--; 2642 #endif 2643 PMAPCOUNT(kernel_unmappings); 2644 } 2645 PMAPCOUNT(unmappings); 2646 2647 pmap_acquire_pmap_lock(pm); 2648 2649 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2650 KDASSERT(l2b != NULL); 2651 2652 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2653 2654 /* 2655 * Update statistics 2656 */ 2657 --pm->pm_stats.resident_count; 2658 2659 /* Wired bit */ 2660 if (pv->pv_flags & PVF_WIRED) 2661 --pm->pm_stats.wired_count; 2662 2663 flags |= pv->pv_flags; 2664 2665 /* 2666 * Invalidate the PTEs. 2667 */ 2668 *ptep = 0; 2669 PTE_SYNC_CURRENT(pm, ptep); 2670 pmap_free_l2_bucket(pm, l2b, 1); 2671 2672 pool_put(&pmap_pv_pool, pv); 2673 pv = npv; 2674 /* 2675 * if we reach the end of the list and there are still 2676 * mappings, they might be able to be cached now. 2677 */ 2678 if (pv == NULL) { 2679 *pvp = NULL; 2680 if (!SLIST_EMPTY(&md->pvh_list)) 2681 pmap_vac_me_harder(md, pa, pm, 0); 2682 } 2683 pmap_release_pmap_lock(pm); 2684 } 2685 #ifdef PMAP_CACHE_VIPT 2686 /* 2687 * Its EXEC cache is now gone. 2688 */ 2689 if (PV_IS_EXEC_P(md->pvh_attrs)) 2690 PMAPCOUNT(exec_discarded_page_protect); 2691 md->pvh_attrs &= ~PVF_EXEC; 2692 KASSERT(md->urw_mappings == 0); 2693 KASSERT(md->uro_mappings == 0); 2694 if (arm_cache_prefer_mask != 0) { 2695 if (md->krw_mappings == 0) 2696 md->pvh_attrs &= ~PVF_WRITE; 2697 PMAP_VALIDATE_MD_PAGE(md); 2698 } 2699 #endif 2700 2701 if (flush) { 2702 /* 2703 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2704 * would need a subsequent call to pmap_update() to ensure 2705 * curpm->pm_cstate.cs_all is reset. Our callers are not 2706 * required to do that (see pmap(9)), so we can't modify 2707 * the current pmap's state. 2708 */ 2709 if (PV_BEEN_EXECD(flags)) 2710 cpu_tlb_flushID(); 2711 else 2712 cpu_tlb_flushD(); 2713 } 2714 cpu_cpwait(); 2715 } 2716 2717 /* 2718 * pmap_t pmap_create(void) 2719 * 2720 * Create a new pmap structure from scratch. 2721 */ 2722 pmap_t 2723 pmap_create(void) 2724 { 2725 pmap_t pm; 2726 2727 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2728 2729 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2730 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2731 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2732 2733 pm->pm_stats.wired_count = 0; 2734 pm->pm_stats.resident_count = 1; 2735 pm->pm_cstate.cs_all = 0; 2736 pmap_alloc_l1(pm); 2737 2738 /* 2739 * Note: The pool cache ensures that the pm_l2[] array is already 2740 * initialised to zero. 2741 */ 2742 2743 pmap_pinit(pm); 2744 2745 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2746 2747 return (pm); 2748 } 2749 2750 u_int 2751 arm32_mmap_flags(paddr_t pa) 2752 { 2753 /* 2754 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 2755 * and we're using the upper bits in page numbers to pass flags around 2756 * so we might as well use the same bits 2757 */ 2758 return (u_int)pa & PMAP_MD_MASK; 2759 } 2760 /* 2761 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2762 * u_int flags) 2763 * 2764 * Insert the given physical page (p) at 2765 * the specified virtual address (v) in the 2766 * target physical map with the protection requested. 2767 * 2768 * NB: This is the only routine which MAY NOT lazy-evaluate 2769 * or lose information. That is, this routine must actually 2770 * insert this page into the given map NOW. 2771 */ 2772 int 2773 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2774 { 2775 struct l2_bucket *l2b; 2776 struct vm_page *pg, *opg; 2777 struct pv_entry *pv; 2778 pt_entry_t *ptep, npte, opte; 2779 u_int nflags; 2780 u_int oflags; 2781 #ifdef ARM_HAS_VBAR 2782 const bool vector_page_p = false; 2783 #else 2784 const bool vector_page_p = (va == vector_page); 2785 #endif 2786 2787 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2788 2789 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2790 KDASSERT(((va | pa) & PGOFSET) == 0); 2791 2792 /* 2793 * Get a pointer to the page. Later on in this function, we 2794 * test for a managed page by checking pg != NULL. 2795 */ 2796 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2797 2798 nflags = 0; 2799 if (prot & VM_PROT_WRITE) 2800 nflags |= PVF_WRITE; 2801 if (prot & VM_PROT_EXECUTE) 2802 nflags |= PVF_EXEC; 2803 if (flags & PMAP_WIRED) 2804 nflags |= PVF_WIRED; 2805 2806 pmap_acquire_pmap_lock(pm); 2807 2808 /* 2809 * Fetch the L2 bucket which maps this page, allocating one if 2810 * necessary for user pmaps. 2811 */ 2812 if (pm == pmap_kernel()) 2813 l2b = pmap_get_l2_bucket(pm, va); 2814 else 2815 l2b = pmap_alloc_l2_bucket(pm, va); 2816 if (l2b == NULL) { 2817 if (flags & PMAP_CANFAIL) { 2818 pmap_release_pmap_lock(pm); 2819 return (ENOMEM); 2820 } 2821 panic("pmap_enter: failed to allocate L2 bucket"); 2822 } 2823 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2824 opte = *ptep; 2825 npte = pa; 2826 oflags = 0; 2827 2828 if (opte) { 2829 /* 2830 * There is already a mapping at this address. 2831 * If the physical address is different, lookup the 2832 * vm_page. 2833 */ 2834 if (l2pte_pa(opte) != pa) 2835 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2836 else 2837 opg = pg; 2838 } else 2839 opg = NULL; 2840 2841 if (pg) { 2842 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2843 2844 /* 2845 * This is to be a managed mapping. 2846 */ 2847 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 2848 /* 2849 * - The access type indicates that we don't need 2850 * to do referenced emulation. 2851 * OR 2852 * - The physical page has already been referenced 2853 * so no need to re-do referenced emulation here. 2854 */ 2855 npte |= l2pte_set_readonly(L2_S_PROTO); 2856 2857 nflags |= PVF_REF; 2858 2859 if ((prot & VM_PROT_WRITE) != 0 && 2860 ((flags & VM_PROT_WRITE) != 0 || 2861 (md->pvh_attrs & PVF_MOD) != 0)) { 2862 /* 2863 * This is a writable mapping, and the 2864 * page's mod state indicates it has 2865 * already been modified. Make it 2866 * writable from the outset. 2867 */ 2868 npte = l2pte_set_writable(npte); 2869 nflags |= PVF_MOD; 2870 } 2871 } else { 2872 /* 2873 * Need to do page referenced emulation. 2874 */ 2875 npte |= L2_TYPE_INV; 2876 } 2877 2878 if (flags & ARM32_MMAP_WRITECOMBINE) { 2879 npte |= pte_l2_s_wc_mode; 2880 } else 2881 npte |= pte_l2_s_cache_mode; 2882 2883 if (pg == opg) { 2884 /* 2885 * We're changing the attrs of an existing mapping. 2886 */ 2887 #ifdef MULTIPROCESSOR 2888 KASSERT(uvm_page_locked_p(pg)); 2889 #endif 2890 oflags = pmap_modify_pv(md, pa, pm, va, 2891 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2892 PVF_MOD | PVF_REF, nflags); 2893 2894 #ifdef PMAP_CACHE_VIVT 2895 /* 2896 * We may need to flush the cache if we're 2897 * doing rw-ro... 2898 */ 2899 if (pm->pm_cstate.cs_cache_d && 2900 (oflags & PVF_NC) == 0 && 2901 l2pte_writable_p(opte) && 2902 (prot & VM_PROT_WRITE) == 0) 2903 cpu_dcache_wb_range(va, PAGE_SIZE); 2904 #endif 2905 } else { 2906 /* 2907 * New mapping, or changing the backing page 2908 * of an existing mapping. 2909 */ 2910 if (opg) { 2911 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2912 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2913 2914 /* 2915 * Replacing an existing mapping with a new one. 2916 * It is part of our managed memory so we 2917 * must remove it from the PV list 2918 */ 2919 #ifdef MULTIPROCESSOR 2920 KASSERT(uvm_page_locked_p(opg)); 2921 #endif 2922 pv = pmap_remove_pv(omd, opa, pm, va); 2923 pmap_vac_me_harder(omd, opa, pm, 0); 2924 oflags = pv->pv_flags; 2925 2926 #ifdef PMAP_CACHE_VIVT 2927 /* 2928 * If the old mapping was valid (ref/mod 2929 * emulation creates 'invalid' mappings 2930 * initially) then make sure to frob 2931 * the cache. 2932 */ 2933 if (!(oflags & PVF_NC) && l2pte_valid(opte)) { 2934 pmap_cache_wbinv_page(pm, va, true, 2935 oflags); 2936 } 2937 #endif 2938 } else 2939 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2940 if ((flags & PMAP_CANFAIL) == 0) 2941 panic("pmap_enter: no pv entries"); 2942 2943 if (pm != pmap_kernel()) 2944 pmap_free_l2_bucket(pm, l2b, 0); 2945 pmap_release_pmap_lock(pm); 2946 NPDEBUG(PDB_ENTER, 2947 printf("pmap_enter: ENOMEM\n")); 2948 return (ENOMEM); 2949 } 2950 2951 #ifdef MULTIPROCESSOR 2952 KASSERT(uvm_page_locked_p(pg)); 2953 #endif 2954 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2955 } 2956 } else { 2957 /* 2958 * We're mapping an unmanaged page. 2959 * These are always readable, and possibly writable, from 2960 * the get go as we don't need to track ref/mod status. 2961 */ 2962 npte |= l2pte_set_readonly(L2_S_PROTO); 2963 if (prot & VM_PROT_WRITE) 2964 npte = l2pte_set_writable(npte); 2965 2966 /* 2967 * Make sure the vector table is mapped cacheable 2968 */ 2969 if ((vector_page_p && pm != pmap_kernel()) 2970 || (flags & ARM32_MMAP_CACHEABLE)) { 2971 npte |= pte_l2_s_cache_mode; 2972 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 2973 npte |= pte_l2_s_wc_mode; 2974 } 2975 if (opg) { 2976 /* 2977 * Looks like there's an existing 'managed' mapping 2978 * at this address. 2979 */ 2980 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2981 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2982 2983 #ifdef MULTIPROCESSOR 2984 KASSERT(uvm_page_locked_p(opg)); 2985 #endif 2986 pv = pmap_remove_pv(omd, opa, pm, va); 2987 pmap_vac_me_harder(omd, opa, pm, 0); 2988 oflags = pv->pv_flags; 2989 2990 #ifdef PMAP_CACHE_VIVT 2991 if (!(oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2992 pmap_cache_wbinv_page(pm, va, true, oflags); 2993 } 2994 #endif 2995 pool_put(&pmap_pv_pool, pv); 2996 } 2997 } 2998 2999 /* 3000 * Make sure userland mappings get the right permissions 3001 */ 3002 if (!vector_page_p && pm != pmap_kernel()) { 3003 npte |= L2_S_PROT_U; 3004 } 3005 3006 /* 3007 * Keep the stats up to date 3008 */ 3009 if (opte == 0) { 3010 l2b->l2b_occupancy++; 3011 pm->pm_stats.resident_count++; 3012 } 3013 3014 NPDEBUG(PDB_ENTER, 3015 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3016 3017 /* 3018 * If this is just a wiring change, the two PTEs will be 3019 * identical, so there's no need to update the page table. 3020 */ 3021 if (npte != opte) { 3022 bool is_cached = pmap_is_cached(pm); 3023 3024 *ptep = npte; 3025 PTE_SYNC(ptep); 3026 if (is_cached) { 3027 /* 3028 * We only need to frob the cache/tlb if this pmap 3029 * is current 3030 */ 3031 if (!vector_page_p && l2pte_valid(npte)) { 3032 /* 3033 * This mapping is likely to be accessed as 3034 * soon as we return to userland. Fix up the 3035 * L1 entry to avoid taking another 3036 * page/domain fault. 3037 */ 3038 pd_entry_t *pl1pd, l1pd; 3039 3040 pl1pd = pmap_l1_kva(pm) + L1_IDX(va); 3041 l1pd = l2b->l2b_phys | L1_C_DOM(pmap_domain(pm)) | 3042 L1_C_PROTO; 3043 if (*pl1pd != l1pd) { 3044 *pl1pd = l1pd; 3045 PTE_SYNC(pl1pd); 3046 } 3047 } 3048 } 3049 3050 pmap_tlb_flush_SE(pm, va, oflags); 3051 3052 NPDEBUG(PDB_ENTER, 3053 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3054 is_cached, pm->pm_cstate.cs_all)); 3055 3056 if (pg != NULL) { 3057 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3058 3059 #ifdef MULTIPROCESSOR 3060 KASSERT(uvm_page_locked_p(pg)); 3061 #endif 3062 pmap_vac_me_harder(md, pa, pm, va); 3063 } 3064 } 3065 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3066 if (pg) { 3067 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3068 3069 #ifdef MULTIPROCESSOR 3070 KASSERT(uvm_page_locked_p(pg)); 3071 #endif 3072 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3073 PMAP_VALIDATE_MD_PAGE(md); 3074 } 3075 #endif 3076 3077 pmap_release_pmap_lock(pm); 3078 3079 return (0); 3080 } 3081 3082 /* 3083 * pmap_remove() 3084 * 3085 * pmap_remove is responsible for nuking a number of mappings for a range 3086 * of virtual address space in the current pmap. To do this efficiently 3087 * is interesting, because in a number of cases a wide virtual address 3088 * range may be supplied that contains few actual mappings. So, the 3089 * optimisations are: 3090 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3091 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3092 * maybe do just a partial cache clean. This path of execution is 3093 * complicated by the fact that the cache must be flushed _before_ 3094 * the PTE is nuked, being a VAC :-) 3095 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3096 * all invalidations until pmap_update(), since pmap_remove_all() has 3097 * already flushed the cache. 3098 * 4. Maybe later fast-case a single page, but I don't think this is 3099 * going to make _that_ much difference overall. 3100 */ 3101 3102 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3103 3104 void 3105 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3106 { 3107 struct l2_bucket *l2b; 3108 vaddr_t next_bucket; 3109 pt_entry_t *ptep; 3110 u_int cleanlist_idx, total, cnt; 3111 struct { 3112 vaddr_t va; 3113 pt_entry_t *ptep; 3114 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3115 u_int mappings; 3116 3117 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3118 "eva=%08lx\n", pm, sva, eva)); 3119 3120 /* 3121 * we lock in the pmap => pv_head direction 3122 */ 3123 pmap_acquire_pmap_lock(pm); 3124 3125 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3126 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3127 if (pm->pm_cstate.cs_tlb == 0) 3128 pm->pm_remove_all = true; 3129 } else 3130 cleanlist_idx = 0; 3131 3132 total = 0; 3133 3134 while (sva < eva) { 3135 /* 3136 * Do one L2 bucket's worth at a time. 3137 */ 3138 next_bucket = L2_NEXT_BUCKET(sva); 3139 if (next_bucket > eva) 3140 next_bucket = eva; 3141 3142 l2b = pmap_get_l2_bucket(pm, sva); 3143 if (l2b == NULL) { 3144 sva = next_bucket; 3145 continue; 3146 } 3147 3148 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3149 3150 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3151 struct vm_page *pg; 3152 pt_entry_t pte; 3153 paddr_t pa; 3154 3155 pte = *ptep; 3156 3157 if (pte == 0) { 3158 /* Nothing here, move along */ 3159 continue; 3160 } 3161 3162 pa = l2pte_pa(pte); 3163 u_int flags = PVF_REF; 3164 3165 /* 3166 * Update flags. In a number of circumstances, 3167 * we could cluster a lot of these and do a 3168 * number of sequential pages in one go. 3169 */ 3170 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3171 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3172 struct pv_entry *pv; 3173 3174 #ifdef MULTIPROCESSOR 3175 KASSERT(uvm_page_locked_p(pg)); 3176 #endif 3177 pv = pmap_remove_pv(md, pa, pm, sva); 3178 pmap_vac_me_harder(md, pa, pm, 0); 3179 if (pv != NULL) { 3180 flags = pv->pv_flags; 3181 pool_put(&pmap_pv_pool, pv); 3182 } 3183 } 3184 mappings++; 3185 3186 if (!l2pte_valid(pte)) { 3187 /* 3188 * Ref/Mod emulation is still active for this 3189 * mapping, therefore it is has not yet been 3190 * accessed. No need to frob the cache/tlb. 3191 */ 3192 *ptep = 0; 3193 PTE_SYNC_CURRENT(pm, ptep); 3194 continue; 3195 } 3196 3197 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3198 /* Add to the clean list. */ 3199 cleanlist[cleanlist_idx].ptep = ptep; 3200 cleanlist[cleanlist_idx].va = 3201 sva | (flags & PVF_EXEC); 3202 cleanlist_idx++; 3203 } else 3204 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3205 /* Nuke everything if needed. */ 3206 #ifdef PMAP_CACHE_VIVT 3207 pmap_cache_wbinv_all(pm, PVF_EXEC); 3208 #endif 3209 pmap_tlb_flushID(pm); 3210 3211 /* 3212 * Roll back the previous PTE list, 3213 * and zero out the current PTE. 3214 */ 3215 for (cnt = 0; 3216 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3217 *cleanlist[cnt].ptep = 0; 3218 PTE_SYNC(cleanlist[cnt].ptep); 3219 } 3220 *ptep = 0; 3221 PTE_SYNC(ptep); 3222 cleanlist_idx++; 3223 pm->pm_remove_all = true; 3224 } else { 3225 *ptep = 0; 3226 PTE_SYNC(ptep); 3227 if (pm->pm_remove_all == false) { 3228 pmap_tlb_flush_SE(pm, sva, flags); 3229 } 3230 } 3231 } 3232 3233 /* 3234 * Deal with any left overs 3235 */ 3236 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3237 total += cleanlist_idx; 3238 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3239 vaddr_t va = cleanlist[cnt].va; 3240 if (pm->pm_cstate.cs_all != 0) { 3241 vaddr_t clva = va & ~PAGE_MASK; 3242 u_int flags = va & PVF_EXEC; 3243 #ifdef PMAP_CACHE_VIVT 3244 pmap_cache_wbinv_page(pm, clva, true, 3245 PVF_REF | PVF_WRITE | flags); 3246 #endif 3247 pmap_tlb_flush_SE(pm, clva, 3248 PVF_REF | flags); 3249 } 3250 *cleanlist[cnt].ptep = 0; 3251 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3252 } 3253 3254 /* 3255 * If it looks like we're removing a whole bunch 3256 * of mappings, it's faster to just write-back 3257 * the whole cache now and defer TLB flushes until 3258 * pmap_update() is called. 3259 */ 3260 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3261 cleanlist_idx = 0; 3262 else { 3263 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3264 #ifdef PMAP_CACHE_VIVT 3265 pmap_cache_wbinv_all(pm, PVF_EXEC); 3266 #endif 3267 pm->pm_remove_all = true; 3268 } 3269 } 3270 3271 pmap_free_l2_bucket(pm, l2b, mappings); 3272 pm->pm_stats.resident_count -= mappings; 3273 } 3274 3275 pmap_release_pmap_lock(pm); 3276 } 3277 3278 #ifdef PMAP_CACHE_VIPT 3279 static struct pv_entry * 3280 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3281 { 3282 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3283 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3284 struct pv_entry *pv; 3285 3286 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3287 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3288 3289 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3290 KASSERT(pv); 3291 KASSERT(pv->pv_flags & PVF_KENTRY); 3292 3293 /* 3294 * If we are removing a writeable mapping to a cached exec page, 3295 * if it's the last mapping then clear it execness other sync 3296 * the page to the icache. 3297 */ 3298 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3299 && (pv->pv_flags & PVF_WRITE) != 0) { 3300 if (SLIST_EMPTY(&md->pvh_list)) { 3301 md->pvh_attrs &= ~PVF_EXEC; 3302 PMAPCOUNT(exec_discarded_kremove); 3303 } else { 3304 pmap_syncicache_page(md, pa); 3305 PMAPCOUNT(exec_synced_kremove); 3306 } 3307 } 3308 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3309 3310 return pv; 3311 } 3312 #endif /* PMAP_CACHE_VIPT */ 3313 3314 /* 3315 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3316 * 3317 * We assume there is already sufficient KVM space available 3318 * to do this, as we can't allocate L2 descriptor tables/metadata 3319 * from here. 3320 */ 3321 void 3322 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3323 { 3324 struct l2_bucket *l2b; 3325 pt_entry_t *ptep, opte; 3326 #ifdef PMAP_CACHE_VIVT 3327 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3328 #endif 3329 #ifdef PMAP_CACHE_VIPT 3330 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3331 struct vm_page *opg; 3332 struct pv_entry *pv = NULL; 3333 #endif 3334 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3335 3336 NPDEBUG(PDB_KENTER, 3337 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3338 va, pa, prot)); 3339 3340 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3341 KDASSERT(l2b != NULL); 3342 3343 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3344 opte = *ptep; 3345 3346 if (opte == 0) { 3347 PMAPCOUNT(kenter_mappings); 3348 l2b->l2b_occupancy++; 3349 } else { 3350 PMAPCOUNT(kenter_remappings); 3351 #ifdef PMAP_CACHE_VIPT 3352 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3353 #ifdef DIAGNOSTIC 3354 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3355 #endif 3356 if (opg) { 3357 KASSERT(opg != pg); 3358 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3359 KASSERT((flags & PMAP_KMPAGE) == 0); 3360 pv = pmap_kremove_pg(opg, va); 3361 } 3362 #endif 3363 if (l2pte_valid(opte)) { 3364 #ifdef PMAP_CACHE_VIVT 3365 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3366 #endif 3367 cpu_tlb_flushD_SE(va); 3368 cpu_cpwait(); 3369 } 3370 } 3371 3372 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3373 | ((flags & PMAP_NOCACHE) ? 0 : pte_l2_s_cache_mode); 3374 PTE_SYNC(ptep); 3375 3376 if (pg) { 3377 #ifdef MULTIPROCESSOR 3378 KASSERT(uvm_page_locked_p(pg)); 3379 #endif 3380 if (flags & PMAP_KMPAGE) { 3381 KASSERT(md->urw_mappings == 0); 3382 KASSERT(md->uro_mappings == 0); 3383 KASSERT(md->krw_mappings == 0); 3384 KASSERT(md->kro_mappings == 0); 3385 #ifdef PMAP_CACHE_VIPT 3386 KASSERT(pv == NULL); 3387 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3388 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3389 /* if there is a color conflict, evict from cache. */ 3390 if (pmap_is_page_colored_p(md) 3391 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3392 PMAPCOUNT(vac_color_change); 3393 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3394 } else if (md->pvh_attrs & PVF_MULTCLR) { 3395 /* 3396 * If this page has multiple colors, expunge 3397 * them. 3398 */ 3399 PMAPCOUNT(vac_flush_lots2); 3400 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3401 } 3402 md->pvh_attrs &= PAGE_SIZE - 1; 3403 md->pvh_attrs |= PVF_KMPAGE 3404 | PVF_COLORED | PVF_DIRTY 3405 | (va & arm_cache_prefer_mask); 3406 #endif 3407 #ifdef PMAP_CACHE_VIVT 3408 md->pvh_attrs |= PVF_KMPAGE; 3409 #endif 3410 pmap_kmpages++; 3411 #ifdef PMAP_CACHE_VIPT 3412 } else { 3413 if (pv == NULL) { 3414 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3415 KASSERT(pv != NULL); 3416 } 3417 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3418 PVF_WIRED | PVF_KENTRY 3419 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3420 if ((prot & VM_PROT_WRITE) 3421 && !(md->pvh_attrs & PVF_NC)) 3422 md->pvh_attrs |= PVF_DIRTY; 3423 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3424 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3425 #endif 3426 } 3427 #ifdef PMAP_CACHE_VIPT 3428 } else { 3429 if (pv != NULL) 3430 pool_put(&pmap_pv_pool, pv); 3431 #endif 3432 } 3433 } 3434 3435 void 3436 pmap_kremove(vaddr_t va, vsize_t len) 3437 { 3438 struct l2_bucket *l2b; 3439 pt_entry_t *ptep, *sptep, opte; 3440 vaddr_t next_bucket, eva; 3441 u_int mappings; 3442 struct vm_page *opg; 3443 3444 PMAPCOUNT(kenter_unmappings); 3445 3446 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3447 va, len)); 3448 3449 eva = va + len; 3450 3451 while (va < eva) { 3452 next_bucket = L2_NEXT_BUCKET(va); 3453 if (next_bucket > eva) 3454 next_bucket = eva; 3455 3456 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3457 KDASSERT(l2b != NULL); 3458 3459 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3460 mappings = 0; 3461 3462 while (va < next_bucket) { 3463 opte = *ptep; 3464 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3465 if (opg) { 3466 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3467 3468 if (omd->pvh_attrs & PVF_KMPAGE) { 3469 KASSERT(omd->urw_mappings == 0); 3470 KASSERT(omd->uro_mappings == 0); 3471 KASSERT(omd->krw_mappings == 0); 3472 KASSERT(omd->kro_mappings == 0); 3473 omd->pvh_attrs &= ~PVF_KMPAGE; 3474 #ifdef PMAP_CACHE_VIPT 3475 if (arm_cache_prefer_mask != 0) { 3476 omd->pvh_attrs &= ~PVF_WRITE; 3477 } 3478 #endif 3479 pmap_kmpages--; 3480 #ifdef PMAP_CACHE_VIPT 3481 } else { 3482 pool_put(&pmap_pv_pool, 3483 pmap_kremove_pg(opg, va)); 3484 #endif 3485 } 3486 } 3487 if (l2pte_valid(opte)) { 3488 #ifdef PMAP_CACHE_VIVT 3489 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3490 #endif 3491 cpu_tlb_flushD_SE(va); 3492 } 3493 if (opte) { 3494 *ptep = 0; 3495 mappings++; 3496 } 3497 va += PAGE_SIZE; 3498 ptep++; 3499 } 3500 KDASSERT(mappings <= l2b->l2b_occupancy); 3501 l2b->l2b_occupancy -= mappings; 3502 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3503 } 3504 cpu_cpwait(); 3505 } 3506 3507 bool 3508 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3509 { 3510 struct l2_dtable *l2; 3511 pd_entry_t *pl1pd, l1pd; 3512 pt_entry_t *ptep, pte; 3513 paddr_t pa; 3514 u_int l1idx; 3515 3516 pmap_acquire_pmap_lock(pm); 3517 3518 l1idx = L1_IDX(va); 3519 pl1pd = pmap_l1_kva(pm) + l1idx; 3520 l1pd = *pl1pd; 3521 3522 if (l1pte_section_p(l1pd)) { 3523 /* 3524 * These should only happen for pmap_kernel() 3525 */ 3526 KDASSERT(pm == pmap_kernel()); 3527 pmap_release_pmap_lock(pm); 3528 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3529 if (l1pte_supersection_p(l1pd)) { 3530 pa = (l1pd & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3531 } else 3532 #endif 3533 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3534 } else { 3535 /* 3536 * Note that we can't rely on the validity of the L1 3537 * descriptor as an indication that a mapping exists. 3538 * We have to look it up in the L2 dtable. 3539 */ 3540 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3541 3542 if (l2 == NULL || 3543 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3544 pmap_release_pmap_lock(pm); 3545 return false; 3546 } 3547 3548 ptep = &ptep[l2pte_index(va)]; 3549 pte = *ptep; 3550 pmap_release_pmap_lock(pm); 3551 3552 if (pte == 0) 3553 return false; 3554 3555 switch (pte & L2_TYPE_MASK) { 3556 case L2_TYPE_L: 3557 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3558 break; 3559 3560 default: 3561 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3562 break; 3563 } 3564 } 3565 3566 if (pap != NULL) 3567 *pap = pa; 3568 3569 return true; 3570 } 3571 3572 void 3573 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3574 { 3575 struct l2_bucket *l2b; 3576 pt_entry_t *ptep, pte; 3577 vaddr_t next_bucket; 3578 u_int flags; 3579 u_int clr_mask; 3580 int flush; 3581 3582 NPDEBUG(PDB_PROTECT, 3583 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3584 pm, sva, eva, prot)); 3585 3586 if ((prot & VM_PROT_READ) == 0) { 3587 pmap_remove(pm, sva, eva); 3588 return; 3589 } 3590 3591 if (prot & VM_PROT_WRITE) { 3592 /* 3593 * If this is a read->write transition, just ignore it and let 3594 * uvm_fault() take care of it later. 3595 */ 3596 return; 3597 } 3598 3599 pmap_acquire_pmap_lock(pm); 3600 3601 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3602 flags = 0; 3603 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3604 3605 while (sva < eva) { 3606 next_bucket = L2_NEXT_BUCKET(sva); 3607 if (next_bucket > eva) 3608 next_bucket = eva; 3609 3610 l2b = pmap_get_l2_bucket(pm, sva); 3611 if (l2b == NULL) { 3612 sva = next_bucket; 3613 continue; 3614 } 3615 3616 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3617 3618 while (sva < next_bucket) { 3619 pte = *ptep; 3620 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3621 struct vm_page *pg; 3622 u_int f; 3623 3624 #ifdef PMAP_CACHE_VIVT 3625 /* 3626 * OK, at this point, we know we're doing 3627 * write-protect operation. If the pmap is 3628 * active, write-back the page. 3629 */ 3630 pmap_cache_wbinv_page(pm, sva, false, PVF_REF); 3631 #endif 3632 3633 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3634 pte = l2pte_set_readonly(pte); 3635 *ptep = pte; 3636 PTE_SYNC(ptep); 3637 3638 if (pg != NULL) { 3639 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3640 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3641 3642 #ifdef MULTIPROCESSOR 3643 KASSERT(uvm_page_locked_p(pg)); 3644 #endif 3645 f = pmap_modify_pv(md, pa, pm, sva, 3646 clr_mask, 0); 3647 pmap_vac_me_harder(md, pa, pm, sva); 3648 } else { 3649 f = PVF_REF | PVF_EXEC; 3650 } 3651 3652 if (flush >= 0) { 3653 flush++; 3654 flags |= f; 3655 } else { 3656 pmap_tlb_flush_SE(pm, sva, f); 3657 } 3658 } 3659 3660 sva += PAGE_SIZE; 3661 ptep++; 3662 } 3663 } 3664 3665 pmap_release_pmap_lock(pm); 3666 3667 if (flush) { 3668 if (PV_BEEN_EXECD(flags)) 3669 pmap_tlb_flushID(pm); 3670 else 3671 if (PV_BEEN_REFD(flags)) 3672 pmap_tlb_flushD(pm); 3673 } 3674 } 3675 3676 void 3677 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3678 { 3679 struct l2_bucket *l2b; 3680 pt_entry_t *ptep; 3681 vaddr_t next_bucket; 3682 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3683 3684 NPDEBUG(PDB_EXEC, 3685 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3686 pm, sva, eva)); 3687 3688 pmap_acquire_pmap_lock(pm); 3689 3690 while (sva < eva) { 3691 next_bucket = L2_NEXT_BUCKET(sva); 3692 if (next_bucket > eva) 3693 next_bucket = eva; 3694 3695 l2b = pmap_get_l2_bucket(pm, sva); 3696 if (l2b == NULL) { 3697 sva = next_bucket; 3698 continue; 3699 } 3700 3701 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3702 sva < next_bucket; 3703 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3704 if (l2pte_valid(*ptep)) { 3705 cpu_icache_sync_range(sva, 3706 min(page_size, eva - sva)); 3707 } 3708 } 3709 } 3710 3711 pmap_release_pmap_lock(pm); 3712 } 3713 3714 void 3715 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3716 { 3717 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3718 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3719 3720 NPDEBUG(PDB_PROTECT, 3721 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3722 md, pa, prot)); 3723 3724 #ifdef MULTIPROCESSOR 3725 KASSERT(uvm_page_locked_p(pg)); 3726 #endif 3727 3728 switch(prot) { 3729 case VM_PROT_READ|VM_PROT_WRITE: 3730 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3731 pmap_clearbit(md, pa, PVF_EXEC); 3732 break; 3733 #endif 3734 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3735 break; 3736 3737 case VM_PROT_READ: 3738 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3739 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3740 break; 3741 #endif 3742 case VM_PROT_READ|VM_PROT_EXECUTE: 3743 pmap_clearbit(md, pa, PVF_WRITE); 3744 break; 3745 3746 default: 3747 pmap_page_remove(md, pa); 3748 break; 3749 } 3750 } 3751 3752 /* 3753 * pmap_clear_modify: 3754 * 3755 * Clear the "modified" attribute for a page. 3756 */ 3757 bool 3758 pmap_clear_modify(struct vm_page *pg) 3759 { 3760 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3761 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3762 bool rv; 3763 3764 #ifdef MULTIPROCESSOR 3765 KASSERT(uvm_page_locked_p(pg)); 3766 #endif 3767 3768 if (md->pvh_attrs & PVF_MOD) { 3769 rv = true; 3770 #ifdef PMAP_CACHE_VIPT 3771 /* 3772 * If we are going to clear the modified bit and there are 3773 * no other modified bits set, flush the page to memory and 3774 * mark it clean. 3775 */ 3776 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3777 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3778 #endif 3779 pmap_clearbit(md, pa, PVF_MOD); 3780 } else 3781 rv = false; 3782 3783 return (rv); 3784 } 3785 3786 /* 3787 * pmap_clear_reference: 3788 * 3789 * Clear the "referenced" attribute for a page. 3790 */ 3791 bool 3792 pmap_clear_reference(struct vm_page *pg) 3793 { 3794 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3795 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3796 bool rv; 3797 3798 #ifdef MULTIPROCESSOR 3799 KASSERT(uvm_page_locked_p(pg)); 3800 #endif 3801 3802 if (md->pvh_attrs & PVF_REF) { 3803 rv = true; 3804 pmap_clearbit(md, pa, PVF_REF); 3805 } else 3806 rv = false; 3807 3808 return (rv); 3809 } 3810 3811 /* 3812 * pmap_is_modified: 3813 * 3814 * Test if a page has the "modified" attribute. 3815 */ 3816 /* See <arm/arm32/pmap.h> */ 3817 3818 /* 3819 * pmap_is_referenced: 3820 * 3821 * Test if a page has the "referenced" attribute. 3822 */ 3823 /* See <arm/arm32/pmap.h> */ 3824 3825 int 3826 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3827 { 3828 struct l2_dtable *l2; 3829 struct l2_bucket *l2b; 3830 pd_entry_t *pl1pd, l1pd; 3831 pt_entry_t *ptep, pte; 3832 paddr_t pa; 3833 u_int l1idx; 3834 int rv = 0; 3835 3836 pmap_acquire_pmap_lock(pm); 3837 3838 l1idx = L1_IDX(va); 3839 3840 /* 3841 * If there is no l2_dtable for this address, then the process 3842 * has no business accessing it. 3843 * 3844 * Note: This will catch userland processes trying to access 3845 * kernel addresses. 3846 */ 3847 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3848 if (l2 == NULL) 3849 goto out; 3850 3851 /* 3852 * Likewise if there is no L2 descriptor table 3853 */ 3854 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3855 if (l2b->l2b_kva == NULL) 3856 goto out; 3857 3858 /* 3859 * Check the PTE itself. 3860 */ 3861 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3862 pte = *ptep; 3863 if (pte == 0) 3864 goto out; 3865 3866 /* 3867 * Catch a userland access to the vector page mapped at 0x0 3868 */ 3869 if (user && (pte & L2_S_PROT_U) == 0) 3870 goto out; 3871 3872 pa = l2pte_pa(pte); 3873 3874 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3875 /* 3876 * This looks like a good candidate for "page modified" 3877 * emulation... 3878 */ 3879 struct pv_entry *pv; 3880 struct vm_page *pg; 3881 3882 /* Extract the physical address of the page */ 3883 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3884 goto out; 3885 3886 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3887 3888 /* Get the current flags for this page. */ 3889 #ifdef MULTIPROCESSOR 3890 KASSERT(uvm_page_locked_p(pg)); 3891 #endif 3892 3893 pv = pmap_find_pv(md, pm, va); 3894 if (pv == NULL) { 3895 goto out; 3896 } 3897 3898 /* 3899 * Do the flags say this page is writable? If not then it 3900 * is a genuine write fault. If yes then the write fault is 3901 * our fault as we did not reflect the write access in the 3902 * PTE. Now we know a write has occurred we can correct this 3903 * and also set the modified bit 3904 */ 3905 if ((pv->pv_flags & PVF_WRITE) == 0) { 3906 goto out; 3907 } 3908 3909 NPDEBUG(PDB_FOLLOW, 3910 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3911 pm, va, pa)); 3912 3913 md->pvh_attrs |= PVF_REF | PVF_MOD; 3914 pv->pv_flags |= PVF_REF | PVF_MOD; 3915 #ifdef PMAP_CACHE_VIPT 3916 /* 3917 * If there are cacheable mappings for this page, mark it dirty. 3918 */ 3919 if ((md->pvh_attrs & PVF_NC) == 0) 3920 md->pvh_attrs |= PVF_DIRTY; 3921 #endif 3922 3923 /* 3924 * Re-enable write permissions for the page. No need to call 3925 * pmap_vac_me_harder(), since this is just a 3926 * modified-emulation fault, and the PVF_WRITE bit isn't 3927 * changing. We've already set the cacheable bits based on 3928 * the assumption that we can write to this page. 3929 */ 3930 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3931 PTE_SYNC(ptep); 3932 rv = 1; 3933 } else 3934 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3935 /* 3936 * This looks like a good candidate for "page referenced" 3937 * emulation. 3938 */ 3939 struct pv_entry *pv; 3940 struct vm_page *pg; 3941 3942 /* Extract the physical address of the page */ 3943 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3944 goto out; 3945 3946 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3947 3948 /* Get the current flags for this page. */ 3949 #ifdef MULTIPROCESSOR 3950 KASSERT(uvm_page_locked_p(pg)); 3951 #endif 3952 3953 pv = pmap_find_pv(md, pm, va); 3954 if (pv == NULL) { 3955 goto out; 3956 } 3957 3958 md->pvh_attrs |= PVF_REF; 3959 pv->pv_flags |= PVF_REF; 3960 3961 NPDEBUG(PDB_FOLLOW, 3962 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3963 pm, va, pa)); 3964 3965 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3966 PTE_SYNC(ptep); 3967 rv = 1; 3968 } 3969 3970 /* 3971 * We know there is a valid mapping here, so simply 3972 * fix up the L1 if necessary. 3973 */ 3974 pl1pd = pmap_l1_kva(pm) + l1idx; 3975 l1pd = l2b->l2b_phys | L1_C_DOM(pmap_domain(pm)) | L1_C_PROTO; 3976 if (*pl1pd != l1pd) { 3977 *pl1pd = l1pd; 3978 PTE_SYNC(pl1pd); 3979 rv = 1; 3980 } 3981 3982 #ifdef CPU_SA110 3983 /* 3984 * There are bugs in the rev K SA110. This is a check for one 3985 * of them. 3986 */ 3987 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3988 curcpu()->ci_arm_cpurev < 3) { 3989 /* Always current pmap */ 3990 if (l2pte_valid(pte)) { 3991 extern int kernel_debug; 3992 if (kernel_debug & 1) { 3993 struct proc *p = curlwp->l_proc; 3994 printf("prefetch_abort: page is already " 3995 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3996 printf("prefetch_abort: pc=%08lx proc=%p " 3997 "process=%s\n", va, p, p->p_comm); 3998 printf("prefetch_abort: far=%08x fs=%x\n", 3999 cpu_faultaddress(), cpu_faultstatus()); 4000 } 4001 #ifdef DDB 4002 if (kernel_debug & 2) 4003 Debugger(); 4004 #endif 4005 rv = 1; 4006 } 4007 } 4008 #endif /* CPU_SA110 */ 4009 4010 /* 4011 * If 'rv == 0' at this point, it generally indicates that there is a 4012 * stale TLB entry for the faulting address. That might be due to a 4013 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4014 */ 4015 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1 4016 && pmap_needs_pte_sync == 0) { 4017 pmap_needs_pte_sync = 1; 4018 PTE_SYNC(ptep); 4019 rv = 1; 4020 } 4021 4022 #ifdef DEBUG 4023 /* 4024 * If 'rv == 0' at this point, it generally indicates that there is a 4025 * stale TLB entry for the faulting address. This happens when two or 4026 * more processes are sharing an L1. Since we don't flush the TLB on 4027 * a context switch between such processes, we can take domain faults 4028 * for mappings which exist at the same VA in both processes. EVEN IF 4029 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4030 * example. 4031 * 4032 * This is extremely likely to happen if pmap_enter() updated the L1 4033 * entry for a recently entered mapping. In this case, the TLB is 4034 * flushed for the new mapping, but there may still be TLB entries for 4035 * other mappings belonging to other processes in the 1MB range 4036 * covered by the L1 entry. 4037 * 4038 * Since 'rv == 0', we know that the L1 already contains the correct 4039 * value, so the fault must be due to a stale TLB entry. 4040 * 4041 * Since we always need to flush the TLB anyway in the case where we 4042 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4043 * stale TLB entries dynamically. 4044 * 4045 * However, the above condition can ONLY happen if the current L1 is 4046 * being shared. If it happens when the L1 is unshared, it indicates 4047 * that other parts of the pmap are not doing their job WRT managing 4048 * the TLB. 4049 */ 4050 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4051 extern int last_fault_code; 4052 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4053 pm, va, ftype); 4054 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4055 l2, l2b, ptep, pl1pd); 4056 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4057 pte, l1pd, last_fault_code); 4058 #ifdef DDB 4059 extern int kernel_debug; 4060 4061 if (kernel_debug & 2) 4062 Debugger(); 4063 #endif 4064 } 4065 #endif 4066 4067 cpu_tlb_flushID_SE(va); 4068 cpu_cpwait(); 4069 4070 rv = 1; 4071 4072 out: 4073 pmap_release_pmap_lock(pm); 4074 4075 return (rv); 4076 } 4077 4078 /* 4079 * Routine: pmap_procwr 4080 * 4081 * Function: 4082 * Synchronize caches corresponding to [addr, addr+len) in p. 4083 * 4084 */ 4085 void 4086 pmap_procwr(struct proc *p, vaddr_t va, int len) 4087 { 4088 /* We only need to do anything if it is the current process. */ 4089 if (p == curproc) 4090 cpu_icache_sync_range(va, len); 4091 } 4092 4093 /* 4094 * Routine: pmap_unwire 4095 * Function: Clear the wired attribute for a map/virtual-address pair. 4096 * 4097 * In/out conditions: 4098 * The mapping must already exist in the pmap. 4099 */ 4100 void 4101 pmap_unwire(pmap_t pm, vaddr_t va) 4102 { 4103 struct l2_bucket *l2b; 4104 pt_entry_t *ptep, pte; 4105 struct vm_page *pg; 4106 paddr_t pa; 4107 4108 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4109 4110 pmap_acquire_pmap_lock(pm); 4111 4112 l2b = pmap_get_l2_bucket(pm, va); 4113 KDASSERT(l2b != NULL); 4114 4115 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4116 pte = *ptep; 4117 4118 /* Extract the physical address of the page */ 4119 pa = l2pte_pa(pte); 4120 4121 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4122 /* Update the wired bit in the pv entry for this page. */ 4123 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4124 4125 #ifdef MULTIPROCESSOR 4126 KASSERT(uvm_page_locked_p(pg)); 4127 #endif 4128 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4129 } 4130 4131 pmap_release_pmap_lock(pm); 4132 } 4133 4134 void 4135 pmap_activate(struct lwp *l) 4136 { 4137 extern int block_userspace_access; 4138 pmap_t opm, npm, rpm; 4139 uint32_t odacr, ndacr; 4140 int oldirqstate; 4141 4142 /* 4143 * If activating a non-current lwp or the current lwp is 4144 * already active, just return. 4145 */ 4146 if (l != curlwp || 4147 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4148 return; 4149 4150 npm = l->l_proc->p_vmspace->vm_map.pmap; 4151 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4152 (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4153 4154 /* 4155 * If TTB and DACR are unchanged, short-circuit all the 4156 * TLB/cache management stuff. 4157 */ 4158 if (pmap_previous_active_lwp != NULL) { 4159 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4160 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4161 (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4162 4163 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4164 goto all_done; 4165 } else 4166 opm = NULL; 4167 4168 PMAPCOUNT(activations); 4169 block_userspace_access = 1; 4170 4171 /* 4172 * If switching to a user vmspace which is different to the 4173 * most recent one, and the most recent one is potentially 4174 * live in the cache, we must write-back and invalidate the 4175 * entire cache. 4176 */ 4177 rpm = pmap_recent_user; 4178 4179 /* 4180 * XXXSCW: There's a corner case here which can leave turds in the cache as 4181 * reported in kern/41058. They're probably left over during tear-down and 4182 * switching away from an exiting process. Until the root cause is identified 4183 * and fixed, zap the cache when switching pmaps. This will result in a few 4184 * unnecessary cache flushes, but that's better than silently corrupting data. 4185 */ 4186 #if 0 4187 if (npm != pmap_kernel() && rpm && npm != rpm && 4188 rpm->pm_cstate.cs_cache) { 4189 rpm->pm_cstate.cs_cache = 0; 4190 #ifdef PMAP_CACHE_VIVT 4191 cpu_idcache_wbinv_all(); 4192 #endif 4193 } 4194 #else 4195 if (rpm) { 4196 rpm->pm_cstate.cs_cache = 0; 4197 if (npm == pmap_kernel()) 4198 pmap_recent_user = NULL; 4199 #ifdef PMAP_CACHE_VIVT 4200 cpu_idcache_wbinv_all(); 4201 #endif 4202 } 4203 #endif 4204 4205 /* No interrupts while we frob the TTB/DACR */ 4206 oldirqstate = disable_interrupts(IF32_bits); 4207 4208 #ifndef ARM_HAS_VBAR 4209 /* 4210 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4211 * entry corresponding to 'vector_page' in the incoming L1 table 4212 * before switching to it otherwise subsequent interrupts/exceptions 4213 * (including domain faults!) will jump into hyperspace. 4214 */ 4215 if (npm->pm_pl1vec != NULL) { 4216 cpu_tlb_flushID_SE((u_int)vector_page); 4217 cpu_cpwait(); 4218 *npm->pm_pl1vec = npm->pm_l1vec; 4219 PTE_SYNC(npm->pm_pl1vec); 4220 } 4221 #endif 4222 4223 cpu_domains(ndacr); 4224 4225 if (npm == pmap_kernel() || npm == rpm) { 4226 /* 4227 * Switching to a kernel thread, or back to the 4228 * same user vmspace as before... Simply update 4229 * the TTB (no TLB flush required) 4230 */ 4231 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4232 cpu_cpwait(); 4233 } else { 4234 /* 4235 * Otherwise, update TTB and flush TLB 4236 */ 4237 cpu_context_switch(npm->pm_l1->l1_physaddr); 4238 if (rpm != NULL) 4239 rpm->pm_cstate.cs_tlb = 0; 4240 } 4241 4242 restore_interrupts(oldirqstate); 4243 4244 block_userspace_access = 0; 4245 4246 all_done: 4247 /* 4248 * The new pmap is resident. Make sure it's marked 4249 * as resident in the cache/TLB. 4250 */ 4251 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4252 if (npm != pmap_kernel()) 4253 pmap_recent_user = npm; 4254 4255 /* The old pmap is not longer active */ 4256 if (opm != NULL) 4257 opm->pm_activated = false; 4258 4259 /* But the new one is */ 4260 npm->pm_activated = true; 4261 } 4262 4263 void 4264 pmap_deactivate(struct lwp *l) 4265 { 4266 4267 /* 4268 * If the process is exiting, make sure pmap_activate() does 4269 * a full MMU context-switch and cache flush, which we might 4270 * otherwise skip. See PR port-arm/38950. 4271 */ 4272 if (l->l_proc->p_sflag & PS_WEXIT) 4273 pmap_previous_active_lwp = NULL; 4274 4275 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4276 } 4277 4278 void 4279 pmap_update(pmap_t pm) 4280 { 4281 4282 if (pm->pm_remove_all) { 4283 /* 4284 * Finish up the pmap_remove_all() optimisation by flushing 4285 * the TLB. 4286 */ 4287 pmap_tlb_flushID(pm); 4288 pm->pm_remove_all = false; 4289 } 4290 4291 if (pmap_is_current(pm)) { 4292 /* 4293 * If we're dealing with a current userland pmap, move its L1 4294 * to the end of the LRU. 4295 */ 4296 if (pm != pmap_kernel()) 4297 pmap_use_l1(pm); 4298 4299 /* 4300 * We can assume we're done with frobbing the cache/tlb for 4301 * now. Make sure any future pmap ops don't skip cache/tlb 4302 * flushes. 4303 */ 4304 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4305 } 4306 4307 PMAPCOUNT(updates); 4308 4309 /* 4310 * make sure TLB/cache operations have completed. 4311 */ 4312 cpu_cpwait(); 4313 } 4314 4315 void 4316 pmap_remove_all(pmap_t pm) 4317 { 4318 4319 /* 4320 * The vmspace described by this pmap is about to be torn down. 4321 * Until pmap_update() is called, UVM will only make calls 4322 * to pmap_remove(). We can make life much simpler by flushing 4323 * the cache now, and deferring TLB invalidation to pmap_update(). 4324 */ 4325 #ifdef PMAP_CACHE_VIVT 4326 pmap_cache_wbinv_all(pm, PVF_EXEC); 4327 #endif 4328 pm->pm_remove_all = true; 4329 } 4330 4331 /* 4332 * Retire the given physical map from service. 4333 * Should only be called if the map contains no valid mappings. 4334 */ 4335 void 4336 pmap_destroy(pmap_t pm) 4337 { 4338 u_int count; 4339 4340 if (pm == NULL) 4341 return; 4342 4343 if (pm->pm_remove_all) { 4344 pmap_tlb_flushID(pm); 4345 pm->pm_remove_all = false; 4346 } 4347 4348 /* 4349 * Drop reference count 4350 */ 4351 mutex_enter(pm->pm_lock); 4352 count = --pm->pm_obj.uo_refs; 4353 mutex_exit(pm->pm_lock); 4354 if (count > 0) { 4355 if (pmap_is_current(pm)) { 4356 if (pm != pmap_kernel()) 4357 pmap_use_l1(pm); 4358 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4359 } 4360 return; 4361 } 4362 4363 /* 4364 * reference count is zero, free pmap resources and then free pmap. 4365 */ 4366 4367 #ifndef ARM_HAS_VBAR 4368 if (vector_page < KERNEL_BASE) { 4369 KDASSERT(!pmap_is_current(pm)); 4370 4371 /* Remove the vector page mapping */ 4372 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4373 pmap_update(pm); 4374 } 4375 #endif 4376 4377 LIST_REMOVE(pm, pm_list); 4378 4379 pmap_free_l1(pm); 4380 4381 if (pmap_recent_user == pm) 4382 pmap_recent_user = NULL; 4383 4384 uvm_obj_destroy(&pm->pm_obj, false); 4385 mutex_destroy(&pm->pm_obj_lock); 4386 pool_cache_put(&pmap_cache, pm); 4387 } 4388 4389 4390 /* 4391 * void pmap_reference(pmap_t pm) 4392 * 4393 * Add a reference to the specified pmap. 4394 */ 4395 void 4396 pmap_reference(pmap_t pm) 4397 { 4398 4399 if (pm == NULL) 4400 return; 4401 4402 pmap_use_l1(pm); 4403 4404 mutex_enter(pm->pm_lock); 4405 pm->pm_obj.uo_refs++; 4406 mutex_exit(pm->pm_lock); 4407 } 4408 4409 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4410 4411 static struct evcnt pmap_prefer_nochange_ev = 4412 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4413 static struct evcnt pmap_prefer_change_ev = 4414 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4415 4416 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4417 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4418 4419 void 4420 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4421 { 4422 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4423 vaddr_t va = *vap; 4424 vaddr_t diff = (hint - va) & mask; 4425 if (diff == 0) { 4426 pmap_prefer_nochange_ev.ev_count++; 4427 } else { 4428 pmap_prefer_change_ev.ev_count++; 4429 if (__predict_false(td)) 4430 va -= mask + 1; 4431 *vap = va + diff; 4432 } 4433 } 4434 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4435 4436 /* 4437 * pmap_zero_page() 4438 * 4439 * Zero a given physical page by mapping it at a page hook point. 4440 * In doing the zero page op, the page we zero is mapped cachable, as with 4441 * StrongARM accesses to non-cached pages are non-burst making writing 4442 * _any_ bulk data very slow. 4443 */ 4444 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4445 void 4446 pmap_zero_page_generic(paddr_t phys) 4447 { 4448 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4449 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4450 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4451 #endif 4452 #if defined(PMAP_CACHE_VIPT) 4453 /* Choose the last page color it had, if any */ 4454 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4455 #else 4456 const vsize_t va_offset = 0; 4457 #endif 4458 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 4459 /* 4460 * Is this page mapped at its natural color? 4461 * If we have all of memory mapped, then just convert PA to VA. 4462 */ 4463 const bool okcolor = va_offset == (phys & arm_cache_prefer_mask); 4464 const vaddr_t vdstp = KERNEL_BASE + (phys - physical_start); 4465 #else 4466 const bool okcolor = false; 4467 const vaddr_t vdstp = cdstp + va_offset; 4468 #endif 4469 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4470 4471 4472 #ifdef DEBUG 4473 if (!SLIST_EMPTY(&md->pvh_list)) 4474 panic("pmap_zero_page: page has mappings"); 4475 #endif 4476 4477 KDASSERT((phys & PGOFSET) == 0); 4478 4479 if (!okcolor) { 4480 /* 4481 * Hook in the page, zero it, and purge the cache for that 4482 * zeroed page. Invalidate the TLB as needed. 4483 */ 4484 *ptep = L2_S_PROTO | phys | 4485 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4486 PTE_SYNC(ptep); 4487 cpu_tlb_flushD_SE(cdstp + va_offset); 4488 cpu_cpwait(); 4489 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 4490 /* 4491 * If we are direct-mapped and our color isn't ok, then before 4492 * we bzero the page invalidate its contents from the cache and 4493 * reset the color to its natural color. 4494 */ 4495 cpu_dcache_inv_range(cdstp + va_offset, PAGE_SIZE); 4496 md->pvh_attrs &= ~arm_cache_prefer_mask; 4497 md->pvh_attrs |= (phys & arm_cache_prefer_mask); 4498 #endif 4499 } 4500 bzero_page(vdstp); 4501 if (!okcolor) { 4502 /* 4503 * Unmap the page. 4504 */ 4505 *ptep = 0; 4506 PTE_SYNC(ptep); 4507 cpu_tlb_flushD_SE(cdstp + va_offset); 4508 #ifdef PMAP_CACHE_VIVT 4509 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4510 #endif 4511 } 4512 #ifdef PMAP_CACHE_VIPT 4513 /* 4514 * This page is now cache resident so it now has a page color. 4515 * Any contents have been obliterated so clear the EXEC flag. 4516 */ 4517 if (!pmap_is_page_colored_p(md)) { 4518 PMAPCOUNT(vac_color_new); 4519 md->pvh_attrs |= PVF_COLORED; 4520 } 4521 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4522 md->pvh_attrs &= ~PVF_EXEC; 4523 PMAPCOUNT(exec_discarded_zero); 4524 } 4525 md->pvh_attrs |= PVF_DIRTY; 4526 #endif 4527 } 4528 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4529 4530 #if ARM_MMU_XSCALE == 1 4531 void 4532 pmap_zero_page_xscale(paddr_t phys) 4533 { 4534 #ifdef DEBUG 4535 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4536 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4537 4538 if (!SLIST_EMPTY(&md->pvh_list)) 4539 panic("pmap_zero_page: page has mappings"); 4540 #endif 4541 4542 KDASSERT((phys & PGOFSET) == 0); 4543 4544 /* 4545 * Hook in the page, zero it, and purge the cache for that 4546 * zeroed page. Invalidate the TLB as needed. 4547 */ 4548 *cdst_pte = L2_S_PROTO | phys | 4549 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4550 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4551 PTE_SYNC(cdst_pte); 4552 cpu_tlb_flushD_SE(cdstp); 4553 cpu_cpwait(); 4554 bzero_page(cdstp); 4555 xscale_cache_clean_minidata(); 4556 } 4557 #endif /* ARM_MMU_XSCALE == 1 */ 4558 4559 /* pmap_pageidlezero() 4560 * 4561 * The same as above, except that we assume that the page is not 4562 * mapped. This means we never have to flush the cache first. Called 4563 * from the idle loop. 4564 */ 4565 bool 4566 pmap_pageidlezero(paddr_t phys) 4567 { 4568 unsigned int i; 4569 int *ptr; 4570 bool rv = true; 4571 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4572 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4573 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4574 #endif 4575 #ifdef PMAP_CACHE_VIPT 4576 /* Choose the last page color it had, if any */ 4577 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4578 #else 4579 const vsize_t va_offset = 0; 4580 #endif 4581 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4582 4583 4584 #ifdef DEBUG 4585 if (!SLIST_EMPTY(&md->pvh_list)) 4586 panic("pmap_pageidlezero: page has mappings"); 4587 #endif 4588 4589 KDASSERT((phys & PGOFSET) == 0); 4590 4591 /* 4592 * Hook in the page, zero it, and purge the cache for that 4593 * zeroed page. Invalidate the TLB as needed. 4594 */ 4595 *ptep = L2_S_PROTO | phys | 4596 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4597 PTE_SYNC(ptep); 4598 cpu_tlb_flushD_SE(cdstp + va_offset); 4599 cpu_cpwait(); 4600 4601 for (i = 0, ptr = (int *)(cdstp + va_offset); 4602 i < (PAGE_SIZE / sizeof(int)); i++) { 4603 if (sched_curcpu_runnable_p() != 0) { 4604 /* 4605 * A process has become ready. Abort now, 4606 * so we don't keep it waiting while we 4607 * do slow memory access to finish this 4608 * page. 4609 */ 4610 rv = false; 4611 break; 4612 } 4613 *ptr++ = 0; 4614 } 4615 4616 #ifdef PMAP_CACHE_VIVT 4617 if (rv) 4618 /* 4619 * if we aborted we'll rezero this page again later so don't 4620 * purge it unless we finished it 4621 */ 4622 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4623 #elif defined(PMAP_CACHE_VIPT) 4624 /* 4625 * This page is now cache resident so it now has a page color. 4626 * Any contents have been obliterated so clear the EXEC flag. 4627 */ 4628 if (!pmap_is_page_colored_p(md)) { 4629 PMAPCOUNT(vac_color_new); 4630 md->pvh_attrs |= PVF_COLORED; 4631 } 4632 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4633 md->pvh_attrs &= ~PVF_EXEC; 4634 PMAPCOUNT(exec_discarded_zero); 4635 } 4636 #endif 4637 /* 4638 * Unmap the page. 4639 */ 4640 *ptep = 0; 4641 PTE_SYNC(ptep); 4642 cpu_tlb_flushD_SE(cdstp + va_offset); 4643 4644 return (rv); 4645 } 4646 4647 /* 4648 * pmap_copy_page() 4649 * 4650 * Copy one physical page into another, by mapping the pages into 4651 * hook points. The same comment regarding cachability as in 4652 * pmap_zero_page also applies here. 4653 */ 4654 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4655 void 4656 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4657 { 4658 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4659 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4660 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4661 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4662 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4663 #endif 4664 #ifdef PMAP_CACHE_VIPT 4665 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4666 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4667 #else 4668 const vsize_t src_va_offset = 0; 4669 const vsize_t dst_va_offset = 0; 4670 #endif 4671 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 4672 /* 4673 * Is this page mapped at its natural color? 4674 * If we have all of memory mapped, then just convert PA to VA. 4675 */ 4676 const bool src_okcolor = src_va_offset == (src & arm_cache_prefer_mask); 4677 const bool dst_okcolor = dst_va_offset == (dst & arm_cache_prefer_mask); 4678 const vaddr_t vsrcp = src_okcolor 4679 ? KERNEL_BASE + (src - physical_start) 4680 : csrcp + src_va_offset; 4681 const vaddr_t vdstp = KERNEL_BASE + (dst - physical_start); 4682 #else 4683 const bool src_okcolor = false; 4684 const bool dst_okcolor = false; 4685 const vaddr_t vsrcp = csrcp + src_va_offset; 4686 const vaddr_t vdstp = cdstp + dst_va_offset; 4687 #endif 4688 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4689 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4690 4691 #ifdef DEBUG 4692 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4693 panic("pmap_copy_page: dst page has mappings"); 4694 #endif 4695 4696 #ifdef PMAP_CACHE_VIPT 4697 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4698 #endif 4699 KDASSERT((src & PGOFSET) == 0); 4700 KDASSERT((dst & PGOFSET) == 0); 4701 4702 /* 4703 * Clean the source page. Hold the source page's lock for 4704 * the duration of the copy so that no other mappings can 4705 * be created while we have a potentially aliased mapping. 4706 */ 4707 #ifdef MULTIPROCESSOR 4708 KASSERT(uvm_page_locked_p(src_pg)); 4709 #endif 4710 #ifdef PMAP_CACHE_VIVT 4711 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4712 #endif 4713 4714 /* 4715 * Map the pages into the page hook points, copy them, and purge 4716 * the cache for the appropriate page. Invalidate the TLB 4717 * as required. 4718 */ 4719 if (!src_okcolor) { 4720 *src_ptep = L2_S_PROTO 4721 | src 4722 #ifdef PMAP_CACHE_VIPT 4723 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4724 #endif 4725 #ifdef PMAP_CACHE_VIVT 4726 | pte_l2_s_cache_mode 4727 #endif 4728 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4729 PTE_SYNC(src_ptep); 4730 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4731 cpu_cpwait(); 4732 } 4733 if (!dst_okcolor) { 4734 *dst_ptep = L2_S_PROTO | dst | 4735 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4736 PTE_SYNC(dst_ptep); 4737 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4738 cpu_cpwait(); 4739 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 4740 /* 4741 * If we are direct-mapped and our color isn't ok, then before 4742 * we bcopy to the new page invalidate its contents from the 4743 * cache and reset its color to its natural color. 4744 */ 4745 cpu_dcache_inv_range(cdstp + dst_va_offset, PAGE_SIZE); 4746 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 4747 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 4748 #endif 4749 } 4750 bcopy_page(vsrcp, vdstp); 4751 #ifdef PMAP_CACHE_VIVT 4752 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 4753 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 4754 #endif 4755 /* 4756 * Unmap the pages. 4757 */ 4758 if (!src_okcolor) { 4759 *src_ptep = 0; 4760 PTE_SYNC(src_ptep); 4761 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4762 cpu_cpwait(); 4763 } 4764 if (!dst_okcolor) { 4765 *dst_ptep = 0; 4766 PTE_SYNC(dst_ptep); 4767 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4768 cpu_cpwait(); 4769 } 4770 #ifdef PMAP_CACHE_VIPT 4771 /* 4772 * Now that the destination page is in the cache, mark it as colored. 4773 * If this was an exec page, discard it. 4774 */ 4775 if (!pmap_is_page_colored_p(dst_md)) { 4776 PMAPCOUNT(vac_color_new); 4777 dst_md->pvh_attrs |= PVF_COLORED; 4778 } 4779 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4780 dst_md->pvh_attrs &= ~PVF_EXEC; 4781 PMAPCOUNT(exec_discarded_copy); 4782 } 4783 dst_md->pvh_attrs |= PVF_DIRTY; 4784 #endif 4785 } 4786 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4787 4788 #if ARM_MMU_XSCALE == 1 4789 void 4790 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4791 { 4792 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4793 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4794 #ifdef DEBUG 4795 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4796 4797 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4798 panic("pmap_copy_page: dst page has mappings"); 4799 #endif 4800 4801 KDASSERT((src & PGOFSET) == 0); 4802 KDASSERT((dst & PGOFSET) == 0); 4803 4804 /* 4805 * Clean the source page. Hold the source page's lock for 4806 * the duration of the copy so that no other mappings can 4807 * be created while we have a potentially aliased mapping. 4808 */ 4809 #ifdef MULTIPROCESSOR 4810 KASSERT(uvm_page_locked_p(src_pg)); 4811 #endif 4812 #ifdef PMAP_CACHE_VIVT 4813 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4814 #endif 4815 4816 /* 4817 * Map the pages into the page hook points, copy them, and purge 4818 * the cache for the appropriate page. Invalidate the TLB 4819 * as required. 4820 */ 4821 *csrc_pte = L2_S_PROTO | src | 4822 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4823 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4824 PTE_SYNC(csrc_pte); 4825 *cdst_pte = L2_S_PROTO | dst | 4826 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4827 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4828 PTE_SYNC(cdst_pte); 4829 cpu_tlb_flushD_SE(csrcp); 4830 cpu_tlb_flushD_SE(cdstp); 4831 cpu_cpwait(); 4832 bcopy_page(csrcp, cdstp); 4833 xscale_cache_clean_minidata(); 4834 } 4835 #endif /* ARM_MMU_XSCALE == 1 */ 4836 4837 /* 4838 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4839 * 4840 * Return the start and end addresses of the kernel's virtual space. 4841 * These values are setup in pmap_bootstrap and are updated as pages 4842 * are allocated. 4843 */ 4844 void 4845 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4846 { 4847 *start = virtual_avail; 4848 *end = virtual_end; 4849 } 4850 4851 /* 4852 * Helper function for pmap_grow_l2_bucket() 4853 */ 4854 static inline int 4855 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4856 { 4857 struct l2_bucket *l2b; 4858 pt_entry_t *ptep; 4859 paddr_t pa; 4860 4861 if (uvm.page_init_done == false) { 4862 #ifdef PMAP_STEAL_MEMORY 4863 pv_addr_t pv; 4864 pmap_boot_pagealloc(PAGE_SIZE, 4865 #ifdef PMAP_CACHE_VIPT 4866 arm_cache_prefer_mask, 4867 va & arm_cache_prefer_mask, 4868 #else 4869 0, 0, 4870 #endif 4871 &pv); 4872 pa = pv.pv_pa; 4873 #else 4874 if (uvm_page_physget(&pa) == false) 4875 return (1); 4876 #endif /* PMAP_STEAL_MEMORY */ 4877 } else { 4878 struct vm_page *pg; 4879 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4880 if (pg == NULL) 4881 return (1); 4882 pa = VM_PAGE_TO_PHYS(pg); 4883 #ifdef PMAP_CACHE_VIPT 4884 #ifdef DIAGNOSTIC 4885 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4886 #endif 4887 /* 4888 * This new page must not have any mappings. Enter it via 4889 * pmap_kenter_pa and let that routine do the hard work. 4890 */ 4891 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4892 pmap_kenter_pa(va, pa, 4893 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4894 #endif 4895 } 4896 4897 if (pap) 4898 *pap = pa; 4899 4900 PMAPCOUNT(pt_mappings); 4901 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4902 KDASSERT(l2b != NULL); 4903 4904 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4905 *ptep = L2_S_PROTO | pa | cache_mode | 4906 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4907 PTE_SYNC(ptep); 4908 memset((void *)va, 0, PAGE_SIZE); 4909 return (0); 4910 } 4911 4912 /* 4913 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4914 * used by pmap_growkernel(). 4915 */ 4916 static inline struct l2_bucket * 4917 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4918 { 4919 struct l2_dtable *l2; 4920 struct l2_bucket *l2b; 4921 u_short l1idx; 4922 vaddr_t nva; 4923 4924 l1idx = L1_IDX(va); 4925 4926 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4927 /* 4928 * No mapping at this address, as there is 4929 * no entry in the L1 table. 4930 * Need to allocate a new l2_dtable. 4931 */ 4932 nva = pmap_kernel_l2dtable_kva; 4933 if ((nva & PGOFSET) == 0) { 4934 /* 4935 * Need to allocate a backing page 4936 */ 4937 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4938 return (NULL); 4939 } 4940 4941 l2 = (struct l2_dtable *)nva; 4942 nva += sizeof(struct l2_dtable); 4943 4944 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4945 /* 4946 * The new l2_dtable straddles a page boundary. 4947 * Map in another page to cover it. 4948 */ 4949 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4950 return (NULL); 4951 } 4952 4953 pmap_kernel_l2dtable_kva = nva; 4954 4955 /* 4956 * Link it into the parent pmap 4957 */ 4958 pm->pm_l2[L2_IDX(l1idx)] = l2; 4959 } 4960 4961 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4962 4963 /* 4964 * Fetch pointer to the L2 page table associated with the address. 4965 */ 4966 if (l2b->l2b_kva == NULL) { 4967 pt_entry_t *ptep; 4968 4969 /* 4970 * No L2 page table has been allocated. Chances are, this 4971 * is because we just allocated the l2_dtable, above. 4972 */ 4973 nva = pmap_kernel_l2ptp_kva; 4974 ptep = (pt_entry_t *)nva; 4975 if ((nva & PGOFSET) == 0) { 4976 /* 4977 * Need to allocate a backing page 4978 */ 4979 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4980 &pmap_kernel_l2ptp_phys)) 4981 return (NULL); 4982 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4983 } 4984 4985 l2->l2_occupancy++; 4986 l2b->l2b_kva = ptep; 4987 l2b->l2b_l1idx = l1idx; 4988 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4989 4990 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4991 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4992 } 4993 4994 return (l2b); 4995 } 4996 4997 vaddr_t 4998 pmap_growkernel(vaddr_t maxkvaddr) 4999 { 5000 pmap_t kpm = pmap_kernel(); 5001 struct l1_ttable *l1; 5002 struct l2_bucket *l2b; 5003 pd_entry_t *pl1pd; 5004 int s; 5005 5006 if (maxkvaddr <= pmap_curmaxkvaddr) 5007 goto out; /* we are OK */ 5008 5009 NPDEBUG(PDB_GROWKERN, 5010 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5011 pmap_curmaxkvaddr, maxkvaddr)); 5012 5013 KDASSERT(maxkvaddr <= virtual_end); 5014 5015 /* 5016 * whoops! we need to add kernel PTPs 5017 */ 5018 5019 s = splhigh(); /* to be safe */ 5020 mutex_enter(kpm->pm_lock); 5021 5022 /* Map 1MB at a time */ 5023 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 5024 5025 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5026 KDASSERT(l2b != NULL); 5027 5028 /* Distribute new L1 entry to all other L1s */ 5029 SLIST_FOREACH(l1, &l1_list, l1_link) { 5030 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 5031 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 5032 L1_C_PROTO; 5033 PTE_SYNC(pl1pd); 5034 } 5035 } 5036 5037 /* 5038 * flush out the cache, expensive but growkernel will happen so 5039 * rarely 5040 */ 5041 cpu_dcache_wbinv_all(); 5042 cpu_tlb_flushD(); 5043 cpu_cpwait(); 5044 5045 mutex_exit(kpm->pm_lock); 5046 splx(s); 5047 5048 out: 5049 return (pmap_curmaxkvaddr); 5050 } 5051 5052 /************************ Utility routines ****************************/ 5053 5054 #ifndef ARM_HAS_VBAR 5055 /* 5056 * vector_page_setprot: 5057 * 5058 * Manipulate the protection of the vector page. 5059 */ 5060 void 5061 vector_page_setprot(int prot) 5062 { 5063 struct l2_bucket *l2b; 5064 pt_entry_t *ptep; 5065 5066 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5067 /* 5068 * If we are using VBAR to use the vectors in the kernel, then it's 5069 * already mapped in the kernel text so no need to anything here. 5070 */ 5071 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5072 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5073 return; 5074 } 5075 #endif 5076 5077 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5078 KDASSERT(l2b != NULL); 5079 5080 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5081 5082 *ptep = (*ptep & ~L2_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 5083 PTE_SYNC(ptep); 5084 cpu_tlb_flushD_SE(vector_page); 5085 cpu_cpwait(); 5086 } 5087 #endif 5088 5089 /* 5090 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5091 * Returns true if the mapping exists, else false. 5092 * 5093 * NOTE: This function is only used by a couple of arm-specific modules. 5094 * It is not safe to take any pmap locks here, since we could be right 5095 * in the middle of debugging the pmap anyway... 5096 * 5097 * It is possible for this routine to return false even though a valid 5098 * mapping does exist. This is because we don't lock, so the metadata 5099 * state may be inconsistent. 5100 * 5101 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5102 * a "section" mapping. 5103 */ 5104 bool 5105 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5106 { 5107 struct l2_dtable *l2; 5108 pd_entry_t *pl1pd, l1pd; 5109 pt_entry_t *ptep; 5110 u_short l1idx; 5111 5112 if (pm->pm_l1 == NULL) 5113 return false; 5114 5115 l1idx = L1_IDX(va); 5116 *pdp = pl1pd = pmap_l1_kva(pm) + l1idx; 5117 l1pd = *pl1pd; 5118 5119 if (l1pte_section_p(l1pd)) { 5120 *ptp = NULL; 5121 return true; 5122 } 5123 5124 if (pm->pm_l2 == NULL) 5125 return false; 5126 5127 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5128 5129 if (l2 == NULL || 5130 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5131 return false; 5132 } 5133 5134 *ptp = &ptep[l2pte_index(va)]; 5135 return true; 5136 } 5137 5138 bool 5139 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5140 { 5141 5142 if (pm->pm_l1 == NULL) 5143 return false; 5144 5145 *pdp = pmap_l1_kva(pm) + L1_IDX(va); 5146 5147 return true; 5148 } 5149 5150 /************************ Bootstrapping routines ****************************/ 5151 5152 static void 5153 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5154 { 5155 int i; 5156 5157 l1->l1_kva = l1pt; 5158 l1->l1_domain_use_count = 0; 5159 l1->l1_domain_first = 0; 5160 5161 for (i = 0; i < PMAP_DOMAINS; i++) 5162 l1->l1_domain_free[i] = i + 1; 5163 5164 /* 5165 * Copy the kernel's L1 entries to each new L1. 5166 */ 5167 if (pmap_initialized) 5168 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5169 5170 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5171 &l1->l1_physaddr) == false) 5172 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5173 5174 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5175 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5176 } 5177 5178 /* 5179 * pmap_bootstrap() is called from the board-specific initarm() routine 5180 * once the kernel L1/L2 descriptors tables have been set up. 5181 * 5182 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5183 * spread over a number of disparate files/functions. 5184 * 5185 * We are passed the following parameters 5186 * - kernel_l1pt 5187 * This is a pointer to the base of the kernel's L1 translation table. 5188 * - vstart 5189 * 1MB-aligned start of managed kernel virtual memory. 5190 * - vend 5191 * 1MB-aligned end of managed kernel virtual memory. 5192 * 5193 * We use the first parameter to build the metadata (struct l1_ttable and 5194 * struct l2_dtable) necessary to track kernel mappings. 5195 */ 5196 #define PMAP_STATIC_L2_SIZE 16 5197 void 5198 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5199 { 5200 static struct l1_ttable static_l1; 5201 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5202 struct l1_ttable *l1 = &static_l1; 5203 struct l2_dtable *l2; 5204 struct l2_bucket *l2b; 5205 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5206 pmap_t pm = pmap_kernel(); 5207 pd_entry_t pde; 5208 pt_entry_t *ptep; 5209 paddr_t pa; 5210 vaddr_t va; 5211 vsize_t size; 5212 int nptes, l1idx, l2idx, l2next = 0; 5213 5214 /* 5215 * Initialise the kernel pmap object 5216 */ 5217 pm->pm_l1 = l1; 5218 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5219 pm->pm_activated = true; 5220 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5221 5222 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5223 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5224 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5225 5226 /* 5227 * Scan the L1 translation table created by initarm() and create 5228 * the required metadata for all valid mappings found in it. 5229 */ 5230 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5231 pde = l1pt[l1idx]; 5232 5233 /* 5234 * We're only interested in Coarse mappings. 5235 * pmap_extract() can deal with section mappings without 5236 * recourse to checking L2 metadata. 5237 */ 5238 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5239 continue; 5240 5241 /* 5242 * Lookup the KVA of this L2 descriptor table 5243 */ 5244 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5245 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5246 if (ptep == NULL) { 5247 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5248 (u_int)l1idx << L1_S_SHIFT, pa); 5249 } 5250 5251 /* 5252 * Fetch the associated L2 metadata structure. 5253 * Allocate a new one if necessary. 5254 */ 5255 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5256 if (l2next == PMAP_STATIC_L2_SIZE) 5257 panic("pmap_bootstrap: out of static L2s"); 5258 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5259 } 5260 5261 /* 5262 * One more L1 slot tracked... 5263 */ 5264 l2->l2_occupancy++; 5265 5266 /* 5267 * Fill in the details of the L2 descriptor in the 5268 * appropriate bucket. 5269 */ 5270 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5271 l2b->l2b_kva = ptep; 5272 l2b->l2b_phys = pa; 5273 l2b->l2b_l1idx = l1idx; 5274 5275 /* 5276 * Establish an initial occupancy count for this descriptor 5277 */ 5278 for (l2idx = 0; 5279 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5280 l2idx++) { 5281 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5282 l2b->l2b_occupancy++; 5283 } 5284 } 5285 5286 /* 5287 * Make sure the descriptor itself has the correct cache mode. 5288 * If not, fix it, but whine about the problem. Port-meisters 5289 * should consider this a clue to fix up their initarm() 5290 * function. :) 5291 */ 5292 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5293 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5294 "L2 pte @ %p\n", ptep); 5295 } 5296 } 5297 5298 /* 5299 * Ensure the primary (kernel) L1 has the correct cache mode for 5300 * a page table. Bitch if it is not correctly set. 5301 */ 5302 for (va = (vaddr_t)l1pt; 5303 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5304 if (pmap_set_pt_cache_mode(l1pt, va)) 5305 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5306 "primary L1 @ 0x%lx\n", va); 5307 } 5308 5309 cpu_dcache_wbinv_all(); 5310 cpu_tlb_flushID(); 5311 cpu_cpwait(); 5312 5313 /* 5314 * now we allocate the "special" VAs which are used for tmp mappings 5315 * by the pmap (and other modules). we allocate the VAs by advancing 5316 * virtual_avail (note that there are no pages mapped at these VAs). 5317 * 5318 * Managed KVM space start from wherever initarm() tells us. 5319 */ 5320 virtual_avail = vstart; 5321 virtual_end = vend; 5322 5323 #ifdef PMAP_CACHE_VIPT 5324 /* 5325 * If we have a VIPT cache, we need one page/pte per possible alias 5326 * page so we won't violate cache aliasing rules. 5327 */ 5328 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5329 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5330 #else 5331 nptes = 1; 5332 #endif 5333 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5334 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5335 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5336 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5337 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5338 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5339 (void *)&msgbufaddr, NULL); 5340 5341 /* 5342 * Allocate a range of kernel virtual address space to be used 5343 * for L2 descriptor tables and metadata allocation in 5344 * pmap_growkernel(). 5345 */ 5346 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5347 pmap_alloc_specials(&virtual_avail, 5348 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5349 &pmap_kernel_l2ptp_kva, NULL); 5350 5351 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5352 pmap_alloc_specials(&virtual_avail, 5353 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5354 &pmap_kernel_l2dtable_kva, NULL); 5355 5356 /* 5357 * init the static-global locks and global pmap list. 5358 */ 5359 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 5360 5361 /* 5362 * We can now initialise the first L1's metadata. 5363 */ 5364 SLIST_INIT(&l1_list); 5365 TAILQ_INIT(&l1_lru_list); 5366 pmap_init_l1(l1, l1pt); 5367 5368 #ifndef ARM_HAS_VBAR 5369 /* Set up vector page L1 details, if necessary */ 5370 if (vector_page < KERNEL_BASE) { 5371 pm->pm_pl1vec = pmap_l1_kva(pm) + L1_IDX(vector_page); 5372 l2b = pmap_get_l2_bucket(pm, vector_page); 5373 KDASSERT(l2b != NULL); 5374 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5375 L1_C_DOM(pmap_domain(pm)); 5376 } else 5377 pm->pm_pl1vec = NULL; 5378 #endif 5379 5380 /* 5381 * Initialize the pmap cache 5382 */ 5383 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5384 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5385 LIST_INIT(&pmap_pmaps); 5386 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5387 5388 /* 5389 * Initialize the pv pool. 5390 */ 5391 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5392 &pmap_bootstrap_pv_allocator, IPL_NONE); 5393 5394 /* 5395 * Initialize the L2 dtable pool and cache. 5396 */ 5397 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5398 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5399 5400 /* 5401 * Initialise the L2 descriptor table pool and cache 5402 */ 5403 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5404 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5405 pmap_l2ptp_ctor, NULL, NULL); 5406 5407 cpu_dcache_wbinv_all(); 5408 } 5409 5410 static int 5411 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5412 { 5413 pd_entry_t *pdep, pde; 5414 pt_entry_t *ptep, pte; 5415 vaddr_t pa; 5416 int rv = 0; 5417 5418 /* 5419 * Make sure the descriptor itself has the correct cache mode 5420 */ 5421 pdep = &kl1[L1_IDX(va)]; 5422 pde = *pdep; 5423 5424 if (l1pte_section_p(pde)) { 5425 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 5426 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5427 *pdep = (pde & ~L1_S_CACHE_MASK) | 5428 pte_l1_s_cache_mode_pt; 5429 PTE_SYNC(pdep); 5430 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5431 rv = 1; 5432 } 5433 } else { 5434 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5435 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5436 if (ptep == NULL) 5437 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5438 5439 ptep = &ptep[l2pte_index(va)]; 5440 pte = *ptep; 5441 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5442 *ptep = (pte & ~L2_S_CACHE_MASK) | 5443 pte_l2_s_cache_mode_pt; 5444 PTE_SYNC(ptep); 5445 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5446 rv = 1; 5447 } 5448 } 5449 5450 return (rv); 5451 } 5452 5453 static void 5454 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5455 { 5456 vaddr_t va = *availp; 5457 struct l2_bucket *l2b; 5458 5459 if (ptep) { 5460 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5461 if (l2b == NULL) 5462 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5463 5464 if (ptep) 5465 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5466 } 5467 5468 *vap = va; 5469 *availp = va + (PAGE_SIZE * pages); 5470 } 5471 5472 void 5473 pmap_init(void) 5474 { 5475 5476 /* 5477 * Set the available memory vars - These do not map to real memory 5478 * addresses and cannot as the physical memory is fragmented. 5479 * They are used by ps for %mem calculations. 5480 * One could argue whether this should be the entire memory or just 5481 * the memory that is useable in a user process. 5482 */ 5483 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5484 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5485 5486 /* 5487 * Now we need to free enough pv_entry structures to allow us to get 5488 * the kmem_map/kmem_object allocated and inited (done after this 5489 * function is finished). to do this we allocate one bootstrap page out 5490 * of kernel_map and use it to provide an initial pool of pv_entry 5491 * structures. we never free this page. 5492 */ 5493 pool_setlowat(&pmap_pv_pool, 5494 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5495 5496 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5497 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5498 UVM_KMF_WIRED|UVM_KMF_ZERO); 5499 5500 pmap_initialized = true; 5501 } 5502 5503 static vaddr_t last_bootstrap_page = 0; 5504 static void *free_bootstrap_pages = NULL; 5505 5506 static void * 5507 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5508 { 5509 extern void *pool_page_alloc(struct pool *, int); 5510 vaddr_t new_page; 5511 void *rv; 5512 5513 if (pmap_initialized) 5514 return (pool_page_alloc(pp, flags)); 5515 5516 if (free_bootstrap_pages) { 5517 rv = free_bootstrap_pages; 5518 free_bootstrap_pages = *((void **)rv); 5519 return (rv); 5520 } 5521 5522 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5523 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5524 5525 KASSERT(new_page > last_bootstrap_page); 5526 last_bootstrap_page = new_page; 5527 return ((void *)new_page); 5528 } 5529 5530 static void 5531 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5532 { 5533 extern void pool_page_free(struct pool *, void *); 5534 5535 if ((vaddr_t)v <= last_bootstrap_page) { 5536 *((void **)v) = free_bootstrap_pages; 5537 free_bootstrap_pages = v; 5538 return; 5539 } 5540 5541 if (pmap_initialized) { 5542 pool_page_free(pp, v); 5543 return; 5544 } 5545 } 5546 5547 /* 5548 * pmap_postinit() 5549 * 5550 * This routine is called after the vm and kmem subsystems have been 5551 * initialised. This allows the pmap code to perform any initialisation 5552 * that can only be done one the memory allocation is in place. 5553 */ 5554 void 5555 pmap_postinit(void) 5556 { 5557 extern paddr_t physical_start, physical_end; 5558 struct l2_bucket *l2b; 5559 struct l1_ttable *l1; 5560 struct pglist plist; 5561 struct vm_page *m; 5562 pd_entry_t *pl1pt; 5563 pt_entry_t *ptep, pte; 5564 vaddr_t va, eva; 5565 u_int loop, needed; 5566 int error; 5567 5568 pool_cache_setlowat(&pmap_l2ptp_cache, 5569 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5570 pool_cache_setlowat(&pmap_l2dtable_cache, 5571 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5572 5573 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5574 needed -= 1; 5575 5576 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 5577 5578 for (loop = 0; loop < needed; loop++, l1++) { 5579 /* Allocate a L1 page table */ 5580 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5581 if (va == 0) 5582 panic("Cannot allocate L1 KVM"); 5583 5584 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5585 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 5586 if (error) 5587 panic("Cannot allocate L1 physical pages"); 5588 5589 m = TAILQ_FIRST(&plist); 5590 eva = va + L1_TABLE_SIZE; 5591 pl1pt = (pd_entry_t *)va; 5592 5593 while (m && va < eva) { 5594 paddr_t pa = VM_PAGE_TO_PHYS(m); 5595 5596 pmap_kenter_pa(va, pa, 5597 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5598 5599 /* 5600 * Make sure the L1 descriptor table is mapped 5601 * with the cache-mode set to write-through. 5602 */ 5603 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5604 KDASSERT(l2b != NULL); 5605 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5606 pte = *ptep; 5607 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5608 *ptep = pte; 5609 PTE_SYNC(ptep); 5610 cpu_tlb_flushD_SE(va); 5611 5612 va += PAGE_SIZE; 5613 m = TAILQ_NEXT(m, pageq.queue); 5614 } 5615 5616 #ifdef DIAGNOSTIC 5617 if (m) 5618 panic("pmap_alloc_l1pt: pglist not empty"); 5619 #endif /* DIAGNOSTIC */ 5620 5621 pmap_init_l1(l1, pl1pt); 5622 } 5623 5624 #ifdef DEBUG 5625 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5626 needed); 5627 #endif 5628 } 5629 5630 /* 5631 * Note that the following routines are used by board-specific initialisation 5632 * code to configure the initial kernel page tables. 5633 * 5634 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5635 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5636 * behaviour of the old pmap, and provides an easy migration path for 5637 * initial bring-up of the new pmap on existing ports. Fortunately, 5638 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5639 * will be deprecated. 5640 * 5641 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5642 * tables. 5643 */ 5644 5645 /* 5646 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5647 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5648 * find them as necessary. 5649 * 5650 * Note that the data on this list MUST remain valid after initarm() returns, 5651 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5652 */ 5653 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5654 5655 static vaddr_t 5656 kernel_pt_lookup(paddr_t pa) 5657 { 5658 pv_addr_t *pv; 5659 5660 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5661 #ifndef ARM32_NEW_VM_LAYOUT 5662 if (pv->pv_pa == (pa & ~PGOFSET)) 5663 return (pv->pv_va | (pa & PGOFSET)); 5664 #else 5665 if (pv->pv_pa == pa) 5666 return (pv->pv_va); 5667 #endif 5668 } 5669 return (0); 5670 } 5671 5672 /* 5673 * pmap_map_section: 5674 * 5675 * Create a single section mapping. 5676 */ 5677 void 5678 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5679 { 5680 pd_entry_t *pde = (pd_entry_t *) l1pt; 5681 pd_entry_t fl; 5682 5683 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5684 5685 switch (cache) { 5686 case PTE_NOCACHE: 5687 default: 5688 fl = 0; 5689 break; 5690 5691 case PTE_CACHE: 5692 fl = pte_l1_s_cache_mode; 5693 break; 5694 5695 case PTE_PAGETABLE: 5696 fl = pte_l1_s_cache_mode_pt; 5697 break; 5698 } 5699 5700 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5701 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5702 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5703 } 5704 5705 /* 5706 * pmap_map_entry: 5707 * 5708 * Create a single page mapping. 5709 */ 5710 void 5711 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5712 { 5713 pd_entry_t *pde = (pd_entry_t *) l1pt; 5714 pt_entry_t fl; 5715 pt_entry_t *pte; 5716 5717 KASSERT(((va | pa) & PGOFSET) == 0); 5718 5719 switch (cache) { 5720 case PTE_NOCACHE: 5721 default: 5722 fl = 0; 5723 break; 5724 5725 case PTE_CACHE: 5726 fl = pte_l2_s_cache_mode; 5727 break; 5728 5729 case PTE_PAGETABLE: 5730 fl = pte_l2_s_cache_mode_pt; 5731 break; 5732 } 5733 5734 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5735 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5736 5737 #ifndef ARM32_NEW_VM_LAYOUT 5738 pte = (pt_entry_t *) 5739 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5740 #else 5741 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5742 #endif 5743 if (pte == NULL) 5744 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5745 5746 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5747 #ifndef ARM32_NEW_VM_LAYOUT 5748 pte += (va >> PGSHIFT) & 0x3ff; 5749 #else 5750 pte += l2pte_index(va); 5751 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5752 #endif 5753 *pte = fl; 5754 PTE_SYNC(pte); 5755 } 5756 5757 /* 5758 * pmap_link_l2pt: 5759 * 5760 * Link the L2 page table specified by "l2pv" into the L1 5761 * page table at the slot for "va". 5762 */ 5763 void 5764 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5765 { 5766 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5767 u_int slot = va >> L1_S_SHIFT; 5768 5769 #ifndef ARM32_NEW_VM_LAYOUT 5770 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5771 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5772 #endif 5773 5774 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5775 5776 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5777 #ifdef ARM32_NEW_VM_LAYOUT 5778 PTE_SYNC(&pde[slot]); 5779 #else 5780 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5781 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5782 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5783 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5784 #endif 5785 5786 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5787 } 5788 5789 /* 5790 * pmap_map_chunk: 5791 * 5792 * Map a chunk of memory using the most efficient mappings 5793 * possible (section, large page, small page) into the 5794 * provided L1 and L2 tables at the specified virtual address. 5795 */ 5796 vsize_t 5797 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5798 int prot, int cache) 5799 { 5800 pd_entry_t *pdep = (pd_entry_t *) l1pt; 5801 pt_entry_t *pte, f1, f2s, f2l; 5802 vsize_t resid; 5803 int i; 5804 5805 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5806 5807 if (l1pt == 0) 5808 panic("pmap_map_chunk: no L1 table provided"); 5809 5810 #ifdef VERBOSE_INIT_ARM 5811 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5812 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5813 #endif 5814 5815 switch (cache) { 5816 case PTE_NOCACHE: 5817 default: 5818 f1 = 0; 5819 f2l = 0; 5820 f2s = 0; 5821 break; 5822 5823 case PTE_CACHE: 5824 f1 = pte_l1_s_cache_mode; 5825 f2l = pte_l2_l_cache_mode; 5826 f2s = pte_l2_s_cache_mode; 5827 break; 5828 5829 case PTE_PAGETABLE: 5830 f1 = pte_l1_s_cache_mode_pt; 5831 f2l = pte_l2_l_cache_mode_pt; 5832 f2s = pte_l2_s_cache_mode_pt; 5833 break; 5834 } 5835 5836 size = resid; 5837 5838 while (resid > 0) { 5839 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5840 /* See if we can use a supersection mapping. */ 5841 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 5842 /* Supersection are always domain 0 */ 5843 pd_entry_t pde = L1_SS_PROTO | pa | 5844 L1_S_PROT(PTE_KERNEL, prot) | f1; 5845 #ifdef VERBOSE_INIT_ARM 5846 printf("sS"); 5847 #endif 5848 for (size_t s = va >> L1_S_SHIFT, 5849 e = s + L1_SS_SIZE / L1_S_SIZE; 5850 s < e; 5851 s++) { 5852 pdep[s] = pde; 5853 PTE_SYNC(&pdep[s]); 5854 } 5855 va += L1_SS_SIZE; 5856 pa += L1_SS_SIZE; 5857 resid -= L1_SS_SIZE; 5858 continue; 5859 } 5860 #endif 5861 /* See if we can use a section mapping. */ 5862 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5863 #ifdef VERBOSE_INIT_ARM 5864 printf("S"); 5865 #endif 5866 pdep[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5867 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5868 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5869 PTE_SYNC(&pdep[va >> L1_S_SHIFT]); 5870 va += L1_S_SIZE; 5871 pa += L1_S_SIZE; 5872 resid -= L1_S_SIZE; 5873 continue; 5874 } 5875 5876 /* 5877 * Ok, we're going to use an L2 table. Make sure 5878 * one is actually in the corresponding L1 slot 5879 * for the current VA. 5880 */ 5881 if ((pdep[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5882 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5883 5884 #ifndef ARM32_NEW_VM_LAYOUT 5885 pte = (pt_entry_t *) 5886 kernel_pt_lookup(pdep[va >> L1_S_SHIFT] & L2_S_FRAME); 5887 #else 5888 pte = (pt_entry_t *) kernel_pt_lookup( 5889 pdep[L1_IDX(va)] & L1_C_ADDR_MASK); 5890 #endif 5891 if (pte == NULL) 5892 panic("pmap_map_chunk: can't find L2 table for VA" 5893 "0x%08lx", va); 5894 5895 /* See if we can use a L2 large page mapping. */ 5896 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5897 #ifdef VERBOSE_INIT_ARM 5898 printf("L"); 5899 #endif 5900 for (i = 0; i < 16; i++) { 5901 #ifndef ARM32_NEW_VM_LAYOUT 5902 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5903 L2_L_PROTO | pa | 5904 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5905 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5906 #else 5907 pte[l2pte_index(va) + i] = 5908 L2_L_PROTO | pa | 5909 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5910 PTE_SYNC(&pte[l2pte_index(va) + i]); 5911 #endif 5912 } 5913 va += L2_L_SIZE; 5914 pa += L2_L_SIZE; 5915 resid -= L2_L_SIZE; 5916 continue; 5917 } 5918 5919 /* Use a small page mapping. */ 5920 #ifdef VERBOSE_INIT_ARM 5921 printf("P"); 5922 #endif 5923 #ifndef ARM32_NEW_VM_LAYOUT 5924 pte[(va >> PGSHIFT) & 0x3ff] = 5925 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5926 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5927 #else 5928 pte[l2pte_index(va)] = 5929 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5930 PTE_SYNC(&pte[l2pte_index(va)]); 5931 #endif 5932 va += PAGE_SIZE; 5933 pa += PAGE_SIZE; 5934 resid -= PAGE_SIZE; 5935 } 5936 #ifdef VERBOSE_INIT_ARM 5937 printf("\n"); 5938 #endif 5939 return (size); 5940 } 5941 5942 /********************** Static device map routines ***************************/ 5943 5944 static const struct pmap_devmap *pmap_devmap_table; 5945 5946 /* 5947 * Register the devmap table. This is provided in case early console 5948 * initialization needs to register mappings created by bootstrap code 5949 * before pmap_devmap_bootstrap() is called. 5950 */ 5951 void 5952 pmap_devmap_register(const struct pmap_devmap *table) 5953 { 5954 5955 pmap_devmap_table = table; 5956 } 5957 5958 /* 5959 * Map all of the static regions in the devmap table, and remember 5960 * the devmap table so other parts of the kernel can look up entries 5961 * later. 5962 */ 5963 void 5964 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5965 { 5966 int i; 5967 5968 pmap_devmap_table = table; 5969 5970 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5971 #ifdef VERBOSE_INIT_ARM 5972 printf("devmap: %08lx -> %08lx @ %08lx\n", 5973 pmap_devmap_table[i].pd_pa, 5974 pmap_devmap_table[i].pd_pa + 5975 pmap_devmap_table[i].pd_size - 1, 5976 pmap_devmap_table[i].pd_va); 5977 #endif 5978 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5979 pmap_devmap_table[i].pd_pa, 5980 pmap_devmap_table[i].pd_size, 5981 pmap_devmap_table[i].pd_prot, 5982 pmap_devmap_table[i].pd_cache); 5983 } 5984 } 5985 5986 const struct pmap_devmap * 5987 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5988 { 5989 uint64_t endpa; 5990 int i; 5991 5992 if (pmap_devmap_table == NULL) 5993 return (NULL); 5994 5995 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5996 5997 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5998 if (pa >= pmap_devmap_table[i].pd_pa && 5999 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6000 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6001 return (&pmap_devmap_table[i]); 6002 } 6003 6004 return (NULL); 6005 } 6006 6007 const struct pmap_devmap * 6008 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6009 { 6010 int i; 6011 6012 if (pmap_devmap_table == NULL) 6013 return (NULL); 6014 6015 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6016 if (va >= pmap_devmap_table[i].pd_va && 6017 va + size - 1 <= pmap_devmap_table[i].pd_va + 6018 pmap_devmap_table[i].pd_size - 1) 6019 return (&pmap_devmap_table[i]); 6020 } 6021 6022 return (NULL); 6023 } 6024 6025 /********************** PTE initialization routines **************************/ 6026 6027 /* 6028 * These routines are called when the CPU type is identified to set up 6029 * the PTE prototypes, cache modes, etc. 6030 * 6031 * The variables are always here, just in case modules need to reference 6032 * them (though, they shouldn't). 6033 */ 6034 6035 pt_entry_t pte_l1_s_cache_mode; 6036 pt_entry_t pte_l1_s_wc_mode; 6037 pt_entry_t pte_l1_s_cache_mode_pt; 6038 pt_entry_t pte_l1_s_cache_mask; 6039 6040 pt_entry_t pte_l2_l_cache_mode; 6041 pt_entry_t pte_l2_l_wc_mode; 6042 pt_entry_t pte_l2_l_cache_mode_pt; 6043 pt_entry_t pte_l2_l_cache_mask; 6044 6045 pt_entry_t pte_l2_s_cache_mode; 6046 pt_entry_t pte_l2_s_wc_mode; 6047 pt_entry_t pte_l2_s_cache_mode_pt; 6048 pt_entry_t pte_l2_s_cache_mask; 6049 6050 pt_entry_t pte_l1_s_prot_u; 6051 pt_entry_t pte_l1_s_prot_w; 6052 pt_entry_t pte_l1_s_prot_ro; 6053 pt_entry_t pte_l1_s_prot_mask; 6054 6055 pt_entry_t pte_l2_s_prot_u; 6056 pt_entry_t pte_l2_s_prot_w; 6057 pt_entry_t pte_l2_s_prot_ro; 6058 pt_entry_t pte_l2_s_prot_mask; 6059 6060 pt_entry_t pte_l2_l_prot_u; 6061 pt_entry_t pte_l2_l_prot_w; 6062 pt_entry_t pte_l2_l_prot_ro; 6063 pt_entry_t pte_l2_l_prot_mask; 6064 6065 pt_entry_t pte_l1_ss_proto; 6066 pt_entry_t pte_l1_s_proto; 6067 pt_entry_t pte_l1_c_proto; 6068 pt_entry_t pte_l2_s_proto; 6069 6070 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6071 void (*pmap_zero_page_func)(paddr_t); 6072 6073 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6074 void 6075 pmap_pte_init_generic(void) 6076 { 6077 6078 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6079 pte_l1_s_wc_mode = L1_S_B; 6080 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6081 6082 pte_l2_l_cache_mode = L2_B|L2_C; 6083 pte_l2_l_wc_mode = L2_B; 6084 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6085 6086 pte_l2_s_cache_mode = L2_B|L2_C; 6087 pte_l2_s_wc_mode = L2_B; 6088 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6089 6090 /* 6091 * If we have a write-through cache, set B and C. If 6092 * we have a write-back cache, then we assume setting 6093 * only C will make those pages write-through (except for those 6094 * Cortex CPUs which can read the L1 caches). 6095 */ 6096 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6097 #if ARM_MMU_V7 > 0 6098 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6099 #endif 6100 #if ARM_MMU_V6 > 0 6101 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6102 #endif 6103 || false) { 6104 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6105 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6106 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6107 } else { 6108 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6109 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6110 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6111 } 6112 6113 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6114 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6115 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6116 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6117 6118 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6119 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6120 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6121 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6122 6123 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6124 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6125 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6126 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6127 6128 pte_l1_ss_proto = L1_SS_PROTO_generic; 6129 pte_l1_s_proto = L1_S_PROTO_generic; 6130 pte_l1_c_proto = L1_C_PROTO_generic; 6131 pte_l2_s_proto = L2_S_PROTO_generic; 6132 6133 pmap_copy_page_func = pmap_copy_page_generic; 6134 pmap_zero_page_func = pmap_zero_page_generic; 6135 } 6136 6137 #if defined(CPU_ARM8) 6138 void 6139 pmap_pte_init_arm8(void) 6140 { 6141 6142 /* 6143 * ARM8 is compatible with generic, but we need to use 6144 * the page tables uncached. 6145 */ 6146 pmap_pte_init_generic(); 6147 6148 pte_l1_s_cache_mode_pt = 0; 6149 pte_l2_l_cache_mode_pt = 0; 6150 pte_l2_s_cache_mode_pt = 0; 6151 } 6152 #endif /* CPU_ARM8 */ 6153 6154 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6155 void 6156 pmap_pte_init_arm9(void) 6157 { 6158 6159 /* 6160 * ARM9 is compatible with generic, but we want to use 6161 * write-through caching for now. 6162 */ 6163 pmap_pte_init_generic(); 6164 6165 pte_l1_s_cache_mode = L1_S_C; 6166 pte_l2_l_cache_mode = L2_C; 6167 pte_l2_s_cache_mode = L2_C; 6168 6169 pte_l1_s_wc_mode = L1_S_B; 6170 pte_l2_l_wc_mode = L2_B; 6171 pte_l2_s_wc_mode = L2_B; 6172 6173 pte_l1_s_cache_mode_pt = L1_S_C; 6174 pte_l2_l_cache_mode_pt = L2_C; 6175 pte_l2_s_cache_mode_pt = L2_C; 6176 } 6177 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6178 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6179 6180 #if defined(CPU_ARM10) 6181 void 6182 pmap_pte_init_arm10(void) 6183 { 6184 6185 /* 6186 * ARM10 is compatible with generic, but we want to use 6187 * write-through caching for now. 6188 */ 6189 pmap_pte_init_generic(); 6190 6191 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6192 pte_l2_l_cache_mode = L2_B | L2_C; 6193 pte_l2_s_cache_mode = L2_B | L2_C; 6194 6195 pte_l1_s_cache_mode = L1_S_B; 6196 pte_l2_l_cache_mode = L2_B; 6197 pte_l2_s_cache_mode = L2_B; 6198 6199 pte_l1_s_cache_mode_pt = L1_S_C; 6200 pte_l2_l_cache_mode_pt = L2_C; 6201 pte_l2_s_cache_mode_pt = L2_C; 6202 6203 } 6204 #endif /* CPU_ARM10 */ 6205 6206 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6207 void 6208 pmap_pte_init_arm11(void) 6209 { 6210 6211 /* 6212 * ARM11 is compatible with generic, but we want to use 6213 * write-through caching for now. 6214 */ 6215 pmap_pte_init_generic(); 6216 6217 pte_l1_s_cache_mode = L1_S_C; 6218 pte_l2_l_cache_mode = L2_C; 6219 pte_l2_s_cache_mode = L2_C; 6220 6221 pte_l1_s_wc_mode = L1_S_B; 6222 pte_l2_l_wc_mode = L2_B; 6223 pte_l2_s_wc_mode = L2_B; 6224 6225 pte_l1_s_cache_mode_pt = L1_S_C; 6226 pte_l2_l_cache_mode_pt = L2_C; 6227 pte_l2_s_cache_mode_pt = L2_C; 6228 } 6229 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6230 6231 #if ARM_MMU_SA1 == 1 6232 void 6233 pmap_pte_init_sa1(void) 6234 { 6235 6236 /* 6237 * The StrongARM SA-1 cache does not have a write-through 6238 * mode. So, do the generic initialization, then reset 6239 * the page table cache mode to B=1,C=1, and note that 6240 * the PTEs need to be sync'd. 6241 */ 6242 pmap_pte_init_generic(); 6243 6244 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6245 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6246 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6247 6248 pmap_needs_pte_sync = 1; 6249 } 6250 #endif /* ARM_MMU_SA1 == 1*/ 6251 6252 #if ARM_MMU_XSCALE == 1 6253 #if (ARM_NMMUS > 1) 6254 static u_int xscale_use_minidata; 6255 #endif 6256 6257 void 6258 pmap_pte_init_xscale(void) 6259 { 6260 uint32_t auxctl; 6261 int write_through = 0; 6262 6263 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6264 pte_l1_s_wc_mode = L1_S_B; 6265 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6266 6267 pte_l2_l_cache_mode = L2_B|L2_C; 6268 pte_l2_l_wc_mode = L2_B; 6269 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6270 6271 pte_l2_s_cache_mode = L2_B|L2_C; 6272 pte_l2_s_wc_mode = L2_B; 6273 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6274 6275 pte_l1_s_cache_mode_pt = L1_S_C; 6276 pte_l2_l_cache_mode_pt = L2_C; 6277 pte_l2_s_cache_mode_pt = L2_C; 6278 6279 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6280 /* 6281 * The XScale core has an enhanced mode where writes that 6282 * miss the cache cause a cache line to be allocated. This 6283 * is significantly faster than the traditional, write-through 6284 * behavior of this case. 6285 */ 6286 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6287 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6288 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6289 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6290 6291 #ifdef XSCALE_CACHE_WRITE_THROUGH 6292 /* 6293 * Some versions of the XScale core have various bugs in 6294 * their cache units, the work-around for which is to run 6295 * the cache in write-through mode. Unfortunately, this 6296 * has a major (negative) impact on performance. So, we 6297 * go ahead and run fast-and-loose, in the hopes that we 6298 * don't line up the planets in a way that will trip the 6299 * bugs. 6300 * 6301 * However, we give you the option to be slow-but-correct. 6302 */ 6303 write_through = 1; 6304 #elif defined(XSCALE_CACHE_WRITE_BACK) 6305 /* force write back cache mode */ 6306 write_through = 0; 6307 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6308 /* 6309 * Intel PXA2[15]0 processors are known to have a bug in 6310 * write-back cache on revision 4 and earlier (stepping 6311 * A[01] and B[012]). Fixed for C0 and later. 6312 */ 6313 { 6314 uint32_t id, type; 6315 6316 id = cpufunc_id(); 6317 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6318 6319 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6320 if ((id & CPU_ID_REVISION_MASK) < 5) { 6321 /* write through for stepping A0-1 and B0-2 */ 6322 write_through = 1; 6323 } 6324 } 6325 } 6326 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6327 6328 if (write_through) { 6329 pte_l1_s_cache_mode = L1_S_C; 6330 pte_l2_l_cache_mode = L2_C; 6331 pte_l2_s_cache_mode = L2_C; 6332 } 6333 6334 #if (ARM_NMMUS > 1) 6335 xscale_use_minidata = 1; 6336 #endif 6337 6338 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6339 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6340 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6341 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6342 6343 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6344 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6345 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6346 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6347 6348 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6349 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6350 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6351 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6352 6353 pte_l1_ss_proto = L1_SS_PROTO_xscale; 6354 pte_l1_s_proto = L1_S_PROTO_xscale; 6355 pte_l1_c_proto = L1_C_PROTO_xscale; 6356 pte_l2_s_proto = L2_S_PROTO_xscale; 6357 6358 pmap_copy_page_func = pmap_copy_page_xscale; 6359 pmap_zero_page_func = pmap_zero_page_xscale; 6360 6361 /* 6362 * Disable ECC protection of page table access, for now. 6363 */ 6364 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6365 auxctl &= ~XSCALE_AUXCTL_P; 6366 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6367 } 6368 6369 /* 6370 * xscale_setup_minidata: 6371 * 6372 * Set up the mini-data cache clean area. We require the 6373 * caller to allocate the right amount of physically and 6374 * virtually contiguous space. 6375 */ 6376 void 6377 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6378 { 6379 extern vaddr_t xscale_minidata_clean_addr; 6380 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6381 pd_entry_t *pde = (pd_entry_t *) l1pt; 6382 pt_entry_t *pte; 6383 vsize_t size; 6384 uint32_t auxctl; 6385 6386 xscale_minidata_clean_addr = va; 6387 6388 /* Round it to page size. */ 6389 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6390 6391 for (; size != 0; 6392 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6393 #ifndef ARM32_NEW_VM_LAYOUT 6394 pte = (pt_entry_t *) 6395 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6396 #else 6397 pte = (pt_entry_t *) kernel_pt_lookup( 6398 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6399 #endif 6400 if (pte == NULL) 6401 panic("xscale_setup_minidata: can't find L2 table for " 6402 "VA 0x%08lx", va); 6403 #ifndef ARM32_NEW_VM_LAYOUT 6404 pte[(va >> PGSHIFT) & 0x3ff] = 6405 #else 6406 pte[l2pte_index(va)] = 6407 #endif 6408 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6409 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6410 } 6411 6412 /* 6413 * Configure the mini-data cache for write-back with 6414 * read/write-allocate. 6415 * 6416 * NOTE: In order to reconfigure the mini-data cache, we must 6417 * make sure it contains no valid data! In order to do that, 6418 * we must issue a global data cache invalidate command! 6419 * 6420 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6421 * THIS IS VERY IMPORTANT! 6422 */ 6423 6424 /* Invalidate data and mini-data. */ 6425 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6426 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6427 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6428 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6429 } 6430 6431 /* 6432 * Change the PTEs for the specified kernel mappings such that they 6433 * will use the mini data cache instead of the main data cache. 6434 */ 6435 void 6436 pmap_uarea(vaddr_t va) 6437 { 6438 struct l2_bucket *l2b; 6439 pt_entry_t *ptep, *sptep, pte; 6440 vaddr_t next_bucket, eva; 6441 6442 #if (ARM_NMMUS > 1) 6443 if (xscale_use_minidata == 0) 6444 return; 6445 #endif 6446 6447 eva = va + USPACE; 6448 6449 while (va < eva) { 6450 next_bucket = L2_NEXT_BUCKET(va); 6451 if (next_bucket > eva) 6452 next_bucket = eva; 6453 6454 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6455 KDASSERT(l2b != NULL); 6456 6457 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6458 6459 while (va < next_bucket) { 6460 pte = *ptep; 6461 if (!l2pte_minidata(pte)) { 6462 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6463 cpu_tlb_flushD_SE(va); 6464 *ptep = pte & ~L2_B; 6465 } 6466 ptep++; 6467 va += PAGE_SIZE; 6468 } 6469 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6470 } 6471 cpu_cpwait(); 6472 } 6473 #endif /* ARM_MMU_XSCALE == 1 */ 6474 6475 6476 #if defined(CPU_ARM11MPCORE) 6477 6478 void 6479 pmap_pte_init_arm11mpcore(void) 6480 { 6481 6482 /* cache mode is controlled by 5 bits (B, C, TEX) */ 6483 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 6484 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 6485 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6486 /* use extended small page (without APn, with TEX) */ 6487 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 6488 #else 6489 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 6490 #endif 6491 6492 /* write-back, write-allocate */ 6493 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6494 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 6495 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6496 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6497 #else 6498 /* no TEX. read-allocate */ 6499 pte_l2_s_cache_mode = L2_C | L2_B; 6500 #endif 6501 /* 6502 * write-back, write-allocate for page tables. 6503 */ 6504 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6505 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 6506 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6507 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6508 #else 6509 pte_l2_s_cache_mode_pt = L2_C | L2_B; 6510 #endif 6511 6512 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 6513 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 6514 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 6515 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 6516 6517 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6518 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 6519 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 6520 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 6521 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 6522 6523 #else 6524 /* with AP[0..3] */ 6525 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6526 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6527 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6528 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6529 #endif 6530 6531 #ifdef ARM11MPCORE_COMPAT_MMU 6532 /* with AP[0..3] */ 6533 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6534 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6535 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6536 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6537 6538 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6539 pte_l1_s_proto = L1_S_PROTO_armv6; 6540 pte_l1_c_proto = L1_C_PROTO_armv6; 6541 pte_l2_s_proto = L2_S_PROTO_armv6c; 6542 #else 6543 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 6544 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 6545 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 6546 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 6547 6548 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6549 pte_l1_s_proto = L1_S_PROTO_armv6; 6550 pte_l1_c_proto = L1_C_PROTO_armv6; 6551 pte_l2_s_proto = L2_S_PROTO_armv6n; 6552 #endif 6553 6554 pmap_copy_page_func = pmap_copy_page_generic; 6555 pmap_zero_page_func = pmap_zero_page_generic; 6556 pmap_needs_pte_sync = 1; 6557 } 6558 #endif /* CPU_ARM11MPCORE */ 6559 6560 6561 #if ARM_MMU_V7 == 1 6562 void 6563 pmap_pte_init_armv7(void) 6564 { 6565 /* 6566 * The ARMv7-A MMU is mostly compatible with generic. If the 6567 * AP field is zero, that now means "no access" rather than 6568 * read-only. The prototypes are a little different because of 6569 * the XN bit. 6570 */ 6571 pmap_pte_init_generic(); 6572 6573 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6574 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6575 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6576 6577 if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) { 6578 /* 6579 * write-back, no write-allocate, shareable for normal pages. 6580 */ 6581 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_S; 6582 pte_l2_l_cache_mode = L2_C | L2_B | L2_XS_S; 6583 pte_l2_s_cache_mode = L2_C | L2_B | L2_XS_S; 6584 6585 /* 6586 * write-back, no write-allocate, shareable for page tables. 6587 */ 6588 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_S; 6589 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6590 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6591 } 6592 6593 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6594 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6595 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6596 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6597 6598 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6599 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6600 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6601 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6602 6603 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6604 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6605 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6606 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6607 6608 pte_l1_ss_proto = L1_SS_PROTO_armv7; 6609 pte_l1_s_proto = L1_S_PROTO_armv7; 6610 pte_l1_c_proto = L1_C_PROTO_armv7; 6611 pte_l2_s_proto = L2_S_PROTO_armv7; 6612 6613 pmap_needs_pte_sync = 1; 6614 } 6615 #endif /* ARM_MMU_V7 */ 6616 6617 /* 6618 * return the PA of the current L1 table, for use when handling a crash dump 6619 */ 6620 uint32_t pmap_kernel_L1_addr(void) 6621 { 6622 return pmap_kernel()->pm_l1->l1_physaddr; 6623 } 6624 6625 #if defined(DDB) 6626 /* 6627 * A couple of ddb-callable functions for dumping pmaps 6628 */ 6629 void pmap_dump_all(void); 6630 void pmap_dump(pmap_t); 6631 6632 void 6633 pmap_dump_all(void) 6634 { 6635 pmap_t pm; 6636 6637 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6638 if (pm == pmap_kernel()) 6639 continue; 6640 pmap_dump(pm); 6641 printf("\n"); 6642 } 6643 } 6644 6645 static pt_entry_t ncptes[64]; 6646 static void pmap_dump_ncpg(pmap_t); 6647 6648 void 6649 pmap_dump(pmap_t pm) 6650 { 6651 struct l2_dtable *l2; 6652 struct l2_bucket *l2b; 6653 pt_entry_t *ptep, pte; 6654 vaddr_t l2_va, l2b_va, va; 6655 int i, j, k, occ, rows = 0; 6656 6657 if (pm == pmap_kernel()) 6658 printf("pmap_kernel (%p): ", pm); 6659 else 6660 printf("user pmap (%p): ", pm); 6661 6662 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 6663 6664 l2_va = 0; 6665 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6666 l2 = pm->pm_l2[i]; 6667 6668 if (l2 == NULL || l2->l2_occupancy == 0) 6669 continue; 6670 6671 l2b_va = l2_va; 6672 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6673 l2b = &l2->l2_bucket[j]; 6674 6675 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6676 continue; 6677 6678 ptep = l2b->l2b_kva; 6679 6680 for (k = 0; k < 256 && ptep[k] == 0; k++) 6681 ; 6682 6683 k &= ~63; 6684 occ = l2b->l2b_occupancy; 6685 va = l2b_va + (k * 4096); 6686 for (; k < 256; k++, va += 0x1000) { 6687 char ch = ' '; 6688 if ((k % 64) == 0) { 6689 if ((rows % 8) == 0) { 6690 printf( 6691 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6692 } 6693 printf("%08lx: ", va); 6694 } 6695 6696 ncptes[k & 63] = 0; 6697 pte = ptep[k]; 6698 if (pte == 0) { 6699 ch = '.'; 6700 } else { 6701 occ--; 6702 switch (pte & 0x0c) { 6703 case 0x00: 6704 ch = 'D'; /* No cache No buff */ 6705 break; 6706 case 0x04: 6707 ch = 'B'; /* No cache buff */ 6708 break; 6709 case 0x08: 6710 if (pte & 0x40) 6711 ch = 'm'; 6712 else 6713 ch = 'C'; /* Cache No buff */ 6714 break; 6715 case 0x0c: 6716 ch = 'F'; /* Cache Buff */ 6717 break; 6718 } 6719 6720 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6721 ch += 0x20; 6722 6723 if ((pte & 0xc) == 0) 6724 ncptes[k & 63] = pte; 6725 } 6726 6727 if ((k % 64) == 63) { 6728 rows++; 6729 printf("%c\n", ch); 6730 pmap_dump_ncpg(pm); 6731 if (occ == 0) 6732 break; 6733 } else 6734 printf("%c", ch); 6735 } 6736 } 6737 } 6738 } 6739 6740 static void 6741 pmap_dump_ncpg(pmap_t pm) 6742 { 6743 struct vm_page *pg; 6744 struct vm_page_md *md; 6745 struct pv_entry *pv; 6746 int i; 6747 6748 for (i = 0; i < 63; i++) { 6749 if (ncptes[i] == 0) 6750 continue; 6751 6752 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6753 if (pg == NULL) 6754 continue; 6755 md = VM_PAGE_TO_MD(pg); 6756 6757 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6758 VM_PAGE_TO_PHYS(pg), 6759 md->krw_mappings, md->kro_mappings, 6760 md->urw_mappings, md->uro_mappings); 6761 6762 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6763 printf(" %c va 0x%08lx, flags 0x%x\n", 6764 (pm == pv->pv_pmap) ? '*' : ' ', 6765 pv->pv_va, pv->pv_flags); 6766 } 6767 } 6768 } 6769 #endif 6770 6771 #ifdef PMAP_STEAL_MEMORY 6772 void 6773 pmap_boot_pageadd(pv_addr_t *newpv) 6774 { 6775 pv_addr_t *pv, *npv; 6776 6777 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6778 if (newpv->pv_pa < pv->pv_va) { 6779 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6780 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6781 newpv->pv_size += pv->pv_size; 6782 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6783 } 6784 pv = NULL; 6785 } else { 6786 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6787 pv = npv) { 6788 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6789 KASSERT(pv->pv_pa < newpv->pv_pa); 6790 if (newpv->pv_pa > npv->pv_pa) 6791 continue; 6792 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6793 pv->pv_size += newpv->pv_size; 6794 return; 6795 } 6796 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6797 break; 6798 newpv->pv_size += npv->pv_size; 6799 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6800 SLIST_REMOVE_AFTER(newpv, pv_list); 6801 return; 6802 } 6803 } 6804 } 6805 6806 if (pv) { 6807 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6808 } else { 6809 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6810 } 6811 } 6812 6813 void 6814 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6815 pv_addr_t *rpv) 6816 { 6817 pv_addr_t *pv, **pvp; 6818 struct vm_physseg *ps; 6819 size_t i; 6820 6821 KASSERT(amount & PGOFSET); 6822 KASSERT((mask & PGOFSET) == 0); 6823 KASSERT((match & PGOFSET) == 0); 6824 KASSERT(amount != 0); 6825 6826 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6827 (pv = *pvp) != NULL; 6828 pvp = &SLIST_NEXT(pv, pv_list)) { 6829 pv_addr_t *newpv; 6830 psize_t off; 6831 /* 6832 * If this entry is too small to satify the request... 6833 */ 6834 KASSERT(pv->pv_size > 0); 6835 if (pv->pv_size < amount) 6836 continue; 6837 6838 for (off = 0; off <= mask; off += PAGE_SIZE) { 6839 if (((pv->pv_pa + off) & mask) == match 6840 && off + amount <= pv->pv_size) 6841 break; 6842 } 6843 if (off > mask) 6844 continue; 6845 6846 rpv->pv_va = pv->pv_va + off; 6847 rpv->pv_pa = pv->pv_pa + off; 6848 rpv->pv_size = amount; 6849 pv->pv_size -= amount; 6850 if (pv->pv_size == 0) { 6851 KASSERT(off == 0); 6852 KASSERT((vaddr_t) pv == rpv->pv_va); 6853 *pvp = SLIST_NEXT(pv, pv_list); 6854 } else if (off == 0) { 6855 KASSERT((vaddr_t) pv == rpv->pv_va); 6856 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6857 *newpv = *pv; 6858 newpv->pv_pa += amount; 6859 newpv->pv_va += amount; 6860 *pvp = newpv; 6861 } else if (off < pv->pv_size) { 6862 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6863 *newpv = *pv; 6864 newpv->pv_size -= off; 6865 newpv->pv_pa += off + amount; 6866 newpv->pv_va += off + amount; 6867 6868 SLIST_NEXT(pv, pv_list) = newpv; 6869 pv->pv_size = off; 6870 } else { 6871 KASSERT((vaddr_t) pv != rpv->pv_va); 6872 } 6873 memset((void *)rpv->pv_va, 0, amount); 6874 return; 6875 } 6876 6877 if (vm_nphysseg == 0) 6878 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6879 6880 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6881 (pv = *pvp) != NULL; 6882 pvp = &SLIST_NEXT(pv, pv_list)) { 6883 if (SLIST_NEXT(pv, pv_list) == NULL) 6884 break; 6885 } 6886 KASSERT(mask == 0); 6887 for (i = 0; i < vm_nphysseg; i++) { 6888 ps = VM_PHYSMEM_PTR(i); 6889 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6890 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6891 rpv->pv_va = pv->pv_va; 6892 rpv->pv_pa = pv->pv_pa; 6893 rpv->pv_size = amount; 6894 *pvp = NULL; 6895 pmap_map_chunk(kernel_l1pt.pv_va, 6896 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6897 ptoa(ps->avail_start), 6898 amount - pv->pv_size, 6899 VM_PROT_READ|VM_PROT_WRITE, 6900 PTE_CACHE); 6901 ps->avail_start += atop(amount - pv->pv_size); 6902 /* 6903 * If we consumed the entire physseg, remove it. 6904 */ 6905 if (ps->avail_start == ps->avail_end) { 6906 for (--vm_nphysseg; i < vm_nphysseg; i++) 6907 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6908 } 6909 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6910 return; 6911 } 6912 } 6913 6914 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6915 } 6916 6917 vaddr_t 6918 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6919 { 6920 pv_addr_t pv; 6921 6922 pmap_boot_pagealloc(size, 0, 0, &pv); 6923 6924 return pv.pv_va; 6925 } 6926 #endif /* PMAP_STEAL_MEMORY */ 6927 6928 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6929 { 6930 sysctl_createv(clog, 0, NULL, NULL, 6931 CTLFLAG_PERMANENT, 6932 CTLTYPE_NODE, "machdep", NULL, 6933 NULL, 0, NULL, 0, 6934 CTL_MACHDEP, CTL_EOL); 6935 6936 sysctl_createv(clog, 0, NULL, NULL, 6937 CTLFLAG_PERMANENT, 6938 CTLTYPE_INT, "kmpages", 6939 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6940 NULL, 0, &pmap_kmpages, 0, 6941 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6942 } 6943 6944 #ifdef PMAP_NEED_ALLOC_POOLPAGE 6945 struct vm_page * 6946 arm_pmap_alloc_poolpage(int flags) 6947 { 6948 /* 6949 * On some systems, only some pages may be "coherent" for dma and we 6950 * want to prefer those for pool pages (think mbufs) but fallback to 6951 * any page if none is available. 6952 */ 6953 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 6954 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 6955 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 6956 } 6957 6958 return uvm_pagealloc(NULL, 0, NULL, flags); 6959 } 6960 #endif 6961
Indexes created Mon Sep 29 03:10:08 GMT 2025