pmap.c revision 1.264
1 /* $NetBSD: pmap.c,v 1.264 2013/09/12 14:45:18 kiyohara Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/pool.h> 201 #include <sys/kmem.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 #include <sys/bus.h> 206 207 #include <uvm/uvm.h> 208 209 #include <arm/locore.h> 210 #include <arm/arm32/katelib.h> 211 212 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.264 2013/09/12 14:45:18 kiyohara Exp $"); 213 214 #ifdef PMAP_DEBUG 215 216 /* XXX need to get rid of all refs to this */ 217 int pmap_debug_level = 0; 218 219 /* 220 * for switching to potentially finer grained debugging 221 */ 222 #define PDB_FOLLOW 0x0001 223 #define PDB_INIT 0x0002 224 #define PDB_ENTER 0x0004 225 #define PDB_REMOVE 0x0008 226 #define PDB_CREATE 0x0010 227 #define PDB_PTPAGE 0x0020 228 #define PDB_GROWKERN 0x0040 229 #define PDB_BITS 0x0080 230 #define PDB_COLLECT 0x0100 231 #define PDB_PROTECT 0x0200 232 #define PDB_MAP_L1 0x0400 233 #define PDB_BOOTSTRAP 0x1000 234 #define PDB_PARANOIA 0x2000 235 #define PDB_WIRING 0x4000 236 #define PDB_PVDUMP 0x8000 237 #define PDB_VAC 0x10000 238 #define PDB_KENTER 0x20000 239 #define PDB_KREMOVE 0x40000 240 #define PDB_EXEC 0x80000 241 242 int debugmap = 1; 243 int pmapdebug = 0; 244 #define NPDEBUG(_lev_,_stat_) \ 245 if (pmapdebug & (_lev_)) \ 246 ((_stat_)) 247 248 #else /* PMAP_DEBUG */ 249 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 250 #endif /* PMAP_DEBUG */ 251 252 /* 253 * pmap_kernel() points here 254 */ 255 static struct pmap kernel_pmap_store; 256 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 257 #ifdef PMAP_NEED_ALLOC_POOLPAGE 258 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 259 #endif 260 261 /* 262 * Which pmap is currently 'live' in the cache 263 * 264 * XXXSCW: Fix for SMP ... 265 */ 266 static pmap_t pmap_recent_user; 267 268 /* 269 * Pointer to last active lwp, or NULL if it exited. 270 */ 271 struct lwp *pmap_previous_active_lwp; 272 273 /* 274 * Pool and cache that pmap structures are allocated from. 275 * We use a cache to avoid clearing the pm_l2[] array (1KB) 276 * in pmap_create(). 277 */ 278 static struct pool_cache pmap_cache; 279 static LIST_HEAD(, pmap) pmap_pmaps; 280 281 /* 282 * Pool of PV structures 283 */ 284 static struct pool pmap_pv_pool; 285 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 286 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 287 static struct pool_allocator pmap_bootstrap_pv_allocator = { 288 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 289 }; 290 291 /* 292 * Pool and cache of l2_dtable structures. 293 * We use a cache to avoid clearing the structures when they're 294 * allocated. (196 bytes) 295 */ 296 static struct pool_cache pmap_l2dtable_cache; 297 static vaddr_t pmap_kernel_l2dtable_kva; 298 299 /* 300 * Pool and cache of L2 page descriptors. 301 * We use a cache to avoid clearing the descriptor table 302 * when they're allocated. (1KB) 303 */ 304 static struct pool_cache pmap_l2ptp_cache; 305 static vaddr_t pmap_kernel_l2ptp_kva; 306 static paddr_t pmap_kernel_l2ptp_phys; 307 308 #ifdef PMAPCOUNTERS 309 #define PMAP_EVCNT_INITIALIZER(name) \ 310 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 311 312 #ifdef PMAP_CACHE_VIPT 313 static struct evcnt pmap_ev_vac_clean_one = 314 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 315 static struct evcnt pmap_ev_vac_flush_one = 316 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 317 static struct evcnt pmap_ev_vac_flush_lots = 318 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 319 static struct evcnt pmap_ev_vac_flush_lots2 = 320 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 325 326 static struct evcnt pmap_ev_vac_color_new = 327 PMAP_EVCNT_INITIALIZER("new page color"); 328 static struct evcnt pmap_ev_vac_color_reuse = 329 PMAP_EVCNT_INITIALIZER("ok first page color"); 330 static struct evcnt pmap_ev_vac_color_ok = 331 PMAP_EVCNT_INITIALIZER("ok page color"); 332 static struct evcnt pmap_ev_vac_color_blind = 333 PMAP_EVCNT_INITIALIZER("blind page color"); 334 static struct evcnt pmap_ev_vac_color_change = 335 PMAP_EVCNT_INITIALIZER("change page color"); 336 static struct evcnt pmap_ev_vac_color_erase = 337 PMAP_EVCNT_INITIALIZER("erase page color"); 338 static struct evcnt pmap_ev_vac_color_none = 339 PMAP_EVCNT_INITIALIZER("no page color"); 340 static struct evcnt pmap_ev_vac_color_restore = 341 PMAP_EVCNT_INITIALIZER("restore page color"); 342 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 351 #endif 352 353 static struct evcnt pmap_ev_mappings = 354 PMAP_EVCNT_INITIALIZER("pages mapped"); 355 static struct evcnt pmap_ev_unmappings = 356 PMAP_EVCNT_INITIALIZER("pages unmapped"); 357 static struct evcnt pmap_ev_remappings = 358 PMAP_EVCNT_INITIALIZER("pages remapped"); 359 360 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 362 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 363 364 static struct evcnt pmap_ev_kernel_mappings = 365 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 366 static struct evcnt pmap_ev_kernel_unmappings = 367 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 368 static struct evcnt pmap_ev_kernel_remappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 370 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 373 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 374 375 static struct evcnt pmap_ev_kenter_mappings = 376 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 377 static struct evcnt pmap_ev_kenter_unmappings = 378 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 379 static struct evcnt pmap_ev_kenter_remappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 381 static struct evcnt pmap_ev_pt_mappings = 382 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 383 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 387 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 388 389 #ifdef PMAP_CACHE_VIPT 390 static struct evcnt pmap_ev_exec_mappings = 391 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 392 static struct evcnt pmap_ev_exec_cached = 393 PMAP_EVCNT_INITIALIZER("exec pages cached"); 394 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 397 398 static struct evcnt pmap_ev_exec_synced = 399 PMAP_EVCNT_INITIALIZER("exec pages synced"); 400 static struct evcnt pmap_ev_exec_synced_map = 401 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 402 static struct evcnt pmap_ev_exec_synced_unmap = 403 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 404 static struct evcnt pmap_ev_exec_synced_remap = 405 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 406 static struct evcnt pmap_ev_exec_synced_clearbit = 407 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 408 static struct evcnt pmap_ev_exec_synced_kremove = 409 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 410 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 417 418 static struct evcnt pmap_ev_exec_discarded_unmap = 419 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 420 static struct evcnt pmap_ev_exec_discarded_zero = 421 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 422 static struct evcnt pmap_ev_exec_discarded_copy = 423 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 424 static struct evcnt pmap_ev_exec_discarded_page_protect = 425 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 426 static struct evcnt pmap_ev_exec_discarded_clearbit = 427 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 428 static struct evcnt pmap_ev_exec_discarded_kremove = 429 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 430 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 437 #endif /* PMAP_CACHE_VIPT */ 438 439 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 440 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 441 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 442 443 EVCNT_ATTACH_STATIC(pmap_ev_updates); 444 EVCNT_ATTACH_STATIC(pmap_ev_collects); 445 EVCNT_ATTACH_STATIC(pmap_ev_activations); 446 447 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 448 #else 449 #define PMAPCOUNT(x) ((void)0) 450 #endif 451 452 /* 453 * pmap copy/zero page, and mem(5) hook point 454 */ 455 static pt_entry_t *csrc_pte, *cdst_pte; 456 static vaddr_t csrcp, cdstp; 457 vaddr_t memhook; /* used by mem.c */ 458 kmutex_t memlock; /* used by mem.c */ 459 void *zeropage; /* used by mem.c */ 460 extern void *msgbufaddr; 461 int pmap_kmpages; 462 /* 463 * Flag to indicate if pmap_init() has done its thing 464 */ 465 bool pmap_initialized; 466 467 /* 468 * Misc. locking data structures 469 */ 470 471 #define pmap_acquire_pmap_lock(pm) \ 472 do { \ 473 if ((pm) != pmap_kernel()) \ 474 mutex_enter((pm)->pm_lock); \ 475 } while (/*CONSTCOND*/0) 476 477 #define pmap_release_pmap_lock(pm) \ 478 do { \ 479 if ((pm) != pmap_kernel()) \ 480 mutex_exit((pm)->pm_lock); \ 481 } while (/*CONSTCOND*/0) 482 483 484 /* 485 * Metadata for L1 translation tables. 486 */ 487 struct l1_ttable { 488 /* Entry on the L1 Table list */ 489 SLIST_ENTRY(l1_ttable) l1_link; 490 491 /* Entry on the L1 Least Recently Used list */ 492 TAILQ_ENTRY(l1_ttable) l1_lru; 493 494 /* Track how many domains are allocated from this L1 */ 495 volatile u_int l1_domain_use_count; 496 497 /* 498 * A free-list of domain numbers for this L1. 499 * We avoid using ffs() and a bitmap to track domains since ffs() 500 * is slow on ARM. 501 */ 502 uint8_t l1_domain_first; 503 uint8_t l1_domain_free[PMAP_DOMAINS]; 504 505 /* Physical address of this L1 page table */ 506 paddr_t l1_physaddr; 507 508 /* KVA of this L1 page table */ 509 pd_entry_t *l1_kva; 510 }; 511 512 /* 513 * Convert a virtual address into its L1 table index. That is, the 514 * index used to locate the L2 descriptor table pointer in an L1 table. 515 * This is basically used to index l1->l1_kva[]. 516 * 517 * Each L2 descriptor table represents 1MB of VA space. 518 */ 519 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 520 521 /* 522 * L1 Page Tables are tracked using a Least Recently Used list. 523 * - New L1s are allocated from the HEAD. 524 * - Freed L1s are added to the TAIl. 525 * - Recently accessed L1s (where an 'access' is some change to one of 526 * the userland pmaps which owns this L1) are moved to the TAIL. 527 */ 528 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 529 static kmutex_t l1_lru_lock __cacheline_aligned; 530 531 /* 532 * A list of all L1 tables 533 */ 534 static SLIST_HEAD(, l1_ttable) l1_list; 535 536 /* 537 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 538 * 539 * This is normally 16MB worth L2 page descriptors for any given pmap. 540 * Reference counts are maintained for L2 descriptors so they can be 541 * freed when empty. 542 */ 543 struct l2_dtable { 544 /* The number of L2 page descriptors allocated to this l2_dtable */ 545 u_int l2_occupancy; 546 547 /* List of L2 page descriptors */ 548 struct l2_bucket { 549 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 550 paddr_t l2b_phys; /* Physical address of same */ 551 u_short l2b_l1idx; /* This L2 table's L1 index */ 552 u_short l2b_occupancy; /* How many active descriptors */ 553 } l2_bucket[L2_BUCKET_SIZE]; 554 }; 555 556 /* 557 * Given an L1 table index, calculate the corresponding l2_dtable index 558 * and bucket index within the l2_dtable. 559 */ 560 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 561 (L2_SIZE - 1)) 562 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 563 564 /* 565 * Given a virtual address, this macro returns the 566 * virtual address required to drop into the next L2 bucket. 567 */ 568 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 569 570 /* 571 * L2 allocation. 572 */ 573 #define pmap_alloc_l2_dtable() \ 574 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 575 #define pmap_free_l2_dtable(l2) \ 576 pool_cache_put(&pmap_l2dtable_cache, (l2)) 577 #define pmap_alloc_l2_ptp(pap) \ 578 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 579 PR_NOWAIT, (pap))) 580 581 /* 582 * We try to map the page tables write-through, if possible. However, not 583 * all CPUs have a write-through cache mode, so on those we have to sync 584 * the cache when we frob page tables. 585 * 586 * We try to evaluate this at compile time, if possible. However, it's 587 * not always possible to do that, hence this run-time var. 588 */ 589 int pmap_needs_pte_sync; 590 591 /* 592 * Real definition of pv_entry. 593 */ 594 struct pv_entry { 595 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 596 pmap_t pv_pmap; /* pmap where mapping lies */ 597 vaddr_t pv_va; /* virtual address for mapping */ 598 u_int pv_flags; /* flags */ 599 }; 600 601 /* 602 * Macro to determine if a mapping might be resident in the 603 * instruction cache and/or TLB 604 */ 605 #if ARM_MMU_V7 > 0 606 /* 607 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 608 * there are no explicit accesses, so there may be always be TLB entries to 609 * flush. If we used ASIDs then this would not be a problem. 610 */ 611 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 612 #else 613 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 614 #endif 615 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 616 617 /* 618 * Macro to determine if a mapping might be resident in the 619 * data cache and/or TLB 620 */ 621 #if ARM_MMU_V7 > 0 622 /* 623 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 624 * there are no explicit accesses, so there may be always be TLB entries to 625 * flush. If we used ASIDs then this would not be a problem. 626 */ 627 #define PV_BEEN_REFD(f) (1) 628 #else 629 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 630 #endif 631 632 /* 633 * Local prototypes 634 */ 635 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 636 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 637 pt_entry_t **); 638 static bool pmap_is_current(pmap_t); 639 static bool pmap_is_cached(pmap_t); 640 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 641 pmap_t, vaddr_t, u_int); 642 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 643 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 644 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 645 u_int, u_int); 646 647 static void pmap_pinit(pmap_t); 648 static int pmap_pmap_ctor(void *, void *, int); 649 650 static void pmap_alloc_l1(pmap_t); 651 static void pmap_free_l1(pmap_t); 652 static void pmap_use_l1(pmap_t); 653 654 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 655 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 656 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 657 static int pmap_l2ptp_ctor(void *, void *, int); 658 static int pmap_l2dtable_ctor(void *, void *, int); 659 660 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 661 #ifdef PMAP_CACHE_VIVT 662 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 663 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 664 #endif 665 666 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 667 #ifdef PMAP_CACHE_VIVT 668 static int pmap_clean_page(struct pv_entry *, bool); 669 #endif 670 #ifdef PMAP_CACHE_VIPT 671 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 672 enum pmap_flush_op { 673 PMAP_FLUSH_PRIMARY, 674 PMAP_FLUSH_SECONDARY, 675 PMAP_CLEAN_PRIMARY 676 }; 677 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 678 #endif 679 static void pmap_page_remove(struct vm_page_md *, paddr_t); 680 681 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 682 static vaddr_t kernel_pt_lookup(paddr_t); 683 684 685 /* 686 * Misc variables 687 */ 688 vaddr_t virtual_avail; 689 vaddr_t virtual_end; 690 vaddr_t pmap_curmaxkvaddr; 691 692 paddr_t avail_start; 693 paddr_t avail_end; 694 695 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 696 pv_addr_t kernelpages; 697 pv_addr_t kernel_l1pt; 698 pv_addr_t systempage; 699 700 /* Function to set the debug level of the pmap code */ 701 702 #ifdef PMAP_DEBUG 703 void 704 pmap_debug(int level) 705 { 706 pmap_debug_level = level; 707 printf("pmap_debug: level=%d\n", pmap_debug_level); 708 } 709 #endif /* PMAP_DEBUG */ 710 711 #ifdef PMAP_CACHE_VIPT 712 #define PMAP_VALIDATE_MD_PAGE(md) \ 713 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 714 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 715 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 716 #endif /* PMAP_CACHE_VIPT */ 717 /* 718 * A bunch of routines to conditionally flush the caches/TLB depending 719 * on whether the specified pmap actually needs to be flushed at any 720 * given time. 721 */ 722 static inline void 723 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 724 { 725 if (pm->pm_cstate.cs_tlb_id != 0) { 726 if (PV_BEEN_EXECD(flags)) { 727 cpu_tlb_flushID_SE(va); 728 } else if (PV_BEEN_REFD(flags)) { 729 cpu_tlb_flushD_SE(va); 730 } 731 } 732 } 733 734 static inline void 735 pmap_tlb_flushID(pmap_t pm) 736 { 737 if (pm->pm_cstate.cs_tlb_id) { 738 cpu_tlb_flushID(); 739 #if ARM_MMU_V7 == 0 740 /* 741 * Speculative loads by Cortex cores can cause TLB entries to 742 * be filled even if there are no explicit accesses, so there 743 * may be always be TLB entries to flush. If we used ASIDs 744 * then it would not be a problem. 745 * This is not true for other CPUs. 746 */ 747 pm->pm_cstate.cs_tlb = 0; 748 #endif /* ARM_MMU_V7 */ 749 } 750 } 751 752 static inline void 753 pmap_tlb_flushD(pmap_t pm) 754 { 755 if (pm->pm_cstate.cs_tlb_d) { 756 cpu_tlb_flushD(); 757 #if ARM_MMU_V7 == 0 758 /* 759 * Speculative loads by Cortex cores can cause TLB entries to 760 * be filled even if there are no explicit accesses, so there 761 * may be always be TLB entries to flush. If we used ASIDs 762 * then it would not be a problem. 763 * This is not true for other CPUs. 764 */ 765 pm->pm_cstate.cs_tlb_d = 0; 766 #endif /* ARM_MMU_V7 */ 767 } 768 } 769 770 #ifdef PMAP_CACHE_VIVT 771 static inline void 772 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 773 { 774 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 775 cpu_idcache_wbinv_range(va, PAGE_SIZE); 776 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 777 if (do_inv) { 778 if (flags & PVF_WRITE) 779 cpu_dcache_wbinv_range(va, PAGE_SIZE); 780 else 781 cpu_dcache_inv_range(va, PAGE_SIZE); 782 } else if (flags & PVF_WRITE) { 783 cpu_dcache_wb_range(va, PAGE_SIZE); 784 } 785 } 786 } 787 788 static inline void 789 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 790 { 791 if (PV_BEEN_EXECD(flags)) { 792 if (pm->pm_cstate.cs_cache_id) { 793 cpu_idcache_wbinv_all(); 794 pm->pm_cstate.cs_cache = 0; 795 } 796 } else if (pm->pm_cstate.cs_cache_d) { 797 cpu_dcache_wbinv_all(); 798 pm->pm_cstate.cs_cache_d = 0; 799 } 800 } 801 #endif /* PMAP_CACHE_VIVT */ 802 803 static inline uint8_t 804 pmap_domain(pmap_t pm) 805 { 806 return pm->pm_domain; 807 } 808 809 static inline pd_entry_t * 810 pmap_l1_kva(pmap_t pm) 811 { 812 return pm->pm_l1->l1_kva; 813 } 814 815 static inline bool 816 pmap_is_current(pmap_t pm) 817 { 818 819 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 820 return true; 821 822 return false; 823 } 824 825 static inline bool 826 pmap_is_cached(pmap_t pm) 827 { 828 829 if (pm == pmap_kernel() || pmap_recent_user == NULL || 830 pmap_recent_user == pm) 831 return (true); 832 833 return false; 834 } 835 836 /* 837 * PTE_SYNC_CURRENT: 838 * 839 * Make sure the pte is written out to RAM. 840 * We need to do this for one of two cases: 841 * - We're dealing with the kernel pmap 842 * - There is no pmap active in the cache/tlb. 843 * - The specified pmap is 'active' in the cache/tlb. 844 */ 845 #ifdef PMAP_INCLUDE_PTE_SYNC 846 #define PTE_SYNC_CURRENT(pm, ptep) \ 847 do { \ 848 if (PMAP_NEEDS_PTE_SYNC && \ 849 pmap_is_cached(pm)) \ 850 PTE_SYNC(ptep); \ 851 } while (/*CONSTCOND*/0) 852 #else 853 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 854 #endif 855 856 /* 857 * main pv_entry manipulation functions: 858 * pmap_enter_pv: enter a mapping onto a vm_page list 859 * pmap_remove_pv: remove a mapping from a vm_page list 860 * 861 * NOTE: pmap_enter_pv expects to lock the pvh itself 862 * pmap_remove_pv expects the caller to lock the pvh before calling 863 */ 864 865 /* 866 * pmap_enter_pv: enter a mapping onto a vm_page lst 867 * 868 * => caller should hold the proper lock on pmap_main_lock 869 * => caller should have pmap locked 870 * => we will gain the lock on the vm_page and allocate the new pv_entry 871 * => caller should adjust ptp's wire_count before calling 872 * => caller should not adjust pmap's wire_count 873 */ 874 static void 875 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 876 vaddr_t va, u_int flags) 877 { 878 struct pv_entry **pvp; 879 880 NPDEBUG(PDB_PVDUMP, 881 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 882 883 pv->pv_pmap = pm; 884 pv->pv_va = va; 885 pv->pv_flags = flags; 886 887 pvp = &SLIST_FIRST(&md->pvh_list); 888 #ifdef PMAP_CACHE_VIPT 889 /* 890 * Insert unmanaged entries, writeable first, at the head of 891 * the pv list. 892 */ 893 if (__predict_true((flags & PVF_KENTRY) == 0)) { 894 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 895 pvp = &SLIST_NEXT(*pvp, pv_link); 896 } else if ((flags & PVF_WRITE) == 0) { 897 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 898 pvp = &SLIST_NEXT(*pvp, pv_link); 899 } 900 #endif 901 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 902 *pvp = pv; /* ... locked list */ 903 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 904 #ifdef PMAP_CACHE_VIPT 905 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 906 md->pvh_attrs |= PVF_KMOD; 907 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 908 md->pvh_attrs |= PVF_DIRTY; 909 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 910 #endif 911 if (pm == pmap_kernel()) { 912 PMAPCOUNT(kernel_mappings); 913 if (flags & PVF_WRITE) 914 md->krw_mappings++; 915 else 916 md->kro_mappings++; 917 } else { 918 if (flags & PVF_WRITE) 919 md->urw_mappings++; 920 else 921 md->uro_mappings++; 922 } 923 924 #ifdef PMAP_CACHE_VIPT 925 /* 926 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 927 * do it here as well to keep the mappings & KVF_WRITE consistent. 928 */ 929 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 930 md->pvh_attrs |= PVF_WRITE; 931 } 932 /* 933 * If this is an exec mapping and its the first exec mapping 934 * for this page, make sure to sync the I-cache. 935 */ 936 if (PV_IS_EXEC_P(flags)) { 937 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 938 pmap_syncicache_page(md, pa); 939 PMAPCOUNT(exec_synced_map); 940 } 941 PMAPCOUNT(exec_mappings); 942 } 943 #endif 944 945 PMAPCOUNT(mappings); 946 947 if (pv->pv_flags & PVF_WIRED) 948 ++pm->pm_stats.wired_count; 949 } 950 951 /* 952 * 953 * pmap_find_pv: Find a pv entry 954 * 955 * => caller should hold lock on vm_page 956 */ 957 static inline struct pv_entry * 958 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 959 { 960 struct pv_entry *pv; 961 962 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 963 if (pm == pv->pv_pmap && va == pv->pv_va) 964 break; 965 } 966 967 return (pv); 968 } 969 970 /* 971 * pmap_remove_pv: try to remove a mapping from a pv_list 972 * 973 * => caller should hold proper lock on pmap_main_lock 974 * => pmap should be locked 975 * => caller should hold lock on vm_page [so that attrs can be adjusted] 976 * => caller should adjust ptp's wire_count and free PTP if needed 977 * => caller should NOT adjust pmap's wire_count 978 * => we return the removed pv 979 */ 980 static struct pv_entry * 981 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 982 { 983 struct pv_entry *pv, **prevptr; 984 985 NPDEBUG(PDB_PVDUMP, 986 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 987 988 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 989 pv = *prevptr; 990 991 while (pv) { 992 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 993 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 994 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 995 if (pv->pv_flags & PVF_WIRED) { 996 --pm->pm_stats.wired_count; 997 } 998 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 999 if (pm == pmap_kernel()) { 1000 PMAPCOUNT(kernel_unmappings); 1001 if (pv->pv_flags & PVF_WRITE) 1002 md->krw_mappings--; 1003 else 1004 md->kro_mappings--; 1005 } else { 1006 if (pv->pv_flags & PVF_WRITE) 1007 md->urw_mappings--; 1008 else 1009 md->uro_mappings--; 1010 } 1011 1012 PMAPCOUNT(unmappings); 1013 #ifdef PMAP_CACHE_VIPT 1014 if (!(pv->pv_flags & PVF_WRITE)) 1015 break; 1016 /* 1017 * If this page has had an exec mapping, then if 1018 * this was the last mapping, discard the contents, 1019 * otherwise sync the i-cache for this page. 1020 */ 1021 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1022 if (SLIST_EMPTY(&md->pvh_list)) { 1023 md->pvh_attrs &= ~PVF_EXEC; 1024 PMAPCOUNT(exec_discarded_unmap); 1025 } else { 1026 pmap_syncicache_page(md, pa); 1027 PMAPCOUNT(exec_synced_unmap); 1028 } 1029 } 1030 #endif /* PMAP_CACHE_VIPT */ 1031 break; 1032 } 1033 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1034 pv = *prevptr; /* advance */ 1035 } 1036 1037 #ifdef PMAP_CACHE_VIPT 1038 /* 1039 * If we no longer have a WRITEABLE KENTRY at the head of list, 1040 * clear the KMOD attribute from the page. 1041 */ 1042 if (SLIST_FIRST(&md->pvh_list) == NULL 1043 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1044 md->pvh_attrs &= ~PVF_KMOD; 1045 1046 /* 1047 * If this was a writeable page and there are no more writeable 1048 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1049 * the contents to memory. 1050 */ 1051 if (arm_cache_prefer_mask != 0) { 1052 if (md->krw_mappings + md->urw_mappings == 0) 1053 md->pvh_attrs &= ~PVF_WRITE; 1054 PMAP_VALIDATE_MD_PAGE(md); 1055 } 1056 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1057 #endif /* PMAP_CACHE_VIPT */ 1058 1059 return(pv); /* return removed pv */ 1060 } 1061 1062 /* 1063 * 1064 * pmap_modify_pv: Update pv flags 1065 * 1066 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1067 * => caller should NOT adjust pmap's wire_count 1068 * => caller must call pmap_vac_me_harder() if writable status of a page 1069 * may have changed. 1070 * => we return the old flags 1071 * 1072 * Modify a physical-virtual mapping in the pv table 1073 */ 1074 static u_int 1075 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1076 u_int clr_mask, u_int set_mask) 1077 { 1078 struct pv_entry *npv; 1079 u_int flags, oflags; 1080 1081 KASSERT((clr_mask & PVF_KENTRY) == 0); 1082 KASSERT((set_mask & PVF_KENTRY) == 0); 1083 1084 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1085 return (0); 1086 1087 NPDEBUG(PDB_PVDUMP, 1088 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1089 1090 /* 1091 * There is at least one VA mapping this page. 1092 */ 1093 1094 if (clr_mask & (PVF_REF | PVF_MOD)) { 1095 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1096 #ifdef PMAP_CACHE_VIPT 1097 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1098 md->pvh_attrs |= PVF_DIRTY; 1099 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1100 #endif 1101 } 1102 1103 oflags = npv->pv_flags; 1104 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1105 1106 if ((flags ^ oflags) & PVF_WIRED) { 1107 if (flags & PVF_WIRED) 1108 ++pm->pm_stats.wired_count; 1109 else 1110 --pm->pm_stats.wired_count; 1111 } 1112 1113 if ((flags ^ oflags) & PVF_WRITE) { 1114 if (pm == pmap_kernel()) { 1115 if (flags & PVF_WRITE) { 1116 md->krw_mappings++; 1117 md->kro_mappings--; 1118 } else { 1119 md->kro_mappings++; 1120 md->krw_mappings--; 1121 } 1122 } else { 1123 if (flags & PVF_WRITE) { 1124 md->urw_mappings++; 1125 md->uro_mappings--; 1126 } else { 1127 md->uro_mappings++; 1128 md->urw_mappings--; 1129 } 1130 } 1131 } 1132 #ifdef PMAP_CACHE_VIPT 1133 if (arm_cache_prefer_mask != 0) { 1134 if (md->urw_mappings + md->krw_mappings == 0) { 1135 md->pvh_attrs &= ~PVF_WRITE; 1136 } else { 1137 md->pvh_attrs |= PVF_WRITE; 1138 } 1139 } 1140 /* 1141 * We have two cases here: the first is from enter_pv (new exec 1142 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1143 * Since in latter, pmap_enter_pv won't do anything, we just have 1144 * to do what pmap_remove_pv would do. 1145 */ 1146 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1147 || (PV_IS_EXEC_P(md->pvh_attrs) 1148 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1149 pmap_syncicache_page(md, pa); 1150 PMAPCOUNT(exec_synced_remap); 1151 } 1152 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1153 #endif 1154 1155 PMAPCOUNT(remappings); 1156 1157 return (oflags); 1158 } 1159 1160 /* 1161 * Allocate an L1 translation table for the specified pmap. 1162 * This is called at pmap creation time. 1163 */ 1164 static void 1165 pmap_alloc_l1(pmap_t pm) 1166 { 1167 struct l1_ttable *l1; 1168 uint8_t domain; 1169 1170 /* 1171 * Remove the L1 at the head of the LRU list 1172 */ 1173 mutex_spin_enter(&l1_lru_lock); 1174 l1 = TAILQ_FIRST(&l1_lru_list); 1175 KDASSERT(l1 != NULL); 1176 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1177 1178 /* 1179 * Pick the first available domain number, and update 1180 * the link to the next number. 1181 */ 1182 domain = l1->l1_domain_first; 1183 l1->l1_domain_first = l1->l1_domain_free[domain]; 1184 1185 /* 1186 * If there are still free domain numbers in this L1, 1187 * put it back on the TAIL of the LRU list. 1188 */ 1189 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1190 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1191 1192 mutex_spin_exit(&l1_lru_lock); 1193 1194 /* 1195 * Fix up the relevant bits in the pmap structure 1196 */ 1197 pm->pm_l1 = l1; 1198 pm->pm_domain = domain + 1; 1199 } 1200 1201 /* 1202 * Free an L1 translation table. 1203 * This is called at pmap destruction time. 1204 */ 1205 static void 1206 pmap_free_l1(pmap_t pm) 1207 { 1208 struct l1_ttable *l1 = pm->pm_l1; 1209 1210 mutex_spin_enter(&l1_lru_lock); 1211 1212 /* 1213 * If this L1 is currently on the LRU list, remove it. 1214 */ 1215 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1216 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1217 1218 /* 1219 * Free up the domain number which was allocated to the pmap 1220 */ 1221 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1222 l1->l1_domain_first = pmap_domain(pm) - 1; 1223 l1->l1_domain_use_count--; 1224 1225 /* 1226 * The L1 now must have at least 1 free domain, so add 1227 * it back to the LRU list. If the use count is zero, 1228 * put it at the head of the list, otherwise it goes 1229 * to the tail. 1230 */ 1231 if (l1->l1_domain_use_count == 0) 1232 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1233 else 1234 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1235 1236 mutex_spin_exit(&l1_lru_lock); 1237 } 1238 1239 static inline void 1240 pmap_use_l1(pmap_t pm) 1241 { 1242 struct l1_ttable *l1; 1243 1244 /* 1245 * Do nothing if we're in interrupt context. 1246 * Access to an L1 by the kernel pmap must not affect 1247 * the LRU list. 1248 */ 1249 if (cpu_intr_p() || pm == pmap_kernel()) 1250 return; 1251 1252 l1 = pm->pm_l1; 1253 1254 /* 1255 * If the L1 is not currently on the LRU list, just return 1256 */ 1257 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1258 return; 1259 1260 mutex_spin_enter(&l1_lru_lock); 1261 1262 /* 1263 * Check the use count again, now that we've acquired the lock 1264 */ 1265 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1266 mutex_spin_exit(&l1_lru_lock); 1267 return; 1268 } 1269 1270 /* 1271 * Move the L1 to the back of the LRU list 1272 */ 1273 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1274 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1275 1276 mutex_spin_exit(&l1_lru_lock); 1277 } 1278 1279 /* 1280 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1281 * 1282 * Free an L2 descriptor table. 1283 */ 1284 static inline void 1285 #ifndef PMAP_INCLUDE_PTE_SYNC 1286 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1287 #else 1288 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1289 #endif 1290 { 1291 #ifdef PMAP_INCLUDE_PTE_SYNC 1292 #ifdef PMAP_CACHE_VIVT 1293 /* 1294 * Note: With a write-back cache, we may need to sync this 1295 * L2 table before re-using it. 1296 * This is because it may have belonged to a non-current 1297 * pmap, in which case the cache syncs would have been 1298 * skipped for the pages that were being unmapped. If the 1299 * L2 table were then to be immediately re-allocated to 1300 * the *current* pmap, it may well contain stale mappings 1301 * which have not yet been cleared by a cache write-back 1302 * and so would still be visible to the mmu. 1303 */ 1304 if (need_sync) 1305 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1306 #endif /* PMAP_CACHE_VIVT */ 1307 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1308 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1309 } 1310 1311 /* 1312 * Returns a pointer to the L2 bucket associated with the specified pmap 1313 * and VA, or NULL if no L2 bucket exists for the address. 1314 */ 1315 static inline struct l2_bucket * 1316 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1317 { 1318 struct l2_dtable *l2; 1319 struct l2_bucket *l2b; 1320 u_short l1idx; 1321 1322 l1idx = L1_IDX(va); 1323 1324 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1325 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1326 return (NULL); 1327 1328 return (l2b); 1329 } 1330 1331 /* 1332 * Returns a pointer to the L2 bucket associated with the specified pmap 1333 * and VA. 1334 * 1335 * If no L2 bucket exists, perform the necessary allocations to put an L2 1336 * bucket/page table in place. 1337 * 1338 * Note that if a new L2 bucket/page was allocated, the caller *must* 1339 * increment the bucket occupancy counter appropriately *before* 1340 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1341 * the bucket/page in the meantime. 1342 */ 1343 static struct l2_bucket * 1344 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1345 { 1346 struct l2_dtable *l2; 1347 struct l2_bucket *l2b; 1348 u_short l1idx; 1349 1350 l1idx = L1_IDX(va); 1351 1352 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1353 /* 1354 * No mapping at this address, as there is 1355 * no entry in the L1 table. 1356 * Need to allocate a new l2_dtable. 1357 */ 1358 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1359 return (NULL); 1360 1361 /* 1362 * Link it into the parent pmap 1363 */ 1364 pm->pm_l2[L2_IDX(l1idx)] = l2; 1365 } 1366 1367 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1368 1369 /* 1370 * Fetch pointer to the L2 page table associated with the address. 1371 */ 1372 if (l2b->l2b_kva == NULL) { 1373 pt_entry_t *ptep; 1374 1375 /* 1376 * No L2 page table has been allocated. Chances are, this 1377 * is because we just allocated the l2_dtable, above. 1378 */ 1379 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1380 /* 1381 * Oops, no more L2 page tables available at this 1382 * time. We may need to deallocate the l2_dtable 1383 * if we allocated a new one above. 1384 */ 1385 if (l2->l2_occupancy == 0) { 1386 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1387 pmap_free_l2_dtable(l2); 1388 } 1389 return (NULL); 1390 } 1391 1392 l2->l2_occupancy++; 1393 l2b->l2b_kva = ptep; 1394 l2b->l2b_l1idx = l1idx; 1395 } 1396 1397 return (l2b); 1398 } 1399 1400 /* 1401 * One or more mappings in the specified L2 descriptor table have just been 1402 * invalidated. 1403 * 1404 * Garbage collect the metadata and descriptor table itself if necessary. 1405 * 1406 * The pmap lock must be acquired when this is called (not necessary 1407 * for the kernel pmap). 1408 */ 1409 static void 1410 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1411 { 1412 struct l2_dtable *l2; 1413 pd_entry_t *pl1pd, l1pd; 1414 pt_entry_t *ptep; 1415 u_short l1idx; 1416 1417 KDASSERT(count <= l2b->l2b_occupancy); 1418 1419 /* 1420 * Update the bucket's reference count according to how many 1421 * PTEs the caller has just invalidated. 1422 */ 1423 l2b->l2b_occupancy -= count; 1424 1425 /* 1426 * Note: 1427 * 1428 * Level 2 page tables allocated to the kernel pmap are never freed 1429 * as that would require checking all Level 1 page tables and 1430 * removing any references to the Level 2 page table. See also the 1431 * comment elsewhere about never freeing bootstrap L2 descriptors. 1432 * 1433 * We make do with just invalidating the mapping in the L2 table. 1434 * 1435 * This isn't really a big deal in practice and, in fact, leads 1436 * to a performance win over time as we don't need to continually 1437 * alloc/free. 1438 */ 1439 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1440 return; 1441 1442 /* 1443 * There are no more valid mappings in this level 2 page table. 1444 * Go ahead and NULL-out the pointer in the bucket, then 1445 * free the page table. 1446 */ 1447 l1idx = l2b->l2b_l1idx; 1448 ptep = l2b->l2b_kva; 1449 l2b->l2b_kva = NULL; 1450 1451 pl1pd = pmap_l1_kva(pm) + l1idx; 1452 1453 /* 1454 * If the L1 slot matches the pmap's domain 1455 * number, then invalidate it. 1456 */ 1457 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1458 if (l1pd == (L1_C_DOM(pmap_domain(pm)) | L1_TYPE_C)) { 1459 *pl1pd = 0; 1460 PTE_SYNC(pl1pd); 1461 } 1462 1463 /* 1464 * Release the L2 descriptor table back to the pool cache. 1465 */ 1466 #ifndef PMAP_INCLUDE_PTE_SYNC 1467 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1468 #else 1469 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1470 #endif 1471 1472 /* 1473 * Update the reference count in the associated l2_dtable 1474 */ 1475 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1476 if (--l2->l2_occupancy > 0) 1477 return; 1478 1479 /* 1480 * There are no more valid mappings in any of the Level 1 1481 * slots managed by this l2_dtable. Go ahead and NULL-out 1482 * the pointer in the parent pmap and free the l2_dtable. 1483 */ 1484 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1485 pmap_free_l2_dtable(l2); 1486 } 1487 1488 /* 1489 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1490 * structures. 1491 */ 1492 static int 1493 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1494 { 1495 #ifndef PMAP_INCLUDE_PTE_SYNC 1496 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1497 1498 /* 1499 * The mappings for these page tables were initially made using 1500 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1501 * mode will not be right for page table mappings. To avoid 1502 * polluting the pmap_kenter_pa() code with a special case for 1503 * page tables, we simply fix up the cache-mode here if it's not 1504 * correct. 1505 */ 1506 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1507 KDASSERT(l2b != NULL); 1508 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 1509 pt_entry_t opte = *ptep; 1510 1511 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1512 /* 1513 * Page tables must have the cache-mode set to Write-Thru. 1514 */ 1515 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1516 | pte_l2_s_cache_mode_pt; 1517 l2pte_set(ptep, npte, opte); 1518 PTE_SYNC(ptep); 1519 cpu_tlb_flushD_SE(va); 1520 cpu_cpwait(); 1521 } 1522 #endif 1523 1524 memset(v, 0, L2_TABLE_SIZE_REAL); 1525 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1526 return (0); 1527 } 1528 1529 static int 1530 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1531 { 1532 1533 memset(v, 0, sizeof(struct l2_dtable)); 1534 return (0); 1535 } 1536 1537 static int 1538 pmap_pmap_ctor(void *arg, void *v, int flags) 1539 { 1540 1541 memset(v, 0, sizeof(struct pmap)); 1542 return (0); 1543 } 1544 1545 static void 1546 pmap_pinit(pmap_t pm) 1547 { 1548 #ifndef ARM_HAS_VBAR 1549 struct l2_bucket *l2b; 1550 1551 if (vector_page < KERNEL_BASE) { 1552 /* 1553 * Map the vector page. 1554 */ 1555 pmap_enter(pm, vector_page, systempage.pv_pa, 1556 VM_PROT_READ | VM_PROT_EXECUTE, 1557 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1558 pmap_update(pm); 1559 1560 pm->pm_pl1vec = pmap_l1_kva(pm) + L1_IDX(vector_page); 1561 l2b = pmap_get_l2_bucket(pm, vector_page); 1562 KDASSERT(l2b != NULL); 1563 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1564 L1_C_DOM(pmap_domain(pm)); 1565 } else 1566 pm->pm_pl1vec = NULL; 1567 #endif 1568 } 1569 1570 #ifdef PMAP_CACHE_VIVT 1571 /* 1572 * Since we have a virtually indexed cache, we may need to inhibit caching if 1573 * there is more than one mapping and at least one of them is writable. 1574 * Since we purge the cache on every context switch, we only need to check for 1575 * other mappings within the same pmap, or kernel_pmap. 1576 * This function is also called when a page is unmapped, to possibly reenable 1577 * caching on any remaining mappings. 1578 * 1579 * The code implements the following logic, where: 1580 * 1581 * KW = # of kernel read/write pages 1582 * KR = # of kernel read only pages 1583 * UW = # of user read/write pages 1584 * UR = # of user read only pages 1585 * 1586 * KC = kernel mapping is cacheable 1587 * UC = user mapping is cacheable 1588 * 1589 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1590 * +--------------------------------------------- 1591 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1592 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1593 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1594 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1595 */ 1596 1597 static const int pmap_vac_flags[4][4] = { 1598 {-1, 0, 0, PVF_KNC}, 1599 {0, 0, PVF_NC, PVF_NC}, 1600 {0, PVF_NC, PVF_NC, PVF_NC}, 1601 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1602 }; 1603 1604 static inline int 1605 pmap_get_vac_flags(const struct vm_page_md *md) 1606 { 1607 int kidx, uidx; 1608 1609 kidx = 0; 1610 if (md->kro_mappings || md->krw_mappings > 1) 1611 kidx |= 1; 1612 if (md->krw_mappings) 1613 kidx |= 2; 1614 1615 uidx = 0; 1616 if (md->uro_mappings || md->urw_mappings > 1) 1617 uidx |= 1; 1618 if (md->urw_mappings) 1619 uidx |= 2; 1620 1621 return (pmap_vac_flags[uidx][kidx]); 1622 } 1623 1624 static inline void 1625 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1626 { 1627 int nattr; 1628 1629 nattr = pmap_get_vac_flags(md); 1630 1631 if (nattr < 0) { 1632 md->pvh_attrs &= ~PVF_NC; 1633 return; 1634 } 1635 1636 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1637 return; 1638 1639 if (pm == pmap_kernel()) 1640 pmap_vac_me_kpmap(md, pa, pm, va); 1641 else 1642 pmap_vac_me_user(md, pa, pm, va); 1643 1644 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1645 } 1646 1647 static void 1648 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1649 { 1650 u_int u_cacheable, u_entries; 1651 struct pv_entry *pv; 1652 pmap_t last_pmap = pm; 1653 1654 /* 1655 * Pass one, see if there are both kernel and user pmaps for 1656 * this page. Calculate whether there are user-writable or 1657 * kernel-writable pages. 1658 */ 1659 u_cacheable = 0; 1660 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1661 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1662 u_cacheable++; 1663 } 1664 1665 u_entries = md->urw_mappings + md->uro_mappings; 1666 1667 /* 1668 * We know we have just been updating a kernel entry, so if 1669 * all user pages are already cacheable, then there is nothing 1670 * further to do. 1671 */ 1672 if (md->k_mappings == 0 && u_cacheable == u_entries) 1673 return; 1674 1675 if (u_entries) { 1676 /* 1677 * Scan over the list again, for each entry, if it 1678 * might not be set correctly, call pmap_vac_me_user 1679 * to recalculate the settings. 1680 */ 1681 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1682 /* 1683 * We know kernel mappings will get set 1684 * correctly in other calls. We also know 1685 * that if the pmap is the same as last_pmap 1686 * then we've just handled this entry. 1687 */ 1688 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1689 continue; 1690 1691 /* 1692 * If there are kernel entries and this page 1693 * is writable but non-cacheable, then we can 1694 * skip this entry also. 1695 */ 1696 if (md->k_mappings && 1697 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1698 (PVF_NC | PVF_WRITE)) 1699 continue; 1700 1701 /* 1702 * Similarly if there are no kernel-writable 1703 * entries and the page is already 1704 * read-only/cacheable. 1705 */ 1706 if (md->krw_mappings == 0 && 1707 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1708 continue; 1709 1710 /* 1711 * For some of the remaining cases, we know 1712 * that we must recalculate, but for others we 1713 * can't tell if they are correct or not, so 1714 * we recalculate anyway. 1715 */ 1716 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1717 } 1718 1719 if (md->k_mappings == 0) 1720 return; 1721 } 1722 1723 pmap_vac_me_user(md, pa, pm, va); 1724 } 1725 1726 static void 1727 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1728 { 1729 pmap_t kpmap = pmap_kernel(); 1730 struct pv_entry *pv, *npv = NULL; 1731 u_int entries = 0; 1732 u_int writable = 0; 1733 u_int cacheable_entries = 0; 1734 u_int kern_cacheable = 0; 1735 u_int other_writable = 0; 1736 1737 /* 1738 * Count mappings and writable mappings in this pmap. 1739 * Include kernel mappings as part of our own. 1740 * Keep a pointer to the first one. 1741 */ 1742 npv = NULL; 1743 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1744 /* Count mappings in the same pmap */ 1745 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1746 if (entries++ == 0) 1747 npv = pv; 1748 1749 /* Cacheable mappings */ 1750 if ((pv->pv_flags & PVF_NC) == 0) { 1751 cacheable_entries++; 1752 if (kpmap == pv->pv_pmap) 1753 kern_cacheable++; 1754 } 1755 1756 /* Writable mappings */ 1757 if (pv->pv_flags & PVF_WRITE) 1758 ++writable; 1759 } else 1760 if (pv->pv_flags & PVF_WRITE) 1761 other_writable = 1; 1762 } 1763 1764 /* 1765 * Enable or disable caching as necessary. 1766 * Note: the first entry might be part of the kernel pmap, 1767 * so we can't assume this is indicative of the state of the 1768 * other (maybe non-kpmap) entries. 1769 */ 1770 if ((entries > 1 && writable) || 1771 (entries > 0 && pm == kpmap && other_writable)) { 1772 if (cacheable_entries == 0) 1773 return; 1774 1775 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1776 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1777 (pv->pv_flags & PVF_NC)) 1778 continue; 1779 1780 pv->pv_flags |= PVF_NC; 1781 1782 struct l2_bucket * const l2b 1783 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1784 KDASSERT(l2b != NULL); 1785 pt_entry_t * const ptep 1786 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1787 const pt_entry_t opte = *ptep; 1788 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1789 1790 if ((va != pv->pv_va || pm != pv->pv_pmap) 1791 && l2pte_valid(npte)) { 1792 #ifdef PMAP_CACHE_VIVT 1793 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1794 true, pv->pv_flags); 1795 #endif 1796 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1797 pv->pv_flags); 1798 } 1799 1800 l2pte_set(ptep, npte, opte); 1801 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1802 } 1803 cpu_cpwait(); 1804 } else 1805 if (entries > cacheable_entries) { 1806 /* 1807 * Turn cacheing back on for some pages. If it is a kernel 1808 * page, only do so if there are no other writable pages. 1809 */ 1810 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1811 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1812 (kpmap != pv->pv_pmap || other_writable))) 1813 continue; 1814 1815 pv->pv_flags &= ~PVF_NC; 1816 1817 struct l2_bucket * const l2b 1818 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1819 KDASSERT(l2b != NULL); 1820 pt_entry_t * const ptep 1821 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1822 const pt_entry_t opte = *ptep; 1823 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1824 | pte_l2_s_cache_mode; 1825 1826 if (l2pte_valid(opte)) { 1827 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1828 pv->pv_flags); 1829 } 1830 1831 l2pte_set(ptep, npte, opte); 1832 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1833 } 1834 } 1835 } 1836 #endif 1837 1838 #ifdef PMAP_CACHE_VIPT 1839 static void 1840 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1841 { 1842 struct pv_entry *pv; 1843 vaddr_t tst_mask; 1844 bool bad_alias; 1845 const u_int 1846 rw_mappings = md->urw_mappings + md->krw_mappings, 1847 ro_mappings = md->uro_mappings + md->kro_mappings; 1848 1849 /* do we need to do anything? */ 1850 if (arm_cache_prefer_mask == 0) 1851 return; 1852 1853 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1854 md, pm, va)); 1855 1856 KASSERT(!va || pm); 1857 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1858 1859 /* Already a conflict? */ 1860 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1861 /* just an add, things are already non-cached */ 1862 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1863 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1864 bad_alias = false; 1865 if (va) { 1866 PMAPCOUNT(vac_color_none); 1867 bad_alias = true; 1868 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1869 goto fixup; 1870 } 1871 pv = SLIST_FIRST(&md->pvh_list); 1872 /* the list can't be empty because it would be cachable */ 1873 if (md->pvh_attrs & PVF_KMPAGE) { 1874 tst_mask = md->pvh_attrs; 1875 } else { 1876 KASSERT(pv); 1877 tst_mask = pv->pv_va; 1878 pv = SLIST_NEXT(pv, pv_link); 1879 } 1880 /* 1881 * Only check for a bad alias if we have writable mappings. 1882 */ 1883 tst_mask &= arm_cache_prefer_mask; 1884 if (rw_mappings > 0) { 1885 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1886 /* if there's a bad alias, stop checking. */ 1887 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1888 bad_alias = true; 1889 } 1890 md->pvh_attrs |= PVF_WRITE; 1891 if (!bad_alias) 1892 md->pvh_attrs |= PVF_DIRTY; 1893 } else { 1894 /* 1895 * We have only read-only mappings. Let's see if there 1896 * are multiple colors in use or if we mapped a KMPAGE. 1897 * If the latter, we have a bad alias. If the former, 1898 * we need to remember that. 1899 */ 1900 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1901 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1902 if (md->pvh_attrs & PVF_KMPAGE) 1903 bad_alias = true; 1904 break; 1905 } 1906 } 1907 md->pvh_attrs &= ~PVF_WRITE; 1908 /* 1909 * No KMPAGE and we exited early, so we must have 1910 * multiple color mappings. 1911 */ 1912 if (!bad_alias && pv != NULL) 1913 md->pvh_attrs |= PVF_MULTCLR; 1914 } 1915 1916 /* If no conflicting colors, set everything back to cached */ 1917 if (!bad_alias) { 1918 #ifdef DEBUG 1919 if ((md->pvh_attrs & PVF_WRITE) 1920 || ro_mappings < 2) { 1921 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1922 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1923 } 1924 #endif 1925 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1926 md->pvh_attrs |= tst_mask | PVF_COLORED; 1927 /* 1928 * Restore DIRTY bit if page is modified 1929 */ 1930 if (md->pvh_attrs & PVF_DMOD) 1931 md->pvh_attrs |= PVF_DIRTY; 1932 PMAPCOUNT(vac_color_restore); 1933 } else { 1934 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1935 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1936 } 1937 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1938 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1939 } else if (!va) { 1940 KASSERT(pmap_is_page_colored_p(md)); 1941 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1942 || (md->pvh_attrs & PVF_DIRTY)); 1943 if (rw_mappings == 0) { 1944 md->pvh_attrs &= ~PVF_WRITE; 1945 if (ro_mappings == 1 1946 && (md->pvh_attrs & PVF_MULTCLR)) { 1947 /* 1948 * If this is the last readonly mapping 1949 * but it doesn't match the current color 1950 * for the page, change the current color 1951 * to match this last readonly mapping. 1952 */ 1953 pv = SLIST_FIRST(&md->pvh_list); 1954 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1955 & arm_cache_prefer_mask; 1956 if (tst_mask) { 1957 md->pvh_attrs ^= tst_mask; 1958 PMAPCOUNT(vac_color_change); 1959 } 1960 } 1961 } 1962 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1963 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1964 return; 1965 } else if (!pmap_is_page_colored_p(md)) { 1966 /* not colored so we just use its color */ 1967 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1968 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1969 PMAPCOUNT(vac_color_new); 1970 md->pvh_attrs &= PAGE_SIZE - 1; 1971 md->pvh_attrs |= PVF_COLORED 1972 | (va & arm_cache_prefer_mask) 1973 | (rw_mappings > 0 ? PVF_WRITE : 0); 1974 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1975 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1976 return; 1977 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1978 bad_alias = false; 1979 if (rw_mappings > 0) { 1980 /* 1981 * We now have writeable mappings and if we have 1982 * readonly mappings in more than once color, we have 1983 * an aliasing problem. Regardless mark the page as 1984 * writeable. 1985 */ 1986 if (md->pvh_attrs & PVF_MULTCLR) { 1987 if (ro_mappings < 2) { 1988 /* 1989 * If we only have less than two 1990 * read-only mappings, just flush the 1991 * non-primary colors from the cache. 1992 */ 1993 pmap_flush_page(md, pa, 1994 PMAP_FLUSH_SECONDARY); 1995 } else { 1996 bad_alias = true; 1997 } 1998 } 1999 md->pvh_attrs |= PVF_WRITE; 2000 } 2001 /* If no conflicting colors, set everything back to cached */ 2002 if (!bad_alias) { 2003 #ifdef DEBUG 2004 if (rw_mappings > 0 2005 || (md->pvh_attrs & PMAP_KMPAGE)) { 2006 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2007 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2008 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2009 } 2010 #endif 2011 if (SLIST_EMPTY(&md->pvh_list)) 2012 PMAPCOUNT(vac_color_reuse); 2013 else 2014 PMAPCOUNT(vac_color_ok); 2015 2016 /* matching color, just return */ 2017 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2018 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2019 return; 2020 } 2021 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2022 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2023 2024 /* color conflict. evict from cache. */ 2025 2026 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2027 md->pvh_attrs &= ~PVF_COLORED; 2028 md->pvh_attrs |= PVF_NC; 2029 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2030 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2031 PMAPCOUNT(vac_color_erase); 2032 } else if (rw_mappings == 0 2033 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2034 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2035 2036 /* 2037 * If the page has dirty cache lines, clean it. 2038 */ 2039 if (md->pvh_attrs & PVF_DIRTY) 2040 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2041 2042 /* 2043 * If this is the first remapping (we know that there are no 2044 * writeable mappings), then this is a simple color change. 2045 * Otherwise this is a seconary r/o mapping, which means 2046 * we don't have to do anything. 2047 */ 2048 if (ro_mappings == 1) { 2049 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2050 md->pvh_attrs &= PAGE_SIZE - 1; 2051 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2052 PMAPCOUNT(vac_color_change); 2053 } else { 2054 PMAPCOUNT(vac_color_blind); 2055 } 2056 md->pvh_attrs |= PVF_MULTCLR; 2057 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2058 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2059 return; 2060 } else { 2061 if (rw_mappings > 0) 2062 md->pvh_attrs |= PVF_WRITE; 2063 2064 /* color conflict. evict from cache. */ 2065 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2066 2067 /* the list can't be empty because this was a enter/modify */ 2068 pv = SLIST_FIRST(&md->pvh_list); 2069 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2070 KASSERT(pv); 2071 /* 2072 * If there's only one mapped page, change color to the 2073 * page's new color and return. Restore the DIRTY bit 2074 * that was erased by pmap_flush_page. 2075 */ 2076 if (SLIST_NEXT(pv, pv_link) == NULL) { 2077 md->pvh_attrs &= PAGE_SIZE - 1; 2078 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2079 if (md->pvh_attrs & PVF_DMOD) 2080 md->pvh_attrs |= PVF_DIRTY; 2081 PMAPCOUNT(vac_color_change); 2082 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2083 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2084 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2085 return; 2086 } 2087 } 2088 bad_alias = true; 2089 md->pvh_attrs &= ~PVF_COLORED; 2090 md->pvh_attrs |= PVF_NC; 2091 PMAPCOUNT(vac_color_erase); 2092 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2093 } 2094 2095 fixup: 2096 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2097 2098 /* 2099 * Turn cacheing on/off for all pages. 2100 */ 2101 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2102 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2103 pv->pv_va); 2104 KDASSERT(l2b != NULL); 2105 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2106 const pt_entry_t opte = *ptep; 2107 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2108 if (bad_alias) { 2109 pv->pv_flags |= PVF_NC; 2110 } else { 2111 pv->pv_flags &= ~PVF_NC; 2112 npte |= pte_l2_s_cache_mode; 2113 } 2114 2115 if (opte == npte) /* only update is there's a change */ 2116 continue; 2117 2118 if (l2pte_valid(npte)) { 2119 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2120 } 2121 2122 l2pte_set(ptep, npte, opte); 2123 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2124 } 2125 } 2126 #endif /* PMAP_CACHE_VIPT */ 2127 2128 2129 /* 2130 * Modify pte bits for all ptes corresponding to the given physical address. 2131 * We use `maskbits' rather than `clearbits' because we're always passing 2132 * constants and the latter would require an extra inversion at run-time. 2133 */ 2134 static void 2135 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2136 { 2137 struct pv_entry *pv; 2138 pmap_t pm; 2139 vaddr_t va; 2140 u_int oflags; 2141 #ifdef PMAP_CACHE_VIPT 2142 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2143 bool need_vac_me_harder = false; 2144 bool need_syncicache = false; 2145 #endif 2146 2147 NPDEBUG(PDB_BITS, 2148 printf("pmap_clearbit: md %p mask 0x%x\n", 2149 md, maskbits)); 2150 2151 #ifdef PMAP_CACHE_VIPT 2152 /* 2153 * If we might want to sync the I-cache and we've modified it, 2154 * then we know we definitely need to sync or discard it. 2155 */ 2156 if (want_syncicache) { 2157 need_syncicache = md->pvh_attrs & PVF_MOD; 2158 } 2159 #endif 2160 /* 2161 * Clear saved attributes (modify, reference) 2162 */ 2163 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2164 2165 if (SLIST_EMPTY(&md->pvh_list)) { 2166 #if defined(PMAP_CACHE_VIPT) 2167 if (need_syncicache) { 2168 /* 2169 * No one has it mapped, so just discard it. The next 2170 * exec remapping will cause it to be synced. 2171 */ 2172 md->pvh_attrs &= ~PVF_EXEC; 2173 PMAPCOUNT(exec_discarded_clearbit); 2174 } 2175 #endif 2176 return; 2177 } 2178 2179 /* 2180 * Loop over all current mappings setting/clearing as appropos 2181 */ 2182 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2183 va = pv->pv_va; 2184 pm = pv->pv_pmap; 2185 oflags = pv->pv_flags; 2186 /* 2187 * Kernel entries are unmanaged and as such not to be changed. 2188 */ 2189 if (oflags & PVF_KENTRY) 2190 continue; 2191 pv->pv_flags &= ~maskbits; 2192 2193 pmap_acquire_pmap_lock(pm); 2194 2195 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2196 KDASSERT(l2b != NULL); 2197 2198 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2199 const pt_entry_t opte = *ptep; 2200 pt_entry_t npte = opte; 2201 2202 NPDEBUG(PDB_BITS, 2203 printf( 2204 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2205 pv, pv->pv_pmap, pv->pv_va, oflags)); 2206 2207 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2208 #ifdef PMAP_CACHE_VIVT 2209 if ((pv->pv_flags & PVF_NC)) { 2210 /* 2211 * Entry is not cacheable: 2212 * 2213 * Don't turn caching on again if this is a 2214 * modified emulation. This would be 2215 * inconsitent with the settings created by 2216 * pmap_vac_me_harder(). Otherwise, it's safe 2217 * to re-enable cacheing. 2218 * 2219 * There's no need to call pmap_vac_me_harder() 2220 * here: all pages are losing their write 2221 * permission. 2222 */ 2223 if (maskbits & PVF_WRITE) { 2224 npte |= pte_l2_s_cache_mode; 2225 pv->pv_flags &= ~PVF_NC; 2226 } 2227 } else 2228 if (l2pte_writable_p(opte)) { 2229 /* 2230 * Entry is writable/cacheable: check if pmap 2231 * is current if it is flush it, otherwise it 2232 * won't be in the cache 2233 */ 2234 pmap_cache_wbinv_page(pm, pv->pv_va, 2235 (maskbits & PVF_REF) != 0, 2236 oflags|PVF_WRITE); 2237 } 2238 #endif 2239 2240 /* make the pte read only */ 2241 npte = l2pte_set_readonly(npte); 2242 2243 if (maskbits & oflags & PVF_WRITE) { 2244 /* 2245 * Keep alias accounting up to date 2246 */ 2247 if (pv->pv_pmap == pmap_kernel()) { 2248 md->krw_mappings--; 2249 md->kro_mappings++; 2250 } else { 2251 md->urw_mappings--; 2252 md->uro_mappings++; 2253 } 2254 #ifdef PMAP_CACHE_VIPT 2255 if (arm_cache_prefer_mask != 0) { 2256 if (md->urw_mappings + md->krw_mappings == 0) { 2257 md->pvh_attrs &= ~PVF_WRITE; 2258 } else { 2259 PMAP_VALIDATE_MD_PAGE(md); 2260 } 2261 } 2262 if (want_syncicache) 2263 need_syncicache = true; 2264 need_vac_me_harder = true; 2265 #endif 2266 } 2267 } 2268 2269 if (maskbits & PVF_REF) { 2270 if ((pv->pv_flags & PVF_NC) == 0 2271 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2272 && l2pte_valid(npte)) { 2273 #ifdef PMAP_CACHE_VIVT 2274 /* 2275 * Check npte here; we may have already 2276 * done the wbinv above, and the validity 2277 * of the PTE is the same for opte and 2278 * npte. 2279 */ 2280 pmap_cache_wbinv_page(pm, pv->pv_va, true, 2281 oflags); 2282 #endif 2283 } 2284 2285 /* 2286 * Make the PTE invalid so that we will take a 2287 * page fault the next time the mapping is 2288 * referenced. 2289 */ 2290 npte &= ~L2_TYPE_MASK; 2291 npte |= L2_TYPE_INV; 2292 } 2293 2294 if (npte != opte) { 2295 l2pte_set(ptep, npte, opte); 2296 PTE_SYNC(ptep); 2297 2298 /* Flush the TLB entry if a current pmap. */ 2299 pmap_tlb_flush_SE(pm, pv->pv_va, oflags); 2300 } 2301 2302 pmap_release_pmap_lock(pm); 2303 2304 NPDEBUG(PDB_BITS, 2305 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2306 pm, va, opte, npte)); 2307 } 2308 2309 #ifdef PMAP_CACHE_VIPT 2310 /* 2311 * If we need to sync the I-cache and we haven't done it yet, do it. 2312 */ 2313 if (need_syncicache) { 2314 pmap_syncicache_page(md, pa); 2315 PMAPCOUNT(exec_synced_clearbit); 2316 } 2317 2318 /* 2319 * If we are changing this to read-only, we need to call vac_me_harder 2320 * so we can change all the read-only pages to cacheable. We pretend 2321 * this as a page deletion. 2322 */ 2323 if (need_vac_me_harder) { 2324 if (md->pvh_attrs & PVF_NC) 2325 pmap_vac_me_harder(md, pa, NULL, 0); 2326 } 2327 #endif 2328 } 2329 2330 /* 2331 * pmap_clean_page() 2332 * 2333 * This is a local function used to work out the best strategy to clean 2334 * a single page referenced by its entry in the PV table. It's used by 2335 * pmap_copy_page, pmap_zero page and maybe some others later on. 2336 * 2337 * Its policy is effectively: 2338 * o If there are no mappings, we don't bother doing anything with the cache. 2339 * o If there is one mapping, we clean just that page. 2340 * o If there are multiple mappings, we clean the entire cache. 2341 * 2342 * So that some functions can be further optimised, it returns 0 if it didn't 2343 * clean the entire cache, or 1 if it did. 2344 * 2345 * XXX One bug in this routine is that if the pv_entry has a single page 2346 * mapped at 0x00000000 a whole cache clean will be performed rather than 2347 * just the 1 page. Since this should not occur in everyday use and if it does 2348 * it will just result in not the most efficient clean for the page. 2349 */ 2350 #ifdef PMAP_CACHE_VIVT 2351 static int 2352 pmap_clean_page(struct pv_entry *pv, bool is_src) 2353 { 2354 pmap_t pm_to_clean = NULL; 2355 struct pv_entry *npv; 2356 u_int cache_needs_cleaning = 0; 2357 u_int flags = 0; 2358 vaddr_t page_to_clean = 0; 2359 2360 if (pv == NULL) { 2361 /* nothing mapped in so nothing to flush */ 2362 return (0); 2363 } 2364 2365 /* 2366 * Since we flush the cache each time we change to a different 2367 * user vmspace, we only need to flush the page if it is in the 2368 * current pmap. 2369 */ 2370 2371 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2372 if (pmap_is_current(npv->pv_pmap)) { 2373 flags |= npv->pv_flags; 2374 /* 2375 * The page is mapped non-cacheable in 2376 * this map. No need to flush the cache. 2377 */ 2378 if (npv->pv_flags & PVF_NC) { 2379 #ifdef DIAGNOSTIC 2380 if (cache_needs_cleaning) 2381 panic("pmap_clean_page: " 2382 "cache inconsistency"); 2383 #endif 2384 break; 2385 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2386 continue; 2387 if (cache_needs_cleaning) { 2388 page_to_clean = 0; 2389 break; 2390 } else { 2391 page_to_clean = npv->pv_va; 2392 pm_to_clean = npv->pv_pmap; 2393 } 2394 cache_needs_cleaning = 1; 2395 } 2396 } 2397 2398 if (page_to_clean) { 2399 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2400 !is_src, flags | PVF_REF); 2401 } else if (cache_needs_cleaning) { 2402 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2403 2404 pmap_cache_wbinv_all(pm, flags); 2405 return (1); 2406 } 2407 return (0); 2408 } 2409 #endif 2410 2411 #ifdef PMAP_CACHE_VIPT 2412 /* 2413 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2414 * right cache alias to make sure we flush the right stuff. 2415 */ 2416 void 2417 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2418 { 2419 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2420 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2421 2422 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2423 md, md->pvh_attrs)); 2424 /* 2425 * No need to clean the page if it's non-cached. 2426 */ 2427 if (md->pvh_attrs & PVF_NC) 2428 return; 2429 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2430 2431 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, PVF_REF | PVF_EXEC); 2432 /* 2433 * Set up a PTE with the right coloring to flush existing cache lines. 2434 */ 2435 const pt_entry_t npte = L2_S_PROTO | 2436 pa 2437 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2438 | pte_l2_s_cache_mode; 2439 l2pte_set(ptep, npte, 0); 2440 PTE_SYNC(ptep); 2441 2442 /* 2443 * Flush it. 2444 */ 2445 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2446 /* 2447 * Unmap the page. 2448 */ 2449 l2pte_reset(ptep); 2450 PTE_SYNC(ptep); 2451 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, PVF_REF | PVF_EXEC); 2452 2453 md->pvh_attrs |= PVF_EXEC; 2454 PMAPCOUNT(exec_synced); 2455 } 2456 2457 void 2458 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2459 { 2460 vsize_t va_offset, end_va; 2461 bool wbinv_p; 2462 2463 if (arm_cache_prefer_mask == 0) 2464 return; 2465 2466 switch (flush) { 2467 case PMAP_FLUSH_PRIMARY: 2468 if (md->pvh_attrs & PVF_MULTCLR) { 2469 va_offset = 0; 2470 end_va = arm_cache_prefer_mask; 2471 md->pvh_attrs &= ~PVF_MULTCLR; 2472 PMAPCOUNT(vac_flush_lots); 2473 } else { 2474 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2475 end_va = va_offset; 2476 PMAPCOUNT(vac_flush_one); 2477 } 2478 /* 2479 * Mark that the page is no longer dirty. 2480 */ 2481 md->pvh_attrs &= ~PVF_DIRTY; 2482 wbinv_p = true; 2483 break; 2484 case PMAP_FLUSH_SECONDARY: 2485 va_offset = 0; 2486 end_va = arm_cache_prefer_mask; 2487 wbinv_p = true; 2488 md->pvh_attrs &= ~PVF_MULTCLR; 2489 PMAPCOUNT(vac_flush_lots); 2490 break; 2491 case PMAP_CLEAN_PRIMARY: 2492 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2493 end_va = va_offset; 2494 wbinv_p = false; 2495 /* 2496 * Mark that the page is no longer dirty. 2497 */ 2498 if ((md->pvh_attrs & PVF_DMOD) == 0) 2499 md->pvh_attrs &= ~PVF_DIRTY; 2500 PMAPCOUNT(vac_clean_one); 2501 break; 2502 default: 2503 return; 2504 } 2505 2506 KASSERT(!(md->pvh_attrs & PVF_NC)); 2507 2508 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2509 md, md->pvh_attrs)); 2510 2511 const size_t scache_line_size = arm_scache.dcache_line_size; 2512 2513 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2514 const size_t pte_offset = va_offset >> PGSHIFT; 2515 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2516 const pt_entry_t opte = *ptep; 2517 2518 if (flush == PMAP_FLUSH_SECONDARY 2519 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2520 continue; 2521 2522 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, 2523 PVF_REF | PVF_EXEC); 2524 /* 2525 * Set up a PTE with the right coloring to flush 2526 * existing cache entries. 2527 */ 2528 const pt_entry_t npte = L2_S_PROTO 2529 | pa 2530 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2531 | pte_l2_s_cache_mode; 2532 l2pte_set(ptep, npte, opte); 2533 PTE_SYNC(ptep); 2534 2535 /* 2536 * Flush it. Make sure to flush secondary cache too since 2537 * bus_dma will ignore uncached pages. 2538 */ 2539 vaddr_t va = cdstp + va_offset; 2540 if (scache_line_size != 0) { 2541 cpu_dcache_wb_range(va, PAGE_SIZE); 2542 if (wbinv_p) { 2543 cpu_sdcache_wbinv_range(va, pa, PAGE_SIZE); 2544 cpu_dcache_inv_range(va, PAGE_SIZE); 2545 } else { 2546 cpu_sdcache_wb_range(va, pa, PAGE_SIZE); 2547 } 2548 } else { 2549 if (wbinv_p) { 2550 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2551 } else { 2552 cpu_dcache_wb_range(va, PAGE_SIZE); 2553 } 2554 } 2555 2556 /* 2557 * Restore the page table entry since we might have interrupted 2558 * pmap_zero_page or pmap_copy_page which was already using 2559 * this pte. 2560 */ 2561 l2pte_set(ptep, opte, npte); 2562 PTE_SYNC(ptep); 2563 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, 2564 PVF_REF | PVF_EXEC); 2565 } 2566 } 2567 #endif /* PMAP_CACHE_VIPT */ 2568 2569 /* 2570 * Routine: pmap_page_remove 2571 * Function: 2572 * Removes this physical page from 2573 * all physical maps in which it resides. 2574 * Reflects back modify bits to the pager. 2575 */ 2576 static void 2577 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2578 { 2579 struct l2_bucket *l2b; 2580 struct pv_entry *pv, *npv, **pvp; 2581 pmap_t pm; 2582 pt_entry_t *ptep; 2583 bool flush; 2584 u_int flags; 2585 2586 NPDEBUG(PDB_FOLLOW, 2587 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2588 pa)); 2589 2590 pv = SLIST_FIRST(&md->pvh_list); 2591 if (pv == NULL) { 2592 #ifdef PMAP_CACHE_VIPT 2593 /* 2594 * We *know* the page contents are about to be replaced. 2595 * Discard the exec contents 2596 */ 2597 if (PV_IS_EXEC_P(md->pvh_attrs)) 2598 PMAPCOUNT(exec_discarded_page_protect); 2599 md->pvh_attrs &= ~PVF_EXEC; 2600 PMAP_VALIDATE_MD_PAGE(md); 2601 #endif 2602 return; 2603 } 2604 #ifdef PMAP_CACHE_VIPT 2605 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2606 #endif 2607 2608 /* 2609 * Clear alias counts 2610 */ 2611 #ifdef PMAP_CACHE_VIVT 2612 md->k_mappings = 0; 2613 #endif 2614 md->urw_mappings = md->uro_mappings = 0; 2615 2616 flush = false; 2617 flags = 0; 2618 2619 #ifdef PMAP_CACHE_VIVT 2620 pmap_clean_page(pv, false); 2621 #endif 2622 2623 pvp = &SLIST_FIRST(&md->pvh_list); 2624 while (pv) { 2625 pm = pv->pv_pmap; 2626 npv = SLIST_NEXT(pv, pv_link); 2627 if (flush == false && pmap_is_current(pm)) 2628 flush = true; 2629 2630 if (pm == pmap_kernel()) { 2631 #ifdef PMAP_CACHE_VIPT 2632 /* 2633 * If this was unmanaged mapping, it must be preserved. 2634 * Move it back on the list and advance the end-of-list 2635 * pointer. 2636 */ 2637 if (pv->pv_flags & PVF_KENTRY) { 2638 *pvp = pv; 2639 pvp = &SLIST_NEXT(pv, pv_link); 2640 pv = npv; 2641 continue; 2642 } 2643 if (pv->pv_flags & PVF_WRITE) 2644 md->krw_mappings--; 2645 else 2646 md->kro_mappings--; 2647 #endif 2648 PMAPCOUNT(kernel_unmappings); 2649 } 2650 PMAPCOUNT(unmappings); 2651 2652 pmap_acquire_pmap_lock(pm); 2653 2654 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2655 KDASSERT(l2b != NULL); 2656 2657 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2658 2659 /* 2660 * Update statistics 2661 */ 2662 --pm->pm_stats.resident_count; 2663 2664 /* Wired bit */ 2665 if (pv->pv_flags & PVF_WIRED) 2666 --pm->pm_stats.wired_count; 2667 2668 flags |= pv->pv_flags; 2669 2670 /* 2671 * Invalidate the PTEs. 2672 */ 2673 l2pte_reset(ptep); 2674 PTE_SYNC_CURRENT(pm, ptep); 2675 pmap_free_l2_bucket(pm, l2b, 1); 2676 2677 pool_put(&pmap_pv_pool, pv); 2678 pv = npv; 2679 /* 2680 * if we reach the end of the list and there are still 2681 * mappings, they might be able to be cached now. 2682 */ 2683 if (pv == NULL) { 2684 *pvp = NULL; 2685 if (!SLIST_EMPTY(&md->pvh_list)) 2686 pmap_vac_me_harder(md, pa, pm, 0); 2687 } 2688 pmap_release_pmap_lock(pm); 2689 } 2690 #ifdef PMAP_CACHE_VIPT 2691 /* 2692 * Its EXEC cache is now gone. 2693 */ 2694 if (PV_IS_EXEC_P(md->pvh_attrs)) 2695 PMAPCOUNT(exec_discarded_page_protect); 2696 md->pvh_attrs &= ~PVF_EXEC; 2697 KASSERT(md->urw_mappings == 0); 2698 KASSERT(md->uro_mappings == 0); 2699 if (arm_cache_prefer_mask != 0) { 2700 if (md->krw_mappings == 0) 2701 md->pvh_attrs &= ~PVF_WRITE; 2702 PMAP_VALIDATE_MD_PAGE(md); 2703 } 2704 #endif 2705 2706 if (flush) { 2707 /* 2708 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2709 * would need a subsequent call to pmap_update() to ensure 2710 * curpm->pm_cstate.cs_all is reset. Our callers are not 2711 * required to do that (see pmap(9)), so we can't modify 2712 * the current pmap's state. 2713 */ 2714 if (PV_BEEN_EXECD(flags)) 2715 cpu_tlb_flushID(); 2716 else 2717 cpu_tlb_flushD(); 2718 } 2719 cpu_cpwait(); 2720 } 2721 2722 /* 2723 * pmap_t pmap_create(void) 2724 * 2725 * Create a new pmap structure from scratch. 2726 */ 2727 pmap_t 2728 pmap_create(void) 2729 { 2730 pmap_t pm; 2731 2732 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2733 2734 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2735 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2736 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2737 2738 pm->pm_stats.wired_count = 0; 2739 pm->pm_stats.resident_count = 1; 2740 pm->pm_cstate.cs_all = 0; 2741 pmap_alloc_l1(pm); 2742 2743 /* 2744 * Note: The pool cache ensures that the pm_l2[] array is already 2745 * initialised to zero. 2746 */ 2747 2748 pmap_pinit(pm); 2749 2750 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2751 2752 return (pm); 2753 } 2754 2755 u_int 2756 arm32_mmap_flags(paddr_t pa) 2757 { 2758 /* 2759 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 2760 * and we're using the upper bits in page numbers to pass flags around 2761 * so we might as well use the same bits 2762 */ 2763 return (u_int)pa & PMAP_MD_MASK; 2764 } 2765 /* 2766 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2767 * u_int flags) 2768 * 2769 * Insert the given physical page (p) at 2770 * the specified virtual address (v) in the 2771 * target physical map with the protection requested. 2772 * 2773 * NB: This is the only routine which MAY NOT lazy-evaluate 2774 * or lose information. That is, this routine must actually 2775 * insert this page into the given map NOW. 2776 */ 2777 int 2778 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2779 { 2780 struct l2_bucket *l2b; 2781 struct vm_page *pg, *opg; 2782 struct pv_entry *pv; 2783 u_int nflags; 2784 u_int oflags; 2785 #ifdef ARM_HAS_VBAR 2786 const bool vector_page_p = false; 2787 #else 2788 const bool vector_page_p = (va == vector_page); 2789 #endif 2790 2791 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2792 2793 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2794 KDASSERT(((va | pa) & PGOFSET) == 0); 2795 2796 /* 2797 * Get a pointer to the page. Later on in this function, we 2798 * test for a managed page by checking pg != NULL. 2799 */ 2800 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2801 2802 nflags = 0; 2803 if (prot & VM_PROT_WRITE) 2804 nflags |= PVF_WRITE; 2805 if (prot & VM_PROT_EXECUTE) 2806 nflags |= PVF_EXEC; 2807 if (flags & PMAP_WIRED) 2808 nflags |= PVF_WIRED; 2809 2810 pmap_acquire_pmap_lock(pm); 2811 2812 /* 2813 * Fetch the L2 bucket which maps this page, allocating one if 2814 * necessary for user pmaps. 2815 */ 2816 if (pm == pmap_kernel()) 2817 l2b = pmap_get_l2_bucket(pm, va); 2818 else 2819 l2b = pmap_alloc_l2_bucket(pm, va); 2820 if (l2b == NULL) { 2821 if (flags & PMAP_CANFAIL) { 2822 pmap_release_pmap_lock(pm); 2823 return (ENOMEM); 2824 } 2825 panic("pmap_enter: failed to allocate L2 bucket"); 2826 } 2827 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2828 const pt_entry_t opte = *ptep; 2829 pt_entry_t npte = pa; 2830 oflags = 0; 2831 2832 if (opte) { 2833 /* 2834 * There is already a mapping at this address. 2835 * If the physical address is different, lookup the 2836 * vm_page. 2837 */ 2838 if (l2pte_pa(opte) != pa) 2839 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2840 else 2841 opg = pg; 2842 } else 2843 opg = NULL; 2844 2845 if (pg) { 2846 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2847 2848 /* 2849 * This is to be a managed mapping. 2850 */ 2851 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 2852 /* 2853 * - The access type indicates that we don't need 2854 * to do referenced emulation. 2855 * OR 2856 * - The physical page has already been referenced 2857 * so no need to re-do referenced emulation here. 2858 */ 2859 npte |= l2pte_set_readonly(L2_S_PROTO); 2860 2861 nflags |= PVF_REF; 2862 2863 if ((prot & VM_PROT_WRITE) != 0 && 2864 ((flags & VM_PROT_WRITE) != 0 || 2865 (md->pvh_attrs & PVF_MOD) != 0)) { 2866 /* 2867 * This is a writable mapping, and the 2868 * page's mod state indicates it has 2869 * already been modified. Make it 2870 * writable from the outset. 2871 */ 2872 npte = l2pte_set_writable(npte); 2873 nflags |= PVF_MOD; 2874 } 2875 } else { 2876 /* 2877 * Need to do page referenced emulation. 2878 */ 2879 npte |= L2_TYPE_INV; 2880 } 2881 2882 if (flags & ARM32_MMAP_WRITECOMBINE) { 2883 npte |= pte_l2_s_wc_mode; 2884 } else 2885 npte |= pte_l2_s_cache_mode; 2886 2887 if (pg == opg) { 2888 /* 2889 * We're changing the attrs of an existing mapping. 2890 */ 2891 #ifdef MULTIPROCESSOR 2892 KASSERT(uvm_page_locked_p(pg)); 2893 #endif 2894 oflags = pmap_modify_pv(md, pa, pm, va, 2895 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2896 PVF_MOD | PVF_REF, nflags); 2897 2898 #ifdef PMAP_CACHE_VIVT 2899 /* 2900 * We may need to flush the cache if we're 2901 * doing rw-ro... 2902 */ 2903 if (pm->pm_cstate.cs_cache_d && 2904 (oflags & PVF_NC) == 0 && 2905 l2pte_writable_p(opte) && 2906 (prot & VM_PROT_WRITE) == 0) 2907 cpu_dcache_wb_range(va, PAGE_SIZE); 2908 #endif 2909 } else { 2910 /* 2911 * New mapping, or changing the backing page 2912 * of an existing mapping. 2913 */ 2914 if (opg) { 2915 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2916 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2917 2918 /* 2919 * Replacing an existing mapping with a new one. 2920 * It is part of our managed memory so we 2921 * must remove it from the PV list 2922 */ 2923 #ifdef MULTIPROCESSOR 2924 KASSERT(uvm_page_locked_p(opg)); 2925 #endif 2926 pv = pmap_remove_pv(omd, opa, pm, va); 2927 pmap_vac_me_harder(omd, opa, pm, 0); 2928 oflags = pv->pv_flags; 2929 2930 #ifdef PMAP_CACHE_VIVT 2931 /* 2932 * If the old mapping was valid (ref/mod 2933 * emulation creates 'invalid' mappings 2934 * initially) then make sure to frob 2935 * the cache. 2936 */ 2937 if (!(oflags & PVF_NC) && l2pte_valid(opte)) { 2938 pmap_cache_wbinv_page(pm, va, true, 2939 oflags); 2940 } 2941 #endif 2942 } else 2943 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2944 if ((flags & PMAP_CANFAIL) == 0) 2945 panic("pmap_enter: no pv entries"); 2946 2947 if (pm != pmap_kernel()) 2948 pmap_free_l2_bucket(pm, l2b, 0); 2949 pmap_release_pmap_lock(pm); 2950 NPDEBUG(PDB_ENTER, 2951 printf("pmap_enter: ENOMEM\n")); 2952 return (ENOMEM); 2953 } 2954 2955 #ifdef MULTIPROCESSOR 2956 KASSERT(uvm_page_locked_p(pg)); 2957 #endif 2958 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2959 } 2960 } else { 2961 /* 2962 * We're mapping an unmanaged page. 2963 * These are always readable, and possibly writable, from 2964 * the get go as we don't need to track ref/mod status. 2965 */ 2966 npte |= l2pte_set_readonly(L2_S_PROTO); 2967 if (prot & VM_PROT_WRITE) 2968 npte = l2pte_set_writable(npte); 2969 2970 /* 2971 * Make sure the vector table is mapped cacheable 2972 */ 2973 if ((vector_page_p && pm != pmap_kernel()) 2974 || (flags & ARM32_MMAP_CACHEABLE)) { 2975 npte |= pte_l2_s_cache_mode; 2976 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 2977 npte |= pte_l2_s_wc_mode; 2978 } 2979 if (opg) { 2980 /* 2981 * Looks like there's an existing 'managed' mapping 2982 * at this address. 2983 */ 2984 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2985 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2986 2987 #ifdef MULTIPROCESSOR 2988 KASSERT(uvm_page_locked_p(opg)); 2989 #endif 2990 pv = pmap_remove_pv(omd, opa, pm, va); 2991 pmap_vac_me_harder(omd, opa, pm, 0); 2992 oflags = pv->pv_flags; 2993 2994 #ifdef PMAP_CACHE_VIVT 2995 if (!(oflags & PVF_NC) && l2pte_valid(opte)) { 2996 pmap_cache_wbinv_page(pm, va, true, oflags); 2997 } 2998 #endif 2999 pool_put(&pmap_pv_pool, pv); 3000 } 3001 } 3002 3003 /* 3004 * Make sure userland mappings get the right permissions 3005 */ 3006 if (!vector_page_p && pm != pmap_kernel()) { 3007 npte |= L2_S_PROT_U; 3008 } 3009 3010 /* 3011 * Keep the stats up to date 3012 */ 3013 if (opte == 0) { 3014 l2b->l2b_occupancy++; 3015 pm->pm_stats.resident_count++; 3016 } 3017 3018 NPDEBUG(PDB_ENTER, 3019 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3020 3021 /* 3022 * If this is just a wiring change, the two PTEs will be 3023 * identical, so there's no need to update the page table. 3024 */ 3025 if (npte != opte) { 3026 bool is_cached = pmap_is_cached(pm); 3027 3028 l2pte_set(ptep, npte, opte); 3029 PTE_SYNC(ptep); 3030 if (is_cached) { 3031 /* 3032 * We only need to frob the cache/tlb if this pmap 3033 * is current 3034 */ 3035 if (!vector_page_p && l2pte_valid(npte)) { 3036 /* 3037 * This mapping is likely to be accessed as 3038 * soon as we return to userland. Fix up the 3039 * L1 entry to avoid taking another 3040 * page/domain fault. 3041 */ 3042 pd_entry_t *pl1pd, l1pd; 3043 3044 pl1pd = pmap_l1_kva(pm) + L1_IDX(va); 3045 l1pd = l2b->l2b_phys | L1_C_DOM(pmap_domain(pm)) | 3046 L1_C_PROTO; 3047 if (*pl1pd != l1pd) { 3048 *pl1pd = l1pd; 3049 PTE_SYNC(pl1pd); 3050 } 3051 } 3052 } 3053 3054 pmap_tlb_flush_SE(pm, va, oflags); 3055 3056 NPDEBUG(PDB_ENTER, 3057 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3058 is_cached, pm->pm_cstate.cs_all)); 3059 3060 if (pg != NULL) { 3061 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3062 3063 #ifdef MULTIPROCESSOR 3064 KASSERT(uvm_page_locked_p(pg)); 3065 #endif 3066 pmap_vac_me_harder(md, pa, pm, va); 3067 } 3068 } 3069 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3070 if (pg) { 3071 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3072 3073 #ifdef MULTIPROCESSOR 3074 KASSERT(uvm_page_locked_p(pg)); 3075 #endif 3076 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3077 PMAP_VALIDATE_MD_PAGE(md); 3078 } 3079 #endif 3080 3081 pmap_release_pmap_lock(pm); 3082 3083 return (0); 3084 } 3085 3086 /* 3087 * pmap_remove() 3088 * 3089 * pmap_remove is responsible for nuking a number of mappings for a range 3090 * of virtual address space in the current pmap. To do this efficiently 3091 * is interesting, because in a number of cases a wide virtual address 3092 * range may be supplied that contains few actual mappings. So, the 3093 * optimisations are: 3094 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3095 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3096 * maybe do just a partial cache clean. This path of execution is 3097 * complicated by the fact that the cache must be flushed _before_ 3098 * the PTE is nuked, being a VAC :-) 3099 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3100 * all invalidations until pmap_update(), since pmap_remove_all() has 3101 * already flushed the cache. 3102 * 4. Maybe later fast-case a single page, but I don't think this is 3103 * going to make _that_ much difference overall. 3104 */ 3105 3106 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3107 3108 void 3109 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3110 { 3111 vaddr_t next_bucket; 3112 u_int cleanlist_idx, total, cnt; 3113 struct { 3114 vaddr_t va; 3115 pt_entry_t *ptep; 3116 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3117 u_int mappings; 3118 3119 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3120 "eva=%08lx\n", pm, sva, eva)); 3121 3122 /* 3123 * we lock in the pmap => pv_head direction 3124 */ 3125 pmap_acquire_pmap_lock(pm); 3126 3127 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3128 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3129 if (pm->pm_cstate.cs_tlb == 0) 3130 pm->pm_remove_all = true; 3131 } else 3132 cleanlist_idx = 0; 3133 3134 total = 0; 3135 3136 while (sva < eva) { 3137 /* 3138 * Do one L2 bucket's worth at a time. 3139 */ 3140 next_bucket = L2_NEXT_BUCKET(sva); 3141 if (next_bucket > eva) 3142 next_bucket = eva; 3143 3144 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3145 if (l2b == NULL) { 3146 sva = next_bucket; 3147 continue; 3148 } 3149 3150 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3151 3152 for (mappings = 0; 3153 sva < next_bucket; 3154 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3155 pt_entry_t opte = *ptep; 3156 3157 if (opte == 0) { 3158 /* Nothing here, move along */ 3159 continue; 3160 } 3161 3162 u_int flags = PVF_REF; 3163 paddr_t pa = l2pte_pa(opte); 3164 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3165 3166 /* 3167 * Update flags. In a number of circumstances, 3168 * we could cluster a lot of these and do a 3169 * number of sequential pages in one go. 3170 */ 3171 if (pg != NULL) { 3172 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3173 struct pv_entry *pv; 3174 3175 #ifdef MULTIPROCESSOR 3176 KASSERT(uvm_page_locked_p(pg)); 3177 #endif 3178 pv = pmap_remove_pv(md, pa, pm, sva); 3179 pmap_vac_me_harder(md, pa, pm, 0); 3180 if (pv != NULL) { 3181 if (pm->pm_remove_all == false) { 3182 flags = pv->pv_flags; 3183 } 3184 pool_put(&pmap_pv_pool, pv); 3185 } 3186 } 3187 mappings++; 3188 3189 if (!l2pte_valid(opte)) { 3190 /* 3191 * Ref/Mod emulation is still active for this 3192 * mapping, therefore it is has not yet been 3193 * accessed. No need to frob the cache/tlb. 3194 */ 3195 l2pte_reset(ptep); 3196 PTE_SYNC_CURRENT(pm, ptep); 3197 continue; 3198 } 3199 3200 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3201 /* Add to the clean list. */ 3202 cleanlist[cleanlist_idx].ptep = ptep; 3203 cleanlist[cleanlist_idx].va = 3204 sva | (flags & PVF_EXEC); 3205 cleanlist_idx++; 3206 } else 3207 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3208 /* Nuke everything if needed. */ 3209 #ifdef PMAP_CACHE_VIVT 3210 pmap_cache_wbinv_all(pm, PVF_EXEC); 3211 #endif 3212 pmap_tlb_flushID(pm); 3213 3214 /* 3215 * Roll back the previous PTE list, 3216 * and zero out the current PTE. 3217 */ 3218 for (cnt = 0; 3219 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3220 l2pte_reset(cleanlist[cnt].ptep); 3221 PTE_SYNC(cleanlist[cnt].ptep); 3222 } 3223 l2pte_reset(ptep); 3224 PTE_SYNC(ptep); 3225 cleanlist_idx++; 3226 pm->pm_remove_all = true; 3227 } else { 3228 l2pte_reset(ptep); 3229 PTE_SYNC(ptep); 3230 if (pm->pm_remove_all == false) { 3231 pmap_tlb_flush_SE(pm, sva, flags); 3232 } 3233 } 3234 } 3235 3236 /* 3237 * Deal with any left overs 3238 */ 3239 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3240 total += cleanlist_idx; 3241 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3242 vaddr_t va = cleanlist[cnt].va; 3243 if (pm->pm_cstate.cs_all != 0) { 3244 vaddr_t clva = va & ~PAGE_MASK; 3245 u_int flags = va & PVF_EXEC; 3246 #ifdef PMAP_CACHE_VIVT 3247 pmap_cache_wbinv_page(pm, clva, true, 3248 PVF_REF | PVF_WRITE | flags); 3249 #endif 3250 pmap_tlb_flush_SE(pm, clva, 3251 PVF_REF | flags); 3252 } 3253 l2pte_reset(cleanlist[cnt].ptep); 3254 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3255 } 3256 3257 /* 3258 * If it looks like we're removing a whole bunch 3259 * of mappings, it's faster to just write-back 3260 * the whole cache now and defer TLB flushes until 3261 * pmap_update() is called. 3262 */ 3263 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3264 cleanlist_idx = 0; 3265 else { 3266 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3267 #ifdef PMAP_CACHE_VIVT 3268 pmap_cache_wbinv_all(pm, PVF_EXEC); 3269 #endif 3270 pm->pm_remove_all = true; 3271 } 3272 } 3273 3274 pmap_free_l2_bucket(pm, l2b, mappings); 3275 pm->pm_stats.resident_count -= mappings; 3276 } 3277 3278 pmap_release_pmap_lock(pm); 3279 } 3280 3281 #ifdef PMAP_CACHE_VIPT 3282 static struct pv_entry * 3283 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3284 { 3285 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3286 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3287 struct pv_entry *pv; 3288 3289 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3290 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3291 3292 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3293 KASSERT(pv); 3294 KASSERT(pv->pv_flags & PVF_KENTRY); 3295 3296 /* 3297 * If we are removing a writeable mapping to a cached exec page, 3298 * if it's the last mapping then clear it execness other sync 3299 * the page to the icache. 3300 */ 3301 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3302 && (pv->pv_flags & PVF_WRITE) != 0) { 3303 if (SLIST_EMPTY(&md->pvh_list)) { 3304 md->pvh_attrs &= ~PVF_EXEC; 3305 PMAPCOUNT(exec_discarded_kremove); 3306 } else { 3307 pmap_syncicache_page(md, pa); 3308 PMAPCOUNT(exec_synced_kremove); 3309 } 3310 } 3311 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3312 3313 return pv; 3314 } 3315 #endif /* PMAP_CACHE_VIPT */ 3316 3317 /* 3318 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3319 * 3320 * We assume there is already sufficient KVM space available 3321 * to do this, as we can't allocate L2 descriptor tables/metadata 3322 * from here. 3323 */ 3324 void 3325 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3326 { 3327 #ifdef PMAP_CACHE_VIVT 3328 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3329 #endif 3330 #ifdef PMAP_CACHE_VIPT 3331 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3332 struct vm_page *opg; 3333 struct pv_entry *pv = NULL; 3334 #endif 3335 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3336 3337 NPDEBUG(PDB_KENTER, 3338 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3339 va, pa, prot)); 3340 3341 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3342 KDASSERT(l2b != NULL); 3343 3344 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3345 const pt_entry_t opte = *ptep; 3346 3347 if (opte == 0) { 3348 PMAPCOUNT(kenter_mappings); 3349 l2b->l2b_occupancy++; 3350 } else { 3351 PMAPCOUNT(kenter_remappings); 3352 #ifdef PMAP_CACHE_VIPT 3353 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3354 #ifdef DIAGNOSTIC 3355 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3356 #endif 3357 if (opg) { 3358 KASSERT(opg != pg); 3359 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3360 KASSERT((flags & PMAP_KMPAGE) == 0); 3361 pv = pmap_kremove_pg(opg, va); 3362 } 3363 #endif 3364 if (l2pte_valid(opte)) { 3365 #ifdef PMAP_CACHE_VIVT 3366 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3367 #endif 3368 cpu_tlb_flushD_SE(va); 3369 cpu_cpwait(); 3370 } 3371 } 3372 3373 const pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3374 | ((flags & PMAP_NOCACHE) ? 0 : pte_l2_s_cache_mode); 3375 l2pte_set(ptep, npte, opte); 3376 PTE_SYNC(ptep); 3377 3378 if (pg) { 3379 #ifdef MULTIPROCESSOR 3380 KASSERT(uvm_page_locked_p(pg)); 3381 #endif 3382 if (flags & PMAP_KMPAGE) { 3383 KASSERT(md->urw_mappings == 0); 3384 KASSERT(md->uro_mappings == 0); 3385 KASSERT(md->krw_mappings == 0); 3386 KASSERT(md->kro_mappings == 0); 3387 #ifdef PMAP_CACHE_VIPT 3388 KASSERT(pv == NULL); 3389 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3390 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3391 /* if there is a color conflict, evict from cache. */ 3392 if (pmap_is_page_colored_p(md) 3393 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3394 PMAPCOUNT(vac_color_change); 3395 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3396 } else if (md->pvh_attrs & PVF_MULTCLR) { 3397 /* 3398 * If this page has multiple colors, expunge 3399 * them. 3400 */ 3401 PMAPCOUNT(vac_flush_lots2); 3402 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3403 } 3404 md->pvh_attrs &= PAGE_SIZE - 1; 3405 md->pvh_attrs |= PVF_KMPAGE 3406 | PVF_COLORED | PVF_DIRTY 3407 | (va & arm_cache_prefer_mask); 3408 #endif 3409 #ifdef PMAP_CACHE_VIVT 3410 md->pvh_attrs |= PVF_KMPAGE; 3411 #endif 3412 pmap_kmpages++; 3413 #ifdef PMAP_CACHE_VIPT 3414 } else { 3415 if (pv == NULL) { 3416 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3417 KASSERT(pv != NULL); 3418 } 3419 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3420 PVF_WIRED | PVF_KENTRY 3421 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3422 if ((prot & VM_PROT_WRITE) 3423 && !(md->pvh_attrs & PVF_NC)) 3424 md->pvh_attrs |= PVF_DIRTY; 3425 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3426 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3427 #endif 3428 } 3429 #ifdef PMAP_CACHE_VIPT 3430 } else { 3431 if (pv != NULL) 3432 pool_put(&pmap_pv_pool, pv); 3433 #endif 3434 } 3435 } 3436 3437 void 3438 pmap_kremove(vaddr_t va, vsize_t len) 3439 { 3440 vaddr_t next_bucket, eva; 3441 u_int mappings; 3442 3443 PMAPCOUNT(kenter_unmappings); 3444 3445 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3446 va, len)); 3447 3448 eva = va + len; 3449 3450 while (va < eva) { 3451 next_bucket = L2_NEXT_BUCKET(va); 3452 if (next_bucket > eva) 3453 next_bucket = eva; 3454 3455 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3456 KDASSERT(l2b != NULL); 3457 3458 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3459 pt_entry_t *ptep = sptep; 3460 mappings = 0; 3461 3462 while (va < next_bucket) { 3463 const pt_entry_t opte = *ptep; 3464 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3465 if (opg != NULL) { 3466 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3467 3468 if (omd->pvh_attrs & PVF_KMPAGE) { 3469 KASSERT(omd->urw_mappings == 0); 3470 KASSERT(omd->uro_mappings == 0); 3471 KASSERT(omd->krw_mappings == 0); 3472 KASSERT(omd->kro_mappings == 0); 3473 omd->pvh_attrs &= ~PVF_KMPAGE; 3474 #ifdef PMAP_CACHE_VIPT 3475 if (arm_cache_prefer_mask != 0) { 3476 omd->pvh_attrs &= ~PVF_WRITE; 3477 } 3478 #endif 3479 pmap_kmpages--; 3480 #ifdef PMAP_CACHE_VIPT 3481 } else { 3482 pool_put(&pmap_pv_pool, 3483 pmap_kremove_pg(opg, va)); 3484 #endif 3485 } 3486 } 3487 if (l2pte_valid(opte)) { 3488 #ifdef PMAP_CACHE_VIVT 3489 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3490 #endif 3491 cpu_tlb_flushD_SE(va); 3492 } 3493 if (opte) { 3494 l2pte_reset(ptep); 3495 mappings++; 3496 } 3497 va += PAGE_SIZE; 3498 ptep += PAGE_SIZE / L2_S_SIZE; 3499 } 3500 KDASSERT(mappings <= l2b->l2b_occupancy); 3501 l2b->l2b_occupancy -= mappings; 3502 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3503 } 3504 cpu_cpwait(); 3505 } 3506 3507 bool 3508 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3509 { 3510 struct l2_dtable *l2; 3511 pd_entry_t *pl1pd, l1pd; 3512 pt_entry_t *ptep, pte; 3513 paddr_t pa; 3514 u_int l1idx; 3515 3516 pmap_acquire_pmap_lock(pm); 3517 3518 l1idx = L1_IDX(va); 3519 pl1pd = pmap_l1_kva(pm) + l1idx; 3520 l1pd = *pl1pd; 3521 3522 if (l1pte_section_p(l1pd)) { 3523 /* 3524 * These should only happen for pmap_kernel() 3525 */ 3526 KDASSERT(pm == pmap_kernel()); 3527 pmap_release_pmap_lock(pm); 3528 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3529 if (l1pte_supersection_p(l1pd)) { 3530 pa = (l1pd & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3531 } else 3532 #endif 3533 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3534 } else { 3535 /* 3536 * Note that we can't rely on the validity of the L1 3537 * descriptor as an indication that a mapping exists. 3538 * We have to look it up in the L2 dtable. 3539 */ 3540 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3541 3542 if (l2 == NULL || 3543 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3544 pmap_release_pmap_lock(pm); 3545 return false; 3546 } 3547 3548 ptep = &ptep[l2pte_index(va)]; 3549 pte = *ptep; 3550 pmap_release_pmap_lock(pm); 3551 3552 if (pte == 0) 3553 return false; 3554 3555 switch (pte & L2_TYPE_MASK) { 3556 case L2_TYPE_L: 3557 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3558 break; 3559 3560 default: 3561 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3562 break; 3563 } 3564 } 3565 3566 if (pap != NULL) 3567 *pap = pa; 3568 3569 return true; 3570 } 3571 3572 void 3573 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3574 { 3575 struct l2_bucket *l2b; 3576 pt_entry_t *ptep, pte; 3577 vaddr_t next_bucket; 3578 3579 NPDEBUG(PDB_PROTECT, 3580 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3581 pm, sva, eva, prot)); 3582 3583 if ((prot & VM_PROT_READ) == 0) { 3584 pmap_remove(pm, sva, eva); 3585 return; 3586 } 3587 3588 if (prot & VM_PROT_WRITE) { 3589 /* 3590 * If this is a read->write transition, just ignore it and let 3591 * uvm_fault() take care of it later. 3592 */ 3593 return; 3594 } 3595 3596 pmap_acquire_pmap_lock(pm); 3597 3598 const bool flush = eva - sva >= PAGE_SIZE * 4; 3599 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3600 u_int flags = 0; 3601 3602 while (sva < eva) { 3603 next_bucket = L2_NEXT_BUCKET(sva); 3604 if (next_bucket > eva) 3605 next_bucket = eva; 3606 3607 l2b = pmap_get_l2_bucket(pm, sva); 3608 if (l2b == NULL) { 3609 sva = next_bucket; 3610 continue; 3611 } 3612 3613 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3614 3615 while (sva < next_bucket) { 3616 pte = *ptep; 3617 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3618 struct vm_page *pg; 3619 u_int f; 3620 3621 #ifdef PMAP_CACHE_VIVT 3622 /* 3623 * OK, at this point, we know we're doing 3624 * write-protect operation. If the pmap is 3625 * active, write-back the page. 3626 */ 3627 pmap_cache_wbinv_page(pm, sva, false, 3628 PVF_REF | PVF_WRITE); 3629 #endif 3630 3631 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3632 pte = l2pte_set_readonly(pte); 3633 *ptep = pte; 3634 PTE_SYNC(ptep); 3635 3636 if (pg != NULL) { 3637 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3638 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3639 3640 #ifdef MULTIPROCESSOR 3641 KASSERT(uvm_page_locked_p(pg)); 3642 #endif 3643 f = pmap_modify_pv(md, pa, pm, sva, 3644 clr_mask, 0); 3645 pmap_vac_me_harder(md, pa, pm, sva); 3646 } else { 3647 f = PVF_REF | PVF_EXEC; 3648 } 3649 3650 if (flush) { 3651 flags |= f; 3652 } else { 3653 pmap_tlb_flush_SE(pm, sva, f); 3654 } 3655 } 3656 3657 sva += PAGE_SIZE; 3658 ptep++; 3659 } 3660 } 3661 3662 if (flush) { 3663 if (PV_BEEN_EXECD(flags)) { 3664 pmap_tlb_flushID(pm); 3665 } else if (PV_BEEN_REFD(flags)) { 3666 pmap_tlb_flushD(pm); 3667 } 3668 } 3669 3670 pmap_release_pmap_lock(pm); 3671 } 3672 3673 void 3674 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3675 { 3676 struct l2_bucket *l2b; 3677 pt_entry_t *ptep; 3678 vaddr_t next_bucket; 3679 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3680 3681 NPDEBUG(PDB_EXEC, 3682 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3683 pm, sva, eva)); 3684 3685 pmap_acquire_pmap_lock(pm); 3686 3687 while (sva < eva) { 3688 next_bucket = L2_NEXT_BUCKET(sva); 3689 if (next_bucket > eva) 3690 next_bucket = eva; 3691 3692 l2b = pmap_get_l2_bucket(pm, sva); 3693 if (l2b == NULL) { 3694 sva = next_bucket; 3695 continue; 3696 } 3697 3698 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3699 sva < next_bucket; 3700 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3701 if (l2pte_valid(*ptep)) { 3702 cpu_icache_sync_range(sva, 3703 min(page_size, eva - sva)); 3704 } 3705 } 3706 } 3707 3708 pmap_release_pmap_lock(pm); 3709 } 3710 3711 void 3712 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3713 { 3714 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3715 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3716 3717 NPDEBUG(PDB_PROTECT, 3718 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3719 md, pa, prot)); 3720 3721 #ifdef MULTIPROCESSOR 3722 KASSERT(uvm_page_locked_p(pg)); 3723 #endif 3724 3725 switch(prot) { 3726 case VM_PROT_READ|VM_PROT_WRITE: 3727 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3728 pmap_clearbit(md, pa, PVF_EXEC); 3729 break; 3730 #endif 3731 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3732 break; 3733 3734 case VM_PROT_READ: 3735 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3736 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3737 break; 3738 #endif 3739 case VM_PROT_READ|VM_PROT_EXECUTE: 3740 pmap_clearbit(md, pa, PVF_WRITE); 3741 break; 3742 3743 default: 3744 pmap_page_remove(md, pa); 3745 break; 3746 } 3747 } 3748 3749 /* 3750 * pmap_clear_modify: 3751 * 3752 * Clear the "modified" attribute for a page. 3753 */ 3754 bool 3755 pmap_clear_modify(struct vm_page *pg) 3756 { 3757 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3758 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3759 bool rv; 3760 3761 #ifdef MULTIPROCESSOR 3762 KASSERT(uvm_page_locked_p(pg)); 3763 #endif 3764 3765 if (md->pvh_attrs & PVF_MOD) { 3766 rv = true; 3767 #ifdef PMAP_CACHE_VIPT 3768 /* 3769 * If we are going to clear the modified bit and there are 3770 * no other modified bits set, flush the page to memory and 3771 * mark it clean. 3772 */ 3773 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3774 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3775 #endif 3776 pmap_clearbit(md, pa, PVF_MOD); 3777 } else 3778 rv = false; 3779 3780 return (rv); 3781 } 3782 3783 /* 3784 * pmap_clear_reference: 3785 * 3786 * Clear the "referenced" attribute for a page. 3787 */ 3788 bool 3789 pmap_clear_reference(struct vm_page *pg) 3790 { 3791 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3792 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3793 bool rv; 3794 3795 #ifdef MULTIPROCESSOR 3796 KASSERT(uvm_page_locked_p(pg)); 3797 #endif 3798 3799 if (md->pvh_attrs & PVF_REF) { 3800 rv = true; 3801 pmap_clearbit(md, pa, PVF_REF); 3802 } else 3803 rv = false; 3804 3805 return (rv); 3806 } 3807 3808 /* 3809 * pmap_is_modified: 3810 * 3811 * Test if a page has the "modified" attribute. 3812 */ 3813 /* See <arm/arm32/pmap.h> */ 3814 3815 /* 3816 * pmap_is_referenced: 3817 * 3818 * Test if a page has the "referenced" attribute. 3819 */ 3820 /* See <arm/arm32/pmap.h> */ 3821 3822 int 3823 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3824 { 3825 struct l2_dtable *l2; 3826 struct l2_bucket *l2b; 3827 pd_entry_t *pl1pd, l1pd; 3828 pt_entry_t *ptep, pte; 3829 paddr_t pa; 3830 u_int l1idx; 3831 int rv = 0; 3832 3833 pmap_acquire_pmap_lock(pm); 3834 3835 l1idx = L1_IDX(va); 3836 3837 /* 3838 * If there is no l2_dtable for this address, then the process 3839 * has no business accessing it. 3840 * 3841 * Note: This will catch userland processes trying to access 3842 * kernel addresses. 3843 */ 3844 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3845 if (l2 == NULL) 3846 goto out; 3847 3848 /* 3849 * Likewise if there is no L2 descriptor table 3850 */ 3851 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3852 if (l2b->l2b_kva == NULL) 3853 goto out; 3854 3855 /* 3856 * Check the PTE itself. 3857 */ 3858 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3859 pte = *ptep; 3860 if (pte == 0) 3861 goto out; 3862 3863 /* 3864 * Catch a userland access to the vector page mapped at 0x0 3865 */ 3866 if (user && (pte & L2_S_PROT_U) == 0) 3867 goto out; 3868 3869 pa = l2pte_pa(pte); 3870 3871 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3872 /* 3873 * This looks like a good candidate for "page modified" 3874 * emulation... 3875 */ 3876 struct pv_entry *pv; 3877 struct vm_page *pg; 3878 3879 /* Extract the physical address of the page */ 3880 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3881 goto out; 3882 3883 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3884 3885 /* Get the current flags for this page. */ 3886 #ifdef MULTIPROCESSOR 3887 KASSERT(uvm_page_locked_p(pg)); 3888 #endif 3889 3890 pv = pmap_find_pv(md, pm, va); 3891 if (pv == NULL) { 3892 goto out; 3893 } 3894 3895 /* 3896 * Do the flags say this page is writable? If not then it 3897 * is a genuine write fault. If yes then the write fault is 3898 * our fault as we did not reflect the write access in the 3899 * PTE. Now we know a write has occurred we can correct this 3900 * and also set the modified bit 3901 */ 3902 if ((pv->pv_flags & PVF_WRITE) == 0) { 3903 goto out; 3904 } 3905 3906 NPDEBUG(PDB_FOLLOW, 3907 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3908 pm, va, pa)); 3909 3910 md->pvh_attrs |= PVF_REF | PVF_MOD; 3911 pv->pv_flags |= PVF_REF | PVF_MOD; 3912 #ifdef PMAP_CACHE_VIPT 3913 /* 3914 * If there are cacheable mappings for this page, mark it dirty. 3915 */ 3916 if ((md->pvh_attrs & PVF_NC) == 0) 3917 md->pvh_attrs |= PVF_DIRTY; 3918 #endif 3919 3920 /* 3921 * Re-enable write permissions for the page. No need to call 3922 * pmap_vac_me_harder(), since this is just a 3923 * modified-emulation fault, and the PVF_WRITE bit isn't 3924 * changing. We've already set the cacheable bits based on 3925 * the assumption that we can write to this page. 3926 */ 3927 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3928 PTE_SYNC(ptep); 3929 rv = 1; 3930 } else 3931 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3932 /* 3933 * This looks like a good candidate for "page referenced" 3934 * emulation. 3935 */ 3936 struct pv_entry *pv; 3937 struct vm_page *pg; 3938 3939 /* Extract the physical address of the page */ 3940 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3941 goto out; 3942 3943 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3944 3945 /* Get the current flags for this page. */ 3946 #ifdef MULTIPROCESSOR 3947 KASSERT(uvm_page_locked_p(pg)); 3948 #endif 3949 3950 pv = pmap_find_pv(md, pm, va); 3951 if (pv == NULL) { 3952 goto out; 3953 } 3954 3955 md->pvh_attrs |= PVF_REF; 3956 pv->pv_flags |= PVF_REF; 3957 3958 NPDEBUG(PDB_FOLLOW, 3959 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3960 pm, va, pa)); 3961 3962 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3963 PTE_SYNC(ptep); 3964 rv = 1; 3965 } 3966 3967 /* 3968 * We know there is a valid mapping here, so simply 3969 * fix up the L1 if necessary. 3970 */ 3971 pl1pd = pmap_l1_kva(pm) + l1idx; 3972 l1pd = l2b->l2b_phys | L1_C_DOM(pmap_domain(pm)) | L1_C_PROTO; 3973 if (*pl1pd != l1pd) { 3974 *pl1pd = l1pd; 3975 PTE_SYNC(pl1pd); 3976 rv = 1; 3977 } 3978 3979 #ifdef CPU_SA110 3980 /* 3981 * There are bugs in the rev K SA110. This is a check for one 3982 * of them. 3983 */ 3984 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3985 curcpu()->ci_arm_cpurev < 3) { 3986 /* Always current pmap */ 3987 if (l2pte_valid(pte)) { 3988 extern int kernel_debug; 3989 if (kernel_debug & 1) { 3990 struct proc *p = curlwp->l_proc; 3991 printf("prefetch_abort: page is already " 3992 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3993 printf("prefetch_abort: pc=%08lx proc=%p " 3994 "process=%s\n", va, p, p->p_comm); 3995 printf("prefetch_abort: far=%08x fs=%x\n", 3996 cpu_faultaddress(), cpu_faultstatus()); 3997 } 3998 #ifdef DDB 3999 if (kernel_debug & 2) 4000 Debugger(); 4001 #endif 4002 rv = 1; 4003 } 4004 } 4005 #endif /* CPU_SA110 */ 4006 4007 /* 4008 * If 'rv == 0' at this point, it generally indicates that there is a 4009 * stale TLB entry for the faulting address. That might be due to a 4010 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4011 */ 4012 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1 4013 && pmap_needs_pte_sync == 0) { 4014 pmap_needs_pte_sync = 1; 4015 PTE_SYNC(ptep); 4016 rv = 1; 4017 } 4018 4019 #ifdef DEBUG 4020 /* 4021 * If 'rv == 0' at this point, it generally indicates that there is a 4022 * stale TLB entry for the faulting address. This happens when two or 4023 * more processes are sharing an L1. Since we don't flush the TLB on 4024 * a context switch between such processes, we can take domain faults 4025 * for mappings which exist at the same VA in both processes. EVEN IF 4026 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4027 * example. 4028 * 4029 * This is extremely likely to happen if pmap_enter() updated the L1 4030 * entry for a recently entered mapping. In this case, the TLB is 4031 * flushed for the new mapping, but there may still be TLB entries for 4032 * other mappings belonging to other processes in the 1MB range 4033 * covered by the L1 entry. 4034 * 4035 * Since 'rv == 0', we know that the L1 already contains the correct 4036 * value, so the fault must be due to a stale TLB entry. 4037 * 4038 * Since we always need to flush the TLB anyway in the case where we 4039 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4040 * stale TLB entries dynamically. 4041 * 4042 * However, the above condition can ONLY happen if the current L1 is 4043 * being shared. If it happens when the L1 is unshared, it indicates 4044 * that other parts of the pmap are not doing their job WRT managing 4045 * the TLB. 4046 */ 4047 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4048 extern int last_fault_code; 4049 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4050 pm, va, ftype); 4051 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4052 l2, l2b, ptep, pl1pd); 4053 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4054 pte, l1pd, last_fault_code); 4055 #ifdef DDB 4056 extern int kernel_debug; 4057 4058 if (kernel_debug & 2) 4059 Debugger(); 4060 #endif 4061 } 4062 #endif 4063 4064 cpu_tlb_flushID_SE(va); 4065 cpu_cpwait(); 4066 4067 rv = 1; 4068 4069 out: 4070 pmap_release_pmap_lock(pm); 4071 4072 return (rv); 4073 } 4074 4075 /* 4076 * Routine: pmap_procwr 4077 * 4078 * Function: 4079 * Synchronize caches corresponding to [addr, addr+len) in p. 4080 * 4081 */ 4082 void 4083 pmap_procwr(struct proc *p, vaddr_t va, int len) 4084 { 4085 /* We only need to do anything if it is the current process. */ 4086 if (p == curproc) 4087 cpu_icache_sync_range(va, len); 4088 } 4089 4090 /* 4091 * Routine: pmap_unwire 4092 * Function: Clear the wired attribute for a map/virtual-address pair. 4093 * 4094 * In/out conditions: 4095 * The mapping must already exist in the pmap. 4096 */ 4097 void 4098 pmap_unwire(pmap_t pm, vaddr_t va) 4099 { 4100 struct l2_bucket *l2b; 4101 pt_entry_t *ptep, pte; 4102 struct vm_page *pg; 4103 paddr_t pa; 4104 4105 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4106 4107 pmap_acquire_pmap_lock(pm); 4108 4109 l2b = pmap_get_l2_bucket(pm, va); 4110 KDASSERT(l2b != NULL); 4111 4112 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4113 pte = *ptep; 4114 4115 /* Extract the physical address of the page */ 4116 pa = l2pte_pa(pte); 4117 4118 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4119 /* Update the wired bit in the pv entry for this page. */ 4120 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4121 4122 #ifdef MULTIPROCESSOR 4123 KASSERT(uvm_page_locked_p(pg)); 4124 #endif 4125 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4126 } 4127 4128 pmap_release_pmap_lock(pm); 4129 } 4130 4131 void 4132 pmap_activate(struct lwp *l) 4133 { 4134 extern int block_userspace_access; 4135 pmap_t opm, npm, rpm; 4136 uint32_t odacr, ndacr; 4137 int oldirqstate; 4138 4139 /* 4140 * If activating a non-current lwp or the current lwp is 4141 * already active, just return. 4142 */ 4143 if (l != curlwp || 4144 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4145 return; 4146 4147 npm = l->l_proc->p_vmspace->vm_map.pmap; 4148 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4149 (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4150 4151 /* 4152 * If TTB and DACR are unchanged, short-circuit all the 4153 * TLB/cache management stuff. 4154 */ 4155 if (pmap_previous_active_lwp != NULL) { 4156 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4157 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4158 (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4159 4160 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4161 goto all_done; 4162 } else 4163 opm = NULL; 4164 4165 PMAPCOUNT(activations); 4166 block_userspace_access = 1; 4167 4168 /* 4169 * If switching to a user vmspace which is different to the 4170 * most recent one, and the most recent one is potentially 4171 * live in the cache, we must write-back and invalidate the 4172 * entire cache. 4173 */ 4174 rpm = pmap_recent_user; 4175 4176 /* 4177 * XXXSCW: There's a corner case here which can leave turds in the cache as 4178 * reported in kern/41058. They're probably left over during tear-down and 4179 * switching away from an exiting process. Until the root cause is identified 4180 * and fixed, zap the cache when switching pmaps. This will result in a few 4181 * unnecessary cache flushes, but that's better than silently corrupting data. 4182 */ 4183 #if 0 4184 if (npm != pmap_kernel() && rpm && npm != rpm && 4185 rpm->pm_cstate.cs_cache) { 4186 rpm->pm_cstate.cs_cache = 0; 4187 #ifdef PMAP_CACHE_VIVT 4188 cpu_idcache_wbinv_all(); 4189 #endif 4190 } 4191 #else 4192 if (rpm) { 4193 rpm->pm_cstate.cs_cache = 0; 4194 if (npm == pmap_kernel()) 4195 pmap_recent_user = NULL; 4196 #ifdef PMAP_CACHE_VIVT 4197 cpu_idcache_wbinv_all(); 4198 #endif 4199 } 4200 #endif 4201 4202 /* No interrupts while we frob the TTB/DACR */ 4203 oldirqstate = disable_interrupts(IF32_bits); 4204 4205 #ifndef ARM_HAS_VBAR 4206 /* 4207 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4208 * entry corresponding to 'vector_page' in the incoming L1 table 4209 * before switching to it otherwise subsequent interrupts/exceptions 4210 * (including domain faults!) will jump into hyperspace. 4211 */ 4212 if (npm->pm_pl1vec != NULL) { 4213 cpu_tlb_flushID_SE((u_int)vector_page); 4214 cpu_cpwait(); 4215 *npm->pm_pl1vec = npm->pm_l1vec; 4216 PTE_SYNC(npm->pm_pl1vec); 4217 } 4218 #endif 4219 4220 cpu_domains(ndacr); 4221 4222 if (npm == pmap_kernel() || npm == rpm) { 4223 /* 4224 * Switching to a kernel thread, or back to the 4225 * same user vmspace as before... Simply update 4226 * the TTB (no TLB flush required) 4227 */ 4228 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4229 cpu_cpwait(); 4230 } else { 4231 /* 4232 * Otherwise, update TTB and flush TLB 4233 */ 4234 cpu_context_switch(npm->pm_l1->l1_physaddr); 4235 if (rpm != NULL) 4236 rpm->pm_cstate.cs_tlb = 0; 4237 } 4238 4239 restore_interrupts(oldirqstate); 4240 4241 block_userspace_access = 0; 4242 4243 all_done: 4244 /* 4245 * The new pmap is resident. Make sure it's marked 4246 * as resident in the cache/TLB. 4247 */ 4248 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4249 if (npm != pmap_kernel()) 4250 pmap_recent_user = npm; 4251 4252 /* The old pmap is not longer active */ 4253 if (opm != NULL) 4254 opm->pm_activated = false; 4255 4256 /* But the new one is */ 4257 npm->pm_activated = true; 4258 } 4259 4260 void 4261 pmap_deactivate(struct lwp *l) 4262 { 4263 4264 /* 4265 * If the process is exiting, make sure pmap_activate() does 4266 * a full MMU context-switch and cache flush, which we might 4267 * otherwise skip. See PR port-arm/38950. 4268 */ 4269 if (l->l_proc->p_sflag & PS_WEXIT) 4270 pmap_previous_active_lwp = NULL; 4271 4272 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4273 } 4274 4275 void 4276 pmap_update(pmap_t pm) 4277 { 4278 4279 if (pm->pm_remove_all) { 4280 /* 4281 * Finish up the pmap_remove_all() optimisation by flushing 4282 * the TLB. 4283 */ 4284 pmap_tlb_flushID(pm); 4285 pm->pm_remove_all = false; 4286 } 4287 4288 if (pmap_is_current(pm)) { 4289 /* 4290 * If we're dealing with a current userland pmap, move its L1 4291 * to the end of the LRU. 4292 */ 4293 if (pm != pmap_kernel()) 4294 pmap_use_l1(pm); 4295 4296 /* 4297 * We can assume we're done with frobbing the cache/tlb for 4298 * now. Make sure any future pmap ops don't skip cache/tlb 4299 * flushes. 4300 */ 4301 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4302 } 4303 4304 PMAPCOUNT(updates); 4305 4306 /* 4307 * make sure TLB/cache operations have completed. 4308 */ 4309 cpu_cpwait(); 4310 } 4311 4312 void 4313 pmap_remove_all(pmap_t pm) 4314 { 4315 4316 /* 4317 * The vmspace described by this pmap is about to be torn down. 4318 * Until pmap_update() is called, UVM will only make calls 4319 * to pmap_remove(). We can make life much simpler by flushing 4320 * the cache now, and deferring TLB invalidation to pmap_update(). 4321 */ 4322 #ifdef PMAP_CACHE_VIVT 4323 pmap_cache_wbinv_all(pm, PVF_EXEC); 4324 #endif 4325 pm->pm_remove_all = true; 4326 } 4327 4328 /* 4329 * Retire the given physical map from service. 4330 * Should only be called if the map contains no valid mappings. 4331 */ 4332 void 4333 pmap_destroy(pmap_t pm) 4334 { 4335 u_int count; 4336 4337 if (pm == NULL) 4338 return; 4339 4340 if (pm->pm_remove_all) { 4341 pmap_tlb_flushID(pm); 4342 pm->pm_remove_all = false; 4343 } 4344 4345 /* 4346 * Drop reference count 4347 */ 4348 mutex_enter(pm->pm_lock); 4349 count = --pm->pm_obj.uo_refs; 4350 mutex_exit(pm->pm_lock); 4351 if (count > 0) { 4352 if (pmap_is_current(pm)) { 4353 if (pm != pmap_kernel()) 4354 pmap_use_l1(pm); 4355 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4356 } 4357 return; 4358 } 4359 4360 /* 4361 * reference count is zero, free pmap resources and then free pmap. 4362 */ 4363 4364 #ifndef ARM_HAS_VBAR 4365 if (vector_page < KERNEL_BASE) { 4366 KDASSERT(!pmap_is_current(pm)); 4367 4368 /* Remove the vector page mapping */ 4369 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4370 pmap_update(pm); 4371 } 4372 #endif 4373 4374 LIST_REMOVE(pm, pm_list); 4375 4376 pmap_free_l1(pm); 4377 4378 if (pmap_recent_user == pm) 4379 pmap_recent_user = NULL; 4380 4381 uvm_obj_destroy(&pm->pm_obj, false); 4382 mutex_destroy(&pm->pm_obj_lock); 4383 pool_cache_put(&pmap_cache, pm); 4384 } 4385 4386 4387 /* 4388 * void pmap_reference(pmap_t pm) 4389 * 4390 * Add a reference to the specified pmap. 4391 */ 4392 void 4393 pmap_reference(pmap_t pm) 4394 { 4395 4396 if (pm == NULL) 4397 return; 4398 4399 pmap_use_l1(pm); 4400 4401 mutex_enter(pm->pm_lock); 4402 pm->pm_obj.uo_refs++; 4403 mutex_exit(pm->pm_lock); 4404 } 4405 4406 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4407 4408 static struct evcnt pmap_prefer_nochange_ev = 4409 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4410 static struct evcnt pmap_prefer_change_ev = 4411 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4412 4413 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4414 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4415 4416 void 4417 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4418 { 4419 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4420 vaddr_t va = *vap; 4421 vaddr_t diff = (hint - va) & mask; 4422 if (diff == 0) { 4423 pmap_prefer_nochange_ev.ev_count++; 4424 } else { 4425 pmap_prefer_change_ev.ev_count++; 4426 if (__predict_false(td)) 4427 va -= mask + 1; 4428 *vap = va + diff; 4429 } 4430 } 4431 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4432 4433 /* 4434 * pmap_zero_page() 4435 * 4436 * Zero a given physical page by mapping it at a page hook point. 4437 * In doing the zero page op, the page we zero is mapped cachable, as with 4438 * StrongARM accesses to non-cached pages are non-burst making writing 4439 * _any_ bulk data very slow. 4440 */ 4441 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4442 void 4443 pmap_zero_page_generic(paddr_t phys) 4444 { 4445 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4446 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4447 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4448 #endif 4449 #if defined(PMAP_CACHE_VIPT) 4450 /* Choose the last page color it had, if any */ 4451 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4452 #else 4453 const vsize_t va_offset = 0; 4454 #endif 4455 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 4456 /* 4457 * Is this page mapped at its natural color? 4458 * If we have all of memory mapped, then just convert PA to VA. 4459 */ 4460 const bool okcolor = va_offset == (phys & arm_cache_prefer_mask); 4461 const vaddr_t vdstp = KERNEL_BASE + (phys - physical_start); 4462 #else 4463 const bool okcolor = false; 4464 const vaddr_t vdstp = cdstp + va_offset; 4465 #endif 4466 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4467 4468 4469 #ifdef DEBUG 4470 if (!SLIST_EMPTY(&md->pvh_list)) 4471 panic("pmap_zero_page: page has mappings"); 4472 #endif 4473 4474 KDASSERT((phys & PGOFSET) == 0); 4475 4476 if (!okcolor) { 4477 /* 4478 * Hook in the page, zero it, and purge the cache for that 4479 * zeroed page. Invalidate the TLB as needed. 4480 */ 4481 *ptep = L2_S_PROTO | phys | 4482 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4483 PTE_SYNC(ptep); 4484 cpu_tlb_flushD_SE(cdstp + va_offset); 4485 cpu_cpwait(); 4486 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 4487 /* 4488 * If we are direct-mapped and our color isn't ok, then before 4489 * we bzero the page invalidate its contents from the cache and 4490 * reset the color to its natural color. 4491 */ 4492 cpu_dcache_inv_range(cdstp + va_offset, PAGE_SIZE); 4493 md->pvh_attrs &= ~arm_cache_prefer_mask; 4494 md->pvh_attrs |= (phys & arm_cache_prefer_mask); 4495 #endif 4496 } 4497 bzero_page(vdstp); 4498 if (!okcolor) { 4499 /* 4500 * Unmap the page. 4501 */ 4502 *ptep = 0; 4503 PTE_SYNC(ptep); 4504 cpu_tlb_flushD_SE(cdstp + va_offset); 4505 #ifdef PMAP_CACHE_VIVT 4506 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4507 #endif 4508 } 4509 #ifdef PMAP_CACHE_VIPT 4510 /* 4511 * This page is now cache resident so it now has a page color. 4512 * Any contents have been obliterated so clear the EXEC flag. 4513 */ 4514 if (!pmap_is_page_colored_p(md)) { 4515 PMAPCOUNT(vac_color_new); 4516 md->pvh_attrs |= PVF_COLORED; 4517 } 4518 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4519 md->pvh_attrs &= ~PVF_EXEC; 4520 PMAPCOUNT(exec_discarded_zero); 4521 } 4522 md->pvh_attrs |= PVF_DIRTY; 4523 #endif 4524 } 4525 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4526 4527 #if ARM_MMU_XSCALE == 1 4528 void 4529 pmap_zero_page_xscale(paddr_t phys) 4530 { 4531 #ifdef DEBUG 4532 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4533 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4534 4535 if (!SLIST_EMPTY(&md->pvh_list)) 4536 panic("pmap_zero_page: page has mappings"); 4537 #endif 4538 4539 KDASSERT((phys & PGOFSET) == 0); 4540 4541 /* 4542 * Hook in the page, zero it, and purge the cache for that 4543 * zeroed page. Invalidate the TLB as needed. 4544 */ 4545 *cdst_pte = L2_S_PROTO | phys | 4546 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4547 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4548 PTE_SYNC(cdst_pte); 4549 cpu_tlb_flushD_SE(cdstp); 4550 cpu_cpwait(); 4551 bzero_page(cdstp); 4552 xscale_cache_clean_minidata(); 4553 } 4554 #endif /* ARM_MMU_XSCALE == 1 */ 4555 4556 /* pmap_pageidlezero() 4557 * 4558 * The same as above, except that we assume that the page is not 4559 * mapped. This means we never have to flush the cache first. Called 4560 * from the idle loop. 4561 */ 4562 bool 4563 pmap_pageidlezero(paddr_t phys) 4564 { 4565 unsigned int i; 4566 int *ptr; 4567 bool rv = true; 4568 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4569 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4570 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4571 #endif 4572 #ifdef PMAP_CACHE_VIPT 4573 /* Choose the last page color it had, if any */ 4574 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4575 #else 4576 const vsize_t va_offset = 0; 4577 #endif 4578 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4579 4580 4581 #ifdef DEBUG 4582 if (!SLIST_EMPTY(&md->pvh_list)) 4583 panic("pmap_pageidlezero: page has mappings"); 4584 #endif 4585 4586 KDASSERT((phys & PGOFSET) == 0); 4587 4588 /* 4589 * Hook in the page, zero it, and purge the cache for that 4590 * zeroed page. Invalidate the TLB as needed. 4591 */ 4592 *ptep = L2_S_PROTO | phys | 4593 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4594 PTE_SYNC(ptep); 4595 cpu_tlb_flushD_SE(cdstp + va_offset); 4596 cpu_cpwait(); 4597 4598 for (i = 0, ptr = (int *)(cdstp + va_offset); 4599 i < (PAGE_SIZE / sizeof(int)); i++) { 4600 if (sched_curcpu_runnable_p() != 0) { 4601 /* 4602 * A process has become ready. Abort now, 4603 * so we don't keep it waiting while we 4604 * do slow memory access to finish this 4605 * page. 4606 */ 4607 rv = false; 4608 break; 4609 } 4610 *ptr++ = 0; 4611 } 4612 4613 #ifdef PMAP_CACHE_VIVT 4614 if (rv) 4615 /* 4616 * if we aborted we'll rezero this page again later so don't 4617 * purge it unless we finished it 4618 */ 4619 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4620 #elif defined(PMAP_CACHE_VIPT) 4621 /* 4622 * This page is now cache resident so it now has a page color. 4623 * Any contents have been obliterated so clear the EXEC flag. 4624 */ 4625 if (!pmap_is_page_colored_p(md)) { 4626 PMAPCOUNT(vac_color_new); 4627 md->pvh_attrs |= PVF_COLORED; 4628 } 4629 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4630 md->pvh_attrs &= ~PVF_EXEC; 4631 PMAPCOUNT(exec_discarded_zero); 4632 } 4633 #endif 4634 /* 4635 * Unmap the page. 4636 */ 4637 *ptep = 0; 4638 PTE_SYNC(ptep); 4639 cpu_tlb_flushD_SE(cdstp + va_offset); 4640 4641 return (rv); 4642 } 4643 4644 /* 4645 * pmap_copy_page() 4646 * 4647 * Copy one physical page into another, by mapping the pages into 4648 * hook points. The same comment regarding cachability as in 4649 * pmap_zero_page also applies here. 4650 */ 4651 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4652 void 4653 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4654 { 4655 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4656 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4657 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4658 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4659 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4660 #endif 4661 #ifdef PMAP_CACHE_VIPT 4662 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4663 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4664 #else 4665 const vsize_t src_va_offset = 0; 4666 const vsize_t dst_va_offset = 0; 4667 #endif 4668 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 4669 /* 4670 * Is this page mapped at its natural color? 4671 * If we have all of memory mapped, then just convert PA to VA. 4672 */ 4673 const bool src_okcolor = src_va_offset == (src & arm_cache_prefer_mask); 4674 const bool dst_okcolor = dst_va_offset == (dst & arm_cache_prefer_mask); 4675 const vaddr_t vsrcp = src_okcolor 4676 ? KERNEL_BASE + (src - physical_start) 4677 : csrcp + src_va_offset; 4678 const vaddr_t vdstp = KERNEL_BASE + (dst - physical_start); 4679 #else 4680 const bool src_okcolor = false; 4681 const bool dst_okcolor = false; 4682 const vaddr_t vsrcp = csrcp + src_va_offset; 4683 const vaddr_t vdstp = cdstp + dst_va_offset; 4684 #endif 4685 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4686 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4687 4688 #ifdef DEBUG 4689 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4690 panic("pmap_copy_page: dst page has mappings"); 4691 #endif 4692 4693 #ifdef PMAP_CACHE_VIPT 4694 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4695 #endif 4696 KDASSERT((src & PGOFSET) == 0); 4697 KDASSERT((dst & PGOFSET) == 0); 4698 4699 /* 4700 * Clean the source page. Hold the source page's lock for 4701 * the duration of the copy so that no other mappings can 4702 * be created while we have a potentially aliased mapping. 4703 */ 4704 #ifdef MULTIPROCESSOR 4705 KASSERT(uvm_page_locked_p(src_pg)); 4706 #endif 4707 #ifdef PMAP_CACHE_VIVT 4708 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4709 #endif 4710 4711 /* 4712 * Map the pages into the page hook points, copy them, and purge 4713 * the cache for the appropriate page. Invalidate the TLB 4714 * as required. 4715 */ 4716 if (!src_okcolor) { 4717 *src_ptep = L2_S_PROTO 4718 | src 4719 #ifdef PMAP_CACHE_VIPT 4720 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4721 #endif 4722 #ifdef PMAP_CACHE_VIVT 4723 | pte_l2_s_cache_mode 4724 #endif 4725 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4726 PTE_SYNC(src_ptep); 4727 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4728 cpu_cpwait(); 4729 } 4730 if (!dst_okcolor) { 4731 *dst_ptep = L2_S_PROTO | dst | 4732 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4733 PTE_SYNC(dst_ptep); 4734 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4735 cpu_cpwait(); 4736 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 4737 /* 4738 * If we are direct-mapped and our color isn't ok, then before 4739 * we bcopy to the new page invalidate its contents from the 4740 * cache and reset its color to its natural color. 4741 */ 4742 cpu_dcache_inv_range(cdstp + dst_va_offset, PAGE_SIZE); 4743 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 4744 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 4745 #endif 4746 } 4747 bcopy_page(vsrcp, vdstp); 4748 #ifdef PMAP_CACHE_VIVT 4749 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 4750 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 4751 #endif 4752 /* 4753 * Unmap the pages. 4754 */ 4755 if (!src_okcolor) { 4756 *src_ptep = 0; 4757 PTE_SYNC(src_ptep); 4758 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4759 cpu_cpwait(); 4760 } 4761 if (!dst_okcolor) { 4762 *dst_ptep = 0; 4763 PTE_SYNC(dst_ptep); 4764 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4765 cpu_cpwait(); 4766 } 4767 #ifdef PMAP_CACHE_VIPT 4768 /* 4769 * Now that the destination page is in the cache, mark it as colored. 4770 * If this was an exec page, discard it. 4771 */ 4772 if (!pmap_is_page_colored_p(dst_md)) { 4773 PMAPCOUNT(vac_color_new); 4774 dst_md->pvh_attrs |= PVF_COLORED; 4775 } 4776 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4777 dst_md->pvh_attrs &= ~PVF_EXEC; 4778 PMAPCOUNT(exec_discarded_copy); 4779 } 4780 dst_md->pvh_attrs |= PVF_DIRTY; 4781 #endif 4782 } 4783 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4784 4785 #if ARM_MMU_XSCALE == 1 4786 void 4787 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4788 { 4789 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4790 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4791 #ifdef DEBUG 4792 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4793 4794 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4795 panic("pmap_copy_page: dst page has mappings"); 4796 #endif 4797 4798 KDASSERT((src & PGOFSET) == 0); 4799 KDASSERT((dst & PGOFSET) == 0); 4800 4801 /* 4802 * Clean the source page. Hold the source page's lock for 4803 * the duration of the copy so that no other mappings can 4804 * be created while we have a potentially aliased mapping. 4805 */ 4806 #ifdef MULTIPROCESSOR 4807 KASSERT(uvm_page_locked_p(src_pg)); 4808 #endif 4809 #ifdef PMAP_CACHE_VIVT 4810 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4811 #endif 4812 4813 /* 4814 * Map the pages into the page hook points, copy them, and purge 4815 * the cache for the appropriate page. Invalidate the TLB 4816 * as required. 4817 */ 4818 *csrc_pte = L2_S_PROTO | src | 4819 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4820 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4821 PTE_SYNC(csrc_pte); 4822 *cdst_pte = L2_S_PROTO | dst | 4823 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4824 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4825 PTE_SYNC(cdst_pte); 4826 cpu_tlb_flushD_SE(csrcp); 4827 cpu_tlb_flushD_SE(cdstp); 4828 cpu_cpwait(); 4829 bcopy_page(csrcp, cdstp); 4830 xscale_cache_clean_minidata(); 4831 } 4832 #endif /* ARM_MMU_XSCALE == 1 */ 4833 4834 /* 4835 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4836 * 4837 * Return the start and end addresses of the kernel's virtual space. 4838 * These values are setup in pmap_bootstrap and are updated as pages 4839 * are allocated. 4840 */ 4841 void 4842 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4843 { 4844 *start = virtual_avail; 4845 *end = virtual_end; 4846 } 4847 4848 /* 4849 * Helper function for pmap_grow_l2_bucket() 4850 */ 4851 static inline int 4852 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4853 { 4854 struct l2_bucket *l2b; 4855 pt_entry_t *ptep; 4856 paddr_t pa; 4857 4858 if (uvm.page_init_done == false) { 4859 #ifdef PMAP_STEAL_MEMORY 4860 pv_addr_t pv; 4861 pmap_boot_pagealloc(PAGE_SIZE, 4862 #ifdef PMAP_CACHE_VIPT 4863 arm_cache_prefer_mask, 4864 va & arm_cache_prefer_mask, 4865 #else 4866 0, 0, 4867 #endif 4868 &pv); 4869 pa = pv.pv_pa; 4870 #else 4871 if (uvm_page_physget(&pa) == false) 4872 return (1); 4873 #endif /* PMAP_STEAL_MEMORY */ 4874 } else { 4875 struct vm_page *pg; 4876 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4877 if (pg == NULL) 4878 return (1); 4879 pa = VM_PAGE_TO_PHYS(pg); 4880 #ifdef PMAP_CACHE_VIPT 4881 #ifdef DIAGNOSTIC 4882 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4883 #endif 4884 /* 4885 * This new page must not have any mappings. Enter it via 4886 * pmap_kenter_pa and let that routine do the hard work. 4887 */ 4888 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4889 pmap_kenter_pa(va, pa, 4890 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4891 #endif 4892 } 4893 4894 if (pap) 4895 *pap = pa; 4896 4897 PMAPCOUNT(pt_mappings); 4898 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4899 KDASSERT(l2b != NULL); 4900 4901 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4902 *ptep = L2_S_PROTO | pa | cache_mode | 4903 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4904 PTE_SYNC(ptep); 4905 memset((void *)va, 0, PAGE_SIZE); 4906 return (0); 4907 } 4908 4909 /* 4910 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4911 * used by pmap_growkernel(). 4912 */ 4913 static inline struct l2_bucket * 4914 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4915 { 4916 struct l2_dtable *l2; 4917 struct l2_bucket *l2b; 4918 u_short l1idx; 4919 vaddr_t nva; 4920 4921 l1idx = L1_IDX(va); 4922 4923 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4924 /* 4925 * No mapping at this address, as there is 4926 * no entry in the L1 table. 4927 * Need to allocate a new l2_dtable. 4928 */ 4929 nva = pmap_kernel_l2dtable_kva; 4930 if ((nva & PGOFSET) == 0) { 4931 /* 4932 * Need to allocate a backing page 4933 */ 4934 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4935 return (NULL); 4936 } 4937 4938 l2 = (struct l2_dtable *)nva; 4939 nva += sizeof(struct l2_dtable); 4940 4941 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4942 /* 4943 * The new l2_dtable straddles a page boundary. 4944 * Map in another page to cover it. 4945 */ 4946 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4947 return (NULL); 4948 } 4949 4950 pmap_kernel_l2dtable_kva = nva; 4951 4952 /* 4953 * Link it into the parent pmap 4954 */ 4955 pm->pm_l2[L2_IDX(l1idx)] = l2; 4956 } 4957 4958 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4959 4960 /* 4961 * Fetch pointer to the L2 page table associated with the address. 4962 */ 4963 if (l2b->l2b_kva == NULL) { 4964 pt_entry_t *ptep; 4965 4966 /* 4967 * No L2 page table has been allocated. Chances are, this 4968 * is because we just allocated the l2_dtable, above. 4969 */ 4970 nva = pmap_kernel_l2ptp_kva; 4971 ptep = (pt_entry_t *)nva; 4972 if ((nva & PGOFSET) == 0) { 4973 /* 4974 * Need to allocate a backing page 4975 */ 4976 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4977 &pmap_kernel_l2ptp_phys)) 4978 return (NULL); 4979 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4980 } 4981 4982 l2->l2_occupancy++; 4983 l2b->l2b_kva = ptep; 4984 l2b->l2b_l1idx = l1idx; 4985 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4986 4987 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4988 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4989 } 4990 4991 return (l2b); 4992 } 4993 4994 vaddr_t 4995 pmap_growkernel(vaddr_t maxkvaddr) 4996 { 4997 pmap_t kpm = pmap_kernel(); 4998 struct l1_ttable *l1; 4999 struct l2_bucket *l2b; 5000 pd_entry_t *pl1pd; 5001 int s; 5002 5003 if (maxkvaddr <= pmap_curmaxkvaddr) 5004 goto out; /* we are OK */ 5005 5006 NPDEBUG(PDB_GROWKERN, 5007 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5008 pmap_curmaxkvaddr, maxkvaddr)); 5009 5010 KDASSERT(maxkvaddr <= virtual_end); 5011 5012 /* 5013 * whoops! we need to add kernel PTPs 5014 */ 5015 5016 s = splhigh(); /* to be safe */ 5017 mutex_enter(kpm->pm_lock); 5018 5019 /* Map 1MB at a time */ 5020 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 5021 5022 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5023 KDASSERT(l2b != NULL); 5024 5025 /* Distribute new L1 entry to all other L1s */ 5026 SLIST_FOREACH(l1, &l1_list, l1_link) { 5027 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 5028 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 5029 L1_C_PROTO; 5030 PTE_SYNC(pl1pd); 5031 } 5032 } 5033 5034 /* 5035 * flush out the cache, expensive but growkernel will happen so 5036 * rarely 5037 */ 5038 cpu_dcache_wbinv_all(); 5039 cpu_tlb_flushD(); 5040 cpu_cpwait(); 5041 5042 mutex_exit(kpm->pm_lock); 5043 splx(s); 5044 5045 out: 5046 return (pmap_curmaxkvaddr); 5047 } 5048 5049 /************************ Utility routines ****************************/ 5050 5051 #ifndef ARM_HAS_VBAR 5052 /* 5053 * vector_page_setprot: 5054 * 5055 * Manipulate the protection of the vector page. 5056 */ 5057 void 5058 vector_page_setprot(int prot) 5059 { 5060 struct l2_bucket *l2b; 5061 pt_entry_t *ptep; 5062 5063 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5064 /* 5065 * If we are using VBAR to use the vectors in the kernel, then it's 5066 * already mapped in the kernel text so no need to anything here. 5067 */ 5068 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5069 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5070 return; 5071 } 5072 #endif 5073 5074 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5075 KDASSERT(l2b != NULL); 5076 5077 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5078 5079 *ptep = (*ptep & ~L2_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 5080 PTE_SYNC(ptep); 5081 cpu_tlb_flushD_SE(vector_page); 5082 cpu_cpwait(); 5083 } 5084 #endif 5085 5086 /* 5087 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5088 * Returns true if the mapping exists, else false. 5089 * 5090 * NOTE: This function is only used by a couple of arm-specific modules. 5091 * It is not safe to take any pmap locks here, since we could be right 5092 * in the middle of debugging the pmap anyway... 5093 * 5094 * It is possible for this routine to return false even though a valid 5095 * mapping does exist. This is because we don't lock, so the metadata 5096 * state may be inconsistent. 5097 * 5098 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5099 * a "section" mapping. 5100 */ 5101 bool 5102 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5103 { 5104 struct l2_dtable *l2; 5105 pd_entry_t *pl1pd, l1pd; 5106 pt_entry_t *ptep; 5107 u_short l1idx; 5108 5109 if (pm->pm_l1 == NULL) 5110 return false; 5111 5112 l1idx = L1_IDX(va); 5113 *pdp = pl1pd = pmap_l1_kva(pm) + l1idx; 5114 l1pd = *pl1pd; 5115 5116 if (l1pte_section_p(l1pd)) { 5117 *ptp = NULL; 5118 return true; 5119 } 5120 5121 if (pm->pm_l2 == NULL) 5122 return false; 5123 5124 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5125 5126 if (l2 == NULL || 5127 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5128 return false; 5129 } 5130 5131 *ptp = &ptep[l2pte_index(va)]; 5132 return true; 5133 } 5134 5135 bool 5136 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5137 { 5138 5139 if (pm->pm_l1 == NULL) 5140 return false; 5141 5142 *pdp = pmap_l1_kva(pm) + L1_IDX(va); 5143 5144 return true; 5145 } 5146 5147 /************************ Bootstrapping routines ****************************/ 5148 5149 static void 5150 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5151 { 5152 int i; 5153 5154 l1->l1_kva = l1pt; 5155 l1->l1_domain_use_count = 0; 5156 l1->l1_domain_first = 0; 5157 5158 for (i = 0; i < PMAP_DOMAINS; i++) 5159 l1->l1_domain_free[i] = i + 1; 5160 5161 /* 5162 * Copy the kernel's L1 entries to each new L1. 5163 */ 5164 if (pmap_initialized) 5165 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5166 5167 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5168 &l1->l1_physaddr) == false) 5169 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5170 5171 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5172 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5173 } 5174 5175 /* 5176 * pmap_bootstrap() is called from the board-specific initarm() routine 5177 * once the kernel L1/L2 descriptors tables have been set up. 5178 * 5179 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5180 * spread over a number of disparate files/functions. 5181 * 5182 * We are passed the following parameters 5183 * - kernel_l1pt 5184 * This is a pointer to the base of the kernel's L1 translation table. 5185 * - vstart 5186 * 1MB-aligned start of managed kernel virtual memory. 5187 * - vend 5188 * 1MB-aligned end of managed kernel virtual memory. 5189 * 5190 * We use the first parameter to build the metadata (struct l1_ttable and 5191 * struct l2_dtable) necessary to track kernel mappings. 5192 */ 5193 #define PMAP_STATIC_L2_SIZE 16 5194 void 5195 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5196 { 5197 static struct l1_ttable static_l1; 5198 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5199 struct l1_ttable *l1 = &static_l1; 5200 struct l2_dtable *l2; 5201 struct l2_bucket *l2b; 5202 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5203 pmap_t pm = pmap_kernel(); 5204 pd_entry_t pde; 5205 pt_entry_t *ptep; 5206 paddr_t pa; 5207 vaddr_t va; 5208 vsize_t size; 5209 int nptes, l1idx, l2idx, l2next = 0; 5210 5211 /* 5212 * Initialise the kernel pmap object 5213 */ 5214 pm->pm_l1 = l1; 5215 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5216 pm->pm_activated = true; 5217 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5218 5219 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5220 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5221 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5222 5223 /* 5224 * Scan the L1 translation table created by initarm() and create 5225 * the required metadata for all valid mappings found in it. 5226 */ 5227 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5228 pde = l1pt[l1idx]; 5229 5230 /* 5231 * We're only interested in Coarse mappings. 5232 * pmap_extract() can deal with section mappings without 5233 * recourse to checking L2 metadata. 5234 */ 5235 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5236 continue; 5237 5238 /* 5239 * Lookup the KVA of this L2 descriptor table 5240 */ 5241 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5242 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5243 if (ptep == NULL) { 5244 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5245 (u_int)l1idx << L1_S_SHIFT, pa); 5246 } 5247 5248 /* 5249 * Fetch the associated L2 metadata structure. 5250 * Allocate a new one if necessary. 5251 */ 5252 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5253 if (l2next == PMAP_STATIC_L2_SIZE) 5254 panic("pmap_bootstrap: out of static L2s"); 5255 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5256 } 5257 5258 /* 5259 * One more L1 slot tracked... 5260 */ 5261 l2->l2_occupancy++; 5262 5263 /* 5264 * Fill in the details of the L2 descriptor in the 5265 * appropriate bucket. 5266 */ 5267 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5268 l2b->l2b_kva = ptep; 5269 l2b->l2b_phys = pa; 5270 l2b->l2b_l1idx = l1idx; 5271 5272 /* 5273 * Establish an initial occupancy count for this descriptor 5274 */ 5275 for (l2idx = 0; 5276 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5277 l2idx++) { 5278 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5279 l2b->l2b_occupancy++; 5280 } 5281 } 5282 5283 /* 5284 * Make sure the descriptor itself has the correct cache mode. 5285 * If not, fix it, but whine about the problem. Port-meisters 5286 * should consider this a clue to fix up their initarm() 5287 * function. :) 5288 */ 5289 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5290 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5291 "L2 pte @ %p\n", ptep); 5292 } 5293 } 5294 5295 /* 5296 * Ensure the primary (kernel) L1 has the correct cache mode for 5297 * a page table. Bitch if it is not correctly set. 5298 */ 5299 for (va = (vaddr_t)l1pt; 5300 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5301 if (pmap_set_pt_cache_mode(l1pt, va)) 5302 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5303 "primary L1 @ 0x%lx\n", va); 5304 } 5305 5306 cpu_dcache_wbinv_all(); 5307 cpu_tlb_flushID(); 5308 cpu_cpwait(); 5309 5310 /* 5311 * now we allocate the "special" VAs which are used for tmp mappings 5312 * by the pmap (and other modules). we allocate the VAs by advancing 5313 * virtual_avail (note that there are no pages mapped at these VAs). 5314 * 5315 * Managed KVM space start from wherever initarm() tells us. 5316 */ 5317 virtual_avail = vstart; 5318 virtual_end = vend; 5319 5320 #ifdef PMAP_CACHE_VIPT 5321 /* 5322 * If we have a VIPT cache, we need one page/pte per possible alias 5323 * page so we won't violate cache aliasing rules. 5324 */ 5325 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5326 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5327 #else 5328 nptes = 1; 5329 #endif 5330 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5331 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5332 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5333 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5334 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5335 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5336 (void *)&msgbufaddr, NULL); 5337 5338 /* 5339 * Allocate a range of kernel virtual address space to be used 5340 * for L2 descriptor tables and metadata allocation in 5341 * pmap_growkernel(). 5342 */ 5343 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5344 pmap_alloc_specials(&virtual_avail, 5345 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5346 &pmap_kernel_l2ptp_kva, NULL); 5347 5348 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5349 pmap_alloc_specials(&virtual_avail, 5350 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5351 &pmap_kernel_l2dtable_kva, NULL); 5352 5353 /* 5354 * init the static-global locks and global pmap list. 5355 */ 5356 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 5357 5358 /* 5359 * We can now initialise the first L1's metadata. 5360 */ 5361 SLIST_INIT(&l1_list); 5362 TAILQ_INIT(&l1_lru_list); 5363 pmap_init_l1(l1, l1pt); 5364 5365 #ifndef ARM_HAS_VBAR 5366 /* Set up vector page L1 details, if necessary */ 5367 if (vector_page < KERNEL_BASE) { 5368 pm->pm_pl1vec = pmap_l1_kva(pm) + L1_IDX(vector_page); 5369 l2b = pmap_get_l2_bucket(pm, vector_page); 5370 KDASSERT(l2b != NULL); 5371 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5372 L1_C_DOM(pmap_domain(pm)); 5373 } else 5374 pm->pm_pl1vec = NULL; 5375 #endif 5376 5377 /* 5378 * Initialize the pmap cache 5379 */ 5380 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5381 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5382 LIST_INIT(&pmap_pmaps); 5383 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5384 5385 /* 5386 * Initialize the pv pool. 5387 */ 5388 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5389 &pmap_bootstrap_pv_allocator, IPL_NONE); 5390 5391 /* 5392 * Initialize the L2 dtable pool and cache. 5393 */ 5394 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5395 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5396 5397 /* 5398 * Initialise the L2 descriptor table pool and cache 5399 */ 5400 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5401 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5402 pmap_l2ptp_ctor, NULL, NULL); 5403 5404 cpu_dcache_wbinv_all(); 5405 } 5406 5407 static int 5408 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5409 { 5410 pd_entry_t *pdep, pde; 5411 pt_entry_t *ptep, pte; 5412 vaddr_t pa; 5413 int rv = 0; 5414 5415 /* 5416 * Make sure the descriptor itself has the correct cache mode 5417 */ 5418 pdep = &kl1[L1_IDX(va)]; 5419 pde = *pdep; 5420 5421 if (l1pte_section_p(pde)) { 5422 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 5423 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5424 *pdep = (pde & ~L1_S_CACHE_MASK) | 5425 pte_l1_s_cache_mode_pt; 5426 PTE_SYNC(pdep); 5427 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5428 rv = 1; 5429 } 5430 } else { 5431 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5432 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5433 if (ptep == NULL) 5434 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5435 5436 ptep = &ptep[l2pte_index(va)]; 5437 pte = *ptep; 5438 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5439 *ptep = (pte & ~L2_S_CACHE_MASK) | 5440 pte_l2_s_cache_mode_pt; 5441 PTE_SYNC(ptep); 5442 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5443 rv = 1; 5444 } 5445 } 5446 5447 return (rv); 5448 } 5449 5450 static void 5451 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5452 { 5453 vaddr_t va = *availp; 5454 struct l2_bucket *l2b; 5455 5456 if (ptep) { 5457 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5458 if (l2b == NULL) 5459 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5460 5461 if (ptep) 5462 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5463 } 5464 5465 *vap = va; 5466 *availp = va + (PAGE_SIZE * pages); 5467 } 5468 5469 void 5470 pmap_init(void) 5471 { 5472 5473 /* 5474 * Set the available memory vars - These do not map to real memory 5475 * addresses and cannot as the physical memory is fragmented. 5476 * They are used by ps for %mem calculations. 5477 * One could argue whether this should be the entire memory or just 5478 * the memory that is useable in a user process. 5479 */ 5480 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5481 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5482 5483 /* 5484 * Now we need to free enough pv_entry structures to allow us to get 5485 * the kmem_map/kmem_object allocated and inited (done after this 5486 * function is finished). to do this we allocate one bootstrap page out 5487 * of kernel_map and use it to provide an initial pool of pv_entry 5488 * structures. we never free this page. 5489 */ 5490 pool_setlowat(&pmap_pv_pool, 5491 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5492 5493 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5494 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5495 UVM_KMF_WIRED|UVM_KMF_ZERO); 5496 5497 pmap_initialized = true; 5498 } 5499 5500 static vaddr_t last_bootstrap_page = 0; 5501 static void *free_bootstrap_pages = NULL; 5502 5503 static void * 5504 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5505 { 5506 extern void *pool_page_alloc(struct pool *, int); 5507 vaddr_t new_page; 5508 void *rv; 5509 5510 if (pmap_initialized) 5511 return (pool_page_alloc(pp, flags)); 5512 5513 if (free_bootstrap_pages) { 5514 rv = free_bootstrap_pages; 5515 free_bootstrap_pages = *((void **)rv); 5516 return (rv); 5517 } 5518 5519 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5520 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5521 5522 KASSERT(new_page > last_bootstrap_page); 5523 last_bootstrap_page = new_page; 5524 return ((void *)new_page); 5525 } 5526 5527 static void 5528 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5529 { 5530 extern void pool_page_free(struct pool *, void *); 5531 5532 if ((vaddr_t)v <= last_bootstrap_page) { 5533 *((void **)v) = free_bootstrap_pages; 5534 free_bootstrap_pages = v; 5535 return; 5536 } 5537 5538 if (pmap_initialized) { 5539 pool_page_free(pp, v); 5540 return; 5541 } 5542 } 5543 5544 /* 5545 * pmap_postinit() 5546 * 5547 * This routine is called after the vm and kmem subsystems have been 5548 * initialised. This allows the pmap code to perform any initialisation 5549 * that can only be done one the memory allocation is in place. 5550 */ 5551 void 5552 pmap_postinit(void) 5553 { 5554 extern paddr_t physical_start, physical_end; 5555 struct l2_bucket *l2b; 5556 struct l1_ttable *l1; 5557 struct pglist plist; 5558 struct vm_page *m; 5559 pd_entry_t *pl1pt; 5560 pt_entry_t *ptep, pte; 5561 vaddr_t va, eva; 5562 u_int loop, needed; 5563 int error; 5564 5565 pool_cache_setlowat(&pmap_l2ptp_cache, 5566 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5567 pool_cache_setlowat(&pmap_l2dtable_cache, 5568 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5569 5570 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5571 needed -= 1; 5572 5573 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 5574 5575 for (loop = 0; loop < needed; loop++, l1++) { 5576 /* Allocate a L1 page table */ 5577 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5578 if (va == 0) 5579 panic("Cannot allocate L1 KVM"); 5580 5581 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5582 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 5583 if (error) 5584 panic("Cannot allocate L1 physical pages"); 5585 5586 m = TAILQ_FIRST(&plist); 5587 eva = va + L1_TABLE_SIZE; 5588 pl1pt = (pd_entry_t *)va; 5589 5590 while (m && va < eva) { 5591 paddr_t pa = VM_PAGE_TO_PHYS(m); 5592 5593 pmap_kenter_pa(va, pa, 5594 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5595 5596 /* 5597 * Make sure the L1 descriptor table is mapped 5598 * with the cache-mode set to write-through. 5599 */ 5600 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5601 KDASSERT(l2b != NULL); 5602 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5603 pte = *ptep; 5604 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5605 *ptep = pte; 5606 PTE_SYNC(ptep); 5607 cpu_tlb_flushD_SE(va); 5608 5609 va += PAGE_SIZE; 5610 m = TAILQ_NEXT(m, pageq.queue); 5611 } 5612 5613 #ifdef DIAGNOSTIC 5614 if (m) 5615 panic("pmap_alloc_l1pt: pglist not empty"); 5616 #endif /* DIAGNOSTIC */ 5617 5618 pmap_init_l1(l1, pl1pt); 5619 } 5620 5621 #ifdef DEBUG 5622 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5623 needed); 5624 #endif 5625 } 5626 5627 /* 5628 * Note that the following routines are used by board-specific initialisation 5629 * code to configure the initial kernel page tables. 5630 * 5631 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5632 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5633 * behaviour of the old pmap, and provides an easy migration path for 5634 * initial bring-up of the new pmap on existing ports. Fortunately, 5635 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5636 * will be deprecated. 5637 * 5638 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5639 * tables. 5640 */ 5641 5642 /* 5643 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5644 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5645 * find them as necessary. 5646 * 5647 * Note that the data on this list MUST remain valid after initarm() returns, 5648 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5649 */ 5650 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5651 5652 static vaddr_t 5653 kernel_pt_lookup(paddr_t pa) 5654 { 5655 pv_addr_t *pv; 5656 5657 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5658 #ifndef ARM32_NEW_VM_LAYOUT 5659 if (pv->pv_pa == (pa & ~PGOFSET)) 5660 return (pv->pv_va | (pa & PGOFSET)); 5661 #else 5662 if (pv->pv_pa == pa) 5663 return (pv->pv_va); 5664 #endif 5665 } 5666 return (0); 5667 } 5668 5669 /* 5670 * pmap_map_section: 5671 * 5672 * Create a single section mapping. 5673 */ 5674 void 5675 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5676 { 5677 pd_entry_t *pde = (pd_entry_t *) l1pt; 5678 pd_entry_t fl; 5679 5680 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5681 5682 switch (cache) { 5683 case PTE_NOCACHE: 5684 default: 5685 fl = 0; 5686 break; 5687 5688 case PTE_CACHE: 5689 fl = pte_l1_s_cache_mode; 5690 break; 5691 5692 case PTE_PAGETABLE: 5693 fl = pte_l1_s_cache_mode_pt; 5694 break; 5695 } 5696 5697 pde[L1_IDX(va)] = L1_S_PROTO | pa | 5698 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5699 PTE_SYNC(&pde[L1_IDX(va)]); 5700 } 5701 5702 /* 5703 * pmap_map_entry: 5704 * 5705 * Create a single page mapping. 5706 */ 5707 void 5708 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5709 { 5710 pd_entry_t *pde = (pd_entry_t *) l1pt; 5711 pt_entry_t npte; 5712 pt_entry_t *ptep; 5713 5714 KASSERT(((va | pa) & PGOFSET) == 0); 5715 5716 switch (cache) { 5717 case PTE_NOCACHE: 5718 default: 5719 npte = 0; 5720 break; 5721 5722 case PTE_CACHE: 5723 npte = pte_l2_s_cache_mode; 5724 break; 5725 5726 case PTE_PAGETABLE: 5727 npte = pte_l2_s_cache_mode_pt; 5728 break; 5729 } 5730 5731 if ((pde[L1_IDX(va)] & L1_TYPE_MASK) != L1_TYPE_C) 5732 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5733 5734 #ifndef ARM32_NEW_VM_LAYOUT 5735 ptep = (pt_entry_t *) 5736 kernel_pt_lookup(pde[L1_IDX(va)] & L2_S_FRAME); 5737 #else 5738 ptep = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5739 #endif 5740 if (ptep == NULL) 5741 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5742 5743 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5744 #ifndef ARM32_NEW_VM_LAYOUT 5745 ptep += (va >> PGSHIFT) & 0x3ff; 5746 #else 5747 ptep += l2pte_index(va); 5748 #endif 5749 l2pte_set(ptep, npte, 0); 5750 PTE_SYNC(ptep); 5751 } 5752 5753 /* 5754 * pmap_link_l2pt: 5755 * 5756 * Link the L2 page table specified by "l2pv" into the L1 5757 * page table at the slot for "va". 5758 */ 5759 void 5760 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5761 { 5762 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5763 u_int slot = L1_IDX(va); 5764 5765 #ifndef ARM32_NEW_VM_LAYOUT 5766 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5767 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5768 #endif 5769 5770 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5771 5772 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5773 #ifdef ARM32_NEW_VM_LAYOUT 5774 PTE_SYNC(&pde[slot]); 5775 #else 5776 for (u_int off = 0, i = 0; off < PAGE_SIZE; off += L2_T_SIZE, i++) { 5777 pde[slot + i] = proto | (l2pv->pv_pa + off); 5778 } 5779 PTE_SYNC_RANGE(&pde[slot + 0], PAGE_SIZE / L2_T_SIZE); 5780 #endif 5781 5782 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5783 } 5784 5785 /* 5786 * pmap_map_chunk: 5787 * 5788 * Map a chunk of memory using the most efficient mappings 5789 * possible (section, large page, small page) into the 5790 * provided L1 and L2 tables at the specified virtual address. 5791 */ 5792 vsize_t 5793 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5794 int prot, int cache) 5795 { 5796 pd_entry_t *pdep = (pd_entry_t *) l1pt; 5797 pt_entry_t *pte, f1, f2s, f2l; 5798 vsize_t resid; 5799 int i; 5800 5801 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5802 5803 if (l1pt == 0) 5804 panic("pmap_map_chunk: no L1 table provided"); 5805 5806 #ifdef VERBOSE_INIT_ARM 5807 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5808 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5809 #endif 5810 5811 switch (cache) { 5812 case PTE_NOCACHE: 5813 default: 5814 f1 = 0; 5815 f2l = 0; 5816 f2s = 0; 5817 break; 5818 5819 case PTE_CACHE: 5820 f1 = pte_l1_s_cache_mode; 5821 f2l = pte_l2_l_cache_mode; 5822 f2s = pte_l2_s_cache_mode; 5823 break; 5824 5825 case PTE_PAGETABLE: 5826 f1 = pte_l1_s_cache_mode_pt; 5827 f2l = pte_l2_l_cache_mode_pt; 5828 f2s = pte_l2_s_cache_mode_pt; 5829 break; 5830 } 5831 5832 size = resid; 5833 5834 while (resid > 0) { 5835 size_t l1idx = L1_IDX(va); 5836 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5837 /* See if we can use a supersection mapping. */ 5838 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 5839 /* Supersection are always domain 0 */ 5840 pd_entry_t pde = L1_SS_PROTO | pa | 5841 L1_S_PROT(PTE_KERNEL, prot) | f1; 5842 #ifdef VERBOSE_INIT_ARM 5843 printf("sS"); 5844 #endif 5845 for (size_t s = l1idx, 5846 e = s + L1_SS_SIZE / L1_S_SIZE; 5847 s < e; 5848 s++) { 5849 pdep[s] = pde; 5850 PTE_SYNC(&pdep[s]); 5851 } 5852 va += L1_SS_SIZE; 5853 pa += L1_SS_SIZE; 5854 resid -= L1_SS_SIZE; 5855 continue; 5856 } 5857 #endif 5858 /* See if we can use a section mapping. */ 5859 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5860 #ifdef VERBOSE_INIT_ARM 5861 printf("S"); 5862 #endif 5863 pdep[l1idx] = L1_S_PROTO | pa | 5864 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5865 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5866 PTE_SYNC(&pdep[l1idx]); 5867 va += L1_S_SIZE; 5868 pa += L1_S_SIZE; 5869 resid -= L1_S_SIZE; 5870 continue; 5871 } 5872 5873 /* 5874 * Ok, we're going to use an L2 table. Make sure 5875 * one is actually in the corresponding L1 slot 5876 * for the current VA. 5877 */ 5878 if ((pdep[l1idx] & L1_TYPE_MASK) != L1_TYPE_C) 5879 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5880 5881 #ifndef ARM32_NEW_VM_LAYOUT 5882 pte = (pt_entry_t *) 5883 kernel_pt_lookup(pdep[l1idx] & L2_S_FRAME); 5884 #else 5885 pte = (pt_entry_t *) kernel_pt_lookup( 5886 pdep[l1idx] & L1_C_ADDR_MASK); 5887 #endif 5888 if (pte == NULL) 5889 panic("pmap_map_chunk: can't find L2 table for VA" 5890 "0x%08lx", va); 5891 5892 /* See if we can use a L2 large page mapping. */ 5893 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5894 #ifdef VERBOSE_INIT_ARM 5895 printf("L"); 5896 #endif 5897 for (i = 0; i < 16; i++) { 5898 #ifndef ARM32_NEW_VM_LAYOUT 5899 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5900 L2_L_PROTO | pa | 5901 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5902 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5903 #else 5904 pte[l2pte_index(va) + i] = 5905 L2_L_PROTO | pa | 5906 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5907 PTE_SYNC(&pte[l2pte_index(va) + i]); 5908 #endif 5909 } 5910 va += L2_L_SIZE; 5911 pa += L2_L_SIZE; 5912 resid -= L2_L_SIZE; 5913 continue; 5914 } 5915 5916 /* Use a small page mapping. */ 5917 #ifdef VERBOSE_INIT_ARM 5918 printf("P"); 5919 #endif 5920 pt_entry_t npte = 5921 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5922 #ifndef ARM32_NEW_VM_LAYOUT 5923 pt_entry_t *ptep = &pte[(va >> PGSHIFT) & 0x3ff]; 5924 #else 5925 pt_entry_t *ptep = &pte[l2pte_index(va)]; 5926 #endif 5927 l2pte_set(ptep, npte, 0); 5928 PTE_SYNC(ptep); 5929 va += PAGE_SIZE; 5930 pa += PAGE_SIZE; 5931 resid -= PAGE_SIZE; 5932 } 5933 #ifdef VERBOSE_INIT_ARM 5934 printf("\n"); 5935 #endif 5936 return (size); 5937 } 5938 5939 /********************** Static device map routines ***************************/ 5940 5941 static const struct pmap_devmap *pmap_devmap_table; 5942 5943 /* 5944 * Register the devmap table. This is provided in case early console 5945 * initialization needs to register mappings created by bootstrap code 5946 * before pmap_devmap_bootstrap() is called. 5947 */ 5948 void 5949 pmap_devmap_register(const struct pmap_devmap *table) 5950 { 5951 5952 pmap_devmap_table = table; 5953 } 5954 5955 /* 5956 * Map all of the static regions in the devmap table, and remember 5957 * the devmap table so other parts of the kernel can look up entries 5958 * later. 5959 */ 5960 void 5961 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5962 { 5963 int i; 5964 5965 pmap_devmap_table = table; 5966 5967 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5968 #ifdef VERBOSE_INIT_ARM 5969 printf("devmap: %08lx -> %08lx @ %08lx\n", 5970 pmap_devmap_table[i].pd_pa, 5971 pmap_devmap_table[i].pd_pa + 5972 pmap_devmap_table[i].pd_size - 1, 5973 pmap_devmap_table[i].pd_va); 5974 #endif 5975 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5976 pmap_devmap_table[i].pd_pa, 5977 pmap_devmap_table[i].pd_size, 5978 pmap_devmap_table[i].pd_prot, 5979 pmap_devmap_table[i].pd_cache); 5980 } 5981 } 5982 5983 const struct pmap_devmap * 5984 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5985 { 5986 uint64_t endpa; 5987 int i; 5988 5989 if (pmap_devmap_table == NULL) 5990 return (NULL); 5991 5992 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5993 5994 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5995 if (pa >= pmap_devmap_table[i].pd_pa && 5996 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5997 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5998 return (&pmap_devmap_table[i]); 5999 } 6000 6001 return (NULL); 6002 } 6003 6004 const struct pmap_devmap * 6005 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6006 { 6007 int i; 6008 6009 if (pmap_devmap_table == NULL) 6010 return (NULL); 6011 6012 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6013 if (va >= pmap_devmap_table[i].pd_va && 6014 va + size - 1 <= pmap_devmap_table[i].pd_va + 6015 pmap_devmap_table[i].pd_size - 1) 6016 return (&pmap_devmap_table[i]); 6017 } 6018 6019 return (NULL); 6020 } 6021 6022 /********************** PTE initialization routines **************************/ 6023 6024 /* 6025 * These routines are called when the CPU type is identified to set up 6026 * the PTE prototypes, cache modes, etc. 6027 * 6028 * The variables are always here, just in case modules need to reference 6029 * them (though, they shouldn't). 6030 */ 6031 6032 pt_entry_t pte_l1_s_cache_mode; 6033 pt_entry_t pte_l1_s_wc_mode; 6034 pt_entry_t pte_l1_s_cache_mode_pt; 6035 pt_entry_t pte_l1_s_cache_mask; 6036 6037 pt_entry_t pte_l2_l_cache_mode; 6038 pt_entry_t pte_l2_l_wc_mode; 6039 pt_entry_t pte_l2_l_cache_mode_pt; 6040 pt_entry_t pte_l2_l_cache_mask; 6041 6042 pt_entry_t pte_l2_s_cache_mode; 6043 pt_entry_t pte_l2_s_wc_mode; 6044 pt_entry_t pte_l2_s_cache_mode_pt; 6045 pt_entry_t pte_l2_s_cache_mask; 6046 6047 pt_entry_t pte_l1_s_prot_u; 6048 pt_entry_t pte_l1_s_prot_w; 6049 pt_entry_t pte_l1_s_prot_ro; 6050 pt_entry_t pte_l1_s_prot_mask; 6051 6052 pt_entry_t pte_l2_s_prot_u; 6053 pt_entry_t pte_l2_s_prot_w; 6054 pt_entry_t pte_l2_s_prot_ro; 6055 pt_entry_t pte_l2_s_prot_mask; 6056 6057 pt_entry_t pte_l2_l_prot_u; 6058 pt_entry_t pte_l2_l_prot_w; 6059 pt_entry_t pte_l2_l_prot_ro; 6060 pt_entry_t pte_l2_l_prot_mask; 6061 6062 pt_entry_t pte_l1_ss_proto; 6063 pt_entry_t pte_l1_s_proto; 6064 pt_entry_t pte_l1_c_proto; 6065 pt_entry_t pte_l2_s_proto; 6066 6067 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6068 void (*pmap_zero_page_func)(paddr_t); 6069 6070 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6071 void 6072 pmap_pte_init_generic(void) 6073 { 6074 6075 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6076 pte_l1_s_wc_mode = L1_S_B; 6077 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6078 6079 pte_l2_l_cache_mode = L2_B|L2_C; 6080 pte_l2_l_wc_mode = L2_B; 6081 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6082 6083 pte_l2_s_cache_mode = L2_B|L2_C; 6084 pte_l2_s_wc_mode = L2_B; 6085 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6086 6087 /* 6088 * If we have a write-through cache, set B and C. If 6089 * we have a write-back cache, then we assume setting 6090 * only C will make those pages write-through (except for those 6091 * Cortex CPUs which can read the L1 caches). 6092 */ 6093 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6094 #if ARM_MMU_V7 > 0 6095 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6096 #endif 6097 #if ARM_MMU_V6 > 0 6098 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6099 #endif 6100 || false) { 6101 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6102 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6103 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6104 } else { 6105 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6106 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6107 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6108 } 6109 6110 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6111 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6112 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6113 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6114 6115 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6116 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6117 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6118 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6119 6120 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6121 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6122 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6123 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6124 6125 pte_l1_ss_proto = L1_SS_PROTO_generic; 6126 pte_l1_s_proto = L1_S_PROTO_generic; 6127 pte_l1_c_proto = L1_C_PROTO_generic; 6128 pte_l2_s_proto = L2_S_PROTO_generic; 6129 6130 pmap_copy_page_func = pmap_copy_page_generic; 6131 pmap_zero_page_func = pmap_zero_page_generic; 6132 } 6133 6134 #if defined(CPU_ARM8) 6135 void 6136 pmap_pte_init_arm8(void) 6137 { 6138 6139 /* 6140 * ARM8 is compatible with generic, but we need to use 6141 * the page tables uncached. 6142 */ 6143 pmap_pte_init_generic(); 6144 6145 pte_l1_s_cache_mode_pt = 0; 6146 pte_l2_l_cache_mode_pt = 0; 6147 pte_l2_s_cache_mode_pt = 0; 6148 } 6149 #endif /* CPU_ARM8 */ 6150 6151 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6152 void 6153 pmap_pte_init_arm9(void) 6154 { 6155 6156 /* 6157 * ARM9 is compatible with generic, but we want to use 6158 * write-through caching for now. 6159 */ 6160 pmap_pte_init_generic(); 6161 6162 pte_l1_s_cache_mode = L1_S_C; 6163 pte_l2_l_cache_mode = L2_C; 6164 pte_l2_s_cache_mode = L2_C; 6165 6166 pte_l1_s_wc_mode = L1_S_B; 6167 pte_l2_l_wc_mode = L2_B; 6168 pte_l2_s_wc_mode = L2_B; 6169 6170 pte_l1_s_cache_mode_pt = L1_S_C; 6171 pte_l2_l_cache_mode_pt = L2_C; 6172 pte_l2_s_cache_mode_pt = L2_C; 6173 } 6174 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6175 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6176 6177 #if defined(CPU_ARM10) 6178 void 6179 pmap_pte_init_arm10(void) 6180 { 6181 6182 /* 6183 * ARM10 is compatible with generic, but we want to use 6184 * write-through caching for now. 6185 */ 6186 pmap_pte_init_generic(); 6187 6188 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6189 pte_l2_l_cache_mode = L2_B | L2_C; 6190 pte_l2_s_cache_mode = L2_B | L2_C; 6191 6192 pte_l1_s_cache_mode = L1_S_B; 6193 pte_l2_l_cache_mode = L2_B; 6194 pte_l2_s_cache_mode = L2_B; 6195 6196 pte_l1_s_cache_mode_pt = L1_S_C; 6197 pte_l2_l_cache_mode_pt = L2_C; 6198 pte_l2_s_cache_mode_pt = L2_C; 6199 6200 } 6201 #endif /* CPU_ARM10 */ 6202 6203 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6204 void 6205 pmap_pte_init_arm11(void) 6206 { 6207 6208 /* 6209 * ARM11 is compatible with generic, but we want to use 6210 * write-through caching for now. 6211 */ 6212 pmap_pte_init_generic(); 6213 6214 pte_l1_s_cache_mode = L1_S_C; 6215 pte_l2_l_cache_mode = L2_C; 6216 pte_l2_s_cache_mode = L2_C; 6217 6218 pte_l1_s_wc_mode = L1_S_B; 6219 pte_l2_l_wc_mode = L2_B; 6220 pte_l2_s_wc_mode = L2_B; 6221 6222 pte_l1_s_cache_mode_pt = L1_S_C; 6223 pte_l2_l_cache_mode_pt = L2_C; 6224 pte_l2_s_cache_mode_pt = L2_C; 6225 } 6226 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6227 6228 #if ARM_MMU_SA1 == 1 6229 void 6230 pmap_pte_init_sa1(void) 6231 { 6232 6233 /* 6234 * The StrongARM SA-1 cache does not have a write-through 6235 * mode. So, do the generic initialization, then reset 6236 * the page table cache mode to B=1,C=1, and note that 6237 * the PTEs need to be sync'd. 6238 */ 6239 pmap_pte_init_generic(); 6240 6241 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6242 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6243 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6244 6245 pmap_needs_pte_sync = 1; 6246 } 6247 #endif /* ARM_MMU_SA1 == 1*/ 6248 6249 #if ARM_MMU_XSCALE == 1 6250 #if (ARM_NMMUS > 1) 6251 static u_int xscale_use_minidata; 6252 #endif 6253 6254 void 6255 pmap_pte_init_xscale(void) 6256 { 6257 uint32_t auxctl; 6258 int write_through = 0; 6259 6260 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6261 pte_l1_s_wc_mode = L1_S_B; 6262 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6263 6264 pte_l2_l_cache_mode = L2_B|L2_C; 6265 pte_l2_l_wc_mode = L2_B; 6266 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6267 6268 pte_l2_s_cache_mode = L2_B|L2_C; 6269 pte_l2_s_wc_mode = L2_B; 6270 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6271 6272 pte_l1_s_cache_mode_pt = L1_S_C; 6273 pte_l2_l_cache_mode_pt = L2_C; 6274 pte_l2_s_cache_mode_pt = L2_C; 6275 6276 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6277 /* 6278 * The XScale core has an enhanced mode where writes that 6279 * miss the cache cause a cache line to be allocated. This 6280 * is significantly faster than the traditional, write-through 6281 * behavior of this case. 6282 */ 6283 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6284 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6285 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6286 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6287 6288 #ifdef XSCALE_CACHE_WRITE_THROUGH 6289 /* 6290 * Some versions of the XScale core have various bugs in 6291 * their cache units, the work-around for which is to run 6292 * the cache in write-through mode. Unfortunately, this 6293 * has a major (negative) impact on performance. So, we 6294 * go ahead and run fast-and-loose, in the hopes that we 6295 * don't line up the planets in a way that will trip the 6296 * bugs. 6297 * 6298 * However, we give you the option to be slow-but-correct. 6299 */ 6300 write_through = 1; 6301 #elif defined(XSCALE_CACHE_WRITE_BACK) 6302 /* force write back cache mode */ 6303 write_through = 0; 6304 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6305 /* 6306 * Intel PXA2[15]0 processors are known to have a bug in 6307 * write-back cache on revision 4 and earlier (stepping 6308 * A[01] and B[012]). Fixed for C0 and later. 6309 */ 6310 { 6311 uint32_t id, type; 6312 6313 id = cpufunc_id(); 6314 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6315 6316 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6317 if ((id & CPU_ID_REVISION_MASK) < 5) { 6318 /* write through for stepping A0-1 and B0-2 */ 6319 write_through = 1; 6320 } 6321 } 6322 } 6323 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6324 6325 if (write_through) { 6326 pte_l1_s_cache_mode = L1_S_C; 6327 pte_l2_l_cache_mode = L2_C; 6328 pte_l2_s_cache_mode = L2_C; 6329 } 6330 6331 #if (ARM_NMMUS > 1) 6332 xscale_use_minidata = 1; 6333 #endif 6334 6335 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6336 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6337 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6338 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6339 6340 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6341 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6342 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6343 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6344 6345 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6346 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6347 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6348 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6349 6350 pte_l1_ss_proto = L1_SS_PROTO_xscale; 6351 pte_l1_s_proto = L1_S_PROTO_xscale; 6352 pte_l1_c_proto = L1_C_PROTO_xscale; 6353 pte_l2_s_proto = L2_S_PROTO_xscale; 6354 6355 pmap_copy_page_func = pmap_copy_page_xscale; 6356 pmap_zero_page_func = pmap_zero_page_xscale; 6357 6358 /* 6359 * Disable ECC protection of page table access, for now. 6360 */ 6361 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6362 auxctl &= ~XSCALE_AUXCTL_P; 6363 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6364 } 6365 6366 /* 6367 * xscale_setup_minidata: 6368 * 6369 * Set up the mini-data cache clean area. We require the 6370 * caller to allocate the right amount of physically and 6371 * virtually contiguous space. 6372 */ 6373 void 6374 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6375 { 6376 extern vaddr_t xscale_minidata_clean_addr; 6377 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6378 pd_entry_t *pde = (pd_entry_t *) l1pt; 6379 vsize_t size; 6380 uint32_t auxctl; 6381 6382 xscale_minidata_clean_addr = va; 6383 6384 /* Round it to page size. */ 6385 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6386 6387 for (; size != 0; 6388 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6389 const size_t l1idx = L1_IDX(va); 6390 #ifndef ARM32_NEW_VM_LAYOUT 6391 pt_entry_t *ptep = (pt_entry_t *) 6392 kernel_pt_lookup(pde[l1idx] & L2_S_FRAME); 6393 #else 6394 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup( 6395 pde[l1idx] & L1_C_ADDR_MASK); 6396 #endif 6397 if (ptep == NULL) 6398 panic("xscale_setup_minidata: can't find L2 table for " 6399 "VA 0x%08lx", va); 6400 6401 #ifndef ARM32_NEW_VM_LAYOUT 6402 ptep += (va >> PGSHIFT) & 0x3ff; 6403 #else 6404 ptep += l2pte_index(va); 6405 #endif 6406 pt_entry_t opte = *ptep; 6407 l2pte_set(ptep, 6408 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 6409 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 6410 } 6411 6412 /* 6413 * Configure the mini-data cache for write-back with 6414 * read/write-allocate. 6415 * 6416 * NOTE: In order to reconfigure the mini-data cache, we must 6417 * make sure it contains no valid data! In order to do that, 6418 * we must issue a global data cache invalidate command! 6419 * 6420 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6421 * THIS IS VERY IMPORTANT! 6422 */ 6423 6424 /* Invalidate data and mini-data. */ 6425 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6426 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6427 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6428 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6429 } 6430 6431 /* 6432 * Change the PTEs for the specified kernel mappings such that they 6433 * will use the mini data cache instead of the main data cache. 6434 */ 6435 void 6436 pmap_uarea(vaddr_t va) 6437 { 6438 vaddr_t next_bucket, eva; 6439 6440 #if (ARM_NMMUS > 1) 6441 if (xscale_use_minidata == 0) 6442 return; 6443 #endif 6444 6445 eva = va + USPACE; 6446 6447 while (va < eva) { 6448 next_bucket = L2_NEXT_BUCKET(va); 6449 if (next_bucket > eva) 6450 next_bucket = eva; 6451 6452 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6453 KDASSERT(l2b != NULL); 6454 6455 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 6456 pt_entry_t *ptep = sptep; 6457 6458 while (va < next_bucket) { 6459 const pt_entry_t opte = *ptep; 6460 if (!l2pte_minidata(opte)) { 6461 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6462 cpu_tlb_flushD_SE(va); 6463 l2pte_set(ptep, opte & ~L2_B, opte); 6464 } 6465 ptep += PAGE_SIZE / L2_S_SIZE; 6466 va += PAGE_SIZE; 6467 } 6468 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6469 } 6470 cpu_cpwait(); 6471 } 6472 #endif /* ARM_MMU_XSCALE == 1 */ 6473 6474 6475 #if defined(CPU_ARM11MPCORE) 6476 6477 void 6478 pmap_pte_init_arm11mpcore(void) 6479 { 6480 6481 /* cache mode is controlled by 5 bits (B, C, TEX) */ 6482 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 6483 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 6484 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6485 /* use extended small page (without APn, with TEX) */ 6486 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 6487 #else 6488 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 6489 #endif 6490 6491 /* write-back, write-allocate */ 6492 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6493 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 6494 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6495 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6496 #else 6497 /* no TEX. read-allocate */ 6498 pte_l2_s_cache_mode = L2_C | L2_B; 6499 #endif 6500 /* 6501 * write-back, write-allocate for page tables. 6502 */ 6503 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6504 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 6505 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6506 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6507 #else 6508 pte_l2_s_cache_mode_pt = L2_C | L2_B; 6509 #endif 6510 6511 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 6512 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 6513 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 6514 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 6515 6516 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6517 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 6518 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 6519 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 6520 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 6521 6522 #else 6523 /* with AP[0..3] */ 6524 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6525 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6526 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6527 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6528 #endif 6529 6530 #ifdef ARM11MPCORE_COMPAT_MMU 6531 /* with AP[0..3] */ 6532 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6533 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6534 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6535 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6536 6537 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6538 pte_l1_s_proto = L1_S_PROTO_armv6; 6539 pte_l1_c_proto = L1_C_PROTO_armv6; 6540 pte_l2_s_proto = L2_S_PROTO_armv6c; 6541 #else 6542 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 6543 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 6544 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 6545 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 6546 6547 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6548 pte_l1_s_proto = L1_S_PROTO_armv6; 6549 pte_l1_c_proto = L1_C_PROTO_armv6; 6550 pte_l2_s_proto = L2_S_PROTO_armv6n; 6551 #endif 6552 6553 pmap_copy_page_func = pmap_copy_page_generic; 6554 pmap_zero_page_func = pmap_zero_page_generic; 6555 pmap_needs_pte_sync = 1; 6556 } 6557 #endif /* CPU_ARM11MPCORE */ 6558 6559 6560 #if ARM_MMU_V7 == 1 6561 void 6562 pmap_pte_init_armv7(void) 6563 { 6564 /* 6565 * The ARMv7-A MMU is mostly compatible with generic. If the 6566 * AP field is zero, that now means "no access" rather than 6567 * read-only. The prototypes are a little different because of 6568 * the XN bit. 6569 */ 6570 pmap_pte_init_generic(); 6571 6572 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6573 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6574 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6575 6576 if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) { 6577 /* 6578 * write-back, no write-allocate, shareable for normal pages. 6579 */ 6580 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_S; 6581 pte_l2_l_cache_mode = L2_C | L2_B | L2_XS_S; 6582 pte_l2_s_cache_mode = L2_C | L2_B | L2_XS_S; 6583 6584 /* 6585 * write-back, no write-allocate, shareable for page tables. 6586 */ 6587 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_S; 6588 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6589 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6590 } 6591 6592 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6593 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6594 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6595 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6596 6597 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6598 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6599 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6600 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6601 6602 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6603 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6604 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6605 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6606 6607 pte_l1_ss_proto = L1_SS_PROTO_armv7; 6608 pte_l1_s_proto = L1_S_PROTO_armv7; 6609 pte_l1_c_proto = L1_C_PROTO_armv7; 6610 pte_l2_s_proto = L2_S_PROTO_armv7; 6611 6612 pmap_needs_pte_sync = 1; 6613 } 6614 #endif /* ARM_MMU_V7 */ 6615 6616 /* 6617 * return the PA of the current L1 table, for use when handling a crash dump 6618 */ 6619 uint32_t pmap_kernel_L1_addr(void) 6620 { 6621 return pmap_kernel()->pm_l1->l1_physaddr; 6622 } 6623 6624 #if defined(DDB) 6625 /* 6626 * A couple of ddb-callable functions for dumping pmaps 6627 */ 6628 void pmap_dump_all(void); 6629 void pmap_dump(pmap_t); 6630 6631 void 6632 pmap_dump_all(void) 6633 { 6634 pmap_t pm; 6635 6636 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6637 if (pm == pmap_kernel()) 6638 continue; 6639 pmap_dump(pm); 6640 printf("\n"); 6641 } 6642 } 6643 6644 static pt_entry_t ncptes[64]; 6645 static void pmap_dump_ncpg(pmap_t); 6646 6647 void 6648 pmap_dump(pmap_t pm) 6649 { 6650 struct l2_dtable *l2; 6651 struct l2_bucket *l2b; 6652 pt_entry_t *ptep, pte; 6653 vaddr_t l2_va, l2b_va, va; 6654 int i, j, k, occ, rows = 0; 6655 6656 if (pm == pmap_kernel()) 6657 printf("pmap_kernel (%p): ", pm); 6658 else 6659 printf("user pmap (%p): ", pm); 6660 6661 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 6662 6663 l2_va = 0; 6664 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6665 l2 = pm->pm_l2[i]; 6666 6667 if (l2 == NULL || l2->l2_occupancy == 0) 6668 continue; 6669 6670 l2b_va = l2_va; 6671 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6672 l2b = &l2->l2_bucket[j]; 6673 6674 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6675 continue; 6676 6677 ptep = l2b->l2b_kva; 6678 6679 for (k = 0; k < 256 && ptep[k] == 0; k++) 6680 ; 6681 6682 k &= ~63; 6683 occ = l2b->l2b_occupancy; 6684 va = l2b_va + (k * 4096); 6685 for (; k < 256; k++, va += 0x1000) { 6686 char ch = ' '; 6687 if ((k % 64) == 0) { 6688 if ((rows % 8) == 0) { 6689 printf( 6690 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6691 } 6692 printf("%08lx: ", va); 6693 } 6694 6695 ncptes[k & 63] = 0; 6696 pte = ptep[k]; 6697 if (pte == 0) { 6698 ch = '.'; 6699 } else { 6700 occ--; 6701 switch (pte & 0x0c) { 6702 case 0x00: 6703 ch = 'D'; /* No cache No buff */ 6704 break; 6705 case 0x04: 6706 ch = 'B'; /* No cache buff */ 6707 break; 6708 case 0x08: 6709 if (pte & 0x40) 6710 ch = 'm'; 6711 else 6712 ch = 'C'; /* Cache No buff */ 6713 break; 6714 case 0x0c: 6715 ch = 'F'; /* Cache Buff */ 6716 break; 6717 } 6718 6719 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6720 ch += 0x20; 6721 6722 if ((pte & 0xc) == 0) 6723 ncptes[k & 63] = pte; 6724 } 6725 6726 if ((k % 64) == 63) { 6727 rows++; 6728 printf("%c\n", ch); 6729 pmap_dump_ncpg(pm); 6730 if (occ == 0) 6731 break; 6732 } else 6733 printf("%c", ch); 6734 } 6735 } 6736 } 6737 } 6738 6739 static void 6740 pmap_dump_ncpg(pmap_t pm) 6741 { 6742 struct vm_page *pg; 6743 struct vm_page_md *md; 6744 struct pv_entry *pv; 6745 int i; 6746 6747 for (i = 0; i < 63; i++) { 6748 if (ncptes[i] == 0) 6749 continue; 6750 6751 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6752 if (pg == NULL) 6753 continue; 6754 md = VM_PAGE_TO_MD(pg); 6755 6756 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6757 VM_PAGE_TO_PHYS(pg), 6758 md->krw_mappings, md->kro_mappings, 6759 md->urw_mappings, md->uro_mappings); 6760 6761 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6762 printf(" %c va 0x%08lx, flags 0x%x\n", 6763 (pm == pv->pv_pmap) ? '*' : ' ', 6764 pv->pv_va, pv->pv_flags); 6765 } 6766 } 6767 } 6768 #endif 6769 6770 #ifdef PMAP_STEAL_MEMORY 6771 void 6772 pmap_boot_pageadd(pv_addr_t *newpv) 6773 { 6774 pv_addr_t *pv, *npv; 6775 6776 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6777 if (newpv->pv_pa < pv->pv_va) { 6778 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6779 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6780 newpv->pv_size += pv->pv_size; 6781 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6782 } 6783 pv = NULL; 6784 } else { 6785 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6786 pv = npv) { 6787 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6788 KASSERT(pv->pv_pa < newpv->pv_pa); 6789 if (newpv->pv_pa > npv->pv_pa) 6790 continue; 6791 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6792 pv->pv_size += newpv->pv_size; 6793 return; 6794 } 6795 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6796 break; 6797 newpv->pv_size += npv->pv_size; 6798 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6799 SLIST_REMOVE_AFTER(newpv, pv_list); 6800 return; 6801 } 6802 } 6803 } 6804 6805 if (pv) { 6806 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6807 } else { 6808 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6809 } 6810 } 6811 6812 void 6813 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6814 pv_addr_t *rpv) 6815 { 6816 pv_addr_t *pv, **pvp; 6817 struct vm_physseg *ps; 6818 size_t i; 6819 6820 KASSERT(amount & PGOFSET); 6821 KASSERT((mask & PGOFSET) == 0); 6822 KASSERT((match & PGOFSET) == 0); 6823 KASSERT(amount != 0); 6824 6825 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6826 (pv = *pvp) != NULL; 6827 pvp = &SLIST_NEXT(pv, pv_list)) { 6828 pv_addr_t *newpv; 6829 psize_t off; 6830 /* 6831 * If this entry is too small to satify the request... 6832 */ 6833 KASSERT(pv->pv_size > 0); 6834 if (pv->pv_size < amount) 6835 continue; 6836 6837 for (off = 0; off <= mask; off += PAGE_SIZE) { 6838 if (((pv->pv_pa + off) & mask) == match 6839 && off + amount <= pv->pv_size) 6840 break; 6841 } 6842 if (off > mask) 6843 continue; 6844 6845 rpv->pv_va = pv->pv_va + off; 6846 rpv->pv_pa = pv->pv_pa + off; 6847 rpv->pv_size = amount; 6848 pv->pv_size -= amount; 6849 if (pv->pv_size == 0) { 6850 KASSERT(off == 0); 6851 KASSERT((vaddr_t) pv == rpv->pv_va); 6852 *pvp = SLIST_NEXT(pv, pv_list); 6853 } else if (off == 0) { 6854 KASSERT((vaddr_t) pv == rpv->pv_va); 6855 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6856 *newpv = *pv; 6857 newpv->pv_pa += amount; 6858 newpv->pv_va += amount; 6859 *pvp = newpv; 6860 } else if (off < pv->pv_size) { 6861 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6862 *newpv = *pv; 6863 newpv->pv_size -= off; 6864 newpv->pv_pa += off + amount; 6865 newpv->pv_va += off + amount; 6866 6867 SLIST_NEXT(pv, pv_list) = newpv; 6868 pv->pv_size = off; 6869 } else { 6870 KASSERT((vaddr_t) pv != rpv->pv_va); 6871 } 6872 memset((void *)rpv->pv_va, 0, amount); 6873 return; 6874 } 6875 6876 if (vm_nphysseg == 0) 6877 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6878 6879 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6880 (pv = *pvp) != NULL; 6881 pvp = &SLIST_NEXT(pv, pv_list)) { 6882 if (SLIST_NEXT(pv, pv_list) == NULL) 6883 break; 6884 } 6885 KASSERT(mask == 0); 6886 for (i = 0; i < vm_nphysseg; i++) { 6887 ps = VM_PHYSMEM_PTR(i); 6888 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6889 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6890 rpv->pv_va = pv->pv_va; 6891 rpv->pv_pa = pv->pv_pa; 6892 rpv->pv_size = amount; 6893 *pvp = NULL; 6894 pmap_map_chunk(kernel_l1pt.pv_va, 6895 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6896 ptoa(ps->avail_start), 6897 amount - pv->pv_size, 6898 VM_PROT_READ|VM_PROT_WRITE, 6899 PTE_CACHE); 6900 ps->avail_start += atop(amount - pv->pv_size); 6901 /* 6902 * If we consumed the entire physseg, remove it. 6903 */ 6904 if (ps->avail_start == ps->avail_end) { 6905 for (--vm_nphysseg; i < vm_nphysseg; i++) 6906 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6907 } 6908 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6909 return; 6910 } 6911 } 6912 6913 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6914 } 6915 6916 vaddr_t 6917 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6918 { 6919 pv_addr_t pv; 6920 6921 pmap_boot_pagealloc(size, 0, 0, &pv); 6922 6923 return pv.pv_va; 6924 } 6925 #endif /* PMAP_STEAL_MEMORY */ 6926 6927 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6928 { 6929 sysctl_createv(clog, 0, NULL, NULL, 6930 CTLFLAG_PERMANENT, 6931 CTLTYPE_NODE, "machdep", NULL, 6932 NULL, 0, NULL, 0, 6933 CTL_MACHDEP, CTL_EOL); 6934 6935 sysctl_createv(clog, 0, NULL, NULL, 6936 CTLFLAG_PERMANENT, 6937 CTLTYPE_INT, "kmpages", 6938 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6939 NULL, 0, &pmap_kmpages, 0, 6940 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6941 } 6942 6943 #ifdef PMAP_NEED_ALLOC_POOLPAGE 6944 struct vm_page * 6945 arm_pmap_alloc_poolpage(int flags) 6946 { 6947 /* 6948 * On some systems, only some pages may be "coherent" for dma and we 6949 * want to prefer those for pool pages (think mbufs) but fallback to 6950 * any page if none is available. 6951 */ 6952 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 6953 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 6954 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 6955 } 6956 6957 return uvm_pagealloc(NULL, 0, NULL, flags); 6958 } 6959 #endif 6960
Indexes created Mon Sep 29 21:09:56 GMT 2025