pmap.c revision 1.265
1 /* $NetBSD: pmap.c,v 1.265 2014/02/26 01:41:40 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/pool.h> 201 #include <sys/kmem.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 #include <sys/bus.h> 206 207 #include <uvm/uvm.h> 208 209 #include <arm/locore.h> 210 #include <arm/arm32/katelib.h> 211 212 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.265 2014/02/26 01:41:40 matt Exp $"); 213 214 #ifdef PMAP_DEBUG 215 216 /* XXX need to get rid of all refs to this */ 217 int pmap_debug_level = 0; 218 219 /* 220 * for switching to potentially finer grained debugging 221 */ 222 #define PDB_FOLLOW 0x0001 223 #define PDB_INIT 0x0002 224 #define PDB_ENTER 0x0004 225 #define PDB_REMOVE 0x0008 226 #define PDB_CREATE 0x0010 227 #define PDB_PTPAGE 0x0020 228 #define PDB_GROWKERN 0x0040 229 #define PDB_BITS 0x0080 230 #define PDB_COLLECT 0x0100 231 #define PDB_PROTECT 0x0200 232 #define PDB_MAP_L1 0x0400 233 #define PDB_BOOTSTRAP 0x1000 234 #define PDB_PARANOIA 0x2000 235 #define PDB_WIRING 0x4000 236 #define PDB_PVDUMP 0x8000 237 #define PDB_VAC 0x10000 238 #define PDB_KENTER 0x20000 239 #define PDB_KREMOVE 0x40000 240 #define PDB_EXEC 0x80000 241 242 int debugmap = 1; 243 int pmapdebug = 0; 244 #define NPDEBUG(_lev_,_stat_) \ 245 if (pmapdebug & (_lev_)) \ 246 ((_stat_)) 247 248 #else /* PMAP_DEBUG */ 249 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 250 #endif /* PMAP_DEBUG */ 251 252 /* 253 * pmap_kernel() points here 254 */ 255 static struct pmap kernel_pmap_store; 256 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 257 #ifdef PMAP_NEED_ALLOC_POOLPAGE 258 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 259 #endif 260 261 /* 262 * Which pmap is currently 'live' in the cache 263 * 264 * XXXSCW: Fix for SMP ... 265 */ 266 static pmap_t pmap_recent_user; 267 268 /* 269 * Pointer to last active lwp, or NULL if it exited. 270 */ 271 struct lwp *pmap_previous_active_lwp; 272 273 /* 274 * Pool and cache that pmap structures are allocated from. 275 * We use a cache to avoid clearing the pm_l2[] array (1KB) 276 * in pmap_create(). 277 */ 278 static struct pool_cache pmap_cache; 279 static LIST_HEAD(, pmap) pmap_pmaps; 280 281 /* 282 * Pool of PV structures 283 */ 284 static struct pool pmap_pv_pool; 285 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 286 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 287 static struct pool_allocator pmap_bootstrap_pv_allocator = { 288 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 289 }; 290 291 /* 292 * Pool and cache of l2_dtable structures. 293 * We use a cache to avoid clearing the structures when they're 294 * allocated. (196 bytes) 295 */ 296 static struct pool_cache pmap_l2dtable_cache; 297 static vaddr_t pmap_kernel_l2dtable_kva; 298 299 /* 300 * Pool and cache of L2 page descriptors. 301 * We use a cache to avoid clearing the descriptor table 302 * when they're allocated. (1KB) 303 */ 304 static struct pool_cache pmap_l2ptp_cache; 305 static vaddr_t pmap_kernel_l2ptp_kva; 306 static paddr_t pmap_kernel_l2ptp_phys; 307 308 #ifdef PMAPCOUNTERS 309 #define PMAP_EVCNT_INITIALIZER(name) \ 310 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 311 312 #ifdef PMAP_CACHE_VIPT 313 static struct evcnt pmap_ev_vac_clean_one = 314 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 315 static struct evcnt pmap_ev_vac_flush_one = 316 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 317 static struct evcnt pmap_ev_vac_flush_lots = 318 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 319 static struct evcnt pmap_ev_vac_flush_lots2 = 320 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 325 326 static struct evcnt pmap_ev_vac_color_new = 327 PMAP_EVCNT_INITIALIZER("new page color"); 328 static struct evcnt pmap_ev_vac_color_reuse = 329 PMAP_EVCNT_INITIALIZER("ok first page color"); 330 static struct evcnt pmap_ev_vac_color_ok = 331 PMAP_EVCNT_INITIALIZER("ok page color"); 332 static struct evcnt pmap_ev_vac_color_blind = 333 PMAP_EVCNT_INITIALIZER("blind page color"); 334 static struct evcnt pmap_ev_vac_color_change = 335 PMAP_EVCNT_INITIALIZER("change page color"); 336 static struct evcnt pmap_ev_vac_color_erase = 337 PMAP_EVCNT_INITIALIZER("erase page color"); 338 static struct evcnt pmap_ev_vac_color_none = 339 PMAP_EVCNT_INITIALIZER("no page color"); 340 static struct evcnt pmap_ev_vac_color_restore = 341 PMAP_EVCNT_INITIALIZER("restore page color"); 342 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 351 #endif 352 353 static struct evcnt pmap_ev_mappings = 354 PMAP_EVCNT_INITIALIZER("pages mapped"); 355 static struct evcnt pmap_ev_unmappings = 356 PMAP_EVCNT_INITIALIZER("pages unmapped"); 357 static struct evcnt pmap_ev_remappings = 358 PMAP_EVCNT_INITIALIZER("pages remapped"); 359 360 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 362 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 363 364 static struct evcnt pmap_ev_kernel_mappings = 365 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 366 static struct evcnt pmap_ev_kernel_unmappings = 367 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 368 static struct evcnt pmap_ev_kernel_remappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 370 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 373 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 374 375 static struct evcnt pmap_ev_kenter_mappings = 376 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 377 static struct evcnt pmap_ev_kenter_unmappings = 378 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 379 static struct evcnt pmap_ev_kenter_remappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 381 static struct evcnt pmap_ev_pt_mappings = 382 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 383 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 387 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 388 389 #ifdef PMAP_CACHE_VIPT 390 static struct evcnt pmap_ev_exec_mappings = 391 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 392 static struct evcnt pmap_ev_exec_cached = 393 PMAP_EVCNT_INITIALIZER("exec pages cached"); 394 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 396 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 397 398 static struct evcnt pmap_ev_exec_synced = 399 PMAP_EVCNT_INITIALIZER("exec pages synced"); 400 static struct evcnt pmap_ev_exec_synced_map = 401 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 402 static struct evcnt pmap_ev_exec_synced_unmap = 403 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 404 static struct evcnt pmap_ev_exec_synced_remap = 405 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 406 static struct evcnt pmap_ev_exec_synced_clearbit = 407 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 408 static struct evcnt pmap_ev_exec_synced_kremove = 409 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 410 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 416 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 417 418 static struct evcnt pmap_ev_exec_discarded_unmap = 419 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 420 static struct evcnt pmap_ev_exec_discarded_zero = 421 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 422 static struct evcnt pmap_ev_exec_discarded_copy = 423 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 424 static struct evcnt pmap_ev_exec_discarded_page_protect = 425 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 426 static struct evcnt pmap_ev_exec_discarded_clearbit = 427 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 428 static struct evcnt pmap_ev_exec_discarded_kremove = 429 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 430 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 437 #endif /* PMAP_CACHE_VIPT */ 438 439 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 440 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 441 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 442 443 EVCNT_ATTACH_STATIC(pmap_ev_updates); 444 EVCNT_ATTACH_STATIC(pmap_ev_collects); 445 EVCNT_ATTACH_STATIC(pmap_ev_activations); 446 447 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 448 #else 449 #define PMAPCOUNT(x) ((void)0) 450 #endif 451 452 /* 453 * pmap copy/zero page, and mem(5) hook point 454 */ 455 static pt_entry_t *csrc_pte, *cdst_pte; 456 static vaddr_t csrcp, cdstp; 457 vaddr_t memhook; /* used by mem.c */ 458 kmutex_t memlock; /* used by mem.c */ 459 void *zeropage; /* used by mem.c */ 460 extern void *msgbufaddr; 461 int pmap_kmpages; 462 /* 463 * Flag to indicate if pmap_init() has done its thing 464 */ 465 bool pmap_initialized; 466 467 /* 468 * Misc. locking data structures 469 */ 470 471 #define pmap_acquire_pmap_lock(pm) \ 472 do { \ 473 if ((pm) != pmap_kernel()) \ 474 mutex_enter((pm)->pm_lock); \ 475 } while (/*CONSTCOND*/0) 476 477 #define pmap_release_pmap_lock(pm) \ 478 do { \ 479 if ((pm) != pmap_kernel()) \ 480 mutex_exit((pm)->pm_lock); \ 481 } while (/*CONSTCOND*/0) 482 483 484 /* 485 * Metadata for L1 translation tables. 486 */ 487 struct l1_ttable { 488 /* Entry on the L1 Table list */ 489 SLIST_ENTRY(l1_ttable) l1_link; 490 491 /* Entry on the L1 Least Recently Used list */ 492 TAILQ_ENTRY(l1_ttable) l1_lru; 493 494 /* Track how many domains are allocated from this L1 */ 495 volatile u_int l1_domain_use_count; 496 497 /* 498 * A free-list of domain numbers for this L1. 499 * We avoid using ffs() and a bitmap to track domains since ffs() 500 * is slow on ARM. 501 */ 502 uint8_t l1_domain_first; 503 uint8_t l1_domain_free[PMAP_DOMAINS]; 504 505 /* Physical address of this L1 page table */ 506 paddr_t l1_physaddr; 507 508 /* KVA of this L1 page table */ 509 pd_entry_t *l1_kva; 510 }; 511 512 /* 513 * Convert a virtual address into its L1 table index. That is, the 514 * index used to locate the L2 descriptor table pointer in an L1 table. 515 * This is basically used to index l1->l1_kva[]. 516 * 517 * Each L2 descriptor table represents 1MB of VA space. 518 */ 519 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 520 521 /* 522 * L1 Page Tables are tracked using a Least Recently Used list. 523 * - New L1s are allocated from the HEAD. 524 * - Freed L1s are added to the TAIl. 525 * - Recently accessed L1s (where an 'access' is some change to one of 526 * the userland pmaps which owns this L1) are moved to the TAIL. 527 */ 528 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 529 static kmutex_t l1_lru_lock __cacheline_aligned; 530 531 /* 532 * A list of all L1 tables 533 */ 534 static SLIST_HEAD(, l1_ttable) l1_list; 535 536 /* 537 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 538 * 539 * This is normally 16MB worth L2 page descriptors for any given pmap. 540 * Reference counts are maintained for L2 descriptors so they can be 541 * freed when empty. 542 */ 543 struct l2_dtable { 544 /* The number of L2 page descriptors allocated to this l2_dtable */ 545 u_int l2_occupancy; 546 547 /* List of L2 page descriptors */ 548 struct l2_bucket { 549 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 550 paddr_t l2b_phys; /* Physical address of same */ 551 u_short l2b_l1idx; /* This L2 table's L1 index */ 552 u_short l2b_occupancy; /* How many active descriptors */ 553 } l2_bucket[L2_BUCKET_SIZE]; 554 }; 555 556 /* 557 * Given an L1 table index, calculate the corresponding l2_dtable index 558 * and bucket index within the l2_dtable. 559 */ 560 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 561 (L2_SIZE - 1)) 562 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 563 564 /* 565 * Given a virtual address, this macro returns the 566 * virtual address required to drop into the next L2 bucket. 567 */ 568 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 569 570 /* 571 * L2 allocation. 572 */ 573 #define pmap_alloc_l2_dtable() \ 574 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 575 #define pmap_free_l2_dtable(l2) \ 576 pool_cache_put(&pmap_l2dtable_cache, (l2)) 577 #define pmap_alloc_l2_ptp(pap) \ 578 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 579 PR_NOWAIT, (pap))) 580 581 /* 582 * We try to map the page tables write-through, if possible. However, not 583 * all CPUs have a write-through cache mode, so on those we have to sync 584 * the cache when we frob page tables. 585 * 586 * We try to evaluate this at compile time, if possible. However, it's 587 * not always possible to do that, hence this run-time var. 588 */ 589 int pmap_needs_pte_sync; 590 591 /* 592 * Real definition of pv_entry. 593 */ 594 struct pv_entry { 595 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 596 pmap_t pv_pmap; /* pmap where mapping lies */ 597 vaddr_t pv_va; /* virtual address for mapping */ 598 u_int pv_flags; /* flags */ 599 }; 600 601 /* 602 * Macro to determine if a mapping might be resident in the 603 * instruction cache and/or TLB 604 */ 605 #if ARM_MMU_V7 > 0 606 /* 607 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 608 * there are no explicit accesses, so there may be always be TLB entries to 609 * flush. If we used ASIDs then this would not be a problem. 610 */ 611 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 612 #else 613 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 614 #endif 615 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 616 617 /* 618 * Macro to determine if a mapping might be resident in the 619 * data cache and/or TLB 620 */ 621 #if ARM_MMU_V7 > 0 622 /* 623 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 624 * there are no explicit accesses, so there may be always be TLB entries to 625 * flush. If we used ASIDs then this would not be a problem. 626 */ 627 #define PV_BEEN_REFD(f) (1) 628 #else 629 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 630 #endif 631 632 /* 633 * Local prototypes 634 */ 635 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 636 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 637 pt_entry_t **); 638 static bool pmap_is_current(pmap_t); 639 static bool pmap_is_cached(pmap_t); 640 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 641 pmap_t, vaddr_t, u_int); 642 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 643 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 644 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 645 u_int, u_int); 646 647 static void pmap_pinit(pmap_t); 648 static int pmap_pmap_ctor(void *, void *, int); 649 650 static void pmap_alloc_l1(pmap_t); 651 static void pmap_free_l1(pmap_t); 652 static void pmap_use_l1(pmap_t); 653 654 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 655 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 656 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 657 static int pmap_l2ptp_ctor(void *, void *, int); 658 static int pmap_l2dtable_ctor(void *, void *, int); 659 660 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 661 #ifdef PMAP_CACHE_VIVT 662 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 663 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 664 #endif 665 666 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 667 #ifdef PMAP_CACHE_VIVT 668 static int pmap_clean_page(struct pv_entry *, bool); 669 #endif 670 #ifdef PMAP_CACHE_VIPT 671 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 672 enum pmap_flush_op { 673 PMAP_FLUSH_PRIMARY, 674 PMAP_FLUSH_SECONDARY, 675 PMAP_CLEAN_PRIMARY 676 }; 677 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 678 #endif 679 static void pmap_page_remove(struct vm_page_md *, paddr_t); 680 681 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 682 static vaddr_t kernel_pt_lookup(paddr_t); 683 684 685 /* 686 * Misc variables 687 */ 688 vaddr_t virtual_avail; 689 vaddr_t virtual_end; 690 vaddr_t pmap_curmaxkvaddr; 691 692 paddr_t avail_start; 693 paddr_t avail_end; 694 695 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 696 pv_addr_t kernelpages; 697 pv_addr_t kernel_l1pt; 698 pv_addr_t systempage; 699 700 /* Function to set the debug level of the pmap code */ 701 702 #ifdef PMAP_DEBUG 703 void 704 pmap_debug(int level) 705 { 706 pmap_debug_level = level; 707 printf("pmap_debug: level=%d\n", pmap_debug_level); 708 } 709 #endif /* PMAP_DEBUG */ 710 711 #ifdef PMAP_CACHE_VIPT 712 #define PMAP_VALIDATE_MD_PAGE(md) \ 713 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 714 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 715 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 716 #endif /* PMAP_CACHE_VIPT */ 717 /* 718 * A bunch of routines to conditionally flush the caches/TLB depending 719 * on whether the specified pmap actually needs to be flushed at any 720 * given time. 721 */ 722 static inline void 723 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 724 { 725 if (pm->pm_cstate.cs_tlb_id != 0) { 726 if (PV_BEEN_EXECD(flags)) { 727 cpu_tlb_flushID_SE(va); 728 } else if (PV_BEEN_REFD(flags)) { 729 cpu_tlb_flushD_SE(va); 730 } 731 } 732 } 733 734 static inline void 735 pmap_tlb_flushID(pmap_t pm) 736 { 737 if (pm->pm_cstate.cs_tlb_id) { 738 cpu_tlb_flushID(); 739 #if ARM_MMU_V7 == 0 740 /* 741 * Speculative loads by Cortex cores can cause TLB entries to 742 * be filled even if there are no explicit accesses, so there 743 * may be always be TLB entries to flush. If we used ASIDs 744 * then it would not be a problem. 745 * This is not true for other CPUs. 746 */ 747 pm->pm_cstate.cs_tlb = 0; 748 #endif /* ARM_MMU_V7 */ 749 } 750 } 751 752 static inline void 753 pmap_tlb_flushD(pmap_t pm) 754 { 755 if (pm->pm_cstate.cs_tlb_d) { 756 cpu_tlb_flushD(); 757 #if ARM_MMU_V7 == 0 758 /* 759 * Speculative loads by Cortex cores can cause TLB entries to 760 * be filled even if there are no explicit accesses, so there 761 * may be always be TLB entries to flush. If we used ASIDs 762 * then it would not be a problem. 763 * This is not true for other CPUs. 764 */ 765 pm->pm_cstate.cs_tlb_d = 0; 766 #endif /* ARM_MMU_V7 */ 767 } 768 } 769 770 #ifdef PMAP_CACHE_VIVT 771 static inline void 772 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 773 { 774 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 775 cpu_idcache_wbinv_range(va, PAGE_SIZE); 776 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 777 if (do_inv) { 778 if (flags & PVF_WRITE) 779 cpu_dcache_wbinv_range(va, PAGE_SIZE); 780 else 781 cpu_dcache_inv_range(va, PAGE_SIZE); 782 } else if (flags & PVF_WRITE) { 783 cpu_dcache_wb_range(va, PAGE_SIZE); 784 } 785 } 786 } 787 788 static inline void 789 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 790 { 791 if (PV_BEEN_EXECD(flags)) { 792 if (pm->pm_cstate.cs_cache_id) { 793 cpu_idcache_wbinv_all(); 794 pm->pm_cstate.cs_cache = 0; 795 } 796 } else if (pm->pm_cstate.cs_cache_d) { 797 cpu_dcache_wbinv_all(); 798 pm->pm_cstate.cs_cache_d = 0; 799 } 800 } 801 #endif /* PMAP_CACHE_VIVT */ 802 803 static inline uint8_t 804 pmap_domain(pmap_t pm) 805 { 806 return pm->pm_domain; 807 } 808 809 static inline pd_entry_t * 810 pmap_l1_kva(pmap_t pm) 811 { 812 return pm->pm_l1->l1_kva; 813 } 814 815 static inline bool 816 pmap_is_current(pmap_t pm) 817 { 818 819 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 820 return true; 821 822 return false; 823 } 824 825 static inline bool 826 pmap_is_cached(pmap_t pm) 827 { 828 829 if (pm == pmap_kernel() || pmap_recent_user == NULL || 830 pmap_recent_user == pm) 831 return (true); 832 833 return false; 834 } 835 836 /* 837 * PTE_SYNC_CURRENT: 838 * 839 * Make sure the pte is written out to RAM. 840 * We need to do this for one of two cases: 841 * - We're dealing with the kernel pmap 842 * - There is no pmap active in the cache/tlb. 843 * - The specified pmap is 'active' in the cache/tlb. 844 */ 845 #ifdef PMAP_INCLUDE_PTE_SYNC 846 #define PTE_SYNC_CURRENT(pm, ptep) \ 847 do { \ 848 if (PMAP_NEEDS_PTE_SYNC && \ 849 pmap_is_cached(pm)) \ 850 PTE_SYNC(ptep); \ 851 } while (/*CONSTCOND*/0) 852 #else 853 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 854 #endif 855 856 /* 857 * main pv_entry manipulation functions: 858 * pmap_enter_pv: enter a mapping onto a vm_page list 859 * pmap_remove_pv: remove a mapping from a vm_page list 860 * 861 * NOTE: pmap_enter_pv expects to lock the pvh itself 862 * pmap_remove_pv expects the caller to lock the pvh before calling 863 */ 864 865 /* 866 * pmap_enter_pv: enter a mapping onto a vm_page lst 867 * 868 * => caller should hold the proper lock on pmap_main_lock 869 * => caller should have pmap locked 870 * => we will gain the lock on the vm_page and allocate the new pv_entry 871 * => caller should adjust ptp's wire_count before calling 872 * => caller should not adjust pmap's wire_count 873 */ 874 static void 875 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 876 vaddr_t va, u_int flags) 877 { 878 struct pv_entry **pvp; 879 880 NPDEBUG(PDB_PVDUMP, 881 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 882 883 pv->pv_pmap = pm; 884 pv->pv_va = va; 885 pv->pv_flags = flags; 886 887 pvp = &SLIST_FIRST(&md->pvh_list); 888 #ifdef PMAP_CACHE_VIPT 889 /* 890 * Insert unmanaged entries, writeable first, at the head of 891 * the pv list. 892 */ 893 if (__predict_true((flags & PVF_KENTRY) == 0)) { 894 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 895 pvp = &SLIST_NEXT(*pvp, pv_link); 896 } else if ((flags & PVF_WRITE) == 0) { 897 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 898 pvp = &SLIST_NEXT(*pvp, pv_link); 899 } 900 #endif 901 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 902 *pvp = pv; /* ... locked list */ 903 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 904 #ifdef PMAP_CACHE_VIPT 905 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 906 md->pvh_attrs |= PVF_KMOD; 907 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 908 md->pvh_attrs |= PVF_DIRTY; 909 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 910 #endif 911 if (pm == pmap_kernel()) { 912 PMAPCOUNT(kernel_mappings); 913 if (flags & PVF_WRITE) 914 md->krw_mappings++; 915 else 916 md->kro_mappings++; 917 } else { 918 if (flags & PVF_WRITE) 919 md->urw_mappings++; 920 else 921 md->uro_mappings++; 922 } 923 924 #ifdef PMAP_CACHE_VIPT 925 /* 926 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 927 * do it here as well to keep the mappings & KVF_WRITE consistent. 928 */ 929 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 930 md->pvh_attrs |= PVF_WRITE; 931 } 932 /* 933 * If this is an exec mapping and its the first exec mapping 934 * for this page, make sure to sync the I-cache. 935 */ 936 if (PV_IS_EXEC_P(flags)) { 937 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 938 pmap_syncicache_page(md, pa); 939 PMAPCOUNT(exec_synced_map); 940 } 941 PMAPCOUNT(exec_mappings); 942 } 943 #endif 944 945 PMAPCOUNT(mappings); 946 947 if (pv->pv_flags & PVF_WIRED) 948 ++pm->pm_stats.wired_count; 949 } 950 951 /* 952 * 953 * pmap_find_pv: Find a pv entry 954 * 955 * => caller should hold lock on vm_page 956 */ 957 static inline struct pv_entry * 958 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 959 { 960 struct pv_entry *pv; 961 962 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 963 if (pm == pv->pv_pmap && va == pv->pv_va) 964 break; 965 } 966 967 return (pv); 968 } 969 970 /* 971 * pmap_remove_pv: try to remove a mapping from a pv_list 972 * 973 * => caller should hold proper lock on pmap_main_lock 974 * => pmap should be locked 975 * => caller should hold lock on vm_page [so that attrs can be adjusted] 976 * => caller should adjust ptp's wire_count and free PTP if needed 977 * => caller should NOT adjust pmap's wire_count 978 * => we return the removed pv 979 */ 980 static struct pv_entry * 981 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 982 { 983 struct pv_entry *pv, **prevptr; 984 985 NPDEBUG(PDB_PVDUMP, 986 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 987 988 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 989 pv = *prevptr; 990 991 while (pv) { 992 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 993 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 994 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 995 if (pv->pv_flags & PVF_WIRED) { 996 --pm->pm_stats.wired_count; 997 } 998 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 999 if (pm == pmap_kernel()) { 1000 PMAPCOUNT(kernel_unmappings); 1001 if (pv->pv_flags & PVF_WRITE) 1002 md->krw_mappings--; 1003 else 1004 md->kro_mappings--; 1005 } else { 1006 if (pv->pv_flags & PVF_WRITE) 1007 md->urw_mappings--; 1008 else 1009 md->uro_mappings--; 1010 } 1011 1012 PMAPCOUNT(unmappings); 1013 #ifdef PMAP_CACHE_VIPT 1014 if (!(pv->pv_flags & PVF_WRITE)) 1015 break; 1016 /* 1017 * If this page has had an exec mapping, then if 1018 * this was the last mapping, discard the contents, 1019 * otherwise sync the i-cache for this page. 1020 */ 1021 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1022 if (SLIST_EMPTY(&md->pvh_list)) { 1023 md->pvh_attrs &= ~PVF_EXEC; 1024 PMAPCOUNT(exec_discarded_unmap); 1025 } else { 1026 pmap_syncicache_page(md, pa); 1027 PMAPCOUNT(exec_synced_unmap); 1028 } 1029 } 1030 #endif /* PMAP_CACHE_VIPT */ 1031 break; 1032 } 1033 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1034 pv = *prevptr; /* advance */ 1035 } 1036 1037 #ifdef PMAP_CACHE_VIPT 1038 /* 1039 * If we no longer have a WRITEABLE KENTRY at the head of list, 1040 * clear the KMOD attribute from the page. 1041 */ 1042 if (SLIST_FIRST(&md->pvh_list) == NULL 1043 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1044 md->pvh_attrs &= ~PVF_KMOD; 1045 1046 /* 1047 * If this was a writeable page and there are no more writeable 1048 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1049 * the contents to memory. 1050 */ 1051 if (arm_cache_prefer_mask != 0) { 1052 if (md->krw_mappings + md->urw_mappings == 0) 1053 md->pvh_attrs &= ~PVF_WRITE; 1054 PMAP_VALIDATE_MD_PAGE(md); 1055 } 1056 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1057 #endif /* PMAP_CACHE_VIPT */ 1058 1059 return(pv); /* return removed pv */ 1060 } 1061 1062 /* 1063 * 1064 * pmap_modify_pv: Update pv flags 1065 * 1066 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1067 * => caller should NOT adjust pmap's wire_count 1068 * => caller must call pmap_vac_me_harder() if writable status of a page 1069 * may have changed. 1070 * => we return the old flags 1071 * 1072 * Modify a physical-virtual mapping in the pv table 1073 */ 1074 static u_int 1075 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1076 u_int clr_mask, u_int set_mask) 1077 { 1078 struct pv_entry *npv; 1079 u_int flags, oflags; 1080 1081 KASSERT((clr_mask & PVF_KENTRY) == 0); 1082 KASSERT((set_mask & PVF_KENTRY) == 0); 1083 1084 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1085 return (0); 1086 1087 NPDEBUG(PDB_PVDUMP, 1088 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1089 1090 /* 1091 * There is at least one VA mapping this page. 1092 */ 1093 1094 if (clr_mask & (PVF_REF | PVF_MOD)) { 1095 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1096 #ifdef PMAP_CACHE_VIPT 1097 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1098 md->pvh_attrs |= PVF_DIRTY; 1099 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1100 #endif 1101 } 1102 1103 oflags = npv->pv_flags; 1104 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1105 1106 if ((flags ^ oflags) & PVF_WIRED) { 1107 if (flags & PVF_WIRED) 1108 ++pm->pm_stats.wired_count; 1109 else 1110 --pm->pm_stats.wired_count; 1111 } 1112 1113 if ((flags ^ oflags) & PVF_WRITE) { 1114 if (pm == pmap_kernel()) { 1115 if (flags & PVF_WRITE) { 1116 md->krw_mappings++; 1117 md->kro_mappings--; 1118 } else { 1119 md->kro_mappings++; 1120 md->krw_mappings--; 1121 } 1122 } else { 1123 if (flags & PVF_WRITE) { 1124 md->urw_mappings++; 1125 md->uro_mappings--; 1126 } else { 1127 md->uro_mappings++; 1128 md->urw_mappings--; 1129 } 1130 } 1131 } 1132 #ifdef PMAP_CACHE_VIPT 1133 if (arm_cache_prefer_mask != 0) { 1134 if (md->urw_mappings + md->krw_mappings == 0) { 1135 md->pvh_attrs &= ~PVF_WRITE; 1136 } else { 1137 md->pvh_attrs |= PVF_WRITE; 1138 } 1139 } 1140 /* 1141 * We have two cases here: the first is from enter_pv (new exec 1142 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1143 * Since in latter, pmap_enter_pv won't do anything, we just have 1144 * to do what pmap_remove_pv would do. 1145 */ 1146 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1147 || (PV_IS_EXEC_P(md->pvh_attrs) 1148 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1149 pmap_syncicache_page(md, pa); 1150 PMAPCOUNT(exec_synced_remap); 1151 } 1152 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1153 #endif 1154 1155 PMAPCOUNT(remappings); 1156 1157 return (oflags); 1158 } 1159 1160 /* 1161 * Allocate an L1 translation table for the specified pmap. 1162 * This is called at pmap creation time. 1163 */ 1164 static void 1165 pmap_alloc_l1(pmap_t pm) 1166 { 1167 struct l1_ttable *l1; 1168 uint8_t domain; 1169 1170 /* 1171 * Remove the L1 at the head of the LRU list 1172 */ 1173 mutex_spin_enter(&l1_lru_lock); 1174 l1 = TAILQ_FIRST(&l1_lru_list); 1175 KDASSERT(l1 != NULL); 1176 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1177 1178 /* 1179 * Pick the first available domain number, and update 1180 * the link to the next number. 1181 */ 1182 domain = l1->l1_domain_first; 1183 l1->l1_domain_first = l1->l1_domain_free[domain]; 1184 1185 /* 1186 * If there are still free domain numbers in this L1, 1187 * put it back on the TAIL of the LRU list. 1188 */ 1189 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1190 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1191 1192 mutex_spin_exit(&l1_lru_lock); 1193 1194 /* 1195 * Fix up the relevant bits in the pmap structure 1196 */ 1197 pm->pm_l1 = l1; 1198 pm->pm_domain = domain + 1; 1199 } 1200 1201 /* 1202 * Free an L1 translation table. 1203 * This is called at pmap destruction time. 1204 */ 1205 static void 1206 pmap_free_l1(pmap_t pm) 1207 { 1208 struct l1_ttable *l1 = pm->pm_l1; 1209 1210 mutex_spin_enter(&l1_lru_lock); 1211 1212 /* 1213 * If this L1 is currently on the LRU list, remove it. 1214 */ 1215 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1216 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1217 1218 /* 1219 * Free up the domain number which was allocated to the pmap 1220 */ 1221 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1222 l1->l1_domain_first = pmap_domain(pm) - 1; 1223 l1->l1_domain_use_count--; 1224 1225 /* 1226 * The L1 now must have at least 1 free domain, so add 1227 * it back to the LRU list. If the use count is zero, 1228 * put it at the head of the list, otherwise it goes 1229 * to the tail. 1230 */ 1231 if (l1->l1_domain_use_count == 0) 1232 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1233 else 1234 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1235 1236 mutex_spin_exit(&l1_lru_lock); 1237 } 1238 1239 static inline void 1240 pmap_use_l1(pmap_t pm) 1241 { 1242 struct l1_ttable *l1; 1243 1244 /* 1245 * Do nothing if we're in interrupt context. 1246 * Access to an L1 by the kernel pmap must not affect 1247 * the LRU list. 1248 */ 1249 if (cpu_intr_p() || pm == pmap_kernel()) 1250 return; 1251 1252 l1 = pm->pm_l1; 1253 1254 /* 1255 * If the L1 is not currently on the LRU list, just return 1256 */ 1257 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1258 return; 1259 1260 mutex_spin_enter(&l1_lru_lock); 1261 1262 /* 1263 * Check the use count again, now that we've acquired the lock 1264 */ 1265 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1266 mutex_spin_exit(&l1_lru_lock); 1267 return; 1268 } 1269 1270 /* 1271 * Move the L1 to the back of the LRU list 1272 */ 1273 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1274 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1275 1276 mutex_spin_exit(&l1_lru_lock); 1277 } 1278 1279 /* 1280 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1281 * 1282 * Free an L2 descriptor table. 1283 */ 1284 static inline void 1285 #ifndef PMAP_INCLUDE_PTE_SYNC 1286 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1287 #else 1288 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1289 #endif 1290 { 1291 #ifdef PMAP_INCLUDE_PTE_SYNC 1292 #ifdef PMAP_CACHE_VIVT 1293 /* 1294 * Note: With a write-back cache, we may need to sync this 1295 * L2 table before re-using it. 1296 * This is because it may have belonged to a non-current 1297 * pmap, in which case the cache syncs would have been 1298 * skipped for the pages that were being unmapped. If the 1299 * L2 table were then to be immediately re-allocated to 1300 * the *current* pmap, it may well contain stale mappings 1301 * which have not yet been cleared by a cache write-back 1302 * and so would still be visible to the mmu. 1303 */ 1304 if (need_sync) 1305 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1306 #endif /* PMAP_CACHE_VIVT */ 1307 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1308 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1309 } 1310 1311 /* 1312 * Returns a pointer to the L2 bucket associated with the specified pmap 1313 * and VA, or NULL if no L2 bucket exists for the address. 1314 */ 1315 static inline struct l2_bucket * 1316 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1317 { 1318 struct l2_dtable *l2; 1319 struct l2_bucket *l2b; 1320 u_short l1idx; 1321 1322 l1idx = L1_IDX(va); 1323 1324 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1325 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1326 return (NULL); 1327 1328 return (l2b); 1329 } 1330 1331 /* 1332 * Returns a pointer to the L2 bucket associated with the specified pmap 1333 * and VA. 1334 * 1335 * If no L2 bucket exists, perform the necessary allocations to put an L2 1336 * bucket/page table in place. 1337 * 1338 * Note that if a new L2 bucket/page was allocated, the caller *must* 1339 * increment the bucket occupancy counter appropriately *before* 1340 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1341 * the bucket/page in the meantime. 1342 */ 1343 static struct l2_bucket * 1344 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1345 { 1346 struct l2_dtable *l2; 1347 struct l2_bucket *l2b; 1348 u_short l1idx; 1349 1350 l1idx = L1_IDX(va); 1351 1352 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1353 /* 1354 * No mapping at this address, as there is 1355 * no entry in the L1 table. 1356 * Need to allocate a new l2_dtable. 1357 */ 1358 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1359 return (NULL); 1360 1361 /* 1362 * Link it into the parent pmap 1363 */ 1364 pm->pm_l2[L2_IDX(l1idx)] = l2; 1365 } 1366 1367 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1368 1369 /* 1370 * Fetch pointer to the L2 page table associated with the address. 1371 */ 1372 if (l2b->l2b_kva == NULL) { 1373 pt_entry_t *ptep; 1374 1375 /* 1376 * No L2 page table has been allocated. Chances are, this 1377 * is because we just allocated the l2_dtable, above. 1378 */ 1379 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1380 /* 1381 * Oops, no more L2 page tables available at this 1382 * time. We may need to deallocate the l2_dtable 1383 * if we allocated a new one above. 1384 */ 1385 if (l2->l2_occupancy == 0) { 1386 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1387 pmap_free_l2_dtable(l2); 1388 } 1389 return (NULL); 1390 } 1391 1392 l2->l2_occupancy++; 1393 l2b->l2b_kva = ptep; 1394 l2b->l2b_l1idx = l1idx; 1395 } 1396 1397 return (l2b); 1398 } 1399 1400 /* 1401 * One or more mappings in the specified L2 descriptor table have just been 1402 * invalidated. 1403 * 1404 * Garbage collect the metadata and descriptor table itself if necessary. 1405 * 1406 * The pmap lock must be acquired when this is called (not necessary 1407 * for the kernel pmap). 1408 */ 1409 static void 1410 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1411 { 1412 struct l2_dtable *l2; 1413 pd_entry_t *pl1pd, l1pd; 1414 pt_entry_t *ptep; 1415 u_short l1idx; 1416 1417 KDASSERT(count <= l2b->l2b_occupancy); 1418 1419 /* 1420 * Update the bucket's reference count according to how many 1421 * PTEs the caller has just invalidated. 1422 */ 1423 l2b->l2b_occupancy -= count; 1424 1425 /* 1426 * Note: 1427 * 1428 * Level 2 page tables allocated to the kernel pmap are never freed 1429 * as that would require checking all Level 1 page tables and 1430 * removing any references to the Level 2 page table. See also the 1431 * comment elsewhere about never freeing bootstrap L2 descriptors. 1432 * 1433 * We make do with just invalidating the mapping in the L2 table. 1434 * 1435 * This isn't really a big deal in practice and, in fact, leads 1436 * to a performance win over time as we don't need to continually 1437 * alloc/free. 1438 */ 1439 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1440 return; 1441 1442 /* 1443 * There are no more valid mappings in this level 2 page table. 1444 * Go ahead and NULL-out the pointer in the bucket, then 1445 * free the page table. 1446 */ 1447 l1idx = l2b->l2b_l1idx; 1448 ptep = l2b->l2b_kva; 1449 l2b->l2b_kva = NULL; 1450 1451 pl1pd = pmap_l1_kva(pm) + l1idx; 1452 1453 /* 1454 * If the L1 slot matches the pmap's domain 1455 * number, then invalidate it. 1456 */ 1457 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1458 if (l1pd == (L1_C_DOM(pmap_domain(pm)) | L1_TYPE_C)) { 1459 *pl1pd = 0; 1460 PTE_SYNC(pl1pd); 1461 } 1462 1463 /* 1464 * Release the L2 descriptor table back to the pool cache. 1465 */ 1466 #ifndef PMAP_INCLUDE_PTE_SYNC 1467 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1468 #else 1469 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1470 #endif 1471 1472 /* 1473 * Update the reference count in the associated l2_dtable 1474 */ 1475 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1476 if (--l2->l2_occupancy > 0) 1477 return; 1478 1479 /* 1480 * There are no more valid mappings in any of the Level 1 1481 * slots managed by this l2_dtable. Go ahead and NULL-out 1482 * the pointer in the parent pmap and free the l2_dtable. 1483 */ 1484 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1485 pmap_free_l2_dtable(l2); 1486 } 1487 1488 /* 1489 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1490 * structures. 1491 */ 1492 static int 1493 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1494 { 1495 #ifndef PMAP_INCLUDE_PTE_SYNC 1496 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1497 1498 /* 1499 * The mappings for these page tables were initially made using 1500 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1501 * mode will not be right for page table mappings. To avoid 1502 * polluting the pmap_kenter_pa() code with a special case for 1503 * page tables, we simply fix up the cache-mode here if it's not 1504 * correct. 1505 */ 1506 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1507 KDASSERT(l2b != NULL); 1508 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 1509 pt_entry_t opte = *ptep; 1510 1511 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1512 /* 1513 * Page tables must have the cache-mode set to Write-Thru. 1514 */ 1515 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1516 | pte_l2_s_cache_mode_pt; 1517 l2pte_set(ptep, npte, opte); 1518 PTE_SYNC(ptep); 1519 cpu_tlb_flushD_SE(va); 1520 cpu_cpwait(); 1521 } 1522 #endif 1523 1524 memset(v, 0, L2_TABLE_SIZE_REAL); 1525 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1526 return (0); 1527 } 1528 1529 static int 1530 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1531 { 1532 1533 memset(v, 0, sizeof(struct l2_dtable)); 1534 return (0); 1535 } 1536 1537 static int 1538 pmap_pmap_ctor(void *arg, void *v, int flags) 1539 { 1540 1541 memset(v, 0, sizeof(struct pmap)); 1542 return (0); 1543 } 1544 1545 static void 1546 pmap_pinit(pmap_t pm) 1547 { 1548 #ifndef ARM_HAS_VBAR 1549 struct l2_bucket *l2b; 1550 1551 if (vector_page < KERNEL_BASE) { 1552 /* 1553 * Map the vector page. 1554 */ 1555 pmap_enter(pm, vector_page, systempage.pv_pa, 1556 VM_PROT_READ | VM_PROT_EXECUTE, 1557 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1558 pmap_update(pm); 1559 1560 pm->pm_pl1vec = pmap_l1_kva(pm) + L1_IDX(vector_page); 1561 l2b = pmap_get_l2_bucket(pm, vector_page); 1562 KDASSERT(l2b != NULL); 1563 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1564 L1_C_DOM(pmap_domain(pm)); 1565 } else 1566 pm->pm_pl1vec = NULL; 1567 #endif 1568 } 1569 1570 #ifdef PMAP_CACHE_VIVT 1571 /* 1572 * Since we have a virtually indexed cache, we may need to inhibit caching if 1573 * there is more than one mapping and at least one of them is writable. 1574 * Since we purge the cache on every context switch, we only need to check for 1575 * other mappings within the same pmap, or kernel_pmap. 1576 * This function is also called when a page is unmapped, to possibly reenable 1577 * caching on any remaining mappings. 1578 * 1579 * The code implements the following logic, where: 1580 * 1581 * KW = # of kernel read/write pages 1582 * KR = # of kernel read only pages 1583 * UW = # of user read/write pages 1584 * UR = # of user read only pages 1585 * 1586 * KC = kernel mapping is cacheable 1587 * UC = user mapping is cacheable 1588 * 1589 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1590 * +--------------------------------------------- 1591 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1592 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1593 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1594 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1595 */ 1596 1597 static const int pmap_vac_flags[4][4] = { 1598 {-1, 0, 0, PVF_KNC}, 1599 {0, 0, PVF_NC, PVF_NC}, 1600 {0, PVF_NC, PVF_NC, PVF_NC}, 1601 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1602 }; 1603 1604 static inline int 1605 pmap_get_vac_flags(const struct vm_page_md *md) 1606 { 1607 int kidx, uidx; 1608 1609 kidx = 0; 1610 if (md->kro_mappings || md->krw_mappings > 1) 1611 kidx |= 1; 1612 if (md->krw_mappings) 1613 kidx |= 2; 1614 1615 uidx = 0; 1616 if (md->uro_mappings || md->urw_mappings > 1) 1617 uidx |= 1; 1618 if (md->urw_mappings) 1619 uidx |= 2; 1620 1621 return (pmap_vac_flags[uidx][kidx]); 1622 } 1623 1624 static inline void 1625 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1626 { 1627 int nattr; 1628 1629 nattr = pmap_get_vac_flags(md); 1630 1631 if (nattr < 0) { 1632 md->pvh_attrs &= ~PVF_NC; 1633 return; 1634 } 1635 1636 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1637 return; 1638 1639 if (pm == pmap_kernel()) 1640 pmap_vac_me_kpmap(md, pa, pm, va); 1641 else 1642 pmap_vac_me_user(md, pa, pm, va); 1643 1644 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1645 } 1646 1647 static void 1648 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1649 { 1650 u_int u_cacheable, u_entries; 1651 struct pv_entry *pv; 1652 pmap_t last_pmap = pm; 1653 1654 /* 1655 * Pass one, see if there are both kernel and user pmaps for 1656 * this page. Calculate whether there are user-writable or 1657 * kernel-writable pages. 1658 */ 1659 u_cacheable = 0; 1660 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1661 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1662 u_cacheable++; 1663 } 1664 1665 u_entries = md->urw_mappings + md->uro_mappings; 1666 1667 /* 1668 * We know we have just been updating a kernel entry, so if 1669 * all user pages are already cacheable, then there is nothing 1670 * further to do. 1671 */ 1672 if (md->k_mappings == 0 && u_cacheable == u_entries) 1673 return; 1674 1675 if (u_entries) { 1676 /* 1677 * Scan over the list again, for each entry, if it 1678 * might not be set correctly, call pmap_vac_me_user 1679 * to recalculate the settings. 1680 */ 1681 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1682 /* 1683 * We know kernel mappings will get set 1684 * correctly in other calls. We also know 1685 * that if the pmap is the same as last_pmap 1686 * then we've just handled this entry. 1687 */ 1688 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1689 continue; 1690 1691 /* 1692 * If there are kernel entries and this page 1693 * is writable but non-cacheable, then we can 1694 * skip this entry also. 1695 */ 1696 if (md->k_mappings && 1697 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1698 (PVF_NC | PVF_WRITE)) 1699 continue; 1700 1701 /* 1702 * Similarly if there are no kernel-writable 1703 * entries and the page is already 1704 * read-only/cacheable. 1705 */ 1706 if (md->krw_mappings == 0 && 1707 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1708 continue; 1709 1710 /* 1711 * For some of the remaining cases, we know 1712 * that we must recalculate, but for others we 1713 * can't tell if they are correct or not, so 1714 * we recalculate anyway. 1715 */ 1716 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1717 } 1718 1719 if (md->k_mappings == 0) 1720 return; 1721 } 1722 1723 pmap_vac_me_user(md, pa, pm, va); 1724 } 1725 1726 static void 1727 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1728 { 1729 pmap_t kpmap = pmap_kernel(); 1730 struct pv_entry *pv, *npv = NULL; 1731 u_int entries = 0; 1732 u_int writable = 0; 1733 u_int cacheable_entries = 0; 1734 u_int kern_cacheable = 0; 1735 u_int other_writable = 0; 1736 1737 /* 1738 * Count mappings and writable mappings in this pmap. 1739 * Include kernel mappings as part of our own. 1740 * Keep a pointer to the first one. 1741 */ 1742 npv = NULL; 1743 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1744 /* Count mappings in the same pmap */ 1745 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1746 if (entries++ == 0) 1747 npv = pv; 1748 1749 /* Cacheable mappings */ 1750 if ((pv->pv_flags & PVF_NC) == 0) { 1751 cacheable_entries++; 1752 if (kpmap == pv->pv_pmap) 1753 kern_cacheable++; 1754 } 1755 1756 /* Writable mappings */ 1757 if (pv->pv_flags & PVF_WRITE) 1758 ++writable; 1759 } else 1760 if (pv->pv_flags & PVF_WRITE) 1761 other_writable = 1; 1762 } 1763 1764 /* 1765 * Enable or disable caching as necessary. 1766 * Note: the first entry might be part of the kernel pmap, 1767 * so we can't assume this is indicative of the state of the 1768 * other (maybe non-kpmap) entries. 1769 */ 1770 if ((entries > 1 && writable) || 1771 (entries > 0 && pm == kpmap && other_writable)) { 1772 if (cacheable_entries == 0) 1773 return; 1774 1775 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1776 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1777 (pv->pv_flags & PVF_NC)) 1778 continue; 1779 1780 pv->pv_flags |= PVF_NC; 1781 1782 struct l2_bucket * const l2b 1783 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1784 KDASSERT(l2b != NULL); 1785 pt_entry_t * const ptep 1786 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1787 const pt_entry_t opte = *ptep; 1788 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1789 1790 if ((va != pv->pv_va || pm != pv->pv_pmap) 1791 && l2pte_valid(npte)) { 1792 #ifdef PMAP_CACHE_VIVT 1793 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1794 true, pv->pv_flags); 1795 #endif 1796 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1797 pv->pv_flags); 1798 } 1799 1800 l2pte_set(ptep, npte, opte); 1801 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1802 } 1803 cpu_cpwait(); 1804 } else 1805 if (entries > cacheable_entries) { 1806 /* 1807 * Turn cacheing back on for some pages. If it is a kernel 1808 * page, only do so if there are no other writable pages. 1809 */ 1810 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1811 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1812 (kpmap != pv->pv_pmap || other_writable))) 1813 continue; 1814 1815 pv->pv_flags &= ~PVF_NC; 1816 1817 struct l2_bucket * const l2b 1818 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1819 KDASSERT(l2b != NULL); 1820 pt_entry_t * const ptep 1821 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1822 const pt_entry_t opte = *ptep; 1823 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1824 | pte_l2_s_cache_mode; 1825 1826 if (l2pte_valid(opte)) { 1827 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1828 pv->pv_flags); 1829 } 1830 1831 l2pte_set(ptep, npte, opte); 1832 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1833 } 1834 } 1835 } 1836 #endif 1837 1838 #ifdef PMAP_CACHE_VIPT 1839 static void 1840 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1841 { 1842 struct pv_entry *pv; 1843 vaddr_t tst_mask; 1844 bool bad_alias; 1845 const u_int 1846 rw_mappings = md->urw_mappings + md->krw_mappings, 1847 ro_mappings = md->uro_mappings + md->kro_mappings; 1848 1849 /* do we need to do anything? */ 1850 if (arm_cache_prefer_mask == 0) 1851 return; 1852 1853 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1854 md, pm, va)); 1855 1856 KASSERT(!va || pm); 1857 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1858 1859 /* Already a conflict? */ 1860 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1861 /* just an add, things are already non-cached */ 1862 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1863 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1864 bad_alias = false; 1865 if (va) { 1866 PMAPCOUNT(vac_color_none); 1867 bad_alias = true; 1868 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1869 goto fixup; 1870 } 1871 pv = SLIST_FIRST(&md->pvh_list); 1872 /* the list can't be empty because it would be cachable */ 1873 if (md->pvh_attrs & PVF_KMPAGE) { 1874 tst_mask = md->pvh_attrs; 1875 } else { 1876 KASSERT(pv); 1877 tst_mask = pv->pv_va; 1878 pv = SLIST_NEXT(pv, pv_link); 1879 } 1880 /* 1881 * Only check for a bad alias if we have writable mappings. 1882 */ 1883 tst_mask &= arm_cache_prefer_mask; 1884 if (rw_mappings > 0) { 1885 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1886 /* if there's a bad alias, stop checking. */ 1887 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1888 bad_alias = true; 1889 } 1890 md->pvh_attrs |= PVF_WRITE; 1891 if (!bad_alias) 1892 md->pvh_attrs |= PVF_DIRTY; 1893 } else { 1894 /* 1895 * We have only read-only mappings. Let's see if there 1896 * are multiple colors in use or if we mapped a KMPAGE. 1897 * If the latter, we have a bad alias. If the former, 1898 * we need to remember that. 1899 */ 1900 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1901 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1902 if (md->pvh_attrs & PVF_KMPAGE) 1903 bad_alias = true; 1904 break; 1905 } 1906 } 1907 md->pvh_attrs &= ~PVF_WRITE; 1908 /* 1909 * No KMPAGE and we exited early, so we must have 1910 * multiple color mappings. 1911 */ 1912 if (!bad_alias && pv != NULL) 1913 md->pvh_attrs |= PVF_MULTCLR; 1914 } 1915 1916 /* If no conflicting colors, set everything back to cached */ 1917 if (!bad_alias) { 1918 #ifdef DEBUG 1919 if ((md->pvh_attrs & PVF_WRITE) 1920 || ro_mappings < 2) { 1921 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1922 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1923 } 1924 #endif 1925 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1926 md->pvh_attrs |= tst_mask | PVF_COLORED; 1927 /* 1928 * Restore DIRTY bit if page is modified 1929 */ 1930 if (md->pvh_attrs & PVF_DMOD) 1931 md->pvh_attrs |= PVF_DIRTY; 1932 PMAPCOUNT(vac_color_restore); 1933 } else { 1934 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1935 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1936 } 1937 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1938 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1939 } else if (!va) { 1940 KASSERT(pmap_is_page_colored_p(md)); 1941 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1942 || (md->pvh_attrs & PVF_DIRTY)); 1943 if (rw_mappings == 0) { 1944 md->pvh_attrs &= ~PVF_WRITE; 1945 if (ro_mappings == 1 1946 && (md->pvh_attrs & PVF_MULTCLR)) { 1947 /* 1948 * If this is the last readonly mapping 1949 * but it doesn't match the current color 1950 * for the page, change the current color 1951 * to match this last readonly mapping. 1952 */ 1953 pv = SLIST_FIRST(&md->pvh_list); 1954 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1955 & arm_cache_prefer_mask; 1956 if (tst_mask) { 1957 md->pvh_attrs ^= tst_mask; 1958 PMAPCOUNT(vac_color_change); 1959 } 1960 } 1961 } 1962 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1963 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1964 return; 1965 } else if (!pmap_is_page_colored_p(md)) { 1966 /* not colored so we just use its color */ 1967 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1968 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1969 PMAPCOUNT(vac_color_new); 1970 md->pvh_attrs &= PAGE_SIZE - 1; 1971 md->pvh_attrs |= PVF_COLORED 1972 | (va & arm_cache_prefer_mask) 1973 | (rw_mappings > 0 ? PVF_WRITE : 0); 1974 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1975 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1976 return; 1977 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1978 bad_alias = false; 1979 if (rw_mappings > 0) { 1980 /* 1981 * We now have writeable mappings and if we have 1982 * readonly mappings in more than once color, we have 1983 * an aliasing problem. Regardless mark the page as 1984 * writeable. 1985 */ 1986 if (md->pvh_attrs & PVF_MULTCLR) { 1987 if (ro_mappings < 2) { 1988 /* 1989 * If we only have less than two 1990 * read-only mappings, just flush the 1991 * non-primary colors from the cache. 1992 */ 1993 pmap_flush_page(md, pa, 1994 PMAP_FLUSH_SECONDARY); 1995 } else { 1996 bad_alias = true; 1997 } 1998 } 1999 md->pvh_attrs |= PVF_WRITE; 2000 } 2001 /* If no conflicting colors, set everything back to cached */ 2002 if (!bad_alias) { 2003 #ifdef DEBUG 2004 if (rw_mappings > 0 2005 || (md->pvh_attrs & PMAP_KMPAGE)) { 2006 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2007 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2008 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2009 } 2010 #endif 2011 if (SLIST_EMPTY(&md->pvh_list)) 2012 PMAPCOUNT(vac_color_reuse); 2013 else 2014 PMAPCOUNT(vac_color_ok); 2015 2016 /* matching color, just return */ 2017 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2018 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2019 return; 2020 } 2021 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2022 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2023 2024 /* color conflict. evict from cache. */ 2025 2026 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2027 md->pvh_attrs &= ~PVF_COLORED; 2028 md->pvh_attrs |= PVF_NC; 2029 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2030 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2031 PMAPCOUNT(vac_color_erase); 2032 } else if (rw_mappings == 0 2033 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2034 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2035 2036 /* 2037 * If the page has dirty cache lines, clean it. 2038 */ 2039 if (md->pvh_attrs & PVF_DIRTY) 2040 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2041 2042 /* 2043 * If this is the first remapping (we know that there are no 2044 * writeable mappings), then this is a simple color change. 2045 * Otherwise this is a seconary r/o mapping, which means 2046 * we don't have to do anything. 2047 */ 2048 if (ro_mappings == 1) { 2049 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2050 md->pvh_attrs &= PAGE_SIZE - 1; 2051 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2052 PMAPCOUNT(vac_color_change); 2053 } else { 2054 PMAPCOUNT(vac_color_blind); 2055 } 2056 md->pvh_attrs |= PVF_MULTCLR; 2057 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2058 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2059 return; 2060 } else { 2061 if (rw_mappings > 0) 2062 md->pvh_attrs |= PVF_WRITE; 2063 2064 /* color conflict. evict from cache. */ 2065 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2066 2067 /* the list can't be empty because this was a enter/modify */ 2068 pv = SLIST_FIRST(&md->pvh_list); 2069 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2070 KASSERT(pv); 2071 /* 2072 * If there's only one mapped page, change color to the 2073 * page's new color and return. Restore the DIRTY bit 2074 * that was erased by pmap_flush_page. 2075 */ 2076 if (SLIST_NEXT(pv, pv_link) == NULL) { 2077 md->pvh_attrs &= PAGE_SIZE - 1; 2078 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2079 if (md->pvh_attrs & PVF_DMOD) 2080 md->pvh_attrs |= PVF_DIRTY; 2081 PMAPCOUNT(vac_color_change); 2082 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2083 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2084 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2085 return; 2086 } 2087 } 2088 bad_alias = true; 2089 md->pvh_attrs &= ~PVF_COLORED; 2090 md->pvh_attrs |= PVF_NC; 2091 PMAPCOUNT(vac_color_erase); 2092 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2093 } 2094 2095 fixup: 2096 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2097 2098 /* 2099 * Turn cacheing on/off for all pages. 2100 */ 2101 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2102 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2103 pv->pv_va); 2104 KDASSERT(l2b != NULL); 2105 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2106 const pt_entry_t opte = *ptep; 2107 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2108 if (bad_alias) { 2109 pv->pv_flags |= PVF_NC; 2110 } else { 2111 pv->pv_flags &= ~PVF_NC; 2112 npte |= pte_l2_s_cache_mode; 2113 } 2114 2115 if (opte == npte) /* only update is there's a change */ 2116 continue; 2117 2118 if (l2pte_valid(npte)) { 2119 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2120 } 2121 2122 l2pte_set(ptep, npte, opte); 2123 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2124 } 2125 } 2126 #endif /* PMAP_CACHE_VIPT */ 2127 2128 2129 /* 2130 * Modify pte bits for all ptes corresponding to the given physical address. 2131 * We use `maskbits' rather than `clearbits' because we're always passing 2132 * constants and the latter would require an extra inversion at run-time. 2133 */ 2134 static void 2135 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2136 { 2137 struct pv_entry *pv; 2138 pmap_t pm; 2139 vaddr_t va; 2140 u_int oflags; 2141 #ifdef PMAP_CACHE_VIPT 2142 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2143 bool need_vac_me_harder = false; 2144 bool need_syncicache = false; 2145 #endif 2146 2147 NPDEBUG(PDB_BITS, 2148 printf("pmap_clearbit: md %p mask 0x%x\n", 2149 md, maskbits)); 2150 2151 #ifdef PMAP_CACHE_VIPT 2152 /* 2153 * If we might want to sync the I-cache and we've modified it, 2154 * then we know we definitely need to sync or discard it. 2155 */ 2156 if (want_syncicache) { 2157 need_syncicache = md->pvh_attrs & PVF_MOD; 2158 } 2159 #endif 2160 /* 2161 * Clear saved attributes (modify, reference) 2162 */ 2163 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2164 2165 if (SLIST_EMPTY(&md->pvh_list)) { 2166 #if defined(PMAP_CACHE_VIPT) 2167 if (need_syncicache) { 2168 /* 2169 * No one has it mapped, so just discard it. The next 2170 * exec remapping will cause it to be synced. 2171 */ 2172 md->pvh_attrs &= ~PVF_EXEC; 2173 PMAPCOUNT(exec_discarded_clearbit); 2174 } 2175 #endif 2176 return; 2177 } 2178 2179 /* 2180 * Loop over all current mappings setting/clearing as appropos 2181 */ 2182 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2183 va = pv->pv_va; 2184 pm = pv->pv_pmap; 2185 oflags = pv->pv_flags; 2186 /* 2187 * Kernel entries are unmanaged and as such not to be changed. 2188 */ 2189 if (oflags & PVF_KENTRY) 2190 continue; 2191 pv->pv_flags &= ~maskbits; 2192 2193 pmap_acquire_pmap_lock(pm); 2194 2195 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2196 KDASSERT(l2b != NULL); 2197 2198 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2199 const pt_entry_t opte = *ptep; 2200 pt_entry_t npte = opte; 2201 2202 NPDEBUG(PDB_BITS, 2203 printf( 2204 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2205 pv, pv->pv_pmap, pv->pv_va, oflags)); 2206 2207 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2208 #ifdef PMAP_CACHE_VIVT 2209 if ((pv->pv_flags & PVF_NC)) { 2210 /* 2211 * Entry is not cacheable: 2212 * 2213 * Don't turn caching on again if this is a 2214 * modified emulation. This would be 2215 * inconsitent with the settings created by 2216 * pmap_vac_me_harder(). Otherwise, it's safe 2217 * to re-enable cacheing. 2218 * 2219 * There's no need to call pmap_vac_me_harder() 2220 * here: all pages are losing their write 2221 * permission. 2222 */ 2223 if (maskbits & PVF_WRITE) { 2224 npte |= pte_l2_s_cache_mode; 2225 pv->pv_flags &= ~PVF_NC; 2226 } 2227 } else 2228 if (l2pte_writable_p(opte)) { 2229 /* 2230 * Entry is writable/cacheable: check if pmap 2231 * is current if it is flush it, otherwise it 2232 * won't be in the cache 2233 */ 2234 pmap_cache_wbinv_page(pm, pv->pv_va, 2235 (maskbits & PVF_REF) != 0, 2236 oflags|PVF_WRITE); 2237 } 2238 #endif 2239 2240 /* make the pte read only */ 2241 npte = l2pte_set_readonly(npte); 2242 2243 if (maskbits & oflags & PVF_WRITE) { 2244 /* 2245 * Keep alias accounting up to date 2246 */ 2247 if (pv->pv_pmap == pmap_kernel()) { 2248 md->krw_mappings--; 2249 md->kro_mappings++; 2250 } else { 2251 md->urw_mappings--; 2252 md->uro_mappings++; 2253 } 2254 #ifdef PMAP_CACHE_VIPT 2255 if (arm_cache_prefer_mask != 0) { 2256 if (md->urw_mappings + md->krw_mappings == 0) { 2257 md->pvh_attrs &= ~PVF_WRITE; 2258 } else { 2259 PMAP_VALIDATE_MD_PAGE(md); 2260 } 2261 } 2262 if (want_syncicache) 2263 need_syncicache = true; 2264 need_vac_me_harder = true; 2265 #endif 2266 } 2267 } 2268 2269 if (maskbits & PVF_REF) { 2270 if ((pv->pv_flags & PVF_NC) == 0 2271 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2272 && l2pte_valid(npte)) { 2273 #ifdef PMAP_CACHE_VIVT 2274 /* 2275 * Check npte here; we may have already 2276 * done the wbinv above, and the validity 2277 * of the PTE is the same for opte and 2278 * npte. 2279 */ 2280 pmap_cache_wbinv_page(pm, pv->pv_va, true, 2281 oflags); 2282 #endif 2283 } 2284 2285 /* 2286 * Make the PTE invalid so that we will take a 2287 * page fault the next time the mapping is 2288 * referenced. 2289 */ 2290 npte &= ~L2_TYPE_MASK; 2291 npte |= L2_TYPE_INV; 2292 } 2293 2294 if (npte != opte) { 2295 l2pte_set(ptep, npte, opte); 2296 PTE_SYNC(ptep); 2297 2298 /* Flush the TLB entry if a current pmap. */ 2299 pmap_tlb_flush_SE(pm, pv->pv_va, oflags); 2300 } 2301 2302 pmap_release_pmap_lock(pm); 2303 2304 NPDEBUG(PDB_BITS, 2305 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2306 pm, va, opte, npte)); 2307 } 2308 2309 #ifdef PMAP_CACHE_VIPT 2310 /* 2311 * If we need to sync the I-cache and we haven't done it yet, do it. 2312 */ 2313 if (need_syncicache) { 2314 pmap_syncicache_page(md, pa); 2315 PMAPCOUNT(exec_synced_clearbit); 2316 } 2317 2318 /* 2319 * If we are changing this to read-only, we need to call vac_me_harder 2320 * so we can change all the read-only pages to cacheable. We pretend 2321 * this as a page deletion. 2322 */ 2323 if (need_vac_me_harder) { 2324 if (md->pvh_attrs & PVF_NC) 2325 pmap_vac_me_harder(md, pa, NULL, 0); 2326 } 2327 #endif 2328 } 2329 2330 /* 2331 * pmap_clean_page() 2332 * 2333 * This is a local function used to work out the best strategy to clean 2334 * a single page referenced by its entry in the PV table. It's used by 2335 * pmap_copy_page, pmap_zero page and maybe some others later on. 2336 * 2337 * Its policy is effectively: 2338 * o If there are no mappings, we don't bother doing anything with the cache. 2339 * o If there is one mapping, we clean just that page. 2340 * o If there are multiple mappings, we clean the entire cache. 2341 * 2342 * So that some functions can be further optimised, it returns 0 if it didn't 2343 * clean the entire cache, or 1 if it did. 2344 * 2345 * XXX One bug in this routine is that if the pv_entry has a single page 2346 * mapped at 0x00000000 a whole cache clean will be performed rather than 2347 * just the 1 page. Since this should not occur in everyday use and if it does 2348 * it will just result in not the most efficient clean for the page. 2349 */ 2350 #ifdef PMAP_CACHE_VIVT 2351 static int 2352 pmap_clean_page(struct pv_entry *pv, bool is_src) 2353 { 2354 pmap_t pm_to_clean = NULL; 2355 struct pv_entry *npv; 2356 u_int cache_needs_cleaning = 0; 2357 u_int flags = 0; 2358 vaddr_t page_to_clean = 0; 2359 2360 if (pv == NULL) { 2361 /* nothing mapped in so nothing to flush */ 2362 return (0); 2363 } 2364 2365 /* 2366 * Since we flush the cache each time we change to a different 2367 * user vmspace, we only need to flush the page if it is in the 2368 * current pmap. 2369 */ 2370 2371 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2372 if (pmap_is_current(npv->pv_pmap)) { 2373 flags |= npv->pv_flags; 2374 /* 2375 * The page is mapped non-cacheable in 2376 * this map. No need to flush the cache. 2377 */ 2378 if (npv->pv_flags & PVF_NC) { 2379 #ifdef DIAGNOSTIC 2380 if (cache_needs_cleaning) 2381 panic("pmap_clean_page: " 2382 "cache inconsistency"); 2383 #endif 2384 break; 2385 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2386 continue; 2387 if (cache_needs_cleaning) { 2388 page_to_clean = 0; 2389 break; 2390 } else { 2391 page_to_clean = npv->pv_va; 2392 pm_to_clean = npv->pv_pmap; 2393 } 2394 cache_needs_cleaning = 1; 2395 } 2396 } 2397 2398 if (page_to_clean) { 2399 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2400 !is_src, flags | PVF_REF); 2401 } else if (cache_needs_cleaning) { 2402 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2403 2404 pmap_cache_wbinv_all(pm, flags); 2405 return (1); 2406 } 2407 return (0); 2408 } 2409 #endif 2410 2411 #ifdef PMAP_CACHE_VIPT 2412 /* 2413 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2414 * right cache alias to make sure we flush the right stuff. 2415 */ 2416 void 2417 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2418 { 2419 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2420 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2421 2422 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2423 md, md->pvh_attrs)); 2424 /* 2425 * No need to clean the page if it's non-cached. 2426 */ 2427 if (md->pvh_attrs & PVF_NC) 2428 return; 2429 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2430 2431 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, PVF_REF | PVF_EXEC); 2432 /* 2433 * Set up a PTE with the right coloring to flush existing cache lines. 2434 */ 2435 const pt_entry_t npte = L2_S_PROTO | 2436 pa 2437 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2438 | pte_l2_s_cache_mode; 2439 l2pte_set(ptep, npte, 0); 2440 PTE_SYNC(ptep); 2441 2442 /* 2443 * Flush it. 2444 */ 2445 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2446 /* 2447 * Unmap the page. 2448 */ 2449 l2pte_reset(ptep); 2450 PTE_SYNC(ptep); 2451 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, PVF_REF | PVF_EXEC); 2452 2453 md->pvh_attrs |= PVF_EXEC; 2454 PMAPCOUNT(exec_synced); 2455 } 2456 2457 void 2458 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2459 { 2460 vsize_t va_offset, end_va; 2461 bool wbinv_p; 2462 2463 if (arm_cache_prefer_mask == 0) 2464 return; 2465 2466 switch (flush) { 2467 case PMAP_FLUSH_PRIMARY: 2468 if (md->pvh_attrs & PVF_MULTCLR) { 2469 va_offset = 0; 2470 end_va = arm_cache_prefer_mask; 2471 md->pvh_attrs &= ~PVF_MULTCLR; 2472 PMAPCOUNT(vac_flush_lots); 2473 } else { 2474 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2475 end_va = va_offset; 2476 PMAPCOUNT(vac_flush_one); 2477 } 2478 /* 2479 * Mark that the page is no longer dirty. 2480 */ 2481 md->pvh_attrs &= ~PVF_DIRTY; 2482 wbinv_p = true; 2483 break; 2484 case PMAP_FLUSH_SECONDARY: 2485 va_offset = 0; 2486 end_va = arm_cache_prefer_mask; 2487 wbinv_p = true; 2488 md->pvh_attrs &= ~PVF_MULTCLR; 2489 PMAPCOUNT(vac_flush_lots); 2490 break; 2491 case PMAP_CLEAN_PRIMARY: 2492 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2493 end_va = va_offset; 2494 wbinv_p = false; 2495 /* 2496 * Mark that the page is no longer dirty. 2497 */ 2498 if ((md->pvh_attrs & PVF_DMOD) == 0) 2499 md->pvh_attrs &= ~PVF_DIRTY; 2500 PMAPCOUNT(vac_clean_one); 2501 break; 2502 default: 2503 return; 2504 } 2505 2506 KASSERT(!(md->pvh_attrs & PVF_NC)); 2507 2508 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2509 md, md->pvh_attrs)); 2510 2511 const size_t scache_line_size = arm_scache.dcache_line_size; 2512 2513 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2514 const size_t pte_offset = va_offset >> PGSHIFT; 2515 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2516 const pt_entry_t opte = *ptep; 2517 2518 if (flush == PMAP_FLUSH_SECONDARY 2519 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2520 continue; 2521 2522 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, 2523 PVF_REF | PVF_EXEC); 2524 /* 2525 * Set up a PTE with the right coloring to flush 2526 * existing cache entries. 2527 */ 2528 const pt_entry_t npte = L2_S_PROTO 2529 | pa 2530 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2531 | pte_l2_s_cache_mode; 2532 l2pte_set(ptep, npte, opte); 2533 PTE_SYNC(ptep); 2534 2535 /* 2536 * Flush it. Make sure to flush secondary cache too since 2537 * bus_dma will ignore uncached pages. 2538 */ 2539 vaddr_t va = cdstp + va_offset; 2540 if (scache_line_size != 0) { 2541 cpu_dcache_wb_range(va, PAGE_SIZE); 2542 if (wbinv_p) { 2543 cpu_sdcache_wbinv_range(va, pa, PAGE_SIZE); 2544 cpu_dcache_inv_range(va, PAGE_SIZE); 2545 } else { 2546 cpu_sdcache_wb_range(va, pa, PAGE_SIZE); 2547 } 2548 } else { 2549 if (wbinv_p) { 2550 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2551 } else { 2552 cpu_dcache_wb_range(va, PAGE_SIZE); 2553 } 2554 } 2555 2556 /* 2557 * Restore the page table entry since we might have interrupted 2558 * pmap_zero_page or pmap_copy_page which was already using 2559 * this pte. 2560 */ 2561 l2pte_set(ptep, opte, npte); 2562 PTE_SYNC(ptep); 2563 pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, 2564 PVF_REF | PVF_EXEC); 2565 } 2566 } 2567 #endif /* PMAP_CACHE_VIPT */ 2568 2569 /* 2570 * Routine: pmap_page_remove 2571 * Function: 2572 * Removes this physical page from 2573 * all physical maps in which it resides. 2574 * Reflects back modify bits to the pager. 2575 */ 2576 static void 2577 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2578 { 2579 struct l2_bucket *l2b; 2580 struct pv_entry *pv, *npv, **pvp; 2581 pmap_t pm; 2582 pt_entry_t *ptep; 2583 bool flush; 2584 u_int flags; 2585 2586 NPDEBUG(PDB_FOLLOW, 2587 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2588 pa)); 2589 2590 pv = SLIST_FIRST(&md->pvh_list); 2591 if (pv == NULL) { 2592 #ifdef PMAP_CACHE_VIPT 2593 /* 2594 * We *know* the page contents are about to be replaced. 2595 * Discard the exec contents 2596 */ 2597 if (PV_IS_EXEC_P(md->pvh_attrs)) 2598 PMAPCOUNT(exec_discarded_page_protect); 2599 md->pvh_attrs &= ~PVF_EXEC; 2600 PMAP_VALIDATE_MD_PAGE(md); 2601 #endif 2602 return; 2603 } 2604 #ifdef PMAP_CACHE_VIPT 2605 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2606 #endif 2607 2608 /* 2609 * Clear alias counts 2610 */ 2611 #ifdef PMAP_CACHE_VIVT 2612 md->k_mappings = 0; 2613 #endif 2614 md->urw_mappings = md->uro_mappings = 0; 2615 2616 flush = false; 2617 flags = 0; 2618 2619 #ifdef PMAP_CACHE_VIVT 2620 pmap_clean_page(pv, false); 2621 #endif 2622 2623 pvp = &SLIST_FIRST(&md->pvh_list); 2624 while (pv) { 2625 pm = pv->pv_pmap; 2626 npv = SLIST_NEXT(pv, pv_link); 2627 if (flush == false && pmap_is_current(pm)) 2628 flush = true; 2629 2630 if (pm == pmap_kernel()) { 2631 #ifdef PMAP_CACHE_VIPT 2632 /* 2633 * If this was unmanaged mapping, it must be preserved. 2634 * Move it back on the list and advance the end-of-list 2635 * pointer. 2636 */ 2637 if (pv->pv_flags & PVF_KENTRY) { 2638 *pvp = pv; 2639 pvp = &SLIST_NEXT(pv, pv_link); 2640 pv = npv; 2641 continue; 2642 } 2643 if (pv->pv_flags & PVF_WRITE) 2644 md->krw_mappings--; 2645 else 2646 md->kro_mappings--; 2647 #endif 2648 PMAPCOUNT(kernel_unmappings); 2649 } 2650 PMAPCOUNT(unmappings); 2651 2652 pmap_acquire_pmap_lock(pm); 2653 2654 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2655 KDASSERT(l2b != NULL); 2656 2657 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2658 2659 /* 2660 * Update statistics 2661 */ 2662 --pm->pm_stats.resident_count; 2663 2664 /* Wired bit */ 2665 if (pv->pv_flags & PVF_WIRED) 2666 --pm->pm_stats.wired_count; 2667 2668 flags |= pv->pv_flags; 2669 2670 /* 2671 * Invalidate the PTEs. 2672 */ 2673 l2pte_reset(ptep); 2674 PTE_SYNC_CURRENT(pm, ptep); 2675 pmap_free_l2_bucket(pm, l2b, 1); 2676 2677 pool_put(&pmap_pv_pool, pv); 2678 pv = npv; 2679 /* 2680 * if we reach the end of the list and there are still 2681 * mappings, they might be able to be cached now. 2682 */ 2683 if (pv == NULL) { 2684 *pvp = NULL; 2685 if (!SLIST_EMPTY(&md->pvh_list)) 2686 pmap_vac_me_harder(md, pa, pm, 0); 2687 } 2688 pmap_release_pmap_lock(pm); 2689 } 2690 #ifdef PMAP_CACHE_VIPT 2691 /* 2692 * Its EXEC cache is now gone. 2693 */ 2694 if (PV_IS_EXEC_P(md->pvh_attrs)) 2695 PMAPCOUNT(exec_discarded_page_protect); 2696 md->pvh_attrs &= ~PVF_EXEC; 2697 KASSERT(md->urw_mappings == 0); 2698 KASSERT(md->uro_mappings == 0); 2699 if (arm_cache_prefer_mask != 0) { 2700 if (md->krw_mappings == 0) 2701 md->pvh_attrs &= ~PVF_WRITE; 2702 PMAP_VALIDATE_MD_PAGE(md); 2703 } 2704 #endif 2705 2706 if (flush) { 2707 /* 2708 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2709 * would need a subsequent call to pmap_update() to ensure 2710 * curpm->pm_cstate.cs_all is reset. Our callers are not 2711 * required to do that (see pmap(9)), so we can't modify 2712 * the current pmap's state. 2713 */ 2714 if (PV_BEEN_EXECD(flags)) 2715 cpu_tlb_flushID(); 2716 else 2717 cpu_tlb_flushD(); 2718 } 2719 cpu_cpwait(); 2720 } 2721 2722 /* 2723 * pmap_t pmap_create(void) 2724 * 2725 * Create a new pmap structure from scratch. 2726 */ 2727 pmap_t 2728 pmap_create(void) 2729 { 2730 pmap_t pm; 2731 2732 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2733 2734 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2735 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2736 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2737 2738 pm->pm_stats.wired_count = 0; 2739 pm->pm_stats.resident_count = 1; 2740 pm->pm_cstate.cs_all = 0; 2741 pmap_alloc_l1(pm); 2742 2743 /* 2744 * Note: The pool cache ensures that the pm_l2[] array is already 2745 * initialised to zero. 2746 */ 2747 2748 pmap_pinit(pm); 2749 2750 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2751 2752 return (pm); 2753 } 2754 2755 u_int 2756 arm32_mmap_flags(paddr_t pa) 2757 { 2758 /* 2759 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 2760 * and we're using the upper bits in page numbers to pass flags around 2761 * so we might as well use the same bits 2762 */ 2763 return (u_int)pa & PMAP_MD_MASK; 2764 } 2765 /* 2766 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2767 * u_int flags) 2768 * 2769 * Insert the given physical page (p) at 2770 * the specified virtual address (v) in the 2771 * target physical map with the protection requested. 2772 * 2773 * NB: This is the only routine which MAY NOT lazy-evaluate 2774 * or lose information. That is, this routine must actually 2775 * insert this page into the given map NOW. 2776 */ 2777 int 2778 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2779 { 2780 struct l2_bucket *l2b; 2781 struct vm_page *pg, *opg; 2782 struct pv_entry *pv; 2783 u_int nflags; 2784 u_int oflags; 2785 #ifdef ARM_HAS_VBAR 2786 const bool vector_page_p = false; 2787 #else 2788 const bool vector_page_p = (va == vector_page); 2789 #endif 2790 2791 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2792 2793 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2794 KDASSERT(((va | pa) & PGOFSET) == 0); 2795 2796 /* 2797 * Get a pointer to the page. Later on in this function, we 2798 * test for a managed page by checking pg != NULL. 2799 */ 2800 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2801 2802 nflags = 0; 2803 if (prot & VM_PROT_WRITE) 2804 nflags |= PVF_WRITE; 2805 if (prot & VM_PROT_EXECUTE) 2806 nflags |= PVF_EXEC; 2807 if (flags & PMAP_WIRED) 2808 nflags |= PVF_WIRED; 2809 2810 pmap_acquire_pmap_lock(pm); 2811 2812 /* 2813 * Fetch the L2 bucket which maps this page, allocating one if 2814 * necessary for user pmaps. 2815 */ 2816 if (pm == pmap_kernel()) 2817 l2b = pmap_get_l2_bucket(pm, va); 2818 else 2819 l2b = pmap_alloc_l2_bucket(pm, va); 2820 if (l2b == NULL) { 2821 if (flags & PMAP_CANFAIL) { 2822 pmap_release_pmap_lock(pm); 2823 return (ENOMEM); 2824 } 2825 panic("pmap_enter: failed to allocate L2 bucket"); 2826 } 2827 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2828 const pt_entry_t opte = *ptep; 2829 pt_entry_t npte = pa; 2830 oflags = 0; 2831 2832 if (opte) { 2833 /* 2834 * There is already a mapping at this address. 2835 * If the physical address is different, lookup the 2836 * vm_page. 2837 */ 2838 if (l2pte_pa(opte) != pa) 2839 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2840 else 2841 opg = pg; 2842 } else 2843 opg = NULL; 2844 2845 if (pg) { 2846 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2847 2848 /* 2849 * This is to be a managed mapping. 2850 */ 2851 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 2852 /* 2853 * - The access type indicates that we don't need 2854 * to do referenced emulation. 2855 * OR 2856 * - The physical page has already been referenced 2857 * so no need to re-do referenced emulation here. 2858 */ 2859 npte |= l2pte_set_readonly(L2_S_PROTO); 2860 2861 nflags |= PVF_REF; 2862 2863 if ((prot & VM_PROT_WRITE) != 0 && 2864 ((flags & VM_PROT_WRITE) != 0 || 2865 (md->pvh_attrs & PVF_MOD) != 0)) { 2866 /* 2867 * This is a writable mapping, and the 2868 * page's mod state indicates it has 2869 * already been modified. Make it 2870 * writable from the outset. 2871 */ 2872 npte = l2pte_set_writable(npte); 2873 nflags |= PVF_MOD; 2874 } 2875 } else { 2876 /* 2877 * Need to do page referenced emulation. 2878 */ 2879 npte |= L2_TYPE_INV; 2880 } 2881 2882 if (flags & ARM32_MMAP_WRITECOMBINE) { 2883 npte |= pte_l2_s_wc_mode; 2884 } else 2885 npte |= pte_l2_s_cache_mode; 2886 2887 if (pg == opg) { 2888 /* 2889 * We're changing the attrs of an existing mapping. 2890 */ 2891 #ifdef MULTIPROCESSOR 2892 KASSERT(uvm_page_locked_p(pg)); 2893 #endif 2894 oflags = pmap_modify_pv(md, pa, pm, va, 2895 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2896 PVF_MOD | PVF_REF, nflags); 2897 2898 #ifdef PMAP_CACHE_VIVT 2899 /* 2900 * We may need to flush the cache if we're 2901 * doing rw-ro... 2902 */ 2903 if (pm->pm_cstate.cs_cache_d && 2904 (oflags & PVF_NC) == 0 && 2905 l2pte_writable_p(opte) && 2906 (prot & VM_PROT_WRITE) == 0) 2907 cpu_dcache_wb_range(va, PAGE_SIZE); 2908 #endif 2909 } else { 2910 /* 2911 * New mapping, or changing the backing page 2912 * of an existing mapping. 2913 */ 2914 if (opg) { 2915 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2916 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2917 2918 /* 2919 * Replacing an existing mapping with a new one. 2920 * It is part of our managed memory so we 2921 * must remove it from the PV list 2922 */ 2923 #ifdef MULTIPROCESSOR 2924 KASSERT(uvm_page_locked_p(opg)); 2925 #endif 2926 pv = pmap_remove_pv(omd, opa, pm, va); 2927 pmap_vac_me_harder(omd, opa, pm, 0); 2928 oflags = pv->pv_flags; 2929 2930 #ifdef PMAP_CACHE_VIVT 2931 /* 2932 * If the old mapping was valid (ref/mod 2933 * emulation creates 'invalid' mappings 2934 * initially) then make sure to frob 2935 * the cache. 2936 */ 2937 if (!(oflags & PVF_NC) && l2pte_valid(opte)) { 2938 pmap_cache_wbinv_page(pm, va, true, 2939 oflags); 2940 } 2941 #endif 2942 } else 2943 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2944 if ((flags & PMAP_CANFAIL) == 0) 2945 panic("pmap_enter: no pv entries"); 2946 2947 if (pm != pmap_kernel()) 2948 pmap_free_l2_bucket(pm, l2b, 0); 2949 pmap_release_pmap_lock(pm); 2950 NPDEBUG(PDB_ENTER, 2951 printf("pmap_enter: ENOMEM\n")); 2952 return (ENOMEM); 2953 } 2954 2955 #ifdef MULTIPROCESSOR 2956 KASSERT(uvm_page_locked_p(pg)); 2957 #endif 2958 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2959 } 2960 } else { 2961 /* 2962 * We're mapping an unmanaged page. 2963 * These are always readable, and possibly writable, from 2964 * the get go as we don't need to track ref/mod status. 2965 */ 2966 npte |= l2pte_set_readonly(L2_S_PROTO); 2967 if (prot & VM_PROT_WRITE) 2968 npte = l2pte_set_writable(npte); 2969 2970 /* 2971 * Make sure the vector table is mapped cacheable 2972 */ 2973 if ((vector_page_p && pm != pmap_kernel()) 2974 || (flags & ARM32_MMAP_CACHEABLE)) { 2975 npte |= pte_l2_s_cache_mode; 2976 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 2977 npte |= pte_l2_s_wc_mode; 2978 } 2979 if (opg) { 2980 /* 2981 * Looks like there's an existing 'managed' mapping 2982 * at this address. 2983 */ 2984 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2985 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2986 2987 #ifdef MULTIPROCESSOR 2988 KASSERT(uvm_page_locked_p(opg)); 2989 #endif 2990 pv = pmap_remove_pv(omd, opa, pm, va); 2991 pmap_vac_me_harder(omd, opa, pm, 0); 2992 oflags = pv->pv_flags; 2993 2994 #ifdef PMAP_CACHE_VIVT 2995 if (!(oflags & PVF_NC) && l2pte_valid(opte)) { 2996 pmap_cache_wbinv_page(pm, va, true, oflags); 2997 } 2998 #endif 2999 pool_put(&pmap_pv_pool, pv); 3000 } 3001 } 3002 3003 /* 3004 * Make sure userland mappings get the right permissions 3005 */ 3006 if (!vector_page_p && pm != pmap_kernel()) { 3007 npte |= L2_S_PROT_U; 3008 } 3009 3010 /* 3011 * Keep the stats up to date 3012 */ 3013 if (opte == 0) { 3014 l2b->l2b_occupancy++; 3015 pm->pm_stats.resident_count++; 3016 } 3017 3018 NPDEBUG(PDB_ENTER, 3019 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3020 3021 /* 3022 * If this is just a wiring change, the two PTEs will be 3023 * identical, so there's no need to update the page table. 3024 */ 3025 if (npte != opte) { 3026 bool is_cached = pmap_is_cached(pm); 3027 3028 l2pte_set(ptep, npte, opte); 3029 PTE_SYNC(ptep); 3030 if (is_cached) { 3031 /* 3032 * We only need to frob the cache/tlb if this pmap 3033 * is current 3034 */ 3035 if (!vector_page_p && l2pte_valid(npte)) { 3036 /* 3037 * This mapping is likely to be accessed as 3038 * soon as we return to userland. Fix up the 3039 * L1 entry to avoid taking another 3040 * page/domain fault. 3041 */ 3042 pd_entry_t *pl1pd, l1pd; 3043 3044 pl1pd = pmap_l1_kva(pm) + L1_IDX(va); 3045 l1pd = l2b->l2b_phys | L1_C_DOM(pmap_domain(pm)) | 3046 L1_C_PROTO; 3047 if (*pl1pd != l1pd) { 3048 *pl1pd = l1pd; 3049 PTE_SYNC(pl1pd); 3050 } 3051 } 3052 } 3053 3054 pmap_tlb_flush_SE(pm, va, oflags); 3055 3056 NPDEBUG(PDB_ENTER, 3057 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3058 is_cached, pm->pm_cstate.cs_all)); 3059 3060 if (pg != NULL) { 3061 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3062 3063 #ifdef MULTIPROCESSOR 3064 KASSERT(uvm_page_locked_p(pg)); 3065 #endif 3066 pmap_vac_me_harder(md, pa, pm, va); 3067 } 3068 } 3069 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3070 if (pg) { 3071 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3072 3073 #ifdef MULTIPROCESSOR 3074 KASSERT(uvm_page_locked_p(pg)); 3075 #endif 3076 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3077 PMAP_VALIDATE_MD_PAGE(md); 3078 } 3079 #endif 3080 3081 pmap_release_pmap_lock(pm); 3082 3083 return (0); 3084 } 3085 3086 /* 3087 * pmap_remove() 3088 * 3089 * pmap_remove is responsible for nuking a number of mappings for a range 3090 * of virtual address space in the current pmap. To do this efficiently 3091 * is interesting, because in a number of cases a wide virtual address 3092 * range may be supplied that contains few actual mappings. So, the 3093 * optimisations are: 3094 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3095 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3096 * maybe do just a partial cache clean. This path of execution is 3097 * complicated by the fact that the cache must be flushed _before_ 3098 * the PTE is nuked, being a VAC :-) 3099 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3100 * all invalidations until pmap_update(), since pmap_remove_all() has 3101 * already flushed the cache. 3102 * 4. Maybe later fast-case a single page, but I don't think this is 3103 * going to make _that_ much difference overall. 3104 */ 3105 3106 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3107 3108 void 3109 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3110 { 3111 vaddr_t next_bucket; 3112 u_int cleanlist_idx, total, cnt; 3113 struct { 3114 vaddr_t va; 3115 pt_entry_t *ptep; 3116 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3117 u_int mappings; 3118 3119 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3120 "eva=%08lx\n", pm, sva, eva)); 3121 3122 /* 3123 * we lock in the pmap => pv_head direction 3124 */ 3125 pmap_acquire_pmap_lock(pm); 3126 3127 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3128 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3129 if (pm->pm_cstate.cs_tlb == 0) 3130 pm->pm_remove_all = true; 3131 } else 3132 cleanlist_idx = 0; 3133 3134 total = 0; 3135 3136 while (sva < eva) { 3137 /* 3138 * Do one L2 bucket's worth at a time. 3139 */ 3140 next_bucket = L2_NEXT_BUCKET(sva); 3141 if (next_bucket > eva) 3142 next_bucket = eva; 3143 3144 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3145 if (l2b == NULL) { 3146 sva = next_bucket; 3147 continue; 3148 } 3149 3150 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3151 3152 for (mappings = 0; 3153 sva < next_bucket; 3154 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3155 pt_entry_t opte = *ptep; 3156 3157 if (opte == 0) { 3158 /* Nothing here, move along */ 3159 continue; 3160 } 3161 3162 u_int flags = PVF_REF; 3163 paddr_t pa = l2pte_pa(opte); 3164 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3165 3166 /* 3167 * Update flags. In a number of circumstances, 3168 * we could cluster a lot of these and do a 3169 * number of sequential pages in one go. 3170 */ 3171 if (pg != NULL) { 3172 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3173 struct pv_entry *pv; 3174 3175 #ifdef MULTIPROCESSOR 3176 KASSERT(uvm_page_locked_p(pg)); 3177 #endif 3178 pv = pmap_remove_pv(md, pa, pm, sva); 3179 pmap_vac_me_harder(md, pa, pm, 0); 3180 if (pv != NULL) { 3181 if (pm->pm_remove_all == false) { 3182 flags = pv->pv_flags; 3183 } 3184 pool_put(&pmap_pv_pool, pv); 3185 } 3186 } 3187 mappings++; 3188 3189 if (!l2pte_valid(opte)) { 3190 /* 3191 * Ref/Mod emulation is still active for this 3192 * mapping, therefore it is has not yet been 3193 * accessed. No need to frob the cache/tlb. 3194 */ 3195 l2pte_reset(ptep); 3196 PTE_SYNC_CURRENT(pm, ptep); 3197 continue; 3198 } 3199 3200 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3201 /* Add to the clean list. */ 3202 cleanlist[cleanlist_idx].ptep = ptep; 3203 cleanlist[cleanlist_idx].va = 3204 sva | (flags & PVF_EXEC); 3205 cleanlist_idx++; 3206 } else 3207 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3208 /* Nuke everything if needed. */ 3209 #ifdef PMAP_CACHE_VIVT 3210 pmap_cache_wbinv_all(pm, PVF_EXEC); 3211 #endif 3212 pmap_tlb_flushID(pm); 3213 3214 /* 3215 * Roll back the previous PTE list, 3216 * and zero out the current PTE. 3217 */ 3218 for (cnt = 0; 3219 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3220 l2pte_reset(cleanlist[cnt].ptep); 3221 PTE_SYNC(cleanlist[cnt].ptep); 3222 } 3223 l2pte_reset(ptep); 3224 PTE_SYNC(ptep); 3225 cleanlist_idx++; 3226 pm->pm_remove_all = true; 3227 } else { 3228 l2pte_reset(ptep); 3229 PTE_SYNC(ptep); 3230 if (pm->pm_remove_all == false) { 3231 pmap_tlb_flush_SE(pm, sva, flags); 3232 } 3233 } 3234 } 3235 3236 /* 3237 * Deal with any left overs 3238 */ 3239 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3240 total += cleanlist_idx; 3241 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3242 vaddr_t va = cleanlist[cnt].va; 3243 if (pm->pm_cstate.cs_all != 0) { 3244 vaddr_t clva = va & ~PAGE_MASK; 3245 u_int flags = va & PVF_EXEC; 3246 #ifdef PMAP_CACHE_VIVT 3247 pmap_cache_wbinv_page(pm, clva, true, 3248 PVF_REF | PVF_WRITE | flags); 3249 #endif 3250 pmap_tlb_flush_SE(pm, clva, 3251 PVF_REF | flags); 3252 } 3253 l2pte_reset(cleanlist[cnt].ptep); 3254 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3255 } 3256 3257 /* 3258 * If it looks like we're removing a whole bunch 3259 * of mappings, it's faster to just write-back 3260 * the whole cache now and defer TLB flushes until 3261 * pmap_update() is called. 3262 */ 3263 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3264 cleanlist_idx = 0; 3265 else { 3266 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3267 #ifdef PMAP_CACHE_VIVT 3268 pmap_cache_wbinv_all(pm, PVF_EXEC); 3269 #endif 3270 pm->pm_remove_all = true; 3271 } 3272 } 3273 3274 pmap_free_l2_bucket(pm, l2b, mappings); 3275 pm->pm_stats.resident_count -= mappings; 3276 } 3277 3278 pmap_release_pmap_lock(pm); 3279 } 3280 3281 #ifdef PMAP_CACHE_VIPT 3282 static struct pv_entry * 3283 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3284 { 3285 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3286 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3287 struct pv_entry *pv; 3288 3289 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3290 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3291 3292 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3293 KASSERT(pv); 3294 KASSERT(pv->pv_flags & PVF_KENTRY); 3295 3296 /* 3297 * If we are removing a writeable mapping to a cached exec page, 3298 * if it's the last mapping then clear it execness other sync 3299 * the page to the icache. 3300 */ 3301 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3302 && (pv->pv_flags & PVF_WRITE) != 0) { 3303 if (SLIST_EMPTY(&md->pvh_list)) { 3304 md->pvh_attrs &= ~PVF_EXEC; 3305 PMAPCOUNT(exec_discarded_kremove); 3306 } else { 3307 pmap_syncicache_page(md, pa); 3308 PMAPCOUNT(exec_synced_kremove); 3309 } 3310 } 3311 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3312 3313 return pv; 3314 } 3315 #endif /* PMAP_CACHE_VIPT */ 3316 3317 /* 3318 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3319 * 3320 * We assume there is already sufficient KVM space available 3321 * to do this, as we can't allocate L2 descriptor tables/metadata 3322 * from here. 3323 */ 3324 void 3325 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3326 { 3327 #ifdef PMAP_CACHE_VIVT 3328 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3329 #endif 3330 #ifdef PMAP_CACHE_VIPT 3331 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3332 struct vm_page *opg; 3333 struct pv_entry *pv = NULL; 3334 #endif 3335 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3336 3337 NPDEBUG(PDB_KENTER, 3338 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3339 va, pa, prot)); 3340 3341 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3342 KDASSERT(l2b != NULL); 3343 3344 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3345 const pt_entry_t opte = *ptep; 3346 3347 if (opte == 0) { 3348 PMAPCOUNT(kenter_mappings); 3349 l2b->l2b_occupancy++; 3350 } else { 3351 PMAPCOUNT(kenter_remappings); 3352 #ifdef PMAP_CACHE_VIPT 3353 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3354 #ifdef DIAGNOSTIC 3355 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3356 #endif 3357 if (opg) { 3358 KASSERT(opg != pg); 3359 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3360 KASSERT((flags & PMAP_KMPAGE) == 0); 3361 pv = pmap_kremove_pg(opg, va); 3362 } 3363 #endif 3364 if (l2pte_valid(opte)) { 3365 #ifdef PMAP_CACHE_VIVT 3366 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3367 #endif 3368 cpu_tlb_flushD_SE(va); 3369 cpu_cpwait(); 3370 } 3371 } 3372 3373 const pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3374 | ((flags & PMAP_NOCACHE) 3375 ? 0 3376 : ((flags & PMAP_PTE) 3377 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3378 l2pte_set(ptep, npte, opte); 3379 PTE_SYNC(ptep); 3380 3381 if (pg) { 3382 #ifdef MULTIPROCESSOR 3383 KASSERT(uvm_page_locked_p(pg)); 3384 #endif 3385 if (flags & PMAP_KMPAGE) { 3386 KASSERT(md->urw_mappings == 0); 3387 KASSERT(md->uro_mappings == 0); 3388 KASSERT(md->krw_mappings == 0); 3389 KASSERT(md->kro_mappings == 0); 3390 #ifdef PMAP_CACHE_VIPT 3391 KASSERT(pv == NULL); 3392 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3393 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3394 /* if there is a color conflict, evict from cache. */ 3395 if (pmap_is_page_colored_p(md) 3396 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3397 PMAPCOUNT(vac_color_change); 3398 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3399 } else if (md->pvh_attrs & PVF_MULTCLR) { 3400 /* 3401 * If this page has multiple colors, expunge 3402 * them. 3403 */ 3404 PMAPCOUNT(vac_flush_lots2); 3405 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3406 } 3407 md->pvh_attrs &= PAGE_SIZE - 1; 3408 md->pvh_attrs |= PVF_KMPAGE 3409 | PVF_COLORED | PVF_DIRTY 3410 | (va & arm_cache_prefer_mask); 3411 #endif 3412 #ifdef PMAP_CACHE_VIVT 3413 md->pvh_attrs |= PVF_KMPAGE; 3414 #endif 3415 pmap_kmpages++; 3416 #ifdef PMAP_CACHE_VIPT 3417 } else { 3418 if (pv == NULL) { 3419 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3420 KASSERT(pv != NULL); 3421 } 3422 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3423 PVF_WIRED | PVF_KENTRY 3424 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3425 if ((prot & VM_PROT_WRITE) 3426 && !(md->pvh_attrs & PVF_NC)) 3427 md->pvh_attrs |= PVF_DIRTY; 3428 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3429 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3430 #endif 3431 } 3432 #ifdef PMAP_CACHE_VIPT 3433 } else { 3434 if (pv != NULL) 3435 pool_put(&pmap_pv_pool, pv); 3436 #endif 3437 } 3438 } 3439 3440 void 3441 pmap_kremove(vaddr_t va, vsize_t len) 3442 { 3443 vaddr_t next_bucket, eva; 3444 u_int mappings; 3445 3446 PMAPCOUNT(kenter_unmappings); 3447 3448 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3449 va, len)); 3450 3451 eva = va + len; 3452 3453 while (va < eva) { 3454 next_bucket = L2_NEXT_BUCKET(va); 3455 if (next_bucket > eva) 3456 next_bucket = eva; 3457 3458 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3459 KDASSERT(l2b != NULL); 3460 3461 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3462 pt_entry_t *ptep = sptep; 3463 mappings = 0; 3464 3465 while (va < next_bucket) { 3466 const pt_entry_t opte = *ptep; 3467 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3468 if (opg != NULL) { 3469 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3470 3471 if (omd->pvh_attrs & PVF_KMPAGE) { 3472 KASSERT(omd->urw_mappings == 0); 3473 KASSERT(omd->uro_mappings == 0); 3474 KASSERT(omd->krw_mappings == 0); 3475 KASSERT(omd->kro_mappings == 0); 3476 omd->pvh_attrs &= ~PVF_KMPAGE; 3477 #ifdef PMAP_CACHE_VIPT 3478 if (arm_cache_prefer_mask != 0) { 3479 omd->pvh_attrs &= ~PVF_WRITE; 3480 } 3481 #endif 3482 pmap_kmpages--; 3483 #ifdef PMAP_CACHE_VIPT 3484 } else { 3485 pool_put(&pmap_pv_pool, 3486 pmap_kremove_pg(opg, va)); 3487 #endif 3488 } 3489 } 3490 if (l2pte_valid(opte)) { 3491 #ifdef PMAP_CACHE_VIVT 3492 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3493 #endif 3494 cpu_tlb_flushD_SE(va); 3495 } 3496 if (opte) { 3497 l2pte_reset(ptep); 3498 mappings++; 3499 } 3500 va += PAGE_SIZE; 3501 ptep += PAGE_SIZE / L2_S_SIZE; 3502 } 3503 KDASSERT(mappings <= l2b->l2b_occupancy); 3504 l2b->l2b_occupancy -= mappings; 3505 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3506 } 3507 cpu_cpwait(); 3508 } 3509 3510 bool 3511 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3512 { 3513 struct l2_dtable *l2; 3514 pd_entry_t *pl1pd, l1pd; 3515 pt_entry_t *ptep, pte; 3516 paddr_t pa; 3517 u_int l1idx; 3518 3519 pmap_acquire_pmap_lock(pm); 3520 3521 l1idx = L1_IDX(va); 3522 pl1pd = pmap_l1_kva(pm) + l1idx; 3523 l1pd = *pl1pd; 3524 3525 if (l1pte_section_p(l1pd)) { 3526 /* 3527 * These should only happen for pmap_kernel() 3528 */ 3529 KDASSERT(pm == pmap_kernel()); 3530 pmap_release_pmap_lock(pm); 3531 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3532 if (l1pte_supersection_p(l1pd)) { 3533 pa = (l1pd & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3534 } else 3535 #endif 3536 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3537 } else { 3538 /* 3539 * Note that we can't rely on the validity of the L1 3540 * descriptor as an indication that a mapping exists. 3541 * We have to look it up in the L2 dtable. 3542 */ 3543 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3544 3545 if (l2 == NULL || 3546 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3547 pmap_release_pmap_lock(pm); 3548 return false; 3549 } 3550 3551 ptep = &ptep[l2pte_index(va)]; 3552 pte = *ptep; 3553 pmap_release_pmap_lock(pm); 3554 3555 if (pte == 0) 3556 return false; 3557 3558 switch (pte & L2_TYPE_MASK) { 3559 case L2_TYPE_L: 3560 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3561 break; 3562 3563 default: 3564 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3565 break; 3566 } 3567 } 3568 3569 if (pap != NULL) 3570 *pap = pa; 3571 3572 return true; 3573 } 3574 3575 void 3576 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3577 { 3578 struct l2_bucket *l2b; 3579 pt_entry_t *ptep, pte; 3580 vaddr_t next_bucket; 3581 3582 NPDEBUG(PDB_PROTECT, 3583 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3584 pm, sva, eva, prot)); 3585 3586 if ((prot & VM_PROT_READ) == 0) { 3587 pmap_remove(pm, sva, eva); 3588 return; 3589 } 3590 3591 if (prot & VM_PROT_WRITE) { 3592 /* 3593 * If this is a read->write transition, just ignore it and let 3594 * uvm_fault() take care of it later. 3595 */ 3596 return; 3597 } 3598 3599 pmap_acquire_pmap_lock(pm); 3600 3601 const bool flush = eva - sva >= PAGE_SIZE * 4; 3602 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3603 u_int flags = 0; 3604 3605 while (sva < eva) { 3606 next_bucket = L2_NEXT_BUCKET(sva); 3607 if (next_bucket > eva) 3608 next_bucket = eva; 3609 3610 l2b = pmap_get_l2_bucket(pm, sva); 3611 if (l2b == NULL) { 3612 sva = next_bucket; 3613 continue; 3614 } 3615 3616 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3617 3618 while (sva < next_bucket) { 3619 pte = *ptep; 3620 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3621 struct vm_page *pg; 3622 u_int f; 3623 3624 #ifdef PMAP_CACHE_VIVT 3625 /* 3626 * OK, at this point, we know we're doing 3627 * write-protect operation. If the pmap is 3628 * active, write-back the page. 3629 */ 3630 pmap_cache_wbinv_page(pm, sva, false, 3631 PVF_REF | PVF_WRITE); 3632 #endif 3633 3634 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3635 pte = l2pte_set_readonly(pte); 3636 *ptep = pte; 3637 PTE_SYNC(ptep); 3638 3639 if (pg != NULL) { 3640 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3641 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3642 3643 #ifdef MULTIPROCESSOR 3644 KASSERT(uvm_page_locked_p(pg)); 3645 #endif 3646 f = pmap_modify_pv(md, pa, pm, sva, 3647 clr_mask, 0); 3648 pmap_vac_me_harder(md, pa, pm, sva); 3649 } else { 3650 f = PVF_REF | PVF_EXEC; 3651 } 3652 3653 if (flush) { 3654 flags |= f; 3655 } else { 3656 pmap_tlb_flush_SE(pm, sva, f); 3657 } 3658 } 3659 3660 sva += PAGE_SIZE; 3661 ptep++; 3662 } 3663 } 3664 3665 if (flush) { 3666 if (PV_BEEN_EXECD(flags)) { 3667 pmap_tlb_flushID(pm); 3668 } else if (PV_BEEN_REFD(flags)) { 3669 pmap_tlb_flushD(pm); 3670 } 3671 } 3672 3673 pmap_release_pmap_lock(pm); 3674 } 3675 3676 void 3677 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3678 { 3679 struct l2_bucket *l2b; 3680 pt_entry_t *ptep; 3681 vaddr_t next_bucket; 3682 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3683 3684 NPDEBUG(PDB_EXEC, 3685 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3686 pm, sva, eva)); 3687 3688 pmap_acquire_pmap_lock(pm); 3689 3690 while (sva < eva) { 3691 next_bucket = L2_NEXT_BUCKET(sva); 3692 if (next_bucket > eva) 3693 next_bucket = eva; 3694 3695 l2b = pmap_get_l2_bucket(pm, sva); 3696 if (l2b == NULL) { 3697 sva = next_bucket; 3698 continue; 3699 } 3700 3701 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3702 sva < next_bucket; 3703 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3704 if (l2pte_valid(*ptep)) { 3705 cpu_icache_sync_range(sva, 3706 min(page_size, eva - sva)); 3707 } 3708 } 3709 } 3710 3711 pmap_release_pmap_lock(pm); 3712 } 3713 3714 void 3715 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3716 { 3717 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3718 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3719 3720 NPDEBUG(PDB_PROTECT, 3721 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3722 md, pa, prot)); 3723 3724 #ifdef MULTIPROCESSOR 3725 KASSERT(uvm_page_locked_p(pg)); 3726 #endif 3727 3728 switch(prot) { 3729 case VM_PROT_READ|VM_PROT_WRITE: 3730 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3731 pmap_clearbit(md, pa, PVF_EXEC); 3732 break; 3733 #endif 3734 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3735 break; 3736 3737 case VM_PROT_READ: 3738 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3739 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3740 break; 3741 #endif 3742 case VM_PROT_READ|VM_PROT_EXECUTE: 3743 pmap_clearbit(md, pa, PVF_WRITE); 3744 break; 3745 3746 default: 3747 pmap_page_remove(md, pa); 3748 break; 3749 } 3750 } 3751 3752 /* 3753 * pmap_clear_modify: 3754 * 3755 * Clear the "modified" attribute for a page. 3756 */ 3757 bool 3758 pmap_clear_modify(struct vm_page *pg) 3759 { 3760 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3761 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3762 bool rv; 3763 3764 #ifdef MULTIPROCESSOR 3765 KASSERT(uvm_page_locked_p(pg)); 3766 #endif 3767 3768 if (md->pvh_attrs & PVF_MOD) { 3769 rv = true; 3770 #ifdef PMAP_CACHE_VIPT 3771 /* 3772 * If we are going to clear the modified bit and there are 3773 * no other modified bits set, flush the page to memory and 3774 * mark it clean. 3775 */ 3776 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3777 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3778 #endif 3779 pmap_clearbit(md, pa, PVF_MOD); 3780 } else 3781 rv = false; 3782 3783 return (rv); 3784 } 3785 3786 /* 3787 * pmap_clear_reference: 3788 * 3789 * Clear the "referenced" attribute for a page. 3790 */ 3791 bool 3792 pmap_clear_reference(struct vm_page *pg) 3793 { 3794 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3795 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3796 bool rv; 3797 3798 #ifdef MULTIPROCESSOR 3799 KASSERT(uvm_page_locked_p(pg)); 3800 #endif 3801 3802 if (md->pvh_attrs & PVF_REF) { 3803 rv = true; 3804 pmap_clearbit(md, pa, PVF_REF); 3805 } else 3806 rv = false; 3807 3808 return (rv); 3809 } 3810 3811 /* 3812 * pmap_is_modified: 3813 * 3814 * Test if a page has the "modified" attribute. 3815 */ 3816 /* See <arm/arm32/pmap.h> */ 3817 3818 /* 3819 * pmap_is_referenced: 3820 * 3821 * Test if a page has the "referenced" attribute. 3822 */ 3823 /* See <arm/arm32/pmap.h> */ 3824 3825 int 3826 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3827 { 3828 struct l2_dtable *l2; 3829 struct l2_bucket *l2b; 3830 pd_entry_t *pl1pd, l1pd; 3831 pt_entry_t *ptep, pte; 3832 paddr_t pa; 3833 u_int l1idx; 3834 int rv = 0; 3835 3836 pmap_acquire_pmap_lock(pm); 3837 3838 l1idx = L1_IDX(va); 3839 3840 /* 3841 * If there is no l2_dtable for this address, then the process 3842 * has no business accessing it. 3843 * 3844 * Note: This will catch userland processes trying to access 3845 * kernel addresses. 3846 */ 3847 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3848 if (l2 == NULL) 3849 goto out; 3850 3851 /* 3852 * Likewise if there is no L2 descriptor table 3853 */ 3854 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3855 if (l2b->l2b_kva == NULL) 3856 goto out; 3857 3858 /* 3859 * Check the PTE itself. 3860 */ 3861 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3862 pte = *ptep; 3863 if (pte == 0) 3864 goto out; 3865 3866 /* 3867 * Catch a userland access to the vector page mapped at 0x0 3868 */ 3869 if (user && (pte & L2_S_PROT_U) == 0) 3870 goto out; 3871 3872 pa = l2pte_pa(pte); 3873 3874 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3875 /* 3876 * This looks like a good candidate for "page modified" 3877 * emulation... 3878 */ 3879 struct pv_entry *pv; 3880 struct vm_page *pg; 3881 3882 /* Extract the physical address of the page */ 3883 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3884 goto out; 3885 3886 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3887 3888 /* Get the current flags for this page. */ 3889 #ifdef MULTIPROCESSOR 3890 KASSERT(uvm_page_locked_p(pg)); 3891 #endif 3892 3893 pv = pmap_find_pv(md, pm, va); 3894 if (pv == NULL) { 3895 goto out; 3896 } 3897 3898 /* 3899 * Do the flags say this page is writable? If not then it 3900 * is a genuine write fault. If yes then the write fault is 3901 * our fault as we did not reflect the write access in the 3902 * PTE. Now we know a write has occurred we can correct this 3903 * and also set the modified bit 3904 */ 3905 if ((pv->pv_flags & PVF_WRITE) == 0) { 3906 goto out; 3907 } 3908 3909 NPDEBUG(PDB_FOLLOW, 3910 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3911 pm, va, pa)); 3912 3913 md->pvh_attrs |= PVF_REF | PVF_MOD; 3914 pv->pv_flags |= PVF_REF | PVF_MOD; 3915 #ifdef PMAP_CACHE_VIPT 3916 /* 3917 * If there are cacheable mappings for this page, mark it dirty. 3918 */ 3919 if ((md->pvh_attrs & PVF_NC) == 0) 3920 md->pvh_attrs |= PVF_DIRTY; 3921 #endif 3922 3923 /* 3924 * Re-enable write permissions for the page. No need to call 3925 * pmap_vac_me_harder(), since this is just a 3926 * modified-emulation fault, and the PVF_WRITE bit isn't 3927 * changing. We've already set the cacheable bits based on 3928 * the assumption that we can write to this page. 3929 */ 3930 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3931 PTE_SYNC(ptep); 3932 rv = 1; 3933 } else 3934 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3935 /* 3936 * This looks like a good candidate for "page referenced" 3937 * emulation. 3938 */ 3939 struct pv_entry *pv; 3940 struct vm_page *pg; 3941 3942 /* Extract the physical address of the page */ 3943 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3944 goto out; 3945 3946 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3947 3948 /* Get the current flags for this page. */ 3949 #ifdef MULTIPROCESSOR 3950 KASSERT(uvm_page_locked_p(pg)); 3951 #endif 3952 3953 pv = pmap_find_pv(md, pm, va); 3954 if (pv == NULL) { 3955 goto out; 3956 } 3957 3958 md->pvh_attrs |= PVF_REF; 3959 pv->pv_flags |= PVF_REF; 3960 3961 NPDEBUG(PDB_FOLLOW, 3962 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3963 pm, va, pa)); 3964 3965 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3966 PTE_SYNC(ptep); 3967 rv = 1; 3968 } 3969 3970 /* 3971 * We know there is a valid mapping here, so simply 3972 * fix up the L1 if necessary. 3973 */ 3974 pl1pd = pmap_l1_kva(pm) + l1idx; 3975 l1pd = l2b->l2b_phys | L1_C_DOM(pmap_domain(pm)) | L1_C_PROTO; 3976 if (*pl1pd != l1pd) { 3977 *pl1pd = l1pd; 3978 PTE_SYNC(pl1pd); 3979 rv = 1; 3980 } 3981 3982 #ifdef CPU_SA110 3983 /* 3984 * There are bugs in the rev K SA110. This is a check for one 3985 * of them. 3986 */ 3987 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3988 curcpu()->ci_arm_cpurev < 3) { 3989 /* Always current pmap */ 3990 if (l2pte_valid(pte)) { 3991 extern int kernel_debug; 3992 if (kernel_debug & 1) { 3993 struct proc *p = curlwp->l_proc; 3994 printf("prefetch_abort: page is already " 3995 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3996 printf("prefetch_abort: pc=%08lx proc=%p " 3997 "process=%s\n", va, p, p->p_comm); 3998 printf("prefetch_abort: far=%08x fs=%x\n", 3999 cpu_faultaddress(), cpu_faultstatus()); 4000 } 4001 #ifdef DDB 4002 if (kernel_debug & 2) 4003 Debugger(); 4004 #endif 4005 rv = 1; 4006 } 4007 } 4008 #endif /* CPU_SA110 */ 4009 4010 /* 4011 * If 'rv == 0' at this point, it generally indicates that there is a 4012 * stale TLB entry for the faulting address. That might be due to a 4013 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4014 */ 4015 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1 4016 && pmap_needs_pte_sync == 0) { 4017 pmap_needs_pte_sync = 1; 4018 PTE_SYNC(ptep); 4019 rv = 1; 4020 } 4021 4022 #ifdef DEBUG 4023 /* 4024 * If 'rv == 0' at this point, it generally indicates that there is a 4025 * stale TLB entry for the faulting address. This happens when two or 4026 * more processes are sharing an L1. Since we don't flush the TLB on 4027 * a context switch between such processes, we can take domain faults 4028 * for mappings which exist at the same VA in both processes. EVEN IF 4029 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4030 * example. 4031 * 4032 * This is extremely likely to happen if pmap_enter() updated the L1 4033 * entry for a recently entered mapping. In this case, the TLB is 4034 * flushed for the new mapping, but there may still be TLB entries for 4035 * other mappings belonging to other processes in the 1MB range 4036 * covered by the L1 entry. 4037 * 4038 * Since 'rv == 0', we know that the L1 already contains the correct 4039 * value, so the fault must be due to a stale TLB entry. 4040 * 4041 * Since we always need to flush the TLB anyway in the case where we 4042 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4043 * stale TLB entries dynamically. 4044 * 4045 * However, the above condition can ONLY happen if the current L1 is 4046 * being shared. If it happens when the L1 is unshared, it indicates 4047 * that other parts of the pmap are not doing their job WRT managing 4048 * the TLB. 4049 */ 4050 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4051 extern int last_fault_code; 4052 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4053 pm, va, ftype); 4054 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4055 l2, l2b, ptep, pl1pd); 4056 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4057 pte, l1pd, last_fault_code); 4058 #ifdef DDB 4059 extern int kernel_debug; 4060 4061 if (kernel_debug & 2) 4062 Debugger(); 4063 #endif 4064 } 4065 #endif 4066 4067 cpu_tlb_flushID_SE(va); 4068 cpu_cpwait(); 4069 4070 rv = 1; 4071 4072 out: 4073 pmap_release_pmap_lock(pm); 4074 4075 return (rv); 4076 } 4077 4078 /* 4079 * Routine: pmap_procwr 4080 * 4081 * Function: 4082 * Synchronize caches corresponding to [addr, addr+len) in p. 4083 * 4084 */ 4085 void 4086 pmap_procwr(struct proc *p, vaddr_t va, int len) 4087 { 4088 /* We only need to do anything if it is the current process. */ 4089 if (p == curproc) 4090 cpu_icache_sync_range(va, len); 4091 } 4092 4093 /* 4094 * Routine: pmap_unwire 4095 * Function: Clear the wired attribute for a map/virtual-address pair. 4096 * 4097 * In/out conditions: 4098 * The mapping must already exist in the pmap. 4099 */ 4100 void 4101 pmap_unwire(pmap_t pm, vaddr_t va) 4102 { 4103 struct l2_bucket *l2b; 4104 pt_entry_t *ptep, pte; 4105 struct vm_page *pg; 4106 paddr_t pa; 4107 4108 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4109 4110 pmap_acquire_pmap_lock(pm); 4111 4112 l2b = pmap_get_l2_bucket(pm, va); 4113 KDASSERT(l2b != NULL); 4114 4115 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4116 pte = *ptep; 4117 4118 /* Extract the physical address of the page */ 4119 pa = l2pte_pa(pte); 4120 4121 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4122 /* Update the wired bit in the pv entry for this page. */ 4123 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4124 4125 #ifdef MULTIPROCESSOR 4126 KASSERT(uvm_page_locked_p(pg)); 4127 #endif 4128 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4129 } 4130 4131 pmap_release_pmap_lock(pm); 4132 } 4133 4134 void 4135 pmap_activate(struct lwp *l) 4136 { 4137 extern int block_userspace_access; 4138 pmap_t opm, npm, rpm; 4139 uint32_t odacr, ndacr; 4140 int oldirqstate; 4141 4142 /* 4143 * If activating a non-current lwp or the current lwp is 4144 * already active, just return. 4145 */ 4146 if (l != curlwp || 4147 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4148 return; 4149 4150 npm = l->l_proc->p_vmspace->vm_map.pmap; 4151 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4152 (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4153 4154 /* 4155 * If TTB and DACR are unchanged, short-circuit all the 4156 * TLB/cache management stuff. 4157 */ 4158 if (pmap_previous_active_lwp != NULL) { 4159 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4160 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4161 (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4162 4163 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4164 goto all_done; 4165 } else 4166 opm = NULL; 4167 4168 PMAPCOUNT(activations); 4169 block_userspace_access = 1; 4170 4171 /* 4172 * If switching to a user vmspace which is different to the 4173 * most recent one, and the most recent one is potentially 4174 * live in the cache, we must write-back and invalidate the 4175 * entire cache. 4176 */ 4177 rpm = pmap_recent_user; 4178 4179 /* 4180 * XXXSCW: There's a corner case here which can leave turds in the cache as 4181 * reported in kern/41058. They're probably left over during tear-down and 4182 * switching away from an exiting process. Until the root cause is identified 4183 * and fixed, zap the cache when switching pmaps. This will result in a few 4184 * unnecessary cache flushes, but that's better than silently corrupting data. 4185 */ 4186 #if 0 4187 if (npm != pmap_kernel() && rpm && npm != rpm && 4188 rpm->pm_cstate.cs_cache) { 4189 rpm->pm_cstate.cs_cache = 0; 4190 #ifdef PMAP_CACHE_VIVT 4191 cpu_idcache_wbinv_all(); 4192 #endif 4193 } 4194 #else 4195 if (rpm) { 4196 rpm->pm_cstate.cs_cache = 0; 4197 if (npm == pmap_kernel()) 4198 pmap_recent_user = NULL; 4199 #ifdef PMAP_CACHE_VIVT 4200 cpu_idcache_wbinv_all(); 4201 #endif 4202 } 4203 #endif 4204 4205 /* No interrupts while we frob the TTB/DACR */ 4206 oldirqstate = disable_interrupts(IF32_bits); 4207 4208 #ifndef ARM_HAS_VBAR 4209 /* 4210 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4211 * entry corresponding to 'vector_page' in the incoming L1 table 4212 * before switching to it otherwise subsequent interrupts/exceptions 4213 * (including domain faults!) will jump into hyperspace. 4214 */ 4215 if (npm->pm_pl1vec != NULL) { 4216 cpu_tlb_flushID_SE((u_int)vector_page); 4217 cpu_cpwait(); 4218 *npm->pm_pl1vec = npm->pm_l1vec; 4219 PTE_SYNC(npm->pm_pl1vec); 4220 } 4221 #endif 4222 4223 cpu_domains(ndacr); 4224 4225 if (npm == pmap_kernel() || npm == rpm) { 4226 /* 4227 * Switching to a kernel thread, or back to the 4228 * same user vmspace as before... Simply update 4229 * the TTB (no TLB flush required) 4230 */ 4231 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4232 cpu_cpwait(); 4233 } else { 4234 /* 4235 * Otherwise, update TTB and flush TLB 4236 */ 4237 cpu_context_switch(npm->pm_l1->l1_physaddr); 4238 if (rpm != NULL) 4239 rpm->pm_cstate.cs_tlb = 0; 4240 } 4241 4242 restore_interrupts(oldirqstate); 4243 4244 block_userspace_access = 0; 4245 4246 all_done: 4247 /* 4248 * The new pmap is resident. Make sure it's marked 4249 * as resident in the cache/TLB. 4250 */ 4251 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4252 if (npm != pmap_kernel()) 4253 pmap_recent_user = npm; 4254 4255 /* The old pmap is not longer active */ 4256 if (opm != NULL) 4257 opm->pm_activated = false; 4258 4259 /* But the new one is */ 4260 npm->pm_activated = true; 4261 } 4262 4263 void 4264 pmap_deactivate(struct lwp *l) 4265 { 4266 4267 /* 4268 * If the process is exiting, make sure pmap_activate() does 4269 * a full MMU context-switch and cache flush, which we might 4270 * otherwise skip. See PR port-arm/38950. 4271 */ 4272 if (l->l_proc->p_sflag & PS_WEXIT) 4273 pmap_previous_active_lwp = NULL; 4274 4275 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4276 } 4277 4278 void 4279 pmap_update(pmap_t pm) 4280 { 4281 4282 if (pm->pm_remove_all) { 4283 /* 4284 * Finish up the pmap_remove_all() optimisation by flushing 4285 * the TLB. 4286 */ 4287 pmap_tlb_flushID(pm); 4288 pm->pm_remove_all = false; 4289 } 4290 4291 if (pmap_is_current(pm)) { 4292 /* 4293 * If we're dealing with a current userland pmap, move its L1 4294 * to the end of the LRU. 4295 */ 4296 if (pm != pmap_kernel()) 4297 pmap_use_l1(pm); 4298 4299 /* 4300 * We can assume we're done with frobbing the cache/tlb for 4301 * now. Make sure any future pmap ops don't skip cache/tlb 4302 * flushes. 4303 */ 4304 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4305 } 4306 4307 PMAPCOUNT(updates); 4308 4309 /* 4310 * make sure TLB/cache operations have completed. 4311 */ 4312 cpu_cpwait(); 4313 } 4314 4315 void 4316 pmap_remove_all(pmap_t pm) 4317 { 4318 4319 /* 4320 * The vmspace described by this pmap is about to be torn down. 4321 * Until pmap_update() is called, UVM will only make calls 4322 * to pmap_remove(). We can make life much simpler by flushing 4323 * the cache now, and deferring TLB invalidation to pmap_update(). 4324 */ 4325 #ifdef PMAP_CACHE_VIVT 4326 pmap_cache_wbinv_all(pm, PVF_EXEC); 4327 #endif 4328 pm->pm_remove_all = true; 4329 } 4330 4331 /* 4332 * Retire the given physical map from service. 4333 * Should only be called if the map contains no valid mappings. 4334 */ 4335 void 4336 pmap_destroy(pmap_t pm) 4337 { 4338 u_int count; 4339 4340 if (pm == NULL) 4341 return; 4342 4343 if (pm->pm_remove_all) { 4344 pmap_tlb_flushID(pm); 4345 pm->pm_remove_all = false; 4346 } 4347 4348 /* 4349 * Drop reference count 4350 */ 4351 mutex_enter(pm->pm_lock); 4352 count = --pm->pm_obj.uo_refs; 4353 mutex_exit(pm->pm_lock); 4354 if (count > 0) { 4355 if (pmap_is_current(pm)) { 4356 if (pm != pmap_kernel()) 4357 pmap_use_l1(pm); 4358 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4359 } 4360 return; 4361 } 4362 4363 /* 4364 * reference count is zero, free pmap resources and then free pmap. 4365 */ 4366 4367 #ifndef ARM_HAS_VBAR 4368 if (vector_page < KERNEL_BASE) { 4369 KDASSERT(!pmap_is_current(pm)); 4370 4371 /* Remove the vector page mapping */ 4372 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4373 pmap_update(pm); 4374 } 4375 #endif 4376 4377 LIST_REMOVE(pm, pm_list); 4378 4379 pmap_free_l1(pm); 4380 4381 if (pmap_recent_user == pm) 4382 pmap_recent_user = NULL; 4383 4384 uvm_obj_destroy(&pm->pm_obj, false); 4385 mutex_destroy(&pm->pm_obj_lock); 4386 pool_cache_put(&pmap_cache, pm); 4387 } 4388 4389 4390 /* 4391 * void pmap_reference(pmap_t pm) 4392 * 4393 * Add a reference to the specified pmap. 4394 */ 4395 void 4396 pmap_reference(pmap_t pm) 4397 { 4398 4399 if (pm == NULL) 4400 return; 4401 4402 pmap_use_l1(pm); 4403 4404 mutex_enter(pm->pm_lock); 4405 pm->pm_obj.uo_refs++; 4406 mutex_exit(pm->pm_lock); 4407 } 4408 4409 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4410 4411 static struct evcnt pmap_prefer_nochange_ev = 4412 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4413 static struct evcnt pmap_prefer_change_ev = 4414 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4415 4416 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4417 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4418 4419 void 4420 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4421 { 4422 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4423 vaddr_t va = *vap; 4424 vaddr_t diff = (hint - va) & mask; 4425 if (diff == 0) { 4426 pmap_prefer_nochange_ev.ev_count++; 4427 } else { 4428 pmap_prefer_change_ev.ev_count++; 4429 if (__predict_false(td)) 4430 va -= mask + 1; 4431 *vap = va + diff; 4432 } 4433 } 4434 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4435 4436 /* 4437 * pmap_zero_page() 4438 * 4439 * Zero a given physical page by mapping it at a page hook point. 4440 * In doing the zero page op, the page we zero is mapped cachable, as with 4441 * StrongARM accesses to non-cached pages are non-burst making writing 4442 * _any_ bulk data very slow. 4443 */ 4444 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4445 void 4446 pmap_zero_page_generic(paddr_t phys) 4447 { 4448 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4449 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4450 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4451 #endif 4452 #if defined(PMAP_CACHE_VIPT) 4453 /* Choose the last page color it had, if any */ 4454 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4455 #else 4456 const vsize_t va_offset = 0; 4457 #endif 4458 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 4459 /* 4460 * Is this page mapped at its natural color? 4461 * If we have all of memory mapped, then just convert PA to VA. 4462 */ 4463 const bool okcolor = va_offset == (phys & arm_cache_prefer_mask); 4464 const vaddr_t vdstp = KERNEL_BASE + (phys - physical_start); 4465 #else 4466 const bool okcolor = false; 4467 const vaddr_t vdstp = cdstp + va_offset; 4468 #endif 4469 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4470 4471 4472 #ifdef DEBUG 4473 if (!SLIST_EMPTY(&md->pvh_list)) 4474 panic("pmap_zero_page: page has mappings"); 4475 #endif 4476 4477 KDASSERT((phys & PGOFSET) == 0); 4478 4479 if (!okcolor) { 4480 /* 4481 * Hook in the page, zero it, and purge the cache for that 4482 * zeroed page. Invalidate the TLB as needed. 4483 */ 4484 *ptep = L2_S_PROTO | phys | 4485 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4486 PTE_SYNC(ptep); 4487 cpu_tlb_flushD_SE(cdstp + va_offset); 4488 cpu_cpwait(); 4489 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 4490 /* 4491 * If we are direct-mapped and our color isn't ok, then before 4492 * we bzero the page invalidate its contents from the cache and 4493 * reset the color to its natural color. 4494 */ 4495 cpu_dcache_inv_range(cdstp + va_offset, PAGE_SIZE); 4496 md->pvh_attrs &= ~arm_cache_prefer_mask; 4497 md->pvh_attrs |= (phys & arm_cache_prefer_mask); 4498 #endif 4499 } 4500 bzero_page(vdstp); 4501 if (!okcolor) { 4502 /* 4503 * Unmap the page. 4504 */ 4505 *ptep = 0; 4506 PTE_SYNC(ptep); 4507 cpu_tlb_flushD_SE(cdstp + va_offset); 4508 #ifdef PMAP_CACHE_VIVT 4509 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4510 #endif 4511 } 4512 #ifdef PMAP_CACHE_VIPT 4513 /* 4514 * This page is now cache resident so it now has a page color. 4515 * Any contents have been obliterated so clear the EXEC flag. 4516 */ 4517 if (!pmap_is_page_colored_p(md)) { 4518 PMAPCOUNT(vac_color_new); 4519 md->pvh_attrs |= PVF_COLORED; 4520 } 4521 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4522 md->pvh_attrs &= ~PVF_EXEC; 4523 PMAPCOUNT(exec_discarded_zero); 4524 } 4525 md->pvh_attrs |= PVF_DIRTY; 4526 #endif 4527 } 4528 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4529 4530 #if ARM_MMU_XSCALE == 1 4531 void 4532 pmap_zero_page_xscale(paddr_t phys) 4533 { 4534 #ifdef DEBUG 4535 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4536 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4537 4538 if (!SLIST_EMPTY(&md->pvh_list)) 4539 panic("pmap_zero_page: page has mappings"); 4540 #endif 4541 4542 KDASSERT((phys & PGOFSET) == 0); 4543 4544 /* 4545 * Hook in the page, zero it, and purge the cache for that 4546 * zeroed page. Invalidate the TLB as needed. 4547 */ 4548 *cdst_pte = L2_S_PROTO | phys | 4549 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4550 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4551 PTE_SYNC(cdst_pte); 4552 cpu_tlb_flushD_SE(cdstp); 4553 cpu_cpwait(); 4554 bzero_page(cdstp); 4555 xscale_cache_clean_minidata(); 4556 } 4557 #endif /* ARM_MMU_XSCALE == 1 */ 4558 4559 /* pmap_pageidlezero() 4560 * 4561 * The same as above, except that we assume that the page is not 4562 * mapped. This means we never have to flush the cache first. Called 4563 * from the idle loop. 4564 */ 4565 bool 4566 pmap_pageidlezero(paddr_t phys) 4567 { 4568 unsigned int i; 4569 int *ptr; 4570 bool rv = true; 4571 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4572 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4573 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4574 #endif 4575 #ifdef PMAP_CACHE_VIPT 4576 /* Choose the last page color it had, if any */ 4577 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4578 #else 4579 const vsize_t va_offset = 0; 4580 #endif 4581 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4582 4583 4584 #ifdef DEBUG 4585 if (!SLIST_EMPTY(&md->pvh_list)) 4586 panic("pmap_pageidlezero: page has mappings"); 4587 #endif 4588 4589 KDASSERT((phys & PGOFSET) == 0); 4590 4591 /* 4592 * Hook in the page, zero it, and purge the cache for that 4593 * zeroed page. Invalidate the TLB as needed. 4594 */ 4595 *ptep = L2_S_PROTO | phys | 4596 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4597 PTE_SYNC(ptep); 4598 cpu_tlb_flushD_SE(cdstp + va_offset); 4599 cpu_cpwait(); 4600 4601 for (i = 0, ptr = (int *)(cdstp + va_offset); 4602 i < (PAGE_SIZE / sizeof(int)); i++) { 4603 if (sched_curcpu_runnable_p() != 0) { 4604 /* 4605 * A process has become ready. Abort now, 4606 * so we don't keep it waiting while we 4607 * do slow memory access to finish this 4608 * page. 4609 */ 4610 rv = false; 4611 break; 4612 } 4613 *ptr++ = 0; 4614 } 4615 4616 #ifdef PMAP_CACHE_VIVT 4617 if (rv) 4618 /* 4619 * if we aborted we'll rezero this page again later so don't 4620 * purge it unless we finished it 4621 */ 4622 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4623 #elif defined(PMAP_CACHE_VIPT) 4624 /* 4625 * This page is now cache resident so it now has a page color. 4626 * Any contents have been obliterated so clear the EXEC flag. 4627 */ 4628 if (!pmap_is_page_colored_p(md)) { 4629 PMAPCOUNT(vac_color_new); 4630 md->pvh_attrs |= PVF_COLORED; 4631 } 4632 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4633 md->pvh_attrs &= ~PVF_EXEC; 4634 PMAPCOUNT(exec_discarded_zero); 4635 } 4636 #endif 4637 /* 4638 * Unmap the page. 4639 */ 4640 *ptep = 0; 4641 PTE_SYNC(ptep); 4642 cpu_tlb_flushD_SE(cdstp + va_offset); 4643 4644 return (rv); 4645 } 4646 4647 /* 4648 * pmap_copy_page() 4649 * 4650 * Copy one physical page into another, by mapping the pages into 4651 * hook points. The same comment regarding cachability as in 4652 * pmap_zero_page also applies here. 4653 */ 4654 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4655 void 4656 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4657 { 4658 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4659 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4660 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4661 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4662 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4663 #endif 4664 #ifdef PMAP_CACHE_VIPT 4665 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4666 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4667 #else 4668 const vsize_t src_va_offset = 0; 4669 const vsize_t dst_va_offset = 0; 4670 #endif 4671 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 4672 /* 4673 * Is this page mapped at its natural color? 4674 * If we have all of memory mapped, then just convert PA to VA. 4675 */ 4676 const bool src_okcolor = src_va_offset == (src & arm_cache_prefer_mask); 4677 const bool dst_okcolor = dst_va_offset == (dst & arm_cache_prefer_mask); 4678 const vaddr_t vsrcp = src_okcolor 4679 ? KERNEL_BASE + (src - physical_start) 4680 : csrcp + src_va_offset; 4681 const vaddr_t vdstp = KERNEL_BASE + (dst - physical_start); 4682 #else 4683 const bool src_okcolor = false; 4684 const bool dst_okcolor = false; 4685 const vaddr_t vsrcp = csrcp + src_va_offset; 4686 const vaddr_t vdstp = cdstp + dst_va_offset; 4687 #endif 4688 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4689 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4690 4691 #ifdef DEBUG 4692 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4693 panic("pmap_copy_page: dst page has mappings"); 4694 #endif 4695 4696 #ifdef PMAP_CACHE_VIPT 4697 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4698 #endif 4699 KDASSERT((src & PGOFSET) == 0); 4700 KDASSERT((dst & PGOFSET) == 0); 4701 4702 /* 4703 * Clean the source page. Hold the source page's lock for 4704 * the duration of the copy so that no other mappings can 4705 * be created while we have a potentially aliased mapping. 4706 */ 4707 #ifdef MULTIPROCESSOR 4708 KASSERT(uvm_page_locked_p(src_pg)); 4709 #endif 4710 #ifdef PMAP_CACHE_VIVT 4711 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4712 #endif 4713 4714 /* 4715 * Map the pages into the page hook points, copy them, and purge 4716 * the cache for the appropriate page. Invalidate the TLB 4717 * as required. 4718 */ 4719 if (!src_okcolor) { 4720 *src_ptep = L2_S_PROTO 4721 | src 4722 #ifdef PMAP_CACHE_VIPT 4723 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4724 #endif 4725 #ifdef PMAP_CACHE_VIVT 4726 | pte_l2_s_cache_mode 4727 #endif 4728 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4729 PTE_SYNC(src_ptep); 4730 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4731 cpu_cpwait(); 4732 } 4733 if (!dst_okcolor) { 4734 *dst_ptep = L2_S_PROTO | dst | 4735 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4736 PTE_SYNC(dst_ptep); 4737 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4738 cpu_cpwait(); 4739 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 4740 /* 4741 * If we are direct-mapped and our color isn't ok, then before 4742 * we bcopy to the new page invalidate its contents from the 4743 * cache and reset its color to its natural color. 4744 */ 4745 cpu_dcache_inv_range(cdstp + dst_va_offset, PAGE_SIZE); 4746 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 4747 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 4748 #endif 4749 } 4750 bcopy_page(vsrcp, vdstp); 4751 #ifdef PMAP_CACHE_VIVT 4752 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 4753 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 4754 #endif 4755 /* 4756 * Unmap the pages. 4757 */ 4758 if (!src_okcolor) { 4759 *src_ptep = 0; 4760 PTE_SYNC(src_ptep); 4761 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4762 cpu_cpwait(); 4763 } 4764 if (!dst_okcolor) { 4765 *dst_ptep = 0; 4766 PTE_SYNC(dst_ptep); 4767 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4768 cpu_cpwait(); 4769 } 4770 #ifdef PMAP_CACHE_VIPT 4771 /* 4772 * Now that the destination page is in the cache, mark it as colored. 4773 * If this was an exec page, discard it. 4774 */ 4775 if (!pmap_is_page_colored_p(dst_md)) { 4776 PMAPCOUNT(vac_color_new); 4777 dst_md->pvh_attrs |= PVF_COLORED; 4778 } 4779 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4780 dst_md->pvh_attrs &= ~PVF_EXEC; 4781 PMAPCOUNT(exec_discarded_copy); 4782 } 4783 dst_md->pvh_attrs |= PVF_DIRTY; 4784 #endif 4785 } 4786 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4787 4788 #if ARM_MMU_XSCALE == 1 4789 void 4790 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4791 { 4792 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4793 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4794 #ifdef DEBUG 4795 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4796 4797 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4798 panic("pmap_copy_page: dst page has mappings"); 4799 #endif 4800 4801 KDASSERT((src & PGOFSET) == 0); 4802 KDASSERT((dst & PGOFSET) == 0); 4803 4804 /* 4805 * Clean the source page. Hold the source page's lock for 4806 * the duration of the copy so that no other mappings can 4807 * be created while we have a potentially aliased mapping. 4808 */ 4809 #ifdef MULTIPROCESSOR 4810 KASSERT(uvm_page_locked_p(src_pg)); 4811 #endif 4812 #ifdef PMAP_CACHE_VIVT 4813 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4814 #endif 4815 4816 /* 4817 * Map the pages into the page hook points, copy them, and purge 4818 * the cache for the appropriate page. Invalidate the TLB 4819 * as required. 4820 */ 4821 *csrc_pte = L2_S_PROTO | src | 4822 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4823 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4824 PTE_SYNC(csrc_pte); 4825 *cdst_pte = L2_S_PROTO | dst | 4826 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4827 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4828 PTE_SYNC(cdst_pte); 4829 cpu_tlb_flushD_SE(csrcp); 4830 cpu_tlb_flushD_SE(cdstp); 4831 cpu_cpwait(); 4832 bcopy_page(csrcp, cdstp); 4833 xscale_cache_clean_minidata(); 4834 } 4835 #endif /* ARM_MMU_XSCALE == 1 */ 4836 4837 /* 4838 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4839 * 4840 * Return the start and end addresses of the kernel's virtual space. 4841 * These values are setup in pmap_bootstrap and are updated as pages 4842 * are allocated. 4843 */ 4844 void 4845 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4846 { 4847 *start = virtual_avail; 4848 *end = virtual_end; 4849 } 4850 4851 /* 4852 * Helper function for pmap_grow_l2_bucket() 4853 */ 4854 static inline int 4855 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4856 { 4857 struct l2_bucket *l2b; 4858 pt_entry_t *ptep; 4859 paddr_t pa; 4860 4861 if (uvm.page_init_done == false) { 4862 #ifdef PMAP_STEAL_MEMORY 4863 pv_addr_t pv; 4864 pmap_boot_pagealloc(PAGE_SIZE, 4865 #ifdef PMAP_CACHE_VIPT 4866 arm_cache_prefer_mask, 4867 va & arm_cache_prefer_mask, 4868 #else 4869 0, 0, 4870 #endif 4871 &pv); 4872 pa = pv.pv_pa; 4873 #else 4874 if (uvm_page_physget(&pa) == false) 4875 return (1); 4876 #endif /* PMAP_STEAL_MEMORY */ 4877 } else { 4878 struct vm_page *pg; 4879 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4880 if (pg == NULL) 4881 return (1); 4882 pa = VM_PAGE_TO_PHYS(pg); 4883 #ifdef PMAP_CACHE_VIPT 4884 #ifdef DIAGNOSTIC 4885 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4886 #endif 4887 /* 4888 * This new page must not have any mappings. Enter it via 4889 * pmap_kenter_pa and let that routine do the hard work. 4890 */ 4891 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4892 pmap_kenter_pa(va, pa, 4893 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 4894 #endif 4895 } 4896 4897 if (pap) 4898 *pap = pa; 4899 4900 PMAPCOUNT(pt_mappings); 4901 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4902 KDASSERT(l2b != NULL); 4903 4904 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4905 *ptep = L2_S_PROTO | pa | cache_mode | 4906 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4907 PTE_SYNC(ptep); 4908 memset((void *)va, 0, PAGE_SIZE); 4909 return (0); 4910 } 4911 4912 /* 4913 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4914 * used by pmap_growkernel(). 4915 */ 4916 static inline struct l2_bucket * 4917 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4918 { 4919 struct l2_dtable *l2; 4920 struct l2_bucket *l2b; 4921 u_short l1idx; 4922 vaddr_t nva; 4923 4924 l1idx = L1_IDX(va); 4925 4926 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4927 /* 4928 * No mapping at this address, as there is 4929 * no entry in the L1 table. 4930 * Need to allocate a new l2_dtable. 4931 */ 4932 nva = pmap_kernel_l2dtable_kva; 4933 if ((nva & PGOFSET) == 0) { 4934 /* 4935 * Need to allocate a backing page 4936 */ 4937 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4938 return (NULL); 4939 } 4940 4941 l2 = (struct l2_dtable *)nva; 4942 nva += sizeof(struct l2_dtable); 4943 4944 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4945 /* 4946 * The new l2_dtable straddles a page boundary. 4947 * Map in another page to cover it. 4948 */ 4949 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4950 return (NULL); 4951 } 4952 4953 pmap_kernel_l2dtable_kva = nva; 4954 4955 /* 4956 * Link it into the parent pmap 4957 */ 4958 pm->pm_l2[L2_IDX(l1idx)] = l2; 4959 } 4960 4961 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4962 4963 /* 4964 * Fetch pointer to the L2 page table associated with the address. 4965 */ 4966 if (l2b->l2b_kva == NULL) { 4967 pt_entry_t *ptep; 4968 4969 /* 4970 * No L2 page table has been allocated. Chances are, this 4971 * is because we just allocated the l2_dtable, above. 4972 */ 4973 nva = pmap_kernel_l2ptp_kva; 4974 ptep = (pt_entry_t *)nva; 4975 if ((nva & PGOFSET) == 0) { 4976 /* 4977 * Need to allocate a backing page 4978 */ 4979 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4980 &pmap_kernel_l2ptp_phys)) 4981 return (NULL); 4982 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4983 } 4984 4985 l2->l2_occupancy++; 4986 l2b->l2b_kva = ptep; 4987 l2b->l2b_l1idx = l1idx; 4988 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4989 4990 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4991 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4992 } 4993 4994 return (l2b); 4995 } 4996 4997 vaddr_t 4998 pmap_growkernel(vaddr_t maxkvaddr) 4999 { 5000 pmap_t kpm = pmap_kernel(); 5001 struct l1_ttable *l1; 5002 struct l2_bucket *l2b; 5003 pd_entry_t *pl1pd; 5004 int s; 5005 5006 if (maxkvaddr <= pmap_curmaxkvaddr) 5007 goto out; /* we are OK */ 5008 5009 NPDEBUG(PDB_GROWKERN, 5010 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5011 pmap_curmaxkvaddr, maxkvaddr)); 5012 5013 KDASSERT(maxkvaddr <= virtual_end); 5014 5015 /* 5016 * whoops! we need to add kernel PTPs 5017 */ 5018 5019 s = splhigh(); /* to be safe */ 5020 mutex_enter(kpm->pm_lock); 5021 5022 /* Map 1MB at a time */ 5023 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 5024 5025 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5026 KDASSERT(l2b != NULL); 5027 5028 /* Distribute new L1 entry to all other L1s */ 5029 SLIST_FOREACH(l1, &l1_list, l1_link) { 5030 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 5031 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 5032 L1_C_PROTO; 5033 PTE_SYNC(pl1pd); 5034 } 5035 } 5036 5037 /* 5038 * flush out the cache, expensive but growkernel will happen so 5039 * rarely 5040 */ 5041 cpu_dcache_wbinv_all(); 5042 cpu_tlb_flushD(); 5043 cpu_cpwait(); 5044 5045 mutex_exit(kpm->pm_lock); 5046 splx(s); 5047 5048 out: 5049 return (pmap_curmaxkvaddr); 5050 } 5051 5052 /************************ Utility routines ****************************/ 5053 5054 #ifndef ARM_HAS_VBAR 5055 /* 5056 * vector_page_setprot: 5057 * 5058 * Manipulate the protection of the vector page. 5059 */ 5060 void 5061 vector_page_setprot(int prot) 5062 { 5063 struct l2_bucket *l2b; 5064 pt_entry_t *ptep; 5065 5066 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5067 /* 5068 * If we are using VBAR to use the vectors in the kernel, then it's 5069 * already mapped in the kernel text so no need to anything here. 5070 */ 5071 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5072 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5073 return; 5074 } 5075 #endif 5076 5077 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5078 KDASSERT(l2b != NULL); 5079 5080 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5081 5082 *ptep = (*ptep & ~L2_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 5083 PTE_SYNC(ptep); 5084 cpu_tlb_flushD_SE(vector_page); 5085 cpu_cpwait(); 5086 } 5087 #endif 5088 5089 /* 5090 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5091 * Returns true if the mapping exists, else false. 5092 * 5093 * NOTE: This function is only used by a couple of arm-specific modules. 5094 * It is not safe to take any pmap locks here, since we could be right 5095 * in the middle of debugging the pmap anyway... 5096 * 5097 * It is possible for this routine to return false even though a valid 5098 * mapping does exist. This is because we don't lock, so the metadata 5099 * state may be inconsistent. 5100 * 5101 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5102 * a "section" mapping. 5103 */ 5104 bool 5105 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5106 { 5107 struct l2_dtable *l2; 5108 pd_entry_t *pl1pd, l1pd; 5109 pt_entry_t *ptep; 5110 u_short l1idx; 5111 5112 if (pm->pm_l1 == NULL) 5113 return false; 5114 5115 l1idx = L1_IDX(va); 5116 *pdp = pl1pd = pmap_l1_kva(pm) + l1idx; 5117 l1pd = *pl1pd; 5118 5119 if (l1pte_section_p(l1pd)) { 5120 *ptp = NULL; 5121 return true; 5122 } 5123 5124 if (pm->pm_l2 == NULL) 5125 return false; 5126 5127 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5128 5129 if (l2 == NULL || 5130 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5131 return false; 5132 } 5133 5134 *ptp = &ptep[l2pte_index(va)]; 5135 return true; 5136 } 5137 5138 bool 5139 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5140 { 5141 5142 if (pm->pm_l1 == NULL) 5143 return false; 5144 5145 *pdp = pmap_l1_kva(pm) + L1_IDX(va); 5146 5147 return true; 5148 } 5149 5150 /************************ Bootstrapping routines ****************************/ 5151 5152 static void 5153 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5154 { 5155 int i; 5156 5157 l1->l1_kva = l1pt; 5158 l1->l1_domain_use_count = 0; 5159 l1->l1_domain_first = 0; 5160 5161 for (i = 0; i < PMAP_DOMAINS; i++) 5162 l1->l1_domain_free[i] = i + 1; 5163 5164 /* 5165 * Copy the kernel's L1 entries to each new L1. 5166 */ 5167 if (pmap_initialized) 5168 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5169 5170 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5171 &l1->l1_physaddr) == false) 5172 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5173 5174 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5175 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5176 } 5177 5178 /* 5179 * pmap_bootstrap() is called from the board-specific initarm() routine 5180 * once the kernel L1/L2 descriptors tables have been set up. 5181 * 5182 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5183 * spread over a number of disparate files/functions. 5184 * 5185 * We are passed the following parameters 5186 * - kernel_l1pt 5187 * This is a pointer to the base of the kernel's L1 translation table. 5188 * - vstart 5189 * 1MB-aligned start of managed kernel virtual memory. 5190 * - vend 5191 * 1MB-aligned end of managed kernel virtual memory. 5192 * 5193 * We use the first parameter to build the metadata (struct l1_ttable and 5194 * struct l2_dtable) necessary to track kernel mappings. 5195 */ 5196 #define PMAP_STATIC_L2_SIZE 16 5197 void 5198 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5199 { 5200 static struct l1_ttable static_l1; 5201 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5202 struct l1_ttable *l1 = &static_l1; 5203 struct l2_dtable *l2; 5204 struct l2_bucket *l2b; 5205 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5206 pmap_t pm = pmap_kernel(); 5207 pd_entry_t pde; 5208 pt_entry_t *ptep; 5209 paddr_t pa; 5210 vaddr_t va; 5211 vsize_t size; 5212 int nptes, l1idx, l2idx, l2next = 0; 5213 5214 /* 5215 * Initialise the kernel pmap object 5216 */ 5217 pm->pm_l1 = l1; 5218 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5219 pm->pm_activated = true; 5220 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5221 5222 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5223 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5224 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5225 5226 /* 5227 * Scan the L1 translation table created by initarm() and create 5228 * the required metadata for all valid mappings found in it. 5229 */ 5230 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5231 pde = l1pt[l1idx]; 5232 5233 /* 5234 * We're only interested in Coarse mappings. 5235 * pmap_extract() can deal with section mappings without 5236 * recourse to checking L2 metadata. 5237 */ 5238 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5239 continue; 5240 5241 /* 5242 * Lookup the KVA of this L2 descriptor table 5243 */ 5244 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5245 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5246 if (ptep == NULL) { 5247 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5248 (u_int)l1idx << L1_S_SHIFT, pa); 5249 } 5250 5251 /* 5252 * Fetch the associated L2 metadata structure. 5253 * Allocate a new one if necessary. 5254 */ 5255 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5256 if (l2next == PMAP_STATIC_L2_SIZE) 5257 panic("pmap_bootstrap: out of static L2s"); 5258 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5259 } 5260 5261 /* 5262 * One more L1 slot tracked... 5263 */ 5264 l2->l2_occupancy++; 5265 5266 /* 5267 * Fill in the details of the L2 descriptor in the 5268 * appropriate bucket. 5269 */ 5270 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5271 l2b->l2b_kva = ptep; 5272 l2b->l2b_phys = pa; 5273 l2b->l2b_l1idx = l1idx; 5274 5275 /* 5276 * Establish an initial occupancy count for this descriptor 5277 */ 5278 for (l2idx = 0; 5279 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5280 l2idx++) { 5281 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5282 l2b->l2b_occupancy++; 5283 } 5284 } 5285 5286 /* 5287 * Make sure the descriptor itself has the correct cache mode. 5288 * If not, fix it, but whine about the problem. Port-meisters 5289 * should consider this a clue to fix up their initarm() 5290 * function. :) 5291 */ 5292 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5293 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5294 "L2 pte @ %p\n", ptep); 5295 } 5296 } 5297 5298 /* 5299 * Ensure the primary (kernel) L1 has the correct cache mode for 5300 * a page table. Bitch if it is not correctly set. 5301 */ 5302 for (va = (vaddr_t)l1pt; 5303 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5304 if (pmap_set_pt_cache_mode(l1pt, va)) 5305 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5306 "primary L1 @ 0x%lx\n", va); 5307 } 5308 5309 cpu_dcache_wbinv_all(); 5310 cpu_tlb_flushID(); 5311 cpu_cpwait(); 5312 5313 /* 5314 * now we allocate the "special" VAs which are used for tmp mappings 5315 * by the pmap (and other modules). we allocate the VAs by advancing 5316 * virtual_avail (note that there are no pages mapped at these VAs). 5317 * 5318 * Managed KVM space start from wherever initarm() tells us. 5319 */ 5320 virtual_avail = vstart; 5321 virtual_end = vend; 5322 5323 #ifdef PMAP_CACHE_VIPT 5324 /* 5325 * If we have a VIPT cache, we need one page/pte per possible alias 5326 * page so we won't violate cache aliasing rules. 5327 */ 5328 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5329 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5330 #else 5331 nptes = 1; 5332 #endif 5333 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5334 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5335 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5336 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5337 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5338 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5339 (void *)&msgbufaddr, NULL); 5340 5341 /* 5342 * Allocate a range of kernel virtual address space to be used 5343 * for L2 descriptor tables and metadata allocation in 5344 * pmap_growkernel(). 5345 */ 5346 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5347 pmap_alloc_specials(&virtual_avail, 5348 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5349 &pmap_kernel_l2ptp_kva, NULL); 5350 5351 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5352 pmap_alloc_specials(&virtual_avail, 5353 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5354 &pmap_kernel_l2dtable_kva, NULL); 5355 5356 /* 5357 * init the static-global locks and global pmap list. 5358 */ 5359 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 5360 5361 /* 5362 * We can now initialise the first L1's metadata. 5363 */ 5364 SLIST_INIT(&l1_list); 5365 TAILQ_INIT(&l1_lru_list); 5366 pmap_init_l1(l1, l1pt); 5367 5368 #ifndef ARM_HAS_VBAR 5369 /* Set up vector page L1 details, if necessary */ 5370 if (vector_page < KERNEL_BASE) { 5371 pm->pm_pl1vec = pmap_l1_kva(pm) + L1_IDX(vector_page); 5372 l2b = pmap_get_l2_bucket(pm, vector_page); 5373 KDASSERT(l2b != NULL); 5374 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5375 L1_C_DOM(pmap_domain(pm)); 5376 } else 5377 pm->pm_pl1vec = NULL; 5378 #endif 5379 5380 /* 5381 * Initialize the pmap cache 5382 */ 5383 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5384 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5385 LIST_INIT(&pmap_pmaps); 5386 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5387 5388 /* 5389 * Initialize the pv pool. 5390 */ 5391 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5392 &pmap_bootstrap_pv_allocator, IPL_NONE); 5393 5394 /* 5395 * Initialize the L2 dtable pool and cache. 5396 */ 5397 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5398 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5399 5400 /* 5401 * Initialise the L2 descriptor table pool and cache 5402 */ 5403 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5404 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5405 pmap_l2ptp_ctor, NULL, NULL); 5406 5407 cpu_dcache_wbinv_all(); 5408 } 5409 5410 static int 5411 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5412 { 5413 pd_entry_t *pdep, pde; 5414 pt_entry_t *ptep, pte; 5415 vaddr_t pa; 5416 int rv = 0; 5417 5418 /* 5419 * Make sure the descriptor itself has the correct cache mode 5420 */ 5421 pdep = &kl1[L1_IDX(va)]; 5422 pde = *pdep; 5423 5424 if (l1pte_section_p(pde)) { 5425 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 5426 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5427 *pdep = (pde & ~L1_S_CACHE_MASK) | 5428 pte_l1_s_cache_mode_pt; 5429 PTE_SYNC(pdep); 5430 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5431 rv = 1; 5432 } 5433 } else { 5434 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5435 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5436 if (ptep == NULL) 5437 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5438 5439 ptep = &ptep[l2pte_index(va)]; 5440 pte = *ptep; 5441 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5442 *ptep = (pte & ~L2_S_CACHE_MASK) | 5443 pte_l2_s_cache_mode_pt; 5444 PTE_SYNC(ptep); 5445 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5446 rv = 1; 5447 } 5448 } 5449 5450 return (rv); 5451 } 5452 5453 static void 5454 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5455 { 5456 vaddr_t va = *availp; 5457 struct l2_bucket *l2b; 5458 5459 if (ptep) { 5460 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5461 if (l2b == NULL) 5462 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5463 5464 if (ptep) 5465 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5466 } 5467 5468 *vap = va; 5469 *availp = va + (PAGE_SIZE * pages); 5470 } 5471 5472 void 5473 pmap_init(void) 5474 { 5475 5476 /* 5477 * Set the available memory vars - These do not map to real memory 5478 * addresses and cannot as the physical memory is fragmented. 5479 * They are used by ps for %mem calculations. 5480 * One could argue whether this should be the entire memory or just 5481 * the memory that is useable in a user process. 5482 */ 5483 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5484 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5485 5486 /* 5487 * Now we need to free enough pv_entry structures to allow us to get 5488 * the kmem_map/kmem_object allocated and inited (done after this 5489 * function is finished). to do this we allocate one bootstrap page out 5490 * of kernel_map and use it to provide an initial pool of pv_entry 5491 * structures. we never free this page. 5492 */ 5493 pool_setlowat(&pmap_pv_pool, 5494 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5495 5496 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5497 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5498 UVM_KMF_WIRED|UVM_KMF_ZERO); 5499 5500 pmap_initialized = true; 5501 } 5502 5503 static vaddr_t last_bootstrap_page = 0; 5504 static void *free_bootstrap_pages = NULL; 5505 5506 static void * 5507 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5508 { 5509 extern void *pool_page_alloc(struct pool *, int); 5510 vaddr_t new_page; 5511 void *rv; 5512 5513 if (pmap_initialized) 5514 return (pool_page_alloc(pp, flags)); 5515 5516 if (free_bootstrap_pages) { 5517 rv = free_bootstrap_pages; 5518 free_bootstrap_pages = *((void **)rv); 5519 return (rv); 5520 } 5521 5522 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5523 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5524 5525 KASSERT(new_page > last_bootstrap_page); 5526 last_bootstrap_page = new_page; 5527 return ((void *)new_page); 5528 } 5529 5530 static void 5531 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5532 { 5533 extern void pool_page_free(struct pool *, void *); 5534 5535 if ((vaddr_t)v <= last_bootstrap_page) { 5536 *((void **)v) = free_bootstrap_pages; 5537 free_bootstrap_pages = v; 5538 return; 5539 } 5540 5541 if (pmap_initialized) { 5542 pool_page_free(pp, v); 5543 return; 5544 } 5545 } 5546 5547 /* 5548 * pmap_postinit() 5549 * 5550 * This routine is called after the vm and kmem subsystems have been 5551 * initialised. This allows the pmap code to perform any initialisation 5552 * that can only be done one the memory allocation is in place. 5553 */ 5554 void 5555 pmap_postinit(void) 5556 { 5557 extern paddr_t physical_start, physical_end; 5558 struct l1_ttable *l1; 5559 struct pglist plist; 5560 struct vm_page *m; 5561 pd_entry_t *pl1pt; 5562 vaddr_t va, eva; 5563 u_int loop, needed; 5564 int error; 5565 5566 pool_cache_setlowat(&pmap_l2ptp_cache, 5567 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5568 pool_cache_setlowat(&pmap_l2dtable_cache, 5569 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5570 5571 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5572 needed -= 1; 5573 5574 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 5575 5576 for (loop = 0; loop < needed; loop++, l1++) { 5577 /* Allocate a L1 page table */ 5578 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5579 if (va == 0) 5580 panic("Cannot allocate L1 KVM"); 5581 5582 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5583 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 5584 if (error) 5585 panic("Cannot allocate L1 physical pages"); 5586 5587 m = TAILQ_FIRST(&plist); 5588 eva = va + L1_TABLE_SIZE; 5589 pl1pt = (pd_entry_t *)va; 5590 5591 while (m && va < eva) { 5592 paddr_t pa = VM_PAGE_TO_PHYS(m); 5593 5594 pmap_kenter_pa(va, pa, 5595 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5596 5597 va += PAGE_SIZE; 5598 m = TAILQ_NEXT(m, pageq.queue); 5599 } 5600 5601 #ifdef DIAGNOSTIC 5602 if (m) 5603 panic("pmap_alloc_l1pt: pglist not empty"); 5604 #endif /* DIAGNOSTIC */ 5605 5606 pmap_init_l1(l1, pl1pt); 5607 } 5608 5609 #ifdef DEBUG 5610 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5611 needed); 5612 #endif 5613 } 5614 5615 /* 5616 * Note that the following routines are used by board-specific initialisation 5617 * code to configure the initial kernel page tables. 5618 * 5619 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5620 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5621 * behaviour of the old pmap, and provides an easy migration path for 5622 * initial bring-up of the new pmap on existing ports. Fortunately, 5623 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5624 * will be deprecated. 5625 * 5626 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5627 * tables. 5628 */ 5629 5630 /* 5631 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5632 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5633 * find them as necessary. 5634 * 5635 * Note that the data on this list MUST remain valid after initarm() returns, 5636 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5637 */ 5638 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5639 5640 static vaddr_t 5641 kernel_pt_lookup(paddr_t pa) 5642 { 5643 pv_addr_t *pv; 5644 5645 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5646 #ifndef ARM32_NEW_VM_LAYOUT 5647 if (pv->pv_pa == (pa & ~PGOFSET)) 5648 return (pv->pv_va | (pa & PGOFSET)); 5649 #else 5650 if (pv->pv_pa == pa) 5651 return (pv->pv_va); 5652 #endif 5653 } 5654 return (0); 5655 } 5656 5657 /* 5658 * pmap_map_section: 5659 * 5660 * Create a single section mapping. 5661 */ 5662 void 5663 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5664 { 5665 pd_entry_t *pde = (pd_entry_t *) l1pt; 5666 pd_entry_t fl; 5667 5668 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5669 5670 switch (cache) { 5671 case PTE_NOCACHE: 5672 default: 5673 fl = 0; 5674 break; 5675 5676 case PTE_CACHE: 5677 fl = pte_l1_s_cache_mode; 5678 break; 5679 5680 case PTE_PAGETABLE: 5681 fl = pte_l1_s_cache_mode_pt; 5682 break; 5683 } 5684 5685 pde[L1_IDX(va)] = L1_S_PROTO | pa | 5686 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5687 PTE_SYNC(&pde[L1_IDX(va)]); 5688 } 5689 5690 /* 5691 * pmap_map_entry: 5692 * 5693 * Create a single page mapping. 5694 */ 5695 void 5696 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5697 { 5698 pd_entry_t *pde = (pd_entry_t *) l1pt; 5699 pt_entry_t npte; 5700 pt_entry_t *ptep; 5701 5702 KASSERT(((va | pa) & PGOFSET) == 0); 5703 5704 switch (cache) { 5705 case PTE_NOCACHE: 5706 default: 5707 npte = 0; 5708 break; 5709 5710 case PTE_CACHE: 5711 npte = pte_l2_s_cache_mode; 5712 break; 5713 5714 case PTE_PAGETABLE: 5715 npte = pte_l2_s_cache_mode_pt; 5716 break; 5717 } 5718 5719 if ((pde[L1_IDX(va)] & L1_TYPE_MASK) != L1_TYPE_C) 5720 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5721 5722 #ifndef ARM32_NEW_VM_LAYOUT 5723 ptep = (pt_entry_t *) 5724 kernel_pt_lookup(pde[L1_IDX(va)] & L2_S_FRAME); 5725 #else 5726 ptep = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5727 #endif 5728 if (ptep == NULL) 5729 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5730 5731 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5732 #ifndef ARM32_NEW_VM_LAYOUT 5733 ptep += (va >> PGSHIFT) & 0x3ff; 5734 #else 5735 ptep += l2pte_index(va); 5736 #endif 5737 l2pte_set(ptep, npte, 0); 5738 PTE_SYNC(ptep); 5739 } 5740 5741 /* 5742 * pmap_link_l2pt: 5743 * 5744 * Link the L2 page table specified by "l2pv" into the L1 5745 * page table at the slot for "va". 5746 */ 5747 void 5748 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5749 { 5750 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5751 u_int slot = L1_IDX(va); 5752 5753 #ifndef ARM32_NEW_VM_LAYOUT 5754 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5755 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5756 #endif 5757 5758 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5759 5760 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5761 #ifdef ARM32_NEW_VM_LAYOUT 5762 PTE_SYNC(&pde[slot]); 5763 #else 5764 for (u_int off = 0, i = 0; off < PAGE_SIZE; off += L2_T_SIZE, i++) { 5765 pde[slot + i] = proto | (l2pv->pv_pa + off); 5766 } 5767 PTE_SYNC_RANGE(&pde[slot + 0], PAGE_SIZE / L2_T_SIZE); 5768 #endif 5769 5770 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5771 } 5772 5773 /* 5774 * pmap_map_chunk: 5775 * 5776 * Map a chunk of memory using the most efficient mappings 5777 * possible (section, large page, small page) into the 5778 * provided L1 and L2 tables at the specified virtual address. 5779 */ 5780 vsize_t 5781 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5782 int prot, int cache) 5783 { 5784 pd_entry_t *pdep = (pd_entry_t *) l1pt; 5785 pt_entry_t *pte, f1, f2s, f2l; 5786 vsize_t resid; 5787 int i; 5788 5789 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5790 5791 if (l1pt == 0) 5792 panic("pmap_map_chunk: no L1 table provided"); 5793 5794 #ifdef VERBOSE_INIT_ARM 5795 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5796 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5797 #endif 5798 5799 switch (cache) { 5800 case PTE_NOCACHE: 5801 default: 5802 f1 = 0; 5803 f2l = 0; 5804 f2s = 0; 5805 break; 5806 5807 case PTE_CACHE: 5808 f1 = pte_l1_s_cache_mode; 5809 f2l = pte_l2_l_cache_mode; 5810 f2s = pte_l2_s_cache_mode; 5811 break; 5812 5813 case PTE_PAGETABLE: 5814 f1 = pte_l1_s_cache_mode_pt; 5815 f2l = pte_l2_l_cache_mode_pt; 5816 f2s = pte_l2_s_cache_mode_pt; 5817 break; 5818 } 5819 5820 size = resid; 5821 5822 while (resid > 0) { 5823 size_t l1idx = L1_IDX(va); 5824 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5825 /* See if we can use a supersection mapping. */ 5826 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 5827 /* Supersection are always domain 0 */ 5828 pd_entry_t pde = L1_SS_PROTO | pa | 5829 L1_S_PROT(PTE_KERNEL, prot) | f1; 5830 #ifdef VERBOSE_INIT_ARM 5831 printf("sS"); 5832 #endif 5833 for (size_t s = l1idx, 5834 e = s + L1_SS_SIZE / L1_S_SIZE; 5835 s < e; 5836 s++) { 5837 pdep[s] = pde; 5838 PTE_SYNC(&pdep[s]); 5839 } 5840 va += L1_SS_SIZE; 5841 pa += L1_SS_SIZE; 5842 resid -= L1_SS_SIZE; 5843 continue; 5844 } 5845 #endif 5846 /* See if we can use a section mapping. */ 5847 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5848 #ifdef VERBOSE_INIT_ARM 5849 printf("S"); 5850 #endif 5851 pdep[l1idx] = L1_S_PROTO | pa | 5852 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5853 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5854 PTE_SYNC(&pdep[l1idx]); 5855 va += L1_S_SIZE; 5856 pa += L1_S_SIZE; 5857 resid -= L1_S_SIZE; 5858 continue; 5859 } 5860 5861 /* 5862 * Ok, we're going to use an L2 table. Make sure 5863 * one is actually in the corresponding L1 slot 5864 * for the current VA. 5865 */ 5866 if ((pdep[l1idx] & L1_TYPE_MASK) != L1_TYPE_C) 5867 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5868 5869 #ifndef ARM32_NEW_VM_LAYOUT 5870 pte = (pt_entry_t *) 5871 kernel_pt_lookup(pdep[l1idx] & L2_S_FRAME); 5872 #else 5873 pte = (pt_entry_t *) kernel_pt_lookup( 5874 pdep[l1idx] & L1_C_ADDR_MASK); 5875 #endif 5876 if (pte == NULL) 5877 panic("pmap_map_chunk: can't find L2 table for VA" 5878 "0x%08lx", va); 5879 5880 /* See if we can use a L2 large page mapping. */ 5881 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5882 #ifdef VERBOSE_INIT_ARM 5883 printf("L"); 5884 #endif 5885 for (i = 0; i < 16; i++) { 5886 #ifndef ARM32_NEW_VM_LAYOUT 5887 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5888 L2_L_PROTO | pa | 5889 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5890 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5891 #else 5892 pte[l2pte_index(va) + i] = 5893 L2_L_PROTO | pa | 5894 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5895 PTE_SYNC(&pte[l2pte_index(va) + i]); 5896 #endif 5897 } 5898 va += L2_L_SIZE; 5899 pa += L2_L_SIZE; 5900 resid -= L2_L_SIZE; 5901 continue; 5902 } 5903 5904 /* Use a small page mapping. */ 5905 #ifdef VERBOSE_INIT_ARM 5906 printf("P"); 5907 #endif 5908 pt_entry_t npte = 5909 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5910 #ifndef ARM32_NEW_VM_LAYOUT 5911 pt_entry_t *ptep = &pte[(va >> PGSHIFT) & 0x3ff]; 5912 #else 5913 pt_entry_t *ptep = &pte[l2pte_index(va)]; 5914 #endif 5915 l2pte_set(ptep, npte, 0); 5916 PTE_SYNC(ptep); 5917 va += PAGE_SIZE; 5918 pa += PAGE_SIZE; 5919 resid -= PAGE_SIZE; 5920 } 5921 #ifdef VERBOSE_INIT_ARM 5922 printf("\n"); 5923 #endif 5924 return (size); 5925 } 5926 5927 /********************** Static device map routines ***************************/ 5928 5929 static const struct pmap_devmap *pmap_devmap_table; 5930 5931 /* 5932 * Register the devmap table. This is provided in case early console 5933 * initialization needs to register mappings created by bootstrap code 5934 * before pmap_devmap_bootstrap() is called. 5935 */ 5936 void 5937 pmap_devmap_register(const struct pmap_devmap *table) 5938 { 5939 5940 pmap_devmap_table = table; 5941 } 5942 5943 /* 5944 * Map all of the static regions in the devmap table, and remember 5945 * the devmap table so other parts of the kernel can look up entries 5946 * later. 5947 */ 5948 void 5949 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5950 { 5951 int i; 5952 5953 pmap_devmap_table = table; 5954 5955 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5956 #ifdef VERBOSE_INIT_ARM 5957 printf("devmap: %08lx -> %08lx @ %08lx\n", 5958 pmap_devmap_table[i].pd_pa, 5959 pmap_devmap_table[i].pd_pa + 5960 pmap_devmap_table[i].pd_size - 1, 5961 pmap_devmap_table[i].pd_va); 5962 #endif 5963 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5964 pmap_devmap_table[i].pd_pa, 5965 pmap_devmap_table[i].pd_size, 5966 pmap_devmap_table[i].pd_prot, 5967 pmap_devmap_table[i].pd_cache); 5968 } 5969 } 5970 5971 const struct pmap_devmap * 5972 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5973 { 5974 uint64_t endpa; 5975 int i; 5976 5977 if (pmap_devmap_table == NULL) 5978 return (NULL); 5979 5980 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5981 5982 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5983 if (pa >= pmap_devmap_table[i].pd_pa && 5984 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5985 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5986 return (&pmap_devmap_table[i]); 5987 } 5988 5989 return (NULL); 5990 } 5991 5992 const struct pmap_devmap * 5993 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5994 { 5995 int i; 5996 5997 if (pmap_devmap_table == NULL) 5998 return (NULL); 5999 6000 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6001 if (va >= pmap_devmap_table[i].pd_va && 6002 va + size - 1 <= pmap_devmap_table[i].pd_va + 6003 pmap_devmap_table[i].pd_size - 1) 6004 return (&pmap_devmap_table[i]); 6005 } 6006 6007 return (NULL); 6008 } 6009 6010 /********************** PTE initialization routines **************************/ 6011 6012 /* 6013 * These routines are called when the CPU type is identified to set up 6014 * the PTE prototypes, cache modes, etc. 6015 * 6016 * The variables are always here, just in case modules need to reference 6017 * them (though, they shouldn't). 6018 */ 6019 6020 pt_entry_t pte_l1_s_cache_mode; 6021 pt_entry_t pte_l1_s_wc_mode; 6022 pt_entry_t pte_l1_s_cache_mode_pt; 6023 pt_entry_t pte_l1_s_cache_mask; 6024 6025 pt_entry_t pte_l2_l_cache_mode; 6026 pt_entry_t pte_l2_l_wc_mode; 6027 pt_entry_t pte_l2_l_cache_mode_pt; 6028 pt_entry_t pte_l2_l_cache_mask; 6029 6030 pt_entry_t pte_l2_s_cache_mode; 6031 pt_entry_t pte_l2_s_wc_mode; 6032 pt_entry_t pte_l2_s_cache_mode_pt; 6033 pt_entry_t pte_l2_s_cache_mask; 6034 6035 pt_entry_t pte_l1_s_prot_u; 6036 pt_entry_t pte_l1_s_prot_w; 6037 pt_entry_t pte_l1_s_prot_ro; 6038 pt_entry_t pte_l1_s_prot_mask; 6039 6040 pt_entry_t pte_l2_s_prot_u; 6041 pt_entry_t pte_l2_s_prot_w; 6042 pt_entry_t pte_l2_s_prot_ro; 6043 pt_entry_t pte_l2_s_prot_mask; 6044 6045 pt_entry_t pte_l2_l_prot_u; 6046 pt_entry_t pte_l2_l_prot_w; 6047 pt_entry_t pte_l2_l_prot_ro; 6048 pt_entry_t pte_l2_l_prot_mask; 6049 6050 pt_entry_t pte_l1_ss_proto; 6051 pt_entry_t pte_l1_s_proto; 6052 pt_entry_t pte_l1_c_proto; 6053 pt_entry_t pte_l2_s_proto; 6054 6055 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6056 void (*pmap_zero_page_func)(paddr_t); 6057 6058 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6059 void 6060 pmap_pte_init_generic(void) 6061 { 6062 6063 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6064 pte_l1_s_wc_mode = L1_S_B; 6065 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6066 6067 pte_l2_l_cache_mode = L2_B|L2_C; 6068 pte_l2_l_wc_mode = L2_B; 6069 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6070 6071 pte_l2_s_cache_mode = L2_B|L2_C; 6072 pte_l2_s_wc_mode = L2_B; 6073 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6074 6075 /* 6076 * If we have a write-through cache, set B and C. If 6077 * we have a write-back cache, then we assume setting 6078 * only C will make those pages write-through (except for those 6079 * Cortex CPUs which can read the L1 caches). 6080 */ 6081 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6082 #if ARM_MMU_V7 > 0 6083 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6084 #endif 6085 #if ARM_MMU_V6 > 0 6086 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6087 #endif 6088 || false) { 6089 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6090 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6091 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6092 } else { 6093 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6094 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6095 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6096 } 6097 6098 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6099 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6100 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6101 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6102 6103 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6104 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6105 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6106 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6107 6108 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6109 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6110 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6111 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6112 6113 pte_l1_ss_proto = L1_SS_PROTO_generic; 6114 pte_l1_s_proto = L1_S_PROTO_generic; 6115 pte_l1_c_proto = L1_C_PROTO_generic; 6116 pte_l2_s_proto = L2_S_PROTO_generic; 6117 6118 pmap_copy_page_func = pmap_copy_page_generic; 6119 pmap_zero_page_func = pmap_zero_page_generic; 6120 } 6121 6122 #if defined(CPU_ARM8) 6123 void 6124 pmap_pte_init_arm8(void) 6125 { 6126 6127 /* 6128 * ARM8 is compatible with generic, but we need to use 6129 * the page tables uncached. 6130 */ 6131 pmap_pte_init_generic(); 6132 6133 pte_l1_s_cache_mode_pt = 0; 6134 pte_l2_l_cache_mode_pt = 0; 6135 pte_l2_s_cache_mode_pt = 0; 6136 } 6137 #endif /* CPU_ARM8 */ 6138 6139 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6140 void 6141 pmap_pte_init_arm9(void) 6142 { 6143 6144 /* 6145 * ARM9 is compatible with generic, but we want to use 6146 * write-through caching for now. 6147 */ 6148 pmap_pte_init_generic(); 6149 6150 pte_l1_s_cache_mode = L1_S_C; 6151 pte_l2_l_cache_mode = L2_C; 6152 pte_l2_s_cache_mode = L2_C; 6153 6154 pte_l1_s_wc_mode = L1_S_B; 6155 pte_l2_l_wc_mode = L2_B; 6156 pte_l2_s_wc_mode = L2_B; 6157 6158 pte_l1_s_cache_mode_pt = L1_S_C; 6159 pte_l2_l_cache_mode_pt = L2_C; 6160 pte_l2_s_cache_mode_pt = L2_C; 6161 } 6162 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6163 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6164 6165 #if defined(CPU_ARM10) 6166 void 6167 pmap_pte_init_arm10(void) 6168 { 6169 6170 /* 6171 * ARM10 is compatible with generic, but we want to use 6172 * write-through caching for now. 6173 */ 6174 pmap_pte_init_generic(); 6175 6176 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6177 pte_l2_l_cache_mode = L2_B | L2_C; 6178 pte_l2_s_cache_mode = L2_B | L2_C; 6179 6180 pte_l1_s_cache_mode = L1_S_B; 6181 pte_l2_l_cache_mode = L2_B; 6182 pte_l2_s_cache_mode = L2_B; 6183 6184 pte_l1_s_cache_mode_pt = L1_S_C; 6185 pte_l2_l_cache_mode_pt = L2_C; 6186 pte_l2_s_cache_mode_pt = L2_C; 6187 6188 } 6189 #endif /* CPU_ARM10 */ 6190 6191 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6192 void 6193 pmap_pte_init_arm11(void) 6194 { 6195 6196 /* 6197 * ARM11 is compatible with generic, but we want to use 6198 * write-through caching for now. 6199 */ 6200 pmap_pte_init_generic(); 6201 6202 pte_l1_s_cache_mode = L1_S_C; 6203 pte_l2_l_cache_mode = L2_C; 6204 pte_l2_s_cache_mode = L2_C; 6205 6206 pte_l1_s_wc_mode = L1_S_B; 6207 pte_l2_l_wc_mode = L2_B; 6208 pte_l2_s_wc_mode = L2_B; 6209 6210 pte_l1_s_cache_mode_pt = L1_S_C; 6211 pte_l2_l_cache_mode_pt = L2_C; 6212 pte_l2_s_cache_mode_pt = L2_C; 6213 } 6214 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6215 6216 #if ARM_MMU_SA1 == 1 6217 void 6218 pmap_pte_init_sa1(void) 6219 { 6220 6221 /* 6222 * The StrongARM SA-1 cache does not have a write-through 6223 * mode. So, do the generic initialization, then reset 6224 * the page table cache mode to B=1,C=1, and note that 6225 * the PTEs need to be sync'd. 6226 */ 6227 pmap_pte_init_generic(); 6228 6229 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6230 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6231 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6232 6233 pmap_needs_pte_sync = 1; 6234 } 6235 #endif /* ARM_MMU_SA1 == 1*/ 6236 6237 #if ARM_MMU_XSCALE == 1 6238 #if (ARM_NMMUS > 1) 6239 static u_int xscale_use_minidata; 6240 #endif 6241 6242 void 6243 pmap_pte_init_xscale(void) 6244 { 6245 uint32_t auxctl; 6246 int write_through = 0; 6247 6248 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6249 pte_l1_s_wc_mode = L1_S_B; 6250 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6251 6252 pte_l2_l_cache_mode = L2_B|L2_C; 6253 pte_l2_l_wc_mode = L2_B; 6254 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6255 6256 pte_l2_s_cache_mode = L2_B|L2_C; 6257 pte_l2_s_wc_mode = L2_B; 6258 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6259 6260 pte_l1_s_cache_mode_pt = L1_S_C; 6261 pte_l2_l_cache_mode_pt = L2_C; 6262 pte_l2_s_cache_mode_pt = L2_C; 6263 6264 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6265 /* 6266 * The XScale core has an enhanced mode where writes that 6267 * miss the cache cause a cache line to be allocated. This 6268 * is significantly faster than the traditional, write-through 6269 * behavior of this case. 6270 */ 6271 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6272 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6273 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6274 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6275 6276 #ifdef XSCALE_CACHE_WRITE_THROUGH 6277 /* 6278 * Some versions of the XScale core have various bugs in 6279 * their cache units, the work-around for which is to run 6280 * the cache in write-through mode. Unfortunately, this 6281 * has a major (negative) impact on performance. So, we 6282 * go ahead and run fast-and-loose, in the hopes that we 6283 * don't line up the planets in a way that will trip the 6284 * bugs. 6285 * 6286 * However, we give you the option to be slow-but-correct. 6287 */ 6288 write_through = 1; 6289 #elif defined(XSCALE_CACHE_WRITE_BACK) 6290 /* force write back cache mode */ 6291 write_through = 0; 6292 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6293 /* 6294 * Intel PXA2[15]0 processors are known to have a bug in 6295 * write-back cache on revision 4 and earlier (stepping 6296 * A[01] and B[012]). Fixed for C0 and later. 6297 */ 6298 { 6299 uint32_t id, type; 6300 6301 id = cpufunc_id(); 6302 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6303 6304 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6305 if ((id & CPU_ID_REVISION_MASK) < 5) { 6306 /* write through for stepping A0-1 and B0-2 */ 6307 write_through = 1; 6308 } 6309 } 6310 } 6311 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6312 6313 if (write_through) { 6314 pte_l1_s_cache_mode = L1_S_C; 6315 pte_l2_l_cache_mode = L2_C; 6316 pte_l2_s_cache_mode = L2_C; 6317 } 6318 6319 #if (ARM_NMMUS > 1) 6320 xscale_use_minidata = 1; 6321 #endif 6322 6323 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6324 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6325 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6326 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6327 6328 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6329 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6330 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6331 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6332 6333 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6334 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6335 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6336 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6337 6338 pte_l1_ss_proto = L1_SS_PROTO_xscale; 6339 pte_l1_s_proto = L1_S_PROTO_xscale; 6340 pte_l1_c_proto = L1_C_PROTO_xscale; 6341 pte_l2_s_proto = L2_S_PROTO_xscale; 6342 6343 pmap_copy_page_func = pmap_copy_page_xscale; 6344 pmap_zero_page_func = pmap_zero_page_xscale; 6345 6346 /* 6347 * Disable ECC protection of page table access, for now. 6348 */ 6349 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6350 auxctl &= ~XSCALE_AUXCTL_P; 6351 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6352 } 6353 6354 /* 6355 * xscale_setup_minidata: 6356 * 6357 * Set up the mini-data cache clean area. We require the 6358 * caller to allocate the right amount of physically and 6359 * virtually contiguous space. 6360 */ 6361 void 6362 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6363 { 6364 extern vaddr_t xscale_minidata_clean_addr; 6365 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6366 pd_entry_t *pde = (pd_entry_t *) l1pt; 6367 vsize_t size; 6368 uint32_t auxctl; 6369 6370 xscale_minidata_clean_addr = va; 6371 6372 /* Round it to page size. */ 6373 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6374 6375 for (; size != 0; 6376 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6377 const size_t l1idx = L1_IDX(va); 6378 #ifndef ARM32_NEW_VM_LAYOUT 6379 pt_entry_t *ptep = (pt_entry_t *) 6380 kernel_pt_lookup(pde[l1idx] & L2_S_FRAME); 6381 #else 6382 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup( 6383 pde[l1idx] & L1_C_ADDR_MASK); 6384 #endif 6385 if (ptep == NULL) 6386 panic("xscale_setup_minidata: can't find L2 table for " 6387 "VA 0x%08lx", va); 6388 6389 #ifndef ARM32_NEW_VM_LAYOUT 6390 ptep += (va >> PGSHIFT) & 0x3ff; 6391 #else 6392 ptep += l2pte_index(va); 6393 #endif 6394 pt_entry_t opte = *ptep; 6395 l2pte_set(ptep, 6396 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 6397 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 6398 } 6399 6400 /* 6401 * Configure the mini-data cache for write-back with 6402 * read/write-allocate. 6403 * 6404 * NOTE: In order to reconfigure the mini-data cache, we must 6405 * make sure it contains no valid data! In order to do that, 6406 * we must issue a global data cache invalidate command! 6407 * 6408 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6409 * THIS IS VERY IMPORTANT! 6410 */ 6411 6412 /* Invalidate data and mini-data. */ 6413 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6414 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6415 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6416 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6417 } 6418 6419 /* 6420 * Change the PTEs for the specified kernel mappings such that they 6421 * will use the mini data cache instead of the main data cache. 6422 */ 6423 void 6424 pmap_uarea(vaddr_t va) 6425 { 6426 vaddr_t next_bucket, eva; 6427 6428 #if (ARM_NMMUS > 1) 6429 if (xscale_use_minidata == 0) 6430 return; 6431 #endif 6432 6433 eva = va + USPACE; 6434 6435 while (va < eva) { 6436 next_bucket = L2_NEXT_BUCKET(va); 6437 if (next_bucket > eva) 6438 next_bucket = eva; 6439 6440 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6441 KDASSERT(l2b != NULL); 6442 6443 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 6444 pt_entry_t *ptep = sptep; 6445 6446 while (va < next_bucket) { 6447 const pt_entry_t opte = *ptep; 6448 if (!l2pte_minidata(opte)) { 6449 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6450 cpu_tlb_flushD_SE(va); 6451 l2pte_set(ptep, opte & ~L2_B, opte); 6452 } 6453 ptep += PAGE_SIZE / L2_S_SIZE; 6454 va += PAGE_SIZE; 6455 } 6456 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6457 } 6458 cpu_cpwait(); 6459 } 6460 #endif /* ARM_MMU_XSCALE == 1 */ 6461 6462 6463 #if defined(CPU_ARM11MPCORE) 6464 6465 void 6466 pmap_pte_init_arm11mpcore(void) 6467 { 6468 6469 /* cache mode is controlled by 5 bits (B, C, TEX) */ 6470 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 6471 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 6472 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6473 /* use extended small page (without APn, with TEX) */ 6474 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 6475 #else 6476 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 6477 #endif 6478 6479 /* write-back, write-allocate */ 6480 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6481 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 6482 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6483 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6484 #else 6485 /* no TEX. read-allocate */ 6486 pte_l2_s_cache_mode = L2_C | L2_B; 6487 #endif 6488 /* 6489 * write-back, write-allocate for page tables. 6490 */ 6491 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 6492 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 6493 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6494 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 6495 #else 6496 pte_l2_s_cache_mode_pt = L2_C | L2_B; 6497 #endif 6498 6499 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 6500 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 6501 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 6502 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 6503 6504 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 6505 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 6506 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 6507 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 6508 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 6509 6510 #else 6511 /* with AP[0..3] */ 6512 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6513 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6514 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6515 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6516 #endif 6517 6518 #ifdef ARM11MPCORE_COMPAT_MMU 6519 /* with AP[0..3] */ 6520 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6521 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6522 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6523 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6524 6525 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6526 pte_l1_s_proto = L1_S_PROTO_armv6; 6527 pte_l1_c_proto = L1_C_PROTO_armv6; 6528 pte_l2_s_proto = L2_S_PROTO_armv6c; 6529 #else 6530 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 6531 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 6532 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 6533 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 6534 6535 pte_l1_ss_proto = L1_SS_PROTO_armv6; 6536 pte_l1_s_proto = L1_S_PROTO_armv6; 6537 pte_l1_c_proto = L1_C_PROTO_armv6; 6538 pte_l2_s_proto = L2_S_PROTO_armv6n; 6539 #endif 6540 6541 pmap_copy_page_func = pmap_copy_page_generic; 6542 pmap_zero_page_func = pmap_zero_page_generic; 6543 pmap_needs_pte_sync = 1; 6544 } 6545 #endif /* CPU_ARM11MPCORE */ 6546 6547 6548 #if ARM_MMU_V7 == 1 6549 void 6550 pmap_pte_init_armv7(void) 6551 { 6552 /* 6553 * The ARMv7-A MMU is mostly compatible with generic. If the 6554 * AP field is zero, that now means "no access" rather than 6555 * read-only. The prototypes are a little different because of 6556 * the XN bit. 6557 */ 6558 pmap_pte_init_generic(); 6559 6560 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6561 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6562 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6563 6564 if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) { 6565 /* 6566 * write-back, no write-allocate, shareable for normal pages. 6567 */ 6568 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_S; 6569 pte_l2_l_cache_mode = L2_C | L2_B | L2_XS_S; 6570 pte_l2_s_cache_mode = L2_C | L2_B | L2_XS_S; 6571 6572 /* 6573 * write-back, no write-allocate, shareable for page tables. 6574 */ 6575 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_S; 6576 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6577 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_XS_S; 6578 } 6579 6580 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6581 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6582 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6583 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6584 6585 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6586 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6587 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6588 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6589 6590 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6591 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6592 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6593 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6594 6595 pte_l1_ss_proto = L1_SS_PROTO_armv7; 6596 pte_l1_s_proto = L1_S_PROTO_armv7; 6597 pte_l1_c_proto = L1_C_PROTO_armv7; 6598 pte_l2_s_proto = L2_S_PROTO_armv7; 6599 6600 pmap_needs_pte_sync = 1; 6601 } 6602 #endif /* ARM_MMU_V7 */ 6603 6604 /* 6605 * return the PA of the current L1 table, for use when handling a crash dump 6606 */ 6607 uint32_t pmap_kernel_L1_addr(void) 6608 { 6609 return pmap_kernel()->pm_l1->l1_physaddr; 6610 } 6611 6612 #if defined(DDB) 6613 /* 6614 * A couple of ddb-callable functions for dumping pmaps 6615 */ 6616 void pmap_dump_all(void); 6617 void pmap_dump(pmap_t); 6618 6619 void 6620 pmap_dump_all(void) 6621 { 6622 pmap_t pm; 6623 6624 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6625 if (pm == pmap_kernel()) 6626 continue; 6627 pmap_dump(pm); 6628 printf("\n"); 6629 } 6630 } 6631 6632 static pt_entry_t ncptes[64]; 6633 static void pmap_dump_ncpg(pmap_t); 6634 6635 void 6636 pmap_dump(pmap_t pm) 6637 { 6638 struct l2_dtable *l2; 6639 struct l2_bucket *l2b; 6640 pt_entry_t *ptep, pte; 6641 vaddr_t l2_va, l2b_va, va; 6642 int i, j, k, occ, rows = 0; 6643 6644 if (pm == pmap_kernel()) 6645 printf("pmap_kernel (%p): ", pm); 6646 else 6647 printf("user pmap (%p): ", pm); 6648 6649 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 6650 6651 l2_va = 0; 6652 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6653 l2 = pm->pm_l2[i]; 6654 6655 if (l2 == NULL || l2->l2_occupancy == 0) 6656 continue; 6657 6658 l2b_va = l2_va; 6659 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6660 l2b = &l2->l2_bucket[j]; 6661 6662 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6663 continue; 6664 6665 ptep = l2b->l2b_kva; 6666 6667 for (k = 0; k < 256 && ptep[k] == 0; k++) 6668 ; 6669 6670 k &= ~63; 6671 occ = l2b->l2b_occupancy; 6672 va = l2b_va + (k * 4096); 6673 for (; k < 256; k++, va += 0x1000) { 6674 char ch = ' '; 6675 if ((k % 64) == 0) { 6676 if ((rows % 8) == 0) { 6677 printf( 6678 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6679 } 6680 printf("%08lx: ", va); 6681 } 6682 6683 ncptes[k & 63] = 0; 6684 pte = ptep[k]; 6685 if (pte == 0) { 6686 ch = '.'; 6687 } else { 6688 occ--; 6689 switch (pte & 0x0c) { 6690 case 0x00: 6691 ch = 'D'; /* No cache No buff */ 6692 break; 6693 case 0x04: 6694 ch = 'B'; /* No cache buff */ 6695 break; 6696 case 0x08: 6697 if (pte & 0x40) 6698 ch = 'm'; 6699 else 6700 ch = 'C'; /* Cache No buff */ 6701 break; 6702 case 0x0c: 6703 ch = 'F'; /* Cache Buff */ 6704 break; 6705 } 6706 6707 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6708 ch += 0x20; 6709 6710 if ((pte & 0xc) == 0) 6711 ncptes[k & 63] = pte; 6712 } 6713 6714 if ((k % 64) == 63) { 6715 rows++; 6716 printf("%c\n", ch); 6717 pmap_dump_ncpg(pm); 6718 if (occ == 0) 6719 break; 6720 } else 6721 printf("%c", ch); 6722 } 6723 } 6724 } 6725 } 6726 6727 static void 6728 pmap_dump_ncpg(pmap_t pm) 6729 { 6730 struct vm_page *pg; 6731 struct vm_page_md *md; 6732 struct pv_entry *pv; 6733 int i; 6734 6735 for (i = 0; i < 63; i++) { 6736 if (ncptes[i] == 0) 6737 continue; 6738 6739 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6740 if (pg == NULL) 6741 continue; 6742 md = VM_PAGE_TO_MD(pg); 6743 6744 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6745 VM_PAGE_TO_PHYS(pg), 6746 md->krw_mappings, md->kro_mappings, 6747 md->urw_mappings, md->uro_mappings); 6748 6749 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6750 printf(" %c va 0x%08lx, flags 0x%x\n", 6751 (pm == pv->pv_pmap) ? '*' : ' ', 6752 pv->pv_va, pv->pv_flags); 6753 } 6754 } 6755 } 6756 #endif 6757 6758 #ifdef PMAP_STEAL_MEMORY 6759 void 6760 pmap_boot_pageadd(pv_addr_t *newpv) 6761 { 6762 pv_addr_t *pv, *npv; 6763 6764 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6765 if (newpv->pv_pa < pv->pv_va) { 6766 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6767 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6768 newpv->pv_size += pv->pv_size; 6769 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6770 } 6771 pv = NULL; 6772 } else { 6773 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6774 pv = npv) { 6775 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6776 KASSERT(pv->pv_pa < newpv->pv_pa); 6777 if (newpv->pv_pa > npv->pv_pa) 6778 continue; 6779 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6780 pv->pv_size += newpv->pv_size; 6781 return; 6782 } 6783 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6784 break; 6785 newpv->pv_size += npv->pv_size; 6786 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6787 SLIST_REMOVE_AFTER(newpv, pv_list); 6788 return; 6789 } 6790 } 6791 } 6792 6793 if (pv) { 6794 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6795 } else { 6796 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6797 } 6798 } 6799 6800 void 6801 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6802 pv_addr_t *rpv) 6803 { 6804 pv_addr_t *pv, **pvp; 6805 struct vm_physseg *ps; 6806 size_t i; 6807 6808 KASSERT(amount & PGOFSET); 6809 KASSERT((mask & PGOFSET) == 0); 6810 KASSERT((match & PGOFSET) == 0); 6811 KASSERT(amount != 0); 6812 6813 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6814 (pv = *pvp) != NULL; 6815 pvp = &SLIST_NEXT(pv, pv_list)) { 6816 pv_addr_t *newpv; 6817 psize_t off; 6818 /* 6819 * If this entry is too small to satify the request... 6820 */ 6821 KASSERT(pv->pv_size > 0); 6822 if (pv->pv_size < amount) 6823 continue; 6824 6825 for (off = 0; off <= mask; off += PAGE_SIZE) { 6826 if (((pv->pv_pa + off) & mask) == match 6827 && off + amount <= pv->pv_size) 6828 break; 6829 } 6830 if (off > mask) 6831 continue; 6832 6833 rpv->pv_va = pv->pv_va + off; 6834 rpv->pv_pa = pv->pv_pa + off; 6835 rpv->pv_size = amount; 6836 pv->pv_size -= amount; 6837 if (pv->pv_size == 0) { 6838 KASSERT(off == 0); 6839 KASSERT((vaddr_t) pv == rpv->pv_va); 6840 *pvp = SLIST_NEXT(pv, pv_list); 6841 } else if (off == 0) { 6842 KASSERT((vaddr_t) pv == rpv->pv_va); 6843 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6844 *newpv = *pv; 6845 newpv->pv_pa += amount; 6846 newpv->pv_va += amount; 6847 *pvp = newpv; 6848 } else if (off < pv->pv_size) { 6849 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6850 *newpv = *pv; 6851 newpv->pv_size -= off; 6852 newpv->pv_pa += off + amount; 6853 newpv->pv_va += off + amount; 6854 6855 SLIST_NEXT(pv, pv_list) = newpv; 6856 pv->pv_size = off; 6857 } else { 6858 KASSERT((vaddr_t) pv != rpv->pv_va); 6859 } 6860 memset((void *)rpv->pv_va, 0, amount); 6861 return; 6862 } 6863 6864 if (vm_nphysseg == 0) 6865 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6866 6867 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6868 (pv = *pvp) != NULL; 6869 pvp = &SLIST_NEXT(pv, pv_list)) { 6870 if (SLIST_NEXT(pv, pv_list) == NULL) 6871 break; 6872 } 6873 KASSERT(mask == 0); 6874 for (i = 0; i < vm_nphysseg; i++) { 6875 ps = VM_PHYSMEM_PTR(i); 6876 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6877 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6878 rpv->pv_va = pv->pv_va; 6879 rpv->pv_pa = pv->pv_pa; 6880 rpv->pv_size = amount; 6881 *pvp = NULL; 6882 pmap_map_chunk(kernel_l1pt.pv_va, 6883 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6884 ptoa(ps->avail_start), 6885 amount - pv->pv_size, 6886 VM_PROT_READ|VM_PROT_WRITE, 6887 PTE_CACHE); 6888 ps->avail_start += atop(amount - pv->pv_size); 6889 /* 6890 * If we consumed the entire physseg, remove it. 6891 */ 6892 if (ps->avail_start == ps->avail_end) { 6893 for (--vm_nphysseg; i < vm_nphysseg; i++) 6894 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6895 } 6896 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6897 return; 6898 } 6899 } 6900 6901 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6902 } 6903 6904 vaddr_t 6905 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6906 { 6907 pv_addr_t pv; 6908 6909 pmap_boot_pagealloc(size, 0, 0, &pv); 6910 6911 return pv.pv_va; 6912 } 6913 #endif /* PMAP_STEAL_MEMORY */ 6914 6915 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6916 { 6917 sysctl_createv(clog, 0, NULL, NULL, 6918 CTLFLAG_PERMANENT, 6919 CTLTYPE_NODE, "machdep", NULL, 6920 NULL, 0, NULL, 0, 6921 CTL_MACHDEP, CTL_EOL); 6922 6923 sysctl_createv(clog, 0, NULL, NULL, 6924 CTLFLAG_PERMANENT, 6925 CTLTYPE_INT, "kmpages", 6926 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6927 NULL, 0, &pmap_kmpages, 0, 6928 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6929 } 6930 6931 #ifdef PMAP_NEED_ALLOC_POOLPAGE 6932 struct vm_page * 6933 arm_pmap_alloc_poolpage(int flags) 6934 { 6935 /* 6936 * On some systems, only some pages may be "coherent" for dma and we 6937 * want to prefer those for pool pages (think mbufs) but fallback to 6938 * any page if none is available. 6939 */ 6940 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 6941 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 6942 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 6943 } 6944 6945 return uvm_pagealloc(NULL, 0, NULL, flags); 6946 } 6947 #endif 6948
Indexes created Fri Sep 26 20:09:58 GMT 2025