pmap.c revision 1.271
1 /* $NetBSD: pmap.c,v 1.271 2014/03/30 15:50:51 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 //#include <arm/arm32/katelib.h> 218 219 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.271 2014/03/30 15:50:51 matt Exp $"); 220 221 //#define PMAP_DEBUG 222 #ifdef PMAP_DEBUG 223 224 /* XXX need to get rid of all refs to this */ 225 int pmap_debug_level = 0; 226 227 /* 228 * for switching to potentially finer grained debugging 229 */ 230 #define PDB_FOLLOW 0x0001 231 #define PDB_INIT 0x0002 232 #define PDB_ENTER 0x0004 233 #define PDB_REMOVE 0x0008 234 #define PDB_CREATE 0x0010 235 #define PDB_PTPAGE 0x0020 236 #define PDB_GROWKERN 0x0040 237 #define PDB_BITS 0x0080 238 #define PDB_COLLECT 0x0100 239 #define PDB_PROTECT 0x0200 240 #define PDB_MAP_L1 0x0400 241 #define PDB_BOOTSTRAP 0x1000 242 #define PDB_PARANOIA 0x2000 243 #define PDB_WIRING 0x4000 244 #define PDB_PVDUMP 0x8000 245 #define PDB_VAC 0x10000 246 #define PDB_KENTER 0x20000 247 #define PDB_KREMOVE 0x40000 248 #define PDB_EXEC 0x80000 249 250 int debugmap = 1; 251 int pmapdebug = 0; 252 #define NPDEBUG(_lev_,_stat_) \ 253 if (pmapdebug & (_lev_)) \ 254 ((_stat_)) 255 256 #else /* PMAP_DEBUG */ 257 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 258 #endif /* PMAP_DEBUG */ 259 260 /* 261 * pmap_kernel() points here 262 */ 263 static struct pmap kernel_pmap_store = { 264 #ifndef ARM_MMU_EXTENDED 265 .pm_activated = true, 266 .pm_domain = PMAP_DOMAIN_KERNEL, 267 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 268 #endif 269 }; 270 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 271 #undef pmap_kernel 272 #define pmap_kernel() (&kernel_pmap_store) 273 #ifdef PMAP_NEED_ALLOC_POOLPAGE 274 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 275 #endif 276 277 /* 278 * Pool and cache that pmap structures are allocated from. 279 * We use a cache to avoid clearing the pm_l2[] array (1KB) 280 * in pmap_create(). 281 */ 282 static struct pool_cache pmap_cache; 283 static LIST_HEAD(, pmap) pmap_pmaps; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 #ifndef ARM_MMU_EXTENDED 426 static struct evcnt pmap_ev_exec_synced_map = 427 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 428 static struct evcnt pmap_ev_exec_synced_unmap = 429 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 430 static struct evcnt pmap_ev_exec_synced_remap = 431 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 432 static struct evcnt pmap_ev_exec_synced_clearbit = 433 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 #ifndef ARM_MMU_EXTENDED 440 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 /* 489 * pmap copy/zero page, and mem(5) hook point 490 */ 491 static pt_entry_t *csrc_pte, *cdst_pte; 492 static vaddr_t csrcp, cdstp; 493 #ifdef MULTIPROCESSOR 494 static size_t cnptes; 495 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 497 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 499 #else 500 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + (o)) 503 #define cpu_cdstp(o) (cdstp + (o)) 504 #endif 505 vaddr_t memhook; /* used by mem.c & others */ 506 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 507 kmutex_t pmap_lock __cacheline_aligned; 508 extern void *msgbufaddr; 509 int pmap_kmpages; 510 /* 511 * Flag to indicate if pmap_init() has done its thing 512 */ 513 bool pmap_initialized; 514 515 /* 516 * Misc. locking data structures 517 */ 518 519 static inline void 520 pmap_acquire_pmap_lock(pmap_t pm) 521 { 522 if (pm == pmap_kernel()) { 523 #ifdef MULTIPROCESSOR 524 KERNEL_LOCK(1, NULL); 525 #endif 526 } else { 527 mutex_enter(pm->pm_lock); 528 } 529 } 530 531 static inline void 532 pmap_release_pmap_lock(pmap_t pm) 533 { 534 if (pm == pmap_kernel()) { 535 #ifdef MULTIPROCESSOR 536 KERNEL_UNLOCK_ONE(NULL); 537 #endif 538 } else { 539 mutex_exit(pm->pm_lock); 540 } 541 } 542 543 static inline void 544 pmap_acquire_page_lock(struct vm_page_md *md) 545 { 546 mutex_enter(&pmap_lock); 547 } 548 549 static inline void 550 pmap_release_page_lock(struct vm_page_md *md) 551 { 552 mutex_exit(&pmap_lock); 553 } 554 555 #ifdef DIAGNOSTIC 556 static inline int 557 pmap_page_locked_p(struct vm_page_md *md) 558 { 559 return mutex_owned(&pmap_lock); 560 } 561 #endif 562 563 564 /* 565 * Metadata for L1 translation tables. 566 */ 567 #ifndef ARM_MMU_EXTENDED 568 struct l1_ttable { 569 /* Entry on the L1 Table list */ 570 SLIST_ENTRY(l1_ttable) l1_link; 571 572 /* Entry on the L1 Least Recently Used list */ 573 TAILQ_ENTRY(l1_ttable) l1_lru; 574 575 /* Track how many domains are allocated from this L1 */ 576 volatile u_int l1_domain_use_count; 577 578 /* 579 * A free-list of domain numbers for this L1. 580 * We avoid using ffs() and a bitmap to track domains since ffs() 581 * is slow on ARM. 582 */ 583 uint8_t l1_domain_first; 584 uint8_t l1_domain_free[PMAP_DOMAINS]; 585 586 /* Physical address of this L1 page table */ 587 paddr_t l1_physaddr; 588 589 /* KVA of this L1 page table */ 590 pd_entry_t *l1_kva; 591 }; 592 593 /* 594 * L1 Page Tables are tracked using a Least Recently Used list. 595 * - New L1s are allocated from the HEAD. 596 * - Freed L1s are added to the TAIl. 597 * - Recently accessed L1s (where an 'access' is some change to one of 598 * the userland pmaps which owns this L1) are moved to the TAIL. 599 */ 600 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 601 static kmutex_t l1_lru_lock __cacheline_aligned; 602 603 /* 604 * A list of all L1 tables 605 */ 606 static SLIST_HEAD(, l1_ttable) l1_list; 607 #endif /* ARM_MMU_EXTENDED */ 608 609 /* 610 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 611 * 612 * This is normally 16MB worth L2 page descriptors for any given pmap. 613 * Reference counts are maintained for L2 descriptors so they can be 614 * freed when empty. 615 */ 616 struct l2_dtable { 617 /* The number of L2 page descriptors allocated to this l2_dtable */ 618 u_int l2_occupancy; 619 620 /* List of L2 page descriptors */ 621 struct l2_bucket { 622 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 623 paddr_t l2b_pa; /* Physical address of same */ 624 u_short l2b_l1slot; /* This L2 table's L1 index */ 625 u_short l2b_occupancy; /* How many active descriptors */ 626 } l2_bucket[L2_BUCKET_SIZE]; 627 }; 628 629 /* 630 * Given an L1 table index, calculate the corresponding l2_dtable index 631 * and bucket index within the l2_dtable. 632 */ 633 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 634 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 635 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 636 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 637 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 638 639 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 640 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 641 642 /* 643 * Given a virtual address, this macro returns the 644 * virtual address required to drop into the next L2 bucket. 645 */ 646 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 647 648 /* 649 * L2 allocation. 650 */ 651 #define pmap_alloc_l2_dtable() \ 652 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 653 #define pmap_free_l2_dtable(l2) \ 654 pool_cache_put(&pmap_l2dtable_cache, (l2)) 655 #define pmap_alloc_l2_ptp(pap) \ 656 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 657 PR_NOWAIT, (pap))) 658 659 /* 660 * We try to map the page tables write-through, if possible. However, not 661 * all CPUs have a write-through cache mode, so on those we have to sync 662 * the cache when we frob page tables. 663 * 664 * We try to evaluate this at compile time, if possible. However, it's 665 * not always possible to do that, hence this run-time var. 666 */ 667 int pmap_needs_pte_sync; 668 669 /* 670 * Real definition of pv_entry. 671 */ 672 struct pv_entry { 673 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 674 pmap_t pv_pmap; /* pmap where mapping lies */ 675 vaddr_t pv_va; /* virtual address for mapping */ 676 u_int pv_flags; /* flags */ 677 }; 678 679 /* 680 * Macro to determine if a mapping might be resident in the 681 * instruction cache and/or TLB 682 */ 683 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 684 /* 685 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 686 * there are no explicit accesses, so there may be always be TLB entries to 687 * flush. If we used ASIDs then this would not be a problem. 688 */ 689 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 690 #else 691 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 692 #endif 693 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 694 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 695 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 696 697 /* 698 * Macro to determine if a mapping might be resident in the 699 * data cache and/or TLB 700 */ 701 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 702 /* 703 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 704 * there are no explicit accesses, so there may be always be TLB entries to 705 * flush. If we used ASIDs then this would not be a problem. 706 */ 707 #define PV_BEEN_REFD(f) (1) 708 #else 709 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 710 #endif 711 712 /* 713 * Local prototypes 714 */ 715 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 716 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 717 pt_entry_t **); 718 static bool pmap_is_current(pmap_t); 719 static bool pmap_is_cached(pmap_t); 720 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 721 pmap_t, vaddr_t, u_int); 722 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 723 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 724 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 725 u_int, u_int); 726 727 static void pmap_pinit(pmap_t); 728 static int pmap_pmap_ctor(void *, void *, int); 729 730 static void pmap_alloc_l1(pmap_t); 731 static void pmap_free_l1(pmap_t); 732 #ifndef ARM_MMU_EXTENDED 733 static void pmap_use_l1(pmap_t); 734 #endif 735 736 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 737 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 738 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 739 static int pmap_l2ptp_ctor(void *, void *, int); 740 static int pmap_l2dtable_ctor(void *, void *, int); 741 742 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 743 #ifdef PMAP_CACHE_VIVT 744 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 745 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 746 #endif 747 748 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 749 #ifdef PMAP_CACHE_VIVT 750 static bool pmap_clean_page(struct vm_page_md *, bool); 751 #endif 752 #ifdef PMAP_CACHE_VIPT 753 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 754 enum pmap_flush_op { 755 PMAP_FLUSH_PRIMARY, 756 PMAP_FLUSH_SECONDARY, 757 PMAP_CLEAN_PRIMARY 758 }; 759 #ifndef ARM_MMU_EXTENDED 760 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 761 #endif 762 #endif 763 static void pmap_page_remove(struct vm_page_md *, paddr_t); 764 765 #ifndef ARM_MMU_EXTENDED 766 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 767 #endif 768 static vaddr_t kernel_pt_lookup(paddr_t); 769 770 771 /* 772 * Misc variables 773 */ 774 vaddr_t virtual_avail; 775 vaddr_t virtual_end; 776 vaddr_t pmap_curmaxkvaddr; 777 778 paddr_t avail_start; 779 paddr_t avail_end; 780 781 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 782 pv_addr_t kernelpages; 783 pv_addr_t kernel_l1pt; 784 pv_addr_t systempage; 785 786 /* Function to set the debug level of the pmap code */ 787 788 #ifdef PMAP_DEBUG 789 void 790 pmap_debug(int level) 791 { 792 pmap_debug_level = level; 793 printf("pmap_debug: level=%d\n", pmap_debug_level); 794 } 795 #endif /* PMAP_DEBUG */ 796 797 #ifdef PMAP_CACHE_VIPT 798 #define PMAP_VALIDATE_MD_PAGE(md) \ 799 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 800 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 801 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 802 #endif /* PMAP_CACHE_VIPT */ 803 /* 804 * A bunch of routines to conditionally flush the caches/TLB depending 805 * on whether the specified pmap actually needs to be flushed at any 806 * given time. 807 */ 808 static inline void 809 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 810 { 811 #ifdef ARM_MMU_EXTENDED 812 pmap_tlb_invalidate_addr(pm, va); 813 #else 814 if (pm->pm_cstate.cs_tlb_id != 0) { 815 if (PV_BEEN_EXECD(flags)) { 816 cpu_tlb_flushID_SE(va); 817 } else if (PV_BEEN_REFD(flags)) { 818 cpu_tlb_flushD_SE(va); 819 } 820 } 821 #endif /* ARM_MMU_EXTENDED */ 822 } 823 824 static inline void 825 pmap_tlb_flushID(pmap_t pm) 826 { 827 #ifdef ARM_MMU_EXTENDED 828 pmap_tlb_asid_release_all(pm); 829 #else 830 if (pm->pm_cstate.cs_tlb_id) { 831 cpu_tlb_flushID(); 832 #if ARM_MMU_V7 == 0 833 /* 834 * Speculative loads by Cortex cores can cause TLB entries to 835 * be filled even if there are no explicit accesses, so there 836 * may be always be TLB entries to flush. If we used ASIDs 837 * then it would not be a problem. 838 * This is not true for other CPUs. 839 */ 840 pm->pm_cstate.cs_tlb = 0; 841 #endif /* ARM_MMU_V7 */ 842 } 843 #endif /* ARM_MMU_EXTENDED */ 844 } 845 846 static inline void 847 pmap_tlb_flushD(pmap_t pm) 848 { 849 #ifdef ARM_MMU_EXTENDED 850 pmap_tlb_asid_release_all(pm); 851 #else 852 if (pm->pm_cstate.cs_tlb_d) { 853 cpu_tlb_flushD(); 854 #if ARM_MMU_V7 == 0 855 /* 856 * Speculative loads by Cortex cores can cause TLB entries to 857 * be filled even if there are no explicit accesses, so there 858 * may be always be TLB entries to flush. If we used ASIDs 859 * then it would not be a problem. 860 * This is not true for other CPUs. 861 */ 862 pm->pm_cstate.cs_tlb_d = 0; 863 #endif /* ARM_MMU_V7 */ 864 } 865 #endif /* ARM_MMU_EXTENDED */ 866 } 867 868 #ifdef PMAP_CACHE_VIVT 869 static inline void 870 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 871 { 872 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 873 cpu_idcache_wbinv_range(va, PAGE_SIZE); 874 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 875 if (do_inv) { 876 if (flags & PVF_WRITE) 877 cpu_dcache_wbinv_range(va, PAGE_SIZE); 878 else 879 cpu_dcache_inv_range(va, PAGE_SIZE); 880 } else if (flags & PVF_WRITE) { 881 cpu_dcache_wb_range(va, PAGE_SIZE); 882 } 883 } 884 } 885 886 static inline void 887 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 888 { 889 if (PV_BEEN_EXECD(flags)) { 890 if (pm->pm_cstate.cs_cache_id) { 891 cpu_idcache_wbinv_all(); 892 pm->pm_cstate.cs_cache = 0; 893 } 894 } else if (pm->pm_cstate.cs_cache_d) { 895 cpu_dcache_wbinv_all(); 896 pm->pm_cstate.cs_cache_d = 0; 897 } 898 } 899 #endif /* PMAP_CACHE_VIVT */ 900 901 static inline uint8_t 902 pmap_domain(pmap_t pm) 903 { 904 #ifdef ARM_MMU_EXTENDED 905 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 906 #else 907 return pm->pm_domain; 908 #endif 909 } 910 911 static inline pd_entry_t * 912 pmap_l1_kva(pmap_t pm) 913 { 914 #ifdef ARM_MMU_EXTENDED 915 return pm->pm_l1; 916 #else 917 return pm->pm_l1->l1_kva; 918 #endif 919 } 920 921 static inline bool 922 pmap_is_current(pmap_t pm) 923 { 924 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 925 return true; 926 927 return false; 928 } 929 930 static inline bool 931 pmap_is_cached(pmap_t pm) 932 { 933 #ifdef ARM_MMU_EXTENDED 934 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 935 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 936 return true; 937 #else 938 struct cpu_info * const ci = curcpu(); 939 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 940 || ci->ci_pmap_lastuser == pm) 941 return true; 942 #endif /* ARM_MMU_EXTENDED */ 943 944 return false; 945 } 946 947 /* 948 * PTE_SYNC_CURRENT: 949 * 950 * Make sure the pte is written out to RAM. 951 * We need to do this for one of two cases: 952 * - We're dealing with the kernel pmap 953 * - There is no pmap active in the cache/tlb. 954 * - The specified pmap is 'active' in the cache/tlb. 955 */ 956 #ifdef PMAP_INCLUDE_PTE_SYNC 957 #define PTE_SYNC_CURRENT(pm, ptep) \ 958 do { \ 959 if (PMAP_NEEDS_PTE_SYNC && \ 960 pmap_is_cached(pm)) \ 961 PTE_SYNC(ptep); \ 962 } while (/*CONSTCOND*/0) 963 #else 964 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 965 #endif 966 967 /* 968 * main pv_entry manipulation functions: 969 * pmap_enter_pv: enter a mapping onto a vm_page list 970 * pmap_remove_pv: remove a mapping from a vm_page list 971 * 972 * NOTE: pmap_enter_pv expects to lock the pvh itself 973 * pmap_remove_pv expects the caller to lock the pvh before calling 974 */ 975 976 /* 977 * pmap_enter_pv: enter a mapping onto a vm_page lst 978 * 979 * => caller should hold the proper lock on pmap_main_lock 980 * => caller should have pmap locked 981 * => we will gain the lock on the vm_page and allocate the new pv_entry 982 * => caller should adjust ptp's wire_count before calling 983 * => caller should not adjust pmap's wire_count 984 */ 985 static void 986 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 987 vaddr_t va, u_int flags) 988 { 989 struct pv_entry **pvp; 990 991 NPDEBUG(PDB_PVDUMP, 992 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 993 994 pv->pv_pmap = pm; 995 pv->pv_va = va; 996 pv->pv_flags = flags; 997 998 pvp = &SLIST_FIRST(&md->pvh_list); 999 #ifdef PMAP_CACHE_VIPT 1000 /* 1001 * Insert unmanaged entries, writeable first, at the head of 1002 * the pv list. 1003 */ 1004 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1005 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1006 pvp = &SLIST_NEXT(*pvp, pv_link); 1007 } 1008 if (!PV_IS_WRITE_P(flags)) { 1009 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1010 pvp = &SLIST_NEXT(*pvp, pv_link); 1011 } 1012 #endif 1013 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1014 *pvp = pv; /* ... locked list */ 1015 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1016 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1017 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1018 md->pvh_attrs |= PVF_KMOD; 1019 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1020 md->pvh_attrs |= PVF_DIRTY; 1021 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1022 #endif 1023 if (pm == pmap_kernel()) { 1024 PMAPCOUNT(kernel_mappings); 1025 if (flags & PVF_WRITE) 1026 md->krw_mappings++; 1027 else 1028 md->kro_mappings++; 1029 } else { 1030 if (flags & PVF_WRITE) 1031 md->urw_mappings++; 1032 else 1033 md->uro_mappings++; 1034 } 1035 1036 #ifdef PMAP_CACHE_VIPT 1037 #ifndef ARM_MMU_EXTENDED 1038 /* 1039 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1040 * do it here as well to keep the mappings & KVF_WRITE consistent. 1041 */ 1042 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1043 md->pvh_attrs |= PVF_WRITE; 1044 } 1045 #endif 1046 /* 1047 * If this is an exec mapping and its the first exec mapping 1048 * for this page, make sure to sync the I-cache. 1049 */ 1050 if (PV_IS_EXEC_P(flags)) { 1051 #ifndef ARM_MMU_EXTENDED 1052 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1053 pmap_syncicache_page(md, pa); 1054 PMAPCOUNT(exec_synced_map); 1055 } 1056 #endif 1057 PMAPCOUNT(exec_mappings); 1058 } 1059 #endif 1060 1061 PMAPCOUNT(mappings); 1062 1063 if (pv->pv_flags & PVF_WIRED) 1064 ++pm->pm_stats.wired_count; 1065 } 1066 1067 /* 1068 * 1069 * pmap_find_pv: Find a pv entry 1070 * 1071 * => caller should hold lock on vm_page 1072 */ 1073 static inline struct pv_entry * 1074 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1075 { 1076 struct pv_entry *pv; 1077 1078 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1079 if (pm == pv->pv_pmap && va == pv->pv_va) 1080 break; 1081 } 1082 1083 return (pv); 1084 } 1085 1086 /* 1087 * pmap_remove_pv: try to remove a mapping from a pv_list 1088 * 1089 * => caller should hold proper lock on pmap_main_lock 1090 * => pmap should be locked 1091 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1092 * => caller should adjust ptp's wire_count and free PTP if needed 1093 * => caller should NOT adjust pmap's wire_count 1094 * => we return the removed pv 1095 */ 1096 static struct pv_entry * 1097 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1098 { 1099 struct pv_entry *pv, **prevptr; 1100 1101 NPDEBUG(PDB_PVDUMP, 1102 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1103 1104 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1105 pv = *prevptr; 1106 1107 while (pv) { 1108 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1109 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1110 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1111 if (pv->pv_flags & PVF_WIRED) { 1112 --pm->pm_stats.wired_count; 1113 } 1114 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1115 if (pm == pmap_kernel()) { 1116 PMAPCOUNT(kernel_unmappings); 1117 if (pv->pv_flags & PVF_WRITE) 1118 md->krw_mappings--; 1119 else 1120 md->kro_mappings--; 1121 } else { 1122 if (pv->pv_flags & PVF_WRITE) 1123 md->urw_mappings--; 1124 else 1125 md->uro_mappings--; 1126 } 1127 1128 PMAPCOUNT(unmappings); 1129 #ifdef PMAP_CACHE_VIPT 1130 if (!(pv->pv_flags & PVF_WRITE)) 1131 break; 1132 /* 1133 * If this page has had an exec mapping, then if 1134 * this was the last mapping, discard the contents, 1135 * otherwise sync the i-cache for this page. 1136 */ 1137 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1138 #ifdef ARM_MMU_EXTENDED 1139 md->pvh_attrs &= ~PVF_EXEC; 1140 PMAPCOUNT(exec_discarded_unmap); 1141 #else 1142 if (SLIST_EMPTY(&md->pvh_list)) { 1143 md->pvh_attrs &= ~PVF_EXEC; 1144 PMAPCOUNT(exec_discarded_unmap); 1145 } else { 1146 pmap_syncicache_page(md, pa); 1147 PMAPCOUNT(exec_synced_unmap); 1148 } 1149 #endif /* ARM_MMU_EXTENDED */ 1150 } 1151 #endif /* PMAP_CACHE_VIPT */ 1152 break; 1153 } 1154 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1155 pv = *prevptr; /* advance */ 1156 } 1157 1158 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1159 /* 1160 * If we no longer have a WRITEABLE KENTRY at the head of list, 1161 * clear the KMOD attribute from the page. 1162 */ 1163 if (SLIST_FIRST(&md->pvh_list) == NULL 1164 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1165 md->pvh_attrs &= ~PVF_KMOD; 1166 1167 /* 1168 * If this was a writeable page and there are no more writeable 1169 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1170 * the contents to memory. 1171 */ 1172 if (arm_cache_prefer_mask != 0) { 1173 if (md->krw_mappings + md->urw_mappings == 0) 1174 md->pvh_attrs &= ~PVF_WRITE; 1175 PMAP_VALIDATE_MD_PAGE(md); 1176 } 1177 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1178 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1179 1180 return(pv); /* return removed pv */ 1181 } 1182 1183 /* 1184 * 1185 * pmap_modify_pv: Update pv flags 1186 * 1187 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1188 * => caller should NOT adjust pmap's wire_count 1189 * => caller must call pmap_vac_me_harder() if writable status of a page 1190 * may have changed. 1191 * => we return the old flags 1192 * 1193 * Modify a physical-virtual mapping in the pv table 1194 */ 1195 static u_int 1196 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1197 u_int clr_mask, u_int set_mask) 1198 { 1199 struct pv_entry *npv; 1200 u_int flags, oflags; 1201 1202 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1203 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1204 1205 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1206 return (0); 1207 1208 NPDEBUG(PDB_PVDUMP, 1209 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1210 1211 /* 1212 * There is at least one VA mapping this page. 1213 */ 1214 1215 if (clr_mask & (PVF_REF | PVF_MOD)) { 1216 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1217 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1218 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1219 md->pvh_attrs |= PVF_DIRTY; 1220 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1221 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1222 } 1223 1224 oflags = npv->pv_flags; 1225 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1226 1227 if ((flags ^ oflags) & PVF_WIRED) { 1228 if (flags & PVF_WIRED) 1229 ++pm->pm_stats.wired_count; 1230 else 1231 --pm->pm_stats.wired_count; 1232 } 1233 1234 if ((flags ^ oflags) & PVF_WRITE) { 1235 if (pm == pmap_kernel()) { 1236 if (flags & PVF_WRITE) { 1237 md->krw_mappings++; 1238 md->kro_mappings--; 1239 } else { 1240 md->kro_mappings++; 1241 md->krw_mappings--; 1242 } 1243 } else { 1244 if (flags & PVF_WRITE) { 1245 md->urw_mappings++; 1246 md->uro_mappings--; 1247 } else { 1248 md->uro_mappings++; 1249 md->urw_mappings--; 1250 } 1251 } 1252 } 1253 #ifdef PMAP_CACHE_VIPT 1254 if (arm_cache_prefer_mask != 0) { 1255 if (md->urw_mappings + md->krw_mappings == 0) { 1256 md->pvh_attrs &= ~PVF_WRITE; 1257 } else { 1258 md->pvh_attrs |= PVF_WRITE; 1259 } 1260 } 1261 #ifndef ARM_MMU_EXTENDED 1262 /* 1263 * We have two cases here: the first is from enter_pv (new exec 1264 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1265 * Since in latter, pmap_enter_pv won't do anything, we just have 1266 * to do what pmap_remove_pv would do. 1267 */ 1268 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1269 || (PV_IS_EXEC_P(md->pvh_attrs) 1270 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1271 pmap_syncicache_page(md, pa); 1272 PMAPCOUNT(exec_synced_remap); 1273 } 1274 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1275 #endif /* !ARM_MMU_EXTENDED */ 1276 #endif /* PMAP_CACHE_VIPT */ 1277 1278 PMAPCOUNT(remappings); 1279 1280 return (oflags); 1281 } 1282 1283 /* 1284 * Allocate an L1 translation table for the specified pmap. 1285 * This is called at pmap creation time. 1286 */ 1287 static void 1288 pmap_alloc_l1(pmap_t pm) 1289 { 1290 #ifdef ARM_MMU_EXTENDED 1291 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1292 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1293 struct vm_page *pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1294 #else 1295 struct vm_page *pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1296 #endif 1297 KASSERT(pg != NULL); 1298 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1299 vaddr_t va = KERNEL_BASE + (pm->pm_l1_pa - physical_start); 1300 1301 #else 1302 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1303 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1304 UVM_KMF_WIRED|UVM_KMF_ZERO); 1305 KASSERT(!va); 1306 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1307 #endif 1308 pm->pm_l1 = (pd_entry_t *)va; 1309 #else 1310 struct l1_ttable *l1; 1311 uint8_t domain; 1312 1313 /* 1314 * Remove the L1 at the head of the LRU list 1315 */ 1316 mutex_spin_enter(&l1_lru_lock); 1317 l1 = TAILQ_FIRST(&l1_lru_list); 1318 KDASSERT(l1 != NULL); 1319 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1320 1321 /* 1322 * Pick the first available domain number, and update 1323 * the link to the next number. 1324 */ 1325 domain = l1->l1_domain_first; 1326 l1->l1_domain_first = l1->l1_domain_free[domain]; 1327 1328 /* 1329 * If there are still free domain numbers in this L1, 1330 * put it back on the TAIL of the LRU list. 1331 */ 1332 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1333 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1334 1335 mutex_spin_exit(&l1_lru_lock); 1336 1337 /* 1338 * Fix up the relevant bits in the pmap structure 1339 */ 1340 pm->pm_l1 = l1; 1341 pm->pm_domain = domain + 1; 1342 #endif 1343 } 1344 1345 /* 1346 * Free an L1 translation table. 1347 * This is called at pmap destruction time. 1348 */ 1349 static void 1350 pmap_free_l1(pmap_t pm) 1351 { 1352 #ifdef ARM_MMU_EXTENDED 1353 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1354 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1355 uvm_pagefree(pg); 1356 #else 1357 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1358 #endif 1359 pm->pm_l1 = NULL; 1360 pm->pm_l1_pa = 0; 1361 #else 1362 struct l1_ttable *l1 = pm->pm_l1; 1363 1364 mutex_spin_enter(&l1_lru_lock); 1365 1366 /* 1367 * If this L1 is currently on the LRU list, remove it. 1368 */ 1369 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1370 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1371 1372 /* 1373 * Free up the domain number which was allocated to the pmap 1374 */ 1375 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1376 l1->l1_domain_first = pmap_domain(pm) - 1; 1377 l1->l1_domain_use_count--; 1378 1379 /* 1380 * The L1 now must have at least 1 free domain, so add 1381 * it back to the LRU list. If the use count is zero, 1382 * put it at the head of the list, otherwise it goes 1383 * to the tail. 1384 */ 1385 if (l1->l1_domain_use_count == 0) 1386 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1387 else 1388 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1389 1390 mutex_spin_exit(&l1_lru_lock); 1391 #endif /* ARM_MMU_EXTENDED */ 1392 } 1393 1394 #ifndef ARM_MMU_EXTENDED 1395 static inline void 1396 pmap_use_l1(pmap_t pm) 1397 { 1398 struct l1_ttable *l1; 1399 1400 /* 1401 * Do nothing if we're in interrupt context. 1402 * Access to an L1 by the kernel pmap must not affect 1403 * the LRU list. 1404 */ 1405 if (cpu_intr_p() || pm == pmap_kernel()) 1406 return; 1407 1408 l1 = pm->pm_l1; 1409 1410 /* 1411 * If the L1 is not currently on the LRU list, just return 1412 */ 1413 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1414 return; 1415 1416 mutex_spin_enter(&l1_lru_lock); 1417 1418 /* 1419 * Check the use count again, now that we've acquired the lock 1420 */ 1421 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1422 mutex_spin_exit(&l1_lru_lock); 1423 return; 1424 } 1425 1426 /* 1427 * Move the L1 to the back of the LRU list 1428 */ 1429 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1430 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1431 1432 mutex_spin_exit(&l1_lru_lock); 1433 } 1434 #endif /* !ARM_MMU_EXTENDED */ 1435 1436 /* 1437 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1438 * 1439 * Free an L2 descriptor table. 1440 */ 1441 static inline void 1442 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1443 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1444 #else 1445 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1446 #endif 1447 { 1448 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1449 /* 1450 * Note: With a write-back cache, we may need to sync this 1451 * L2 table before re-using it. 1452 * This is because it may have belonged to a non-current 1453 * pmap, in which case the cache syncs would have been 1454 * skipped for the pages that were being unmapped. If the 1455 * L2 table were then to be immediately re-allocated to 1456 * the *current* pmap, it may well contain stale mappings 1457 * which have not yet been cleared by a cache write-back 1458 * and so would still be visible to the mmu. 1459 */ 1460 if (need_sync) 1461 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1462 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1463 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1464 } 1465 1466 /* 1467 * Returns a pointer to the L2 bucket associated with the specified pmap 1468 * and VA, or NULL if no L2 bucket exists for the address. 1469 */ 1470 static inline struct l2_bucket * 1471 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1472 { 1473 const size_t l1slot = l1pte_index(va); 1474 struct l2_dtable *l2; 1475 struct l2_bucket *l2b; 1476 1477 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1478 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1479 return (NULL); 1480 1481 return (l2b); 1482 } 1483 1484 /* 1485 * Returns a pointer to the L2 bucket associated with the specified pmap 1486 * and VA. 1487 * 1488 * If no L2 bucket exists, perform the necessary allocations to put an L2 1489 * bucket/page table in place. 1490 * 1491 * Note that if a new L2 bucket/page was allocated, the caller *must* 1492 * increment the bucket occupancy counter appropriately *before* 1493 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1494 * the bucket/page in the meantime. 1495 */ 1496 static struct l2_bucket * 1497 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1498 { 1499 const size_t l1slot = l1pte_index(va); 1500 struct l2_dtable *l2; 1501 1502 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1503 /* 1504 * No mapping at this address, as there is 1505 * no entry in the L1 table. 1506 * Need to allocate a new l2_dtable. 1507 */ 1508 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1509 return (NULL); 1510 1511 /* 1512 * Link it into the parent pmap 1513 */ 1514 pm->pm_l2[L2_IDX(l1slot)] = l2; 1515 } 1516 1517 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1518 1519 /* 1520 * Fetch pointer to the L2 page table associated with the address. 1521 */ 1522 if (l2b->l2b_kva == NULL) { 1523 pt_entry_t *ptep; 1524 1525 /* 1526 * No L2 page table has been allocated. Chances are, this 1527 * is because we just allocated the l2_dtable, above. 1528 */ 1529 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1530 /* 1531 * Oops, no more L2 page tables available at this 1532 * time. We may need to deallocate the l2_dtable 1533 * if we allocated a new one above. 1534 */ 1535 if (l2->l2_occupancy == 0) { 1536 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1537 pmap_free_l2_dtable(l2); 1538 } 1539 return (NULL); 1540 } 1541 1542 l2->l2_occupancy++; 1543 l2b->l2b_kva = ptep; 1544 l2b->l2b_l1slot = l1slot; 1545 1546 #ifdef ARM_MMU_EXTENDED 1547 /* 1548 * We know there will be a mapping here, so simply 1549 * enter this PTP into the L1 now. 1550 */ 1551 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1552 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1553 | L1_C_DOM(pmap_domain(pm)); 1554 KASSERT(*pdep == 0); 1555 l1pte_setone(pdep, npde); 1556 PTE_SYNC(pdep); 1557 #endif 1558 } 1559 1560 return (l2b); 1561 } 1562 1563 /* 1564 * One or more mappings in the specified L2 descriptor table have just been 1565 * invalidated. 1566 * 1567 * Garbage collect the metadata and descriptor table itself if necessary. 1568 * 1569 * The pmap lock must be acquired when this is called (not necessary 1570 * for the kernel pmap). 1571 */ 1572 static void 1573 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1574 { 1575 KDASSERT(count <= l2b->l2b_occupancy); 1576 1577 /* 1578 * Update the bucket's reference count according to how many 1579 * PTEs the caller has just invalidated. 1580 */ 1581 l2b->l2b_occupancy -= count; 1582 1583 /* 1584 * Note: 1585 * 1586 * Level 2 page tables allocated to the kernel pmap are never freed 1587 * as that would require checking all Level 1 page tables and 1588 * removing any references to the Level 2 page table. See also the 1589 * comment elsewhere about never freeing bootstrap L2 descriptors. 1590 * 1591 * We make do with just invalidating the mapping in the L2 table. 1592 * 1593 * This isn't really a big deal in practice and, in fact, leads 1594 * to a performance win over time as we don't need to continually 1595 * alloc/free. 1596 */ 1597 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1598 return; 1599 1600 /* 1601 * There are no more valid mappings in this level 2 page table. 1602 * Go ahead and NULL-out the pointer in the bucket, then 1603 * free the page table. 1604 */ 1605 const size_t l1slot = l2b->l2b_l1slot; 1606 pt_entry_t * const ptep = l2b->l2b_kva; 1607 l2b->l2b_kva = NULL; 1608 1609 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1610 pd_entry_t pde = *pdep; 1611 1612 #ifdef ARM_MMU_EXTENDED 1613 /* 1614 * Invalidate the L1 slot. 1615 */ 1616 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1617 #else 1618 /* 1619 * If the L1 slot matches the pmap's domain number, then invalidate it. 1620 */ 1621 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1622 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1623 #endif 1624 l1pte_setone(pdep, 0); 1625 PDE_SYNC(pdep); 1626 #ifndef ARM_MMU_EXTENDED 1627 } 1628 #endif 1629 1630 /* 1631 * Release the L2 descriptor table back to the pool cache. 1632 */ 1633 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1634 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1635 #else 1636 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1637 #endif 1638 1639 /* 1640 * Update the reference count in the associated l2_dtable 1641 */ 1642 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1643 if (--l2->l2_occupancy > 0) 1644 return; 1645 1646 /* 1647 * There are no more valid mappings in any of the Level 1 1648 * slots managed by this l2_dtable. Go ahead and NULL-out 1649 * the pointer in the parent pmap and free the l2_dtable. 1650 */ 1651 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1652 pmap_free_l2_dtable(l2); 1653 } 1654 1655 /* 1656 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1657 * structures. 1658 */ 1659 static int 1660 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1661 { 1662 #ifndef PMAP_INCLUDE_PTE_SYNC 1663 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1664 1665 /* 1666 * The mappings for these page tables were initially made using 1667 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1668 * mode will not be right for page table mappings. To avoid 1669 * polluting the pmap_kenter_pa() code with a special case for 1670 * page tables, we simply fix up the cache-mode here if it's not 1671 * correct. 1672 */ 1673 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1674 const struct l2_bucket * const l2b = 1675 pmap_get_l2_bucket(pmap_kernel(), va); 1676 KASSERTMSG(l2b != NULL, "%#lx", va); 1677 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1678 const pt_entry_t opte = *ptep; 1679 1680 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1681 /* 1682 * Page tables must have the cache-mode set correctly. 1683 */ 1684 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1685 | pte_l2_s_cache_mode_pt; 1686 l2pte_set(ptep, npte, opte); 1687 PTE_SYNC(ptep); 1688 cpu_tlb_flushD_SE(va); 1689 cpu_cpwait(); 1690 } 1691 } 1692 #endif 1693 1694 memset(v, 0, L2_TABLE_SIZE_REAL); 1695 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1696 return (0); 1697 } 1698 1699 static int 1700 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1701 { 1702 1703 memset(v, 0, sizeof(struct l2_dtable)); 1704 return (0); 1705 } 1706 1707 static int 1708 pmap_pmap_ctor(void *arg, void *v, int flags) 1709 { 1710 1711 memset(v, 0, sizeof(struct pmap)); 1712 return (0); 1713 } 1714 1715 static void 1716 pmap_pinit(pmap_t pm) 1717 { 1718 #ifndef ARM_HAS_VBAR 1719 struct l2_bucket *l2b; 1720 1721 if (vector_page < KERNEL_BASE) { 1722 /* 1723 * Map the vector page. 1724 */ 1725 pmap_enter(pm, vector_page, systempage.pv_pa, 1726 VM_PROT_READ | VM_PROT_EXECUTE, 1727 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1728 pmap_update(pm); 1729 1730 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1731 l2b = pmap_get_l2_bucket(pm, vector_page); 1732 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1733 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1734 L1_C_DOM(pmap_domain(pm)); 1735 } else 1736 pm->pm_pl1vec = NULL; 1737 #endif 1738 } 1739 1740 #ifdef PMAP_CACHE_VIVT 1741 /* 1742 * Since we have a virtually indexed cache, we may need to inhibit caching if 1743 * there is more than one mapping and at least one of them is writable. 1744 * Since we purge the cache on every context switch, we only need to check for 1745 * other mappings within the same pmap, or kernel_pmap. 1746 * This function is also called when a page is unmapped, to possibly reenable 1747 * caching on any remaining mappings. 1748 * 1749 * The code implements the following logic, where: 1750 * 1751 * KW = # of kernel read/write pages 1752 * KR = # of kernel read only pages 1753 * UW = # of user read/write pages 1754 * UR = # of user read only pages 1755 * 1756 * KC = kernel mapping is cacheable 1757 * UC = user mapping is cacheable 1758 * 1759 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1760 * +--------------------------------------------- 1761 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1762 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1763 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1764 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1765 */ 1766 1767 static const int pmap_vac_flags[4][4] = { 1768 {-1, 0, 0, PVF_KNC}, 1769 {0, 0, PVF_NC, PVF_NC}, 1770 {0, PVF_NC, PVF_NC, PVF_NC}, 1771 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1772 }; 1773 1774 static inline int 1775 pmap_get_vac_flags(const struct vm_page_md *md) 1776 { 1777 int kidx, uidx; 1778 1779 kidx = 0; 1780 if (md->kro_mappings || md->krw_mappings > 1) 1781 kidx |= 1; 1782 if (md->krw_mappings) 1783 kidx |= 2; 1784 1785 uidx = 0; 1786 if (md->uro_mappings || md->urw_mappings > 1) 1787 uidx |= 1; 1788 if (md->urw_mappings) 1789 uidx |= 2; 1790 1791 return (pmap_vac_flags[uidx][kidx]); 1792 } 1793 1794 static inline void 1795 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1796 { 1797 int nattr; 1798 1799 nattr = pmap_get_vac_flags(md); 1800 1801 if (nattr < 0) { 1802 md->pvh_attrs &= ~PVF_NC; 1803 return; 1804 } 1805 1806 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1807 return; 1808 1809 if (pm == pmap_kernel()) 1810 pmap_vac_me_kpmap(md, pa, pm, va); 1811 else 1812 pmap_vac_me_user(md, pa, pm, va); 1813 1814 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1815 } 1816 1817 static void 1818 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1819 { 1820 u_int u_cacheable, u_entries; 1821 struct pv_entry *pv; 1822 pmap_t last_pmap = pm; 1823 1824 /* 1825 * Pass one, see if there are both kernel and user pmaps for 1826 * this page. Calculate whether there are user-writable or 1827 * kernel-writable pages. 1828 */ 1829 u_cacheable = 0; 1830 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1831 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1832 u_cacheable++; 1833 } 1834 1835 u_entries = md->urw_mappings + md->uro_mappings; 1836 1837 /* 1838 * We know we have just been updating a kernel entry, so if 1839 * all user pages are already cacheable, then there is nothing 1840 * further to do. 1841 */ 1842 if (md->k_mappings == 0 && u_cacheable == u_entries) 1843 return; 1844 1845 if (u_entries) { 1846 /* 1847 * Scan over the list again, for each entry, if it 1848 * might not be set correctly, call pmap_vac_me_user 1849 * to recalculate the settings. 1850 */ 1851 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1852 /* 1853 * We know kernel mappings will get set 1854 * correctly in other calls. We also know 1855 * that if the pmap is the same as last_pmap 1856 * then we've just handled this entry. 1857 */ 1858 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1859 continue; 1860 1861 /* 1862 * If there are kernel entries and this page 1863 * is writable but non-cacheable, then we can 1864 * skip this entry also. 1865 */ 1866 if (md->k_mappings && 1867 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1868 (PVF_NC | PVF_WRITE)) 1869 continue; 1870 1871 /* 1872 * Similarly if there are no kernel-writable 1873 * entries and the page is already 1874 * read-only/cacheable. 1875 */ 1876 if (md->krw_mappings == 0 && 1877 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1878 continue; 1879 1880 /* 1881 * For some of the remaining cases, we know 1882 * that we must recalculate, but for others we 1883 * can't tell if they are correct or not, so 1884 * we recalculate anyway. 1885 */ 1886 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1887 } 1888 1889 if (md->k_mappings == 0) 1890 return; 1891 } 1892 1893 pmap_vac_me_user(md, pa, pm, va); 1894 } 1895 1896 static void 1897 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1898 { 1899 pmap_t kpmap = pmap_kernel(); 1900 struct pv_entry *pv, *npv = NULL; 1901 u_int entries = 0; 1902 u_int writable = 0; 1903 u_int cacheable_entries = 0; 1904 u_int kern_cacheable = 0; 1905 u_int other_writable = 0; 1906 1907 /* 1908 * Count mappings and writable mappings in this pmap. 1909 * Include kernel mappings as part of our own. 1910 * Keep a pointer to the first one. 1911 */ 1912 npv = NULL; 1913 KASSERT(pmap_page_locked_p(md)); 1914 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1915 /* Count mappings in the same pmap */ 1916 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1917 if (entries++ == 0) 1918 npv = pv; 1919 1920 /* Cacheable mappings */ 1921 if ((pv->pv_flags & PVF_NC) == 0) { 1922 cacheable_entries++; 1923 if (kpmap == pv->pv_pmap) 1924 kern_cacheable++; 1925 } 1926 1927 /* Writable mappings */ 1928 if (pv->pv_flags & PVF_WRITE) 1929 ++writable; 1930 } else 1931 if (pv->pv_flags & PVF_WRITE) 1932 other_writable = 1; 1933 } 1934 1935 /* 1936 * Enable or disable caching as necessary. 1937 * Note: the first entry might be part of the kernel pmap, 1938 * so we can't assume this is indicative of the state of the 1939 * other (maybe non-kpmap) entries. 1940 */ 1941 if ((entries > 1 && writable) || 1942 (entries > 0 && pm == kpmap && other_writable)) { 1943 if (cacheable_entries == 0) { 1944 return; 1945 } 1946 1947 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1948 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1949 (pv->pv_flags & PVF_NC)) 1950 continue; 1951 1952 pv->pv_flags |= PVF_NC; 1953 1954 struct l2_bucket * const l2b 1955 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1956 KASSERTMSG(l2b != NULL, "%#lx", va); 1957 pt_entry_t * const ptep 1958 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1959 const pt_entry_t opte = *ptep; 1960 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1961 1962 if ((va != pv->pv_va || pm != pv->pv_pmap) 1963 && l2pte_valid_p(npte)) { 1964 #ifdef PMAP_CACHE_VIVT 1965 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1966 true, pv->pv_flags); 1967 #endif 1968 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1969 pv->pv_flags); 1970 } 1971 1972 l2pte_set(ptep, npte, opte); 1973 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1974 } 1975 cpu_cpwait(); 1976 } else 1977 if (entries > cacheable_entries) { 1978 /* 1979 * Turn cacheing back on for some pages. If it is a kernel 1980 * page, only do so if there are no other writable pages. 1981 */ 1982 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1983 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1984 (kpmap != pv->pv_pmap || other_writable))) 1985 continue; 1986 1987 pv->pv_flags &= ~PVF_NC; 1988 1989 struct l2_bucket * const l2b 1990 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1991 KASSERTMSG(l2b != NULL, "%#lx", va); 1992 pt_entry_t * const ptep 1993 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1994 const pt_entry_t opte = *ptep; 1995 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1996 | pte_l2_s_cache_mode; 1997 1998 if (l2pte_valid_p(opte)) { 1999 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2000 pv->pv_flags); 2001 } 2002 2003 l2pte_set(ptep, npte, opte); 2004 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2005 } 2006 } 2007 } 2008 #endif 2009 2010 #ifdef PMAP_CACHE_VIPT 2011 static void 2012 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2013 { 2014 #ifndef ARM_MMU_EXTENDED 2015 struct pv_entry *pv; 2016 vaddr_t tst_mask; 2017 bool bad_alias; 2018 const u_int 2019 rw_mappings = md->urw_mappings + md->krw_mappings, 2020 ro_mappings = md->uro_mappings + md->kro_mappings; 2021 2022 /* do we need to do anything? */ 2023 if (arm_cache_prefer_mask == 0) 2024 return; 2025 2026 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2027 md, pm, va)); 2028 2029 KASSERT(!va || pm); 2030 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2031 2032 /* Already a conflict? */ 2033 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2034 /* just an add, things are already non-cached */ 2035 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2036 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2037 bad_alias = false; 2038 if (va) { 2039 PMAPCOUNT(vac_color_none); 2040 bad_alias = true; 2041 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2042 goto fixup; 2043 } 2044 pv = SLIST_FIRST(&md->pvh_list); 2045 /* the list can't be empty because it would be cachable */ 2046 if (md->pvh_attrs & PVF_KMPAGE) { 2047 tst_mask = md->pvh_attrs; 2048 } else { 2049 KASSERT(pv); 2050 tst_mask = pv->pv_va; 2051 pv = SLIST_NEXT(pv, pv_link); 2052 } 2053 /* 2054 * Only check for a bad alias if we have writable mappings. 2055 */ 2056 tst_mask &= arm_cache_prefer_mask; 2057 if (rw_mappings > 0) { 2058 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2059 /* if there's a bad alias, stop checking. */ 2060 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2061 bad_alias = true; 2062 } 2063 md->pvh_attrs |= PVF_WRITE; 2064 if (!bad_alias) 2065 md->pvh_attrs |= PVF_DIRTY; 2066 } else { 2067 /* 2068 * We have only read-only mappings. Let's see if there 2069 * are multiple colors in use or if we mapped a KMPAGE. 2070 * If the latter, we have a bad alias. If the former, 2071 * we need to remember that. 2072 */ 2073 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2074 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2075 if (md->pvh_attrs & PVF_KMPAGE) 2076 bad_alias = true; 2077 break; 2078 } 2079 } 2080 md->pvh_attrs &= ~PVF_WRITE; 2081 /* 2082 * No KMPAGE and we exited early, so we must have 2083 * multiple color mappings. 2084 */ 2085 if (!bad_alias && pv != NULL) 2086 md->pvh_attrs |= PVF_MULTCLR; 2087 } 2088 2089 /* If no conflicting colors, set everything back to cached */ 2090 if (!bad_alias) { 2091 #ifdef DEBUG 2092 if ((md->pvh_attrs & PVF_WRITE) 2093 || ro_mappings < 2) { 2094 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2095 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2096 } 2097 #endif 2098 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2099 md->pvh_attrs |= tst_mask | PVF_COLORED; 2100 /* 2101 * Restore DIRTY bit if page is modified 2102 */ 2103 if (md->pvh_attrs & PVF_DMOD) 2104 md->pvh_attrs |= PVF_DIRTY; 2105 PMAPCOUNT(vac_color_restore); 2106 } else { 2107 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2108 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2109 } 2110 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2111 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2112 } else if (!va) { 2113 KASSERT(pmap_is_page_colored_p(md)); 2114 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2115 || (md->pvh_attrs & PVF_DIRTY)); 2116 if (rw_mappings == 0) { 2117 md->pvh_attrs &= ~PVF_WRITE; 2118 if (ro_mappings == 1 2119 && (md->pvh_attrs & PVF_MULTCLR)) { 2120 /* 2121 * If this is the last readonly mapping 2122 * but it doesn't match the current color 2123 * for the page, change the current color 2124 * to match this last readonly mapping. 2125 */ 2126 pv = SLIST_FIRST(&md->pvh_list); 2127 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2128 & arm_cache_prefer_mask; 2129 if (tst_mask) { 2130 md->pvh_attrs ^= tst_mask; 2131 PMAPCOUNT(vac_color_change); 2132 } 2133 } 2134 } 2135 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2136 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2137 return; 2138 } else if (!pmap_is_page_colored_p(md)) { 2139 /* not colored so we just use its color */ 2140 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2141 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2142 PMAPCOUNT(vac_color_new); 2143 md->pvh_attrs &= PAGE_SIZE - 1; 2144 md->pvh_attrs |= PVF_COLORED 2145 | (va & arm_cache_prefer_mask) 2146 | (rw_mappings > 0 ? PVF_WRITE : 0); 2147 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2148 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2149 return; 2150 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2151 bad_alias = false; 2152 if (rw_mappings > 0) { 2153 /* 2154 * We now have writeable mappings and if we have 2155 * readonly mappings in more than once color, we have 2156 * an aliasing problem. Regardless mark the page as 2157 * writeable. 2158 */ 2159 if (md->pvh_attrs & PVF_MULTCLR) { 2160 if (ro_mappings < 2) { 2161 /* 2162 * If we only have less than two 2163 * read-only mappings, just flush the 2164 * non-primary colors from the cache. 2165 */ 2166 pmap_flush_page(md, pa, 2167 PMAP_FLUSH_SECONDARY); 2168 } else { 2169 bad_alias = true; 2170 } 2171 } 2172 md->pvh_attrs |= PVF_WRITE; 2173 } 2174 /* If no conflicting colors, set everything back to cached */ 2175 if (!bad_alias) { 2176 #ifdef DEBUG 2177 if (rw_mappings > 0 2178 || (md->pvh_attrs & PMAP_KMPAGE)) { 2179 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2180 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2181 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2182 } 2183 #endif 2184 if (SLIST_EMPTY(&md->pvh_list)) 2185 PMAPCOUNT(vac_color_reuse); 2186 else 2187 PMAPCOUNT(vac_color_ok); 2188 2189 /* matching color, just return */ 2190 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2191 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2192 return; 2193 } 2194 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2195 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2196 2197 /* color conflict. evict from cache. */ 2198 2199 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2200 md->pvh_attrs &= ~PVF_COLORED; 2201 md->pvh_attrs |= PVF_NC; 2202 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2203 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2204 PMAPCOUNT(vac_color_erase); 2205 } else if (rw_mappings == 0 2206 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2207 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2208 2209 /* 2210 * If the page has dirty cache lines, clean it. 2211 */ 2212 if (md->pvh_attrs & PVF_DIRTY) 2213 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2214 2215 /* 2216 * If this is the first remapping (we know that there are no 2217 * writeable mappings), then this is a simple color change. 2218 * Otherwise this is a seconary r/o mapping, which means 2219 * we don't have to do anything. 2220 */ 2221 if (ro_mappings == 1) { 2222 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2223 md->pvh_attrs &= PAGE_SIZE - 1; 2224 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2225 PMAPCOUNT(vac_color_change); 2226 } else { 2227 PMAPCOUNT(vac_color_blind); 2228 } 2229 md->pvh_attrs |= PVF_MULTCLR; 2230 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2231 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2232 return; 2233 } else { 2234 if (rw_mappings > 0) 2235 md->pvh_attrs |= PVF_WRITE; 2236 2237 /* color conflict. evict from cache. */ 2238 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2239 2240 /* the list can't be empty because this was a enter/modify */ 2241 pv = SLIST_FIRST(&md->pvh_list); 2242 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2243 KASSERT(pv); 2244 /* 2245 * If there's only one mapped page, change color to the 2246 * page's new color and return. Restore the DIRTY bit 2247 * that was erased by pmap_flush_page. 2248 */ 2249 if (SLIST_NEXT(pv, pv_link) == NULL) { 2250 md->pvh_attrs &= PAGE_SIZE - 1; 2251 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2252 if (md->pvh_attrs & PVF_DMOD) 2253 md->pvh_attrs |= PVF_DIRTY; 2254 PMAPCOUNT(vac_color_change); 2255 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2256 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2257 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2258 return; 2259 } 2260 } 2261 bad_alias = true; 2262 md->pvh_attrs &= ~PVF_COLORED; 2263 md->pvh_attrs |= PVF_NC; 2264 PMAPCOUNT(vac_color_erase); 2265 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2266 } 2267 2268 fixup: 2269 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2270 2271 /* 2272 * Turn cacheing on/off for all pages. 2273 */ 2274 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2275 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2276 pv->pv_va); 2277 KASSERTMSG(l2b != NULL, "%#lx", va); 2278 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2279 const pt_entry_t opte = *ptep; 2280 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2281 if (bad_alias) { 2282 pv->pv_flags |= PVF_NC; 2283 } else { 2284 pv->pv_flags &= ~PVF_NC; 2285 npte |= pte_l2_s_cache_mode; 2286 } 2287 2288 if (opte == npte) /* only update is there's a change */ 2289 continue; 2290 2291 if (l2pte_valid_p(npte)) { 2292 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2293 } 2294 2295 l2pte_set(ptep, npte, opte); 2296 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2297 } 2298 #endif /* !ARM_MMU_EXTENDED */ 2299 } 2300 #endif /* PMAP_CACHE_VIPT */ 2301 2302 2303 /* 2304 * Modify pte bits for all ptes corresponding to the given physical address. 2305 * We use `maskbits' rather than `clearbits' because we're always passing 2306 * constants and the latter would require an extra inversion at run-time. 2307 */ 2308 static void 2309 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2310 { 2311 struct pv_entry *pv; 2312 #ifdef PMAP_CACHE_VIPT 2313 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2314 #ifdef ARM_MMU_EXTENDED 2315 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2316 #else 2317 const u_int execbits = 0; 2318 bool need_vac_me_harder = false; 2319 bool need_syncicache = false; 2320 #endif 2321 #else 2322 const u_int execbits = 0; 2323 #endif 2324 2325 NPDEBUG(PDB_BITS, 2326 printf("pmap_clearbit: md %p mask 0x%x\n", 2327 md, maskbits)); 2328 2329 #ifdef PMAP_CACHE_VIPT 2330 /* 2331 * If we might want to sync the I-cache and we've modified it, 2332 * then we know we definitely need to sync or discard it. 2333 */ 2334 if (want_syncicache) { 2335 #ifdef ARM_MMU_EXTENDED 2336 if (md->pvh_attrs & PVF_MOD) 2337 md->pvh_attrs &= ~PVF_EXEC; 2338 #else 2339 need_syncicache = md->pvh_attrs & PVF_MOD; 2340 #endif 2341 } 2342 #endif 2343 KASSERT(pmap_page_locked_p(md)); 2344 2345 /* 2346 * Clear saved attributes (modify, reference) 2347 */ 2348 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2349 2350 if (SLIST_EMPTY(&md->pvh_list)) { 2351 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2352 if (need_syncicache) { 2353 /* 2354 * No one has it mapped, so just discard it. The next 2355 * exec remapping will cause it to be synced. 2356 */ 2357 md->pvh_attrs &= ~PVF_EXEC; 2358 PMAPCOUNT(exec_discarded_clearbit); 2359 } 2360 #endif 2361 return; 2362 } 2363 2364 /* 2365 * Loop over all current mappings setting/clearing as appropos 2366 */ 2367 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2368 pmap_t pm = pv->pv_pmap; 2369 const vaddr_t va = pv->pv_va; 2370 const u_int oflags = pv->pv_flags; 2371 #ifndef ARM_MMU_EXTENDED 2372 /* 2373 * Kernel entries are unmanaged and as such not to be changed. 2374 */ 2375 if (PV_IS_KENTRY_P(oflags)) 2376 continue; 2377 #endif 2378 pv->pv_flags &= ~maskbits; 2379 2380 pmap_release_page_lock(md); 2381 pmap_acquire_pmap_lock(pm); 2382 2383 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2384 if (l2b == NULL) { 2385 pmap_release_pmap_lock(pm); 2386 pmap_acquire_page_lock(md); 2387 continue; 2388 } 2389 KASSERTMSG(l2b != NULL, "%#lx", va); 2390 2391 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2392 const pt_entry_t opte = *ptep; 2393 pt_entry_t npte = opte | execbits; 2394 2395 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2396 2397 NPDEBUG(PDB_BITS, 2398 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2399 __func__, pv, pm, va, oflags)); 2400 2401 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2402 #ifdef PMAP_CACHE_VIVT 2403 if ((oflags & PVF_NC)) { 2404 /* 2405 * Entry is not cacheable: 2406 * 2407 * Don't turn caching on again if this is a 2408 * modified emulation. This would be 2409 * inconsitent with the settings created by 2410 * pmap_vac_me_harder(). Otherwise, it's safe 2411 * to re-enable cacheing. 2412 * 2413 * There's no need to call pmap_vac_me_harder() 2414 * here: all pages are losing their write 2415 * permission. 2416 */ 2417 if (maskbits & PVF_WRITE) { 2418 npte |= pte_l2_s_cache_mode; 2419 pv->pv_flags &= ~PVF_NC; 2420 } 2421 } else 2422 if (l2pte_writable_p(opte)) { 2423 /* 2424 * Entry is writable/cacheable: check if pmap 2425 * is current if it is flush it, otherwise it 2426 * won't be in the cache 2427 */ 2428 pmap_cache_wbinv_page(pm, va, 2429 (maskbits & PVF_REF) != 0, 2430 oflags|PVF_WRITE); 2431 } 2432 #endif 2433 2434 /* make the pte read only */ 2435 npte = l2pte_set_readonly(npte); 2436 2437 pmap_acquire_page_lock(md); 2438 #ifdef MULTIPROCESSOR 2439 pv = pmap_find_pv(md, pm, va); 2440 #endif 2441 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2442 /* 2443 * Keep alias accounting up to date 2444 */ 2445 if (pm == pmap_kernel()) { 2446 md->krw_mappings--; 2447 md->kro_mappings++; 2448 } else { 2449 md->urw_mappings--; 2450 md->uro_mappings++; 2451 } 2452 #ifdef PMAP_CACHE_VIPT 2453 if (arm_cache_prefer_mask != 0) { 2454 if (md->urw_mappings + md->krw_mappings == 0) { 2455 md->pvh_attrs &= ~PVF_WRITE; 2456 } else { 2457 PMAP_VALIDATE_MD_PAGE(md); 2458 } 2459 } 2460 #ifndef ARM_MMU_EXTENDED 2461 if (want_syncicache) 2462 need_syncicache = true; 2463 need_vac_me_harder = true; 2464 #endif 2465 #endif /* PMAP_CACHE_VIPT */ 2466 } 2467 pmap_release_page_lock(md); 2468 } 2469 2470 if (maskbits & PVF_REF) { 2471 if (true 2472 #ifndef ARM_MMU_EXTENDED 2473 && (oflags & PVF_NC) == 0 2474 #endif 2475 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2476 && l2pte_valid_p(npte)) { 2477 #ifdef PMAP_CACHE_VIVT 2478 /* 2479 * Check npte here; we may have already 2480 * done the wbinv above, and the validity 2481 * of the PTE is the same for opte and 2482 * npte. 2483 */ 2484 pmap_cache_wbinv_page(pm, va, true, oflags); 2485 #endif 2486 } 2487 2488 /* 2489 * Make the PTE invalid so that we will take a 2490 * page fault the next time the mapping is 2491 * referenced. 2492 */ 2493 npte &= ~L2_TYPE_MASK; 2494 npte |= L2_TYPE_INV; 2495 } 2496 2497 if (npte != opte) { 2498 l2pte_set(ptep, npte, opte); 2499 PTE_SYNC(ptep); 2500 2501 /* Flush the TLB entry if a current pmap. */ 2502 pmap_tlb_flush_SE(pm, va, oflags); 2503 } 2504 2505 pmap_release_pmap_lock(pm); 2506 pmap_acquire_page_lock(md); 2507 2508 NPDEBUG(PDB_BITS, 2509 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2510 pm, va, opte, npte)); 2511 } 2512 2513 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2514 /* 2515 * If we need to sync the I-cache and we haven't done it yet, do it. 2516 */ 2517 if (need_syncicache) { 2518 pmap_release_page_lock(md); 2519 pmap_syncicache_page(md, pa); 2520 pmap_acquire_page_lock(md); 2521 PMAPCOUNT(exec_synced_clearbit); 2522 } 2523 2524 /* 2525 * If we are changing this to read-only, we need to call vac_me_harder 2526 * so we can change all the read-only pages to cacheable. We pretend 2527 * this as a page deletion. 2528 */ 2529 if (need_vac_me_harder) { 2530 if (md->pvh_attrs & PVF_NC) 2531 pmap_vac_me_harder(md, pa, NULL, 0); 2532 } 2533 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2534 } 2535 2536 /* 2537 * pmap_clean_page() 2538 * 2539 * This is a local function used to work out the best strategy to clean 2540 * a single page referenced by its entry in the PV table. It's used by 2541 * pmap_copy_page, pmap_zero page and maybe some others later on. 2542 * 2543 * Its policy is effectively: 2544 * o If there are no mappings, we don't bother doing anything with the cache. 2545 * o If there is one mapping, we clean just that page. 2546 * o If there are multiple mappings, we clean the entire cache. 2547 * 2548 * So that some functions can be further optimised, it returns 0 if it didn't 2549 * clean the entire cache, or 1 if it did. 2550 * 2551 * XXX One bug in this routine is that if the pv_entry has a single page 2552 * mapped at 0x00000000 a whole cache clean will be performed rather than 2553 * just the 1 page. Since this should not occur in everyday use and if it does 2554 * it will just result in not the most efficient clean for the page. 2555 */ 2556 #ifdef PMAP_CACHE_VIVT 2557 static bool 2558 pmap_clean_page(struct vm_page_md *md, bool is_src) 2559 { 2560 struct pv_entry *pv; 2561 pmap_t pm_to_clean = NULL; 2562 bool cache_needs_cleaning = false; 2563 vaddr_t page_to_clean = 0; 2564 u_int flags = 0; 2565 2566 /* 2567 * Since we flush the cache each time we change to a different 2568 * user vmspace, we only need to flush the page if it is in the 2569 * current pmap. 2570 */ 2571 KASSERT(pmap_page_locked_p(md)); 2572 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2573 if (pmap_is_current(pv->pv_pmap)) { 2574 flags |= pv->pv_flags; 2575 /* 2576 * The page is mapped non-cacheable in 2577 * this map. No need to flush the cache. 2578 */ 2579 if (pv->pv_flags & PVF_NC) { 2580 #ifdef DIAGNOSTIC 2581 KASSERT(!cache_needs_cleaning); 2582 #endif 2583 break; 2584 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2585 continue; 2586 if (cache_needs_cleaning) { 2587 page_to_clean = 0; 2588 break; 2589 } else { 2590 page_to_clean = pv->pv_va; 2591 pm_to_clean = pv->pv_pmap; 2592 } 2593 cache_needs_cleaning = true; 2594 } 2595 } 2596 2597 if (page_to_clean) { 2598 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2599 !is_src, flags | PVF_REF); 2600 } else if (cache_needs_cleaning) { 2601 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2602 2603 pmap_cache_wbinv_all(pm, flags); 2604 return true; 2605 } 2606 return false; 2607 } 2608 #endif 2609 2610 #ifdef PMAP_CACHE_VIPT 2611 /* 2612 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2613 * right cache alias to make sure we flush the right stuff. 2614 */ 2615 void 2616 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2617 { 2618 pmap_t kpm = pmap_kernel(); 2619 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2620 ? PAGE_SIZE 2621 : arm_pcache.icache_way_size; 2622 2623 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2624 md, md->pvh_attrs)); 2625 /* 2626 * No need to clean the page if it's non-cached. 2627 */ 2628 #ifndef ARM_MMU_EXTENDED 2629 if (md->pvh_attrs & PVF_NC) 2630 return; 2631 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2632 #endif 2633 2634 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2635 if (way_size == PAGE_SIZE) { 2636 vaddr_t vdstp = KERNEL_BASE + (pa - physical_start); 2637 cpu_icache_sync_range(vdstp, way_size); 2638 return; 2639 } 2640 #endif 2641 2642 /* 2643 * We don't worry about the color of the exec page, we map the 2644 * same page to pages in the way and then do the icache_sync on 2645 * the entire way making sure we are cleaned. 2646 */ 2647 pt_entry_t * const ptep = cpu_cdst_pte(0); 2648 const vaddr_t dstp = cpu_cdstp(0); 2649 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2650 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2651 2652 for (size_t i = 0, j = 0; i < way_size; 2653 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2654 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2655 /* 2656 * Set up a PTE with to flush these cache lines. 2657 */ 2658 l2pte_set(ptep + j, npte, 0); 2659 } 2660 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2661 2662 /* 2663 * Flush it. 2664 */ 2665 cpu_icache_sync_range(dstp, way_size); 2666 2667 for (size_t i = 0, j = 0; i < way_size; 2668 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2669 /* 2670 * Unmap the page(s). 2671 */ 2672 l2pte_reset(ptep + j); 2673 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2674 } 2675 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2676 2677 md->pvh_attrs |= PVF_EXEC; 2678 PMAPCOUNT(exec_synced); 2679 } 2680 2681 #ifndef ARM_MMU_EXTENDED 2682 void 2683 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2684 { 2685 vsize_t va_offset, end_va; 2686 bool wbinv_p; 2687 2688 if (arm_cache_prefer_mask == 0) 2689 return; 2690 2691 switch (flush) { 2692 case PMAP_FLUSH_PRIMARY: 2693 if (md->pvh_attrs & PVF_MULTCLR) { 2694 va_offset = 0; 2695 end_va = arm_cache_prefer_mask; 2696 md->pvh_attrs &= ~PVF_MULTCLR; 2697 PMAPCOUNT(vac_flush_lots); 2698 } else { 2699 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2700 end_va = va_offset; 2701 PMAPCOUNT(vac_flush_one); 2702 } 2703 /* 2704 * Mark that the page is no longer dirty. 2705 */ 2706 md->pvh_attrs &= ~PVF_DIRTY; 2707 wbinv_p = true; 2708 break; 2709 case PMAP_FLUSH_SECONDARY: 2710 va_offset = 0; 2711 end_va = arm_cache_prefer_mask; 2712 wbinv_p = true; 2713 md->pvh_attrs &= ~PVF_MULTCLR; 2714 PMAPCOUNT(vac_flush_lots); 2715 break; 2716 case PMAP_CLEAN_PRIMARY: 2717 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2718 end_va = va_offset; 2719 wbinv_p = false; 2720 /* 2721 * Mark that the page is no longer dirty. 2722 */ 2723 if ((md->pvh_attrs & PVF_DMOD) == 0) 2724 md->pvh_attrs &= ~PVF_DIRTY; 2725 PMAPCOUNT(vac_clean_one); 2726 break; 2727 default: 2728 return; 2729 } 2730 2731 KASSERT(!(md->pvh_attrs & PVF_NC)); 2732 2733 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2734 md, md->pvh_attrs)); 2735 2736 const size_t scache_line_size = arm_scache.dcache_line_size; 2737 2738 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2739 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2740 const vaddr_t dstp = cpu_cdstp(va_offset); 2741 const pt_entry_t opte = *ptep; 2742 2743 if (flush == PMAP_FLUSH_SECONDARY 2744 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2745 continue; 2746 2747 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2748 /* 2749 * Set up a PTE with the right coloring to flush 2750 * existing cache entries. 2751 */ 2752 const pt_entry_t npte = L2_S_PROTO 2753 | pa 2754 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2755 | pte_l2_s_cache_mode; 2756 l2pte_set(ptep, npte, opte); 2757 PTE_SYNC(ptep); 2758 2759 /* 2760 * Flush it. Make sure to flush secondary cache too since 2761 * bus_dma will ignore uncached pages. 2762 */ 2763 if (scache_line_size != 0) { 2764 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2765 if (wbinv_p) { 2766 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2767 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2768 } else { 2769 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2770 } 2771 } else { 2772 if (wbinv_p) { 2773 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2774 } else { 2775 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2776 } 2777 } 2778 2779 /* 2780 * Restore the page table entry since we might have interrupted 2781 * pmap_zero_page or pmap_copy_page which was already using 2782 * this pte. 2783 */ 2784 if (opte) { 2785 l2pte_set(ptep, opte, npte); 2786 } else { 2787 l2pte_reset(ptep); 2788 } 2789 PTE_SYNC(ptep); 2790 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2791 } 2792 } 2793 #endif /* ARM_MMU_EXTENDED */ 2794 #endif /* PMAP_CACHE_VIPT */ 2795 2796 /* 2797 * Routine: pmap_page_remove 2798 * Function: 2799 * Removes this physical page from 2800 * all physical maps in which it resides. 2801 * Reflects back modify bits to the pager. 2802 */ 2803 static void 2804 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2805 { 2806 struct l2_bucket *l2b; 2807 struct pv_entry *pv; 2808 pt_entry_t *ptep; 2809 #ifndef ARM_MMU_EXTENDED 2810 bool flush = false; 2811 #endif 2812 u_int flags = 0; 2813 2814 NPDEBUG(PDB_FOLLOW, 2815 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2816 pa)); 2817 2818 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2819 pmap_acquire_page_lock(md); 2820 if (*pvp == NULL) { 2821 #ifdef PMAP_CACHE_VIPT 2822 /* 2823 * We *know* the page contents are about to be replaced. 2824 * Discard the exec contents 2825 */ 2826 if (PV_IS_EXEC_P(md->pvh_attrs)) 2827 PMAPCOUNT(exec_discarded_page_protect); 2828 md->pvh_attrs &= ~PVF_EXEC; 2829 PMAP_VALIDATE_MD_PAGE(md); 2830 #endif 2831 pmap_release_page_lock(md); 2832 return; 2833 } 2834 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2835 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2836 #endif 2837 2838 /* 2839 * Clear alias counts 2840 */ 2841 #ifdef PMAP_CACHE_VIVT 2842 md->k_mappings = 0; 2843 #endif 2844 md->urw_mappings = md->uro_mappings = 0; 2845 2846 #ifdef PMAP_CACHE_VIVT 2847 pmap_clean_page(md, false); 2848 #endif 2849 2850 while ((pv = *pvp) != NULL) { 2851 pmap_t pm = pv->pv_pmap; 2852 #ifndef ARM_MMU_EXTENDED 2853 if (flush == false && pmap_is_current(pm)) 2854 flush = true; 2855 #endif 2856 2857 if (pm == pmap_kernel()) { 2858 #ifdef PMAP_CACHE_VIPT 2859 /* 2860 * If this was unmanaged mapping, it must be preserved. 2861 * Move it back on the list and advance the end-of-list 2862 * pointer. 2863 */ 2864 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2865 *pvp = pv; 2866 pvp = &SLIST_NEXT(pv, pv_link); 2867 continue; 2868 } 2869 if (pv->pv_flags & PVF_WRITE) 2870 md->krw_mappings--; 2871 else 2872 md->kro_mappings--; 2873 #endif 2874 PMAPCOUNT(kernel_unmappings); 2875 } 2876 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2877 PMAPCOUNT(unmappings); 2878 2879 pmap_release_page_lock(md); 2880 pmap_acquire_pmap_lock(pm); 2881 2882 #ifdef ARM_MMU_EXTENDED 2883 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2884 #endif 2885 2886 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2887 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2888 2889 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2890 2891 /* 2892 * Update statistics 2893 */ 2894 --pm->pm_stats.resident_count; 2895 2896 /* Wired bit */ 2897 if (pv->pv_flags & PVF_WIRED) 2898 --pm->pm_stats.wired_count; 2899 2900 flags |= pv->pv_flags; 2901 2902 /* 2903 * Invalidate the PTEs. 2904 */ 2905 l2pte_reset(ptep); 2906 PTE_SYNC_CURRENT(pm, ptep); 2907 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2908 pmap_release_pmap_lock(pm); 2909 2910 pool_put(&pmap_pv_pool, pv); 2911 pmap_acquire_page_lock(md); 2912 #ifdef MULTIPROCESSOR 2913 /* 2914 * Restart of the beginning of the list. 2915 */ 2916 pvp = &SLIST_FIRST(&md->pvh_list); 2917 #endif 2918 } 2919 /* 2920 * if we reach the end of the list and there are still mappings, they 2921 * might be able to be cached now. And they must be kernel mappings. 2922 */ 2923 if (!SLIST_EMPTY(&md->pvh_list)) { 2924 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2925 } 2926 2927 #ifdef PMAP_CACHE_VIPT 2928 /* 2929 * Its EXEC cache is now gone. 2930 */ 2931 if (PV_IS_EXEC_P(md->pvh_attrs)) 2932 PMAPCOUNT(exec_discarded_page_protect); 2933 md->pvh_attrs &= ~PVF_EXEC; 2934 KASSERT(md->urw_mappings == 0); 2935 KASSERT(md->uro_mappings == 0); 2936 #ifndef ARM_MMU_EXTENDED 2937 if (arm_cache_prefer_mask != 0) { 2938 if (md->krw_mappings == 0) 2939 md->pvh_attrs &= ~PVF_WRITE; 2940 PMAP_VALIDATE_MD_PAGE(md); 2941 } 2942 #endif /* ARM_MMU_EXTENDED */ 2943 #endif /* PMAP_CACHE_VIPT */ 2944 pmap_release_page_lock(md); 2945 2946 #ifndef ARM_MMU_EXTENDED 2947 if (flush) { 2948 /* 2949 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2950 * would need a subsequent call to pmap_update() to ensure 2951 * curpm->pm_cstate.cs_all is reset. Our callers are not 2952 * required to do that (see pmap(9)), so we can't modify 2953 * the current pmap's state. 2954 */ 2955 if (PV_BEEN_EXECD(flags)) 2956 cpu_tlb_flushID(); 2957 else 2958 cpu_tlb_flushD(); 2959 } 2960 cpu_cpwait(); 2961 #endif /* ARM_MMU_EXTENDED */ 2962 } 2963 2964 /* 2965 * pmap_t pmap_create(void) 2966 * 2967 * Create a new pmap structure from scratch. 2968 */ 2969 pmap_t 2970 pmap_create(void) 2971 { 2972 pmap_t pm; 2973 2974 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2975 2976 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2977 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2978 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2979 2980 pm->pm_stats.wired_count = 0; 2981 pm->pm_stats.resident_count = 1; 2982 #ifdef ARM_MMU_EXTENDED 2983 #ifdef MULTIPROCESSOR 2984 kcpuset_create(&pm->pm_active, true); 2985 kcpuset_create(&pm->pm_onproc, true); 2986 #endif 2987 #else 2988 pm->pm_cstate.cs_all = 0; 2989 #endif 2990 pmap_alloc_l1(pm); 2991 2992 /* 2993 * Note: The pool cache ensures that the pm_l2[] array is already 2994 * initialised to zero. 2995 */ 2996 2997 pmap_pinit(pm); 2998 2999 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3000 3001 return (pm); 3002 } 3003 3004 u_int 3005 arm32_mmap_flags(paddr_t pa) 3006 { 3007 /* 3008 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3009 * and we're using the upper bits in page numbers to pass flags around 3010 * so we might as well use the same bits 3011 */ 3012 return (u_int)pa & PMAP_MD_MASK; 3013 } 3014 /* 3015 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3016 * u_int flags) 3017 * 3018 * Insert the given physical page (p) at 3019 * the specified virtual address (v) in the 3020 * target physical map with the protection requested. 3021 * 3022 * NB: This is the only routine which MAY NOT lazy-evaluate 3023 * or lose information. That is, this routine must actually 3024 * insert this page into the given map NOW. 3025 */ 3026 int 3027 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3028 { 3029 struct l2_bucket *l2b; 3030 struct vm_page *pg, *opg; 3031 u_int nflags; 3032 u_int oflags; 3033 const bool kpm_p = (pm == pmap_kernel()); 3034 #ifdef ARM_HAS_VBAR 3035 const bool vector_page_p = false; 3036 #else 3037 const bool vector_page_p = (va == vector_page); 3038 #endif 3039 3040 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3041 3042 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot #x", 3043 pm, va, pa, prot); 3044 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3045 3046 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3047 KDASSERT(((va | pa) & PGOFSET) == 0); 3048 3049 /* 3050 * Get a pointer to the page. Later on in this function, we 3051 * test for a managed page by checking pg != NULL. 3052 */ 3053 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3054 3055 nflags = 0; 3056 if (prot & VM_PROT_WRITE) 3057 nflags |= PVF_WRITE; 3058 if (prot & VM_PROT_EXECUTE) 3059 nflags |= PVF_EXEC; 3060 if (flags & PMAP_WIRED) 3061 nflags |= PVF_WIRED; 3062 3063 pmap_acquire_pmap_lock(pm); 3064 3065 /* 3066 * Fetch the L2 bucket which maps this page, allocating one if 3067 * necessary for user pmaps. 3068 */ 3069 if (kpm_p) { 3070 l2b = pmap_get_l2_bucket(pm, va); 3071 } else { 3072 l2b = pmap_alloc_l2_bucket(pm, va); 3073 } 3074 if (l2b == NULL) { 3075 if (flags & PMAP_CANFAIL) { 3076 pmap_release_pmap_lock(pm); 3077 return (ENOMEM); 3078 } 3079 panic("pmap_enter: failed to allocate L2 bucket"); 3080 } 3081 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3082 const pt_entry_t opte = *ptep; 3083 pt_entry_t npte = pa; 3084 oflags = 0; 3085 3086 if (opte) { 3087 /* 3088 * There is already a mapping at this address. 3089 * If the physical address is different, lookup the 3090 * vm_page. 3091 */ 3092 if (l2pte_pa(opte) != pa) 3093 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3094 else 3095 opg = pg; 3096 } else 3097 opg = NULL; 3098 3099 if (pg) { 3100 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3101 3102 /* 3103 * This is to be a managed mapping. 3104 */ 3105 pmap_acquire_page_lock(md); 3106 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3107 /* 3108 * - The access type indicates that we don't need 3109 * to do referenced emulation. 3110 * OR 3111 * - The physical page has already been referenced 3112 * so no need to re-do referenced emulation here. 3113 */ 3114 npte |= l2pte_set_readonly(L2_S_PROTO); 3115 3116 nflags |= PVF_REF; 3117 3118 if ((prot & VM_PROT_WRITE) != 0 && 3119 ((flags & VM_PROT_WRITE) != 0 || 3120 (md->pvh_attrs & PVF_MOD) != 0)) { 3121 /* 3122 * This is a writable mapping, and the 3123 * page's mod state indicates it has 3124 * already been modified. Make it 3125 * writable from the outset. 3126 */ 3127 npte = l2pte_set_writable(npte); 3128 nflags |= PVF_MOD; 3129 } 3130 3131 #ifdef ARM_MMU_EXTENDED 3132 /* 3133 * If the page has been cleaned, then the pvh_attrs 3134 * will have PVF_EXEC set, so mark it execute so we 3135 * don't get an access fault when trying to execute 3136 * from it. 3137 */ 3138 if (md->pvh_attrs & nflags & PVF_EXEC) { 3139 npte &= ~L2_XS_XN; 3140 } 3141 #endif 3142 } else { 3143 /* 3144 * Need to do page referenced emulation. 3145 */ 3146 npte |= L2_TYPE_INV; 3147 } 3148 3149 if (flags & ARM32_MMAP_WRITECOMBINE) { 3150 npte |= pte_l2_s_wc_mode; 3151 } else 3152 npte |= pte_l2_s_cache_mode; 3153 3154 if (pg == opg) { 3155 /* 3156 * We're changing the attrs of an existing mapping. 3157 */ 3158 oflags = pmap_modify_pv(md, pa, pm, va, 3159 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3160 PVF_MOD | PVF_REF, nflags); 3161 3162 #ifdef PMAP_CACHE_VIVT 3163 /* 3164 * We may need to flush the cache if we're 3165 * doing rw-ro... 3166 */ 3167 if (pm->pm_cstate.cs_cache_d && 3168 (oflags & PVF_NC) == 0 && 3169 l2pte_writable_p(opte) && 3170 (prot & VM_PROT_WRITE) == 0) 3171 cpu_dcache_wb_range(va, PAGE_SIZE); 3172 #endif 3173 } else { 3174 struct pv_entry *pv; 3175 /* 3176 * New mapping, or changing the backing page 3177 * of an existing mapping. 3178 */ 3179 if (opg) { 3180 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3181 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3182 3183 /* 3184 * Replacing an existing mapping with a new one. 3185 * It is part of our managed memory so we 3186 * must remove it from the PV list 3187 */ 3188 pv = pmap_remove_pv(omd, opa, pm, va); 3189 pmap_vac_me_harder(omd, opa, pm, 0); 3190 oflags = pv->pv_flags; 3191 3192 #ifdef PMAP_CACHE_VIVT 3193 /* 3194 * If the old mapping was valid (ref/mod 3195 * emulation creates 'invalid' mappings 3196 * initially) then make sure to frob 3197 * the cache. 3198 */ 3199 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3200 pmap_cache_wbinv_page(pm, va, true, 3201 oflags); 3202 } 3203 #endif 3204 } else 3205 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 3206 pmap_release_page_lock(md); 3207 if ((flags & PMAP_CANFAIL) == 0) 3208 panic("pmap_enter: no pv entries"); 3209 3210 if (pm != pmap_kernel()) 3211 pmap_free_l2_bucket(pm, l2b, 0); 3212 pmap_release_pmap_lock(pm); 3213 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3214 0, 0, 0, 0); 3215 return (ENOMEM); 3216 } 3217 3218 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3219 } 3220 pmap_release_page_lock(md); 3221 } else { 3222 /* 3223 * We're mapping an unmanaged page. 3224 * These are always readable, and possibly writable, from 3225 * the get go as we don't need to track ref/mod status. 3226 */ 3227 npte |= l2pte_set_readonly(L2_S_PROTO); 3228 if (prot & VM_PROT_WRITE) 3229 npte = l2pte_set_writable(npte); 3230 3231 /* 3232 * Make sure the vector table is mapped cacheable 3233 */ 3234 if ((vector_page_p && !kpm_p) 3235 || (flags & ARM32_MMAP_CACHEABLE)) { 3236 npte |= pte_l2_s_cache_mode; 3237 #ifdef ARM_MMU_EXTENDED 3238 npte &= ~L2_XS_XN; /* and executable */ 3239 #endif 3240 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3241 npte |= pte_l2_s_wc_mode; 3242 } 3243 if (opg) { 3244 /* 3245 * Looks like there's an existing 'managed' mapping 3246 * at this address. 3247 */ 3248 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3249 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3250 3251 pmap_acquire_page_lock(omd); 3252 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3253 pmap_vac_me_harder(omd, opa, pm, 0); 3254 oflags = pv->pv_flags; 3255 pmap_release_page_lock(omd); 3256 3257 #ifdef PMAP_CACHE_VIVT 3258 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3259 pmap_cache_wbinv_page(pm, va, true, oflags); 3260 } 3261 #endif 3262 pool_put(&pmap_pv_pool, pv); 3263 } 3264 } 3265 3266 /* 3267 * Make sure userland mappings get the right permissions 3268 */ 3269 if (!vector_page_p && !kpm_p) { 3270 npte |= L2_S_PROT_U; 3271 #ifdef ARM_MMU_EXTENDED 3272 npte |= L2_XS_nG; /* user pages are not global */ 3273 #endif 3274 } 3275 3276 /* 3277 * Keep the stats up to date 3278 */ 3279 if (opte == 0) { 3280 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3281 pm->pm_stats.resident_count++; 3282 } 3283 3284 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3285 3286 /* 3287 * If this is just a wiring change, the two PTEs will be 3288 * identical, so there's no need to update the page table. 3289 */ 3290 if (npte != opte) { 3291 3292 l2pte_set(ptep, npte, opte); 3293 PTE_SYNC(ptep); 3294 #ifndef ARM_MMU_EXTENDED 3295 bool is_cached = pmap_is_cached(pm); 3296 if (is_cached) { 3297 /* 3298 * We only need to frob the cache/tlb if this pmap 3299 * is current 3300 */ 3301 if (!vector_page_p && l2pte_valid_p(npte)) { 3302 /* 3303 * This mapping is likely to be accessed as 3304 * soon as we return to userland. Fix up the 3305 * L1 entry to avoid taking another 3306 * page/domain fault. 3307 */ 3308 pd_entry_t *pdep = pmap_l1_kva(pm) 3309 + l1pte_index(va); 3310 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3311 | L1_C_DOM(pmap_domain(pm)); 3312 if (*pdep != pde) { 3313 l1pte_setone(pdep, pde); 3314 PTE_SYNC(pdep); 3315 } 3316 } 3317 } 3318 #endif /* !ARMM_MMU_EXTENDED */ 3319 3320 pmap_tlb_flush_SE(pm, va, oflags); 3321 3322 #ifndef ARM_MMU_EXTENDED 3323 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3324 is_cached, pm->pm_cstate.cs_all, 0, 0); 3325 #endif 3326 3327 if (pg != NULL) { 3328 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3329 3330 pmap_acquire_page_lock(md); 3331 pmap_vac_me_harder(md, pa, pm, va); 3332 pmap_release_page_lock(md); 3333 } 3334 } 3335 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3336 if (pg) { 3337 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3338 3339 pmap_acquire_page_lock(md); 3340 #ifndef ARM_MMU_EXTENDED 3341 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3342 #endif 3343 PMAP_VALIDATE_MD_PAGE(md); 3344 pmap_release_page_lock(md); 3345 } 3346 #endif 3347 3348 pmap_release_pmap_lock(pm); 3349 3350 return (0); 3351 } 3352 3353 /* 3354 * pmap_remove() 3355 * 3356 * pmap_remove is responsible for nuking a number of mappings for a range 3357 * of virtual address space in the current pmap. To do this efficiently 3358 * is interesting, because in a number of cases a wide virtual address 3359 * range may be supplied that contains few actual mappings. So, the 3360 * optimisations are: 3361 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3362 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3363 * maybe do just a partial cache clean. This path of execution is 3364 * complicated by the fact that the cache must be flushed _before_ 3365 * the PTE is nuked, being a VAC :-) 3366 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3367 * all invalidations until pmap_update(), since pmap_remove_all() has 3368 * already flushed the cache. 3369 * 4. Maybe later fast-case a single page, but I don't think this is 3370 * going to make _that_ much difference overall. 3371 */ 3372 3373 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3374 3375 void 3376 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3377 { 3378 vaddr_t next_bucket; 3379 u_int cleanlist_idx, total, cnt; 3380 struct { 3381 vaddr_t va; 3382 pt_entry_t *ptep; 3383 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3384 u_int mappings; 3385 3386 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3387 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3388 3389 /* 3390 * we lock in the pmap => pv_head direction 3391 */ 3392 pmap_acquire_pmap_lock(pm); 3393 3394 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3395 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3396 #ifndef ARM_MMU_EXTENDED 3397 if (pm->pm_cstate.cs_tlb == 0) 3398 pm->pm_remove_all = true; 3399 #endif 3400 } else 3401 cleanlist_idx = 0; 3402 3403 total = 0; 3404 3405 while (sva < eva) { 3406 /* 3407 * Do one L2 bucket's worth at a time. 3408 */ 3409 next_bucket = L2_NEXT_BUCKET_VA(sva); 3410 if (next_bucket > eva) 3411 next_bucket = eva; 3412 3413 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3414 if (l2b == NULL) { 3415 sva = next_bucket; 3416 continue; 3417 } 3418 3419 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3420 3421 for (mappings = 0; 3422 sva < next_bucket; 3423 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3424 pt_entry_t opte = *ptep; 3425 3426 if (opte == 0) { 3427 /* Nothing here, move along */ 3428 continue; 3429 } 3430 3431 u_int flags = PVF_REF; 3432 paddr_t pa = l2pte_pa(opte); 3433 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3434 3435 /* 3436 * Update flags. In a number of circumstances, 3437 * we could cluster a lot of these and do a 3438 * number of sequential pages in one go. 3439 */ 3440 if (pg != NULL) { 3441 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3442 struct pv_entry *pv; 3443 3444 pmap_acquire_page_lock(md); 3445 pv = pmap_remove_pv(md, pa, pm, sva); 3446 pmap_vac_me_harder(md, pa, pm, 0); 3447 pmap_release_page_lock(md); 3448 if (pv != NULL) { 3449 if (pm->pm_remove_all == false) { 3450 flags = pv->pv_flags; 3451 } 3452 pool_put(&pmap_pv_pool, pv); 3453 } 3454 } 3455 mappings += PAGE_SIZE / L2_S_SIZE; 3456 3457 if (!l2pte_valid_p(opte)) { 3458 /* 3459 * Ref/Mod emulation is still active for this 3460 * mapping, therefore it is has not yet been 3461 * accessed. No need to frob the cache/tlb. 3462 */ 3463 l2pte_reset(ptep); 3464 PTE_SYNC_CURRENT(pm, ptep); 3465 continue; 3466 } 3467 3468 #ifdef ARM_MMU_EXTENDED 3469 if (pm == pmap_kernel()) { 3470 l2pte_reset(ptep); 3471 PTE_SYNC(ptep); 3472 pmap_tlb_flush_SE(pm, sva, flags); 3473 continue; 3474 } 3475 #endif 3476 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3477 /* Add to the clean list. */ 3478 cleanlist[cleanlist_idx].ptep = ptep; 3479 cleanlist[cleanlist_idx].va = 3480 sva | (flags & PVF_EXEC); 3481 cleanlist_idx++; 3482 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3483 /* Nuke everything if needed. */ 3484 #ifdef PMAP_CACHE_VIVT 3485 pmap_cache_wbinv_all(pm, PVF_EXEC); 3486 #endif 3487 /* 3488 * Roll back the previous PTE list, 3489 * and zero out the current PTE. 3490 */ 3491 for (cnt = 0; 3492 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3493 l2pte_reset(cleanlist[cnt].ptep); 3494 PTE_SYNC(cleanlist[cnt].ptep); 3495 } 3496 l2pte_reset(ptep); 3497 PTE_SYNC(ptep); 3498 cleanlist_idx++; 3499 pm->pm_remove_all = true; 3500 } else { 3501 l2pte_reset(ptep); 3502 PTE_SYNC(ptep); 3503 if (pm->pm_remove_all == false) { 3504 pmap_tlb_flush_SE(pm, sva, flags); 3505 } 3506 } 3507 } 3508 3509 /* 3510 * Deal with any left overs 3511 */ 3512 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3513 total += cleanlist_idx; 3514 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3515 #ifdef ARM_MMU_EXTENDED 3516 vaddr_t clva = cleanlist[cnt].va; 3517 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3518 #else 3519 vaddr_t va = cleanlist[cnt].va; 3520 if (pm->pm_cstate.cs_all != 0) { 3521 vaddr_t clva = va & ~PAGE_MASK; 3522 u_int flags = va & PVF_EXEC; 3523 #ifdef PMAP_CACHE_VIVT 3524 pmap_cache_wbinv_page(pm, clva, true, 3525 PVF_REF | PVF_WRITE | flags); 3526 #endif 3527 pmap_tlb_flush_SE(pm, clva, 3528 PVF_REF | flags); 3529 } 3530 #endif /* ARM_MMU_EXTENDED */ 3531 l2pte_reset(cleanlist[cnt].ptep); 3532 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3533 } 3534 3535 /* 3536 * If it looks like we're removing a whole bunch 3537 * of mappings, it's faster to just write-back 3538 * the whole cache now and defer TLB flushes until 3539 * pmap_update() is called. 3540 */ 3541 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3542 cleanlist_idx = 0; 3543 else { 3544 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3545 #ifdef PMAP_CACHE_VIVT 3546 pmap_cache_wbinv_all(pm, PVF_EXEC); 3547 #endif 3548 pm->pm_remove_all = true; 3549 } 3550 } 3551 3552 pmap_free_l2_bucket(pm, l2b, mappings); 3553 pm->pm_stats.resident_count -= mappings; 3554 } 3555 3556 pmap_release_pmap_lock(pm); 3557 } 3558 3559 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3560 static struct pv_entry * 3561 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3562 { 3563 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3564 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3565 struct pv_entry *pv; 3566 3567 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3568 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3569 KASSERT(pmap_page_locked_p(md)); 3570 3571 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3572 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3573 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3574 3575 /* 3576 * If we are removing a writeable mapping to a cached exec page, 3577 * if it's the last mapping then clear it execness other sync 3578 * the page to the icache. 3579 */ 3580 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3581 && (pv->pv_flags & PVF_WRITE) != 0) { 3582 if (SLIST_EMPTY(&md->pvh_list)) { 3583 md->pvh_attrs &= ~PVF_EXEC; 3584 PMAPCOUNT(exec_discarded_kremove); 3585 } else { 3586 pmap_syncicache_page(md, pa); 3587 PMAPCOUNT(exec_synced_kremove); 3588 } 3589 } 3590 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3591 3592 return pv; 3593 } 3594 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3595 3596 /* 3597 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3598 * 3599 * We assume there is already sufficient KVM space available 3600 * to do this, as we can't allocate L2 descriptor tables/metadata 3601 * from here. 3602 */ 3603 void 3604 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3605 { 3606 #ifdef PMAP_CACHE_VIVT 3607 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3608 #endif 3609 #ifdef PMAP_CACHE_VIPT 3610 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3611 struct vm_page *opg; 3612 #ifndef ARM_MMU_EXTENDED 3613 struct pv_entry *pv = NULL; 3614 #endif 3615 #endif 3616 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3617 3618 UVMHIST_FUNC(__func__); 3619 3620 if (pmap_initialized) { 3621 UVMHIST_CALLED(maphist); 3622 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3623 va, pa, prot, flags); 3624 } 3625 3626 pmap_t kpm = pmap_kernel(); 3627 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3628 const size_t l1slot __diagused = l1pte_index(va); 3629 KASSERTMSG(l2b != NULL, 3630 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3631 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3632 kpm->pm_l2[L2_IDX(l1slot)] 3633 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3634 : NULL, 3635 kpm->pm_l2[L2_IDX(l1slot)] 3636 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3637 : NULL); 3638 KASSERT(l2b->l2b_kva != NULL); 3639 3640 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3641 const pt_entry_t opte = *ptep; 3642 3643 if (opte == 0) { 3644 PMAPCOUNT(kenter_mappings); 3645 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3646 } else { 3647 PMAPCOUNT(kenter_remappings); 3648 #ifdef PMAP_CACHE_VIPT 3649 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3650 #ifdef DIAGNOSTIC 3651 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3652 #endif 3653 if (opg && arm_cache_prefer_mask != 0) { 3654 KASSERT(opg != pg); 3655 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3656 KASSERT((flags & PMAP_KMPAGE) == 0); 3657 #ifndef ARM_MMU_EXTENDED 3658 pmap_acquire_page_lock(md); 3659 pv = pmap_kremove_pg(opg, va); 3660 pmap_release_page_lock(md); 3661 #endif 3662 } 3663 #endif 3664 if (l2pte_valid_p(opte)) { 3665 #ifdef PMAP_CACHE_VIVT 3666 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3667 #endif 3668 cpu_tlb_flushD_SE(va); 3669 cpu_cpwait(); 3670 } 3671 } 3672 3673 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3674 | ((flags & PMAP_NOCACHE) 3675 ? 0 3676 : ((flags & PMAP_PTE) 3677 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3678 #ifdef ARM_MMU_EXTENDED 3679 if (prot & VM_PROT_EXECUTE) 3680 npte &= ~L2_XS_XN; 3681 #endif 3682 l2pte_set(ptep, npte, opte); 3683 PTE_SYNC(ptep); 3684 3685 if (pg) { 3686 if (flags & PMAP_KMPAGE) { 3687 KASSERT(md->urw_mappings == 0); 3688 KASSERT(md->uro_mappings == 0); 3689 KASSERT(md->krw_mappings == 0); 3690 KASSERT(md->kro_mappings == 0); 3691 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3692 KASSERT(pv == NULL); 3693 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3694 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3695 /* if there is a color conflict, evict from cache. */ 3696 if (pmap_is_page_colored_p(md) 3697 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3698 PMAPCOUNT(vac_color_change); 3699 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3700 } else if (md->pvh_attrs & PVF_MULTCLR) { 3701 /* 3702 * If this page has multiple colors, expunge 3703 * them. 3704 */ 3705 PMAPCOUNT(vac_flush_lots2); 3706 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3707 } 3708 pmap_acquire_page_lock(md); 3709 md->pvh_attrs &= PAGE_SIZE - 1; 3710 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3711 | (va & arm_cache_prefer_mask); 3712 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3713 pmap_acquire_page_lock(md); 3714 md->pvh_attrs |= PVF_KMPAGE; 3715 #endif 3716 pmap_kmpages++; 3717 pmap_release_page_lock(md); 3718 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3719 } else if (arm_cache_prefer_mask != 0) { 3720 if (pv == NULL) { 3721 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3722 KASSERT(pv != NULL); 3723 } 3724 pmap_acquire_page_lock(md); 3725 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3726 PVF_WIRED | PVF_KENTRY 3727 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3728 if ((prot & VM_PROT_WRITE) 3729 && !(md->pvh_attrs & PVF_NC)) 3730 md->pvh_attrs |= PVF_DIRTY; 3731 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3732 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3733 pmap_release_page_lock(md); 3734 #endif 3735 } 3736 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3737 } else { 3738 if (pv != NULL) 3739 pool_put(&pmap_pv_pool, pv); 3740 #endif 3741 } 3742 3743 if (pmap_initialized) { 3744 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3745 ptep, opte, npte, 0); 3746 } 3747 } 3748 3749 void 3750 pmap_kremove(vaddr_t va, vsize_t len) 3751 { 3752 #ifdef UVMHIST 3753 u_int total_mappings = 0; 3754 #endif 3755 3756 PMAPCOUNT(kenter_unmappings); 3757 3758 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3759 3760 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3761 3762 const vaddr_t eva = va + len; 3763 3764 while (va < eva) { 3765 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3766 if (next_bucket > eva) 3767 next_bucket = eva; 3768 3769 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3770 KDASSERT(l2b != NULL); 3771 3772 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3773 pt_entry_t *ptep = sptep; 3774 u_int mappings = 0; 3775 3776 while (va < next_bucket) { 3777 const pt_entry_t opte = *ptep; 3778 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3779 if (opg != NULL) { 3780 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3781 3782 pmap_acquire_page_lock(omd); 3783 if (omd->pvh_attrs & PVF_KMPAGE) { 3784 KASSERT(omd->urw_mappings == 0); 3785 KASSERT(omd->uro_mappings == 0); 3786 KASSERT(omd->krw_mappings == 0); 3787 KASSERT(omd->kro_mappings == 0); 3788 omd->pvh_attrs &= ~PVF_KMPAGE; 3789 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3790 if (arm_cache_prefer_mask != 0) { 3791 omd->pvh_attrs &= ~PVF_WRITE; 3792 } 3793 #endif 3794 pmap_kmpages--; 3795 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3796 } else if (arm_cache_prefer_mask != 0) { 3797 pool_put(&pmap_pv_pool, 3798 pmap_kremove_pg(opg, va)); 3799 #endif 3800 } 3801 pmap_release_page_lock(omd); 3802 } 3803 if (l2pte_valid_p(opte)) { 3804 #ifdef PMAP_CACHE_VIVT 3805 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3806 #endif 3807 cpu_tlb_flushD_SE(va); 3808 } 3809 if (opte) { 3810 l2pte_reset(ptep); 3811 mappings += PAGE_SIZE / L2_S_SIZE; 3812 } 3813 va += PAGE_SIZE; 3814 ptep += PAGE_SIZE / L2_S_SIZE; 3815 } 3816 KDASSERT(mappings <= l2b->l2b_occupancy); 3817 l2b->l2b_occupancy -= mappings; 3818 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3819 #ifdef UVMHIST 3820 total_mappings += mappings; 3821 #endif 3822 } 3823 cpu_cpwait(); 3824 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3825 total_mappings, 0, 0, 0); 3826 } 3827 3828 bool 3829 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3830 { 3831 struct l2_dtable *l2; 3832 pd_entry_t *pdep, pde; 3833 pt_entry_t *ptep, pte; 3834 paddr_t pa; 3835 u_int l1slot; 3836 3837 pmap_acquire_pmap_lock(pm); 3838 3839 l1slot = l1pte_index(va); 3840 pdep = pmap_l1_kva(pm) + l1slot; 3841 pde = *pdep; 3842 3843 if (l1pte_section_p(pde)) { 3844 /* 3845 * These should only happen for pmap_kernel() 3846 */ 3847 KDASSERT(pm == pmap_kernel()); 3848 pmap_release_pmap_lock(pm); 3849 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3850 if (l1pte_supersection_p(pde)) { 3851 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3852 } else 3853 #endif 3854 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3855 } else { 3856 /* 3857 * Note that we can't rely on the validity of the L1 3858 * descriptor as an indication that a mapping exists. 3859 * We have to look it up in the L2 dtable. 3860 */ 3861 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3862 3863 if (l2 == NULL || 3864 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3865 pmap_release_pmap_lock(pm); 3866 return false; 3867 } 3868 3869 ptep = &ptep[l2pte_index(va)]; 3870 pte = *ptep; 3871 pmap_release_pmap_lock(pm); 3872 3873 if (pte == 0) 3874 return false; 3875 3876 switch (pte & L2_TYPE_MASK) { 3877 case L2_TYPE_L: 3878 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3879 break; 3880 3881 default: 3882 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3883 break; 3884 } 3885 } 3886 3887 if (pap != NULL) 3888 *pap = pa; 3889 3890 return true; 3891 } 3892 3893 void 3894 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3895 { 3896 struct l2_bucket *l2b; 3897 vaddr_t next_bucket; 3898 3899 NPDEBUG(PDB_PROTECT, 3900 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3901 pm, sva, eva, prot)); 3902 3903 if ((prot & VM_PROT_READ) == 0) { 3904 pmap_remove(pm, sva, eva); 3905 return; 3906 } 3907 3908 if (prot & VM_PROT_WRITE) { 3909 /* 3910 * If this is a read->write transition, just ignore it and let 3911 * uvm_fault() take care of it later. 3912 */ 3913 return; 3914 } 3915 3916 pmap_acquire_pmap_lock(pm); 3917 3918 const bool flush = eva - sva >= PAGE_SIZE * 4; 3919 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3920 u_int flags = 0; 3921 3922 while (sva < eva) { 3923 next_bucket = L2_NEXT_BUCKET_VA(sva); 3924 if (next_bucket > eva) 3925 next_bucket = eva; 3926 3927 l2b = pmap_get_l2_bucket(pm, sva); 3928 if (l2b == NULL) { 3929 sva = next_bucket; 3930 continue; 3931 } 3932 3933 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3934 3935 while (sva < next_bucket) { 3936 const pt_entry_t opte = *ptep; 3937 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3938 struct vm_page *pg; 3939 u_int f; 3940 3941 #ifdef PMAP_CACHE_VIVT 3942 /* 3943 * OK, at this point, we know we're doing 3944 * write-protect operation. If the pmap is 3945 * active, write-back the page. 3946 */ 3947 pmap_cache_wbinv_page(pm, sva, false, 3948 PVF_REF | PVF_WRITE); 3949 #endif 3950 3951 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3952 pt_entry_t npte = l2pte_set_readonly(opte); 3953 l2pte_set(ptep, npte, opte); 3954 PTE_SYNC(ptep); 3955 3956 if (pg != NULL) { 3957 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3958 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3959 3960 pmap_acquire_page_lock(md); 3961 f = pmap_modify_pv(md, pa, pm, sva, 3962 clr_mask, 0); 3963 pmap_vac_me_harder(md, pa, pm, sva); 3964 pmap_release_page_lock(md); 3965 } else { 3966 f = PVF_REF | PVF_EXEC; 3967 } 3968 3969 if (flush) { 3970 flags |= f; 3971 } else { 3972 pmap_tlb_flush_SE(pm, sva, f); 3973 } 3974 } 3975 3976 sva += PAGE_SIZE; 3977 ptep += PAGE_SIZE / L2_S_SIZE; 3978 } 3979 } 3980 3981 if (flush) { 3982 if (PV_BEEN_EXECD(flags)) { 3983 pmap_tlb_flushID(pm); 3984 } else if (PV_BEEN_REFD(flags)) { 3985 pmap_tlb_flushD(pm); 3986 } 3987 } 3988 3989 pmap_release_pmap_lock(pm); 3990 } 3991 3992 void 3993 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3994 { 3995 struct l2_bucket *l2b; 3996 pt_entry_t *ptep; 3997 vaddr_t next_bucket; 3998 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3999 4000 NPDEBUG(PDB_EXEC, 4001 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4002 pm, sva, eva)); 4003 4004 pmap_acquire_pmap_lock(pm); 4005 4006 while (sva < eva) { 4007 next_bucket = L2_NEXT_BUCKET_VA(sva); 4008 if (next_bucket > eva) 4009 next_bucket = eva; 4010 4011 l2b = pmap_get_l2_bucket(pm, sva); 4012 if (l2b == NULL) { 4013 sva = next_bucket; 4014 continue; 4015 } 4016 4017 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4018 sva < next_bucket; 4019 sva += page_size, 4020 ptep += PAGE_SIZE / L2_S_SIZE, 4021 page_size = PAGE_SIZE) { 4022 if (l2pte_valid_p(*ptep)) { 4023 cpu_icache_sync_range(sva, 4024 min(page_size, eva - sva)); 4025 } 4026 } 4027 } 4028 4029 pmap_release_pmap_lock(pm); 4030 } 4031 4032 void 4033 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4034 { 4035 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4036 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4037 4038 NPDEBUG(PDB_PROTECT, 4039 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4040 md, pa, prot)); 4041 4042 switch(prot) { 4043 case VM_PROT_READ|VM_PROT_WRITE: 4044 #if defined(ARM_MMU_EXTENDED) 4045 pmap_acquire_page_lock(md); 4046 pmap_clearbit(md, pa, PVF_EXEC); 4047 pmap_release_page_lock(md); 4048 break; 4049 #endif 4050 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4051 break; 4052 4053 case VM_PROT_READ: 4054 #if defined(ARM_MMU_EXTENDED) 4055 pmap_acquire_page_lock(md); 4056 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4057 pmap_release_page_lock(md); 4058 break; 4059 #endif 4060 case VM_PROT_READ|VM_PROT_EXECUTE: 4061 pmap_acquire_page_lock(md); 4062 pmap_clearbit(md, pa, PVF_WRITE); 4063 pmap_release_page_lock(md); 4064 break; 4065 4066 default: 4067 pmap_page_remove(md, pa); 4068 break; 4069 } 4070 } 4071 4072 /* 4073 * pmap_clear_modify: 4074 * 4075 * Clear the "modified" attribute for a page. 4076 */ 4077 bool 4078 pmap_clear_modify(struct vm_page *pg) 4079 { 4080 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4081 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4082 bool rv; 4083 4084 pmap_acquire_page_lock(md); 4085 4086 if (md->pvh_attrs & PVF_MOD) { 4087 rv = true; 4088 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4089 /* 4090 * If we are going to clear the modified bit and there are 4091 * no other modified bits set, flush the page to memory and 4092 * mark it clean. 4093 */ 4094 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4095 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4096 #endif 4097 pmap_clearbit(md, pa, PVF_MOD); 4098 } else { 4099 rv = false; 4100 } 4101 pmap_release_page_lock(md); 4102 4103 return rv; 4104 } 4105 4106 /* 4107 * pmap_clear_reference: 4108 * 4109 * Clear the "referenced" attribute for a page. 4110 */ 4111 bool 4112 pmap_clear_reference(struct vm_page *pg) 4113 { 4114 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4115 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4116 bool rv; 4117 4118 pmap_acquire_page_lock(md); 4119 4120 if (md->pvh_attrs & PVF_REF) { 4121 rv = true; 4122 pmap_clearbit(md, pa, PVF_REF); 4123 } else { 4124 rv = false; 4125 } 4126 pmap_release_page_lock(md); 4127 4128 return rv; 4129 } 4130 4131 /* 4132 * pmap_is_modified: 4133 * 4134 * Test if a page has the "modified" attribute. 4135 */ 4136 /* See <arm/arm32/pmap.h> */ 4137 4138 /* 4139 * pmap_is_referenced: 4140 * 4141 * Test if a page has the "referenced" attribute. 4142 */ 4143 /* See <arm/arm32/pmap.h> */ 4144 4145 #if defined(ARM_MMU_EXTENDED) && 0 4146 int 4147 pmap_prefetchabt_fixup(void *v) 4148 { 4149 struct trapframe * const tf = v; 4150 vaddr_t va = trunc_page(tf->tf_pc); 4151 int rv = ABORT_FIXUP_FAILED; 4152 4153 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4154 return rv; 4155 4156 kpreempt_disable(); 4157 pmap_t pm = curcpu()->ci_pmap_cur; 4158 const size_t l1slot = l1pte_index(va); 4159 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4160 if (l2 == NULL) 4161 goto out; 4162 4163 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4164 if (l2b->l2b_kva == NULL) 4165 goto out; 4166 4167 /* 4168 * Check the PTE itself. 4169 */ 4170 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4171 const pt_entry_t opte = *ptep; 4172 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4173 goto out; 4174 4175 paddr_t pa = l2pte_pa(pte); 4176 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4177 KASSERT(pg != NULL); 4178 4179 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4180 4181 pmap_acquire_page_lock(md); 4182 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4183 KASSERT(pv != NULL); 4184 4185 if (PV_IS_EXEC_P(pv->pv_flags)) { 4186 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4187 pmap_syncicache_page(md, pa); 4188 } 4189 rv = ABORT_FIXUP_RETURN; 4190 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4191 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4192 } 4193 pmap_release_page_lock(md); 4194 4195 out: 4196 kpreempt_enable(); 4197 return rv; 4198 } 4199 #endif 4200 4201 int 4202 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4203 { 4204 struct l2_dtable *l2; 4205 struct l2_bucket *l2b; 4206 paddr_t pa; 4207 const size_t l1slot = l1pte_index(va); 4208 int rv = 0; 4209 4210 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4211 4212 va = trunc_page(va); 4213 4214 KASSERT(!user || (pm != pmap_kernel())); 4215 4216 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4217 pm, va, ftype, user); 4218 #ifdef ARM_MMU_EXTENDED 4219 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4220 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4221 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4222 #endif 4223 4224 pmap_acquire_pmap_lock(pm); 4225 4226 /* 4227 * If there is no l2_dtable for this address, then the process 4228 * has no business accessing it. 4229 * 4230 * Note: This will catch userland processes trying to access 4231 * kernel addresses. 4232 */ 4233 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4234 if (l2 == NULL) { 4235 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4236 goto out; 4237 } 4238 4239 /* 4240 * Likewise if there is no L2 descriptor table 4241 */ 4242 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4243 if (l2b->l2b_kva == NULL) { 4244 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4245 goto out; 4246 } 4247 4248 /* 4249 * Check the PTE itself. 4250 */ 4251 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4252 pt_entry_t const opte = *ptep; 4253 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4254 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4255 goto out; 4256 } 4257 4258 #ifndef ARM_HAS_VBAR 4259 /* 4260 * Catch a userland access to the vector page mapped at 0x0 4261 */ 4262 if (user && (opte & L2_S_PROT_U) == 0) { 4263 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4264 goto out; 4265 } 4266 #endif 4267 4268 pa = l2pte_pa(opte); 4269 4270 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4271 /* 4272 * This looks like a good candidate for "page modified" 4273 * emulation... 4274 */ 4275 struct pv_entry *pv; 4276 struct vm_page *pg; 4277 4278 /* Extract the physical address of the page */ 4279 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4280 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4281 goto out; 4282 } 4283 4284 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4285 4286 /* Get the current flags for this page. */ 4287 pmap_acquire_page_lock(md); 4288 pv = pmap_find_pv(md, pm, va); 4289 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4290 pmap_release_page_lock(md); 4291 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4292 goto out; 4293 } 4294 4295 /* 4296 * Do the flags say this page is writable? If not then it 4297 * is a genuine write fault. If yes then the write fault is 4298 * our fault as we did not reflect the write access in the 4299 * PTE. Now we know a write has occurred we can correct this 4300 * and also set the modified bit 4301 */ 4302 if ((pv->pv_flags & PVF_WRITE) == 0) { 4303 pmap_release_page_lock(md); 4304 goto out; 4305 } 4306 4307 md->pvh_attrs |= PVF_REF | PVF_MOD; 4308 pv->pv_flags |= PVF_REF | PVF_MOD; 4309 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4310 /* 4311 * If there are cacheable mappings for this page, mark it dirty. 4312 */ 4313 if ((md->pvh_attrs & PVF_NC) == 0) 4314 md->pvh_attrs |= PVF_DIRTY; 4315 #endif 4316 #ifdef ARM_MMU_EXTENDED 4317 if (md->pvh_attrs & PVF_EXEC) { 4318 md->pvh_attrs &= ~PVF_EXEC; 4319 PMAPCOUNT(exec_discarded_modfixup); 4320 } 4321 #endif 4322 pmap_release_page_lock(md); 4323 4324 /* 4325 * Re-enable write permissions for the page. No need to call 4326 * pmap_vac_me_harder(), since this is just a 4327 * modified-emulation fault, and the PVF_WRITE bit isn't 4328 * changing. We've already set the cacheable bits based on 4329 * the assumption that we can write to this page. 4330 */ 4331 const pt_entry_t npte = 4332 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4333 #ifdef ARM_MMU_EXTENDED 4334 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4335 #endif 4336 | 0; 4337 l2pte_set(ptep, npte, opte); 4338 PTE_SYNC(ptep); 4339 PMAPCOUNT(fixup_mod); 4340 rv = 1; 4341 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4342 opte, npte, 0, 0); 4343 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4344 /* 4345 * This looks like a good candidate for "page referenced" 4346 * emulation. 4347 */ 4348 struct vm_page *pg; 4349 4350 /* Extract the physical address of the page */ 4351 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4352 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4353 goto out; 4354 } 4355 4356 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4357 4358 /* Get the current flags for this page. */ 4359 pmap_acquire_page_lock(md); 4360 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4361 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4362 pmap_release_page_lock(md); 4363 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4364 goto out; 4365 } 4366 4367 md->pvh_attrs |= PVF_REF; 4368 pv->pv_flags |= PVF_REF; 4369 4370 pt_entry_t npte = 4371 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4372 #ifdef ARM_MMU_EXTENDED 4373 if (pm != pmap_kernel()) { 4374 npte |= L2_XS_nG; 4375 } 4376 /* 4377 * If we got called from prefetch abort, then ftype will have 4378 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4379 * the PTE. 4380 */ 4381 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4382 /* 4383 * Is this a mapping of an executable page? 4384 */ 4385 if ((pv->pv_flags & PVF_EXEC) == 0) { 4386 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4387 0, 0, 0, 0); 4388 goto out; 4389 } 4390 /* 4391 * If we haven't synced the page, do so now. 4392 */ 4393 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4394 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4395 pa, 0, 0, 0); 4396 pmap_syncicache_page(md, pa); 4397 PMAPCOUNT(fixup_exec); 4398 } 4399 npte &= ~L2_XS_XN; 4400 } 4401 #endif /* ARM_MMU_EXTENDED */ 4402 pmap_release_page_lock(md); 4403 l2pte_set(ptep, npte, opte); 4404 PTE_SYNC(ptep); 4405 PMAPCOUNT(fixup_ref); 4406 rv = 1; 4407 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4408 opte, npte, 0, 0); 4409 #ifdef ARM_MMU_EXTENDED 4410 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4411 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4412 if (pg == NULL) { 4413 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4414 goto out; 4415 } 4416 4417 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4418 4419 /* Get the current flags for this page. */ 4420 pmap_acquire_page_lock(md); 4421 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4422 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4423 pmap_release_page_lock(md); 4424 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4425 goto out; 4426 } 4427 4428 /* 4429 * If we haven't synced the page, do so now. 4430 */ 4431 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4432 UVMHIST_LOG(maphist, "syncicache page #%#x", 4433 pa, 0, 0, 0); 4434 pmap_syncicache_page(md, pa); 4435 } 4436 pmap_release_page_lock(md); 4437 /* 4438 * Turn off no-execute. 4439 */ 4440 KASSERT(opte & L2_XS_nG); 4441 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4442 PTE_SYNC(ptep); 4443 rv = 1; 4444 PMAPCOUNT(fixup_exec); 4445 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4446 opte, opte & ~L2_XS_XN, 0, 0); 4447 #endif 4448 } 4449 4450 #ifndef ARM_MMU_EXTENDED 4451 /* 4452 * We know there is a valid mapping here, so simply 4453 * fix up the L1 if necessary. 4454 */ 4455 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4456 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4457 if (*pdep != pde) { 4458 l1pte_setone(pdep, pde); 4459 PTE_SYNC(pdep); 4460 rv = 1; 4461 PMAPCOUNT(fixup_pdes); 4462 } 4463 #endif 4464 4465 #ifdef CPU_SA110 4466 /* 4467 * There are bugs in the rev K SA110. This is a check for one 4468 * of them. 4469 */ 4470 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4471 curcpu()->ci_arm_cpurev < 3) { 4472 /* Always current pmap */ 4473 if (l2pte_valid_p(opte)) { 4474 extern int kernel_debug; 4475 if (kernel_debug & 1) { 4476 struct proc *p = curlwp->l_proc; 4477 printf("prefetch_abort: page is already " 4478 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4479 printf("prefetch_abort: pc=%08lx proc=%p " 4480 "process=%s\n", va, p, p->p_comm); 4481 printf("prefetch_abort: far=%08x fs=%x\n", 4482 cpu_faultaddress(), cpu_faultstatus()); 4483 } 4484 #ifdef DDB 4485 if (kernel_debug & 2) 4486 Debugger(); 4487 #endif 4488 rv = 1; 4489 } 4490 } 4491 #endif /* CPU_SA110 */ 4492 4493 #ifndef ARM_MMU_EXTENDED 4494 /* 4495 * If 'rv == 0' at this point, it generally indicates that there is a 4496 * stale TLB entry for the faulting address. That might be due to a 4497 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4498 */ 4499 if (rv == 0 4500 && pm->pm_l1->l1_domain_use_count == 1 4501 && pmap_needs_pte_sync == 0) { 4502 pmap_needs_pte_sync = 1; 4503 PTE_SYNC(ptep); 4504 PMAPCOUNT(fixup_ptesync); 4505 rv = 1; 4506 } 4507 #endif 4508 4509 #if defined(DEBUG) || 1 4510 /* 4511 * If 'rv == 0' at this point, it generally indicates that there is a 4512 * stale TLB entry for the faulting address. This happens when two or 4513 * more processes are sharing an L1. Since we don't flush the TLB on 4514 * a context switch between such processes, we can take domain faults 4515 * for mappings which exist at the same VA in both processes. EVEN IF 4516 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4517 * example. 4518 * 4519 * This is extremely likely to happen if pmap_enter() updated the L1 4520 * entry for a recently entered mapping. In this case, the TLB is 4521 * flushed for the new mapping, but there may still be TLB entries for 4522 * other mappings belonging to other processes in the 1MB range 4523 * covered by the L1 entry. 4524 * 4525 * Since 'rv == 0', we know that the L1 already contains the correct 4526 * value, so the fault must be due to a stale TLB entry. 4527 * 4528 * Since we always need to flush the TLB anyway in the case where we 4529 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4530 * stale TLB entries dynamically. 4531 * 4532 * However, the above condition can ONLY happen if the current L1 is 4533 * being shared. If it happens when the L1 is unshared, it indicates 4534 * that other parts of the pmap are not doing their job WRT managing 4535 * the TLB. 4536 */ 4537 if (rv == 0 4538 #ifndef ARM_MMU_EXTENDED 4539 && pm->pm_l1->l1_domain_use_count == 1 4540 #endif 4541 && true) { 4542 #ifdef DEBUG 4543 extern int last_fault_code; 4544 #else 4545 int last_fault_code = ftype & VM_PROT_EXECUTE 4546 ? armreg_ifsr_read() 4547 : armreg_dfsr_read(); 4548 #endif 4549 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4550 pm, va, ftype); 4551 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4552 l2, l2b, ptep, opte); 4553 4554 #ifndef ARM_MMU_EXTENDED 4555 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4556 pdep, pde, last_fault_code); 4557 #else 4558 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4559 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4560 armreg_ttbcr_read()); 4561 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4562 last_fault_code, curcpu()->ci_pmap_cur, 4563 curcpu()->ci_pmap_asid_cur, 4564 armreg_contextidr_read(), armreg_dacr_read()); 4565 #ifdef _ARM_ARCH_7 4566 if (ftype & VM_PROT_WRITE) 4567 armreg_ats1cuw_write(va); 4568 else 4569 armreg_ats1cur_write(va); 4570 arm_isb(); 4571 printf("fixup: par %#x\n", armreg_par_read()); 4572 #endif 4573 #endif 4574 #ifdef DDB 4575 //extern int kernel_debug; 4576 4577 //if (kernel_debug & 2) 4578 pmap_release_pmap_lock(pm); 4579 KERNHIST_DUMP(maphist); 4580 cpu_Debugger(); 4581 pmap_acquire_pmap_lock(pm); 4582 #endif 4583 } 4584 #endif 4585 4586 pmap_tlb_flush_SE(pm, va, 4587 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4588 4589 rv = 1; 4590 4591 out: 4592 pmap_release_pmap_lock(pm); 4593 4594 return (rv); 4595 } 4596 4597 /* 4598 * Routine: pmap_procwr 4599 * 4600 * Function: 4601 * Synchronize caches corresponding to [addr, addr+len) in p. 4602 * 4603 */ 4604 void 4605 pmap_procwr(struct proc *p, vaddr_t va, int len) 4606 { 4607 /* We only need to do anything if it is the current process. */ 4608 if (p == curproc) 4609 cpu_icache_sync_range(va, len); 4610 } 4611 4612 /* 4613 * Routine: pmap_unwire 4614 * Function: Clear the wired attribute for a map/virtual-address pair. 4615 * 4616 * In/out conditions: 4617 * The mapping must already exist in the pmap. 4618 */ 4619 void 4620 pmap_unwire(pmap_t pm, vaddr_t va) 4621 { 4622 struct l2_bucket *l2b; 4623 pt_entry_t *ptep, pte; 4624 struct vm_page *pg; 4625 paddr_t pa; 4626 4627 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4628 4629 pmap_acquire_pmap_lock(pm); 4630 4631 l2b = pmap_get_l2_bucket(pm, va); 4632 KDASSERT(l2b != NULL); 4633 4634 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4635 pte = *ptep; 4636 4637 /* Extract the physical address of the page */ 4638 pa = l2pte_pa(pte); 4639 4640 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4641 /* Update the wired bit in the pv entry for this page. */ 4642 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4643 4644 pmap_acquire_page_lock(md); 4645 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4646 pmap_release_page_lock(md); 4647 } 4648 4649 pmap_release_pmap_lock(pm); 4650 } 4651 4652 void 4653 pmap_activate(struct lwp *l) 4654 { 4655 struct cpu_info * const ci = curcpu(); 4656 extern int block_userspace_access; 4657 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4658 #ifdef ARM_MMU_EXTENDED 4659 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4660 #endif 4661 4662 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4663 4664 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4665 4666 /* 4667 * If activating a non-current lwp or the current lwp is 4668 * already active, just return. 4669 */ 4670 if (false 4671 || l != curlwp 4672 #ifdef ARM_MMU_EXTENDED 4673 || (ci->ci_pmap_cur == npm && 4674 (npm == pmap_kernel() 4675 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4676 #else 4677 || npm->pm_activated == true 4678 #endif 4679 || false) { 4680 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4681 return; 4682 } 4683 4684 #ifndef ARM_MMU_EXTENDED 4685 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4686 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4687 4688 /* 4689 * If TTB and DACR are unchanged, short-circuit all the 4690 * TLB/cache management stuff. 4691 */ 4692 pmap_t opm = ci->ci_lastlwp 4693 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4694 : NULL; 4695 if (opm != NULL) { 4696 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4697 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4698 4699 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4700 goto all_done; 4701 } 4702 #endif /* !ARM_MMU_EXTENDED */ 4703 4704 PMAPCOUNT(activations); 4705 block_userspace_access = 1; 4706 4707 #ifndef ARM_MMU_EXTENDED 4708 /* 4709 * If switching to a user vmspace which is different to the 4710 * most recent one, and the most recent one is potentially 4711 * live in the cache, we must write-back and invalidate the 4712 * entire cache. 4713 */ 4714 pmap_t rpm = ci->ci_pmap_lastuser; 4715 #endif 4716 4717 /* 4718 * XXXSCW: There's a corner case here which can leave turds in the cache as 4719 * reported in kern/41058. They're probably left over during tear-down and 4720 * switching away from an exiting process. Until the root cause is identified 4721 * and fixed, zap the cache when switching pmaps. This will result in a few 4722 * unnecessary cache flushes, but that's better than silently corrupting data. 4723 */ 4724 #ifndef ARM_MMU_EXTENDED 4725 #if 0 4726 if (npm != pmap_kernel() && rpm && npm != rpm && 4727 rpm->pm_cstate.cs_cache) { 4728 rpm->pm_cstate.cs_cache = 0; 4729 #ifdef PMAP_CACHE_VIVT 4730 cpu_idcache_wbinv_all(); 4731 #endif 4732 } 4733 #else 4734 if (rpm) { 4735 rpm->pm_cstate.cs_cache = 0; 4736 if (npm == pmap_kernel()) 4737 ci->ci_pmap_lastuser = NULL; 4738 #ifdef PMAP_CACHE_VIVT 4739 cpu_idcache_wbinv_all(); 4740 #endif 4741 } 4742 #endif 4743 4744 /* No interrupts while we frob the TTB/DACR */ 4745 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4746 #endif /* !ARM_MMU_EXTENDED */ 4747 4748 #ifndef ARM_HAS_VBAR 4749 /* 4750 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4751 * entry corresponding to 'vector_page' in the incoming L1 table 4752 * before switching to it otherwise subsequent interrupts/exceptions 4753 * (including domain faults!) will jump into hyperspace. 4754 */ 4755 if (npm->pm_pl1vec != NULL) { 4756 cpu_tlb_flushID_SE((u_int)vector_page); 4757 cpu_cpwait(); 4758 *npm->pm_pl1vec = npm->pm_l1vec; 4759 PTE_SYNC(npm->pm_pl1vec); 4760 } 4761 #endif 4762 4763 #ifdef ARM_MMU_EXTENDED 4764 /* 4765 * Assume that TTBR1 has only global mappings and TTBR0 only has 4766 * non-global mappings. To prevent speculation from doing evil things 4767 * we disable translation table walks using TTBR0 before setting the 4768 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4769 * walks are reenabled. 4770 */ 4771 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4772 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4773 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4774 arm_isb(); 4775 pmap_tlb_asid_acquire(npm, l); 4776 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4777 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4778 /* 4779 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4780 * been updated. 4781 */ 4782 arm_isb(); 4783 if (npm != pmap_kernel()) { 4784 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4785 } 4786 cpu_cpwait(); 4787 ci->ci_pmap_asid_cur = pai->pai_asid; 4788 #else 4789 cpu_domains(ndacr); 4790 if (npm == pmap_kernel() || npm == rpm) { 4791 /* 4792 * Switching to a kernel thread, or back to the 4793 * same user vmspace as before... Simply update 4794 * the TTB (no TLB flush required) 4795 */ 4796 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4797 cpu_cpwait(); 4798 } else { 4799 /* 4800 * Otherwise, update TTB and flush TLB 4801 */ 4802 cpu_context_switch(npm->pm_l1->l1_physaddr); 4803 if (rpm != NULL) 4804 rpm->pm_cstate.cs_tlb = 0; 4805 } 4806 4807 restore_interrupts(oldirqstate); 4808 #endif /* ARM_MMU_EXTENDED */ 4809 4810 block_userspace_access = 0; 4811 4812 #ifndef ARM_MMU_EXTENDED 4813 all_done: 4814 /* 4815 * The new pmap is resident. Make sure it's marked 4816 * as resident in the cache/TLB. 4817 */ 4818 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4819 if (npm != pmap_kernel()) 4820 ci->ci_pmap_lastuser = npm; 4821 4822 /* The old pmap is not longer active */ 4823 if (opm != npm) { 4824 if (opm != NULL) 4825 opm->pm_activated = false; 4826 4827 /* But the new one is */ 4828 npm->pm_activated = true; 4829 } 4830 #endif 4831 ci->ci_pmap_cur = npm; 4832 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4833 } 4834 4835 void 4836 pmap_deactivate(struct lwp *l) 4837 { 4838 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4839 4840 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4841 4842 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4843 4844 #ifdef ARM_MMU_EXTENDED 4845 kpreempt_disable(); 4846 struct cpu_info * const ci = curcpu(); 4847 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4848 /* 4849 * Disable translation table walks from TTBR0 while no pmap has been 4850 * activated. 4851 */ 4852 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4853 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4854 arm_isb(); 4855 pmap_tlb_asid_deactivate(pm); 4856 cpu_setttb(pmap_kernel()->pm_l1_pa, pai->pai_asid); 4857 ci->ci_pmap_cur = pmap_kernel(); 4858 kpreempt_enable(); 4859 #else 4860 /* 4861 * If the process is exiting, make sure pmap_activate() does 4862 * a full MMU context-switch and cache flush, which we might 4863 * otherwise skip. See PR port-arm/38950. 4864 */ 4865 if (l->l_proc->p_sflag & PS_WEXIT) 4866 curcpu()->ci_lastlwp = NULL; 4867 4868 pm->pm_activated = false; 4869 #endif 4870 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4871 } 4872 4873 void 4874 pmap_update(pmap_t pm) 4875 { 4876 4877 if (pm->pm_remove_all) { 4878 #ifdef ARM_MMU_EXTENDED 4879 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4880 /* 4881 * Finish up the pmap_remove_all() optimisation by flushing 4882 * all our ASIDs. 4883 */ 4884 pmap_tlb_asid_release_all(pm); 4885 #else 4886 /* 4887 * Finish up the pmap_remove_all() optimisation by flushing 4888 * the TLB. 4889 */ 4890 pmap_tlb_flushID(pm); 4891 #endif 4892 pm->pm_remove_all = false; 4893 } 4894 4895 #ifdef ARM_MMU_EXTENDED 4896 4897 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4898 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4899 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4900 PMAP_COUNT(shootdown_ipis); 4901 } 4902 #endif 4903 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4904 #else 4905 if (pmap_is_current(pm)) { 4906 /* 4907 * If we're dealing with a current userland pmap, move its L1 4908 * to the end of the LRU. 4909 */ 4910 if (pm != pmap_kernel()) 4911 pmap_use_l1(pm); 4912 4913 /* 4914 * We can assume we're done with frobbing the cache/tlb for 4915 * now. Make sure any future pmap ops don't skip cache/tlb 4916 * flushes. 4917 */ 4918 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4919 } 4920 #endif 4921 4922 PMAPCOUNT(updates); 4923 4924 /* 4925 * make sure TLB/cache operations have completed. 4926 */ 4927 cpu_cpwait(); 4928 } 4929 4930 void 4931 pmap_remove_all(pmap_t pm) 4932 { 4933 4934 /* 4935 * The vmspace described by this pmap is about to be torn down. 4936 * Until pmap_update() is called, UVM will only make calls 4937 * to pmap_remove(). We can make life much simpler by flushing 4938 * the cache now, and deferring TLB invalidation to pmap_update(). 4939 */ 4940 #ifdef PMAP_CACHE_VIVT 4941 pmap_cache_wbinv_all(pm, PVF_EXEC); 4942 #endif 4943 pm->pm_remove_all = true; 4944 } 4945 4946 /* 4947 * Retire the given physical map from service. 4948 * Should only be called if the map contains no valid mappings. 4949 */ 4950 void 4951 pmap_destroy(pmap_t pm) 4952 { 4953 u_int count; 4954 4955 if (pm == NULL) 4956 return; 4957 4958 if (pm->pm_remove_all) { 4959 pmap_tlb_flushID(pm); 4960 pm->pm_remove_all = false; 4961 } 4962 4963 /* 4964 * Drop reference count 4965 */ 4966 mutex_enter(pm->pm_lock); 4967 count = --pm->pm_obj.uo_refs; 4968 mutex_exit(pm->pm_lock); 4969 if (count > 0) { 4970 #ifndef ARM_MMU_EXTENDED 4971 if (pmap_is_current(pm)) { 4972 if (pm != pmap_kernel()) 4973 pmap_use_l1(pm); 4974 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4975 } 4976 #endif 4977 return; 4978 } 4979 4980 /* 4981 * reference count is zero, free pmap resources and then free pmap. 4982 */ 4983 4984 #ifndef ARM_HAS_VBAR 4985 if (vector_page < KERNEL_BASE) { 4986 KDASSERT(!pmap_is_current(pm)); 4987 4988 /* Remove the vector page mapping */ 4989 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4990 pmap_update(pm); 4991 } 4992 #endif 4993 4994 LIST_REMOVE(pm, pm_list); 4995 4996 pmap_free_l1(pm); 4997 4998 #ifdef ARM_MMU_EXTENDED 4999 #ifdef MULTIPROCESSOR 5000 kcpuset_destroy(pm->pm_active); 5001 kcpuset_destroy(pm->pm_onproc); 5002 #endif 5003 #else 5004 struct cpu_info * const ci = curcpu(); 5005 if (ci->ci_pmap_lastuser == pm) 5006 ci->ci_pmap_lastuser = NULL; 5007 #endif 5008 5009 uvm_obj_destroy(&pm->pm_obj, false); 5010 mutex_destroy(&pm->pm_obj_lock); 5011 pool_cache_put(&pmap_cache, pm); 5012 } 5013 5014 5015 /* 5016 * void pmap_reference(pmap_t pm) 5017 * 5018 * Add a reference to the specified pmap. 5019 */ 5020 void 5021 pmap_reference(pmap_t pm) 5022 { 5023 5024 if (pm == NULL) 5025 return; 5026 5027 #ifndef ARM_MMU_EXTENDED 5028 pmap_use_l1(pm); 5029 #endif 5030 5031 mutex_enter(pm->pm_lock); 5032 pm->pm_obj.uo_refs++; 5033 mutex_exit(pm->pm_lock); 5034 } 5035 5036 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5037 5038 static struct evcnt pmap_prefer_nochange_ev = 5039 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5040 static struct evcnt pmap_prefer_change_ev = 5041 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5042 5043 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5044 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5045 5046 void 5047 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5048 { 5049 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5050 vaddr_t va = *vap; 5051 vaddr_t diff = (hint - va) & mask; 5052 if (diff == 0) { 5053 pmap_prefer_nochange_ev.ev_count++; 5054 } else { 5055 pmap_prefer_change_ev.ev_count++; 5056 if (__predict_false(td)) 5057 va -= mask + 1; 5058 *vap = va + diff; 5059 } 5060 } 5061 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5062 5063 /* 5064 * pmap_zero_page() 5065 * 5066 * Zero a given physical page by mapping it at a page hook point. 5067 * In doing the zero page op, the page we zero is mapped cachable, as with 5068 * StrongARM accesses to non-cached pages are non-burst making writing 5069 * _any_ bulk data very slow. 5070 */ 5071 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5072 void 5073 pmap_zero_page_generic(paddr_t pa) 5074 { 5075 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5076 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5077 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5078 #endif 5079 #if defined(PMAP_CACHE_VIPT) 5080 /* Choose the last page color it had, if any */ 5081 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5082 #else 5083 const vsize_t va_offset = 0; 5084 #endif 5085 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5086 /* 5087 * Is this page mapped at its natural color? 5088 * If we have all of memory mapped, then just convert PA to VA. 5089 */ 5090 const bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5091 || va_offset == (pa & arm_cache_prefer_mask); 5092 const vaddr_t vdstp = okcolor 5093 ? KERNEL_BASE + (pa - physical_start) 5094 : cpu_cdstp(va_offset); 5095 #else 5096 const bool okcolor = false; 5097 const vaddr_t vdstp = cpu_cdstp(va_offset); 5098 #endif 5099 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5100 5101 5102 #ifdef DEBUG 5103 if (!SLIST_EMPTY(&md->pvh_list)) 5104 panic("pmap_zero_page: page has mappings"); 5105 #endif 5106 5107 KDASSERT((pa & PGOFSET) == 0); 5108 5109 if (!okcolor) { 5110 /* 5111 * Hook in the page, zero it, and purge the cache for that 5112 * zeroed page. Invalidate the TLB as needed. 5113 */ 5114 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5115 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5116 l2pte_set(ptep, npte, 0); 5117 PTE_SYNC(ptep); 5118 cpu_tlb_flushD_SE(vdstp); 5119 cpu_cpwait(); 5120 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5121 /* 5122 * If we are direct-mapped and our color isn't ok, then before 5123 * we bzero the page invalidate its contents from the cache and 5124 * reset the color to its natural color. 5125 */ 5126 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5127 md->pvh_attrs &= ~arm_cache_prefer_mask; 5128 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5129 #endif 5130 } 5131 bzero_page(vdstp); 5132 if (!okcolor) { 5133 /* 5134 * Unmap the page. 5135 */ 5136 l2pte_reset(ptep); 5137 PTE_SYNC(ptep); 5138 cpu_tlb_flushD_SE(vdstp); 5139 #ifdef PMAP_CACHE_VIVT 5140 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5141 #endif 5142 } 5143 #ifdef PMAP_CACHE_VIPT 5144 /* 5145 * This page is now cache resident so it now has a page color. 5146 * Any contents have been obliterated so clear the EXEC flag. 5147 */ 5148 #ifndef ARM_MMU_EXTENDED 5149 if (!pmap_is_page_colored_p(md)) { 5150 PMAPCOUNT(vac_color_new); 5151 md->pvh_attrs |= PVF_COLORED; 5152 } 5153 md->pvh_attrs |= PVF_DIRTY; 5154 #endif 5155 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5156 md->pvh_attrs &= ~PVF_EXEC; 5157 PMAPCOUNT(exec_discarded_zero); 5158 } 5159 #endif 5160 } 5161 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5162 5163 #if ARM_MMU_XSCALE == 1 5164 void 5165 pmap_zero_page_xscale(paddr_t pa) 5166 { 5167 #ifdef DEBUG 5168 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5169 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5170 5171 if (!SLIST_EMPTY(&md->pvh_list)) 5172 panic("pmap_zero_page: page has mappings"); 5173 #endif 5174 5175 KDASSERT((pa & PGOFSET) == 0); 5176 5177 /* 5178 * Hook in the page, zero it, and purge the cache for that 5179 * zeroed page. Invalidate the TLB as needed. 5180 */ 5181 5182 pt_entry_t npte = L2_S_PROTO | pa | 5183 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5184 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5185 l2pte_set(cdst_pte, npte, 0); 5186 PTE_SYNC(cdst_pte); 5187 cpu_tlb_flushD_SE(cdstp); 5188 cpu_cpwait(); 5189 bzero_page(cdstp); 5190 xscale_cache_clean_minidata(); 5191 l2pte_reset(cdst_pte); 5192 PTE_SYNC(cdst_pte); 5193 } 5194 #endif /* ARM_MMU_XSCALE == 1 */ 5195 5196 /* pmap_pageidlezero() 5197 * 5198 * The same as above, except that we assume that the page is not 5199 * mapped. This means we never have to flush the cache first. Called 5200 * from the idle loop. 5201 */ 5202 bool 5203 pmap_pageidlezero(paddr_t pa) 5204 { 5205 bool rv = true; 5206 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5207 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5208 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5209 #endif 5210 #ifdef PMAP_CACHE_VIPT 5211 /* Choose the last page color it had, if any */ 5212 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5213 #else 5214 const vsize_t va_offset = 0; 5215 #endif 5216 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5217 const bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5218 || va_offset == (pa & arm_cache_prefer_mask); 5219 const vaddr_t vdstp = okcolor 5220 ? KERNEL_BASE + (pa - physical_start) 5221 : cpu_cdstp(va_offset); 5222 #else 5223 const bool okcolor = false; 5224 const vaddr_t vdstp = cpu_cdstp(va_offset); 5225 #endif 5226 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5227 5228 5229 #ifdef DEBUG 5230 if (!SLIST_EMPTY(&md->pvh_list)) 5231 panic("pmap_pageidlezero: page has mappings"); 5232 #endif 5233 5234 KDASSERT((pa & PGOFSET) == 0); 5235 5236 if (!okcolor) { 5237 /* 5238 * Hook in the page, zero it, and purge the cache for that 5239 * zeroed page. Invalidate the TLB as needed. 5240 */ 5241 const pt_entry_t npte = L2_S_PROTO | pa | 5242 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5243 l2pte_set(ptep, npte, 0); 5244 PTE_SYNC(ptep); 5245 cpu_tlb_flushD_SE(vdstp); 5246 cpu_cpwait(); 5247 } 5248 5249 uint64_t *ptr = (uint64_t *)vdstp; 5250 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5251 if (sched_curcpu_runnable_p() != 0) { 5252 /* 5253 * A process has become ready. Abort now, 5254 * so we don't keep it waiting while we 5255 * do slow memory access to finish this 5256 * page. 5257 */ 5258 rv = false; 5259 break; 5260 } 5261 *ptr++ = 0; 5262 } 5263 5264 #ifdef PMAP_CACHE_VIVT 5265 if (rv) 5266 /* 5267 * if we aborted we'll rezero this page again later so don't 5268 * purge it unless we finished it 5269 */ 5270 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5271 #elif defined(PMAP_CACHE_VIPT) 5272 /* 5273 * This page is now cache resident so it now has a page color. 5274 * Any contents have been obliterated so clear the EXEC flag. 5275 */ 5276 #ifndef ARM_MMU_EXTENDED 5277 if (!pmap_is_page_colored_p(md)) { 5278 PMAPCOUNT(vac_color_new); 5279 md->pvh_attrs |= PVF_COLORED; 5280 } 5281 #endif 5282 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5283 md->pvh_attrs &= ~PVF_EXEC; 5284 PMAPCOUNT(exec_discarded_zero); 5285 } 5286 #endif 5287 /* 5288 * Unmap the page. 5289 */ 5290 if (!okcolor) { 5291 l2pte_reset(ptep); 5292 PTE_SYNC(ptep); 5293 cpu_tlb_flushD_SE(vdstp); 5294 } 5295 5296 return rv; 5297 } 5298 5299 /* 5300 * pmap_copy_page() 5301 * 5302 * Copy one physical page into another, by mapping the pages into 5303 * hook points. The same comment regarding cachability as in 5304 * pmap_zero_page also applies here. 5305 */ 5306 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5307 void 5308 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5309 { 5310 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5311 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5312 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5313 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5314 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5315 #endif 5316 #ifdef PMAP_CACHE_VIPT 5317 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5318 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5319 #else 5320 const vsize_t src_va_offset = 0; 5321 const vsize_t dst_va_offset = 0; 5322 #endif 5323 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5324 /* 5325 * Is this page mapped at its natural color? 5326 * If we have all of memory mapped, then just convert PA to VA. 5327 */ 5328 const bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5329 || src_va_offset == (src & arm_cache_prefer_mask); 5330 const bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5331 || dst_va_offset == (dst & arm_cache_prefer_mask); 5332 const vaddr_t vsrcp = src_okcolor 5333 ? KERNEL_BASE + (src - physical_start) 5334 : cpu_csrcp(src_va_offset); 5335 const vaddr_t vdstp = KERNEL_BASE + (dst - physical_start); 5336 #else 5337 const bool src_okcolor = false; 5338 const bool dst_okcolor = false; 5339 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5340 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5341 #endif 5342 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5343 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5344 5345 #ifdef DEBUG 5346 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5347 panic("pmap_copy_page: dst page has mappings"); 5348 #endif 5349 5350 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5351 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5352 #endif 5353 KDASSERT((src & PGOFSET) == 0); 5354 KDASSERT((dst & PGOFSET) == 0); 5355 5356 /* 5357 * Clean the source page. Hold the source page's lock for 5358 * the duration of the copy so that no other mappings can 5359 * be created while we have a potentially aliased mapping. 5360 */ 5361 #ifdef PMAP_CACHE_VIVT 5362 pmap_acquire_page_lock(src_md); 5363 (void) pmap_clean_page(src_md, true); 5364 pmap_release_page_lock(src_md); 5365 #endif 5366 5367 /* 5368 * Map the pages into the page hook points, copy them, and purge 5369 * the cache for the appropriate page. Invalidate the TLB 5370 * as required. 5371 */ 5372 if (!src_okcolor) { 5373 const pt_entry_t nsrc_pte = L2_S_PROTO 5374 | src 5375 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5376 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5377 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5378 | pte_l2_s_cache_mode 5379 #endif 5380 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5381 l2pte_set(src_ptep, nsrc_pte, 0); 5382 PTE_SYNC(src_ptep); 5383 cpu_tlb_flushD_SE(vsrcp); 5384 cpu_cpwait(); 5385 } 5386 if (!dst_okcolor) { 5387 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5388 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5389 l2pte_set(dst_ptep, ndst_pte, 0); 5390 PTE_SYNC(dst_ptep); 5391 cpu_tlb_flushD_SE(vdstp); 5392 cpu_cpwait(); 5393 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5394 /* 5395 * If we are direct-mapped and our color isn't ok, then before 5396 * we bcopy to the new page invalidate its contents from the 5397 * cache and reset its color to its natural color. 5398 */ 5399 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5400 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5401 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5402 #endif 5403 } 5404 bcopy_page(vsrcp, vdstp); 5405 #ifdef PMAP_CACHE_VIVT 5406 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5407 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5408 #endif 5409 /* 5410 * Unmap the pages. 5411 */ 5412 if (!src_okcolor) { 5413 l2pte_reset(src_ptep); 5414 PTE_SYNC(src_ptep); 5415 cpu_tlb_flushD_SE(vsrcp); 5416 cpu_cpwait(); 5417 } 5418 if (!dst_okcolor) { 5419 l2pte_reset(dst_ptep); 5420 PTE_SYNC(dst_ptep); 5421 cpu_tlb_flushD_SE(vdstp); 5422 cpu_cpwait(); 5423 } 5424 #ifdef PMAP_CACHE_VIPT 5425 /* 5426 * Now that the destination page is in the cache, mark it as colored. 5427 * If this was an exec page, discard it. 5428 */ 5429 pmap_acquire_page_lock(dst_md); 5430 #ifndef ARM_MMU_EXTENDED 5431 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5432 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5433 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5434 } 5435 if (!pmap_is_page_colored_p(dst_md)) { 5436 PMAPCOUNT(vac_color_new); 5437 dst_md->pvh_attrs |= PVF_COLORED; 5438 } 5439 dst_md->pvh_attrs |= PVF_DIRTY; 5440 #endif 5441 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5442 dst_md->pvh_attrs &= ~PVF_EXEC; 5443 PMAPCOUNT(exec_discarded_copy); 5444 } 5445 pmap_release_page_lock(dst_md); 5446 #endif 5447 } 5448 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5449 5450 #if ARM_MMU_XSCALE == 1 5451 void 5452 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5453 { 5454 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5455 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5456 #ifdef DEBUG 5457 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5458 5459 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5460 panic("pmap_copy_page: dst page has mappings"); 5461 #endif 5462 5463 KDASSERT((src & PGOFSET) == 0); 5464 KDASSERT((dst & PGOFSET) == 0); 5465 5466 /* 5467 * Clean the source page. Hold the source page's lock for 5468 * the duration of the copy so that no other mappings can 5469 * be created while we have a potentially aliased mapping. 5470 */ 5471 #ifdef PMAP_CACHE_VIVT 5472 pmap_acquire_page_lock(src_md); 5473 (void) pmap_clean_page(src_md, true); 5474 pmap_release_page_lock(src_md); 5475 #endif 5476 5477 /* 5478 * Map the pages into the page hook points, copy them, and purge 5479 * the cache for the appropriate page. Invalidate the TLB 5480 * as required. 5481 */ 5482 *csrc_pte = L2_S_PROTO | src | 5483 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 5484 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5485 PTE_SYNC(csrc_pte); 5486 *cdst_pte = L2_S_PROTO | dst | 5487 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5488 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5489 PTE_SYNC(cdst_pte); 5490 cpu_tlb_flushD_SE(csrcp); 5491 cpu_tlb_flushD_SE(cdstp); 5492 cpu_cpwait(); 5493 bcopy_page(csrcp, cdstp); 5494 xscale_cache_clean_minidata(); 5495 } 5496 #endif /* ARM_MMU_XSCALE == 1 */ 5497 5498 /* 5499 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5500 * 5501 * Return the start and end addresses of the kernel's virtual space. 5502 * These values are setup in pmap_bootstrap and are updated as pages 5503 * are allocated. 5504 */ 5505 void 5506 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5507 { 5508 *start = virtual_avail; 5509 *end = virtual_end; 5510 } 5511 5512 /* 5513 * Helper function for pmap_grow_l2_bucket() 5514 */ 5515 static inline int 5516 pmap_grow_map(vaddr_t va, paddr_t *pap) 5517 { 5518 paddr_t pa; 5519 5520 if (uvm.page_init_done == false) { 5521 #ifdef PMAP_STEAL_MEMORY 5522 pv_addr_t pv; 5523 pmap_boot_pagealloc(PAGE_SIZE, 5524 #ifdef PMAP_CACHE_VIPT 5525 arm_cache_prefer_mask, 5526 va & arm_cache_prefer_mask, 5527 #else 5528 0, 0, 5529 #endif 5530 &pv); 5531 pa = pv.pv_pa; 5532 #else 5533 if (uvm_page_physget(&pa) == false) 5534 return (1); 5535 #endif /* PMAP_STEAL_MEMORY */ 5536 } else { 5537 struct vm_page *pg; 5538 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5539 if (pg == NULL) 5540 return (1); 5541 pa = VM_PAGE_TO_PHYS(pg); 5542 #ifdef PMAP_CACHE_VIPT 5543 #ifdef DIAGNOSTIC 5544 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5545 #endif 5546 /* 5547 * This new page must not have any mappings. Enter it via 5548 * pmap_kenter_pa and let that routine do the hard work. 5549 */ 5550 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5551 pmap_kenter_pa(va, pa, 5552 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5553 #endif 5554 } 5555 5556 if (pap) 5557 *pap = pa; 5558 5559 PMAPCOUNT(pt_mappings); 5560 #ifdef DEBUG 5561 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5562 KDASSERT(l2b != NULL); 5563 5564 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5565 const pt_entry_t opte = *ptep; 5566 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5567 #endif 5568 memset((void *)va, 0, PAGE_SIZE); 5569 return (0); 5570 } 5571 5572 /* 5573 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5574 * used by pmap_growkernel(). 5575 */ 5576 static inline struct l2_bucket * 5577 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5578 { 5579 struct l2_dtable *l2; 5580 struct l2_bucket *l2b; 5581 u_short l1slot; 5582 vaddr_t nva; 5583 5584 l1slot = l1pte_index(va); 5585 5586 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5587 /* 5588 * No mapping at this address, as there is 5589 * no entry in the L1 table. 5590 * Need to allocate a new l2_dtable. 5591 */ 5592 nva = pmap_kernel_l2dtable_kva; 5593 if ((nva & PGOFSET) == 0) { 5594 /* 5595 * Need to allocate a backing page 5596 */ 5597 if (pmap_grow_map(nva, NULL)) 5598 return (NULL); 5599 } 5600 5601 l2 = (struct l2_dtable *)nva; 5602 nva += sizeof(struct l2_dtable); 5603 5604 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5605 /* 5606 * The new l2_dtable straddles a page boundary. 5607 * Map in another page to cover it. 5608 */ 5609 if (pmap_grow_map(nva, NULL)) 5610 return (NULL); 5611 } 5612 5613 pmap_kernel_l2dtable_kva = nva; 5614 5615 /* 5616 * Link it into the parent pmap 5617 */ 5618 pm->pm_l2[L2_IDX(l1slot)] = l2; 5619 } 5620 5621 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5622 5623 /* 5624 * Fetch pointer to the L2 page table associated with the address. 5625 */ 5626 if (l2b->l2b_kva == NULL) { 5627 pt_entry_t *ptep; 5628 5629 /* 5630 * No L2 page table has been allocated. Chances are, this 5631 * is because we just allocated the l2_dtable, above. 5632 */ 5633 nva = pmap_kernel_l2ptp_kva; 5634 ptep = (pt_entry_t *)nva; 5635 if ((nva & PGOFSET) == 0) { 5636 /* 5637 * Need to allocate a backing page 5638 */ 5639 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5640 return (NULL); 5641 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5642 } 5643 5644 l2->l2_occupancy++; 5645 l2b->l2b_kva = ptep; 5646 l2b->l2b_l1slot = l1slot; 5647 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5648 5649 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5650 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5651 } 5652 5653 return (l2b); 5654 } 5655 5656 vaddr_t 5657 pmap_growkernel(vaddr_t maxkvaddr) 5658 { 5659 pmap_t kpm = pmap_kernel(); 5660 #ifndef ARM_MMU_EXTENDED 5661 struct l1_ttable *l1; 5662 #endif 5663 int s; 5664 5665 if (maxkvaddr <= pmap_curmaxkvaddr) 5666 goto out; /* we are OK */ 5667 5668 NPDEBUG(PDB_GROWKERN, 5669 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5670 pmap_curmaxkvaddr, maxkvaddr)); 5671 5672 KDASSERT(maxkvaddr <= virtual_end); 5673 5674 /* 5675 * whoops! we need to add kernel PTPs 5676 */ 5677 5678 s = splhigh(); /* to be safe */ 5679 mutex_enter(kpm->pm_lock); 5680 5681 /* Map 1MB at a time */ 5682 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5683 #ifdef ARM_MMU_EXTENDED 5684 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5685 pd_entry_t *pdep = spdep; 5686 #endif 5687 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5688 #ifdef ARM_MMU_EXTENDED 5689 pdep++, 5690 #endif 5691 l1slot++) { 5692 struct l2_bucket *l2b = 5693 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5694 KASSERT(l2b != NULL); 5695 5696 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5697 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5698 #ifdef ARM_MMU_EXTENDED 5699 l1pte_setone(pdep, npde); 5700 #else 5701 /* Distribute new L1 entry to all other L1s */ 5702 SLIST_FOREACH(l1, &l1_list, l1_link) { 5703 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5704 l1pte_setone(pdep, npde); 5705 PDE_SYNC(pdep); 5706 } 5707 #endif 5708 } 5709 #ifdef ARM_MMU_EXTENDED 5710 PDE_SYNC_RANGE(spdep, pdep - spdep); 5711 #endif 5712 5713 #ifdef PMAP_CACHE_VIVT 5714 /* 5715 * flush out the cache, expensive but growkernel will happen so 5716 * rarely 5717 */ 5718 cpu_dcache_wbinv_all(); 5719 cpu_tlb_flushD(); 5720 cpu_cpwait(); 5721 #endif 5722 5723 mutex_exit(kpm->pm_lock); 5724 splx(s); 5725 5726 out: 5727 return (pmap_curmaxkvaddr); 5728 } 5729 5730 /************************ Utility routines ****************************/ 5731 5732 #ifndef ARM_HAS_VBAR 5733 /* 5734 * vector_page_setprot: 5735 * 5736 * Manipulate the protection of the vector page. 5737 */ 5738 void 5739 vector_page_setprot(int prot) 5740 { 5741 struct l2_bucket *l2b; 5742 pt_entry_t *ptep; 5743 5744 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5745 /* 5746 * If we are using VBAR to use the vectors in the kernel, then it's 5747 * already mapped in the kernel text so no need to anything here. 5748 */ 5749 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5750 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5751 return; 5752 } 5753 #endif 5754 5755 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5756 KASSERT(l2b != NULL); 5757 5758 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5759 5760 const pt_entry_t opte = *ptep; 5761 #ifdef ARM_MMU_EXTENDED 5762 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5763 | L2_S_PROT(PTE_KERNEL, prot); 5764 #else 5765 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5766 | L2_S_PROT(PTE_KERNEL, prot); 5767 #endif 5768 l2pte_set(ptep, npte, opte); 5769 PTE_SYNC(ptep); 5770 cpu_tlb_flushD_SE(vector_page); 5771 cpu_cpwait(); 5772 } 5773 #endif 5774 5775 /* 5776 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5777 * Returns true if the mapping exists, else false. 5778 * 5779 * NOTE: This function is only used by a couple of arm-specific modules. 5780 * It is not safe to take any pmap locks here, since we could be right 5781 * in the middle of debugging the pmap anyway... 5782 * 5783 * It is possible for this routine to return false even though a valid 5784 * mapping does exist. This is because we don't lock, so the metadata 5785 * state may be inconsistent. 5786 * 5787 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5788 * a "section" mapping. 5789 */ 5790 bool 5791 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5792 { 5793 struct l2_dtable *l2; 5794 pd_entry_t *pdep, pde; 5795 pt_entry_t *ptep; 5796 u_short l1slot; 5797 5798 if (pm->pm_l1 == NULL) 5799 return false; 5800 5801 l1slot = l1pte_index(va); 5802 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5803 pde = *pdep; 5804 5805 if (l1pte_section_p(pde)) { 5806 *ptp = NULL; 5807 return true; 5808 } 5809 5810 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5811 if (l2 == NULL || 5812 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5813 return false; 5814 } 5815 5816 *ptp = &ptep[l2pte_index(va)]; 5817 return true; 5818 } 5819 5820 bool 5821 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5822 { 5823 5824 if (pm->pm_l1 == NULL) 5825 return false; 5826 5827 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5828 5829 return true; 5830 } 5831 5832 /************************ Bootstrapping routines ****************************/ 5833 5834 #ifndef ARM_MMU_EXTENDED 5835 static void 5836 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5837 { 5838 int i; 5839 5840 l1->l1_kva = l1pt; 5841 l1->l1_domain_use_count = 0; 5842 l1->l1_domain_first = 0; 5843 5844 for (i = 0; i < PMAP_DOMAINS; i++) 5845 l1->l1_domain_free[i] = i + 1; 5846 5847 /* 5848 * Copy the kernel's L1 entries to each new L1. 5849 */ 5850 if (pmap_initialized) 5851 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5852 5853 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5854 &l1->l1_physaddr) == false) 5855 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5856 5857 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5858 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5859 } 5860 #endif /* !ARM_MMU_EXTENDED */ 5861 5862 /* 5863 * pmap_bootstrap() is called from the board-specific initarm() routine 5864 * once the kernel L1/L2 descriptors tables have been set up. 5865 * 5866 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5867 * spread over a number of disparate files/functions. 5868 * 5869 * We are passed the following parameters 5870 * - kernel_l1pt 5871 * This is a pointer to the base of the kernel's L1 translation table. 5872 * - vstart 5873 * 1MB-aligned start of managed kernel virtual memory. 5874 * - vend 5875 * 1MB-aligned end of managed kernel virtual memory. 5876 * 5877 * We use the first parameter to build the metadata (struct l1_ttable and 5878 * struct l2_dtable) necessary to track kernel mappings. 5879 */ 5880 #define PMAP_STATIC_L2_SIZE 16 5881 void 5882 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5883 { 5884 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5885 #ifndef ARM_MMU_EXTENDED 5886 static struct l1_ttable static_l1; 5887 struct l1_ttable *l1 = &static_l1; 5888 #endif 5889 struct l2_dtable *l2; 5890 struct l2_bucket *l2b; 5891 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5892 pmap_t pm = pmap_kernel(); 5893 pt_entry_t *ptep; 5894 paddr_t pa; 5895 vsize_t size; 5896 int nptes, l2idx, l2next = 0; 5897 5898 #ifdef ARM_MMU_EXTENDED 5899 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5900 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5901 #endif 5902 5903 #ifdef VERBOSE_INIT_ARM 5904 printf("kpm "); 5905 #endif 5906 /* 5907 * Initialise the kernel pmap object 5908 */ 5909 curcpu()->ci_pmap_cur = pm; 5910 #ifdef ARM_MMU_EXTENDED 5911 pm->pm_l1 = l1pt; 5912 pm->pm_l1_pa = kernel_l1pt.pv_pa; 5913 #ifdef VERBOSE_INIT_ARM 5914 printf("tlb0 "); 5915 #endif 5916 pmap_tlb_info_init(&pmap_tlb0_info); 5917 #ifdef MULTIPROCESSOR 5918 #ifdef VERBOSE_INIT_ARM 5919 printf("kcpusets "); 5920 #endif 5921 pm->pm_onproc = kcpuset_running; 5922 pm->pm_active = kcpuset_running; 5923 #endif 5924 #else 5925 pm->pm_l1 = l1; 5926 #endif 5927 5928 #ifdef VERBOSE_INIT_ARM 5929 printf("locks "); 5930 #endif 5931 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 5932 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5933 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5934 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5935 5936 #ifdef VERBOSE_INIT_ARM 5937 printf("l1pt "); 5938 #endif 5939 /* 5940 * Scan the L1 translation table created by initarm() and create 5941 * the required metadata for all valid mappings found in it. 5942 */ 5943 for (size_t l1slot = 0; l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 5944 l1slot++) { 5945 pd_entry_t pde = l1pt[l1slot]; 5946 5947 /* 5948 * We're only interested in Coarse mappings. 5949 * pmap_extract() can deal with section mappings without 5950 * recourse to checking L2 metadata. 5951 */ 5952 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5953 continue; 5954 5955 /* 5956 * Lookup the KVA of this L2 descriptor table 5957 */ 5958 pa = l1pte_pa(pde); 5959 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5960 if (ptep == NULL) { 5961 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5962 (u_int)l1slot << L1_S_SHIFT, pa); 5963 } 5964 5965 /* 5966 * Fetch the associated L2 metadata structure. 5967 * Allocate a new one if necessary. 5968 */ 5969 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5970 if (l2next == PMAP_STATIC_L2_SIZE) 5971 panic("pmap_bootstrap: out of static L2s"); 5972 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 5973 } 5974 5975 /* 5976 * One more L1 slot tracked... 5977 */ 5978 l2->l2_occupancy++; 5979 5980 /* 5981 * Fill in the details of the L2 descriptor in the 5982 * appropriate bucket. 5983 */ 5984 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5985 l2b->l2b_kva = ptep; 5986 l2b->l2b_pa = pa; 5987 l2b->l2b_l1slot = l1slot; 5988 5989 /* 5990 * Establish an initial occupancy count for this descriptor 5991 */ 5992 for (l2idx = 0; 5993 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5994 l2idx++) { 5995 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5996 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 5997 } 5998 } 5999 6000 /* 6001 * Make sure the descriptor itself has the correct cache mode. 6002 * If not, fix it, but whine about the problem. Port-meisters 6003 * should consider this a clue to fix up their initarm() 6004 * function. :) 6005 */ 6006 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6007 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6008 "L2 pte @ %p\n", ptep); 6009 } 6010 } 6011 6012 #ifdef VERBOSE_INIT_ARM 6013 printf("cache(l1pt) "); 6014 #endif 6015 /* 6016 * Ensure the primary (kernel) L1 has the correct cache mode for 6017 * a page table. Bitch if it is not correctly set. 6018 */ 6019 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6020 L1_TABLE_SIZE / L2_S_SIZE)) { 6021 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6022 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6023 } 6024 6025 #ifdef PMAP_CACHE_VIVT 6026 cpu_dcache_wbinv_all(); 6027 cpu_tlb_flushID(); 6028 cpu_cpwait(); 6029 #endif 6030 6031 /* 6032 * now we allocate the "special" VAs which are used for tmp mappings 6033 * by the pmap (and other modules). we allocate the VAs by advancing 6034 * virtual_avail (note that there are no pages mapped at these VAs). 6035 * 6036 * Managed KVM space start from wherever initarm() tells us. 6037 */ 6038 virtual_avail = vstart; 6039 virtual_end = vend; 6040 6041 #ifdef VERBOSE_INIT_ARM 6042 printf("specials "); 6043 #endif 6044 #ifdef PMAP_CACHE_VIPT 6045 /* 6046 * If we have a VIPT cache, we need one page/pte per possible alias 6047 * page so we won't violate cache aliasing rules. 6048 */ 6049 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6050 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6051 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6052 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6053 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6054 } 6055 #else 6056 nptes = PAGE_SIZE / L2_S_SIZE; 6057 #endif 6058 #ifdef MULTIPROCESSOR 6059 cnptes = nptes; 6060 nptes *= arm_cpu_max; 6061 #endif 6062 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6063 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6064 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6065 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6066 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6067 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 6068 (void *)&msgbufaddr, NULL); 6069 6070 /* 6071 * Allocate a range of kernel virtual address space to be used 6072 * for L2 descriptor tables and metadata allocation in 6073 * pmap_growkernel(). 6074 */ 6075 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6076 pmap_alloc_specials(&virtual_avail, 6077 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6078 &pmap_kernel_l2ptp_kva, NULL); 6079 6080 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6081 pmap_alloc_specials(&virtual_avail, 6082 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6083 &pmap_kernel_l2dtable_kva, NULL); 6084 6085 #ifndef ARM_MMU_EXTENDED 6086 /* 6087 * init the static-global locks and global pmap list. 6088 */ 6089 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6090 6091 /* 6092 * We can now initialise the first L1's metadata. 6093 */ 6094 SLIST_INIT(&l1_list); 6095 TAILQ_INIT(&l1_lru_list); 6096 pmap_init_l1(l1, l1pt); 6097 #endif /* ARM_MMU_EXTENDED */ 6098 6099 #ifndef ARM_HAS_VBAR 6100 /* Set up vector page L1 details, if necessary */ 6101 if (vector_page < KERNEL_BASE) { 6102 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6103 l2b = pmap_get_l2_bucket(pm, vector_page); 6104 KDASSERT(l2b != NULL); 6105 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6106 L1_C_DOM(pmap_domain(pm)); 6107 } else 6108 pm->pm_pl1vec = NULL; 6109 #endif 6110 6111 #ifdef VERBOSE_INIT_ARM 6112 printf("pools "); 6113 #endif 6114 /* 6115 * Initialize the pmap cache 6116 */ 6117 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6118 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6119 LIST_INIT(&pmap_pmaps); 6120 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6121 6122 /* 6123 * Initialize the pv pool. 6124 */ 6125 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6126 &pmap_bootstrap_pv_allocator, IPL_NONE); 6127 6128 /* 6129 * Initialize the L2 dtable pool and cache. 6130 */ 6131 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6132 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6133 6134 /* 6135 * Initialise the L2 descriptor table pool and cache 6136 */ 6137 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6138 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6139 pmap_l2ptp_ctor, NULL, NULL); 6140 6141 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6142 6143 cpu_dcache_wbinv_all(); 6144 } 6145 6146 static bool 6147 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6148 { 6149 #ifdef ARM_MMU_EXTENDED 6150 return false; 6151 #else 6152 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6153 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6154 return false; 6155 6156 const vaddr_t eva = va + nptes * PAGE_SIZE; 6157 int rv = 0; 6158 6159 while (va < eva) { 6160 /* 6161 * Make sure the descriptor itself has the correct cache mode 6162 */ 6163 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6164 pd_entry_t pde = *pdep; 6165 6166 if (l1pte_section_p(pde)) { 6167 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6168 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6169 *pdep = (pde & ~L1_S_CACHE_MASK) | 6170 pte_l1_s_cache_mode_pt; 6171 PDE_SYNC(pdep); 6172 cpu_dcache_wbinv_range((vaddr_t)pdep, 6173 sizeof(*pdep)); 6174 rv = 1; 6175 } 6176 return rv; 6177 if (pde & L1_S_V6_SUPER) { 6178 va = (va & -L1_SS_SIZE) + L1_SS_SIZE; 6179 } else { 6180 va = (va & -L1_S_SIZE) + L1_S_SIZE; 6181 } 6182 continue; 6183 } 6184 vaddr_t pa = l1pte_pa(pde); 6185 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6186 if (ptep == NULL) 6187 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6188 6189 ptep += l2pte_index(va); 6190 const pt_entry_t opte = *ptep; 6191 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6192 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6193 | pte_l2_s_cache_mode_pt; 6194 l2pte_set(ptep, npte, opte); 6195 PTE_SYNC(ptep); 6196 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6197 rv = 1; 6198 } 6199 va += PAGE_SIZE; 6200 } 6201 6202 return (rv); 6203 #endif 6204 } 6205 6206 static void 6207 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6208 { 6209 vaddr_t va = *availp; 6210 struct l2_bucket *l2b; 6211 6212 if (ptep) { 6213 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6214 if (l2b == NULL) 6215 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6216 6217 if (ptep) 6218 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6219 } 6220 6221 *vap = va; 6222 *availp = va + (PAGE_SIZE * pages); 6223 } 6224 6225 void 6226 pmap_init(void) 6227 { 6228 6229 /* 6230 * Set the available memory vars - These do not map to real memory 6231 * addresses and cannot as the physical memory is fragmented. 6232 * They are used by ps for %mem calculations. 6233 * One could argue whether this should be the entire memory or just 6234 * the memory that is useable in a user process. 6235 */ 6236 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6237 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6238 6239 /* 6240 * Now we need to free enough pv_entry structures to allow us to get 6241 * the kmem_map/kmem_object allocated and inited (done after this 6242 * function is finished). to do this we allocate one bootstrap page out 6243 * of kernel_map and use it to provide an initial pool of pv_entry 6244 * structures. we never free this page. 6245 */ 6246 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6247 6248 #ifdef ARM_MMU_EXTENDED 6249 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6250 #endif 6251 6252 pmap_initialized = true; 6253 } 6254 6255 static vaddr_t last_bootstrap_page = 0; 6256 static void *free_bootstrap_pages = NULL; 6257 6258 static void * 6259 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6260 { 6261 extern void *pool_page_alloc(struct pool *, int); 6262 vaddr_t new_page; 6263 void *rv; 6264 6265 if (pmap_initialized) 6266 return (pool_page_alloc(pp, flags)); 6267 6268 if (free_bootstrap_pages) { 6269 rv = free_bootstrap_pages; 6270 free_bootstrap_pages = *((void **)rv); 6271 return (rv); 6272 } 6273 6274 KASSERT(kernel_map != NULL); 6275 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6276 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6277 6278 KASSERT(new_page > last_bootstrap_page); 6279 last_bootstrap_page = new_page; 6280 return ((void *)new_page); 6281 } 6282 6283 static void 6284 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6285 { 6286 extern void pool_page_free(struct pool *, void *); 6287 6288 if ((vaddr_t)v <= last_bootstrap_page) { 6289 *((void **)v) = free_bootstrap_pages; 6290 free_bootstrap_pages = v; 6291 return; 6292 } 6293 6294 if (pmap_initialized) { 6295 pool_page_free(pp, v); 6296 return; 6297 } 6298 } 6299 6300 /* 6301 * pmap_postinit() 6302 * 6303 * This routine is called after the vm and kmem subsystems have been 6304 * initialised. This allows the pmap code to perform any initialisation 6305 * that can only be done one the memory allocation is in place. 6306 */ 6307 void 6308 pmap_postinit(void) 6309 { 6310 #ifndef ARM_MMU_EXTENDED 6311 extern paddr_t physical_start, physical_end; 6312 struct l1_ttable *l1; 6313 struct pglist plist; 6314 struct vm_page *m; 6315 pd_entry_t *pdep; 6316 vaddr_t va, eva; 6317 u_int loop, needed; 6318 int error; 6319 #endif 6320 6321 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6322 pool_cache_setlowat(&pmap_l2dtable_cache, 6323 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6324 6325 #ifndef ARM_MMU_EXTENDED 6326 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6327 needed -= 1; 6328 6329 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6330 6331 for (loop = 0; loop < needed; loop++, l1++) { 6332 /* Allocate a L1 page table */ 6333 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6334 if (va == 0) 6335 panic("Cannot allocate L1 KVM"); 6336 6337 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6338 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6339 if (error) 6340 panic("Cannot allocate L1 physical pages"); 6341 6342 m = TAILQ_FIRST(&plist); 6343 eva = va + L1_TABLE_SIZE; 6344 pdep = (pd_entry_t *)va; 6345 6346 while (m && va < eva) { 6347 paddr_t pa = VM_PAGE_TO_PHYS(m); 6348 6349 pmap_kenter_pa(va, pa, 6350 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6351 6352 va += PAGE_SIZE; 6353 m = TAILQ_NEXT(m, pageq.queue); 6354 } 6355 6356 #ifdef DIAGNOSTIC 6357 if (m) 6358 panic("pmap_alloc_l1pt: pglist not empty"); 6359 #endif /* DIAGNOSTIC */ 6360 6361 pmap_init_l1(l1, pdep); 6362 } 6363 6364 #ifdef DEBUG 6365 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6366 needed); 6367 #endif 6368 #endif /* !ARM_MMU_EXTENDED */ 6369 } 6370 6371 /* 6372 * Note that the following routines are used by board-specific initialisation 6373 * code to configure the initial kernel page tables. 6374 * 6375 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6376 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6377 * behaviour of the old pmap, and provides an easy migration path for 6378 * initial bring-up of the new pmap on existing ports. Fortunately, 6379 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6380 * will be deprecated. 6381 * 6382 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6383 * tables. 6384 */ 6385 6386 /* 6387 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6388 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6389 * find them as necessary. 6390 * 6391 * Note that the data on this list MUST remain valid after initarm() returns, 6392 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6393 */ 6394 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6395 6396 static vaddr_t 6397 kernel_pt_lookup(paddr_t pa) 6398 { 6399 pv_addr_t *pv; 6400 6401 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6402 if (pv->pv_pa == (pa & ~PGOFSET)) 6403 return (pv->pv_va | (pa & PGOFSET)); 6404 } 6405 return (0); 6406 } 6407 6408 /* 6409 * pmap_map_section: 6410 * 6411 * Create a single section mapping. 6412 */ 6413 void 6414 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6415 { 6416 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6417 const size_t l1slot = l1pte_index(va); 6418 pd_entry_t fl; 6419 6420 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6421 6422 switch (cache) { 6423 case PTE_NOCACHE: 6424 default: 6425 fl = 0; 6426 break; 6427 6428 case PTE_CACHE: 6429 fl = pte_l1_s_cache_mode; 6430 break; 6431 6432 case PTE_PAGETABLE: 6433 fl = pte_l1_s_cache_mode_pt; 6434 break; 6435 } 6436 6437 const pd_entry_t npde = L1_S_PROTO | pa | 6438 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6439 l1pte_setone(pdep + l1slot, npde); 6440 PDE_SYNC(pdep + l1slot); 6441 } 6442 6443 /* 6444 * pmap_map_entry: 6445 * 6446 * Create a single page mapping. 6447 */ 6448 void 6449 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6450 { 6451 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6452 const size_t l1slot = l1pte_index(va); 6453 pt_entry_t npte; 6454 pt_entry_t *ptep; 6455 6456 KASSERT(((va | pa) & PGOFSET) == 0); 6457 6458 switch (cache) { 6459 case PTE_NOCACHE: 6460 default: 6461 npte = 0; 6462 break; 6463 6464 case PTE_CACHE: 6465 npte = pte_l2_s_cache_mode; 6466 break; 6467 6468 case PTE_PAGETABLE: 6469 npte = pte_l2_s_cache_mode_pt; 6470 break; 6471 } 6472 6473 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6474 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6475 6476 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1pte_index(va)])); 6477 if (ptep == NULL) 6478 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6479 6480 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6481 #ifdef ARM_MMU_EXTENDED 6482 if (prot & VM_PROT_EXECUTE) { 6483 npte &= ~L2_XS_XN; 6484 } 6485 #endif 6486 ptep += l2pte_index(va); 6487 l2pte_set(ptep, npte, 0); 6488 PTE_SYNC(ptep); 6489 } 6490 6491 /* 6492 * pmap_link_l2pt: 6493 * 6494 * Link the L2 page table specified by "l2pv" into the L1 6495 * page table at the slot for "va". 6496 */ 6497 void 6498 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6499 { 6500 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6501 6502 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6503 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6504 6505 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6506 | l2pv->pv_pa; 6507 6508 l1pte_set(pdep, npde); 6509 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6510 6511 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6512 } 6513 6514 /* 6515 * pmap_map_chunk: 6516 * 6517 * Map a chunk of memory using the most efficient mappings 6518 * possible (section, large page, small page) into the 6519 * provided L1 and L2 tables at the specified virtual address. 6520 */ 6521 vsize_t 6522 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6523 int prot, int cache) 6524 { 6525 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6526 pt_entry_t f1, f2s, f2l; 6527 vsize_t resid; 6528 6529 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6530 6531 if (l1pt == 0) 6532 panic("pmap_map_chunk: no L1 table provided"); 6533 6534 #ifdef VERBOSE_INIT_ARM 6535 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6536 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6537 #endif 6538 6539 switch (cache) { 6540 case PTE_NOCACHE: 6541 default: 6542 f1 = 0; 6543 f2l = 0; 6544 f2s = 0; 6545 break; 6546 6547 case PTE_CACHE: 6548 f1 = pte_l1_s_cache_mode; 6549 f2l = pte_l2_l_cache_mode; 6550 f2s = pte_l2_s_cache_mode; 6551 break; 6552 6553 case PTE_PAGETABLE: 6554 f1 = pte_l1_s_cache_mode_pt; 6555 f2l = pte_l2_l_cache_mode_pt; 6556 f2s = pte_l2_s_cache_mode_pt; 6557 break; 6558 } 6559 6560 size = resid; 6561 6562 while (resid > 0) { 6563 const size_t l1slot = l1pte_index(va); 6564 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6565 /* See if we can use a supersection mapping. */ 6566 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6567 /* Supersection are always domain 0 */ 6568 const pd_entry_t npde = L1_SS_PROTO | pa 6569 #ifdef ARM_MMU_EXTENDED_XXX 6570 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6571 #endif 6572 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6573 #ifdef VERBOSE_INIT_ARM 6574 printf("sS"); 6575 #endif 6576 l1pte_set(&pdep[l1slot], npde); 6577 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6578 va += L1_SS_SIZE; 6579 pa += L1_SS_SIZE; 6580 resid -= L1_SS_SIZE; 6581 continue; 6582 } 6583 #endif 6584 /* See if we can use a section mapping. */ 6585 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6586 const pd_entry_t npde = L1_S_PROTO | pa 6587 #ifdef ARM_MMU_EXTENDED_XXX 6588 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6589 #endif 6590 | L1_S_PROT(PTE_KERNEL, prot) | f1 6591 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6592 #ifdef VERBOSE_INIT_ARM 6593 printf("S"); 6594 #endif 6595 l1pte_set(&pdep[l1slot], npde); 6596 PDE_SYNC(&pdep[l1slot]); 6597 va += L1_S_SIZE; 6598 pa += L1_S_SIZE; 6599 resid -= L1_S_SIZE; 6600 continue; 6601 } 6602 6603 /* 6604 * Ok, we're going to use an L2 table. Make sure 6605 * one is actually in the corresponding L1 slot 6606 * for the current VA. 6607 */ 6608 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6609 panic("%s: no L2 table for VA %#lx", __func__, va); 6610 6611 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6612 if (ptep == NULL) 6613 panic("%s: can't find L2 table for VA %#lx", __func__, 6614 va); 6615 6616 ptep += l2pte_index(va); 6617 6618 /* See if we can use a L2 large page mapping. */ 6619 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6620 const pt_entry_t npte = L2_L_PROTO | pa 6621 #ifdef ARM_MMU_EXTENDED_XXX 6622 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6623 #endif 6624 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6625 #ifdef VERBOSE_INIT_ARM 6626 printf("L"); 6627 #endif 6628 l2pte_set(ptep, npte, 0); 6629 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6630 va += L2_L_SIZE; 6631 pa += L2_L_SIZE; 6632 resid -= L2_L_SIZE; 6633 continue; 6634 } 6635 6636 /* Use a small page mapping. */ 6637 #ifdef VERBOSE_INIT_ARM 6638 printf("P"); 6639 #endif 6640 const pt_entry_t npte = L2_S_PROTO | pa 6641 #ifdef ARM_MMU_EXTENDED_XXX 6642 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6643 #endif 6644 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6645 l2pte_set(ptep, npte, 0); 6646 PTE_SYNC(ptep); 6647 va += PAGE_SIZE; 6648 pa += PAGE_SIZE; 6649 resid -= PAGE_SIZE; 6650 } 6651 #ifdef VERBOSE_INIT_ARM 6652 printf("\n"); 6653 #endif 6654 return (size); 6655 } 6656 6657 /********************** Static device map routines ***************************/ 6658 6659 static const struct pmap_devmap *pmap_devmap_table; 6660 6661 /* 6662 * Register the devmap table. This is provided in case early console 6663 * initialization needs to register mappings created by bootstrap code 6664 * before pmap_devmap_bootstrap() is called. 6665 */ 6666 void 6667 pmap_devmap_register(const struct pmap_devmap *table) 6668 { 6669 6670 pmap_devmap_table = table; 6671 } 6672 6673 /* 6674 * Map all of the static regions in the devmap table, and remember 6675 * the devmap table so other parts of the kernel can look up entries 6676 * later. 6677 */ 6678 void 6679 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6680 { 6681 int i; 6682 6683 pmap_devmap_table = table; 6684 6685 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6686 #ifdef VERBOSE_INIT_ARM 6687 printf("devmap: %08lx -> %08lx @ %08lx\n", 6688 pmap_devmap_table[i].pd_pa, 6689 pmap_devmap_table[i].pd_pa + 6690 pmap_devmap_table[i].pd_size - 1, 6691 pmap_devmap_table[i].pd_va); 6692 #endif 6693 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6694 pmap_devmap_table[i].pd_pa, 6695 pmap_devmap_table[i].pd_size, 6696 pmap_devmap_table[i].pd_prot, 6697 pmap_devmap_table[i].pd_cache); 6698 } 6699 } 6700 6701 const struct pmap_devmap * 6702 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6703 { 6704 uint64_t endpa; 6705 int i; 6706 6707 if (pmap_devmap_table == NULL) 6708 return (NULL); 6709 6710 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6711 6712 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6713 if (pa >= pmap_devmap_table[i].pd_pa && 6714 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6715 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6716 return (&pmap_devmap_table[i]); 6717 } 6718 6719 return (NULL); 6720 } 6721 6722 const struct pmap_devmap * 6723 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6724 { 6725 int i; 6726 6727 if (pmap_devmap_table == NULL) 6728 return (NULL); 6729 6730 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6731 if (va >= pmap_devmap_table[i].pd_va && 6732 va + size - 1 <= pmap_devmap_table[i].pd_va + 6733 pmap_devmap_table[i].pd_size - 1) 6734 return (&pmap_devmap_table[i]); 6735 } 6736 6737 return (NULL); 6738 } 6739 6740 /********************** PTE initialization routines **************************/ 6741 6742 /* 6743 * These routines are called when the CPU type is identified to set up 6744 * the PTE prototypes, cache modes, etc. 6745 * 6746 * The variables are always here, just in case modules need to reference 6747 * them (though, they shouldn't). 6748 */ 6749 6750 pt_entry_t pte_l1_s_cache_mode; 6751 pt_entry_t pte_l1_s_wc_mode; 6752 pt_entry_t pte_l1_s_cache_mode_pt; 6753 pt_entry_t pte_l1_s_cache_mask; 6754 6755 pt_entry_t pte_l2_l_cache_mode; 6756 pt_entry_t pte_l2_l_wc_mode; 6757 pt_entry_t pte_l2_l_cache_mode_pt; 6758 pt_entry_t pte_l2_l_cache_mask; 6759 6760 pt_entry_t pte_l2_s_cache_mode; 6761 pt_entry_t pte_l2_s_wc_mode; 6762 pt_entry_t pte_l2_s_cache_mode_pt; 6763 pt_entry_t pte_l2_s_cache_mask; 6764 6765 pt_entry_t pte_l1_s_prot_u; 6766 pt_entry_t pte_l1_s_prot_w; 6767 pt_entry_t pte_l1_s_prot_ro; 6768 pt_entry_t pte_l1_s_prot_mask; 6769 6770 pt_entry_t pte_l2_s_prot_u; 6771 pt_entry_t pte_l2_s_prot_w; 6772 pt_entry_t pte_l2_s_prot_ro; 6773 pt_entry_t pte_l2_s_prot_mask; 6774 6775 pt_entry_t pte_l2_l_prot_u; 6776 pt_entry_t pte_l2_l_prot_w; 6777 pt_entry_t pte_l2_l_prot_ro; 6778 pt_entry_t pte_l2_l_prot_mask; 6779 6780 pt_entry_t pte_l1_ss_proto; 6781 pt_entry_t pte_l1_s_proto; 6782 pt_entry_t pte_l1_c_proto; 6783 pt_entry_t pte_l2_s_proto; 6784 6785 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6786 void (*pmap_zero_page_func)(paddr_t); 6787 6788 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6789 void 6790 pmap_pte_init_generic(void) 6791 { 6792 6793 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6794 pte_l1_s_wc_mode = L1_S_B; 6795 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6796 6797 pte_l2_l_cache_mode = L2_B|L2_C; 6798 pte_l2_l_wc_mode = L2_B; 6799 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6800 6801 pte_l2_s_cache_mode = L2_B|L2_C; 6802 pte_l2_s_wc_mode = L2_B; 6803 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6804 6805 /* 6806 * If we have a write-through cache, set B and C. If 6807 * we have a write-back cache, then we assume setting 6808 * only C will make those pages write-through (except for those 6809 * Cortex CPUs which can read the L1 caches). 6810 */ 6811 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6812 #if ARM_MMU_V7 > 0 6813 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6814 #endif 6815 #if ARM_MMU_V6 > 0 6816 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6817 #endif 6818 || false) { 6819 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6820 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6821 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6822 } else { 6823 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6824 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6825 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6826 } 6827 6828 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6829 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6830 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6831 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6832 6833 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6834 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6835 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6836 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6837 6838 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6839 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6840 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6841 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6842 6843 pte_l1_ss_proto = L1_SS_PROTO_generic; 6844 pte_l1_s_proto = L1_S_PROTO_generic; 6845 pte_l1_c_proto = L1_C_PROTO_generic; 6846 pte_l2_s_proto = L2_S_PROTO_generic; 6847 6848 pmap_copy_page_func = pmap_copy_page_generic; 6849 pmap_zero_page_func = pmap_zero_page_generic; 6850 } 6851 6852 #if defined(CPU_ARM8) 6853 void 6854 pmap_pte_init_arm8(void) 6855 { 6856 6857 /* 6858 * ARM8 is compatible with generic, but we need to use 6859 * the page tables uncached. 6860 */ 6861 pmap_pte_init_generic(); 6862 6863 pte_l1_s_cache_mode_pt = 0; 6864 pte_l2_l_cache_mode_pt = 0; 6865 pte_l2_s_cache_mode_pt = 0; 6866 } 6867 #endif /* CPU_ARM8 */ 6868 6869 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6870 void 6871 pmap_pte_init_arm9(void) 6872 { 6873 6874 /* 6875 * ARM9 is compatible with generic, but we want to use 6876 * write-through caching for now. 6877 */ 6878 pmap_pte_init_generic(); 6879 6880 pte_l1_s_cache_mode = L1_S_C; 6881 pte_l2_l_cache_mode = L2_C; 6882 pte_l2_s_cache_mode = L2_C; 6883 6884 pte_l1_s_wc_mode = L1_S_B; 6885 pte_l2_l_wc_mode = L2_B; 6886 pte_l2_s_wc_mode = L2_B; 6887 6888 pte_l1_s_cache_mode_pt = L1_S_C; 6889 pte_l2_l_cache_mode_pt = L2_C; 6890 pte_l2_s_cache_mode_pt = L2_C; 6891 } 6892 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6893 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6894 6895 #if defined(CPU_ARM10) 6896 void 6897 pmap_pte_init_arm10(void) 6898 { 6899 6900 /* 6901 * ARM10 is compatible with generic, but we want to use 6902 * write-through caching for now. 6903 */ 6904 pmap_pte_init_generic(); 6905 6906 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6907 pte_l2_l_cache_mode = L2_B | L2_C; 6908 pte_l2_s_cache_mode = L2_B | L2_C; 6909 6910 pte_l1_s_cache_mode = L1_S_B; 6911 pte_l2_l_cache_mode = L2_B; 6912 pte_l2_s_cache_mode = L2_B; 6913 6914 pte_l1_s_cache_mode_pt = L1_S_C; 6915 pte_l2_l_cache_mode_pt = L2_C; 6916 pte_l2_s_cache_mode_pt = L2_C; 6917 6918 } 6919 #endif /* CPU_ARM10 */ 6920 6921 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6922 void 6923 pmap_pte_init_arm11(void) 6924 { 6925 6926 /* 6927 * ARM11 is compatible with generic, but we want to use 6928 * write-through caching for now. 6929 */ 6930 pmap_pte_init_generic(); 6931 6932 pte_l1_s_cache_mode = L1_S_C; 6933 pte_l2_l_cache_mode = L2_C; 6934 pte_l2_s_cache_mode = L2_C; 6935 6936 pte_l1_s_wc_mode = L1_S_B; 6937 pte_l2_l_wc_mode = L2_B; 6938 pte_l2_s_wc_mode = L2_B; 6939 6940 pte_l1_s_cache_mode_pt = L1_S_C; 6941 pte_l2_l_cache_mode_pt = L2_C; 6942 pte_l2_s_cache_mode_pt = L2_C; 6943 } 6944 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6945 6946 #if ARM_MMU_SA1 == 1 6947 void 6948 pmap_pte_init_sa1(void) 6949 { 6950 6951 /* 6952 * The StrongARM SA-1 cache does not have a write-through 6953 * mode. So, do the generic initialization, then reset 6954 * the page table cache mode to B=1,C=1, and note that 6955 * the PTEs need to be sync'd. 6956 */ 6957 pmap_pte_init_generic(); 6958 6959 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6960 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6961 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6962 6963 pmap_needs_pte_sync = 1; 6964 } 6965 #endif /* ARM_MMU_SA1 == 1*/ 6966 6967 #if ARM_MMU_XSCALE == 1 6968 #if (ARM_NMMUS > 1) 6969 static u_int xscale_use_minidata; 6970 #endif 6971 6972 void 6973 pmap_pte_init_xscale(void) 6974 { 6975 uint32_t auxctl; 6976 int write_through = 0; 6977 6978 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6979 pte_l1_s_wc_mode = L1_S_B; 6980 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6981 6982 pte_l2_l_cache_mode = L2_B|L2_C; 6983 pte_l2_l_wc_mode = L2_B; 6984 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6985 6986 pte_l2_s_cache_mode = L2_B|L2_C; 6987 pte_l2_s_wc_mode = L2_B; 6988 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6989 6990 pte_l1_s_cache_mode_pt = L1_S_C; 6991 pte_l2_l_cache_mode_pt = L2_C; 6992 pte_l2_s_cache_mode_pt = L2_C; 6993 6994 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6995 /* 6996 * The XScale core has an enhanced mode where writes that 6997 * miss the cache cause a cache line to be allocated. This 6998 * is significantly faster than the traditional, write-through 6999 * behavior of this case. 7000 */ 7001 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7002 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7003 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7004 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7005 7006 #ifdef XSCALE_CACHE_WRITE_THROUGH 7007 /* 7008 * Some versions of the XScale core have various bugs in 7009 * their cache units, the work-around for which is to run 7010 * the cache in write-through mode. Unfortunately, this 7011 * has a major (negative) impact on performance. So, we 7012 * go ahead and run fast-and-loose, in the hopes that we 7013 * don't line up the planets in a way that will trip the 7014 * bugs. 7015 * 7016 * However, we give you the option to be slow-but-correct. 7017 */ 7018 write_through = 1; 7019 #elif defined(XSCALE_CACHE_WRITE_BACK) 7020 /* force write back cache mode */ 7021 write_through = 0; 7022 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7023 /* 7024 * Intel PXA2[15]0 processors are known to have a bug in 7025 * write-back cache on revision 4 and earlier (stepping 7026 * A[01] and B[012]). Fixed for C0 and later. 7027 */ 7028 { 7029 uint32_t id, type; 7030 7031 id = cpufunc_id(); 7032 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7033 7034 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7035 if ((id & CPU_ID_REVISION_MASK) < 5) { 7036 /* write through for stepping A0-1 and B0-2 */ 7037 write_through = 1; 7038 } 7039 } 7040 } 7041 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7042 7043 if (write_through) { 7044 pte_l1_s_cache_mode = L1_S_C; 7045 pte_l2_l_cache_mode = L2_C; 7046 pte_l2_s_cache_mode = L2_C; 7047 } 7048 7049 #if (ARM_NMMUS > 1) 7050 xscale_use_minidata = 1; 7051 #endif 7052 7053 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7054 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7055 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7056 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7057 7058 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7059 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7060 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7061 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7062 7063 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7064 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7065 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7066 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7067 7068 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7069 pte_l1_s_proto = L1_S_PROTO_xscale; 7070 pte_l1_c_proto = L1_C_PROTO_xscale; 7071 pte_l2_s_proto = L2_S_PROTO_xscale; 7072 7073 pmap_copy_page_func = pmap_copy_page_xscale; 7074 pmap_zero_page_func = pmap_zero_page_xscale; 7075 7076 /* 7077 * Disable ECC protection of page table access, for now. 7078 */ 7079 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7080 auxctl &= ~XSCALE_AUXCTL_P; 7081 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7082 } 7083 7084 /* 7085 * xscale_setup_minidata: 7086 * 7087 * Set up the mini-data cache clean area. We require the 7088 * caller to allocate the right amount of physically and 7089 * virtually contiguous space. 7090 */ 7091 void 7092 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7093 { 7094 extern vaddr_t xscale_minidata_clean_addr; 7095 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7096 pd_entry_t *pde = (pd_entry_t *) l1pt; 7097 vsize_t size; 7098 uint32_t auxctl; 7099 7100 xscale_minidata_clean_addr = va; 7101 7102 /* Round it to page size. */ 7103 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7104 7105 for (; size != 0; 7106 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7107 const size_t l1slot = l1pte_index(va); 7108 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7109 if (ptep == NULL) 7110 panic("xscale_setup_minidata: can't find L2 table for " 7111 "VA 0x%08lx", va); 7112 7113 ptep += l2pte_index(va); 7114 pt_entry_t opte = *ptep; 7115 l2pte_set(ptep, 7116 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7117 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7118 } 7119 7120 /* 7121 * Configure the mini-data cache for write-back with 7122 * read/write-allocate. 7123 * 7124 * NOTE: In order to reconfigure the mini-data cache, we must 7125 * make sure it contains no valid data! In order to do that, 7126 * we must issue a global data cache invalidate command! 7127 * 7128 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7129 * THIS IS VERY IMPORTANT! 7130 */ 7131 7132 /* Invalidate data and mini-data. */ 7133 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7134 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7135 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7136 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7137 } 7138 7139 /* 7140 * Change the PTEs for the specified kernel mappings such that they 7141 * will use the mini data cache instead of the main data cache. 7142 */ 7143 void 7144 pmap_uarea(vaddr_t va) 7145 { 7146 vaddr_t next_bucket, eva; 7147 7148 #if (ARM_NMMUS > 1) 7149 if (xscale_use_minidata == 0) 7150 return; 7151 #endif 7152 7153 eva = va + USPACE; 7154 7155 while (va < eva) { 7156 next_bucket = L2_NEXT_BUCKET_VA(va); 7157 if (next_bucket > eva) 7158 next_bucket = eva; 7159 7160 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7161 KDASSERT(l2b != NULL); 7162 7163 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7164 pt_entry_t *ptep = sptep; 7165 7166 while (va < next_bucket) { 7167 const pt_entry_t opte = *ptep; 7168 if (!l2pte_minidata_p(opte)) { 7169 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7170 cpu_tlb_flushD_SE(va); 7171 l2pte_set(ptep, opte & ~L2_B, opte); 7172 } 7173 ptep += PAGE_SIZE / L2_S_SIZE; 7174 va += PAGE_SIZE; 7175 } 7176 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7177 } 7178 cpu_cpwait(); 7179 } 7180 #endif /* ARM_MMU_XSCALE == 1 */ 7181 7182 7183 #if defined(CPU_ARM11MPCORE) 7184 7185 void 7186 pmap_pte_init_arm11mpcore(void) 7187 { 7188 7189 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7190 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7191 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7192 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7193 /* use extended small page (without APn, with TEX) */ 7194 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7195 #else 7196 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7197 #endif 7198 7199 /* write-back, write-allocate */ 7200 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7201 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7202 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7203 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7204 #else 7205 /* no TEX. read-allocate */ 7206 pte_l2_s_cache_mode = L2_C | L2_B; 7207 #endif 7208 /* 7209 * write-back, write-allocate for page tables. 7210 */ 7211 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7212 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7213 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7214 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7215 #else 7216 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7217 #endif 7218 7219 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7220 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7221 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7222 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7223 7224 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7225 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7226 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7227 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7228 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7229 7230 #else 7231 /* with AP[0..3] */ 7232 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7233 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7234 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7235 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7236 #endif 7237 7238 #ifdef ARM11MPCORE_COMPAT_MMU 7239 /* with AP[0..3] */ 7240 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7241 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7242 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7243 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7244 7245 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7246 pte_l1_s_proto = L1_S_PROTO_armv6; 7247 pte_l1_c_proto = L1_C_PROTO_armv6; 7248 pte_l2_s_proto = L2_S_PROTO_armv6c; 7249 #else 7250 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7251 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7252 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7253 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7254 7255 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7256 pte_l1_s_proto = L1_S_PROTO_armv6; 7257 pte_l1_c_proto = L1_C_PROTO_armv6; 7258 pte_l2_s_proto = L2_S_PROTO_armv6n; 7259 #endif 7260 7261 pmap_copy_page_func = pmap_copy_page_generic; 7262 pmap_zero_page_func = pmap_zero_page_generic; 7263 pmap_needs_pte_sync = 1; 7264 } 7265 #endif /* CPU_ARM11MPCORE */ 7266 7267 7268 #if ARM_MMU_V7 == 1 7269 void 7270 pmap_pte_init_armv7(void) 7271 { 7272 /* 7273 * The ARMv7-A MMU is mostly compatible with generic. If the 7274 * AP field is zero, that now means "no access" rather than 7275 * read-only. The prototypes are a little different because of 7276 * the XN bit. 7277 */ 7278 pmap_pte_init_generic(); 7279 7280 pmap_needs_pte_sync = 1; 7281 7282 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7283 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7284 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7285 7286 /* 7287 * If the core support coherent walk then updates to translation tables 7288 * do not require a clean to the point of unification to ensure 7289 * visibility by subsequent translation table walks. That means we can 7290 * map everything shareable and cached and the right thing will happen. 7291 */ 7292 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7293 pmap_needs_pte_sync = 0; 7294 7295 /* 7296 * write-back, no write-allocate, shareable for normal pages. 7297 */ 7298 pte_l1_s_cache_mode |= L1_S_V6_S; 7299 pte_l2_l_cache_mode |= L2_XS_S; 7300 pte_l2_s_cache_mode |= L2_XS_S; 7301 7302 /* 7303 * write-back, no write-allocate, shareable for page tables. 7304 */ 7305 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7306 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7307 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7308 } 7309 7310 /* 7311 * Check the Memory Model Features to see if this CPU supports 7312 * the TLBIASID coproc op. 7313 */ 7314 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7315 arm_has_tlbiasid_p = true; 7316 } 7317 7318 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7319 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7320 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7321 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7322 7323 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7324 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7325 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7326 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7327 7328 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7329 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7330 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7331 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7332 7333 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7334 pte_l1_s_proto = L1_S_PROTO_armv7; 7335 pte_l1_c_proto = L1_C_PROTO_armv7; 7336 pte_l2_s_proto = L2_S_PROTO_armv7; 7337 7338 } 7339 #endif /* ARM_MMU_V7 */ 7340 7341 /* 7342 * return the PA of the current L1 table, for use when handling a crash dump 7343 */ 7344 uint32_t 7345 pmap_kernel_L1_addr(void) 7346 { 7347 #ifdef ARM_MMU_EXTENDED 7348 return pmap_kernel()->pm_l1_pa; 7349 #else 7350 return pmap_kernel()->pm_l1->l1_physaddr; 7351 #endif 7352 } 7353 7354 #if defined(DDB) 7355 /* 7356 * A couple of ddb-callable functions for dumping pmaps 7357 */ 7358 void pmap_dump_all(void); 7359 void pmap_dump(pmap_t); 7360 7361 void 7362 pmap_dump_all(void) 7363 { 7364 pmap_t pm; 7365 7366 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7367 if (pm == pmap_kernel()) 7368 continue; 7369 pmap_dump(pm); 7370 printf("\n"); 7371 } 7372 } 7373 7374 static pt_entry_t ncptes[64]; 7375 static void pmap_dump_ncpg(pmap_t); 7376 7377 void 7378 pmap_dump(pmap_t pm) 7379 { 7380 struct l2_dtable *l2; 7381 struct l2_bucket *l2b; 7382 pt_entry_t *ptep, pte; 7383 vaddr_t l2_va, l2b_va, va; 7384 int i, j, k, occ, rows = 0; 7385 7386 if (pm == pmap_kernel()) 7387 printf("pmap_kernel (%p): ", pm); 7388 else 7389 printf("user pmap (%p): ", pm); 7390 7391 #ifdef ARM_MMU_EXTENDED 7392 printf("l1 at %p\n", pmap_l1_kva(pm)); 7393 #else 7394 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7395 #endif 7396 7397 l2_va = 0; 7398 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7399 l2 = pm->pm_l2[i]; 7400 7401 if (l2 == NULL || l2->l2_occupancy == 0) 7402 continue; 7403 7404 l2b_va = l2_va; 7405 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7406 l2b = &l2->l2_bucket[j]; 7407 7408 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7409 continue; 7410 7411 ptep = l2b->l2b_kva; 7412 7413 for (k = 0; k < 256 && ptep[k] == 0; k++) 7414 ; 7415 7416 k &= ~63; 7417 occ = l2b->l2b_occupancy; 7418 va = l2b_va + (k * 4096); 7419 for (; k < 256; k++, va += 0x1000) { 7420 char ch = ' '; 7421 if ((k % 64) == 0) { 7422 if ((rows % 8) == 0) { 7423 printf( 7424 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7425 } 7426 printf("%08lx: ", va); 7427 } 7428 7429 ncptes[k & 63] = 0; 7430 pte = ptep[k]; 7431 if (pte == 0) { 7432 ch = '.'; 7433 } else { 7434 occ--; 7435 switch (pte & 0x0c) { 7436 case 0x00: 7437 ch = 'D'; /* No cache No buff */ 7438 break; 7439 case 0x04: 7440 ch = 'B'; /* No cache buff */ 7441 break; 7442 case 0x08: 7443 if (pte & 0x40) 7444 ch = 'm'; 7445 else 7446 ch = 'C'; /* Cache No buff */ 7447 break; 7448 case 0x0c: 7449 ch = 'F'; /* Cache Buff */ 7450 break; 7451 } 7452 7453 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7454 ch += 0x20; 7455 7456 if ((pte & 0xc) == 0) 7457 ncptes[k & 63] = pte; 7458 } 7459 7460 if ((k % 64) == 63) { 7461 rows++; 7462 printf("%c\n", ch); 7463 pmap_dump_ncpg(pm); 7464 if (occ == 0) 7465 break; 7466 } else 7467 printf("%c", ch); 7468 } 7469 } 7470 } 7471 } 7472 7473 static void 7474 pmap_dump_ncpg(pmap_t pm) 7475 { 7476 struct vm_page *pg; 7477 struct vm_page_md *md; 7478 struct pv_entry *pv; 7479 int i; 7480 7481 for (i = 0; i < 63; i++) { 7482 if (ncptes[i] == 0) 7483 continue; 7484 7485 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7486 if (pg == NULL) 7487 continue; 7488 md = VM_PAGE_TO_MD(pg); 7489 7490 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7491 VM_PAGE_TO_PHYS(pg), 7492 md->krw_mappings, md->kro_mappings, 7493 md->urw_mappings, md->uro_mappings); 7494 7495 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7496 printf(" %c va 0x%08lx, flags 0x%x\n", 7497 (pm == pv->pv_pmap) ? '*' : ' ', 7498 pv->pv_va, pv->pv_flags); 7499 } 7500 } 7501 } 7502 #endif 7503 7504 #ifdef PMAP_STEAL_MEMORY 7505 void 7506 pmap_boot_pageadd(pv_addr_t *newpv) 7507 { 7508 pv_addr_t *pv, *npv; 7509 7510 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7511 if (newpv->pv_pa < pv->pv_va) { 7512 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7513 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7514 newpv->pv_size += pv->pv_size; 7515 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7516 } 7517 pv = NULL; 7518 } else { 7519 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7520 pv = npv) { 7521 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7522 KASSERT(pv->pv_pa < newpv->pv_pa); 7523 if (newpv->pv_pa > npv->pv_pa) 7524 continue; 7525 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7526 pv->pv_size += newpv->pv_size; 7527 return; 7528 } 7529 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7530 break; 7531 newpv->pv_size += npv->pv_size; 7532 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7533 SLIST_REMOVE_AFTER(newpv, pv_list); 7534 return; 7535 } 7536 } 7537 } 7538 7539 if (pv) { 7540 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7541 } else { 7542 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7543 } 7544 } 7545 7546 void 7547 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7548 pv_addr_t *rpv) 7549 { 7550 pv_addr_t *pv, **pvp; 7551 struct vm_physseg *ps; 7552 size_t i; 7553 7554 KASSERT(amount & PGOFSET); 7555 KASSERT((mask & PGOFSET) == 0); 7556 KASSERT((match & PGOFSET) == 0); 7557 KASSERT(amount != 0); 7558 7559 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7560 (pv = *pvp) != NULL; 7561 pvp = &SLIST_NEXT(pv, pv_list)) { 7562 pv_addr_t *newpv; 7563 psize_t off; 7564 /* 7565 * If this entry is too small to satify the request... 7566 */ 7567 KASSERT(pv->pv_size > 0); 7568 if (pv->pv_size < amount) 7569 continue; 7570 7571 for (off = 0; off <= mask; off += PAGE_SIZE) { 7572 if (((pv->pv_pa + off) & mask) == match 7573 && off + amount <= pv->pv_size) 7574 break; 7575 } 7576 if (off > mask) 7577 continue; 7578 7579 rpv->pv_va = pv->pv_va + off; 7580 rpv->pv_pa = pv->pv_pa + off; 7581 rpv->pv_size = amount; 7582 pv->pv_size -= amount; 7583 if (pv->pv_size == 0) { 7584 KASSERT(off == 0); 7585 KASSERT((vaddr_t) pv == rpv->pv_va); 7586 *pvp = SLIST_NEXT(pv, pv_list); 7587 } else if (off == 0) { 7588 KASSERT((vaddr_t) pv == rpv->pv_va); 7589 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7590 *newpv = *pv; 7591 newpv->pv_pa += amount; 7592 newpv->pv_va += amount; 7593 *pvp = newpv; 7594 } else if (off < pv->pv_size) { 7595 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7596 *newpv = *pv; 7597 newpv->pv_size -= off; 7598 newpv->pv_pa += off + amount; 7599 newpv->pv_va += off + amount; 7600 7601 SLIST_NEXT(pv, pv_list) = newpv; 7602 pv->pv_size = off; 7603 } else { 7604 KASSERT((vaddr_t) pv != rpv->pv_va); 7605 } 7606 memset((void *)rpv->pv_va, 0, amount); 7607 return; 7608 } 7609 7610 if (vm_nphysseg == 0) 7611 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7612 7613 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7614 (pv = *pvp) != NULL; 7615 pvp = &SLIST_NEXT(pv, pv_list)) { 7616 if (SLIST_NEXT(pv, pv_list) == NULL) 7617 break; 7618 } 7619 KASSERT(mask == 0); 7620 for (i = 0; i < vm_nphysseg; i++) { 7621 ps = VM_PHYSMEM_PTR(i); 7622 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7623 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7624 rpv->pv_va = pv->pv_va; 7625 rpv->pv_pa = pv->pv_pa; 7626 rpv->pv_size = amount; 7627 *pvp = NULL; 7628 pmap_map_chunk(kernel_l1pt.pv_va, 7629 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7630 ptoa(ps->avail_start), 7631 amount - pv->pv_size, 7632 VM_PROT_READ|VM_PROT_WRITE, 7633 PTE_CACHE); 7634 ps->avail_start += atop(amount - pv->pv_size); 7635 /* 7636 * If we consumed the entire physseg, remove it. 7637 */ 7638 if (ps->avail_start == ps->avail_end) { 7639 for (--vm_nphysseg; i < vm_nphysseg; i++) 7640 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7641 } 7642 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7643 return; 7644 } 7645 } 7646 7647 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7648 } 7649 7650 vaddr_t 7651 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7652 { 7653 pv_addr_t pv; 7654 7655 pmap_boot_pagealloc(size, 0, 0, &pv); 7656 7657 return pv.pv_va; 7658 } 7659 #endif /* PMAP_STEAL_MEMORY */ 7660 7661 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7662 { 7663 sysctl_createv(clog, 0, NULL, NULL, 7664 CTLFLAG_PERMANENT, 7665 CTLTYPE_NODE, "machdep", NULL, 7666 NULL, 0, NULL, 0, 7667 CTL_MACHDEP, CTL_EOL); 7668 7669 sysctl_createv(clog, 0, NULL, NULL, 7670 CTLFLAG_PERMANENT, 7671 CTLTYPE_INT, "kmpages", 7672 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7673 NULL, 0, &pmap_kmpages, 0, 7674 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7675 } 7676 7677 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7678 struct vm_page * 7679 arm_pmap_alloc_poolpage(int flags) 7680 { 7681 /* 7682 * On some systems, only some pages may be "coherent" for dma and we 7683 * want to prefer those for pool pages (think mbufs) but fallback to 7684 * any page if none is available. 7685 */ 7686 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7687 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7688 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 7689 } 7690 7691 return uvm_pagealloc(NULL, 0, NULL, flags); 7692 } 7693 #endif 7694 7695 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7696 void 7697 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7698 { 7699 /* nothing */ 7700 } 7701 7702 int 7703 pic_ipi_shootdown(void *arg) 7704 { 7705 #if PMAP_NEED_TLB_SHOOTDOWN 7706 pmap_tlb_shootdown_process() 7707 #endif 7708 return 1; 7709 } 7710 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7711
Indexes created Mon Sep 29 03:10:08 GMT 2025