pmap.c revision 1.280
1 /* $NetBSD: pmap.c,v 1.280 2014/04/02 15:45:51 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 //#include <arm/arm32/katelib.h> 218 219 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.280 2014/04/02 15:45:51 matt Exp $"); 220 221 //#define PMAP_DEBUG 222 #ifdef PMAP_DEBUG 223 224 /* XXX need to get rid of all refs to this */ 225 int pmap_debug_level = 0; 226 227 /* 228 * for switching to potentially finer grained debugging 229 */ 230 #define PDB_FOLLOW 0x0001 231 #define PDB_INIT 0x0002 232 #define PDB_ENTER 0x0004 233 #define PDB_REMOVE 0x0008 234 #define PDB_CREATE 0x0010 235 #define PDB_PTPAGE 0x0020 236 #define PDB_GROWKERN 0x0040 237 #define PDB_BITS 0x0080 238 #define PDB_COLLECT 0x0100 239 #define PDB_PROTECT 0x0200 240 #define PDB_MAP_L1 0x0400 241 #define PDB_BOOTSTRAP 0x1000 242 #define PDB_PARANOIA 0x2000 243 #define PDB_WIRING 0x4000 244 #define PDB_PVDUMP 0x8000 245 #define PDB_VAC 0x10000 246 #define PDB_KENTER 0x20000 247 #define PDB_KREMOVE 0x40000 248 #define PDB_EXEC 0x80000 249 250 int debugmap = 1; 251 int pmapdebug = 0; 252 #define NPDEBUG(_lev_,_stat_) \ 253 if (pmapdebug & (_lev_)) \ 254 ((_stat_)) 255 256 #else /* PMAP_DEBUG */ 257 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 258 #endif /* PMAP_DEBUG */ 259 260 /* 261 * pmap_kernel() points here 262 */ 263 static struct pmap kernel_pmap_store = { 264 #ifndef ARM_MMU_EXTENDED 265 .pm_activated = true, 266 .pm_domain = PMAP_DOMAIN_KERNEL, 267 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 268 #endif 269 }; 270 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 271 #undef pmap_kernel 272 #define pmap_kernel() (&kernel_pmap_store) 273 #ifdef PMAP_NEED_ALLOC_POOLPAGE 274 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 275 #endif 276 277 /* 278 * Pool and cache that pmap structures are allocated from. 279 * We use a cache to avoid clearing the pm_l2[] array (1KB) 280 * in pmap_create(). 281 */ 282 static struct pool_cache pmap_cache; 283 static LIST_HEAD(, pmap) pmap_pmaps; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 static struct evcnt pmap_ev_exec_synced_map = 426 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 427 #ifndef ARM_MMU_EXTENDED 428 static struct evcnt pmap_ev_exec_synced_unmap = 429 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 430 static struct evcnt pmap_ev_exec_synced_remap = 431 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 432 static struct evcnt pmap_ev_exec_synced_clearbit = 433 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 440 #ifndef ARM_MMU_EXTENDED 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 /* 489 * pmap copy/zero page, and mem(5) hook point 490 */ 491 static pt_entry_t *csrc_pte, *cdst_pte; 492 static vaddr_t csrcp, cdstp; 493 #ifdef MULTIPROCESSOR 494 static size_t cnptes; 495 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 497 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 499 #else 500 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + (o)) 503 #define cpu_cdstp(o) (cdstp + (o)) 504 #endif 505 vaddr_t memhook; /* used by mem.c & others */ 506 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 507 kmutex_t pmap_lock __cacheline_aligned; 508 extern void *msgbufaddr; 509 int pmap_kmpages; 510 /* 511 * Flag to indicate if pmap_init() has done its thing 512 */ 513 bool pmap_initialized; 514 515 /* 516 * Misc. locking data structures 517 */ 518 519 static inline void 520 pmap_acquire_pmap_lock(pmap_t pm) 521 { 522 if (pm == pmap_kernel()) { 523 #ifdef MULTIPROCESSOR 524 KERNEL_LOCK(1, NULL); 525 #endif 526 } else { 527 mutex_enter(pm->pm_lock); 528 } 529 } 530 531 static inline void 532 pmap_release_pmap_lock(pmap_t pm) 533 { 534 if (pm == pmap_kernel()) { 535 #ifdef MULTIPROCESSOR 536 KERNEL_UNLOCK_ONE(NULL); 537 #endif 538 } else { 539 mutex_exit(pm->pm_lock); 540 } 541 } 542 543 static inline void 544 pmap_acquire_page_lock(struct vm_page_md *md) 545 { 546 mutex_enter(&pmap_lock); 547 } 548 549 static inline void 550 pmap_release_page_lock(struct vm_page_md *md) 551 { 552 mutex_exit(&pmap_lock); 553 } 554 555 #ifdef DIAGNOSTIC 556 static inline int 557 pmap_page_locked_p(struct vm_page_md *md) 558 { 559 return mutex_owned(&pmap_lock); 560 } 561 #endif 562 563 564 /* 565 * Metadata for L1 translation tables. 566 */ 567 #ifndef ARM_MMU_EXTENDED 568 struct l1_ttable { 569 /* Entry on the L1 Table list */ 570 SLIST_ENTRY(l1_ttable) l1_link; 571 572 /* Entry on the L1 Least Recently Used list */ 573 TAILQ_ENTRY(l1_ttable) l1_lru; 574 575 /* Track how many domains are allocated from this L1 */ 576 volatile u_int l1_domain_use_count; 577 578 /* 579 * A free-list of domain numbers for this L1. 580 * We avoid using ffs() and a bitmap to track domains since ffs() 581 * is slow on ARM. 582 */ 583 uint8_t l1_domain_first; 584 uint8_t l1_domain_free[PMAP_DOMAINS]; 585 586 /* Physical address of this L1 page table */ 587 paddr_t l1_physaddr; 588 589 /* KVA of this L1 page table */ 590 pd_entry_t *l1_kva; 591 }; 592 593 /* 594 * L1 Page Tables are tracked using a Least Recently Used list. 595 * - New L1s are allocated from the HEAD. 596 * - Freed L1s are added to the TAIl. 597 * - Recently accessed L1s (where an 'access' is some change to one of 598 * the userland pmaps which owns this L1) are moved to the TAIL. 599 */ 600 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 601 static kmutex_t l1_lru_lock __cacheline_aligned; 602 603 /* 604 * A list of all L1 tables 605 */ 606 static SLIST_HEAD(, l1_ttable) l1_list; 607 #endif /* ARM_MMU_EXTENDED */ 608 609 /* 610 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 611 * 612 * This is normally 16MB worth L2 page descriptors for any given pmap. 613 * Reference counts are maintained for L2 descriptors so they can be 614 * freed when empty. 615 */ 616 struct l2_dtable { 617 /* The number of L2 page descriptors allocated to this l2_dtable */ 618 u_int l2_occupancy; 619 620 /* List of L2 page descriptors */ 621 struct l2_bucket { 622 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 623 paddr_t l2b_pa; /* Physical address of same */ 624 u_short l2b_l1slot; /* This L2 table's L1 index */ 625 u_short l2b_occupancy; /* How many active descriptors */ 626 } l2_bucket[L2_BUCKET_SIZE]; 627 }; 628 629 /* 630 * Given an L1 table index, calculate the corresponding l2_dtable index 631 * and bucket index within the l2_dtable. 632 */ 633 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 634 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 635 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 636 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 637 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 638 639 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 640 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 641 642 /* 643 * Given a virtual address, this macro returns the 644 * virtual address required to drop into the next L2 bucket. 645 */ 646 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 647 648 /* 649 * L2 allocation. 650 */ 651 #define pmap_alloc_l2_dtable() \ 652 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 653 #define pmap_free_l2_dtable(l2) \ 654 pool_cache_put(&pmap_l2dtable_cache, (l2)) 655 #define pmap_alloc_l2_ptp(pap) \ 656 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 657 PR_NOWAIT, (pap))) 658 659 /* 660 * We try to map the page tables write-through, if possible. However, not 661 * all CPUs have a write-through cache mode, so on those we have to sync 662 * the cache when we frob page tables. 663 * 664 * We try to evaluate this at compile time, if possible. However, it's 665 * not always possible to do that, hence this run-time var. 666 */ 667 int pmap_needs_pte_sync; 668 669 /* 670 * Real definition of pv_entry. 671 */ 672 struct pv_entry { 673 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 674 pmap_t pv_pmap; /* pmap where mapping lies */ 675 vaddr_t pv_va; /* virtual address for mapping */ 676 u_int pv_flags; /* flags */ 677 }; 678 679 /* 680 * Macro to determine if a mapping might be resident in the 681 * instruction cache and/or TLB 682 */ 683 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 684 /* 685 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 686 * there are no explicit accesses, so there may be always be TLB entries to 687 * flush. If we used ASIDs then this would not be a problem. 688 */ 689 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 690 #else 691 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 692 #endif 693 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 694 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 695 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 696 697 /* 698 * Macro to determine if a mapping might be resident in the 699 * data cache and/or TLB 700 */ 701 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 702 /* 703 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 704 * there are no explicit accesses, so there may be always be TLB entries to 705 * flush. If we used ASIDs then this would not be a problem. 706 */ 707 #define PV_BEEN_REFD(f) (1) 708 #else 709 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 710 #endif 711 712 /* 713 * Local prototypes 714 */ 715 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 716 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 717 pt_entry_t **); 718 static bool pmap_is_current(pmap_t); 719 static bool pmap_is_cached(pmap_t); 720 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 721 pmap_t, vaddr_t, u_int); 722 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 723 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 724 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 725 u_int, u_int); 726 727 static void pmap_pinit(pmap_t); 728 static int pmap_pmap_ctor(void *, void *, int); 729 730 static void pmap_alloc_l1(pmap_t); 731 static void pmap_free_l1(pmap_t); 732 #ifndef ARM_MMU_EXTENDED 733 static void pmap_use_l1(pmap_t); 734 #endif 735 736 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 737 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 738 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 739 static int pmap_l2ptp_ctor(void *, void *, int); 740 static int pmap_l2dtable_ctor(void *, void *, int); 741 742 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 743 #ifdef PMAP_CACHE_VIVT 744 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 745 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 746 #endif 747 748 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 749 #ifdef PMAP_CACHE_VIVT 750 static bool pmap_clean_page(struct vm_page_md *, bool); 751 #endif 752 #ifdef PMAP_CACHE_VIPT 753 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 754 enum pmap_flush_op { 755 PMAP_FLUSH_PRIMARY, 756 PMAP_FLUSH_SECONDARY, 757 PMAP_CLEAN_PRIMARY 758 }; 759 #ifndef ARM_MMU_EXTENDED 760 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 761 #endif 762 #endif 763 static void pmap_page_remove(struct vm_page_md *, paddr_t); 764 765 #ifndef ARM_MMU_EXTENDED 766 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 767 #endif 768 static vaddr_t kernel_pt_lookup(paddr_t); 769 770 771 /* 772 * Misc variables 773 */ 774 vaddr_t virtual_avail; 775 vaddr_t virtual_end; 776 vaddr_t pmap_curmaxkvaddr; 777 778 paddr_t avail_start; 779 paddr_t avail_end; 780 781 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 782 pv_addr_t kernelpages; 783 pv_addr_t kernel_l1pt; 784 pv_addr_t systempage; 785 786 /* Function to set the debug level of the pmap code */ 787 788 #ifdef PMAP_DEBUG 789 void 790 pmap_debug(int level) 791 { 792 pmap_debug_level = level; 793 printf("pmap_debug: level=%d\n", pmap_debug_level); 794 } 795 #endif /* PMAP_DEBUG */ 796 797 #ifdef PMAP_CACHE_VIPT 798 #define PMAP_VALIDATE_MD_PAGE(md) \ 799 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 800 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 801 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 802 #endif /* PMAP_CACHE_VIPT */ 803 /* 804 * A bunch of routines to conditionally flush the caches/TLB depending 805 * on whether the specified pmap actually needs to be flushed at any 806 * given time. 807 */ 808 static inline void 809 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 810 { 811 #ifdef ARM_MMU_EXTENDED 812 pmap_tlb_invalidate_addr(pm, va); 813 #else 814 if (pm->pm_cstate.cs_tlb_id != 0) { 815 if (PV_BEEN_EXECD(flags)) { 816 cpu_tlb_flushID_SE(va); 817 } else if (PV_BEEN_REFD(flags)) { 818 cpu_tlb_flushD_SE(va); 819 } 820 } 821 #endif /* ARM_MMU_EXTENDED */ 822 } 823 824 static inline void 825 pmap_tlb_flushID(pmap_t pm) 826 { 827 #ifdef ARM_MMU_EXTENDED 828 pmap_tlb_asid_release_all(pm); 829 #else 830 if (pm->pm_cstate.cs_tlb_id) { 831 cpu_tlb_flushID(); 832 #if ARM_MMU_V7 == 0 833 /* 834 * Speculative loads by Cortex cores can cause TLB entries to 835 * be filled even if there are no explicit accesses, so there 836 * may be always be TLB entries to flush. If we used ASIDs 837 * then it would not be a problem. 838 * This is not true for other CPUs. 839 */ 840 pm->pm_cstate.cs_tlb = 0; 841 #endif /* ARM_MMU_V7 */ 842 } 843 #endif /* ARM_MMU_EXTENDED */ 844 } 845 846 static inline void 847 pmap_tlb_flushD(pmap_t pm) 848 { 849 #ifdef ARM_MMU_EXTENDED 850 pmap_tlb_asid_release_all(pm); 851 #else 852 if (pm->pm_cstate.cs_tlb_d) { 853 cpu_tlb_flushD(); 854 #if ARM_MMU_V7 == 0 855 /* 856 * Speculative loads by Cortex cores can cause TLB entries to 857 * be filled even if there are no explicit accesses, so there 858 * may be always be TLB entries to flush. If we used ASIDs 859 * then it would not be a problem. 860 * This is not true for other CPUs. 861 */ 862 pm->pm_cstate.cs_tlb_d = 0; 863 #endif /* ARM_MMU_V7 */ 864 } 865 #endif /* ARM_MMU_EXTENDED */ 866 } 867 868 #ifdef PMAP_CACHE_VIVT 869 static inline void 870 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 871 { 872 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 873 cpu_idcache_wbinv_range(va, PAGE_SIZE); 874 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 875 if (do_inv) { 876 if (flags & PVF_WRITE) 877 cpu_dcache_wbinv_range(va, PAGE_SIZE); 878 else 879 cpu_dcache_inv_range(va, PAGE_SIZE); 880 } else if (flags & PVF_WRITE) { 881 cpu_dcache_wb_range(va, PAGE_SIZE); 882 } 883 } 884 } 885 886 static inline void 887 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 888 { 889 if (PV_BEEN_EXECD(flags)) { 890 if (pm->pm_cstate.cs_cache_id) { 891 cpu_idcache_wbinv_all(); 892 pm->pm_cstate.cs_cache = 0; 893 } 894 } else if (pm->pm_cstate.cs_cache_d) { 895 cpu_dcache_wbinv_all(); 896 pm->pm_cstate.cs_cache_d = 0; 897 } 898 } 899 #endif /* PMAP_CACHE_VIVT */ 900 901 static inline uint8_t 902 pmap_domain(pmap_t pm) 903 { 904 #ifdef ARM_MMU_EXTENDED 905 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 906 #else 907 return pm->pm_domain; 908 #endif 909 } 910 911 static inline pd_entry_t * 912 pmap_l1_kva(pmap_t pm) 913 { 914 #ifdef ARM_MMU_EXTENDED 915 return pm->pm_l1; 916 #else 917 return pm->pm_l1->l1_kva; 918 #endif 919 } 920 921 static inline bool 922 pmap_is_current(pmap_t pm) 923 { 924 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 925 return true; 926 927 return false; 928 } 929 930 static inline bool 931 pmap_is_cached(pmap_t pm) 932 { 933 #ifdef ARM_MMU_EXTENDED 934 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 935 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 936 return true; 937 #else 938 struct cpu_info * const ci = curcpu(); 939 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 940 || ci->ci_pmap_lastuser == pm) 941 return true; 942 #endif /* ARM_MMU_EXTENDED */ 943 944 return false; 945 } 946 947 /* 948 * PTE_SYNC_CURRENT: 949 * 950 * Make sure the pte is written out to RAM. 951 * We need to do this for one of two cases: 952 * - We're dealing with the kernel pmap 953 * - There is no pmap active in the cache/tlb. 954 * - The specified pmap is 'active' in the cache/tlb. 955 */ 956 #ifdef PMAP_INCLUDE_PTE_SYNC 957 #define PTE_SYNC_CURRENT(pm, ptep) \ 958 do { \ 959 if (PMAP_NEEDS_PTE_SYNC && \ 960 pmap_is_cached(pm)) \ 961 PTE_SYNC(ptep); \ 962 } while (/*CONSTCOND*/0) 963 #else 964 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 965 #endif 966 967 /* 968 * main pv_entry manipulation functions: 969 * pmap_enter_pv: enter a mapping onto a vm_page list 970 * pmap_remove_pv: remove a mapping from a vm_page list 971 * 972 * NOTE: pmap_enter_pv expects to lock the pvh itself 973 * pmap_remove_pv expects the caller to lock the pvh before calling 974 */ 975 976 /* 977 * pmap_enter_pv: enter a mapping onto a vm_page lst 978 * 979 * => caller should hold the proper lock on pmap_main_lock 980 * => caller should have pmap locked 981 * => we will gain the lock on the vm_page and allocate the new pv_entry 982 * => caller should adjust ptp's wire_count before calling 983 * => caller should not adjust pmap's wire_count 984 */ 985 static void 986 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 987 vaddr_t va, u_int flags) 988 { 989 struct pv_entry **pvp; 990 991 NPDEBUG(PDB_PVDUMP, 992 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 993 994 pv->pv_pmap = pm; 995 pv->pv_va = va; 996 pv->pv_flags = flags; 997 998 pvp = &SLIST_FIRST(&md->pvh_list); 999 #ifdef PMAP_CACHE_VIPT 1000 /* 1001 * Insert unmanaged entries, writeable first, at the head of 1002 * the pv list. 1003 */ 1004 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1005 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1006 pvp = &SLIST_NEXT(*pvp, pv_link); 1007 } 1008 if (!PV_IS_WRITE_P(flags)) { 1009 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1010 pvp = &SLIST_NEXT(*pvp, pv_link); 1011 } 1012 #endif 1013 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1014 *pvp = pv; /* ... locked list */ 1015 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1016 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1017 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1018 md->pvh_attrs |= PVF_KMOD; 1019 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1020 md->pvh_attrs |= PVF_DIRTY; 1021 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1022 #endif 1023 if (pm == pmap_kernel()) { 1024 PMAPCOUNT(kernel_mappings); 1025 if (flags & PVF_WRITE) 1026 md->krw_mappings++; 1027 else 1028 md->kro_mappings++; 1029 } else { 1030 if (flags & PVF_WRITE) 1031 md->urw_mappings++; 1032 else 1033 md->uro_mappings++; 1034 } 1035 1036 #ifdef PMAP_CACHE_VIPT 1037 #ifndef ARM_MMU_EXTENDED 1038 /* 1039 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1040 * do it here as well to keep the mappings & KVF_WRITE consistent. 1041 */ 1042 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1043 md->pvh_attrs |= PVF_WRITE; 1044 } 1045 #endif 1046 /* 1047 * If this is an exec mapping and its the first exec mapping 1048 * for this page, make sure to sync the I-cache. 1049 */ 1050 if (PV_IS_EXEC_P(flags)) { 1051 #ifndef ARM_MMU_EXTENDED 1052 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1053 pmap_syncicache_page(md, pa); 1054 PMAPCOUNT(exec_synced_map); 1055 } 1056 #endif 1057 PMAPCOUNT(exec_mappings); 1058 } 1059 #endif 1060 1061 PMAPCOUNT(mappings); 1062 1063 if (pv->pv_flags & PVF_WIRED) 1064 ++pm->pm_stats.wired_count; 1065 } 1066 1067 /* 1068 * 1069 * pmap_find_pv: Find a pv entry 1070 * 1071 * => caller should hold lock on vm_page 1072 */ 1073 static inline struct pv_entry * 1074 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1075 { 1076 struct pv_entry *pv; 1077 1078 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1079 if (pm == pv->pv_pmap && va == pv->pv_va) 1080 break; 1081 } 1082 1083 return (pv); 1084 } 1085 1086 /* 1087 * pmap_remove_pv: try to remove a mapping from a pv_list 1088 * 1089 * => caller should hold proper lock on pmap_main_lock 1090 * => pmap should be locked 1091 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1092 * => caller should adjust ptp's wire_count and free PTP if needed 1093 * => caller should NOT adjust pmap's wire_count 1094 * => we return the removed pv 1095 */ 1096 static struct pv_entry * 1097 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1098 { 1099 struct pv_entry *pv, **prevptr; 1100 1101 NPDEBUG(PDB_PVDUMP, 1102 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1103 1104 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1105 pv = *prevptr; 1106 1107 while (pv) { 1108 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1109 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1110 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1111 if (pv->pv_flags & PVF_WIRED) { 1112 --pm->pm_stats.wired_count; 1113 } 1114 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1115 if (pm == pmap_kernel()) { 1116 PMAPCOUNT(kernel_unmappings); 1117 if (pv->pv_flags & PVF_WRITE) 1118 md->krw_mappings--; 1119 else 1120 md->kro_mappings--; 1121 } else { 1122 if (pv->pv_flags & PVF_WRITE) 1123 md->urw_mappings--; 1124 else 1125 md->uro_mappings--; 1126 } 1127 1128 PMAPCOUNT(unmappings); 1129 #ifdef PMAP_CACHE_VIPT 1130 if (!(pv->pv_flags & PVF_WRITE)) 1131 break; 1132 /* 1133 * If this page has had an exec mapping, then if 1134 * this was the last mapping, discard the contents, 1135 * otherwise sync the i-cache for this page. 1136 */ 1137 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1138 #ifdef ARM_MMU_EXTENDED 1139 md->pvh_attrs &= ~PVF_EXEC; 1140 PMAPCOUNT(exec_discarded_unmap); 1141 #else 1142 if (SLIST_EMPTY(&md->pvh_list)) { 1143 md->pvh_attrs &= ~PVF_EXEC; 1144 PMAPCOUNT(exec_discarded_unmap); 1145 } else { 1146 pmap_syncicache_page(md, pa); 1147 PMAPCOUNT(exec_synced_unmap); 1148 } 1149 #endif /* ARM_MMU_EXTENDED */ 1150 } 1151 #endif /* PMAP_CACHE_VIPT */ 1152 break; 1153 } 1154 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1155 pv = *prevptr; /* advance */ 1156 } 1157 1158 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1159 /* 1160 * If we no longer have a WRITEABLE KENTRY at the head of list, 1161 * clear the KMOD attribute from the page. 1162 */ 1163 if (SLIST_FIRST(&md->pvh_list) == NULL 1164 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1165 md->pvh_attrs &= ~PVF_KMOD; 1166 1167 /* 1168 * If this was a writeable page and there are no more writeable 1169 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1170 * the contents to memory. 1171 */ 1172 if (arm_cache_prefer_mask != 0) { 1173 if (md->krw_mappings + md->urw_mappings == 0) 1174 md->pvh_attrs &= ~PVF_WRITE; 1175 PMAP_VALIDATE_MD_PAGE(md); 1176 } 1177 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1178 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1179 1180 return(pv); /* return removed pv */ 1181 } 1182 1183 /* 1184 * 1185 * pmap_modify_pv: Update pv flags 1186 * 1187 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1188 * => caller should NOT adjust pmap's wire_count 1189 * => caller must call pmap_vac_me_harder() if writable status of a page 1190 * may have changed. 1191 * => we return the old flags 1192 * 1193 * Modify a physical-virtual mapping in the pv table 1194 */ 1195 static u_int 1196 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1197 u_int clr_mask, u_int set_mask) 1198 { 1199 struct pv_entry *npv; 1200 u_int flags, oflags; 1201 1202 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1203 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1204 1205 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1206 return (0); 1207 1208 NPDEBUG(PDB_PVDUMP, 1209 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1210 1211 /* 1212 * There is at least one VA mapping this page. 1213 */ 1214 1215 if (clr_mask & (PVF_REF | PVF_MOD)) { 1216 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1217 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1218 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1219 md->pvh_attrs |= PVF_DIRTY; 1220 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1221 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1222 } 1223 1224 oflags = npv->pv_flags; 1225 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1226 1227 if ((flags ^ oflags) & PVF_WIRED) { 1228 if (flags & PVF_WIRED) 1229 ++pm->pm_stats.wired_count; 1230 else 1231 --pm->pm_stats.wired_count; 1232 } 1233 1234 if ((flags ^ oflags) & PVF_WRITE) { 1235 if (pm == pmap_kernel()) { 1236 if (flags & PVF_WRITE) { 1237 md->krw_mappings++; 1238 md->kro_mappings--; 1239 } else { 1240 md->kro_mappings++; 1241 md->krw_mappings--; 1242 } 1243 } else { 1244 if (flags & PVF_WRITE) { 1245 md->urw_mappings++; 1246 md->uro_mappings--; 1247 } else { 1248 md->uro_mappings++; 1249 md->urw_mappings--; 1250 } 1251 } 1252 } 1253 #ifdef PMAP_CACHE_VIPT 1254 if (arm_cache_prefer_mask != 0) { 1255 if (md->urw_mappings + md->krw_mappings == 0) { 1256 md->pvh_attrs &= ~PVF_WRITE; 1257 } else { 1258 md->pvh_attrs |= PVF_WRITE; 1259 } 1260 } 1261 #ifndef ARM_MMU_EXTENDED 1262 /* 1263 * We have two cases here: the first is from enter_pv (new exec 1264 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1265 * Since in latter, pmap_enter_pv won't do anything, we just have 1266 * to do what pmap_remove_pv would do. 1267 */ 1268 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1269 || (PV_IS_EXEC_P(md->pvh_attrs) 1270 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1271 pmap_syncicache_page(md, pa); 1272 PMAPCOUNT(exec_synced_remap); 1273 } 1274 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1275 #endif /* !ARM_MMU_EXTENDED */ 1276 #endif /* PMAP_CACHE_VIPT */ 1277 1278 PMAPCOUNT(remappings); 1279 1280 return (oflags); 1281 } 1282 1283 /* 1284 * Allocate an L1 translation table for the specified pmap. 1285 * This is called at pmap creation time. 1286 */ 1287 static void 1288 pmap_alloc_l1(pmap_t pm) 1289 { 1290 #ifdef ARM_MMU_EXTENDED 1291 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1292 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1293 struct vm_page *pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1294 #else 1295 struct vm_page *pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1296 #endif 1297 KASSERT(pg != NULL); 1298 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1299 vaddr_t va = KERNEL_BASE + (pm->pm_l1_pa - physical_start); 1300 1301 #else 1302 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1303 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1304 UVM_KMF_WIRED|UVM_KMF_ZERO); 1305 KASSERT(!va); 1306 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1307 #endif 1308 pm->pm_l1 = (pd_entry_t *)va; 1309 #else 1310 struct l1_ttable *l1; 1311 uint8_t domain; 1312 1313 /* 1314 * Remove the L1 at the head of the LRU list 1315 */ 1316 mutex_spin_enter(&l1_lru_lock); 1317 l1 = TAILQ_FIRST(&l1_lru_list); 1318 KDASSERT(l1 != NULL); 1319 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1320 1321 /* 1322 * Pick the first available domain number, and update 1323 * the link to the next number. 1324 */ 1325 domain = l1->l1_domain_first; 1326 l1->l1_domain_first = l1->l1_domain_free[domain]; 1327 1328 /* 1329 * If there are still free domain numbers in this L1, 1330 * put it back on the TAIL of the LRU list. 1331 */ 1332 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1333 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1334 1335 mutex_spin_exit(&l1_lru_lock); 1336 1337 /* 1338 * Fix up the relevant bits in the pmap structure 1339 */ 1340 pm->pm_l1 = l1; 1341 pm->pm_domain = domain + 1; 1342 #endif 1343 } 1344 1345 /* 1346 * Free an L1 translation table. 1347 * This is called at pmap destruction time. 1348 */ 1349 static void 1350 pmap_free_l1(pmap_t pm) 1351 { 1352 #ifdef ARM_MMU_EXTENDED 1353 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1354 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1355 uvm_pagefree(pg); 1356 #else 1357 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1358 #endif 1359 pm->pm_l1 = NULL; 1360 pm->pm_l1_pa = 0; 1361 #else 1362 struct l1_ttable *l1 = pm->pm_l1; 1363 1364 mutex_spin_enter(&l1_lru_lock); 1365 1366 /* 1367 * If this L1 is currently on the LRU list, remove it. 1368 */ 1369 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1370 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1371 1372 /* 1373 * Free up the domain number which was allocated to the pmap 1374 */ 1375 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1376 l1->l1_domain_first = pmap_domain(pm) - 1; 1377 l1->l1_domain_use_count--; 1378 1379 /* 1380 * The L1 now must have at least 1 free domain, so add 1381 * it back to the LRU list. If the use count is zero, 1382 * put it at the head of the list, otherwise it goes 1383 * to the tail. 1384 */ 1385 if (l1->l1_domain_use_count == 0) 1386 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1387 else 1388 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1389 1390 mutex_spin_exit(&l1_lru_lock); 1391 #endif /* ARM_MMU_EXTENDED */ 1392 } 1393 1394 #ifndef ARM_MMU_EXTENDED 1395 static inline void 1396 pmap_use_l1(pmap_t pm) 1397 { 1398 struct l1_ttable *l1; 1399 1400 /* 1401 * Do nothing if we're in interrupt context. 1402 * Access to an L1 by the kernel pmap must not affect 1403 * the LRU list. 1404 */ 1405 if (cpu_intr_p() || pm == pmap_kernel()) 1406 return; 1407 1408 l1 = pm->pm_l1; 1409 1410 /* 1411 * If the L1 is not currently on the LRU list, just return 1412 */ 1413 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1414 return; 1415 1416 mutex_spin_enter(&l1_lru_lock); 1417 1418 /* 1419 * Check the use count again, now that we've acquired the lock 1420 */ 1421 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1422 mutex_spin_exit(&l1_lru_lock); 1423 return; 1424 } 1425 1426 /* 1427 * Move the L1 to the back of the LRU list 1428 */ 1429 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1430 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1431 1432 mutex_spin_exit(&l1_lru_lock); 1433 } 1434 #endif /* !ARM_MMU_EXTENDED */ 1435 1436 /* 1437 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1438 * 1439 * Free an L2 descriptor table. 1440 */ 1441 static inline void 1442 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1443 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1444 #else 1445 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1446 #endif 1447 { 1448 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1449 /* 1450 * Note: With a write-back cache, we may need to sync this 1451 * L2 table before re-using it. 1452 * This is because it may have belonged to a non-current 1453 * pmap, in which case the cache syncs would have been 1454 * skipped for the pages that were being unmapped. If the 1455 * L2 table were then to be immediately re-allocated to 1456 * the *current* pmap, it may well contain stale mappings 1457 * which have not yet been cleared by a cache write-back 1458 * and so would still be visible to the mmu. 1459 */ 1460 if (need_sync) 1461 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1462 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1463 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1464 } 1465 1466 /* 1467 * Returns a pointer to the L2 bucket associated with the specified pmap 1468 * and VA, or NULL if no L2 bucket exists for the address. 1469 */ 1470 static inline struct l2_bucket * 1471 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1472 { 1473 const size_t l1slot = l1pte_index(va); 1474 struct l2_dtable *l2; 1475 struct l2_bucket *l2b; 1476 1477 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1478 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1479 return (NULL); 1480 1481 return (l2b); 1482 } 1483 1484 /* 1485 * Returns a pointer to the L2 bucket associated with the specified pmap 1486 * and VA. 1487 * 1488 * If no L2 bucket exists, perform the necessary allocations to put an L2 1489 * bucket/page table in place. 1490 * 1491 * Note that if a new L2 bucket/page was allocated, the caller *must* 1492 * increment the bucket occupancy counter appropriately *before* 1493 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1494 * the bucket/page in the meantime. 1495 */ 1496 static struct l2_bucket * 1497 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1498 { 1499 const size_t l1slot = l1pte_index(va); 1500 struct l2_dtable *l2; 1501 1502 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1503 /* 1504 * No mapping at this address, as there is 1505 * no entry in the L1 table. 1506 * Need to allocate a new l2_dtable. 1507 */ 1508 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1509 return (NULL); 1510 1511 /* 1512 * Link it into the parent pmap 1513 */ 1514 pm->pm_l2[L2_IDX(l1slot)] = l2; 1515 } 1516 1517 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1518 1519 /* 1520 * Fetch pointer to the L2 page table associated with the address. 1521 */ 1522 if (l2b->l2b_kva == NULL) { 1523 pt_entry_t *ptep; 1524 1525 /* 1526 * No L2 page table has been allocated. Chances are, this 1527 * is because we just allocated the l2_dtable, above. 1528 */ 1529 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1530 /* 1531 * Oops, no more L2 page tables available at this 1532 * time. We may need to deallocate the l2_dtable 1533 * if we allocated a new one above. 1534 */ 1535 if (l2->l2_occupancy == 0) { 1536 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1537 pmap_free_l2_dtable(l2); 1538 } 1539 return (NULL); 1540 } 1541 1542 l2->l2_occupancy++; 1543 l2b->l2b_kva = ptep; 1544 l2b->l2b_l1slot = l1slot; 1545 1546 #ifdef ARM_MMU_EXTENDED 1547 /* 1548 * We know there will be a mapping here, so simply 1549 * enter this PTP into the L1 now. 1550 */ 1551 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1552 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1553 | L1_C_DOM(pmap_domain(pm)); 1554 KASSERT(*pdep == 0); 1555 l1pte_setone(pdep, npde); 1556 PTE_SYNC(pdep); 1557 #endif 1558 } 1559 1560 return (l2b); 1561 } 1562 1563 /* 1564 * One or more mappings in the specified L2 descriptor table have just been 1565 * invalidated. 1566 * 1567 * Garbage collect the metadata and descriptor table itself if necessary. 1568 * 1569 * The pmap lock must be acquired when this is called (not necessary 1570 * for the kernel pmap). 1571 */ 1572 static void 1573 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1574 { 1575 KASSERT(pm != pmap_kernel()); 1576 KDASSERT(count <= l2b->l2b_occupancy); 1577 1578 /* 1579 * Update the bucket's reference count according to how many 1580 * PTEs the caller has just invalidated. 1581 */ 1582 l2b->l2b_occupancy -= count; 1583 1584 /* 1585 * Note: 1586 * 1587 * Level 2 page tables allocated to the kernel pmap are never freed 1588 * as that would require checking all Level 1 page tables and 1589 * removing any references to the Level 2 page table. See also the 1590 * comment elsewhere about never freeing bootstrap L2 descriptors. 1591 * 1592 * We make do with just invalidating the mapping in the L2 table. 1593 * 1594 * This isn't really a big deal in practice and, in fact, leads 1595 * to a performance win over time as we don't need to continually 1596 * alloc/free. 1597 */ 1598 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1599 return; 1600 1601 /* 1602 * There are no more valid mappings in this level 2 page table. 1603 * Go ahead and NULL-out the pointer in the bucket, then 1604 * free the page table. 1605 */ 1606 const size_t l1slot = l2b->l2b_l1slot; 1607 pt_entry_t * const ptep = l2b->l2b_kva; 1608 l2b->l2b_kva = NULL; 1609 1610 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1611 pd_entry_t pde __diagused = *pdep; 1612 1613 #ifdef ARM_MMU_EXTENDED 1614 /* 1615 * Invalidate the L1 slot. 1616 */ 1617 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1618 #else 1619 /* 1620 * If the L1 slot matches the pmap's domain number, then invalidate it. 1621 */ 1622 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1623 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1624 #endif 1625 l1pte_setone(pdep, 0); 1626 PDE_SYNC(pdep); 1627 #ifndef ARM_MMU_EXTENDED 1628 } 1629 #endif 1630 1631 /* 1632 * Release the L2 descriptor table back to the pool cache. 1633 */ 1634 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1635 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1636 #else 1637 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1638 #endif 1639 1640 /* 1641 * Update the reference count in the associated l2_dtable 1642 */ 1643 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1644 if (--l2->l2_occupancy > 0) 1645 return; 1646 1647 /* 1648 * There are no more valid mappings in any of the Level 1 1649 * slots managed by this l2_dtable. Go ahead and NULL-out 1650 * the pointer in the parent pmap and free the l2_dtable. 1651 */ 1652 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1653 pmap_free_l2_dtable(l2); 1654 } 1655 1656 /* 1657 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1658 * structures. 1659 */ 1660 static int 1661 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1662 { 1663 #ifndef PMAP_INCLUDE_PTE_SYNC 1664 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1665 1666 /* 1667 * The mappings for these page tables were initially made using 1668 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1669 * mode will not be right for page table mappings. To avoid 1670 * polluting the pmap_kenter_pa() code with a special case for 1671 * page tables, we simply fix up the cache-mode here if it's not 1672 * correct. 1673 */ 1674 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1675 const struct l2_bucket * const l2b = 1676 pmap_get_l2_bucket(pmap_kernel(), va); 1677 KASSERTMSG(l2b != NULL, "%#lx", va); 1678 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1679 const pt_entry_t opte = *ptep; 1680 1681 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1682 /* 1683 * Page tables must have the cache-mode set correctly. 1684 */ 1685 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1686 | pte_l2_s_cache_mode_pt; 1687 l2pte_set(ptep, npte, opte); 1688 PTE_SYNC(ptep); 1689 cpu_tlb_flushD_SE(va); 1690 cpu_cpwait(); 1691 } 1692 } 1693 #endif 1694 1695 memset(v, 0, L2_TABLE_SIZE_REAL); 1696 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1697 return (0); 1698 } 1699 1700 static int 1701 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1702 { 1703 1704 memset(v, 0, sizeof(struct l2_dtable)); 1705 return (0); 1706 } 1707 1708 static int 1709 pmap_pmap_ctor(void *arg, void *v, int flags) 1710 { 1711 1712 memset(v, 0, sizeof(struct pmap)); 1713 return (0); 1714 } 1715 1716 static void 1717 pmap_pinit(pmap_t pm) 1718 { 1719 #ifndef ARM_HAS_VBAR 1720 struct l2_bucket *l2b; 1721 1722 if (vector_page < KERNEL_BASE) { 1723 /* 1724 * Map the vector page. 1725 */ 1726 pmap_enter(pm, vector_page, systempage.pv_pa, 1727 VM_PROT_READ | VM_PROT_EXECUTE, 1728 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1729 pmap_update(pm); 1730 1731 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1732 l2b = pmap_get_l2_bucket(pm, vector_page); 1733 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1734 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1735 L1_C_DOM(pmap_domain(pm)); 1736 } else 1737 pm->pm_pl1vec = NULL; 1738 #endif 1739 } 1740 1741 #ifdef PMAP_CACHE_VIVT 1742 /* 1743 * Since we have a virtually indexed cache, we may need to inhibit caching if 1744 * there is more than one mapping and at least one of them is writable. 1745 * Since we purge the cache on every context switch, we only need to check for 1746 * other mappings within the same pmap, or kernel_pmap. 1747 * This function is also called when a page is unmapped, to possibly reenable 1748 * caching on any remaining mappings. 1749 * 1750 * The code implements the following logic, where: 1751 * 1752 * KW = # of kernel read/write pages 1753 * KR = # of kernel read only pages 1754 * UW = # of user read/write pages 1755 * UR = # of user read only pages 1756 * 1757 * KC = kernel mapping is cacheable 1758 * UC = user mapping is cacheable 1759 * 1760 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1761 * +--------------------------------------------- 1762 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1763 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1764 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1765 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1766 */ 1767 1768 static const int pmap_vac_flags[4][4] = { 1769 {-1, 0, 0, PVF_KNC}, 1770 {0, 0, PVF_NC, PVF_NC}, 1771 {0, PVF_NC, PVF_NC, PVF_NC}, 1772 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1773 }; 1774 1775 static inline int 1776 pmap_get_vac_flags(const struct vm_page_md *md) 1777 { 1778 int kidx, uidx; 1779 1780 kidx = 0; 1781 if (md->kro_mappings || md->krw_mappings > 1) 1782 kidx |= 1; 1783 if (md->krw_mappings) 1784 kidx |= 2; 1785 1786 uidx = 0; 1787 if (md->uro_mappings || md->urw_mappings > 1) 1788 uidx |= 1; 1789 if (md->urw_mappings) 1790 uidx |= 2; 1791 1792 return (pmap_vac_flags[uidx][kidx]); 1793 } 1794 1795 static inline void 1796 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1797 { 1798 int nattr; 1799 1800 nattr = pmap_get_vac_flags(md); 1801 1802 if (nattr < 0) { 1803 md->pvh_attrs &= ~PVF_NC; 1804 return; 1805 } 1806 1807 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1808 return; 1809 1810 if (pm == pmap_kernel()) 1811 pmap_vac_me_kpmap(md, pa, pm, va); 1812 else 1813 pmap_vac_me_user(md, pa, pm, va); 1814 1815 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1816 } 1817 1818 static void 1819 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1820 { 1821 u_int u_cacheable, u_entries; 1822 struct pv_entry *pv; 1823 pmap_t last_pmap = pm; 1824 1825 /* 1826 * Pass one, see if there are both kernel and user pmaps for 1827 * this page. Calculate whether there are user-writable or 1828 * kernel-writable pages. 1829 */ 1830 u_cacheable = 0; 1831 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1832 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1833 u_cacheable++; 1834 } 1835 1836 u_entries = md->urw_mappings + md->uro_mappings; 1837 1838 /* 1839 * We know we have just been updating a kernel entry, so if 1840 * all user pages are already cacheable, then there is nothing 1841 * further to do. 1842 */ 1843 if (md->k_mappings == 0 && u_cacheable == u_entries) 1844 return; 1845 1846 if (u_entries) { 1847 /* 1848 * Scan over the list again, for each entry, if it 1849 * might not be set correctly, call pmap_vac_me_user 1850 * to recalculate the settings. 1851 */ 1852 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1853 /* 1854 * We know kernel mappings will get set 1855 * correctly in other calls. We also know 1856 * that if the pmap is the same as last_pmap 1857 * then we've just handled this entry. 1858 */ 1859 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1860 continue; 1861 1862 /* 1863 * If there are kernel entries and this page 1864 * is writable but non-cacheable, then we can 1865 * skip this entry also. 1866 */ 1867 if (md->k_mappings && 1868 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1869 (PVF_NC | PVF_WRITE)) 1870 continue; 1871 1872 /* 1873 * Similarly if there are no kernel-writable 1874 * entries and the page is already 1875 * read-only/cacheable. 1876 */ 1877 if (md->krw_mappings == 0 && 1878 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1879 continue; 1880 1881 /* 1882 * For some of the remaining cases, we know 1883 * that we must recalculate, but for others we 1884 * can't tell if they are correct or not, so 1885 * we recalculate anyway. 1886 */ 1887 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1888 } 1889 1890 if (md->k_mappings == 0) 1891 return; 1892 } 1893 1894 pmap_vac_me_user(md, pa, pm, va); 1895 } 1896 1897 static void 1898 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1899 { 1900 pmap_t kpmap = pmap_kernel(); 1901 struct pv_entry *pv, *npv = NULL; 1902 u_int entries = 0; 1903 u_int writable = 0; 1904 u_int cacheable_entries = 0; 1905 u_int kern_cacheable = 0; 1906 u_int other_writable = 0; 1907 1908 /* 1909 * Count mappings and writable mappings in this pmap. 1910 * Include kernel mappings as part of our own. 1911 * Keep a pointer to the first one. 1912 */ 1913 npv = NULL; 1914 KASSERT(pmap_page_locked_p(md)); 1915 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1916 /* Count mappings in the same pmap */ 1917 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1918 if (entries++ == 0) 1919 npv = pv; 1920 1921 /* Cacheable mappings */ 1922 if ((pv->pv_flags & PVF_NC) == 0) { 1923 cacheable_entries++; 1924 if (kpmap == pv->pv_pmap) 1925 kern_cacheable++; 1926 } 1927 1928 /* Writable mappings */ 1929 if (pv->pv_flags & PVF_WRITE) 1930 ++writable; 1931 } else 1932 if (pv->pv_flags & PVF_WRITE) 1933 other_writable = 1; 1934 } 1935 1936 /* 1937 * Enable or disable caching as necessary. 1938 * Note: the first entry might be part of the kernel pmap, 1939 * so we can't assume this is indicative of the state of the 1940 * other (maybe non-kpmap) entries. 1941 */ 1942 if ((entries > 1 && writable) || 1943 (entries > 0 && pm == kpmap && other_writable)) { 1944 if (cacheable_entries == 0) { 1945 return; 1946 } 1947 1948 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1949 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1950 (pv->pv_flags & PVF_NC)) 1951 continue; 1952 1953 pv->pv_flags |= PVF_NC; 1954 1955 struct l2_bucket * const l2b 1956 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1957 KASSERTMSG(l2b != NULL, "%#lx", va); 1958 pt_entry_t * const ptep 1959 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1960 const pt_entry_t opte = *ptep; 1961 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1962 1963 if ((va != pv->pv_va || pm != pv->pv_pmap) 1964 && l2pte_valid_p(npte)) { 1965 #ifdef PMAP_CACHE_VIVT 1966 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1967 true, pv->pv_flags); 1968 #endif 1969 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1970 pv->pv_flags); 1971 } 1972 1973 l2pte_set(ptep, npte, opte); 1974 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1975 } 1976 cpu_cpwait(); 1977 } else 1978 if (entries > cacheable_entries) { 1979 /* 1980 * Turn cacheing back on for some pages. If it is a kernel 1981 * page, only do so if there are no other writable pages. 1982 */ 1983 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1984 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1985 (kpmap != pv->pv_pmap || other_writable))) 1986 continue; 1987 1988 pv->pv_flags &= ~PVF_NC; 1989 1990 struct l2_bucket * const l2b 1991 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1992 KASSERTMSG(l2b != NULL, "%#lx", va); 1993 pt_entry_t * const ptep 1994 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1995 const pt_entry_t opte = *ptep; 1996 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1997 | pte_l2_s_cache_mode; 1998 1999 if (l2pte_valid_p(opte)) { 2000 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2001 pv->pv_flags); 2002 } 2003 2004 l2pte_set(ptep, npte, opte); 2005 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2006 } 2007 } 2008 } 2009 #endif 2010 2011 #ifdef PMAP_CACHE_VIPT 2012 static void 2013 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2014 { 2015 #ifndef ARM_MMU_EXTENDED 2016 struct pv_entry *pv; 2017 vaddr_t tst_mask; 2018 bool bad_alias; 2019 const u_int 2020 rw_mappings = md->urw_mappings + md->krw_mappings, 2021 ro_mappings = md->uro_mappings + md->kro_mappings; 2022 2023 /* do we need to do anything? */ 2024 if (arm_cache_prefer_mask == 0) 2025 return; 2026 2027 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2028 md, pm, va)); 2029 2030 KASSERT(!va || pm); 2031 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2032 2033 /* Already a conflict? */ 2034 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2035 /* just an add, things are already non-cached */ 2036 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2037 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2038 bad_alias = false; 2039 if (va) { 2040 PMAPCOUNT(vac_color_none); 2041 bad_alias = true; 2042 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2043 goto fixup; 2044 } 2045 pv = SLIST_FIRST(&md->pvh_list); 2046 /* the list can't be empty because it would be cachable */ 2047 if (md->pvh_attrs & PVF_KMPAGE) { 2048 tst_mask = md->pvh_attrs; 2049 } else { 2050 KASSERT(pv); 2051 tst_mask = pv->pv_va; 2052 pv = SLIST_NEXT(pv, pv_link); 2053 } 2054 /* 2055 * Only check for a bad alias if we have writable mappings. 2056 */ 2057 tst_mask &= arm_cache_prefer_mask; 2058 if (rw_mappings > 0) { 2059 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2060 /* if there's a bad alias, stop checking. */ 2061 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2062 bad_alias = true; 2063 } 2064 md->pvh_attrs |= PVF_WRITE; 2065 if (!bad_alias) 2066 md->pvh_attrs |= PVF_DIRTY; 2067 } else { 2068 /* 2069 * We have only read-only mappings. Let's see if there 2070 * are multiple colors in use or if we mapped a KMPAGE. 2071 * If the latter, we have a bad alias. If the former, 2072 * we need to remember that. 2073 */ 2074 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2075 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2076 if (md->pvh_attrs & PVF_KMPAGE) 2077 bad_alias = true; 2078 break; 2079 } 2080 } 2081 md->pvh_attrs &= ~PVF_WRITE; 2082 /* 2083 * No KMPAGE and we exited early, so we must have 2084 * multiple color mappings. 2085 */ 2086 if (!bad_alias && pv != NULL) 2087 md->pvh_attrs |= PVF_MULTCLR; 2088 } 2089 2090 /* If no conflicting colors, set everything back to cached */ 2091 if (!bad_alias) { 2092 #ifdef DEBUG 2093 if ((md->pvh_attrs & PVF_WRITE) 2094 || ro_mappings < 2) { 2095 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2096 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2097 } 2098 #endif 2099 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2100 md->pvh_attrs |= tst_mask | PVF_COLORED; 2101 /* 2102 * Restore DIRTY bit if page is modified 2103 */ 2104 if (md->pvh_attrs & PVF_DMOD) 2105 md->pvh_attrs |= PVF_DIRTY; 2106 PMAPCOUNT(vac_color_restore); 2107 } else { 2108 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2109 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2110 } 2111 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2112 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2113 } else if (!va) { 2114 KASSERT(pmap_is_page_colored_p(md)); 2115 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2116 || (md->pvh_attrs & PVF_DIRTY)); 2117 if (rw_mappings == 0) { 2118 md->pvh_attrs &= ~PVF_WRITE; 2119 if (ro_mappings == 1 2120 && (md->pvh_attrs & PVF_MULTCLR)) { 2121 /* 2122 * If this is the last readonly mapping 2123 * but it doesn't match the current color 2124 * for the page, change the current color 2125 * to match this last readonly mapping. 2126 */ 2127 pv = SLIST_FIRST(&md->pvh_list); 2128 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2129 & arm_cache_prefer_mask; 2130 if (tst_mask) { 2131 md->pvh_attrs ^= tst_mask; 2132 PMAPCOUNT(vac_color_change); 2133 } 2134 } 2135 } 2136 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2137 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2138 return; 2139 } else if (!pmap_is_page_colored_p(md)) { 2140 /* not colored so we just use its color */ 2141 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2142 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2143 PMAPCOUNT(vac_color_new); 2144 md->pvh_attrs &= PAGE_SIZE - 1; 2145 md->pvh_attrs |= PVF_COLORED 2146 | (va & arm_cache_prefer_mask) 2147 | (rw_mappings > 0 ? PVF_WRITE : 0); 2148 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2149 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2150 return; 2151 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2152 bad_alias = false; 2153 if (rw_mappings > 0) { 2154 /* 2155 * We now have writeable mappings and if we have 2156 * readonly mappings in more than once color, we have 2157 * an aliasing problem. Regardless mark the page as 2158 * writeable. 2159 */ 2160 if (md->pvh_attrs & PVF_MULTCLR) { 2161 if (ro_mappings < 2) { 2162 /* 2163 * If we only have less than two 2164 * read-only mappings, just flush the 2165 * non-primary colors from the cache. 2166 */ 2167 pmap_flush_page(md, pa, 2168 PMAP_FLUSH_SECONDARY); 2169 } else { 2170 bad_alias = true; 2171 } 2172 } 2173 md->pvh_attrs |= PVF_WRITE; 2174 } 2175 /* If no conflicting colors, set everything back to cached */ 2176 if (!bad_alias) { 2177 #ifdef DEBUG 2178 if (rw_mappings > 0 2179 || (md->pvh_attrs & PMAP_KMPAGE)) { 2180 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2181 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2182 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2183 } 2184 #endif 2185 if (SLIST_EMPTY(&md->pvh_list)) 2186 PMAPCOUNT(vac_color_reuse); 2187 else 2188 PMAPCOUNT(vac_color_ok); 2189 2190 /* matching color, just return */ 2191 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2192 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2193 return; 2194 } 2195 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2196 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2197 2198 /* color conflict. evict from cache. */ 2199 2200 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2201 md->pvh_attrs &= ~PVF_COLORED; 2202 md->pvh_attrs |= PVF_NC; 2203 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2204 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2205 PMAPCOUNT(vac_color_erase); 2206 } else if (rw_mappings == 0 2207 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2208 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2209 2210 /* 2211 * If the page has dirty cache lines, clean it. 2212 */ 2213 if (md->pvh_attrs & PVF_DIRTY) 2214 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2215 2216 /* 2217 * If this is the first remapping (we know that there are no 2218 * writeable mappings), then this is a simple color change. 2219 * Otherwise this is a seconary r/o mapping, which means 2220 * we don't have to do anything. 2221 */ 2222 if (ro_mappings == 1) { 2223 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2224 md->pvh_attrs &= PAGE_SIZE - 1; 2225 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2226 PMAPCOUNT(vac_color_change); 2227 } else { 2228 PMAPCOUNT(vac_color_blind); 2229 } 2230 md->pvh_attrs |= PVF_MULTCLR; 2231 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2232 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2233 return; 2234 } else { 2235 if (rw_mappings > 0) 2236 md->pvh_attrs |= PVF_WRITE; 2237 2238 /* color conflict. evict from cache. */ 2239 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2240 2241 /* the list can't be empty because this was a enter/modify */ 2242 pv = SLIST_FIRST(&md->pvh_list); 2243 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2244 KASSERT(pv); 2245 /* 2246 * If there's only one mapped page, change color to the 2247 * page's new color and return. Restore the DIRTY bit 2248 * that was erased by pmap_flush_page. 2249 */ 2250 if (SLIST_NEXT(pv, pv_link) == NULL) { 2251 md->pvh_attrs &= PAGE_SIZE - 1; 2252 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2253 if (md->pvh_attrs & PVF_DMOD) 2254 md->pvh_attrs |= PVF_DIRTY; 2255 PMAPCOUNT(vac_color_change); 2256 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2257 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2258 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2259 return; 2260 } 2261 } 2262 bad_alias = true; 2263 md->pvh_attrs &= ~PVF_COLORED; 2264 md->pvh_attrs |= PVF_NC; 2265 PMAPCOUNT(vac_color_erase); 2266 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2267 } 2268 2269 fixup: 2270 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2271 2272 /* 2273 * Turn cacheing on/off for all pages. 2274 */ 2275 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2276 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2277 pv->pv_va); 2278 KASSERTMSG(l2b != NULL, "%#lx", va); 2279 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2280 const pt_entry_t opte = *ptep; 2281 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2282 if (bad_alias) { 2283 pv->pv_flags |= PVF_NC; 2284 } else { 2285 pv->pv_flags &= ~PVF_NC; 2286 npte |= pte_l2_s_cache_mode; 2287 } 2288 2289 if (opte == npte) /* only update is there's a change */ 2290 continue; 2291 2292 if (l2pte_valid_p(npte)) { 2293 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2294 } 2295 2296 l2pte_set(ptep, npte, opte); 2297 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2298 } 2299 #endif /* !ARM_MMU_EXTENDED */ 2300 } 2301 #endif /* PMAP_CACHE_VIPT */ 2302 2303 2304 /* 2305 * Modify pte bits for all ptes corresponding to the given physical address. 2306 * We use `maskbits' rather than `clearbits' because we're always passing 2307 * constants and the latter would require an extra inversion at run-time. 2308 */ 2309 static void 2310 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2311 { 2312 struct pv_entry *pv; 2313 #ifdef PMAP_CACHE_VIPT 2314 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2315 #ifdef ARM_MMU_EXTENDED 2316 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2317 #else 2318 const u_int execbits = 0; 2319 bool need_vac_me_harder = false; 2320 bool need_syncicache = false; 2321 #endif 2322 #else 2323 const u_int execbits = 0; 2324 #endif 2325 2326 NPDEBUG(PDB_BITS, 2327 printf("pmap_clearbit: md %p mask 0x%x\n", 2328 md, maskbits)); 2329 2330 #ifdef PMAP_CACHE_VIPT 2331 /* 2332 * If we might want to sync the I-cache and we've modified it, 2333 * then we know we definitely need to sync or discard it. 2334 */ 2335 if (want_syncicache) { 2336 #ifdef ARM_MMU_EXTENDED 2337 if (md->pvh_attrs & PVF_MOD) 2338 md->pvh_attrs &= ~PVF_EXEC; 2339 #else 2340 need_syncicache = md->pvh_attrs & PVF_MOD; 2341 #endif 2342 } 2343 #endif 2344 KASSERT(pmap_page_locked_p(md)); 2345 2346 /* 2347 * Clear saved attributes (modify, reference) 2348 */ 2349 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2350 2351 if (SLIST_EMPTY(&md->pvh_list)) { 2352 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2353 if (need_syncicache) { 2354 /* 2355 * No one has it mapped, so just discard it. The next 2356 * exec remapping will cause it to be synced. 2357 */ 2358 md->pvh_attrs &= ~PVF_EXEC; 2359 PMAPCOUNT(exec_discarded_clearbit); 2360 } 2361 #endif 2362 return; 2363 } 2364 2365 /* 2366 * Loop over all current mappings setting/clearing as appropos 2367 */ 2368 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2369 pmap_t pm = pv->pv_pmap; 2370 const vaddr_t va = pv->pv_va; 2371 const u_int oflags = pv->pv_flags; 2372 #ifndef ARM_MMU_EXTENDED 2373 /* 2374 * Kernel entries are unmanaged and as such not to be changed. 2375 */ 2376 if (PV_IS_KENTRY_P(oflags)) 2377 continue; 2378 #endif 2379 pv->pv_flags &= ~maskbits; 2380 2381 pmap_release_page_lock(md); 2382 pmap_acquire_pmap_lock(pm); 2383 2384 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2385 if (l2b == NULL) { 2386 pmap_release_pmap_lock(pm); 2387 pmap_acquire_page_lock(md); 2388 continue; 2389 } 2390 KASSERTMSG(l2b != NULL, "%#lx", va); 2391 2392 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2393 const pt_entry_t opte = *ptep; 2394 pt_entry_t npte = opte | execbits; 2395 2396 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2397 2398 NPDEBUG(PDB_BITS, 2399 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2400 __func__, pv, pm, va, oflags)); 2401 2402 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2403 #ifdef PMAP_CACHE_VIVT 2404 if ((oflags & PVF_NC)) { 2405 /* 2406 * Entry is not cacheable: 2407 * 2408 * Don't turn caching on again if this is a 2409 * modified emulation. This would be 2410 * inconsitent with the settings created by 2411 * pmap_vac_me_harder(). Otherwise, it's safe 2412 * to re-enable cacheing. 2413 * 2414 * There's no need to call pmap_vac_me_harder() 2415 * here: all pages are losing their write 2416 * permission. 2417 */ 2418 if (maskbits & PVF_WRITE) { 2419 npte |= pte_l2_s_cache_mode; 2420 pv->pv_flags &= ~PVF_NC; 2421 } 2422 } else 2423 if (l2pte_writable_p(opte)) { 2424 /* 2425 * Entry is writable/cacheable: check if pmap 2426 * is current if it is flush it, otherwise it 2427 * won't be in the cache 2428 */ 2429 pmap_cache_wbinv_page(pm, va, 2430 (maskbits & PVF_REF) != 0, 2431 oflags|PVF_WRITE); 2432 } 2433 #endif 2434 2435 /* make the pte read only */ 2436 npte = l2pte_set_readonly(npte); 2437 2438 pmap_acquire_page_lock(md); 2439 #ifdef MULTIPROCESSOR 2440 pv = pmap_find_pv(md, pm, va); 2441 #endif 2442 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2443 /* 2444 * Keep alias accounting up to date 2445 */ 2446 if (pm == pmap_kernel()) { 2447 md->krw_mappings--; 2448 md->kro_mappings++; 2449 } else { 2450 md->urw_mappings--; 2451 md->uro_mappings++; 2452 } 2453 #ifdef PMAP_CACHE_VIPT 2454 if (arm_cache_prefer_mask != 0) { 2455 if (md->urw_mappings + md->krw_mappings == 0) { 2456 md->pvh_attrs &= ~PVF_WRITE; 2457 } else { 2458 PMAP_VALIDATE_MD_PAGE(md); 2459 } 2460 } 2461 #ifndef ARM_MMU_EXTENDED 2462 if (want_syncicache) 2463 need_syncicache = true; 2464 need_vac_me_harder = true; 2465 #endif 2466 #endif /* PMAP_CACHE_VIPT */ 2467 } 2468 pmap_release_page_lock(md); 2469 } 2470 2471 if (maskbits & PVF_REF) { 2472 if (true 2473 #ifndef ARM_MMU_EXTENDED 2474 && (oflags & PVF_NC) == 0 2475 #endif 2476 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2477 && l2pte_valid_p(npte)) { 2478 #ifdef PMAP_CACHE_VIVT 2479 /* 2480 * Check npte here; we may have already 2481 * done the wbinv above, and the validity 2482 * of the PTE is the same for opte and 2483 * npte. 2484 */ 2485 pmap_cache_wbinv_page(pm, va, true, oflags); 2486 #endif 2487 } 2488 2489 /* 2490 * Make the PTE invalid so that we will take a 2491 * page fault the next time the mapping is 2492 * referenced. 2493 */ 2494 npte &= ~L2_TYPE_MASK; 2495 npte |= L2_TYPE_INV; 2496 } 2497 2498 if (npte != opte) { 2499 l2pte_set(ptep, npte, opte); 2500 PTE_SYNC(ptep); 2501 2502 /* Flush the TLB entry if a current pmap. */ 2503 pmap_tlb_flush_SE(pm, va, oflags); 2504 } 2505 2506 pmap_release_pmap_lock(pm); 2507 pmap_acquire_page_lock(md); 2508 2509 NPDEBUG(PDB_BITS, 2510 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2511 pm, va, opte, npte)); 2512 } 2513 2514 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2515 /* 2516 * If we need to sync the I-cache and we haven't done it yet, do it. 2517 */ 2518 if (need_syncicache) { 2519 pmap_release_page_lock(md); 2520 pmap_syncicache_page(md, pa); 2521 pmap_acquire_page_lock(md); 2522 PMAPCOUNT(exec_synced_clearbit); 2523 } 2524 2525 /* 2526 * If we are changing this to read-only, we need to call vac_me_harder 2527 * so we can change all the read-only pages to cacheable. We pretend 2528 * this as a page deletion. 2529 */ 2530 if (need_vac_me_harder) { 2531 if (md->pvh_attrs & PVF_NC) 2532 pmap_vac_me_harder(md, pa, NULL, 0); 2533 } 2534 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2535 } 2536 2537 /* 2538 * pmap_clean_page() 2539 * 2540 * This is a local function used to work out the best strategy to clean 2541 * a single page referenced by its entry in the PV table. It's used by 2542 * pmap_copy_page, pmap_zero page and maybe some others later on. 2543 * 2544 * Its policy is effectively: 2545 * o If there are no mappings, we don't bother doing anything with the cache. 2546 * o If there is one mapping, we clean just that page. 2547 * o If there are multiple mappings, we clean the entire cache. 2548 * 2549 * So that some functions can be further optimised, it returns 0 if it didn't 2550 * clean the entire cache, or 1 if it did. 2551 * 2552 * XXX One bug in this routine is that if the pv_entry has a single page 2553 * mapped at 0x00000000 a whole cache clean will be performed rather than 2554 * just the 1 page. Since this should not occur in everyday use and if it does 2555 * it will just result in not the most efficient clean for the page. 2556 */ 2557 #ifdef PMAP_CACHE_VIVT 2558 static bool 2559 pmap_clean_page(struct vm_page_md *md, bool is_src) 2560 { 2561 struct pv_entry *pv; 2562 pmap_t pm_to_clean = NULL; 2563 bool cache_needs_cleaning = false; 2564 vaddr_t page_to_clean = 0; 2565 u_int flags = 0; 2566 2567 /* 2568 * Since we flush the cache each time we change to a different 2569 * user vmspace, we only need to flush the page if it is in the 2570 * current pmap. 2571 */ 2572 KASSERT(pmap_page_locked_p(md)); 2573 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2574 if (pmap_is_current(pv->pv_pmap)) { 2575 flags |= pv->pv_flags; 2576 /* 2577 * The page is mapped non-cacheable in 2578 * this map. No need to flush the cache. 2579 */ 2580 if (pv->pv_flags & PVF_NC) { 2581 #ifdef DIAGNOSTIC 2582 KASSERT(!cache_needs_cleaning); 2583 #endif 2584 break; 2585 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2586 continue; 2587 if (cache_needs_cleaning) { 2588 page_to_clean = 0; 2589 break; 2590 } else { 2591 page_to_clean = pv->pv_va; 2592 pm_to_clean = pv->pv_pmap; 2593 } 2594 cache_needs_cleaning = true; 2595 } 2596 } 2597 2598 if (page_to_clean) { 2599 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2600 !is_src, flags | PVF_REF); 2601 } else if (cache_needs_cleaning) { 2602 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2603 2604 pmap_cache_wbinv_all(pm, flags); 2605 return true; 2606 } 2607 return false; 2608 } 2609 #endif 2610 2611 #ifdef PMAP_CACHE_VIPT 2612 /* 2613 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2614 * right cache alias to make sure we flush the right stuff. 2615 */ 2616 void 2617 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2618 { 2619 pmap_t kpm = pmap_kernel(); 2620 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2621 ? PAGE_SIZE 2622 : arm_pcache.icache_way_size; 2623 2624 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2625 md, md->pvh_attrs)); 2626 /* 2627 * No need to clean the page if it's non-cached. 2628 */ 2629 #ifndef ARM_MMU_EXTENDED 2630 if (md->pvh_attrs & PVF_NC) 2631 return; 2632 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2633 #endif 2634 2635 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2636 if (way_size == PAGE_SIZE) { 2637 vaddr_t vdstp = KERNEL_BASE + (pa - physical_start); 2638 cpu_icache_sync_range(vdstp, way_size); 2639 return; 2640 } 2641 #endif 2642 2643 /* 2644 * We don't worry about the color of the exec page, we map the 2645 * same page to pages in the way and then do the icache_sync on 2646 * the entire way making sure we are cleaned. 2647 */ 2648 pt_entry_t * const ptep = cpu_cdst_pte(0); 2649 const vaddr_t dstp = cpu_cdstp(0); 2650 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2651 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2652 2653 for (size_t i = 0, j = 0; i < way_size; 2654 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2655 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2656 /* 2657 * Set up a PTE with to flush these cache lines. 2658 */ 2659 l2pte_set(ptep + j, npte, 0); 2660 } 2661 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2662 2663 /* 2664 * Flush it. 2665 */ 2666 cpu_icache_sync_range(dstp, way_size); 2667 2668 for (size_t i = 0, j = 0; i < way_size; 2669 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2670 /* 2671 * Unmap the page(s). 2672 */ 2673 l2pte_reset(ptep + j); 2674 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2675 } 2676 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2677 2678 md->pvh_attrs |= PVF_EXEC; 2679 PMAPCOUNT(exec_synced); 2680 } 2681 2682 #ifndef ARM_MMU_EXTENDED 2683 void 2684 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2685 { 2686 vsize_t va_offset, end_va; 2687 bool wbinv_p; 2688 2689 if (arm_cache_prefer_mask == 0) 2690 return; 2691 2692 switch (flush) { 2693 case PMAP_FLUSH_PRIMARY: 2694 if (md->pvh_attrs & PVF_MULTCLR) { 2695 va_offset = 0; 2696 end_va = arm_cache_prefer_mask; 2697 md->pvh_attrs &= ~PVF_MULTCLR; 2698 PMAPCOUNT(vac_flush_lots); 2699 } else { 2700 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2701 end_va = va_offset; 2702 PMAPCOUNT(vac_flush_one); 2703 } 2704 /* 2705 * Mark that the page is no longer dirty. 2706 */ 2707 md->pvh_attrs &= ~PVF_DIRTY; 2708 wbinv_p = true; 2709 break; 2710 case PMAP_FLUSH_SECONDARY: 2711 va_offset = 0; 2712 end_va = arm_cache_prefer_mask; 2713 wbinv_p = true; 2714 md->pvh_attrs &= ~PVF_MULTCLR; 2715 PMAPCOUNT(vac_flush_lots); 2716 break; 2717 case PMAP_CLEAN_PRIMARY: 2718 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2719 end_va = va_offset; 2720 wbinv_p = false; 2721 /* 2722 * Mark that the page is no longer dirty. 2723 */ 2724 if ((md->pvh_attrs & PVF_DMOD) == 0) 2725 md->pvh_attrs &= ~PVF_DIRTY; 2726 PMAPCOUNT(vac_clean_one); 2727 break; 2728 default: 2729 return; 2730 } 2731 2732 KASSERT(!(md->pvh_attrs & PVF_NC)); 2733 2734 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2735 md, md->pvh_attrs)); 2736 2737 const size_t scache_line_size = arm_scache.dcache_line_size; 2738 2739 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2740 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2741 const vaddr_t dstp = cpu_cdstp(va_offset); 2742 const pt_entry_t opte = *ptep; 2743 2744 if (flush == PMAP_FLUSH_SECONDARY 2745 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2746 continue; 2747 2748 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2749 /* 2750 * Set up a PTE with the right coloring to flush 2751 * existing cache entries. 2752 */ 2753 const pt_entry_t npte = L2_S_PROTO 2754 | pa 2755 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2756 | pte_l2_s_cache_mode; 2757 l2pte_set(ptep, npte, opte); 2758 PTE_SYNC(ptep); 2759 2760 /* 2761 * Flush it. Make sure to flush secondary cache too since 2762 * bus_dma will ignore uncached pages. 2763 */ 2764 if (scache_line_size != 0) { 2765 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2766 if (wbinv_p) { 2767 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2768 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2769 } else { 2770 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2771 } 2772 } else { 2773 if (wbinv_p) { 2774 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2775 } else { 2776 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2777 } 2778 } 2779 2780 /* 2781 * Restore the page table entry since we might have interrupted 2782 * pmap_zero_page or pmap_copy_page which was already using 2783 * this pte. 2784 */ 2785 if (opte) { 2786 l2pte_set(ptep, opte, npte); 2787 } else { 2788 l2pte_reset(ptep); 2789 } 2790 PTE_SYNC(ptep); 2791 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2792 } 2793 } 2794 #endif /* ARM_MMU_EXTENDED */ 2795 #endif /* PMAP_CACHE_VIPT */ 2796 2797 /* 2798 * Routine: pmap_page_remove 2799 * Function: 2800 * Removes this physical page from 2801 * all physical maps in which it resides. 2802 * Reflects back modify bits to the pager. 2803 */ 2804 static void 2805 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2806 { 2807 struct l2_bucket *l2b; 2808 struct pv_entry *pv; 2809 pt_entry_t *ptep; 2810 #ifndef ARM_MMU_EXTENDED 2811 bool flush = false; 2812 #endif 2813 u_int flags = 0; 2814 2815 NPDEBUG(PDB_FOLLOW, 2816 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2817 pa)); 2818 2819 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2820 pmap_acquire_page_lock(md); 2821 if (*pvp == NULL) { 2822 #ifdef PMAP_CACHE_VIPT 2823 /* 2824 * We *know* the page contents are about to be replaced. 2825 * Discard the exec contents 2826 */ 2827 if (PV_IS_EXEC_P(md->pvh_attrs)) 2828 PMAPCOUNT(exec_discarded_page_protect); 2829 md->pvh_attrs &= ~PVF_EXEC; 2830 PMAP_VALIDATE_MD_PAGE(md); 2831 #endif 2832 pmap_release_page_lock(md); 2833 return; 2834 } 2835 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2836 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2837 #endif 2838 2839 /* 2840 * Clear alias counts 2841 */ 2842 #ifdef PMAP_CACHE_VIVT 2843 md->k_mappings = 0; 2844 #endif 2845 md->urw_mappings = md->uro_mappings = 0; 2846 2847 #ifdef PMAP_CACHE_VIVT 2848 pmap_clean_page(md, false); 2849 #endif 2850 2851 while ((pv = *pvp) != NULL) { 2852 pmap_t pm = pv->pv_pmap; 2853 #ifndef ARM_MMU_EXTENDED 2854 if (flush == false && pmap_is_current(pm)) 2855 flush = true; 2856 #endif 2857 2858 if (pm == pmap_kernel()) { 2859 #ifdef PMAP_CACHE_VIPT 2860 /* 2861 * If this was unmanaged mapping, it must be preserved. 2862 * Move it back on the list and advance the end-of-list 2863 * pointer. 2864 */ 2865 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2866 *pvp = pv; 2867 pvp = &SLIST_NEXT(pv, pv_link); 2868 continue; 2869 } 2870 if (pv->pv_flags & PVF_WRITE) 2871 md->krw_mappings--; 2872 else 2873 md->kro_mappings--; 2874 #endif 2875 PMAPCOUNT(kernel_unmappings); 2876 } 2877 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2878 PMAPCOUNT(unmappings); 2879 2880 pmap_release_page_lock(md); 2881 pmap_acquire_pmap_lock(pm); 2882 2883 #ifdef ARM_MMU_EXTENDED 2884 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2885 #endif 2886 2887 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2888 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2889 2890 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2891 2892 /* 2893 * Update statistics 2894 */ 2895 --pm->pm_stats.resident_count; 2896 2897 /* Wired bit */ 2898 if (pv->pv_flags & PVF_WIRED) 2899 --pm->pm_stats.wired_count; 2900 2901 flags |= pv->pv_flags; 2902 2903 /* 2904 * Invalidate the PTEs. 2905 */ 2906 l2pte_reset(ptep); 2907 PTE_SYNC_CURRENT(pm, ptep); 2908 if (pm != pmap_kernel()) { 2909 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2910 } 2911 pmap_release_pmap_lock(pm); 2912 2913 pool_put(&pmap_pv_pool, pv); 2914 pmap_acquire_page_lock(md); 2915 #ifdef MULTIPROCESSOR 2916 /* 2917 * Restart of the beginning of the list. 2918 */ 2919 pvp = &SLIST_FIRST(&md->pvh_list); 2920 #endif 2921 } 2922 /* 2923 * if we reach the end of the list and there are still mappings, they 2924 * might be able to be cached now. And they must be kernel mappings. 2925 */ 2926 if (!SLIST_EMPTY(&md->pvh_list)) { 2927 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2928 } 2929 2930 #ifdef PMAP_CACHE_VIPT 2931 /* 2932 * Its EXEC cache is now gone. 2933 */ 2934 if (PV_IS_EXEC_P(md->pvh_attrs)) 2935 PMAPCOUNT(exec_discarded_page_protect); 2936 md->pvh_attrs &= ~PVF_EXEC; 2937 KASSERT(md->urw_mappings == 0); 2938 KASSERT(md->uro_mappings == 0); 2939 #ifndef ARM_MMU_EXTENDED 2940 if (arm_cache_prefer_mask != 0) { 2941 if (md->krw_mappings == 0) 2942 md->pvh_attrs &= ~PVF_WRITE; 2943 PMAP_VALIDATE_MD_PAGE(md); 2944 } 2945 #endif /* ARM_MMU_EXTENDED */ 2946 #endif /* PMAP_CACHE_VIPT */ 2947 pmap_release_page_lock(md); 2948 2949 #ifndef ARM_MMU_EXTENDED 2950 if (flush) { 2951 /* 2952 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2953 * would need a subsequent call to pmap_update() to ensure 2954 * curpm->pm_cstate.cs_all is reset. Our callers are not 2955 * required to do that (see pmap(9)), so we can't modify 2956 * the current pmap's state. 2957 */ 2958 if (PV_BEEN_EXECD(flags)) 2959 cpu_tlb_flushID(); 2960 else 2961 cpu_tlb_flushD(); 2962 } 2963 cpu_cpwait(); 2964 #endif /* ARM_MMU_EXTENDED */ 2965 } 2966 2967 /* 2968 * pmap_t pmap_create(void) 2969 * 2970 * Create a new pmap structure from scratch. 2971 */ 2972 pmap_t 2973 pmap_create(void) 2974 { 2975 pmap_t pm; 2976 2977 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2978 2979 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2980 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2981 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2982 2983 pm->pm_stats.wired_count = 0; 2984 pm->pm_stats.resident_count = 1; 2985 #ifdef ARM_MMU_EXTENDED 2986 #ifdef MULTIPROCESSOR 2987 kcpuset_create(&pm->pm_active, true); 2988 kcpuset_create(&pm->pm_onproc, true); 2989 #endif 2990 #else 2991 pm->pm_cstate.cs_all = 0; 2992 #endif 2993 pmap_alloc_l1(pm); 2994 2995 /* 2996 * Note: The pool cache ensures that the pm_l2[] array is already 2997 * initialised to zero. 2998 */ 2999 3000 pmap_pinit(pm); 3001 3002 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3003 3004 return (pm); 3005 } 3006 3007 u_int 3008 arm32_mmap_flags(paddr_t pa) 3009 { 3010 /* 3011 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3012 * and we're using the upper bits in page numbers to pass flags around 3013 * so we might as well use the same bits 3014 */ 3015 return (u_int)pa & PMAP_MD_MASK; 3016 } 3017 /* 3018 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3019 * u_int flags) 3020 * 3021 * Insert the given physical page (p) at 3022 * the specified virtual address (v) in the 3023 * target physical map with the protection requested. 3024 * 3025 * NB: This is the only routine which MAY NOT lazy-evaluate 3026 * or lose information. That is, this routine must actually 3027 * insert this page into the given map NOW. 3028 */ 3029 int 3030 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3031 { 3032 struct l2_bucket *l2b; 3033 struct vm_page *pg, *opg; 3034 u_int nflags; 3035 u_int oflags; 3036 const bool kpm_p = (pm == pmap_kernel()); 3037 #ifdef ARM_HAS_VBAR 3038 const bool vector_page_p = false; 3039 #else 3040 const bool vector_page_p = (va == vector_page); 3041 #endif 3042 3043 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3044 3045 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot #x", 3046 pm, va, pa, prot); 3047 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3048 3049 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3050 KDASSERT(((va | pa) & PGOFSET) == 0); 3051 3052 /* 3053 * Get a pointer to the page. Later on in this function, we 3054 * test for a managed page by checking pg != NULL. 3055 */ 3056 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3057 3058 nflags = 0; 3059 if (prot & VM_PROT_WRITE) 3060 nflags |= PVF_WRITE; 3061 if (prot & VM_PROT_EXECUTE) 3062 nflags |= PVF_EXEC; 3063 if (flags & PMAP_WIRED) 3064 nflags |= PVF_WIRED; 3065 3066 pmap_acquire_pmap_lock(pm); 3067 3068 /* 3069 * Fetch the L2 bucket which maps this page, allocating one if 3070 * necessary for user pmaps. 3071 */ 3072 if (kpm_p) { 3073 l2b = pmap_get_l2_bucket(pm, va); 3074 } else { 3075 l2b = pmap_alloc_l2_bucket(pm, va); 3076 } 3077 if (l2b == NULL) { 3078 if (flags & PMAP_CANFAIL) { 3079 pmap_release_pmap_lock(pm); 3080 return (ENOMEM); 3081 } 3082 panic("pmap_enter: failed to allocate L2 bucket"); 3083 } 3084 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3085 const pt_entry_t opte = *ptep; 3086 pt_entry_t npte = pa; 3087 oflags = 0; 3088 3089 if (opte) { 3090 /* 3091 * There is already a mapping at this address. 3092 * If the physical address is different, lookup the 3093 * vm_page. 3094 */ 3095 if (l2pte_pa(opte) != pa) 3096 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3097 else 3098 opg = pg; 3099 } else 3100 opg = NULL; 3101 3102 if (pg) { 3103 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3104 3105 /* 3106 * This is to be a managed mapping. 3107 */ 3108 pmap_acquire_page_lock(md); 3109 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3110 /* 3111 * - The access type indicates that we don't need 3112 * to do referenced emulation. 3113 * OR 3114 * - The physical page has already been referenced 3115 * so no need to re-do referenced emulation here. 3116 */ 3117 npte |= l2pte_set_readonly(L2_S_PROTO); 3118 3119 nflags |= PVF_REF; 3120 3121 if ((prot & VM_PROT_WRITE) != 0 && 3122 ((flags & VM_PROT_WRITE) != 0 || 3123 (md->pvh_attrs & PVF_MOD) != 0)) { 3124 /* 3125 * This is a writable mapping, and the 3126 * page's mod state indicates it has 3127 * already been modified. Make it 3128 * writable from the outset. 3129 */ 3130 npte = l2pte_set_writable(npte); 3131 nflags |= PVF_MOD; 3132 } 3133 3134 #ifdef ARM_MMU_EXTENDED 3135 /* 3136 * If the page has been cleaned, then the pvh_attrs 3137 * will have PVF_EXEC set, so mark it execute so we 3138 * don't get an access fault when trying to execute 3139 * from it. 3140 */ 3141 if (md->pvh_attrs & nflags & PVF_EXEC) { 3142 npte &= ~L2_XS_XN; 3143 } 3144 #endif 3145 } else { 3146 /* 3147 * Need to do page referenced emulation. 3148 */ 3149 npte |= L2_TYPE_INV; 3150 } 3151 3152 if (flags & ARM32_MMAP_WRITECOMBINE) { 3153 npte |= pte_l2_s_wc_mode; 3154 } else 3155 npte |= pte_l2_s_cache_mode; 3156 3157 if (pg == opg) { 3158 /* 3159 * We're changing the attrs of an existing mapping. 3160 */ 3161 oflags = pmap_modify_pv(md, pa, pm, va, 3162 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3163 PVF_MOD | PVF_REF, nflags); 3164 3165 #ifdef PMAP_CACHE_VIVT 3166 /* 3167 * We may need to flush the cache if we're 3168 * doing rw-ro... 3169 */ 3170 if (pm->pm_cstate.cs_cache_d && 3171 (oflags & PVF_NC) == 0 && 3172 l2pte_writable_p(opte) && 3173 (prot & VM_PROT_WRITE) == 0) 3174 cpu_dcache_wb_range(va, PAGE_SIZE); 3175 #endif 3176 } else { 3177 struct pv_entry *pv; 3178 /* 3179 * New mapping, or changing the backing page 3180 * of an existing mapping. 3181 */ 3182 if (opg) { 3183 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3184 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3185 3186 /* 3187 * Replacing an existing mapping with a new one. 3188 * It is part of our managed memory so we 3189 * must remove it from the PV list 3190 */ 3191 pv = pmap_remove_pv(omd, opa, pm, va); 3192 pmap_vac_me_harder(omd, opa, pm, 0); 3193 oflags = pv->pv_flags; 3194 3195 #ifdef PMAP_CACHE_VIVT 3196 /* 3197 * If the old mapping was valid (ref/mod 3198 * emulation creates 'invalid' mappings 3199 * initially) then make sure to frob 3200 * the cache. 3201 */ 3202 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3203 pmap_cache_wbinv_page(pm, va, true, 3204 oflags); 3205 } 3206 #endif 3207 } else { 3208 pmap_release_page_lock(md); 3209 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3210 if (pv == NULL) { 3211 pmap_release_pmap_lock(pm); 3212 if ((flags & PMAP_CANFAIL) == 0) 3213 panic("pmap_enter: " 3214 "no pv entries"); 3215 3216 if (pm != pmap_kernel()) 3217 pmap_free_l2_bucket(pm, l2b, 0); 3218 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3219 0, 0, 0, 0); 3220 return (ENOMEM); 3221 } 3222 pmap_acquire_page_lock(md); 3223 } 3224 3225 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3226 } 3227 pmap_release_page_lock(md); 3228 } else { 3229 /* 3230 * We're mapping an unmanaged page. 3231 * These are always readable, and possibly writable, from 3232 * the get go as we don't need to track ref/mod status. 3233 */ 3234 npte |= l2pte_set_readonly(L2_S_PROTO); 3235 if (prot & VM_PROT_WRITE) 3236 npte = l2pte_set_writable(npte); 3237 3238 /* 3239 * Make sure the vector table is mapped cacheable 3240 */ 3241 if ((vector_page_p && !kpm_p) 3242 || (flags & ARM32_MMAP_CACHEABLE)) { 3243 npte |= pte_l2_s_cache_mode; 3244 #ifdef ARM_MMU_EXTENDED 3245 npte &= ~L2_XS_XN; /* and executable */ 3246 #endif 3247 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3248 npte |= pte_l2_s_wc_mode; 3249 } 3250 if (opg) { 3251 /* 3252 * Looks like there's an existing 'managed' mapping 3253 * at this address. 3254 */ 3255 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3256 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3257 3258 pmap_acquire_page_lock(omd); 3259 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3260 pmap_vac_me_harder(omd, opa, pm, 0); 3261 oflags = pv->pv_flags; 3262 pmap_release_page_lock(omd); 3263 3264 #ifdef PMAP_CACHE_VIVT 3265 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3266 pmap_cache_wbinv_page(pm, va, true, oflags); 3267 } 3268 #endif 3269 pool_put(&pmap_pv_pool, pv); 3270 } 3271 } 3272 3273 /* 3274 * Make sure userland mappings get the right permissions 3275 */ 3276 if (!vector_page_p && !kpm_p) { 3277 npte |= L2_S_PROT_U; 3278 #ifdef ARM_MMU_EXTENDED 3279 npte |= L2_XS_nG; /* user pages are not global */ 3280 #endif 3281 } 3282 3283 /* 3284 * Keep the stats up to date 3285 */ 3286 if (opte == 0) { 3287 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3288 pm->pm_stats.resident_count++; 3289 } 3290 3291 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3292 3293 #if defined(ARM_MMU_EXTENDED) 3294 /* 3295 * If exec protection was requested but the page hasn't been synced, 3296 * sync it now and allow execution from it. 3297 */ 3298 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3299 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3300 npte &= ~L2_XS_XN; 3301 pmap_syncicache_page(md, pa); 3302 PMAPCOUNT(exec_synced_map); 3303 } 3304 #endif 3305 /* 3306 * If this is just a wiring change, the two PTEs will be 3307 * identical, so there's no need to update the page table. 3308 */ 3309 if (npte != opte) { 3310 3311 l2pte_set(ptep, npte, opte); 3312 PTE_SYNC(ptep); 3313 #ifndef ARM_MMU_EXTENDED 3314 bool is_cached = pmap_is_cached(pm); 3315 if (is_cached) { 3316 /* 3317 * We only need to frob the cache/tlb if this pmap 3318 * is current 3319 */ 3320 if (!vector_page_p && l2pte_valid_p(npte)) { 3321 /* 3322 * This mapping is likely to be accessed as 3323 * soon as we return to userland. Fix up the 3324 * L1 entry to avoid taking another 3325 * page/domain fault. 3326 */ 3327 pd_entry_t *pdep = pmap_l1_kva(pm) 3328 + l1pte_index(va); 3329 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3330 | L1_C_DOM(pmap_domain(pm)); 3331 if (*pdep != pde) { 3332 l1pte_setone(pdep, pde); 3333 PTE_SYNC(pdep); 3334 } 3335 } 3336 } 3337 #endif /* !ARMM_MMU_EXTENDED */ 3338 3339 pmap_tlb_flush_SE(pm, va, oflags); 3340 3341 #ifndef ARM_MMU_EXTENDED 3342 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3343 is_cached, pm->pm_cstate.cs_all, 0, 0); 3344 3345 if (pg != NULL) { 3346 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3347 3348 pmap_acquire_page_lock(md); 3349 pmap_vac_me_harder(md, pa, pm, va); 3350 pmap_release_page_lock(md); 3351 } 3352 #endif 3353 } 3354 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3355 if (pg) { 3356 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3357 3358 pmap_acquire_page_lock(md); 3359 #ifndef ARM_MMU_EXTENDED 3360 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3361 #endif 3362 PMAP_VALIDATE_MD_PAGE(md); 3363 pmap_release_page_lock(md); 3364 } 3365 #endif 3366 3367 pmap_release_pmap_lock(pm); 3368 3369 return (0); 3370 } 3371 3372 /* 3373 * pmap_remove() 3374 * 3375 * pmap_remove is responsible for nuking a number of mappings for a range 3376 * of virtual address space in the current pmap. To do this efficiently 3377 * is interesting, because in a number of cases a wide virtual address 3378 * range may be supplied that contains few actual mappings. So, the 3379 * optimisations are: 3380 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3381 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3382 * maybe do just a partial cache clean. This path of execution is 3383 * complicated by the fact that the cache must be flushed _before_ 3384 * the PTE is nuked, being a VAC :-) 3385 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3386 * all invalidations until pmap_update(), since pmap_remove_all() has 3387 * already flushed the cache. 3388 * 4. Maybe later fast-case a single page, but I don't think this is 3389 * going to make _that_ much difference overall. 3390 */ 3391 3392 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3393 3394 void 3395 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3396 { 3397 vaddr_t next_bucket; 3398 u_int cleanlist_idx, total, cnt; 3399 struct { 3400 vaddr_t va; 3401 pt_entry_t *ptep; 3402 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3403 u_int mappings; 3404 3405 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3406 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3407 3408 /* 3409 * we lock in the pmap => pv_head direction 3410 */ 3411 pmap_acquire_pmap_lock(pm); 3412 3413 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3414 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3415 #ifndef ARM_MMU_EXTENDED 3416 if (pm->pm_cstate.cs_tlb == 0) 3417 pm->pm_remove_all = true; 3418 #endif 3419 } else 3420 cleanlist_idx = 0; 3421 3422 total = 0; 3423 3424 while (sva < eva) { 3425 /* 3426 * Do one L2 bucket's worth at a time. 3427 */ 3428 next_bucket = L2_NEXT_BUCKET_VA(sva); 3429 if (next_bucket > eva) 3430 next_bucket = eva; 3431 3432 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3433 if (l2b == NULL) { 3434 sva = next_bucket; 3435 continue; 3436 } 3437 3438 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3439 3440 for (mappings = 0; 3441 sva < next_bucket; 3442 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3443 pt_entry_t opte = *ptep; 3444 3445 if (opte == 0) { 3446 /* Nothing here, move along */ 3447 continue; 3448 } 3449 3450 u_int flags = PVF_REF; 3451 paddr_t pa = l2pte_pa(opte); 3452 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3453 3454 /* 3455 * Update flags. In a number of circumstances, 3456 * we could cluster a lot of these and do a 3457 * number of sequential pages in one go. 3458 */ 3459 if (pg != NULL) { 3460 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3461 struct pv_entry *pv; 3462 3463 pmap_acquire_page_lock(md); 3464 pv = pmap_remove_pv(md, pa, pm, sva); 3465 pmap_vac_me_harder(md, pa, pm, 0); 3466 pmap_release_page_lock(md); 3467 if (pv != NULL) { 3468 if (pm->pm_remove_all == false) { 3469 flags = pv->pv_flags; 3470 } 3471 pool_put(&pmap_pv_pool, pv); 3472 } 3473 } 3474 mappings += PAGE_SIZE / L2_S_SIZE; 3475 3476 if (!l2pte_valid_p(opte)) { 3477 /* 3478 * Ref/Mod emulation is still active for this 3479 * mapping, therefore it is has not yet been 3480 * accessed. No need to frob the cache/tlb. 3481 */ 3482 l2pte_reset(ptep); 3483 PTE_SYNC_CURRENT(pm, ptep); 3484 continue; 3485 } 3486 3487 #ifdef ARM_MMU_EXTENDED 3488 if (pm == pmap_kernel()) { 3489 l2pte_reset(ptep); 3490 PTE_SYNC(ptep); 3491 pmap_tlb_flush_SE(pm, sva, flags); 3492 continue; 3493 } 3494 #endif 3495 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3496 /* Add to the clean list. */ 3497 cleanlist[cleanlist_idx].ptep = ptep; 3498 cleanlist[cleanlist_idx].va = 3499 sva | (flags & PVF_EXEC); 3500 cleanlist_idx++; 3501 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3502 /* Nuke everything if needed. */ 3503 #ifdef PMAP_CACHE_VIVT 3504 pmap_cache_wbinv_all(pm, PVF_EXEC); 3505 #endif 3506 /* 3507 * Roll back the previous PTE list, 3508 * and zero out the current PTE. 3509 */ 3510 for (cnt = 0; 3511 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3512 l2pte_reset(cleanlist[cnt].ptep); 3513 PTE_SYNC(cleanlist[cnt].ptep); 3514 } 3515 l2pte_reset(ptep); 3516 PTE_SYNC(ptep); 3517 cleanlist_idx++; 3518 pm->pm_remove_all = true; 3519 } else { 3520 l2pte_reset(ptep); 3521 PTE_SYNC(ptep); 3522 if (pm->pm_remove_all == false) { 3523 pmap_tlb_flush_SE(pm, sva, flags); 3524 } 3525 } 3526 } 3527 3528 /* 3529 * Deal with any left overs 3530 */ 3531 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3532 total += cleanlist_idx; 3533 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3534 #ifdef ARM_MMU_EXTENDED 3535 vaddr_t clva = cleanlist[cnt].va; 3536 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3537 #else 3538 vaddr_t va = cleanlist[cnt].va; 3539 if (pm->pm_cstate.cs_all != 0) { 3540 vaddr_t clva = va & ~PAGE_MASK; 3541 u_int flags = va & PVF_EXEC; 3542 #ifdef PMAP_CACHE_VIVT 3543 pmap_cache_wbinv_page(pm, clva, true, 3544 PVF_REF | PVF_WRITE | flags); 3545 #endif 3546 pmap_tlb_flush_SE(pm, clva, 3547 PVF_REF | flags); 3548 } 3549 #endif /* ARM_MMU_EXTENDED */ 3550 l2pte_reset(cleanlist[cnt].ptep); 3551 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3552 } 3553 3554 /* 3555 * If it looks like we're removing a whole bunch 3556 * of mappings, it's faster to just write-back 3557 * the whole cache now and defer TLB flushes until 3558 * pmap_update() is called. 3559 */ 3560 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3561 cleanlist_idx = 0; 3562 else { 3563 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3564 #ifdef PMAP_CACHE_VIVT 3565 pmap_cache_wbinv_all(pm, PVF_EXEC); 3566 #endif 3567 pm->pm_remove_all = true; 3568 } 3569 } 3570 3571 if (pm != pmap_kernel()) 3572 pmap_free_l2_bucket(pm, l2b, mappings); 3573 pm->pm_stats.resident_count -= mappings; 3574 } 3575 3576 pmap_release_pmap_lock(pm); 3577 } 3578 3579 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3580 static struct pv_entry * 3581 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3582 { 3583 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3584 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3585 struct pv_entry *pv; 3586 3587 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3588 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3589 KASSERT(pmap_page_locked_p(md)); 3590 3591 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3592 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3593 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3594 3595 /* 3596 * If we are removing a writeable mapping to a cached exec page, 3597 * if it's the last mapping then clear it execness other sync 3598 * the page to the icache. 3599 */ 3600 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3601 && (pv->pv_flags & PVF_WRITE) != 0) { 3602 if (SLIST_EMPTY(&md->pvh_list)) { 3603 md->pvh_attrs &= ~PVF_EXEC; 3604 PMAPCOUNT(exec_discarded_kremove); 3605 } else { 3606 pmap_syncicache_page(md, pa); 3607 PMAPCOUNT(exec_synced_kremove); 3608 } 3609 } 3610 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3611 3612 return pv; 3613 } 3614 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3615 3616 /* 3617 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3618 * 3619 * We assume there is already sufficient KVM space available 3620 * to do this, as we can't allocate L2 descriptor tables/metadata 3621 * from here. 3622 */ 3623 void 3624 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3625 { 3626 #ifdef PMAP_CACHE_VIVT 3627 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3628 #endif 3629 #ifdef PMAP_CACHE_VIPT 3630 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3631 struct vm_page *opg; 3632 #ifndef ARM_MMU_EXTENDED 3633 struct pv_entry *pv = NULL; 3634 #endif 3635 #endif 3636 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3637 3638 UVMHIST_FUNC(__func__); 3639 3640 if (pmap_initialized) { 3641 UVMHIST_CALLED(maphist); 3642 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3643 va, pa, prot, flags); 3644 } 3645 3646 pmap_t kpm = pmap_kernel(); 3647 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3648 const size_t l1slot __diagused = l1pte_index(va); 3649 KASSERTMSG(l2b != NULL, 3650 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3651 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3652 kpm->pm_l2[L2_IDX(l1slot)] 3653 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3654 : NULL, 3655 kpm->pm_l2[L2_IDX(l1slot)] 3656 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3657 : NULL); 3658 KASSERT(l2b->l2b_kva != NULL); 3659 3660 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3661 const pt_entry_t opte = *ptep; 3662 3663 if (opte == 0) { 3664 PMAPCOUNT(kenter_mappings); 3665 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3666 } else { 3667 PMAPCOUNT(kenter_remappings); 3668 #ifdef PMAP_CACHE_VIPT 3669 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3670 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3671 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3672 #endif 3673 if (opg && arm_cache_prefer_mask != 0) { 3674 KASSERT(opg != pg); 3675 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3676 KASSERT((flags & PMAP_KMPAGE) == 0); 3677 #ifndef ARM_MMU_EXTENDED 3678 pmap_acquire_page_lock(omd); 3679 pv = pmap_kremove_pg(opg, va); 3680 pmap_release_page_lock(omd); 3681 #endif 3682 } 3683 #endif 3684 if (l2pte_valid_p(opte)) { 3685 #ifdef PMAP_CACHE_VIVT 3686 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3687 #endif 3688 cpu_tlb_flushD_SE(va); 3689 cpu_cpwait(); 3690 } 3691 } 3692 3693 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3694 | ((flags & PMAP_NOCACHE) 3695 ? 0 3696 : ((flags & PMAP_PTE) 3697 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3698 #ifdef ARM_MMU_EXTENDED 3699 if (prot & VM_PROT_EXECUTE) 3700 npte &= ~L2_XS_XN; 3701 #endif 3702 l2pte_set(ptep, npte, opte); 3703 PTE_SYNC(ptep); 3704 3705 if (pg) { 3706 if (flags & PMAP_KMPAGE) { 3707 KASSERT(md->urw_mappings == 0); 3708 KASSERT(md->uro_mappings == 0); 3709 KASSERT(md->krw_mappings == 0); 3710 KASSERT(md->kro_mappings == 0); 3711 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3712 KASSERT(pv == NULL); 3713 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3714 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3715 /* if there is a color conflict, evict from cache. */ 3716 if (pmap_is_page_colored_p(md) 3717 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3718 PMAPCOUNT(vac_color_change); 3719 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3720 } else if (md->pvh_attrs & PVF_MULTCLR) { 3721 /* 3722 * If this page has multiple colors, expunge 3723 * them. 3724 */ 3725 PMAPCOUNT(vac_flush_lots2); 3726 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3727 } 3728 /* 3729 * Since this is a KMPAGE, there can be no contention 3730 * for this page so don't lock it. 3731 */ 3732 md->pvh_attrs &= PAGE_SIZE - 1; 3733 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3734 | (va & arm_cache_prefer_mask); 3735 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3736 md->pvh_attrs |= PVF_KMPAGE; 3737 #endif 3738 atomic_inc_32(&pmap_kmpages); 3739 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3740 } else if (arm_cache_prefer_mask != 0) { 3741 if (pv == NULL) { 3742 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3743 KASSERT(pv != NULL); 3744 } 3745 pmap_acquire_page_lock(md); 3746 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3747 PVF_WIRED | PVF_KENTRY 3748 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3749 if ((prot & VM_PROT_WRITE) 3750 && !(md->pvh_attrs & PVF_NC)) 3751 md->pvh_attrs |= PVF_DIRTY; 3752 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3753 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3754 pmap_release_page_lock(md); 3755 #endif 3756 } 3757 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3758 } else { 3759 if (pv != NULL) 3760 pool_put(&pmap_pv_pool, pv); 3761 #endif 3762 } 3763 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3764 if (pmap_initialized) { 3765 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3766 ptep, opte, npte, 0); 3767 } 3768 3769 } 3770 3771 void 3772 pmap_kremove(vaddr_t va, vsize_t len) 3773 { 3774 #ifdef UVMHIST 3775 u_int total_mappings = 0; 3776 #endif 3777 3778 PMAPCOUNT(kenter_unmappings); 3779 3780 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3781 3782 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3783 3784 const vaddr_t eva = va + len; 3785 3786 while (va < eva) { 3787 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3788 if (next_bucket > eva) 3789 next_bucket = eva; 3790 3791 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3792 KDASSERT(l2b != NULL); 3793 3794 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3795 pt_entry_t *ptep = sptep; 3796 u_int mappings = 0; 3797 3798 while (va < next_bucket) { 3799 const pt_entry_t opte = *ptep; 3800 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3801 if (opg != NULL) { 3802 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3803 3804 if (omd->pvh_attrs & PVF_KMPAGE) { 3805 KASSERT(omd->urw_mappings == 0); 3806 KASSERT(omd->uro_mappings == 0); 3807 KASSERT(omd->krw_mappings == 0); 3808 KASSERT(omd->kro_mappings == 0); 3809 omd->pvh_attrs &= ~PVF_KMPAGE; 3810 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3811 if (arm_cache_prefer_mask != 0) { 3812 omd->pvh_attrs &= ~PVF_WRITE; 3813 } 3814 #endif 3815 atomic_dec_32(&pmap_kmpages); 3816 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3817 } else if (arm_cache_prefer_mask != 0) { 3818 pmap_acquire_page_lock(omd); 3819 pool_put(&pmap_pv_pool, 3820 pmap_kremove_pg(opg, va)); 3821 pmap_release_page_lock(omd); 3822 #endif 3823 } 3824 } 3825 if (l2pte_valid_p(opte)) { 3826 #ifdef PMAP_CACHE_VIVT 3827 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3828 #endif 3829 cpu_tlb_flushD_SE(va); 3830 } 3831 if (opte) { 3832 l2pte_reset(ptep); 3833 mappings += PAGE_SIZE / L2_S_SIZE; 3834 } 3835 va += PAGE_SIZE; 3836 ptep += PAGE_SIZE / L2_S_SIZE; 3837 } 3838 KDASSERT(mappings <= l2b->l2b_occupancy); 3839 l2b->l2b_occupancy -= mappings; 3840 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3841 #ifdef UVMHIST 3842 total_mappings += mappings; 3843 #endif 3844 } 3845 cpu_cpwait(); 3846 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3847 total_mappings, 0, 0, 0); 3848 } 3849 3850 bool 3851 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3852 { 3853 struct l2_dtable *l2; 3854 pd_entry_t *pdep, pde; 3855 pt_entry_t *ptep, pte; 3856 paddr_t pa; 3857 u_int l1slot; 3858 3859 pmap_acquire_pmap_lock(pm); 3860 3861 l1slot = l1pte_index(va); 3862 pdep = pmap_l1_kva(pm) + l1slot; 3863 pde = *pdep; 3864 3865 if (l1pte_section_p(pde)) { 3866 /* 3867 * These should only happen for pmap_kernel() 3868 */ 3869 KDASSERT(pm == pmap_kernel()); 3870 pmap_release_pmap_lock(pm); 3871 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3872 if (l1pte_supersection_p(pde)) { 3873 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3874 } else 3875 #endif 3876 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3877 } else { 3878 /* 3879 * Note that we can't rely on the validity of the L1 3880 * descriptor as an indication that a mapping exists. 3881 * We have to look it up in the L2 dtable. 3882 */ 3883 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3884 3885 if (l2 == NULL || 3886 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3887 pmap_release_pmap_lock(pm); 3888 return false; 3889 } 3890 3891 ptep = &ptep[l2pte_index(va)]; 3892 pte = *ptep; 3893 pmap_release_pmap_lock(pm); 3894 3895 if (pte == 0) 3896 return false; 3897 3898 switch (pte & L2_TYPE_MASK) { 3899 case L2_TYPE_L: 3900 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3901 break; 3902 3903 default: 3904 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3905 break; 3906 } 3907 } 3908 3909 if (pap != NULL) 3910 *pap = pa; 3911 3912 return true; 3913 } 3914 3915 void 3916 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3917 { 3918 struct l2_bucket *l2b; 3919 vaddr_t next_bucket; 3920 3921 NPDEBUG(PDB_PROTECT, 3922 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3923 pm, sva, eva, prot)); 3924 3925 if ((prot & VM_PROT_READ) == 0) { 3926 pmap_remove(pm, sva, eva); 3927 return; 3928 } 3929 3930 if (prot & VM_PROT_WRITE) { 3931 /* 3932 * If this is a read->write transition, just ignore it and let 3933 * uvm_fault() take care of it later. 3934 */ 3935 return; 3936 } 3937 3938 pmap_acquire_pmap_lock(pm); 3939 3940 const bool flush = eva - sva >= PAGE_SIZE * 4; 3941 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3942 u_int flags = 0; 3943 3944 while (sva < eva) { 3945 next_bucket = L2_NEXT_BUCKET_VA(sva); 3946 if (next_bucket > eva) 3947 next_bucket = eva; 3948 3949 l2b = pmap_get_l2_bucket(pm, sva); 3950 if (l2b == NULL) { 3951 sva = next_bucket; 3952 continue; 3953 } 3954 3955 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3956 3957 while (sva < next_bucket) { 3958 const pt_entry_t opte = *ptep; 3959 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3960 struct vm_page *pg; 3961 u_int f; 3962 3963 #ifdef PMAP_CACHE_VIVT 3964 /* 3965 * OK, at this point, we know we're doing 3966 * write-protect operation. If the pmap is 3967 * active, write-back the page. 3968 */ 3969 pmap_cache_wbinv_page(pm, sva, false, 3970 PVF_REF | PVF_WRITE); 3971 #endif 3972 3973 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3974 pt_entry_t npte = l2pte_set_readonly(opte); 3975 l2pte_set(ptep, npte, opte); 3976 PTE_SYNC(ptep); 3977 3978 if (pg != NULL) { 3979 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3980 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3981 3982 pmap_acquire_page_lock(md); 3983 f = pmap_modify_pv(md, pa, pm, sva, 3984 clr_mask, 0); 3985 pmap_vac_me_harder(md, pa, pm, sva); 3986 pmap_release_page_lock(md); 3987 } else { 3988 f = PVF_REF | PVF_EXEC; 3989 } 3990 3991 if (flush) { 3992 flags |= f; 3993 } else { 3994 pmap_tlb_flush_SE(pm, sva, f); 3995 } 3996 } 3997 3998 sva += PAGE_SIZE; 3999 ptep += PAGE_SIZE / L2_S_SIZE; 4000 } 4001 } 4002 4003 if (flush) { 4004 if (PV_BEEN_EXECD(flags)) { 4005 pmap_tlb_flushID(pm); 4006 } else if (PV_BEEN_REFD(flags)) { 4007 pmap_tlb_flushD(pm); 4008 } 4009 } 4010 4011 pmap_release_pmap_lock(pm); 4012 } 4013 4014 void 4015 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4016 { 4017 struct l2_bucket *l2b; 4018 pt_entry_t *ptep; 4019 vaddr_t next_bucket; 4020 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4021 4022 NPDEBUG(PDB_EXEC, 4023 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4024 pm, sva, eva)); 4025 4026 pmap_acquire_pmap_lock(pm); 4027 4028 while (sva < eva) { 4029 next_bucket = L2_NEXT_BUCKET_VA(sva); 4030 if (next_bucket > eva) 4031 next_bucket = eva; 4032 4033 l2b = pmap_get_l2_bucket(pm, sva); 4034 if (l2b == NULL) { 4035 sva = next_bucket; 4036 continue; 4037 } 4038 4039 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4040 sva < next_bucket; 4041 sva += page_size, 4042 ptep += PAGE_SIZE / L2_S_SIZE, 4043 page_size = PAGE_SIZE) { 4044 if (l2pte_valid_p(*ptep)) { 4045 cpu_icache_sync_range(sva, 4046 min(page_size, eva - sva)); 4047 } 4048 } 4049 } 4050 4051 pmap_release_pmap_lock(pm); 4052 } 4053 4054 void 4055 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4056 { 4057 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4058 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4059 4060 NPDEBUG(PDB_PROTECT, 4061 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4062 md, pa, prot)); 4063 4064 switch(prot) { 4065 case VM_PROT_READ|VM_PROT_WRITE: 4066 #if defined(ARM_MMU_EXTENDED) 4067 pmap_acquire_page_lock(md); 4068 pmap_clearbit(md, pa, PVF_EXEC); 4069 pmap_release_page_lock(md); 4070 break; 4071 #endif 4072 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4073 break; 4074 4075 case VM_PROT_READ: 4076 #if defined(ARM_MMU_EXTENDED) 4077 pmap_acquire_page_lock(md); 4078 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4079 pmap_release_page_lock(md); 4080 break; 4081 #endif 4082 case VM_PROT_READ|VM_PROT_EXECUTE: 4083 pmap_acquire_page_lock(md); 4084 pmap_clearbit(md, pa, PVF_WRITE); 4085 pmap_release_page_lock(md); 4086 break; 4087 4088 default: 4089 pmap_page_remove(md, pa); 4090 break; 4091 } 4092 } 4093 4094 /* 4095 * pmap_clear_modify: 4096 * 4097 * Clear the "modified" attribute for a page. 4098 */ 4099 bool 4100 pmap_clear_modify(struct vm_page *pg) 4101 { 4102 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4103 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4104 bool rv; 4105 4106 pmap_acquire_page_lock(md); 4107 4108 if (md->pvh_attrs & PVF_MOD) { 4109 rv = true; 4110 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4111 /* 4112 * If we are going to clear the modified bit and there are 4113 * no other modified bits set, flush the page to memory and 4114 * mark it clean. 4115 */ 4116 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4117 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4118 #endif 4119 pmap_clearbit(md, pa, PVF_MOD); 4120 } else { 4121 rv = false; 4122 } 4123 pmap_release_page_lock(md); 4124 4125 return rv; 4126 } 4127 4128 /* 4129 * pmap_clear_reference: 4130 * 4131 * Clear the "referenced" attribute for a page. 4132 */ 4133 bool 4134 pmap_clear_reference(struct vm_page *pg) 4135 { 4136 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4137 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4138 bool rv; 4139 4140 pmap_acquire_page_lock(md); 4141 4142 if (md->pvh_attrs & PVF_REF) { 4143 rv = true; 4144 pmap_clearbit(md, pa, PVF_REF); 4145 } else { 4146 rv = false; 4147 } 4148 pmap_release_page_lock(md); 4149 4150 return rv; 4151 } 4152 4153 /* 4154 * pmap_is_modified: 4155 * 4156 * Test if a page has the "modified" attribute. 4157 */ 4158 /* See <arm/arm32/pmap.h> */ 4159 4160 /* 4161 * pmap_is_referenced: 4162 * 4163 * Test if a page has the "referenced" attribute. 4164 */ 4165 /* See <arm/arm32/pmap.h> */ 4166 4167 #if defined(ARM_MMU_EXTENDED) && 0 4168 int 4169 pmap_prefetchabt_fixup(void *v) 4170 { 4171 struct trapframe * const tf = v; 4172 vaddr_t va = trunc_page(tf->tf_pc); 4173 int rv = ABORT_FIXUP_FAILED; 4174 4175 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4176 return rv; 4177 4178 kpreempt_disable(); 4179 pmap_t pm = curcpu()->ci_pmap_cur; 4180 const size_t l1slot = l1pte_index(va); 4181 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4182 if (l2 == NULL) 4183 goto out; 4184 4185 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4186 if (l2b->l2b_kva == NULL) 4187 goto out; 4188 4189 /* 4190 * Check the PTE itself. 4191 */ 4192 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4193 const pt_entry_t opte = *ptep; 4194 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4195 goto out; 4196 4197 paddr_t pa = l2pte_pa(pte); 4198 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4199 KASSERT(pg != NULL); 4200 4201 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4202 4203 pmap_acquire_page_lock(md); 4204 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4205 KASSERT(pv != NULL); 4206 4207 if (PV_IS_EXEC_P(pv->pv_flags)) { 4208 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4209 pmap_syncicache_page(md, pa); 4210 } 4211 rv = ABORT_FIXUP_RETURN; 4212 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4213 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4214 } 4215 pmap_release_page_lock(md); 4216 4217 out: 4218 kpreempt_enable(); 4219 return rv; 4220 } 4221 #endif 4222 4223 int 4224 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4225 { 4226 struct l2_dtable *l2; 4227 struct l2_bucket *l2b; 4228 paddr_t pa; 4229 const size_t l1slot = l1pte_index(va); 4230 int rv = 0; 4231 4232 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4233 4234 va = trunc_page(va); 4235 4236 KASSERT(!user || (pm != pmap_kernel())); 4237 4238 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4239 pm, va, ftype, user); 4240 #ifdef ARM_MMU_EXTENDED 4241 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4242 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4243 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4244 #endif 4245 4246 pmap_acquire_pmap_lock(pm); 4247 4248 /* 4249 * If there is no l2_dtable for this address, then the process 4250 * has no business accessing it. 4251 * 4252 * Note: This will catch userland processes trying to access 4253 * kernel addresses. 4254 */ 4255 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4256 if (l2 == NULL) { 4257 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4258 goto out; 4259 } 4260 4261 /* 4262 * Likewise if there is no L2 descriptor table 4263 */ 4264 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4265 if (l2b->l2b_kva == NULL) { 4266 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4267 goto out; 4268 } 4269 4270 /* 4271 * Check the PTE itself. 4272 */ 4273 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4274 pt_entry_t const opte = *ptep; 4275 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4276 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4277 goto out; 4278 } 4279 4280 #ifndef ARM_HAS_VBAR 4281 /* 4282 * Catch a userland access to the vector page mapped at 0x0 4283 */ 4284 if (user && (opte & L2_S_PROT_U) == 0) { 4285 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4286 goto out; 4287 } 4288 #endif 4289 4290 pa = l2pte_pa(opte); 4291 4292 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4293 /* 4294 * This looks like a good candidate for "page modified" 4295 * emulation... 4296 */ 4297 struct pv_entry *pv; 4298 struct vm_page *pg; 4299 4300 /* Extract the physical address of the page */ 4301 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4302 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4303 goto out; 4304 } 4305 4306 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4307 4308 /* Get the current flags for this page. */ 4309 pmap_acquire_page_lock(md); 4310 pv = pmap_find_pv(md, pm, va); 4311 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4312 pmap_release_page_lock(md); 4313 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4314 goto out; 4315 } 4316 4317 /* 4318 * Do the flags say this page is writable? If not then it 4319 * is a genuine write fault. If yes then the write fault is 4320 * our fault as we did not reflect the write access in the 4321 * PTE. Now we know a write has occurred we can correct this 4322 * and also set the modified bit 4323 */ 4324 if ((pv->pv_flags & PVF_WRITE) == 0) { 4325 pmap_release_page_lock(md); 4326 goto out; 4327 } 4328 4329 md->pvh_attrs |= PVF_REF | PVF_MOD; 4330 pv->pv_flags |= PVF_REF | PVF_MOD; 4331 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4332 /* 4333 * If there are cacheable mappings for this page, mark it dirty. 4334 */ 4335 if ((md->pvh_attrs & PVF_NC) == 0) 4336 md->pvh_attrs |= PVF_DIRTY; 4337 #endif 4338 #ifdef ARM_MMU_EXTENDED 4339 if (md->pvh_attrs & PVF_EXEC) { 4340 md->pvh_attrs &= ~PVF_EXEC; 4341 PMAPCOUNT(exec_discarded_modfixup); 4342 } 4343 #endif 4344 pmap_release_page_lock(md); 4345 4346 /* 4347 * Re-enable write permissions for the page. No need to call 4348 * pmap_vac_me_harder(), since this is just a 4349 * modified-emulation fault, and the PVF_WRITE bit isn't 4350 * changing. We've already set the cacheable bits based on 4351 * the assumption that we can write to this page. 4352 */ 4353 const pt_entry_t npte = 4354 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4355 #ifdef ARM_MMU_EXTENDED 4356 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4357 #endif 4358 | 0; 4359 l2pte_set(ptep, npte, opte); 4360 PTE_SYNC(ptep); 4361 PMAPCOUNT(fixup_mod); 4362 rv = 1; 4363 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4364 opte, npte, 0, 0); 4365 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4366 /* 4367 * This looks like a good candidate for "page referenced" 4368 * emulation. 4369 */ 4370 struct vm_page *pg; 4371 4372 /* Extract the physical address of the page */ 4373 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4374 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4375 goto out; 4376 } 4377 4378 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4379 4380 /* Get the current flags for this page. */ 4381 pmap_acquire_page_lock(md); 4382 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4383 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4384 pmap_release_page_lock(md); 4385 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4386 goto out; 4387 } 4388 4389 md->pvh_attrs |= PVF_REF; 4390 pv->pv_flags |= PVF_REF; 4391 4392 pt_entry_t npte = 4393 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4394 #ifdef ARM_MMU_EXTENDED 4395 if (pm != pmap_kernel()) { 4396 npte |= L2_XS_nG; 4397 } 4398 /* 4399 * If we got called from prefetch abort, then ftype will have 4400 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4401 * the PTE. 4402 */ 4403 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4404 /* 4405 * Is this a mapping of an executable page? 4406 */ 4407 if ((pv->pv_flags & PVF_EXEC) == 0) { 4408 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4409 0, 0, 0, 0); 4410 goto out; 4411 } 4412 /* 4413 * If we haven't synced the page, do so now. 4414 */ 4415 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4416 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4417 pa, 0, 0, 0); 4418 pmap_syncicache_page(md, pa); 4419 PMAPCOUNT(fixup_exec); 4420 } 4421 npte &= ~L2_XS_XN; 4422 } 4423 #endif /* ARM_MMU_EXTENDED */ 4424 pmap_release_page_lock(md); 4425 l2pte_set(ptep, npte, opte); 4426 PTE_SYNC(ptep); 4427 PMAPCOUNT(fixup_ref); 4428 rv = 1; 4429 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4430 opte, npte, 0, 0); 4431 #ifdef ARM_MMU_EXTENDED 4432 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4433 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4434 if (pg == NULL) { 4435 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4436 goto out; 4437 } 4438 4439 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4440 4441 /* Get the current flags for this page. */ 4442 pmap_acquire_page_lock(md); 4443 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4444 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4445 pmap_release_page_lock(md); 4446 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4447 goto out; 4448 } 4449 4450 /* 4451 * If we haven't synced the page, do so now. 4452 */ 4453 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4454 UVMHIST_LOG(maphist, "syncicache page #%#x", 4455 pa, 0, 0, 0); 4456 pmap_syncicache_page(md, pa); 4457 } 4458 pmap_release_page_lock(md); 4459 /* 4460 * Turn off no-execute. 4461 */ 4462 KASSERT(opte & L2_XS_nG); 4463 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4464 PTE_SYNC(ptep); 4465 rv = 1; 4466 PMAPCOUNT(fixup_exec); 4467 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4468 opte, opte & ~L2_XS_XN, 0, 0); 4469 #endif 4470 } 4471 4472 #ifndef ARM_MMU_EXTENDED 4473 /* 4474 * We know there is a valid mapping here, so simply 4475 * fix up the L1 if necessary. 4476 */ 4477 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4478 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4479 if (*pdep != pde) { 4480 l1pte_setone(pdep, pde); 4481 PTE_SYNC(pdep); 4482 rv = 1; 4483 PMAPCOUNT(fixup_pdes); 4484 } 4485 #endif 4486 4487 #ifdef CPU_SA110 4488 /* 4489 * There are bugs in the rev K SA110. This is a check for one 4490 * of them. 4491 */ 4492 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4493 curcpu()->ci_arm_cpurev < 3) { 4494 /* Always current pmap */ 4495 if (l2pte_valid_p(opte)) { 4496 extern int kernel_debug; 4497 if (kernel_debug & 1) { 4498 struct proc *p = curlwp->l_proc; 4499 printf("prefetch_abort: page is already " 4500 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4501 printf("prefetch_abort: pc=%08lx proc=%p " 4502 "process=%s\n", va, p, p->p_comm); 4503 printf("prefetch_abort: far=%08x fs=%x\n", 4504 cpu_faultaddress(), cpu_faultstatus()); 4505 } 4506 #ifdef DDB 4507 if (kernel_debug & 2) 4508 Debugger(); 4509 #endif 4510 rv = 1; 4511 } 4512 } 4513 #endif /* CPU_SA110 */ 4514 4515 #ifndef ARM_MMU_EXTENDED 4516 /* 4517 * If 'rv == 0' at this point, it generally indicates that there is a 4518 * stale TLB entry for the faulting address. That might be due to a 4519 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4520 */ 4521 if (rv == 0 4522 && pm->pm_l1->l1_domain_use_count == 1 4523 && pmap_needs_pte_sync == 0) { 4524 pmap_needs_pte_sync = 1; 4525 PTE_SYNC(ptep); 4526 PMAPCOUNT(fixup_ptesync); 4527 rv = 1; 4528 } 4529 #endif 4530 4531 #if defined(DEBUG) || 1 4532 /* 4533 * If 'rv == 0' at this point, it generally indicates that there is a 4534 * stale TLB entry for the faulting address. This happens when two or 4535 * more processes are sharing an L1. Since we don't flush the TLB on 4536 * a context switch between such processes, we can take domain faults 4537 * for mappings which exist at the same VA in both processes. EVEN IF 4538 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4539 * example. 4540 * 4541 * This is extremely likely to happen if pmap_enter() updated the L1 4542 * entry for a recently entered mapping. In this case, the TLB is 4543 * flushed for the new mapping, but there may still be TLB entries for 4544 * other mappings belonging to other processes in the 1MB range 4545 * covered by the L1 entry. 4546 * 4547 * Since 'rv == 0', we know that the L1 already contains the correct 4548 * value, so the fault must be due to a stale TLB entry. 4549 * 4550 * Since we always need to flush the TLB anyway in the case where we 4551 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4552 * stale TLB entries dynamically. 4553 * 4554 * However, the above condition can ONLY happen if the current L1 is 4555 * being shared. If it happens when the L1 is unshared, it indicates 4556 * that other parts of the pmap are not doing their job WRT managing 4557 * the TLB. 4558 */ 4559 if (rv == 0 4560 #ifndef ARM_MMU_EXTENDED 4561 && pm->pm_l1->l1_domain_use_count == 1 4562 #endif 4563 && true) { 4564 #ifdef DEBUG 4565 extern int last_fault_code; 4566 #else 4567 int last_fault_code = ftype & VM_PROT_EXECUTE 4568 ? armreg_ifsr_read() 4569 : armreg_dfsr_read(); 4570 #endif 4571 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4572 pm, va, ftype); 4573 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4574 l2, l2b, ptep, opte); 4575 4576 #ifndef ARM_MMU_EXTENDED 4577 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4578 pdep, pde, last_fault_code); 4579 #else 4580 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4581 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4582 armreg_ttbcr_read()); 4583 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4584 last_fault_code, curcpu()->ci_pmap_cur, 4585 curcpu()->ci_pmap_asid_cur, 4586 armreg_contextidr_read(), armreg_dacr_read()); 4587 #ifdef _ARM_ARCH_7 4588 if (ftype & VM_PROT_WRITE) 4589 armreg_ats1cuw_write(va); 4590 else 4591 armreg_ats1cur_write(va); 4592 arm_isb(); 4593 printf("fixup: par %#x\n", armreg_par_read()); 4594 #endif 4595 #endif 4596 #ifdef DDB 4597 extern int kernel_debug; 4598 4599 if (kernel_debug & 2) { 4600 pmap_release_pmap_lock(pm); 4601 #ifdef UVMHIST 4602 KERNHIST_DUMP(maphist); 4603 #endif 4604 cpu_Debugger(); 4605 pmap_acquire_pmap_lock(pm); 4606 } 4607 #endif 4608 } 4609 #endif 4610 4611 pmap_tlb_flush_SE(pm, va, 4612 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4613 4614 rv = 1; 4615 4616 out: 4617 pmap_release_pmap_lock(pm); 4618 4619 return (rv); 4620 } 4621 4622 /* 4623 * Routine: pmap_procwr 4624 * 4625 * Function: 4626 * Synchronize caches corresponding to [addr, addr+len) in p. 4627 * 4628 */ 4629 void 4630 pmap_procwr(struct proc *p, vaddr_t va, int len) 4631 { 4632 /* We only need to do anything if it is the current process. */ 4633 if (p == curproc) 4634 cpu_icache_sync_range(va, len); 4635 } 4636 4637 /* 4638 * Routine: pmap_unwire 4639 * Function: Clear the wired attribute for a map/virtual-address pair. 4640 * 4641 * In/out conditions: 4642 * The mapping must already exist in the pmap. 4643 */ 4644 void 4645 pmap_unwire(pmap_t pm, vaddr_t va) 4646 { 4647 struct l2_bucket *l2b; 4648 pt_entry_t *ptep, pte; 4649 struct vm_page *pg; 4650 paddr_t pa; 4651 4652 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4653 4654 pmap_acquire_pmap_lock(pm); 4655 4656 l2b = pmap_get_l2_bucket(pm, va); 4657 KDASSERT(l2b != NULL); 4658 4659 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4660 pte = *ptep; 4661 4662 /* Extract the physical address of the page */ 4663 pa = l2pte_pa(pte); 4664 4665 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4666 /* Update the wired bit in the pv entry for this page. */ 4667 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4668 4669 pmap_acquire_page_lock(md); 4670 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4671 pmap_release_page_lock(md); 4672 } 4673 4674 pmap_release_pmap_lock(pm); 4675 } 4676 4677 void 4678 pmap_activate(struct lwp *l) 4679 { 4680 struct cpu_info * const ci = curcpu(); 4681 extern int block_userspace_access; 4682 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4683 #ifdef ARM_MMU_EXTENDED 4684 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4685 #endif 4686 4687 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4688 4689 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4690 4691 /* 4692 * If activating a non-current lwp or the current lwp is 4693 * already active, just return. 4694 */ 4695 if (false 4696 || l != curlwp 4697 #ifdef ARM_MMU_EXTENDED 4698 || (ci->ci_pmap_cur == npm && 4699 (npm == pmap_kernel() 4700 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4701 #else 4702 || npm->pm_activated == true 4703 #endif 4704 || false) { 4705 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4706 return; 4707 } 4708 4709 #ifndef ARM_MMU_EXTENDED 4710 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4711 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4712 4713 /* 4714 * If TTB and DACR are unchanged, short-circuit all the 4715 * TLB/cache management stuff. 4716 */ 4717 pmap_t opm = ci->ci_lastlwp 4718 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4719 : NULL; 4720 if (opm != NULL) { 4721 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4722 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4723 4724 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4725 goto all_done; 4726 } 4727 #endif /* !ARM_MMU_EXTENDED */ 4728 4729 PMAPCOUNT(activations); 4730 block_userspace_access = 1; 4731 4732 #ifndef ARM_MMU_EXTENDED 4733 /* 4734 * If switching to a user vmspace which is different to the 4735 * most recent one, and the most recent one is potentially 4736 * live in the cache, we must write-back and invalidate the 4737 * entire cache. 4738 */ 4739 pmap_t rpm = ci->ci_pmap_lastuser; 4740 #endif 4741 4742 /* 4743 * XXXSCW: There's a corner case here which can leave turds in the cache as 4744 * reported in kern/41058. They're probably left over during tear-down and 4745 * switching away from an exiting process. Until the root cause is identified 4746 * and fixed, zap the cache when switching pmaps. This will result in a few 4747 * unnecessary cache flushes, but that's better than silently corrupting data. 4748 */ 4749 #ifndef ARM_MMU_EXTENDED 4750 #if 0 4751 if (npm != pmap_kernel() && rpm && npm != rpm && 4752 rpm->pm_cstate.cs_cache) { 4753 rpm->pm_cstate.cs_cache = 0; 4754 #ifdef PMAP_CACHE_VIVT 4755 cpu_idcache_wbinv_all(); 4756 #endif 4757 } 4758 #else 4759 if (rpm) { 4760 rpm->pm_cstate.cs_cache = 0; 4761 if (npm == pmap_kernel()) 4762 ci->ci_pmap_lastuser = NULL; 4763 #ifdef PMAP_CACHE_VIVT 4764 cpu_idcache_wbinv_all(); 4765 #endif 4766 } 4767 #endif 4768 4769 /* No interrupts while we frob the TTB/DACR */ 4770 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4771 #endif /* !ARM_MMU_EXTENDED */ 4772 4773 #ifndef ARM_HAS_VBAR 4774 /* 4775 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4776 * entry corresponding to 'vector_page' in the incoming L1 table 4777 * before switching to it otherwise subsequent interrupts/exceptions 4778 * (including domain faults!) will jump into hyperspace. 4779 */ 4780 if (npm->pm_pl1vec != NULL) { 4781 cpu_tlb_flushID_SE((u_int)vector_page); 4782 cpu_cpwait(); 4783 *npm->pm_pl1vec = npm->pm_l1vec; 4784 PTE_SYNC(npm->pm_pl1vec); 4785 } 4786 #endif 4787 4788 #ifdef ARM_MMU_EXTENDED 4789 /* 4790 * Assume that TTBR1 has only global mappings and TTBR0 only has 4791 * non-global mappings. To prevent speculation from doing evil things 4792 * we disable translation table walks using TTBR0 before setting the 4793 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4794 * walks are reenabled. 4795 */ 4796 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4797 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4798 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4799 arm_isb(); 4800 pmap_tlb_asid_acquire(npm, l); 4801 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4802 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4803 /* 4804 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4805 * been updated. 4806 */ 4807 arm_isb(); 4808 if (npm != pmap_kernel()) { 4809 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4810 } 4811 cpu_cpwait(); 4812 ci->ci_pmap_asid_cur = pai->pai_asid; 4813 #else 4814 cpu_domains(ndacr); 4815 if (npm == pmap_kernel() || npm == rpm) { 4816 /* 4817 * Switching to a kernel thread, or back to the 4818 * same user vmspace as before... Simply update 4819 * the TTB (no TLB flush required) 4820 */ 4821 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4822 cpu_cpwait(); 4823 } else { 4824 /* 4825 * Otherwise, update TTB and flush TLB 4826 */ 4827 cpu_context_switch(npm->pm_l1->l1_physaddr); 4828 if (rpm != NULL) 4829 rpm->pm_cstate.cs_tlb = 0; 4830 } 4831 4832 restore_interrupts(oldirqstate); 4833 #endif /* ARM_MMU_EXTENDED */ 4834 4835 block_userspace_access = 0; 4836 4837 #ifndef ARM_MMU_EXTENDED 4838 all_done: 4839 /* 4840 * The new pmap is resident. Make sure it's marked 4841 * as resident in the cache/TLB. 4842 */ 4843 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4844 if (npm != pmap_kernel()) 4845 ci->ci_pmap_lastuser = npm; 4846 4847 /* The old pmap is not longer active */ 4848 if (opm != npm) { 4849 if (opm != NULL) 4850 opm->pm_activated = false; 4851 4852 /* But the new one is */ 4853 npm->pm_activated = true; 4854 } 4855 #endif 4856 ci->ci_pmap_cur = npm; 4857 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4858 } 4859 4860 void 4861 pmap_deactivate(struct lwp *l) 4862 { 4863 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4864 4865 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4866 4867 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4868 4869 #ifdef ARM_MMU_EXTENDED 4870 kpreempt_disable(); 4871 struct cpu_info * const ci = curcpu(); 4872 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4873 /* 4874 * Disable translation table walks from TTBR0 while no pmap has been 4875 * activated. 4876 */ 4877 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4878 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4879 arm_isb(); 4880 pmap_tlb_asid_deactivate(pm); 4881 cpu_setttb(pmap_kernel()->pm_l1_pa, pai->pai_asid); 4882 ci->ci_pmap_cur = pmap_kernel(); 4883 kpreempt_enable(); 4884 #else 4885 /* 4886 * If the process is exiting, make sure pmap_activate() does 4887 * a full MMU context-switch and cache flush, which we might 4888 * otherwise skip. See PR port-arm/38950. 4889 */ 4890 if (l->l_proc->p_sflag & PS_WEXIT) 4891 curcpu()->ci_lastlwp = NULL; 4892 4893 pm->pm_activated = false; 4894 #endif 4895 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4896 } 4897 4898 void 4899 pmap_update(pmap_t pm) 4900 { 4901 4902 if (pm->pm_remove_all) { 4903 #ifdef ARM_MMU_EXTENDED 4904 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4905 /* 4906 * Finish up the pmap_remove_all() optimisation by flushing 4907 * all our ASIDs. 4908 */ 4909 pmap_tlb_asid_release_all(pm); 4910 #else 4911 /* 4912 * Finish up the pmap_remove_all() optimisation by flushing 4913 * the TLB. 4914 */ 4915 pmap_tlb_flushID(pm); 4916 #endif 4917 pm->pm_remove_all = false; 4918 } 4919 4920 #ifdef ARM_MMU_EXTENDED 4921 4922 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4923 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4924 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4925 PMAP_COUNT(shootdown_ipis); 4926 } 4927 #endif 4928 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4929 #else 4930 if (pmap_is_current(pm)) { 4931 /* 4932 * If we're dealing with a current userland pmap, move its L1 4933 * to the end of the LRU. 4934 */ 4935 if (pm != pmap_kernel()) 4936 pmap_use_l1(pm); 4937 4938 /* 4939 * We can assume we're done with frobbing the cache/tlb for 4940 * now. Make sure any future pmap ops don't skip cache/tlb 4941 * flushes. 4942 */ 4943 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4944 } 4945 #endif 4946 4947 PMAPCOUNT(updates); 4948 4949 /* 4950 * make sure TLB/cache operations have completed. 4951 */ 4952 cpu_cpwait(); 4953 } 4954 4955 void 4956 pmap_remove_all(pmap_t pm) 4957 { 4958 4959 /* 4960 * The vmspace described by this pmap is about to be torn down. 4961 * Until pmap_update() is called, UVM will only make calls 4962 * to pmap_remove(). We can make life much simpler by flushing 4963 * the cache now, and deferring TLB invalidation to pmap_update(). 4964 */ 4965 #ifdef PMAP_CACHE_VIVT 4966 pmap_cache_wbinv_all(pm, PVF_EXEC); 4967 #endif 4968 pm->pm_remove_all = true; 4969 } 4970 4971 /* 4972 * Retire the given physical map from service. 4973 * Should only be called if the map contains no valid mappings. 4974 */ 4975 void 4976 pmap_destroy(pmap_t pm) 4977 { 4978 u_int count; 4979 4980 if (pm == NULL) 4981 return; 4982 4983 if (pm->pm_remove_all) { 4984 pmap_tlb_flushID(pm); 4985 pm->pm_remove_all = false; 4986 } 4987 4988 /* 4989 * Drop reference count 4990 */ 4991 mutex_enter(pm->pm_lock); 4992 count = --pm->pm_obj.uo_refs; 4993 mutex_exit(pm->pm_lock); 4994 if (count > 0) { 4995 #ifndef ARM_MMU_EXTENDED 4996 if (pmap_is_current(pm)) { 4997 if (pm != pmap_kernel()) 4998 pmap_use_l1(pm); 4999 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5000 } 5001 #endif 5002 return; 5003 } 5004 5005 /* 5006 * reference count is zero, free pmap resources and then free pmap. 5007 */ 5008 5009 #ifndef ARM_HAS_VBAR 5010 if (vector_page < KERNEL_BASE) { 5011 KDASSERT(!pmap_is_current(pm)); 5012 5013 /* Remove the vector page mapping */ 5014 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5015 pmap_update(pm); 5016 } 5017 #endif 5018 5019 LIST_REMOVE(pm, pm_list); 5020 5021 pmap_free_l1(pm); 5022 5023 #ifdef ARM_MMU_EXTENDED 5024 #ifdef MULTIPROCESSOR 5025 kcpuset_destroy(pm->pm_active); 5026 kcpuset_destroy(pm->pm_onproc); 5027 #endif 5028 #else 5029 struct cpu_info * const ci = curcpu(); 5030 if (ci->ci_pmap_lastuser == pm) 5031 ci->ci_pmap_lastuser = NULL; 5032 #endif 5033 5034 uvm_obj_destroy(&pm->pm_obj, false); 5035 mutex_destroy(&pm->pm_obj_lock); 5036 pool_cache_put(&pmap_cache, pm); 5037 } 5038 5039 5040 /* 5041 * void pmap_reference(pmap_t pm) 5042 * 5043 * Add a reference to the specified pmap. 5044 */ 5045 void 5046 pmap_reference(pmap_t pm) 5047 { 5048 5049 if (pm == NULL) 5050 return; 5051 5052 #ifndef ARM_MMU_EXTENDED 5053 pmap_use_l1(pm); 5054 #endif 5055 5056 mutex_enter(pm->pm_lock); 5057 pm->pm_obj.uo_refs++; 5058 mutex_exit(pm->pm_lock); 5059 } 5060 5061 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5062 5063 static struct evcnt pmap_prefer_nochange_ev = 5064 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5065 static struct evcnt pmap_prefer_change_ev = 5066 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5067 5068 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5069 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5070 5071 void 5072 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5073 { 5074 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5075 vaddr_t va = *vap; 5076 vaddr_t diff = (hint - va) & mask; 5077 if (diff == 0) { 5078 pmap_prefer_nochange_ev.ev_count++; 5079 } else { 5080 pmap_prefer_change_ev.ev_count++; 5081 if (__predict_false(td)) 5082 va -= mask + 1; 5083 *vap = va + diff; 5084 } 5085 } 5086 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5087 5088 /* 5089 * pmap_zero_page() 5090 * 5091 * Zero a given physical page by mapping it at a page hook point. 5092 * In doing the zero page op, the page we zero is mapped cachable, as with 5093 * StrongARM accesses to non-cached pages are non-burst making writing 5094 * _any_ bulk data very slow. 5095 */ 5096 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5097 void 5098 pmap_zero_page_generic(paddr_t pa) 5099 { 5100 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5101 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5102 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5103 #endif 5104 #if defined(PMAP_CACHE_VIPT) 5105 /* Choose the last page color it had, if any */ 5106 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5107 #else 5108 const vsize_t va_offset = 0; 5109 #endif 5110 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5111 /* 5112 * Is this page mapped at its natural color? 5113 * If we have all of memory mapped, then just convert PA to VA. 5114 */ 5115 const bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5116 || va_offset == (pa & arm_cache_prefer_mask); 5117 const vaddr_t vdstp = okcolor 5118 ? KERNEL_BASE + (pa - physical_start) 5119 : cpu_cdstp(va_offset); 5120 #else 5121 const bool okcolor = false; 5122 const vaddr_t vdstp = cpu_cdstp(va_offset); 5123 #endif 5124 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5125 5126 5127 #ifdef DEBUG 5128 if (!SLIST_EMPTY(&md->pvh_list)) 5129 panic("pmap_zero_page: page has mappings"); 5130 #endif 5131 5132 KDASSERT((pa & PGOFSET) == 0); 5133 5134 if (!okcolor) { 5135 /* 5136 * Hook in the page, zero it, and purge the cache for that 5137 * zeroed page. Invalidate the TLB as needed. 5138 */ 5139 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5140 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5141 l2pte_set(ptep, npte, 0); 5142 PTE_SYNC(ptep); 5143 cpu_tlb_flushD_SE(vdstp); 5144 cpu_cpwait(); 5145 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5146 /* 5147 * If we are direct-mapped and our color isn't ok, then before 5148 * we bzero the page invalidate its contents from the cache and 5149 * reset the color to its natural color. 5150 */ 5151 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5152 md->pvh_attrs &= ~arm_cache_prefer_mask; 5153 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5154 #endif 5155 } 5156 bzero_page(vdstp); 5157 if (!okcolor) { 5158 /* 5159 * Unmap the page. 5160 */ 5161 l2pte_reset(ptep); 5162 PTE_SYNC(ptep); 5163 cpu_tlb_flushD_SE(vdstp); 5164 #ifdef PMAP_CACHE_VIVT 5165 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5166 #endif 5167 } 5168 #ifdef PMAP_CACHE_VIPT 5169 /* 5170 * This page is now cache resident so it now has a page color. 5171 * Any contents have been obliterated so clear the EXEC flag. 5172 */ 5173 #ifndef ARM_MMU_EXTENDED 5174 if (!pmap_is_page_colored_p(md)) { 5175 PMAPCOUNT(vac_color_new); 5176 md->pvh_attrs |= PVF_COLORED; 5177 } 5178 md->pvh_attrs |= PVF_DIRTY; 5179 #endif 5180 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5181 md->pvh_attrs &= ~PVF_EXEC; 5182 PMAPCOUNT(exec_discarded_zero); 5183 } 5184 #endif 5185 } 5186 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5187 5188 #if ARM_MMU_XSCALE == 1 5189 void 5190 pmap_zero_page_xscale(paddr_t pa) 5191 { 5192 #ifdef DEBUG 5193 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5194 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5195 5196 if (!SLIST_EMPTY(&md->pvh_list)) 5197 panic("pmap_zero_page: page has mappings"); 5198 #endif 5199 5200 KDASSERT((pa & PGOFSET) == 0); 5201 5202 /* 5203 * Hook in the page, zero it, and purge the cache for that 5204 * zeroed page. Invalidate the TLB as needed. 5205 */ 5206 5207 pt_entry_t npte = L2_S_PROTO | pa | 5208 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5209 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5210 l2pte_set(cdst_pte, npte, 0); 5211 PTE_SYNC(cdst_pte); 5212 cpu_tlb_flushD_SE(cdstp); 5213 cpu_cpwait(); 5214 bzero_page(cdstp); 5215 xscale_cache_clean_minidata(); 5216 l2pte_reset(cdst_pte); 5217 PTE_SYNC(cdst_pte); 5218 } 5219 #endif /* ARM_MMU_XSCALE == 1 */ 5220 5221 /* pmap_pageidlezero() 5222 * 5223 * The same as above, except that we assume that the page is not 5224 * mapped. This means we never have to flush the cache first. Called 5225 * from the idle loop. 5226 */ 5227 bool 5228 pmap_pageidlezero(paddr_t pa) 5229 { 5230 bool rv = true; 5231 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5232 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5233 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5234 #endif 5235 #ifdef PMAP_CACHE_VIPT 5236 /* Choose the last page color it had, if any */ 5237 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5238 #else 5239 const vsize_t va_offset = 0; 5240 #endif 5241 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5242 const bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5243 || va_offset == (pa & arm_cache_prefer_mask); 5244 const vaddr_t vdstp = okcolor 5245 ? KERNEL_BASE + (pa - physical_start) 5246 : cpu_cdstp(va_offset); 5247 #else 5248 const bool okcolor = false; 5249 const vaddr_t vdstp = cpu_cdstp(va_offset); 5250 #endif 5251 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5252 5253 5254 #ifdef DEBUG 5255 if (!SLIST_EMPTY(&md->pvh_list)) 5256 panic("pmap_pageidlezero: page has mappings"); 5257 #endif 5258 5259 KDASSERT((pa & PGOFSET) == 0); 5260 5261 if (!okcolor) { 5262 /* 5263 * Hook in the page, zero it, and purge the cache for that 5264 * zeroed page. Invalidate the TLB as needed. 5265 */ 5266 const pt_entry_t npte = L2_S_PROTO | pa | 5267 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5268 l2pte_set(ptep, npte, 0); 5269 PTE_SYNC(ptep); 5270 cpu_tlb_flushD_SE(vdstp); 5271 cpu_cpwait(); 5272 } 5273 5274 uint64_t *ptr = (uint64_t *)vdstp; 5275 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5276 if (sched_curcpu_runnable_p() != 0) { 5277 /* 5278 * A process has become ready. Abort now, 5279 * so we don't keep it waiting while we 5280 * do slow memory access to finish this 5281 * page. 5282 */ 5283 rv = false; 5284 break; 5285 } 5286 *ptr++ = 0; 5287 } 5288 5289 #ifdef PMAP_CACHE_VIVT 5290 if (rv) 5291 /* 5292 * if we aborted we'll rezero this page again later so don't 5293 * purge it unless we finished it 5294 */ 5295 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5296 #elif defined(PMAP_CACHE_VIPT) 5297 /* 5298 * This page is now cache resident so it now has a page color. 5299 * Any contents have been obliterated so clear the EXEC flag. 5300 */ 5301 #ifndef ARM_MMU_EXTENDED 5302 if (!pmap_is_page_colored_p(md)) { 5303 PMAPCOUNT(vac_color_new); 5304 md->pvh_attrs |= PVF_COLORED; 5305 } 5306 #endif 5307 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5308 md->pvh_attrs &= ~PVF_EXEC; 5309 PMAPCOUNT(exec_discarded_zero); 5310 } 5311 #endif 5312 /* 5313 * Unmap the page. 5314 */ 5315 if (!okcolor) { 5316 l2pte_reset(ptep); 5317 PTE_SYNC(ptep); 5318 cpu_tlb_flushD_SE(vdstp); 5319 } 5320 5321 return rv; 5322 } 5323 5324 /* 5325 * pmap_copy_page() 5326 * 5327 * Copy one physical page into another, by mapping the pages into 5328 * hook points. The same comment regarding cachability as in 5329 * pmap_zero_page also applies here. 5330 */ 5331 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5332 void 5333 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5334 { 5335 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5336 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5337 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5338 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5339 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5340 #endif 5341 #ifdef PMAP_CACHE_VIPT 5342 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5343 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5344 #else 5345 const vsize_t src_va_offset = 0; 5346 const vsize_t dst_va_offset = 0; 5347 #endif 5348 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5349 /* 5350 * Is this page mapped at its natural color? 5351 * If we have all of memory mapped, then just convert PA to VA. 5352 */ 5353 const bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5354 || src_va_offset == (src & arm_cache_prefer_mask); 5355 const bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5356 || dst_va_offset == (dst & arm_cache_prefer_mask); 5357 const vaddr_t vsrcp = src_okcolor 5358 ? KERNEL_BASE + (src - physical_start) 5359 : cpu_csrcp(src_va_offset); 5360 const vaddr_t vdstp = KERNEL_BASE + (dst - physical_start); 5361 #else 5362 const bool src_okcolor = false; 5363 const bool dst_okcolor = false; 5364 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5365 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5366 #endif 5367 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5368 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5369 5370 #ifdef DEBUG 5371 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5372 panic("pmap_copy_page: dst page has mappings"); 5373 #endif 5374 5375 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5376 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5377 #endif 5378 KDASSERT((src & PGOFSET) == 0); 5379 KDASSERT((dst & PGOFSET) == 0); 5380 5381 /* 5382 * Clean the source page. Hold the source page's lock for 5383 * the duration of the copy so that no other mappings can 5384 * be created while we have a potentially aliased mapping. 5385 */ 5386 #ifdef PMAP_CACHE_VIVT 5387 pmap_acquire_page_lock(src_md); 5388 (void) pmap_clean_page(src_md, true); 5389 pmap_release_page_lock(src_md); 5390 #endif 5391 5392 /* 5393 * Map the pages into the page hook points, copy them, and purge 5394 * the cache for the appropriate page. Invalidate the TLB 5395 * as required. 5396 */ 5397 if (!src_okcolor) { 5398 const pt_entry_t nsrc_pte = L2_S_PROTO 5399 | src 5400 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5401 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5402 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5403 | pte_l2_s_cache_mode 5404 #endif 5405 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5406 l2pte_set(src_ptep, nsrc_pte, 0); 5407 PTE_SYNC(src_ptep); 5408 cpu_tlb_flushD_SE(vsrcp); 5409 cpu_cpwait(); 5410 } 5411 if (!dst_okcolor) { 5412 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5413 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5414 l2pte_set(dst_ptep, ndst_pte, 0); 5415 PTE_SYNC(dst_ptep); 5416 cpu_tlb_flushD_SE(vdstp); 5417 cpu_cpwait(); 5418 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5419 /* 5420 * If we are direct-mapped and our color isn't ok, then before 5421 * we bcopy to the new page invalidate its contents from the 5422 * cache and reset its color to its natural color. 5423 */ 5424 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5425 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5426 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5427 #endif 5428 } 5429 bcopy_page(vsrcp, vdstp); 5430 #ifdef PMAP_CACHE_VIVT 5431 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5432 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5433 #endif 5434 /* 5435 * Unmap the pages. 5436 */ 5437 if (!src_okcolor) { 5438 l2pte_reset(src_ptep); 5439 PTE_SYNC(src_ptep); 5440 cpu_tlb_flushD_SE(vsrcp); 5441 cpu_cpwait(); 5442 } 5443 if (!dst_okcolor) { 5444 l2pte_reset(dst_ptep); 5445 PTE_SYNC(dst_ptep); 5446 cpu_tlb_flushD_SE(vdstp); 5447 cpu_cpwait(); 5448 } 5449 #ifdef PMAP_CACHE_VIPT 5450 /* 5451 * Now that the destination page is in the cache, mark it as colored. 5452 * If this was an exec page, discard it. 5453 */ 5454 pmap_acquire_page_lock(dst_md); 5455 #ifndef ARM_MMU_EXTENDED 5456 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5457 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5458 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5459 } 5460 if (!pmap_is_page_colored_p(dst_md)) { 5461 PMAPCOUNT(vac_color_new); 5462 dst_md->pvh_attrs |= PVF_COLORED; 5463 } 5464 dst_md->pvh_attrs |= PVF_DIRTY; 5465 #endif 5466 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5467 dst_md->pvh_attrs &= ~PVF_EXEC; 5468 PMAPCOUNT(exec_discarded_copy); 5469 } 5470 pmap_release_page_lock(dst_md); 5471 #endif 5472 } 5473 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5474 5475 #if ARM_MMU_XSCALE == 1 5476 void 5477 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5478 { 5479 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5480 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5481 #ifdef DEBUG 5482 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5483 5484 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5485 panic("pmap_copy_page: dst page has mappings"); 5486 #endif 5487 5488 KDASSERT((src & PGOFSET) == 0); 5489 KDASSERT((dst & PGOFSET) == 0); 5490 5491 /* 5492 * Clean the source page. Hold the source page's lock for 5493 * the duration of the copy so that no other mappings can 5494 * be created while we have a potentially aliased mapping. 5495 */ 5496 #ifdef PMAP_CACHE_VIVT 5497 pmap_acquire_page_lock(src_md); 5498 (void) pmap_clean_page(src_md, true); 5499 pmap_release_page_lock(src_md); 5500 #endif 5501 5502 /* 5503 * Map the pages into the page hook points, copy them, and purge 5504 * the cache for the appropriate page. Invalidate the TLB 5505 * as required. 5506 */ 5507 *csrc_pte = L2_S_PROTO | src | 5508 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 5509 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5510 PTE_SYNC(csrc_pte); 5511 *cdst_pte = L2_S_PROTO | dst | 5512 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5513 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5514 PTE_SYNC(cdst_pte); 5515 cpu_tlb_flushD_SE(csrcp); 5516 cpu_tlb_flushD_SE(cdstp); 5517 cpu_cpwait(); 5518 bcopy_page(csrcp, cdstp); 5519 xscale_cache_clean_minidata(); 5520 } 5521 #endif /* ARM_MMU_XSCALE == 1 */ 5522 5523 /* 5524 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5525 * 5526 * Return the start and end addresses of the kernel's virtual space. 5527 * These values are setup in pmap_bootstrap and are updated as pages 5528 * are allocated. 5529 */ 5530 void 5531 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5532 { 5533 *start = virtual_avail; 5534 *end = virtual_end; 5535 } 5536 5537 /* 5538 * Helper function for pmap_grow_l2_bucket() 5539 */ 5540 static inline int 5541 pmap_grow_map(vaddr_t va, paddr_t *pap) 5542 { 5543 paddr_t pa; 5544 5545 if (uvm.page_init_done == false) { 5546 #ifdef PMAP_STEAL_MEMORY 5547 pv_addr_t pv; 5548 pmap_boot_pagealloc(PAGE_SIZE, 5549 #ifdef PMAP_CACHE_VIPT 5550 arm_cache_prefer_mask, 5551 va & arm_cache_prefer_mask, 5552 #else 5553 0, 0, 5554 #endif 5555 &pv); 5556 pa = pv.pv_pa; 5557 #else 5558 if (uvm_page_physget(&pa) == false) 5559 return (1); 5560 #endif /* PMAP_STEAL_MEMORY */ 5561 } else { 5562 struct vm_page *pg; 5563 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5564 if (pg == NULL) 5565 return (1); 5566 pa = VM_PAGE_TO_PHYS(pg); 5567 /* 5568 * This new page must not have any mappings. Enter it via 5569 * pmap_kenter_pa and let that routine do the hard work. 5570 */ 5571 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5572 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5573 pmap_kenter_pa(va, pa, 5574 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5575 } 5576 5577 if (pap) 5578 *pap = pa; 5579 5580 PMAPCOUNT(pt_mappings); 5581 #ifdef DEBUG 5582 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5583 KDASSERT(l2b != NULL); 5584 5585 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5586 const pt_entry_t opte = *ptep; 5587 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5588 #endif 5589 memset((void *)va, 0, PAGE_SIZE); 5590 return (0); 5591 } 5592 5593 /* 5594 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5595 * used by pmap_growkernel(). 5596 */ 5597 static inline struct l2_bucket * 5598 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5599 { 5600 struct l2_dtable *l2; 5601 struct l2_bucket *l2b; 5602 u_short l1slot; 5603 vaddr_t nva; 5604 5605 l1slot = l1pte_index(va); 5606 5607 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5608 /* 5609 * No mapping at this address, as there is 5610 * no entry in the L1 table. 5611 * Need to allocate a new l2_dtable. 5612 */ 5613 nva = pmap_kernel_l2dtable_kva; 5614 if ((nva & PGOFSET) == 0) { 5615 /* 5616 * Need to allocate a backing page 5617 */ 5618 if (pmap_grow_map(nva, NULL)) 5619 return (NULL); 5620 } 5621 5622 l2 = (struct l2_dtable *)nva; 5623 nva += sizeof(struct l2_dtable); 5624 5625 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5626 /* 5627 * The new l2_dtable straddles a page boundary. 5628 * Map in another page to cover it. 5629 */ 5630 if (pmap_grow_map(nva, NULL)) 5631 return (NULL); 5632 } 5633 5634 pmap_kernel_l2dtable_kva = nva; 5635 5636 /* 5637 * Link it into the parent pmap 5638 */ 5639 pm->pm_l2[L2_IDX(l1slot)] = l2; 5640 } 5641 5642 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5643 5644 /* 5645 * Fetch pointer to the L2 page table associated with the address. 5646 */ 5647 if (l2b->l2b_kva == NULL) { 5648 pt_entry_t *ptep; 5649 5650 /* 5651 * No L2 page table has been allocated. Chances are, this 5652 * is because we just allocated the l2_dtable, above. 5653 */ 5654 nva = pmap_kernel_l2ptp_kva; 5655 ptep = (pt_entry_t *)nva; 5656 if ((nva & PGOFSET) == 0) { 5657 /* 5658 * Need to allocate a backing page 5659 */ 5660 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5661 return (NULL); 5662 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5663 } 5664 5665 l2->l2_occupancy++; 5666 l2b->l2b_kva = ptep; 5667 l2b->l2b_l1slot = l1slot; 5668 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5669 5670 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5671 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5672 } 5673 5674 return (l2b); 5675 } 5676 5677 vaddr_t 5678 pmap_growkernel(vaddr_t maxkvaddr) 5679 { 5680 pmap_t kpm = pmap_kernel(); 5681 #ifndef ARM_MMU_EXTENDED 5682 struct l1_ttable *l1; 5683 #endif 5684 int s; 5685 5686 if (maxkvaddr <= pmap_curmaxkvaddr) 5687 goto out; /* we are OK */ 5688 5689 NPDEBUG(PDB_GROWKERN, 5690 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5691 pmap_curmaxkvaddr, maxkvaddr)); 5692 5693 KDASSERT(maxkvaddr <= virtual_end); 5694 5695 /* 5696 * whoops! we need to add kernel PTPs 5697 */ 5698 5699 s = splhigh(); /* to be safe */ 5700 mutex_enter(kpm->pm_lock); 5701 5702 /* Map 1MB at a time */ 5703 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5704 #ifdef ARM_MMU_EXTENDED 5705 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5706 pd_entry_t *pdep = spdep; 5707 #endif 5708 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5709 #ifdef ARM_MMU_EXTENDED 5710 pdep++, 5711 #endif 5712 l1slot++) { 5713 struct l2_bucket *l2b = 5714 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5715 KASSERT(l2b != NULL); 5716 5717 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5718 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5719 #ifdef ARM_MMU_EXTENDED 5720 l1pte_setone(pdep, npde); 5721 #else 5722 /* Distribute new L1 entry to all other L1s */ 5723 SLIST_FOREACH(l1, &l1_list, l1_link) { 5724 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5725 l1pte_setone(pdep, npde); 5726 PDE_SYNC(pdep); 5727 } 5728 #endif 5729 } 5730 #ifdef ARM_MMU_EXTENDED 5731 PDE_SYNC_RANGE(spdep, pdep - spdep); 5732 #endif 5733 5734 #ifdef PMAP_CACHE_VIVT 5735 /* 5736 * flush out the cache, expensive but growkernel will happen so 5737 * rarely 5738 */ 5739 cpu_dcache_wbinv_all(); 5740 cpu_tlb_flushD(); 5741 cpu_cpwait(); 5742 #endif 5743 5744 mutex_exit(kpm->pm_lock); 5745 splx(s); 5746 5747 out: 5748 return (pmap_curmaxkvaddr); 5749 } 5750 5751 /************************ Utility routines ****************************/ 5752 5753 #ifndef ARM_HAS_VBAR 5754 /* 5755 * vector_page_setprot: 5756 * 5757 * Manipulate the protection of the vector page. 5758 */ 5759 void 5760 vector_page_setprot(int prot) 5761 { 5762 struct l2_bucket *l2b; 5763 pt_entry_t *ptep; 5764 5765 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5766 /* 5767 * If we are using VBAR to use the vectors in the kernel, then it's 5768 * already mapped in the kernel text so no need to anything here. 5769 */ 5770 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5771 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5772 return; 5773 } 5774 #endif 5775 5776 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5777 KASSERT(l2b != NULL); 5778 5779 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5780 5781 const pt_entry_t opte = *ptep; 5782 #ifdef ARM_MMU_EXTENDED 5783 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5784 | L2_S_PROT(PTE_KERNEL, prot); 5785 #else 5786 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5787 | L2_S_PROT(PTE_KERNEL, prot); 5788 #endif 5789 l2pte_set(ptep, npte, opte); 5790 PTE_SYNC(ptep); 5791 cpu_tlb_flushD_SE(vector_page); 5792 cpu_cpwait(); 5793 } 5794 #endif 5795 5796 /* 5797 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5798 * Returns true if the mapping exists, else false. 5799 * 5800 * NOTE: This function is only used by a couple of arm-specific modules. 5801 * It is not safe to take any pmap locks here, since we could be right 5802 * in the middle of debugging the pmap anyway... 5803 * 5804 * It is possible for this routine to return false even though a valid 5805 * mapping does exist. This is because we don't lock, so the metadata 5806 * state may be inconsistent. 5807 * 5808 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5809 * a "section" mapping. 5810 */ 5811 bool 5812 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5813 { 5814 struct l2_dtable *l2; 5815 pd_entry_t *pdep, pde; 5816 pt_entry_t *ptep; 5817 u_short l1slot; 5818 5819 if (pm->pm_l1 == NULL) 5820 return false; 5821 5822 l1slot = l1pte_index(va); 5823 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5824 pde = *pdep; 5825 5826 if (l1pte_section_p(pde)) { 5827 *ptp = NULL; 5828 return true; 5829 } 5830 5831 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5832 if (l2 == NULL || 5833 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5834 return false; 5835 } 5836 5837 *ptp = &ptep[l2pte_index(va)]; 5838 return true; 5839 } 5840 5841 bool 5842 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5843 { 5844 5845 if (pm->pm_l1 == NULL) 5846 return false; 5847 5848 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5849 5850 return true; 5851 } 5852 5853 /************************ Bootstrapping routines ****************************/ 5854 5855 #ifndef ARM_MMU_EXTENDED 5856 static void 5857 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5858 { 5859 int i; 5860 5861 l1->l1_kva = l1pt; 5862 l1->l1_domain_use_count = 0; 5863 l1->l1_domain_first = 0; 5864 5865 for (i = 0; i < PMAP_DOMAINS; i++) 5866 l1->l1_domain_free[i] = i + 1; 5867 5868 /* 5869 * Copy the kernel's L1 entries to each new L1. 5870 */ 5871 if (pmap_initialized) 5872 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5873 5874 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5875 &l1->l1_physaddr) == false) 5876 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5877 5878 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5879 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5880 } 5881 #endif /* !ARM_MMU_EXTENDED */ 5882 5883 /* 5884 * pmap_bootstrap() is called from the board-specific initarm() routine 5885 * once the kernel L1/L2 descriptors tables have been set up. 5886 * 5887 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5888 * spread over a number of disparate files/functions. 5889 * 5890 * We are passed the following parameters 5891 * - kernel_l1pt 5892 * This is a pointer to the base of the kernel's L1 translation table. 5893 * - vstart 5894 * 1MB-aligned start of managed kernel virtual memory. 5895 * - vend 5896 * 1MB-aligned end of managed kernel virtual memory. 5897 * 5898 * We use the first parameter to build the metadata (struct l1_ttable and 5899 * struct l2_dtable) necessary to track kernel mappings. 5900 */ 5901 #define PMAP_STATIC_L2_SIZE 16 5902 void 5903 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5904 { 5905 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5906 #ifndef ARM_MMU_EXTENDED 5907 static struct l1_ttable static_l1; 5908 struct l1_ttable *l1 = &static_l1; 5909 #endif 5910 struct l2_dtable *l2; 5911 struct l2_bucket *l2b; 5912 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5913 pmap_t pm = pmap_kernel(); 5914 pt_entry_t *ptep; 5915 paddr_t pa; 5916 vsize_t size; 5917 int nptes, l2idx, l2next = 0; 5918 5919 #ifdef ARM_MMU_EXTENDED 5920 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5921 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5922 #endif 5923 5924 #ifdef VERBOSE_INIT_ARM 5925 printf("kpm "); 5926 #endif 5927 /* 5928 * Initialise the kernel pmap object 5929 */ 5930 curcpu()->ci_pmap_cur = pm; 5931 #ifdef ARM_MMU_EXTENDED 5932 pm->pm_l1 = l1pt; 5933 pm->pm_l1_pa = kernel_l1pt.pv_pa; 5934 #ifdef VERBOSE_INIT_ARM 5935 printf("tlb0 "); 5936 #endif 5937 pmap_tlb_info_init(&pmap_tlb0_info); 5938 #ifdef MULTIPROCESSOR 5939 #ifdef VERBOSE_INIT_ARM 5940 printf("kcpusets "); 5941 #endif 5942 pm->pm_onproc = kcpuset_running; 5943 pm->pm_active = kcpuset_running; 5944 #endif 5945 #else 5946 pm->pm_l1 = l1; 5947 #endif 5948 5949 #ifdef VERBOSE_INIT_ARM 5950 printf("locks "); 5951 #endif 5952 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5953 if (arm_cache_prefer_mask != 0) { 5954 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 5955 } else { 5956 #endif 5957 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 5958 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5959 } 5960 #endif 5961 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5962 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5963 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5964 5965 #ifdef VERBOSE_INIT_ARM 5966 printf("l1pt "); 5967 #endif 5968 /* 5969 * Scan the L1 translation table created by initarm() and create 5970 * the required metadata for all valid mappings found in it. 5971 */ 5972 for (size_t l1slot = 0; 5973 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 5974 l1slot++) { 5975 pd_entry_t pde = l1pt[l1slot]; 5976 5977 /* 5978 * We're only interested in Coarse mappings. 5979 * pmap_extract() can deal with section mappings without 5980 * recourse to checking L2 metadata. 5981 */ 5982 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5983 continue; 5984 5985 /* 5986 * Lookup the KVA of this L2 descriptor table 5987 */ 5988 pa = l1pte_pa(pde); 5989 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5990 if (ptep == NULL) { 5991 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5992 (u_int)l1slot << L1_S_SHIFT, pa); 5993 } 5994 5995 /* 5996 * Fetch the associated L2 metadata structure. 5997 * Allocate a new one if necessary. 5998 */ 5999 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6000 if (l2next == PMAP_STATIC_L2_SIZE) 6001 panic("pmap_bootstrap: out of static L2s"); 6002 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6003 } 6004 6005 /* 6006 * One more L1 slot tracked... 6007 */ 6008 l2->l2_occupancy++; 6009 6010 /* 6011 * Fill in the details of the L2 descriptor in the 6012 * appropriate bucket. 6013 */ 6014 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6015 l2b->l2b_kva = ptep; 6016 l2b->l2b_pa = pa; 6017 l2b->l2b_l1slot = l1slot; 6018 6019 /* 6020 * Establish an initial occupancy count for this descriptor 6021 */ 6022 for (l2idx = 0; 6023 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6024 l2idx++) { 6025 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6026 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 6027 } 6028 } 6029 6030 /* 6031 * Make sure the descriptor itself has the correct cache mode. 6032 * If not, fix it, but whine about the problem. Port-meisters 6033 * should consider this a clue to fix up their initarm() 6034 * function. :) 6035 */ 6036 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6037 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6038 "L2 pte @ %p\n", ptep); 6039 } 6040 } 6041 6042 #ifdef VERBOSE_INIT_ARM 6043 printf("cache(l1pt) "); 6044 #endif 6045 /* 6046 * Ensure the primary (kernel) L1 has the correct cache mode for 6047 * a page table. Bitch if it is not correctly set. 6048 */ 6049 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6050 L1_TABLE_SIZE / L2_S_SIZE)) { 6051 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6052 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6053 } 6054 6055 #ifdef PMAP_CACHE_VIVT 6056 cpu_dcache_wbinv_all(); 6057 cpu_tlb_flushID(); 6058 cpu_cpwait(); 6059 #endif 6060 6061 /* 6062 * now we allocate the "special" VAs which are used for tmp mappings 6063 * by the pmap (and other modules). we allocate the VAs by advancing 6064 * virtual_avail (note that there are no pages mapped at these VAs). 6065 * 6066 * Managed KVM space start from wherever initarm() tells us. 6067 */ 6068 virtual_avail = vstart; 6069 virtual_end = vend; 6070 6071 #ifdef VERBOSE_INIT_ARM 6072 printf("specials "); 6073 #endif 6074 #ifdef PMAP_CACHE_VIPT 6075 /* 6076 * If we have a VIPT cache, we need one page/pte per possible alias 6077 * page so we won't violate cache aliasing rules. 6078 */ 6079 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6080 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6081 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6082 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6083 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6084 } 6085 #else 6086 nptes = PAGE_SIZE / L2_S_SIZE; 6087 #endif 6088 #ifdef MULTIPROCESSOR 6089 cnptes = nptes; 6090 nptes *= arm_cpu_max; 6091 #endif 6092 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6093 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6094 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6095 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6096 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6097 if (msgbufaddr == NULL) { 6098 pmap_alloc_specials(&virtual_avail, 6099 round_page(MSGBUFSIZE) / PAGE_SIZE, 6100 (void *)&msgbufaddr, NULL); 6101 } 6102 6103 /* 6104 * Allocate a range of kernel virtual address space to be used 6105 * for L2 descriptor tables and metadata allocation in 6106 * pmap_growkernel(). 6107 */ 6108 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6109 pmap_alloc_specials(&virtual_avail, 6110 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6111 &pmap_kernel_l2ptp_kva, NULL); 6112 6113 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6114 pmap_alloc_specials(&virtual_avail, 6115 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6116 &pmap_kernel_l2dtable_kva, NULL); 6117 6118 #ifndef ARM_MMU_EXTENDED 6119 /* 6120 * init the static-global locks and global pmap list. 6121 */ 6122 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6123 6124 /* 6125 * We can now initialise the first L1's metadata. 6126 */ 6127 SLIST_INIT(&l1_list); 6128 TAILQ_INIT(&l1_lru_list); 6129 pmap_init_l1(l1, l1pt); 6130 #endif /* ARM_MMU_EXTENDED */ 6131 6132 #ifndef ARM_HAS_VBAR 6133 /* Set up vector page L1 details, if necessary */ 6134 if (vector_page < KERNEL_BASE) { 6135 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6136 l2b = pmap_get_l2_bucket(pm, vector_page); 6137 KDASSERT(l2b != NULL); 6138 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6139 L1_C_DOM(pmap_domain(pm)); 6140 } else 6141 pm->pm_pl1vec = NULL; 6142 #endif 6143 6144 #ifdef VERBOSE_INIT_ARM 6145 printf("pools "); 6146 #endif 6147 /* 6148 * Initialize the pmap cache 6149 */ 6150 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6151 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6152 LIST_INIT(&pmap_pmaps); 6153 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6154 6155 /* 6156 * Initialize the pv pool. 6157 */ 6158 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6159 &pmap_bootstrap_pv_allocator, IPL_NONE); 6160 6161 /* 6162 * Initialize the L2 dtable pool and cache. 6163 */ 6164 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6165 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6166 6167 /* 6168 * Initialise the L2 descriptor table pool and cache 6169 */ 6170 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6171 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6172 pmap_l2ptp_ctor, NULL, NULL); 6173 6174 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6175 6176 cpu_dcache_wbinv_all(); 6177 } 6178 6179 static bool 6180 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6181 { 6182 #ifdef ARM_MMU_EXTENDED 6183 return false; 6184 #else 6185 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6186 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6187 return false; 6188 6189 const vaddr_t eva = va + nptes * PAGE_SIZE; 6190 int rv = 0; 6191 6192 while (va < eva) { 6193 /* 6194 * Make sure the descriptor itself has the correct cache mode 6195 */ 6196 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6197 pd_entry_t pde = *pdep; 6198 6199 if (l1pte_section_p(pde)) { 6200 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6201 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6202 *pdep = (pde & ~L1_S_CACHE_MASK) | 6203 pte_l1_s_cache_mode_pt; 6204 PDE_SYNC(pdep); 6205 cpu_dcache_wbinv_range((vaddr_t)pdep, 6206 sizeof(*pdep)); 6207 rv = 1; 6208 } 6209 return rv; 6210 if (pde & L1_S_V6_SUPER) { 6211 va = (va & -L1_SS_SIZE) + L1_SS_SIZE; 6212 } else { 6213 va = (va & -L1_S_SIZE) + L1_S_SIZE; 6214 } 6215 continue; 6216 } 6217 vaddr_t pa = l1pte_pa(pde); 6218 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6219 if (ptep == NULL) 6220 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6221 6222 ptep += l2pte_index(va); 6223 const pt_entry_t opte = *ptep; 6224 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6225 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6226 | pte_l2_s_cache_mode_pt; 6227 l2pte_set(ptep, npte, opte); 6228 PTE_SYNC(ptep); 6229 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6230 rv = 1; 6231 } 6232 va += PAGE_SIZE; 6233 } 6234 6235 return (rv); 6236 #endif 6237 } 6238 6239 static void 6240 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6241 { 6242 vaddr_t va = *availp; 6243 struct l2_bucket *l2b; 6244 6245 if (ptep) { 6246 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6247 if (l2b == NULL) 6248 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6249 6250 if (ptep) 6251 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6252 } 6253 6254 *vap = va; 6255 *availp = va + (PAGE_SIZE * pages); 6256 } 6257 6258 void 6259 pmap_init(void) 6260 { 6261 6262 /* 6263 * Set the available memory vars - These do not map to real memory 6264 * addresses and cannot as the physical memory is fragmented. 6265 * They are used by ps for %mem calculations. 6266 * One could argue whether this should be the entire memory or just 6267 * the memory that is useable in a user process. 6268 */ 6269 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6270 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6271 6272 /* 6273 * Now we need to free enough pv_entry structures to allow us to get 6274 * the kmem_map/kmem_object allocated and inited (done after this 6275 * function is finished). to do this we allocate one bootstrap page out 6276 * of kernel_map and use it to provide an initial pool of pv_entry 6277 * structures. we never free this page. 6278 */ 6279 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6280 6281 #ifdef ARM_MMU_EXTENDED 6282 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6283 #endif 6284 6285 pmap_initialized = true; 6286 } 6287 6288 static vaddr_t last_bootstrap_page = 0; 6289 static void *free_bootstrap_pages = NULL; 6290 6291 static void * 6292 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6293 { 6294 extern void *pool_page_alloc(struct pool *, int); 6295 vaddr_t new_page; 6296 void *rv; 6297 6298 if (pmap_initialized) 6299 return (pool_page_alloc(pp, flags)); 6300 6301 if (free_bootstrap_pages) { 6302 rv = free_bootstrap_pages; 6303 free_bootstrap_pages = *((void **)rv); 6304 return (rv); 6305 } 6306 6307 KASSERT(kernel_map != NULL); 6308 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6309 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6310 6311 KASSERT(new_page > last_bootstrap_page); 6312 last_bootstrap_page = new_page; 6313 return ((void *)new_page); 6314 } 6315 6316 static void 6317 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6318 { 6319 extern void pool_page_free(struct pool *, void *); 6320 6321 if ((vaddr_t)v <= last_bootstrap_page) { 6322 *((void **)v) = free_bootstrap_pages; 6323 free_bootstrap_pages = v; 6324 return; 6325 } 6326 6327 if (pmap_initialized) { 6328 pool_page_free(pp, v); 6329 return; 6330 } 6331 } 6332 6333 /* 6334 * pmap_postinit() 6335 * 6336 * This routine is called after the vm and kmem subsystems have been 6337 * initialised. This allows the pmap code to perform any initialisation 6338 * that can only be done one the memory allocation is in place. 6339 */ 6340 void 6341 pmap_postinit(void) 6342 { 6343 #ifndef ARM_MMU_EXTENDED 6344 extern paddr_t physical_start, physical_end; 6345 struct l1_ttable *l1; 6346 struct pglist plist; 6347 struct vm_page *m; 6348 pd_entry_t *pdep; 6349 vaddr_t va, eva; 6350 u_int loop, needed; 6351 int error; 6352 #endif 6353 6354 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6355 pool_cache_setlowat(&pmap_l2dtable_cache, 6356 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6357 6358 #ifndef ARM_MMU_EXTENDED 6359 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6360 needed -= 1; 6361 6362 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6363 6364 for (loop = 0; loop < needed; loop++, l1++) { 6365 /* Allocate a L1 page table */ 6366 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6367 if (va == 0) 6368 panic("Cannot allocate L1 KVM"); 6369 6370 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6371 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6372 if (error) 6373 panic("Cannot allocate L1 physical pages"); 6374 6375 m = TAILQ_FIRST(&plist); 6376 eva = va + L1_TABLE_SIZE; 6377 pdep = (pd_entry_t *)va; 6378 6379 while (m && va < eva) { 6380 paddr_t pa = VM_PAGE_TO_PHYS(m); 6381 6382 pmap_kenter_pa(va, pa, 6383 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6384 6385 va += PAGE_SIZE; 6386 m = TAILQ_NEXT(m, pageq.queue); 6387 } 6388 6389 #ifdef DIAGNOSTIC 6390 if (m) 6391 panic("pmap_alloc_l1pt: pglist not empty"); 6392 #endif /* DIAGNOSTIC */ 6393 6394 pmap_init_l1(l1, pdep); 6395 } 6396 6397 #ifdef DEBUG 6398 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6399 needed); 6400 #endif 6401 #endif /* !ARM_MMU_EXTENDED */ 6402 } 6403 6404 /* 6405 * Note that the following routines are used by board-specific initialisation 6406 * code to configure the initial kernel page tables. 6407 * 6408 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6409 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6410 * behaviour of the old pmap, and provides an easy migration path for 6411 * initial bring-up of the new pmap on existing ports. Fortunately, 6412 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6413 * will be deprecated. 6414 * 6415 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6416 * tables. 6417 */ 6418 6419 /* 6420 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6421 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6422 * find them as necessary. 6423 * 6424 * Note that the data on this list MUST remain valid after initarm() returns, 6425 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6426 */ 6427 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6428 6429 static vaddr_t 6430 kernel_pt_lookup(paddr_t pa) 6431 { 6432 pv_addr_t *pv; 6433 6434 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6435 if (pv->pv_pa == (pa & ~PGOFSET)) 6436 return (pv->pv_va | (pa & PGOFSET)); 6437 } 6438 return (0); 6439 } 6440 6441 /* 6442 * pmap_map_section: 6443 * 6444 * Create a single section mapping. 6445 */ 6446 void 6447 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6448 { 6449 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6450 const size_t l1slot = l1pte_index(va); 6451 pd_entry_t fl; 6452 6453 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6454 6455 switch (cache) { 6456 case PTE_NOCACHE: 6457 default: 6458 fl = 0; 6459 break; 6460 6461 case PTE_CACHE: 6462 fl = pte_l1_s_cache_mode; 6463 break; 6464 6465 case PTE_PAGETABLE: 6466 fl = pte_l1_s_cache_mode_pt; 6467 break; 6468 } 6469 6470 const pd_entry_t npde = L1_S_PROTO | pa | 6471 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6472 l1pte_setone(pdep + l1slot, npde); 6473 PDE_SYNC(pdep + l1slot); 6474 } 6475 6476 /* 6477 * pmap_map_entry: 6478 * 6479 * Create a single page mapping. 6480 */ 6481 void 6482 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6483 { 6484 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6485 const size_t l1slot = l1pte_index(va); 6486 pt_entry_t npte; 6487 pt_entry_t *ptep; 6488 6489 KASSERT(((va | pa) & PGOFSET) == 0); 6490 6491 switch (cache) { 6492 case PTE_NOCACHE: 6493 default: 6494 npte = 0; 6495 break; 6496 6497 case PTE_CACHE: 6498 npte = pte_l2_s_cache_mode; 6499 break; 6500 6501 case PTE_PAGETABLE: 6502 npte = pte_l2_s_cache_mode_pt; 6503 break; 6504 } 6505 6506 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6507 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6508 6509 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6510 if (ptep == NULL) 6511 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6512 6513 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6514 #ifdef ARM_MMU_EXTENDED 6515 if (prot & VM_PROT_EXECUTE) { 6516 npte &= ~L2_XS_XN; 6517 } 6518 #endif 6519 ptep += l2pte_index(va); 6520 l2pte_set(ptep, npte, 0); 6521 PTE_SYNC(ptep); 6522 } 6523 6524 /* 6525 * pmap_link_l2pt: 6526 * 6527 * Link the L2 page table specified by "l2pv" into the L1 6528 * page table at the slot for "va". 6529 */ 6530 void 6531 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6532 { 6533 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6534 6535 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6536 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6537 6538 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6539 | l2pv->pv_pa; 6540 6541 l1pte_set(pdep, npde); 6542 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6543 6544 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6545 } 6546 6547 /* 6548 * pmap_map_chunk: 6549 * 6550 * Map a chunk of memory using the most efficient mappings 6551 * possible (section, large page, small page) into the 6552 * provided L1 and L2 tables at the specified virtual address. 6553 */ 6554 vsize_t 6555 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6556 int prot, int cache) 6557 { 6558 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6559 pt_entry_t f1, f2s, f2l; 6560 vsize_t resid; 6561 6562 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6563 6564 if (l1pt == 0) 6565 panic("pmap_map_chunk: no L1 table provided"); 6566 6567 #ifdef VERBOSE_INIT_ARM 6568 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6569 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6570 #endif 6571 6572 switch (cache) { 6573 case PTE_NOCACHE: 6574 default: 6575 f1 = 0; 6576 f2l = 0; 6577 f2s = 0; 6578 break; 6579 6580 case PTE_CACHE: 6581 f1 = pte_l1_s_cache_mode; 6582 f2l = pte_l2_l_cache_mode; 6583 f2s = pte_l2_s_cache_mode; 6584 break; 6585 6586 case PTE_PAGETABLE: 6587 f1 = pte_l1_s_cache_mode_pt; 6588 f2l = pte_l2_l_cache_mode_pt; 6589 f2s = pte_l2_s_cache_mode_pt; 6590 break; 6591 } 6592 6593 size = resid; 6594 6595 while (resid > 0) { 6596 const size_t l1slot = l1pte_index(va); 6597 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6598 /* See if we can use a supersection mapping. */ 6599 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6600 /* Supersection are always domain 0 */ 6601 const pd_entry_t npde = L1_SS_PROTO | pa 6602 #ifdef ARM_MMU_EXTENDED_XXX 6603 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6604 #endif 6605 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6606 #ifdef VERBOSE_INIT_ARM 6607 printf("sS"); 6608 #endif 6609 l1pte_set(&pdep[l1slot], npde); 6610 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6611 va += L1_SS_SIZE; 6612 pa += L1_SS_SIZE; 6613 resid -= L1_SS_SIZE; 6614 continue; 6615 } 6616 #endif 6617 /* See if we can use a section mapping. */ 6618 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6619 const pd_entry_t npde = L1_S_PROTO | pa 6620 #ifdef ARM_MMU_EXTENDED_XXX 6621 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6622 #endif 6623 | L1_S_PROT(PTE_KERNEL, prot) | f1 6624 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6625 #ifdef VERBOSE_INIT_ARM 6626 printf("S"); 6627 #endif 6628 l1pte_set(&pdep[l1slot], npde); 6629 PDE_SYNC(&pdep[l1slot]); 6630 va += L1_S_SIZE; 6631 pa += L1_S_SIZE; 6632 resid -= L1_S_SIZE; 6633 continue; 6634 } 6635 6636 /* 6637 * Ok, we're going to use an L2 table. Make sure 6638 * one is actually in the corresponding L1 slot 6639 * for the current VA. 6640 */ 6641 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6642 panic("%s: no L2 table for VA %#lx", __func__, va); 6643 6644 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6645 if (ptep == NULL) 6646 panic("%s: can't find L2 table for VA %#lx", __func__, 6647 va); 6648 6649 ptep += l2pte_index(va); 6650 6651 /* See if we can use a L2 large page mapping. */ 6652 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6653 const pt_entry_t npte = L2_L_PROTO | pa 6654 #ifdef ARM_MMU_EXTENDED_XXX 6655 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6656 #endif 6657 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6658 #ifdef VERBOSE_INIT_ARM 6659 printf("L"); 6660 #endif 6661 l2pte_set(ptep, npte, 0); 6662 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6663 va += L2_L_SIZE; 6664 pa += L2_L_SIZE; 6665 resid -= L2_L_SIZE; 6666 continue; 6667 } 6668 6669 /* Use a small page mapping. */ 6670 #ifdef VERBOSE_INIT_ARM 6671 printf("P"); 6672 #endif 6673 const pt_entry_t npte = L2_S_PROTO | pa 6674 #ifdef ARM_MMU_EXTENDED_XXX 6675 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6676 #endif 6677 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6678 l2pte_set(ptep, npte, 0); 6679 PTE_SYNC(ptep); 6680 va += PAGE_SIZE; 6681 pa += PAGE_SIZE; 6682 resid -= PAGE_SIZE; 6683 } 6684 #ifdef VERBOSE_INIT_ARM 6685 printf("\n"); 6686 #endif 6687 return (size); 6688 } 6689 6690 /********************** Static device map routines ***************************/ 6691 6692 static const struct pmap_devmap *pmap_devmap_table; 6693 6694 /* 6695 * Register the devmap table. This is provided in case early console 6696 * initialization needs to register mappings created by bootstrap code 6697 * before pmap_devmap_bootstrap() is called. 6698 */ 6699 void 6700 pmap_devmap_register(const struct pmap_devmap *table) 6701 { 6702 6703 pmap_devmap_table = table; 6704 } 6705 6706 /* 6707 * Map all of the static regions in the devmap table, and remember 6708 * the devmap table so other parts of the kernel can look up entries 6709 * later. 6710 */ 6711 void 6712 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6713 { 6714 int i; 6715 6716 pmap_devmap_table = table; 6717 6718 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6719 #ifdef VERBOSE_INIT_ARM 6720 printf("devmap: %08lx -> %08lx @ %08lx\n", 6721 pmap_devmap_table[i].pd_pa, 6722 pmap_devmap_table[i].pd_pa + 6723 pmap_devmap_table[i].pd_size - 1, 6724 pmap_devmap_table[i].pd_va); 6725 #endif 6726 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6727 pmap_devmap_table[i].pd_pa, 6728 pmap_devmap_table[i].pd_size, 6729 pmap_devmap_table[i].pd_prot, 6730 pmap_devmap_table[i].pd_cache); 6731 } 6732 } 6733 6734 const struct pmap_devmap * 6735 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6736 { 6737 uint64_t endpa; 6738 int i; 6739 6740 if (pmap_devmap_table == NULL) 6741 return (NULL); 6742 6743 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6744 6745 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6746 if (pa >= pmap_devmap_table[i].pd_pa && 6747 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6748 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6749 return (&pmap_devmap_table[i]); 6750 } 6751 6752 return (NULL); 6753 } 6754 6755 const struct pmap_devmap * 6756 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6757 { 6758 int i; 6759 6760 if (pmap_devmap_table == NULL) 6761 return (NULL); 6762 6763 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6764 if (va >= pmap_devmap_table[i].pd_va && 6765 va + size - 1 <= pmap_devmap_table[i].pd_va + 6766 pmap_devmap_table[i].pd_size - 1) 6767 return (&pmap_devmap_table[i]); 6768 } 6769 6770 return (NULL); 6771 } 6772 6773 /********************** PTE initialization routines **************************/ 6774 6775 /* 6776 * These routines are called when the CPU type is identified to set up 6777 * the PTE prototypes, cache modes, etc. 6778 * 6779 * The variables are always here, just in case modules need to reference 6780 * them (though, they shouldn't). 6781 */ 6782 6783 pt_entry_t pte_l1_s_cache_mode; 6784 pt_entry_t pte_l1_s_wc_mode; 6785 pt_entry_t pte_l1_s_cache_mode_pt; 6786 pt_entry_t pte_l1_s_cache_mask; 6787 6788 pt_entry_t pte_l2_l_cache_mode; 6789 pt_entry_t pte_l2_l_wc_mode; 6790 pt_entry_t pte_l2_l_cache_mode_pt; 6791 pt_entry_t pte_l2_l_cache_mask; 6792 6793 pt_entry_t pte_l2_s_cache_mode; 6794 pt_entry_t pte_l2_s_wc_mode; 6795 pt_entry_t pte_l2_s_cache_mode_pt; 6796 pt_entry_t pte_l2_s_cache_mask; 6797 6798 pt_entry_t pte_l1_s_prot_u; 6799 pt_entry_t pte_l1_s_prot_w; 6800 pt_entry_t pte_l1_s_prot_ro; 6801 pt_entry_t pte_l1_s_prot_mask; 6802 6803 pt_entry_t pte_l2_s_prot_u; 6804 pt_entry_t pte_l2_s_prot_w; 6805 pt_entry_t pte_l2_s_prot_ro; 6806 pt_entry_t pte_l2_s_prot_mask; 6807 6808 pt_entry_t pte_l2_l_prot_u; 6809 pt_entry_t pte_l2_l_prot_w; 6810 pt_entry_t pte_l2_l_prot_ro; 6811 pt_entry_t pte_l2_l_prot_mask; 6812 6813 pt_entry_t pte_l1_ss_proto; 6814 pt_entry_t pte_l1_s_proto; 6815 pt_entry_t pte_l1_c_proto; 6816 pt_entry_t pte_l2_s_proto; 6817 6818 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6819 void (*pmap_zero_page_func)(paddr_t); 6820 6821 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6822 void 6823 pmap_pte_init_generic(void) 6824 { 6825 6826 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6827 pte_l1_s_wc_mode = L1_S_B; 6828 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6829 6830 pte_l2_l_cache_mode = L2_B|L2_C; 6831 pte_l2_l_wc_mode = L2_B; 6832 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6833 6834 pte_l2_s_cache_mode = L2_B|L2_C; 6835 pte_l2_s_wc_mode = L2_B; 6836 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6837 6838 /* 6839 * If we have a write-through cache, set B and C. If 6840 * we have a write-back cache, then we assume setting 6841 * only C will make those pages write-through (except for those 6842 * Cortex CPUs which can read the L1 caches). 6843 */ 6844 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6845 #if ARM_MMU_V7 > 0 6846 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6847 #endif 6848 #if ARM_MMU_V6 > 0 6849 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6850 #endif 6851 || false) { 6852 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6853 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6854 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6855 } else { 6856 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6857 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6858 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6859 } 6860 6861 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6862 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6863 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6864 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6865 6866 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6867 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6868 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6869 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6870 6871 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6872 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6873 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6874 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6875 6876 pte_l1_ss_proto = L1_SS_PROTO_generic; 6877 pte_l1_s_proto = L1_S_PROTO_generic; 6878 pte_l1_c_proto = L1_C_PROTO_generic; 6879 pte_l2_s_proto = L2_S_PROTO_generic; 6880 6881 pmap_copy_page_func = pmap_copy_page_generic; 6882 pmap_zero_page_func = pmap_zero_page_generic; 6883 } 6884 6885 #if defined(CPU_ARM8) 6886 void 6887 pmap_pte_init_arm8(void) 6888 { 6889 6890 /* 6891 * ARM8 is compatible with generic, but we need to use 6892 * the page tables uncached. 6893 */ 6894 pmap_pte_init_generic(); 6895 6896 pte_l1_s_cache_mode_pt = 0; 6897 pte_l2_l_cache_mode_pt = 0; 6898 pte_l2_s_cache_mode_pt = 0; 6899 } 6900 #endif /* CPU_ARM8 */ 6901 6902 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6903 void 6904 pmap_pte_init_arm9(void) 6905 { 6906 6907 /* 6908 * ARM9 is compatible with generic, but we want to use 6909 * write-through caching for now. 6910 */ 6911 pmap_pte_init_generic(); 6912 6913 pte_l1_s_cache_mode = L1_S_C; 6914 pte_l2_l_cache_mode = L2_C; 6915 pte_l2_s_cache_mode = L2_C; 6916 6917 pte_l1_s_wc_mode = L1_S_B; 6918 pte_l2_l_wc_mode = L2_B; 6919 pte_l2_s_wc_mode = L2_B; 6920 6921 pte_l1_s_cache_mode_pt = L1_S_C; 6922 pte_l2_l_cache_mode_pt = L2_C; 6923 pte_l2_s_cache_mode_pt = L2_C; 6924 } 6925 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6926 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6927 6928 #if defined(CPU_ARM10) 6929 void 6930 pmap_pte_init_arm10(void) 6931 { 6932 6933 /* 6934 * ARM10 is compatible with generic, but we want to use 6935 * write-through caching for now. 6936 */ 6937 pmap_pte_init_generic(); 6938 6939 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6940 pte_l2_l_cache_mode = L2_B | L2_C; 6941 pte_l2_s_cache_mode = L2_B | L2_C; 6942 6943 pte_l1_s_cache_mode = L1_S_B; 6944 pte_l2_l_cache_mode = L2_B; 6945 pte_l2_s_cache_mode = L2_B; 6946 6947 pte_l1_s_cache_mode_pt = L1_S_C; 6948 pte_l2_l_cache_mode_pt = L2_C; 6949 pte_l2_s_cache_mode_pt = L2_C; 6950 6951 } 6952 #endif /* CPU_ARM10 */ 6953 6954 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6955 void 6956 pmap_pte_init_arm11(void) 6957 { 6958 6959 /* 6960 * ARM11 is compatible with generic, but we want to use 6961 * write-through caching for now. 6962 */ 6963 pmap_pte_init_generic(); 6964 6965 pte_l1_s_cache_mode = L1_S_C; 6966 pte_l2_l_cache_mode = L2_C; 6967 pte_l2_s_cache_mode = L2_C; 6968 6969 pte_l1_s_wc_mode = L1_S_B; 6970 pte_l2_l_wc_mode = L2_B; 6971 pte_l2_s_wc_mode = L2_B; 6972 6973 pte_l1_s_cache_mode_pt = L1_S_C; 6974 pte_l2_l_cache_mode_pt = L2_C; 6975 pte_l2_s_cache_mode_pt = L2_C; 6976 } 6977 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6978 6979 #if ARM_MMU_SA1 == 1 6980 void 6981 pmap_pte_init_sa1(void) 6982 { 6983 6984 /* 6985 * The StrongARM SA-1 cache does not have a write-through 6986 * mode. So, do the generic initialization, then reset 6987 * the page table cache mode to B=1,C=1, and note that 6988 * the PTEs need to be sync'd. 6989 */ 6990 pmap_pte_init_generic(); 6991 6992 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6993 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6994 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6995 6996 pmap_needs_pte_sync = 1; 6997 } 6998 #endif /* ARM_MMU_SA1 == 1*/ 6999 7000 #if ARM_MMU_XSCALE == 1 7001 #if (ARM_NMMUS > 1) 7002 static u_int xscale_use_minidata; 7003 #endif 7004 7005 void 7006 pmap_pte_init_xscale(void) 7007 { 7008 uint32_t auxctl; 7009 int write_through = 0; 7010 7011 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7012 pte_l1_s_wc_mode = L1_S_B; 7013 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7014 7015 pte_l2_l_cache_mode = L2_B|L2_C; 7016 pte_l2_l_wc_mode = L2_B; 7017 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7018 7019 pte_l2_s_cache_mode = L2_B|L2_C; 7020 pte_l2_s_wc_mode = L2_B; 7021 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7022 7023 pte_l1_s_cache_mode_pt = L1_S_C; 7024 pte_l2_l_cache_mode_pt = L2_C; 7025 pte_l2_s_cache_mode_pt = L2_C; 7026 7027 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7028 /* 7029 * The XScale core has an enhanced mode where writes that 7030 * miss the cache cause a cache line to be allocated. This 7031 * is significantly faster than the traditional, write-through 7032 * behavior of this case. 7033 */ 7034 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7035 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7036 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7037 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7038 7039 #ifdef XSCALE_CACHE_WRITE_THROUGH 7040 /* 7041 * Some versions of the XScale core have various bugs in 7042 * their cache units, the work-around for which is to run 7043 * the cache in write-through mode. Unfortunately, this 7044 * has a major (negative) impact on performance. So, we 7045 * go ahead and run fast-and-loose, in the hopes that we 7046 * don't line up the planets in a way that will trip the 7047 * bugs. 7048 * 7049 * However, we give you the option to be slow-but-correct. 7050 */ 7051 write_through = 1; 7052 #elif defined(XSCALE_CACHE_WRITE_BACK) 7053 /* force write back cache mode */ 7054 write_through = 0; 7055 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7056 /* 7057 * Intel PXA2[15]0 processors are known to have a bug in 7058 * write-back cache on revision 4 and earlier (stepping 7059 * A[01] and B[012]). Fixed for C0 and later. 7060 */ 7061 { 7062 uint32_t id, type; 7063 7064 id = cpufunc_id(); 7065 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7066 7067 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7068 if ((id & CPU_ID_REVISION_MASK) < 5) { 7069 /* write through for stepping A0-1 and B0-2 */ 7070 write_through = 1; 7071 } 7072 } 7073 } 7074 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7075 7076 if (write_through) { 7077 pte_l1_s_cache_mode = L1_S_C; 7078 pte_l2_l_cache_mode = L2_C; 7079 pte_l2_s_cache_mode = L2_C; 7080 } 7081 7082 #if (ARM_NMMUS > 1) 7083 xscale_use_minidata = 1; 7084 #endif 7085 7086 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7087 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7088 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7089 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7090 7091 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7092 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7093 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7094 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7095 7096 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7097 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7098 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7099 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7100 7101 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7102 pte_l1_s_proto = L1_S_PROTO_xscale; 7103 pte_l1_c_proto = L1_C_PROTO_xscale; 7104 pte_l2_s_proto = L2_S_PROTO_xscale; 7105 7106 pmap_copy_page_func = pmap_copy_page_xscale; 7107 pmap_zero_page_func = pmap_zero_page_xscale; 7108 7109 /* 7110 * Disable ECC protection of page table access, for now. 7111 */ 7112 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7113 auxctl &= ~XSCALE_AUXCTL_P; 7114 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7115 } 7116 7117 /* 7118 * xscale_setup_minidata: 7119 * 7120 * Set up the mini-data cache clean area. We require the 7121 * caller to allocate the right amount of physically and 7122 * virtually contiguous space. 7123 */ 7124 void 7125 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7126 { 7127 extern vaddr_t xscale_minidata_clean_addr; 7128 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7129 pd_entry_t *pde = (pd_entry_t *) l1pt; 7130 vsize_t size; 7131 uint32_t auxctl; 7132 7133 xscale_minidata_clean_addr = va; 7134 7135 /* Round it to page size. */ 7136 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7137 7138 for (; size != 0; 7139 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7140 const size_t l1slot = l1pte_index(va); 7141 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7142 if (ptep == NULL) 7143 panic("xscale_setup_minidata: can't find L2 table for " 7144 "VA 0x%08lx", va); 7145 7146 ptep += l2pte_index(va); 7147 pt_entry_t opte = *ptep; 7148 l2pte_set(ptep, 7149 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7150 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7151 } 7152 7153 /* 7154 * Configure the mini-data cache for write-back with 7155 * read/write-allocate. 7156 * 7157 * NOTE: In order to reconfigure the mini-data cache, we must 7158 * make sure it contains no valid data! In order to do that, 7159 * we must issue a global data cache invalidate command! 7160 * 7161 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7162 * THIS IS VERY IMPORTANT! 7163 */ 7164 7165 /* Invalidate data and mini-data. */ 7166 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7167 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7168 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7169 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7170 } 7171 7172 /* 7173 * Change the PTEs for the specified kernel mappings such that they 7174 * will use the mini data cache instead of the main data cache. 7175 */ 7176 void 7177 pmap_uarea(vaddr_t va) 7178 { 7179 vaddr_t next_bucket, eva; 7180 7181 #if (ARM_NMMUS > 1) 7182 if (xscale_use_minidata == 0) 7183 return; 7184 #endif 7185 7186 eva = va + USPACE; 7187 7188 while (va < eva) { 7189 next_bucket = L2_NEXT_BUCKET_VA(va); 7190 if (next_bucket > eva) 7191 next_bucket = eva; 7192 7193 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7194 KDASSERT(l2b != NULL); 7195 7196 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7197 pt_entry_t *ptep = sptep; 7198 7199 while (va < next_bucket) { 7200 const pt_entry_t opte = *ptep; 7201 if (!l2pte_minidata_p(opte)) { 7202 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7203 cpu_tlb_flushD_SE(va); 7204 l2pte_set(ptep, opte & ~L2_B, opte); 7205 } 7206 ptep += PAGE_SIZE / L2_S_SIZE; 7207 va += PAGE_SIZE; 7208 } 7209 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7210 } 7211 cpu_cpwait(); 7212 } 7213 #endif /* ARM_MMU_XSCALE == 1 */ 7214 7215 7216 #if defined(CPU_ARM11MPCORE) 7217 7218 void 7219 pmap_pte_init_arm11mpcore(void) 7220 { 7221 7222 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7223 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7224 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7225 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7226 /* use extended small page (without APn, with TEX) */ 7227 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7228 #else 7229 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7230 #endif 7231 7232 /* write-back, write-allocate */ 7233 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7234 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7235 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7236 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7237 #else 7238 /* no TEX. read-allocate */ 7239 pte_l2_s_cache_mode = L2_C | L2_B; 7240 #endif 7241 /* 7242 * write-back, write-allocate for page tables. 7243 */ 7244 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7245 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7246 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7247 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7248 #else 7249 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7250 #endif 7251 7252 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7253 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7254 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7255 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7256 7257 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7258 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7259 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7260 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7261 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7262 7263 #else 7264 /* with AP[0..3] */ 7265 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7266 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7267 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7268 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7269 #endif 7270 7271 #ifdef ARM11MPCORE_COMPAT_MMU 7272 /* with AP[0..3] */ 7273 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7274 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7275 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7276 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7277 7278 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7279 pte_l1_s_proto = L1_S_PROTO_armv6; 7280 pte_l1_c_proto = L1_C_PROTO_armv6; 7281 pte_l2_s_proto = L2_S_PROTO_armv6c; 7282 #else 7283 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7284 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7285 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7286 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7287 7288 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7289 pte_l1_s_proto = L1_S_PROTO_armv6; 7290 pte_l1_c_proto = L1_C_PROTO_armv6; 7291 pte_l2_s_proto = L2_S_PROTO_armv6n; 7292 #endif 7293 7294 pmap_copy_page_func = pmap_copy_page_generic; 7295 pmap_zero_page_func = pmap_zero_page_generic; 7296 pmap_needs_pte_sync = 1; 7297 } 7298 #endif /* CPU_ARM11MPCORE */ 7299 7300 7301 #if ARM_MMU_V7 == 1 7302 void 7303 pmap_pte_init_armv7(void) 7304 { 7305 /* 7306 * The ARMv7-A MMU is mostly compatible with generic. If the 7307 * AP field is zero, that now means "no access" rather than 7308 * read-only. The prototypes are a little different because of 7309 * the XN bit. 7310 */ 7311 pmap_pte_init_generic(); 7312 7313 pmap_needs_pte_sync = 1; 7314 7315 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7316 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7317 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7318 7319 /* 7320 * If the core support coherent walk then updates to translation tables 7321 * do not require a clean to the point of unification to ensure 7322 * visibility by subsequent translation table walks. That means we can 7323 * map everything shareable and cached and the right thing will happen. 7324 */ 7325 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7326 pmap_needs_pte_sync = 0; 7327 7328 /* 7329 * write-back, no write-allocate, shareable for normal pages. 7330 */ 7331 pte_l1_s_cache_mode |= L1_S_V6_S; 7332 pte_l2_l_cache_mode |= L2_XS_S; 7333 pte_l2_s_cache_mode |= L2_XS_S; 7334 7335 /* 7336 * write-back, no write-allocate, shareable for page tables. 7337 */ 7338 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7339 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7340 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7341 } 7342 7343 /* 7344 * Check the Memory Model Features to see if this CPU supports 7345 * the TLBIASID coproc op. 7346 */ 7347 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7348 arm_has_tlbiasid_p = true; 7349 } 7350 7351 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7352 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7353 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7354 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7355 7356 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7357 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7358 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7359 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7360 7361 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7362 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7363 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7364 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7365 7366 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7367 pte_l1_s_proto = L1_S_PROTO_armv7; 7368 pte_l1_c_proto = L1_C_PROTO_armv7; 7369 pte_l2_s_proto = L2_S_PROTO_armv7; 7370 7371 } 7372 #endif /* ARM_MMU_V7 */ 7373 7374 /* 7375 * return the PA of the current L1 table, for use when handling a crash dump 7376 */ 7377 uint32_t 7378 pmap_kernel_L1_addr(void) 7379 { 7380 #ifdef ARM_MMU_EXTENDED 7381 return pmap_kernel()->pm_l1_pa; 7382 #else 7383 return pmap_kernel()->pm_l1->l1_physaddr; 7384 #endif 7385 } 7386 7387 #if defined(DDB) 7388 /* 7389 * A couple of ddb-callable functions for dumping pmaps 7390 */ 7391 void pmap_dump_all(void); 7392 void pmap_dump(pmap_t); 7393 7394 void 7395 pmap_dump_all(void) 7396 { 7397 pmap_t pm; 7398 7399 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7400 if (pm == pmap_kernel()) 7401 continue; 7402 pmap_dump(pm); 7403 printf("\n"); 7404 } 7405 } 7406 7407 static pt_entry_t ncptes[64]; 7408 static void pmap_dump_ncpg(pmap_t); 7409 7410 void 7411 pmap_dump(pmap_t pm) 7412 { 7413 struct l2_dtable *l2; 7414 struct l2_bucket *l2b; 7415 pt_entry_t *ptep, pte; 7416 vaddr_t l2_va, l2b_va, va; 7417 int i, j, k, occ, rows = 0; 7418 7419 if (pm == pmap_kernel()) 7420 printf("pmap_kernel (%p): ", pm); 7421 else 7422 printf("user pmap (%p): ", pm); 7423 7424 #ifdef ARM_MMU_EXTENDED 7425 printf("l1 at %p\n", pmap_l1_kva(pm)); 7426 #else 7427 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7428 #endif 7429 7430 l2_va = 0; 7431 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7432 l2 = pm->pm_l2[i]; 7433 7434 if (l2 == NULL || l2->l2_occupancy == 0) 7435 continue; 7436 7437 l2b_va = l2_va; 7438 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7439 l2b = &l2->l2_bucket[j]; 7440 7441 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7442 continue; 7443 7444 ptep = l2b->l2b_kva; 7445 7446 for (k = 0; k < 256 && ptep[k] == 0; k++) 7447 ; 7448 7449 k &= ~63; 7450 occ = l2b->l2b_occupancy; 7451 va = l2b_va + (k * 4096); 7452 for (; k < 256; k++, va += 0x1000) { 7453 char ch = ' '; 7454 if ((k % 64) == 0) { 7455 if ((rows % 8) == 0) { 7456 printf( 7457 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7458 } 7459 printf("%08lx: ", va); 7460 } 7461 7462 ncptes[k & 63] = 0; 7463 pte = ptep[k]; 7464 if (pte == 0) { 7465 ch = '.'; 7466 } else { 7467 occ--; 7468 switch (pte & 0x0c) { 7469 case 0x00: 7470 ch = 'D'; /* No cache No buff */ 7471 break; 7472 case 0x04: 7473 ch = 'B'; /* No cache buff */ 7474 break; 7475 case 0x08: 7476 if (pte & 0x40) 7477 ch = 'm'; 7478 else 7479 ch = 'C'; /* Cache No buff */ 7480 break; 7481 case 0x0c: 7482 ch = 'F'; /* Cache Buff */ 7483 break; 7484 } 7485 7486 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7487 ch += 0x20; 7488 7489 if ((pte & 0xc) == 0) 7490 ncptes[k & 63] = pte; 7491 } 7492 7493 if ((k % 64) == 63) { 7494 rows++; 7495 printf("%c\n", ch); 7496 pmap_dump_ncpg(pm); 7497 if (occ == 0) 7498 break; 7499 } else 7500 printf("%c", ch); 7501 } 7502 } 7503 } 7504 } 7505 7506 static void 7507 pmap_dump_ncpg(pmap_t pm) 7508 { 7509 struct vm_page *pg; 7510 struct vm_page_md *md; 7511 struct pv_entry *pv; 7512 int i; 7513 7514 for (i = 0; i < 63; i++) { 7515 if (ncptes[i] == 0) 7516 continue; 7517 7518 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7519 if (pg == NULL) 7520 continue; 7521 md = VM_PAGE_TO_MD(pg); 7522 7523 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7524 VM_PAGE_TO_PHYS(pg), 7525 md->krw_mappings, md->kro_mappings, 7526 md->urw_mappings, md->uro_mappings); 7527 7528 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7529 printf(" %c va 0x%08lx, flags 0x%x\n", 7530 (pm == pv->pv_pmap) ? '*' : ' ', 7531 pv->pv_va, pv->pv_flags); 7532 } 7533 } 7534 } 7535 #endif 7536 7537 #ifdef PMAP_STEAL_MEMORY 7538 void 7539 pmap_boot_pageadd(pv_addr_t *newpv) 7540 { 7541 pv_addr_t *pv, *npv; 7542 7543 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7544 if (newpv->pv_pa < pv->pv_va) { 7545 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7546 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7547 newpv->pv_size += pv->pv_size; 7548 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7549 } 7550 pv = NULL; 7551 } else { 7552 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7553 pv = npv) { 7554 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7555 KASSERT(pv->pv_pa < newpv->pv_pa); 7556 if (newpv->pv_pa > npv->pv_pa) 7557 continue; 7558 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7559 pv->pv_size += newpv->pv_size; 7560 return; 7561 } 7562 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7563 break; 7564 newpv->pv_size += npv->pv_size; 7565 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7566 SLIST_REMOVE_AFTER(newpv, pv_list); 7567 return; 7568 } 7569 } 7570 } 7571 7572 if (pv) { 7573 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7574 } else { 7575 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7576 } 7577 } 7578 7579 void 7580 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7581 pv_addr_t *rpv) 7582 { 7583 pv_addr_t *pv, **pvp; 7584 struct vm_physseg *ps; 7585 size_t i; 7586 7587 KASSERT(amount & PGOFSET); 7588 KASSERT((mask & PGOFSET) == 0); 7589 KASSERT((match & PGOFSET) == 0); 7590 KASSERT(amount != 0); 7591 7592 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7593 (pv = *pvp) != NULL; 7594 pvp = &SLIST_NEXT(pv, pv_list)) { 7595 pv_addr_t *newpv; 7596 psize_t off; 7597 /* 7598 * If this entry is too small to satify the request... 7599 */ 7600 KASSERT(pv->pv_size > 0); 7601 if (pv->pv_size < amount) 7602 continue; 7603 7604 for (off = 0; off <= mask; off += PAGE_SIZE) { 7605 if (((pv->pv_pa + off) & mask) == match 7606 && off + amount <= pv->pv_size) 7607 break; 7608 } 7609 if (off > mask) 7610 continue; 7611 7612 rpv->pv_va = pv->pv_va + off; 7613 rpv->pv_pa = pv->pv_pa + off; 7614 rpv->pv_size = amount; 7615 pv->pv_size -= amount; 7616 if (pv->pv_size == 0) { 7617 KASSERT(off == 0); 7618 KASSERT((vaddr_t) pv == rpv->pv_va); 7619 *pvp = SLIST_NEXT(pv, pv_list); 7620 } else if (off == 0) { 7621 KASSERT((vaddr_t) pv == rpv->pv_va); 7622 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7623 *newpv = *pv; 7624 newpv->pv_pa += amount; 7625 newpv->pv_va += amount; 7626 *pvp = newpv; 7627 } else if (off < pv->pv_size) { 7628 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7629 *newpv = *pv; 7630 newpv->pv_size -= off; 7631 newpv->pv_pa += off + amount; 7632 newpv->pv_va += off + amount; 7633 7634 SLIST_NEXT(pv, pv_list) = newpv; 7635 pv->pv_size = off; 7636 } else { 7637 KASSERT((vaddr_t) pv != rpv->pv_va); 7638 } 7639 memset((void *)rpv->pv_va, 0, amount); 7640 return; 7641 } 7642 7643 if (vm_nphysseg == 0) 7644 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7645 7646 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7647 (pv = *pvp) != NULL; 7648 pvp = &SLIST_NEXT(pv, pv_list)) { 7649 if (SLIST_NEXT(pv, pv_list) == NULL) 7650 break; 7651 } 7652 KASSERT(mask == 0); 7653 for (i = 0; i < vm_nphysseg; i++) { 7654 ps = VM_PHYSMEM_PTR(i); 7655 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7656 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7657 rpv->pv_va = pv->pv_va; 7658 rpv->pv_pa = pv->pv_pa; 7659 rpv->pv_size = amount; 7660 *pvp = NULL; 7661 pmap_map_chunk(kernel_l1pt.pv_va, 7662 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7663 ptoa(ps->avail_start), 7664 amount - pv->pv_size, 7665 VM_PROT_READ|VM_PROT_WRITE, 7666 PTE_CACHE); 7667 ps->avail_start += atop(amount - pv->pv_size); 7668 /* 7669 * If we consumed the entire physseg, remove it. 7670 */ 7671 if (ps->avail_start == ps->avail_end) { 7672 for (--vm_nphysseg; i < vm_nphysseg; i++) 7673 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7674 } 7675 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7676 return; 7677 } 7678 } 7679 7680 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7681 } 7682 7683 vaddr_t 7684 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7685 { 7686 pv_addr_t pv; 7687 7688 pmap_boot_pagealloc(size, 0, 0, &pv); 7689 7690 return pv.pv_va; 7691 } 7692 #endif /* PMAP_STEAL_MEMORY */ 7693 7694 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7695 { 7696 sysctl_createv(clog, 0, NULL, NULL, 7697 CTLFLAG_PERMANENT, 7698 CTLTYPE_NODE, "machdep", NULL, 7699 NULL, 0, NULL, 0, 7700 CTL_MACHDEP, CTL_EOL); 7701 7702 sysctl_createv(clog, 0, NULL, NULL, 7703 CTLFLAG_PERMANENT, 7704 CTLTYPE_INT, "kmpages", 7705 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7706 NULL, 0, &pmap_kmpages, 0, 7707 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7708 } 7709 7710 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7711 struct vm_page * 7712 arm_pmap_alloc_poolpage(int flags) 7713 { 7714 /* 7715 * On some systems, only some pages may be "coherent" for dma and we 7716 * want to prefer those for pool pages (think mbufs) but fallback to 7717 * any page if none is available. 7718 */ 7719 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7720 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7721 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 7722 } 7723 7724 return uvm_pagealloc(NULL, 0, NULL, flags); 7725 } 7726 #endif 7727 7728 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7729 void 7730 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7731 { 7732 /* nothing */ 7733 } 7734 7735 int 7736 pic_ipi_shootdown(void *arg) 7737 { 7738 #if PMAP_NEED_TLB_SHOOTDOWN 7739 pmap_tlb_shootdown_process() 7740 #endif 7741 return 1; 7742 } 7743 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7744
Indexes created Sat Sep 27 14:09:57 GMT 2025