pmap.c revision 1.284
1 /* $NetBSD: pmap.c,v 1.284 2014/04/11 04:19:47 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 //#include <arm/arm32/katelib.h> 218 219 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.284 2014/04/11 04:19:47 matt Exp $"); 220 221 //#define PMAP_DEBUG 222 #ifdef PMAP_DEBUG 223 224 /* XXX need to get rid of all refs to this */ 225 int pmap_debug_level = 0; 226 227 /* 228 * for switching to potentially finer grained debugging 229 */ 230 #define PDB_FOLLOW 0x0001 231 #define PDB_INIT 0x0002 232 #define PDB_ENTER 0x0004 233 #define PDB_REMOVE 0x0008 234 #define PDB_CREATE 0x0010 235 #define PDB_PTPAGE 0x0020 236 #define PDB_GROWKERN 0x0040 237 #define PDB_BITS 0x0080 238 #define PDB_COLLECT 0x0100 239 #define PDB_PROTECT 0x0200 240 #define PDB_MAP_L1 0x0400 241 #define PDB_BOOTSTRAP 0x1000 242 #define PDB_PARANOIA 0x2000 243 #define PDB_WIRING 0x4000 244 #define PDB_PVDUMP 0x8000 245 #define PDB_VAC 0x10000 246 #define PDB_KENTER 0x20000 247 #define PDB_KREMOVE 0x40000 248 #define PDB_EXEC 0x80000 249 250 int debugmap = 1; 251 int pmapdebug = 0; 252 #define NPDEBUG(_lev_,_stat_) \ 253 if (pmapdebug & (_lev_)) \ 254 ((_stat_)) 255 256 #else /* PMAP_DEBUG */ 257 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 258 #endif /* PMAP_DEBUG */ 259 260 /* 261 * pmap_kernel() points here 262 */ 263 static struct pmap kernel_pmap_store = { 264 #ifndef ARM_MMU_EXTENDED 265 .pm_activated = true, 266 .pm_domain = PMAP_DOMAIN_KERNEL, 267 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 268 #endif 269 }; 270 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 271 #undef pmap_kernel 272 #define pmap_kernel() (&kernel_pmap_store) 273 #ifdef PMAP_NEED_ALLOC_POOLPAGE 274 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 275 #endif 276 277 /* 278 * Pool and cache that pmap structures are allocated from. 279 * We use a cache to avoid clearing the pm_l2[] array (1KB) 280 * in pmap_create(). 281 */ 282 static struct pool_cache pmap_cache; 283 static LIST_HEAD(, pmap) pmap_pmaps; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 static struct evcnt pmap_ev_exec_synced_map = 426 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 427 #ifndef ARM_MMU_EXTENDED 428 static struct evcnt pmap_ev_exec_synced_unmap = 429 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 430 static struct evcnt pmap_ev_exec_synced_remap = 431 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 432 static struct evcnt pmap_ev_exec_synced_clearbit = 433 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 440 #ifndef ARM_MMU_EXTENDED 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 /* 489 * pmap copy/zero page, and mem(5) hook point 490 */ 491 static pt_entry_t *csrc_pte, *cdst_pte; 492 static vaddr_t csrcp, cdstp; 493 #ifdef MULTIPROCESSOR 494 static size_t cnptes; 495 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 497 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 499 #else 500 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + (o)) 503 #define cpu_cdstp(o) (cdstp + (o)) 504 #endif 505 vaddr_t memhook; /* used by mem.c & others */ 506 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 507 kmutex_t pmap_lock __cacheline_aligned; 508 extern void *msgbufaddr; 509 int pmap_kmpages; 510 /* 511 * Flag to indicate if pmap_init() has done its thing 512 */ 513 bool pmap_initialized; 514 515 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 516 /* 517 * Start of direct-mapped memory 518 */ 519 vaddr_t pmap_directbase = KERNEL_BASE; 520 #endif 521 522 /* 523 * Misc. locking data structures 524 */ 525 526 static inline void 527 pmap_acquire_pmap_lock(pmap_t pm) 528 { 529 if (pm == pmap_kernel()) { 530 #ifdef MULTIPROCESSOR 531 KERNEL_LOCK(1, NULL); 532 #endif 533 } else { 534 mutex_enter(pm->pm_lock); 535 } 536 } 537 538 static inline void 539 pmap_release_pmap_lock(pmap_t pm) 540 { 541 if (pm == pmap_kernel()) { 542 #ifdef MULTIPROCESSOR 543 KERNEL_UNLOCK_ONE(NULL); 544 #endif 545 } else { 546 mutex_exit(pm->pm_lock); 547 } 548 } 549 550 static inline void 551 pmap_acquire_page_lock(struct vm_page_md *md) 552 { 553 mutex_enter(&pmap_lock); 554 } 555 556 static inline void 557 pmap_release_page_lock(struct vm_page_md *md) 558 { 559 mutex_exit(&pmap_lock); 560 } 561 562 #ifdef DIAGNOSTIC 563 static inline int 564 pmap_page_locked_p(struct vm_page_md *md) 565 { 566 return mutex_owned(&pmap_lock); 567 } 568 #endif 569 570 571 /* 572 * Metadata for L1 translation tables. 573 */ 574 #ifndef ARM_MMU_EXTENDED 575 struct l1_ttable { 576 /* Entry on the L1 Table list */ 577 SLIST_ENTRY(l1_ttable) l1_link; 578 579 /* Entry on the L1 Least Recently Used list */ 580 TAILQ_ENTRY(l1_ttable) l1_lru; 581 582 /* Track how many domains are allocated from this L1 */ 583 volatile u_int l1_domain_use_count; 584 585 /* 586 * A free-list of domain numbers for this L1. 587 * We avoid using ffs() and a bitmap to track domains since ffs() 588 * is slow on ARM. 589 */ 590 uint8_t l1_domain_first; 591 uint8_t l1_domain_free[PMAP_DOMAINS]; 592 593 /* Physical address of this L1 page table */ 594 paddr_t l1_physaddr; 595 596 /* KVA of this L1 page table */ 597 pd_entry_t *l1_kva; 598 }; 599 600 /* 601 * L1 Page Tables are tracked using a Least Recently Used list. 602 * - New L1s are allocated from the HEAD. 603 * - Freed L1s are added to the TAIl. 604 * - Recently accessed L1s (where an 'access' is some change to one of 605 * the userland pmaps which owns this L1) are moved to the TAIL. 606 */ 607 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 608 static kmutex_t l1_lru_lock __cacheline_aligned; 609 610 /* 611 * A list of all L1 tables 612 */ 613 static SLIST_HEAD(, l1_ttable) l1_list; 614 #endif /* ARM_MMU_EXTENDED */ 615 616 /* 617 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 618 * 619 * This is normally 16MB worth L2 page descriptors for any given pmap. 620 * Reference counts are maintained for L2 descriptors so they can be 621 * freed when empty. 622 */ 623 struct l2_dtable { 624 /* The number of L2 page descriptors allocated to this l2_dtable */ 625 u_int l2_occupancy; 626 627 /* List of L2 page descriptors */ 628 struct l2_bucket { 629 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 630 paddr_t l2b_pa; /* Physical address of same */ 631 u_short l2b_l1slot; /* This L2 table's L1 index */ 632 u_short l2b_occupancy; /* How many active descriptors */ 633 } l2_bucket[L2_BUCKET_SIZE]; 634 }; 635 636 /* 637 * Given an L1 table index, calculate the corresponding l2_dtable index 638 * and bucket index within the l2_dtable. 639 */ 640 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 641 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 642 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 643 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 644 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 645 646 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 647 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 648 649 /* 650 * Given a virtual address, this macro returns the 651 * virtual address required to drop into the next L2 bucket. 652 */ 653 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 654 655 /* 656 * L2 allocation. 657 */ 658 #define pmap_alloc_l2_dtable() \ 659 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 660 #define pmap_free_l2_dtable(l2) \ 661 pool_cache_put(&pmap_l2dtable_cache, (l2)) 662 #define pmap_alloc_l2_ptp(pap) \ 663 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 664 PR_NOWAIT, (pap))) 665 666 /* 667 * We try to map the page tables write-through, if possible. However, not 668 * all CPUs have a write-through cache mode, so on those we have to sync 669 * the cache when we frob page tables. 670 * 671 * We try to evaluate this at compile time, if possible. However, it's 672 * not always possible to do that, hence this run-time var. 673 */ 674 int pmap_needs_pte_sync; 675 676 /* 677 * Real definition of pv_entry. 678 */ 679 struct pv_entry { 680 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 681 pmap_t pv_pmap; /* pmap where mapping lies */ 682 vaddr_t pv_va; /* virtual address for mapping */ 683 u_int pv_flags; /* flags */ 684 }; 685 686 /* 687 * Macro to determine if a mapping might be resident in the 688 * instruction cache and/or TLB 689 */ 690 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 691 /* 692 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 693 * there are no explicit accesses, so there may be always be TLB entries to 694 * flush. If we used ASIDs then this would not be a problem. 695 */ 696 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 697 #else 698 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 699 #endif 700 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 701 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 702 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 703 704 /* 705 * Macro to determine if a mapping might be resident in the 706 * data cache and/or TLB 707 */ 708 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 709 /* 710 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 711 * there are no explicit accesses, so there may be always be TLB entries to 712 * flush. If we used ASIDs then this would not be a problem. 713 */ 714 #define PV_BEEN_REFD(f) (1) 715 #else 716 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 717 #endif 718 719 /* 720 * Local prototypes 721 */ 722 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 723 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 724 pt_entry_t **); 725 static bool pmap_is_current(pmap_t); 726 static bool pmap_is_cached(pmap_t); 727 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 728 pmap_t, vaddr_t, u_int); 729 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 730 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 731 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 732 u_int, u_int); 733 734 static void pmap_pinit(pmap_t); 735 static int pmap_pmap_ctor(void *, void *, int); 736 737 static void pmap_alloc_l1(pmap_t); 738 static void pmap_free_l1(pmap_t); 739 #ifndef ARM_MMU_EXTENDED 740 static void pmap_use_l1(pmap_t); 741 #endif 742 743 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 744 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 745 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 746 static int pmap_l2ptp_ctor(void *, void *, int); 747 static int pmap_l2dtable_ctor(void *, void *, int); 748 749 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 750 #ifdef PMAP_CACHE_VIVT 751 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 752 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 753 #endif 754 755 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 756 #ifdef PMAP_CACHE_VIVT 757 static bool pmap_clean_page(struct vm_page_md *, bool); 758 #endif 759 #ifdef PMAP_CACHE_VIPT 760 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 761 enum pmap_flush_op { 762 PMAP_FLUSH_PRIMARY, 763 PMAP_FLUSH_SECONDARY, 764 PMAP_CLEAN_PRIMARY 765 }; 766 #ifndef ARM_MMU_EXTENDED 767 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 768 #endif 769 #endif 770 static void pmap_page_remove(struct vm_page_md *, paddr_t); 771 772 #ifndef ARM_MMU_EXTENDED 773 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 774 #endif 775 static vaddr_t kernel_pt_lookup(paddr_t); 776 777 778 /* 779 * Misc variables 780 */ 781 vaddr_t virtual_avail; 782 vaddr_t virtual_end; 783 vaddr_t pmap_curmaxkvaddr; 784 785 paddr_t avail_start; 786 paddr_t avail_end; 787 788 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 789 pv_addr_t kernelpages; 790 pv_addr_t kernel_l1pt; 791 pv_addr_t systempage; 792 793 /* Function to set the debug level of the pmap code */ 794 795 #ifdef PMAP_DEBUG 796 void 797 pmap_debug(int level) 798 { 799 pmap_debug_level = level; 800 printf("pmap_debug: level=%d\n", pmap_debug_level); 801 } 802 #endif /* PMAP_DEBUG */ 803 804 #ifdef PMAP_CACHE_VIPT 805 #define PMAP_VALIDATE_MD_PAGE(md) \ 806 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 807 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 808 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 809 #endif /* PMAP_CACHE_VIPT */ 810 /* 811 * A bunch of routines to conditionally flush the caches/TLB depending 812 * on whether the specified pmap actually needs to be flushed at any 813 * given time. 814 */ 815 static inline void 816 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 817 { 818 #ifdef ARM_MMU_EXTENDED 819 pmap_tlb_invalidate_addr(pm, va); 820 #else 821 if (pm->pm_cstate.cs_tlb_id != 0) { 822 if (PV_BEEN_EXECD(flags)) { 823 cpu_tlb_flushID_SE(va); 824 } else if (PV_BEEN_REFD(flags)) { 825 cpu_tlb_flushD_SE(va); 826 } 827 } 828 #endif /* ARM_MMU_EXTENDED */ 829 } 830 831 static inline void 832 pmap_tlb_flushID(pmap_t pm) 833 { 834 #ifdef ARM_MMU_EXTENDED 835 pmap_tlb_asid_release_all(pm); 836 #else 837 if (pm->pm_cstate.cs_tlb_id) { 838 cpu_tlb_flushID(); 839 #if ARM_MMU_V7 == 0 840 /* 841 * Speculative loads by Cortex cores can cause TLB entries to 842 * be filled even if there are no explicit accesses, so there 843 * may be always be TLB entries to flush. If we used ASIDs 844 * then it would not be a problem. 845 * This is not true for other CPUs. 846 */ 847 pm->pm_cstate.cs_tlb = 0; 848 #endif /* ARM_MMU_V7 */ 849 } 850 #endif /* ARM_MMU_EXTENDED */ 851 } 852 853 static inline void 854 pmap_tlb_flushD(pmap_t pm) 855 { 856 #ifdef ARM_MMU_EXTENDED 857 pmap_tlb_asid_release_all(pm); 858 #else 859 if (pm->pm_cstate.cs_tlb_d) { 860 cpu_tlb_flushD(); 861 #if ARM_MMU_V7 == 0 862 /* 863 * Speculative loads by Cortex cores can cause TLB entries to 864 * be filled even if there are no explicit accesses, so there 865 * may be always be TLB entries to flush. If we used ASIDs 866 * then it would not be a problem. 867 * This is not true for other CPUs. 868 */ 869 pm->pm_cstate.cs_tlb_d = 0; 870 #endif /* ARM_MMU_V7 */ 871 } 872 #endif /* ARM_MMU_EXTENDED */ 873 } 874 875 #ifdef PMAP_CACHE_VIVT 876 static inline void 877 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 878 { 879 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 880 cpu_idcache_wbinv_range(va, PAGE_SIZE); 881 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 882 if (do_inv) { 883 if (flags & PVF_WRITE) 884 cpu_dcache_wbinv_range(va, PAGE_SIZE); 885 else 886 cpu_dcache_inv_range(va, PAGE_SIZE); 887 } else if (flags & PVF_WRITE) { 888 cpu_dcache_wb_range(va, PAGE_SIZE); 889 } 890 } 891 } 892 893 static inline void 894 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 895 { 896 if (PV_BEEN_EXECD(flags)) { 897 if (pm->pm_cstate.cs_cache_id) { 898 cpu_idcache_wbinv_all(); 899 pm->pm_cstate.cs_cache = 0; 900 } 901 } else if (pm->pm_cstate.cs_cache_d) { 902 cpu_dcache_wbinv_all(); 903 pm->pm_cstate.cs_cache_d = 0; 904 } 905 } 906 #endif /* PMAP_CACHE_VIVT */ 907 908 static inline uint8_t 909 pmap_domain(pmap_t pm) 910 { 911 #ifdef ARM_MMU_EXTENDED 912 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 913 #else 914 return pm->pm_domain; 915 #endif 916 } 917 918 static inline pd_entry_t * 919 pmap_l1_kva(pmap_t pm) 920 { 921 #ifdef ARM_MMU_EXTENDED 922 return pm->pm_l1; 923 #else 924 return pm->pm_l1->l1_kva; 925 #endif 926 } 927 928 static inline bool 929 pmap_is_current(pmap_t pm) 930 { 931 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 932 return true; 933 934 return false; 935 } 936 937 static inline bool 938 pmap_is_cached(pmap_t pm) 939 { 940 #ifdef ARM_MMU_EXTENDED 941 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 942 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 943 return true; 944 #else 945 struct cpu_info * const ci = curcpu(); 946 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 947 || ci->ci_pmap_lastuser == pm) 948 return true; 949 #endif /* ARM_MMU_EXTENDED */ 950 951 return false; 952 } 953 954 /* 955 * PTE_SYNC_CURRENT: 956 * 957 * Make sure the pte is written out to RAM. 958 * We need to do this for one of two cases: 959 * - We're dealing with the kernel pmap 960 * - There is no pmap active in the cache/tlb. 961 * - The specified pmap is 'active' in the cache/tlb. 962 */ 963 #ifdef PMAP_INCLUDE_PTE_SYNC 964 #define PTE_SYNC_CURRENT(pm, ptep) \ 965 do { \ 966 if (PMAP_NEEDS_PTE_SYNC && \ 967 pmap_is_cached(pm)) \ 968 PTE_SYNC(ptep); \ 969 } while (/*CONSTCOND*/0) 970 #else 971 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 972 #endif 973 974 /* 975 * main pv_entry manipulation functions: 976 * pmap_enter_pv: enter a mapping onto a vm_page list 977 * pmap_remove_pv: remove a mapping from a vm_page list 978 * 979 * NOTE: pmap_enter_pv expects to lock the pvh itself 980 * pmap_remove_pv expects the caller to lock the pvh before calling 981 */ 982 983 /* 984 * pmap_enter_pv: enter a mapping onto a vm_page lst 985 * 986 * => caller should hold the proper lock on pmap_main_lock 987 * => caller should have pmap locked 988 * => we will gain the lock on the vm_page and allocate the new pv_entry 989 * => caller should adjust ptp's wire_count before calling 990 * => caller should not adjust pmap's wire_count 991 */ 992 static void 993 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 994 vaddr_t va, u_int flags) 995 { 996 struct pv_entry **pvp; 997 998 NPDEBUG(PDB_PVDUMP, 999 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 1000 1001 pv->pv_pmap = pm; 1002 pv->pv_va = va; 1003 pv->pv_flags = flags; 1004 1005 pvp = &SLIST_FIRST(&md->pvh_list); 1006 #ifdef PMAP_CACHE_VIPT 1007 /* 1008 * Insert unmanaged entries, writeable first, at the head of 1009 * the pv list. 1010 */ 1011 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1012 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1013 pvp = &SLIST_NEXT(*pvp, pv_link); 1014 } 1015 if (!PV_IS_WRITE_P(flags)) { 1016 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1017 pvp = &SLIST_NEXT(*pvp, pv_link); 1018 } 1019 #endif 1020 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1021 *pvp = pv; /* ... locked list */ 1022 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1023 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1024 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1025 md->pvh_attrs |= PVF_KMOD; 1026 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1027 md->pvh_attrs |= PVF_DIRTY; 1028 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1029 #endif 1030 if (pm == pmap_kernel()) { 1031 PMAPCOUNT(kernel_mappings); 1032 if (flags & PVF_WRITE) 1033 md->krw_mappings++; 1034 else 1035 md->kro_mappings++; 1036 } else { 1037 if (flags & PVF_WRITE) 1038 md->urw_mappings++; 1039 else 1040 md->uro_mappings++; 1041 } 1042 1043 #ifdef PMAP_CACHE_VIPT 1044 #ifndef ARM_MMU_EXTENDED 1045 /* 1046 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1047 * do it here as well to keep the mappings & KVF_WRITE consistent. 1048 */ 1049 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1050 md->pvh_attrs |= PVF_WRITE; 1051 } 1052 #endif 1053 /* 1054 * If this is an exec mapping and its the first exec mapping 1055 * for this page, make sure to sync the I-cache. 1056 */ 1057 if (PV_IS_EXEC_P(flags)) { 1058 #ifndef ARM_MMU_EXTENDED 1059 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1060 pmap_syncicache_page(md, pa); 1061 PMAPCOUNT(exec_synced_map); 1062 } 1063 #endif 1064 PMAPCOUNT(exec_mappings); 1065 } 1066 #endif 1067 1068 PMAPCOUNT(mappings); 1069 1070 if (pv->pv_flags & PVF_WIRED) 1071 ++pm->pm_stats.wired_count; 1072 } 1073 1074 /* 1075 * 1076 * pmap_find_pv: Find a pv entry 1077 * 1078 * => caller should hold lock on vm_page 1079 */ 1080 static inline struct pv_entry * 1081 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1082 { 1083 struct pv_entry *pv; 1084 1085 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1086 if (pm == pv->pv_pmap && va == pv->pv_va) 1087 break; 1088 } 1089 1090 return (pv); 1091 } 1092 1093 /* 1094 * pmap_remove_pv: try to remove a mapping from a pv_list 1095 * 1096 * => caller should hold proper lock on pmap_main_lock 1097 * => pmap should be locked 1098 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1099 * => caller should adjust ptp's wire_count and free PTP if needed 1100 * => caller should NOT adjust pmap's wire_count 1101 * => we return the removed pv 1102 */ 1103 static struct pv_entry * 1104 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1105 { 1106 struct pv_entry *pv, **prevptr; 1107 1108 NPDEBUG(PDB_PVDUMP, 1109 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1110 1111 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1112 pv = *prevptr; 1113 1114 while (pv) { 1115 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1116 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1117 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1118 if (pv->pv_flags & PVF_WIRED) { 1119 --pm->pm_stats.wired_count; 1120 } 1121 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1122 if (pm == pmap_kernel()) { 1123 PMAPCOUNT(kernel_unmappings); 1124 if (pv->pv_flags & PVF_WRITE) 1125 md->krw_mappings--; 1126 else 1127 md->kro_mappings--; 1128 } else { 1129 if (pv->pv_flags & PVF_WRITE) 1130 md->urw_mappings--; 1131 else 1132 md->uro_mappings--; 1133 } 1134 1135 PMAPCOUNT(unmappings); 1136 #ifdef PMAP_CACHE_VIPT 1137 if (!(pv->pv_flags & PVF_WRITE)) 1138 break; 1139 /* 1140 * If this page has had an exec mapping, then if 1141 * this was the last mapping, discard the contents, 1142 * otherwise sync the i-cache for this page. 1143 */ 1144 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1145 #ifdef ARM_MMU_EXTENDED 1146 md->pvh_attrs &= ~PVF_EXEC; 1147 PMAPCOUNT(exec_discarded_unmap); 1148 #else 1149 if (SLIST_EMPTY(&md->pvh_list)) { 1150 md->pvh_attrs &= ~PVF_EXEC; 1151 PMAPCOUNT(exec_discarded_unmap); 1152 } else { 1153 pmap_syncicache_page(md, pa); 1154 PMAPCOUNT(exec_synced_unmap); 1155 } 1156 #endif /* ARM_MMU_EXTENDED */ 1157 } 1158 #endif /* PMAP_CACHE_VIPT */ 1159 break; 1160 } 1161 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1162 pv = *prevptr; /* advance */ 1163 } 1164 1165 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1166 /* 1167 * If we no longer have a WRITEABLE KENTRY at the head of list, 1168 * clear the KMOD attribute from the page. 1169 */ 1170 if (SLIST_FIRST(&md->pvh_list) == NULL 1171 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1172 md->pvh_attrs &= ~PVF_KMOD; 1173 1174 /* 1175 * If this was a writeable page and there are no more writeable 1176 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1177 * the contents to memory. 1178 */ 1179 if (arm_cache_prefer_mask != 0) { 1180 if (md->krw_mappings + md->urw_mappings == 0) 1181 md->pvh_attrs &= ~PVF_WRITE; 1182 PMAP_VALIDATE_MD_PAGE(md); 1183 } 1184 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1185 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1186 1187 return(pv); /* return removed pv */ 1188 } 1189 1190 /* 1191 * 1192 * pmap_modify_pv: Update pv flags 1193 * 1194 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1195 * => caller should NOT adjust pmap's wire_count 1196 * => caller must call pmap_vac_me_harder() if writable status of a page 1197 * may have changed. 1198 * => we return the old flags 1199 * 1200 * Modify a physical-virtual mapping in the pv table 1201 */ 1202 static u_int 1203 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1204 u_int clr_mask, u_int set_mask) 1205 { 1206 struct pv_entry *npv; 1207 u_int flags, oflags; 1208 1209 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1210 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1211 1212 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1213 return (0); 1214 1215 NPDEBUG(PDB_PVDUMP, 1216 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1217 1218 /* 1219 * There is at least one VA mapping this page. 1220 */ 1221 1222 if (clr_mask & (PVF_REF | PVF_MOD)) { 1223 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1224 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1225 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1226 md->pvh_attrs |= PVF_DIRTY; 1227 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1228 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1229 } 1230 1231 oflags = npv->pv_flags; 1232 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1233 1234 if ((flags ^ oflags) & PVF_WIRED) { 1235 if (flags & PVF_WIRED) 1236 ++pm->pm_stats.wired_count; 1237 else 1238 --pm->pm_stats.wired_count; 1239 } 1240 1241 if ((flags ^ oflags) & PVF_WRITE) { 1242 if (pm == pmap_kernel()) { 1243 if (flags & PVF_WRITE) { 1244 md->krw_mappings++; 1245 md->kro_mappings--; 1246 } else { 1247 md->kro_mappings++; 1248 md->krw_mappings--; 1249 } 1250 } else { 1251 if (flags & PVF_WRITE) { 1252 md->urw_mappings++; 1253 md->uro_mappings--; 1254 } else { 1255 md->uro_mappings++; 1256 md->urw_mappings--; 1257 } 1258 } 1259 } 1260 #ifdef PMAP_CACHE_VIPT 1261 if (arm_cache_prefer_mask != 0) { 1262 if (md->urw_mappings + md->krw_mappings == 0) { 1263 md->pvh_attrs &= ~PVF_WRITE; 1264 } else { 1265 md->pvh_attrs |= PVF_WRITE; 1266 } 1267 } 1268 #ifndef ARM_MMU_EXTENDED 1269 /* 1270 * We have two cases here: the first is from enter_pv (new exec 1271 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1272 * Since in latter, pmap_enter_pv won't do anything, we just have 1273 * to do what pmap_remove_pv would do. 1274 */ 1275 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1276 || (PV_IS_EXEC_P(md->pvh_attrs) 1277 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1278 pmap_syncicache_page(md, pa); 1279 PMAPCOUNT(exec_synced_remap); 1280 } 1281 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1282 #endif /* !ARM_MMU_EXTENDED */ 1283 #endif /* PMAP_CACHE_VIPT */ 1284 1285 PMAPCOUNT(remappings); 1286 1287 return (oflags); 1288 } 1289 1290 /* 1291 * Allocate an L1 translation table for the specified pmap. 1292 * This is called at pmap creation time. 1293 */ 1294 static void 1295 pmap_alloc_l1(pmap_t pm) 1296 { 1297 #ifdef ARM_MMU_EXTENDED 1298 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1299 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1300 struct vm_page *pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1301 #else 1302 struct vm_page *pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1303 #endif 1304 bool ok __diagused; 1305 KASSERT(pg != NULL); 1306 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1307 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0xdeadbeef); 1308 KASSERT(ok); 1309 KASSERT(va >= KERNEL_BASE); 1310 1311 #else 1312 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1313 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1314 UVM_KMF_WIRED|UVM_KMF_ZERO); 1315 KASSERT(!va); 1316 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1317 #endif 1318 pm->pm_l1 = (pd_entry_t *)va; 1319 #else 1320 struct l1_ttable *l1; 1321 uint8_t domain; 1322 1323 /* 1324 * Remove the L1 at the head of the LRU list 1325 */ 1326 mutex_spin_enter(&l1_lru_lock); 1327 l1 = TAILQ_FIRST(&l1_lru_list); 1328 KDASSERT(l1 != NULL); 1329 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1330 1331 /* 1332 * Pick the first available domain number, and update 1333 * the link to the next number. 1334 */ 1335 domain = l1->l1_domain_first; 1336 l1->l1_domain_first = l1->l1_domain_free[domain]; 1337 1338 /* 1339 * If there are still free domain numbers in this L1, 1340 * put it back on the TAIL of the LRU list. 1341 */ 1342 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1343 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1344 1345 mutex_spin_exit(&l1_lru_lock); 1346 1347 /* 1348 * Fix up the relevant bits in the pmap structure 1349 */ 1350 pm->pm_l1 = l1; 1351 pm->pm_domain = domain + 1; 1352 #endif 1353 } 1354 1355 /* 1356 * Free an L1 translation table. 1357 * This is called at pmap destruction time. 1358 */ 1359 static void 1360 pmap_free_l1(pmap_t pm) 1361 { 1362 #ifdef ARM_MMU_EXTENDED 1363 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1364 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1365 uvm_pagefree(pg); 1366 #else 1367 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1368 #endif 1369 pm->pm_l1 = NULL; 1370 pm->pm_l1_pa = 0; 1371 #else 1372 struct l1_ttable *l1 = pm->pm_l1; 1373 1374 mutex_spin_enter(&l1_lru_lock); 1375 1376 /* 1377 * If this L1 is currently on the LRU list, remove it. 1378 */ 1379 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1380 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1381 1382 /* 1383 * Free up the domain number which was allocated to the pmap 1384 */ 1385 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1386 l1->l1_domain_first = pmap_domain(pm) - 1; 1387 l1->l1_domain_use_count--; 1388 1389 /* 1390 * The L1 now must have at least 1 free domain, so add 1391 * it back to the LRU list. If the use count is zero, 1392 * put it at the head of the list, otherwise it goes 1393 * to the tail. 1394 */ 1395 if (l1->l1_domain_use_count == 0) 1396 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1397 else 1398 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1399 1400 mutex_spin_exit(&l1_lru_lock); 1401 #endif /* ARM_MMU_EXTENDED */ 1402 } 1403 1404 #ifndef ARM_MMU_EXTENDED 1405 static inline void 1406 pmap_use_l1(pmap_t pm) 1407 { 1408 struct l1_ttable *l1; 1409 1410 /* 1411 * Do nothing if we're in interrupt context. 1412 * Access to an L1 by the kernel pmap must not affect 1413 * the LRU list. 1414 */ 1415 if (cpu_intr_p() || pm == pmap_kernel()) 1416 return; 1417 1418 l1 = pm->pm_l1; 1419 1420 /* 1421 * If the L1 is not currently on the LRU list, just return 1422 */ 1423 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1424 return; 1425 1426 mutex_spin_enter(&l1_lru_lock); 1427 1428 /* 1429 * Check the use count again, now that we've acquired the lock 1430 */ 1431 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1432 mutex_spin_exit(&l1_lru_lock); 1433 return; 1434 } 1435 1436 /* 1437 * Move the L1 to the back of the LRU list 1438 */ 1439 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1440 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1441 1442 mutex_spin_exit(&l1_lru_lock); 1443 } 1444 #endif /* !ARM_MMU_EXTENDED */ 1445 1446 /* 1447 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1448 * 1449 * Free an L2 descriptor table. 1450 */ 1451 static inline void 1452 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1453 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1454 #else 1455 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1456 #endif 1457 { 1458 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1459 /* 1460 * Note: With a write-back cache, we may need to sync this 1461 * L2 table before re-using it. 1462 * This is because it may have belonged to a non-current 1463 * pmap, in which case the cache syncs would have been 1464 * skipped for the pages that were being unmapped. If the 1465 * L2 table were then to be immediately re-allocated to 1466 * the *current* pmap, it may well contain stale mappings 1467 * which have not yet been cleared by a cache write-back 1468 * and so would still be visible to the mmu. 1469 */ 1470 if (need_sync) 1471 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1472 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1473 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1474 } 1475 1476 /* 1477 * Returns a pointer to the L2 bucket associated with the specified pmap 1478 * and VA, or NULL if no L2 bucket exists for the address. 1479 */ 1480 static inline struct l2_bucket * 1481 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1482 { 1483 const size_t l1slot = l1pte_index(va); 1484 struct l2_dtable *l2; 1485 struct l2_bucket *l2b; 1486 1487 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1488 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1489 return (NULL); 1490 1491 return (l2b); 1492 } 1493 1494 /* 1495 * Returns a pointer to the L2 bucket associated with the specified pmap 1496 * and VA. 1497 * 1498 * If no L2 bucket exists, perform the necessary allocations to put an L2 1499 * bucket/page table in place. 1500 * 1501 * Note that if a new L2 bucket/page was allocated, the caller *must* 1502 * increment the bucket occupancy counter appropriately *before* 1503 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1504 * the bucket/page in the meantime. 1505 */ 1506 static struct l2_bucket * 1507 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1508 { 1509 const size_t l1slot = l1pte_index(va); 1510 struct l2_dtable *l2; 1511 1512 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1513 /* 1514 * No mapping at this address, as there is 1515 * no entry in the L1 table. 1516 * Need to allocate a new l2_dtable. 1517 */ 1518 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1519 return (NULL); 1520 1521 /* 1522 * Link it into the parent pmap 1523 */ 1524 pm->pm_l2[L2_IDX(l1slot)] = l2; 1525 } 1526 1527 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1528 1529 /* 1530 * Fetch pointer to the L2 page table associated with the address. 1531 */ 1532 if (l2b->l2b_kva == NULL) { 1533 pt_entry_t *ptep; 1534 1535 /* 1536 * No L2 page table has been allocated. Chances are, this 1537 * is because we just allocated the l2_dtable, above. 1538 */ 1539 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1540 /* 1541 * Oops, no more L2 page tables available at this 1542 * time. We may need to deallocate the l2_dtable 1543 * if we allocated a new one above. 1544 */ 1545 if (l2->l2_occupancy == 0) { 1546 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1547 pmap_free_l2_dtable(l2); 1548 } 1549 return (NULL); 1550 } 1551 1552 l2->l2_occupancy++; 1553 l2b->l2b_kva = ptep; 1554 l2b->l2b_l1slot = l1slot; 1555 1556 #ifdef ARM_MMU_EXTENDED 1557 /* 1558 * We know there will be a mapping here, so simply 1559 * enter this PTP into the L1 now. 1560 */ 1561 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1562 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1563 | L1_C_DOM(pmap_domain(pm)); 1564 KASSERT(*pdep == 0); 1565 l1pte_setone(pdep, npde); 1566 PTE_SYNC(pdep); 1567 #endif 1568 } 1569 1570 return (l2b); 1571 } 1572 1573 /* 1574 * One or more mappings in the specified L2 descriptor table have just been 1575 * invalidated. 1576 * 1577 * Garbage collect the metadata and descriptor table itself if necessary. 1578 * 1579 * The pmap lock must be acquired when this is called (not necessary 1580 * for the kernel pmap). 1581 */ 1582 static void 1583 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1584 { 1585 KASSERT(pm != pmap_kernel()); 1586 KDASSERT(count <= l2b->l2b_occupancy); 1587 1588 /* 1589 * Update the bucket's reference count according to how many 1590 * PTEs the caller has just invalidated. 1591 */ 1592 l2b->l2b_occupancy -= count; 1593 1594 /* 1595 * Note: 1596 * 1597 * Level 2 page tables allocated to the kernel pmap are never freed 1598 * as that would require checking all Level 1 page tables and 1599 * removing any references to the Level 2 page table. See also the 1600 * comment elsewhere about never freeing bootstrap L2 descriptors. 1601 * 1602 * We make do with just invalidating the mapping in the L2 table. 1603 * 1604 * This isn't really a big deal in practice and, in fact, leads 1605 * to a performance win over time as we don't need to continually 1606 * alloc/free. 1607 */ 1608 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1609 return; 1610 1611 /* 1612 * There are no more valid mappings in this level 2 page table. 1613 * Go ahead and NULL-out the pointer in the bucket, then 1614 * free the page table. 1615 */ 1616 const size_t l1slot = l2b->l2b_l1slot; 1617 pt_entry_t * const ptep = l2b->l2b_kva; 1618 l2b->l2b_kva = NULL; 1619 1620 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1621 pd_entry_t pde __diagused = *pdep; 1622 1623 #ifdef ARM_MMU_EXTENDED 1624 /* 1625 * Invalidate the L1 slot. 1626 */ 1627 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1628 #else 1629 /* 1630 * If the L1 slot matches the pmap's domain number, then invalidate it. 1631 */ 1632 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1633 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1634 #endif 1635 l1pte_setone(pdep, 0); 1636 PDE_SYNC(pdep); 1637 #ifndef ARM_MMU_EXTENDED 1638 } 1639 #endif 1640 1641 /* 1642 * Release the L2 descriptor table back to the pool cache. 1643 */ 1644 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1645 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1646 #else 1647 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1648 #endif 1649 1650 /* 1651 * Update the reference count in the associated l2_dtable 1652 */ 1653 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1654 if (--l2->l2_occupancy > 0) 1655 return; 1656 1657 /* 1658 * There are no more valid mappings in any of the Level 1 1659 * slots managed by this l2_dtable. Go ahead and NULL-out 1660 * the pointer in the parent pmap and free the l2_dtable. 1661 */ 1662 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1663 pmap_free_l2_dtable(l2); 1664 } 1665 1666 /* 1667 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1668 * structures. 1669 */ 1670 static int 1671 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1672 { 1673 #ifndef PMAP_INCLUDE_PTE_SYNC 1674 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1675 1676 /* 1677 * The mappings for these page tables were initially made using 1678 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1679 * mode will not be right for page table mappings. To avoid 1680 * polluting the pmap_kenter_pa() code with a special case for 1681 * page tables, we simply fix up the cache-mode here if it's not 1682 * correct. 1683 */ 1684 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1685 const struct l2_bucket * const l2b = 1686 pmap_get_l2_bucket(pmap_kernel(), va); 1687 KASSERTMSG(l2b != NULL, "%#lx", va); 1688 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1689 const pt_entry_t opte = *ptep; 1690 1691 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1692 /* 1693 * Page tables must have the cache-mode set correctly. 1694 */ 1695 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1696 | pte_l2_s_cache_mode_pt; 1697 l2pte_set(ptep, npte, opte); 1698 PTE_SYNC(ptep); 1699 cpu_tlb_flushD_SE(va); 1700 cpu_cpwait(); 1701 } 1702 } 1703 #endif 1704 1705 memset(v, 0, L2_TABLE_SIZE_REAL); 1706 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1707 return (0); 1708 } 1709 1710 static int 1711 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1712 { 1713 1714 memset(v, 0, sizeof(struct l2_dtable)); 1715 return (0); 1716 } 1717 1718 static int 1719 pmap_pmap_ctor(void *arg, void *v, int flags) 1720 { 1721 1722 memset(v, 0, sizeof(struct pmap)); 1723 return (0); 1724 } 1725 1726 static void 1727 pmap_pinit(pmap_t pm) 1728 { 1729 #ifndef ARM_HAS_VBAR 1730 struct l2_bucket *l2b; 1731 1732 if (vector_page < KERNEL_BASE) { 1733 /* 1734 * Map the vector page. 1735 */ 1736 pmap_enter(pm, vector_page, systempage.pv_pa, 1737 VM_PROT_READ | VM_PROT_EXECUTE, 1738 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1739 pmap_update(pm); 1740 1741 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1742 l2b = pmap_get_l2_bucket(pm, vector_page); 1743 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1744 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1745 L1_C_DOM(pmap_domain(pm)); 1746 } else 1747 pm->pm_pl1vec = NULL; 1748 #endif 1749 } 1750 1751 #ifdef PMAP_CACHE_VIVT 1752 /* 1753 * Since we have a virtually indexed cache, we may need to inhibit caching if 1754 * there is more than one mapping and at least one of them is writable. 1755 * Since we purge the cache on every context switch, we only need to check for 1756 * other mappings within the same pmap, or kernel_pmap. 1757 * This function is also called when a page is unmapped, to possibly reenable 1758 * caching on any remaining mappings. 1759 * 1760 * The code implements the following logic, where: 1761 * 1762 * KW = # of kernel read/write pages 1763 * KR = # of kernel read only pages 1764 * UW = # of user read/write pages 1765 * UR = # of user read only pages 1766 * 1767 * KC = kernel mapping is cacheable 1768 * UC = user mapping is cacheable 1769 * 1770 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1771 * +--------------------------------------------- 1772 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1773 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1774 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1775 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1776 */ 1777 1778 static const int pmap_vac_flags[4][4] = { 1779 {-1, 0, 0, PVF_KNC}, 1780 {0, 0, PVF_NC, PVF_NC}, 1781 {0, PVF_NC, PVF_NC, PVF_NC}, 1782 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1783 }; 1784 1785 static inline int 1786 pmap_get_vac_flags(const struct vm_page_md *md) 1787 { 1788 int kidx, uidx; 1789 1790 kidx = 0; 1791 if (md->kro_mappings || md->krw_mappings > 1) 1792 kidx |= 1; 1793 if (md->krw_mappings) 1794 kidx |= 2; 1795 1796 uidx = 0; 1797 if (md->uro_mappings || md->urw_mappings > 1) 1798 uidx |= 1; 1799 if (md->urw_mappings) 1800 uidx |= 2; 1801 1802 return (pmap_vac_flags[uidx][kidx]); 1803 } 1804 1805 static inline void 1806 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1807 { 1808 int nattr; 1809 1810 nattr = pmap_get_vac_flags(md); 1811 1812 if (nattr < 0) { 1813 md->pvh_attrs &= ~PVF_NC; 1814 return; 1815 } 1816 1817 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1818 return; 1819 1820 if (pm == pmap_kernel()) 1821 pmap_vac_me_kpmap(md, pa, pm, va); 1822 else 1823 pmap_vac_me_user(md, pa, pm, va); 1824 1825 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1826 } 1827 1828 static void 1829 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1830 { 1831 u_int u_cacheable, u_entries; 1832 struct pv_entry *pv; 1833 pmap_t last_pmap = pm; 1834 1835 /* 1836 * Pass one, see if there are both kernel and user pmaps for 1837 * this page. Calculate whether there are user-writable or 1838 * kernel-writable pages. 1839 */ 1840 u_cacheable = 0; 1841 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1842 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1843 u_cacheable++; 1844 } 1845 1846 u_entries = md->urw_mappings + md->uro_mappings; 1847 1848 /* 1849 * We know we have just been updating a kernel entry, so if 1850 * all user pages are already cacheable, then there is nothing 1851 * further to do. 1852 */ 1853 if (md->k_mappings == 0 && u_cacheable == u_entries) 1854 return; 1855 1856 if (u_entries) { 1857 /* 1858 * Scan over the list again, for each entry, if it 1859 * might not be set correctly, call pmap_vac_me_user 1860 * to recalculate the settings. 1861 */ 1862 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1863 /* 1864 * We know kernel mappings will get set 1865 * correctly in other calls. We also know 1866 * that if the pmap is the same as last_pmap 1867 * then we've just handled this entry. 1868 */ 1869 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1870 continue; 1871 1872 /* 1873 * If there are kernel entries and this page 1874 * is writable but non-cacheable, then we can 1875 * skip this entry also. 1876 */ 1877 if (md->k_mappings && 1878 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1879 (PVF_NC | PVF_WRITE)) 1880 continue; 1881 1882 /* 1883 * Similarly if there are no kernel-writable 1884 * entries and the page is already 1885 * read-only/cacheable. 1886 */ 1887 if (md->krw_mappings == 0 && 1888 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1889 continue; 1890 1891 /* 1892 * For some of the remaining cases, we know 1893 * that we must recalculate, but for others we 1894 * can't tell if they are correct or not, so 1895 * we recalculate anyway. 1896 */ 1897 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1898 } 1899 1900 if (md->k_mappings == 0) 1901 return; 1902 } 1903 1904 pmap_vac_me_user(md, pa, pm, va); 1905 } 1906 1907 static void 1908 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1909 { 1910 pmap_t kpmap = pmap_kernel(); 1911 struct pv_entry *pv, *npv = NULL; 1912 u_int entries = 0; 1913 u_int writable = 0; 1914 u_int cacheable_entries = 0; 1915 u_int kern_cacheable = 0; 1916 u_int other_writable = 0; 1917 1918 /* 1919 * Count mappings and writable mappings in this pmap. 1920 * Include kernel mappings as part of our own. 1921 * Keep a pointer to the first one. 1922 */ 1923 npv = NULL; 1924 KASSERT(pmap_page_locked_p(md)); 1925 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1926 /* Count mappings in the same pmap */ 1927 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1928 if (entries++ == 0) 1929 npv = pv; 1930 1931 /* Cacheable mappings */ 1932 if ((pv->pv_flags & PVF_NC) == 0) { 1933 cacheable_entries++; 1934 if (kpmap == pv->pv_pmap) 1935 kern_cacheable++; 1936 } 1937 1938 /* Writable mappings */ 1939 if (pv->pv_flags & PVF_WRITE) 1940 ++writable; 1941 } else 1942 if (pv->pv_flags & PVF_WRITE) 1943 other_writable = 1; 1944 } 1945 1946 /* 1947 * Enable or disable caching as necessary. 1948 * Note: the first entry might be part of the kernel pmap, 1949 * so we can't assume this is indicative of the state of the 1950 * other (maybe non-kpmap) entries. 1951 */ 1952 if ((entries > 1 && writable) || 1953 (entries > 0 && pm == kpmap && other_writable)) { 1954 if (cacheable_entries == 0) { 1955 return; 1956 } 1957 1958 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1959 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1960 (pv->pv_flags & PVF_NC)) 1961 continue; 1962 1963 pv->pv_flags |= PVF_NC; 1964 1965 struct l2_bucket * const l2b 1966 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1967 KASSERTMSG(l2b != NULL, "%#lx", va); 1968 pt_entry_t * const ptep 1969 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1970 const pt_entry_t opte = *ptep; 1971 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1972 1973 if ((va != pv->pv_va || pm != pv->pv_pmap) 1974 && l2pte_valid_p(npte)) { 1975 #ifdef PMAP_CACHE_VIVT 1976 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1977 true, pv->pv_flags); 1978 #endif 1979 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1980 pv->pv_flags); 1981 } 1982 1983 l2pte_set(ptep, npte, opte); 1984 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1985 } 1986 cpu_cpwait(); 1987 } else 1988 if (entries > cacheable_entries) { 1989 /* 1990 * Turn cacheing back on for some pages. If it is a kernel 1991 * page, only do so if there are no other writable pages. 1992 */ 1993 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1994 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1995 (kpmap != pv->pv_pmap || other_writable))) 1996 continue; 1997 1998 pv->pv_flags &= ~PVF_NC; 1999 2000 struct l2_bucket * const l2b 2001 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2002 KASSERTMSG(l2b != NULL, "%#lx", va); 2003 pt_entry_t * const ptep 2004 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2005 const pt_entry_t opte = *ptep; 2006 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2007 | pte_l2_s_cache_mode; 2008 2009 if (l2pte_valid_p(opte)) { 2010 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2011 pv->pv_flags); 2012 } 2013 2014 l2pte_set(ptep, npte, opte); 2015 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2016 } 2017 } 2018 } 2019 #endif 2020 2021 #ifdef PMAP_CACHE_VIPT 2022 static void 2023 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2024 { 2025 #ifndef ARM_MMU_EXTENDED 2026 struct pv_entry *pv; 2027 vaddr_t tst_mask; 2028 bool bad_alias; 2029 const u_int 2030 rw_mappings = md->urw_mappings + md->krw_mappings, 2031 ro_mappings = md->uro_mappings + md->kro_mappings; 2032 2033 /* do we need to do anything? */ 2034 if (arm_cache_prefer_mask == 0) 2035 return; 2036 2037 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2038 md, pm, va)); 2039 2040 KASSERT(!va || pm); 2041 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2042 2043 /* Already a conflict? */ 2044 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2045 /* just an add, things are already non-cached */ 2046 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2047 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2048 bad_alias = false; 2049 if (va) { 2050 PMAPCOUNT(vac_color_none); 2051 bad_alias = true; 2052 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2053 goto fixup; 2054 } 2055 pv = SLIST_FIRST(&md->pvh_list); 2056 /* the list can't be empty because it would be cachable */ 2057 if (md->pvh_attrs & PVF_KMPAGE) { 2058 tst_mask = md->pvh_attrs; 2059 } else { 2060 KASSERT(pv); 2061 tst_mask = pv->pv_va; 2062 pv = SLIST_NEXT(pv, pv_link); 2063 } 2064 /* 2065 * Only check for a bad alias if we have writable mappings. 2066 */ 2067 tst_mask &= arm_cache_prefer_mask; 2068 if (rw_mappings > 0) { 2069 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2070 /* if there's a bad alias, stop checking. */ 2071 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2072 bad_alias = true; 2073 } 2074 md->pvh_attrs |= PVF_WRITE; 2075 if (!bad_alias) 2076 md->pvh_attrs |= PVF_DIRTY; 2077 } else { 2078 /* 2079 * We have only read-only mappings. Let's see if there 2080 * are multiple colors in use or if we mapped a KMPAGE. 2081 * If the latter, we have a bad alias. If the former, 2082 * we need to remember that. 2083 */ 2084 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2085 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2086 if (md->pvh_attrs & PVF_KMPAGE) 2087 bad_alias = true; 2088 break; 2089 } 2090 } 2091 md->pvh_attrs &= ~PVF_WRITE; 2092 /* 2093 * No KMPAGE and we exited early, so we must have 2094 * multiple color mappings. 2095 */ 2096 if (!bad_alias && pv != NULL) 2097 md->pvh_attrs |= PVF_MULTCLR; 2098 } 2099 2100 /* If no conflicting colors, set everything back to cached */ 2101 if (!bad_alias) { 2102 #ifdef DEBUG 2103 if ((md->pvh_attrs & PVF_WRITE) 2104 || ro_mappings < 2) { 2105 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2106 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2107 } 2108 #endif 2109 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2110 md->pvh_attrs |= tst_mask | PVF_COLORED; 2111 /* 2112 * Restore DIRTY bit if page is modified 2113 */ 2114 if (md->pvh_attrs & PVF_DMOD) 2115 md->pvh_attrs |= PVF_DIRTY; 2116 PMAPCOUNT(vac_color_restore); 2117 } else { 2118 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2119 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2120 } 2121 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2122 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2123 } else if (!va) { 2124 KASSERT(pmap_is_page_colored_p(md)); 2125 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2126 || (md->pvh_attrs & PVF_DIRTY)); 2127 if (rw_mappings == 0) { 2128 md->pvh_attrs &= ~PVF_WRITE; 2129 if (ro_mappings == 1 2130 && (md->pvh_attrs & PVF_MULTCLR)) { 2131 /* 2132 * If this is the last readonly mapping 2133 * but it doesn't match the current color 2134 * for the page, change the current color 2135 * to match this last readonly mapping. 2136 */ 2137 pv = SLIST_FIRST(&md->pvh_list); 2138 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2139 & arm_cache_prefer_mask; 2140 if (tst_mask) { 2141 md->pvh_attrs ^= tst_mask; 2142 PMAPCOUNT(vac_color_change); 2143 } 2144 } 2145 } 2146 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2147 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2148 return; 2149 } else if (!pmap_is_page_colored_p(md)) { 2150 /* not colored so we just use its color */ 2151 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2152 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2153 PMAPCOUNT(vac_color_new); 2154 md->pvh_attrs &= PAGE_SIZE - 1; 2155 md->pvh_attrs |= PVF_COLORED 2156 | (va & arm_cache_prefer_mask) 2157 | (rw_mappings > 0 ? PVF_WRITE : 0); 2158 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2159 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2160 return; 2161 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2162 bad_alias = false; 2163 if (rw_mappings > 0) { 2164 /* 2165 * We now have writeable mappings and if we have 2166 * readonly mappings in more than once color, we have 2167 * an aliasing problem. Regardless mark the page as 2168 * writeable. 2169 */ 2170 if (md->pvh_attrs & PVF_MULTCLR) { 2171 if (ro_mappings < 2) { 2172 /* 2173 * If we only have less than two 2174 * read-only mappings, just flush the 2175 * non-primary colors from the cache. 2176 */ 2177 pmap_flush_page(md, pa, 2178 PMAP_FLUSH_SECONDARY); 2179 } else { 2180 bad_alias = true; 2181 } 2182 } 2183 md->pvh_attrs |= PVF_WRITE; 2184 } 2185 /* If no conflicting colors, set everything back to cached */ 2186 if (!bad_alias) { 2187 #ifdef DEBUG 2188 if (rw_mappings > 0 2189 || (md->pvh_attrs & PMAP_KMPAGE)) { 2190 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2191 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2192 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2193 } 2194 #endif 2195 if (SLIST_EMPTY(&md->pvh_list)) 2196 PMAPCOUNT(vac_color_reuse); 2197 else 2198 PMAPCOUNT(vac_color_ok); 2199 2200 /* matching color, just return */ 2201 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2202 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2203 return; 2204 } 2205 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2206 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2207 2208 /* color conflict. evict from cache. */ 2209 2210 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2211 md->pvh_attrs &= ~PVF_COLORED; 2212 md->pvh_attrs |= PVF_NC; 2213 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2214 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2215 PMAPCOUNT(vac_color_erase); 2216 } else if (rw_mappings == 0 2217 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2218 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2219 2220 /* 2221 * If the page has dirty cache lines, clean it. 2222 */ 2223 if (md->pvh_attrs & PVF_DIRTY) 2224 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2225 2226 /* 2227 * If this is the first remapping (we know that there are no 2228 * writeable mappings), then this is a simple color change. 2229 * Otherwise this is a seconary r/o mapping, which means 2230 * we don't have to do anything. 2231 */ 2232 if (ro_mappings == 1) { 2233 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2234 md->pvh_attrs &= PAGE_SIZE - 1; 2235 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2236 PMAPCOUNT(vac_color_change); 2237 } else { 2238 PMAPCOUNT(vac_color_blind); 2239 } 2240 md->pvh_attrs |= PVF_MULTCLR; 2241 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2242 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2243 return; 2244 } else { 2245 if (rw_mappings > 0) 2246 md->pvh_attrs |= PVF_WRITE; 2247 2248 /* color conflict. evict from cache. */ 2249 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2250 2251 /* the list can't be empty because this was a enter/modify */ 2252 pv = SLIST_FIRST(&md->pvh_list); 2253 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2254 KASSERT(pv); 2255 /* 2256 * If there's only one mapped page, change color to the 2257 * page's new color and return. Restore the DIRTY bit 2258 * that was erased by pmap_flush_page. 2259 */ 2260 if (SLIST_NEXT(pv, pv_link) == NULL) { 2261 md->pvh_attrs &= PAGE_SIZE - 1; 2262 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2263 if (md->pvh_attrs & PVF_DMOD) 2264 md->pvh_attrs |= PVF_DIRTY; 2265 PMAPCOUNT(vac_color_change); 2266 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2267 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2268 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2269 return; 2270 } 2271 } 2272 bad_alias = true; 2273 md->pvh_attrs &= ~PVF_COLORED; 2274 md->pvh_attrs |= PVF_NC; 2275 PMAPCOUNT(vac_color_erase); 2276 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2277 } 2278 2279 fixup: 2280 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2281 2282 /* 2283 * Turn cacheing on/off for all pages. 2284 */ 2285 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2286 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2287 pv->pv_va); 2288 KASSERTMSG(l2b != NULL, "%#lx", va); 2289 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2290 const pt_entry_t opte = *ptep; 2291 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2292 if (bad_alias) { 2293 pv->pv_flags |= PVF_NC; 2294 } else { 2295 pv->pv_flags &= ~PVF_NC; 2296 npte |= pte_l2_s_cache_mode; 2297 } 2298 2299 if (opte == npte) /* only update is there's a change */ 2300 continue; 2301 2302 if (l2pte_valid_p(npte)) { 2303 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2304 } 2305 2306 l2pte_set(ptep, npte, opte); 2307 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2308 } 2309 #endif /* !ARM_MMU_EXTENDED */ 2310 } 2311 #endif /* PMAP_CACHE_VIPT */ 2312 2313 2314 /* 2315 * Modify pte bits for all ptes corresponding to the given physical address. 2316 * We use `maskbits' rather than `clearbits' because we're always passing 2317 * constants and the latter would require an extra inversion at run-time. 2318 */ 2319 static void 2320 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2321 { 2322 struct pv_entry *pv; 2323 #ifdef PMAP_CACHE_VIPT 2324 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2325 #ifdef ARM_MMU_EXTENDED 2326 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2327 #else 2328 const u_int execbits = 0; 2329 bool need_vac_me_harder = false; 2330 bool need_syncicache = false; 2331 #endif 2332 #else 2333 const u_int execbits = 0; 2334 #endif 2335 2336 NPDEBUG(PDB_BITS, 2337 printf("pmap_clearbit: md %p mask 0x%x\n", 2338 md, maskbits)); 2339 2340 #ifdef PMAP_CACHE_VIPT 2341 /* 2342 * If we might want to sync the I-cache and we've modified it, 2343 * then we know we definitely need to sync or discard it. 2344 */ 2345 if (want_syncicache) { 2346 #ifdef ARM_MMU_EXTENDED 2347 if (md->pvh_attrs & PVF_MOD) 2348 md->pvh_attrs &= ~PVF_EXEC; 2349 #else 2350 need_syncicache = md->pvh_attrs & PVF_MOD; 2351 #endif 2352 } 2353 #endif 2354 KASSERT(pmap_page_locked_p(md)); 2355 2356 /* 2357 * Clear saved attributes (modify, reference) 2358 */ 2359 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2360 2361 if (SLIST_EMPTY(&md->pvh_list)) { 2362 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2363 if (need_syncicache) { 2364 /* 2365 * No one has it mapped, so just discard it. The next 2366 * exec remapping will cause it to be synced. 2367 */ 2368 md->pvh_attrs &= ~PVF_EXEC; 2369 PMAPCOUNT(exec_discarded_clearbit); 2370 } 2371 #endif 2372 return; 2373 } 2374 2375 /* 2376 * Loop over all current mappings setting/clearing as appropos 2377 */ 2378 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2379 pmap_t pm = pv->pv_pmap; 2380 const vaddr_t va = pv->pv_va; 2381 const u_int oflags = pv->pv_flags; 2382 #ifndef ARM_MMU_EXTENDED 2383 /* 2384 * Kernel entries are unmanaged and as such not to be changed. 2385 */ 2386 if (PV_IS_KENTRY_P(oflags)) 2387 continue; 2388 #endif 2389 pv->pv_flags &= ~maskbits; 2390 2391 pmap_release_page_lock(md); 2392 pmap_acquire_pmap_lock(pm); 2393 2394 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2395 if (l2b == NULL) { 2396 pmap_release_pmap_lock(pm); 2397 pmap_acquire_page_lock(md); 2398 continue; 2399 } 2400 KASSERTMSG(l2b != NULL, "%#lx", va); 2401 2402 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2403 const pt_entry_t opte = *ptep; 2404 pt_entry_t npte = opte | execbits; 2405 2406 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2407 2408 NPDEBUG(PDB_BITS, 2409 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2410 __func__, pv, pm, va, oflags)); 2411 2412 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2413 #ifdef PMAP_CACHE_VIVT 2414 if ((oflags & PVF_NC)) { 2415 /* 2416 * Entry is not cacheable: 2417 * 2418 * Don't turn caching on again if this is a 2419 * modified emulation. This would be 2420 * inconsitent with the settings created by 2421 * pmap_vac_me_harder(). Otherwise, it's safe 2422 * to re-enable cacheing. 2423 * 2424 * There's no need to call pmap_vac_me_harder() 2425 * here: all pages are losing their write 2426 * permission. 2427 */ 2428 if (maskbits & PVF_WRITE) { 2429 npte |= pte_l2_s_cache_mode; 2430 pv->pv_flags &= ~PVF_NC; 2431 } 2432 } else 2433 if (l2pte_writable_p(opte)) { 2434 /* 2435 * Entry is writable/cacheable: check if pmap 2436 * is current if it is flush it, otherwise it 2437 * won't be in the cache 2438 */ 2439 pmap_cache_wbinv_page(pm, va, 2440 (maskbits & PVF_REF) != 0, 2441 oflags|PVF_WRITE); 2442 } 2443 #endif 2444 2445 /* make the pte read only */ 2446 npte = l2pte_set_readonly(npte); 2447 2448 pmap_acquire_page_lock(md); 2449 #ifdef MULTIPROCESSOR 2450 pv = pmap_find_pv(md, pm, va); 2451 #endif 2452 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2453 /* 2454 * Keep alias accounting up to date 2455 */ 2456 if (pm == pmap_kernel()) { 2457 md->krw_mappings--; 2458 md->kro_mappings++; 2459 } else { 2460 md->urw_mappings--; 2461 md->uro_mappings++; 2462 } 2463 #ifdef PMAP_CACHE_VIPT 2464 if (arm_cache_prefer_mask != 0) { 2465 if (md->urw_mappings + md->krw_mappings == 0) { 2466 md->pvh_attrs &= ~PVF_WRITE; 2467 } else { 2468 PMAP_VALIDATE_MD_PAGE(md); 2469 } 2470 } 2471 #ifndef ARM_MMU_EXTENDED 2472 if (want_syncicache) 2473 need_syncicache = true; 2474 need_vac_me_harder = true; 2475 #endif 2476 #endif /* PMAP_CACHE_VIPT */ 2477 } 2478 pmap_release_page_lock(md); 2479 } 2480 2481 if (maskbits & PVF_REF) { 2482 if (true 2483 #ifndef ARM_MMU_EXTENDED 2484 && (oflags & PVF_NC) == 0 2485 #endif 2486 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2487 && l2pte_valid_p(npte)) { 2488 #ifdef PMAP_CACHE_VIVT 2489 /* 2490 * Check npte here; we may have already 2491 * done the wbinv above, and the validity 2492 * of the PTE is the same for opte and 2493 * npte. 2494 */ 2495 pmap_cache_wbinv_page(pm, va, true, oflags); 2496 #endif 2497 } 2498 2499 /* 2500 * Make the PTE invalid so that we will take a 2501 * page fault the next time the mapping is 2502 * referenced. 2503 */ 2504 npte &= ~L2_TYPE_MASK; 2505 npte |= L2_TYPE_INV; 2506 } 2507 2508 if (npte != opte) { 2509 l2pte_set(ptep, npte, opte); 2510 PTE_SYNC(ptep); 2511 2512 /* Flush the TLB entry if a current pmap. */ 2513 pmap_tlb_flush_SE(pm, va, oflags); 2514 } 2515 2516 pmap_release_pmap_lock(pm); 2517 pmap_acquire_page_lock(md); 2518 2519 NPDEBUG(PDB_BITS, 2520 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2521 pm, va, opte, npte)); 2522 } 2523 2524 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2525 /* 2526 * If we need to sync the I-cache and we haven't done it yet, do it. 2527 */ 2528 if (need_syncicache) { 2529 pmap_release_page_lock(md); 2530 pmap_syncicache_page(md, pa); 2531 pmap_acquire_page_lock(md); 2532 PMAPCOUNT(exec_synced_clearbit); 2533 } 2534 2535 /* 2536 * If we are changing this to read-only, we need to call vac_me_harder 2537 * so we can change all the read-only pages to cacheable. We pretend 2538 * this as a page deletion. 2539 */ 2540 if (need_vac_me_harder) { 2541 if (md->pvh_attrs & PVF_NC) 2542 pmap_vac_me_harder(md, pa, NULL, 0); 2543 } 2544 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2545 } 2546 2547 /* 2548 * pmap_clean_page() 2549 * 2550 * This is a local function used to work out the best strategy to clean 2551 * a single page referenced by its entry in the PV table. It's used by 2552 * pmap_copy_page, pmap_zero page and maybe some others later on. 2553 * 2554 * Its policy is effectively: 2555 * o If there are no mappings, we don't bother doing anything with the cache. 2556 * o If there is one mapping, we clean just that page. 2557 * o If there are multiple mappings, we clean the entire cache. 2558 * 2559 * So that some functions can be further optimised, it returns 0 if it didn't 2560 * clean the entire cache, or 1 if it did. 2561 * 2562 * XXX One bug in this routine is that if the pv_entry has a single page 2563 * mapped at 0x00000000 a whole cache clean will be performed rather than 2564 * just the 1 page. Since this should not occur in everyday use and if it does 2565 * it will just result in not the most efficient clean for the page. 2566 */ 2567 #ifdef PMAP_CACHE_VIVT 2568 static bool 2569 pmap_clean_page(struct vm_page_md *md, bool is_src) 2570 { 2571 struct pv_entry *pv; 2572 pmap_t pm_to_clean = NULL; 2573 bool cache_needs_cleaning = false; 2574 vaddr_t page_to_clean = 0; 2575 u_int flags = 0; 2576 2577 /* 2578 * Since we flush the cache each time we change to a different 2579 * user vmspace, we only need to flush the page if it is in the 2580 * current pmap. 2581 */ 2582 KASSERT(pmap_page_locked_p(md)); 2583 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2584 if (pmap_is_current(pv->pv_pmap)) { 2585 flags |= pv->pv_flags; 2586 /* 2587 * The page is mapped non-cacheable in 2588 * this map. No need to flush the cache. 2589 */ 2590 if (pv->pv_flags & PVF_NC) { 2591 #ifdef DIAGNOSTIC 2592 KASSERT(!cache_needs_cleaning); 2593 #endif 2594 break; 2595 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2596 continue; 2597 if (cache_needs_cleaning) { 2598 page_to_clean = 0; 2599 break; 2600 } else { 2601 page_to_clean = pv->pv_va; 2602 pm_to_clean = pv->pv_pmap; 2603 } 2604 cache_needs_cleaning = true; 2605 } 2606 } 2607 2608 if (page_to_clean) { 2609 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2610 !is_src, flags | PVF_REF); 2611 } else if (cache_needs_cleaning) { 2612 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2613 2614 pmap_cache_wbinv_all(pm, flags); 2615 return true; 2616 } 2617 return false; 2618 } 2619 #endif 2620 2621 #ifdef PMAP_CACHE_VIPT 2622 /* 2623 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2624 * right cache alias to make sure we flush the right stuff. 2625 */ 2626 void 2627 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2628 { 2629 pmap_t kpm = pmap_kernel(); 2630 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2631 ? PAGE_SIZE 2632 : arm_pcache.icache_way_size; 2633 2634 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2635 md, md->pvh_attrs)); 2636 /* 2637 * No need to clean the page if it's non-cached. 2638 */ 2639 #ifndef ARM_MMU_EXTENDED 2640 if (md->pvh_attrs & PVF_NC) 2641 return; 2642 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2643 #endif 2644 2645 pt_entry_t * const ptep = cpu_cdst_pte(0); 2646 const vaddr_t dstp = cpu_cdstp(0); 2647 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2648 if (way_size <= PAGE_SIZE) { 2649 bool ok = false; 2650 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2651 if (ok) { 2652 cpu_icache_sync_range(vdstp, way_size); 2653 return; 2654 } 2655 } 2656 #endif 2657 2658 /* 2659 * We don't worry about the color of the exec page, we map the 2660 * same page to pages in the way and then do the icache_sync on 2661 * the entire way making sure we are cleaned. 2662 */ 2663 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2664 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2665 2666 for (size_t i = 0, j = 0; i < way_size; 2667 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2668 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2669 /* 2670 * Set up a PTE with to flush these cache lines. 2671 */ 2672 l2pte_set(ptep + j, npte, 0); 2673 } 2674 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2675 2676 /* 2677 * Flush it. 2678 */ 2679 cpu_icache_sync_range(dstp, way_size); 2680 2681 for (size_t i = 0, j = 0; i < way_size; 2682 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2683 /* 2684 * Unmap the page(s). 2685 */ 2686 l2pte_reset(ptep + j); 2687 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2688 } 2689 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2690 2691 md->pvh_attrs |= PVF_EXEC; 2692 PMAPCOUNT(exec_synced); 2693 } 2694 2695 #ifndef ARM_MMU_EXTENDED 2696 void 2697 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2698 { 2699 vsize_t va_offset, end_va; 2700 bool wbinv_p; 2701 2702 if (arm_cache_prefer_mask == 0) 2703 return; 2704 2705 switch (flush) { 2706 case PMAP_FLUSH_PRIMARY: 2707 if (md->pvh_attrs & PVF_MULTCLR) { 2708 va_offset = 0; 2709 end_va = arm_cache_prefer_mask; 2710 md->pvh_attrs &= ~PVF_MULTCLR; 2711 PMAPCOUNT(vac_flush_lots); 2712 } else { 2713 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2714 end_va = va_offset; 2715 PMAPCOUNT(vac_flush_one); 2716 } 2717 /* 2718 * Mark that the page is no longer dirty. 2719 */ 2720 md->pvh_attrs &= ~PVF_DIRTY; 2721 wbinv_p = true; 2722 break; 2723 case PMAP_FLUSH_SECONDARY: 2724 va_offset = 0; 2725 end_va = arm_cache_prefer_mask; 2726 wbinv_p = true; 2727 md->pvh_attrs &= ~PVF_MULTCLR; 2728 PMAPCOUNT(vac_flush_lots); 2729 break; 2730 case PMAP_CLEAN_PRIMARY: 2731 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2732 end_va = va_offset; 2733 wbinv_p = false; 2734 /* 2735 * Mark that the page is no longer dirty. 2736 */ 2737 if ((md->pvh_attrs & PVF_DMOD) == 0) 2738 md->pvh_attrs &= ~PVF_DIRTY; 2739 PMAPCOUNT(vac_clean_one); 2740 break; 2741 default: 2742 return; 2743 } 2744 2745 KASSERT(!(md->pvh_attrs & PVF_NC)); 2746 2747 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2748 md, md->pvh_attrs)); 2749 2750 const size_t scache_line_size = arm_scache.dcache_line_size; 2751 2752 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2753 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2754 const vaddr_t dstp = cpu_cdstp(va_offset); 2755 const pt_entry_t opte = *ptep; 2756 2757 if (flush == PMAP_FLUSH_SECONDARY 2758 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2759 continue; 2760 2761 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2762 /* 2763 * Set up a PTE with the right coloring to flush 2764 * existing cache entries. 2765 */ 2766 const pt_entry_t npte = L2_S_PROTO 2767 | pa 2768 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2769 | pte_l2_s_cache_mode; 2770 l2pte_set(ptep, npte, opte); 2771 PTE_SYNC(ptep); 2772 2773 /* 2774 * Flush it. Make sure to flush secondary cache too since 2775 * bus_dma will ignore uncached pages. 2776 */ 2777 if (scache_line_size != 0) { 2778 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2779 if (wbinv_p) { 2780 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2781 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2782 } else { 2783 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2784 } 2785 } else { 2786 if (wbinv_p) { 2787 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2788 } else { 2789 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2790 } 2791 } 2792 2793 /* 2794 * Restore the page table entry since we might have interrupted 2795 * pmap_zero_page or pmap_copy_page which was already using 2796 * this pte. 2797 */ 2798 if (opte) { 2799 l2pte_set(ptep, opte, npte); 2800 } else { 2801 l2pte_reset(ptep); 2802 } 2803 PTE_SYNC(ptep); 2804 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2805 } 2806 } 2807 #endif /* ARM_MMU_EXTENDED */ 2808 #endif /* PMAP_CACHE_VIPT */ 2809 2810 /* 2811 * Routine: pmap_page_remove 2812 * Function: 2813 * Removes this physical page from 2814 * all physical maps in which it resides. 2815 * Reflects back modify bits to the pager. 2816 */ 2817 static void 2818 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2819 { 2820 struct l2_bucket *l2b; 2821 struct pv_entry *pv; 2822 pt_entry_t *ptep; 2823 #ifndef ARM_MMU_EXTENDED 2824 bool flush = false; 2825 #endif 2826 u_int flags = 0; 2827 2828 NPDEBUG(PDB_FOLLOW, 2829 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2830 pa)); 2831 2832 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2833 pmap_acquire_page_lock(md); 2834 if (*pvp == NULL) { 2835 #ifdef PMAP_CACHE_VIPT 2836 /* 2837 * We *know* the page contents are about to be replaced. 2838 * Discard the exec contents 2839 */ 2840 if (PV_IS_EXEC_P(md->pvh_attrs)) 2841 PMAPCOUNT(exec_discarded_page_protect); 2842 md->pvh_attrs &= ~PVF_EXEC; 2843 PMAP_VALIDATE_MD_PAGE(md); 2844 #endif 2845 pmap_release_page_lock(md); 2846 return; 2847 } 2848 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2849 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2850 #endif 2851 2852 /* 2853 * Clear alias counts 2854 */ 2855 #ifdef PMAP_CACHE_VIVT 2856 md->k_mappings = 0; 2857 #endif 2858 md->urw_mappings = md->uro_mappings = 0; 2859 2860 #ifdef PMAP_CACHE_VIVT 2861 pmap_clean_page(md, false); 2862 #endif 2863 2864 while ((pv = *pvp) != NULL) { 2865 pmap_t pm = pv->pv_pmap; 2866 #ifndef ARM_MMU_EXTENDED 2867 if (flush == false && pmap_is_current(pm)) 2868 flush = true; 2869 #endif 2870 2871 if (pm == pmap_kernel()) { 2872 #ifdef PMAP_CACHE_VIPT 2873 /* 2874 * If this was unmanaged mapping, it must be preserved. 2875 * Move it back on the list and advance the end-of-list 2876 * pointer. 2877 */ 2878 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2879 *pvp = pv; 2880 pvp = &SLIST_NEXT(pv, pv_link); 2881 continue; 2882 } 2883 if (pv->pv_flags & PVF_WRITE) 2884 md->krw_mappings--; 2885 else 2886 md->kro_mappings--; 2887 #endif 2888 PMAPCOUNT(kernel_unmappings); 2889 } 2890 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2891 PMAPCOUNT(unmappings); 2892 2893 pmap_release_page_lock(md); 2894 pmap_acquire_pmap_lock(pm); 2895 2896 #ifdef ARM_MMU_EXTENDED 2897 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2898 #endif 2899 2900 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2901 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2902 2903 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2904 2905 /* 2906 * Update statistics 2907 */ 2908 --pm->pm_stats.resident_count; 2909 2910 /* Wired bit */ 2911 if (pv->pv_flags & PVF_WIRED) 2912 --pm->pm_stats.wired_count; 2913 2914 flags |= pv->pv_flags; 2915 2916 /* 2917 * Invalidate the PTEs. 2918 */ 2919 l2pte_reset(ptep); 2920 PTE_SYNC_CURRENT(pm, ptep); 2921 if (pm != pmap_kernel()) { 2922 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2923 } 2924 pmap_release_pmap_lock(pm); 2925 2926 pool_put(&pmap_pv_pool, pv); 2927 pmap_acquire_page_lock(md); 2928 #ifdef MULTIPROCESSOR 2929 /* 2930 * Restart of the beginning of the list. 2931 */ 2932 pvp = &SLIST_FIRST(&md->pvh_list); 2933 #endif 2934 } 2935 /* 2936 * if we reach the end of the list and there are still mappings, they 2937 * might be able to be cached now. And they must be kernel mappings. 2938 */ 2939 if (!SLIST_EMPTY(&md->pvh_list)) { 2940 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2941 } 2942 2943 #ifdef PMAP_CACHE_VIPT 2944 /* 2945 * Its EXEC cache is now gone. 2946 */ 2947 if (PV_IS_EXEC_P(md->pvh_attrs)) 2948 PMAPCOUNT(exec_discarded_page_protect); 2949 md->pvh_attrs &= ~PVF_EXEC; 2950 KASSERT(md->urw_mappings == 0); 2951 KASSERT(md->uro_mappings == 0); 2952 #ifndef ARM_MMU_EXTENDED 2953 if (arm_cache_prefer_mask != 0) { 2954 if (md->krw_mappings == 0) 2955 md->pvh_attrs &= ~PVF_WRITE; 2956 PMAP_VALIDATE_MD_PAGE(md); 2957 } 2958 #endif /* ARM_MMU_EXTENDED */ 2959 #endif /* PMAP_CACHE_VIPT */ 2960 pmap_release_page_lock(md); 2961 2962 #ifndef ARM_MMU_EXTENDED 2963 if (flush) { 2964 /* 2965 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2966 * would need a subsequent call to pmap_update() to ensure 2967 * curpm->pm_cstate.cs_all is reset. Our callers are not 2968 * required to do that (see pmap(9)), so we can't modify 2969 * the current pmap's state. 2970 */ 2971 if (PV_BEEN_EXECD(flags)) 2972 cpu_tlb_flushID(); 2973 else 2974 cpu_tlb_flushD(); 2975 } 2976 cpu_cpwait(); 2977 #endif /* ARM_MMU_EXTENDED */ 2978 } 2979 2980 /* 2981 * pmap_t pmap_create(void) 2982 * 2983 * Create a new pmap structure from scratch. 2984 */ 2985 pmap_t 2986 pmap_create(void) 2987 { 2988 pmap_t pm; 2989 2990 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2991 2992 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2993 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2994 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2995 2996 pm->pm_stats.wired_count = 0; 2997 pm->pm_stats.resident_count = 1; 2998 #ifdef ARM_MMU_EXTENDED 2999 #ifdef MULTIPROCESSOR 3000 kcpuset_create(&pm->pm_active, true); 3001 kcpuset_create(&pm->pm_onproc, true); 3002 #endif 3003 #else 3004 pm->pm_cstate.cs_all = 0; 3005 #endif 3006 pmap_alloc_l1(pm); 3007 3008 /* 3009 * Note: The pool cache ensures that the pm_l2[] array is already 3010 * initialised to zero. 3011 */ 3012 3013 pmap_pinit(pm); 3014 3015 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3016 3017 return (pm); 3018 } 3019 3020 u_int 3021 arm32_mmap_flags(paddr_t pa) 3022 { 3023 /* 3024 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3025 * and we're using the upper bits in page numbers to pass flags around 3026 * so we might as well use the same bits 3027 */ 3028 return (u_int)pa & PMAP_MD_MASK; 3029 } 3030 /* 3031 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3032 * u_int flags) 3033 * 3034 * Insert the given physical page (p) at 3035 * the specified virtual address (v) in the 3036 * target physical map with the protection requested. 3037 * 3038 * NB: This is the only routine which MAY NOT lazy-evaluate 3039 * or lose information. That is, this routine must actually 3040 * insert this page into the given map NOW. 3041 */ 3042 int 3043 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3044 { 3045 struct l2_bucket *l2b; 3046 struct vm_page *pg, *opg; 3047 u_int nflags; 3048 u_int oflags; 3049 const bool kpm_p = (pm == pmap_kernel()); 3050 #ifdef ARM_HAS_VBAR 3051 const bool vector_page_p = false; 3052 #else 3053 const bool vector_page_p = (va == vector_page); 3054 #endif 3055 3056 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3057 3058 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot #x", 3059 pm, va, pa, prot); 3060 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3061 3062 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3063 KDASSERT(((va | pa) & PGOFSET) == 0); 3064 3065 /* 3066 * Get a pointer to the page. Later on in this function, we 3067 * test for a managed page by checking pg != NULL. 3068 */ 3069 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3070 3071 nflags = 0; 3072 if (prot & VM_PROT_WRITE) 3073 nflags |= PVF_WRITE; 3074 if (prot & VM_PROT_EXECUTE) 3075 nflags |= PVF_EXEC; 3076 if (flags & PMAP_WIRED) 3077 nflags |= PVF_WIRED; 3078 3079 pmap_acquire_pmap_lock(pm); 3080 3081 /* 3082 * Fetch the L2 bucket which maps this page, allocating one if 3083 * necessary for user pmaps. 3084 */ 3085 if (kpm_p) { 3086 l2b = pmap_get_l2_bucket(pm, va); 3087 } else { 3088 l2b = pmap_alloc_l2_bucket(pm, va); 3089 } 3090 if (l2b == NULL) { 3091 if (flags & PMAP_CANFAIL) { 3092 pmap_release_pmap_lock(pm); 3093 return (ENOMEM); 3094 } 3095 panic("pmap_enter: failed to allocate L2 bucket"); 3096 } 3097 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3098 const pt_entry_t opte = *ptep; 3099 pt_entry_t npte = pa; 3100 oflags = 0; 3101 3102 if (opte) { 3103 /* 3104 * There is already a mapping at this address. 3105 * If the physical address is different, lookup the 3106 * vm_page. 3107 */ 3108 if (l2pte_pa(opte) != pa) 3109 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3110 else 3111 opg = pg; 3112 } else 3113 opg = NULL; 3114 3115 if (pg) { 3116 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3117 3118 /* 3119 * This is to be a managed mapping. 3120 */ 3121 pmap_acquire_page_lock(md); 3122 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3123 /* 3124 * - The access type indicates that we don't need 3125 * to do referenced emulation. 3126 * OR 3127 * - The physical page has already been referenced 3128 * so no need to re-do referenced emulation here. 3129 */ 3130 npte |= l2pte_set_readonly(L2_S_PROTO); 3131 3132 nflags |= PVF_REF; 3133 3134 if ((prot & VM_PROT_WRITE) != 0 && 3135 ((flags & VM_PROT_WRITE) != 0 || 3136 (md->pvh_attrs & PVF_MOD) != 0)) { 3137 /* 3138 * This is a writable mapping, and the 3139 * page's mod state indicates it has 3140 * already been modified. Make it 3141 * writable from the outset. 3142 */ 3143 npte = l2pte_set_writable(npte); 3144 nflags |= PVF_MOD; 3145 } 3146 3147 #ifdef ARM_MMU_EXTENDED 3148 /* 3149 * If the page has been cleaned, then the pvh_attrs 3150 * will have PVF_EXEC set, so mark it execute so we 3151 * don't get an access fault when trying to execute 3152 * from it. 3153 */ 3154 if (md->pvh_attrs & nflags & PVF_EXEC) { 3155 npte &= ~L2_XS_XN; 3156 } 3157 #endif 3158 } else { 3159 /* 3160 * Need to do page referenced emulation. 3161 */ 3162 npte |= L2_TYPE_INV; 3163 } 3164 3165 if (flags & ARM32_MMAP_WRITECOMBINE) { 3166 npte |= pte_l2_s_wc_mode; 3167 } else 3168 npte |= pte_l2_s_cache_mode; 3169 3170 if (pg == opg) { 3171 /* 3172 * We're changing the attrs of an existing mapping. 3173 */ 3174 oflags = pmap_modify_pv(md, pa, pm, va, 3175 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3176 PVF_MOD | PVF_REF, nflags); 3177 3178 #ifdef PMAP_CACHE_VIVT 3179 /* 3180 * We may need to flush the cache if we're 3181 * doing rw-ro... 3182 */ 3183 if (pm->pm_cstate.cs_cache_d && 3184 (oflags & PVF_NC) == 0 && 3185 l2pte_writable_p(opte) && 3186 (prot & VM_PROT_WRITE) == 0) 3187 cpu_dcache_wb_range(va, PAGE_SIZE); 3188 #endif 3189 } else { 3190 struct pv_entry *pv; 3191 /* 3192 * New mapping, or changing the backing page 3193 * of an existing mapping. 3194 */ 3195 if (opg) { 3196 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3197 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3198 3199 /* 3200 * Replacing an existing mapping with a new one. 3201 * It is part of our managed memory so we 3202 * must remove it from the PV list 3203 */ 3204 pv = pmap_remove_pv(omd, opa, pm, va); 3205 pmap_vac_me_harder(omd, opa, pm, 0); 3206 oflags = pv->pv_flags; 3207 3208 #ifdef PMAP_CACHE_VIVT 3209 /* 3210 * If the old mapping was valid (ref/mod 3211 * emulation creates 'invalid' mappings 3212 * initially) then make sure to frob 3213 * the cache. 3214 */ 3215 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3216 pmap_cache_wbinv_page(pm, va, true, 3217 oflags); 3218 } 3219 #endif 3220 } else { 3221 pmap_release_page_lock(md); 3222 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3223 if (pv == NULL) { 3224 pmap_release_pmap_lock(pm); 3225 if ((flags & PMAP_CANFAIL) == 0) 3226 panic("pmap_enter: " 3227 "no pv entries"); 3228 3229 if (pm != pmap_kernel()) 3230 pmap_free_l2_bucket(pm, l2b, 0); 3231 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3232 0, 0, 0, 0); 3233 return (ENOMEM); 3234 } 3235 pmap_acquire_page_lock(md); 3236 } 3237 3238 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3239 } 3240 pmap_release_page_lock(md); 3241 } else { 3242 /* 3243 * We're mapping an unmanaged page. 3244 * These are always readable, and possibly writable, from 3245 * the get go as we don't need to track ref/mod status. 3246 */ 3247 npte |= l2pte_set_readonly(L2_S_PROTO); 3248 if (prot & VM_PROT_WRITE) 3249 npte = l2pte_set_writable(npte); 3250 3251 /* 3252 * Make sure the vector table is mapped cacheable 3253 */ 3254 if ((vector_page_p && !kpm_p) 3255 || (flags & ARM32_MMAP_CACHEABLE)) { 3256 npte |= pte_l2_s_cache_mode; 3257 #ifdef ARM_MMU_EXTENDED 3258 npte &= ~L2_XS_XN; /* and executable */ 3259 #endif 3260 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3261 npte |= pte_l2_s_wc_mode; 3262 } 3263 if (opg) { 3264 /* 3265 * Looks like there's an existing 'managed' mapping 3266 * at this address. 3267 */ 3268 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3269 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3270 3271 pmap_acquire_page_lock(omd); 3272 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3273 pmap_vac_me_harder(omd, opa, pm, 0); 3274 oflags = pv->pv_flags; 3275 pmap_release_page_lock(omd); 3276 3277 #ifdef PMAP_CACHE_VIVT 3278 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3279 pmap_cache_wbinv_page(pm, va, true, oflags); 3280 } 3281 #endif 3282 pool_put(&pmap_pv_pool, pv); 3283 } 3284 } 3285 3286 /* 3287 * Make sure userland mappings get the right permissions 3288 */ 3289 if (!vector_page_p && !kpm_p) { 3290 npte |= L2_S_PROT_U; 3291 #ifdef ARM_MMU_EXTENDED 3292 npte |= L2_XS_nG; /* user pages are not global */ 3293 #endif 3294 } 3295 3296 /* 3297 * Keep the stats up to date 3298 */ 3299 if (opte == 0) { 3300 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3301 pm->pm_stats.resident_count++; 3302 } 3303 3304 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3305 3306 #if defined(ARM_MMU_EXTENDED) 3307 /* 3308 * If exec protection was requested but the page hasn't been synced, 3309 * sync it now and allow execution from it. 3310 */ 3311 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3312 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3313 npte &= ~L2_XS_XN; 3314 pmap_syncicache_page(md, pa); 3315 PMAPCOUNT(exec_synced_map); 3316 } 3317 #endif 3318 /* 3319 * If this is just a wiring change, the two PTEs will be 3320 * identical, so there's no need to update the page table. 3321 */ 3322 if (npte != opte) { 3323 3324 l2pte_set(ptep, npte, opte); 3325 PTE_SYNC(ptep); 3326 #ifndef ARM_MMU_EXTENDED 3327 bool is_cached = pmap_is_cached(pm); 3328 if (is_cached) { 3329 /* 3330 * We only need to frob the cache/tlb if this pmap 3331 * is current 3332 */ 3333 if (!vector_page_p && l2pte_valid_p(npte)) { 3334 /* 3335 * This mapping is likely to be accessed as 3336 * soon as we return to userland. Fix up the 3337 * L1 entry to avoid taking another 3338 * page/domain fault. 3339 */ 3340 pd_entry_t *pdep = pmap_l1_kva(pm) 3341 + l1pte_index(va); 3342 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3343 | L1_C_DOM(pmap_domain(pm)); 3344 if (*pdep != pde) { 3345 l1pte_setone(pdep, pde); 3346 PTE_SYNC(pdep); 3347 } 3348 } 3349 } 3350 #endif /* !ARMM_MMU_EXTENDED */ 3351 3352 pmap_tlb_flush_SE(pm, va, oflags); 3353 3354 #ifndef ARM_MMU_EXTENDED 3355 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3356 is_cached, pm->pm_cstate.cs_all, 0, 0); 3357 3358 if (pg != NULL) { 3359 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3360 3361 pmap_acquire_page_lock(md); 3362 pmap_vac_me_harder(md, pa, pm, va); 3363 pmap_release_page_lock(md); 3364 } 3365 #endif 3366 } 3367 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3368 if (pg) { 3369 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3370 3371 pmap_acquire_page_lock(md); 3372 #ifndef ARM_MMU_EXTENDED 3373 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3374 #endif 3375 PMAP_VALIDATE_MD_PAGE(md); 3376 pmap_release_page_lock(md); 3377 } 3378 #endif 3379 3380 pmap_release_pmap_lock(pm); 3381 3382 return (0); 3383 } 3384 3385 /* 3386 * pmap_remove() 3387 * 3388 * pmap_remove is responsible for nuking a number of mappings for a range 3389 * of virtual address space in the current pmap. To do this efficiently 3390 * is interesting, because in a number of cases a wide virtual address 3391 * range may be supplied that contains few actual mappings. So, the 3392 * optimisations are: 3393 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3394 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3395 * maybe do just a partial cache clean. This path of execution is 3396 * complicated by the fact that the cache must be flushed _before_ 3397 * the PTE is nuked, being a VAC :-) 3398 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3399 * all invalidations until pmap_update(), since pmap_remove_all() has 3400 * already flushed the cache. 3401 * 4. Maybe later fast-case a single page, but I don't think this is 3402 * going to make _that_ much difference overall. 3403 */ 3404 3405 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3406 3407 void 3408 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3409 { 3410 vaddr_t next_bucket; 3411 u_int cleanlist_idx, total, cnt; 3412 struct { 3413 vaddr_t va; 3414 pt_entry_t *ptep; 3415 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3416 u_int mappings; 3417 3418 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3419 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3420 3421 /* 3422 * we lock in the pmap => pv_head direction 3423 */ 3424 pmap_acquire_pmap_lock(pm); 3425 3426 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3427 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3428 #ifndef ARM_MMU_EXTENDED 3429 if (pm->pm_cstate.cs_tlb == 0) 3430 pm->pm_remove_all = true; 3431 #endif 3432 } else 3433 cleanlist_idx = 0; 3434 3435 total = 0; 3436 3437 while (sva < eva) { 3438 /* 3439 * Do one L2 bucket's worth at a time. 3440 */ 3441 next_bucket = L2_NEXT_BUCKET_VA(sva); 3442 if (next_bucket > eva) 3443 next_bucket = eva; 3444 3445 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3446 if (l2b == NULL) { 3447 sva = next_bucket; 3448 continue; 3449 } 3450 3451 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3452 3453 for (mappings = 0; 3454 sva < next_bucket; 3455 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3456 pt_entry_t opte = *ptep; 3457 3458 if (opte == 0) { 3459 /* Nothing here, move along */ 3460 continue; 3461 } 3462 3463 u_int flags = PVF_REF; 3464 paddr_t pa = l2pte_pa(opte); 3465 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3466 3467 /* 3468 * Update flags. In a number of circumstances, 3469 * we could cluster a lot of these and do a 3470 * number of sequential pages in one go. 3471 */ 3472 if (pg != NULL) { 3473 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3474 struct pv_entry *pv; 3475 3476 pmap_acquire_page_lock(md); 3477 pv = pmap_remove_pv(md, pa, pm, sva); 3478 pmap_vac_me_harder(md, pa, pm, 0); 3479 pmap_release_page_lock(md); 3480 if (pv != NULL) { 3481 if (pm->pm_remove_all == false) { 3482 flags = pv->pv_flags; 3483 } 3484 pool_put(&pmap_pv_pool, pv); 3485 } 3486 } 3487 mappings += PAGE_SIZE / L2_S_SIZE; 3488 3489 if (!l2pte_valid_p(opte)) { 3490 /* 3491 * Ref/Mod emulation is still active for this 3492 * mapping, therefore it is has not yet been 3493 * accessed. No need to frob the cache/tlb. 3494 */ 3495 l2pte_reset(ptep); 3496 PTE_SYNC_CURRENT(pm, ptep); 3497 continue; 3498 } 3499 3500 #ifdef ARM_MMU_EXTENDED 3501 if (pm == pmap_kernel()) { 3502 l2pte_reset(ptep); 3503 PTE_SYNC(ptep); 3504 pmap_tlb_flush_SE(pm, sva, flags); 3505 continue; 3506 } 3507 #endif 3508 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3509 /* Add to the clean list. */ 3510 cleanlist[cleanlist_idx].ptep = ptep; 3511 cleanlist[cleanlist_idx].va = 3512 sva | (flags & PVF_EXEC); 3513 cleanlist_idx++; 3514 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3515 /* Nuke everything if needed. */ 3516 #ifdef PMAP_CACHE_VIVT 3517 pmap_cache_wbinv_all(pm, PVF_EXEC); 3518 #endif 3519 /* 3520 * Roll back the previous PTE list, 3521 * and zero out the current PTE. 3522 */ 3523 for (cnt = 0; 3524 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3525 l2pte_reset(cleanlist[cnt].ptep); 3526 PTE_SYNC(cleanlist[cnt].ptep); 3527 } 3528 l2pte_reset(ptep); 3529 PTE_SYNC(ptep); 3530 cleanlist_idx++; 3531 pm->pm_remove_all = true; 3532 } else { 3533 l2pte_reset(ptep); 3534 PTE_SYNC(ptep); 3535 if (pm->pm_remove_all == false) { 3536 pmap_tlb_flush_SE(pm, sva, flags); 3537 } 3538 } 3539 } 3540 3541 /* 3542 * Deal with any left overs 3543 */ 3544 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3545 total += cleanlist_idx; 3546 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3547 #ifdef ARM_MMU_EXTENDED 3548 vaddr_t clva = cleanlist[cnt].va; 3549 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3550 #else 3551 vaddr_t va = cleanlist[cnt].va; 3552 if (pm->pm_cstate.cs_all != 0) { 3553 vaddr_t clva = va & ~PAGE_MASK; 3554 u_int flags = va & PVF_EXEC; 3555 #ifdef PMAP_CACHE_VIVT 3556 pmap_cache_wbinv_page(pm, clva, true, 3557 PVF_REF | PVF_WRITE | flags); 3558 #endif 3559 pmap_tlb_flush_SE(pm, clva, 3560 PVF_REF | flags); 3561 } 3562 #endif /* ARM_MMU_EXTENDED */ 3563 l2pte_reset(cleanlist[cnt].ptep); 3564 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3565 } 3566 3567 /* 3568 * If it looks like we're removing a whole bunch 3569 * of mappings, it's faster to just write-back 3570 * the whole cache now and defer TLB flushes until 3571 * pmap_update() is called. 3572 */ 3573 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3574 cleanlist_idx = 0; 3575 else { 3576 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3577 #ifdef PMAP_CACHE_VIVT 3578 pmap_cache_wbinv_all(pm, PVF_EXEC); 3579 #endif 3580 pm->pm_remove_all = true; 3581 } 3582 } 3583 3584 if (pm != pmap_kernel()) 3585 pmap_free_l2_bucket(pm, l2b, mappings); 3586 pm->pm_stats.resident_count -= mappings; 3587 } 3588 3589 pmap_release_pmap_lock(pm); 3590 } 3591 3592 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3593 static struct pv_entry * 3594 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3595 { 3596 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3597 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3598 struct pv_entry *pv; 3599 3600 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3601 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3602 KASSERT(pmap_page_locked_p(md)); 3603 3604 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3605 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3606 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3607 3608 /* 3609 * If we are removing a writeable mapping to a cached exec page, 3610 * if it's the last mapping then clear it execness other sync 3611 * the page to the icache. 3612 */ 3613 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3614 && (pv->pv_flags & PVF_WRITE) != 0) { 3615 if (SLIST_EMPTY(&md->pvh_list)) { 3616 md->pvh_attrs &= ~PVF_EXEC; 3617 PMAPCOUNT(exec_discarded_kremove); 3618 } else { 3619 pmap_syncicache_page(md, pa); 3620 PMAPCOUNT(exec_synced_kremove); 3621 } 3622 } 3623 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3624 3625 return pv; 3626 } 3627 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3628 3629 /* 3630 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3631 * 3632 * We assume there is already sufficient KVM space available 3633 * to do this, as we can't allocate L2 descriptor tables/metadata 3634 * from here. 3635 */ 3636 void 3637 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3638 { 3639 #ifdef PMAP_CACHE_VIVT 3640 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3641 #endif 3642 #ifdef PMAP_CACHE_VIPT 3643 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3644 struct vm_page *opg; 3645 #ifndef ARM_MMU_EXTENDED 3646 struct pv_entry *pv = NULL; 3647 #endif 3648 #endif 3649 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3650 3651 UVMHIST_FUNC(__func__); 3652 3653 if (pmap_initialized) { 3654 UVMHIST_CALLED(maphist); 3655 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3656 va, pa, prot, flags); 3657 } 3658 3659 pmap_t kpm = pmap_kernel(); 3660 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3661 const size_t l1slot __diagused = l1pte_index(va); 3662 KASSERTMSG(l2b != NULL, 3663 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3664 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3665 kpm->pm_l2[L2_IDX(l1slot)] 3666 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3667 : NULL, 3668 kpm->pm_l2[L2_IDX(l1slot)] 3669 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3670 : NULL); 3671 KASSERT(l2b->l2b_kva != NULL); 3672 3673 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3674 const pt_entry_t opte = *ptep; 3675 3676 if (opte == 0) { 3677 PMAPCOUNT(kenter_mappings); 3678 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3679 } else { 3680 PMAPCOUNT(kenter_remappings); 3681 #ifdef PMAP_CACHE_VIPT 3682 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3683 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3684 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3685 #endif 3686 if (opg && arm_cache_prefer_mask != 0) { 3687 KASSERT(opg != pg); 3688 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3689 KASSERT((flags & PMAP_KMPAGE) == 0); 3690 #ifndef ARM_MMU_EXTENDED 3691 pmap_acquire_page_lock(omd); 3692 pv = pmap_kremove_pg(opg, va); 3693 pmap_release_page_lock(omd); 3694 #endif 3695 } 3696 #endif 3697 if (l2pte_valid_p(opte)) { 3698 #ifdef PMAP_CACHE_VIVT 3699 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3700 #endif 3701 cpu_tlb_flushD_SE(va); 3702 cpu_cpwait(); 3703 } 3704 } 3705 3706 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3707 | ((flags & PMAP_NOCACHE) 3708 ? 0 3709 : ((flags & PMAP_PTE) 3710 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3711 #ifdef ARM_MMU_EXTENDED 3712 if (prot & VM_PROT_EXECUTE) 3713 npte &= ~L2_XS_XN; 3714 #endif 3715 l2pte_set(ptep, npte, opte); 3716 PTE_SYNC(ptep); 3717 3718 if (pg) { 3719 if (flags & PMAP_KMPAGE) { 3720 KASSERT(md->urw_mappings == 0); 3721 KASSERT(md->uro_mappings == 0); 3722 KASSERT(md->krw_mappings == 0); 3723 KASSERT(md->kro_mappings == 0); 3724 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3725 KASSERT(pv == NULL); 3726 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3727 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3728 /* if there is a color conflict, evict from cache. */ 3729 if (pmap_is_page_colored_p(md) 3730 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3731 PMAPCOUNT(vac_color_change); 3732 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3733 } else if (md->pvh_attrs & PVF_MULTCLR) { 3734 /* 3735 * If this page has multiple colors, expunge 3736 * them. 3737 */ 3738 PMAPCOUNT(vac_flush_lots2); 3739 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3740 } 3741 /* 3742 * Since this is a KMPAGE, there can be no contention 3743 * for this page so don't lock it. 3744 */ 3745 md->pvh_attrs &= PAGE_SIZE - 1; 3746 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3747 | (va & arm_cache_prefer_mask); 3748 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3749 md->pvh_attrs |= PVF_KMPAGE; 3750 #endif 3751 atomic_inc_32(&pmap_kmpages); 3752 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3753 } else if (arm_cache_prefer_mask != 0) { 3754 if (pv == NULL) { 3755 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3756 KASSERT(pv != NULL); 3757 } 3758 pmap_acquire_page_lock(md); 3759 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3760 PVF_WIRED | PVF_KENTRY 3761 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3762 if ((prot & VM_PROT_WRITE) 3763 && !(md->pvh_attrs & PVF_NC)) 3764 md->pvh_attrs |= PVF_DIRTY; 3765 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3766 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3767 pmap_release_page_lock(md); 3768 #endif 3769 } 3770 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3771 } else { 3772 if (pv != NULL) 3773 pool_put(&pmap_pv_pool, pv); 3774 #endif 3775 } 3776 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3777 if (pmap_initialized) { 3778 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3779 ptep, opte, npte, 0); 3780 } 3781 3782 } 3783 3784 void 3785 pmap_kremove(vaddr_t va, vsize_t len) 3786 { 3787 #ifdef UVMHIST 3788 u_int total_mappings = 0; 3789 #endif 3790 3791 PMAPCOUNT(kenter_unmappings); 3792 3793 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3794 3795 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3796 3797 const vaddr_t eva = va + len; 3798 3799 while (va < eva) { 3800 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3801 if (next_bucket > eva) 3802 next_bucket = eva; 3803 3804 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3805 KDASSERT(l2b != NULL); 3806 3807 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3808 pt_entry_t *ptep = sptep; 3809 u_int mappings = 0; 3810 3811 while (va < next_bucket) { 3812 const pt_entry_t opte = *ptep; 3813 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3814 if (opg != NULL) { 3815 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3816 3817 if (omd->pvh_attrs & PVF_KMPAGE) { 3818 KASSERT(omd->urw_mappings == 0); 3819 KASSERT(omd->uro_mappings == 0); 3820 KASSERT(omd->krw_mappings == 0); 3821 KASSERT(omd->kro_mappings == 0); 3822 omd->pvh_attrs &= ~PVF_KMPAGE; 3823 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3824 if (arm_cache_prefer_mask != 0) { 3825 omd->pvh_attrs &= ~PVF_WRITE; 3826 } 3827 #endif 3828 atomic_dec_32(&pmap_kmpages); 3829 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3830 } else if (arm_cache_prefer_mask != 0) { 3831 pmap_acquire_page_lock(omd); 3832 pool_put(&pmap_pv_pool, 3833 pmap_kremove_pg(opg, va)); 3834 pmap_release_page_lock(omd); 3835 #endif 3836 } 3837 } 3838 if (l2pte_valid_p(opte)) { 3839 #ifdef PMAP_CACHE_VIVT 3840 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3841 #endif 3842 cpu_tlb_flushD_SE(va); 3843 } 3844 if (opte) { 3845 l2pte_reset(ptep); 3846 mappings += PAGE_SIZE / L2_S_SIZE; 3847 } 3848 va += PAGE_SIZE; 3849 ptep += PAGE_SIZE / L2_S_SIZE; 3850 } 3851 KDASSERT(mappings <= l2b->l2b_occupancy); 3852 l2b->l2b_occupancy -= mappings; 3853 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3854 #ifdef UVMHIST 3855 total_mappings += mappings; 3856 #endif 3857 } 3858 cpu_cpwait(); 3859 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3860 total_mappings, 0, 0, 0); 3861 } 3862 3863 bool 3864 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3865 { 3866 struct l2_dtable *l2; 3867 pd_entry_t *pdep, pde; 3868 pt_entry_t *ptep, pte; 3869 paddr_t pa; 3870 u_int l1slot; 3871 3872 pmap_acquire_pmap_lock(pm); 3873 3874 l1slot = l1pte_index(va); 3875 pdep = pmap_l1_kva(pm) + l1slot; 3876 pde = *pdep; 3877 3878 if (l1pte_section_p(pde)) { 3879 /* 3880 * These should only happen for pmap_kernel() 3881 */ 3882 KDASSERT(pm == pmap_kernel()); 3883 pmap_release_pmap_lock(pm); 3884 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3885 if (l1pte_supersection_p(pde)) { 3886 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3887 } else 3888 #endif 3889 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3890 } else { 3891 /* 3892 * Note that we can't rely on the validity of the L1 3893 * descriptor as an indication that a mapping exists. 3894 * We have to look it up in the L2 dtable. 3895 */ 3896 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3897 3898 if (l2 == NULL || 3899 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3900 pmap_release_pmap_lock(pm); 3901 return false; 3902 } 3903 3904 pte = ptep[l2pte_index(va)]; 3905 pmap_release_pmap_lock(pm); 3906 3907 if (pte == 0) 3908 return false; 3909 3910 switch (pte & L2_TYPE_MASK) { 3911 case L2_TYPE_L: 3912 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3913 break; 3914 3915 default: 3916 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3917 break; 3918 } 3919 } 3920 3921 if (pap != NULL) 3922 *pap = pa; 3923 3924 return true; 3925 } 3926 3927 void 3928 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3929 { 3930 struct l2_bucket *l2b; 3931 vaddr_t next_bucket; 3932 3933 NPDEBUG(PDB_PROTECT, 3934 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3935 pm, sva, eva, prot)); 3936 3937 if ((prot & VM_PROT_READ) == 0) { 3938 pmap_remove(pm, sva, eva); 3939 return; 3940 } 3941 3942 if (prot & VM_PROT_WRITE) { 3943 /* 3944 * If this is a read->write transition, just ignore it and let 3945 * uvm_fault() take care of it later. 3946 */ 3947 return; 3948 } 3949 3950 pmap_acquire_pmap_lock(pm); 3951 3952 const bool flush = eva - sva >= PAGE_SIZE * 4; 3953 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3954 u_int flags = 0; 3955 3956 while (sva < eva) { 3957 next_bucket = L2_NEXT_BUCKET_VA(sva); 3958 if (next_bucket > eva) 3959 next_bucket = eva; 3960 3961 l2b = pmap_get_l2_bucket(pm, sva); 3962 if (l2b == NULL) { 3963 sva = next_bucket; 3964 continue; 3965 } 3966 3967 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3968 3969 while (sva < next_bucket) { 3970 const pt_entry_t opte = *ptep; 3971 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3972 struct vm_page *pg; 3973 u_int f; 3974 3975 #ifdef PMAP_CACHE_VIVT 3976 /* 3977 * OK, at this point, we know we're doing 3978 * write-protect operation. If the pmap is 3979 * active, write-back the page. 3980 */ 3981 pmap_cache_wbinv_page(pm, sva, false, 3982 PVF_REF | PVF_WRITE); 3983 #endif 3984 3985 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3986 pt_entry_t npte = l2pte_set_readonly(opte); 3987 l2pte_set(ptep, npte, opte); 3988 PTE_SYNC(ptep); 3989 3990 if (pg != NULL) { 3991 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3992 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3993 3994 pmap_acquire_page_lock(md); 3995 f = pmap_modify_pv(md, pa, pm, sva, 3996 clr_mask, 0); 3997 pmap_vac_me_harder(md, pa, pm, sva); 3998 pmap_release_page_lock(md); 3999 } else { 4000 f = PVF_REF | PVF_EXEC; 4001 } 4002 4003 if (flush) { 4004 flags |= f; 4005 } else { 4006 pmap_tlb_flush_SE(pm, sva, f); 4007 } 4008 } 4009 4010 sva += PAGE_SIZE; 4011 ptep += PAGE_SIZE / L2_S_SIZE; 4012 } 4013 } 4014 4015 if (flush) { 4016 if (PV_BEEN_EXECD(flags)) { 4017 pmap_tlb_flushID(pm); 4018 } else if (PV_BEEN_REFD(flags)) { 4019 pmap_tlb_flushD(pm); 4020 } 4021 } 4022 4023 pmap_release_pmap_lock(pm); 4024 } 4025 4026 void 4027 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4028 { 4029 struct l2_bucket *l2b; 4030 pt_entry_t *ptep; 4031 vaddr_t next_bucket; 4032 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4033 4034 NPDEBUG(PDB_EXEC, 4035 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4036 pm, sva, eva)); 4037 4038 pmap_acquire_pmap_lock(pm); 4039 4040 while (sva < eva) { 4041 next_bucket = L2_NEXT_BUCKET_VA(sva); 4042 if (next_bucket > eva) 4043 next_bucket = eva; 4044 4045 l2b = pmap_get_l2_bucket(pm, sva); 4046 if (l2b == NULL) { 4047 sva = next_bucket; 4048 continue; 4049 } 4050 4051 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4052 sva < next_bucket; 4053 sva += page_size, 4054 ptep += PAGE_SIZE / L2_S_SIZE, 4055 page_size = PAGE_SIZE) { 4056 if (l2pte_valid_p(*ptep)) { 4057 cpu_icache_sync_range(sva, 4058 min(page_size, eva - sva)); 4059 } 4060 } 4061 } 4062 4063 pmap_release_pmap_lock(pm); 4064 } 4065 4066 void 4067 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4068 { 4069 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4070 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4071 4072 NPDEBUG(PDB_PROTECT, 4073 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4074 md, pa, prot)); 4075 4076 switch(prot) { 4077 case VM_PROT_READ|VM_PROT_WRITE: 4078 #if defined(ARM_MMU_EXTENDED) 4079 pmap_acquire_page_lock(md); 4080 pmap_clearbit(md, pa, PVF_EXEC); 4081 pmap_release_page_lock(md); 4082 break; 4083 #endif 4084 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4085 break; 4086 4087 case VM_PROT_READ: 4088 #if defined(ARM_MMU_EXTENDED) 4089 pmap_acquire_page_lock(md); 4090 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4091 pmap_release_page_lock(md); 4092 break; 4093 #endif 4094 case VM_PROT_READ|VM_PROT_EXECUTE: 4095 pmap_acquire_page_lock(md); 4096 pmap_clearbit(md, pa, PVF_WRITE); 4097 pmap_release_page_lock(md); 4098 break; 4099 4100 default: 4101 pmap_page_remove(md, pa); 4102 break; 4103 } 4104 } 4105 4106 /* 4107 * pmap_clear_modify: 4108 * 4109 * Clear the "modified" attribute for a page. 4110 */ 4111 bool 4112 pmap_clear_modify(struct vm_page *pg) 4113 { 4114 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4115 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4116 bool rv; 4117 4118 pmap_acquire_page_lock(md); 4119 4120 if (md->pvh_attrs & PVF_MOD) { 4121 rv = true; 4122 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4123 /* 4124 * If we are going to clear the modified bit and there are 4125 * no other modified bits set, flush the page to memory and 4126 * mark it clean. 4127 */ 4128 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4129 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4130 #endif 4131 pmap_clearbit(md, pa, PVF_MOD); 4132 } else { 4133 rv = false; 4134 } 4135 pmap_release_page_lock(md); 4136 4137 return rv; 4138 } 4139 4140 /* 4141 * pmap_clear_reference: 4142 * 4143 * Clear the "referenced" attribute for a page. 4144 */ 4145 bool 4146 pmap_clear_reference(struct vm_page *pg) 4147 { 4148 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4149 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4150 bool rv; 4151 4152 pmap_acquire_page_lock(md); 4153 4154 if (md->pvh_attrs & PVF_REF) { 4155 rv = true; 4156 pmap_clearbit(md, pa, PVF_REF); 4157 } else { 4158 rv = false; 4159 } 4160 pmap_release_page_lock(md); 4161 4162 return rv; 4163 } 4164 4165 /* 4166 * pmap_is_modified: 4167 * 4168 * Test if a page has the "modified" attribute. 4169 */ 4170 /* See <arm/arm32/pmap.h> */ 4171 4172 /* 4173 * pmap_is_referenced: 4174 * 4175 * Test if a page has the "referenced" attribute. 4176 */ 4177 /* See <arm/arm32/pmap.h> */ 4178 4179 #if defined(ARM_MMU_EXTENDED) && 0 4180 int 4181 pmap_prefetchabt_fixup(void *v) 4182 { 4183 struct trapframe * const tf = v; 4184 vaddr_t va = trunc_page(tf->tf_pc); 4185 int rv = ABORT_FIXUP_FAILED; 4186 4187 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4188 return rv; 4189 4190 kpreempt_disable(); 4191 pmap_t pm = curcpu()->ci_pmap_cur; 4192 const size_t l1slot = l1pte_index(va); 4193 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4194 if (l2 == NULL) 4195 goto out; 4196 4197 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4198 if (l2b->l2b_kva == NULL) 4199 goto out; 4200 4201 /* 4202 * Check the PTE itself. 4203 */ 4204 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4205 const pt_entry_t opte = *ptep; 4206 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4207 goto out; 4208 4209 paddr_t pa = l2pte_pa(pte); 4210 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4211 KASSERT(pg != NULL); 4212 4213 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4214 4215 pmap_acquire_page_lock(md); 4216 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4217 KASSERT(pv != NULL); 4218 4219 if (PV_IS_EXEC_P(pv->pv_flags)) { 4220 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4221 pmap_syncicache_page(md, pa); 4222 } 4223 rv = ABORT_FIXUP_RETURN; 4224 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4225 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4226 } 4227 pmap_release_page_lock(md); 4228 4229 out: 4230 kpreempt_enable(); 4231 return rv; 4232 } 4233 #endif 4234 4235 int 4236 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4237 { 4238 struct l2_dtable *l2; 4239 struct l2_bucket *l2b; 4240 paddr_t pa; 4241 const size_t l1slot = l1pte_index(va); 4242 int rv = 0; 4243 4244 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4245 4246 va = trunc_page(va); 4247 4248 KASSERT(!user || (pm != pmap_kernel())); 4249 4250 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4251 pm, va, ftype, user); 4252 #ifdef ARM_MMU_EXTENDED 4253 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4254 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4255 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4256 #endif 4257 4258 pmap_acquire_pmap_lock(pm); 4259 4260 /* 4261 * If there is no l2_dtable for this address, then the process 4262 * has no business accessing it. 4263 * 4264 * Note: This will catch userland processes trying to access 4265 * kernel addresses. 4266 */ 4267 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4268 if (l2 == NULL) { 4269 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4270 goto out; 4271 } 4272 4273 /* 4274 * Likewise if there is no L2 descriptor table 4275 */ 4276 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4277 if (l2b->l2b_kva == NULL) { 4278 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4279 goto out; 4280 } 4281 4282 /* 4283 * Check the PTE itself. 4284 */ 4285 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4286 pt_entry_t const opte = *ptep; 4287 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4288 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4289 goto out; 4290 } 4291 4292 #ifndef ARM_HAS_VBAR 4293 /* 4294 * Catch a userland access to the vector page mapped at 0x0 4295 */ 4296 if (user && (opte & L2_S_PROT_U) == 0) { 4297 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4298 goto out; 4299 } 4300 #endif 4301 4302 pa = l2pte_pa(opte); 4303 4304 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4305 /* 4306 * This looks like a good candidate for "page modified" 4307 * emulation... 4308 */ 4309 struct pv_entry *pv; 4310 struct vm_page *pg; 4311 4312 /* Extract the physical address of the page */ 4313 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4314 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4315 goto out; 4316 } 4317 4318 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4319 4320 /* Get the current flags for this page. */ 4321 pmap_acquire_page_lock(md); 4322 pv = pmap_find_pv(md, pm, va); 4323 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4324 pmap_release_page_lock(md); 4325 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4326 goto out; 4327 } 4328 4329 /* 4330 * Do the flags say this page is writable? If not then it 4331 * is a genuine write fault. If yes then the write fault is 4332 * our fault as we did not reflect the write access in the 4333 * PTE. Now we know a write has occurred we can correct this 4334 * and also set the modified bit 4335 */ 4336 if ((pv->pv_flags & PVF_WRITE) == 0) { 4337 pmap_release_page_lock(md); 4338 goto out; 4339 } 4340 4341 md->pvh_attrs |= PVF_REF | PVF_MOD; 4342 pv->pv_flags |= PVF_REF | PVF_MOD; 4343 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4344 /* 4345 * If there are cacheable mappings for this page, mark it dirty. 4346 */ 4347 if ((md->pvh_attrs & PVF_NC) == 0) 4348 md->pvh_attrs |= PVF_DIRTY; 4349 #endif 4350 #ifdef ARM_MMU_EXTENDED 4351 if (md->pvh_attrs & PVF_EXEC) { 4352 md->pvh_attrs &= ~PVF_EXEC; 4353 PMAPCOUNT(exec_discarded_modfixup); 4354 } 4355 #endif 4356 pmap_release_page_lock(md); 4357 4358 /* 4359 * Re-enable write permissions for the page. No need to call 4360 * pmap_vac_me_harder(), since this is just a 4361 * modified-emulation fault, and the PVF_WRITE bit isn't 4362 * changing. We've already set the cacheable bits based on 4363 * the assumption that we can write to this page. 4364 */ 4365 const pt_entry_t npte = 4366 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4367 #ifdef ARM_MMU_EXTENDED 4368 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4369 #endif 4370 | 0; 4371 l2pte_set(ptep, npte, opte); 4372 PTE_SYNC(ptep); 4373 PMAPCOUNT(fixup_mod); 4374 rv = 1; 4375 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4376 opte, npte, 0, 0); 4377 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4378 /* 4379 * This looks like a good candidate for "page referenced" 4380 * emulation. 4381 */ 4382 struct vm_page *pg; 4383 4384 /* Extract the physical address of the page */ 4385 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4386 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4387 goto out; 4388 } 4389 4390 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4391 4392 /* Get the current flags for this page. */ 4393 pmap_acquire_page_lock(md); 4394 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4395 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4396 pmap_release_page_lock(md); 4397 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4398 goto out; 4399 } 4400 4401 md->pvh_attrs |= PVF_REF; 4402 pv->pv_flags |= PVF_REF; 4403 4404 pt_entry_t npte = 4405 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4406 #ifdef ARM_MMU_EXTENDED 4407 if (pm != pmap_kernel()) { 4408 npte |= L2_XS_nG; 4409 } 4410 /* 4411 * If we got called from prefetch abort, then ftype will have 4412 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4413 * the PTE. 4414 */ 4415 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4416 /* 4417 * Is this a mapping of an executable page? 4418 */ 4419 if ((pv->pv_flags & PVF_EXEC) == 0) { 4420 pmap_release_page_lock(md); 4421 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4422 0, 0, 0, 0); 4423 goto out; 4424 } 4425 /* 4426 * If we haven't synced the page, do so now. 4427 */ 4428 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4429 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4430 pa, 0, 0, 0); 4431 pmap_syncicache_page(md, pa); 4432 PMAPCOUNT(fixup_exec); 4433 } 4434 npte &= ~L2_XS_XN; 4435 } 4436 #endif /* ARM_MMU_EXTENDED */ 4437 pmap_release_page_lock(md); 4438 l2pte_set(ptep, npte, opte); 4439 PTE_SYNC(ptep); 4440 PMAPCOUNT(fixup_ref); 4441 rv = 1; 4442 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4443 opte, npte, 0, 0); 4444 #ifdef ARM_MMU_EXTENDED 4445 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4446 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4447 if (pg == NULL) { 4448 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4449 goto out; 4450 } 4451 4452 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4453 4454 /* Get the current flags for this page. */ 4455 pmap_acquire_page_lock(md); 4456 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4457 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4458 pmap_release_page_lock(md); 4459 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4460 goto out; 4461 } 4462 4463 /* 4464 * If we haven't synced the page, do so now. 4465 */ 4466 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4467 UVMHIST_LOG(maphist, "syncicache page #%#x", 4468 pa, 0, 0, 0); 4469 pmap_syncicache_page(md, pa); 4470 } 4471 pmap_release_page_lock(md); 4472 /* 4473 * Turn off no-execute. 4474 */ 4475 KASSERT(opte & L2_XS_nG); 4476 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4477 PTE_SYNC(ptep); 4478 rv = 1; 4479 PMAPCOUNT(fixup_exec); 4480 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4481 opte, opte & ~L2_XS_XN, 0, 0); 4482 #endif 4483 } 4484 4485 #ifndef ARM_MMU_EXTENDED 4486 /* 4487 * We know there is a valid mapping here, so simply 4488 * fix up the L1 if necessary. 4489 */ 4490 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4491 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4492 if (*pdep != pde) { 4493 l1pte_setone(pdep, pde); 4494 PTE_SYNC(pdep); 4495 rv = 1; 4496 PMAPCOUNT(fixup_pdes); 4497 } 4498 #endif 4499 4500 #ifdef CPU_SA110 4501 /* 4502 * There are bugs in the rev K SA110. This is a check for one 4503 * of them. 4504 */ 4505 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4506 curcpu()->ci_arm_cpurev < 3) { 4507 /* Always current pmap */ 4508 if (l2pte_valid_p(opte)) { 4509 extern int kernel_debug; 4510 if (kernel_debug & 1) { 4511 struct proc *p = curlwp->l_proc; 4512 printf("prefetch_abort: page is already " 4513 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4514 printf("prefetch_abort: pc=%08lx proc=%p " 4515 "process=%s\n", va, p, p->p_comm); 4516 printf("prefetch_abort: far=%08x fs=%x\n", 4517 cpu_faultaddress(), cpu_faultstatus()); 4518 } 4519 #ifdef DDB 4520 if (kernel_debug & 2) 4521 Debugger(); 4522 #endif 4523 rv = 1; 4524 } 4525 } 4526 #endif /* CPU_SA110 */ 4527 4528 #ifndef ARM_MMU_EXTENDED 4529 /* 4530 * If 'rv == 0' at this point, it generally indicates that there is a 4531 * stale TLB entry for the faulting address. That might be due to a 4532 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4533 */ 4534 if (rv == 0 4535 && pm->pm_l1->l1_domain_use_count == 1 4536 && pmap_needs_pte_sync == 0) { 4537 pmap_needs_pte_sync = 1; 4538 PTE_SYNC(ptep); 4539 PMAPCOUNT(fixup_ptesync); 4540 rv = 1; 4541 } 4542 #endif 4543 4544 #if defined(DEBUG) || 1 4545 /* 4546 * If 'rv == 0' at this point, it generally indicates that there is a 4547 * stale TLB entry for the faulting address. This happens when two or 4548 * more processes are sharing an L1. Since we don't flush the TLB on 4549 * a context switch between such processes, we can take domain faults 4550 * for mappings which exist at the same VA in both processes. EVEN IF 4551 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4552 * example. 4553 * 4554 * This is extremely likely to happen if pmap_enter() updated the L1 4555 * entry for a recently entered mapping. In this case, the TLB is 4556 * flushed for the new mapping, but there may still be TLB entries for 4557 * other mappings belonging to other processes in the 1MB range 4558 * covered by the L1 entry. 4559 * 4560 * Since 'rv == 0', we know that the L1 already contains the correct 4561 * value, so the fault must be due to a stale TLB entry. 4562 * 4563 * Since we always need to flush the TLB anyway in the case where we 4564 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4565 * stale TLB entries dynamically. 4566 * 4567 * However, the above condition can ONLY happen if the current L1 is 4568 * being shared. If it happens when the L1 is unshared, it indicates 4569 * that other parts of the pmap are not doing their job WRT managing 4570 * the TLB. 4571 */ 4572 if (rv == 0 4573 #ifndef ARM_MMU_EXTENDED 4574 && pm->pm_l1->l1_domain_use_count == 1 4575 #endif 4576 && true) { 4577 #ifdef DEBUG 4578 extern int last_fault_code; 4579 #else 4580 int last_fault_code = ftype & VM_PROT_EXECUTE 4581 ? armreg_ifsr_read() 4582 : armreg_dfsr_read(); 4583 #endif 4584 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4585 pm, va, ftype); 4586 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4587 l2, l2b, ptep, opte); 4588 4589 #ifndef ARM_MMU_EXTENDED 4590 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4591 pdep, pde, last_fault_code); 4592 #else 4593 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4594 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4595 armreg_ttbcr_read()); 4596 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4597 last_fault_code, curcpu()->ci_pmap_cur, 4598 curcpu()->ci_pmap_asid_cur, 4599 armreg_contextidr_read(), armreg_dacr_read()); 4600 #ifdef _ARM_ARCH_7 4601 if (ftype & VM_PROT_WRITE) 4602 armreg_ats1cuw_write(va); 4603 else 4604 armreg_ats1cur_write(va); 4605 arm_isb(); 4606 printf("fixup: par %#x\n", armreg_par_read()); 4607 #endif 4608 #endif 4609 #ifdef DDB 4610 extern int kernel_debug; 4611 4612 if (kernel_debug & 2) { 4613 pmap_release_pmap_lock(pm); 4614 #ifdef UVMHIST 4615 KERNHIST_DUMP(maphist); 4616 #endif 4617 cpu_Debugger(); 4618 pmap_acquire_pmap_lock(pm); 4619 } 4620 #endif 4621 } 4622 #endif 4623 4624 pmap_tlb_flush_SE(pm, va, 4625 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4626 4627 rv = 1; 4628 4629 out: 4630 pmap_release_pmap_lock(pm); 4631 4632 return (rv); 4633 } 4634 4635 /* 4636 * Routine: pmap_procwr 4637 * 4638 * Function: 4639 * Synchronize caches corresponding to [addr, addr+len) in p. 4640 * 4641 */ 4642 void 4643 pmap_procwr(struct proc *p, vaddr_t va, int len) 4644 { 4645 /* We only need to do anything if it is the current process. */ 4646 if (p == curproc) 4647 cpu_icache_sync_range(va, len); 4648 } 4649 4650 /* 4651 * Routine: pmap_unwire 4652 * Function: Clear the wired attribute for a map/virtual-address pair. 4653 * 4654 * In/out conditions: 4655 * The mapping must already exist in the pmap. 4656 */ 4657 void 4658 pmap_unwire(pmap_t pm, vaddr_t va) 4659 { 4660 struct l2_bucket *l2b; 4661 pt_entry_t *ptep, pte; 4662 struct vm_page *pg; 4663 paddr_t pa; 4664 4665 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4666 4667 pmap_acquire_pmap_lock(pm); 4668 4669 l2b = pmap_get_l2_bucket(pm, va); 4670 KDASSERT(l2b != NULL); 4671 4672 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4673 pte = *ptep; 4674 4675 /* Extract the physical address of the page */ 4676 pa = l2pte_pa(pte); 4677 4678 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4679 /* Update the wired bit in the pv entry for this page. */ 4680 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4681 4682 pmap_acquire_page_lock(md); 4683 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4684 pmap_release_page_lock(md); 4685 } 4686 4687 pmap_release_pmap_lock(pm); 4688 } 4689 4690 void 4691 pmap_activate(struct lwp *l) 4692 { 4693 struct cpu_info * const ci = curcpu(); 4694 extern int block_userspace_access; 4695 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4696 #ifdef ARM_MMU_EXTENDED 4697 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4698 #endif 4699 4700 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4701 4702 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4703 4704 /* 4705 * If activating a non-current lwp or the current lwp is 4706 * already active, just return. 4707 */ 4708 if (false 4709 || l != curlwp 4710 #ifdef ARM_MMU_EXTENDED 4711 || (ci->ci_pmap_cur == npm && 4712 (npm == pmap_kernel() 4713 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4714 #else 4715 || npm->pm_activated == true 4716 #endif 4717 || false) { 4718 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4719 return; 4720 } 4721 4722 #ifndef ARM_MMU_EXTENDED 4723 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4724 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4725 4726 /* 4727 * If TTB and DACR are unchanged, short-circuit all the 4728 * TLB/cache management stuff. 4729 */ 4730 pmap_t opm = ci->ci_lastlwp 4731 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4732 : NULL; 4733 if (opm != NULL) { 4734 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4735 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4736 4737 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4738 goto all_done; 4739 } 4740 #endif /* !ARM_MMU_EXTENDED */ 4741 4742 PMAPCOUNT(activations); 4743 block_userspace_access = 1; 4744 4745 #ifndef ARM_MMU_EXTENDED 4746 /* 4747 * If switching to a user vmspace which is different to the 4748 * most recent one, and the most recent one is potentially 4749 * live in the cache, we must write-back and invalidate the 4750 * entire cache. 4751 */ 4752 pmap_t rpm = ci->ci_pmap_lastuser; 4753 #endif 4754 4755 /* 4756 * XXXSCW: There's a corner case here which can leave turds in the cache as 4757 * reported in kern/41058. They're probably left over during tear-down and 4758 * switching away from an exiting process. Until the root cause is identified 4759 * and fixed, zap the cache when switching pmaps. This will result in a few 4760 * unnecessary cache flushes, but that's better than silently corrupting data. 4761 */ 4762 #ifndef ARM_MMU_EXTENDED 4763 #if 0 4764 if (npm != pmap_kernel() && rpm && npm != rpm && 4765 rpm->pm_cstate.cs_cache) { 4766 rpm->pm_cstate.cs_cache = 0; 4767 #ifdef PMAP_CACHE_VIVT 4768 cpu_idcache_wbinv_all(); 4769 #endif 4770 } 4771 #else 4772 if (rpm) { 4773 rpm->pm_cstate.cs_cache = 0; 4774 if (npm == pmap_kernel()) 4775 ci->ci_pmap_lastuser = NULL; 4776 #ifdef PMAP_CACHE_VIVT 4777 cpu_idcache_wbinv_all(); 4778 #endif 4779 } 4780 #endif 4781 4782 /* No interrupts while we frob the TTB/DACR */ 4783 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4784 #endif /* !ARM_MMU_EXTENDED */ 4785 4786 #ifndef ARM_HAS_VBAR 4787 /* 4788 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4789 * entry corresponding to 'vector_page' in the incoming L1 table 4790 * before switching to it otherwise subsequent interrupts/exceptions 4791 * (including domain faults!) will jump into hyperspace. 4792 */ 4793 if (npm->pm_pl1vec != NULL) { 4794 cpu_tlb_flushID_SE((u_int)vector_page); 4795 cpu_cpwait(); 4796 *npm->pm_pl1vec = npm->pm_l1vec; 4797 PTE_SYNC(npm->pm_pl1vec); 4798 } 4799 #endif 4800 4801 #ifdef ARM_MMU_EXTENDED 4802 /* 4803 * Assume that TTBR1 has only global mappings and TTBR0 only has 4804 * non-global mappings. To prevent speculation from doing evil things 4805 * we disable translation table walks using TTBR0 before setting the 4806 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4807 * walks are reenabled. 4808 */ 4809 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4810 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4811 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4812 arm_isb(); 4813 pmap_tlb_asid_acquire(npm, l); 4814 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4815 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4816 /* 4817 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4818 * been updated. 4819 */ 4820 arm_isb(); 4821 if (npm != pmap_kernel()) { 4822 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4823 } 4824 cpu_cpwait(); 4825 ci->ci_pmap_asid_cur = pai->pai_asid; 4826 #else 4827 cpu_domains(ndacr); 4828 if (npm == pmap_kernel() || npm == rpm) { 4829 /* 4830 * Switching to a kernel thread, or back to the 4831 * same user vmspace as before... Simply update 4832 * the TTB (no TLB flush required) 4833 */ 4834 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4835 cpu_cpwait(); 4836 } else { 4837 /* 4838 * Otherwise, update TTB and flush TLB 4839 */ 4840 cpu_context_switch(npm->pm_l1->l1_physaddr); 4841 if (rpm != NULL) 4842 rpm->pm_cstate.cs_tlb = 0; 4843 } 4844 4845 restore_interrupts(oldirqstate); 4846 #endif /* ARM_MMU_EXTENDED */ 4847 4848 block_userspace_access = 0; 4849 4850 #ifndef ARM_MMU_EXTENDED 4851 all_done: 4852 /* 4853 * The new pmap is resident. Make sure it's marked 4854 * as resident in the cache/TLB. 4855 */ 4856 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4857 if (npm != pmap_kernel()) 4858 ci->ci_pmap_lastuser = npm; 4859 4860 /* The old pmap is not longer active */ 4861 if (opm != npm) { 4862 if (opm != NULL) 4863 opm->pm_activated = false; 4864 4865 /* But the new one is */ 4866 npm->pm_activated = true; 4867 } 4868 #endif 4869 ci->ci_pmap_cur = npm; 4870 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4871 } 4872 4873 void 4874 pmap_deactivate(struct lwp *l) 4875 { 4876 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4877 4878 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4879 4880 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4881 4882 #ifdef ARM_MMU_EXTENDED 4883 kpreempt_disable(); 4884 struct cpu_info * const ci = curcpu(); 4885 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4886 /* 4887 * Disable translation table walks from TTBR0 while no pmap has been 4888 * activated. 4889 */ 4890 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4891 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4892 arm_isb(); 4893 pmap_tlb_asid_deactivate(pm); 4894 cpu_setttb(pmap_kernel()->pm_l1_pa, pai->pai_asid); 4895 ci->ci_pmap_cur = pmap_kernel(); 4896 kpreempt_enable(); 4897 #else 4898 /* 4899 * If the process is exiting, make sure pmap_activate() does 4900 * a full MMU context-switch and cache flush, which we might 4901 * otherwise skip. See PR port-arm/38950. 4902 */ 4903 if (l->l_proc->p_sflag & PS_WEXIT) 4904 curcpu()->ci_lastlwp = NULL; 4905 4906 pm->pm_activated = false; 4907 #endif 4908 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4909 } 4910 4911 void 4912 pmap_update(pmap_t pm) 4913 { 4914 4915 if (pm->pm_remove_all) { 4916 #ifdef ARM_MMU_EXTENDED 4917 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4918 /* 4919 * Finish up the pmap_remove_all() optimisation by flushing 4920 * all our ASIDs. 4921 */ 4922 pmap_tlb_asid_release_all(pm); 4923 #else 4924 /* 4925 * Finish up the pmap_remove_all() optimisation by flushing 4926 * the TLB. 4927 */ 4928 pmap_tlb_flushID(pm); 4929 #endif 4930 pm->pm_remove_all = false; 4931 } 4932 4933 #ifdef ARM_MMU_EXTENDED 4934 4935 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4936 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4937 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4938 PMAP_COUNT(shootdown_ipis); 4939 } 4940 #endif 4941 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4942 #else 4943 if (pmap_is_current(pm)) { 4944 /* 4945 * If we're dealing with a current userland pmap, move its L1 4946 * to the end of the LRU. 4947 */ 4948 if (pm != pmap_kernel()) 4949 pmap_use_l1(pm); 4950 4951 /* 4952 * We can assume we're done with frobbing the cache/tlb for 4953 * now. Make sure any future pmap ops don't skip cache/tlb 4954 * flushes. 4955 */ 4956 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4957 } 4958 #endif 4959 4960 PMAPCOUNT(updates); 4961 4962 /* 4963 * make sure TLB/cache operations have completed. 4964 */ 4965 cpu_cpwait(); 4966 } 4967 4968 void 4969 pmap_remove_all(pmap_t pm) 4970 { 4971 4972 /* 4973 * The vmspace described by this pmap is about to be torn down. 4974 * Until pmap_update() is called, UVM will only make calls 4975 * to pmap_remove(). We can make life much simpler by flushing 4976 * the cache now, and deferring TLB invalidation to pmap_update(). 4977 */ 4978 #ifdef PMAP_CACHE_VIVT 4979 pmap_cache_wbinv_all(pm, PVF_EXEC); 4980 #endif 4981 pm->pm_remove_all = true; 4982 } 4983 4984 /* 4985 * Retire the given physical map from service. 4986 * Should only be called if the map contains no valid mappings. 4987 */ 4988 void 4989 pmap_destroy(pmap_t pm) 4990 { 4991 u_int count; 4992 4993 if (pm == NULL) 4994 return; 4995 4996 if (pm->pm_remove_all) { 4997 pmap_tlb_flushID(pm); 4998 pm->pm_remove_all = false; 4999 } 5000 5001 /* 5002 * Drop reference count 5003 */ 5004 mutex_enter(pm->pm_lock); 5005 count = --pm->pm_obj.uo_refs; 5006 mutex_exit(pm->pm_lock); 5007 if (count > 0) { 5008 #ifndef ARM_MMU_EXTENDED 5009 if (pmap_is_current(pm)) { 5010 if (pm != pmap_kernel()) 5011 pmap_use_l1(pm); 5012 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5013 } 5014 #endif 5015 return; 5016 } 5017 5018 /* 5019 * reference count is zero, free pmap resources and then free pmap. 5020 */ 5021 5022 #ifndef ARM_HAS_VBAR 5023 if (vector_page < KERNEL_BASE) { 5024 KDASSERT(!pmap_is_current(pm)); 5025 5026 /* Remove the vector page mapping */ 5027 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5028 pmap_update(pm); 5029 } 5030 #endif 5031 5032 LIST_REMOVE(pm, pm_list); 5033 5034 pmap_free_l1(pm); 5035 5036 #ifdef ARM_MMU_EXTENDED 5037 #ifdef MULTIPROCESSOR 5038 kcpuset_destroy(pm->pm_active); 5039 kcpuset_destroy(pm->pm_onproc); 5040 #endif 5041 #else 5042 struct cpu_info * const ci = curcpu(); 5043 if (ci->ci_pmap_lastuser == pm) 5044 ci->ci_pmap_lastuser = NULL; 5045 #endif 5046 5047 uvm_obj_destroy(&pm->pm_obj, false); 5048 mutex_destroy(&pm->pm_obj_lock); 5049 pool_cache_put(&pmap_cache, pm); 5050 } 5051 5052 5053 /* 5054 * void pmap_reference(pmap_t pm) 5055 * 5056 * Add a reference to the specified pmap. 5057 */ 5058 void 5059 pmap_reference(pmap_t pm) 5060 { 5061 5062 if (pm == NULL) 5063 return; 5064 5065 #ifndef ARM_MMU_EXTENDED 5066 pmap_use_l1(pm); 5067 #endif 5068 5069 mutex_enter(pm->pm_lock); 5070 pm->pm_obj.uo_refs++; 5071 mutex_exit(pm->pm_lock); 5072 } 5073 5074 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5075 5076 static struct evcnt pmap_prefer_nochange_ev = 5077 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5078 static struct evcnt pmap_prefer_change_ev = 5079 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5080 5081 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5082 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5083 5084 void 5085 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5086 { 5087 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5088 vaddr_t va = *vap; 5089 vaddr_t diff = (hint - va) & mask; 5090 if (diff == 0) { 5091 pmap_prefer_nochange_ev.ev_count++; 5092 } else { 5093 pmap_prefer_change_ev.ev_count++; 5094 if (__predict_false(td)) 5095 va -= mask + 1; 5096 *vap = va + diff; 5097 } 5098 } 5099 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5100 5101 /* 5102 * pmap_zero_page() 5103 * 5104 * Zero a given physical page by mapping it at a page hook point. 5105 * In doing the zero page op, the page we zero is mapped cachable, as with 5106 * StrongARM accesses to non-cached pages are non-burst making writing 5107 * _any_ bulk data very slow. 5108 */ 5109 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5110 void 5111 pmap_zero_page_generic(paddr_t pa) 5112 { 5113 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5114 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5115 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5116 #endif 5117 #if defined(PMAP_CACHE_VIPT) 5118 /* Choose the last page color it had, if any */ 5119 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5120 #else 5121 const vsize_t va_offset = 0; 5122 #endif 5123 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5124 /* 5125 * Is this page mapped at its natural color? 5126 * If we have all of memory mapped, then just convert PA to VA. 5127 */ 5128 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5129 || va_offset == (pa & arm_cache_prefer_mask); 5130 const vaddr_t vdstp = okcolor 5131 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5132 : cpu_cdstp(va_offset); 5133 #else 5134 const bool okcolor = false; 5135 const vaddr_t vdstp = cpu_cdstp(va_offset); 5136 #endif 5137 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5138 5139 5140 #ifdef DEBUG 5141 if (!SLIST_EMPTY(&md->pvh_list)) 5142 panic("pmap_zero_page: page has mappings"); 5143 #endif 5144 5145 KDASSERT((pa & PGOFSET) == 0); 5146 5147 if (!okcolor) { 5148 /* 5149 * Hook in the page, zero it, and purge the cache for that 5150 * zeroed page. Invalidate the TLB as needed. 5151 */ 5152 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5153 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5154 l2pte_set(ptep, npte, 0); 5155 PTE_SYNC(ptep); 5156 cpu_tlb_flushD_SE(vdstp); 5157 cpu_cpwait(); 5158 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5159 && !defined(ARM_MMU_EXTENDED) 5160 /* 5161 * If we are direct-mapped and our color isn't ok, then before 5162 * we bzero the page invalidate its contents from the cache and 5163 * reset the color to its natural color. 5164 */ 5165 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5166 md->pvh_attrs &= ~arm_cache_prefer_mask; 5167 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5168 #endif 5169 } 5170 bzero_page(vdstp); 5171 if (!okcolor) { 5172 /* 5173 * Unmap the page. 5174 */ 5175 l2pte_reset(ptep); 5176 PTE_SYNC(ptep); 5177 cpu_tlb_flushD_SE(vdstp); 5178 #ifdef PMAP_CACHE_VIVT 5179 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5180 #endif 5181 } 5182 #ifdef PMAP_CACHE_VIPT 5183 /* 5184 * This page is now cache resident so it now has a page color. 5185 * Any contents have been obliterated so clear the EXEC flag. 5186 */ 5187 #ifndef ARM_MMU_EXTENDED 5188 if (!pmap_is_page_colored_p(md)) { 5189 PMAPCOUNT(vac_color_new); 5190 md->pvh_attrs |= PVF_COLORED; 5191 } 5192 md->pvh_attrs |= PVF_DIRTY; 5193 #endif 5194 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5195 md->pvh_attrs &= ~PVF_EXEC; 5196 PMAPCOUNT(exec_discarded_zero); 5197 } 5198 #endif 5199 } 5200 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5201 5202 #if ARM_MMU_XSCALE == 1 5203 void 5204 pmap_zero_page_xscale(paddr_t pa) 5205 { 5206 #ifdef DEBUG 5207 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5208 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5209 5210 if (!SLIST_EMPTY(&md->pvh_list)) 5211 panic("pmap_zero_page: page has mappings"); 5212 #endif 5213 5214 KDASSERT((pa & PGOFSET) == 0); 5215 5216 /* 5217 * Hook in the page, zero it, and purge the cache for that 5218 * zeroed page. Invalidate the TLB as needed. 5219 */ 5220 5221 pt_entry_t npte = L2_S_PROTO | pa | 5222 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5223 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5224 l2pte_set(cdst_pte, npte, 0); 5225 PTE_SYNC(cdst_pte); 5226 cpu_tlb_flushD_SE(cdstp); 5227 cpu_cpwait(); 5228 bzero_page(cdstp); 5229 xscale_cache_clean_minidata(); 5230 l2pte_reset(cdst_pte); 5231 PTE_SYNC(cdst_pte); 5232 } 5233 #endif /* ARM_MMU_XSCALE == 1 */ 5234 5235 /* pmap_pageidlezero() 5236 * 5237 * The same as above, except that we assume that the page is not 5238 * mapped. This means we never have to flush the cache first. Called 5239 * from the idle loop. 5240 */ 5241 bool 5242 pmap_pageidlezero(paddr_t pa) 5243 { 5244 bool rv = true; 5245 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5246 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5247 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5248 #endif 5249 #ifdef PMAP_CACHE_VIPT 5250 /* Choose the last page color it had, if any */ 5251 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5252 #else 5253 const vsize_t va_offset = 0; 5254 #endif 5255 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5256 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5257 || va_offset == (pa & arm_cache_prefer_mask); 5258 const vaddr_t vdstp = okcolor 5259 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5260 : cpu_cdstp(va_offset); 5261 #else 5262 const bool okcolor = false; 5263 const vaddr_t vdstp = cpu_cdstp(va_offset); 5264 #endif 5265 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5266 5267 5268 #ifdef DEBUG 5269 if (!SLIST_EMPTY(&md->pvh_list)) 5270 panic("pmap_pageidlezero: page has mappings"); 5271 #endif 5272 5273 KDASSERT((pa & PGOFSET) == 0); 5274 5275 if (!okcolor) { 5276 /* 5277 * Hook in the page, zero it, and purge the cache for that 5278 * zeroed page. Invalidate the TLB as needed. 5279 */ 5280 const pt_entry_t npte = L2_S_PROTO | pa | 5281 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5282 l2pte_set(ptep, npte, 0); 5283 PTE_SYNC(ptep); 5284 cpu_tlb_flushD_SE(vdstp); 5285 cpu_cpwait(); 5286 } 5287 5288 uint64_t *ptr = (uint64_t *)vdstp; 5289 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5290 if (sched_curcpu_runnable_p() != 0) { 5291 /* 5292 * A process has become ready. Abort now, 5293 * so we don't keep it waiting while we 5294 * do slow memory access to finish this 5295 * page. 5296 */ 5297 rv = false; 5298 break; 5299 } 5300 *ptr++ = 0; 5301 } 5302 5303 #ifdef PMAP_CACHE_VIVT 5304 if (rv) 5305 /* 5306 * if we aborted we'll rezero this page again later so don't 5307 * purge it unless we finished it 5308 */ 5309 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5310 #elif defined(PMAP_CACHE_VIPT) 5311 /* 5312 * This page is now cache resident so it now has a page color. 5313 * Any contents have been obliterated so clear the EXEC flag. 5314 */ 5315 #ifndef ARM_MMU_EXTENDED 5316 if (!pmap_is_page_colored_p(md)) { 5317 PMAPCOUNT(vac_color_new); 5318 md->pvh_attrs |= PVF_COLORED; 5319 } 5320 #endif 5321 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5322 md->pvh_attrs &= ~PVF_EXEC; 5323 PMAPCOUNT(exec_discarded_zero); 5324 } 5325 #endif 5326 /* 5327 * Unmap the page. 5328 */ 5329 if (!okcolor) { 5330 l2pte_reset(ptep); 5331 PTE_SYNC(ptep); 5332 cpu_tlb_flushD_SE(vdstp); 5333 } 5334 5335 return rv; 5336 } 5337 5338 /* 5339 * pmap_copy_page() 5340 * 5341 * Copy one physical page into another, by mapping the pages into 5342 * hook points. The same comment regarding cachability as in 5343 * pmap_zero_page also applies here. 5344 */ 5345 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5346 void 5347 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5348 { 5349 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5350 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5351 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5352 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5353 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5354 #endif 5355 #ifdef PMAP_CACHE_VIPT 5356 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5357 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5358 #else 5359 const vsize_t src_va_offset = 0; 5360 const vsize_t dst_va_offset = 0; 5361 #endif 5362 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5363 /* 5364 * Is this page mapped at its natural color? 5365 * If we have all of memory mapped, then just convert PA to VA. 5366 */ 5367 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5368 || src_va_offset == (src & arm_cache_prefer_mask); 5369 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5370 || dst_va_offset == (dst & arm_cache_prefer_mask); 5371 const vaddr_t vsrcp = src_okcolor 5372 ? pmap_direct_mapped_phys(src, &src_okcolor, 5373 cpu_csrcp(src_va_offset)) 5374 : cpu_csrcp(src_va_offset); 5375 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5376 cpu_cdstp(dst_va_offset)); 5377 #else 5378 const bool src_okcolor = false; 5379 const bool dst_okcolor = false; 5380 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5381 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5382 #endif 5383 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5384 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5385 5386 #ifdef DEBUG 5387 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5388 panic("pmap_copy_page: dst page has mappings"); 5389 #endif 5390 5391 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5392 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5393 #endif 5394 KDASSERT((src & PGOFSET) == 0); 5395 KDASSERT((dst & PGOFSET) == 0); 5396 5397 /* 5398 * Clean the source page. Hold the source page's lock for 5399 * the duration of the copy so that no other mappings can 5400 * be created while we have a potentially aliased mapping. 5401 */ 5402 #ifdef PMAP_CACHE_VIVT 5403 pmap_acquire_page_lock(src_md); 5404 (void) pmap_clean_page(src_md, true); 5405 pmap_release_page_lock(src_md); 5406 #endif 5407 5408 /* 5409 * Map the pages into the page hook points, copy them, and purge 5410 * the cache for the appropriate page. Invalidate the TLB 5411 * as required. 5412 */ 5413 if (!src_okcolor) { 5414 const pt_entry_t nsrc_pte = L2_S_PROTO 5415 | src 5416 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5417 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5418 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5419 | pte_l2_s_cache_mode 5420 #endif 5421 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5422 l2pte_set(src_ptep, nsrc_pte, 0); 5423 PTE_SYNC(src_ptep); 5424 cpu_tlb_flushD_SE(vsrcp); 5425 cpu_cpwait(); 5426 } 5427 if (!dst_okcolor) { 5428 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5429 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5430 l2pte_set(dst_ptep, ndst_pte, 0); 5431 PTE_SYNC(dst_ptep); 5432 cpu_tlb_flushD_SE(vdstp); 5433 cpu_cpwait(); 5434 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5435 /* 5436 * If we are direct-mapped and our color isn't ok, then before 5437 * we bcopy to the new page invalidate its contents from the 5438 * cache and reset its color to its natural color. 5439 */ 5440 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5441 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5442 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5443 #endif 5444 } 5445 bcopy_page(vsrcp, vdstp); 5446 #ifdef PMAP_CACHE_VIVT 5447 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5448 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5449 #endif 5450 /* 5451 * Unmap the pages. 5452 */ 5453 if (!src_okcolor) { 5454 l2pte_reset(src_ptep); 5455 PTE_SYNC(src_ptep); 5456 cpu_tlb_flushD_SE(vsrcp); 5457 cpu_cpwait(); 5458 } 5459 if (!dst_okcolor) { 5460 l2pte_reset(dst_ptep); 5461 PTE_SYNC(dst_ptep); 5462 cpu_tlb_flushD_SE(vdstp); 5463 cpu_cpwait(); 5464 } 5465 #ifdef PMAP_CACHE_VIPT 5466 /* 5467 * Now that the destination page is in the cache, mark it as colored. 5468 * If this was an exec page, discard it. 5469 */ 5470 pmap_acquire_page_lock(dst_md); 5471 #ifndef ARM_MMU_EXTENDED 5472 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5473 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5474 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5475 } 5476 if (!pmap_is_page_colored_p(dst_md)) { 5477 PMAPCOUNT(vac_color_new); 5478 dst_md->pvh_attrs |= PVF_COLORED; 5479 } 5480 dst_md->pvh_attrs |= PVF_DIRTY; 5481 #endif 5482 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5483 dst_md->pvh_attrs &= ~PVF_EXEC; 5484 PMAPCOUNT(exec_discarded_copy); 5485 } 5486 pmap_release_page_lock(dst_md); 5487 #endif 5488 } 5489 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5490 5491 #if ARM_MMU_XSCALE == 1 5492 void 5493 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5494 { 5495 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5496 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5497 #ifdef DEBUG 5498 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5499 5500 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5501 panic("pmap_copy_page: dst page has mappings"); 5502 #endif 5503 5504 KDASSERT((src & PGOFSET) == 0); 5505 KDASSERT((dst & PGOFSET) == 0); 5506 5507 /* 5508 * Clean the source page. Hold the source page's lock for 5509 * the duration of the copy so that no other mappings can 5510 * be created while we have a potentially aliased mapping. 5511 */ 5512 #ifdef PMAP_CACHE_VIVT 5513 pmap_acquire_page_lock(src_md); 5514 (void) pmap_clean_page(src_md, true); 5515 pmap_release_page_lock(src_md); 5516 #endif 5517 5518 /* 5519 * Map the pages into the page hook points, copy them, and purge 5520 * the cache for the appropriate page. Invalidate the TLB 5521 * as required. 5522 */ 5523 *csrc_pte = L2_S_PROTO | src | 5524 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 5525 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5526 PTE_SYNC(csrc_pte); 5527 *cdst_pte = L2_S_PROTO | dst | 5528 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5529 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5530 PTE_SYNC(cdst_pte); 5531 cpu_tlb_flushD_SE(csrcp); 5532 cpu_tlb_flushD_SE(cdstp); 5533 cpu_cpwait(); 5534 bcopy_page(csrcp, cdstp); 5535 xscale_cache_clean_minidata(); 5536 } 5537 #endif /* ARM_MMU_XSCALE == 1 */ 5538 5539 /* 5540 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5541 * 5542 * Return the start and end addresses of the kernel's virtual space. 5543 * These values are setup in pmap_bootstrap and are updated as pages 5544 * are allocated. 5545 */ 5546 void 5547 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5548 { 5549 *start = virtual_avail; 5550 *end = virtual_end; 5551 } 5552 5553 /* 5554 * Helper function for pmap_grow_l2_bucket() 5555 */ 5556 static inline int 5557 pmap_grow_map(vaddr_t va, paddr_t *pap) 5558 { 5559 paddr_t pa; 5560 5561 if (uvm.page_init_done == false) { 5562 #ifdef PMAP_STEAL_MEMORY 5563 pv_addr_t pv; 5564 pmap_boot_pagealloc(PAGE_SIZE, 5565 #ifdef PMAP_CACHE_VIPT 5566 arm_cache_prefer_mask, 5567 va & arm_cache_prefer_mask, 5568 #else 5569 0, 0, 5570 #endif 5571 &pv); 5572 pa = pv.pv_pa; 5573 #else 5574 if (uvm_page_physget(&pa) == false) 5575 return (1); 5576 #endif /* PMAP_STEAL_MEMORY */ 5577 } else { 5578 struct vm_page *pg; 5579 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5580 if (pg == NULL) 5581 return (1); 5582 pa = VM_PAGE_TO_PHYS(pg); 5583 /* 5584 * This new page must not have any mappings. Enter it via 5585 * pmap_kenter_pa and let that routine do the hard work. 5586 */ 5587 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5588 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5589 pmap_kenter_pa(va, pa, 5590 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5591 } 5592 5593 if (pap) 5594 *pap = pa; 5595 5596 PMAPCOUNT(pt_mappings); 5597 #ifdef DEBUG 5598 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5599 KDASSERT(l2b != NULL); 5600 5601 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5602 const pt_entry_t opte = *ptep; 5603 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5604 #endif 5605 memset((void *)va, 0, PAGE_SIZE); 5606 return (0); 5607 } 5608 5609 /* 5610 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5611 * used by pmap_growkernel(). 5612 */ 5613 static inline struct l2_bucket * 5614 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5615 { 5616 struct l2_dtable *l2; 5617 struct l2_bucket *l2b; 5618 u_short l1slot; 5619 vaddr_t nva; 5620 5621 l1slot = l1pte_index(va); 5622 5623 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5624 /* 5625 * No mapping at this address, as there is 5626 * no entry in the L1 table. 5627 * Need to allocate a new l2_dtable. 5628 */ 5629 nva = pmap_kernel_l2dtable_kva; 5630 if ((nva & PGOFSET) == 0) { 5631 /* 5632 * Need to allocate a backing page 5633 */ 5634 if (pmap_grow_map(nva, NULL)) 5635 return (NULL); 5636 } 5637 5638 l2 = (struct l2_dtable *)nva; 5639 nva += sizeof(struct l2_dtable); 5640 5641 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5642 /* 5643 * The new l2_dtable straddles a page boundary. 5644 * Map in another page to cover it. 5645 */ 5646 if (pmap_grow_map(nva, NULL)) 5647 return (NULL); 5648 } 5649 5650 pmap_kernel_l2dtable_kva = nva; 5651 5652 /* 5653 * Link it into the parent pmap 5654 */ 5655 pm->pm_l2[L2_IDX(l1slot)] = l2; 5656 } 5657 5658 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5659 5660 /* 5661 * Fetch pointer to the L2 page table associated with the address. 5662 */ 5663 if (l2b->l2b_kva == NULL) { 5664 pt_entry_t *ptep; 5665 5666 /* 5667 * No L2 page table has been allocated. Chances are, this 5668 * is because we just allocated the l2_dtable, above. 5669 */ 5670 nva = pmap_kernel_l2ptp_kva; 5671 ptep = (pt_entry_t *)nva; 5672 if ((nva & PGOFSET) == 0) { 5673 /* 5674 * Need to allocate a backing page 5675 */ 5676 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5677 return (NULL); 5678 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5679 } 5680 5681 l2->l2_occupancy++; 5682 l2b->l2b_kva = ptep; 5683 l2b->l2b_l1slot = l1slot; 5684 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5685 5686 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5687 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5688 } 5689 5690 return (l2b); 5691 } 5692 5693 vaddr_t 5694 pmap_growkernel(vaddr_t maxkvaddr) 5695 { 5696 pmap_t kpm = pmap_kernel(); 5697 #ifndef ARM_MMU_EXTENDED 5698 struct l1_ttable *l1; 5699 #endif 5700 int s; 5701 5702 if (maxkvaddr <= pmap_curmaxkvaddr) 5703 goto out; /* we are OK */ 5704 5705 NPDEBUG(PDB_GROWKERN, 5706 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5707 pmap_curmaxkvaddr, maxkvaddr)); 5708 5709 KDASSERT(maxkvaddr <= virtual_end); 5710 5711 /* 5712 * whoops! we need to add kernel PTPs 5713 */ 5714 5715 s = splhigh(); /* to be safe */ 5716 mutex_enter(kpm->pm_lock); 5717 5718 /* Map 1MB at a time */ 5719 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5720 #ifdef ARM_MMU_EXTENDED 5721 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5722 pd_entry_t *pdep = spdep; 5723 #endif 5724 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5725 #ifdef ARM_MMU_EXTENDED 5726 pdep++, 5727 #endif 5728 l1slot++) { 5729 struct l2_bucket *l2b = 5730 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5731 KASSERT(l2b != NULL); 5732 5733 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5734 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5735 #ifdef ARM_MMU_EXTENDED 5736 l1pte_setone(pdep, npde); 5737 #else 5738 /* Distribute new L1 entry to all other L1s */ 5739 SLIST_FOREACH(l1, &l1_list, l1_link) { 5740 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5741 l1pte_setone(pdep, npde); 5742 PDE_SYNC(pdep); 5743 } 5744 #endif 5745 } 5746 #ifdef ARM_MMU_EXTENDED 5747 PDE_SYNC_RANGE(spdep, pdep - spdep); 5748 #endif 5749 5750 #ifdef PMAP_CACHE_VIVT 5751 /* 5752 * flush out the cache, expensive but growkernel will happen so 5753 * rarely 5754 */ 5755 cpu_dcache_wbinv_all(); 5756 cpu_tlb_flushD(); 5757 cpu_cpwait(); 5758 #endif 5759 5760 mutex_exit(kpm->pm_lock); 5761 splx(s); 5762 5763 out: 5764 return (pmap_curmaxkvaddr); 5765 } 5766 5767 /************************ Utility routines ****************************/ 5768 5769 #ifndef ARM_HAS_VBAR 5770 /* 5771 * vector_page_setprot: 5772 * 5773 * Manipulate the protection of the vector page. 5774 */ 5775 void 5776 vector_page_setprot(int prot) 5777 { 5778 struct l2_bucket *l2b; 5779 pt_entry_t *ptep; 5780 5781 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5782 /* 5783 * If we are using VBAR to use the vectors in the kernel, then it's 5784 * already mapped in the kernel text so no need to anything here. 5785 */ 5786 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5787 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5788 return; 5789 } 5790 #endif 5791 5792 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5793 KASSERT(l2b != NULL); 5794 5795 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5796 5797 const pt_entry_t opte = *ptep; 5798 #ifdef ARM_MMU_EXTENDED 5799 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5800 | L2_S_PROT(PTE_KERNEL, prot); 5801 #else 5802 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5803 | L2_S_PROT(PTE_KERNEL, prot); 5804 #endif 5805 l2pte_set(ptep, npte, opte); 5806 PTE_SYNC(ptep); 5807 cpu_tlb_flushD_SE(vector_page); 5808 cpu_cpwait(); 5809 } 5810 #endif 5811 5812 /* 5813 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5814 * Returns true if the mapping exists, else false. 5815 * 5816 * NOTE: This function is only used by a couple of arm-specific modules. 5817 * It is not safe to take any pmap locks here, since we could be right 5818 * in the middle of debugging the pmap anyway... 5819 * 5820 * It is possible for this routine to return false even though a valid 5821 * mapping does exist. This is because we don't lock, so the metadata 5822 * state may be inconsistent. 5823 * 5824 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5825 * a "section" mapping. 5826 */ 5827 bool 5828 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5829 { 5830 struct l2_dtable *l2; 5831 pd_entry_t *pdep, pde; 5832 pt_entry_t *ptep; 5833 u_short l1slot; 5834 5835 if (pm->pm_l1 == NULL) 5836 return false; 5837 5838 l1slot = l1pte_index(va); 5839 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5840 pde = *pdep; 5841 5842 if (l1pte_section_p(pde)) { 5843 *ptp = NULL; 5844 return true; 5845 } 5846 5847 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5848 if (l2 == NULL || 5849 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5850 return false; 5851 } 5852 5853 *ptp = &ptep[l2pte_index(va)]; 5854 return true; 5855 } 5856 5857 bool 5858 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5859 { 5860 5861 if (pm->pm_l1 == NULL) 5862 return false; 5863 5864 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5865 5866 return true; 5867 } 5868 5869 /************************ Bootstrapping routines ****************************/ 5870 5871 #ifndef ARM_MMU_EXTENDED 5872 static void 5873 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5874 { 5875 int i; 5876 5877 l1->l1_kva = l1pt; 5878 l1->l1_domain_use_count = 0; 5879 l1->l1_domain_first = 0; 5880 5881 for (i = 0; i < PMAP_DOMAINS; i++) 5882 l1->l1_domain_free[i] = i + 1; 5883 5884 /* 5885 * Copy the kernel's L1 entries to each new L1. 5886 */ 5887 if (pmap_initialized) 5888 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5889 5890 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5891 &l1->l1_physaddr) == false) 5892 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5893 5894 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5895 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5896 } 5897 #endif /* !ARM_MMU_EXTENDED */ 5898 5899 /* 5900 * pmap_bootstrap() is called from the board-specific initarm() routine 5901 * once the kernel L1/L2 descriptors tables have been set up. 5902 * 5903 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5904 * spread over a number of disparate files/functions. 5905 * 5906 * We are passed the following parameters 5907 * - kernel_l1pt 5908 * This is a pointer to the base of the kernel's L1 translation table. 5909 * - vstart 5910 * 1MB-aligned start of managed kernel virtual memory. 5911 * - vend 5912 * 1MB-aligned end of managed kernel virtual memory. 5913 * 5914 * We use the first parameter to build the metadata (struct l1_ttable and 5915 * struct l2_dtable) necessary to track kernel mappings. 5916 */ 5917 #define PMAP_STATIC_L2_SIZE 16 5918 void 5919 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5920 { 5921 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5922 #ifndef ARM_MMU_EXTENDED 5923 static struct l1_ttable static_l1; 5924 struct l1_ttable *l1 = &static_l1; 5925 #endif 5926 struct l2_dtable *l2; 5927 struct l2_bucket *l2b; 5928 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5929 pmap_t pm = pmap_kernel(); 5930 pt_entry_t *ptep; 5931 paddr_t pa; 5932 vsize_t size; 5933 int nptes, l2idx, l2next = 0; 5934 5935 #ifdef ARM_MMU_EXTENDED 5936 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5937 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5938 #endif 5939 5940 #ifdef VERBOSE_INIT_ARM 5941 printf("kpm "); 5942 #endif 5943 /* 5944 * Initialise the kernel pmap object 5945 */ 5946 curcpu()->ci_pmap_cur = pm; 5947 #ifdef ARM_MMU_EXTENDED 5948 pm->pm_l1 = l1pt; 5949 pm->pm_l1_pa = kernel_l1pt.pv_pa; 5950 #ifdef VERBOSE_INIT_ARM 5951 printf("tlb0 "); 5952 #endif 5953 pmap_tlb_info_init(&pmap_tlb0_info); 5954 #ifdef MULTIPROCESSOR 5955 #ifdef VERBOSE_INIT_ARM 5956 printf("kcpusets "); 5957 #endif 5958 pm->pm_onproc = kcpuset_running; 5959 pm->pm_active = kcpuset_running; 5960 #endif 5961 #else 5962 pm->pm_l1 = l1; 5963 #endif 5964 5965 #ifdef VERBOSE_INIT_ARM 5966 printf("locks "); 5967 #endif 5968 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5969 if (arm_cache_prefer_mask != 0) { 5970 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 5971 } else { 5972 #endif 5973 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 5974 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5975 } 5976 #endif 5977 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5978 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5979 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5980 5981 #ifdef VERBOSE_INIT_ARM 5982 printf("l1pt "); 5983 #endif 5984 /* 5985 * Scan the L1 translation table created by initarm() and create 5986 * the required metadata for all valid mappings found in it. 5987 */ 5988 for (size_t l1slot = 0; 5989 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 5990 l1slot++) { 5991 pd_entry_t pde = l1pt[l1slot]; 5992 5993 /* 5994 * We're only interested in Coarse mappings. 5995 * pmap_extract() can deal with section mappings without 5996 * recourse to checking L2 metadata. 5997 */ 5998 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5999 continue; 6000 6001 /* 6002 * Lookup the KVA of this L2 descriptor table 6003 */ 6004 pa = l1pte_pa(pde); 6005 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6006 if (ptep == NULL) { 6007 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6008 (u_int)l1slot << L1_S_SHIFT, pa); 6009 } 6010 6011 /* 6012 * Fetch the associated L2 metadata structure. 6013 * Allocate a new one if necessary. 6014 */ 6015 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6016 if (l2next == PMAP_STATIC_L2_SIZE) 6017 panic("pmap_bootstrap: out of static L2s"); 6018 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6019 } 6020 6021 /* 6022 * One more L1 slot tracked... 6023 */ 6024 l2->l2_occupancy++; 6025 6026 /* 6027 * Fill in the details of the L2 descriptor in the 6028 * appropriate bucket. 6029 */ 6030 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6031 l2b->l2b_kva = ptep; 6032 l2b->l2b_pa = pa; 6033 l2b->l2b_l1slot = l1slot; 6034 6035 /* 6036 * Establish an initial occupancy count for this descriptor 6037 */ 6038 for (l2idx = 0; 6039 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6040 l2idx++) { 6041 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6042 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 6043 } 6044 } 6045 6046 /* 6047 * Make sure the descriptor itself has the correct cache mode. 6048 * If not, fix it, but whine about the problem. Port-meisters 6049 * should consider this a clue to fix up their initarm() 6050 * function. :) 6051 */ 6052 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6053 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6054 "L2 pte @ %p\n", ptep); 6055 } 6056 } 6057 6058 #ifdef VERBOSE_INIT_ARM 6059 printf("cache(l1pt) "); 6060 #endif 6061 /* 6062 * Ensure the primary (kernel) L1 has the correct cache mode for 6063 * a page table. Bitch if it is not correctly set. 6064 */ 6065 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6066 L1_TABLE_SIZE / L2_S_SIZE)) { 6067 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6068 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6069 } 6070 6071 #ifdef PMAP_CACHE_VIVT 6072 cpu_dcache_wbinv_all(); 6073 cpu_tlb_flushID(); 6074 cpu_cpwait(); 6075 #endif 6076 6077 /* 6078 * now we allocate the "special" VAs which are used for tmp mappings 6079 * by the pmap (and other modules). we allocate the VAs by advancing 6080 * virtual_avail (note that there are no pages mapped at these VAs). 6081 * 6082 * Managed KVM space start from wherever initarm() tells us. 6083 */ 6084 virtual_avail = vstart; 6085 virtual_end = vend; 6086 6087 #ifdef VERBOSE_INIT_ARM 6088 printf("specials "); 6089 #endif 6090 #ifdef PMAP_CACHE_VIPT 6091 /* 6092 * If we have a VIPT cache, we need one page/pte per possible alias 6093 * page so we won't violate cache aliasing rules. 6094 */ 6095 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6096 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6097 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6098 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6099 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6100 } 6101 #else 6102 nptes = PAGE_SIZE / L2_S_SIZE; 6103 #endif 6104 #ifdef MULTIPROCESSOR 6105 cnptes = nptes; 6106 nptes *= arm_cpu_max; 6107 #endif 6108 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6109 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6110 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6111 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6112 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6113 if (msgbufaddr == NULL) { 6114 pmap_alloc_specials(&virtual_avail, 6115 round_page(MSGBUFSIZE) / PAGE_SIZE, 6116 (void *)&msgbufaddr, NULL); 6117 } 6118 6119 /* 6120 * Allocate a range of kernel virtual address space to be used 6121 * for L2 descriptor tables and metadata allocation in 6122 * pmap_growkernel(). 6123 */ 6124 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6125 pmap_alloc_specials(&virtual_avail, 6126 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6127 &pmap_kernel_l2ptp_kva, NULL); 6128 6129 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6130 pmap_alloc_specials(&virtual_avail, 6131 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6132 &pmap_kernel_l2dtable_kva, NULL); 6133 6134 #ifndef ARM_MMU_EXTENDED 6135 /* 6136 * init the static-global locks and global pmap list. 6137 */ 6138 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6139 6140 /* 6141 * We can now initialise the first L1's metadata. 6142 */ 6143 SLIST_INIT(&l1_list); 6144 TAILQ_INIT(&l1_lru_list); 6145 pmap_init_l1(l1, l1pt); 6146 #endif /* ARM_MMU_EXTENDED */ 6147 6148 #ifndef ARM_HAS_VBAR 6149 /* Set up vector page L1 details, if necessary */ 6150 if (vector_page < KERNEL_BASE) { 6151 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6152 l2b = pmap_get_l2_bucket(pm, vector_page); 6153 KDASSERT(l2b != NULL); 6154 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6155 L1_C_DOM(pmap_domain(pm)); 6156 } else 6157 pm->pm_pl1vec = NULL; 6158 #endif 6159 6160 #ifdef VERBOSE_INIT_ARM 6161 printf("pools "); 6162 #endif 6163 /* 6164 * Initialize the pmap cache 6165 */ 6166 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6167 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6168 LIST_INIT(&pmap_pmaps); 6169 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6170 6171 /* 6172 * Initialize the pv pool. 6173 */ 6174 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6175 &pmap_bootstrap_pv_allocator, IPL_NONE); 6176 6177 /* 6178 * Initialize the L2 dtable pool and cache. 6179 */ 6180 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6181 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6182 6183 /* 6184 * Initialise the L2 descriptor table pool and cache 6185 */ 6186 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6187 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6188 pmap_l2ptp_ctor, NULL, NULL); 6189 6190 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6191 6192 cpu_dcache_wbinv_all(); 6193 } 6194 6195 static bool 6196 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6197 { 6198 #ifdef ARM_MMU_EXTENDED 6199 return false; 6200 #else 6201 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6202 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6203 return false; 6204 6205 const vaddr_t eva = va + nptes * PAGE_SIZE; 6206 int rv = 0; 6207 6208 while (va < eva) { 6209 /* 6210 * Make sure the descriptor itself has the correct cache mode 6211 */ 6212 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6213 pd_entry_t pde = *pdep; 6214 6215 if (l1pte_section_p(pde)) { 6216 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6217 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6218 *pdep = (pde & ~L1_S_CACHE_MASK) | 6219 pte_l1_s_cache_mode_pt; 6220 PDE_SYNC(pdep); 6221 cpu_dcache_wbinv_range((vaddr_t)pdep, 6222 sizeof(*pdep)); 6223 rv = 1; 6224 } 6225 return rv; 6226 if (pde & L1_S_V6_SUPER) { 6227 va = (va & -L1_SS_SIZE) + L1_SS_SIZE; 6228 } else { 6229 va = (va & -L1_S_SIZE) + L1_S_SIZE; 6230 } 6231 continue; 6232 } 6233 vaddr_t pa = l1pte_pa(pde); 6234 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6235 if (ptep == NULL) 6236 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6237 6238 ptep += l2pte_index(va); 6239 const pt_entry_t opte = *ptep; 6240 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6241 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6242 | pte_l2_s_cache_mode_pt; 6243 l2pte_set(ptep, npte, opte); 6244 PTE_SYNC(ptep); 6245 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6246 rv = 1; 6247 } 6248 va += PAGE_SIZE; 6249 } 6250 6251 return (rv); 6252 #endif 6253 } 6254 6255 static void 6256 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6257 { 6258 vaddr_t va = *availp; 6259 struct l2_bucket *l2b; 6260 6261 if (ptep) { 6262 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6263 if (l2b == NULL) 6264 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6265 6266 if (ptep) 6267 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6268 } 6269 6270 *vap = va; 6271 *availp = va + (PAGE_SIZE * pages); 6272 } 6273 6274 void 6275 pmap_init(void) 6276 { 6277 6278 /* 6279 * Set the available memory vars - These do not map to real memory 6280 * addresses and cannot as the physical memory is fragmented. 6281 * They are used by ps for %mem calculations. 6282 * One could argue whether this should be the entire memory or just 6283 * the memory that is useable in a user process. 6284 */ 6285 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6286 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6287 6288 /* 6289 * Now we need to free enough pv_entry structures to allow us to get 6290 * the kmem_map/kmem_object allocated and inited (done after this 6291 * function is finished). to do this we allocate one bootstrap page out 6292 * of kernel_map and use it to provide an initial pool of pv_entry 6293 * structures. we never free this page. 6294 */ 6295 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6296 6297 #ifdef ARM_MMU_EXTENDED 6298 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6299 #endif 6300 6301 pmap_initialized = true; 6302 } 6303 6304 static vaddr_t last_bootstrap_page = 0; 6305 static void *free_bootstrap_pages = NULL; 6306 6307 static void * 6308 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6309 { 6310 extern void *pool_page_alloc(struct pool *, int); 6311 vaddr_t new_page; 6312 void *rv; 6313 6314 if (pmap_initialized) 6315 return (pool_page_alloc(pp, flags)); 6316 6317 if (free_bootstrap_pages) { 6318 rv = free_bootstrap_pages; 6319 free_bootstrap_pages = *((void **)rv); 6320 return (rv); 6321 } 6322 6323 KASSERT(kernel_map != NULL); 6324 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6325 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6326 6327 KASSERT(new_page > last_bootstrap_page); 6328 last_bootstrap_page = new_page; 6329 return ((void *)new_page); 6330 } 6331 6332 static void 6333 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6334 { 6335 extern void pool_page_free(struct pool *, void *); 6336 6337 if ((vaddr_t)v <= last_bootstrap_page) { 6338 *((void **)v) = free_bootstrap_pages; 6339 free_bootstrap_pages = v; 6340 return; 6341 } 6342 6343 if (pmap_initialized) { 6344 pool_page_free(pp, v); 6345 return; 6346 } 6347 } 6348 6349 /* 6350 * pmap_postinit() 6351 * 6352 * This routine is called after the vm and kmem subsystems have been 6353 * initialised. This allows the pmap code to perform any initialisation 6354 * that can only be done one the memory allocation is in place. 6355 */ 6356 void 6357 pmap_postinit(void) 6358 { 6359 #ifndef ARM_MMU_EXTENDED 6360 extern paddr_t physical_start, physical_end; 6361 struct l1_ttable *l1; 6362 struct pglist plist; 6363 struct vm_page *m; 6364 pd_entry_t *pdep; 6365 vaddr_t va, eva; 6366 u_int loop, needed; 6367 int error; 6368 #endif 6369 6370 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6371 pool_cache_setlowat(&pmap_l2dtable_cache, 6372 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6373 6374 #ifndef ARM_MMU_EXTENDED 6375 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6376 needed -= 1; 6377 6378 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6379 6380 for (loop = 0; loop < needed; loop++, l1++) { 6381 /* Allocate a L1 page table */ 6382 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6383 if (va == 0) 6384 panic("Cannot allocate L1 KVM"); 6385 6386 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6387 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6388 if (error) 6389 panic("Cannot allocate L1 physical pages"); 6390 6391 m = TAILQ_FIRST(&plist); 6392 eva = va + L1_TABLE_SIZE; 6393 pdep = (pd_entry_t *)va; 6394 6395 while (m && va < eva) { 6396 paddr_t pa = VM_PAGE_TO_PHYS(m); 6397 6398 pmap_kenter_pa(va, pa, 6399 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6400 6401 va += PAGE_SIZE; 6402 m = TAILQ_NEXT(m, pageq.queue); 6403 } 6404 6405 #ifdef DIAGNOSTIC 6406 if (m) 6407 panic("pmap_alloc_l1pt: pglist not empty"); 6408 #endif /* DIAGNOSTIC */ 6409 6410 pmap_init_l1(l1, pdep); 6411 } 6412 6413 #ifdef DEBUG 6414 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6415 needed); 6416 #endif 6417 #endif /* !ARM_MMU_EXTENDED */ 6418 } 6419 6420 /* 6421 * Note that the following routines are used by board-specific initialisation 6422 * code to configure the initial kernel page tables. 6423 * 6424 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6425 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6426 * behaviour of the old pmap, and provides an easy migration path for 6427 * initial bring-up of the new pmap on existing ports. Fortunately, 6428 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6429 * will be deprecated. 6430 * 6431 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6432 * tables. 6433 */ 6434 6435 /* 6436 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6437 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6438 * find them as necessary. 6439 * 6440 * Note that the data on this list MUST remain valid after initarm() returns, 6441 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6442 */ 6443 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6444 6445 static vaddr_t 6446 kernel_pt_lookup(paddr_t pa) 6447 { 6448 pv_addr_t *pv; 6449 6450 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6451 if (pv->pv_pa == (pa & ~PGOFSET)) 6452 return (pv->pv_va | (pa & PGOFSET)); 6453 } 6454 return (0); 6455 } 6456 6457 /* 6458 * pmap_map_section: 6459 * 6460 * Create a single section mapping. 6461 */ 6462 void 6463 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6464 { 6465 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6466 const size_t l1slot = l1pte_index(va); 6467 pd_entry_t fl; 6468 6469 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6470 6471 switch (cache) { 6472 case PTE_NOCACHE: 6473 default: 6474 fl = 0; 6475 break; 6476 6477 case PTE_CACHE: 6478 fl = pte_l1_s_cache_mode; 6479 break; 6480 6481 case PTE_PAGETABLE: 6482 fl = pte_l1_s_cache_mode_pt; 6483 break; 6484 } 6485 6486 const pd_entry_t npde = L1_S_PROTO | pa | 6487 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6488 l1pte_setone(pdep + l1slot, npde); 6489 PDE_SYNC(pdep + l1slot); 6490 } 6491 6492 /* 6493 * pmap_map_entry: 6494 * 6495 * Create a single page mapping. 6496 */ 6497 void 6498 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6499 { 6500 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6501 const size_t l1slot = l1pte_index(va); 6502 pt_entry_t npte; 6503 pt_entry_t *ptep; 6504 6505 KASSERT(((va | pa) & PGOFSET) == 0); 6506 6507 switch (cache) { 6508 case PTE_NOCACHE: 6509 default: 6510 npte = 0; 6511 break; 6512 6513 case PTE_CACHE: 6514 npte = pte_l2_s_cache_mode; 6515 break; 6516 6517 case PTE_PAGETABLE: 6518 npte = pte_l2_s_cache_mode_pt; 6519 break; 6520 } 6521 6522 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6523 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6524 6525 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6526 if (ptep == NULL) 6527 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6528 6529 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6530 #ifdef ARM_MMU_EXTENDED 6531 if (prot & VM_PROT_EXECUTE) { 6532 npte &= ~L2_XS_XN; 6533 } 6534 #endif 6535 ptep += l2pte_index(va); 6536 l2pte_set(ptep, npte, 0); 6537 PTE_SYNC(ptep); 6538 } 6539 6540 /* 6541 * pmap_link_l2pt: 6542 * 6543 * Link the L2 page table specified by "l2pv" into the L1 6544 * page table at the slot for "va". 6545 */ 6546 void 6547 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6548 { 6549 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6550 6551 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6552 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6553 6554 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6555 | l2pv->pv_pa; 6556 6557 l1pte_set(pdep, npde); 6558 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6559 6560 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6561 } 6562 6563 /* 6564 * pmap_map_chunk: 6565 * 6566 * Map a chunk of memory using the most efficient mappings 6567 * possible (section, large page, small page) into the 6568 * provided L1 and L2 tables at the specified virtual address. 6569 */ 6570 vsize_t 6571 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6572 int prot, int cache) 6573 { 6574 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6575 pt_entry_t f1, f2s, f2l; 6576 vsize_t resid; 6577 6578 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6579 6580 if (l1pt == 0) 6581 panic("pmap_map_chunk: no L1 table provided"); 6582 6583 #ifdef VERBOSE_INIT_ARM 6584 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6585 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6586 #endif 6587 6588 switch (cache) { 6589 case PTE_NOCACHE: 6590 default: 6591 f1 = 0; 6592 f2l = 0; 6593 f2s = 0; 6594 break; 6595 6596 case PTE_CACHE: 6597 f1 = pte_l1_s_cache_mode; 6598 f2l = pte_l2_l_cache_mode; 6599 f2s = pte_l2_s_cache_mode; 6600 break; 6601 6602 case PTE_PAGETABLE: 6603 f1 = pte_l1_s_cache_mode_pt; 6604 f2l = pte_l2_l_cache_mode_pt; 6605 f2s = pte_l2_s_cache_mode_pt; 6606 break; 6607 } 6608 6609 size = resid; 6610 6611 while (resid > 0) { 6612 const size_t l1slot = l1pte_index(va); 6613 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6614 /* See if we can use a supersection mapping. */ 6615 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6616 /* Supersection are always domain 0 */ 6617 const pd_entry_t npde = L1_SS_PROTO | pa 6618 #ifdef ARM_MMU_EXTENDED_XXX 6619 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6620 #endif 6621 #ifdef ARM_MMU_EXTENDED 6622 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6623 #endif 6624 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6625 #ifdef VERBOSE_INIT_ARM 6626 printf("sS"); 6627 #endif 6628 l1pte_set(&pdep[l1slot], npde); 6629 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6630 va += L1_SS_SIZE; 6631 pa += L1_SS_SIZE; 6632 resid -= L1_SS_SIZE; 6633 continue; 6634 } 6635 #endif 6636 /* See if we can use a section mapping. */ 6637 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6638 const pd_entry_t npde = L1_S_PROTO | pa 6639 #ifdef ARM_MMU_EXTENDED_XXX 6640 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6641 #endif 6642 #ifdef ARM_MMU_EXTENDED 6643 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6644 #endif 6645 | L1_S_PROT(PTE_KERNEL, prot) | f1 6646 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6647 #ifdef VERBOSE_INIT_ARM 6648 printf("S"); 6649 #endif 6650 l1pte_set(&pdep[l1slot], npde); 6651 PDE_SYNC(&pdep[l1slot]); 6652 va += L1_S_SIZE; 6653 pa += L1_S_SIZE; 6654 resid -= L1_S_SIZE; 6655 continue; 6656 } 6657 6658 /* 6659 * Ok, we're going to use an L2 table. Make sure 6660 * one is actually in the corresponding L1 slot 6661 * for the current VA. 6662 */ 6663 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6664 panic("%s: no L2 table for VA %#lx", __func__, va); 6665 6666 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6667 if (ptep == NULL) 6668 panic("%s: can't find L2 table for VA %#lx", __func__, 6669 va); 6670 6671 ptep += l2pte_index(va); 6672 6673 /* See if we can use a L2 large page mapping. */ 6674 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6675 const pt_entry_t npte = L2_L_PROTO | pa 6676 #ifdef ARM_MMU_EXTENDED_XXX 6677 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6678 #endif 6679 #ifdef ARM_MMU_EXTENDED 6680 | (va & 0x80000000 ? 0 : L2_XS_nG) 6681 #endif 6682 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6683 #ifdef VERBOSE_INIT_ARM 6684 printf("L"); 6685 #endif 6686 l2pte_set(ptep, npte, 0); 6687 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6688 va += L2_L_SIZE; 6689 pa += L2_L_SIZE; 6690 resid -= L2_L_SIZE; 6691 continue; 6692 } 6693 6694 /* Use a small page mapping. */ 6695 #ifdef VERBOSE_INIT_ARM 6696 printf("P"); 6697 #endif 6698 const pt_entry_t npte = L2_S_PROTO | pa 6699 #ifdef ARM_MMU_EXTENDED_XXX 6700 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6701 #endif 6702 #ifdef ARM_MMU_EXTENDED 6703 | (va & 0x80000000 ? 0 : L2_XS_nG) 6704 #endif 6705 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6706 l2pte_set(ptep, npte, 0); 6707 PTE_SYNC(ptep); 6708 va += PAGE_SIZE; 6709 pa += PAGE_SIZE; 6710 resid -= PAGE_SIZE; 6711 } 6712 #ifdef VERBOSE_INIT_ARM 6713 printf("\n"); 6714 #endif 6715 return (size); 6716 } 6717 6718 /********************** Static device map routines ***************************/ 6719 6720 static const struct pmap_devmap *pmap_devmap_table; 6721 6722 /* 6723 * Register the devmap table. This is provided in case early console 6724 * initialization needs to register mappings created by bootstrap code 6725 * before pmap_devmap_bootstrap() is called. 6726 */ 6727 void 6728 pmap_devmap_register(const struct pmap_devmap *table) 6729 { 6730 6731 pmap_devmap_table = table; 6732 } 6733 6734 /* 6735 * Map all of the static regions in the devmap table, and remember 6736 * the devmap table so other parts of the kernel can look up entries 6737 * later. 6738 */ 6739 void 6740 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6741 { 6742 int i; 6743 6744 pmap_devmap_table = table; 6745 6746 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6747 #ifdef VERBOSE_INIT_ARM 6748 printf("devmap: %08lx -> %08lx @ %08lx\n", 6749 pmap_devmap_table[i].pd_pa, 6750 pmap_devmap_table[i].pd_pa + 6751 pmap_devmap_table[i].pd_size - 1, 6752 pmap_devmap_table[i].pd_va); 6753 #endif 6754 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6755 pmap_devmap_table[i].pd_pa, 6756 pmap_devmap_table[i].pd_size, 6757 pmap_devmap_table[i].pd_prot, 6758 pmap_devmap_table[i].pd_cache); 6759 } 6760 } 6761 6762 const struct pmap_devmap * 6763 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6764 { 6765 uint64_t endpa; 6766 int i; 6767 6768 if (pmap_devmap_table == NULL) 6769 return (NULL); 6770 6771 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6772 6773 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6774 if (pa >= pmap_devmap_table[i].pd_pa && 6775 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6776 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6777 return (&pmap_devmap_table[i]); 6778 } 6779 6780 return (NULL); 6781 } 6782 6783 const struct pmap_devmap * 6784 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6785 { 6786 int i; 6787 6788 if (pmap_devmap_table == NULL) 6789 return (NULL); 6790 6791 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6792 if (va >= pmap_devmap_table[i].pd_va && 6793 va + size - 1 <= pmap_devmap_table[i].pd_va + 6794 pmap_devmap_table[i].pd_size - 1) 6795 return (&pmap_devmap_table[i]); 6796 } 6797 6798 return (NULL); 6799 } 6800 6801 /********************** PTE initialization routines **************************/ 6802 6803 /* 6804 * These routines are called when the CPU type is identified to set up 6805 * the PTE prototypes, cache modes, etc. 6806 * 6807 * The variables are always here, just in case modules need to reference 6808 * them (though, they shouldn't). 6809 */ 6810 6811 pt_entry_t pte_l1_s_cache_mode; 6812 pt_entry_t pte_l1_s_wc_mode; 6813 pt_entry_t pte_l1_s_cache_mode_pt; 6814 pt_entry_t pte_l1_s_cache_mask; 6815 6816 pt_entry_t pte_l2_l_cache_mode; 6817 pt_entry_t pte_l2_l_wc_mode; 6818 pt_entry_t pte_l2_l_cache_mode_pt; 6819 pt_entry_t pte_l2_l_cache_mask; 6820 6821 pt_entry_t pte_l2_s_cache_mode; 6822 pt_entry_t pte_l2_s_wc_mode; 6823 pt_entry_t pte_l2_s_cache_mode_pt; 6824 pt_entry_t pte_l2_s_cache_mask; 6825 6826 pt_entry_t pte_l1_s_prot_u; 6827 pt_entry_t pte_l1_s_prot_w; 6828 pt_entry_t pte_l1_s_prot_ro; 6829 pt_entry_t pte_l1_s_prot_mask; 6830 6831 pt_entry_t pte_l2_s_prot_u; 6832 pt_entry_t pte_l2_s_prot_w; 6833 pt_entry_t pte_l2_s_prot_ro; 6834 pt_entry_t pte_l2_s_prot_mask; 6835 6836 pt_entry_t pte_l2_l_prot_u; 6837 pt_entry_t pte_l2_l_prot_w; 6838 pt_entry_t pte_l2_l_prot_ro; 6839 pt_entry_t pte_l2_l_prot_mask; 6840 6841 pt_entry_t pte_l1_ss_proto; 6842 pt_entry_t pte_l1_s_proto; 6843 pt_entry_t pte_l1_c_proto; 6844 pt_entry_t pte_l2_s_proto; 6845 6846 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6847 void (*pmap_zero_page_func)(paddr_t); 6848 6849 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6850 void 6851 pmap_pte_init_generic(void) 6852 { 6853 6854 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6855 pte_l1_s_wc_mode = L1_S_B; 6856 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6857 6858 pte_l2_l_cache_mode = L2_B|L2_C; 6859 pte_l2_l_wc_mode = L2_B; 6860 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6861 6862 pte_l2_s_cache_mode = L2_B|L2_C; 6863 pte_l2_s_wc_mode = L2_B; 6864 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6865 6866 /* 6867 * If we have a write-through cache, set B and C. If 6868 * we have a write-back cache, then we assume setting 6869 * only C will make those pages write-through (except for those 6870 * Cortex CPUs which can read the L1 caches). 6871 */ 6872 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6873 #if ARM_MMU_V7 > 0 6874 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6875 #endif 6876 #if ARM_MMU_V6 > 0 6877 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6878 #endif 6879 || false) { 6880 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6881 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6882 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6883 } else { 6884 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6885 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6886 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6887 } 6888 6889 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6890 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6891 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6892 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6893 6894 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6895 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6896 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6897 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6898 6899 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6900 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6901 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6902 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6903 6904 pte_l1_ss_proto = L1_SS_PROTO_generic; 6905 pte_l1_s_proto = L1_S_PROTO_generic; 6906 pte_l1_c_proto = L1_C_PROTO_generic; 6907 pte_l2_s_proto = L2_S_PROTO_generic; 6908 6909 pmap_copy_page_func = pmap_copy_page_generic; 6910 pmap_zero_page_func = pmap_zero_page_generic; 6911 } 6912 6913 #if defined(CPU_ARM8) 6914 void 6915 pmap_pte_init_arm8(void) 6916 { 6917 6918 /* 6919 * ARM8 is compatible with generic, but we need to use 6920 * the page tables uncached. 6921 */ 6922 pmap_pte_init_generic(); 6923 6924 pte_l1_s_cache_mode_pt = 0; 6925 pte_l2_l_cache_mode_pt = 0; 6926 pte_l2_s_cache_mode_pt = 0; 6927 } 6928 #endif /* CPU_ARM8 */ 6929 6930 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6931 void 6932 pmap_pte_init_arm9(void) 6933 { 6934 6935 /* 6936 * ARM9 is compatible with generic, but we want to use 6937 * write-through caching for now. 6938 */ 6939 pmap_pte_init_generic(); 6940 6941 pte_l1_s_cache_mode = L1_S_C; 6942 pte_l2_l_cache_mode = L2_C; 6943 pte_l2_s_cache_mode = L2_C; 6944 6945 pte_l1_s_wc_mode = L1_S_B; 6946 pte_l2_l_wc_mode = L2_B; 6947 pte_l2_s_wc_mode = L2_B; 6948 6949 pte_l1_s_cache_mode_pt = L1_S_C; 6950 pte_l2_l_cache_mode_pt = L2_C; 6951 pte_l2_s_cache_mode_pt = L2_C; 6952 } 6953 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6954 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6955 6956 #if defined(CPU_ARM10) 6957 void 6958 pmap_pte_init_arm10(void) 6959 { 6960 6961 /* 6962 * ARM10 is compatible with generic, but we want to use 6963 * write-through caching for now. 6964 */ 6965 pmap_pte_init_generic(); 6966 6967 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6968 pte_l2_l_cache_mode = L2_B | L2_C; 6969 pte_l2_s_cache_mode = L2_B | L2_C; 6970 6971 pte_l1_s_cache_mode = L1_S_B; 6972 pte_l2_l_cache_mode = L2_B; 6973 pte_l2_s_cache_mode = L2_B; 6974 6975 pte_l1_s_cache_mode_pt = L1_S_C; 6976 pte_l2_l_cache_mode_pt = L2_C; 6977 pte_l2_s_cache_mode_pt = L2_C; 6978 6979 } 6980 #endif /* CPU_ARM10 */ 6981 6982 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6983 void 6984 pmap_pte_init_arm11(void) 6985 { 6986 6987 /* 6988 * ARM11 is compatible with generic, but we want to use 6989 * write-through caching for now. 6990 */ 6991 pmap_pte_init_generic(); 6992 6993 pte_l1_s_cache_mode = L1_S_C; 6994 pte_l2_l_cache_mode = L2_C; 6995 pte_l2_s_cache_mode = L2_C; 6996 6997 pte_l1_s_wc_mode = L1_S_B; 6998 pte_l2_l_wc_mode = L2_B; 6999 pte_l2_s_wc_mode = L2_B; 7000 7001 pte_l1_s_cache_mode_pt = L1_S_C; 7002 pte_l2_l_cache_mode_pt = L2_C; 7003 pte_l2_s_cache_mode_pt = L2_C; 7004 } 7005 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7006 7007 #if ARM_MMU_SA1 == 1 7008 void 7009 pmap_pte_init_sa1(void) 7010 { 7011 7012 /* 7013 * The StrongARM SA-1 cache does not have a write-through 7014 * mode. So, do the generic initialization, then reset 7015 * the page table cache mode to B=1,C=1, and note that 7016 * the PTEs need to be sync'd. 7017 */ 7018 pmap_pte_init_generic(); 7019 7020 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7021 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7022 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7023 7024 pmap_needs_pte_sync = 1; 7025 } 7026 #endif /* ARM_MMU_SA1 == 1*/ 7027 7028 #if ARM_MMU_XSCALE == 1 7029 #if (ARM_NMMUS > 1) 7030 static u_int xscale_use_minidata; 7031 #endif 7032 7033 void 7034 pmap_pte_init_xscale(void) 7035 { 7036 uint32_t auxctl; 7037 int write_through = 0; 7038 7039 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7040 pte_l1_s_wc_mode = L1_S_B; 7041 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7042 7043 pte_l2_l_cache_mode = L2_B|L2_C; 7044 pte_l2_l_wc_mode = L2_B; 7045 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7046 7047 pte_l2_s_cache_mode = L2_B|L2_C; 7048 pte_l2_s_wc_mode = L2_B; 7049 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7050 7051 pte_l1_s_cache_mode_pt = L1_S_C; 7052 pte_l2_l_cache_mode_pt = L2_C; 7053 pte_l2_s_cache_mode_pt = L2_C; 7054 7055 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7056 /* 7057 * The XScale core has an enhanced mode where writes that 7058 * miss the cache cause a cache line to be allocated. This 7059 * is significantly faster than the traditional, write-through 7060 * behavior of this case. 7061 */ 7062 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7063 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7064 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7065 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7066 7067 #ifdef XSCALE_CACHE_WRITE_THROUGH 7068 /* 7069 * Some versions of the XScale core have various bugs in 7070 * their cache units, the work-around for which is to run 7071 * the cache in write-through mode. Unfortunately, this 7072 * has a major (negative) impact on performance. So, we 7073 * go ahead and run fast-and-loose, in the hopes that we 7074 * don't line up the planets in a way that will trip the 7075 * bugs. 7076 * 7077 * However, we give you the option to be slow-but-correct. 7078 */ 7079 write_through = 1; 7080 #elif defined(XSCALE_CACHE_WRITE_BACK) 7081 /* force write back cache mode */ 7082 write_through = 0; 7083 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7084 /* 7085 * Intel PXA2[15]0 processors are known to have a bug in 7086 * write-back cache on revision 4 and earlier (stepping 7087 * A[01] and B[012]). Fixed for C0 and later. 7088 */ 7089 { 7090 uint32_t id, type; 7091 7092 id = cpufunc_id(); 7093 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7094 7095 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7096 if ((id & CPU_ID_REVISION_MASK) < 5) { 7097 /* write through for stepping A0-1 and B0-2 */ 7098 write_through = 1; 7099 } 7100 } 7101 } 7102 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7103 7104 if (write_through) { 7105 pte_l1_s_cache_mode = L1_S_C; 7106 pte_l2_l_cache_mode = L2_C; 7107 pte_l2_s_cache_mode = L2_C; 7108 } 7109 7110 #if (ARM_NMMUS > 1) 7111 xscale_use_minidata = 1; 7112 #endif 7113 7114 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7115 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7116 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7117 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7118 7119 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7120 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7121 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7122 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7123 7124 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7125 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7126 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7127 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7128 7129 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7130 pte_l1_s_proto = L1_S_PROTO_xscale; 7131 pte_l1_c_proto = L1_C_PROTO_xscale; 7132 pte_l2_s_proto = L2_S_PROTO_xscale; 7133 7134 pmap_copy_page_func = pmap_copy_page_xscale; 7135 pmap_zero_page_func = pmap_zero_page_xscale; 7136 7137 /* 7138 * Disable ECC protection of page table access, for now. 7139 */ 7140 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7141 auxctl &= ~XSCALE_AUXCTL_P; 7142 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7143 } 7144 7145 /* 7146 * xscale_setup_minidata: 7147 * 7148 * Set up the mini-data cache clean area. We require the 7149 * caller to allocate the right amount of physically and 7150 * virtually contiguous space. 7151 */ 7152 void 7153 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7154 { 7155 extern vaddr_t xscale_minidata_clean_addr; 7156 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7157 pd_entry_t *pde = (pd_entry_t *) l1pt; 7158 vsize_t size; 7159 uint32_t auxctl; 7160 7161 xscale_minidata_clean_addr = va; 7162 7163 /* Round it to page size. */ 7164 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7165 7166 for (; size != 0; 7167 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7168 const size_t l1slot = l1pte_index(va); 7169 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7170 if (ptep == NULL) 7171 panic("xscale_setup_minidata: can't find L2 table for " 7172 "VA 0x%08lx", va); 7173 7174 ptep += l2pte_index(va); 7175 pt_entry_t opte = *ptep; 7176 l2pte_set(ptep, 7177 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7178 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7179 } 7180 7181 /* 7182 * Configure the mini-data cache for write-back with 7183 * read/write-allocate. 7184 * 7185 * NOTE: In order to reconfigure the mini-data cache, we must 7186 * make sure it contains no valid data! In order to do that, 7187 * we must issue a global data cache invalidate command! 7188 * 7189 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7190 * THIS IS VERY IMPORTANT! 7191 */ 7192 7193 /* Invalidate data and mini-data. */ 7194 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7195 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7196 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7197 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7198 } 7199 7200 /* 7201 * Change the PTEs for the specified kernel mappings such that they 7202 * will use the mini data cache instead of the main data cache. 7203 */ 7204 void 7205 pmap_uarea(vaddr_t va) 7206 { 7207 vaddr_t next_bucket, eva; 7208 7209 #if (ARM_NMMUS > 1) 7210 if (xscale_use_minidata == 0) 7211 return; 7212 #endif 7213 7214 eva = va + USPACE; 7215 7216 while (va < eva) { 7217 next_bucket = L2_NEXT_BUCKET_VA(va); 7218 if (next_bucket > eva) 7219 next_bucket = eva; 7220 7221 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7222 KDASSERT(l2b != NULL); 7223 7224 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7225 pt_entry_t *ptep = sptep; 7226 7227 while (va < next_bucket) { 7228 const pt_entry_t opte = *ptep; 7229 if (!l2pte_minidata_p(opte)) { 7230 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7231 cpu_tlb_flushD_SE(va); 7232 l2pte_set(ptep, opte & ~L2_B, opte); 7233 } 7234 ptep += PAGE_SIZE / L2_S_SIZE; 7235 va += PAGE_SIZE; 7236 } 7237 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7238 } 7239 cpu_cpwait(); 7240 } 7241 #endif /* ARM_MMU_XSCALE == 1 */ 7242 7243 7244 #if defined(CPU_ARM11MPCORE) 7245 7246 void 7247 pmap_pte_init_arm11mpcore(void) 7248 { 7249 7250 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7251 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7252 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7253 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7254 /* use extended small page (without APn, with TEX) */ 7255 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7256 #else 7257 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7258 #endif 7259 7260 /* write-back, write-allocate */ 7261 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7262 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7263 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7264 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7265 #else 7266 /* no TEX. read-allocate */ 7267 pte_l2_s_cache_mode = L2_C | L2_B; 7268 #endif 7269 /* 7270 * write-back, write-allocate for page tables. 7271 */ 7272 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7273 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7274 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7275 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7276 #else 7277 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7278 #endif 7279 7280 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7281 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7282 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7283 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7284 7285 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7286 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7287 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7288 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7289 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7290 7291 #else 7292 /* with AP[0..3] */ 7293 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7294 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7295 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7296 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7297 #endif 7298 7299 #ifdef ARM11MPCORE_COMPAT_MMU 7300 /* with AP[0..3] */ 7301 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7302 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7303 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7304 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7305 7306 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7307 pte_l1_s_proto = L1_S_PROTO_armv6; 7308 pte_l1_c_proto = L1_C_PROTO_armv6; 7309 pte_l2_s_proto = L2_S_PROTO_armv6c; 7310 #else 7311 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7312 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7313 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7314 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7315 7316 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7317 pte_l1_s_proto = L1_S_PROTO_armv6; 7318 pte_l1_c_proto = L1_C_PROTO_armv6; 7319 pte_l2_s_proto = L2_S_PROTO_armv6n; 7320 #endif 7321 7322 pmap_copy_page_func = pmap_copy_page_generic; 7323 pmap_zero_page_func = pmap_zero_page_generic; 7324 pmap_needs_pte_sync = 1; 7325 } 7326 #endif /* CPU_ARM11MPCORE */ 7327 7328 7329 #if ARM_MMU_V7 == 1 7330 void 7331 pmap_pte_init_armv7(void) 7332 { 7333 /* 7334 * The ARMv7-A MMU is mostly compatible with generic. If the 7335 * AP field is zero, that now means "no access" rather than 7336 * read-only. The prototypes are a little different because of 7337 * the XN bit. 7338 */ 7339 pmap_pte_init_generic(); 7340 7341 pmap_needs_pte_sync = 1; 7342 7343 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7344 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7345 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7346 7347 /* 7348 * If the core support coherent walk then updates to translation tables 7349 * do not require a clean to the point of unification to ensure 7350 * visibility by subsequent translation table walks. That means we can 7351 * map everything shareable and cached and the right thing will happen. 7352 */ 7353 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7354 pmap_needs_pte_sync = 0; 7355 7356 /* 7357 * write-back, no write-allocate, shareable for normal pages. 7358 */ 7359 pte_l1_s_cache_mode |= L1_S_V6_S; 7360 pte_l2_l_cache_mode |= L2_XS_S; 7361 pte_l2_s_cache_mode |= L2_XS_S; 7362 } 7363 7364 /* 7365 * Page tables are just all other memory. We can use write-back since 7366 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7367 */ 7368 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7369 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7370 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7371 7372 /* 7373 * Check the Memory Model Features to see if this CPU supports 7374 * the TLBIASID coproc op. 7375 */ 7376 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7377 arm_has_tlbiasid_p = true; 7378 } 7379 7380 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7381 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7382 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7383 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7384 7385 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7386 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7387 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7388 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7389 7390 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7391 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7392 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7393 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7394 7395 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7396 pte_l1_s_proto = L1_S_PROTO_armv7; 7397 pte_l1_c_proto = L1_C_PROTO_armv7; 7398 pte_l2_s_proto = L2_S_PROTO_armv7; 7399 7400 } 7401 #endif /* ARM_MMU_V7 */ 7402 7403 /* 7404 * return the PA of the current L1 table, for use when handling a crash dump 7405 */ 7406 uint32_t 7407 pmap_kernel_L1_addr(void) 7408 { 7409 #ifdef ARM_MMU_EXTENDED 7410 return pmap_kernel()->pm_l1_pa; 7411 #else 7412 return pmap_kernel()->pm_l1->l1_physaddr; 7413 #endif 7414 } 7415 7416 #if defined(DDB) 7417 /* 7418 * A couple of ddb-callable functions for dumping pmaps 7419 */ 7420 void pmap_dump_all(void); 7421 void pmap_dump(pmap_t); 7422 7423 void 7424 pmap_dump_all(void) 7425 { 7426 pmap_t pm; 7427 7428 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7429 if (pm == pmap_kernel()) 7430 continue; 7431 pmap_dump(pm); 7432 printf("\n"); 7433 } 7434 } 7435 7436 static pt_entry_t ncptes[64]; 7437 static void pmap_dump_ncpg(pmap_t); 7438 7439 void 7440 pmap_dump(pmap_t pm) 7441 { 7442 struct l2_dtable *l2; 7443 struct l2_bucket *l2b; 7444 pt_entry_t *ptep, pte; 7445 vaddr_t l2_va, l2b_va, va; 7446 int i, j, k, occ, rows = 0; 7447 7448 if (pm == pmap_kernel()) 7449 printf("pmap_kernel (%p): ", pm); 7450 else 7451 printf("user pmap (%p): ", pm); 7452 7453 #ifdef ARM_MMU_EXTENDED 7454 printf("l1 at %p\n", pmap_l1_kva(pm)); 7455 #else 7456 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7457 #endif 7458 7459 l2_va = 0; 7460 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7461 l2 = pm->pm_l2[i]; 7462 7463 if (l2 == NULL || l2->l2_occupancy == 0) 7464 continue; 7465 7466 l2b_va = l2_va; 7467 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7468 l2b = &l2->l2_bucket[j]; 7469 7470 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7471 continue; 7472 7473 ptep = l2b->l2b_kva; 7474 7475 for (k = 0; k < 256 && ptep[k] == 0; k++) 7476 ; 7477 7478 k &= ~63; 7479 occ = l2b->l2b_occupancy; 7480 va = l2b_va + (k * 4096); 7481 for (; k < 256; k++, va += 0x1000) { 7482 char ch = ' '; 7483 if ((k % 64) == 0) { 7484 if ((rows % 8) == 0) { 7485 printf( 7486 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7487 } 7488 printf("%08lx: ", va); 7489 } 7490 7491 ncptes[k & 63] = 0; 7492 pte = ptep[k]; 7493 if (pte == 0) { 7494 ch = '.'; 7495 } else { 7496 occ--; 7497 switch (pte & 0x0c) { 7498 case 0x00: 7499 ch = 'D'; /* No cache No buff */ 7500 break; 7501 case 0x04: 7502 ch = 'B'; /* No cache buff */ 7503 break; 7504 case 0x08: 7505 if (pte & 0x40) 7506 ch = 'm'; 7507 else 7508 ch = 'C'; /* Cache No buff */ 7509 break; 7510 case 0x0c: 7511 ch = 'F'; /* Cache Buff */ 7512 break; 7513 } 7514 7515 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7516 ch += 0x20; 7517 7518 if ((pte & 0xc) == 0) 7519 ncptes[k & 63] = pte; 7520 } 7521 7522 if ((k % 64) == 63) { 7523 rows++; 7524 printf("%c\n", ch); 7525 pmap_dump_ncpg(pm); 7526 if (occ == 0) 7527 break; 7528 } else 7529 printf("%c", ch); 7530 } 7531 } 7532 } 7533 } 7534 7535 static void 7536 pmap_dump_ncpg(pmap_t pm) 7537 { 7538 struct vm_page *pg; 7539 struct vm_page_md *md; 7540 struct pv_entry *pv; 7541 int i; 7542 7543 for (i = 0; i < 63; i++) { 7544 if (ncptes[i] == 0) 7545 continue; 7546 7547 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7548 if (pg == NULL) 7549 continue; 7550 md = VM_PAGE_TO_MD(pg); 7551 7552 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7553 VM_PAGE_TO_PHYS(pg), 7554 md->krw_mappings, md->kro_mappings, 7555 md->urw_mappings, md->uro_mappings); 7556 7557 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7558 printf(" %c va 0x%08lx, flags 0x%x\n", 7559 (pm == pv->pv_pmap) ? '*' : ' ', 7560 pv->pv_va, pv->pv_flags); 7561 } 7562 } 7563 } 7564 #endif 7565 7566 #ifdef PMAP_STEAL_MEMORY 7567 void 7568 pmap_boot_pageadd(pv_addr_t *newpv) 7569 { 7570 pv_addr_t *pv, *npv; 7571 7572 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7573 if (newpv->pv_pa < pv->pv_va) { 7574 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7575 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7576 newpv->pv_size += pv->pv_size; 7577 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7578 } 7579 pv = NULL; 7580 } else { 7581 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7582 pv = npv) { 7583 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7584 KASSERT(pv->pv_pa < newpv->pv_pa); 7585 if (newpv->pv_pa > npv->pv_pa) 7586 continue; 7587 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7588 pv->pv_size += newpv->pv_size; 7589 return; 7590 } 7591 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7592 break; 7593 newpv->pv_size += npv->pv_size; 7594 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7595 SLIST_REMOVE_AFTER(newpv, pv_list); 7596 return; 7597 } 7598 } 7599 } 7600 7601 if (pv) { 7602 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7603 } else { 7604 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7605 } 7606 } 7607 7608 void 7609 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7610 pv_addr_t *rpv) 7611 { 7612 pv_addr_t *pv, **pvp; 7613 struct vm_physseg *ps; 7614 size_t i; 7615 7616 KASSERT(amount & PGOFSET); 7617 KASSERT((mask & PGOFSET) == 0); 7618 KASSERT((match & PGOFSET) == 0); 7619 KASSERT(amount != 0); 7620 7621 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7622 (pv = *pvp) != NULL; 7623 pvp = &SLIST_NEXT(pv, pv_list)) { 7624 pv_addr_t *newpv; 7625 psize_t off; 7626 /* 7627 * If this entry is too small to satify the request... 7628 */ 7629 KASSERT(pv->pv_size > 0); 7630 if (pv->pv_size < amount) 7631 continue; 7632 7633 for (off = 0; off <= mask; off += PAGE_SIZE) { 7634 if (((pv->pv_pa + off) & mask) == match 7635 && off + amount <= pv->pv_size) 7636 break; 7637 } 7638 if (off > mask) 7639 continue; 7640 7641 rpv->pv_va = pv->pv_va + off; 7642 rpv->pv_pa = pv->pv_pa + off; 7643 rpv->pv_size = amount; 7644 pv->pv_size -= amount; 7645 if (pv->pv_size == 0) { 7646 KASSERT(off == 0); 7647 KASSERT((vaddr_t) pv == rpv->pv_va); 7648 *pvp = SLIST_NEXT(pv, pv_list); 7649 } else if (off == 0) { 7650 KASSERT((vaddr_t) pv == rpv->pv_va); 7651 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7652 *newpv = *pv; 7653 newpv->pv_pa += amount; 7654 newpv->pv_va += amount; 7655 *pvp = newpv; 7656 } else if (off < pv->pv_size) { 7657 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7658 *newpv = *pv; 7659 newpv->pv_size -= off; 7660 newpv->pv_pa += off + amount; 7661 newpv->pv_va += off + amount; 7662 7663 SLIST_NEXT(pv, pv_list) = newpv; 7664 pv->pv_size = off; 7665 } else { 7666 KASSERT((vaddr_t) pv != rpv->pv_va); 7667 } 7668 memset((void *)rpv->pv_va, 0, amount); 7669 return; 7670 } 7671 7672 if (vm_nphysseg == 0) 7673 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7674 7675 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7676 (pv = *pvp) != NULL; 7677 pvp = &SLIST_NEXT(pv, pv_list)) { 7678 if (SLIST_NEXT(pv, pv_list) == NULL) 7679 break; 7680 } 7681 KASSERT(mask == 0); 7682 for (i = 0; i < vm_nphysseg; i++) { 7683 ps = VM_PHYSMEM_PTR(i); 7684 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7685 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7686 rpv->pv_va = pv->pv_va; 7687 rpv->pv_pa = pv->pv_pa; 7688 rpv->pv_size = amount; 7689 *pvp = NULL; 7690 pmap_map_chunk(kernel_l1pt.pv_va, 7691 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7692 ptoa(ps->avail_start), 7693 amount - pv->pv_size, 7694 VM_PROT_READ|VM_PROT_WRITE, 7695 PTE_CACHE); 7696 ps->avail_start += atop(amount - pv->pv_size); 7697 /* 7698 * If we consumed the entire physseg, remove it. 7699 */ 7700 if (ps->avail_start == ps->avail_end) { 7701 for (--vm_nphysseg; i < vm_nphysseg; i++) 7702 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7703 } 7704 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7705 return; 7706 } 7707 } 7708 7709 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7710 } 7711 7712 vaddr_t 7713 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7714 { 7715 pv_addr_t pv; 7716 7717 pmap_boot_pagealloc(size, 0, 0, &pv); 7718 7719 return pv.pv_va; 7720 } 7721 #endif /* PMAP_STEAL_MEMORY */ 7722 7723 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7724 { 7725 sysctl_createv(clog, 0, NULL, NULL, 7726 CTLFLAG_PERMANENT, 7727 CTLTYPE_NODE, "machdep", NULL, 7728 NULL, 0, NULL, 0, 7729 CTL_MACHDEP, CTL_EOL); 7730 7731 sysctl_createv(clog, 0, NULL, NULL, 7732 CTLFLAG_PERMANENT, 7733 CTLTYPE_INT, "kmpages", 7734 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7735 NULL, 0, &pmap_kmpages, 0, 7736 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7737 } 7738 7739 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7740 struct vm_page * 7741 arm_pmap_alloc_poolpage(int flags) 7742 { 7743 /* 7744 * On some systems, only some pages may be "coherent" for dma and we 7745 * want to prefer those for pool pages (think mbufs) but fallback to 7746 * any page if none is available. But we can only fallback if we 7747 * aren't direct mapping memory or all of memory can be direct-mapped. 7748 * If that isn't true, pool changes can only come from direct-mapped 7749 * memory. 7750 */ 7751 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7752 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7753 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7754 (pmap_directbase < KERNEL_BASE 7755 ? UVM_PGA_STRAT_ONLY 7756 : UVM_PGA_STRAT_FALLBACK), 7757 #else 7758 UVM_PGA_STRAT_FALLBACK, 7759 #endif 7760 arm_poolpage_vmfreelist); 7761 } 7762 7763 return uvm_pagealloc(NULL, 0, NULL, flags); 7764 } 7765 #endif 7766 7767 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7768 void 7769 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7770 { 7771 /* nothing */ 7772 } 7773 7774 int 7775 pic_ipi_shootdown(void *arg) 7776 { 7777 #if PMAP_NEED_TLB_SHOOTDOWN 7778 pmap_tlb_shootdown_process() 7779 #endif 7780 return 1; 7781 } 7782 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7783 7784 7785 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7786 vaddr_t 7787 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7788 { 7789 bool ok = false; 7790 if (physical_start <= pa && pa < physical_end) { 7791 #ifdef ARM_MMU_EXTENDED 7792 const vaddr_t newva = pmap_directbase + pa - physical_start; 7793 if (newva >= KERNEL_BASE) { 7794 va = newva; 7795 ok = true; 7796 } 7797 #else 7798 va = KERNEL_BASE + pa - physical_start; 7799 ok = true; 7800 #endif 7801 } 7802 KASSERT(ok_p); 7803 *ok_p = ok; 7804 return va; 7805 } 7806 7807 vaddr_t 7808 pmap_map_poolpage(paddr_t pa) 7809 { 7810 bool ok __diagused; 7811 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7812 KASSERT(ok); 7813 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7814 if (arm_cache_prefer_mask != 0) { 7815 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7816 struct vn_page_md * const md = VM_PAGE_TO_MD(pg); 7817 pmap_acquire_page_lock(md); 7818 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7819 pmap_release_page_lock(md); 7820 } 7821 #endif 7822 return va; 7823 } 7824 7825 paddr_t 7826 pmap_unmap_poolpage(vaddr_t va) 7827 { 7828 KASSERT(va >= KERNEL_BASE); 7829 #if defined(ARM_MMU_EXTENDED) 7830 return va - pmap_directbase + physical_start; 7831 #else 7832 #ifdef PMAP_CACHE_VIVT 7833 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7834 #endif 7835 return va - KERNEL_BASE + physical_start; 7836 #endif 7837 } 7838 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7839
Indexes created Mon Sep 29 21:09:56 GMT 2025