pmap.c revision 1.291
1 /* $NetBSD: pmap.c,v 1.291 2014/04/22 14:20:03 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 //#include <arm/arm32/katelib.h> 218 219 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.291 2014/04/22 14:20:03 skrll Exp $"); 220 221 //#define PMAP_DEBUG 222 #ifdef PMAP_DEBUG 223 224 /* XXX need to get rid of all refs to this */ 225 int pmap_debug_level = 0; 226 227 /* 228 * for switching to potentially finer grained debugging 229 */ 230 #define PDB_FOLLOW 0x0001 231 #define PDB_INIT 0x0002 232 #define PDB_ENTER 0x0004 233 #define PDB_REMOVE 0x0008 234 #define PDB_CREATE 0x0010 235 #define PDB_PTPAGE 0x0020 236 #define PDB_GROWKERN 0x0040 237 #define PDB_BITS 0x0080 238 #define PDB_COLLECT 0x0100 239 #define PDB_PROTECT 0x0200 240 #define PDB_MAP_L1 0x0400 241 #define PDB_BOOTSTRAP 0x1000 242 #define PDB_PARANOIA 0x2000 243 #define PDB_WIRING 0x4000 244 #define PDB_PVDUMP 0x8000 245 #define PDB_VAC 0x10000 246 #define PDB_KENTER 0x20000 247 #define PDB_KREMOVE 0x40000 248 #define PDB_EXEC 0x80000 249 250 int debugmap = 1; 251 int pmapdebug = 0; 252 #define NPDEBUG(_lev_,_stat_) \ 253 if (pmapdebug & (_lev_)) \ 254 ((_stat_)) 255 256 #else /* PMAP_DEBUG */ 257 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 258 #endif /* PMAP_DEBUG */ 259 260 /* 261 * pmap_kernel() points here 262 */ 263 static struct pmap kernel_pmap_store = { 264 #ifndef ARM_MMU_EXTENDED 265 .pm_activated = true, 266 .pm_domain = PMAP_DOMAIN_KERNEL, 267 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 268 #endif 269 }; 270 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 271 #undef pmap_kernel 272 #define pmap_kernel() (&kernel_pmap_store) 273 #ifdef PMAP_NEED_ALLOC_POOLPAGE 274 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 275 #endif 276 277 /* 278 * Pool and cache that pmap structures are allocated from. 279 * We use a cache to avoid clearing the pm_l2[] array (1KB) 280 * in pmap_create(). 281 */ 282 static struct pool_cache pmap_cache; 283 static LIST_HEAD(, pmap) pmap_pmaps; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 static struct evcnt pmap_ev_exec_synced_map = 426 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 427 #ifndef ARM_MMU_EXTENDED 428 static struct evcnt pmap_ev_exec_synced_unmap = 429 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 430 static struct evcnt pmap_ev_exec_synced_remap = 431 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 432 static struct evcnt pmap_ev_exec_synced_clearbit = 433 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 440 #ifndef ARM_MMU_EXTENDED 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 /* 489 * pmap copy/zero page, and mem(5) hook point 490 */ 491 static pt_entry_t *csrc_pte, *cdst_pte; 492 static vaddr_t csrcp, cdstp; 493 #ifdef MULTIPROCESSOR 494 static size_t cnptes; 495 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 497 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 499 #else 500 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + (o)) 503 #define cpu_cdstp(o) (cdstp + (o)) 504 #endif 505 vaddr_t memhook; /* used by mem.c & others */ 506 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 507 kmutex_t pmap_lock __cacheline_aligned; 508 extern void *msgbufaddr; 509 int pmap_kmpages; 510 /* 511 * Flag to indicate if pmap_init() has done its thing 512 */ 513 bool pmap_initialized; 514 515 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 516 /* 517 * Start of direct-mapped memory 518 */ 519 vaddr_t pmap_directbase = KERNEL_BASE; 520 #endif 521 522 /* 523 * Misc. locking data structures 524 */ 525 526 static inline void 527 pmap_acquire_pmap_lock(pmap_t pm) 528 { 529 if (pm == pmap_kernel()) { 530 #ifdef MULTIPROCESSOR 531 KERNEL_LOCK(1, NULL); 532 #endif 533 } else { 534 mutex_enter(pm->pm_lock); 535 } 536 } 537 538 static inline void 539 pmap_release_pmap_lock(pmap_t pm) 540 { 541 if (pm == pmap_kernel()) { 542 #ifdef MULTIPROCESSOR 543 KERNEL_UNLOCK_ONE(NULL); 544 #endif 545 } else { 546 mutex_exit(pm->pm_lock); 547 } 548 } 549 550 static inline void 551 pmap_acquire_page_lock(struct vm_page_md *md) 552 { 553 mutex_enter(&pmap_lock); 554 } 555 556 static inline void 557 pmap_release_page_lock(struct vm_page_md *md) 558 { 559 mutex_exit(&pmap_lock); 560 } 561 562 #ifdef DIAGNOSTIC 563 static inline int 564 pmap_page_locked_p(struct vm_page_md *md) 565 { 566 return mutex_owned(&pmap_lock); 567 } 568 #endif 569 570 571 /* 572 * Metadata for L1 translation tables. 573 */ 574 #ifndef ARM_MMU_EXTENDED 575 struct l1_ttable { 576 /* Entry on the L1 Table list */ 577 SLIST_ENTRY(l1_ttable) l1_link; 578 579 /* Entry on the L1 Least Recently Used list */ 580 TAILQ_ENTRY(l1_ttable) l1_lru; 581 582 /* Track how many domains are allocated from this L1 */ 583 volatile u_int l1_domain_use_count; 584 585 /* 586 * A free-list of domain numbers for this L1. 587 * We avoid using ffs() and a bitmap to track domains since ffs() 588 * is slow on ARM. 589 */ 590 uint8_t l1_domain_first; 591 uint8_t l1_domain_free[PMAP_DOMAINS]; 592 593 /* Physical address of this L1 page table */ 594 paddr_t l1_physaddr; 595 596 /* KVA of this L1 page table */ 597 pd_entry_t *l1_kva; 598 }; 599 600 /* 601 * L1 Page Tables are tracked using a Least Recently Used list. 602 * - New L1s are allocated from the HEAD. 603 * - Freed L1s are added to the TAIl. 604 * - Recently accessed L1s (where an 'access' is some change to one of 605 * the userland pmaps which owns this L1) are moved to the TAIL. 606 */ 607 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 608 static kmutex_t l1_lru_lock __cacheline_aligned; 609 610 /* 611 * A list of all L1 tables 612 */ 613 static SLIST_HEAD(, l1_ttable) l1_list; 614 #endif /* ARM_MMU_EXTENDED */ 615 616 /* 617 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 618 * 619 * This is normally 16MB worth L2 page descriptors for any given pmap. 620 * Reference counts are maintained for L2 descriptors so they can be 621 * freed when empty. 622 */ 623 struct l2_dtable { 624 /* The number of L2 page descriptors allocated to this l2_dtable */ 625 u_int l2_occupancy; 626 627 /* List of L2 page descriptors */ 628 struct l2_bucket { 629 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 630 paddr_t l2b_pa; /* Physical address of same */ 631 u_short l2b_l1slot; /* This L2 table's L1 index */ 632 u_short l2b_occupancy; /* How many active descriptors */ 633 } l2_bucket[L2_BUCKET_SIZE]; 634 }; 635 636 /* 637 * Given an L1 table index, calculate the corresponding l2_dtable index 638 * and bucket index within the l2_dtable. 639 */ 640 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 641 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 642 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 643 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 644 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 645 646 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 647 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 648 649 /* 650 * Given a virtual address, this macro returns the 651 * virtual address required to drop into the next L2 bucket. 652 */ 653 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 654 655 /* 656 * L2 allocation. 657 */ 658 #define pmap_alloc_l2_dtable() \ 659 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 660 #define pmap_free_l2_dtable(l2) \ 661 pool_cache_put(&pmap_l2dtable_cache, (l2)) 662 #define pmap_alloc_l2_ptp(pap) \ 663 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 664 PR_NOWAIT, (pap))) 665 666 /* 667 * We try to map the page tables write-through, if possible. However, not 668 * all CPUs have a write-through cache mode, so on those we have to sync 669 * the cache when we frob page tables. 670 * 671 * We try to evaluate this at compile time, if possible. However, it's 672 * not always possible to do that, hence this run-time var. 673 */ 674 int pmap_needs_pte_sync; 675 676 /* 677 * Real definition of pv_entry. 678 */ 679 struct pv_entry { 680 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 681 pmap_t pv_pmap; /* pmap where mapping lies */ 682 vaddr_t pv_va; /* virtual address for mapping */ 683 u_int pv_flags; /* flags */ 684 }; 685 686 /* 687 * Macro to determine if a mapping might be resident in the 688 * instruction cache and/or TLB 689 */ 690 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 691 /* 692 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 693 * there are no explicit accesses, so there may be always be TLB entries to 694 * flush. If we used ASIDs then this would not be a problem. 695 */ 696 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 697 #else 698 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 699 #endif 700 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 701 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 702 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 703 704 /* 705 * Macro to determine if a mapping might be resident in the 706 * data cache and/or TLB 707 */ 708 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 709 /* 710 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 711 * there are no explicit accesses, so there may be always be TLB entries to 712 * flush. If we used ASIDs then this would not be a problem. 713 */ 714 #define PV_BEEN_REFD(f) (1) 715 #else 716 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 717 #endif 718 719 /* 720 * Local prototypes 721 */ 722 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 723 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 724 pt_entry_t **); 725 static bool pmap_is_current(pmap_t); 726 static bool pmap_is_cached(pmap_t); 727 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 728 pmap_t, vaddr_t, u_int); 729 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 730 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 731 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 732 u_int, u_int); 733 734 static void pmap_pinit(pmap_t); 735 static int pmap_pmap_ctor(void *, void *, int); 736 737 static void pmap_alloc_l1(pmap_t); 738 static void pmap_free_l1(pmap_t); 739 #ifndef ARM_MMU_EXTENDED 740 static void pmap_use_l1(pmap_t); 741 #endif 742 743 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 744 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 745 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 746 static int pmap_l2ptp_ctor(void *, void *, int); 747 static int pmap_l2dtable_ctor(void *, void *, int); 748 749 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 750 #ifdef PMAP_CACHE_VIVT 751 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 752 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 753 #endif 754 755 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 756 #ifdef PMAP_CACHE_VIVT 757 static bool pmap_clean_page(struct vm_page_md *, bool); 758 #endif 759 #ifdef PMAP_CACHE_VIPT 760 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 761 enum pmap_flush_op { 762 PMAP_FLUSH_PRIMARY, 763 PMAP_FLUSH_SECONDARY, 764 PMAP_CLEAN_PRIMARY 765 }; 766 #ifndef ARM_MMU_EXTENDED 767 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 768 #endif 769 #endif 770 static void pmap_page_remove(struct vm_page_md *, paddr_t); 771 772 #ifndef ARM_MMU_EXTENDED 773 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 774 #endif 775 static vaddr_t kernel_pt_lookup(paddr_t); 776 777 778 /* 779 * Misc variables 780 */ 781 vaddr_t virtual_avail; 782 vaddr_t virtual_end; 783 vaddr_t pmap_curmaxkvaddr; 784 785 paddr_t avail_start; 786 paddr_t avail_end; 787 788 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 789 pv_addr_t kernelpages; 790 pv_addr_t kernel_l1pt; 791 pv_addr_t systempage; 792 793 /* Function to set the debug level of the pmap code */ 794 795 #ifdef PMAP_DEBUG 796 void 797 pmap_debug(int level) 798 { 799 pmap_debug_level = level; 800 printf("pmap_debug: level=%d\n", pmap_debug_level); 801 } 802 #endif /* PMAP_DEBUG */ 803 804 #ifdef PMAP_CACHE_VIPT 805 #define PMAP_VALIDATE_MD_PAGE(md) \ 806 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 807 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 808 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 809 #endif /* PMAP_CACHE_VIPT */ 810 /* 811 * A bunch of routines to conditionally flush the caches/TLB depending 812 * on whether the specified pmap actually needs to be flushed at any 813 * given time. 814 */ 815 static inline void 816 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 817 { 818 #ifdef ARM_MMU_EXTENDED 819 pmap_tlb_invalidate_addr(pm, va); 820 #else 821 if (pm->pm_cstate.cs_tlb_id != 0) { 822 if (PV_BEEN_EXECD(flags)) { 823 cpu_tlb_flushID_SE(va); 824 } else if (PV_BEEN_REFD(flags)) { 825 cpu_tlb_flushD_SE(va); 826 } 827 } 828 #endif /* ARM_MMU_EXTENDED */ 829 } 830 831 static inline void 832 pmap_tlb_flushID(pmap_t pm) 833 { 834 #ifdef ARM_MMU_EXTENDED 835 pmap_tlb_asid_release_all(pm); 836 #else 837 if (pm->pm_cstate.cs_tlb_id) { 838 cpu_tlb_flushID(); 839 #if ARM_MMU_V7 == 0 840 /* 841 * Speculative loads by Cortex cores can cause TLB entries to 842 * be filled even if there are no explicit accesses, so there 843 * may be always be TLB entries to flush. If we used ASIDs 844 * then it would not be a problem. 845 * This is not true for other CPUs. 846 */ 847 pm->pm_cstate.cs_tlb = 0; 848 #endif /* ARM_MMU_V7 */ 849 } 850 #endif /* ARM_MMU_EXTENDED */ 851 } 852 853 static inline void 854 pmap_tlb_flushD(pmap_t pm) 855 { 856 #ifdef ARM_MMU_EXTENDED 857 pmap_tlb_asid_release_all(pm); 858 #else 859 if (pm->pm_cstate.cs_tlb_d) { 860 cpu_tlb_flushD(); 861 #if ARM_MMU_V7 == 0 862 /* 863 * Speculative loads by Cortex cores can cause TLB entries to 864 * be filled even if there are no explicit accesses, so there 865 * may be always be TLB entries to flush. If we used ASIDs 866 * then it would not be a problem. 867 * This is not true for other CPUs. 868 */ 869 pm->pm_cstate.cs_tlb_d = 0; 870 #endif /* ARM_MMU_V7 */ 871 } 872 #endif /* ARM_MMU_EXTENDED */ 873 } 874 875 #ifdef PMAP_CACHE_VIVT 876 static inline void 877 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 878 { 879 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 880 cpu_idcache_wbinv_range(va, PAGE_SIZE); 881 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 882 if (do_inv) { 883 if (flags & PVF_WRITE) 884 cpu_dcache_wbinv_range(va, PAGE_SIZE); 885 else 886 cpu_dcache_inv_range(va, PAGE_SIZE); 887 } else if (flags & PVF_WRITE) { 888 cpu_dcache_wb_range(va, PAGE_SIZE); 889 } 890 } 891 } 892 893 static inline void 894 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 895 { 896 if (PV_BEEN_EXECD(flags)) { 897 if (pm->pm_cstate.cs_cache_id) { 898 cpu_idcache_wbinv_all(); 899 pm->pm_cstate.cs_cache = 0; 900 } 901 } else if (pm->pm_cstate.cs_cache_d) { 902 cpu_dcache_wbinv_all(); 903 pm->pm_cstate.cs_cache_d = 0; 904 } 905 } 906 #endif /* PMAP_CACHE_VIVT */ 907 908 static inline uint8_t 909 pmap_domain(pmap_t pm) 910 { 911 #ifdef ARM_MMU_EXTENDED 912 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 913 #else 914 return pm->pm_domain; 915 #endif 916 } 917 918 static inline pd_entry_t * 919 pmap_l1_kva(pmap_t pm) 920 { 921 #ifdef ARM_MMU_EXTENDED 922 return pm->pm_l1; 923 #else 924 return pm->pm_l1->l1_kva; 925 #endif 926 } 927 928 static inline bool 929 pmap_is_current(pmap_t pm) 930 { 931 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 932 return true; 933 934 return false; 935 } 936 937 static inline bool 938 pmap_is_cached(pmap_t pm) 939 { 940 #ifdef ARM_MMU_EXTENDED 941 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 942 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 943 return true; 944 #else 945 struct cpu_info * const ci = curcpu(); 946 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 947 || ci->ci_pmap_lastuser == pm) 948 return true; 949 #endif /* ARM_MMU_EXTENDED */ 950 951 return false; 952 } 953 954 /* 955 * PTE_SYNC_CURRENT: 956 * 957 * Make sure the pte is written out to RAM. 958 * We need to do this for one of two cases: 959 * - We're dealing with the kernel pmap 960 * - There is no pmap active in the cache/tlb. 961 * - The specified pmap is 'active' in the cache/tlb. 962 */ 963 #ifdef PMAP_INCLUDE_PTE_SYNC 964 #define PTE_SYNC_CURRENT(pm, ptep) \ 965 do { \ 966 if (PMAP_NEEDS_PTE_SYNC && \ 967 pmap_is_cached(pm)) \ 968 PTE_SYNC(ptep); \ 969 } while (/*CONSTCOND*/0) 970 #else 971 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 972 #endif 973 974 /* 975 * main pv_entry manipulation functions: 976 * pmap_enter_pv: enter a mapping onto a vm_page list 977 * pmap_remove_pv: remove a mapping from a vm_page list 978 * 979 * NOTE: pmap_enter_pv expects to lock the pvh itself 980 * pmap_remove_pv expects the caller to lock the pvh before calling 981 */ 982 983 /* 984 * pmap_enter_pv: enter a mapping onto a vm_page lst 985 * 986 * => caller should hold the proper lock on pmap_main_lock 987 * => caller should have pmap locked 988 * => we will gain the lock on the vm_page and allocate the new pv_entry 989 * => caller should adjust ptp's wire_count before calling 990 * => caller should not adjust pmap's wire_count 991 */ 992 static void 993 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 994 vaddr_t va, u_int flags) 995 { 996 struct pv_entry **pvp; 997 998 NPDEBUG(PDB_PVDUMP, 999 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 1000 1001 pv->pv_pmap = pm; 1002 pv->pv_va = va; 1003 pv->pv_flags = flags; 1004 1005 pvp = &SLIST_FIRST(&md->pvh_list); 1006 #ifdef PMAP_CACHE_VIPT 1007 /* 1008 * Insert unmanaged entries, writeable first, at the head of 1009 * the pv list. 1010 */ 1011 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1012 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1013 pvp = &SLIST_NEXT(*pvp, pv_link); 1014 } 1015 if (!PV_IS_WRITE_P(flags)) { 1016 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1017 pvp = &SLIST_NEXT(*pvp, pv_link); 1018 } 1019 #endif 1020 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1021 *pvp = pv; /* ... locked list */ 1022 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1023 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1024 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1025 md->pvh_attrs |= PVF_KMOD; 1026 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1027 md->pvh_attrs |= PVF_DIRTY; 1028 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1029 #endif 1030 if (pm == pmap_kernel()) { 1031 PMAPCOUNT(kernel_mappings); 1032 if (flags & PVF_WRITE) 1033 md->krw_mappings++; 1034 else 1035 md->kro_mappings++; 1036 } else { 1037 if (flags & PVF_WRITE) 1038 md->urw_mappings++; 1039 else 1040 md->uro_mappings++; 1041 } 1042 1043 #ifdef PMAP_CACHE_VIPT 1044 #ifndef ARM_MMU_EXTENDED 1045 /* 1046 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1047 * do it here as well to keep the mappings & KVF_WRITE consistent. 1048 */ 1049 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1050 md->pvh_attrs |= PVF_WRITE; 1051 } 1052 #endif 1053 /* 1054 * If this is an exec mapping and its the first exec mapping 1055 * for this page, make sure to sync the I-cache. 1056 */ 1057 if (PV_IS_EXEC_P(flags)) { 1058 #ifndef ARM_MMU_EXTENDED 1059 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1060 pmap_syncicache_page(md, pa); 1061 PMAPCOUNT(exec_synced_map); 1062 } 1063 #endif 1064 PMAPCOUNT(exec_mappings); 1065 } 1066 #endif 1067 1068 PMAPCOUNT(mappings); 1069 1070 if (pv->pv_flags & PVF_WIRED) 1071 ++pm->pm_stats.wired_count; 1072 } 1073 1074 /* 1075 * 1076 * pmap_find_pv: Find a pv entry 1077 * 1078 * => caller should hold lock on vm_page 1079 */ 1080 static inline struct pv_entry * 1081 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1082 { 1083 struct pv_entry *pv; 1084 1085 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1086 if (pm == pv->pv_pmap && va == pv->pv_va) 1087 break; 1088 } 1089 1090 return (pv); 1091 } 1092 1093 /* 1094 * pmap_remove_pv: try to remove a mapping from a pv_list 1095 * 1096 * => caller should hold proper lock on pmap_main_lock 1097 * => pmap should be locked 1098 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1099 * => caller should adjust ptp's wire_count and free PTP if needed 1100 * => caller should NOT adjust pmap's wire_count 1101 * => we return the removed pv 1102 */ 1103 static struct pv_entry * 1104 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1105 { 1106 struct pv_entry *pv, **prevptr; 1107 1108 NPDEBUG(PDB_PVDUMP, 1109 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1110 1111 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1112 pv = *prevptr; 1113 1114 while (pv) { 1115 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1116 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1117 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1118 if (pv->pv_flags & PVF_WIRED) { 1119 --pm->pm_stats.wired_count; 1120 } 1121 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1122 if (pm == pmap_kernel()) { 1123 PMAPCOUNT(kernel_unmappings); 1124 if (pv->pv_flags & PVF_WRITE) 1125 md->krw_mappings--; 1126 else 1127 md->kro_mappings--; 1128 } else { 1129 if (pv->pv_flags & PVF_WRITE) 1130 md->urw_mappings--; 1131 else 1132 md->uro_mappings--; 1133 } 1134 1135 PMAPCOUNT(unmappings); 1136 #ifdef PMAP_CACHE_VIPT 1137 if (!(pv->pv_flags & PVF_WRITE)) 1138 break; 1139 /* 1140 * If this page has had an exec mapping, then if 1141 * this was the last mapping, discard the contents, 1142 * otherwise sync the i-cache for this page. 1143 */ 1144 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1145 #ifdef ARM_MMU_EXTENDED 1146 md->pvh_attrs &= ~PVF_EXEC; 1147 PMAPCOUNT(exec_discarded_unmap); 1148 #else 1149 if (SLIST_EMPTY(&md->pvh_list)) { 1150 md->pvh_attrs &= ~PVF_EXEC; 1151 PMAPCOUNT(exec_discarded_unmap); 1152 } else { 1153 pmap_syncicache_page(md, pa); 1154 PMAPCOUNT(exec_synced_unmap); 1155 } 1156 #endif /* ARM_MMU_EXTENDED */ 1157 } 1158 #endif /* PMAP_CACHE_VIPT */ 1159 break; 1160 } 1161 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1162 pv = *prevptr; /* advance */ 1163 } 1164 1165 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1166 /* 1167 * If we no longer have a WRITEABLE KENTRY at the head of list, 1168 * clear the KMOD attribute from the page. 1169 */ 1170 if (SLIST_FIRST(&md->pvh_list) == NULL 1171 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1172 md->pvh_attrs &= ~PVF_KMOD; 1173 1174 /* 1175 * If this was a writeable page and there are no more writeable 1176 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1177 * the contents to memory. 1178 */ 1179 if (arm_cache_prefer_mask != 0) { 1180 if (md->krw_mappings + md->urw_mappings == 0) 1181 md->pvh_attrs &= ~PVF_WRITE; 1182 PMAP_VALIDATE_MD_PAGE(md); 1183 } 1184 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1185 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1186 1187 return(pv); /* return removed pv */ 1188 } 1189 1190 /* 1191 * 1192 * pmap_modify_pv: Update pv flags 1193 * 1194 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1195 * => caller should NOT adjust pmap's wire_count 1196 * => caller must call pmap_vac_me_harder() if writable status of a page 1197 * may have changed. 1198 * => we return the old flags 1199 * 1200 * Modify a physical-virtual mapping in the pv table 1201 */ 1202 static u_int 1203 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1204 u_int clr_mask, u_int set_mask) 1205 { 1206 struct pv_entry *npv; 1207 u_int flags, oflags; 1208 1209 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1210 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1211 1212 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1213 return (0); 1214 1215 NPDEBUG(PDB_PVDUMP, 1216 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1217 1218 /* 1219 * There is at least one VA mapping this page. 1220 */ 1221 1222 if (clr_mask & (PVF_REF | PVF_MOD)) { 1223 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1224 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1225 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1226 md->pvh_attrs |= PVF_DIRTY; 1227 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1228 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1229 } 1230 1231 oflags = npv->pv_flags; 1232 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1233 1234 if ((flags ^ oflags) & PVF_WIRED) { 1235 if (flags & PVF_WIRED) 1236 ++pm->pm_stats.wired_count; 1237 else 1238 --pm->pm_stats.wired_count; 1239 } 1240 1241 if ((flags ^ oflags) & PVF_WRITE) { 1242 if (pm == pmap_kernel()) { 1243 if (flags & PVF_WRITE) { 1244 md->krw_mappings++; 1245 md->kro_mappings--; 1246 } else { 1247 md->kro_mappings++; 1248 md->krw_mappings--; 1249 } 1250 } else { 1251 if (flags & PVF_WRITE) { 1252 md->urw_mappings++; 1253 md->uro_mappings--; 1254 } else { 1255 md->uro_mappings++; 1256 md->urw_mappings--; 1257 } 1258 } 1259 } 1260 #ifdef PMAP_CACHE_VIPT 1261 if (arm_cache_prefer_mask != 0) { 1262 if (md->urw_mappings + md->krw_mappings == 0) { 1263 md->pvh_attrs &= ~PVF_WRITE; 1264 } else { 1265 md->pvh_attrs |= PVF_WRITE; 1266 } 1267 } 1268 #ifndef ARM_MMU_EXTENDED 1269 /* 1270 * We have two cases here: the first is from enter_pv (new exec 1271 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1272 * Since in latter, pmap_enter_pv won't do anything, we just have 1273 * to do what pmap_remove_pv would do. 1274 */ 1275 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1276 || (PV_IS_EXEC_P(md->pvh_attrs) 1277 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1278 pmap_syncicache_page(md, pa); 1279 PMAPCOUNT(exec_synced_remap); 1280 } 1281 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1282 #endif /* !ARM_MMU_EXTENDED */ 1283 #endif /* PMAP_CACHE_VIPT */ 1284 1285 PMAPCOUNT(remappings); 1286 1287 return (oflags); 1288 } 1289 1290 /* 1291 * Allocate an L1 translation table for the specified pmap. 1292 * This is called at pmap creation time. 1293 */ 1294 static void 1295 pmap_alloc_l1(pmap_t pm) 1296 { 1297 #ifdef ARM_MMU_EXTENDED 1298 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1299 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1300 struct vm_page *pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1301 #else 1302 struct vm_page *pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1303 #endif 1304 bool ok __diagused; 1305 KASSERT(pg != NULL); 1306 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1307 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0xdeadbeef); 1308 KASSERT(ok); 1309 KASSERT(va >= KERNEL_BASE); 1310 1311 #else 1312 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1313 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1314 UVM_KMF_WIRED|UVM_KMF_ZERO); 1315 KASSERT(!va); 1316 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1317 #endif 1318 pm->pm_l1 = (pd_entry_t *)va; 1319 #else 1320 struct l1_ttable *l1; 1321 uint8_t domain; 1322 1323 /* 1324 * Remove the L1 at the head of the LRU list 1325 */ 1326 mutex_spin_enter(&l1_lru_lock); 1327 l1 = TAILQ_FIRST(&l1_lru_list); 1328 KDASSERT(l1 != NULL); 1329 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1330 1331 /* 1332 * Pick the first available domain number, and update 1333 * the link to the next number. 1334 */ 1335 domain = l1->l1_domain_first; 1336 l1->l1_domain_first = l1->l1_domain_free[domain]; 1337 1338 /* 1339 * If there are still free domain numbers in this L1, 1340 * put it back on the TAIL of the LRU list. 1341 */ 1342 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1343 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1344 1345 mutex_spin_exit(&l1_lru_lock); 1346 1347 /* 1348 * Fix up the relevant bits in the pmap structure 1349 */ 1350 pm->pm_l1 = l1; 1351 pm->pm_domain = domain + 1; 1352 #endif 1353 } 1354 1355 /* 1356 * Free an L1 translation table. 1357 * This is called at pmap destruction time. 1358 */ 1359 static void 1360 pmap_free_l1(pmap_t pm) 1361 { 1362 #ifdef ARM_MMU_EXTENDED 1363 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1364 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1365 uvm_pagefree(pg); 1366 #else 1367 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1368 #endif 1369 pm->pm_l1 = NULL; 1370 pm->pm_l1_pa = 0; 1371 #else 1372 struct l1_ttable *l1 = pm->pm_l1; 1373 1374 mutex_spin_enter(&l1_lru_lock); 1375 1376 /* 1377 * If this L1 is currently on the LRU list, remove it. 1378 */ 1379 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1380 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1381 1382 /* 1383 * Free up the domain number which was allocated to the pmap 1384 */ 1385 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1386 l1->l1_domain_first = pmap_domain(pm) - 1; 1387 l1->l1_domain_use_count--; 1388 1389 /* 1390 * The L1 now must have at least 1 free domain, so add 1391 * it back to the LRU list. If the use count is zero, 1392 * put it at the head of the list, otherwise it goes 1393 * to the tail. 1394 */ 1395 if (l1->l1_domain_use_count == 0) 1396 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1397 else 1398 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1399 1400 mutex_spin_exit(&l1_lru_lock); 1401 #endif /* ARM_MMU_EXTENDED */ 1402 } 1403 1404 #ifndef ARM_MMU_EXTENDED 1405 static inline void 1406 pmap_use_l1(pmap_t pm) 1407 { 1408 struct l1_ttable *l1; 1409 1410 /* 1411 * Do nothing if we're in interrupt context. 1412 * Access to an L1 by the kernel pmap must not affect 1413 * the LRU list. 1414 */ 1415 if (cpu_intr_p() || pm == pmap_kernel()) 1416 return; 1417 1418 l1 = pm->pm_l1; 1419 1420 /* 1421 * If the L1 is not currently on the LRU list, just return 1422 */ 1423 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1424 return; 1425 1426 mutex_spin_enter(&l1_lru_lock); 1427 1428 /* 1429 * Check the use count again, now that we've acquired the lock 1430 */ 1431 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1432 mutex_spin_exit(&l1_lru_lock); 1433 return; 1434 } 1435 1436 /* 1437 * Move the L1 to the back of the LRU list 1438 */ 1439 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1440 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1441 1442 mutex_spin_exit(&l1_lru_lock); 1443 } 1444 #endif /* !ARM_MMU_EXTENDED */ 1445 1446 /* 1447 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1448 * 1449 * Free an L2 descriptor table. 1450 */ 1451 static inline void 1452 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1453 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1454 #else 1455 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1456 #endif 1457 { 1458 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1459 /* 1460 * Note: With a write-back cache, we may need to sync this 1461 * L2 table before re-using it. 1462 * This is because it may have belonged to a non-current 1463 * pmap, in which case the cache syncs would have been 1464 * skipped for the pages that were being unmapped. If the 1465 * L2 table were then to be immediately re-allocated to 1466 * the *current* pmap, it may well contain stale mappings 1467 * which have not yet been cleared by a cache write-back 1468 * and so would still be visible to the mmu. 1469 */ 1470 if (need_sync) 1471 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1472 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1473 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1474 } 1475 1476 /* 1477 * Returns a pointer to the L2 bucket associated with the specified pmap 1478 * and VA, or NULL if no L2 bucket exists for the address. 1479 */ 1480 static inline struct l2_bucket * 1481 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1482 { 1483 const size_t l1slot = l1pte_index(va); 1484 struct l2_dtable *l2; 1485 struct l2_bucket *l2b; 1486 1487 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1488 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1489 return (NULL); 1490 1491 return (l2b); 1492 } 1493 1494 /* 1495 * Returns a pointer to the L2 bucket associated with the specified pmap 1496 * and VA. 1497 * 1498 * If no L2 bucket exists, perform the necessary allocations to put an L2 1499 * bucket/page table in place. 1500 * 1501 * Note that if a new L2 bucket/page was allocated, the caller *must* 1502 * increment the bucket occupancy counter appropriately *before* 1503 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1504 * the bucket/page in the meantime. 1505 */ 1506 static struct l2_bucket * 1507 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1508 { 1509 const size_t l1slot = l1pte_index(va); 1510 struct l2_dtable *l2; 1511 1512 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1513 /* 1514 * No mapping at this address, as there is 1515 * no entry in the L1 table. 1516 * Need to allocate a new l2_dtable. 1517 */ 1518 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1519 return (NULL); 1520 1521 /* 1522 * Link it into the parent pmap 1523 */ 1524 pm->pm_l2[L2_IDX(l1slot)] = l2; 1525 } 1526 1527 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1528 1529 /* 1530 * Fetch pointer to the L2 page table associated with the address. 1531 */ 1532 if (l2b->l2b_kva == NULL) { 1533 pt_entry_t *ptep; 1534 1535 /* 1536 * No L2 page table has been allocated. Chances are, this 1537 * is because we just allocated the l2_dtable, above. 1538 */ 1539 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1540 /* 1541 * Oops, no more L2 page tables available at this 1542 * time. We may need to deallocate the l2_dtable 1543 * if we allocated a new one above. 1544 */ 1545 if (l2->l2_occupancy == 0) { 1546 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1547 pmap_free_l2_dtable(l2); 1548 } 1549 return (NULL); 1550 } 1551 1552 l2->l2_occupancy++; 1553 l2b->l2b_kva = ptep; 1554 l2b->l2b_l1slot = l1slot; 1555 1556 #ifdef ARM_MMU_EXTENDED 1557 /* 1558 * We know there will be a mapping here, so simply 1559 * enter this PTP into the L1 now. 1560 */ 1561 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1562 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1563 | L1_C_DOM(pmap_domain(pm)); 1564 KASSERT(*pdep == 0); 1565 l1pte_setone(pdep, npde); 1566 PTE_SYNC(pdep); 1567 #endif 1568 } 1569 1570 return (l2b); 1571 } 1572 1573 /* 1574 * One or more mappings in the specified L2 descriptor table have just been 1575 * invalidated. 1576 * 1577 * Garbage collect the metadata and descriptor table itself if necessary. 1578 * 1579 * The pmap lock must be acquired when this is called (not necessary 1580 * for the kernel pmap). 1581 */ 1582 static void 1583 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1584 { 1585 KDASSERT(count <= l2b->l2b_occupancy); 1586 1587 /* 1588 * Update the bucket's reference count according to how many 1589 * PTEs the caller has just invalidated. 1590 */ 1591 l2b->l2b_occupancy -= count; 1592 1593 /* 1594 * Note: 1595 * 1596 * Level 2 page tables allocated to the kernel pmap are never freed 1597 * as that would require checking all Level 1 page tables and 1598 * removing any references to the Level 2 page table. See also the 1599 * comment elsewhere about never freeing bootstrap L2 descriptors. 1600 * 1601 * We make do with just invalidating the mapping in the L2 table. 1602 * 1603 * This isn't really a big deal in practice and, in fact, leads 1604 * to a performance win over time as we don't need to continually 1605 * alloc/free. 1606 */ 1607 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1608 return; 1609 1610 /* 1611 * There are no more valid mappings in this level 2 page table. 1612 * Go ahead and NULL-out the pointer in the bucket, then 1613 * free the page table. 1614 */ 1615 const size_t l1slot = l2b->l2b_l1slot; 1616 pt_entry_t * const ptep = l2b->l2b_kva; 1617 l2b->l2b_kva = NULL; 1618 1619 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1620 pd_entry_t pde __diagused = *pdep; 1621 1622 #ifdef ARM_MMU_EXTENDED 1623 /* 1624 * Invalidate the L1 slot. 1625 */ 1626 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1627 #else 1628 /* 1629 * If the L1 slot matches the pmap's domain number, then invalidate it. 1630 */ 1631 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1632 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1633 #endif 1634 l1pte_setone(pdep, 0); 1635 PDE_SYNC(pdep); 1636 #ifndef ARM_MMU_EXTENDED 1637 } 1638 #endif 1639 1640 /* 1641 * Release the L2 descriptor table back to the pool cache. 1642 */ 1643 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1644 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1645 #else 1646 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1647 #endif 1648 1649 /* 1650 * Update the reference count in the associated l2_dtable 1651 */ 1652 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1653 if (--l2->l2_occupancy > 0) 1654 return; 1655 1656 /* 1657 * There are no more valid mappings in any of the Level 1 1658 * slots managed by this l2_dtable. Go ahead and NULL-out 1659 * the pointer in the parent pmap and free the l2_dtable. 1660 */ 1661 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1662 pmap_free_l2_dtable(l2); 1663 } 1664 1665 /* 1666 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1667 * structures. 1668 */ 1669 static int 1670 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1671 { 1672 #ifndef PMAP_INCLUDE_PTE_SYNC 1673 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1674 1675 /* 1676 * The mappings for these page tables were initially made using 1677 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1678 * mode will not be right for page table mappings. To avoid 1679 * polluting the pmap_kenter_pa() code with a special case for 1680 * page tables, we simply fix up the cache-mode here if it's not 1681 * correct. 1682 */ 1683 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1684 const struct l2_bucket * const l2b = 1685 pmap_get_l2_bucket(pmap_kernel(), va); 1686 KASSERTMSG(l2b != NULL, "%#lx", va); 1687 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1688 const pt_entry_t opte = *ptep; 1689 1690 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1691 /* 1692 * Page tables must have the cache-mode set correctly. 1693 */ 1694 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1695 | pte_l2_s_cache_mode_pt; 1696 l2pte_set(ptep, npte, opte); 1697 PTE_SYNC(ptep); 1698 cpu_tlb_flushD_SE(va); 1699 cpu_cpwait(); 1700 } 1701 } 1702 #endif 1703 1704 memset(v, 0, L2_TABLE_SIZE_REAL); 1705 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1706 return (0); 1707 } 1708 1709 static int 1710 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1711 { 1712 1713 memset(v, 0, sizeof(struct l2_dtable)); 1714 return (0); 1715 } 1716 1717 static int 1718 pmap_pmap_ctor(void *arg, void *v, int flags) 1719 { 1720 1721 memset(v, 0, sizeof(struct pmap)); 1722 return (0); 1723 } 1724 1725 static void 1726 pmap_pinit(pmap_t pm) 1727 { 1728 #ifndef ARM_HAS_VBAR 1729 struct l2_bucket *l2b; 1730 1731 if (vector_page < KERNEL_BASE) { 1732 /* 1733 * Map the vector page. 1734 */ 1735 pmap_enter(pm, vector_page, systempage.pv_pa, 1736 VM_PROT_READ | VM_PROT_EXECUTE, 1737 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1738 pmap_update(pm); 1739 1740 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1741 l2b = pmap_get_l2_bucket(pm, vector_page); 1742 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1743 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1744 L1_C_DOM(pmap_domain(pm)); 1745 } else 1746 pm->pm_pl1vec = NULL; 1747 #endif 1748 } 1749 1750 #ifdef PMAP_CACHE_VIVT 1751 /* 1752 * Since we have a virtually indexed cache, we may need to inhibit caching if 1753 * there is more than one mapping and at least one of them is writable. 1754 * Since we purge the cache on every context switch, we only need to check for 1755 * other mappings within the same pmap, or kernel_pmap. 1756 * This function is also called when a page is unmapped, to possibly reenable 1757 * caching on any remaining mappings. 1758 * 1759 * The code implements the following logic, where: 1760 * 1761 * KW = # of kernel read/write pages 1762 * KR = # of kernel read only pages 1763 * UW = # of user read/write pages 1764 * UR = # of user read only pages 1765 * 1766 * KC = kernel mapping is cacheable 1767 * UC = user mapping is cacheable 1768 * 1769 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1770 * +--------------------------------------------- 1771 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1772 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1773 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1774 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1775 */ 1776 1777 static const int pmap_vac_flags[4][4] = { 1778 {-1, 0, 0, PVF_KNC}, 1779 {0, 0, PVF_NC, PVF_NC}, 1780 {0, PVF_NC, PVF_NC, PVF_NC}, 1781 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1782 }; 1783 1784 static inline int 1785 pmap_get_vac_flags(const struct vm_page_md *md) 1786 { 1787 int kidx, uidx; 1788 1789 kidx = 0; 1790 if (md->kro_mappings || md->krw_mappings > 1) 1791 kidx |= 1; 1792 if (md->krw_mappings) 1793 kidx |= 2; 1794 1795 uidx = 0; 1796 if (md->uro_mappings || md->urw_mappings > 1) 1797 uidx |= 1; 1798 if (md->urw_mappings) 1799 uidx |= 2; 1800 1801 return (pmap_vac_flags[uidx][kidx]); 1802 } 1803 1804 static inline void 1805 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1806 { 1807 int nattr; 1808 1809 nattr = pmap_get_vac_flags(md); 1810 1811 if (nattr < 0) { 1812 md->pvh_attrs &= ~PVF_NC; 1813 return; 1814 } 1815 1816 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1817 return; 1818 1819 if (pm == pmap_kernel()) 1820 pmap_vac_me_kpmap(md, pa, pm, va); 1821 else 1822 pmap_vac_me_user(md, pa, pm, va); 1823 1824 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1825 } 1826 1827 static void 1828 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1829 { 1830 u_int u_cacheable, u_entries; 1831 struct pv_entry *pv; 1832 pmap_t last_pmap = pm; 1833 1834 /* 1835 * Pass one, see if there are both kernel and user pmaps for 1836 * this page. Calculate whether there are user-writable or 1837 * kernel-writable pages. 1838 */ 1839 u_cacheable = 0; 1840 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1841 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1842 u_cacheable++; 1843 } 1844 1845 u_entries = md->urw_mappings + md->uro_mappings; 1846 1847 /* 1848 * We know we have just been updating a kernel entry, so if 1849 * all user pages are already cacheable, then there is nothing 1850 * further to do. 1851 */ 1852 if (md->k_mappings == 0 && u_cacheable == u_entries) 1853 return; 1854 1855 if (u_entries) { 1856 /* 1857 * Scan over the list again, for each entry, if it 1858 * might not be set correctly, call pmap_vac_me_user 1859 * to recalculate the settings. 1860 */ 1861 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1862 /* 1863 * We know kernel mappings will get set 1864 * correctly in other calls. We also know 1865 * that if the pmap is the same as last_pmap 1866 * then we've just handled this entry. 1867 */ 1868 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1869 continue; 1870 1871 /* 1872 * If there are kernel entries and this page 1873 * is writable but non-cacheable, then we can 1874 * skip this entry also. 1875 */ 1876 if (md->k_mappings && 1877 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1878 (PVF_NC | PVF_WRITE)) 1879 continue; 1880 1881 /* 1882 * Similarly if there are no kernel-writable 1883 * entries and the page is already 1884 * read-only/cacheable. 1885 */ 1886 if (md->krw_mappings == 0 && 1887 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1888 continue; 1889 1890 /* 1891 * For some of the remaining cases, we know 1892 * that we must recalculate, but for others we 1893 * can't tell if they are correct or not, so 1894 * we recalculate anyway. 1895 */ 1896 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1897 } 1898 1899 if (md->k_mappings == 0) 1900 return; 1901 } 1902 1903 pmap_vac_me_user(md, pa, pm, va); 1904 } 1905 1906 static void 1907 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1908 { 1909 pmap_t kpmap = pmap_kernel(); 1910 struct pv_entry *pv, *npv = NULL; 1911 u_int entries = 0; 1912 u_int writable = 0; 1913 u_int cacheable_entries = 0; 1914 u_int kern_cacheable = 0; 1915 u_int other_writable = 0; 1916 1917 /* 1918 * Count mappings and writable mappings in this pmap. 1919 * Include kernel mappings as part of our own. 1920 * Keep a pointer to the first one. 1921 */ 1922 npv = NULL; 1923 KASSERT(pmap_page_locked_p(md)); 1924 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1925 /* Count mappings in the same pmap */ 1926 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1927 if (entries++ == 0) 1928 npv = pv; 1929 1930 /* Cacheable mappings */ 1931 if ((pv->pv_flags & PVF_NC) == 0) { 1932 cacheable_entries++; 1933 if (kpmap == pv->pv_pmap) 1934 kern_cacheable++; 1935 } 1936 1937 /* Writable mappings */ 1938 if (pv->pv_flags & PVF_WRITE) 1939 ++writable; 1940 } else 1941 if (pv->pv_flags & PVF_WRITE) 1942 other_writable = 1; 1943 } 1944 1945 /* 1946 * Enable or disable caching as necessary. 1947 * Note: the first entry might be part of the kernel pmap, 1948 * so we can't assume this is indicative of the state of the 1949 * other (maybe non-kpmap) entries. 1950 */ 1951 if ((entries > 1 && writable) || 1952 (entries > 0 && pm == kpmap && other_writable)) { 1953 if (cacheable_entries == 0) { 1954 return; 1955 } 1956 1957 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1958 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1959 (pv->pv_flags & PVF_NC)) 1960 continue; 1961 1962 pv->pv_flags |= PVF_NC; 1963 1964 struct l2_bucket * const l2b 1965 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1966 KASSERTMSG(l2b != NULL, "%#lx", va); 1967 pt_entry_t * const ptep 1968 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1969 const pt_entry_t opte = *ptep; 1970 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1971 1972 if ((va != pv->pv_va || pm != pv->pv_pmap) 1973 && l2pte_valid_p(npte)) { 1974 #ifdef PMAP_CACHE_VIVT 1975 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1976 true, pv->pv_flags); 1977 #endif 1978 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1979 pv->pv_flags); 1980 } 1981 1982 l2pte_set(ptep, npte, opte); 1983 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1984 } 1985 cpu_cpwait(); 1986 } else 1987 if (entries > cacheable_entries) { 1988 /* 1989 * Turn cacheing back on for some pages. If it is a kernel 1990 * page, only do so if there are no other writable pages. 1991 */ 1992 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1993 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1994 (kpmap != pv->pv_pmap || other_writable))) 1995 continue; 1996 1997 pv->pv_flags &= ~PVF_NC; 1998 1999 struct l2_bucket * const l2b 2000 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2001 KASSERTMSG(l2b != NULL, "%#lx", va); 2002 pt_entry_t * const ptep 2003 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2004 const pt_entry_t opte = *ptep; 2005 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2006 | pte_l2_s_cache_mode; 2007 2008 if (l2pte_valid_p(opte)) { 2009 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2010 pv->pv_flags); 2011 } 2012 2013 l2pte_set(ptep, npte, opte); 2014 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2015 } 2016 } 2017 } 2018 #endif 2019 2020 #ifdef PMAP_CACHE_VIPT 2021 static void 2022 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2023 { 2024 #ifndef ARM_MMU_EXTENDED 2025 struct pv_entry *pv; 2026 vaddr_t tst_mask; 2027 bool bad_alias; 2028 const u_int 2029 rw_mappings = md->urw_mappings + md->krw_mappings, 2030 ro_mappings = md->uro_mappings + md->kro_mappings; 2031 2032 /* do we need to do anything? */ 2033 if (arm_cache_prefer_mask == 0) 2034 return; 2035 2036 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2037 md, pm, va)); 2038 2039 KASSERT(!va || pm); 2040 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2041 2042 /* Already a conflict? */ 2043 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2044 /* just an add, things are already non-cached */ 2045 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2046 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2047 bad_alias = false; 2048 if (va) { 2049 PMAPCOUNT(vac_color_none); 2050 bad_alias = true; 2051 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2052 goto fixup; 2053 } 2054 pv = SLIST_FIRST(&md->pvh_list); 2055 /* the list can't be empty because it would be cachable */ 2056 if (md->pvh_attrs & PVF_KMPAGE) { 2057 tst_mask = md->pvh_attrs; 2058 } else { 2059 KASSERT(pv); 2060 tst_mask = pv->pv_va; 2061 pv = SLIST_NEXT(pv, pv_link); 2062 } 2063 /* 2064 * Only check for a bad alias if we have writable mappings. 2065 */ 2066 tst_mask &= arm_cache_prefer_mask; 2067 if (rw_mappings > 0) { 2068 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2069 /* if there's a bad alias, stop checking. */ 2070 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2071 bad_alias = true; 2072 } 2073 md->pvh_attrs |= PVF_WRITE; 2074 if (!bad_alias) 2075 md->pvh_attrs |= PVF_DIRTY; 2076 } else { 2077 /* 2078 * We have only read-only mappings. Let's see if there 2079 * are multiple colors in use or if we mapped a KMPAGE. 2080 * If the latter, we have a bad alias. If the former, 2081 * we need to remember that. 2082 */ 2083 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2084 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2085 if (md->pvh_attrs & PVF_KMPAGE) 2086 bad_alias = true; 2087 break; 2088 } 2089 } 2090 md->pvh_attrs &= ~PVF_WRITE; 2091 /* 2092 * No KMPAGE and we exited early, so we must have 2093 * multiple color mappings. 2094 */ 2095 if (!bad_alias && pv != NULL) 2096 md->pvh_attrs |= PVF_MULTCLR; 2097 } 2098 2099 /* If no conflicting colors, set everything back to cached */ 2100 if (!bad_alias) { 2101 #ifdef DEBUG 2102 if ((md->pvh_attrs & PVF_WRITE) 2103 || ro_mappings < 2) { 2104 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2105 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2106 } 2107 #endif 2108 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2109 md->pvh_attrs |= tst_mask | PVF_COLORED; 2110 /* 2111 * Restore DIRTY bit if page is modified 2112 */ 2113 if (md->pvh_attrs & PVF_DMOD) 2114 md->pvh_attrs |= PVF_DIRTY; 2115 PMAPCOUNT(vac_color_restore); 2116 } else { 2117 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2118 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2119 } 2120 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2121 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2122 } else if (!va) { 2123 KASSERT(pmap_is_page_colored_p(md)); 2124 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2125 || (md->pvh_attrs & PVF_DIRTY)); 2126 if (rw_mappings == 0) { 2127 md->pvh_attrs &= ~PVF_WRITE; 2128 if (ro_mappings == 1 2129 && (md->pvh_attrs & PVF_MULTCLR)) { 2130 /* 2131 * If this is the last readonly mapping 2132 * but it doesn't match the current color 2133 * for the page, change the current color 2134 * to match this last readonly mapping. 2135 */ 2136 pv = SLIST_FIRST(&md->pvh_list); 2137 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2138 & arm_cache_prefer_mask; 2139 if (tst_mask) { 2140 md->pvh_attrs ^= tst_mask; 2141 PMAPCOUNT(vac_color_change); 2142 } 2143 } 2144 } 2145 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2146 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2147 return; 2148 } else if (!pmap_is_page_colored_p(md)) { 2149 /* not colored so we just use its color */ 2150 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2151 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2152 PMAPCOUNT(vac_color_new); 2153 md->pvh_attrs &= PAGE_SIZE - 1; 2154 md->pvh_attrs |= PVF_COLORED 2155 | (va & arm_cache_prefer_mask) 2156 | (rw_mappings > 0 ? PVF_WRITE : 0); 2157 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2158 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2159 return; 2160 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2161 bad_alias = false; 2162 if (rw_mappings > 0) { 2163 /* 2164 * We now have writeable mappings and if we have 2165 * readonly mappings in more than once color, we have 2166 * an aliasing problem. Regardless mark the page as 2167 * writeable. 2168 */ 2169 if (md->pvh_attrs & PVF_MULTCLR) { 2170 if (ro_mappings < 2) { 2171 /* 2172 * If we only have less than two 2173 * read-only mappings, just flush the 2174 * non-primary colors from the cache. 2175 */ 2176 pmap_flush_page(md, pa, 2177 PMAP_FLUSH_SECONDARY); 2178 } else { 2179 bad_alias = true; 2180 } 2181 } 2182 md->pvh_attrs |= PVF_WRITE; 2183 } 2184 /* If no conflicting colors, set everything back to cached */ 2185 if (!bad_alias) { 2186 #ifdef DEBUG 2187 if (rw_mappings > 0 2188 || (md->pvh_attrs & PMAP_KMPAGE)) { 2189 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2190 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2191 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2192 } 2193 #endif 2194 if (SLIST_EMPTY(&md->pvh_list)) 2195 PMAPCOUNT(vac_color_reuse); 2196 else 2197 PMAPCOUNT(vac_color_ok); 2198 2199 /* matching color, just return */ 2200 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2201 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2202 return; 2203 } 2204 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2205 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2206 2207 /* color conflict. evict from cache. */ 2208 2209 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2210 md->pvh_attrs &= ~PVF_COLORED; 2211 md->pvh_attrs |= PVF_NC; 2212 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2213 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2214 PMAPCOUNT(vac_color_erase); 2215 } else if (rw_mappings == 0 2216 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2217 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2218 2219 /* 2220 * If the page has dirty cache lines, clean it. 2221 */ 2222 if (md->pvh_attrs & PVF_DIRTY) 2223 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2224 2225 /* 2226 * If this is the first remapping (we know that there are no 2227 * writeable mappings), then this is a simple color change. 2228 * Otherwise this is a seconary r/o mapping, which means 2229 * we don't have to do anything. 2230 */ 2231 if (ro_mappings == 1) { 2232 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2233 md->pvh_attrs &= PAGE_SIZE - 1; 2234 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2235 PMAPCOUNT(vac_color_change); 2236 } else { 2237 PMAPCOUNT(vac_color_blind); 2238 } 2239 md->pvh_attrs |= PVF_MULTCLR; 2240 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2241 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2242 return; 2243 } else { 2244 if (rw_mappings > 0) 2245 md->pvh_attrs |= PVF_WRITE; 2246 2247 /* color conflict. evict from cache. */ 2248 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2249 2250 /* the list can't be empty because this was a enter/modify */ 2251 pv = SLIST_FIRST(&md->pvh_list); 2252 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2253 KASSERT(pv); 2254 /* 2255 * If there's only one mapped page, change color to the 2256 * page's new color and return. Restore the DIRTY bit 2257 * that was erased by pmap_flush_page. 2258 */ 2259 if (SLIST_NEXT(pv, pv_link) == NULL) { 2260 md->pvh_attrs &= PAGE_SIZE - 1; 2261 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2262 if (md->pvh_attrs & PVF_DMOD) 2263 md->pvh_attrs |= PVF_DIRTY; 2264 PMAPCOUNT(vac_color_change); 2265 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2266 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2267 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2268 return; 2269 } 2270 } 2271 bad_alias = true; 2272 md->pvh_attrs &= ~PVF_COLORED; 2273 md->pvh_attrs |= PVF_NC; 2274 PMAPCOUNT(vac_color_erase); 2275 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2276 } 2277 2278 fixup: 2279 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2280 2281 /* 2282 * Turn cacheing on/off for all pages. 2283 */ 2284 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2285 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2286 pv->pv_va); 2287 KASSERTMSG(l2b != NULL, "%#lx", va); 2288 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2289 const pt_entry_t opte = *ptep; 2290 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2291 if (bad_alias) { 2292 pv->pv_flags |= PVF_NC; 2293 } else { 2294 pv->pv_flags &= ~PVF_NC; 2295 npte |= pte_l2_s_cache_mode; 2296 } 2297 2298 if (opte == npte) /* only update is there's a change */ 2299 continue; 2300 2301 if (l2pte_valid_p(npte)) { 2302 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2303 } 2304 2305 l2pte_set(ptep, npte, opte); 2306 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2307 } 2308 #endif /* !ARM_MMU_EXTENDED */ 2309 } 2310 #endif /* PMAP_CACHE_VIPT */ 2311 2312 2313 /* 2314 * Modify pte bits for all ptes corresponding to the given physical address. 2315 * We use `maskbits' rather than `clearbits' because we're always passing 2316 * constants and the latter would require an extra inversion at run-time. 2317 */ 2318 static void 2319 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2320 { 2321 struct pv_entry *pv; 2322 #ifdef PMAP_CACHE_VIPT 2323 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2324 #ifdef ARM_MMU_EXTENDED 2325 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2326 #else 2327 const u_int execbits = 0; 2328 bool need_vac_me_harder = false; 2329 bool need_syncicache = false; 2330 #endif 2331 #else 2332 const u_int execbits = 0; 2333 #endif 2334 2335 NPDEBUG(PDB_BITS, 2336 printf("pmap_clearbit: md %p mask 0x%x\n", 2337 md, maskbits)); 2338 2339 #ifdef PMAP_CACHE_VIPT 2340 /* 2341 * If we might want to sync the I-cache and we've modified it, 2342 * then we know we definitely need to sync or discard it. 2343 */ 2344 if (want_syncicache) { 2345 #ifdef ARM_MMU_EXTENDED 2346 if (md->pvh_attrs & PVF_MOD) 2347 md->pvh_attrs &= ~PVF_EXEC; 2348 #else 2349 need_syncicache = md->pvh_attrs & PVF_MOD; 2350 #endif 2351 } 2352 #endif 2353 KASSERT(pmap_page_locked_p(md)); 2354 2355 /* 2356 * Clear saved attributes (modify, reference) 2357 */ 2358 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2359 2360 if (SLIST_EMPTY(&md->pvh_list)) { 2361 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2362 if (need_syncicache) { 2363 /* 2364 * No one has it mapped, so just discard it. The next 2365 * exec remapping will cause it to be synced. 2366 */ 2367 md->pvh_attrs &= ~PVF_EXEC; 2368 PMAPCOUNT(exec_discarded_clearbit); 2369 } 2370 #endif 2371 return; 2372 } 2373 2374 /* 2375 * Loop over all current mappings setting/clearing as appropos 2376 */ 2377 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2378 pmap_t pm = pv->pv_pmap; 2379 const vaddr_t va = pv->pv_va; 2380 const u_int oflags = pv->pv_flags; 2381 #ifndef ARM_MMU_EXTENDED 2382 /* 2383 * Kernel entries are unmanaged and as such not to be changed. 2384 */ 2385 if (PV_IS_KENTRY_P(oflags)) 2386 continue; 2387 #endif 2388 pv->pv_flags &= ~maskbits; 2389 2390 pmap_release_page_lock(md); 2391 pmap_acquire_pmap_lock(pm); 2392 2393 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2394 if (l2b == NULL) { 2395 pmap_release_pmap_lock(pm); 2396 pmap_acquire_page_lock(md); 2397 continue; 2398 } 2399 KASSERTMSG(l2b != NULL, "%#lx", va); 2400 2401 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2402 const pt_entry_t opte = *ptep; 2403 pt_entry_t npte = opte | execbits; 2404 2405 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2406 2407 NPDEBUG(PDB_BITS, 2408 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2409 __func__, pv, pm, va, oflags)); 2410 2411 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2412 #ifdef PMAP_CACHE_VIVT 2413 if ((oflags & PVF_NC)) { 2414 /* 2415 * Entry is not cacheable: 2416 * 2417 * Don't turn caching on again if this is a 2418 * modified emulation. This would be 2419 * inconsitent with the settings created by 2420 * pmap_vac_me_harder(). Otherwise, it's safe 2421 * to re-enable cacheing. 2422 * 2423 * There's no need to call pmap_vac_me_harder() 2424 * here: all pages are losing their write 2425 * permission. 2426 */ 2427 if (maskbits & PVF_WRITE) { 2428 npte |= pte_l2_s_cache_mode; 2429 pv->pv_flags &= ~PVF_NC; 2430 } 2431 } else 2432 if (l2pte_writable_p(opte)) { 2433 /* 2434 * Entry is writable/cacheable: check if pmap 2435 * is current if it is flush it, otherwise it 2436 * won't be in the cache 2437 */ 2438 pmap_cache_wbinv_page(pm, va, 2439 (maskbits & PVF_REF) != 0, 2440 oflags|PVF_WRITE); 2441 } 2442 #endif 2443 2444 /* make the pte read only */ 2445 npte = l2pte_set_readonly(npte); 2446 2447 pmap_acquire_page_lock(md); 2448 #ifdef MULTIPROCESSOR 2449 pv = pmap_find_pv(md, pm, va); 2450 #endif 2451 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2452 /* 2453 * Keep alias accounting up to date 2454 */ 2455 if (pm == pmap_kernel()) { 2456 md->krw_mappings--; 2457 md->kro_mappings++; 2458 } else { 2459 md->urw_mappings--; 2460 md->uro_mappings++; 2461 } 2462 #ifdef PMAP_CACHE_VIPT 2463 if (arm_cache_prefer_mask != 0) { 2464 if (md->urw_mappings + md->krw_mappings == 0) { 2465 md->pvh_attrs &= ~PVF_WRITE; 2466 } else { 2467 PMAP_VALIDATE_MD_PAGE(md); 2468 } 2469 } 2470 #ifndef ARM_MMU_EXTENDED 2471 if (want_syncicache) 2472 need_syncicache = true; 2473 need_vac_me_harder = true; 2474 #endif 2475 #endif /* PMAP_CACHE_VIPT */ 2476 } 2477 pmap_release_page_lock(md); 2478 } 2479 2480 if (maskbits & PVF_REF) { 2481 if (true 2482 #ifndef ARM_MMU_EXTENDED 2483 && (oflags & PVF_NC) == 0 2484 #endif 2485 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2486 && l2pte_valid_p(npte)) { 2487 #ifdef PMAP_CACHE_VIVT 2488 /* 2489 * Check npte here; we may have already 2490 * done the wbinv above, and the validity 2491 * of the PTE is the same for opte and 2492 * npte. 2493 */ 2494 pmap_cache_wbinv_page(pm, va, true, oflags); 2495 #endif 2496 } 2497 2498 /* 2499 * Make the PTE invalid so that we will take a 2500 * page fault the next time the mapping is 2501 * referenced. 2502 */ 2503 npte &= ~L2_TYPE_MASK; 2504 npte |= L2_TYPE_INV; 2505 } 2506 2507 if (npte != opte) { 2508 l2pte_set(ptep, npte, opte); 2509 PTE_SYNC(ptep); 2510 2511 /* Flush the TLB entry if a current pmap. */ 2512 pmap_tlb_flush_SE(pm, va, oflags); 2513 } 2514 2515 pmap_release_pmap_lock(pm); 2516 pmap_acquire_page_lock(md); 2517 2518 NPDEBUG(PDB_BITS, 2519 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2520 pm, va, opte, npte)); 2521 } 2522 2523 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2524 /* 2525 * If we need to sync the I-cache and we haven't done it yet, do it. 2526 */ 2527 if (need_syncicache) { 2528 pmap_release_page_lock(md); 2529 pmap_syncicache_page(md, pa); 2530 pmap_acquire_page_lock(md); 2531 PMAPCOUNT(exec_synced_clearbit); 2532 } 2533 2534 /* 2535 * If we are changing this to read-only, we need to call vac_me_harder 2536 * so we can change all the read-only pages to cacheable. We pretend 2537 * this as a page deletion. 2538 */ 2539 if (need_vac_me_harder) { 2540 if (md->pvh_attrs & PVF_NC) 2541 pmap_vac_me_harder(md, pa, NULL, 0); 2542 } 2543 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2544 } 2545 2546 /* 2547 * pmap_clean_page() 2548 * 2549 * This is a local function used to work out the best strategy to clean 2550 * a single page referenced by its entry in the PV table. It's used by 2551 * pmap_copy_page, pmap_zero page and maybe some others later on. 2552 * 2553 * Its policy is effectively: 2554 * o If there are no mappings, we don't bother doing anything with the cache. 2555 * o If there is one mapping, we clean just that page. 2556 * o If there are multiple mappings, we clean the entire cache. 2557 * 2558 * So that some functions can be further optimised, it returns 0 if it didn't 2559 * clean the entire cache, or 1 if it did. 2560 * 2561 * XXX One bug in this routine is that if the pv_entry has a single page 2562 * mapped at 0x00000000 a whole cache clean will be performed rather than 2563 * just the 1 page. Since this should not occur in everyday use and if it does 2564 * it will just result in not the most efficient clean for the page. 2565 */ 2566 #ifdef PMAP_CACHE_VIVT 2567 static bool 2568 pmap_clean_page(struct vm_page_md *md, bool is_src) 2569 { 2570 struct pv_entry *pv; 2571 pmap_t pm_to_clean = NULL; 2572 bool cache_needs_cleaning = false; 2573 vaddr_t page_to_clean = 0; 2574 u_int flags = 0; 2575 2576 /* 2577 * Since we flush the cache each time we change to a different 2578 * user vmspace, we only need to flush the page if it is in the 2579 * current pmap. 2580 */ 2581 KASSERT(pmap_page_locked_p(md)); 2582 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2583 if (pmap_is_current(pv->pv_pmap)) { 2584 flags |= pv->pv_flags; 2585 /* 2586 * The page is mapped non-cacheable in 2587 * this map. No need to flush the cache. 2588 */ 2589 if (pv->pv_flags & PVF_NC) { 2590 #ifdef DIAGNOSTIC 2591 KASSERT(!cache_needs_cleaning); 2592 #endif 2593 break; 2594 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2595 continue; 2596 if (cache_needs_cleaning) { 2597 page_to_clean = 0; 2598 break; 2599 } else { 2600 page_to_clean = pv->pv_va; 2601 pm_to_clean = pv->pv_pmap; 2602 } 2603 cache_needs_cleaning = true; 2604 } 2605 } 2606 2607 if (page_to_clean) { 2608 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2609 !is_src, flags | PVF_REF); 2610 } else if (cache_needs_cleaning) { 2611 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2612 2613 pmap_cache_wbinv_all(pm, flags); 2614 return true; 2615 } 2616 return false; 2617 } 2618 #endif 2619 2620 #ifdef PMAP_CACHE_VIPT 2621 /* 2622 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2623 * right cache alias to make sure we flush the right stuff. 2624 */ 2625 void 2626 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2627 { 2628 pmap_t kpm = pmap_kernel(); 2629 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2630 ? PAGE_SIZE 2631 : arm_pcache.icache_way_size; 2632 2633 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2634 md, md->pvh_attrs)); 2635 /* 2636 * No need to clean the page if it's non-cached. 2637 */ 2638 #ifndef ARM_MMU_EXTENDED 2639 if (md->pvh_attrs & PVF_NC) 2640 return; 2641 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2642 #endif 2643 2644 pt_entry_t * const ptep = cpu_cdst_pte(0); 2645 const vaddr_t dstp = cpu_cdstp(0); 2646 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2647 if (way_size <= PAGE_SIZE) { 2648 bool ok = false; 2649 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2650 if (ok) { 2651 cpu_icache_sync_range(vdstp, way_size); 2652 return; 2653 } 2654 } 2655 #endif 2656 2657 /* 2658 * We don't worry about the color of the exec page, we map the 2659 * same page to pages in the way and then do the icache_sync on 2660 * the entire way making sure we are cleaned. 2661 */ 2662 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2663 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2664 2665 for (size_t i = 0, j = 0; i < way_size; 2666 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2667 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2668 /* 2669 * Set up a PTE with to flush these cache lines. 2670 */ 2671 l2pte_set(ptep + j, npte, 0); 2672 } 2673 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2674 2675 /* 2676 * Flush it. 2677 */ 2678 cpu_icache_sync_range(dstp, way_size); 2679 2680 for (size_t i = 0, j = 0; i < way_size; 2681 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2682 /* 2683 * Unmap the page(s). 2684 */ 2685 l2pte_reset(ptep + j); 2686 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2687 } 2688 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2689 2690 md->pvh_attrs |= PVF_EXEC; 2691 PMAPCOUNT(exec_synced); 2692 } 2693 2694 #ifndef ARM_MMU_EXTENDED 2695 void 2696 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2697 { 2698 vsize_t va_offset, end_va; 2699 bool wbinv_p; 2700 2701 if (arm_cache_prefer_mask == 0) 2702 return; 2703 2704 switch (flush) { 2705 case PMAP_FLUSH_PRIMARY: 2706 if (md->pvh_attrs & PVF_MULTCLR) { 2707 va_offset = 0; 2708 end_va = arm_cache_prefer_mask; 2709 md->pvh_attrs &= ~PVF_MULTCLR; 2710 PMAPCOUNT(vac_flush_lots); 2711 } else { 2712 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2713 end_va = va_offset; 2714 PMAPCOUNT(vac_flush_one); 2715 } 2716 /* 2717 * Mark that the page is no longer dirty. 2718 */ 2719 md->pvh_attrs &= ~PVF_DIRTY; 2720 wbinv_p = true; 2721 break; 2722 case PMAP_FLUSH_SECONDARY: 2723 va_offset = 0; 2724 end_va = arm_cache_prefer_mask; 2725 wbinv_p = true; 2726 md->pvh_attrs &= ~PVF_MULTCLR; 2727 PMAPCOUNT(vac_flush_lots); 2728 break; 2729 case PMAP_CLEAN_PRIMARY: 2730 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2731 end_va = va_offset; 2732 wbinv_p = false; 2733 /* 2734 * Mark that the page is no longer dirty. 2735 */ 2736 if ((md->pvh_attrs & PVF_DMOD) == 0) 2737 md->pvh_attrs &= ~PVF_DIRTY; 2738 PMAPCOUNT(vac_clean_one); 2739 break; 2740 default: 2741 return; 2742 } 2743 2744 KASSERT(!(md->pvh_attrs & PVF_NC)); 2745 2746 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2747 md, md->pvh_attrs)); 2748 2749 const size_t scache_line_size = arm_scache.dcache_line_size; 2750 2751 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2752 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2753 const vaddr_t dstp = cpu_cdstp(va_offset); 2754 const pt_entry_t opte = *ptep; 2755 2756 if (flush == PMAP_FLUSH_SECONDARY 2757 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2758 continue; 2759 2760 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2761 /* 2762 * Set up a PTE with the right coloring to flush 2763 * existing cache entries. 2764 */ 2765 const pt_entry_t npte = L2_S_PROTO 2766 | pa 2767 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2768 | pte_l2_s_cache_mode; 2769 l2pte_set(ptep, npte, opte); 2770 PTE_SYNC(ptep); 2771 2772 /* 2773 * Flush it. Make sure to flush secondary cache too since 2774 * bus_dma will ignore uncached pages. 2775 */ 2776 if (scache_line_size != 0) { 2777 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2778 if (wbinv_p) { 2779 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2780 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2781 } else { 2782 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2783 } 2784 } else { 2785 if (wbinv_p) { 2786 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2787 } else { 2788 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2789 } 2790 } 2791 2792 /* 2793 * Restore the page table entry since we might have interrupted 2794 * pmap_zero_page or pmap_copy_page which was already using 2795 * this pte. 2796 */ 2797 if (opte) { 2798 l2pte_set(ptep, opte, npte); 2799 } else { 2800 l2pte_reset(ptep); 2801 } 2802 PTE_SYNC(ptep); 2803 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2804 } 2805 } 2806 #endif /* ARM_MMU_EXTENDED */ 2807 #endif /* PMAP_CACHE_VIPT */ 2808 2809 /* 2810 * Routine: pmap_page_remove 2811 * Function: 2812 * Removes this physical page from 2813 * all physical maps in which it resides. 2814 * Reflects back modify bits to the pager. 2815 */ 2816 static void 2817 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2818 { 2819 struct l2_bucket *l2b; 2820 struct pv_entry *pv; 2821 pt_entry_t *ptep; 2822 #ifndef ARM_MMU_EXTENDED 2823 bool flush = false; 2824 #endif 2825 u_int flags = 0; 2826 2827 NPDEBUG(PDB_FOLLOW, 2828 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2829 pa)); 2830 2831 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2832 pmap_acquire_page_lock(md); 2833 if (*pvp == NULL) { 2834 #ifdef PMAP_CACHE_VIPT 2835 /* 2836 * We *know* the page contents are about to be replaced. 2837 * Discard the exec contents 2838 */ 2839 if (PV_IS_EXEC_P(md->pvh_attrs)) 2840 PMAPCOUNT(exec_discarded_page_protect); 2841 md->pvh_attrs &= ~PVF_EXEC; 2842 PMAP_VALIDATE_MD_PAGE(md); 2843 #endif 2844 pmap_release_page_lock(md); 2845 return; 2846 } 2847 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2848 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2849 #endif 2850 2851 /* 2852 * Clear alias counts 2853 */ 2854 #ifdef PMAP_CACHE_VIVT 2855 md->k_mappings = 0; 2856 #endif 2857 md->urw_mappings = md->uro_mappings = 0; 2858 2859 #ifdef PMAP_CACHE_VIVT 2860 pmap_clean_page(md, false); 2861 #endif 2862 2863 while ((pv = *pvp) != NULL) { 2864 pmap_t pm = pv->pv_pmap; 2865 #ifndef ARM_MMU_EXTENDED 2866 if (flush == false && pmap_is_current(pm)) 2867 flush = true; 2868 #endif 2869 2870 if (pm == pmap_kernel()) { 2871 #ifdef PMAP_CACHE_VIPT 2872 /* 2873 * If this was unmanaged mapping, it must be preserved. 2874 * Move it back on the list and advance the end-of-list 2875 * pointer. 2876 */ 2877 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2878 *pvp = pv; 2879 pvp = &SLIST_NEXT(pv, pv_link); 2880 continue; 2881 } 2882 if (pv->pv_flags & PVF_WRITE) 2883 md->krw_mappings--; 2884 else 2885 md->kro_mappings--; 2886 #endif 2887 PMAPCOUNT(kernel_unmappings); 2888 } 2889 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2890 PMAPCOUNT(unmappings); 2891 2892 pmap_release_page_lock(md); 2893 pmap_acquire_pmap_lock(pm); 2894 2895 #ifdef ARM_MMU_EXTENDED 2896 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2897 #endif 2898 2899 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2900 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2901 2902 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2903 2904 /* 2905 * Update statistics 2906 */ 2907 --pm->pm_stats.resident_count; 2908 2909 /* Wired bit */ 2910 if (pv->pv_flags & PVF_WIRED) 2911 --pm->pm_stats.wired_count; 2912 2913 flags |= pv->pv_flags; 2914 2915 /* 2916 * Invalidate the PTEs. 2917 */ 2918 l2pte_reset(ptep); 2919 PTE_SYNC_CURRENT(pm, ptep); 2920 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2921 pmap_release_pmap_lock(pm); 2922 2923 pool_put(&pmap_pv_pool, pv); 2924 pmap_acquire_page_lock(md); 2925 #ifdef MULTIPROCESSOR 2926 /* 2927 * Restart of the beginning of the list. 2928 */ 2929 pvp = &SLIST_FIRST(&md->pvh_list); 2930 #endif 2931 } 2932 /* 2933 * if we reach the end of the list and there are still mappings, they 2934 * might be able to be cached now. And they must be kernel mappings. 2935 */ 2936 if (!SLIST_EMPTY(&md->pvh_list)) { 2937 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2938 } 2939 2940 #ifdef PMAP_CACHE_VIPT 2941 /* 2942 * Its EXEC cache is now gone. 2943 */ 2944 if (PV_IS_EXEC_P(md->pvh_attrs)) 2945 PMAPCOUNT(exec_discarded_page_protect); 2946 md->pvh_attrs &= ~PVF_EXEC; 2947 KASSERT(md->urw_mappings == 0); 2948 KASSERT(md->uro_mappings == 0); 2949 #ifndef ARM_MMU_EXTENDED 2950 if (arm_cache_prefer_mask != 0) { 2951 if (md->krw_mappings == 0) 2952 md->pvh_attrs &= ~PVF_WRITE; 2953 PMAP_VALIDATE_MD_PAGE(md); 2954 } 2955 #endif /* ARM_MMU_EXTENDED */ 2956 #endif /* PMAP_CACHE_VIPT */ 2957 pmap_release_page_lock(md); 2958 2959 #ifndef ARM_MMU_EXTENDED 2960 if (flush) { 2961 /* 2962 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2963 * would need a subsequent call to pmap_update() to ensure 2964 * curpm->pm_cstate.cs_all is reset. Our callers are not 2965 * required to do that (see pmap(9)), so we can't modify 2966 * the current pmap's state. 2967 */ 2968 if (PV_BEEN_EXECD(flags)) 2969 cpu_tlb_flushID(); 2970 else 2971 cpu_tlb_flushD(); 2972 } 2973 cpu_cpwait(); 2974 #endif /* ARM_MMU_EXTENDED */ 2975 } 2976 2977 /* 2978 * pmap_t pmap_create(void) 2979 * 2980 * Create a new pmap structure from scratch. 2981 */ 2982 pmap_t 2983 pmap_create(void) 2984 { 2985 pmap_t pm; 2986 2987 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2988 2989 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2990 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2991 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2992 2993 pm->pm_stats.wired_count = 0; 2994 pm->pm_stats.resident_count = 1; 2995 #ifdef ARM_MMU_EXTENDED 2996 #ifdef MULTIPROCESSOR 2997 kcpuset_create(&pm->pm_active, true); 2998 kcpuset_create(&pm->pm_onproc, true); 2999 #endif 3000 #else 3001 pm->pm_cstate.cs_all = 0; 3002 #endif 3003 pmap_alloc_l1(pm); 3004 3005 /* 3006 * Note: The pool cache ensures that the pm_l2[] array is already 3007 * initialised to zero. 3008 */ 3009 3010 pmap_pinit(pm); 3011 3012 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3013 3014 return (pm); 3015 } 3016 3017 u_int 3018 arm32_mmap_flags(paddr_t pa) 3019 { 3020 /* 3021 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3022 * and we're using the upper bits in page numbers to pass flags around 3023 * so we might as well use the same bits 3024 */ 3025 return (u_int)pa & PMAP_MD_MASK; 3026 } 3027 /* 3028 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3029 * u_int flags) 3030 * 3031 * Insert the given physical page (p) at 3032 * the specified virtual address (v) in the 3033 * target physical map with the protection requested. 3034 * 3035 * NB: This is the only routine which MAY NOT lazy-evaluate 3036 * or lose information. That is, this routine must actually 3037 * insert this page into the given map NOW. 3038 */ 3039 int 3040 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3041 { 3042 struct l2_bucket *l2b; 3043 struct vm_page *pg, *opg; 3044 u_int nflags; 3045 u_int oflags; 3046 const bool kpm_p = (pm == pmap_kernel()); 3047 #ifdef ARM_HAS_VBAR 3048 const bool vector_page_p = false; 3049 #else 3050 const bool vector_page_p = (va == vector_page); 3051 #endif 3052 3053 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3054 3055 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3056 pm, va, pa, prot); 3057 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3058 3059 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3060 KDASSERT(((va | pa) & PGOFSET) == 0); 3061 3062 /* 3063 * Get a pointer to the page. Later on in this function, we 3064 * test for a managed page by checking pg != NULL. 3065 */ 3066 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3067 3068 nflags = 0; 3069 if (prot & VM_PROT_WRITE) 3070 nflags |= PVF_WRITE; 3071 if (prot & VM_PROT_EXECUTE) 3072 nflags |= PVF_EXEC; 3073 if (flags & PMAP_WIRED) 3074 nflags |= PVF_WIRED; 3075 3076 pmap_acquire_pmap_lock(pm); 3077 3078 /* 3079 * Fetch the L2 bucket which maps this page, allocating one if 3080 * necessary for user pmaps. 3081 */ 3082 if (kpm_p) { 3083 l2b = pmap_get_l2_bucket(pm, va); 3084 } else { 3085 l2b = pmap_alloc_l2_bucket(pm, va); 3086 } 3087 if (l2b == NULL) { 3088 if (flags & PMAP_CANFAIL) { 3089 pmap_release_pmap_lock(pm); 3090 return (ENOMEM); 3091 } 3092 panic("pmap_enter: failed to allocate L2 bucket"); 3093 } 3094 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3095 const pt_entry_t opte = *ptep; 3096 pt_entry_t npte = pa; 3097 oflags = 0; 3098 3099 if (opte) { 3100 /* 3101 * There is already a mapping at this address. 3102 * If the physical address is different, lookup the 3103 * vm_page. 3104 */ 3105 if (l2pte_pa(opte) != pa) 3106 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3107 else 3108 opg = pg; 3109 } else 3110 opg = NULL; 3111 3112 if (pg) { 3113 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3114 3115 /* 3116 * This is to be a managed mapping. 3117 */ 3118 pmap_acquire_page_lock(md); 3119 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3120 /* 3121 * - The access type indicates that we don't need 3122 * to do referenced emulation. 3123 * OR 3124 * - The physical page has already been referenced 3125 * so no need to re-do referenced emulation here. 3126 */ 3127 npte |= l2pte_set_readonly(L2_S_PROTO); 3128 3129 nflags |= PVF_REF; 3130 3131 if ((prot & VM_PROT_WRITE) != 0 && 3132 ((flags & VM_PROT_WRITE) != 0 || 3133 (md->pvh_attrs & PVF_MOD) != 0)) { 3134 /* 3135 * This is a writable mapping, and the 3136 * page's mod state indicates it has 3137 * already been modified. Make it 3138 * writable from the outset. 3139 */ 3140 npte = l2pte_set_writable(npte); 3141 nflags |= PVF_MOD; 3142 } 3143 3144 #ifdef ARM_MMU_EXTENDED 3145 /* 3146 * If the page has been cleaned, then the pvh_attrs 3147 * will have PVF_EXEC set, so mark it execute so we 3148 * don't get an access fault when trying to execute 3149 * from it. 3150 */ 3151 if (md->pvh_attrs & nflags & PVF_EXEC) { 3152 npte &= ~L2_XS_XN; 3153 } 3154 #endif 3155 } else { 3156 /* 3157 * Need to do page referenced emulation. 3158 */ 3159 npte |= L2_TYPE_INV; 3160 } 3161 3162 if (flags & ARM32_MMAP_WRITECOMBINE) { 3163 npte |= pte_l2_s_wc_mode; 3164 } else 3165 npte |= pte_l2_s_cache_mode; 3166 3167 if (pg == opg) { 3168 /* 3169 * We're changing the attrs of an existing mapping. 3170 */ 3171 oflags = pmap_modify_pv(md, pa, pm, va, 3172 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3173 PVF_MOD | PVF_REF, nflags); 3174 3175 #ifdef PMAP_CACHE_VIVT 3176 /* 3177 * We may need to flush the cache if we're 3178 * doing rw-ro... 3179 */ 3180 if (pm->pm_cstate.cs_cache_d && 3181 (oflags & PVF_NC) == 0 && 3182 l2pte_writable_p(opte) && 3183 (prot & VM_PROT_WRITE) == 0) 3184 cpu_dcache_wb_range(va, PAGE_SIZE); 3185 #endif 3186 } else { 3187 struct pv_entry *pv; 3188 /* 3189 * New mapping, or changing the backing page 3190 * of an existing mapping. 3191 */ 3192 if (opg) { 3193 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3194 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3195 3196 /* 3197 * Replacing an existing mapping with a new one. 3198 * It is part of our managed memory so we 3199 * must remove it from the PV list 3200 */ 3201 pv = pmap_remove_pv(omd, opa, pm, va); 3202 pmap_vac_me_harder(omd, opa, pm, 0); 3203 oflags = pv->pv_flags; 3204 3205 #ifdef PMAP_CACHE_VIVT 3206 /* 3207 * If the old mapping was valid (ref/mod 3208 * emulation creates 'invalid' mappings 3209 * initially) then make sure to frob 3210 * the cache. 3211 */ 3212 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3213 pmap_cache_wbinv_page(pm, va, true, 3214 oflags); 3215 } 3216 #endif 3217 } else { 3218 pmap_release_page_lock(md); 3219 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3220 if (pv == NULL) { 3221 pmap_release_pmap_lock(pm); 3222 if ((flags & PMAP_CANFAIL) == 0) 3223 panic("pmap_enter: " 3224 "no pv entries"); 3225 3226 pmap_free_l2_bucket(pm, l2b, 0); 3227 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3228 0, 0, 0, 0); 3229 return (ENOMEM); 3230 } 3231 pmap_acquire_page_lock(md); 3232 } 3233 3234 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3235 } 3236 pmap_release_page_lock(md); 3237 } else { 3238 /* 3239 * We're mapping an unmanaged page. 3240 * These are always readable, and possibly writable, from 3241 * the get go as we don't need to track ref/mod status. 3242 */ 3243 npte |= l2pte_set_readonly(L2_S_PROTO); 3244 if (prot & VM_PROT_WRITE) 3245 npte = l2pte_set_writable(npte); 3246 3247 /* 3248 * Make sure the vector table is mapped cacheable 3249 */ 3250 if ((vector_page_p && !kpm_p) 3251 || (flags & ARM32_MMAP_CACHEABLE)) { 3252 npte |= pte_l2_s_cache_mode; 3253 #ifdef ARM_MMU_EXTENDED 3254 npte &= ~L2_XS_XN; /* and executable */ 3255 #endif 3256 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3257 npte |= pte_l2_s_wc_mode; 3258 } 3259 if (opg) { 3260 /* 3261 * Looks like there's an existing 'managed' mapping 3262 * at this address. 3263 */ 3264 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3265 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3266 3267 pmap_acquire_page_lock(omd); 3268 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3269 pmap_vac_me_harder(omd, opa, pm, 0); 3270 oflags = pv->pv_flags; 3271 pmap_release_page_lock(omd); 3272 3273 #ifdef PMAP_CACHE_VIVT 3274 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3275 pmap_cache_wbinv_page(pm, va, true, oflags); 3276 } 3277 #endif 3278 pool_put(&pmap_pv_pool, pv); 3279 } 3280 } 3281 3282 /* 3283 * Make sure userland mappings get the right permissions 3284 */ 3285 if (!vector_page_p && !kpm_p) { 3286 npte |= L2_S_PROT_U; 3287 #ifdef ARM_MMU_EXTENDED 3288 npte |= L2_XS_nG; /* user pages are not global */ 3289 #endif 3290 } 3291 3292 /* 3293 * Keep the stats up to date 3294 */ 3295 if (opte == 0) { 3296 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3297 pm->pm_stats.resident_count++; 3298 } 3299 3300 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3301 3302 #if defined(ARM_MMU_EXTENDED) 3303 /* 3304 * If exec protection was requested but the page hasn't been synced, 3305 * sync it now and allow execution from it. 3306 */ 3307 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3308 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3309 npte &= ~L2_XS_XN; 3310 pmap_syncicache_page(md, pa); 3311 PMAPCOUNT(exec_synced_map); 3312 } 3313 #endif 3314 /* 3315 * If this is just a wiring change, the two PTEs will be 3316 * identical, so there's no need to update the page table. 3317 */ 3318 if (npte != opte) { 3319 3320 l2pte_set(ptep, npte, opte); 3321 PTE_SYNC(ptep); 3322 #ifndef ARM_MMU_EXTENDED 3323 bool is_cached = pmap_is_cached(pm); 3324 if (is_cached) { 3325 /* 3326 * We only need to frob the cache/tlb if this pmap 3327 * is current 3328 */ 3329 if (!vector_page_p && l2pte_valid_p(npte)) { 3330 /* 3331 * This mapping is likely to be accessed as 3332 * soon as we return to userland. Fix up the 3333 * L1 entry to avoid taking another 3334 * page/domain fault. 3335 */ 3336 pd_entry_t *pdep = pmap_l1_kva(pm) 3337 + l1pte_index(va); 3338 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3339 | L1_C_DOM(pmap_domain(pm)); 3340 if (*pdep != pde) { 3341 l1pte_setone(pdep, pde); 3342 PTE_SYNC(pdep); 3343 } 3344 } 3345 } 3346 #endif /* !ARMM_MMU_EXTENDED */ 3347 3348 pmap_tlb_flush_SE(pm, va, oflags); 3349 3350 #ifndef ARM_MMU_EXTENDED 3351 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3352 is_cached, pm->pm_cstate.cs_all, 0, 0); 3353 3354 if (pg != NULL) { 3355 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3356 3357 pmap_acquire_page_lock(md); 3358 pmap_vac_me_harder(md, pa, pm, va); 3359 pmap_release_page_lock(md); 3360 } 3361 #endif 3362 } 3363 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3364 if (pg) { 3365 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3366 3367 pmap_acquire_page_lock(md); 3368 #ifndef ARM_MMU_EXTENDED 3369 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3370 #endif 3371 PMAP_VALIDATE_MD_PAGE(md); 3372 pmap_release_page_lock(md); 3373 } 3374 #endif 3375 3376 pmap_release_pmap_lock(pm); 3377 3378 return (0); 3379 } 3380 3381 /* 3382 * pmap_remove() 3383 * 3384 * pmap_remove is responsible for nuking a number of mappings for a range 3385 * of virtual address space in the current pmap. To do this efficiently 3386 * is interesting, because in a number of cases a wide virtual address 3387 * range may be supplied that contains few actual mappings. So, the 3388 * optimisations are: 3389 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3390 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3391 * maybe do just a partial cache clean. This path of execution is 3392 * complicated by the fact that the cache must be flushed _before_ 3393 * the PTE is nuked, being a VAC :-) 3394 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3395 * all invalidations until pmap_update(), since pmap_remove_all() has 3396 * already flushed the cache. 3397 * 4. Maybe later fast-case a single page, but I don't think this is 3398 * going to make _that_ much difference overall. 3399 */ 3400 3401 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3402 3403 void 3404 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3405 { 3406 vaddr_t next_bucket; 3407 u_int cleanlist_idx, total, cnt; 3408 struct { 3409 vaddr_t va; 3410 pt_entry_t *ptep; 3411 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3412 u_int mappings; 3413 3414 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3415 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3416 3417 /* 3418 * we lock in the pmap => pv_head direction 3419 */ 3420 pmap_acquire_pmap_lock(pm); 3421 3422 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3423 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3424 #ifndef ARM_MMU_EXTENDED 3425 if (pm->pm_cstate.cs_tlb == 0) 3426 pm->pm_remove_all = true; 3427 #endif 3428 } else 3429 cleanlist_idx = 0; 3430 3431 total = 0; 3432 3433 while (sva < eva) { 3434 /* 3435 * Do one L2 bucket's worth at a time. 3436 */ 3437 next_bucket = L2_NEXT_BUCKET_VA(sva); 3438 if (next_bucket > eva) 3439 next_bucket = eva; 3440 3441 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3442 if (l2b == NULL) { 3443 sva = next_bucket; 3444 continue; 3445 } 3446 3447 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3448 3449 for (mappings = 0; 3450 sva < next_bucket; 3451 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3452 pt_entry_t opte = *ptep; 3453 3454 if (opte == 0) { 3455 /* Nothing here, move along */ 3456 continue; 3457 } 3458 3459 u_int flags = PVF_REF; 3460 paddr_t pa = l2pte_pa(opte); 3461 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3462 3463 /* 3464 * Update flags. In a number of circumstances, 3465 * we could cluster a lot of these and do a 3466 * number of sequential pages in one go. 3467 */ 3468 if (pg != NULL) { 3469 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3470 struct pv_entry *pv; 3471 3472 pmap_acquire_page_lock(md); 3473 pv = pmap_remove_pv(md, pa, pm, sva); 3474 pmap_vac_me_harder(md, pa, pm, 0); 3475 pmap_release_page_lock(md); 3476 if (pv != NULL) { 3477 if (pm->pm_remove_all == false) { 3478 flags = pv->pv_flags; 3479 } 3480 pool_put(&pmap_pv_pool, pv); 3481 } 3482 } 3483 mappings += PAGE_SIZE / L2_S_SIZE; 3484 3485 if (!l2pte_valid_p(opte)) { 3486 /* 3487 * Ref/Mod emulation is still active for this 3488 * mapping, therefore it is has not yet been 3489 * accessed. No need to frob the cache/tlb. 3490 */ 3491 l2pte_reset(ptep); 3492 PTE_SYNC_CURRENT(pm, ptep); 3493 continue; 3494 } 3495 3496 #ifdef ARM_MMU_EXTENDED 3497 if (pm == pmap_kernel()) { 3498 l2pte_reset(ptep); 3499 PTE_SYNC(ptep); 3500 pmap_tlb_flush_SE(pm, sva, flags); 3501 continue; 3502 } 3503 #endif 3504 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3505 /* Add to the clean list. */ 3506 cleanlist[cleanlist_idx].ptep = ptep; 3507 cleanlist[cleanlist_idx].va = 3508 sva | (flags & PVF_EXEC); 3509 cleanlist_idx++; 3510 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3511 /* Nuke everything if needed. */ 3512 #ifdef PMAP_CACHE_VIVT 3513 pmap_cache_wbinv_all(pm, PVF_EXEC); 3514 #endif 3515 /* 3516 * Roll back the previous PTE list, 3517 * and zero out the current PTE. 3518 */ 3519 for (cnt = 0; 3520 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3521 l2pte_reset(cleanlist[cnt].ptep); 3522 PTE_SYNC(cleanlist[cnt].ptep); 3523 } 3524 l2pte_reset(ptep); 3525 PTE_SYNC(ptep); 3526 cleanlist_idx++; 3527 pm->pm_remove_all = true; 3528 } else { 3529 l2pte_reset(ptep); 3530 PTE_SYNC(ptep); 3531 if (pm->pm_remove_all == false) { 3532 pmap_tlb_flush_SE(pm, sva, flags); 3533 } 3534 } 3535 } 3536 3537 /* 3538 * Deal with any left overs 3539 */ 3540 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3541 total += cleanlist_idx; 3542 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3543 #ifdef ARM_MMU_EXTENDED 3544 vaddr_t clva = cleanlist[cnt].va; 3545 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3546 #else 3547 vaddr_t va = cleanlist[cnt].va; 3548 if (pm->pm_cstate.cs_all != 0) { 3549 vaddr_t clva = va & ~PAGE_MASK; 3550 u_int flags = va & PVF_EXEC; 3551 #ifdef PMAP_CACHE_VIVT 3552 pmap_cache_wbinv_page(pm, clva, true, 3553 PVF_REF | PVF_WRITE | flags); 3554 #endif 3555 pmap_tlb_flush_SE(pm, clva, 3556 PVF_REF | flags); 3557 } 3558 #endif /* ARM_MMU_EXTENDED */ 3559 l2pte_reset(cleanlist[cnt].ptep); 3560 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3561 } 3562 3563 /* 3564 * If it looks like we're removing a whole bunch 3565 * of mappings, it's faster to just write-back 3566 * the whole cache now and defer TLB flushes until 3567 * pmap_update() is called. 3568 */ 3569 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3570 cleanlist_idx = 0; 3571 else { 3572 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3573 #ifdef PMAP_CACHE_VIVT 3574 pmap_cache_wbinv_all(pm, PVF_EXEC); 3575 #endif 3576 pm->pm_remove_all = true; 3577 } 3578 } 3579 3580 3581 pmap_free_l2_bucket(pm, l2b, mappings); 3582 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3583 } 3584 3585 pmap_release_pmap_lock(pm); 3586 } 3587 3588 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3589 static struct pv_entry * 3590 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3591 { 3592 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3593 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3594 struct pv_entry *pv; 3595 3596 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3597 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3598 KASSERT(pmap_page_locked_p(md)); 3599 3600 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3601 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3602 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3603 3604 /* 3605 * If we are removing a writeable mapping to a cached exec page, 3606 * if it's the last mapping then clear it execness other sync 3607 * the page to the icache. 3608 */ 3609 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3610 && (pv->pv_flags & PVF_WRITE) != 0) { 3611 if (SLIST_EMPTY(&md->pvh_list)) { 3612 md->pvh_attrs &= ~PVF_EXEC; 3613 PMAPCOUNT(exec_discarded_kremove); 3614 } else { 3615 pmap_syncicache_page(md, pa); 3616 PMAPCOUNT(exec_synced_kremove); 3617 } 3618 } 3619 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3620 3621 return pv; 3622 } 3623 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3624 3625 /* 3626 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3627 * 3628 * We assume there is already sufficient KVM space available 3629 * to do this, as we can't allocate L2 descriptor tables/metadata 3630 * from here. 3631 */ 3632 void 3633 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3634 { 3635 #ifdef PMAP_CACHE_VIVT 3636 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3637 #endif 3638 #ifdef PMAP_CACHE_VIPT 3639 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3640 struct vm_page *opg; 3641 #ifndef ARM_MMU_EXTENDED 3642 struct pv_entry *pv = NULL; 3643 #endif 3644 #endif 3645 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3646 3647 UVMHIST_FUNC(__func__); 3648 3649 if (pmap_initialized) { 3650 UVMHIST_CALLED(maphist); 3651 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3652 va, pa, prot, flags); 3653 } 3654 3655 pmap_t kpm = pmap_kernel(); 3656 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3657 const size_t l1slot __diagused = l1pte_index(va); 3658 KASSERTMSG(l2b != NULL, 3659 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3660 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3661 kpm->pm_l2[L2_IDX(l1slot)] 3662 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3663 : NULL, 3664 kpm->pm_l2[L2_IDX(l1slot)] 3665 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3666 : NULL); 3667 KASSERT(l2b->l2b_kva != NULL); 3668 3669 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3670 const pt_entry_t opte = *ptep; 3671 3672 if (opte == 0) { 3673 PMAPCOUNT(kenter_mappings); 3674 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3675 } else { 3676 PMAPCOUNT(kenter_remappings); 3677 #ifdef PMAP_CACHE_VIPT 3678 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3679 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3680 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3681 #endif 3682 if (opg && arm_cache_prefer_mask != 0) { 3683 KASSERT(opg != pg); 3684 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3685 KASSERT((flags & PMAP_KMPAGE) == 0); 3686 #ifndef ARM_MMU_EXTENDED 3687 pmap_acquire_page_lock(omd); 3688 pv = pmap_kremove_pg(opg, va); 3689 pmap_release_page_lock(omd); 3690 #endif 3691 } 3692 #endif 3693 if (l2pte_valid_p(opte)) { 3694 #ifdef PMAP_CACHE_VIVT 3695 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3696 #endif 3697 cpu_tlb_flushD_SE(va); 3698 cpu_cpwait(); 3699 } 3700 } 3701 3702 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3703 | ((flags & PMAP_NOCACHE) 3704 ? 0 3705 : ((flags & PMAP_PTE) 3706 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3707 #ifdef ARM_MMU_EXTENDED 3708 if (prot & VM_PROT_EXECUTE) 3709 npte &= ~L2_XS_XN; 3710 #endif 3711 l2pte_set(ptep, npte, opte); 3712 PTE_SYNC(ptep); 3713 3714 if (pg) { 3715 if (flags & PMAP_KMPAGE) { 3716 KASSERT(md->urw_mappings == 0); 3717 KASSERT(md->uro_mappings == 0); 3718 KASSERT(md->krw_mappings == 0); 3719 KASSERT(md->kro_mappings == 0); 3720 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3721 KASSERT(pv == NULL); 3722 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3723 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3724 /* if there is a color conflict, evict from cache. */ 3725 if (pmap_is_page_colored_p(md) 3726 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3727 PMAPCOUNT(vac_color_change); 3728 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3729 } else if (md->pvh_attrs & PVF_MULTCLR) { 3730 /* 3731 * If this page has multiple colors, expunge 3732 * them. 3733 */ 3734 PMAPCOUNT(vac_flush_lots2); 3735 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3736 } 3737 /* 3738 * Since this is a KMPAGE, there can be no contention 3739 * for this page so don't lock it. 3740 */ 3741 md->pvh_attrs &= PAGE_SIZE - 1; 3742 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3743 | (va & arm_cache_prefer_mask); 3744 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3745 md->pvh_attrs |= PVF_KMPAGE; 3746 #endif 3747 atomic_inc_32(&pmap_kmpages); 3748 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3749 } else if (arm_cache_prefer_mask != 0) { 3750 if (pv == NULL) { 3751 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3752 KASSERT(pv != NULL); 3753 } 3754 pmap_acquire_page_lock(md); 3755 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3756 PVF_WIRED | PVF_KENTRY 3757 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3758 if ((prot & VM_PROT_WRITE) 3759 && !(md->pvh_attrs & PVF_NC)) 3760 md->pvh_attrs |= PVF_DIRTY; 3761 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3762 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3763 pmap_release_page_lock(md); 3764 #endif 3765 } 3766 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3767 } else { 3768 if (pv != NULL) 3769 pool_put(&pmap_pv_pool, pv); 3770 #endif 3771 } 3772 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3773 if (pmap_initialized) { 3774 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3775 ptep, opte, npte, 0); 3776 } 3777 3778 } 3779 3780 void 3781 pmap_kremove(vaddr_t va, vsize_t len) 3782 { 3783 #ifdef UVMHIST 3784 u_int total_mappings = 0; 3785 #endif 3786 3787 PMAPCOUNT(kenter_unmappings); 3788 3789 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3790 3791 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3792 3793 const vaddr_t eva = va + len; 3794 3795 while (va < eva) { 3796 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3797 if (next_bucket > eva) 3798 next_bucket = eva; 3799 3800 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3801 KDASSERT(l2b != NULL); 3802 3803 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3804 pt_entry_t *ptep = sptep; 3805 u_int mappings = 0; 3806 3807 while (va < next_bucket) { 3808 const pt_entry_t opte = *ptep; 3809 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3810 if (opg != NULL) { 3811 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3812 3813 if (omd->pvh_attrs & PVF_KMPAGE) { 3814 KASSERT(omd->urw_mappings == 0); 3815 KASSERT(omd->uro_mappings == 0); 3816 KASSERT(omd->krw_mappings == 0); 3817 KASSERT(omd->kro_mappings == 0); 3818 omd->pvh_attrs &= ~PVF_KMPAGE; 3819 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3820 if (arm_cache_prefer_mask != 0) { 3821 omd->pvh_attrs &= ~PVF_WRITE; 3822 } 3823 #endif 3824 atomic_dec_32(&pmap_kmpages); 3825 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3826 } else if (arm_cache_prefer_mask != 0) { 3827 pmap_acquire_page_lock(omd); 3828 pool_put(&pmap_pv_pool, 3829 pmap_kremove_pg(opg, va)); 3830 pmap_release_page_lock(omd); 3831 #endif 3832 } 3833 } 3834 if (l2pte_valid_p(opte)) { 3835 #ifdef PMAP_CACHE_VIVT 3836 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3837 #endif 3838 cpu_tlb_flushD_SE(va); 3839 } 3840 if (opte) { 3841 l2pte_reset(ptep); 3842 mappings += PAGE_SIZE / L2_S_SIZE; 3843 } 3844 va += PAGE_SIZE; 3845 ptep += PAGE_SIZE / L2_S_SIZE; 3846 } 3847 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3848 mappings, l2b->l2b_occupancy); 3849 l2b->l2b_occupancy -= mappings; 3850 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3851 #ifdef UVMHIST 3852 total_mappings += mappings; 3853 #endif 3854 } 3855 cpu_cpwait(); 3856 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3857 total_mappings, 0, 0, 0); 3858 } 3859 3860 bool 3861 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3862 { 3863 struct l2_dtable *l2; 3864 pd_entry_t *pdep, pde; 3865 pt_entry_t *ptep, pte; 3866 paddr_t pa; 3867 u_int l1slot; 3868 3869 pmap_acquire_pmap_lock(pm); 3870 3871 l1slot = l1pte_index(va); 3872 pdep = pmap_l1_kva(pm) + l1slot; 3873 pde = *pdep; 3874 3875 if (l1pte_section_p(pde)) { 3876 /* 3877 * These should only happen for pmap_kernel() 3878 */ 3879 KDASSERT(pm == pmap_kernel()); 3880 pmap_release_pmap_lock(pm); 3881 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3882 if (l1pte_supersection_p(pde)) { 3883 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3884 } else 3885 #endif 3886 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3887 } else { 3888 /* 3889 * Note that we can't rely on the validity of the L1 3890 * descriptor as an indication that a mapping exists. 3891 * We have to look it up in the L2 dtable. 3892 */ 3893 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3894 3895 if (l2 == NULL || 3896 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3897 pmap_release_pmap_lock(pm); 3898 return false; 3899 } 3900 3901 pte = ptep[l2pte_index(va)]; 3902 pmap_release_pmap_lock(pm); 3903 3904 if (pte == 0) 3905 return false; 3906 3907 switch (pte & L2_TYPE_MASK) { 3908 case L2_TYPE_L: 3909 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3910 break; 3911 3912 default: 3913 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3914 break; 3915 } 3916 } 3917 3918 if (pap != NULL) 3919 *pap = pa; 3920 3921 return true; 3922 } 3923 3924 void 3925 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3926 { 3927 struct l2_bucket *l2b; 3928 vaddr_t next_bucket; 3929 3930 NPDEBUG(PDB_PROTECT, 3931 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3932 pm, sva, eva, prot)); 3933 3934 if ((prot & VM_PROT_READ) == 0) { 3935 pmap_remove(pm, sva, eva); 3936 return; 3937 } 3938 3939 if (prot & VM_PROT_WRITE) { 3940 /* 3941 * If this is a read->write transition, just ignore it and let 3942 * uvm_fault() take care of it later. 3943 */ 3944 return; 3945 } 3946 3947 pmap_acquire_pmap_lock(pm); 3948 3949 const bool flush = eva - sva >= PAGE_SIZE * 4; 3950 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3951 u_int flags = 0; 3952 3953 while (sva < eva) { 3954 next_bucket = L2_NEXT_BUCKET_VA(sva); 3955 if (next_bucket > eva) 3956 next_bucket = eva; 3957 3958 l2b = pmap_get_l2_bucket(pm, sva); 3959 if (l2b == NULL) { 3960 sva = next_bucket; 3961 continue; 3962 } 3963 3964 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3965 3966 while (sva < next_bucket) { 3967 const pt_entry_t opte = *ptep; 3968 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3969 struct vm_page *pg; 3970 u_int f; 3971 3972 #ifdef PMAP_CACHE_VIVT 3973 /* 3974 * OK, at this point, we know we're doing 3975 * write-protect operation. If the pmap is 3976 * active, write-back the page. 3977 */ 3978 pmap_cache_wbinv_page(pm, sva, false, 3979 PVF_REF | PVF_WRITE); 3980 #endif 3981 3982 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3983 pt_entry_t npte = l2pte_set_readonly(opte); 3984 l2pte_set(ptep, npte, opte); 3985 PTE_SYNC(ptep); 3986 3987 if (pg != NULL) { 3988 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3989 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3990 3991 pmap_acquire_page_lock(md); 3992 f = pmap_modify_pv(md, pa, pm, sva, 3993 clr_mask, 0); 3994 pmap_vac_me_harder(md, pa, pm, sva); 3995 pmap_release_page_lock(md); 3996 } else { 3997 f = PVF_REF | PVF_EXEC; 3998 } 3999 4000 if (flush) { 4001 flags |= f; 4002 } else { 4003 pmap_tlb_flush_SE(pm, sva, f); 4004 } 4005 } 4006 4007 sva += PAGE_SIZE; 4008 ptep += PAGE_SIZE / L2_S_SIZE; 4009 } 4010 } 4011 4012 if (flush) { 4013 if (PV_BEEN_EXECD(flags)) { 4014 pmap_tlb_flushID(pm); 4015 } else if (PV_BEEN_REFD(flags)) { 4016 pmap_tlb_flushD(pm); 4017 } 4018 } 4019 4020 pmap_release_pmap_lock(pm); 4021 } 4022 4023 void 4024 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4025 { 4026 struct l2_bucket *l2b; 4027 pt_entry_t *ptep; 4028 vaddr_t next_bucket; 4029 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4030 4031 NPDEBUG(PDB_EXEC, 4032 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4033 pm, sva, eva)); 4034 4035 pmap_acquire_pmap_lock(pm); 4036 4037 while (sva < eva) { 4038 next_bucket = L2_NEXT_BUCKET_VA(sva); 4039 if (next_bucket > eva) 4040 next_bucket = eva; 4041 4042 l2b = pmap_get_l2_bucket(pm, sva); 4043 if (l2b == NULL) { 4044 sva = next_bucket; 4045 continue; 4046 } 4047 4048 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4049 sva < next_bucket; 4050 sva += page_size, 4051 ptep += PAGE_SIZE / L2_S_SIZE, 4052 page_size = PAGE_SIZE) { 4053 if (l2pte_valid_p(*ptep)) { 4054 cpu_icache_sync_range(sva, 4055 min(page_size, eva - sva)); 4056 } 4057 } 4058 } 4059 4060 pmap_release_pmap_lock(pm); 4061 } 4062 4063 void 4064 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4065 { 4066 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4067 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4068 4069 NPDEBUG(PDB_PROTECT, 4070 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4071 md, pa, prot)); 4072 4073 switch(prot) { 4074 case VM_PROT_READ|VM_PROT_WRITE: 4075 #if defined(ARM_MMU_EXTENDED) 4076 pmap_acquire_page_lock(md); 4077 pmap_clearbit(md, pa, PVF_EXEC); 4078 pmap_release_page_lock(md); 4079 break; 4080 #endif 4081 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4082 break; 4083 4084 case VM_PROT_READ: 4085 #if defined(ARM_MMU_EXTENDED) 4086 pmap_acquire_page_lock(md); 4087 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4088 pmap_release_page_lock(md); 4089 break; 4090 #endif 4091 case VM_PROT_READ|VM_PROT_EXECUTE: 4092 pmap_acquire_page_lock(md); 4093 pmap_clearbit(md, pa, PVF_WRITE); 4094 pmap_release_page_lock(md); 4095 break; 4096 4097 default: 4098 pmap_page_remove(md, pa); 4099 break; 4100 } 4101 } 4102 4103 /* 4104 * pmap_clear_modify: 4105 * 4106 * Clear the "modified" attribute for a page. 4107 */ 4108 bool 4109 pmap_clear_modify(struct vm_page *pg) 4110 { 4111 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4112 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4113 bool rv; 4114 4115 pmap_acquire_page_lock(md); 4116 4117 if (md->pvh_attrs & PVF_MOD) { 4118 rv = true; 4119 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4120 /* 4121 * If we are going to clear the modified bit and there are 4122 * no other modified bits set, flush the page to memory and 4123 * mark it clean. 4124 */ 4125 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4126 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4127 #endif 4128 pmap_clearbit(md, pa, PVF_MOD); 4129 } else { 4130 rv = false; 4131 } 4132 pmap_release_page_lock(md); 4133 4134 return rv; 4135 } 4136 4137 /* 4138 * pmap_clear_reference: 4139 * 4140 * Clear the "referenced" attribute for a page. 4141 */ 4142 bool 4143 pmap_clear_reference(struct vm_page *pg) 4144 { 4145 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4146 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4147 bool rv; 4148 4149 pmap_acquire_page_lock(md); 4150 4151 if (md->pvh_attrs & PVF_REF) { 4152 rv = true; 4153 pmap_clearbit(md, pa, PVF_REF); 4154 } else { 4155 rv = false; 4156 } 4157 pmap_release_page_lock(md); 4158 4159 return rv; 4160 } 4161 4162 /* 4163 * pmap_is_modified: 4164 * 4165 * Test if a page has the "modified" attribute. 4166 */ 4167 /* See <arm/arm32/pmap.h> */ 4168 4169 /* 4170 * pmap_is_referenced: 4171 * 4172 * Test if a page has the "referenced" attribute. 4173 */ 4174 /* See <arm/arm32/pmap.h> */ 4175 4176 #if defined(ARM_MMU_EXTENDED) && 0 4177 int 4178 pmap_prefetchabt_fixup(void *v) 4179 { 4180 struct trapframe * const tf = v; 4181 vaddr_t va = trunc_page(tf->tf_pc); 4182 int rv = ABORT_FIXUP_FAILED; 4183 4184 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4185 return rv; 4186 4187 kpreempt_disable(); 4188 pmap_t pm = curcpu()->ci_pmap_cur; 4189 const size_t l1slot = l1pte_index(va); 4190 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4191 if (l2 == NULL) 4192 goto out; 4193 4194 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4195 if (l2b->l2b_kva == NULL) 4196 goto out; 4197 4198 /* 4199 * Check the PTE itself. 4200 */ 4201 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4202 const pt_entry_t opte = *ptep; 4203 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4204 goto out; 4205 4206 paddr_t pa = l2pte_pa(pte); 4207 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4208 KASSERT(pg != NULL); 4209 4210 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4211 4212 pmap_acquire_page_lock(md); 4213 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4214 KASSERT(pv != NULL); 4215 4216 if (PV_IS_EXEC_P(pv->pv_flags)) { 4217 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4218 pmap_syncicache_page(md, pa); 4219 } 4220 rv = ABORT_FIXUP_RETURN; 4221 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4222 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4223 } 4224 pmap_release_page_lock(md); 4225 4226 out: 4227 kpreempt_enable(); 4228 return rv; 4229 } 4230 #endif 4231 4232 int 4233 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4234 { 4235 struct l2_dtable *l2; 4236 struct l2_bucket *l2b; 4237 paddr_t pa; 4238 const size_t l1slot = l1pte_index(va); 4239 int rv = 0; 4240 4241 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4242 4243 va = trunc_page(va); 4244 4245 KASSERT(!user || (pm != pmap_kernel())); 4246 4247 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4248 pm, va, ftype, user); 4249 #ifdef ARM_MMU_EXTENDED 4250 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4251 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4252 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4253 #endif 4254 4255 pmap_acquire_pmap_lock(pm); 4256 4257 /* 4258 * If there is no l2_dtable for this address, then the process 4259 * has no business accessing it. 4260 * 4261 * Note: This will catch userland processes trying to access 4262 * kernel addresses. 4263 */ 4264 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4265 if (l2 == NULL) { 4266 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4267 goto out; 4268 } 4269 4270 /* 4271 * Likewise if there is no L2 descriptor table 4272 */ 4273 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4274 if (l2b->l2b_kva == NULL) { 4275 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4276 goto out; 4277 } 4278 4279 /* 4280 * Check the PTE itself. 4281 */ 4282 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4283 pt_entry_t const opte = *ptep; 4284 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4285 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4286 goto out; 4287 } 4288 4289 #ifndef ARM_HAS_VBAR 4290 /* 4291 * Catch a userland access to the vector page mapped at 0x0 4292 */ 4293 if (user && (opte & L2_S_PROT_U) == 0) { 4294 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4295 goto out; 4296 } 4297 #endif 4298 4299 pa = l2pte_pa(opte); 4300 4301 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4302 /* 4303 * This looks like a good candidate for "page modified" 4304 * emulation... 4305 */ 4306 struct pv_entry *pv; 4307 struct vm_page *pg; 4308 4309 /* Extract the physical address of the page */ 4310 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4311 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4312 goto out; 4313 } 4314 4315 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4316 4317 /* Get the current flags for this page. */ 4318 pmap_acquire_page_lock(md); 4319 pv = pmap_find_pv(md, pm, va); 4320 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4321 pmap_release_page_lock(md); 4322 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4323 goto out; 4324 } 4325 4326 /* 4327 * Do the flags say this page is writable? If not then it 4328 * is a genuine write fault. If yes then the write fault is 4329 * our fault as we did not reflect the write access in the 4330 * PTE. Now we know a write has occurred we can correct this 4331 * and also set the modified bit 4332 */ 4333 if ((pv->pv_flags & PVF_WRITE) == 0) { 4334 pmap_release_page_lock(md); 4335 goto out; 4336 } 4337 4338 md->pvh_attrs |= PVF_REF | PVF_MOD; 4339 pv->pv_flags |= PVF_REF | PVF_MOD; 4340 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4341 /* 4342 * If there are cacheable mappings for this page, mark it dirty. 4343 */ 4344 if ((md->pvh_attrs & PVF_NC) == 0) 4345 md->pvh_attrs |= PVF_DIRTY; 4346 #endif 4347 #ifdef ARM_MMU_EXTENDED 4348 if (md->pvh_attrs & PVF_EXEC) { 4349 md->pvh_attrs &= ~PVF_EXEC; 4350 PMAPCOUNT(exec_discarded_modfixup); 4351 } 4352 #endif 4353 pmap_release_page_lock(md); 4354 4355 /* 4356 * Re-enable write permissions for the page. No need to call 4357 * pmap_vac_me_harder(), since this is just a 4358 * modified-emulation fault, and the PVF_WRITE bit isn't 4359 * changing. We've already set the cacheable bits based on 4360 * the assumption that we can write to this page. 4361 */ 4362 const pt_entry_t npte = 4363 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4364 #ifdef ARM_MMU_EXTENDED 4365 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4366 #endif 4367 | 0; 4368 l2pte_set(ptep, npte, opte); 4369 PTE_SYNC(ptep); 4370 PMAPCOUNT(fixup_mod); 4371 rv = 1; 4372 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4373 opte, npte, 0, 0); 4374 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4375 /* 4376 * This looks like a good candidate for "page referenced" 4377 * emulation. 4378 */ 4379 struct vm_page *pg; 4380 4381 /* Extract the physical address of the page */ 4382 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4383 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4384 goto out; 4385 } 4386 4387 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4388 4389 /* Get the current flags for this page. */ 4390 pmap_acquire_page_lock(md); 4391 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4392 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4393 pmap_release_page_lock(md); 4394 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4395 goto out; 4396 } 4397 4398 md->pvh_attrs |= PVF_REF; 4399 pv->pv_flags |= PVF_REF; 4400 4401 pt_entry_t npte = 4402 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4403 #ifdef ARM_MMU_EXTENDED 4404 if (pm != pmap_kernel()) { 4405 npte |= L2_XS_nG; 4406 } 4407 /* 4408 * If we got called from prefetch abort, then ftype will have 4409 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4410 * the PTE. 4411 */ 4412 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4413 /* 4414 * Is this a mapping of an executable page? 4415 */ 4416 if ((pv->pv_flags & PVF_EXEC) == 0) { 4417 pmap_release_page_lock(md); 4418 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4419 0, 0, 0, 0); 4420 goto out; 4421 } 4422 /* 4423 * If we haven't synced the page, do so now. 4424 */ 4425 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4426 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4427 pa, 0, 0, 0); 4428 pmap_syncicache_page(md, pa); 4429 PMAPCOUNT(fixup_exec); 4430 } 4431 npte &= ~L2_XS_XN; 4432 } 4433 #endif /* ARM_MMU_EXTENDED */ 4434 pmap_release_page_lock(md); 4435 l2pte_set(ptep, npte, opte); 4436 PTE_SYNC(ptep); 4437 PMAPCOUNT(fixup_ref); 4438 rv = 1; 4439 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4440 opte, npte, 0, 0); 4441 #ifdef ARM_MMU_EXTENDED 4442 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4443 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4444 if (pg == NULL) { 4445 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4446 goto out; 4447 } 4448 4449 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4450 4451 /* Get the current flags for this page. */ 4452 pmap_acquire_page_lock(md); 4453 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4454 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4455 pmap_release_page_lock(md); 4456 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4457 goto out; 4458 } 4459 4460 /* 4461 * If we haven't synced the page, do so now. 4462 */ 4463 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4464 UVMHIST_LOG(maphist, "syncicache page #%#x", 4465 pa, 0, 0, 0); 4466 pmap_syncicache_page(md, pa); 4467 } 4468 pmap_release_page_lock(md); 4469 /* 4470 * Turn off no-execute. 4471 */ 4472 KASSERT(opte & L2_XS_nG); 4473 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4474 PTE_SYNC(ptep); 4475 rv = 1; 4476 PMAPCOUNT(fixup_exec); 4477 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4478 opte, opte & ~L2_XS_XN, 0, 0); 4479 #endif 4480 } 4481 4482 #ifndef ARM_MMU_EXTENDED 4483 /* 4484 * We know there is a valid mapping here, so simply 4485 * fix up the L1 if necessary. 4486 */ 4487 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4488 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4489 if (*pdep != pde) { 4490 l1pte_setone(pdep, pde); 4491 PTE_SYNC(pdep); 4492 rv = 1; 4493 PMAPCOUNT(fixup_pdes); 4494 } 4495 #endif 4496 4497 #ifdef CPU_SA110 4498 /* 4499 * There are bugs in the rev K SA110. This is a check for one 4500 * of them. 4501 */ 4502 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4503 curcpu()->ci_arm_cpurev < 3) { 4504 /* Always current pmap */ 4505 if (l2pte_valid_p(opte)) { 4506 extern int kernel_debug; 4507 if (kernel_debug & 1) { 4508 struct proc *p = curlwp->l_proc; 4509 printf("prefetch_abort: page is already " 4510 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4511 printf("prefetch_abort: pc=%08lx proc=%p " 4512 "process=%s\n", va, p, p->p_comm); 4513 printf("prefetch_abort: far=%08x fs=%x\n", 4514 cpu_faultaddress(), cpu_faultstatus()); 4515 } 4516 #ifdef DDB 4517 if (kernel_debug & 2) 4518 Debugger(); 4519 #endif 4520 rv = 1; 4521 } 4522 } 4523 #endif /* CPU_SA110 */ 4524 4525 #ifndef ARM_MMU_EXTENDED 4526 /* 4527 * If 'rv == 0' at this point, it generally indicates that there is a 4528 * stale TLB entry for the faulting address. That might be due to a 4529 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4530 */ 4531 if (rv == 0 4532 && pm->pm_l1->l1_domain_use_count == 1 4533 && pmap_needs_pte_sync == 0) { 4534 pmap_needs_pte_sync = 1; 4535 PTE_SYNC(ptep); 4536 PMAPCOUNT(fixup_ptesync); 4537 rv = 1; 4538 } 4539 #endif 4540 4541 #if defined(DEBUG) || 1 4542 /* 4543 * If 'rv == 0' at this point, it generally indicates that there is a 4544 * stale TLB entry for the faulting address. This happens when two or 4545 * more processes are sharing an L1. Since we don't flush the TLB on 4546 * a context switch between such processes, we can take domain faults 4547 * for mappings which exist at the same VA in both processes. EVEN IF 4548 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4549 * example. 4550 * 4551 * This is extremely likely to happen if pmap_enter() updated the L1 4552 * entry for a recently entered mapping. In this case, the TLB is 4553 * flushed for the new mapping, but there may still be TLB entries for 4554 * other mappings belonging to other processes in the 1MB range 4555 * covered by the L1 entry. 4556 * 4557 * Since 'rv == 0', we know that the L1 already contains the correct 4558 * value, so the fault must be due to a stale TLB entry. 4559 * 4560 * Since we always need to flush the TLB anyway in the case where we 4561 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4562 * stale TLB entries dynamically. 4563 * 4564 * However, the above condition can ONLY happen if the current L1 is 4565 * being shared. If it happens when the L1 is unshared, it indicates 4566 * that other parts of the pmap are not doing their job WRT managing 4567 * the TLB. 4568 */ 4569 if (rv == 0 4570 #ifndef ARM_MMU_EXTENDED 4571 && pm->pm_l1->l1_domain_use_count == 1 4572 #endif 4573 && true) { 4574 #ifdef DEBUG 4575 extern int last_fault_code; 4576 #else 4577 int last_fault_code = ftype & VM_PROT_EXECUTE 4578 ? armreg_ifsr_read() 4579 : armreg_dfsr_read(); 4580 #endif 4581 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4582 pm, va, ftype); 4583 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4584 l2, l2b, ptep, opte); 4585 4586 #ifndef ARM_MMU_EXTENDED 4587 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4588 pdep, pde, last_fault_code); 4589 #else 4590 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4591 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4592 armreg_ttbcr_read()); 4593 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4594 last_fault_code, curcpu()->ci_pmap_cur, 4595 curcpu()->ci_pmap_asid_cur, 4596 armreg_contextidr_read(), armreg_dacr_read()); 4597 #ifdef _ARM_ARCH_7 4598 if (ftype & VM_PROT_WRITE) 4599 armreg_ats1cuw_write(va); 4600 else 4601 armreg_ats1cur_write(va); 4602 arm_isb(); 4603 printf("fixup: par %#x\n", armreg_par_read()); 4604 #endif 4605 #endif 4606 #ifdef DDB 4607 extern int kernel_debug; 4608 4609 if (kernel_debug & 2) { 4610 pmap_release_pmap_lock(pm); 4611 #ifdef UVMHIST 4612 KERNHIST_DUMP(maphist); 4613 #endif 4614 cpu_Debugger(); 4615 pmap_acquire_pmap_lock(pm); 4616 } 4617 #endif 4618 } 4619 #endif 4620 4621 pmap_tlb_flush_SE(pm, va, 4622 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4623 4624 rv = 1; 4625 4626 out: 4627 pmap_release_pmap_lock(pm); 4628 4629 return (rv); 4630 } 4631 4632 /* 4633 * Routine: pmap_procwr 4634 * 4635 * Function: 4636 * Synchronize caches corresponding to [addr, addr+len) in p. 4637 * 4638 */ 4639 void 4640 pmap_procwr(struct proc *p, vaddr_t va, int len) 4641 { 4642 /* We only need to do anything if it is the current process. */ 4643 if (p == curproc) 4644 cpu_icache_sync_range(va, len); 4645 } 4646 4647 /* 4648 * Routine: pmap_unwire 4649 * Function: Clear the wired attribute for a map/virtual-address pair. 4650 * 4651 * In/out conditions: 4652 * The mapping must already exist in the pmap. 4653 */ 4654 void 4655 pmap_unwire(pmap_t pm, vaddr_t va) 4656 { 4657 struct l2_bucket *l2b; 4658 pt_entry_t *ptep, pte; 4659 struct vm_page *pg; 4660 paddr_t pa; 4661 4662 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4663 4664 pmap_acquire_pmap_lock(pm); 4665 4666 l2b = pmap_get_l2_bucket(pm, va); 4667 KDASSERT(l2b != NULL); 4668 4669 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4670 pte = *ptep; 4671 4672 /* Extract the physical address of the page */ 4673 pa = l2pte_pa(pte); 4674 4675 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4676 /* Update the wired bit in the pv entry for this page. */ 4677 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4678 4679 pmap_acquire_page_lock(md); 4680 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4681 pmap_release_page_lock(md); 4682 } 4683 4684 pmap_release_pmap_lock(pm); 4685 } 4686 4687 void 4688 pmap_activate(struct lwp *l) 4689 { 4690 struct cpu_info * const ci = curcpu(); 4691 extern int block_userspace_access; 4692 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4693 #ifdef ARM_MMU_EXTENDED 4694 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4695 #endif 4696 4697 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4698 4699 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4700 4701 /* 4702 * If activating a non-current lwp or the current lwp is 4703 * already active, just return. 4704 */ 4705 if (false 4706 || l != curlwp 4707 #ifdef ARM_MMU_EXTENDED 4708 || (ci->ci_pmap_cur == npm && 4709 (npm == pmap_kernel() 4710 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4711 #else 4712 || npm->pm_activated == true 4713 #endif 4714 || false) { 4715 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4716 return; 4717 } 4718 4719 #ifndef ARM_MMU_EXTENDED 4720 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4721 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4722 4723 /* 4724 * If TTB and DACR are unchanged, short-circuit all the 4725 * TLB/cache management stuff. 4726 */ 4727 pmap_t opm = ci->ci_lastlwp 4728 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4729 : NULL; 4730 if (opm != NULL) { 4731 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4732 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4733 4734 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4735 goto all_done; 4736 } 4737 #endif /* !ARM_MMU_EXTENDED */ 4738 4739 PMAPCOUNT(activations); 4740 block_userspace_access = 1; 4741 4742 #ifndef ARM_MMU_EXTENDED 4743 /* 4744 * If switching to a user vmspace which is different to the 4745 * most recent one, and the most recent one is potentially 4746 * live in the cache, we must write-back and invalidate the 4747 * entire cache. 4748 */ 4749 pmap_t rpm = ci->ci_pmap_lastuser; 4750 #endif 4751 4752 /* 4753 * XXXSCW: There's a corner case here which can leave turds in the cache as 4754 * reported in kern/41058. They're probably left over during tear-down and 4755 * switching away from an exiting process. Until the root cause is identified 4756 * and fixed, zap the cache when switching pmaps. This will result in a few 4757 * unnecessary cache flushes, but that's better than silently corrupting data. 4758 */ 4759 #ifndef ARM_MMU_EXTENDED 4760 #if 0 4761 if (npm != pmap_kernel() && rpm && npm != rpm && 4762 rpm->pm_cstate.cs_cache) { 4763 rpm->pm_cstate.cs_cache = 0; 4764 #ifdef PMAP_CACHE_VIVT 4765 cpu_idcache_wbinv_all(); 4766 #endif 4767 } 4768 #else 4769 if (rpm) { 4770 rpm->pm_cstate.cs_cache = 0; 4771 if (npm == pmap_kernel()) 4772 ci->ci_pmap_lastuser = NULL; 4773 #ifdef PMAP_CACHE_VIVT 4774 cpu_idcache_wbinv_all(); 4775 #endif 4776 } 4777 #endif 4778 4779 /* No interrupts while we frob the TTB/DACR */ 4780 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4781 #endif /* !ARM_MMU_EXTENDED */ 4782 4783 #ifndef ARM_HAS_VBAR 4784 /* 4785 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4786 * entry corresponding to 'vector_page' in the incoming L1 table 4787 * before switching to it otherwise subsequent interrupts/exceptions 4788 * (including domain faults!) will jump into hyperspace. 4789 */ 4790 if (npm->pm_pl1vec != NULL) { 4791 cpu_tlb_flushID_SE((u_int)vector_page); 4792 cpu_cpwait(); 4793 *npm->pm_pl1vec = npm->pm_l1vec; 4794 PTE_SYNC(npm->pm_pl1vec); 4795 } 4796 #endif 4797 4798 #ifdef ARM_MMU_EXTENDED 4799 /* 4800 * Assume that TTBR1 has only global mappings and TTBR0 only has 4801 * non-global mappings. To prevent speculation from doing evil things 4802 * we disable translation table walks using TTBR0 before setting the 4803 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4804 * walks are reenabled. 4805 */ 4806 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4807 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4808 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4809 arm_isb(); 4810 pmap_tlb_asid_acquire(npm, l); 4811 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4812 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4813 /* 4814 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4815 * been updated. 4816 */ 4817 arm_isb(); 4818 if (npm != pmap_kernel()) { 4819 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4820 } 4821 cpu_cpwait(); 4822 ci->ci_pmap_asid_cur = pai->pai_asid; 4823 #else 4824 cpu_domains(ndacr); 4825 if (npm == pmap_kernel() || npm == rpm) { 4826 /* 4827 * Switching to a kernel thread, or back to the 4828 * same user vmspace as before... Simply update 4829 * the TTB (no TLB flush required) 4830 */ 4831 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4832 cpu_cpwait(); 4833 } else { 4834 /* 4835 * Otherwise, update TTB and flush TLB 4836 */ 4837 cpu_context_switch(npm->pm_l1->l1_physaddr); 4838 if (rpm != NULL) 4839 rpm->pm_cstate.cs_tlb = 0; 4840 } 4841 4842 restore_interrupts(oldirqstate); 4843 #endif /* ARM_MMU_EXTENDED */ 4844 4845 block_userspace_access = 0; 4846 4847 #ifndef ARM_MMU_EXTENDED 4848 all_done: 4849 /* 4850 * The new pmap is resident. Make sure it's marked 4851 * as resident in the cache/TLB. 4852 */ 4853 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4854 if (npm != pmap_kernel()) 4855 ci->ci_pmap_lastuser = npm; 4856 4857 /* The old pmap is not longer active */ 4858 if (opm != npm) { 4859 if (opm != NULL) 4860 opm->pm_activated = false; 4861 4862 /* But the new one is */ 4863 npm->pm_activated = true; 4864 } 4865 #endif 4866 ci->ci_pmap_cur = npm; 4867 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4868 } 4869 4870 void 4871 pmap_deactivate(struct lwp *l) 4872 { 4873 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4874 4875 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4876 4877 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4878 4879 #ifdef ARM_MMU_EXTENDED 4880 kpreempt_disable(); 4881 struct cpu_info * const ci = curcpu(); 4882 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4883 /* 4884 * Disable translation table walks from TTBR0 while no pmap has been 4885 * activated. 4886 */ 4887 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4888 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4889 arm_isb(); 4890 pmap_tlb_asid_deactivate(pm); 4891 cpu_setttb(pmap_kernel()->pm_l1_pa, pai->pai_asid); 4892 ci->ci_pmap_cur = pmap_kernel(); 4893 kpreempt_enable(); 4894 #else 4895 /* 4896 * If the process is exiting, make sure pmap_activate() does 4897 * a full MMU context-switch and cache flush, which we might 4898 * otherwise skip. See PR port-arm/38950. 4899 */ 4900 if (l->l_proc->p_sflag & PS_WEXIT) 4901 curcpu()->ci_lastlwp = NULL; 4902 4903 pm->pm_activated = false; 4904 #endif 4905 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4906 } 4907 4908 void 4909 pmap_update(pmap_t pm) 4910 { 4911 4912 if (pm->pm_remove_all) { 4913 #ifdef ARM_MMU_EXTENDED 4914 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4915 /* 4916 * Finish up the pmap_remove_all() optimisation by flushing 4917 * all our ASIDs. 4918 */ 4919 pmap_tlb_asid_release_all(pm); 4920 #else 4921 /* 4922 * Finish up the pmap_remove_all() optimisation by flushing 4923 * the TLB. 4924 */ 4925 pmap_tlb_flushID(pm); 4926 #endif 4927 pm->pm_remove_all = false; 4928 } 4929 4930 #ifdef ARM_MMU_EXTENDED 4931 4932 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4933 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4934 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4935 PMAP_COUNT(shootdown_ipis); 4936 } 4937 #endif 4938 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4939 #else 4940 if (pmap_is_current(pm)) { 4941 /* 4942 * If we're dealing with a current userland pmap, move its L1 4943 * to the end of the LRU. 4944 */ 4945 if (pm != pmap_kernel()) 4946 pmap_use_l1(pm); 4947 4948 /* 4949 * We can assume we're done with frobbing the cache/tlb for 4950 * now. Make sure any future pmap ops don't skip cache/tlb 4951 * flushes. 4952 */ 4953 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4954 } 4955 #endif 4956 4957 PMAPCOUNT(updates); 4958 4959 /* 4960 * make sure TLB/cache operations have completed. 4961 */ 4962 cpu_cpwait(); 4963 } 4964 4965 void 4966 pmap_remove_all(pmap_t pm) 4967 { 4968 4969 /* 4970 * The vmspace described by this pmap is about to be torn down. 4971 * Until pmap_update() is called, UVM will only make calls 4972 * to pmap_remove(). We can make life much simpler by flushing 4973 * the cache now, and deferring TLB invalidation to pmap_update(). 4974 */ 4975 #ifdef PMAP_CACHE_VIVT 4976 pmap_cache_wbinv_all(pm, PVF_EXEC); 4977 #endif 4978 pm->pm_remove_all = true; 4979 } 4980 4981 /* 4982 * Retire the given physical map from service. 4983 * Should only be called if the map contains no valid mappings. 4984 */ 4985 void 4986 pmap_destroy(pmap_t pm) 4987 { 4988 u_int count; 4989 4990 if (pm == NULL) 4991 return; 4992 4993 if (pm->pm_remove_all) { 4994 pmap_tlb_flushID(pm); 4995 pm->pm_remove_all = false; 4996 } 4997 4998 /* 4999 * Drop reference count 5000 */ 5001 mutex_enter(pm->pm_lock); 5002 count = --pm->pm_obj.uo_refs; 5003 mutex_exit(pm->pm_lock); 5004 if (count > 0) { 5005 #ifndef ARM_MMU_EXTENDED 5006 if (pmap_is_current(pm)) { 5007 if (pm != pmap_kernel()) 5008 pmap_use_l1(pm); 5009 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5010 } 5011 #endif 5012 return; 5013 } 5014 5015 /* 5016 * reference count is zero, free pmap resources and then free pmap. 5017 */ 5018 5019 #ifndef ARM_HAS_VBAR 5020 if (vector_page < KERNEL_BASE) { 5021 KDASSERT(!pmap_is_current(pm)); 5022 5023 /* Remove the vector page mapping */ 5024 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5025 pmap_update(pm); 5026 } 5027 #endif 5028 5029 LIST_REMOVE(pm, pm_list); 5030 5031 pmap_free_l1(pm); 5032 5033 #ifdef ARM_MMU_EXTENDED 5034 #ifdef MULTIPROCESSOR 5035 kcpuset_destroy(pm->pm_active); 5036 kcpuset_destroy(pm->pm_onproc); 5037 #endif 5038 #else 5039 struct cpu_info * const ci = curcpu(); 5040 if (ci->ci_pmap_lastuser == pm) 5041 ci->ci_pmap_lastuser = NULL; 5042 #endif 5043 5044 uvm_obj_destroy(&pm->pm_obj, false); 5045 mutex_destroy(&pm->pm_obj_lock); 5046 pool_cache_put(&pmap_cache, pm); 5047 } 5048 5049 5050 /* 5051 * void pmap_reference(pmap_t pm) 5052 * 5053 * Add a reference to the specified pmap. 5054 */ 5055 void 5056 pmap_reference(pmap_t pm) 5057 { 5058 5059 if (pm == NULL) 5060 return; 5061 5062 #ifndef ARM_MMU_EXTENDED 5063 pmap_use_l1(pm); 5064 #endif 5065 5066 mutex_enter(pm->pm_lock); 5067 pm->pm_obj.uo_refs++; 5068 mutex_exit(pm->pm_lock); 5069 } 5070 5071 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5072 5073 static struct evcnt pmap_prefer_nochange_ev = 5074 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5075 static struct evcnt pmap_prefer_change_ev = 5076 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5077 5078 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5079 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5080 5081 void 5082 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5083 { 5084 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5085 vaddr_t va = *vap; 5086 vaddr_t diff = (hint - va) & mask; 5087 if (diff == 0) { 5088 pmap_prefer_nochange_ev.ev_count++; 5089 } else { 5090 pmap_prefer_change_ev.ev_count++; 5091 if (__predict_false(td)) 5092 va -= mask + 1; 5093 *vap = va + diff; 5094 } 5095 } 5096 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5097 5098 /* 5099 * pmap_zero_page() 5100 * 5101 * Zero a given physical page by mapping it at a page hook point. 5102 * In doing the zero page op, the page we zero is mapped cachable, as with 5103 * StrongARM accesses to non-cached pages are non-burst making writing 5104 * _any_ bulk data very slow. 5105 */ 5106 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5107 void 5108 pmap_zero_page_generic(paddr_t pa) 5109 { 5110 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5111 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5112 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5113 #endif 5114 #if defined(PMAP_CACHE_VIPT) 5115 /* Choose the last page color it had, if any */ 5116 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5117 #else 5118 const vsize_t va_offset = 0; 5119 #endif 5120 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5121 /* 5122 * Is this page mapped at its natural color? 5123 * If we have all of memory mapped, then just convert PA to VA. 5124 */ 5125 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5126 || va_offset == (pa & arm_cache_prefer_mask); 5127 const vaddr_t vdstp = okcolor 5128 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5129 : cpu_cdstp(va_offset); 5130 #else 5131 const bool okcolor = false; 5132 const vaddr_t vdstp = cpu_cdstp(va_offset); 5133 #endif 5134 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5135 5136 5137 #ifdef DEBUG 5138 if (!SLIST_EMPTY(&md->pvh_list)) 5139 panic("pmap_zero_page: page has mappings"); 5140 #endif 5141 5142 KDASSERT((pa & PGOFSET) == 0); 5143 5144 if (!okcolor) { 5145 /* 5146 * Hook in the page, zero it, and purge the cache for that 5147 * zeroed page. Invalidate the TLB as needed. 5148 */ 5149 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5150 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5151 l2pte_set(ptep, npte, 0); 5152 PTE_SYNC(ptep); 5153 cpu_tlb_flushD_SE(vdstp); 5154 cpu_cpwait(); 5155 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5156 && !defined(ARM_MMU_EXTENDED) 5157 /* 5158 * If we are direct-mapped and our color isn't ok, then before 5159 * we bzero the page invalidate its contents from the cache and 5160 * reset the color to its natural color. 5161 */ 5162 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5163 md->pvh_attrs &= ~arm_cache_prefer_mask; 5164 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5165 #endif 5166 } 5167 bzero_page(vdstp); 5168 if (!okcolor) { 5169 /* 5170 * Unmap the page. 5171 */ 5172 l2pte_reset(ptep); 5173 PTE_SYNC(ptep); 5174 cpu_tlb_flushD_SE(vdstp); 5175 #ifdef PMAP_CACHE_VIVT 5176 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5177 #endif 5178 } 5179 #ifdef PMAP_CACHE_VIPT 5180 /* 5181 * This page is now cache resident so it now has a page color. 5182 * Any contents have been obliterated so clear the EXEC flag. 5183 */ 5184 #ifndef ARM_MMU_EXTENDED 5185 if (!pmap_is_page_colored_p(md)) { 5186 PMAPCOUNT(vac_color_new); 5187 md->pvh_attrs |= PVF_COLORED; 5188 } 5189 md->pvh_attrs |= PVF_DIRTY; 5190 #endif 5191 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5192 md->pvh_attrs &= ~PVF_EXEC; 5193 PMAPCOUNT(exec_discarded_zero); 5194 } 5195 #endif 5196 } 5197 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5198 5199 #if ARM_MMU_XSCALE == 1 5200 void 5201 pmap_zero_page_xscale(paddr_t pa) 5202 { 5203 #ifdef DEBUG 5204 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5205 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5206 5207 if (!SLIST_EMPTY(&md->pvh_list)) 5208 panic("pmap_zero_page: page has mappings"); 5209 #endif 5210 5211 KDASSERT((pa & PGOFSET) == 0); 5212 5213 /* 5214 * Hook in the page, zero it, and purge the cache for that 5215 * zeroed page. Invalidate the TLB as needed. 5216 */ 5217 5218 pt_entry_t npte = L2_S_PROTO | pa | 5219 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5220 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5221 l2pte_set(cdst_pte, npte, 0); 5222 PTE_SYNC(cdst_pte); 5223 cpu_tlb_flushD_SE(cdstp); 5224 cpu_cpwait(); 5225 bzero_page(cdstp); 5226 xscale_cache_clean_minidata(); 5227 l2pte_reset(cdst_pte); 5228 PTE_SYNC(cdst_pte); 5229 } 5230 #endif /* ARM_MMU_XSCALE == 1 */ 5231 5232 /* pmap_pageidlezero() 5233 * 5234 * The same as above, except that we assume that the page is not 5235 * mapped. This means we never have to flush the cache first. Called 5236 * from the idle loop. 5237 */ 5238 bool 5239 pmap_pageidlezero(paddr_t pa) 5240 { 5241 bool rv = true; 5242 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5243 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5244 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5245 #endif 5246 #ifdef PMAP_CACHE_VIPT 5247 /* Choose the last page color it had, if any */ 5248 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5249 #else 5250 const vsize_t va_offset = 0; 5251 #endif 5252 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5253 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5254 || va_offset == (pa & arm_cache_prefer_mask); 5255 const vaddr_t vdstp = okcolor 5256 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5257 : cpu_cdstp(va_offset); 5258 #else 5259 const bool okcolor = false; 5260 const vaddr_t vdstp = cpu_cdstp(va_offset); 5261 #endif 5262 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5263 5264 5265 #ifdef DEBUG 5266 if (!SLIST_EMPTY(&md->pvh_list)) 5267 panic("pmap_pageidlezero: page has mappings"); 5268 #endif 5269 5270 KDASSERT((pa & PGOFSET) == 0); 5271 5272 if (!okcolor) { 5273 /* 5274 * Hook in the page, zero it, and purge the cache for that 5275 * zeroed page. Invalidate the TLB as needed. 5276 */ 5277 const pt_entry_t npte = L2_S_PROTO | pa | 5278 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5279 l2pte_set(ptep, npte, 0); 5280 PTE_SYNC(ptep); 5281 cpu_tlb_flushD_SE(vdstp); 5282 cpu_cpwait(); 5283 } 5284 5285 uint64_t *ptr = (uint64_t *)vdstp; 5286 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5287 if (sched_curcpu_runnable_p() != 0) { 5288 /* 5289 * A process has become ready. Abort now, 5290 * so we don't keep it waiting while we 5291 * do slow memory access to finish this 5292 * page. 5293 */ 5294 rv = false; 5295 break; 5296 } 5297 *ptr++ = 0; 5298 } 5299 5300 #ifdef PMAP_CACHE_VIVT 5301 if (rv) 5302 /* 5303 * if we aborted we'll rezero this page again later so don't 5304 * purge it unless we finished it 5305 */ 5306 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5307 #elif defined(PMAP_CACHE_VIPT) 5308 /* 5309 * This page is now cache resident so it now has a page color. 5310 * Any contents have been obliterated so clear the EXEC flag. 5311 */ 5312 #ifndef ARM_MMU_EXTENDED 5313 if (!pmap_is_page_colored_p(md)) { 5314 PMAPCOUNT(vac_color_new); 5315 md->pvh_attrs |= PVF_COLORED; 5316 } 5317 #endif 5318 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5319 md->pvh_attrs &= ~PVF_EXEC; 5320 PMAPCOUNT(exec_discarded_zero); 5321 } 5322 #endif 5323 /* 5324 * Unmap the page. 5325 */ 5326 if (!okcolor) { 5327 l2pte_reset(ptep); 5328 PTE_SYNC(ptep); 5329 cpu_tlb_flushD_SE(vdstp); 5330 } 5331 5332 return rv; 5333 } 5334 5335 /* 5336 * pmap_copy_page() 5337 * 5338 * Copy one physical page into another, by mapping the pages into 5339 * hook points. The same comment regarding cachability as in 5340 * pmap_zero_page also applies here. 5341 */ 5342 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5343 void 5344 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5345 { 5346 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5347 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5348 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5349 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5350 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5351 #endif 5352 #ifdef PMAP_CACHE_VIPT 5353 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5354 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5355 #else 5356 const vsize_t src_va_offset = 0; 5357 const vsize_t dst_va_offset = 0; 5358 #endif 5359 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5360 /* 5361 * Is this page mapped at its natural color? 5362 * If we have all of memory mapped, then just convert PA to VA. 5363 */ 5364 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5365 || src_va_offset == (src & arm_cache_prefer_mask); 5366 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5367 || dst_va_offset == (dst & arm_cache_prefer_mask); 5368 const vaddr_t vsrcp = src_okcolor 5369 ? pmap_direct_mapped_phys(src, &src_okcolor, 5370 cpu_csrcp(src_va_offset)) 5371 : cpu_csrcp(src_va_offset); 5372 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5373 cpu_cdstp(dst_va_offset)); 5374 #else 5375 const bool src_okcolor = false; 5376 const bool dst_okcolor = false; 5377 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5378 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5379 #endif 5380 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5381 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5382 5383 #ifdef DEBUG 5384 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5385 panic("pmap_copy_page: dst page has mappings"); 5386 #endif 5387 5388 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5389 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5390 #endif 5391 KDASSERT((src & PGOFSET) == 0); 5392 KDASSERT((dst & PGOFSET) == 0); 5393 5394 /* 5395 * Clean the source page. Hold the source page's lock for 5396 * the duration of the copy so that no other mappings can 5397 * be created while we have a potentially aliased mapping. 5398 */ 5399 #ifdef PMAP_CACHE_VIVT 5400 pmap_acquire_page_lock(src_md); 5401 (void) pmap_clean_page(src_md, true); 5402 pmap_release_page_lock(src_md); 5403 #endif 5404 5405 /* 5406 * Map the pages into the page hook points, copy them, and purge 5407 * the cache for the appropriate page. Invalidate the TLB 5408 * as required. 5409 */ 5410 if (!src_okcolor) { 5411 const pt_entry_t nsrc_pte = L2_S_PROTO 5412 | src 5413 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5414 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5415 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5416 | pte_l2_s_cache_mode 5417 #endif 5418 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5419 l2pte_set(src_ptep, nsrc_pte, 0); 5420 PTE_SYNC(src_ptep); 5421 cpu_tlb_flushD_SE(vsrcp); 5422 cpu_cpwait(); 5423 } 5424 if (!dst_okcolor) { 5425 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5426 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5427 l2pte_set(dst_ptep, ndst_pte, 0); 5428 PTE_SYNC(dst_ptep); 5429 cpu_tlb_flushD_SE(vdstp); 5430 cpu_cpwait(); 5431 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5432 /* 5433 * If we are direct-mapped and our color isn't ok, then before 5434 * we bcopy to the new page invalidate its contents from the 5435 * cache and reset its color to its natural color. 5436 */ 5437 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5438 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5439 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5440 #endif 5441 } 5442 bcopy_page(vsrcp, vdstp); 5443 #ifdef PMAP_CACHE_VIVT 5444 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5445 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5446 #endif 5447 /* 5448 * Unmap the pages. 5449 */ 5450 if (!src_okcolor) { 5451 l2pte_reset(src_ptep); 5452 PTE_SYNC(src_ptep); 5453 cpu_tlb_flushD_SE(vsrcp); 5454 cpu_cpwait(); 5455 } 5456 if (!dst_okcolor) { 5457 l2pte_reset(dst_ptep); 5458 PTE_SYNC(dst_ptep); 5459 cpu_tlb_flushD_SE(vdstp); 5460 cpu_cpwait(); 5461 } 5462 #ifdef PMAP_CACHE_VIPT 5463 /* 5464 * Now that the destination page is in the cache, mark it as colored. 5465 * If this was an exec page, discard it. 5466 */ 5467 pmap_acquire_page_lock(dst_md); 5468 #ifndef ARM_MMU_EXTENDED 5469 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5470 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5471 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5472 } 5473 if (!pmap_is_page_colored_p(dst_md)) { 5474 PMAPCOUNT(vac_color_new); 5475 dst_md->pvh_attrs |= PVF_COLORED; 5476 } 5477 dst_md->pvh_attrs |= PVF_DIRTY; 5478 #endif 5479 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5480 dst_md->pvh_attrs &= ~PVF_EXEC; 5481 PMAPCOUNT(exec_discarded_copy); 5482 } 5483 pmap_release_page_lock(dst_md); 5484 #endif 5485 } 5486 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5487 5488 #if ARM_MMU_XSCALE == 1 5489 void 5490 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5491 { 5492 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5493 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5494 #ifdef DEBUG 5495 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5496 5497 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5498 panic("pmap_copy_page: dst page has mappings"); 5499 #endif 5500 5501 KDASSERT((src & PGOFSET) == 0); 5502 KDASSERT((dst & PGOFSET) == 0); 5503 5504 /* 5505 * Clean the source page. Hold the source page's lock for 5506 * the duration of the copy so that no other mappings can 5507 * be created while we have a potentially aliased mapping. 5508 */ 5509 #ifdef PMAP_CACHE_VIVT 5510 pmap_acquire_page_lock(src_md); 5511 (void) pmap_clean_page(src_md, true); 5512 pmap_release_page_lock(src_md); 5513 #endif 5514 5515 /* 5516 * Map the pages into the page hook points, copy them, and purge 5517 * the cache for the appropriate page. Invalidate the TLB 5518 * as required. 5519 */ 5520 *csrc_pte = L2_S_PROTO | src | 5521 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 5522 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5523 PTE_SYNC(csrc_pte); 5524 *cdst_pte = L2_S_PROTO | dst | 5525 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5526 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5527 PTE_SYNC(cdst_pte); 5528 cpu_tlb_flushD_SE(csrcp); 5529 cpu_tlb_flushD_SE(cdstp); 5530 cpu_cpwait(); 5531 bcopy_page(csrcp, cdstp); 5532 xscale_cache_clean_minidata(); 5533 } 5534 #endif /* ARM_MMU_XSCALE == 1 */ 5535 5536 /* 5537 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5538 * 5539 * Return the start and end addresses of the kernel's virtual space. 5540 * These values are setup in pmap_bootstrap and are updated as pages 5541 * are allocated. 5542 */ 5543 void 5544 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5545 { 5546 *start = virtual_avail; 5547 *end = virtual_end; 5548 } 5549 5550 /* 5551 * Helper function for pmap_grow_l2_bucket() 5552 */ 5553 static inline int 5554 pmap_grow_map(vaddr_t va, paddr_t *pap) 5555 { 5556 paddr_t pa; 5557 5558 if (uvm.page_init_done == false) { 5559 #ifdef PMAP_STEAL_MEMORY 5560 pv_addr_t pv; 5561 pmap_boot_pagealloc(PAGE_SIZE, 5562 #ifdef PMAP_CACHE_VIPT 5563 arm_cache_prefer_mask, 5564 va & arm_cache_prefer_mask, 5565 #else 5566 0, 0, 5567 #endif 5568 &pv); 5569 pa = pv.pv_pa; 5570 #else 5571 if (uvm_page_physget(&pa) == false) 5572 return (1); 5573 #endif /* PMAP_STEAL_MEMORY */ 5574 } else { 5575 struct vm_page *pg; 5576 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5577 if (pg == NULL) 5578 return (1); 5579 pa = VM_PAGE_TO_PHYS(pg); 5580 /* 5581 * This new page must not have any mappings. Enter it via 5582 * pmap_kenter_pa and let that routine do the hard work. 5583 */ 5584 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5585 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5586 pmap_kenter_pa(va, pa, 5587 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5588 } 5589 5590 if (pap) 5591 *pap = pa; 5592 5593 PMAPCOUNT(pt_mappings); 5594 #ifdef DEBUG 5595 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5596 KDASSERT(l2b != NULL); 5597 5598 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5599 const pt_entry_t opte = *ptep; 5600 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5601 #endif 5602 memset((void *)va, 0, PAGE_SIZE); 5603 return (0); 5604 } 5605 5606 /* 5607 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5608 * used by pmap_growkernel(). 5609 */ 5610 static inline struct l2_bucket * 5611 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5612 { 5613 struct l2_dtable *l2; 5614 struct l2_bucket *l2b; 5615 u_short l1slot; 5616 vaddr_t nva; 5617 5618 l1slot = l1pte_index(va); 5619 5620 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5621 /* 5622 * No mapping at this address, as there is 5623 * no entry in the L1 table. 5624 * Need to allocate a new l2_dtable. 5625 */ 5626 nva = pmap_kernel_l2dtable_kva; 5627 if ((nva & PGOFSET) == 0) { 5628 /* 5629 * Need to allocate a backing page 5630 */ 5631 if (pmap_grow_map(nva, NULL)) 5632 return (NULL); 5633 } 5634 5635 l2 = (struct l2_dtable *)nva; 5636 nva += sizeof(struct l2_dtable); 5637 5638 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5639 /* 5640 * The new l2_dtable straddles a page boundary. 5641 * Map in another page to cover it. 5642 */ 5643 if (pmap_grow_map(nva, NULL)) 5644 return (NULL); 5645 } 5646 5647 pmap_kernel_l2dtable_kva = nva; 5648 5649 /* 5650 * Link it into the parent pmap 5651 */ 5652 pm->pm_l2[L2_IDX(l1slot)] = l2; 5653 } 5654 5655 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5656 5657 /* 5658 * Fetch pointer to the L2 page table associated with the address. 5659 */ 5660 if (l2b->l2b_kva == NULL) { 5661 pt_entry_t *ptep; 5662 5663 /* 5664 * No L2 page table has been allocated. Chances are, this 5665 * is because we just allocated the l2_dtable, above. 5666 */ 5667 nva = pmap_kernel_l2ptp_kva; 5668 ptep = (pt_entry_t *)nva; 5669 if ((nva & PGOFSET) == 0) { 5670 /* 5671 * Need to allocate a backing page 5672 */ 5673 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5674 return (NULL); 5675 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5676 } 5677 5678 l2->l2_occupancy++; 5679 l2b->l2b_kva = ptep; 5680 l2b->l2b_l1slot = l1slot; 5681 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5682 5683 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5684 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5685 } 5686 5687 return (l2b); 5688 } 5689 5690 vaddr_t 5691 pmap_growkernel(vaddr_t maxkvaddr) 5692 { 5693 pmap_t kpm = pmap_kernel(); 5694 #ifndef ARM_MMU_EXTENDED 5695 struct l1_ttable *l1; 5696 #endif 5697 int s; 5698 5699 if (maxkvaddr <= pmap_curmaxkvaddr) 5700 goto out; /* we are OK */ 5701 5702 NPDEBUG(PDB_GROWKERN, 5703 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5704 pmap_curmaxkvaddr, maxkvaddr)); 5705 5706 KDASSERT(maxkvaddr <= virtual_end); 5707 5708 /* 5709 * whoops! we need to add kernel PTPs 5710 */ 5711 5712 s = splhigh(); /* to be safe */ 5713 mutex_enter(kpm->pm_lock); 5714 5715 /* Map 1MB at a time */ 5716 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5717 #ifdef ARM_MMU_EXTENDED 5718 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5719 pd_entry_t *pdep = spdep; 5720 #endif 5721 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5722 #ifdef ARM_MMU_EXTENDED 5723 pdep++, 5724 #endif 5725 l1slot++) { 5726 struct l2_bucket *l2b = 5727 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5728 KASSERT(l2b != NULL); 5729 5730 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5731 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5732 #ifdef ARM_MMU_EXTENDED 5733 l1pte_setone(pdep, npde); 5734 #else 5735 /* Distribute new L1 entry to all other L1s */ 5736 SLIST_FOREACH(l1, &l1_list, l1_link) { 5737 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5738 l1pte_setone(pdep, npde); 5739 PDE_SYNC(pdep); 5740 } 5741 #endif 5742 } 5743 #ifdef ARM_MMU_EXTENDED 5744 PDE_SYNC_RANGE(spdep, pdep - spdep); 5745 #endif 5746 5747 #ifdef PMAP_CACHE_VIVT 5748 /* 5749 * flush out the cache, expensive but growkernel will happen so 5750 * rarely 5751 */ 5752 cpu_dcache_wbinv_all(); 5753 cpu_tlb_flushD(); 5754 cpu_cpwait(); 5755 #endif 5756 5757 mutex_exit(kpm->pm_lock); 5758 splx(s); 5759 5760 out: 5761 return (pmap_curmaxkvaddr); 5762 } 5763 5764 /************************ Utility routines ****************************/ 5765 5766 #ifndef ARM_HAS_VBAR 5767 /* 5768 * vector_page_setprot: 5769 * 5770 * Manipulate the protection of the vector page. 5771 */ 5772 void 5773 vector_page_setprot(int prot) 5774 { 5775 struct l2_bucket *l2b; 5776 pt_entry_t *ptep; 5777 5778 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5779 /* 5780 * If we are using VBAR to use the vectors in the kernel, then it's 5781 * already mapped in the kernel text so no need to anything here. 5782 */ 5783 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5784 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5785 return; 5786 } 5787 #endif 5788 5789 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5790 KASSERT(l2b != NULL); 5791 5792 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5793 5794 const pt_entry_t opte = *ptep; 5795 #ifdef ARM_MMU_EXTENDED 5796 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5797 | L2_S_PROT(PTE_KERNEL, prot); 5798 #else 5799 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5800 | L2_S_PROT(PTE_KERNEL, prot); 5801 #endif 5802 l2pte_set(ptep, npte, opte); 5803 PTE_SYNC(ptep); 5804 cpu_tlb_flushD_SE(vector_page); 5805 cpu_cpwait(); 5806 } 5807 #endif 5808 5809 /* 5810 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5811 * Returns true if the mapping exists, else false. 5812 * 5813 * NOTE: This function is only used by a couple of arm-specific modules. 5814 * It is not safe to take any pmap locks here, since we could be right 5815 * in the middle of debugging the pmap anyway... 5816 * 5817 * It is possible for this routine to return false even though a valid 5818 * mapping does exist. This is because we don't lock, so the metadata 5819 * state may be inconsistent. 5820 * 5821 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5822 * a "section" mapping. 5823 */ 5824 bool 5825 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5826 { 5827 struct l2_dtable *l2; 5828 pd_entry_t *pdep, pde; 5829 pt_entry_t *ptep; 5830 u_short l1slot; 5831 5832 if (pm->pm_l1 == NULL) 5833 return false; 5834 5835 l1slot = l1pte_index(va); 5836 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5837 pde = *pdep; 5838 5839 if (l1pte_section_p(pde)) { 5840 *ptp = NULL; 5841 return true; 5842 } 5843 5844 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5845 if (l2 == NULL || 5846 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5847 return false; 5848 } 5849 5850 *ptp = &ptep[l2pte_index(va)]; 5851 return true; 5852 } 5853 5854 bool 5855 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5856 { 5857 5858 if (pm->pm_l1 == NULL) 5859 return false; 5860 5861 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5862 5863 return true; 5864 } 5865 5866 /************************ Bootstrapping routines ****************************/ 5867 5868 #ifndef ARM_MMU_EXTENDED 5869 static void 5870 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5871 { 5872 int i; 5873 5874 l1->l1_kva = l1pt; 5875 l1->l1_domain_use_count = 0; 5876 l1->l1_domain_first = 0; 5877 5878 for (i = 0; i < PMAP_DOMAINS; i++) 5879 l1->l1_domain_free[i] = i + 1; 5880 5881 /* 5882 * Copy the kernel's L1 entries to each new L1. 5883 */ 5884 if (pmap_initialized) 5885 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5886 5887 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5888 &l1->l1_physaddr) == false) 5889 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5890 5891 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5892 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5893 } 5894 #endif /* !ARM_MMU_EXTENDED */ 5895 5896 /* 5897 * pmap_bootstrap() is called from the board-specific initarm() routine 5898 * once the kernel L1/L2 descriptors tables have been set up. 5899 * 5900 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5901 * spread over a number of disparate files/functions. 5902 * 5903 * We are passed the following parameters 5904 * - kernel_l1pt 5905 * This is a pointer to the base of the kernel's L1 translation table. 5906 * - vstart 5907 * 1MB-aligned start of managed kernel virtual memory. 5908 * - vend 5909 * 1MB-aligned end of managed kernel virtual memory. 5910 * 5911 * We use the first parameter to build the metadata (struct l1_ttable and 5912 * struct l2_dtable) necessary to track kernel mappings. 5913 */ 5914 #define PMAP_STATIC_L2_SIZE 16 5915 void 5916 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5917 { 5918 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5919 #ifndef ARM_MMU_EXTENDED 5920 static struct l1_ttable static_l1; 5921 struct l1_ttable *l1 = &static_l1; 5922 #endif 5923 struct l2_dtable *l2; 5924 struct l2_bucket *l2b; 5925 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5926 pmap_t pm = pmap_kernel(); 5927 pt_entry_t *ptep; 5928 paddr_t pa; 5929 vsize_t size; 5930 int nptes, l2idx, l2next = 0; 5931 5932 #ifdef ARM_MMU_EXTENDED 5933 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5934 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5935 #endif 5936 5937 #ifdef VERBOSE_INIT_ARM 5938 printf("kpm "); 5939 #endif 5940 /* 5941 * Initialise the kernel pmap object 5942 */ 5943 curcpu()->ci_pmap_cur = pm; 5944 #ifdef ARM_MMU_EXTENDED 5945 pm->pm_l1 = l1pt; 5946 pm->pm_l1_pa = kernel_l1pt.pv_pa; 5947 #ifdef VERBOSE_INIT_ARM 5948 printf("tlb0 "); 5949 #endif 5950 pmap_tlb_info_init(&pmap_tlb0_info); 5951 #ifdef MULTIPROCESSOR 5952 #ifdef VERBOSE_INIT_ARM 5953 printf("kcpusets "); 5954 #endif 5955 pm->pm_onproc = kcpuset_running; 5956 pm->pm_active = kcpuset_running; 5957 #endif 5958 #else 5959 pm->pm_l1 = l1; 5960 #endif 5961 5962 #ifdef VERBOSE_INIT_ARM 5963 printf("locks "); 5964 #endif 5965 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5966 if (arm_cache_prefer_mask != 0) { 5967 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 5968 } else { 5969 #endif 5970 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 5971 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5972 } 5973 #endif 5974 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5975 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5976 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5977 5978 #ifdef VERBOSE_INIT_ARM 5979 printf("l1pt "); 5980 #endif 5981 /* 5982 * Scan the L1 translation table created by initarm() and create 5983 * the required metadata for all valid mappings found in it. 5984 */ 5985 for (size_t l1slot = 0; 5986 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 5987 l1slot++) { 5988 pd_entry_t pde = l1pt[l1slot]; 5989 5990 /* 5991 * We're only interested in Coarse mappings. 5992 * pmap_extract() can deal with section mappings without 5993 * recourse to checking L2 metadata. 5994 */ 5995 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5996 continue; 5997 5998 /* 5999 * Lookup the KVA of this L2 descriptor table 6000 */ 6001 pa = l1pte_pa(pde); 6002 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6003 if (ptep == NULL) { 6004 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6005 (u_int)l1slot << L1_S_SHIFT, pa); 6006 } 6007 6008 /* 6009 * Fetch the associated L2 metadata structure. 6010 * Allocate a new one if necessary. 6011 */ 6012 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6013 if (l2next == PMAP_STATIC_L2_SIZE) 6014 panic("pmap_bootstrap: out of static L2s"); 6015 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6016 } 6017 6018 /* 6019 * One more L1 slot tracked... 6020 */ 6021 l2->l2_occupancy++; 6022 6023 /* 6024 * Fill in the details of the L2 descriptor in the 6025 * appropriate bucket. 6026 */ 6027 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6028 l2b->l2b_kva = ptep; 6029 l2b->l2b_pa = pa; 6030 l2b->l2b_l1slot = l1slot; 6031 6032 /* 6033 * Establish an initial occupancy count for this descriptor 6034 */ 6035 for (l2idx = 0; 6036 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6037 l2idx++) { 6038 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6039 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 6040 } 6041 } 6042 6043 /* 6044 * Make sure the descriptor itself has the correct cache mode. 6045 * If not, fix it, but whine about the problem. Port-meisters 6046 * should consider this a clue to fix up their initarm() 6047 * function. :) 6048 */ 6049 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6050 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6051 "L2 pte @ %p\n", ptep); 6052 } 6053 } 6054 6055 #ifdef VERBOSE_INIT_ARM 6056 printf("cache(l1pt) "); 6057 #endif 6058 /* 6059 * Ensure the primary (kernel) L1 has the correct cache mode for 6060 * a page table. Bitch if it is not correctly set. 6061 */ 6062 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6063 L1_TABLE_SIZE / L2_S_SIZE)) { 6064 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6065 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6066 } 6067 6068 #ifdef PMAP_CACHE_VIVT 6069 cpu_dcache_wbinv_all(); 6070 cpu_tlb_flushID(); 6071 cpu_cpwait(); 6072 #endif 6073 6074 /* 6075 * now we allocate the "special" VAs which are used for tmp mappings 6076 * by the pmap (and other modules). we allocate the VAs by advancing 6077 * virtual_avail (note that there are no pages mapped at these VAs). 6078 * 6079 * Managed KVM space start from wherever initarm() tells us. 6080 */ 6081 virtual_avail = vstart; 6082 virtual_end = vend; 6083 6084 #ifdef VERBOSE_INIT_ARM 6085 printf("specials "); 6086 #endif 6087 #ifdef PMAP_CACHE_VIPT 6088 /* 6089 * If we have a VIPT cache, we need one page/pte per possible alias 6090 * page so we won't violate cache aliasing rules. 6091 */ 6092 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6093 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6094 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6095 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6096 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6097 } 6098 #else 6099 nptes = PAGE_SIZE / L2_S_SIZE; 6100 #endif 6101 #ifdef MULTIPROCESSOR 6102 cnptes = nptes; 6103 nptes *= arm_cpu_max; 6104 #endif 6105 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6106 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6107 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6108 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6109 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6110 if (msgbufaddr == NULL) { 6111 pmap_alloc_specials(&virtual_avail, 6112 round_page(MSGBUFSIZE) / PAGE_SIZE, 6113 (void *)&msgbufaddr, NULL); 6114 } 6115 6116 /* 6117 * Allocate a range of kernel virtual address space to be used 6118 * for L2 descriptor tables and metadata allocation in 6119 * pmap_growkernel(). 6120 */ 6121 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6122 pmap_alloc_specials(&virtual_avail, 6123 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6124 &pmap_kernel_l2ptp_kva, NULL); 6125 6126 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6127 pmap_alloc_specials(&virtual_avail, 6128 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6129 &pmap_kernel_l2dtable_kva, NULL); 6130 6131 #ifndef ARM_MMU_EXTENDED 6132 /* 6133 * init the static-global locks and global pmap list. 6134 */ 6135 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6136 6137 /* 6138 * We can now initialise the first L1's metadata. 6139 */ 6140 SLIST_INIT(&l1_list); 6141 TAILQ_INIT(&l1_lru_list); 6142 pmap_init_l1(l1, l1pt); 6143 #endif /* ARM_MMU_EXTENDED */ 6144 6145 #ifndef ARM_HAS_VBAR 6146 /* Set up vector page L1 details, if necessary */ 6147 if (vector_page < KERNEL_BASE) { 6148 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6149 l2b = pmap_get_l2_bucket(pm, vector_page); 6150 KDASSERT(l2b != NULL); 6151 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6152 L1_C_DOM(pmap_domain(pm)); 6153 } else 6154 pm->pm_pl1vec = NULL; 6155 #endif 6156 6157 #ifdef VERBOSE_INIT_ARM 6158 printf("pools "); 6159 #endif 6160 /* 6161 * Initialize the pmap cache 6162 */ 6163 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6164 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6165 LIST_INIT(&pmap_pmaps); 6166 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6167 6168 /* 6169 * Initialize the pv pool. 6170 */ 6171 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6172 &pmap_bootstrap_pv_allocator, IPL_NONE); 6173 6174 /* 6175 * Initialize the L2 dtable pool and cache. 6176 */ 6177 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6178 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6179 6180 /* 6181 * Initialise the L2 descriptor table pool and cache 6182 */ 6183 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6184 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6185 pmap_l2ptp_ctor, NULL, NULL); 6186 6187 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6188 6189 cpu_dcache_wbinv_all(); 6190 } 6191 6192 static bool 6193 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6194 { 6195 #ifdef ARM_MMU_EXTENDED 6196 return false; 6197 #else 6198 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6199 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6200 return false; 6201 6202 const vaddr_t eva = va + nptes * PAGE_SIZE; 6203 int rv = 0; 6204 6205 while (va < eva) { 6206 /* 6207 * Make sure the descriptor itself has the correct cache mode 6208 */ 6209 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6210 pd_entry_t pde = *pdep; 6211 6212 if (l1pte_section_p(pde)) { 6213 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6214 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6215 *pdep = (pde & ~L1_S_CACHE_MASK) | 6216 pte_l1_s_cache_mode_pt; 6217 PDE_SYNC(pdep); 6218 cpu_dcache_wbinv_range((vaddr_t)pdep, 6219 sizeof(*pdep)); 6220 rv = 1; 6221 } 6222 return rv; 6223 if (pde & L1_S_V6_SUPER) { 6224 va = (va & -L1_SS_SIZE) + L1_SS_SIZE; 6225 } else { 6226 va = (va & -L1_S_SIZE) + L1_S_SIZE; 6227 } 6228 continue; 6229 } 6230 vaddr_t pa = l1pte_pa(pde); 6231 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6232 if (ptep == NULL) 6233 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6234 6235 ptep += l2pte_index(va); 6236 const pt_entry_t opte = *ptep; 6237 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6238 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6239 | pte_l2_s_cache_mode_pt; 6240 l2pte_set(ptep, npte, opte); 6241 PTE_SYNC(ptep); 6242 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6243 rv = 1; 6244 } 6245 va += PAGE_SIZE; 6246 } 6247 6248 return (rv); 6249 #endif 6250 } 6251 6252 static void 6253 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6254 { 6255 vaddr_t va = *availp; 6256 struct l2_bucket *l2b; 6257 6258 if (ptep) { 6259 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6260 if (l2b == NULL) 6261 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6262 6263 if (ptep) 6264 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6265 } 6266 6267 *vap = va; 6268 *availp = va + (PAGE_SIZE * pages); 6269 } 6270 6271 void 6272 pmap_init(void) 6273 { 6274 6275 /* 6276 * Set the available memory vars - These do not map to real memory 6277 * addresses and cannot as the physical memory is fragmented. 6278 * They are used by ps for %mem calculations. 6279 * One could argue whether this should be the entire memory or just 6280 * the memory that is useable in a user process. 6281 */ 6282 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6283 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6284 6285 /* 6286 * Now we need to free enough pv_entry structures to allow us to get 6287 * the kmem_map/kmem_object allocated and inited (done after this 6288 * function is finished). to do this we allocate one bootstrap page out 6289 * of kernel_map and use it to provide an initial pool of pv_entry 6290 * structures. we never free this page. 6291 */ 6292 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6293 6294 #ifdef ARM_MMU_EXTENDED 6295 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6296 #endif 6297 6298 pmap_initialized = true; 6299 } 6300 6301 static vaddr_t last_bootstrap_page = 0; 6302 static void *free_bootstrap_pages = NULL; 6303 6304 static void * 6305 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6306 { 6307 extern void *pool_page_alloc(struct pool *, int); 6308 vaddr_t new_page; 6309 void *rv; 6310 6311 if (pmap_initialized) 6312 return (pool_page_alloc(pp, flags)); 6313 6314 if (free_bootstrap_pages) { 6315 rv = free_bootstrap_pages; 6316 free_bootstrap_pages = *((void **)rv); 6317 return (rv); 6318 } 6319 6320 KASSERT(kernel_map != NULL); 6321 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6322 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6323 6324 KASSERT(new_page > last_bootstrap_page); 6325 last_bootstrap_page = new_page; 6326 return ((void *)new_page); 6327 } 6328 6329 static void 6330 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6331 { 6332 extern void pool_page_free(struct pool *, void *); 6333 6334 if ((vaddr_t)v <= last_bootstrap_page) { 6335 *((void **)v) = free_bootstrap_pages; 6336 free_bootstrap_pages = v; 6337 return; 6338 } 6339 6340 if (pmap_initialized) { 6341 pool_page_free(pp, v); 6342 return; 6343 } 6344 } 6345 6346 /* 6347 * pmap_postinit() 6348 * 6349 * This routine is called after the vm and kmem subsystems have been 6350 * initialised. This allows the pmap code to perform any initialisation 6351 * that can only be done one the memory allocation is in place. 6352 */ 6353 void 6354 pmap_postinit(void) 6355 { 6356 #ifndef ARM_MMU_EXTENDED 6357 extern paddr_t physical_start, physical_end; 6358 struct l1_ttable *l1; 6359 struct pglist plist; 6360 struct vm_page *m; 6361 pd_entry_t *pdep; 6362 vaddr_t va, eva; 6363 u_int loop, needed; 6364 int error; 6365 #endif 6366 6367 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6368 pool_cache_setlowat(&pmap_l2dtable_cache, 6369 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6370 6371 #ifndef ARM_MMU_EXTENDED 6372 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6373 needed -= 1; 6374 6375 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6376 6377 for (loop = 0; loop < needed; loop++, l1++) { 6378 /* Allocate a L1 page table */ 6379 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6380 if (va == 0) 6381 panic("Cannot allocate L1 KVM"); 6382 6383 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6384 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6385 if (error) 6386 panic("Cannot allocate L1 physical pages"); 6387 6388 m = TAILQ_FIRST(&plist); 6389 eva = va + L1_TABLE_SIZE; 6390 pdep = (pd_entry_t *)va; 6391 6392 while (m && va < eva) { 6393 paddr_t pa = VM_PAGE_TO_PHYS(m); 6394 6395 pmap_kenter_pa(va, pa, 6396 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6397 6398 va += PAGE_SIZE; 6399 m = TAILQ_NEXT(m, pageq.queue); 6400 } 6401 6402 #ifdef DIAGNOSTIC 6403 if (m) 6404 panic("pmap_alloc_l1pt: pglist not empty"); 6405 #endif /* DIAGNOSTIC */ 6406 6407 pmap_init_l1(l1, pdep); 6408 } 6409 6410 #ifdef DEBUG 6411 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6412 needed); 6413 #endif 6414 #endif /* !ARM_MMU_EXTENDED */ 6415 } 6416 6417 /* 6418 * Note that the following routines are used by board-specific initialisation 6419 * code to configure the initial kernel page tables. 6420 * 6421 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6422 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6423 * behaviour of the old pmap, and provides an easy migration path for 6424 * initial bring-up of the new pmap on existing ports. Fortunately, 6425 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6426 * will be deprecated. 6427 * 6428 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6429 * tables. 6430 */ 6431 6432 /* 6433 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6434 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6435 * find them as necessary. 6436 * 6437 * Note that the data on this list MUST remain valid after initarm() returns, 6438 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6439 */ 6440 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6441 6442 static vaddr_t 6443 kernel_pt_lookup(paddr_t pa) 6444 { 6445 pv_addr_t *pv; 6446 6447 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6448 if (pv->pv_pa == (pa & ~PGOFSET)) 6449 return (pv->pv_va | (pa & PGOFSET)); 6450 } 6451 return (0); 6452 } 6453 6454 /* 6455 * pmap_map_section: 6456 * 6457 * Create a single section mapping. 6458 */ 6459 void 6460 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6461 { 6462 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6463 const size_t l1slot = l1pte_index(va); 6464 pd_entry_t fl; 6465 6466 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6467 6468 switch (cache) { 6469 case PTE_NOCACHE: 6470 default: 6471 fl = 0; 6472 break; 6473 6474 case PTE_CACHE: 6475 fl = pte_l1_s_cache_mode; 6476 break; 6477 6478 case PTE_PAGETABLE: 6479 fl = pte_l1_s_cache_mode_pt; 6480 break; 6481 } 6482 6483 const pd_entry_t npde = L1_S_PROTO | pa | 6484 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6485 l1pte_setone(pdep + l1slot, npde); 6486 PDE_SYNC(pdep + l1slot); 6487 } 6488 6489 /* 6490 * pmap_map_entry: 6491 * 6492 * Create a single page mapping. 6493 */ 6494 void 6495 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6496 { 6497 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6498 const size_t l1slot = l1pte_index(va); 6499 pt_entry_t npte; 6500 pt_entry_t *ptep; 6501 6502 KASSERT(((va | pa) & PGOFSET) == 0); 6503 6504 switch (cache) { 6505 case PTE_NOCACHE: 6506 default: 6507 npte = 0; 6508 break; 6509 6510 case PTE_CACHE: 6511 npte = pte_l2_s_cache_mode; 6512 break; 6513 6514 case PTE_PAGETABLE: 6515 npte = pte_l2_s_cache_mode_pt; 6516 break; 6517 } 6518 6519 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6520 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6521 6522 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6523 if (ptep == NULL) 6524 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6525 6526 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6527 #ifdef ARM_MMU_EXTENDED 6528 if (prot & VM_PROT_EXECUTE) { 6529 npte &= ~L2_XS_XN; 6530 } 6531 #endif 6532 ptep += l2pte_index(va); 6533 l2pte_set(ptep, npte, 0); 6534 PTE_SYNC(ptep); 6535 } 6536 6537 /* 6538 * pmap_link_l2pt: 6539 * 6540 * Link the L2 page table specified by "l2pv" into the L1 6541 * page table at the slot for "va". 6542 */ 6543 void 6544 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6545 { 6546 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6547 6548 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6549 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6550 6551 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6552 | l2pv->pv_pa; 6553 6554 l1pte_set(pdep, npde); 6555 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6556 6557 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6558 } 6559 6560 /* 6561 * pmap_map_chunk: 6562 * 6563 * Map a chunk of memory using the most efficient mappings 6564 * possible (section, large page, small page) into the 6565 * provided L1 and L2 tables at the specified virtual address. 6566 */ 6567 vsize_t 6568 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6569 int prot, int cache) 6570 { 6571 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6572 pt_entry_t f1, f2s, f2l; 6573 vsize_t resid; 6574 6575 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6576 6577 if (l1pt == 0) 6578 panic("pmap_map_chunk: no L1 table provided"); 6579 6580 #ifdef VERBOSE_INIT_ARM 6581 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6582 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6583 #endif 6584 6585 switch (cache) { 6586 case PTE_NOCACHE: 6587 default: 6588 f1 = 0; 6589 f2l = 0; 6590 f2s = 0; 6591 break; 6592 6593 case PTE_CACHE: 6594 f1 = pte_l1_s_cache_mode; 6595 f2l = pte_l2_l_cache_mode; 6596 f2s = pte_l2_s_cache_mode; 6597 break; 6598 6599 case PTE_PAGETABLE: 6600 f1 = pte_l1_s_cache_mode_pt; 6601 f2l = pte_l2_l_cache_mode_pt; 6602 f2s = pte_l2_s_cache_mode_pt; 6603 break; 6604 } 6605 6606 size = resid; 6607 6608 while (resid > 0) { 6609 const size_t l1slot = l1pte_index(va); 6610 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6611 /* See if we can use a supersection mapping. */ 6612 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6613 /* Supersection are always domain 0 */ 6614 const pd_entry_t npde = L1_SS_PROTO | pa 6615 #ifdef ARM_MMU_EXTENDED_XXX 6616 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6617 #endif 6618 #ifdef ARM_MMU_EXTENDED 6619 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6620 #endif 6621 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6622 #ifdef VERBOSE_INIT_ARM 6623 printf("sS"); 6624 #endif 6625 l1pte_set(&pdep[l1slot], npde); 6626 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6627 va += L1_SS_SIZE; 6628 pa += L1_SS_SIZE; 6629 resid -= L1_SS_SIZE; 6630 continue; 6631 } 6632 #endif 6633 /* See if we can use a section mapping. */ 6634 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6635 const pd_entry_t npde = L1_S_PROTO | pa 6636 #ifdef ARM_MMU_EXTENDED_XXX 6637 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6638 #endif 6639 #ifdef ARM_MMU_EXTENDED 6640 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6641 #endif 6642 | L1_S_PROT(PTE_KERNEL, prot) | f1 6643 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6644 #ifdef VERBOSE_INIT_ARM 6645 printf("S"); 6646 #endif 6647 l1pte_set(&pdep[l1slot], npde); 6648 PDE_SYNC(&pdep[l1slot]); 6649 va += L1_S_SIZE; 6650 pa += L1_S_SIZE; 6651 resid -= L1_S_SIZE; 6652 continue; 6653 } 6654 6655 /* 6656 * Ok, we're going to use an L2 table. Make sure 6657 * one is actually in the corresponding L1 slot 6658 * for the current VA. 6659 */ 6660 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6661 panic("%s: no L2 table for VA %#lx", __func__, va); 6662 6663 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6664 if (ptep == NULL) 6665 panic("%s: can't find L2 table for VA %#lx", __func__, 6666 va); 6667 6668 ptep += l2pte_index(va); 6669 6670 /* See if we can use a L2 large page mapping. */ 6671 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6672 const pt_entry_t npte = L2_L_PROTO | pa 6673 #ifdef ARM_MMU_EXTENDED_XXX 6674 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6675 #endif 6676 #ifdef ARM_MMU_EXTENDED 6677 | (va & 0x80000000 ? 0 : L2_XS_nG) 6678 #endif 6679 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6680 #ifdef VERBOSE_INIT_ARM 6681 printf("L"); 6682 #endif 6683 l2pte_set(ptep, npte, 0); 6684 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6685 va += L2_L_SIZE; 6686 pa += L2_L_SIZE; 6687 resid -= L2_L_SIZE; 6688 continue; 6689 } 6690 6691 /* Use a small page mapping. */ 6692 #ifdef VERBOSE_INIT_ARM 6693 printf("P"); 6694 #endif 6695 const pt_entry_t npte = L2_S_PROTO | pa 6696 #ifdef ARM_MMU_EXTENDED_XXX 6697 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6698 #endif 6699 #ifdef ARM_MMU_EXTENDED 6700 | (va & 0x80000000 ? 0 : L2_XS_nG) 6701 #endif 6702 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6703 l2pte_set(ptep, npte, 0); 6704 PTE_SYNC(ptep); 6705 va += PAGE_SIZE; 6706 pa += PAGE_SIZE; 6707 resid -= PAGE_SIZE; 6708 } 6709 #ifdef VERBOSE_INIT_ARM 6710 printf("\n"); 6711 #endif 6712 return (size); 6713 } 6714 6715 /********************** Static device map routines ***************************/ 6716 6717 static const struct pmap_devmap *pmap_devmap_table; 6718 6719 /* 6720 * Register the devmap table. This is provided in case early console 6721 * initialization needs to register mappings created by bootstrap code 6722 * before pmap_devmap_bootstrap() is called. 6723 */ 6724 void 6725 pmap_devmap_register(const struct pmap_devmap *table) 6726 { 6727 6728 pmap_devmap_table = table; 6729 } 6730 6731 /* 6732 * Map all of the static regions in the devmap table, and remember 6733 * the devmap table so other parts of the kernel can look up entries 6734 * later. 6735 */ 6736 void 6737 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6738 { 6739 int i; 6740 6741 pmap_devmap_table = table; 6742 6743 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6744 #ifdef VERBOSE_INIT_ARM 6745 printf("devmap: %08lx -> %08lx @ %08lx\n", 6746 pmap_devmap_table[i].pd_pa, 6747 pmap_devmap_table[i].pd_pa + 6748 pmap_devmap_table[i].pd_size - 1, 6749 pmap_devmap_table[i].pd_va); 6750 #endif 6751 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6752 pmap_devmap_table[i].pd_pa, 6753 pmap_devmap_table[i].pd_size, 6754 pmap_devmap_table[i].pd_prot, 6755 pmap_devmap_table[i].pd_cache); 6756 } 6757 } 6758 6759 const struct pmap_devmap * 6760 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6761 { 6762 uint64_t endpa; 6763 int i; 6764 6765 if (pmap_devmap_table == NULL) 6766 return (NULL); 6767 6768 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6769 6770 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6771 if (pa >= pmap_devmap_table[i].pd_pa && 6772 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6773 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6774 return (&pmap_devmap_table[i]); 6775 } 6776 6777 return (NULL); 6778 } 6779 6780 const struct pmap_devmap * 6781 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6782 { 6783 int i; 6784 6785 if (pmap_devmap_table == NULL) 6786 return (NULL); 6787 6788 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6789 if (va >= pmap_devmap_table[i].pd_va && 6790 va + size - 1 <= pmap_devmap_table[i].pd_va + 6791 pmap_devmap_table[i].pd_size - 1) 6792 return (&pmap_devmap_table[i]); 6793 } 6794 6795 return (NULL); 6796 } 6797 6798 /********************** PTE initialization routines **************************/ 6799 6800 /* 6801 * These routines are called when the CPU type is identified to set up 6802 * the PTE prototypes, cache modes, etc. 6803 * 6804 * The variables are always here, just in case modules need to reference 6805 * them (though, they shouldn't). 6806 */ 6807 6808 pt_entry_t pte_l1_s_cache_mode; 6809 pt_entry_t pte_l1_s_wc_mode; 6810 pt_entry_t pte_l1_s_cache_mode_pt; 6811 pt_entry_t pte_l1_s_cache_mask; 6812 6813 pt_entry_t pte_l2_l_cache_mode; 6814 pt_entry_t pte_l2_l_wc_mode; 6815 pt_entry_t pte_l2_l_cache_mode_pt; 6816 pt_entry_t pte_l2_l_cache_mask; 6817 6818 pt_entry_t pte_l2_s_cache_mode; 6819 pt_entry_t pte_l2_s_wc_mode; 6820 pt_entry_t pte_l2_s_cache_mode_pt; 6821 pt_entry_t pte_l2_s_cache_mask; 6822 6823 pt_entry_t pte_l1_s_prot_u; 6824 pt_entry_t pte_l1_s_prot_w; 6825 pt_entry_t pte_l1_s_prot_ro; 6826 pt_entry_t pte_l1_s_prot_mask; 6827 6828 pt_entry_t pte_l2_s_prot_u; 6829 pt_entry_t pte_l2_s_prot_w; 6830 pt_entry_t pte_l2_s_prot_ro; 6831 pt_entry_t pte_l2_s_prot_mask; 6832 6833 pt_entry_t pte_l2_l_prot_u; 6834 pt_entry_t pte_l2_l_prot_w; 6835 pt_entry_t pte_l2_l_prot_ro; 6836 pt_entry_t pte_l2_l_prot_mask; 6837 6838 pt_entry_t pte_l1_ss_proto; 6839 pt_entry_t pte_l1_s_proto; 6840 pt_entry_t pte_l1_c_proto; 6841 pt_entry_t pte_l2_s_proto; 6842 6843 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6844 void (*pmap_zero_page_func)(paddr_t); 6845 6846 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6847 void 6848 pmap_pte_init_generic(void) 6849 { 6850 6851 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6852 pte_l1_s_wc_mode = L1_S_B; 6853 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6854 6855 pte_l2_l_cache_mode = L2_B|L2_C; 6856 pte_l2_l_wc_mode = L2_B; 6857 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6858 6859 pte_l2_s_cache_mode = L2_B|L2_C; 6860 pte_l2_s_wc_mode = L2_B; 6861 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6862 6863 /* 6864 * If we have a write-through cache, set B and C. If 6865 * we have a write-back cache, then we assume setting 6866 * only C will make those pages write-through (except for those 6867 * Cortex CPUs which can read the L1 caches). 6868 */ 6869 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6870 #if ARM_MMU_V7 > 0 6871 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6872 #endif 6873 #if ARM_MMU_V6 > 0 6874 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6875 #endif 6876 || false) { 6877 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6878 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6879 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6880 } else { 6881 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6882 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6883 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6884 } 6885 6886 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6887 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6888 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6889 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6890 6891 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6892 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6893 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6894 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6895 6896 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6897 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6898 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6899 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6900 6901 pte_l1_ss_proto = L1_SS_PROTO_generic; 6902 pte_l1_s_proto = L1_S_PROTO_generic; 6903 pte_l1_c_proto = L1_C_PROTO_generic; 6904 pte_l2_s_proto = L2_S_PROTO_generic; 6905 6906 pmap_copy_page_func = pmap_copy_page_generic; 6907 pmap_zero_page_func = pmap_zero_page_generic; 6908 } 6909 6910 #if defined(CPU_ARM8) 6911 void 6912 pmap_pte_init_arm8(void) 6913 { 6914 6915 /* 6916 * ARM8 is compatible with generic, but we need to use 6917 * the page tables uncached. 6918 */ 6919 pmap_pte_init_generic(); 6920 6921 pte_l1_s_cache_mode_pt = 0; 6922 pte_l2_l_cache_mode_pt = 0; 6923 pte_l2_s_cache_mode_pt = 0; 6924 } 6925 #endif /* CPU_ARM8 */ 6926 6927 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6928 void 6929 pmap_pte_init_arm9(void) 6930 { 6931 6932 /* 6933 * ARM9 is compatible with generic, but we want to use 6934 * write-through caching for now. 6935 */ 6936 pmap_pte_init_generic(); 6937 6938 pte_l1_s_cache_mode = L1_S_C; 6939 pte_l2_l_cache_mode = L2_C; 6940 pte_l2_s_cache_mode = L2_C; 6941 6942 pte_l1_s_wc_mode = L1_S_B; 6943 pte_l2_l_wc_mode = L2_B; 6944 pte_l2_s_wc_mode = L2_B; 6945 6946 pte_l1_s_cache_mode_pt = L1_S_C; 6947 pte_l2_l_cache_mode_pt = L2_C; 6948 pte_l2_s_cache_mode_pt = L2_C; 6949 } 6950 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6951 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6952 6953 #if defined(CPU_ARM10) 6954 void 6955 pmap_pte_init_arm10(void) 6956 { 6957 6958 /* 6959 * ARM10 is compatible with generic, but we want to use 6960 * write-through caching for now. 6961 */ 6962 pmap_pte_init_generic(); 6963 6964 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6965 pte_l2_l_cache_mode = L2_B | L2_C; 6966 pte_l2_s_cache_mode = L2_B | L2_C; 6967 6968 pte_l1_s_cache_mode = L1_S_B; 6969 pte_l2_l_cache_mode = L2_B; 6970 pte_l2_s_cache_mode = L2_B; 6971 6972 pte_l1_s_cache_mode_pt = L1_S_C; 6973 pte_l2_l_cache_mode_pt = L2_C; 6974 pte_l2_s_cache_mode_pt = L2_C; 6975 6976 } 6977 #endif /* CPU_ARM10 */ 6978 6979 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6980 void 6981 pmap_pte_init_arm11(void) 6982 { 6983 6984 /* 6985 * ARM11 is compatible with generic, but we want to use 6986 * write-through caching for now. 6987 */ 6988 pmap_pte_init_generic(); 6989 6990 pte_l1_s_cache_mode = L1_S_C; 6991 pte_l2_l_cache_mode = L2_C; 6992 pte_l2_s_cache_mode = L2_C; 6993 6994 pte_l1_s_wc_mode = L1_S_B; 6995 pte_l2_l_wc_mode = L2_B; 6996 pte_l2_s_wc_mode = L2_B; 6997 6998 pte_l1_s_cache_mode_pt = L1_S_C; 6999 pte_l2_l_cache_mode_pt = L2_C; 7000 pte_l2_s_cache_mode_pt = L2_C; 7001 } 7002 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7003 7004 #if ARM_MMU_SA1 == 1 7005 void 7006 pmap_pte_init_sa1(void) 7007 { 7008 7009 /* 7010 * The StrongARM SA-1 cache does not have a write-through 7011 * mode. So, do the generic initialization, then reset 7012 * the page table cache mode to B=1,C=1, and note that 7013 * the PTEs need to be sync'd. 7014 */ 7015 pmap_pte_init_generic(); 7016 7017 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7018 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7019 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7020 7021 pmap_needs_pte_sync = 1; 7022 } 7023 #endif /* ARM_MMU_SA1 == 1*/ 7024 7025 #if ARM_MMU_XSCALE == 1 7026 #if (ARM_NMMUS > 1) 7027 static u_int xscale_use_minidata; 7028 #endif 7029 7030 void 7031 pmap_pte_init_xscale(void) 7032 { 7033 uint32_t auxctl; 7034 int write_through = 0; 7035 7036 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7037 pte_l1_s_wc_mode = L1_S_B; 7038 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7039 7040 pte_l2_l_cache_mode = L2_B|L2_C; 7041 pte_l2_l_wc_mode = L2_B; 7042 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7043 7044 pte_l2_s_cache_mode = L2_B|L2_C; 7045 pte_l2_s_wc_mode = L2_B; 7046 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7047 7048 pte_l1_s_cache_mode_pt = L1_S_C; 7049 pte_l2_l_cache_mode_pt = L2_C; 7050 pte_l2_s_cache_mode_pt = L2_C; 7051 7052 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7053 /* 7054 * The XScale core has an enhanced mode where writes that 7055 * miss the cache cause a cache line to be allocated. This 7056 * is significantly faster than the traditional, write-through 7057 * behavior of this case. 7058 */ 7059 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7060 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7061 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7062 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7063 7064 #ifdef XSCALE_CACHE_WRITE_THROUGH 7065 /* 7066 * Some versions of the XScale core have various bugs in 7067 * their cache units, the work-around for which is to run 7068 * the cache in write-through mode. Unfortunately, this 7069 * has a major (negative) impact on performance. So, we 7070 * go ahead and run fast-and-loose, in the hopes that we 7071 * don't line up the planets in a way that will trip the 7072 * bugs. 7073 * 7074 * However, we give you the option to be slow-but-correct. 7075 */ 7076 write_through = 1; 7077 #elif defined(XSCALE_CACHE_WRITE_BACK) 7078 /* force write back cache mode */ 7079 write_through = 0; 7080 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7081 /* 7082 * Intel PXA2[15]0 processors are known to have a bug in 7083 * write-back cache on revision 4 and earlier (stepping 7084 * A[01] and B[012]). Fixed for C0 and later. 7085 */ 7086 { 7087 uint32_t id, type; 7088 7089 id = cpufunc_id(); 7090 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7091 7092 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7093 if ((id & CPU_ID_REVISION_MASK) < 5) { 7094 /* write through for stepping A0-1 and B0-2 */ 7095 write_through = 1; 7096 } 7097 } 7098 } 7099 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7100 7101 if (write_through) { 7102 pte_l1_s_cache_mode = L1_S_C; 7103 pte_l2_l_cache_mode = L2_C; 7104 pte_l2_s_cache_mode = L2_C; 7105 } 7106 7107 #if (ARM_NMMUS > 1) 7108 xscale_use_minidata = 1; 7109 #endif 7110 7111 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7112 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7113 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7114 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7115 7116 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7117 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7118 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7119 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7120 7121 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7122 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7123 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7124 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7125 7126 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7127 pte_l1_s_proto = L1_S_PROTO_xscale; 7128 pte_l1_c_proto = L1_C_PROTO_xscale; 7129 pte_l2_s_proto = L2_S_PROTO_xscale; 7130 7131 pmap_copy_page_func = pmap_copy_page_xscale; 7132 pmap_zero_page_func = pmap_zero_page_xscale; 7133 7134 /* 7135 * Disable ECC protection of page table access, for now. 7136 */ 7137 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7138 auxctl &= ~XSCALE_AUXCTL_P; 7139 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7140 } 7141 7142 /* 7143 * xscale_setup_minidata: 7144 * 7145 * Set up the mini-data cache clean area. We require the 7146 * caller to allocate the right amount of physically and 7147 * virtually contiguous space. 7148 */ 7149 void 7150 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7151 { 7152 extern vaddr_t xscale_minidata_clean_addr; 7153 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7154 pd_entry_t *pde = (pd_entry_t *) l1pt; 7155 vsize_t size; 7156 uint32_t auxctl; 7157 7158 xscale_minidata_clean_addr = va; 7159 7160 /* Round it to page size. */ 7161 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7162 7163 for (; size != 0; 7164 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7165 const size_t l1slot = l1pte_index(va); 7166 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7167 if (ptep == NULL) 7168 panic("xscale_setup_minidata: can't find L2 table for " 7169 "VA 0x%08lx", va); 7170 7171 ptep += l2pte_index(va); 7172 pt_entry_t opte = *ptep; 7173 l2pte_set(ptep, 7174 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7175 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7176 } 7177 7178 /* 7179 * Configure the mini-data cache for write-back with 7180 * read/write-allocate. 7181 * 7182 * NOTE: In order to reconfigure the mini-data cache, we must 7183 * make sure it contains no valid data! In order to do that, 7184 * we must issue a global data cache invalidate command! 7185 * 7186 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7187 * THIS IS VERY IMPORTANT! 7188 */ 7189 7190 /* Invalidate data and mini-data. */ 7191 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7192 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7193 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7194 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7195 } 7196 7197 /* 7198 * Change the PTEs for the specified kernel mappings such that they 7199 * will use the mini data cache instead of the main data cache. 7200 */ 7201 void 7202 pmap_uarea(vaddr_t va) 7203 { 7204 vaddr_t next_bucket, eva; 7205 7206 #if (ARM_NMMUS > 1) 7207 if (xscale_use_minidata == 0) 7208 return; 7209 #endif 7210 7211 eva = va + USPACE; 7212 7213 while (va < eva) { 7214 next_bucket = L2_NEXT_BUCKET_VA(va); 7215 if (next_bucket > eva) 7216 next_bucket = eva; 7217 7218 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7219 KDASSERT(l2b != NULL); 7220 7221 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7222 pt_entry_t *ptep = sptep; 7223 7224 while (va < next_bucket) { 7225 const pt_entry_t opte = *ptep; 7226 if (!l2pte_minidata_p(opte)) { 7227 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7228 cpu_tlb_flushD_SE(va); 7229 l2pte_set(ptep, opte & ~L2_B, opte); 7230 } 7231 ptep += PAGE_SIZE / L2_S_SIZE; 7232 va += PAGE_SIZE; 7233 } 7234 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7235 } 7236 cpu_cpwait(); 7237 } 7238 #endif /* ARM_MMU_XSCALE == 1 */ 7239 7240 7241 #if defined(CPU_ARM11MPCORE) 7242 7243 void 7244 pmap_pte_init_arm11mpcore(void) 7245 { 7246 7247 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7248 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7249 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7250 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7251 /* use extended small page (without APn, with TEX) */ 7252 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7253 #else 7254 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7255 #endif 7256 7257 /* write-back, write-allocate */ 7258 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7259 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7260 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7261 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7262 #else 7263 /* no TEX. read-allocate */ 7264 pte_l2_s_cache_mode = L2_C | L2_B; 7265 #endif 7266 /* 7267 * write-back, write-allocate for page tables. 7268 */ 7269 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7270 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7271 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7272 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7273 #else 7274 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7275 #endif 7276 7277 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7278 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7279 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7280 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7281 7282 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7283 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7284 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7285 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7286 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7287 7288 #else 7289 /* with AP[0..3] */ 7290 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7291 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7292 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7293 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7294 #endif 7295 7296 #ifdef ARM11MPCORE_COMPAT_MMU 7297 /* with AP[0..3] */ 7298 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7299 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7300 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7301 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7302 7303 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7304 pte_l1_s_proto = L1_S_PROTO_armv6; 7305 pte_l1_c_proto = L1_C_PROTO_armv6; 7306 pte_l2_s_proto = L2_S_PROTO_armv6c; 7307 #else 7308 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7309 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7310 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7311 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7312 7313 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7314 pte_l1_s_proto = L1_S_PROTO_armv6; 7315 pte_l1_c_proto = L1_C_PROTO_armv6; 7316 pte_l2_s_proto = L2_S_PROTO_armv6n; 7317 #endif 7318 7319 pmap_copy_page_func = pmap_copy_page_generic; 7320 pmap_zero_page_func = pmap_zero_page_generic; 7321 pmap_needs_pte_sync = 1; 7322 } 7323 #endif /* CPU_ARM11MPCORE */ 7324 7325 7326 #if ARM_MMU_V7 == 1 7327 void 7328 pmap_pte_init_armv7(void) 7329 { 7330 /* 7331 * The ARMv7-A MMU is mostly compatible with generic. If the 7332 * AP field is zero, that now means "no access" rather than 7333 * read-only. The prototypes are a little different because of 7334 * the XN bit. 7335 */ 7336 pmap_pte_init_generic(); 7337 7338 pmap_needs_pte_sync = 1; 7339 7340 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7341 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7342 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7343 7344 /* 7345 * If the core support coherent walk then updates to translation tables 7346 * do not require a clean to the point of unification to ensure 7347 * visibility by subsequent translation table walks. That means we can 7348 * map everything shareable and cached and the right thing will happen. 7349 */ 7350 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7351 pmap_needs_pte_sync = 0; 7352 7353 /* 7354 * write-back, no write-allocate, shareable for normal pages. 7355 */ 7356 pte_l1_s_cache_mode |= L1_S_V6_S; 7357 pte_l2_l_cache_mode |= L2_XS_S; 7358 pte_l2_s_cache_mode |= L2_XS_S; 7359 } 7360 7361 /* 7362 * Page tables are just all other memory. We can use write-back since 7363 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7364 */ 7365 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7366 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7367 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7368 7369 /* 7370 * Check the Memory Model Features to see if this CPU supports 7371 * the TLBIASID coproc op. 7372 */ 7373 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7374 arm_has_tlbiasid_p = true; 7375 } 7376 7377 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7378 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7379 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7380 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7381 7382 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7383 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7384 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7385 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7386 7387 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7388 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7389 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7390 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7391 7392 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7393 pte_l1_s_proto = L1_S_PROTO_armv7; 7394 pte_l1_c_proto = L1_C_PROTO_armv7; 7395 pte_l2_s_proto = L2_S_PROTO_armv7; 7396 7397 } 7398 #endif /* ARM_MMU_V7 */ 7399 7400 /* 7401 * return the PA of the current L1 table, for use when handling a crash dump 7402 */ 7403 uint32_t 7404 pmap_kernel_L1_addr(void) 7405 { 7406 #ifdef ARM_MMU_EXTENDED 7407 return pmap_kernel()->pm_l1_pa; 7408 #else 7409 return pmap_kernel()->pm_l1->l1_physaddr; 7410 #endif 7411 } 7412 7413 #if defined(DDB) 7414 /* 7415 * A couple of ddb-callable functions for dumping pmaps 7416 */ 7417 void pmap_dump_all(void); 7418 void pmap_dump(pmap_t); 7419 7420 void 7421 pmap_dump_all(void) 7422 { 7423 pmap_t pm; 7424 7425 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7426 if (pm == pmap_kernel()) 7427 continue; 7428 pmap_dump(pm); 7429 printf("\n"); 7430 } 7431 } 7432 7433 static pt_entry_t ncptes[64]; 7434 static void pmap_dump_ncpg(pmap_t); 7435 7436 void 7437 pmap_dump(pmap_t pm) 7438 { 7439 struct l2_dtable *l2; 7440 struct l2_bucket *l2b; 7441 pt_entry_t *ptep, pte; 7442 vaddr_t l2_va, l2b_va, va; 7443 int i, j, k, occ, rows = 0; 7444 7445 if (pm == pmap_kernel()) 7446 printf("pmap_kernel (%p): ", pm); 7447 else 7448 printf("user pmap (%p): ", pm); 7449 7450 #ifdef ARM_MMU_EXTENDED 7451 printf("l1 at %p\n", pmap_l1_kva(pm)); 7452 #else 7453 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7454 #endif 7455 7456 l2_va = 0; 7457 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7458 l2 = pm->pm_l2[i]; 7459 7460 if (l2 == NULL || l2->l2_occupancy == 0) 7461 continue; 7462 7463 l2b_va = l2_va; 7464 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7465 l2b = &l2->l2_bucket[j]; 7466 7467 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7468 continue; 7469 7470 ptep = l2b->l2b_kva; 7471 7472 for (k = 0; k < 256 && ptep[k] == 0; k++) 7473 ; 7474 7475 k &= ~63; 7476 occ = l2b->l2b_occupancy; 7477 va = l2b_va + (k * 4096); 7478 for (; k < 256; k++, va += 0x1000) { 7479 char ch = ' '; 7480 if ((k % 64) == 0) { 7481 if ((rows % 8) == 0) { 7482 printf( 7483 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7484 } 7485 printf("%08lx: ", va); 7486 } 7487 7488 ncptes[k & 63] = 0; 7489 pte = ptep[k]; 7490 if (pte == 0) { 7491 ch = '.'; 7492 } else { 7493 occ--; 7494 switch (pte & 0x0c) { 7495 case 0x00: 7496 ch = 'D'; /* No cache No buff */ 7497 break; 7498 case 0x04: 7499 ch = 'B'; /* No cache buff */ 7500 break; 7501 case 0x08: 7502 if (pte & 0x40) 7503 ch = 'm'; 7504 else 7505 ch = 'C'; /* Cache No buff */ 7506 break; 7507 case 0x0c: 7508 ch = 'F'; /* Cache Buff */ 7509 break; 7510 } 7511 7512 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7513 ch += 0x20; 7514 7515 if ((pte & 0xc) == 0) 7516 ncptes[k & 63] = pte; 7517 } 7518 7519 if ((k % 64) == 63) { 7520 rows++; 7521 printf("%c\n", ch); 7522 pmap_dump_ncpg(pm); 7523 if (occ == 0) 7524 break; 7525 } else 7526 printf("%c", ch); 7527 } 7528 } 7529 } 7530 } 7531 7532 static void 7533 pmap_dump_ncpg(pmap_t pm) 7534 { 7535 struct vm_page *pg; 7536 struct vm_page_md *md; 7537 struct pv_entry *pv; 7538 int i; 7539 7540 for (i = 0; i < 63; i++) { 7541 if (ncptes[i] == 0) 7542 continue; 7543 7544 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7545 if (pg == NULL) 7546 continue; 7547 md = VM_PAGE_TO_MD(pg); 7548 7549 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7550 VM_PAGE_TO_PHYS(pg), 7551 md->krw_mappings, md->kro_mappings, 7552 md->urw_mappings, md->uro_mappings); 7553 7554 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7555 printf(" %c va 0x%08lx, flags 0x%x\n", 7556 (pm == pv->pv_pmap) ? '*' : ' ', 7557 pv->pv_va, pv->pv_flags); 7558 } 7559 } 7560 } 7561 #endif 7562 7563 #ifdef PMAP_STEAL_MEMORY 7564 void 7565 pmap_boot_pageadd(pv_addr_t *newpv) 7566 { 7567 pv_addr_t *pv, *npv; 7568 7569 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7570 if (newpv->pv_pa < pv->pv_va) { 7571 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7572 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7573 newpv->pv_size += pv->pv_size; 7574 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7575 } 7576 pv = NULL; 7577 } else { 7578 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7579 pv = npv) { 7580 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7581 KASSERT(pv->pv_pa < newpv->pv_pa); 7582 if (newpv->pv_pa > npv->pv_pa) 7583 continue; 7584 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7585 pv->pv_size += newpv->pv_size; 7586 return; 7587 } 7588 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7589 break; 7590 newpv->pv_size += npv->pv_size; 7591 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7592 SLIST_REMOVE_AFTER(newpv, pv_list); 7593 return; 7594 } 7595 } 7596 } 7597 7598 if (pv) { 7599 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7600 } else { 7601 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7602 } 7603 } 7604 7605 void 7606 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7607 pv_addr_t *rpv) 7608 { 7609 pv_addr_t *pv, **pvp; 7610 struct vm_physseg *ps; 7611 size_t i; 7612 7613 KASSERT(amount & PGOFSET); 7614 KASSERT((mask & PGOFSET) == 0); 7615 KASSERT((match & PGOFSET) == 0); 7616 KASSERT(amount != 0); 7617 7618 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7619 (pv = *pvp) != NULL; 7620 pvp = &SLIST_NEXT(pv, pv_list)) { 7621 pv_addr_t *newpv; 7622 psize_t off; 7623 /* 7624 * If this entry is too small to satify the request... 7625 */ 7626 KASSERT(pv->pv_size > 0); 7627 if (pv->pv_size < amount) 7628 continue; 7629 7630 for (off = 0; off <= mask; off += PAGE_SIZE) { 7631 if (((pv->pv_pa + off) & mask) == match 7632 && off + amount <= pv->pv_size) 7633 break; 7634 } 7635 if (off > mask) 7636 continue; 7637 7638 rpv->pv_va = pv->pv_va + off; 7639 rpv->pv_pa = pv->pv_pa + off; 7640 rpv->pv_size = amount; 7641 pv->pv_size -= amount; 7642 if (pv->pv_size == 0) { 7643 KASSERT(off == 0); 7644 KASSERT((vaddr_t) pv == rpv->pv_va); 7645 *pvp = SLIST_NEXT(pv, pv_list); 7646 } else if (off == 0) { 7647 KASSERT((vaddr_t) pv == rpv->pv_va); 7648 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7649 *newpv = *pv; 7650 newpv->pv_pa += amount; 7651 newpv->pv_va += amount; 7652 *pvp = newpv; 7653 } else if (off < pv->pv_size) { 7654 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7655 *newpv = *pv; 7656 newpv->pv_size -= off; 7657 newpv->pv_pa += off + amount; 7658 newpv->pv_va += off + amount; 7659 7660 SLIST_NEXT(pv, pv_list) = newpv; 7661 pv->pv_size = off; 7662 } else { 7663 KASSERT((vaddr_t) pv != rpv->pv_va); 7664 } 7665 memset((void *)rpv->pv_va, 0, amount); 7666 return; 7667 } 7668 7669 if (vm_nphysseg == 0) 7670 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7671 7672 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7673 (pv = *pvp) != NULL; 7674 pvp = &SLIST_NEXT(pv, pv_list)) { 7675 if (SLIST_NEXT(pv, pv_list) == NULL) 7676 break; 7677 } 7678 KASSERT(mask == 0); 7679 for (i = 0; i < vm_nphysseg; i++) { 7680 ps = VM_PHYSMEM_PTR(i); 7681 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7682 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7683 rpv->pv_va = pv->pv_va; 7684 rpv->pv_pa = pv->pv_pa; 7685 rpv->pv_size = amount; 7686 *pvp = NULL; 7687 pmap_map_chunk(kernel_l1pt.pv_va, 7688 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7689 ptoa(ps->avail_start), 7690 amount - pv->pv_size, 7691 VM_PROT_READ|VM_PROT_WRITE, 7692 PTE_CACHE); 7693 ps->avail_start += atop(amount - pv->pv_size); 7694 /* 7695 * If we consumed the entire physseg, remove it. 7696 */ 7697 if (ps->avail_start == ps->avail_end) { 7698 for (--vm_nphysseg; i < vm_nphysseg; i++) 7699 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7700 } 7701 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7702 return; 7703 } 7704 } 7705 7706 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7707 } 7708 7709 vaddr_t 7710 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7711 { 7712 pv_addr_t pv; 7713 7714 pmap_boot_pagealloc(size, 0, 0, &pv); 7715 7716 return pv.pv_va; 7717 } 7718 #endif /* PMAP_STEAL_MEMORY */ 7719 7720 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7721 { 7722 sysctl_createv(clog, 0, NULL, NULL, 7723 CTLFLAG_PERMANENT, 7724 CTLTYPE_NODE, "machdep", NULL, 7725 NULL, 0, NULL, 0, 7726 CTL_MACHDEP, CTL_EOL); 7727 7728 sysctl_createv(clog, 0, NULL, NULL, 7729 CTLFLAG_PERMANENT, 7730 CTLTYPE_INT, "kmpages", 7731 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7732 NULL, 0, &pmap_kmpages, 0, 7733 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7734 } 7735 7736 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7737 struct vm_page * 7738 arm_pmap_alloc_poolpage(int flags) 7739 { 7740 /* 7741 * On some systems, only some pages may be "coherent" for dma and we 7742 * want to prefer those for pool pages (think mbufs) but fallback to 7743 * any page if none is available. But we can only fallback if we 7744 * aren't direct mapping memory or all of memory can be direct-mapped. 7745 * If that isn't true, pool changes can only come from direct-mapped 7746 * memory. 7747 */ 7748 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7749 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7750 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7751 (pmap_directbase < KERNEL_BASE 7752 ? UVM_PGA_STRAT_ONLY 7753 : UVM_PGA_STRAT_FALLBACK), 7754 #else 7755 UVM_PGA_STRAT_FALLBACK, 7756 #endif 7757 arm_poolpage_vmfreelist); 7758 } 7759 7760 return uvm_pagealloc(NULL, 0, NULL, flags); 7761 } 7762 #endif 7763 7764 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7765 void 7766 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7767 { 7768 /* nothing */ 7769 } 7770 7771 int 7772 pic_ipi_shootdown(void *arg) 7773 { 7774 #if PMAP_NEED_TLB_SHOOTDOWN 7775 pmap_tlb_shootdown_process() 7776 #endif 7777 return 1; 7778 } 7779 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7780 7781 7782 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7783 vaddr_t 7784 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7785 { 7786 bool ok = false; 7787 if (physical_start <= pa && pa < physical_end) { 7788 #ifdef ARM_MMU_EXTENDED 7789 const vaddr_t newva = pmap_directbase + pa - physical_start; 7790 if (newva >= KERNEL_BASE) { 7791 va = newva; 7792 ok = true; 7793 } 7794 #else 7795 va = KERNEL_BASE + pa - physical_start; 7796 ok = true; 7797 #endif 7798 } 7799 KASSERT(ok_p); 7800 *ok_p = ok; 7801 return va; 7802 } 7803 7804 vaddr_t 7805 pmap_map_poolpage(paddr_t pa) 7806 { 7807 bool ok __diagused; 7808 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7809 KASSERT(ok); 7810 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7811 if (arm_cache_prefer_mask != 0) { 7812 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7813 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7814 pmap_acquire_page_lock(md); 7815 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7816 pmap_release_page_lock(md); 7817 } 7818 #endif 7819 return va; 7820 } 7821 7822 paddr_t 7823 pmap_unmap_poolpage(vaddr_t va) 7824 { 7825 KASSERT(va >= KERNEL_BASE); 7826 #if defined(ARM_MMU_EXTENDED) 7827 return va - pmap_directbase + physical_start; 7828 #else 7829 #ifdef PMAP_CACHE_VIVT 7830 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7831 #endif 7832 return va - KERNEL_BASE + physical_start; 7833 #endif 7834 } 7835 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7836
Indexes created Fri Sep 26 20:09:58 GMT 2025