pmap.c revision 1.301
1 /* $NetBSD: pmap.c,v 1.301 2014/09/23 05:45:01 nonaka Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 //#include <arm/arm32/katelib.h> 218 219 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.301 2014/09/23 05:45:01 nonaka Exp $"); 220 221 //#define PMAP_DEBUG 222 #ifdef PMAP_DEBUG 223 224 /* XXX need to get rid of all refs to this */ 225 int pmap_debug_level = 0; 226 227 /* 228 * for switching to potentially finer grained debugging 229 */ 230 #define PDB_FOLLOW 0x0001 231 #define PDB_INIT 0x0002 232 #define PDB_ENTER 0x0004 233 #define PDB_REMOVE 0x0008 234 #define PDB_CREATE 0x0010 235 #define PDB_PTPAGE 0x0020 236 #define PDB_GROWKERN 0x0040 237 #define PDB_BITS 0x0080 238 #define PDB_COLLECT 0x0100 239 #define PDB_PROTECT 0x0200 240 #define PDB_MAP_L1 0x0400 241 #define PDB_BOOTSTRAP 0x1000 242 #define PDB_PARANOIA 0x2000 243 #define PDB_WIRING 0x4000 244 #define PDB_PVDUMP 0x8000 245 #define PDB_VAC 0x10000 246 #define PDB_KENTER 0x20000 247 #define PDB_KREMOVE 0x40000 248 #define PDB_EXEC 0x80000 249 250 int debugmap = 1; 251 int pmapdebug = 0; 252 #define NPDEBUG(_lev_,_stat_) \ 253 if (pmapdebug & (_lev_)) \ 254 ((_stat_)) 255 256 #else /* PMAP_DEBUG */ 257 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 258 #endif /* PMAP_DEBUG */ 259 260 /* 261 * pmap_kernel() points here 262 */ 263 static struct pmap kernel_pmap_store = { 264 #ifndef ARM_MMU_EXTENDED 265 .pm_activated = true, 266 .pm_domain = PMAP_DOMAIN_KERNEL, 267 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 268 #endif 269 }; 270 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 271 #undef pmap_kernel 272 #define pmap_kernel() (&kernel_pmap_store) 273 #ifdef PMAP_NEED_ALLOC_POOLPAGE 274 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 275 #endif 276 277 /* 278 * Pool and cache that pmap structures are allocated from. 279 * We use a cache to avoid clearing the pm_l2[] array (1KB) 280 * in pmap_create(). 281 */ 282 static struct pool_cache pmap_cache; 283 static LIST_HEAD(, pmap) pmap_pmaps; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 static struct evcnt pmap_ev_exec_synced_map = 426 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 427 #ifndef ARM_MMU_EXTENDED 428 static struct evcnt pmap_ev_exec_synced_unmap = 429 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 430 static struct evcnt pmap_ev_exec_synced_remap = 431 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 432 static struct evcnt pmap_ev_exec_synced_clearbit = 433 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 440 #ifndef ARM_MMU_EXTENDED 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 /* 489 * pmap copy/zero page, and mem(5) hook point 490 */ 491 static pt_entry_t *csrc_pte, *cdst_pte; 492 static vaddr_t csrcp, cdstp; 493 #ifdef MULTIPROCESSOR 494 static size_t cnptes; 495 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 497 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 499 #else 500 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + (o)) 503 #define cpu_cdstp(o) (cdstp + (o)) 504 #endif 505 vaddr_t memhook; /* used by mem.c & others */ 506 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 507 kmutex_t pmap_lock __cacheline_aligned; 508 extern void *msgbufaddr; 509 int pmap_kmpages; 510 /* 511 * Flag to indicate if pmap_init() has done its thing 512 */ 513 bool pmap_initialized; 514 515 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 516 /* 517 * Start of direct-mapped memory 518 */ 519 vaddr_t pmap_directbase = KERNEL_BASE; 520 #endif 521 522 /* 523 * Misc. locking data structures 524 */ 525 526 static inline void 527 pmap_acquire_pmap_lock(pmap_t pm) 528 { 529 if (pm == pmap_kernel()) { 530 #ifdef MULTIPROCESSOR 531 KERNEL_LOCK(1, NULL); 532 #endif 533 } else { 534 mutex_enter(pm->pm_lock); 535 } 536 } 537 538 static inline void 539 pmap_release_pmap_lock(pmap_t pm) 540 { 541 if (pm == pmap_kernel()) { 542 #ifdef MULTIPROCESSOR 543 KERNEL_UNLOCK_ONE(NULL); 544 #endif 545 } else { 546 mutex_exit(pm->pm_lock); 547 } 548 } 549 550 static inline void 551 pmap_acquire_page_lock(struct vm_page_md *md) 552 { 553 mutex_enter(&pmap_lock); 554 } 555 556 static inline void 557 pmap_release_page_lock(struct vm_page_md *md) 558 { 559 mutex_exit(&pmap_lock); 560 } 561 562 #ifdef DIAGNOSTIC 563 static inline int 564 pmap_page_locked_p(struct vm_page_md *md) 565 { 566 return mutex_owned(&pmap_lock); 567 } 568 #endif 569 570 571 /* 572 * Metadata for L1 translation tables. 573 */ 574 #ifndef ARM_MMU_EXTENDED 575 struct l1_ttable { 576 /* Entry on the L1 Table list */ 577 SLIST_ENTRY(l1_ttable) l1_link; 578 579 /* Entry on the L1 Least Recently Used list */ 580 TAILQ_ENTRY(l1_ttable) l1_lru; 581 582 /* Track how many domains are allocated from this L1 */ 583 volatile u_int l1_domain_use_count; 584 585 /* 586 * A free-list of domain numbers for this L1. 587 * We avoid using ffs() and a bitmap to track domains since ffs() 588 * is slow on ARM. 589 */ 590 uint8_t l1_domain_first; 591 uint8_t l1_domain_free[PMAP_DOMAINS]; 592 593 /* Physical address of this L1 page table */ 594 paddr_t l1_physaddr; 595 596 /* KVA of this L1 page table */ 597 pd_entry_t *l1_kva; 598 }; 599 600 /* 601 * L1 Page Tables are tracked using a Least Recently Used list. 602 * - New L1s are allocated from the HEAD. 603 * - Freed L1s are added to the TAIl. 604 * - Recently accessed L1s (where an 'access' is some change to one of 605 * the userland pmaps which owns this L1) are moved to the TAIL. 606 */ 607 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 608 static kmutex_t l1_lru_lock __cacheline_aligned; 609 610 /* 611 * A list of all L1 tables 612 */ 613 static SLIST_HEAD(, l1_ttable) l1_list; 614 #endif /* ARM_MMU_EXTENDED */ 615 616 /* 617 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 618 * 619 * This is normally 16MB worth L2 page descriptors for any given pmap. 620 * Reference counts are maintained for L2 descriptors so they can be 621 * freed when empty. 622 */ 623 struct l2_bucket { 624 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 625 paddr_t l2b_pa; /* Physical address of same */ 626 u_short l2b_l1slot; /* This L2 table's L1 index */ 627 u_short l2b_occupancy; /* How many active descriptors */ 628 }; 629 630 struct l2_dtable { 631 /* The number of L2 page descriptors allocated to this l2_dtable */ 632 u_int l2_occupancy; 633 634 /* List of L2 page descriptors */ 635 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 636 }; 637 638 /* 639 * Given an L1 table index, calculate the corresponding l2_dtable index 640 * and bucket index within the l2_dtable. 641 */ 642 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 643 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 644 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 645 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 646 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 647 648 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 649 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 650 651 /* 652 * Given a virtual address, this macro returns the 653 * virtual address required to drop into the next L2 bucket. 654 */ 655 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 656 657 /* 658 * L2 allocation. 659 */ 660 #define pmap_alloc_l2_dtable() \ 661 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 662 #define pmap_free_l2_dtable(l2) \ 663 pool_cache_put(&pmap_l2dtable_cache, (l2)) 664 #define pmap_alloc_l2_ptp(pap) \ 665 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 666 PR_NOWAIT, (pap))) 667 668 /* 669 * We try to map the page tables write-through, if possible. However, not 670 * all CPUs have a write-through cache mode, so on those we have to sync 671 * the cache when we frob page tables. 672 * 673 * We try to evaluate this at compile time, if possible. However, it's 674 * not always possible to do that, hence this run-time var. 675 */ 676 int pmap_needs_pte_sync; 677 678 /* 679 * Real definition of pv_entry. 680 */ 681 struct pv_entry { 682 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 683 pmap_t pv_pmap; /* pmap where mapping lies */ 684 vaddr_t pv_va; /* virtual address for mapping */ 685 u_int pv_flags; /* flags */ 686 }; 687 688 /* 689 * Macro to determine if a mapping might be resident in the 690 * instruction cache and/or TLB 691 */ 692 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 693 /* 694 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 695 * there are no explicit accesses, so there may be always be TLB entries to 696 * flush. If we used ASIDs then this would not be a problem. 697 */ 698 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 699 #else 700 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 701 #endif 702 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 703 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 704 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 705 706 /* 707 * Macro to determine if a mapping might be resident in the 708 * data cache and/or TLB 709 */ 710 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 711 /* 712 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 713 * there are no explicit accesses, so there may be always be TLB entries to 714 * flush. If we used ASIDs then this would not be a problem. 715 */ 716 #define PV_BEEN_REFD(f) (1) 717 #else 718 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 719 #endif 720 721 /* 722 * Local prototypes 723 */ 724 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 725 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 726 pt_entry_t **); 727 static bool pmap_is_current(pmap_t) __unused; 728 static bool pmap_is_cached(pmap_t); 729 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 730 pmap_t, vaddr_t, u_int); 731 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 732 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 733 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 734 u_int, u_int); 735 736 static void pmap_pinit(pmap_t); 737 static int pmap_pmap_ctor(void *, void *, int); 738 739 static void pmap_alloc_l1(pmap_t); 740 static void pmap_free_l1(pmap_t); 741 #ifndef ARM_MMU_EXTENDED 742 static void pmap_use_l1(pmap_t); 743 #endif 744 745 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 746 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 747 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 748 static int pmap_l2ptp_ctor(void *, void *, int); 749 static int pmap_l2dtable_ctor(void *, void *, int); 750 751 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 752 #ifdef PMAP_CACHE_VIVT 753 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 754 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 755 #endif 756 757 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 758 #ifdef PMAP_CACHE_VIVT 759 static bool pmap_clean_page(struct vm_page_md *, bool); 760 #endif 761 #ifdef PMAP_CACHE_VIPT 762 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 763 enum pmap_flush_op { 764 PMAP_FLUSH_PRIMARY, 765 PMAP_FLUSH_SECONDARY, 766 PMAP_CLEAN_PRIMARY 767 }; 768 #ifndef ARM_MMU_EXTENDED 769 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 770 #endif 771 #endif 772 static void pmap_page_remove(struct vm_page_md *, paddr_t); 773 774 #ifndef ARM_MMU_EXTENDED 775 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 776 #endif 777 static vaddr_t kernel_pt_lookup(paddr_t); 778 779 780 /* 781 * Misc variables 782 */ 783 vaddr_t virtual_avail; 784 vaddr_t virtual_end; 785 vaddr_t pmap_curmaxkvaddr; 786 787 paddr_t avail_start; 788 paddr_t avail_end; 789 790 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 791 pv_addr_t kernelpages; 792 pv_addr_t kernel_l1pt; 793 pv_addr_t systempage; 794 795 /* Function to set the debug level of the pmap code */ 796 797 #ifdef PMAP_DEBUG 798 void 799 pmap_debug(int level) 800 { 801 pmap_debug_level = level; 802 printf("pmap_debug: level=%d\n", pmap_debug_level); 803 } 804 #endif /* PMAP_DEBUG */ 805 806 #ifdef PMAP_CACHE_VIPT 807 #define PMAP_VALIDATE_MD_PAGE(md) \ 808 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 809 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 810 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 811 #endif /* PMAP_CACHE_VIPT */ 812 /* 813 * A bunch of routines to conditionally flush the caches/TLB depending 814 * on whether the specified pmap actually needs to be flushed at any 815 * given time. 816 */ 817 static inline void 818 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 819 { 820 #ifdef ARM_MMU_EXTENDED 821 pmap_tlb_invalidate_addr(pm, va); 822 #else 823 if (pm->pm_cstate.cs_tlb_id != 0) { 824 if (PV_BEEN_EXECD(flags)) { 825 cpu_tlb_flushID_SE(va); 826 } else if (PV_BEEN_REFD(flags)) { 827 cpu_tlb_flushD_SE(va); 828 } 829 } 830 #endif /* ARM_MMU_EXTENDED */ 831 } 832 833 static inline void 834 pmap_tlb_flushID(pmap_t pm) 835 { 836 #ifdef ARM_MMU_EXTENDED 837 pmap_tlb_asid_release_all(pm); 838 #else 839 if (pm->pm_cstate.cs_tlb_id) { 840 cpu_tlb_flushID(); 841 #if ARM_MMU_V7 == 0 842 /* 843 * Speculative loads by Cortex cores can cause TLB entries to 844 * be filled even if there are no explicit accesses, so there 845 * may be always be TLB entries to flush. If we used ASIDs 846 * then it would not be a problem. 847 * This is not true for other CPUs. 848 */ 849 pm->pm_cstate.cs_tlb = 0; 850 #endif /* ARM_MMU_V7 */ 851 } 852 #endif /* ARM_MMU_EXTENDED */ 853 } 854 855 static inline void 856 pmap_tlb_flushD(pmap_t pm) 857 { 858 #ifdef ARM_MMU_EXTENDED 859 pmap_tlb_asid_release_all(pm); 860 #else 861 if (pm->pm_cstate.cs_tlb_d) { 862 cpu_tlb_flushD(); 863 #if ARM_MMU_V7 == 0 864 /* 865 * Speculative loads by Cortex cores can cause TLB entries to 866 * be filled even if there are no explicit accesses, so there 867 * may be always be TLB entries to flush. If we used ASIDs 868 * then it would not be a problem. 869 * This is not true for other CPUs. 870 */ 871 pm->pm_cstate.cs_tlb_d = 0; 872 #endif /* ARM_MMU_V7 */ 873 } 874 #endif /* ARM_MMU_EXTENDED */ 875 } 876 877 #ifdef PMAP_CACHE_VIVT 878 static inline void 879 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 880 { 881 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 882 cpu_idcache_wbinv_range(va, PAGE_SIZE); 883 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 884 if (do_inv) { 885 if (flags & PVF_WRITE) 886 cpu_dcache_wbinv_range(va, PAGE_SIZE); 887 else 888 cpu_dcache_inv_range(va, PAGE_SIZE); 889 } else if (flags & PVF_WRITE) { 890 cpu_dcache_wb_range(va, PAGE_SIZE); 891 } 892 } 893 } 894 895 static inline void 896 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 897 { 898 if (PV_BEEN_EXECD(flags)) { 899 if (pm->pm_cstate.cs_cache_id) { 900 cpu_idcache_wbinv_all(); 901 pm->pm_cstate.cs_cache = 0; 902 } 903 } else if (pm->pm_cstate.cs_cache_d) { 904 cpu_dcache_wbinv_all(); 905 pm->pm_cstate.cs_cache_d = 0; 906 } 907 } 908 #endif /* PMAP_CACHE_VIVT */ 909 910 static inline uint8_t 911 pmap_domain(pmap_t pm) 912 { 913 #ifdef ARM_MMU_EXTENDED 914 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 915 #else 916 return pm->pm_domain; 917 #endif 918 } 919 920 static inline pd_entry_t * 921 pmap_l1_kva(pmap_t pm) 922 { 923 #ifdef ARM_MMU_EXTENDED 924 return pm->pm_l1; 925 #else 926 return pm->pm_l1->l1_kva; 927 #endif 928 } 929 930 static inline bool 931 pmap_is_current(pmap_t pm) 932 { 933 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 934 return true; 935 936 return false; 937 } 938 939 static inline bool 940 pmap_is_cached(pmap_t pm) 941 { 942 #ifdef ARM_MMU_EXTENDED 943 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 944 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 945 return true; 946 #else 947 struct cpu_info * const ci = curcpu(); 948 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 949 || ci->ci_pmap_lastuser == pm) 950 return true; 951 #endif /* ARM_MMU_EXTENDED */ 952 953 return false; 954 } 955 956 /* 957 * PTE_SYNC_CURRENT: 958 * 959 * Make sure the pte is written out to RAM. 960 * We need to do this for one of two cases: 961 * - We're dealing with the kernel pmap 962 * - There is no pmap active in the cache/tlb. 963 * - The specified pmap is 'active' in the cache/tlb. 964 */ 965 #ifdef PMAP_INCLUDE_PTE_SYNC 966 #define PTE_SYNC_CURRENT(pm, ptep) \ 967 do { \ 968 if (PMAP_NEEDS_PTE_SYNC && \ 969 pmap_is_cached(pm)) \ 970 PTE_SYNC(ptep); \ 971 } while (/*CONSTCOND*/0) 972 #else 973 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 974 #endif 975 976 /* 977 * main pv_entry manipulation functions: 978 * pmap_enter_pv: enter a mapping onto a vm_page list 979 * pmap_remove_pv: remove a mapping from a vm_page list 980 * 981 * NOTE: pmap_enter_pv expects to lock the pvh itself 982 * pmap_remove_pv expects the caller to lock the pvh before calling 983 */ 984 985 /* 986 * pmap_enter_pv: enter a mapping onto a vm_page lst 987 * 988 * => caller should hold the proper lock on pmap_main_lock 989 * => caller should have pmap locked 990 * => we will gain the lock on the vm_page and allocate the new pv_entry 991 * => caller should adjust ptp's wire_count before calling 992 * => caller should not adjust pmap's wire_count 993 */ 994 static void 995 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 996 vaddr_t va, u_int flags) 997 { 998 struct pv_entry **pvp; 999 1000 NPDEBUG(PDB_PVDUMP, 1001 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 1002 1003 pv->pv_pmap = pm; 1004 pv->pv_va = va; 1005 pv->pv_flags = flags; 1006 1007 pvp = &SLIST_FIRST(&md->pvh_list); 1008 #ifdef PMAP_CACHE_VIPT 1009 /* 1010 * Insert unmanaged entries, writeable first, at the head of 1011 * the pv list. 1012 */ 1013 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1014 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1015 pvp = &SLIST_NEXT(*pvp, pv_link); 1016 } 1017 if (!PV_IS_WRITE_P(flags)) { 1018 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1019 pvp = &SLIST_NEXT(*pvp, pv_link); 1020 } 1021 #endif 1022 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1023 *pvp = pv; /* ... locked list */ 1024 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1025 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1026 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1027 md->pvh_attrs |= PVF_KMOD; 1028 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1029 md->pvh_attrs |= PVF_DIRTY; 1030 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1031 #endif 1032 if (pm == pmap_kernel()) { 1033 PMAPCOUNT(kernel_mappings); 1034 if (flags & PVF_WRITE) 1035 md->krw_mappings++; 1036 else 1037 md->kro_mappings++; 1038 } else { 1039 if (flags & PVF_WRITE) 1040 md->urw_mappings++; 1041 else 1042 md->uro_mappings++; 1043 } 1044 1045 #ifdef PMAP_CACHE_VIPT 1046 #ifndef ARM_MMU_EXTENDED 1047 /* 1048 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1049 * do it here as well to keep the mappings & KVF_WRITE consistent. 1050 */ 1051 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1052 md->pvh_attrs |= PVF_WRITE; 1053 } 1054 #endif 1055 /* 1056 * If this is an exec mapping and its the first exec mapping 1057 * for this page, make sure to sync the I-cache. 1058 */ 1059 if (PV_IS_EXEC_P(flags)) { 1060 #ifndef ARM_MMU_EXTENDED 1061 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1062 pmap_syncicache_page(md, pa); 1063 PMAPCOUNT(exec_synced_map); 1064 } 1065 #endif 1066 PMAPCOUNT(exec_mappings); 1067 } 1068 #endif 1069 1070 PMAPCOUNT(mappings); 1071 1072 if (pv->pv_flags & PVF_WIRED) 1073 ++pm->pm_stats.wired_count; 1074 } 1075 1076 /* 1077 * 1078 * pmap_find_pv: Find a pv entry 1079 * 1080 * => caller should hold lock on vm_page 1081 */ 1082 static inline struct pv_entry * 1083 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1084 { 1085 struct pv_entry *pv; 1086 1087 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1088 if (pm == pv->pv_pmap && va == pv->pv_va) 1089 break; 1090 } 1091 1092 return (pv); 1093 } 1094 1095 /* 1096 * pmap_remove_pv: try to remove a mapping from a pv_list 1097 * 1098 * => caller should hold proper lock on pmap_main_lock 1099 * => pmap should be locked 1100 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1101 * => caller should adjust ptp's wire_count and free PTP if needed 1102 * => caller should NOT adjust pmap's wire_count 1103 * => we return the removed pv 1104 */ 1105 static struct pv_entry * 1106 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1107 { 1108 struct pv_entry *pv, **prevptr; 1109 1110 NPDEBUG(PDB_PVDUMP, 1111 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1112 1113 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1114 pv = *prevptr; 1115 1116 while (pv) { 1117 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1118 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1119 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1120 if (pv->pv_flags & PVF_WIRED) { 1121 --pm->pm_stats.wired_count; 1122 } 1123 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1124 if (pm == pmap_kernel()) { 1125 PMAPCOUNT(kernel_unmappings); 1126 if (pv->pv_flags & PVF_WRITE) 1127 md->krw_mappings--; 1128 else 1129 md->kro_mappings--; 1130 } else { 1131 if (pv->pv_flags & PVF_WRITE) 1132 md->urw_mappings--; 1133 else 1134 md->uro_mappings--; 1135 } 1136 1137 PMAPCOUNT(unmappings); 1138 #ifdef PMAP_CACHE_VIPT 1139 if (!(pv->pv_flags & PVF_WRITE)) 1140 break; 1141 /* 1142 * If this page has had an exec mapping, then if 1143 * this was the last mapping, discard the contents, 1144 * otherwise sync the i-cache for this page. 1145 */ 1146 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1147 #ifdef ARM_MMU_EXTENDED 1148 md->pvh_attrs &= ~PVF_EXEC; 1149 PMAPCOUNT(exec_discarded_unmap); 1150 #else 1151 if (SLIST_EMPTY(&md->pvh_list)) { 1152 md->pvh_attrs &= ~PVF_EXEC; 1153 PMAPCOUNT(exec_discarded_unmap); 1154 } else { 1155 pmap_syncicache_page(md, pa); 1156 PMAPCOUNT(exec_synced_unmap); 1157 } 1158 #endif /* ARM_MMU_EXTENDED */ 1159 } 1160 #endif /* PMAP_CACHE_VIPT */ 1161 break; 1162 } 1163 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1164 pv = *prevptr; /* advance */ 1165 } 1166 1167 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1168 /* 1169 * If we no longer have a WRITEABLE KENTRY at the head of list, 1170 * clear the KMOD attribute from the page. 1171 */ 1172 if (SLIST_FIRST(&md->pvh_list) == NULL 1173 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1174 md->pvh_attrs &= ~PVF_KMOD; 1175 1176 /* 1177 * If this was a writeable page and there are no more writeable 1178 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1179 * the contents to memory. 1180 */ 1181 if (arm_cache_prefer_mask != 0) { 1182 if (md->krw_mappings + md->urw_mappings == 0) 1183 md->pvh_attrs &= ~PVF_WRITE; 1184 PMAP_VALIDATE_MD_PAGE(md); 1185 } 1186 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1187 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1188 1189 return(pv); /* return removed pv */ 1190 } 1191 1192 /* 1193 * 1194 * pmap_modify_pv: Update pv flags 1195 * 1196 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1197 * => caller should NOT adjust pmap's wire_count 1198 * => caller must call pmap_vac_me_harder() if writable status of a page 1199 * may have changed. 1200 * => we return the old flags 1201 * 1202 * Modify a physical-virtual mapping in the pv table 1203 */ 1204 static u_int 1205 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1206 u_int clr_mask, u_int set_mask) 1207 { 1208 struct pv_entry *npv; 1209 u_int flags, oflags; 1210 1211 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1212 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1213 1214 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1215 return (0); 1216 1217 NPDEBUG(PDB_PVDUMP, 1218 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1219 1220 /* 1221 * There is at least one VA mapping this page. 1222 */ 1223 1224 if (clr_mask & (PVF_REF | PVF_MOD)) { 1225 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1226 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1227 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1228 md->pvh_attrs |= PVF_DIRTY; 1229 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1230 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1231 } 1232 1233 oflags = npv->pv_flags; 1234 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1235 1236 if ((flags ^ oflags) & PVF_WIRED) { 1237 if (flags & PVF_WIRED) 1238 ++pm->pm_stats.wired_count; 1239 else 1240 --pm->pm_stats.wired_count; 1241 } 1242 1243 if ((flags ^ oflags) & PVF_WRITE) { 1244 if (pm == pmap_kernel()) { 1245 if (flags & PVF_WRITE) { 1246 md->krw_mappings++; 1247 md->kro_mappings--; 1248 } else { 1249 md->kro_mappings++; 1250 md->krw_mappings--; 1251 } 1252 } else { 1253 if (flags & PVF_WRITE) { 1254 md->urw_mappings++; 1255 md->uro_mappings--; 1256 } else { 1257 md->uro_mappings++; 1258 md->urw_mappings--; 1259 } 1260 } 1261 } 1262 #ifdef PMAP_CACHE_VIPT 1263 if (arm_cache_prefer_mask != 0) { 1264 if (md->urw_mappings + md->krw_mappings == 0) { 1265 md->pvh_attrs &= ~PVF_WRITE; 1266 } else { 1267 md->pvh_attrs |= PVF_WRITE; 1268 } 1269 } 1270 #ifndef ARM_MMU_EXTENDED 1271 /* 1272 * We have two cases here: the first is from enter_pv (new exec 1273 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1274 * Since in latter, pmap_enter_pv won't do anything, we just have 1275 * to do what pmap_remove_pv would do. 1276 */ 1277 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1278 || (PV_IS_EXEC_P(md->pvh_attrs) 1279 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1280 pmap_syncicache_page(md, pa); 1281 PMAPCOUNT(exec_synced_remap); 1282 } 1283 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1284 #endif /* !ARM_MMU_EXTENDED */ 1285 #endif /* PMAP_CACHE_VIPT */ 1286 1287 PMAPCOUNT(remappings); 1288 1289 return (oflags); 1290 } 1291 1292 /* 1293 * Allocate an L1 translation table for the specified pmap. 1294 * This is called at pmap creation time. 1295 */ 1296 static void 1297 pmap_alloc_l1(pmap_t pm) 1298 { 1299 #ifdef ARM_MMU_EXTENDED 1300 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1301 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1302 struct vm_page *pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1303 #else 1304 struct vm_page *pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1305 #endif 1306 bool ok __diagused; 1307 KASSERT(pg != NULL); 1308 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1309 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1310 KASSERT(ok); 1311 KASSERT(va >= KERNEL_BASE); 1312 1313 #else 1314 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1315 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1316 UVM_KMF_WIRED|UVM_KMF_ZERO); 1317 KASSERT(va); 1318 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1319 #endif 1320 pm->pm_l1 = (pd_entry_t *)va; 1321 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1322 #else 1323 struct l1_ttable *l1; 1324 uint8_t domain; 1325 1326 /* 1327 * Remove the L1 at the head of the LRU list 1328 */ 1329 mutex_spin_enter(&l1_lru_lock); 1330 l1 = TAILQ_FIRST(&l1_lru_list); 1331 KDASSERT(l1 != NULL); 1332 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1333 1334 /* 1335 * Pick the first available domain number, and update 1336 * the link to the next number. 1337 */ 1338 domain = l1->l1_domain_first; 1339 l1->l1_domain_first = l1->l1_domain_free[domain]; 1340 1341 /* 1342 * If there are still free domain numbers in this L1, 1343 * put it back on the TAIL of the LRU list. 1344 */ 1345 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1346 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1347 1348 mutex_spin_exit(&l1_lru_lock); 1349 1350 /* 1351 * Fix up the relevant bits in the pmap structure 1352 */ 1353 pm->pm_l1 = l1; 1354 pm->pm_domain = domain + 1; 1355 #endif 1356 } 1357 1358 /* 1359 * Free an L1 translation table. 1360 * This is called at pmap destruction time. 1361 */ 1362 static void 1363 pmap_free_l1(pmap_t pm) 1364 { 1365 #ifdef ARM_MMU_EXTENDED 1366 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1367 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1368 uvm_pagefree(pg); 1369 #else 1370 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1371 #endif 1372 pm->pm_l1 = NULL; 1373 pm->pm_l1_pa = 0; 1374 #else 1375 struct l1_ttable *l1 = pm->pm_l1; 1376 1377 mutex_spin_enter(&l1_lru_lock); 1378 1379 /* 1380 * If this L1 is currently on the LRU list, remove it. 1381 */ 1382 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1383 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1384 1385 /* 1386 * Free up the domain number which was allocated to the pmap 1387 */ 1388 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1389 l1->l1_domain_first = pmap_domain(pm) - 1; 1390 l1->l1_domain_use_count--; 1391 1392 /* 1393 * The L1 now must have at least 1 free domain, so add 1394 * it back to the LRU list. If the use count is zero, 1395 * put it at the head of the list, otherwise it goes 1396 * to the tail. 1397 */ 1398 if (l1->l1_domain_use_count == 0) 1399 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1400 else 1401 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1402 1403 mutex_spin_exit(&l1_lru_lock); 1404 #endif /* ARM_MMU_EXTENDED */ 1405 } 1406 1407 #ifndef ARM_MMU_EXTENDED 1408 static inline void 1409 pmap_use_l1(pmap_t pm) 1410 { 1411 struct l1_ttable *l1; 1412 1413 /* 1414 * Do nothing if we're in interrupt context. 1415 * Access to an L1 by the kernel pmap must not affect 1416 * the LRU list. 1417 */ 1418 if (cpu_intr_p() || pm == pmap_kernel()) 1419 return; 1420 1421 l1 = pm->pm_l1; 1422 1423 /* 1424 * If the L1 is not currently on the LRU list, just return 1425 */ 1426 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1427 return; 1428 1429 mutex_spin_enter(&l1_lru_lock); 1430 1431 /* 1432 * Check the use count again, now that we've acquired the lock 1433 */ 1434 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1435 mutex_spin_exit(&l1_lru_lock); 1436 return; 1437 } 1438 1439 /* 1440 * Move the L1 to the back of the LRU list 1441 */ 1442 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1443 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1444 1445 mutex_spin_exit(&l1_lru_lock); 1446 } 1447 #endif /* !ARM_MMU_EXTENDED */ 1448 1449 /* 1450 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1451 * 1452 * Free an L2 descriptor table. 1453 */ 1454 static inline void 1455 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1456 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1457 #else 1458 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1459 #endif 1460 { 1461 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1462 /* 1463 * Note: With a write-back cache, we may need to sync this 1464 * L2 table before re-using it. 1465 * This is because it may have belonged to a non-current 1466 * pmap, in which case the cache syncs would have been 1467 * skipped for the pages that were being unmapped. If the 1468 * L2 table were then to be immediately re-allocated to 1469 * the *current* pmap, it may well contain stale mappings 1470 * which have not yet been cleared by a cache write-back 1471 * and so would still be visible to the mmu. 1472 */ 1473 if (need_sync) 1474 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1475 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1476 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1477 } 1478 1479 /* 1480 * Returns a pointer to the L2 bucket associated with the specified pmap 1481 * and VA, or NULL if no L2 bucket exists for the address. 1482 */ 1483 static inline struct l2_bucket * 1484 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1485 { 1486 const size_t l1slot = l1pte_index(va); 1487 struct l2_dtable *l2; 1488 struct l2_bucket *l2b; 1489 1490 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1491 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1492 return (NULL); 1493 1494 return (l2b); 1495 } 1496 1497 /* 1498 * Returns a pointer to the L2 bucket associated with the specified pmap 1499 * and VA. 1500 * 1501 * If no L2 bucket exists, perform the necessary allocations to put an L2 1502 * bucket/page table in place. 1503 * 1504 * Note that if a new L2 bucket/page was allocated, the caller *must* 1505 * increment the bucket occupancy counter appropriately *before* 1506 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1507 * the bucket/page in the meantime. 1508 */ 1509 static struct l2_bucket * 1510 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1511 { 1512 const size_t l1slot = l1pte_index(va); 1513 struct l2_dtable *l2; 1514 1515 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1516 /* 1517 * No mapping at this address, as there is 1518 * no entry in the L1 table. 1519 * Need to allocate a new l2_dtable. 1520 */ 1521 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1522 return (NULL); 1523 1524 /* 1525 * Link it into the parent pmap 1526 */ 1527 pm->pm_l2[L2_IDX(l1slot)] = l2; 1528 } 1529 1530 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1531 1532 /* 1533 * Fetch pointer to the L2 page table associated with the address. 1534 */ 1535 if (l2b->l2b_kva == NULL) { 1536 pt_entry_t *ptep; 1537 1538 /* 1539 * No L2 page table has been allocated. Chances are, this 1540 * is because we just allocated the l2_dtable, above. 1541 */ 1542 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1543 /* 1544 * Oops, no more L2 page tables available at this 1545 * time. We may need to deallocate the l2_dtable 1546 * if we allocated a new one above. 1547 */ 1548 if (l2->l2_occupancy == 0) { 1549 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1550 pmap_free_l2_dtable(l2); 1551 } 1552 return (NULL); 1553 } 1554 1555 l2->l2_occupancy++; 1556 l2b->l2b_kva = ptep; 1557 l2b->l2b_l1slot = l1slot; 1558 1559 #ifdef ARM_MMU_EXTENDED 1560 /* 1561 * We know there will be a mapping here, so simply 1562 * enter this PTP into the L1 now. 1563 */ 1564 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1565 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1566 | L1_C_DOM(pmap_domain(pm)); 1567 KASSERT(*pdep == 0); 1568 l1pte_setone(pdep, npde); 1569 PTE_SYNC(pdep); 1570 #endif 1571 } 1572 1573 return (l2b); 1574 } 1575 1576 /* 1577 * One or more mappings in the specified L2 descriptor table have just been 1578 * invalidated. 1579 * 1580 * Garbage collect the metadata and descriptor table itself if necessary. 1581 * 1582 * The pmap lock must be acquired when this is called (not necessary 1583 * for the kernel pmap). 1584 */ 1585 static void 1586 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1587 { 1588 KDASSERT(count <= l2b->l2b_occupancy); 1589 1590 /* 1591 * Update the bucket's reference count according to how many 1592 * PTEs the caller has just invalidated. 1593 */ 1594 l2b->l2b_occupancy -= count; 1595 1596 /* 1597 * Note: 1598 * 1599 * Level 2 page tables allocated to the kernel pmap are never freed 1600 * as that would require checking all Level 1 page tables and 1601 * removing any references to the Level 2 page table. See also the 1602 * comment elsewhere about never freeing bootstrap L2 descriptors. 1603 * 1604 * We make do with just invalidating the mapping in the L2 table. 1605 * 1606 * This isn't really a big deal in practice and, in fact, leads 1607 * to a performance win over time as we don't need to continually 1608 * alloc/free. 1609 */ 1610 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1611 return; 1612 1613 /* 1614 * There are no more valid mappings in this level 2 page table. 1615 * Go ahead and NULL-out the pointer in the bucket, then 1616 * free the page table. 1617 */ 1618 const size_t l1slot = l2b->l2b_l1slot; 1619 pt_entry_t * const ptep = l2b->l2b_kva; 1620 l2b->l2b_kva = NULL; 1621 1622 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1623 pd_entry_t pde __diagused = *pdep; 1624 1625 #ifdef ARM_MMU_EXTENDED 1626 /* 1627 * Invalidate the L1 slot. 1628 */ 1629 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1630 #else 1631 /* 1632 * If the L1 slot matches the pmap's domain number, then invalidate it. 1633 */ 1634 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1635 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1636 #endif 1637 l1pte_setone(pdep, 0); 1638 PDE_SYNC(pdep); 1639 #ifndef ARM_MMU_EXTENDED 1640 } 1641 #endif 1642 1643 /* 1644 * Release the L2 descriptor table back to the pool cache. 1645 */ 1646 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1647 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1648 #else 1649 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1650 #endif 1651 1652 /* 1653 * Update the reference count in the associated l2_dtable 1654 */ 1655 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1656 if (--l2->l2_occupancy > 0) 1657 return; 1658 1659 /* 1660 * There are no more valid mappings in any of the Level 1 1661 * slots managed by this l2_dtable. Go ahead and NULL-out 1662 * the pointer in the parent pmap and free the l2_dtable. 1663 */ 1664 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1665 pmap_free_l2_dtable(l2); 1666 } 1667 1668 /* 1669 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1670 * structures. 1671 */ 1672 static int 1673 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1674 { 1675 #ifndef PMAP_INCLUDE_PTE_SYNC 1676 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1677 1678 /* 1679 * The mappings for these page tables were initially made using 1680 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1681 * mode will not be right for page table mappings. To avoid 1682 * polluting the pmap_kenter_pa() code with a special case for 1683 * page tables, we simply fix up the cache-mode here if it's not 1684 * correct. 1685 */ 1686 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1687 const struct l2_bucket * const l2b = 1688 pmap_get_l2_bucket(pmap_kernel(), va); 1689 KASSERTMSG(l2b != NULL, "%#lx", va); 1690 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1691 const pt_entry_t opte = *ptep; 1692 1693 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1694 /* 1695 * Page tables must have the cache-mode set correctly. 1696 */ 1697 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1698 | pte_l2_s_cache_mode_pt; 1699 l2pte_set(ptep, npte, opte); 1700 PTE_SYNC(ptep); 1701 cpu_tlb_flushD_SE(va); 1702 cpu_cpwait(); 1703 } 1704 } 1705 #endif 1706 1707 memset(v, 0, L2_TABLE_SIZE_REAL); 1708 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1709 return (0); 1710 } 1711 1712 static int 1713 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1714 { 1715 1716 memset(v, 0, sizeof(struct l2_dtable)); 1717 return (0); 1718 } 1719 1720 static int 1721 pmap_pmap_ctor(void *arg, void *v, int flags) 1722 { 1723 1724 memset(v, 0, sizeof(struct pmap)); 1725 return (0); 1726 } 1727 1728 static void 1729 pmap_pinit(pmap_t pm) 1730 { 1731 #ifndef ARM_HAS_VBAR 1732 struct l2_bucket *l2b; 1733 1734 if (vector_page < KERNEL_BASE) { 1735 /* 1736 * Map the vector page. 1737 */ 1738 pmap_enter(pm, vector_page, systempage.pv_pa, 1739 VM_PROT_READ | VM_PROT_EXECUTE, 1740 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1741 pmap_update(pm); 1742 1743 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1744 l2b = pmap_get_l2_bucket(pm, vector_page); 1745 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1746 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1747 L1_C_DOM(pmap_domain(pm)); 1748 } else 1749 pm->pm_pl1vec = NULL; 1750 #endif 1751 } 1752 1753 #ifdef PMAP_CACHE_VIVT 1754 /* 1755 * Since we have a virtually indexed cache, we may need to inhibit caching if 1756 * there is more than one mapping and at least one of them is writable. 1757 * Since we purge the cache on every context switch, we only need to check for 1758 * other mappings within the same pmap, or kernel_pmap. 1759 * This function is also called when a page is unmapped, to possibly reenable 1760 * caching on any remaining mappings. 1761 * 1762 * The code implements the following logic, where: 1763 * 1764 * KW = # of kernel read/write pages 1765 * KR = # of kernel read only pages 1766 * UW = # of user read/write pages 1767 * UR = # of user read only pages 1768 * 1769 * KC = kernel mapping is cacheable 1770 * UC = user mapping is cacheable 1771 * 1772 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1773 * +--------------------------------------------- 1774 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1775 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1776 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1777 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1778 */ 1779 1780 static const int pmap_vac_flags[4][4] = { 1781 {-1, 0, 0, PVF_KNC}, 1782 {0, 0, PVF_NC, PVF_NC}, 1783 {0, PVF_NC, PVF_NC, PVF_NC}, 1784 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1785 }; 1786 1787 static inline int 1788 pmap_get_vac_flags(const struct vm_page_md *md) 1789 { 1790 int kidx, uidx; 1791 1792 kidx = 0; 1793 if (md->kro_mappings || md->krw_mappings > 1) 1794 kidx |= 1; 1795 if (md->krw_mappings) 1796 kidx |= 2; 1797 1798 uidx = 0; 1799 if (md->uro_mappings || md->urw_mappings > 1) 1800 uidx |= 1; 1801 if (md->urw_mappings) 1802 uidx |= 2; 1803 1804 return (pmap_vac_flags[uidx][kidx]); 1805 } 1806 1807 static inline void 1808 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1809 { 1810 int nattr; 1811 1812 nattr = pmap_get_vac_flags(md); 1813 1814 if (nattr < 0) { 1815 md->pvh_attrs &= ~PVF_NC; 1816 return; 1817 } 1818 1819 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1820 return; 1821 1822 if (pm == pmap_kernel()) 1823 pmap_vac_me_kpmap(md, pa, pm, va); 1824 else 1825 pmap_vac_me_user(md, pa, pm, va); 1826 1827 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1828 } 1829 1830 static void 1831 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1832 { 1833 u_int u_cacheable, u_entries; 1834 struct pv_entry *pv; 1835 pmap_t last_pmap = pm; 1836 1837 /* 1838 * Pass one, see if there are both kernel and user pmaps for 1839 * this page. Calculate whether there are user-writable or 1840 * kernel-writable pages. 1841 */ 1842 u_cacheable = 0; 1843 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1844 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1845 u_cacheable++; 1846 } 1847 1848 u_entries = md->urw_mappings + md->uro_mappings; 1849 1850 /* 1851 * We know we have just been updating a kernel entry, so if 1852 * all user pages are already cacheable, then there is nothing 1853 * further to do. 1854 */ 1855 if (md->k_mappings == 0 && u_cacheable == u_entries) 1856 return; 1857 1858 if (u_entries) { 1859 /* 1860 * Scan over the list again, for each entry, if it 1861 * might not be set correctly, call pmap_vac_me_user 1862 * to recalculate the settings. 1863 */ 1864 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1865 /* 1866 * We know kernel mappings will get set 1867 * correctly in other calls. We also know 1868 * that if the pmap is the same as last_pmap 1869 * then we've just handled this entry. 1870 */ 1871 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1872 continue; 1873 1874 /* 1875 * If there are kernel entries and this page 1876 * is writable but non-cacheable, then we can 1877 * skip this entry also. 1878 */ 1879 if (md->k_mappings && 1880 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1881 (PVF_NC | PVF_WRITE)) 1882 continue; 1883 1884 /* 1885 * Similarly if there are no kernel-writable 1886 * entries and the page is already 1887 * read-only/cacheable. 1888 */ 1889 if (md->krw_mappings == 0 && 1890 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1891 continue; 1892 1893 /* 1894 * For some of the remaining cases, we know 1895 * that we must recalculate, but for others we 1896 * can't tell if they are correct or not, so 1897 * we recalculate anyway. 1898 */ 1899 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1900 } 1901 1902 if (md->k_mappings == 0) 1903 return; 1904 } 1905 1906 pmap_vac_me_user(md, pa, pm, va); 1907 } 1908 1909 static void 1910 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1911 { 1912 pmap_t kpmap = pmap_kernel(); 1913 struct pv_entry *pv, *npv = NULL; 1914 u_int entries = 0; 1915 u_int writable = 0; 1916 u_int cacheable_entries = 0; 1917 u_int kern_cacheable = 0; 1918 u_int other_writable = 0; 1919 1920 /* 1921 * Count mappings and writable mappings in this pmap. 1922 * Include kernel mappings as part of our own. 1923 * Keep a pointer to the first one. 1924 */ 1925 npv = NULL; 1926 KASSERT(pmap_page_locked_p(md)); 1927 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1928 /* Count mappings in the same pmap */ 1929 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1930 if (entries++ == 0) 1931 npv = pv; 1932 1933 /* Cacheable mappings */ 1934 if ((pv->pv_flags & PVF_NC) == 0) { 1935 cacheable_entries++; 1936 if (kpmap == pv->pv_pmap) 1937 kern_cacheable++; 1938 } 1939 1940 /* Writable mappings */ 1941 if (pv->pv_flags & PVF_WRITE) 1942 ++writable; 1943 } else 1944 if (pv->pv_flags & PVF_WRITE) 1945 other_writable = 1; 1946 } 1947 1948 /* 1949 * Enable or disable caching as necessary. 1950 * Note: the first entry might be part of the kernel pmap, 1951 * so we can't assume this is indicative of the state of the 1952 * other (maybe non-kpmap) entries. 1953 */ 1954 if ((entries > 1 && writable) || 1955 (entries > 0 && pm == kpmap && other_writable)) { 1956 if (cacheable_entries == 0) { 1957 return; 1958 } 1959 1960 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1961 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1962 (pv->pv_flags & PVF_NC)) 1963 continue; 1964 1965 pv->pv_flags |= PVF_NC; 1966 1967 struct l2_bucket * const l2b 1968 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1969 KASSERTMSG(l2b != NULL, "%#lx", va); 1970 pt_entry_t * const ptep 1971 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1972 const pt_entry_t opte = *ptep; 1973 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1974 1975 if ((va != pv->pv_va || pm != pv->pv_pmap) 1976 && l2pte_valid_p(npte)) { 1977 #ifdef PMAP_CACHE_VIVT 1978 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1979 true, pv->pv_flags); 1980 #endif 1981 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1982 pv->pv_flags); 1983 } 1984 1985 l2pte_set(ptep, npte, opte); 1986 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1987 } 1988 cpu_cpwait(); 1989 } else 1990 if (entries > cacheable_entries) { 1991 /* 1992 * Turn cacheing back on for some pages. If it is a kernel 1993 * page, only do so if there are no other writable pages. 1994 */ 1995 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1996 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1997 (kpmap != pv->pv_pmap || other_writable))) 1998 continue; 1999 2000 pv->pv_flags &= ~PVF_NC; 2001 2002 struct l2_bucket * const l2b 2003 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2004 KASSERTMSG(l2b != NULL, "%#lx", va); 2005 pt_entry_t * const ptep 2006 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2007 const pt_entry_t opte = *ptep; 2008 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2009 | pte_l2_s_cache_mode; 2010 2011 if (l2pte_valid_p(opte)) { 2012 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2013 pv->pv_flags); 2014 } 2015 2016 l2pte_set(ptep, npte, opte); 2017 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2018 } 2019 } 2020 } 2021 #endif 2022 2023 #ifdef PMAP_CACHE_VIPT 2024 static void 2025 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2026 { 2027 #ifndef ARM_MMU_EXTENDED 2028 struct pv_entry *pv; 2029 vaddr_t tst_mask; 2030 bool bad_alias; 2031 const u_int 2032 rw_mappings = md->urw_mappings + md->krw_mappings, 2033 ro_mappings = md->uro_mappings + md->kro_mappings; 2034 2035 /* do we need to do anything? */ 2036 if (arm_cache_prefer_mask == 0) 2037 return; 2038 2039 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2040 md, pm, va)); 2041 2042 KASSERT(!va || pm); 2043 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2044 2045 /* Already a conflict? */ 2046 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2047 /* just an add, things are already non-cached */ 2048 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2049 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2050 bad_alias = false; 2051 if (va) { 2052 PMAPCOUNT(vac_color_none); 2053 bad_alias = true; 2054 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2055 goto fixup; 2056 } 2057 pv = SLIST_FIRST(&md->pvh_list); 2058 /* the list can't be empty because it would be cachable */ 2059 if (md->pvh_attrs & PVF_KMPAGE) { 2060 tst_mask = md->pvh_attrs; 2061 } else { 2062 KASSERT(pv); 2063 tst_mask = pv->pv_va; 2064 pv = SLIST_NEXT(pv, pv_link); 2065 } 2066 /* 2067 * Only check for a bad alias if we have writable mappings. 2068 */ 2069 tst_mask &= arm_cache_prefer_mask; 2070 if (rw_mappings > 0) { 2071 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2072 /* if there's a bad alias, stop checking. */ 2073 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2074 bad_alias = true; 2075 } 2076 md->pvh_attrs |= PVF_WRITE; 2077 if (!bad_alias) 2078 md->pvh_attrs |= PVF_DIRTY; 2079 } else { 2080 /* 2081 * We have only read-only mappings. Let's see if there 2082 * are multiple colors in use or if we mapped a KMPAGE. 2083 * If the latter, we have a bad alias. If the former, 2084 * we need to remember that. 2085 */ 2086 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2087 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2088 if (md->pvh_attrs & PVF_KMPAGE) 2089 bad_alias = true; 2090 break; 2091 } 2092 } 2093 md->pvh_attrs &= ~PVF_WRITE; 2094 /* 2095 * No KMPAGE and we exited early, so we must have 2096 * multiple color mappings. 2097 */ 2098 if (!bad_alias && pv != NULL) 2099 md->pvh_attrs |= PVF_MULTCLR; 2100 } 2101 2102 /* If no conflicting colors, set everything back to cached */ 2103 if (!bad_alias) { 2104 #ifdef DEBUG 2105 if ((md->pvh_attrs & PVF_WRITE) 2106 || ro_mappings < 2) { 2107 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2108 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2109 } 2110 #endif 2111 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2112 md->pvh_attrs |= tst_mask | PVF_COLORED; 2113 /* 2114 * Restore DIRTY bit if page is modified 2115 */ 2116 if (md->pvh_attrs & PVF_DMOD) 2117 md->pvh_attrs |= PVF_DIRTY; 2118 PMAPCOUNT(vac_color_restore); 2119 } else { 2120 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2121 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2122 } 2123 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2124 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2125 } else if (!va) { 2126 KASSERT(pmap_is_page_colored_p(md)); 2127 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2128 || (md->pvh_attrs & PVF_DIRTY)); 2129 if (rw_mappings == 0) { 2130 md->pvh_attrs &= ~PVF_WRITE; 2131 if (ro_mappings == 1 2132 && (md->pvh_attrs & PVF_MULTCLR)) { 2133 /* 2134 * If this is the last readonly mapping 2135 * but it doesn't match the current color 2136 * for the page, change the current color 2137 * to match this last readonly mapping. 2138 */ 2139 pv = SLIST_FIRST(&md->pvh_list); 2140 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2141 & arm_cache_prefer_mask; 2142 if (tst_mask) { 2143 md->pvh_attrs ^= tst_mask; 2144 PMAPCOUNT(vac_color_change); 2145 } 2146 } 2147 } 2148 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2149 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2150 return; 2151 } else if (!pmap_is_page_colored_p(md)) { 2152 /* not colored so we just use its color */ 2153 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2154 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2155 PMAPCOUNT(vac_color_new); 2156 md->pvh_attrs &= PAGE_SIZE - 1; 2157 md->pvh_attrs |= PVF_COLORED 2158 | (va & arm_cache_prefer_mask) 2159 | (rw_mappings > 0 ? PVF_WRITE : 0); 2160 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2161 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2162 return; 2163 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2164 bad_alias = false; 2165 if (rw_mappings > 0) { 2166 /* 2167 * We now have writeable mappings and if we have 2168 * readonly mappings in more than once color, we have 2169 * an aliasing problem. Regardless mark the page as 2170 * writeable. 2171 */ 2172 if (md->pvh_attrs & PVF_MULTCLR) { 2173 if (ro_mappings < 2) { 2174 /* 2175 * If we only have less than two 2176 * read-only mappings, just flush the 2177 * non-primary colors from the cache. 2178 */ 2179 pmap_flush_page(md, pa, 2180 PMAP_FLUSH_SECONDARY); 2181 } else { 2182 bad_alias = true; 2183 } 2184 } 2185 md->pvh_attrs |= PVF_WRITE; 2186 } 2187 /* If no conflicting colors, set everything back to cached */ 2188 if (!bad_alias) { 2189 #ifdef DEBUG 2190 if (rw_mappings > 0 2191 || (md->pvh_attrs & PMAP_KMPAGE)) { 2192 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2193 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2194 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2195 } 2196 #endif 2197 if (SLIST_EMPTY(&md->pvh_list)) 2198 PMAPCOUNT(vac_color_reuse); 2199 else 2200 PMAPCOUNT(vac_color_ok); 2201 2202 /* matching color, just return */ 2203 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2204 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2205 return; 2206 } 2207 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2208 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2209 2210 /* color conflict. evict from cache. */ 2211 2212 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2213 md->pvh_attrs &= ~PVF_COLORED; 2214 md->pvh_attrs |= PVF_NC; 2215 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2216 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2217 PMAPCOUNT(vac_color_erase); 2218 } else if (rw_mappings == 0 2219 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2220 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2221 2222 /* 2223 * If the page has dirty cache lines, clean it. 2224 */ 2225 if (md->pvh_attrs & PVF_DIRTY) 2226 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2227 2228 /* 2229 * If this is the first remapping (we know that there are no 2230 * writeable mappings), then this is a simple color change. 2231 * Otherwise this is a seconary r/o mapping, which means 2232 * we don't have to do anything. 2233 */ 2234 if (ro_mappings == 1) { 2235 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2236 md->pvh_attrs &= PAGE_SIZE - 1; 2237 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2238 PMAPCOUNT(vac_color_change); 2239 } else { 2240 PMAPCOUNT(vac_color_blind); 2241 } 2242 md->pvh_attrs |= PVF_MULTCLR; 2243 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2244 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2245 return; 2246 } else { 2247 if (rw_mappings > 0) 2248 md->pvh_attrs |= PVF_WRITE; 2249 2250 /* color conflict. evict from cache. */ 2251 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2252 2253 /* the list can't be empty because this was a enter/modify */ 2254 pv = SLIST_FIRST(&md->pvh_list); 2255 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2256 KASSERT(pv); 2257 /* 2258 * If there's only one mapped page, change color to the 2259 * page's new color and return. Restore the DIRTY bit 2260 * that was erased by pmap_flush_page. 2261 */ 2262 if (SLIST_NEXT(pv, pv_link) == NULL) { 2263 md->pvh_attrs &= PAGE_SIZE - 1; 2264 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2265 if (md->pvh_attrs & PVF_DMOD) 2266 md->pvh_attrs |= PVF_DIRTY; 2267 PMAPCOUNT(vac_color_change); 2268 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2269 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2270 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2271 return; 2272 } 2273 } 2274 bad_alias = true; 2275 md->pvh_attrs &= ~PVF_COLORED; 2276 md->pvh_attrs |= PVF_NC; 2277 PMAPCOUNT(vac_color_erase); 2278 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2279 } 2280 2281 fixup: 2282 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2283 2284 /* 2285 * Turn cacheing on/off for all pages. 2286 */ 2287 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2288 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2289 pv->pv_va); 2290 KASSERTMSG(l2b != NULL, "%#lx", va); 2291 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2292 const pt_entry_t opte = *ptep; 2293 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2294 if (bad_alias) { 2295 pv->pv_flags |= PVF_NC; 2296 } else { 2297 pv->pv_flags &= ~PVF_NC; 2298 npte |= pte_l2_s_cache_mode; 2299 } 2300 2301 if (opte == npte) /* only update is there's a change */ 2302 continue; 2303 2304 if (l2pte_valid_p(npte)) { 2305 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2306 } 2307 2308 l2pte_set(ptep, npte, opte); 2309 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2310 } 2311 #endif /* !ARM_MMU_EXTENDED */ 2312 } 2313 #endif /* PMAP_CACHE_VIPT */ 2314 2315 2316 /* 2317 * Modify pte bits for all ptes corresponding to the given physical address. 2318 * We use `maskbits' rather than `clearbits' because we're always passing 2319 * constants and the latter would require an extra inversion at run-time. 2320 */ 2321 static void 2322 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2323 { 2324 struct pv_entry *pv; 2325 #ifdef PMAP_CACHE_VIPT 2326 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2327 #ifdef ARM_MMU_EXTENDED 2328 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2329 #else 2330 const u_int execbits = 0; 2331 bool need_vac_me_harder = false; 2332 bool need_syncicache = false; 2333 #endif 2334 #else 2335 const u_int execbits = 0; 2336 #endif 2337 2338 NPDEBUG(PDB_BITS, 2339 printf("pmap_clearbit: md %p mask 0x%x\n", 2340 md, maskbits)); 2341 2342 #ifdef PMAP_CACHE_VIPT 2343 /* 2344 * If we might want to sync the I-cache and we've modified it, 2345 * then we know we definitely need to sync or discard it. 2346 */ 2347 if (want_syncicache) { 2348 #ifdef ARM_MMU_EXTENDED 2349 if (md->pvh_attrs & PVF_MOD) 2350 md->pvh_attrs &= ~PVF_EXEC; 2351 #else 2352 need_syncicache = md->pvh_attrs & PVF_MOD; 2353 #endif 2354 } 2355 #endif 2356 KASSERT(pmap_page_locked_p(md)); 2357 2358 /* 2359 * Clear saved attributes (modify, reference) 2360 */ 2361 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2362 2363 if (SLIST_EMPTY(&md->pvh_list)) { 2364 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2365 if (need_syncicache) { 2366 /* 2367 * No one has it mapped, so just discard it. The next 2368 * exec remapping will cause it to be synced. 2369 */ 2370 md->pvh_attrs &= ~PVF_EXEC; 2371 PMAPCOUNT(exec_discarded_clearbit); 2372 } 2373 #endif 2374 return; 2375 } 2376 2377 /* 2378 * Loop over all current mappings setting/clearing as appropos 2379 */ 2380 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2381 pmap_t pm = pv->pv_pmap; 2382 const vaddr_t va = pv->pv_va; 2383 const u_int oflags = pv->pv_flags; 2384 #ifndef ARM_MMU_EXTENDED 2385 /* 2386 * Kernel entries are unmanaged and as such not to be changed. 2387 */ 2388 if (PV_IS_KENTRY_P(oflags)) 2389 continue; 2390 #endif 2391 pv->pv_flags &= ~maskbits; 2392 2393 pmap_release_page_lock(md); 2394 pmap_acquire_pmap_lock(pm); 2395 2396 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2397 if (l2b == NULL) { 2398 pmap_release_pmap_lock(pm); 2399 pmap_acquire_page_lock(md); 2400 continue; 2401 } 2402 KASSERTMSG(l2b != NULL, "%#lx", va); 2403 2404 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2405 const pt_entry_t opte = *ptep; 2406 pt_entry_t npte = opte | execbits; 2407 2408 #if defined(DIAGNOSTIC) && (defined(CPU_ARMV6) || defined(CPU_ARMV7)) 2409 if (CPU_IS_ARMV6_P() || CPU_IS_ARMV7_P()) { 2410 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2411 } 2412 #endif 2413 2414 NPDEBUG(PDB_BITS, 2415 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2416 __func__, pv, pm, va, oflags)); 2417 2418 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2419 #ifdef PMAP_CACHE_VIVT 2420 if ((oflags & PVF_NC)) { 2421 /* 2422 * Entry is not cacheable: 2423 * 2424 * Don't turn caching on again if this is a 2425 * modified emulation. This would be 2426 * inconsitent with the settings created by 2427 * pmap_vac_me_harder(). Otherwise, it's safe 2428 * to re-enable cacheing. 2429 * 2430 * There's no need to call pmap_vac_me_harder() 2431 * here: all pages are losing their write 2432 * permission. 2433 */ 2434 if (maskbits & PVF_WRITE) { 2435 npte |= pte_l2_s_cache_mode; 2436 pv->pv_flags &= ~PVF_NC; 2437 } 2438 } else 2439 if (l2pte_writable_p(opte)) { 2440 /* 2441 * Entry is writable/cacheable: check if pmap 2442 * is current if it is flush it, otherwise it 2443 * won't be in the cache 2444 */ 2445 pmap_cache_wbinv_page(pm, va, 2446 (maskbits & PVF_REF) != 0, 2447 oflags|PVF_WRITE); 2448 } 2449 #endif 2450 2451 /* make the pte read only */ 2452 npte = l2pte_set_readonly(npte); 2453 2454 pmap_acquire_page_lock(md); 2455 #ifdef MULTIPROCESSOR 2456 pv = pmap_find_pv(md, pm, va); 2457 #endif 2458 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2459 /* 2460 * Keep alias accounting up to date 2461 */ 2462 if (pm == pmap_kernel()) { 2463 md->krw_mappings--; 2464 md->kro_mappings++; 2465 } else { 2466 md->urw_mappings--; 2467 md->uro_mappings++; 2468 } 2469 #ifdef PMAP_CACHE_VIPT 2470 if (arm_cache_prefer_mask != 0) { 2471 if (md->urw_mappings + md->krw_mappings == 0) { 2472 md->pvh_attrs &= ~PVF_WRITE; 2473 } else { 2474 PMAP_VALIDATE_MD_PAGE(md); 2475 } 2476 } 2477 #ifndef ARM_MMU_EXTENDED 2478 if (want_syncicache) 2479 need_syncicache = true; 2480 need_vac_me_harder = true; 2481 #endif 2482 #endif /* PMAP_CACHE_VIPT */ 2483 } 2484 pmap_release_page_lock(md); 2485 } 2486 2487 if (maskbits & PVF_REF) { 2488 if (true 2489 #ifndef ARM_MMU_EXTENDED 2490 && (oflags & PVF_NC) == 0 2491 #endif 2492 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2493 && l2pte_valid_p(npte)) { 2494 #ifdef PMAP_CACHE_VIVT 2495 /* 2496 * Check npte here; we may have already 2497 * done the wbinv above, and the validity 2498 * of the PTE is the same for opte and 2499 * npte. 2500 */ 2501 pmap_cache_wbinv_page(pm, va, true, oflags); 2502 #endif 2503 } 2504 2505 /* 2506 * Make the PTE invalid so that we will take a 2507 * page fault the next time the mapping is 2508 * referenced. 2509 */ 2510 npte &= ~L2_TYPE_MASK; 2511 npte |= L2_TYPE_INV; 2512 } 2513 2514 if (npte != opte) { 2515 l2pte_set(ptep, npte, opte); 2516 PTE_SYNC(ptep); 2517 2518 /* Flush the TLB entry if a current pmap. */ 2519 pmap_tlb_flush_SE(pm, va, oflags); 2520 } 2521 2522 pmap_release_pmap_lock(pm); 2523 pmap_acquire_page_lock(md); 2524 2525 NPDEBUG(PDB_BITS, 2526 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2527 pm, va, opte, npte)); 2528 } 2529 2530 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2531 /* 2532 * If we need to sync the I-cache and we haven't done it yet, do it. 2533 */ 2534 if (need_syncicache) { 2535 pmap_release_page_lock(md); 2536 pmap_syncicache_page(md, pa); 2537 pmap_acquire_page_lock(md); 2538 PMAPCOUNT(exec_synced_clearbit); 2539 } 2540 2541 /* 2542 * If we are changing this to read-only, we need to call vac_me_harder 2543 * so we can change all the read-only pages to cacheable. We pretend 2544 * this as a page deletion. 2545 */ 2546 if (need_vac_me_harder) { 2547 if (md->pvh_attrs & PVF_NC) 2548 pmap_vac_me_harder(md, pa, NULL, 0); 2549 } 2550 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2551 } 2552 2553 /* 2554 * pmap_clean_page() 2555 * 2556 * This is a local function used to work out the best strategy to clean 2557 * a single page referenced by its entry in the PV table. It's used by 2558 * pmap_copy_page, pmap_zero page and maybe some others later on. 2559 * 2560 * Its policy is effectively: 2561 * o If there are no mappings, we don't bother doing anything with the cache. 2562 * o If there is one mapping, we clean just that page. 2563 * o If there are multiple mappings, we clean the entire cache. 2564 * 2565 * So that some functions can be further optimised, it returns 0 if it didn't 2566 * clean the entire cache, or 1 if it did. 2567 * 2568 * XXX One bug in this routine is that if the pv_entry has a single page 2569 * mapped at 0x00000000 a whole cache clean will be performed rather than 2570 * just the 1 page. Since this should not occur in everyday use and if it does 2571 * it will just result in not the most efficient clean for the page. 2572 */ 2573 #ifdef PMAP_CACHE_VIVT 2574 static bool 2575 pmap_clean_page(struct vm_page_md *md, bool is_src) 2576 { 2577 struct pv_entry *pv; 2578 pmap_t pm_to_clean = NULL; 2579 bool cache_needs_cleaning = false; 2580 vaddr_t page_to_clean = 0; 2581 u_int flags = 0; 2582 2583 /* 2584 * Since we flush the cache each time we change to a different 2585 * user vmspace, we only need to flush the page if it is in the 2586 * current pmap. 2587 */ 2588 KASSERT(pmap_page_locked_p(md)); 2589 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2590 if (pmap_is_current(pv->pv_pmap)) { 2591 flags |= pv->pv_flags; 2592 /* 2593 * The page is mapped non-cacheable in 2594 * this map. No need to flush the cache. 2595 */ 2596 if (pv->pv_flags & PVF_NC) { 2597 #ifdef DIAGNOSTIC 2598 KASSERT(!cache_needs_cleaning); 2599 #endif 2600 break; 2601 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2602 continue; 2603 if (cache_needs_cleaning) { 2604 page_to_clean = 0; 2605 break; 2606 } else { 2607 page_to_clean = pv->pv_va; 2608 pm_to_clean = pv->pv_pmap; 2609 } 2610 cache_needs_cleaning = true; 2611 } 2612 } 2613 2614 if (page_to_clean) { 2615 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2616 !is_src, flags | PVF_REF); 2617 } else if (cache_needs_cleaning) { 2618 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2619 2620 pmap_cache_wbinv_all(pm, flags); 2621 return true; 2622 } 2623 return false; 2624 } 2625 #endif 2626 2627 #ifdef PMAP_CACHE_VIPT 2628 /* 2629 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2630 * right cache alias to make sure we flush the right stuff. 2631 */ 2632 void 2633 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2634 { 2635 pmap_t kpm = pmap_kernel(); 2636 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2637 ? PAGE_SIZE 2638 : arm_pcache.icache_way_size; 2639 2640 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2641 md, md->pvh_attrs)); 2642 /* 2643 * No need to clean the page if it's non-cached. 2644 */ 2645 #ifndef ARM_MMU_EXTENDED 2646 if (md->pvh_attrs & PVF_NC) 2647 return; 2648 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2649 #endif 2650 2651 pt_entry_t * const ptep = cpu_cdst_pte(0); 2652 const vaddr_t dstp = cpu_cdstp(0); 2653 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2654 if (way_size <= PAGE_SIZE) { 2655 bool ok = false; 2656 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2657 if (ok) { 2658 cpu_icache_sync_range(vdstp, way_size); 2659 return; 2660 } 2661 } 2662 #endif 2663 2664 /* 2665 * We don't worry about the color of the exec page, we map the 2666 * same page to pages in the way and then do the icache_sync on 2667 * the entire way making sure we are cleaned. 2668 */ 2669 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2670 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2671 2672 for (size_t i = 0, j = 0; i < way_size; 2673 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2674 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2675 /* 2676 * Set up a PTE with to flush these cache lines. 2677 */ 2678 l2pte_set(ptep + j, npte, 0); 2679 } 2680 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2681 2682 /* 2683 * Flush it. 2684 */ 2685 cpu_icache_sync_range(dstp, way_size); 2686 2687 for (size_t i = 0, j = 0; i < way_size; 2688 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2689 /* 2690 * Unmap the page(s). 2691 */ 2692 l2pte_reset(ptep + j); 2693 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2694 } 2695 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2696 2697 md->pvh_attrs |= PVF_EXEC; 2698 PMAPCOUNT(exec_synced); 2699 } 2700 2701 #ifndef ARM_MMU_EXTENDED 2702 void 2703 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2704 { 2705 vsize_t va_offset, end_va; 2706 bool wbinv_p; 2707 2708 if (arm_cache_prefer_mask == 0) 2709 return; 2710 2711 switch (flush) { 2712 case PMAP_FLUSH_PRIMARY: 2713 if (md->pvh_attrs & PVF_MULTCLR) { 2714 va_offset = 0; 2715 end_va = arm_cache_prefer_mask; 2716 md->pvh_attrs &= ~PVF_MULTCLR; 2717 PMAPCOUNT(vac_flush_lots); 2718 } else { 2719 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2720 end_va = va_offset; 2721 PMAPCOUNT(vac_flush_one); 2722 } 2723 /* 2724 * Mark that the page is no longer dirty. 2725 */ 2726 md->pvh_attrs &= ~PVF_DIRTY; 2727 wbinv_p = true; 2728 break; 2729 case PMAP_FLUSH_SECONDARY: 2730 va_offset = 0; 2731 end_va = arm_cache_prefer_mask; 2732 wbinv_p = true; 2733 md->pvh_attrs &= ~PVF_MULTCLR; 2734 PMAPCOUNT(vac_flush_lots); 2735 break; 2736 case PMAP_CLEAN_PRIMARY: 2737 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2738 end_va = va_offset; 2739 wbinv_p = false; 2740 /* 2741 * Mark that the page is no longer dirty. 2742 */ 2743 if ((md->pvh_attrs & PVF_DMOD) == 0) 2744 md->pvh_attrs &= ~PVF_DIRTY; 2745 PMAPCOUNT(vac_clean_one); 2746 break; 2747 default: 2748 return; 2749 } 2750 2751 KASSERT(!(md->pvh_attrs & PVF_NC)); 2752 2753 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2754 md, md->pvh_attrs)); 2755 2756 const size_t scache_line_size = arm_scache.dcache_line_size; 2757 2758 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2759 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2760 const vaddr_t dstp = cpu_cdstp(va_offset); 2761 const pt_entry_t opte = *ptep; 2762 2763 if (flush == PMAP_FLUSH_SECONDARY 2764 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2765 continue; 2766 2767 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2768 /* 2769 * Set up a PTE with the right coloring to flush 2770 * existing cache entries. 2771 */ 2772 const pt_entry_t npte = L2_S_PROTO 2773 | pa 2774 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2775 | pte_l2_s_cache_mode; 2776 l2pte_set(ptep, npte, opte); 2777 PTE_SYNC(ptep); 2778 2779 /* 2780 * Flush it. Make sure to flush secondary cache too since 2781 * bus_dma will ignore uncached pages. 2782 */ 2783 if (scache_line_size != 0) { 2784 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2785 if (wbinv_p) { 2786 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2787 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2788 } else { 2789 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2790 } 2791 } else { 2792 if (wbinv_p) { 2793 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2794 } else { 2795 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2796 } 2797 } 2798 2799 /* 2800 * Restore the page table entry since we might have interrupted 2801 * pmap_zero_page or pmap_copy_page which was already using 2802 * this pte. 2803 */ 2804 if (opte) { 2805 l2pte_set(ptep, opte, npte); 2806 } else { 2807 l2pte_reset(ptep); 2808 } 2809 PTE_SYNC(ptep); 2810 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2811 } 2812 } 2813 #endif /* ARM_MMU_EXTENDED */ 2814 #endif /* PMAP_CACHE_VIPT */ 2815 2816 /* 2817 * Routine: pmap_page_remove 2818 * Function: 2819 * Removes this physical page from 2820 * all physical maps in which it resides. 2821 * Reflects back modify bits to the pager. 2822 */ 2823 static void 2824 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2825 { 2826 struct l2_bucket *l2b; 2827 struct pv_entry *pv; 2828 pt_entry_t *ptep; 2829 #ifndef ARM_MMU_EXTENDED 2830 bool flush = false; 2831 #endif 2832 u_int flags = 0; 2833 2834 NPDEBUG(PDB_FOLLOW, 2835 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2836 pa)); 2837 2838 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2839 pmap_acquire_page_lock(md); 2840 if (*pvp == NULL) { 2841 #ifdef PMAP_CACHE_VIPT 2842 /* 2843 * We *know* the page contents are about to be replaced. 2844 * Discard the exec contents 2845 */ 2846 if (PV_IS_EXEC_P(md->pvh_attrs)) 2847 PMAPCOUNT(exec_discarded_page_protect); 2848 md->pvh_attrs &= ~PVF_EXEC; 2849 PMAP_VALIDATE_MD_PAGE(md); 2850 #endif 2851 pmap_release_page_lock(md); 2852 return; 2853 } 2854 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2855 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2856 #endif 2857 2858 /* 2859 * Clear alias counts 2860 */ 2861 #ifdef PMAP_CACHE_VIVT 2862 md->k_mappings = 0; 2863 #endif 2864 md->urw_mappings = md->uro_mappings = 0; 2865 2866 #ifdef PMAP_CACHE_VIVT 2867 pmap_clean_page(md, false); 2868 #endif 2869 2870 while ((pv = *pvp) != NULL) { 2871 pmap_t pm = pv->pv_pmap; 2872 #ifndef ARM_MMU_EXTENDED 2873 if (flush == false && pmap_is_current(pm)) 2874 flush = true; 2875 #endif 2876 2877 if (pm == pmap_kernel()) { 2878 #ifdef PMAP_CACHE_VIPT 2879 /* 2880 * If this was unmanaged mapping, it must be preserved. 2881 * Move it back on the list and advance the end-of-list 2882 * pointer. 2883 */ 2884 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2885 *pvp = pv; 2886 pvp = &SLIST_NEXT(pv, pv_link); 2887 continue; 2888 } 2889 if (pv->pv_flags & PVF_WRITE) 2890 md->krw_mappings--; 2891 else 2892 md->kro_mappings--; 2893 #endif 2894 PMAPCOUNT(kernel_unmappings); 2895 } 2896 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2897 PMAPCOUNT(unmappings); 2898 2899 pmap_release_page_lock(md); 2900 pmap_acquire_pmap_lock(pm); 2901 2902 #ifdef ARM_MMU_EXTENDED 2903 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2904 #endif 2905 2906 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2907 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2908 2909 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2910 2911 /* 2912 * Update statistics 2913 */ 2914 --pm->pm_stats.resident_count; 2915 2916 /* Wired bit */ 2917 if (pv->pv_flags & PVF_WIRED) 2918 --pm->pm_stats.wired_count; 2919 2920 flags |= pv->pv_flags; 2921 2922 /* 2923 * Invalidate the PTEs. 2924 */ 2925 l2pte_reset(ptep); 2926 PTE_SYNC_CURRENT(pm, ptep); 2927 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2928 pmap_release_pmap_lock(pm); 2929 2930 pool_put(&pmap_pv_pool, pv); 2931 pmap_acquire_page_lock(md); 2932 #ifdef MULTIPROCESSOR 2933 /* 2934 * Restart of the beginning of the list. 2935 */ 2936 pvp = &SLIST_FIRST(&md->pvh_list); 2937 #endif 2938 } 2939 /* 2940 * if we reach the end of the list and there are still mappings, they 2941 * might be able to be cached now. And they must be kernel mappings. 2942 */ 2943 if (!SLIST_EMPTY(&md->pvh_list)) { 2944 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2945 } 2946 2947 #ifdef PMAP_CACHE_VIPT 2948 /* 2949 * Its EXEC cache is now gone. 2950 */ 2951 if (PV_IS_EXEC_P(md->pvh_attrs)) 2952 PMAPCOUNT(exec_discarded_page_protect); 2953 md->pvh_attrs &= ~PVF_EXEC; 2954 KASSERT(md->urw_mappings == 0); 2955 KASSERT(md->uro_mappings == 0); 2956 #ifndef ARM_MMU_EXTENDED 2957 if (arm_cache_prefer_mask != 0) { 2958 if (md->krw_mappings == 0) 2959 md->pvh_attrs &= ~PVF_WRITE; 2960 PMAP_VALIDATE_MD_PAGE(md); 2961 } 2962 #endif /* ARM_MMU_EXTENDED */ 2963 #endif /* PMAP_CACHE_VIPT */ 2964 pmap_release_page_lock(md); 2965 2966 #ifndef ARM_MMU_EXTENDED 2967 if (flush) { 2968 /* 2969 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2970 * would need a subsequent call to pmap_update() to ensure 2971 * curpm->pm_cstate.cs_all is reset. Our callers are not 2972 * required to do that (see pmap(9)), so we can't modify 2973 * the current pmap's state. 2974 */ 2975 if (PV_BEEN_EXECD(flags)) 2976 cpu_tlb_flushID(); 2977 else 2978 cpu_tlb_flushD(); 2979 } 2980 cpu_cpwait(); 2981 #endif /* ARM_MMU_EXTENDED */ 2982 } 2983 2984 /* 2985 * pmap_t pmap_create(void) 2986 * 2987 * Create a new pmap structure from scratch. 2988 */ 2989 pmap_t 2990 pmap_create(void) 2991 { 2992 pmap_t pm; 2993 2994 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2995 2996 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2997 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2998 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2999 3000 pm->pm_stats.wired_count = 0; 3001 pm->pm_stats.resident_count = 1; 3002 #ifdef ARM_MMU_EXTENDED 3003 #ifdef MULTIPROCESSOR 3004 kcpuset_create(&pm->pm_active, true); 3005 kcpuset_create(&pm->pm_onproc, true); 3006 #endif 3007 #else 3008 pm->pm_cstate.cs_all = 0; 3009 #endif 3010 pmap_alloc_l1(pm); 3011 3012 /* 3013 * Note: The pool cache ensures that the pm_l2[] array is already 3014 * initialised to zero. 3015 */ 3016 3017 pmap_pinit(pm); 3018 3019 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3020 3021 return (pm); 3022 } 3023 3024 u_int 3025 arm32_mmap_flags(paddr_t pa) 3026 { 3027 /* 3028 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3029 * and we're using the upper bits in page numbers to pass flags around 3030 * so we might as well use the same bits 3031 */ 3032 return (u_int)pa & PMAP_MD_MASK; 3033 } 3034 /* 3035 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3036 * u_int flags) 3037 * 3038 * Insert the given physical page (p) at 3039 * the specified virtual address (v) in the 3040 * target physical map with the protection requested. 3041 * 3042 * NB: This is the only routine which MAY NOT lazy-evaluate 3043 * or lose information. That is, this routine must actually 3044 * insert this page into the given map NOW. 3045 */ 3046 int 3047 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3048 { 3049 struct l2_bucket *l2b; 3050 struct vm_page *pg, *opg; 3051 u_int nflags; 3052 u_int oflags; 3053 const bool kpm_p = (pm == pmap_kernel()); 3054 #ifdef ARM_HAS_VBAR 3055 const bool vector_page_p = false; 3056 #else 3057 const bool vector_page_p = (va == vector_page); 3058 #endif 3059 3060 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3061 3062 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3063 pm, va, pa, prot); 3064 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3065 3066 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3067 KDASSERT(((va | pa) & PGOFSET) == 0); 3068 3069 /* 3070 * Get a pointer to the page. Later on in this function, we 3071 * test for a managed page by checking pg != NULL. 3072 */ 3073 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3074 3075 nflags = 0; 3076 if (prot & VM_PROT_WRITE) 3077 nflags |= PVF_WRITE; 3078 if (prot & VM_PROT_EXECUTE) 3079 nflags |= PVF_EXEC; 3080 if (flags & PMAP_WIRED) 3081 nflags |= PVF_WIRED; 3082 3083 pmap_acquire_pmap_lock(pm); 3084 3085 /* 3086 * Fetch the L2 bucket which maps this page, allocating one if 3087 * necessary for user pmaps. 3088 */ 3089 if (kpm_p) { 3090 l2b = pmap_get_l2_bucket(pm, va); 3091 } else { 3092 l2b = pmap_alloc_l2_bucket(pm, va); 3093 } 3094 if (l2b == NULL) { 3095 if (flags & PMAP_CANFAIL) { 3096 pmap_release_pmap_lock(pm); 3097 return (ENOMEM); 3098 } 3099 panic("pmap_enter: failed to allocate L2 bucket"); 3100 } 3101 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3102 const pt_entry_t opte = *ptep; 3103 pt_entry_t npte = pa; 3104 oflags = 0; 3105 3106 if (opte) { 3107 /* 3108 * There is already a mapping at this address. 3109 * If the physical address is different, lookup the 3110 * vm_page. 3111 */ 3112 if (l2pte_pa(opte) != pa) 3113 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3114 else 3115 opg = pg; 3116 } else 3117 opg = NULL; 3118 3119 if (pg) { 3120 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3121 3122 /* 3123 * This is to be a managed mapping. 3124 */ 3125 pmap_acquire_page_lock(md); 3126 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3127 /* 3128 * - The access type indicates that we don't need 3129 * to do referenced emulation. 3130 * OR 3131 * - The physical page has already been referenced 3132 * so no need to re-do referenced emulation here. 3133 */ 3134 npte |= l2pte_set_readonly(L2_S_PROTO); 3135 3136 nflags |= PVF_REF; 3137 3138 if ((prot & VM_PROT_WRITE) != 0 && 3139 ((flags & VM_PROT_WRITE) != 0 || 3140 (md->pvh_attrs & PVF_MOD) != 0)) { 3141 /* 3142 * This is a writable mapping, and the 3143 * page's mod state indicates it has 3144 * already been modified. Make it 3145 * writable from the outset. 3146 */ 3147 npte = l2pte_set_writable(npte); 3148 nflags |= PVF_MOD; 3149 } 3150 3151 #ifdef ARM_MMU_EXTENDED 3152 /* 3153 * If the page has been cleaned, then the pvh_attrs 3154 * will have PVF_EXEC set, so mark it execute so we 3155 * don't get an access fault when trying to execute 3156 * from it. 3157 */ 3158 if (md->pvh_attrs & nflags & PVF_EXEC) { 3159 npte &= ~L2_XS_XN; 3160 } 3161 #endif 3162 } else { 3163 /* 3164 * Need to do page referenced emulation. 3165 */ 3166 npte |= L2_TYPE_INV; 3167 } 3168 3169 if (flags & ARM32_MMAP_WRITECOMBINE) { 3170 npte |= pte_l2_s_wc_mode; 3171 } else 3172 npte |= pte_l2_s_cache_mode; 3173 3174 if (pg == opg) { 3175 /* 3176 * We're changing the attrs of an existing mapping. 3177 */ 3178 oflags = pmap_modify_pv(md, pa, pm, va, 3179 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3180 PVF_MOD | PVF_REF, nflags); 3181 3182 #ifdef PMAP_CACHE_VIVT 3183 /* 3184 * We may need to flush the cache if we're 3185 * doing rw-ro... 3186 */ 3187 if (pm->pm_cstate.cs_cache_d && 3188 (oflags & PVF_NC) == 0 && 3189 l2pte_writable_p(opte) && 3190 (prot & VM_PROT_WRITE) == 0) 3191 cpu_dcache_wb_range(va, PAGE_SIZE); 3192 #endif 3193 } else { 3194 struct pv_entry *pv; 3195 /* 3196 * New mapping, or changing the backing page 3197 * of an existing mapping. 3198 */ 3199 if (opg) { 3200 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3201 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3202 3203 /* 3204 * Replacing an existing mapping with a new one. 3205 * It is part of our managed memory so we 3206 * must remove it from the PV list 3207 */ 3208 pv = pmap_remove_pv(omd, opa, pm, va); 3209 pmap_vac_me_harder(omd, opa, pm, 0); 3210 oflags = pv->pv_flags; 3211 3212 #ifdef PMAP_CACHE_VIVT 3213 /* 3214 * If the old mapping was valid (ref/mod 3215 * emulation creates 'invalid' mappings 3216 * initially) then make sure to frob 3217 * the cache. 3218 */ 3219 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3220 pmap_cache_wbinv_page(pm, va, true, 3221 oflags); 3222 } 3223 #endif 3224 } else { 3225 pmap_release_page_lock(md); 3226 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3227 if (pv == NULL) { 3228 pmap_release_pmap_lock(pm); 3229 if ((flags & PMAP_CANFAIL) == 0) 3230 panic("pmap_enter: " 3231 "no pv entries"); 3232 3233 pmap_free_l2_bucket(pm, l2b, 0); 3234 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3235 0, 0, 0, 0); 3236 return (ENOMEM); 3237 } 3238 pmap_acquire_page_lock(md); 3239 } 3240 3241 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3242 } 3243 pmap_release_page_lock(md); 3244 } else { 3245 /* 3246 * We're mapping an unmanaged page. 3247 * These are always readable, and possibly writable, from 3248 * the get go as we don't need to track ref/mod status. 3249 */ 3250 npte |= l2pte_set_readonly(L2_S_PROTO); 3251 if (prot & VM_PROT_WRITE) 3252 npte = l2pte_set_writable(npte); 3253 3254 /* 3255 * Make sure the vector table is mapped cacheable 3256 */ 3257 if ((vector_page_p && !kpm_p) 3258 || (flags & ARM32_MMAP_CACHEABLE)) { 3259 npte |= pte_l2_s_cache_mode; 3260 #ifdef ARM_MMU_EXTENDED 3261 npte &= ~L2_XS_XN; /* and executable */ 3262 #endif 3263 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3264 npte |= pte_l2_s_wc_mode; 3265 } 3266 if (opg) { 3267 /* 3268 * Looks like there's an existing 'managed' mapping 3269 * at this address. 3270 */ 3271 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3272 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3273 3274 pmap_acquire_page_lock(omd); 3275 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3276 pmap_vac_me_harder(omd, opa, pm, 0); 3277 oflags = pv->pv_flags; 3278 pmap_release_page_lock(omd); 3279 3280 #ifdef PMAP_CACHE_VIVT 3281 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3282 pmap_cache_wbinv_page(pm, va, true, oflags); 3283 } 3284 #endif 3285 pool_put(&pmap_pv_pool, pv); 3286 } 3287 } 3288 3289 /* 3290 * Make sure userland mappings get the right permissions 3291 */ 3292 if (!vector_page_p && !kpm_p) { 3293 npte |= L2_S_PROT_U; 3294 #ifdef ARM_MMU_EXTENDED 3295 npte |= L2_XS_nG; /* user pages are not global */ 3296 #endif 3297 } 3298 3299 /* 3300 * Keep the stats up to date 3301 */ 3302 if (opte == 0) { 3303 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3304 pm->pm_stats.resident_count++; 3305 } 3306 3307 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3308 3309 #if defined(ARM_MMU_EXTENDED) 3310 /* 3311 * If exec protection was requested but the page hasn't been synced, 3312 * sync it now and allow execution from it. 3313 */ 3314 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3315 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3316 npte &= ~L2_XS_XN; 3317 pmap_syncicache_page(md, pa); 3318 PMAPCOUNT(exec_synced_map); 3319 } 3320 #endif 3321 /* 3322 * If this is just a wiring change, the two PTEs will be 3323 * identical, so there's no need to update the page table. 3324 */ 3325 if (npte != opte) { 3326 3327 l2pte_set(ptep, npte, opte); 3328 PTE_SYNC(ptep); 3329 #ifndef ARM_MMU_EXTENDED 3330 bool is_cached = pmap_is_cached(pm); 3331 if (is_cached) { 3332 /* 3333 * We only need to frob the cache/tlb if this pmap 3334 * is current 3335 */ 3336 if (!vector_page_p && l2pte_valid_p(npte)) { 3337 /* 3338 * This mapping is likely to be accessed as 3339 * soon as we return to userland. Fix up the 3340 * L1 entry to avoid taking another 3341 * page/domain fault. 3342 */ 3343 pd_entry_t *pdep = pmap_l1_kva(pm) 3344 + l1pte_index(va); 3345 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3346 | L1_C_DOM(pmap_domain(pm)); 3347 if (*pdep != pde) { 3348 l1pte_setone(pdep, pde); 3349 PTE_SYNC(pdep); 3350 } 3351 } 3352 } 3353 #endif /* !ARMM_MMU_EXTENDED */ 3354 3355 pmap_tlb_flush_SE(pm, va, oflags); 3356 3357 #ifndef ARM_MMU_EXTENDED 3358 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3359 is_cached, pm->pm_cstate.cs_all, 0, 0); 3360 3361 if (pg != NULL) { 3362 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3363 3364 pmap_acquire_page_lock(md); 3365 pmap_vac_me_harder(md, pa, pm, va); 3366 pmap_release_page_lock(md); 3367 } 3368 #endif 3369 } 3370 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3371 if (pg) { 3372 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3373 3374 pmap_acquire_page_lock(md); 3375 #ifndef ARM_MMU_EXTENDED 3376 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3377 #endif 3378 PMAP_VALIDATE_MD_PAGE(md); 3379 pmap_release_page_lock(md); 3380 } 3381 #endif 3382 3383 pmap_release_pmap_lock(pm); 3384 3385 return (0); 3386 } 3387 3388 /* 3389 * pmap_remove() 3390 * 3391 * pmap_remove is responsible for nuking a number of mappings for a range 3392 * of virtual address space in the current pmap. To do this efficiently 3393 * is interesting, because in a number of cases a wide virtual address 3394 * range may be supplied that contains few actual mappings. So, the 3395 * optimisations are: 3396 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3397 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3398 * maybe do just a partial cache clean. This path of execution is 3399 * complicated by the fact that the cache must be flushed _before_ 3400 * the PTE is nuked, being a VAC :-) 3401 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3402 * all invalidations until pmap_update(), since pmap_remove_all() has 3403 * already flushed the cache. 3404 * 4. Maybe later fast-case a single page, but I don't think this is 3405 * going to make _that_ much difference overall. 3406 */ 3407 3408 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3409 3410 void 3411 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3412 { 3413 vaddr_t next_bucket; 3414 u_int cleanlist_idx, total, cnt; 3415 struct { 3416 vaddr_t va; 3417 pt_entry_t *ptep; 3418 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3419 u_int mappings; 3420 3421 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3422 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3423 3424 /* 3425 * we lock in the pmap => pv_head direction 3426 */ 3427 pmap_acquire_pmap_lock(pm); 3428 3429 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3430 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3431 #ifndef ARM_MMU_EXTENDED 3432 if (pm->pm_cstate.cs_tlb == 0) 3433 pm->pm_remove_all = true; 3434 #endif 3435 } else 3436 cleanlist_idx = 0; 3437 3438 total = 0; 3439 3440 while (sva < eva) { 3441 /* 3442 * Do one L2 bucket's worth at a time. 3443 */ 3444 next_bucket = L2_NEXT_BUCKET_VA(sva); 3445 if (next_bucket > eva) 3446 next_bucket = eva; 3447 3448 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3449 if (l2b == NULL) { 3450 sva = next_bucket; 3451 continue; 3452 } 3453 3454 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3455 3456 for (mappings = 0; 3457 sva < next_bucket; 3458 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3459 pt_entry_t opte = *ptep; 3460 3461 if (opte == 0) { 3462 /* Nothing here, move along */ 3463 continue; 3464 } 3465 3466 u_int flags = PVF_REF; 3467 paddr_t pa = l2pte_pa(opte); 3468 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3469 3470 /* 3471 * Update flags. In a number of circumstances, 3472 * we could cluster a lot of these and do a 3473 * number of sequential pages in one go. 3474 */ 3475 if (pg != NULL) { 3476 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3477 struct pv_entry *pv; 3478 3479 pmap_acquire_page_lock(md); 3480 pv = pmap_remove_pv(md, pa, pm, sva); 3481 pmap_vac_me_harder(md, pa, pm, 0); 3482 pmap_release_page_lock(md); 3483 if (pv != NULL) { 3484 if (pm->pm_remove_all == false) { 3485 flags = pv->pv_flags; 3486 } 3487 pool_put(&pmap_pv_pool, pv); 3488 } 3489 } 3490 mappings += PAGE_SIZE / L2_S_SIZE; 3491 3492 if (!l2pte_valid_p(opte)) { 3493 /* 3494 * Ref/Mod emulation is still active for this 3495 * mapping, therefore it is has not yet been 3496 * accessed. No need to frob the cache/tlb. 3497 */ 3498 l2pte_reset(ptep); 3499 PTE_SYNC_CURRENT(pm, ptep); 3500 continue; 3501 } 3502 3503 #ifdef ARM_MMU_EXTENDED 3504 if (pm == pmap_kernel()) { 3505 l2pte_reset(ptep); 3506 PTE_SYNC(ptep); 3507 pmap_tlb_flush_SE(pm, sva, flags); 3508 continue; 3509 } 3510 #endif 3511 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3512 /* Add to the clean list. */ 3513 cleanlist[cleanlist_idx].ptep = ptep; 3514 cleanlist[cleanlist_idx].va = 3515 sva | (flags & PVF_EXEC); 3516 cleanlist_idx++; 3517 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3518 /* Nuke everything if needed. */ 3519 #ifdef PMAP_CACHE_VIVT 3520 pmap_cache_wbinv_all(pm, PVF_EXEC); 3521 #endif 3522 /* 3523 * Roll back the previous PTE list, 3524 * and zero out the current PTE. 3525 */ 3526 for (cnt = 0; 3527 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3528 l2pte_reset(cleanlist[cnt].ptep); 3529 PTE_SYNC(cleanlist[cnt].ptep); 3530 } 3531 l2pte_reset(ptep); 3532 PTE_SYNC(ptep); 3533 cleanlist_idx++; 3534 pm->pm_remove_all = true; 3535 } else { 3536 l2pte_reset(ptep); 3537 PTE_SYNC(ptep); 3538 if (pm->pm_remove_all == false) { 3539 pmap_tlb_flush_SE(pm, sva, flags); 3540 } 3541 } 3542 } 3543 3544 /* 3545 * Deal with any left overs 3546 */ 3547 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3548 total += cleanlist_idx; 3549 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3550 #ifdef ARM_MMU_EXTENDED 3551 vaddr_t clva = cleanlist[cnt].va; 3552 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3553 #else 3554 vaddr_t va = cleanlist[cnt].va; 3555 if (pm->pm_cstate.cs_all != 0) { 3556 vaddr_t clva = va & ~PAGE_MASK; 3557 u_int flags = va & PVF_EXEC; 3558 #ifdef PMAP_CACHE_VIVT 3559 pmap_cache_wbinv_page(pm, clva, true, 3560 PVF_REF | PVF_WRITE | flags); 3561 #endif 3562 pmap_tlb_flush_SE(pm, clva, 3563 PVF_REF | flags); 3564 } 3565 #endif /* ARM_MMU_EXTENDED */ 3566 l2pte_reset(cleanlist[cnt].ptep); 3567 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3568 } 3569 3570 /* 3571 * If it looks like we're removing a whole bunch 3572 * of mappings, it's faster to just write-back 3573 * the whole cache now and defer TLB flushes until 3574 * pmap_update() is called. 3575 */ 3576 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3577 cleanlist_idx = 0; 3578 else { 3579 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3580 #ifdef PMAP_CACHE_VIVT 3581 pmap_cache_wbinv_all(pm, PVF_EXEC); 3582 #endif 3583 pm->pm_remove_all = true; 3584 } 3585 } 3586 3587 3588 pmap_free_l2_bucket(pm, l2b, mappings); 3589 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3590 } 3591 3592 pmap_release_pmap_lock(pm); 3593 } 3594 3595 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3596 static struct pv_entry * 3597 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3598 { 3599 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3600 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3601 struct pv_entry *pv; 3602 3603 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3604 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3605 KASSERT(pmap_page_locked_p(md)); 3606 3607 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3608 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3609 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3610 3611 /* 3612 * If we are removing a writeable mapping to a cached exec page, 3613 * if it's the last mapping then clear it execness other sync 3614 * the page to the icache. 3615 */ 3616 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3617 && (pv->pv_flags & PVF_WRITE) != 0) { 3618 if (SLIST_EMPTY(&md->pvh_list)) { 3619 md->pvh_attrs &= ~PVF_EXEC; 3620 PMAPCOUNT(exec_discarded_kremove); 3621 } else { 3622 pmap_syncicache_page(md, pa); 3623 PMAPCOUNT(exec_synced_kremove); 3624 } 3625 } 3626 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3627 3628 return pv; 3629 } 3630 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3631 3632 /* 3633 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3634 * 3635 * We assume there is already sufficient KVM space available 3636 * to do this, as we can't allocate L2 descriptor tables/metadata 3637 * from here. 3638 */ 3639 void 3640 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3641 { 3642 #ifdef PMAP_CACHE_VIVT 3643 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3644 #endif 3645 #ifdef PMAP_CACHE_VIPT 3646 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3647 struct vm_page *opg; 3648 #ifndef ARM_MMU_EXTENDED 3649 struct pv_entry *pv = NULL; 3650 #endif 3651 #endif 3652 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3653 3654 UVMHIST_FUNC(__func__); 3655 3656 if (pmap_initialized) { 3657 UVMHIST_CALLED(maphist); 3658 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3659 va, pa, prot, flags); 3660 } 3661 3662 pmap_t kpm = pmap_kernel(); 3663 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3664 const size_t l1slot __diagused = l1pte_index(va); 3665 KASSERTMSG(l2b != NULL, 3666 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3667 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3668 kpm->pm_l2[L2_IDX(l1slot)] 3669 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3670 : NULL, 3671 kpm->pm_l2[L2_IDX(l1slot)] 3672 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3673 : NULL); 3674 KASSERT(l2b->l2b_kva != NULL); 3675 3676 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3677 const pt_entry_t opte = *ptep; 3678 3679 if (opte == 0) { 3680 PMAPCOUNT(kenter_mappings); 3681 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3682 } else { 3683 PMAPCOUNT(kenter_remappings); 3684 #ifdef PMAP_CACHE_VIPT 3685 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3686 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3687 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3688 #endif 3689 if (opg && arm_cache_prefer_mask != 0) { 3690 KASSERT(opg != pg); 3691 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3692 KASSERT((flags & PMAP_KMPAGE) == 0); 3693 #ifndef ARM_MMU_EXTENDED 3694 pmap_acquire_page_lock(omd); 3695 pv = pmap_kremove_pg(opg, va); 3696 pmap_release_page_lock(omd); 3697 #endif 3698 } 3699 #endif 3700 if (l2pte_valid_p(opte)) { 3701 #ifdef PMAP_CACHE_VIVT 3702 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3703 #endif 3704 cpu_tlb_flushD_SE(va); 3705 cpu_cpwait(); 3706 } 3707 } 3708 3709 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3710 | ((flags & PMAP_NOCACHE) 3711 ? 0 3712 : ((flags & PMAP_PTE) 3713 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3714 #ifdef ARM_MMU_EXTENDED 3715 if (prot & VM_PROT_EXECUTE) 3716 npte &= ~L2_XS_XN; 3717 #endif 3718 l2pte_set(ptep, npte, opte); 3719 PTE_SYNC(ptep); 3720 3721 if (pg) { 3722 if (flags & PMAP_KMPAGE) { 3723 KASSERT(md->urw_mappings == 0); 3724 KASSERT(md->uro_mappings == 0); 3725 KASSERT(md->krw_mappings == 0); 3726 KASSERT(md->kro_mappings == 0); 3727 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3728 KASSERT(pv == NULL); 3729 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3730 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3731 /* if there is a color conflict, evict from cache. */ 3732 if (pmap_is_page_colored_p(md) 3733 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3734 PMAPCOUNT(vac_color_change); 3735 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3736 } else if (md->pvh_attrs & PVF_MULTCLR) { 3737 /* 3738 * If this page has multiple colors, expunge 3739 * them. 3740 */ 3741 PMAPCOUNT(vac_flush_lots2); 3742 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3743 } 3744 /* 3745 * Since this is a KMPAGE, there can be no contention 3746 * for this page so don't lock it. 3747 */ 3748 md->pvh_attrs &= PAGE_SIZE - 1; 3749 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3750 | (va & arm_cache_prefer_mask); 3751 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3752 md->pvh_attrs |= PVF_KMPAGE; 3753 #endif 3754 atomic_inc_32(&pmap_kmpages); 3755 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3756 } else if (arm_cache_prefer_mask != 0) { 3757 if (pv == NULL) { 3758 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3759 KASSERT(pv != NULL); 3760 } 3761 pmap_acquire_page_lock(md); 3762 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3763 PVF_WIRED | PVF_KENTRY 3764 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3765 if ((prot & VM_PROT_WRITE) 3766 && !(md->pvh_attrs & PVF_NC)) 3767 md->pvh_attrs |= PVF_DIRTY; 3768 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3769 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3770 pmap_release_page_lock(md); 3771 #endif 3772 } 3773 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3774 } else { 3775 if (pv != NULL) 3776 pool_put(&pmap_pv_pool, pv); 3777 #endif 3778 } 3779 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3780 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3781 #endif 3782 if (pmap_initialized) { 3783 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3784 ptep, opte, npte, 0); 3785 } 3786 3787 } 3788 3789 void 3790 pmap_kremove(vaddr_t va, vsize_t len) 3791 { 3792 #ifdef UVMHIST 3793 u_int total_mappings = 0; 3794 #endif 3795 3796 PMAPCOUNT(kenter_unmappings); 3797 3798 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3799 3800 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3801 3802 const vaddr_t eva = va + len; 3803 3804 while (va < eva) { 3805 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3806 if (next_bucket > eva) 3807 next_bucket = eva; 3808 3809 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3810 KDASSERT(l2b != NULL); 3811 3812 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3813 pt_entry_t *ptep = sptep; 3814 u_int mappings = 0; 3815 3816 while (va < next_bucket) { 3817 const pt_entry_t opte = *ptep; 3818 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3819 if (opg != NULL) { 3820 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3821 3822 if (omd->pvh_attrs & PVF_KMPAGE) { 3823 KASSERT(omd->urw_mappings == 0); 3824 KASSERT(omd->uro_mappings == 0); 3825 KASSERT(omd->krw_mappings == 0); 3826 KASSERT(omd->kro_mappings == 0); 3827 omd->pvh_attrs &= ~PVF_KMPAGE; 3828 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3829 if (arm_cache_prefer_mask != 0) { 3830 omd->pvh_attrs &= ~PVF_WRITE; 3831 } 3832 #endif 3833 atomic_dec_32(&pmap_kmpages); 3834 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3835 } else if (arm_cache_prefer_mask != 0) { 3836 pmap_acquire_page_lock(omd); 3837 pool_put(&pmap_pv_pool, 3838 pmap_kremove_pg(opg, va)); 3839 pmap_release_page_lock(omd); 3840 #endif 3841 } 3842 } 3843 if (l2pte_valid_p(opte)) { 3844 #ifdef PMAP_CACHE_VIVT 3845 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3846 #endif 3847 cpu_tlb_flushD_SE(va); 3848 } 3849 if (opte) { 3850 l2pte_reset(ptep); 3851 mappings += PAGE_SIZE / L2_S_SIZE; 3852 } 3853 va += PAGE_SIZE; 3854 ptep += PAGE_SIZE / L2_S_SIZE; 3855 } 3856 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3857 mappings, l2b->l2b_occupancy); 3858 l2b->l2b_occupancy -= mappings; 3859 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3860 #ifdef UVMHIST 3861 total_mappings += mappings; 3862 #endif 3863 } 3864 cpu_cpwait(); 3865 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3866 total_mappings, 0, 0, 0); 3867 } 3868 3869 bool 3870 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3871 { 3872 struct l2_dtable *l2; 3873 pd_entry_t *pdep, pde; 3874 pt_entry_t *ptep, pte; 3875 paddr_t pa; 3876 u_int l1slot; 3877 3878 pmap_acquire_pmap_lock(pm); 3879 3880 l1slot = l1pte_index(va); 3881 pdep = pmap_l1_kva(pm) + l1slot; 3882 pde = *pdep; 3883 3884 if (l1pte_section_p(pde)) { 3885 /* 3886 * These should only happen for pmap_kernel() 3887 */ 3888 KDASSERT(pm == pmap_kernel()); 3889 pmap_release_pmap_lock(pm); 3890 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3891 if (l1pte_supersection_p(pde)) { 3892 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3893 } else 3894 #endif 3895 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3896 } else { 3897 /* 3898 * Note that we can't rely on the validity of the L1 3899 * descriptor as an indication that a mapping exists. 3900 * We have to look it up in the L2 dtable. 3901 */ 3902 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3903 3904 if (l2 == NULL || 3905 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3906 pmap_release_pmap_lock(pm); 3907 return false; 3908 } 3909 3910 pte = ptep[l2pte_index(va)]; 3911 pmap_release_pmap_lock(pm); 3912 3913 if (pte == 0) 3914 return false; 3915 3916 switch (pte & L2_TYPE_MASK) { 3917 case L2_TYPE_L: 3918 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3919 break; 3920 3921 default: 3922 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3923 break; 3924 } 3925 } 3926 3927 if (pap != NULL) 3928 *pap = pa; 3929 3930 return true; 3931 } 3932 3933 void 3934 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3935 { 3936 struct l2_bucket *l2b; 3937 vaddr_t next_bucket; 3938 3939 NPDEBUG(PDB_PROTECT, 3940 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3941 pm, sva, eva, prot)); 3942 3943 if ((prot & VM_PROT_READ) == 0) { 3944 pmap_remove(pm, sva, eva); 3945 return; 3946 } 3947 3948 if (prot & VM_PROT_WRITE) { 3949 /* 3950 * If this is a read->write transition, just ignore it and let 3951 * uvm_fault() take care of it later. 3952 */ 3953 return; 3954 } 3955 3956 pmap_acquire_pmap_lock(pm); 3957 3958 const bool flush = eva - sva >= PAGE_SIZE * 4; 3959 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3960 u_int flags = 0; 3961 3962 while (sva < eva) { 3963 next_bucket = L2_NEXT_BUCKET_VA(sva); 3964 if (next_bucket > eva) 3965 next_bucket = eva; 3966 3967 l2b = pmap_get_l2_bucket(pm, sva); 3968 if (l2b == NULL) { 3969 sva = next_bucket; 3970 continue; 3971 } 3972 3973 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3974 3975 while (sva < next_bucket) { 3976 const pt_entry_t opte = *ptep; 3977 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3978 struct vm_page *pg; 3979 u_int f; 3980 3981 #ifdef PMAP_CACHE_VIVT 3982 /* 3983 * OK, at this point, we know we're doing 3984 * write-protect operation. If the pmap is 3985 * active, write-back the page. 3986 */ 3987 pmap_cache_wbinv_page(pm, sva, false, 3988 PVF_REF | PVF_WRITE); 3989 #endif 3990 3991 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3992 pt_entry_t npte = l2pte_set_readonly(opte); 3993 l2pte_set(ptep, npte, opte); 3994 PTE_SYNC(ptep); 3995 3996 if (pg != NULL) { 3997 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3998 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3999 4000 pmap_acquire_page_lock(md); 4001 f = pmap_modify_pv(md, pa, pm, sva, 4002 clr_mask, 0); 4003 pmap_vac_me_harder(md, pa, pm, sva); 4004 pmap_release_page_lock(md); 4005 } else { 4006 f = PVF_REF | PVF_EXEC; 4007 } 4008 4009 if (flush) { 4010 flags |= f; 4011 } else { 4012 pmap_tlb_flush_SE(pm, sva, f); 4013 } 4014 } 4015 4016 sva += PAGE_SIZE; 4017 ptep += PAGE_SIZE / L2_S_SIZE; 4018 } 4019 } 4020 4021 if (flush) { 4022 if (PV_BEEN_EXECD(flags)) { 4023 pmap_tlb_flushID(pm); 4024 } else if (PV_BEEN_REFD(flags)) { 4025 pmap_tlb_flushD(pm); 4026 } 4027 } 4028 4029 pmap_release_pmap_lock(pm); 4030 } 4031 4032 void 4033 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4034 { 4035 struct l2_bucket *l2b; 4036 pt_entry_t *ptep; 4037 vaddr_t next_bucket; 4038 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4039 4040 NPDEBUG(PDB_EXEC, 4041 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4042 pm, sva, eva)); 4043 4044 pmap_acquire_pmap_lock(pm); 4045 4046 while (sva < eva) { 4047 next_bucket = L2_NEXT_BUCKET_VA(sva); 4048 if (next_bucket > eva) 4049 next_bucket = eva; 4050 4051 l2b = pmap_get_l2_bucket(pm, sva); 4052 if (l2b == NULL) { 4053 sva = next_bucket; 4054 continue; 4055 } 4056 4057 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4058 sva < next_bucket; 4059 sva += page_size, 4060 ptep += PAGE_SIZE / L2_S_SIZE, 4061 page_size = PAGE_SIZE) { 4062 if (l2pte_valid_p(*ptep)) { 4063 cpu_icache_sync_range(sva, 4064 min(page_size, eva - sva)); 4065 } 4066 } 4067 } 4068 4069 pmap_release_pmap_lock(pm); 4070 } 4071 4072 void 4073 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4074 { 4075 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4076 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4077 4078 NPDEBUG(PDB_PROTECT, 4079 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4080 md, pa, prot)); 4081 4082 switch(prot) { 4083 case VM_PROT_READ|VM_PROT_WRITE: 4084 #if defined(ARM_MMU_EXTENDED) 4085 pmap_acquire_page_lock(md); 4086 pmap_clearbit(md, pa, PVF_EXEC); 4087 pmap_release_page_lock(md); 4088 break; 4089 #endif 4090 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4091 break; 4092 4093 case VM_PROT_READ: 4094 #if defined(ARM_MMU_EXTENDED) 4095 pmap_acquire_page_lock(md); 4096 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4097 pmap_release_page_lock(md); 4098 break; 4099 #endif 4100 case VM_PROT_READ|VM_PROT_EXECUTE: 4101 pmap_acquire_page_lock(md); 4102 pmap_clearbit(md, pa, PVF_WRITE); 4103 pmap_release_page_lock(md); 4104 break; 4105 4106 default: 4107 pmap_page_remove(md, pa); 4108 break; 4109 } 4110 } 4111 4112 /* 4113 * pmap_clear_modify: 4114 * 4115 * Clear the "modified" attribute for a page. 4116 */ 4117 bool 4118 pmap_clear_modify(struct vm_page *pg) 4119 { 4120 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4121 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4122 bool rv; 4123 4124 pmap_acquire_page_lock(md); 4125 4126 if (md->pvh_attrs & PVF_MOD) { 4127 rv = true; 4128 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4129 /* 4130 * If we are going to clear the modified bit and there are 4131 * no other modified bits set, flush the page to memory and 4132 * mark it clean. 4133 */ 4134 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4135 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4136 #endif 4137 pmap_clearbit(md, pa, PVF_MOD); 4138 } else { 4139 rv = false; 4140 } 4141 pmap_release_page_lock(md); 4142 4143 return rv; 4144 } 4145 4146 /* 4147 * pmap_clear_reference: 4148 * 4149 * Clear the "referenced" attribute for a page. 4150 */ 4151 bool 4152 pmap_clear_reference(struct vm_page *pg) 4153 { 4154 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4155 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4156 bool rv; 4157 4158 pmap_acquire_page_lock(md); 4159 4160 if (md->pvh_attrs & PVF_REF) { 4161 rv = true; 4162 pmap_clearbit(md, pa, PVF_REF); 4163 } else { 4164 rv = false; 4165 } 4166 pmap_release_page_lock(md); 4167 4168 return rv; 4169 } 4170 4171 /* 4172 * pmap_is_modified: 4173 * 4174 * Test if a page has the "modified" attribute. 4175 */ 4176 /* See <arm/arm32/pmap.h> */ 4177 4178 /* 4179 * pmap_is_referenced: 4180 * 4181 * Test if a page has the "referenced" attribute. 4182 */ 4183 /* See <arm/arm32/pmap.h> */ 4184 4185 #if defined(ARM_MMU_EXTENDED) && 0 4186 int 4187 pmap_prefetchabt_fixup(void *v) 4188 { 4189 struct trapframe * const tf = v; 4190 vaddr_t va = trunc_page(tf->tf_pc); 4191 int rv = ABORT_FIXUP_FAILED; 4192 4193 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4194 return rv; 4195 4196 kpreempt_disable(); 4197 pmap_t pm = curcpu()->ci_pmap_cur; 4198 const size_t l1slot = l1pte_index(va); 4199 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4200 if (l2 == NULL) 4201 goto out; 4202 4203 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4204 if (l2b->l2b_kva == NULL) 4205 goto out; 4206 4207 /* 4208 * Check the PTE itself. 4209 */ 4210 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4211 const pt_entry_t opte = *ptep; 4212 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4213 goto out; 4214 4215 paddr_t pa = l2pte_pa(pte); 4216 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4217 KASSERT(pg != NULL); 4218 4219 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4220 4221 pmap_acquire_page_lock(md); 4222 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4223 KASSERT(pv != NULL); 4224 4225 if (PV_IS_EXEC_P(pv->pv_flags)) { 4226 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4227 pmap_syncicache_page(md, pa); 4228 } 4229 rv = ABORT_FIXUP_RETURN; 4230 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4231 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4232 } 4233 pmap_release_page_lock(md); 4234 4235 out: 4236 kpreempt_enable(); 4237 return rv; 4238 } 4239 #endif 4240 4241 int 4242 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4243 { 4244 struct l2_dtable *l2; 4245 struct l2_bucket *l2b; 4246 paddr_t pa; 4247 const size_t l1slot = l1pte_index(va); 4248 int rv = 0; 4249 4250 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4251 4252 va = trunc_page(va); 4253 4254 KASSERT(!user || (pm != pmap_kernel())); 4255 4256 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4257 pm, va, ftype, user); 4258 #ifdef ARM_MMU_EXTENDED 4259 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4260 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4261 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4262 #endif 4263 4264 pmap_acquire_pmap_lock(pm); 4265 4266 /* 4267 * If there is no l2_dtable for this address, then the process 4268 * has no business accessing it. 4269 * 4270 * Note: This will catch userland processes trying to access 4271 * kernel addresses. 4272 */ 4273 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4274 if (l2 == NULL) { 4275 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4276 goto out; 4277 } 4278 4279 /* 4280 * Likewise if there is no L2 descriptor table 4281 */ 4282 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4283 if (l2b->l2b_kva == NULL) { 4284 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4285 goto out; 4286 } 4287 4288 /* 4289 * Check the PTE itself. 4290 */ 4291 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4292 pt_entry_t const opte = *ptep; 4293 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4294 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4295 goto out; 4296 } 4297 4298 #ifndef ARM_HAS_VBAR 4299 /* 4300 * Catch a userland access to the vector page mapped at 0x0 4301 */ 4302 if (user && (opte & L2_S_PROT_U) == 0) { 4303 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4304 goto out; 4305 } 4306 #endif 4307 4308 pa = l2pte_pa(opte); 4309 4310 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4311 /* 4312 * This looks like a good candidate for "page modified" 4313 * emulation... 4314 */ 4315 struct pv_entry *pv; 4316 struct vm_page *pg; 4317 4318 /* Extract the physical address of the page */ 4319 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4320 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4321 goto out; 4322 } 4323 4324 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4325 4326 /* Get the current flags for this page. */ 4327 pmap_acquire_page_lock(md); 4328 pv = pmap_find_pv(md, pm, va); 4329 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4330 pmap_release_page_lock(md); 4331 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4332 goto out; 4333 } 4334 4335 /* 4336 * Do the flags say this page is writable? If not then it 4337 * is a genuine write fault. If yes then the write fault is 4338 * our fault as we did not reflect the write access in the 4339 * PTE. Now we know a write has occurred we can correct this 4340 * and also set the modified bit 4341 */ 4342 if ((pv->pv_flags & PVF_WRITE) == 0) { 4343 pmap_release_page_lock(md); 4344 goto out; 4345 } 4346 4347 md->pvh_attrs |= PVF_REF | PVF_MOD; 4348 pv->pv_flags |= PVF_REF | PVF_MOD; 4349 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4350 /* 4351 * If there are cacheable mappings for this page, mark it dirty. 4352 */ 4353 if ((md->pvh_attrs & PVF_NC) == 0) 4354 md->pvh_attrs |= PVF_DIRTY; 4355 #endif 4356 #ifdef ARM_MMU_EXTENDED 4357 if (md->pvh_attrs & PVF_EXEC) { 4358 md->pvh_attrs &= ~PVF_EXEC; 4359 PMAPCOUNT(exec_discarded_modfixup); 4360 } 4361 #endif 4362 pmap_release_page_lock(md); 4363 4364 /* 4365 * Re-enable write permissions for the page. No need to call 4366 * pmap_vac_me_harder(), since this is just a 4367 * modified-emulation fault, and the PVF_WRITE bit isn't 4368 * changing. We've already set the cacheable bits based on 4369 * the assumption that we can write to this page. 4370 */ 4371 const pt_entry_t npte = 4372 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4373 #ifdef ARM_MMU_EXTENDED 4374 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4375 #endif 4376 | 0; 4377 l2pte_set(ptep, npte, opte); 4378 PTE_SYNC(ptep); 4379 PMAPCOUNT(fixup_mod); 4380 rv = 1; 4381 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4382 opte, npte, 0, 0); 4383 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4384 /* 4385 * This looks like a good candidate for "page referenced" 4386 * emulation. 4387 */ 4388 struct vm_page *pg; 4389 4390 /* Extract the physical address of the page */ 4391 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4392 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4393 goto out; 4394 } 4395 4396 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4397 4398 /* Get the current flags for this page. */ 4399 pmap_acquire_page_lock(md); 4400 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4401 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4402 pmap_release_page_lock(md); 4403 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4404 goto out; 4405 } 4406 4407 md->pvh_attrs |= PVF_REF; 4408 pv->pv_flags |= PVF_REF; 4409 4410 pt_entry_t npte = 4411 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4412 #ifdef ARM_MMU_EXTENDED 4413 if (pm != pmap_kernel()) { 4414 npte |= L2_XS_nG; 4415 } 4416 /* 4417 * If we got called from prefetch abort, then ftype will have 4418 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4419 * the PTE. 4420 */ 4421 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4422 /* 4423 * Is this a mapping of an executable page? 4424 */ 4425 if ((pv->pv_flags & PVF_EXEC) == 0) { 4426 pmap_release_page_lock(md); 4427 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4428 0, 0, 0, 0); 4429 goto out; 4430 } 4431 /* 4432 * If we haven't synced the page, do so now. 4433 */ 4434 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4435 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4436 pa, 0, 0, 0); 4437 pmap_syncicache_page(md, pa); 4438 PMAPCOUNT(fixup_exec); 4439 } 4440 npte &= ~L2_XS_XN; 4441 } 4442 #endif /* ARM_MMU_EXTENDED */ 4443 pmap_release_page_lock(md); 4444 l2pte_set(ptep, npte, opte); 4445 PTE_SYNC(ptep); 4446 PMAPCOUNT(fixup_ref); 4447 rv = 1; 4448 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4449 opte, npte, 0, 0); 4450 #ifdef ARM_MMU_EXTENDED 4451 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4452 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4453 if (pg == NULL) { 4454 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4455 goto out; 4456 } 4457 4458 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4459 4460 /* Get the current flags for this page. */ 4461 pmap_acquire_page_lock(md); 4462 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4463 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4464 pmap_release_page_lock(md); 4465 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4466 goto out; 4467 } 4468 4469 /* 4470 * If we haven't synced the page, do so now. 4471 */ 4472 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4473 UVMHIST_LOG(maphist, "syncicache page #%#x", 4474 pa, 0, 0, 0); 4475 pmap_syncicache_page(md, pa); 4476 } 4477 pmap_release_page_lock(md); 4478 /* 4479 * Turn off no-execute. 4480 */ 4481 KASSERT(opte & L2_XS_nG); 4482 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4483 PTE_SYNC(ptep); 4484 rv = 1; 4485 PMAPCOUNT(fixup_exec); 4486 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4487 opte, opte & ~L2_XS_XN, 0, 0); 4488 #endif 4489 } 4490 4491 #ifndef ARM_MMU_EXTENDED 4492 /* 4493 * We know there is a valid mapping here, so simply 4494 * fix up the L1 if necessary. 4495 */ 4496 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4497 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4498 if (*pdep != pde) { 4499 l1pte_setone(pdep, pde); 4500 PTE_SYNC(pdep); 4501 rv = 1; 4502 PMAPCOUNT(fixup_pdes); 4503 } 4504 #endif 4505 4506 #ifdef CPU_SA110 4507 /* 4508 * There are bugs in the rev K SA110. This is a check for one 4509 * of them. 4510 */ 4511 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4512 curcpu()->ci_arm_cpurev < 3) { 4513 /* Always current pmap */ 4514 if (l2pte_valid_p(opte)) { 4515 extern int kernel_debug; 4516 if (kernel_debug & 1) { 4517 struct proc *p = curlwp->l_proc; 4518 printf("prefetch_abort: page is already " 4519 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4520 printf("prefetch_abort: pc=%08lx proc=%p " 4521 "process=%s\n", va, p, p->p_comm); 4522 printf("prefetch_abort: far=%08x fs=%x\n", 4523 cpu_faultaddress(), cpu_faultstatus()); 4524 } 4525 #ifdef DDB 4526 if (kernel_debug & 2) 4527 Debugger(); 4528 #endif 4529 rv = 1; 4530 } 4531 } 4532 #endif /* CPU_SA110 */ 4533 4534 #ifndef ARM_MMU_EXTENDED 4535 /* 4536 * If 'rv == 0' at this point, it generally indicates that there is a 4537 * stale TLB entry for the faulting address. That might be due to a 4538 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4539 */ 4540 if (rv == 0 4541 && pm->pm_l1->l1_domain_use_count == 1 4542 && pmap_needs_pte_sync == 0) { 4543 pmap_needs_pte_sync = 1; 4544 PTE_SYNC(ptep); 4545 PMAPCOUNT(fixup_ptesync); 4546 rv = 1; 4547 } 4548 #endif 4549 4550 #if defined(DEBUG) || 1 4551 /* 4552 * If 'rv == 0' at this point, it generally indicates that there is a 4553 * stale TLB entry for the faulting address. This happens when two or 4554 * more processes are sharing an L1. Since we don't flush the TLB on 4555 * a context switch between such processes, we can take domain faults 4556 * for mappings which exist at the same VA in both processes. EVEN IF 4557 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4558 * example. 4559 * 4560 * This is extremely likely to happen if pmap_enter() updated the L1 4561 * entry for a recently entered mapping. In this case, the TLB is 4562 * flushed for the new mapping, but there may still be TLB entries for 4563 * other mappings belonging to other processes in the 1MB range 4564 * covered by the L1 entry. 4565 * 4566 * Since 'rv == 0', we know that the L1 already contains the correct 4567 * value, so the fault must be due to a stale TLB entry. 4568 * 4569 * Since we always need to flush the TLB anyway in the case where we 4570 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4571 * stale TLB entries dynamically. 4572 * 4573 * However, the above condition can ONLY happen if the current L1 is 4574 * being shared. If it happens when the L1 is unshared, it indicates 4575 * that other parts of the pmap are not doing their job WRT managing 4576 * the TLB. 4577 */ 4578 if (rv == 0 4579 #ifndef ARM_MMU_EXTENDED 4580 && pm->pm_l1->l1_domain_use_count == 1 4581 #endif 4582 && true) { 4583 #ifdef DEBUG 4584 extern int last_fault_code; 4585 #else 4586 int last_fault_code = ftype & VM_PROT_EXECUTE 4587 ? armreg_ifsr_read() 4588 : armreg_dfsr_read(); 4589 #endif 4590 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4591 pm, va, ftype); 4592 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4593 l2, l2b, ptep, opte); 4594 4595 #ifndef ARM_MMU_EXTENDED 4596 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4597 pdep, pde, last_fault_code); 4598 #else 4599 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4600 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4601 armreg_ttbcr_read()); 4602 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4603 last_fault_code, curcpu()->ci_pmap_cur, 4604 curcpu()->ci_pmap_asid_cur, 4605 armreg_contextidr_read(), armreg_dacr_read()); 4606 #ifdef _ARM_ARCH_7 4607 if (ftype & VM_PROT_WRITE) 4608 armreg_ats1cuw_write(va); 4609 else 4610 armreg_ats1cur_write(va); 4611 arm_isb(); 4612 printf("fixup: par %#x\n", armreg_par_read()); 4613 #endif 4614 #endif 4615 #ifdef DDB 4616 extern int kernel_debug; 4617 4618 if (kernel_debug & 2) { 4619 pmap_release_pmap_lock(pm); 4620 #ifdef UVMHIST 4621 KERNHIST_DUMP(maphist); 4622 #endif 4623 cpu_Debugger(); 4624 pmap_acquire_pmap_lock(pm); 4625 } 4626 #endif 4627 } 4628 #endif 4629 4630 pmap_tlb_flush_SE(pm, va, 4631 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4632 4633 rv = 1; 4634 4635 out: 4636 pmap_release_pmap_lock(pm); 4637 4638 return (rv); 4639 } 4640 4641 /* 4642 * Routine: pmap_procwr 4643 * 4644 * Function: 4645 * Synchronize caches corresponding to [addr, addr+len) in p. 4646 * 4647 */ 4648 void 4649 pmap_procwr(struct proc *p, vaddr_t va, int len) 4650 { 4651 /* We only need to do anything if it is the current process. */ 4652 if (p == curproc) 4653 cpu_icache_sync_range(va, len); 4654 } 4655 4656 /* 4657 * Routine: pmap_unwire 4658 * Function: Clear the wired attribute for a map/virtual-address pair. 4659 * 4660 * In/out conditions: 4661 * The mapping must already exist in the pmap. 4662 */ 4663 void 4664 pmap_unwire(pmap_t pm, vaddr_t va) 4665 { 4666 struct l2_bucket *l2b; 4667 pt_entry_t *ptep, pte; 4668 struct vm_page *pg; 4669 paddr_t pa; 4670 4671 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4672 4673 pmap_acquire_pmap_lock(pm); 4674 4675 l2b = pmap_get_l2_bucket(pm, va); 4676 KDASSERT(l2b != NULL); 4677 4678 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4679 pte = *ptep; 4680 4681 /* Extract the physical address of the page */ 4682 pa = l2pte_pa(pte); 4683 4684 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4685 /* Update the wired bit in the pv entry for this page. */ 4686 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4687 4688 pmap_acquire_page_lock(md); 4689 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4690 pmap_release_page_lock(md); 4691 } 4692 4693 pmap_release_pmap_lock(pm); 4694 } 4695 4696 void 4697 pmap_activate(struct lwp *l) 4698 { 4699 struct cpu_info * const ci = curcpu(); 4700 extern int block_userspace_access; 4701 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4702 #ifdef ARM_MMU_EXTENDED 4703 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4704 #endif 4705 4706 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4707 4708 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4709 4710 /* 4711 * If activating a non-current lwp or the current lwp is 4712 * already active, just return. 4713 */ 4714 if (false 4715 || l != curlwp 4716 #ifdef ARM_MMU_EXTENDED 4717 || (ci->ci_pmap_cur == npm && 4718 (npm == pmap_kernel() 4719 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4720 #else 4721 || npm->pm_activated == true 4722 #endif 4723 || false) { 4724 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4725 return; 4726 } 4727 4728 #ifndef ARM_MMU_EXTENDED 4729 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4730 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4731 4732 /* 4733 * If TTB and DACR are unchanged, short-circuit all the 4734 * TLB/cache management stuff. 4735 */ 4736 pmap_t opm = ci->ci_lastlwp 4737 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4738 : NULL; 4739 if (opm != NULL) { 4740 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4741 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4742 4743 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4744 goto all_done; 4745 } 4746 #endif /* !ARM_MMU_EXTENDED */ 4747 4748 PMAPCOUNT(activations); 4749 block_userspace_access = 1; 4750 4751 #ifndef ARM_MMU_EXTENDED 4752 /* 4753 * If switching to a user vmspace which is different to the 4754 * most recent one, and the most recent one is potentially 4755 * live in the cache, we must write-back and invalidate the 4756 * entire cache. 4757 */ 4758 pmap_t rpm = ci->ci_pmap_lastuser; 4759 #endif 4760 4761 /* 4762 * XXXSCW: There's a corner case here which can leave turds in the cache as 4763 * reported in kern/41058. They're probably left over during tear-down and 4764 * switching away from an exiting process. Until the root cause is identified 4765 * and fixed, zap the cache when switching pmaps. This will result in a few 4766 * unnecessary cache flushes, but that's better than silently corrupting data. 4767 */ 4768 #ifndef ARM_MMU_EXTENDED 4769 #if 0 4770 if (npm != pmap_kernel() && rpm && npm != rpm && 4771 rpm->pm_cstate.cs_cache) { 4772 rpm->pm_cstate.cs_cache = 0; 4773 #ifdef PMAP_CACHE_VIVT 4774 cpu_idcache_wbinv_all(); 4775 #endif 4776 } 4777 #else 4778 if (rpm) { 4779 rpm->pm_cstate.cs_cache = 0; 4780 if (npm == pmap_kernel()) 4781 ci->ci_pmap_lastuser = NULL; 4782 #ifdef PMAP_CACHE_VIVT 4783 cpu_idcache_wbinv_all(); 4784 #endif 4785 } 4786 #endif 4787 4788 /* No interrupts while we frob the TTB/DACR */ 4789 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4790 #endif /* !ARM_MMU_EXTENDED */ 4791 4792 #ifndef ARM_HAS_VBAR 4793 /* 4794 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4795 * entry corresponding to 'vector_page' in the incoming L1 table 4796 * before switching to it otherwise subsequent interrupts/exceptions 4797 * (including domain faults!) will jump into hyperspace. 4798 */ 4799 if (npm->pm_pl1vec != NULL) { 4800 cpu_tlb_flushID_SE((u_int)vector_page); 4801 cpu_cpwait(); 4802 *npm->pm_pl1vec = npm->pm_l1vec; 4803 PTE_SYNC(npm->pm_pl1vec); 4804 } 4805 #endif 4806 4807 #ifdef ARM_MMU_EXTENDED 4808 /* 4809 * Assume that TTBR1 has only global mappings and TTBR0 only has 4810 * non-global mappings. To prevent speculation from doing evil things 4811 * we disable translation table walks using TTBR0 before setting the 4812 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4813 * walks are reenabled. 4814 */ 4815 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4816 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4817 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4818 arm_isb(); 4819 pmap_tlb_asid_acquire(npm, l); 4820 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4821 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4822 /* 4823 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4824 * been updated. 4825 */ 4826 arm_isb(); 4827 if (npm != pmap_kernel()) { 4828 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4829 } 4830 cpu_cpwait(); 4831 ci->ci_pmap_asid_cur = pai->pai_asid; 4832 #else 4833 cpu_domains(ndacr); 4834 if (npm == pmap_kernel() || npm == rpm) { 4835 /* 4836 * Switching to a kernel thread, or back to the 4837 * same user vmspace as before... Simply update 4838 * the TTB (no TLB flush required) 4839 */ 4840 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4841 cpu_cpwait(); 4842 } else { 4843 /* 4844 * Otherwise, update TTB and flush TLB 4845 */ 4846 cpu_context_switch(npm->pm_l1->l1_physaddr); 4847 if (rpm != NULL) 4848 rpm->pm_cstate.cs_tlb = 0; 4849 } 4850 4851 restore_interrupts(oldirqstate); 4852 #endif /* ARM_MMU_EXTENDED */ 4853 4854 block_userspace_access = 0; 4855 4856 #ifndef ARM_MMU_EXTENDED 4857 all_done: 4858 /* 4859 * The new pmap is resident. Make sure it's marked 4860 * as resident in the cache/TLB. 4861 */ 4862 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4863 if (npm != pmap_kernel()) 4864 ci->ci_pmap_lastuser = npm; 4865 4866 /* The old pmap is not longer active */ 4867 if (opm != npm) { 4868 if (opm != NULL) 4869 opm->pm_activated = false; 4870 4871 /* But the new one is */ 4872 npm->pm_activated = true; 4873 } 4874 #endif 4875 ci->ci_pmap_cur = npm; 4876 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4877 } 4878 4879 void 4880 pmap_deactivate(struct lwp *l) 4881 { 4882 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4883 4884 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4885 4886 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4887 4888 #ifdef ARM_MMU_EXTENDED 4889 kpreempt_disable(); 4890 struct cpu_info * const ci = curcpu(); 4891 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4892 /* 4893 * Disable translation table walks from TTBR0 while no pmap has been 4894 * activated. 4895 */ 4896 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4897 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4898 arm_isb(); 4899 pmap_tlb_asid_deactivate(pm); 4900 cpu_setttb(pmap_kernel()->pm_l1_pa, pai->pai_asid); 4901 ci->ci_pmap_cur = pmap_kernel(); 4902 kpreempt_enable(); 4903 #else 4904 /* 4905 * If the process is exiting, make sure pmap_activate() does 4906 * a full MMU context-switch and cache flush, which we might 4907 * otherwise skip. See PR port-arm/38950. 4908 */ 4909 if (l->l_proc->p_sflag & PS_WEXIT) 4910 curcpu()->ci_lastlwp = NULL; 4911 4912 pm->pm_activated = false; 4913 #endif 4914 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4915 } 4916 4917 void 4918 pmap_update(pmap_t pm) 4919 { 4920 4921 if (pm->pm_remove_all) { 4922 #ifdef ARM_MMU_EXTENDED 4923 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4924 /* 4925 * Finish up the pmap_remove_all() optimisation by flushing 4926 * all our ASIDs. 4927 */ 4928 pmap_tlb_asid_release_all(pm); 4929 #else 4930 /* 4931 * Finish up the pmap_remove_all() optimisation by flushing 4932 * the TLB. 4933 */ 4934 pmap_tlb_flushID(pm); 4935 #endif 4936 pm->pm_remove_all = false; 4937 } 4938 4939 #ifdef ARM_MMU_EXTENDED 4940 4941 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4942 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4943 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4944 PMAP_COUNT(shootdown_ipis); 4945 } 4946 #endif 4947 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4948 #else 4949 if (pmap_is_current(pm)) { 4950 /* 4951 * If we're dealing with a current userland pmap, move its L1 4952 * to the end of the LRU. 4953 */ 4954 if (pm != pmap_kernel()) 4955 pmap_use_l1(pm); 4956 4957 /* 4958 * We can assume we're done with frobbing the cache/tlb for 4959 * now. Make sure any future pmap ops don't skip cache/tlb 4960 * flushes. 4961 */ 4962 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4963 } 4964 #endif 4965 4966 PMAPCOUNT(updates); 4967 4968 /* 4969 * make sure TLB/cache operations have completed. 4970 */ 4971 cpu_cpwait(); 4972 } 4973 4974 void 4975 pmap_remove_all(pmap_t pm) 4976 { 4977 4978 /* 4979 * The vmspace described by this pmap is about to be torn down. 4980 * Until pmap_update() is called, UVM will only make calls 4981 * to pmap_remove(). We can make life much simpler by flushing 4982 * the cache now, and deferring TLB invalidation to pmap_update(). 4983 */ 4984 #ifdef PMAP_CACHE_VIVT 4985 pmap_cache_wbinv_all(pm, PVF_EXEC); 4986 #endif 4987 pm->pm_remove_all = true; 4988 } 4989 4990 /* 4991 * Retire the given physical map from service. 4992 * Should only be called if the map contains no valid mappings. 4993 */ 4994 void 4995 pmap_destroy(pmap_t pm) 4996 { 4997 u_int count; 4998 4999 if (pm == NULL) 5000 return; 5001 5002 if (pm->pm_remove_all) { 5003 pmap_tlb_flushID(pm); 5004 pm->pm_remove_all = false; 5005 } 5006 5007 /* 5008 * Drop reference count 5009 */ 5010 mutex_enter(pm->pm_lock); 5011 count = --pm->pm_obj.uo_refs; 5012 mutex_exit(pm->pm_lock); 5013 if (count > 0) { 5014 #ifndef ARM_MMU_EXTENDED 5015 if (pmap_is_current(pm)) { 5016 if (pm != pmap_kernel()) 5017 pmap_use_l1(pm); 5018 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5019 } 5020 #endif 5021 return; 5022 } 5023 5024 /* 5025 * reference count is zero, free pmap resources and then free pmap. 5026 */ 5027 5028 #ifndef ARM_HAS_VBAR 5029 if (vector_page < KERNEL_BASE) { 5030 KDASSERT(!pmap_is_current(pm)); 5031 5032 /* Remove the vector page mapping */ 5033 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5034 pmap_update(pm); 5035 } 5036 #endif 5037 5038 LIST_REMOVE(pm, pm_list); 5039 5040 pmap_free_l1(pm); 5041 5042 #ifdef ARM_MMU_EXTENDED 5043 #ifdef MULTIPROCESSOR 5044 kcpuset_destroy(pm->pm_active); 5045 kcpuset_destroy(pm->pm_onproc); 5046 #endif 5047 #else 5048 struct cpu_info * const ci = curcpu(); 5049 if (ci->ci_pmap_lastuser == pm) 5050 ci->ci_pmap_lastuser = NULL; 5051 #endif 5052 5053 uvm_obj_destroy(&pm->pm_obj, false); 5054 mutex_destroy(&pm->pm_obj_lock); 5055 pool_cache_put(&pmap_cache, pm); 5056 } 5057 5058 5059 /* 5060 * void pmap_reference(pmap_t pm) 5061 * 5062 * Add a reference to the specified pmap. 5063 */ 5064 void 5065 pmap_reference(pmap_t pm) 5066 { 5067 5068 if (pm == NULL) 5069 return; 5070 5071 #ifndef ARM_MMU_EXTENDED 5072 pmap_use_l1(pm); 5073 #endif 5074 5075 mutex_enter(pm->pm_lock); 5076 pm->pm_obj.uo_refs++; 5077 mutex_exit(pm->pm_lock); 5078 } 5079 5080 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5081 5082 static struct evcnt pmap_prefer_nochange_ev = 5083 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5084 static struct evcnt pmap_prefer_change_ev = 5085 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5086 5087 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5088 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5089 5090 void 5091 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5092 { 5093 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5094 vaddr_t va = *vap; 5095 vaddr_t diff = (hint - va) & mask; 5096 if (diff == 0) { 5097 pmap_prefer_nochange_ev.ev_count++; 5098 } else { 5099 pmap_prefer_change_ev.ev_count++; 5100 if (__predict_false(td)) 5101 va -= mask + 1; 5102 *vap = va + diff; 5103 } 5104 } 5105 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5106 5107 /* 5108 * pmap_zero_page() 5109 * 5110 * Zero a given physical page by mapping it at a page hook point. 5111 * In doing the zero page op, the page we zero is mapped cachable, as with 5112 * StrongARM accesses to non-cached pages are non-burst making writing 5113 * _any_ bulk data very slow. 5114 */ 5115 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5116 void 5117 pmap_zero_page_generic(paddr_t pa) 5118 { 5119 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5120 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5121 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5122 #endif 5123 #if defined(PMAP_CACHE_VIPT) 5124 /* Choose the last page color it had, if any */ 5125 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5126 #else 5127 const vsize_t va_offset = 0; 5128 #endif 5129 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5130 /* 5131 * Is this page mapped at its natural color? 5132 * If we have all of memory mapped, then just convert PA to VA. 5133 */ 5134 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5135 || va_offset == (pa & arm_cache_prefer_mask); 5136 const vaddr_t vdstp = okcolor 5137 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5138 : cpu_cdstp(va_offset); 5139 #else 5140 const bool okcolor = false; 5141 const vaddr_t vdstp = cpu_cdstp(va_offset); 5142 #endif 5143 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5144 5145 5146 #ifdef DEBUG 5147 if (!SLIST_EMPTY(&md->pvh_list)) 5148 panic("pmap_zero_page: page has mappings"); 5149 #endif 5150 5151 KDASSERT((pa & PGOFSET) == 0); 5152 5153 if (!okcolor) { 5154 /* 5155 * Hook in the page, zero it, and purge the cache for that 5156 * zeroed page. Invalidate the TLB as needed. 5157 */ 5158 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5159 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5160 l2pte_set(ptep, npte, 0); 5161 PTE_SYNC(ptep); 5162 cpu_tlb_flushD_SE(vdstp); 5163 cpu_cpwait(); 5164 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5165 && !defined(ARM_MMU_EXTENDED) 5166 /* 5167 * If we are direct-mapped and our color isn't ok, then before 5168 * we bzero the page invalidate its contents from the cache and 5169 * reset the color to its natural color. 5170 */ 5171 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5172 md->pvh_attrs &= ~arm_cache_prefer_mask; 5173 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5174 #endif 5175 } 5176 bzero_page(vdstp); 5177 if (!okcolor) { 5178 /* 5179 * Unmap the page. 5180 */ 5181 l2pte_reset(ptep); 5182 PTE_SYNC(ptep); 5183 cpu_tlb_flushD_SE(vdstp); 5184 #ifdef PMAP_CACHE_VIVT 5185 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5186 #endif 5187 } 5188 #ifdef PMAP_CACHE_VIPT 5189 /* 5190 * This page is now cache resident so it now has a page color. 5191 * Any contents have been obliterated so clear the EXEC flag. 5192 */ 5193 #ifndef ARM_MMU_EXTENDED 5194 if (!pmap_is_page_colored_p(md)) { 5195 PMAPCOUNT(vac_color_new); 5196 md->pvh_attrs |= PVF_COLORED; 5197 } 5198 md->pvh_attrs |= PVF_DIRTY; 5199 #endif 5200 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5201 md->pvh_attrs &= ~PVF_EXEC; 5202 PMAPCOUNT(exec_discarded_zero); 5203 } 5204 #endif 5205 } 5206 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5207 5208 #if ARM_MMU_XSCALE == 1 5209 void 5210 pmap_zero_page_xscale(paddr_t pa) 5211 { 5212 #ifdef DEBUG 5213 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5214 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5215 5216 if (!SLIST_EMPTY(&md->pvh_list)) 5217 panic("pmap_zero_page: page has mappings"); 5218 #endif 5219 5220 KDASSERT((pa & PGOFSET) == 0); 5221 5222 /* 5223 * Hook in the page, zero it, and purge the cache for that 5224 * zeroed page. Invalidate the TLB as needed. 5225 */ 5226 5227 pt_entry_t npte = L2_S_PROTO | pa | 5228 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5229 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5230 l2pte_set(cdst_pte, npte, 0); 5231 PTE_SYNC(cdst_pte); 5232 cpu_tlb_flushD_SE(cdstp); 5233 cpu_cpwait(); 5234 bzero_page(cdstp); 5235 xscale_cache_clean_minidata(); 5236 l2pte_reset(cdst_pte); 5237 PTE_SYNC(cdst_pte); 5238 } 5239 #endif /* ARM_MMU_XSCALE == 1 */ 5240 5241 /* pmap_pageidlezero() 5242 * 5243 * The same as above, except that we assume that the page is not 5244 * mapped. This means we never have to flush the cache first. Called 5245 * from the idle loop. 5246 */ 5247 bool 5248 pmap_pageidlezero(paddr_t pa) 5249 { 5250 bool rv = true; 5251 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5252 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5253 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5254 #endif 5255 #ifdef PMAP_CACHE_VIPT 5256 /* Choose the last page color it had, if any */ 5257 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5258 #else 5259 const vsize_t va_offset = 0; 5260 #endif 5261 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5262 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5263 || va_offset == (pa & arm_cache_prefer_mask); 5264 const vaddr_t vdstp = okcolor 5265 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5266 : cpu_cdstp(va_offset); 5267 #else 5268 const bool okcolor = false; 5269 const vaddr_t vdstp = cpu_cdstp(va_offset); 5270 #endif 5271 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5272 5273 5274 #ifdef DEBUG 5275 if (!SLIST_EMPTY(&md->pvh_list)) 5276 panic("pmap_pageidlezero: page has mappings"); 5277 #endif 5278 5279 KDASSERT((pa & PGOFSET) == 0); 5280 5281 if (!okcolor) { 5282 /* 5283 * Hook in the page, zero it, and purge the cache for that 5284 * zeroed page. Invalidate the TLB as needed. 5285 */ 5286 const pt_entry_t npte = L2_S_PROTO | pa | 5287 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5288 l2pte_set(ptep, npte, 0); 5289 PTE_SYNC(ptep); 5290 cpu_tlb_flushD_SE(vdstp); 5291 cpu_cpwait(); 5292 } 5293 5294 uint64_t *ptr = (uint64_t *)vdstp; 5295 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5296 if (sched_curcpu_runnable_p() != 0) { 5297 /* 5298 * A process has become ready. Abort now, 5299 * so we don't keep it waiting while we 5300 * do slow memory access to finish this 5301 * page. 5302 */ 5303 rv = false; 5304 break; 5305 } 5306 *ptr++ = 0; 5307 } 5308 5309 #ifdef PMAP_CACHE_VIVT 5310 if (rv) 5311 /* 5312 * if we aborted we'll rezero this page again later so don't 5313 * purge it unless we finished it 5314 */ 5315 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5316 #elif defined(PMAP_CACHE_VIPT) 5317 /* 5318 * This page is now cache resident so it now has a page color. 5319 * Any contents have been obliterated so clear the EXEC flag. 5320 */ 5321 #ifndef ARM_MMU_EXTENDED 5322 if (!pmap_is_page_colored_p(md)) { 5323 PMAPCOUNT(vac_color_new); 5324 md->pvh_attrs |= PVF_COLORED; 5325 } 5326 #endif 5327 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5328 md->pvh_attrs &= ~PVF_EXEC; 5329 PMAPCOUNT(exec_discarded_zero); 5330 } 5331 #endif 5332 /* 5333 * Unmap the page. 5334 */ 5335 if (!okcolor) { 5336 l2pte_reset(ptep); 5337 PTE_SYNC(ptep); 5338 cpu_tlb_flushD_SE(vdstp); 5339 } 5340 5341 return rv; 5342 } 5343 5344 /* 5345 * pmap_copy_page() 5346 * 5347 * Copy one physical page into another, by mapping the pages into 5348 * hook points. The same comment regarding cachability as in 5349 * pmap_zero_page also applies here. 5350 */ 5351 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5352 void 5353 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5354 { 5355 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5356 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5357 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5358 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5359 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5360 #endif 5361 #ifdef PMAP_CACHE_VIPT 5362 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5363 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5364 #else 5365 const vsize_t src_va_offset = 0; 5366 const vsize_t dst_va_offset = 0; 5367 #endif 5368 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5369 /* 5370 * Is this page mapped at its natural color? 5371 * If we have all of memory mapped, then just convert PA to VA. 5372 */ 5373 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5374 || src_va_offset == (src & arm_cache_prefer_mask); 5375 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5376 || dst_va_offset == (dst & arm_cache_prefer_mask); 5377 const vaddr_t vsrcp = src_okcolor 5378 ? pmap_direct_mapped_phys(src, &src_okcolor, 5379 cpu_csrcp(src_va_offset)) 5380 : cpu_csrcp(src_va_offset); 5381 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5382 cpu_cdstp(dst_va_offset)); 5383 #else 5384 const bool src_okcolor = false; 5385 const bool dst_okcolor = false; 5386 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5387 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5388 #endif 5389 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5390 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5391 5392 #ifdef DEBUG 5393 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5394 panic("pmap_copy_page: dst page has mappings"); 5395 #endif 5396 5397 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5398 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5399 #endif 5400 KDASSERT((src & PGOFSET) == 0); 5401 KDASSERT((dst & PGOFSET) == 0); 5402 5403 /* 5404 * Clean the source page. Hold the source page's lock for 5405 * the duration of the copy so that no other mappings can 5406 * be created while we have a potentially aliased mapping. 5407 */ 5408 #ifdef PMAP_CACHE_VIVT 5409 pmap_acquire_page_lock(src_md); 5410 (void) pmap_clean_page(src_md, true); 5411 pmap_release_page_lock(src_md); 5412 #endif 5413 5414 /* 5415 * Map the pages into the page hook points, copy them, and purge 5416 * the cache for the appropriate page. Invalidate the TLB 5417 * as required. 5418 */ 5419 if (!src_okcolor) { 5420 const pt_entry_t nsrc_pte = L2_S_PROTO 5421 | src 5422 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5423 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5424 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5425 | pte_l2_s_cache_mode 5426 #endif 5427 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5428 l2pte_set(src_ptep, nsrc_pte, 0); 5429 PTE_SYNC(src_ptep); 5430 cpu_tlb_flushD_SE(vsrcp); 5431 cpu_cpwait(); 5432 } 5433 if (!dst_okcolor) { 5434 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5435 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5436 l2pte_set(dst_ptep, ndst_pte, 0); 5437 PTE_SYNC(dst_ptep); 5438 cpu_tlb_flushD_SE(vdstp); 5439 cpu_cpwait(); 5440 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5441 /* 5442 * If we are direct-mapped and our color isn't ok, then before 5443 * we bcopy to the new page invalidate its contents from the 5444 * cache and reset its color to its natural color. 5445 */ 5446 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5447 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5448 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5449 #endif 5450 } 5451 bcopy_page(vsrcp, vdstp); 5452 #ifdef PMAP_CACHE_VIVT 5453 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5454 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5455 #endif 5456 /* 5457 * Unmap the pages. 5458 */ 5459 if (!src_okcolor) { 5460 l2pte_reset(src_ptep); 5461 PTE_SYNC(src_ptep); 5462 cpu_tlb_flushD_SE(vsrcp); 5463 cpu_cpwait(); 5464 } 5465 if (!dst_okcolor) { 5466 l2pte_reset(dst_ptep); 5467 PTE_SYNC(dst_ptep); 5468 cpu_tlb_flushD_SE(vdstp); 5469 cpu_cpwait(); 5470 } 5471 #ifdef PMAP_CACHE_VIPT 5472 /* 5473 * Now that the destination page is in the cache, mark it as colored. 5474 * If this was an exec page, discard it. 5475 */ 5476 pmap_acquire_page_lock(dst_md); 5477 #ifndef ARM_MMU_EXTENDED 5478 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5479 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5480 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5481 } 5482 if (!pmap_is_page_colored_p(dst_md)) { 5483 PMAPCOUNT(vac_color_new); 5484 dst_md->pvh_attrs |= PVF_COLORED; 5485 } 5486 dst_md->pvh_attrs |= PVF_DIRTY; 5487 #endif 5488 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5489 dst_md->pvh_attrs &= ~PVF_EXEC; 5490 PMAPCOUNT(exec_discarded_copy); 5491 } 5492 pmap_release_page_lock(dst_md); 5493 #endif 5494 } 5495 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5496 5497 #if ARM_MMU_XSCALE == 1 5498 void 5499 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5500 { 5501 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5502 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5503 #ifdef DEBUG 5504 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5505 5506 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5507 panic("pmap_copy_page: dst page has mappings"); 5508 #endif 5509 5510 KDASSERT((src & PGOFSET) == 0); 5511 KDASSERT((dst & PGOFSET) == 0); 5512 5513 /* 5514 * Clean the source page. Hold the source page's lock for 5515 * the duration of the copy so that no other mappings can 5516 * be created while we have a potentially aliased mapping. 5517 */ 5518 #ifdef PMAP_CACHE_VIVT 5519 pmap_acquire_page_lock(src_md); 5520 (void) pmap_clean_page(src_md, true); 5521 pmap_release_page_lock(src_md); 5522 #endif 5523 5524 /* 5525 * Map the pages into the page hook points, copy them, and purge 5526 * the cache for the appropriate page. Invalidate the TLB 5527 * as required. 5528 */ 5529 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5530 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5531 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5532 l2pte_set(csrc_pte, nsrc_pte, 0); 5533 PTE_SYNC(csrc_pte); 5534 5535 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5536 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5537 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5538 l2pte_set(cdst_pte, ndst_pte, 0); 5539 PTE_SYNC(cdst_pte); 5540 5541 cpu_tlb_flushD_SE(csrcp); 5542 cpu_tlb_flushD_SE(cdstp); 5543 cpu_cpwait(); 5544 bcopy_page(csrcp, cdstp); 5545 xscale_cache_clean_minidata(); 5546 l2pte_reset(csrc_pte); 5547 l2pte_reset(cdst_pte); 5548 PTE_SYNC(csrc_pte); 5549 PTE_SYNC(cdst_pte); 5550 } 5551 #endif /* ARM_MMU_XSCALE == 1 */ 5552 5553 /* 5554 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5555 * 5556 * Return the start and end addresses of the kernel's virtual space. 5557 * These values are setup in pmap_bootstrap and are updated as pages 5558 * are allocated. 5559 */ 5560 void 5561 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5562 { 5563 *start = virtual_avail; 5564 *end = virtual_end; 5565 } 5566 5567 /* 5568 * Helper function for pmap_grow_l2_bucket() 5569 */ 5570 static inline int 5571 pmap_grow_map(vaddr_t va, paddr_t *pap) 5572 { 5573 paddr_t pa; 5574 5575 if (uvm.page_init_done == false) { 5576 #ifdef PMAP_STEAL_MEMORY 5577 pv_addr_t pv; 5578 pmap_boot_pagealloc(PAGE_SIZE, 5579 #ifdef PMAP_CACHE_VIPT 5580 arm_cache_prefer_mask, 5581 va & arm_cache_prefer_mask, 5582 #else 5583 0, 0, 5584 #endif 5585 &pv); 5586 pa = pv.pv_pa; 5587 #else 5588 if (uvm_page_physget(&pa) == false) 5589 return (1); 5590 #endif /* PMAP_STEAL_MEMORY */ 5591 } else { 5592 struct vm_page *pg; 5593 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5594 if (pg == NULL) 5595 return (1); 5596 pa = VM_PAGE_TO_PHYS(pg); 5597 /* 5598 * This new page must not have any mappings. Enter it via 5599 * pmap_kenter_pa and let that routine do the hard work. 5600 */ 5601 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5602 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5603 pmap_kenter_pa(va, pa, 5604 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5605 } 5606 5607 if (pap) 5608 *pap = pa; 5609 5610 PMAPCOUNT(pt_mappings); 5611 #ifdef DEBUG 5612 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5613 KDASSERT(l2b != NULL); 5614 5615 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5616 const pt_entry_t opte = *ptep; 5617 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5618 #endif 5619 memset((void *)va, 0, PAGE_SIZE); 5620 return (0); 5621 } 5622 5623 /* 5624 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5625 * used by pmap_growkernel(). 5626 */ 5627 static inline struct l2_bucket * 5628 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5629 { 5630 struct l2_dtable *l2; 5631 struct l2_bucket *l2b; 5632 u_short l1slot; 5633 vaddr_t nva; 5634 5635 l1slot = l1pte_index(va); 5636 5637 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5638 /* 5639 * No mapping at this address, as there is 5640 * no entry in the L1 table. 5641 * Need to allocate a new l2_dtable. 5642 */ 5643 nva = pmap_kernel_l2dtable_kva; 5644 if ((nva & PGOFSET) == 0) { 5645 /* 5646 * Need to allocate a backing page 5647 */ 5648 if (pmap_grow_map(nva, NULL)) 5649 return (NULL); 5650 } 5651 5652 l2 = (struct l2_dtable *)nva; 5653 nva += sizeof(struct l2_dtable); 5654 5655 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5656 /* 5657 * The new l2_dtable straddles a page boundary. 5658 * Map in another page to cover it. 5659 */ 5660 if (pmap_grow_map(nva, NULL)) 5661 return (NULL); 5662 } 5663 5664 pmap_kernel_l2dtable_kva = nva; 5665 5666 /* 5667 * Link it into the parent pmap 5668 */ 5669 pm->pm_l2[L2_IDX(l1slot)] = l2; 5670 } 5671 5672 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5673 5674 /* 5675 * Fetch pointer to the L2 page table associated with the address. 5676 */ 5677 if (l2b->l2b_kva == NULL) { 5678 pt_entry_t *ptep; 5679 5680 /* 5681 * No L2 page table has been allocated. Chances are, this 5682 * is because we just allocated the l2_dtable, above. 5683 */ 5684 nva = pmap_kernel_l2ptp_kva; 5685 ptep = (pt_entry_t *)nva; 5686 if ((nva & PGOFSET) == 0) { 5687 /* 5688 * Need to allocate a backing page 5689 */ 5690 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5691 return (NULL); 5692 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5693 } 5694 5695 l2->l2_occupancy++; 5696 l2b->l2b_kva = ptep; 5697 l2b->l2b_l1slot = l1slot; 5698 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5699 5700 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5701 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5702 } 5703 5704 return (l2b); 5705 } 5706 5707 vaddr_t 5708 pmap_growkernel(vaddr_t maxkvaddr) 5709 { 5710 pmap_t kpm = pmap_kernel(); 5711 #ifndef ARM_MMU_EXTENDED 5712 struct l1_ttable *l1; 5713 #endif 5714 int s; 5715 5716 if (maxkvaddr <= pmap_curmaxkvaddr) 5717 goto out; /* we are OK */ 5718 5719 NPDEBUG(PDB_GROWKERN, 5720 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5721 pmap_curmaxkvaddr, maxkvaddr)); 5722 5723 KDASSERT(maxkvaddr <= virtual_end); 5724 5725 /* 5726 * whoops! we need to add kernel PTPs 5727 */ 5728 5729 s = splhigh(); /* to be safe */ 5730 mutex_enter(kpm->pm_lock); 5731 5732 /* Map 1MB at a time */ 5733 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5734 #ifdef ARM_MMU_EXTENDED 5735 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5736 pd_entry_t *pdep = spdep; 5737 #endif 5738 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5739 #ifdef ARM_MMU_EXTENDED 5740 pdep++, 5741 #endif 5742 l1slot++) { 5743 struct l2_bucket *l2b = 5744 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5745 KASSERT(l2b != NULL); 5746 5747 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5748 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5749 #ifdef ARM_MMU_EXTENDED 5750 l1pte_setone(pdep, npde); 5751 #else 5752 /* Distribute new L1 entry to all other L1s */ 5753 SLIST_FOREACH(l1, &l1_list, l1_link) { 5754 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5755 l1pte_setone(pdep, npde); 5756 PDE_SYNC(pdep); 5757 } 5758 #endif 5759 } 5760 #ifdef ARM_MMU_EXTENDED 5761 PDE_SYNC_RANGE(spdep, pdep - spdep); 5762 #endif 5763 5764 #ifdef PMAP_CACHE_VIVT 5765 /* 5766 * flush out the cache, expensive but growkernel will happen so 5767 * rarely 5768 */ 5769 cpu_dcache_wbinv_all(); 5770 cpu_tlb_flushD(); 5771 cpu_cpwait(); 5772 #endif 5773 5774 mutex_exit(kpm->pm_lock); 5775 splx(s); 5776 5777 out: 5778 return (pmap_curmaxkvaddr); 5779 } 5780 5781 /************************ Utility routines ****************************/ 5782 5783 #ifndef ARM_HAS_VBAR 5784 /* 5785 * vector_page_setprot: 5786 * 5787 * Manipulate the protection of the vector page. 5788 */ 5789 void 5790 vector_page_setprot(int prot) 5791 { 5792 struct l2_bucket *l2b; 5793 pt_entry_t *ptep; 5794 5795 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5796 /* 5797 * If we are using VBAR to use the vectors in the kernel, then it's 5798 * already mapped in the kernel text so no need to anything here. 5799 */ 5800 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5801 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5802 return; 5803 } 5804 #endif 5805 5806 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5807 KASSERT(l2b != NULL); 5808 5809 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5810 5811 const pt_entry_t opte = *ptep; 5812 #ifdef ARM_MMU_EXTENDED 5813 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5814 | L2_S_PROT(PTE_KERNEL, prot); 5815 #else 5816 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5817 | L2_S_PROT(PTE_KERNEL, prot); 5818 #endif 5819 l2pte_set(ptep, npte, opte); 5820 PTE_SYNC(ptep); 5821 cpu_tlb_flushD_SE(vector_page); 5822 cpu_cpwait(); 5823 } 5824 #endif 5825 5826 /* 5827 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5828 * Returns true if the mapping exists, else false. 5829 * 5830 * NOTE: This function is only used by a couple of arm-specific modules. 5831 * It is not safe to take any pmap locks here, since we could be right 5832 * in the middle of debugging the pmap anyway... 5833 * 5834 * It is possible for this routine to return false even though a valid 5835 * mapping does exist. This is because we don't lock, so the metadata 5836 * state may be inconsistent. 5837 * 5838 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5839 * a "section" mapping. 5840 */ 5841 bool 5842 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5843 { 5844 struct l2_dtable *l2; 5845 pd_entry_t *pdep, pde; 5846 pt_entry_t *ptep; 5847 u_short l1slot; 5848 5849 if (pm->pm_l1 == NULL) 5850 return false; 5851 5852 l1slot = l1pte_index(va); 5853 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5854 pde = *pdep; 5855 5856 if (l1pte_section_p(pde)) { 5857 *ptp = NULL; 5858 return true; 5859 } 5860 5861 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5862 if (l2 == NULL || 5863 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5864 return false; 5865 } 5866 5867 *ptp = &ptep[l2pte_index(va)]; 5868 return true; 5869 } 5870 5871 bool 5872 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5873 { 5874 5875 if (pm->pm_l1 == NULL) 5876 return false; 5877 5878 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5879 5880 return true; 5881 } 5882 5883 /************************ Bootstrapping routines ****************************/ 5884 5885 #ifndef ARM_MMU_EXTENDED 5886 static void 5887 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5888 { 5889 int i; 5890 5891 l1->l1_kva = l1pt; 5892 l1->l1_domain_use_count = 0; 5893 l1->l1_domain_first = 0; 5894 5895 for (i = 0; i < PMAP_DOMAINS; i++) 5896 l1->l1_domain_free[i] = i + 1; 5897 5898 /* 5899 * Copy the kernel's L1 entries to each new L1. 5900 */ 5901 if (pmap_initialized) 5902 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5903 5904 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5905 &l1->l1_physaddr) == false) 5906 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5907 5908 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5909 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5910 } 5911 #endif /* !ARM_MMU_EXTENDED */ 5912 5913 /* 5914 * pmap_bootstrap() is called from the board-specific initarm() routine 5915 * once the kernel L1/L2 descriptors tables have been set up. 5916 * 5917 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5918 * spread over a number of disparate files/functions. 5919 * 5920 * We are passed the following parameters 5921 * - kernel_l1pt 5922 * This is a pointer to the base of the kernel's L1 translation table. 5923 * - vstart 5924 * 1MB-aligned start of managed kernel virtual memory. 5925 * - vend 5926 * 1MB-aligned end of managed kernel virtual memory. 5927 * 5928 * We use the first parameter to build the metadata (struct l1_ttable and 5929 * struct l2_dtable) necessary to track kernel mappings. 5930 */ 5931 #define PMAP_STATIC_L2_SIZE 16 5932 void 5933 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5934 { 5935 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5936 #ifndef ARM_MMU_EXTENDED 5937 static struct l1_ttable static_l1; 5938 struct l1_ttable *l1 = &static_l1; 5939 #endif 5940 struct l2_dtable *l2; 5941 struct l2_bucket *l2b; 5942 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5943 pmap_t pm = pmap_kernel(); 5944 pt_entry_t *ptep; 5945 paddr_t pa; 5946 vsize_t size; 5947 int nptes, l2idx, l2next = 0; 5948 5949 #ifdef ARM_MMU_EXTENDED 5950 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5951 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5952 #endif 5953 5954 #ifdef VERBOSE_INIT_ARM 5955 printf("kpm "); 5956 #endif 5957 /* 5958 * Initialise the kernel pmap object 5959 */ 5960 curcpu()->ci_pmap_cur = pm; 5961 #ifdef ARM_MMU_EXTENDED 5962 pm->pm_l1 = l1pt; 5963 pm->pm_l1_pa = kernel_l1pt.pv_pa; 5964 #ifdef VERBOSE_INIT_ARM 5965 printf("tlb0 "); 5966 #endif 5967 pmap_tlb_info_init(&pmap_tlb0_info); 5968 #ifdef MULTIPROCESSOR 5969 #ifdef VERBOSE_INIT_ARM 5970 printf("kcpusets "); 5971 #endif 5972 pm->pm_onproc = kcpuset_running; 5973 pm->pm_active = kcpuset_running; 5974 #endif 5975 #else 5976 pm->pm_l1 = l1; 5977 #endif 5978 5979 #ifdef VERBOSE_INIT_ARM 5980 printf("locks "); 5981 #endif 5982 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5983 if (arm_cache_prefer_mask != 0) { 5984 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 5985 } else { 5986 #endif 5987 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 5988 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5989 } 5990 #endif 5991 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5992 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5993 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5994 5995 #ifdef VERBOSE_INIT_ARM 5996 printf("l1pt "); 5997 #endif 5998 /* 5999 * Scan the L1 translation table created by initarm() and create 6000 * the required metadata for all valid mappings found in it. 6001 */ 6002 for (size_t l1slot = 0; 6003 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6004 l1slot++) { 6005 pd_entry_t pde = l1pt[l1slot]; 6006 6007 /* 6008 * We're only interested in Coarse mappings. 6009 * pmap_extract() can deal with section mappings without 6010 * recourse to checking L2 metadata. 6011 */ 6012 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6013 continue; 6014 6015 /* 6016 * Lookup the KVA of this L2 descriptor table 6017 */ 6018 pa = l1pte_pa(pde); 6019 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6020 if (ptep == NULL) { 6021 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6022 (u_int)l1slot << L1_S_SHIFT, pa); 6023 } 6024 6025 /* 6026 * Fetch the associated L2 metadata structure. 6027 * Allocate a new one if necessary. 6028 */ 6029 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6030 if (l2next == PMAP_STATIC_L2_SIZE) 6031 panic("pmap_bootstrap: out of static L2s"); 6032 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6033 } 6034 6035 /* 6036 * One more L1 slot tracked... 6037 */ 6038 l2->l2_occupancy++; 6039 6040 /* 6041 * Fill in the details of the L2 descriptor in the 6042 * appropriate bucket. 6043 */ 6044 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6045 l2b->l2b_kva = ptep; 6046 l2b->l2b_pa = pa; 6047 l2b->l2b_l1slot = l1slot; 6048 6049 /* 6050 * Establish an initial occupancy count for this descriptor 6051 */ 6052 for (l2idx = 0; 6053 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6054 l2idx++) { 6055 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6056 l2b->l2b_occupancy++; 6057 } 6058 } 6059 6060 /* 6061 * Make sure the descriptor itself has the correct cache mode. 6062 * If not, fix it, but whine about the problem. Port-meisters 6063 * should consider this a clue to fix up their initarm() 6064 * function. :) 6065 */ 6066 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6067 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6068 "L2 pte @ %p\n", ptep); 6069 } 6070 } 6071 6072 #ifdef VERBOSE_INIT_ARM 6073 printf("cache(l1pt) "); 6074 #endif 6075 /* 6076 * Ensure the primary (kernel) L1 has the correct cache mode for 6077 * a page table. Bitch if it is not correctly set. 6078 */ 6079 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6080 L1_TABLE_SIZE / L2_S_SIZE)) { 6081 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6082 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6083 } 6084 6085 #ifdef PMAP_CACHE_VIVT 6086 cpu_dcache_wbinv_all(); 6087 cpu_tlb_flushID(); 6088 cpu_cpwait(); 6089 #endif 6090 6091 /* 6092 * now we allocate the "special" VAs which are used for tmp mappings 6093 * by the pmap (and other modules). we allocate the VAs by advancing 6094 * virtual_avail (note that there are no pages mapped at these VAs). 6095 * 6096 * Managed KVM space start from wherever initarm() tells us. 6097 */ 6098 virtual_avail = vstart; 6099 virtual_end = vend; 6100 6101 #ifdef VERBOSE_INIT_ARM 6102 printf("specials "); 6103 #endif 6104 #ifdef PMAP_CACHE_VIPT 6105 /* 6106 * If we have a VIPT cache, we need one page/pte per possible alias 6107 * page so we won't violate cache aliasing rules. 6108 */ 6109 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6110 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6111 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6112 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6113 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6114 } 6115 #else 6116 nptes = PAGE_SIZE / L2_S_SIZE; 6117 #endif 6118 #ifdef MULTIPROCESSOR 6119 cnptes = nptes; 6120 nptes *= arm_cpu_max; 6121 #endif 6122 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6123 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6124 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6125 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6126 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6127 if (msgbufaddr == NULL) { 6128 pmap_alloc_specials(&virtual_avail, 6129 round_page(MSGBUFSIZE) / PAGE_SIZE, 6130 (void *)&msgbufaddr, NULL); 6131 } 6132 6133 /* 6134 * Allocate a range of kernel virtual address space to be used 6135 * for L2 descriptor tables and metadata allocation in 6136 * pmap_growkernel(). 6137 */ 6138 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6139 pmap_alloc_specials(&virtual_avail, 6140 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6141 &pmap_kernel_l2ptp_kva, NULL); 6142 6143 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6144 pmap_alloc_specials(&virtual_avail, 6145 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6146 &pmap_kernel_l2dtable_kva, NULL); 6147 6148 #ifndef ARM_MMU_EXTENDED 6149 /* 6150 * init the static-global locks and global pmap list. 6151 */ 6152 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6153 6154 /* 6155 * We can now initialise the first L1's metadata. 6156 */ 6157 SLIST_INIT(&l1_list); 6158 TAILQ_INIT(&l1_lru_list); 6159 pmap_init_l1(l1, l1pt); 6160 #endif /* ARM_MMU_EXTENDED */ 6161 6162 #ifndef ARM_HAS_VBAR 6163 /* Set up vector page L1 details, if necessary */ 6164 if (vector_page < KERNEL_BASE) { 6165 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6166 l2b = pmap_get_l2_bucket(pm, vector_page); 6167 KDASSERT(l2b != NULL); 6168 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6169 L1_C_DOM(pmap_domain(pm)); 6170 } else 6171 pm->pm_pl1vec = NULL; 6172 #endif 6173 6174 #ifdef VERBOSE_INIT_ARM 6175 printf("pools "); 6176 #endif 6177 /* 6178 * Initialize the pmap cache 6179 */ 6180 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6181 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6182 LIST_INIT(&pmap_pmaps); 6183 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6184 6185 /* 6186 * Initialize the pv pool. 6187 */ 6188 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6189 &pmap_bootstrap_pv_allocator, IPL_NONE); 6190 6191 /* 6192 * Initialize the L2 dtable pool and cache. 6193 */ 6194 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6195 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6196 6197 /* 6198 * Initialise the L2 descriptor table pool and cache 6199 */ 6200 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6201 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6202 pmap_l2ptp_ctor, NULL, NULL); 6203 6204 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6205 6206 cpu_dcache_wbinv_all(); 6207 } 6208 6209 static bool 6210 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6211 { 6212 #ifdef ARM_MMU_EXTENDED 6213 return false; 6214 #else 6215 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6216 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6217 return false; 6218 6219 const vaddr_t eva = va + nptes * PAGE_SIZE; 6220 int rv = 0; 6221 6222 while (va < eva) { 6223 /* 6224 * Make sure the descriptor itself has the correct cache mode 6225 */ 6226 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6227 pd_entry_t pde = *pdep; 6228 6229 if (l1pte_section_p(pde)) { 6230 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6231 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6232 *pdep = (pde & ~L1_S_CACHE_MASK) | 6233 pte_l1_s_cache_mode_pt; 6234 PDE_SYNC(pdep); 6235 cpu_dcache_wbinv_range((vaddr_t)pdep, 6236 sizeof(*pdep)); 6237 rv = 1; 6238 } 6239 return rv; 6240 } 6241 vaddr_t pa = l1pte_pa(pde); 6242 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6243 if (ptep == NULL) 6244 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6245 6246 ptep += l2pte_index(va); 6247 const pt_entry_t opte = *ptep; 6248 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6249 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6250 | pte_l2_s_cache_mode_pt; 6251 l2pte_set(ptep, npte, opte); 6252 PTE_SYNC(ptep); 6253 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6254 rv = 1; 6255 } 6256 va += PAGE_SIZE; 6257 } 6258 6259 return (rv); 6260 #endif 6261 } 6262 6263 static void 6264 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6265 { 6266 vaddr_t va = *availp; 6267 struct l2_bucket *l2b; 6268 6269 if (ptep) { 6270 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6271 if (l2b == NULL) 6272 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6273 6274 if (ptep) 6275 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6276 } 6277 6278 *vap = va; 6279 *availp = va + (PAGE_SIZE * pages); 6280 } 6281 6282 void 6283 pmap_init(void) 6284 { 6285 6286 /* 6287 * Set the available memory vars - These do not map to real memory 6288 * addresses and cannot as the physical memory is fragmented. 6289 * They are used by ps for %mem calculations. 6290 * One could argue whether this should be the entire memory or just 6291 * the memory that is useable in a user process. 6292 */ 6293 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6294 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6295 6296 /* 6297 * Now we need to free enough pv_entry structures to allow us to get 6298 * the kmem_map/kmem_object allocated and inited (done after this 6299 * function is finished). to do this we allocate one bootstrap page out 6300 * of kernel_map and use it to provide an initial pool of pv_entry 6301 * structures. we never free this page. 6302 */ 6303 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6304 6305 #ifdef ARM_MMU_EXTENDED 6306 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6307 #endif 6308 6309 pmap_initialized = true; 6310 } 6311 6312 static vaddr_t last_bootstrap_page = 0; 6313 static void *free_bootstrap_pages = NULL; 6314 6315 static void * 6316 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6317 { 6318 extern void *pool_page_alloc(struct pool *, int); 6319 vaddr_t new_page; 6320 void *rv; 6321 6322 if (pmap_initialized) 6323 return (pool_page_alloc(pp, flags)); 6324 6325 if (free_bootstrap_pages) { 6326 rv = free_bootstrap_pages; 6327 free_bootstrap_pages = *((void **)rv); 6328 return (rv); 6329 } 6330 6331 KASSERT(kernel_map != NULL); 6332 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6333 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6334 6335 KASSERT(new_page > last_bootstrap_page); 6336 last_bootstrap_page = new_page; 6337 return ((void *)new_page); 6338 } 6339 6340 static void 6341 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6342 { 6343 extern void pool_page_free(struct pool *, void *); 6344 6345 if ((vaddr_t)v <= last_bootstrap_page) { 6346 *((void **)v) = free_bootstrap_pages; 6347 free_bootstrap_pages = v; 6348 return; 6349 } 6350 6351 if (pmap_initialized) { 6352 pool_page_free(pp, v); 6353 return; 6354 } 6355 } 6356 6357 /* 6358 * pmap_postinit() 6359 * 6360 * This routine is called after the vm and kmem subsystems have been 6361 * initialised. This allows the pmap code to perform any initialisation 6362 * that can only be done one the memory allocation is in place. 6363 */ 6364 void 6365 pmap_postinit(void) 6366 { 6367 #ifndef ARM_MMU_EXTENDED 6368 extern paddr_t physical_start, physical_end; 6369 struct l1_ttable *l1; 6370 struct pglist plist; 6371 struct vm_page *m; 6372 pd_entry_t *pdep; 6373 vaddr_t va, eva; 6374 u_int loop, needed; 6375 int error; 6376 #endif 6377 6378 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6379 pool_cache_setlowat(&pmap_l2dtable_cache, 6380 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6381 6382 #ifndef ARM_MMU_EXTENDED 6383 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6384 needed -= 1; 6385 6386 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6387 6388 for (loop = 0; loop < needed; loop++, l1++) { 6389 /* Allocate a L1 page table */ 6390 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6391 if (va == 0) 6392 panic("Cannot allocate L1 KVM"); 6393 6394 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6395 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6396 if (error) 6397 panic("Cannot allocate L1 physical pages"); 6398 6399 m = TAILQ_FIRST(&plist); 6400 eva = va + L1_TABLE_SIZE; 6401 pdep = (pd_entry_t *)va; 6402 6403 while (m && va < eva) { 6404 paddr_t pa = VM_PAGE_TO_PHYS(m); 6405 6406 pmap_kenter_pa(va, pa, 6407 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6408 6409 va += PAGE_SIZE; 6410 m = TAILQ_NEXT(m, pageq.queue); 6411 } 6412 6413 #ifdef DIAGNOSTIC 6414 if (m) 6415 panic("pmap_alloc_l1pt: pglist not empty"); 6416 #endif /* DIAGNOSTIC */ 6417 6418 pmap_init_l1(l1, pdep); 6419 } 6420 6421 #ifdef DEBUG 6422 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6423 needed); 6424 #endif 6425 #endif /* !ARM_MMU_EXTENDED */ 6426 } 6427 6428 /* 6429 * Note that the following routines are used by board-specific initialisation 6430 * code to configure the initial kernel page tables. 6431 * 6432 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6433 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6434 * behaviour of the old pmap, and provides an easy migration path for 6435 * initial bring-up of the new pmap on existing ports. Fortunately, 6436 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6437 * will be deprecated. 6438 * 6439 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6440 * tables. 6441 */ 6442 6443 /* 6444 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6445 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6446 * find them as necessary. 6447 * 6448 * Note that the data on this list MUST remain valid after initarm() returns, 6449 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6450 */ 6451 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6452 6453 static vaddr_t 6454 kernel_pt_lookup(paddr_t pa) 6455 { 6456 pv_addr_t *pv; 6457 6458 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6459 if (pv->pv_pa == (pa & ~PGOFSET)) 6460 return (pv->pv_va | (pa & PGOFSET)); 6461 } 6462 return (0); 6463 } 6464 6465 /* 6466 * pmap_map_section: 6467 * 6468 * Create a single section mapping. 6469 */ 6470 void 6471 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6472 { 6473 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6474 const size_t l1slot = l1pte_index(va); 6475 pd_entry_t fl; 6476 6477 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6478 6479 switch (cache) { 6480 case PTE_NOCACHE: 6481 default: 6482 fl = 0; 6483 break; 6484 6485 case PTE_CACHE: 6486 fl = pte_l1_s_cache_mode; 6487 break; 6488 6489 case PTE_PAGETABLE: 6490 fl = pte_l1_s_cache_mode_pt; 6491 break; 6492 } 6493 6494 const pd_entry_t npde = L1_S_PROTO | pa | 6495 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6496 l1pte_setone(pdep + l1slot, npde); 6497 PDE_SYNC(pdep + l1slot); 6498 } 6499 6500 /* 6501 * pmap_map_entry: 6502 * 6503 * Create a single page mapping. 6504 */ 6505 void 6506 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6507 { 6508 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6509 const size_t l1slot = l1pte_index(va); 6510 pt_entry_t npte; 6511 pt_entry_t *ptep; 6512 6513 KASSERT(((va | pa) & PGOFSET) == 0); 6514 6515 switch (cache) { 6516 case PTE_NOCACHE: 6517 default: 6518 npte = 0; 6519 break; 6520 6521 case PTE_CACHE: 6522 npte = pte_l2_s_cache_mode; 6523 break; 6524 6525 case PTE_PAGETABLE: 6526 npte = pte_l2_s_cache_mode_pt; 6527 break; 6528 } 6529 6530 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6531 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6532 6533 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6534 if (ptep == NULL) 6535 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6536 6537 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6538 #ifdef ARM_MMU_EXTENDED 6539 if (prot & VM_PROT_EXECUTE) { 6540 npte &= ~L2_XS_XN; 6541 } 6542 #endif 6543 ptep += l2pte_index(va); 6544 l2pte_set(ptep, npte, 0); 6545 PTE_SYNC(ptep); 6546 } 6547 6548 /* 6549 * pmap_link_l2pt: 6550 * 6551 * Link the L2 page table specified by "l2pv" into the L1 6552 * page table at the slot for "va". 6553 */ 6554 void 6555 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6556 { 6557 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6558 6559 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6560 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6561 6562 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6563 | l2pv->pv_pa; 6564 6565 l1pte_set(pdep, npde); 6566 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6567 6568 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6569 } 6570 6571 /* 6572 * pmap_map_chunk: 6573 * 6574 * Map a chunk of memory using the most efficient mappings 6575 * possible (section, large page, small page) into the 6576 * provided L1 and L2 tables at the specified virtual address. 6577 */ 6578 vsize_t 6579 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6580 int prot, int cache) 6581 { 6582 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6583 pt_entry_t f1, f2s, f2l; 6584 vsize_t resid; 6585 6586 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6587 6588 if (l1pt == 0) 6589 panic("pmap_map_chunk: no L1 table provided"); 6590 6591 #ifdef VERBOSE_INIT_ARM 6592 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6593 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6594 #endif 6595 6596 switch (cache) { 6597 case PTE_NOCACHE: 6598 default: 6599 f1 = 0; 6600 f2l = 0; 6601 f2s = 0; 6602 break; 6603 6604 case PTE_CACHE: 6605 f1 = pte_l1_s_cache_mode; 6606 f2l = pte_l2_l_cache_mode; 6607 f2s = pte_l2_s_cache_mode; 6608 break; 6609 6610 case PTE_PAGETABLE: 6611 f1 = pte_l1_s_cache_mode_pt; 6612 f2l = pte_l2_l_cache_mode_pt; 6613 f2s = pte_l2_s_cache_mode_pt; 6614 break; 6615 } 6616 6617 size = resid; 6618 6619 while (resid > 0) { 6620 const size_t l1slot = l1pte_index(va); 6621 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6622 /* See if we can use a supersection mapping. */ 6623 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6624 /* Supersection are always domain 0 */ 6625 const pd_entry_t npde = L1_SS_PROTO | pa 6626 #ifdef ARM_MMU_EXTENDED_XXX 6627 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6628 #endif 6629 #ifdef ARM_MMU_EXTENDED 6630 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6631 #endif 6632 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6633 #ifdef VERBOSE_INIT_ARM 6634 printf("sS"); 6635 #endif 6636 l1pte_set(&pdep[l1slot], npde); 6637 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6638 va += L1_SS_SIZE; 6639 pa += L1_SS_SIZE; 6640 resid -= L1_SS_SIZE; 6641 continue; 6642 } 6643 #endif 6644 /* See if we can use a section mapping. */ 6645 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6646 const pd_entry_t npde = L1_S_PROTO | pa 6647 #ifdef ARM_MMU_EXTENDED_XXX 6648 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6649 #endif 6650 #ifdef ARM_MMU_EXTENDED 6651 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6652 #endif 6653 | L1_S_PROT(PTE_KERNEL, prot) | f1 6654 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6655 #ifdef VERBOSE_INIT_ARM 6656 printf("S"); 6657 #endif 6658 l1pte_set(&pdep[l1slot], npde); 6659 PDE_SYNC(&pdep[l1slot]); 6660 va += L1_S_SIZE; 6661 pa += L1_S_SIZE; 6662 resid -= L1_S_SIZE; 6663 continue; 6664 } 6665 6666 /* 6667 * Ok, we're going to use an L2 table. Make sure 6668 * one is actually in the corresponding L1 slot 6669 * for the current VA. 6670 */ 6671 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6672 panic("%s: no L2 table for VA %#lx", __func__, va); 6673 6674 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6675 if (ptep == NULL) 6676 panic("%s: can't find L2 table for VA %#lx", __func__, 6677 va); 6678 6679 ptep += l2pte_index(va); 6680 6681 /* See if we can use a L2 large page mapping. */ 6682 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6683 const pt_entry_t npte = L2_L_PROTO | pa 6684 #ifdef ARM_MMU_EXTENDED_XXX 6685 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6686 #endif 6687 #ifdef ARM_MMU_EXTENDED 6688 | (va & 0x80000000 ? 0 : L2_XS_nG) 6689 #endif 6690 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6691 #ifdef VERBOSE_INIT_ARM 6692 printf("L"); 6693 #endif 6694 l2pte_set(ptep, npte, 0); 6695 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6696 va += L2_L_SIZE; 6697 pa += L2_L_SIZE; 6698 resid -= L2_L_SIZE; 6699 continue; 6700 } 6701 6702 /* Use a small page mapping. */ 6703 #ifdef VERBOSE_INIT_ARM 6704 printf("P"); 6705 #endif 6706 const pt_entry_t npte = L2_S_PROTO | pa 6707 #ifdef ARM_MMU_EXTENDED_XXX 6708 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6709 #endif 6710 #ifdef ARM_MMU_EXTENDED 6711 | (va & 0x80000000 ? 0 : L2_XS_nG) 6712 #endif 6713 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6714 l2pte_set(ptep, npte, 0); 6715 PTE_SYNC(ptep); 6716 va += PAGE_SIZE; 6717 pa += PAGE_SIZE; 6718 resid -= PAGE_SIZE; 6719 } 6720 #ifdef VERBOSE_INIT_ARM 6721 printf("\n"); 6722 #endif 6723 return (size); 6724 } 6725 6726 /********************** Static device map routines ***************************/ 6727 6728 static const struct pmap_devmap *pmap_devmap_table; 6729 6730 /* 6731 * Register the devmap table. This is provided in case early console 6732 * initialization needs to register mappings created by bootstrap code 6733 * before pmap_devmap_bootstrap() is called. 6734 */ 6735 void 6736 pmap_devmap_register(const struct pmap_devmap *table) 6737 { 6738 6739 pmap_devmap_table = table; 6740 } 6741 6742 /* 6743 * Map all of the static regions in the devmap table, and remember 6744 * the devmap table so other parts of the kernel can look up entries 6745 * later. 6746 */ 6747 void 6748 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6749 { 6750 int i; 6751 6752 pmap_devmap_table = table; 6753 6754 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6755 #ifdef VERBOSE_INIT_ARM 6756 printf("devmap: %08lx -> %08lx @ %08lx\n", 6757 pmap_devmap_table[i].pd_pa, 6758 pmap_devmap_table[i].pd_pa + 6759 pmap_devmap_table[i].pd_size - 1, 6760 pmap_devmap_table[i].pd_va); 6761 #endif 6762 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6763 pmap_devmap_table[i].pd_pa, 6764 pmap_devmap_table[i].pd_size, 6765 pmap_devmap_table[i].pd_prot, 6766 pmap_devmap_table[i].pd_cache); 6767 } 6768 } 6769 6770 const struct pmap_devmap * 6771 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6772 { 6773 uint64_t endpa; 6774 int i; 6775 6776 if (pmap_devmap_table == NULL) 6777 return (NULL); 6778 6779 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6780 6781 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6782 if (pa >= pmap_devmap_table[i].pd_pa && 6783 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6784 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6785 return (&pmap_devmap_table[i]); 6786 } 6787 6788 return (NULL); 6789 } 6790 6791 const struct pmap_devmap * 6792 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6793 { 6794 int i; 6795 6796 if (pmap_devmap_table == NULL) 6797 return (NULL); 6798 6799 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6800 if (va >= pmap_devmap_table[i].pd_va && 6801 va + size - 1 <= pmap_devmap_table[i].pd_va + 6802 pmap_devmap_table[i].pd_size - 1) 6803 return (&pmap_devmap_table[i]); 6804 } 6805 6806 return (NULL); 6807 } 6808 6809 /********************** PTE initialization routines **************************/ 6810 6811 /* 6812 * These routines are called when the CPU type is identified to set up 6813 * the PTE prototypes, cache modes, etc. 6814 * 6815 * The variables are always here, just in case modules need to reference 6816 * them (though, they shouldn't). 6817 */ 6818 6819 pt_entry_t pte_l1_s_cache_mode; 6820 pt_entry_t pte_l1_s_wc_mode; 6821 pt_entry_t pte_l1_s_cache_mode_pt; 6822 pt_entry_t pte_l1_s_cache_mask; 6823 6824 pt_entry_t pte_l2_l_cache_mode; 6825 pt_entry_t pte_l2_l_wc_mode; 6826 pt_entry_t pte_l2_l_cache_mode_pt; 6827 pt_entry_t pte_l2_l_cache_mask; 6828 6829 pt_entry_t pte_l2_s_cache_mode; 6830 pt_entry_t pte_l2_s_wc_mode; 6831 pt_entry_t pte_l2_s_cache_mode_pt; 6832 pt_entry_t pte_l2_s_cache_mask; 6833 6834 pt_entry_t pte_l1_s_prot_u; 6835 pt_entry_t pte_l1_s_prot_w; 6836 pt_entry_t pte_l1_s_prot_ro; 6837 pt_entry_t pte_l1_s_prot_mask; 6838 6839 pt_entry_t pte_l2_s_prot_u; 6840 pt_entry_t pte_l2_s_prot_w; 6841 pt_entry_t pte_l2_s_prot_ro; 6842 pt_entry_t pte_l2_s_prot_mask; 6843 6844 pt_entry_t pte_l2_l_prot_u; 6845 pt_entry_t pte_l2_l_prot_w; 6846 pt_entry_t pte_l2_l_prot_ro; 6847 pt_entry_t pte_l2_l_prot_mask; 6848 6849 pt_entry_t pte_l1_ss_proto; 6850 pt_entry_t pte_l1_s_proto; 6851 pt_entry_t pte_l1_c_proto; 6852 pt_entry_t pte_l2_s_proto; 6853 6854 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6855 void (*pmap_zero_page_func)(paddr_t); 6856 6857 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6858 void 6859 pmap_pte_init_generic(void) 6860 { 6861 6862 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6863 pte_l1_s_wc_mode = L1_S_B; 6864 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6865 6866 pte_l2_l_cache_mode = L2_B|L2_C; 6867 pte_l2_l_wc_mode = L2_B; 6868 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6869 6870 pte_l2_s_cache_mode = L2_B|L2_C; 6871 pte_l2_s_wc_mode = L2_B; 6872 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6873 6874 /* 6875 * If we have a write-through cache, set B and C. If 6876 * we have a write-back cache, then we assume setting 6877 * only C will make those pages write-through (except for those 6878 * Cortex CPUs which can read the L1 caches). 6879 */ 6880 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6881 #if ARM_MMU_V7 > 0 6882 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6883 #endif 6884 #if ARM_MMU_V6 > 0 6885 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6886 #endif 6887 || false) { 6888 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6889 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6890 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6891 } else { 6892 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6893 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6894 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6895 } 6896 6897 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6898 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6899 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6900 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6901 6902 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6903 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6904 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6905 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6906 6907 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6908 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6909 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6910 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6911 6912 pte_l1_ss_proto = L1_SS_PROTO_generic; 6913 pte_l1_s_proto = L1_S_PROTO_generic; 6914 pte_l1_c_proto = L1_C_PROTO_generic; 6915 pte_l2_s_proto = L2_S_PROTO_generic; 6916 6917 pmap_copy_page_func = pmap_copy_page_generic; 6918 pmap_zero_page_func = pmap_zero_page_generic; 6919 } 6920 6921 #if defined(CPU_ARM8) 6922 void 6923 pmap_pte_init_arm8(void) 6924 { 6925 6926 /* 6927 * ARM8 is compatible with generic, but we need to use 6928 * the page tables uncached. 6929 */ 6930 pmap_pte_init_generic(); 6931 6932 pte_l1_s_cache_mode_pt = 0; 6933 pte_l2_l_cache_mode_pt = 0; 6934 pte_l2_s_cache_mode_pt = 0; 6935 } 6936 #endif /* CPU_ARM8 */ 6937 6938 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6939 void 6940 pmap_pte_init_arm9(void) 6941 { 6942 6943 /* 6944 * ARM9 is compatible with generic, but we want to use 6945 * write-through caching for now. 6946 */ 6947 pmap_pte_init_generic(); 6948 6949 pte_l1_s_cache_mode = L1_S_C; 6950 pte_l2_l_cache_mode = L2_C; 6951 pte_l2_s_cache_mode = L2_C; 6952 6953 pte_l1_s_wc_mode = L1_S_B; 6954 pte_l2_l_wc_mode = L2_B; 6955 pte_l2_s_wc_mode = L2_B; 6956 6957 pte_l1_s_cache_mode_pt = L1_S_C; 6958 pte_l2_l_cache_mode_pt = L2_C; 6959 pte_l2_s_cache_mode_pt = L2_C; 6960 } 6961 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6962 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6963 6964 #if defined(CPU_ARM10) 6965 void 6966 pmap_pte_init_arm10(void) 6967 { 6968 6969 /* 6970 * ARM10 is compatible with generic, but we want to use 6971 * write-through caching for now. 6972 */ 6973 pmap_pte_init_generic(); 6974 6975 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6976 pte_l2_l_cache_mode = L2_B | L2_C; 6977 pte_l2_s_cache_mode = L2_B | L2_C; 6978 6979 pte_l1_s_cache_mode = L1_S_B; 6980 pte_l2_l_cache_mode = L2_B; 6981 pte_l2_s_cache_mode = L2_B; 6982 6983 pte_l1_s_cache_mode_pt = L1_S_C; 6984 pte_l2_l_cache_mode_pt = L2_C; 6985 pte_l2_s_cache_mode_pt = L2_C; 6986 6987 } 6988 #endif /* CPU_ARM10 */ 6989 6990 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6991 void 6992 pmap_pte_init_arm11(void) 6993 { 6994 6995 /* 6996 * ARM11 is compatible with generic, but we want to use 6997 * write-through caching for now. 6998 */ 6999 pmap_pte_init_generic(); 7000 7001 pte_l1_s_cache_mode = L1_S_C; 7002 pte_l2_l_cache_mode = L2_C; 7003 pte_l2_s_cache_mode = L2_C; 7004 7005 pte_l1_s_wc_mode = L1_S_B; 7006 pte_l2_l_wc_mode = L2_B; 7007 pte_l2_s_wc_mode = L2_B; 7008 7009 pte_l1_s_cache_mode_pt = L1_S_C; 7010 pte_l2_l_cache_mode_pt = L2_C; 7011 pte_l2_s_cache_mode_pt = L2_C; 7012 } 7013 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7014 7015 #if ARM_MMU_SA1 == 1 7016 void 7017 pmap_pte_init_sa1(void) 7018 { 7019 7020 /* 7021 * The StrongARM SA-1 cache does not have a write-through 7022 * mode. So, do the generic initialization, then reset 7023 * the page table cache mode to B=1,C=1, and note that 7024 * the PTEs need to be sync'd. 7025 */ 7026 pmap_pte_init_generic(); 7027 7028 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7029 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7030 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7031 7032 pmap_needs_pte_sync = 1; 7033 } 7034 #endif /* ARM_MMU_SA1 == 1*/ 7035 7036 #if ARM_MMU_XSCALE == 1 7037 #if (ARM_NMMUS > 1) 7038 static u_int xscale_use_minidata; 7039 #endif 7040 7041 void 7042 pmap_pte_init_xscale(void) 7043 { 7044 uint32_t auxctl; 7045 int write_through = 0; 7046 7047 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7048 pte_l1_s_wc_mode = L1_S_B; 7049 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7050 7051 pte_l2_l_cache_mode = L2_B|L2_C; 7052 pte_l2_l_wc_mode = L2_B; 7053 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7054 7055 pte_l2_s_cache_mode = L2_B|L2_C; 7056 pte_l2_s_wc_mode = L2_B; 7057 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7058 7059 pte_l1_s_cache_mode_pt = L1_S_C; 7060 pte_l2_l_cache_mode_pt = L2_C; 7061 pte_l2_s_cache_mode_pt = L2_C; 7062 7063 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7064 /* 7065 * The XScale core has an enhanced mode where writes that 7066 * miss the cache cause a cache line to be allocated. This 7067 * is significantly faster than the traditional, write-through 7068 * behavior of this case. 7069 */ 7070 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7071 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7072 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7073 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7074 7075 #ifdef XSCALE_CACHE_WRITE_THROUGH 7076 /* 7077 * Some versions of the XScale core have various bugs in 7078 * their cache units, the work-around for which is to run 7079 * the cache in write-through mode. Unfortunately, this 7080 * has a major (negative) impact on performance. So, we 7081 * go ahead and run fast-and-loose, in the hopes that we 7082 * don't line up the planets in a way that will trip the 7083 * bugs. 7084 * 7085 * However, we give you the option to be slow-but-correct. 7086 */ 7087 write_through = 1; 7088 #elif defined(XSCALE_CACHE_WRITE_BACK) 7089 /* force write back cache mode */ 7090 write_through = 0; 7091 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7092 /* 7093 * Intel PXA2[15]0 processors are known to have a bug in 7094 * write-back cache on revision 4 and earlier (stepping 7095 * A[01] and B[012]). Fixed for C0 and later. 7096 */ 7097 { 7098 uint32_t id, type; 7099 7100 id = cpufunc_id(); 7101 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7102 7103 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7104 if ((id & CPU_ID_REVISION_MASK) < 5) { 7105 /* write through for stepping A0-1 and B0-2 */ 7106 write_through = 1; 7107 } 7108 } 7109 } 7110 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7111 7112 if (write_through) { 7113 pte_l1_s_cache_mode = L1_S_C; 7114 pte_l2_l_cache_mode = L2_C; 7115 pte_l2_s_cache_mode = L2_C; 7116 } 7117 7118 #if (ARM_NMMUS > 1) 7119 xscale_use_minidata = 1; 7120 #endif 7121 7122 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7123 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7124 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7125 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7126 7127 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7128 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7129 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7130 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7131 7132 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7133 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7134 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7135 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7136 7137 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7138 pte_l1_s_proto = L1_S_PROTO_xscale; 7139 pte_l1_c_proto = L1_C_PROTO_xscale; 7140 pte_l2_s_proto = L2_S_PROTO_xscale; 7141 7142 pmap_copy_page_func = pmap_copy_page_xscale; 7143 pmap_zero_page_func = pmap_zero_page_xscale; 7144 7145 /* 7146 * Disable ECC protection of page table access, for now. 7147 */ 7148 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7149 auxctl &= ~XSCALE_AUXCTL_P; 7150 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7151 } 7152 7153 /* 7154 * xscale_setup_minidata: 7155 * 7156 * Set up the mini-data cache clean area. We require the 7157 * caller to allocate the right amount of physically and 7158 * virtually contiguous space. 7159 */ 7160 void 7161 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7162 { 7163 extern vaddr_t xscale_minidata_clean_addr; 7164 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7165 pd_entry_t *pde = (pd_entry_t *) l1pt; 7166 vsize_t size; 7167 uint32_t auxctl; 7168 7169 xscale_minidata_clean_addr = va; 7170 7171 /* Round it to page size. */ 7172 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7173 7174 for (; size != 0; 7175 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7176 const size_t l1slot = l1pte_index(va); 7177 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7178 if (ptep == NULL) 7179 panic("xscale_setup_minidata: can't find L2 table for " 7180 "VA 0x%08lx", va); 7181 7182 ptep += l2pte_index(va); 7183 pt_entry_t opte = *ptep; 7184 l2pte_set(ptep, 7185 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7186 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7187 } 7188 7189 /* 7190 * Configure the mini-data cache for write-back with 7191 * read/write-allocate. 7192 * 7193 * NOTE: In order to reconfigure the mini-data cache, we must 7194 * make sure it contains no valid data! In order to do that, 7195 * we must issue a global data cache invalidate command! 7196 * 7197 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7198 * THIS IS VERY IMPORTANT! 7199 */ 7200 7201 /* Invalidate data and mini-data. */ 7202 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7203 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7204 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7205 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7206 } 7207 7208 /* 7209 * Change the PTEs for the specified kernel mappings such that they 7210 * will use the mini data cache instead of the main data cache. 7211 */ 7212 void 7213 pmap_uarea(vaddr_t va) 7214 { 7215 vaddr_t next_bucket, eva; 7216 7217 #if (ARM_NMMUS > 1) 7218 if (xscale_use_minidata == 0) 7219 return; 7220 #endif 7221 7222 eva = va + USPACE; 7223 7224 while (va < eva) { 7225 next_bucket = L2_NEXT_BUCKET_VA(va); 7226 if (next_bucket > eva) 7227 next_bucket = eva; 7228 7229 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7230 KDASSERT(l2b != NULL); 7231 7232 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7233 pt_entry_t *ptep = sptep; 7234 7235 while (va < next_bucket) { 7236 const pt_entry_t opte = *ptep; 7237 if (!l2pte_minidata_p(opte)) { 7238 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7239 cpu_tlb_flushD_SE(va); 7240 l2pte_set(ptep, opte & ~L2_B, opte); 7241 } 7242 ptep += PAGE_SIZE / L2_S_SIZE; 7243 va += PAGE_SIZE; 7244 } 7245 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7246 } 7247 cpu_cpwait(); 7248 } 7249 #endif /* ARM_MMU_XSCALE == 1 */ 7250 7251 7252 #if defined(CPU_ARM11MPCORE) 7253 7254 void 7255 pmap_pte_init_arm11mpcore(void) 7256 { 7257 7258 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7259 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7260 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7261 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7262 /* use extended small page (without APn, with TEX) */ 7263 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7264 #else 7265 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7266 #endif 7267 7268 /* write-back, write-allocate */ 7269 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7270 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7271 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7272 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7273 #else 7274 /* no TEX. read-allocate */ 7275 pte_l2_s_cache_mode = L2_C | L2_B; 7276 #endif 7277 /* 7278 * write-back, write-allocate for page tables. 7279 */ 7280 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7281 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7282 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7283 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7284 #else 7285 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7286 #endif 7287 7288 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7289 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7290 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7291 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7292 7293 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7294 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7295 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7296 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7297 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7298 7299 #else 7300 /* with AP[0..3] */ 7301 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7302 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7303 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7304 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7305 #endif 7306 7307 #ifdef ARM11MPCORE_COMPAT_MMU 7308 /* with AP[0..3] */ 7309 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7310 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7311 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7312 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7313 7314 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7315 pte_l1_s_proto = L1_S_PROTO_armv6; 7316 pte_l1_c_proto = L1_C_PROTO_armv6; 7317 pte_l2_s_proto = L2_S_PROTO_armv6c; 7318 #else 7319 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7320 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7321 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7322 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7323 7324 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7325 pte_l1_s_proto = L1_S_PROTO_armv6; 7326 pte_l1_c_proto = L1_C_PROTO_armv6; 7327 pte_l2_s_proto = L2_S_PROTO_armv6n; 7328 #endif 7329 7330 pmap_copy_page_func = pmap_copy_page_generic; 7331 pmap_zero_page_func = pmap_zero_page_generic; 7332 pmap_needs_pte_sync = 1; 7333 } 7334 #endif /* CPU_ARM11MPCORE */ 7335 7336 7337 #if ARM_MMU_V7 == 1 7338 void 7339 pmap_pte_init_armv7(void) 7340 { 7341 /* 7342 * The ARMv7-A MMU is mostly compatible with generic. If the 7343 * AP field is zero, that now means "no access" rather than 7344 * read-only. The prototypes are a little different because of 7345 * the XN bit. 7346 */ 7347 pmap_pte_init_generic(); 7348 7349 pmap_needs_pte_sync = 1; 7350 7351 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7352 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7353 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7354 7355 /* 7356 * If the core support coherent walk then updates to translation tables 7357 * do not require a clean to the point of unification to ensure 7358 * visibility by subsequent translation table walks. That means we can 7359 * map everything shareable and cached and the right thing will happen. 7360 */ 7361 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7362 pmap_needs_pte_sync = 0; 7363 7364 /* 7365 * write-back, no write-allocate, shareable for normal pages. 7366 */ 7367 pte_l1_s_cache_mode |= L1_S_V6_S; 7368 pte_l2_l_cache_mode |= L2_XS_S; 7369 pte_l2_s_cache_mode |= L2_XS_S; 7370 } 7371 7372 /* 7373 * Page tables are just all other memory. We can use write-back since 7374 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7375 */ 7376 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7377 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7378 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7379 7380 /* 7381 * Check the Memory Model Features to see if this CPU supports 7382 * the TLBIASID coproc op. 7383 */ 7384 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7385 arm_has_tlbiasid_p = true; 7386 } 7387 7388 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7389 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7390 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7391 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7392 7393 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7394 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7395 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7396 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7397 7398 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7399 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7400 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7401 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7402 7403 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7404 pte_l1_s_proto = L1_S_PROTO_armv7; 7405 pte_l1_c_proto = L1_C_PROTO_armv7; 7406 pte_l2_s_proto = L2_S_PROTO_armv7; 7407 7408 } 7409 #endif /* ARM_MMU_V7 */ 7410 7411 /* 7412 * return the PA of the current L1 table, for use when handling a crash dump 7413 */ 7414 uint32_t 7415 pmap_kernel_L1_addr(void) 7416 { 7417 #ifdef ARM_MMU_EXTENDED 7418 return pmap_kernel()->pm_l1_pa; 7419 #else 7420 return pmap_kernel()->pm_l1->l1_physaddr; 7421 #endif 7422 } 7423 7424 #if defined(DDB) 7425 /* 7426 * A couple of ddb-callable functions for dumping pmaps 7427 */ 7428 void pmap_dump_all(void); 7429 void pmap_dump(pmap_t); 7430 7431 void 7432 pmap_dump_all(void) 7433 { 7434 pmap_t pm; 7435 7436 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7437 if (pm == pmap_kernel()) 7438 continue; 7439 pmap_dump(pm); 7440 printf("\n"); 7441 } 7442 } 7443 7444 static pt_entry_t ncptes[64]; 7445 static void pmap_dump_ncpg(pmap_t); 7446 7447 void 7448 pmap_dump(pmap_t pm) 7449 { 7450 struct l2_dtable *l2; 7451 struct l2_bucket *l2b; 7452 pt_entry_t *ptep, pte; 7453 vaddr_t l2_va, l2b_va, va; 7454 int i, j, k, occ, rows = 0; 7455 7456 if (pm == pmap_kernel()) 7457 printf("pmap_kernel (%p): ", pm); 7458 else 7459 printf("user pmap (%p): ", pm); 7460 7461 #ifdef ARM_MMU_EXTENDED 7462 printf("l1 at %p\n", pmap_l1_kva(pm)); 7463 #else 7464 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7465 #endif 7466 7467 l2_va = 0; 7468 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7469 l2 = pm->pm_l2[i]; 7470 7471 if (l2 == NULL || l2->l2_occupancy == 0) 7472 continue; 7473 7474 l2b_va = l2_va; 7475 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7476 l2b = &l2->l2_bucket[j]; 7477 7478 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7479 continue; 7480 7481 ptep = l2b->l2b_kva; 7482 7483 for (k = 0; k < 256 && ptep[k] == 0; k++) 7484 ; 7485 7486 k &= ~63; 7487 occ = l2b->l2b_occupancy; 7488 va = l2b_va + (k * 4096); 7489 for (; k < 256; k++, va += 0x1000) { 7490 char ch = ' '; 7491 if ((k % 64) == 0) { 7492 if ((rows % 8) == 0) { 7493 printf( 7494 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7495 } 7496 printf("%08lx: ", va); 7497 } 7498 7499 ncptes[k & 63] = 0; 7500 pte = ptep[k]; 7501 if (pte == 0) { 7502 ch = '.'; 7503 } else { 7504 occ--; 7505 switch (pte & 0x0c) { 7506 case 0x00: 7507 ch = 'D'; /* No cache No buff */ 7508 break; 7509 case 0x04: 7510 ch = 'B'; /* No cache buff */ 7511 break; 7512 case 0x08: 7513 if (pte & 0x40) 7514 ch = 'm'; 7515 else 7516 ch = 'C'; /* Cache No buff */ 7517 break; 7518 case 0x0c: 7519 ch = 'F'; /* Cache Buff */ 7520 break; 7521 } 7522 7523 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7524 ch += 0x20; 7525 7526 if ((pte & 0xc) == 0) 7527 ncptes[k & 63] = pte; 7528 } 7529 7530 if ((k % 64) == 63) { 7531 rows++; 7532 printf("%c\n", ch); 7533 pmap_dump_ncpg(pm); 7534 if (occ == 0) 7535 break; 7536 } else 7537 printf("%c", ch); 7538 } 7539 } 7540 } 7541 } 7542 7543 static void 7544 pmap_dump_ncpg(pmap_t pm) 7545 { 7546 struct vm_page *pg; 7547 struct vm_page_md *md; 7548 struct pv_entry *pv; 7549 int i; 7550 7551 for (i = 0; i < 63; i++) { 7552 if (ncptes[i] == 0) 7553 continue; 7554 7555 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7556 if (pg == NULL) 7557 continue; 7558 md = VM_PAGE_TO_MD(pg); 7559 7560 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7561 VM_PAGE_TO_PHYS(pg), 7562 md->krw_mappings, md->kro_mappings, 7563 md->urw_mappings, md->uro_mappings); 7564 7565 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7566 printf(" %c va 0x%08lx, flags 0x%x\n", 7567 (pm == pv->pv_pmap) ? '*' : ' ', 7568 pv->pv_va, pv->pv_flags); 7569 } 7570 } 7571 } 7572 #endif 7573 7574 #ifdef PMAP_STEAL_MEMORY 7575 void 7576 pmap_boot_pageadd(pv_addr_t *newpv) 7577 { 7578 pv_addr_t *pv, *npv; 7579 7580 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7581 if (newpv->pv_pa < pv->pv_va) { 7582 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7583 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7584 newpv->pv_size += pv->pv_size; 7585 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7586 } 7587 pv = NULL; 7588 } else { 7589 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7590 pv = npv) { 7591 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7592 KASSERT(pv->pv_pa < newpv->pv_pa); 7593 if (newpv->pv_pa > npv->pv_pa) 7594 continue; 7595 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7596 pv->pv_size += newpv->pv_size; 7597 return; 7598 } 7599 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7600 break; 7601 newpv->pv_size += npv->pv_size; 7602 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7603 SLIST_REMOVE_AFTER(newpv, pv_list); 7604 return; 7605 } 7606 } 7607 } 7608 7609 if (pv) { 7610 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7611 } else { 7612 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7613 } 7614 } 7615 7616 void 7617 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7618 pv_addr_t *rpv) 7619 { 7620 pv_addr_t *pv, **pvp; 7621 struct vm_physseg *ps; 7622 size_t i; 7623 7624 KASSERT(amount & PGOFSET); 7625 KASSERT((mask & PGOFSET) == 0); 7626 KASSERT((match & PGOFSET) == 0); 7627 KASSERT(amount != 0); 7628 7629 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7630 (pv = *pvp) != NULL; 7631 pvp = &SLIST_NEXT(pv, pv_list)) { 7632 pv_addr_t *newpv; 7633 psize_t off; 7634 /* 7635 * If this entry is too small to satify the request... 7636 */ 7637 KASSERT(pv->pv_size > 0); 7638 if (pv->pv_size < amount) 7639 continue; 7640 7641 for (off = 0; off <= mask; off += PAGE_SIZE) { 7642 if (((pv->pv_pa + off) & mask) == match 7643 && off + amount <= pv->pv_size) 7644 break; 7645 } 7646 if (off > mask) 7647 continue; 7648 7649 rpv->pv_va = pv->pv_va + off; 7650 rpv->pv_pa = pv->pv_pa + off; 7651 rpv->pv_size = amount; 7652 pv->pv_size -= amount; 7653 if (pv->pv_size == 0) { 7654 KASSERT(off == 0); 7655 KASSERT((vaddr_t) pv == rpv->pv_va); 7656 *pvp = SLIST_NEXT(pv, pv_list); 7657 } else if (off == 0) { 7658 KASSERT((vaddr_t) pv == rpv->pv_va); 7659 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7660 *newpv = *pv; 7661 newpv->pv_pa += amount; 7662 newpv->pv_va += amount; 7663 *pvp = newpv; 7664 } else if (off < pv->pv_size) { 7665 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7666 *newpv = *pv; 7667 newpv->pv_size -= off; 7668 newpv->pv_pa += off + amount; 7669 newpv->pv_va += off + amount; 7670 7671 SLIST_NEXT(pv, pv_list) = newpv; 7672 pv->pv_size = off; 7673 } else { 7674 KASSERT((vaddr_t) pv != rpv->pv_va); 7675 } 7676 memset((void *)rpv->pv_va, 0, amount); 7677 return; 7678 } 7679 7680 if (vm_nphysseg == 0) 7681 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7682 7683 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7684 (pv = *pvp) != NULL; 7685 pvp = &SLIST_NEXT(pv, pv_list)) { 7686 if (SLIST_NEXT(pv, pv_list) == NULL) 7687 break; 7688 } 7689 KASSERT(mask == 0); 7690 for (i = 0; i < vm_nphysseg; i++) { 7691 ps = VM_PHYSMEM_PTR(i); 7692 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7693 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7694 rpv->pv_va = pv->pv_va; 7695 rpv->pv_pa = pv->pv_pa; 7696 rpv->pv_size = amount; 7697 *pvp = NULL; 7698 pmap_map_chunk(kernel_l1pt.pv_va, 7699 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7700 ptoa(ps->avail_start), 7701 amount - pv->pv_size, 7702 VM_PROT_READ|VM_PROT_WRITE, 7703 PTE_CACHE); 7704 ps->avail_start += atop(amount - pv->pv_size); 7705 /* 7706 * If we consumed the entire physseg, remove it. 7707 */ 7708 if (ps->avail_start == ps->avail_end) { 7709 for (--vm_nphysseg; i < vm_nphysseg; i++) 7710 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7711 } 7712 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7713 return; 7714 } 7715 } 7716 7717 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7718 } 7719 7720 vaddr_t 7721 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7722 { 7723 pv_addr_t pv; 7724 7725 pmap_boot_pagealloc(size, 0, 0, &pv); 7726 7727 return pv.pv_va; 7728 } 7729 #endif /* PMAP_STEAL_MEMORY */ 7730 7731 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7732 { 7733 sysctl_createv(clog, 0, NULL, NULL, 7734 CTLFLAG_PERMANENT, 7735 CTLTYPE_NODE, "machdep", NULL, 7736 NULL, 0, NULL, 0, 7737 CTL_MACHDEP, CTL_EOL); 7738 7739 sysctl_createv(clog, 0, NULL, NULL, 7740 CTLFLAG_PERMANENT, 7741 CTLTYPE_INT, "kmpages", 7742 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7743 NULL, 0, &pmap_kmpages, 0, 7744 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7745 } 7746 7747 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7748 struct vm_page * 7749 arm_pmap_alloc_poolpage(int flags) 7750 { 7751 /* 7752 * On some systems, only some pages may be "coherent" for dma and we 7753 * want to prefer those for pool pages (think mbufs) but fallback to 7754 * any page if none is available. But we can only fallback if we 7755 * aren't direct mapping memory or all of memory can be direct-mapped. 7756 * If that isn't true, pool changes can only come from direct-mapped 7757 * memory. 7758 */ 7759 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7760 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7761 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7762 (pmap_directbase < KERNEL_BASE 7763 ? UVM_PGA_STRAT_ONLY 7764 : UVM_PGA_STRAT_FALLBACK), 7765 #else 7766 UVM_PGA_STRAT_FALLBACK, 7767 #endif 7768 arm_poolpage_vmfreelist); 7769 } 7770 7771 return uvm_pagealloc(NULL, 0, NULL, flags); 7772 } 7773 #endif 7774 7775 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7776 void 7777 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7778 { 7779 /* nothing */ 7780 } 7781 7782 int 7783 pic_ipi_shootdown(void *arg) 7784 { 7785 #if PMAP_NEED_TLB_SHOOTDOWN 7786 pmap_tlb_shootdown_process(); 7787 #endif 7788 return 1; 7789 } 7790 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7791 7792 7793 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7794 vaddr_t 7795 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7796 { 7797 bool ok = false; 7798 if (physical_start <= pa && pa < physical_end) { 7799 #ifdef ARM_MMU_EXTENDED 7800 const vaddr_t newva = pmap_directbase + pa - physical_start; 7801 if (newva >= KERNEL_BASE) { 7802 va = newva; 7803 ok = true; 7804 } 7805 #else 7806 va = KERNEL_BASE + pa - physical_start; 7807 ok = true; 7808 #endif 7809 } 7810 KASSERT(ok_p); 7811 *ok_p = ok; 7812 return va; 7813 } 7814 7815 vaddr_t 7816 pmap_map_poolpage(paddr_t pa) 7817 { 7818 bool ok __diagused; 7819 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7820 KASSERT(ok); 7821 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7822 if (arm_cache_prefer_mask != 0) { 7823 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7824 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7825 pmap_acquire_page_lock(md); 7826 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7827 pmap_release_page_lock(md); 7828 } 7829 #endif 7830 return va; 7831 } 7832 7833 paddr_t 7834 pmap_unmap_poolpage(vaddr_t va) 7835 { 7836 KASSERT(va >= KERNEL_BASE); 7837 #if defined(ARM_MMU_EXTENDED) 7838 return va - pmap_directbase + physical_start; 7839 #else 7840 #ifdef PMAP_CACHE_VIVT 7841 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7842 #endif 7843 return va - KERNEL_BASE + physical_start; 7844 #endif 7845 } 7846 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7847
Indexes created Mon Sep 29 21:09:56 GMT 2025