pmap.c revision 1.303
1 /* $NetBSD: pmap.c,v 1.303 2014/10/14 12:31:14 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 //#include <arm/arm32/katelib.h> 218 219 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.303 2014/10/14 12:31:14 skrll Exp $"); 220 221 //#define PMAP_DEBUG 222 #ifdef PMAP_DEBUG 223 224 /* XXX need to get rid of all refs to this */ 225 int pmap_debug_level = 0; 226 227 /* 228 * for switching to potentially finer grained debugging 229 */ 230 #define PDB_FOLLOW 0x0001 231 #define PDB_INIT 0x0002 232 #define PDB_ENTER 0x0004 233 #define PDB_REMOVE 0x0008 234 #define PDB_CREATE 0x0010 235 #define PDB_PTPAGE 0x0020 236 #define PDB_GROWKERN 0x0040 237 #define PDB_BITS 0x0080 238 #define PDB_COLLECT 0x0100 239 #define PDB_PROTECT 0x0200 240 #define PDB_MAP_L1 0x0400 241 #define PDB_BOOTSTRAP 0x1000 242 #define PDB_PARANOIA 0x2000 243 #define PDB_WIRING 0x4000 244 #define PDB_PVDUMP 0x8000 245 #define PDB_VAC 0x10000 246 #define PDB_KENTER 0x20000 247 #define PDB_KREMOVE 0x40000 248 #define PDB_EXEC 0x80000 249 250 int debugmap = 1; 251 int pmapdebug = 0; 252 #define NPDEBUG(_lev_,_stat_) \ 253 if (pmapdebug & (_lev_)) \ 254 ((_stat_)) 255 256 #else /* PMAP_DEBUG */ 257 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 258 #endif /* PMAP_DEBUG */ 259 260 /* 261 * pmap_kernel() points here 262 */ 263 static struct pmap kernel_pmap_store = { 264 #ifndef ARM_MMU_EXTENDED 265 .pm_activated = true, 266 .pm_domain = PMAP_DOMAIN_KERNEL, 267 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 268 #endif 269 }; 270 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 271 #undef pmap_kernel 272 #define pmap_kernel() (&kernel_pmap_store) 273 #ifdef PMAP_NEED_ALLOC_POOLPAGE 274 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 275 #endif 276 277 /* 278 * Pool and cache that pmap structures are allocated from. 279 * We use a cache to avoid clearing the pm_l2[] array (1KB) 280 * in pmap_create(). 281 */ 282 static struct pool_cache pmap_cache; 283 static LIST_HEAD(, pmap) pmap_pmaps; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 static struct evcnt pmap_ev_exec_synced_map = 426 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 427 #ifndef ARM_MMU_EXTENDED 428 static struct evcnt pmap_ev_exec_synced_unmap = 429 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 430 static struct evcnt pmap_ev_exec_synced_remap = 431 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 432 static struct evcnt pmap_ev_exec_synced_clearbit = 433 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 440 #ifndef ARM_MMU_EXTENDED 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 /* 489 * pmap copy/zero page, and mem(5) hook point 490 */ 491 static pt_entry_t *csrc_pte, *cdst_pte; 492 static vaddr_t csrcp, cdstp; 493 #ifdef MULTIPROCESSOR 494 static size_t cnptes; 495 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 497 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 499 #else 500 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + (o)) 503 #define cpu_cdstp(o) (cdstp + (o)) 504 #endif 505 vaddr_t memhook; /* used by mem.c & others */ 506 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 507 kmutex_t pmap_lock __cacheline_aligned; 508 extern void *msgbufaddr; 509 int pmap_kmpages; 510 /* 511 * Flag to indicate if pmap_init() has done its thing 512 */ 513 bool pmap_initialized; 514 515 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 516 /* 517 * Start of direct-mapped memory 518 */ 519 vaddr_t pmap_directbase = KERNEL_BASE; 520 #endif 521 522 /* 523 * Misc. locking data structures 524 */ 525 526 static inline void 527 pmap_acquire_pmap_lock(pmap_t pm) 528 { 529 if (pm == pmap_kernel()) { 530 #ifdef MULTIPROCESSOR 531 KERNEL_LOCK(1, NULL); 532 #endif 533 } else { 534 mutex_enter(pm->pm_lock); 535 } 536 } 537 538 static inline void 539 pmap_release_pmap_lock(pmap_t pm) 540 { 541 if (pm == pmap_kernel()) { 542 #ifdef MULTIPROCESSOR 543 KERNEL_UNLOCK_ONE(NULL); 544 #endif 545 } else { 546 mutex_exit(pm->pm_lock); 547 } 548 } 549 550 static inline void 551 pmap_acquire_page_lock(struct vm_page_md *md) 552 { 553 mutex_enter(&pmap_lock); 554 } 555 556 static inline void 557 pmap_release_page_lock(struct vm_page_md *md) 558 { 559 mutex_exit(&pmap_lock); 560 } 561 562 #ifdef DIAGNOSTIC 563 static inline int 564 pmap_page_locked_p(struct vm_page_md *md) 565 { 566 return mutex_owned(&pmap_lock); 567 } 568 #endif 569 570 571 /* 572 * Metadata for L1 translation tables. 573 */ 574 #ifndef ARM_MMU_EXTENDED 575 struct l1_ttable { 576 /* Entry on the L1 Table list */ 577 SLIST_ENTRY(l1_ttable) l1_link; 578 579 /* Entry on the L1 Least Recently Used list */ 580 TAILQ_ENTRY(l1_ttable) l1_lru; 581 582 /* Track how many domains are allocated from this L1 */ 583 volatile u_int l1_domain_use_count; 584 585 /* 586 * A free-list of domain numbers for this L1. 587 * We avoid using ffs() and a bitmap to track domains since ffs() 588 * is slow on ARM. 589 */ 590 uint8_t l1_domain_first; 591 uint8_t l1_domain_free[PMAP_DOMAINS]; 592 593 /* Physical address of this L1 page table */ 594 paddr_t l1_physaddr; 595 596 /* KVA of this L1 page table */ 597 pd_entry_t *l1_kva; 598 }; 599 600 /* 601 * L1 Page Tables are tracked using a Least Recently Used list. 602 * - New L1s are allocated from the HEAD. 603 * - Freed L1s are added to the TAIl. 604 * - Recently accessed L1s (where an 'access' is some change to one of 605 * the userland pmaps which owns this L1) are moved to the TAIL. 606 */ 607 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 608 static kmutex_t l1_lru_lock __cacheline_aligned; 609 610 /* 611 * A list of all L1 tables 612 */ 613 static SLIST_HEAD(, l1_ttable) l1_list; 614 #endif /* ARM_MMU_EXTENDED */ 615 616 /* 617 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 618 * 619 * This is normally 16MB worth L2 page descriptors for any given pmap. 620 * Reference counts are maintained for L2 descriptors so they can be 621 * freed when empty. 622 */ 623 struct l2_bucket { 624 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 625 paddr_t l2b_pa; /* Physical address of same */ 626 u_short l2b_l1slot; /* This L2 table's L1 index */ 627 u_short l2b_occupancy; /* How many active descriptors */ 628 }; 629 630 struct l2_dtable { 631 /* The number of L2 page descriptors allocated to this l2_dtable */ 632 u_int l2_occupancy; 633 634 /* List of L2 page descriptors */ 635 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 636 }; 637 638 /* 639 * Given an L1 table index, calculate the corresponding l2_dtable index 640 * and bucket index within the l2_dtable. 641 */ 642 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 643 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 644 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 645 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 646 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 647 648 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 649 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 650 651 /* 652 * Given a virtual address, this macro returns the 653 * virtual address required to drop into the next L2 bucket. 654 */ 655 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 656 657 /* 658 * L2 allocation. 659 */ 660 #define pmap_alloc_l2_dtable() \ 661 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 662 #define pmap_free_l2_dtable(l2) \ 663 pool_cache_put(&pmap_l2dtable_cache, (l2)) 664 #define pmap_alloc_l2_ptp(pap) \ 665 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 666 PR_NOWAIT, (pap))) 667 668 /* 669 * We try to map the page tables write-through, if possible. However, not 670 * all CPUs have a write-through cache mode, so on those we have to sync 671 * the cache when we frob page tables. 672 * 673 * We try to evaluate this at compile time, if possible. However, it's 674 * not always possible to do that, hence this run-time var. 675 */ 676 int pmap_needs_pte_sync; 677 678 /* 679 * Real definition of pv_entry. 680 */ 681 struct pv_entry { 682 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 683 pmap_t pv_pmap; /* pmap where mapping lies */ 684 vaddr_t pv_va; /* virtual address for mapping */ 685 u_int pv_flags; /* flags */ 686 }; 687 688 /* 689 * Macro to determine if a mapping might be resident in the 690 * instruction cache and/or TLB 691 */ 692 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 693 /* 694 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 695 * there are no explicit accesses, so there may be always be TLB entries to 696 * flush. If we used ASIDs then this would not be a problem. 697 */ 698 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 699 #else 700 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 701 #endif 702 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 703 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 704 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 705 706 /* 707 * Macro to determine if a mapping might be resident in the 708 * data cache and/or TLB 709 */ 710 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 711 /* 712 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 713 * there are no explicit accesses, so there may be always be TLB entries to 714 * flush. If we used ASIDs then this would not be a problem. 715 */ 716 #define PV_BEEN_REFD(f) (1) 717 #else 718 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 719 #endif 720 721 /* 722 * Local prototypes 723 */ 724 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 725 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 726 pt_entry_t **); 727 static bool pmap_is_current(pmap_t) __unused; 728 static bool pmap_is_cached(pmap_t); 729 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 730 pmap_t, vaddr_t, u_int); 731 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 732 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 733 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 734 u_int, u_int); 735 736 static void pmap_pinit(pmap_t); 737 static int pmap_pmap_ctor(void *, void *, int); 738 739 static void pmap_alloc_l1(pmap_t); 740 static void pmap_free_l1(pmap_t); 741 #ifndef ARM_MMU_EXTENDED 742 static void pmap_use_l1(pmap_t); 743 #endif 744 745 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 746 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 747 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 748 static int pmap_l2ptp_ctor(void *, void *, int); 749 static int pmap_l2dtable_ctor(void *, void *, int); 750 751 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 752 #ifdef PMAP_CACHE_VIVT 753 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 754 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 755 #endif 756 757 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 758 #ifdef PMAP_CACHE_VIVT 759 static bool pmap_clean_page(struct vm_page_md *, bool); 760 #endif 761 #ifdef PMAP_CACHE_VIPT 762 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 763 enum pmap_flush_op { 764 PMAP_FLUSH_PRIMARY, 765 PMAP_FLUSH_SECONDARY, 766 PMAP_CLEAN_PRIMARY 767 }; 768 #ifndef ARM_MMU_EXTENDED 769 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 770 #endif 771 #endif 772 static void pmap_page_remove(struct vm_page_md *, paddr_t); 773 774 #ifndef ARM_MMU_EXTENDED 775 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 776 #endif 777 static vaddr_t kernel_pt_lookup(paddr_t); 778 779 780 /* 781 * Misc variables 782 */ 783 vaddr_t virtual_avail; 784 vaddr_t virtual_end; 785 vaddr_t pmap_curmaxkvaddr; 786 787 paddr_t avail_start; 788 paddr_t avail_end; 789 790 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 791 pv_addr_t kernelpages; 792 pv_addr_t kernel_l1pt; 793 pv_addr_t systempage; 794 795 /* Function to set the debug level of the pmap code */ 796 797 #ifdef PMAP_DEBUG 798 void 799 pmap_debug(int level) 800 { 801 pmap_debug_level = level; 802 printf("pmap_debug: level=%d\n", pmap_debug_level); 803 } 804 #endif /* PMAP_DEBUG */ 805 806 #ifdef PMAP_CACHE_VIPT 807 #define PMAP_VALIDATE_MD_PAGE(md) \ 808 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 809 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 810 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 811 #endif /* PMAP_CACHE_VIPT */ 812 /* 813 * A bunch of routines to conditionally flush the caches/TLB depending 814 * on whether the specified pmap actually needs to be flushed at any 815 * given time. 816 */ 817 static inline void 818 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 819 { 820 #ifdef ARM_MMU_EXTENDED 821 pmap_tlb_invalidate_addr(pm, va); 822 #else 823 if (pm->pm_cstate.cs_tlb_id != 0) { 824 if (PV_BEEN_EXECD(flags)) { 825 cpu_tlb_flushID_SE(va); 826 } else if (PV_BEEN_REFD(flags)) { 827 cpu_tlb_flushD_SE(va); 828 } 829 } 830 #endif /* ARM_MMU_EXTENDED */ 831 } 832 833 static inline void 834 pmap_tlb_flushID(pmap_t pm) 835 { 836 #ifdef ARM_MMU_EXTENDED 837 pmap_tlb_asid_release_all(pm); 838 #else 839 if (pm->pm_cstate.cs_tlb_id) { 840 cpu_tlb_flushID(); 841 #if ARM_MMU_V7 == 0 842 /* 843 * Speculative loads by Cortex cores can cause TLB entries to 844 * be filled even if there are no explicit accesses, so there 845 * may be always be TLB entries to flush. If we used ASIDs 846 * then it would not be a problem. 847 * This is not true for other CPUs. 848 */ 849 pm->pm_cstate.cs_tlb = 0; 850 #endif /* ARM_MMU_V7 */ 851 } 852 #endif /* ARM_MMU_EXTENDED */ 853 } 854 855 static inline void 856 pmap_tlb_flushD(pmap_t pm) 857 { 858 #ifdef ARM_MMU_EXTENDED 859 pmap_tlb_asid_release_all(pm); 860 #else 861 if (pm->pm_cstate.cs_tlb_d) { 862 cpu_tlb_flushD(); 863 #if ARM_MMU_V7 == 0 864 /* 865 * Speculative loads by Cortex cores can cause TLB entries to 866 * be filled even if there are no explicit accesses, so there 867 * may be always be TLB entries to flush. If we used ASIDs 868 * then it would not be a problem. 869 * This is not true for other CPUs. 870 */ 871 pm->pm_cstate.cs_tlb_d = 0; 872 #endif /* ARM_MMU_V7 */ 873 } 874 #endif /* ARM_MMU_EXTENDED */ 875 } 876 877 #ifdef PMAP_CACHE_VIVT 878 static inline void 879 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 880 { 881 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 882 cpu_idcache_wbinv_range(va, PAGE_SIZE); 883 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 884 if (do_inv) { 885 if (flags & PVF_WRITE) 886 cpu_dcache_wbinv_range(va, PAGE_SIZE); 887 else 888 cpu_dcache_inv_range(va, PAGE_SIZE); 889 } else if (flags & PVF_WRITE) { 890 cpu_dcache_wb_range(va, PAGE_SIZE); 891 } 892 } 893 } 894 895 static inline void 896 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 897 { 898 if (PV_BEEN_EXECD(flags)) { 899 if (pm->pm_cstate.cs_cache_id) { 900 cpu_idcache_wbinv_all(); 901 pm->pm_cstate.cs_cache = 0; 902 } 903 } else if (pm->pm_cstate.cs_cache_d) { 904 cpu_dcache_wbinv_all(); 905 pm->pm_cstate.cs_cache_d = 0; 906 } 907 } 908 #endif /* PMAP_CACHE_VIVT */ 909 910 static inline uint8_t 911 pmap_domain(pmap_t pm) 912 { 913 #ifdef ARM_MMU_EXTENDED 914 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 915 #else 916 return pm->pm_domain; 917 #endif 918 } 919 920 static inline pd_entry_t * 921 pmap_l1_kva(pmap_t pm) 922 { 923 #ifdef ARM_MMU_EXTENDED 924 return pm->pm_l1; 925 #else 926 return pm->pm_l1->l1_kva; 927 #endif 928 } 929 930 static inline bool 931 pmap_is_current(pmap_t pm) 932 { 933 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 934 return true; 935 936 return false; 937 } 938 939 static inline bool 940 pmap_is_cached(pmap_t pm) 941 { 942 #ifdef ARM_MMU_EXTENDED 943 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 944 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 945 return true; 946 #else 947 struct cpu_info * const ci = curcpu(); 948 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 949 || ci->ci_pmap_lastuser == pm) 950 return true; 951 #endif /* ARM_MMU_EXTENDED */ 952 953 return false; 954 } 955 956 /* 957 * PTE_SYNC_CURRENT: 958 * 959 * Make sure the pte is written out to RAM. 960 * We need to do this for one of two cases: 961 * - We're dealing with the kernel pmap 962 * - There is no pmap active in the cache/tlb. 963 * - The specified pmap is 'active' in the cache/tlb. 964 */ 965 #ifdef PMAP_INCLUDE_PTE_SYNC 966 #define PTE_SYNC_CURRENT(pm, ptep) \ 967 do { \ 968 if (PMAP_NEEDS_PTE_SYNC && \ 969 pmap_is_cached(pm)) \ 970 PTE_SYNC(ptep); \ 971 } while (/*CONSTCOND*/0) 972 #else 973 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 974 #endif 975 976 /* 977 * main pv_entry manipulation functions: 978 * pmap_enter_pv: enter a mapping onto a vm_page list 979 * pmap_remove_pv: remove a mapping from a vm_page list 980 * 981 * NOTE: pmap_enter_pv expects to lock the pvh itself 982 * pmap_remove_pv expects the caller to lock the pvh before calling 983 */ 984 985 /* 986 * pmap_enter_pv: enter a mapping onto a vm_page lst 987 * 988 * => caller should hold the proper lock on pmap_main_lock 989 * => caller should have pmap locked 990 * => we will gain the lock on the vm_page and allocate the new pv_entry 991 * => caller should adjust ptp's wire_count before calling 992 * => caller should not adjust pmap's wire_count 993 */ 994 static void 995 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 996 vaddr_t va, u_int flags) 997 { 998 struct pv_entry **pvp; 999 1000 NPDEBUG(PDB_PVDUMP, 1001 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 1002 1003 pv->pv_pmap = pm; 1004 pv->pv_va = va; 1005 pv->pv_flags = flags; 1006 1007 pvp = &SLIST_FIRST(&md->pvh_list); 1008 #ifdef PMAP_CACHE_VIPT 1009 /* 1010 * Insert unmanaged entries, writeable first, at the head of 1011 * the pv list. 1012 */ 1013 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1014 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1015 pvp = &SLIST_NEXT(*pvp, pv_link); 1016 } 1017 if (!PV_IS_WRITE_P(flags)) { 1018 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1019 pvp = &SLIST_NEXT(*pvp, pv_link); 1020 } 1021 #endif 1022 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1023 *pvp = pv; /* ... locked list */ 1024 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1025 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1026 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1027 md->pvh_attrs |= PVF_KMOD; 1028 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1029 md->pvh_attrs |= PVF_DIRTY; 1030 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1031 #endif 1032 if (pm == pmap_kernel()) { 1033 PMAPCOUNT(kernel_mappings); 1034 if (flags & PVF_WRITE) 1035 md->krw_mappings++; 1036 else 1037 md->kro_mappings++; 1038 } else { 1039 if (flags & PVF_WRITE) 1040 md->urw_mappings++; 1041 else 1042 md->uro_mappings++; 1043 } 1044 1045 #ifdef PMAP_CACHE_VIPT 1046 #ifndef ARM_MMU_EXTENDED 1047 /* 1048 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1049 * do it here as well to keep the mappings & KVF_WRITE consistent. 1050 */ 1051 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1052 md->pvh_attrs |= PVF_WRITE; 1053 } 1054 #endif 1055 /* 1056 * If this is an exec mapping and its the first exec mapping 1057 * for this page, make sure to sync the I-cache. 1058 */ 1059 if (PV_IS_EXEC_P(flags)) { 1060 #ifndef ARM_MMU_EXTENDED 1061 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1062 pmap_syncicache_page(md, pa); 1063 PMAPCOUNT(exec_synced_map); 1064 } 1065 #endif 1066 PMAPCOUNT(exec_mappings); 1067 } 1068 #endif 1069 1070 PMAPCOUNT(mappings); 1071 1072 if (pv->pv_flags & PVF_WIRED) 1073 ++pm->pm_stats.wired_count; 1074 } 1075 1076 /* 1077 * 1078 * pmap_find_pv: Find a pv entry 1079 * 1080 * => caller should hold lock on vm_page 1081 */ 1082 static inline struct pv_entry * 1083 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1084 { 1085 struct pv_entry *pv; 1086 1087 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1088 if (pm == pv->pv_pmap && va == pv->pv_va) 1089 break; 1090 } 1091 1092 return (pv); 1093 } 1094 1095 /* 1096 * pmap_remove_pv: try to remove a mapping from a pv_list 1097 * 1098 * => caller should hold proper lock on pmap_main_lock 1099 * => pmap should be locked 1100 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1101 * => caller should adjust ptp's wire_count and free PTP if needed 1102 * => caller should NOT adjust pmap's wire_count 1103 * => we return the removed pv 1104 */ 1105 static struct pv_entry * 1106 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1107 { 1108 struct pv_entry *pv, **prevptr; 1109 1110 NPDEBUG(PDB_PVDUMP, 1111 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1112 1113 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1114 pv = *prevptr; 1115 1116 while (pv) { 1117 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1118 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1119 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1120 if (pv->pv_flags & PVF_WIRED) { 1121 --pm->pm_stats.wired_count; 1122 } 1123 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1124 if (pm == pmap_kernel()) { 1125 PMAPCOUNT(kernel_unmappings); 1126 if (pv->pv_flags & PVF_WRITE) 1127 md->krw_mappings--; 1128 else 1129 md->kro_mappings--; 1130 } else { 1131 if (pv->pv_flags & PVF_WRITE) 1132 md->urw_mappings--; 1133 else 1134 md->uro_mappings--; 1135 } 1136 1137 PMAPCOUNT(unmappings); 1138 #ifdef PMAP_CACHE_VIPT 1139 if (!(pv->pv_flags & PVF_WRITE)) 1140 break; 1141 /* 1142 * If this page has had an exec mapping, then if 1143 * this was the last mapping, discard the contents, 1144 * otherwise sync the i-cache for this page. 1145 */ 1146 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1147 #ifdef ARM_MMU_EXTENDED 1148 md->pvh_attrs &= ~PVF_EXEC; 1149 PMAPCOUNT(exec_discarded_unmap); 1150 #else 1151 if (SLIST_EMPTY(&md->pvh_list)) { 1152 md->pvh_attrs &= ~PVF_EXEC; 1153 PMAPCOUNT(exec_discarded_unmap); 1154 } else { 1155 pmap_syncicache_page(md, pa); 1156 PMAPCOUNT(exec_synced_unmap); 1157 } 1158 #endif /* ARM_MMU_EXTENDED */ 1159 } 1160 #endif /* PMAP_CACHE_VIPT */ 1161 break; 1162 } 1163 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1164 pv = *prevptr; /* advance */ 1165 } 1166 1167 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1168 /* 1169 * If we no longer have a WRITEABLE KENTRY at the head of list, 1170 * clear the KMOD attribute from the page. 1171 */ 1172 if (SLIST_FIRST(&md->pvh_list) == NULL 1173 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1174 md->pvh_attrs &= ~PVF_KMOD; 1175 1176 /* 1177 * If this was a writeable page and there are no more writeable 1178 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1179 * the contents to memory. 1180 */ 1181 if (arm_cache_prefer_mask != 0) { 1182 if (md->krw_mappings + md->urw_mappings == 0) 1183 md->pvh_attrs &= ~PVF_WRITE; 1184 PMAP_VALIDATE_MD_PAGE(md); 1185 } 1186 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1187 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1188 1189 return(pv); /* return removed pv */ 1190 } 1191 1192 /* 1193 * 1194 * pmap_modify_pv: Update pv flags 1195 * 1196 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1197 * => caller should NOT adjust pmap's wire_count 1198 * => caller must call pmap_vac_me_harder() if writable status of a page 1199 * may have changed. 1200 * => we return the old flags 1201 * 1202 * Modify a physical-virtual mapping in the pv table 1203 */ 1204 static u_int 1205 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1206 u_int clr_mask, u_int set_mask) 1207 { 1208 struct pv_entry *npv; 1209 u_int flags, oflags; 1210 1211 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1212 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1213 1214 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1215 return (0); 1216 1217 NPDEBUG(PDB_PVDUMP, 1218 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1219 1220 /* 1221 * There is at least one VA mapping this page. 1222 */ 1223 1224 if (clr_mask & (PVF_REF | PVF_MOD)) { 1225 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1226 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1227 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1228 md->pvh_attrs |= PVF_DIRTY; 1229 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1230 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1231 } 1232 1233 oflags = npv->pv_flags; 1234 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1235 1236 if ((flags ^ oflags) & PVF_WIRED) { 1237 if (flags & PVF_WIRED) 1238 ++pm->pm_stats.wired_count; 1239 else 1240 --pm->pm_stats.wired_count; 1241 } 1242 1243 if ((flags ^ oflags) & PVF_WRITE) { 1244 if (pm == pmap_kernel()) { 1245 if (flags & PVF_WRITE) { 1246 md->krw_mappings++; 1247 md->kro_mappings--; 1248 } else { 1249 md->kro_mappings++; 1250 md->krw_mappings--; 1251 } 1252 } else { 1253 if (flags & PVF_WRITE) { 1254 md->urw_mappings++; 1255 md->uro_mappings--; 1256 } else { 1257 md->uro_mappings++; 1258 md->urw_mappings--; 1259 } 1260 } 1261 } 1262 #ifdef PMAP_CACHE_VIPT 1263 if (arm_cache_prefer_mask != 0) { 1264 if (md->urw_mappings + md->krw_mappings == 0) { 1265 md->pvh_attrs &= ~PVF_WRITE; 1266 } else { 1267 md->pvh_attrs |= PVF_WRITE; 1268 } 1269 } 1270 #ifndef ARM_MMU_EXTENDED 1271 /* 1272 * We have two cases here: the first is from enter_pv (new exec 1273 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1274 * Since in latter, pmap_enter_pv won't do anything, we just have 1275 * to do what pmap_remove_pv would do. 1276 */ 1277 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1278 || (PV_IS_EXEC_P(md->pvh_attrs) 1279 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1280 pmap_syncicache_page(md, pa); 1281 PMAPCOUNT(exec_synced_remap); 1282 } 1283 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1284 #endif /* !ARM_MMU_EXTENDED */ 1285 #endif /* PMAP_CACHE_VIPT */ 1286 1287 PMAPCOUNT(remappings); 1288 1289 return (oflags); 1290 } 1291 1292 /* 1293 * Allocate an L1 translation table for the specified pmap. 1294 * This is called at pmap creation time. 1295 */ 1296 static void 1297 pmap_alloc_l1(pmap_t pm) 1298 { 1299 #ifdef ARM_MMU_EXTENDED 1300 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1301 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1302 struct vm_page *pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1303 #else 1304 struct vm_page *pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1305 #endif 1306 bool ok __diagused; 1307 KASSERT(pg != NULL); 1308 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1309 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1310 KASSERT(ok); 1311 KASSERT(va >= KERNEL_BASE); 1312 1313 #else 1314 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1315 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1316 UVM_KMF_WIRED|UVM_KMF_ZERO); 1317 KASSERT(va); 1318 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1319 #endif 1320 pm->pm_l1 = (pd_entry_t *)va; 1321 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1322 #else 1323 struct l1_ttable *l1; 1324 uint8_t domain; 1325 1326 /* 1327 * Remove the L1 at the head of the LRU list 1328 */ 1329 mutex_spin_enter(&l1_lru_lock); 1330 l1 = TAILQ_FIRST(&l1_lru_list); 1331 KDASSERT(l1 != NULL); 1332 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1333 1334 /* 1335 * Pick the first available domain number, and update 1336 * the link to the next number. 1337 */ 1338 domain = l1->l1_domain_first; 1339 l1->l1_domain_first = l1->l1_domain_free[domain]; 1340 1341 /* 1342 * If there are still free domain numbers in this L1, 1343 * put it back on the TAIL of the LRU list. 1344 */ 1345 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1346 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1347 1348 mutex_spin_exit(&l1_lru_lock); 1349 1350 /* 1351 * Fix up the relevant bits in the pmap structure 1352 */ 1353 pm->pm_l1 = l1; 1354 pm->pm_domain = domain + 1; 1355 #endif 1356 } 1357 1358 /* 1359 * Free an L1 translation table. 1360 * This is called at pmap destruction time. 1361 */ 1362 static void 1363 pmap_free_l1(pmap_t pm) 1364 { 1365 #ifdef ARM_MMU_EXTENDED 1366 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1367 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1368 uvm_pagefree(pg); 1369 #else 1370 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1371 #endif 1372 pm->pm_l1 = NULL; 1373 pm->pm_l1_pa = 0; 1374 #else 1375 struct l1_ttable *l1 = pm->pm_l1; 1376 1377 mutex_spin_enter(&l1_lru_lock); 1378 1379 /* 1380 * If this L1 is currently on the LRU list, remove it. 1381 */ 1382 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1383 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1384 1385 /* 1386 * Free up the domain number which was allocated to the pmap 1387 */ 1388 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1389 l1->l1_domain_first = pmap_domain(pm) - 1; 1390 l1->l1_domain_use_count--; 1391 1392 /* 1393 * The L1 now must have at least 1 free domain, so add 1394 * it back to the LRU list. If the use count is zero, 1395 * put it at the head of the list, otherwise it goes 1396 * to the tail. 1397 */ 1398 if (l1->l1_domain_use_count == 0) 1399 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1400 else 1401 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1402 1403 mutex_spin_exit(&l1_lru_lock); 1404 #endif /* ARM_MMU_EXTENDED */ 1405 } 1406 1407 #ifndef ARM_MMU_EXTENDED 1408 static inline void 1409 pmap_use_l1(pmap_t pm) 1410 { 1411 struct l1_ttable *l1; 1412 1413 /* 1414 * Do nothing if we're in interrupt context. 1415 * Access to an L1 by the kernel pmap must not affect 1416 * the LRU list. 1417 */ 1418 if (cpu_intr_p() || pm == pmap_kernel()) 1419 return; 1420 1421 l1 = pm->pm_l1; 1422 1423 /* 1424 * If the L1 is not currently on the LRU list, just return 1425 */ 1426 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1427 return; 1428 1429 mutex_spin_enter(&l1_lru_lock); 1430 1431 /* 1432 * Check the use count again, now that we've acquired the lock 1433 */ 1434 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1435 mutex_spin_exit(&l1_lru_lock); 1436 return; 1437 } 1438 1439 /* 1440 * Move the L1 to the back of the LRU list 1441 */ 1442 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1443 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1444 1445 mutex_spin_exit(&l1_lru_lock); 1446 } 1447 #endif /* !ARM_MMU_EXTENDED */ 1448 1449 /* 1450 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1451 * 1452 * Free an L2 descriptor table. 1453 */ 1454 static inline void 1455 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1456 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1457 #else 1458 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1459 #endif 1460 { 1461 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1462 /* 1463 * Note: With a write-back cache, we may need to sync this 1464 * L2 table before re-using it. 1465 * This is because it may have belonged to a non-current 1466 * pmap, in which case the cache syncs would have been 1467 * skipped for the pages that were being unmapped. If the 1468 * L2 table were then to be immediately re-allocated to 1469 * the *current* pmap, it may well contain stale mappings 1470 * which have not yet been cleared by a cache write-back 1471 * and so would still be visible to the mmu. 1472 */ 1473 if (need_sync) 1474 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1475 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1476 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1477 } 1478 1479 /* 1480 * Returns a pointer to the L2 bucket associated with the specified pmap 1481 * and VA, or NULL if no L2 bucket exists for the address. 1482 */ 1483 static inline struct l2_bucket * 1484 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1485 { 1486 const size_t l1slot = l1pte_index(va); 1487 struct l2_dtable *l2; 1488 struct l2_bucket *l2b; 1489 1490 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1491 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1492 return (NULL); 1493 1494 return (l2b); 1495 } 1496 1497 /* 1498 * Returns a pointer to the L2 bucket associated with the specified pmap 1499 * and VA. 1500 * 1501 * If no L2 bucket exists, perform the necessary allocations to put an L2 1502 * bucket/page table in place. 1503 * 1504 * Note that if a new L2 bucket/page was allocated, the caller *must* 1505 * increment the bucket occupancy counter appropriately *before* 1506 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1507 * the bucket/page in the meantime. 1508 */ 1509 static struct l2_bucket * 1510 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1511 { 1512 const size_t l1slot = l1pte_index(va); 1513 struct l2_dtable *l2; 1514 1515 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1516 /* 1517 * No mapping at this address, as there is 1518 * no entry in the L1 table. 1519 * Need to allocate a new l2_dtable. 1520 */ 1521 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1522 return (NULL); 1523 1524 /* 1525 * Link it into the parent pmap 1526 */ 1527 pm->pm_l2[L2_IDX(l1slot)] = l2; 1528 } 1529 1530 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1531 1532 /* 1533 * Fetch pointer to the L2 page table associated with the address. 1534 */ 1535 if (l2b->l2b_kva == NULL) { 1536 pt_entry_t *ptep; 1537 1538 /* 1539 * No L2 page table has been allocated. Chances are, this 1540 * is because we just allocated the l2_dtable, above. 1541 */ 1542 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1543 /* 1544 * Oops, no more L2 page tables available at this 1545 * time. We may need to deallocate the l2_dtable 1546 * if we allocated a new one above. 1547 */ 1548 if (l2->l2_occupancy == 0) { 1549 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1550 pmap_free_l2_dtable(l2); 1551 } 1552 return (NULL); 1553 } 1554 1555 l2->l2_occupancy++; 1556 l2b->l2b_kva = ptep; 1557 l2b->l2b_l1slot = l1slot; 1558 1559 #ifdef ARM_MMU_EXTENDED 1560 /* 1561 * We know there will be a mapping here, so simply 1562 * enter this PTP into the L1 now. 1563 */ 1564 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1565 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1566 | L1_C_DOM(pmap_domain(pm)); 1567 KASSERT(*pdep == 0); 1568 l1pte_setone(pdep, npde); 1569 PTE_SYNC(pdep); 1570 #endif 1571 } 1572 1573 return (l2b); 1574 } 1575 1576 /* 1577 * One or more mappings in the specified L2 descriptor table have just been 1578 * invalidated. 1579 * 1580 * Garbage collect the metadata and descriptor table itself if necessary. 1581 * 1582 * The pmap lock must be acquired when this is called (not necessary 1583 * for the kernel pmap). 1584 */ 1585 static void 1586 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1587 { 1588 KDASSERT(count <= l2b->l2b_occupancy); 1589 1590 /* 1591 * Update the bucket's reference count according to how many 1592 * PTEs the caller has just invalidated. 1593 */ 1594 l2b->l2b_occupancy -= count; 1595 1596 /* 1597 * Note: 1598 * 1599 * Level 2 page tables allocated to the kernel pmap are never freed 1600 * as that would require checking all Level 1 page tables and 1601 * removing any references to the Level 2 page table. See also the 1602 * comment elsewhere about never freeing bootstrap L2 descriptors. 1603 * 1604 * We make do with just invalidating the mapping in the L2 table. 1605 * 1606 * This isn't really a big deal in practice and, in fact, leads 1607 * to a performance win over time as we don't need to continually 1608 * alloc/free. 1609 */ 1610 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1611 return; 1612 1613 /* 1614 * There are no more valid mappings in this level 2 page table. 1615 * Go ahead and NULL-out the pointer in the bucket, then 1616 * free the page table. 1617 */ 1618 const size_t l1slot = l2b->l2b_l1slot; 1619 pt_entry_t * const ptep = l2b->l2b_kva; 1620 l2b->l2b_kva = NULL; 1621 1622 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1623 pd_entry_t pde __diagused = *pdep; 1624 1625 #ifdef ARM_MMU_EXTENDED 1626 /* 1627 * Invalidate the L1 slot. 1628 */ 1629 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1630 #else 1631 /* 1632 * If the L1 slot matches the pmap's domain number, then invalidate it. 1633 */ 1634 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1635 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1636 #endif 1637 l1pte_setone(pdep, 0); 1638 PDE_SYNC(pdep); 1639 #ifndef ARM_MMU_EXTENDED 1640 } 1641 #endif 1642 1643 /* 1644 * Release the L2 descriptor table back to the pool cache. 1645 */ 1646 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1647 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1648 #else 1649 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1650 #endif 1651 1652 /* 1653 * Update the reference count in the associated l2_dtable 1654 */ 1655 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1656 if (--l2->l2_occupancy > 0) 1657 return; 1658 1659 /* 1660 * There are no more valid mappings in any of the Level 1 1661 * slots managed by this l2_dtable. Go ahead and NULL-out 1662 * the pointer in the parent pmap and free the l2_dtable. 1663 */ 1664 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1665 pmap_free_l2_dtable(l2); 1666 } 1667 1668 /* 1669 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1670 * structures. 1671 */ 1672 static int 1673 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1674 { 1675 #ifndef PMAP_INCLUDE_PTE_SYNC 1676 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1677 1678 /* 1679 * The mappings for these page tables were initially made using 1680 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1681 * mode will not be right for page table mappings. To avoid 1682 * polluting the pmap_kenter_pa() code with a special case for 1683 * page tables, we simply fix up the cache-mode here if it's not 1684 * correct. 1685 */ 1686 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1687 const struct l2_bucket * const l2b = 1688 pmap_get_l2_bucket(pmap_kernel(), va); 1689 KASSERTMSG(l2b != NULL, "%#lx", va); 1690 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1691 const pt_entry_t opte = *ptep; 1692 1693 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1694 /* 1695 * Page tables must have the cache-mode set correctly. 1696 */ 1697 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1698 | pte_l2_s_cache_mode_pt; 1699 l2pte_set(ptep, npte, opte); 1700 PTE_SYNC(ptep); 1701 cpu_tlb_flushD_SE(va); 1702 cpu_cpwait(); 1703 } 1704 } 1705 #endif 1706 1707 memset(v, 0, L2_TABLE_SIZE_REAL); 1708 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1709 return (0); 1710 } 1711 1712 static int 1713 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1714 { 1715 1716 memset(v, 0, sizeof(struct l2_dtable)); 1717 return (0); 1718 } 1719 1720 static int 1721 pmap_pmap_ctor(void *arg, void *v, int flags) 1722 { 1723 1724 memset(v, 0, sizeof(struct pmap)); 1725 return (0); 1726 } 1727 1728 static void 1729 pmap_pinit(pmap_t pm) 1730 { 1731 #ifndef ARM_HAS_VBAR 1732 struct l2_bucket *l2b; 1733 1734 if (vector_page < KERNEL_BASE) { 1735 /* 1736 * Map the vector page. 1737 */ 1738 pmap_enter(pm, vector_page, systempage.pv_pa, 1739 VM_PROT_READ | VM_PROT_EXECUTE, 1740 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1741 pmap_update(pm); 1742 1743 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1744 l2b = pmap_get_l2_bucket(pm, vector_page); 1745 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1746 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1747 L1_C_DOM(pmap_domain(pm)); 1748 } else 1749 pm->pm_pl1vec = NULL; 1750 #endif 1751 } 1752 1753 #ifdef PMAP_CACHE_VIVT 1754 /* 1755 * Since we have a virtually indexed cache, we may need to inhibit caching if 1756 * there is more than one mapping and at least one of them is writable. 1757 * Since we purge the cache on every context switch, we only need to check for 1758 * other mappings within the same pmap, or kernel_pmap. 1759 * This function is also called when a page is unmapped, to possibly reenable 1760 * caching on any remaining mappings. 1761 * 1762 * The code implements the following logic, where: 1763 * 1764 * KW = # of kernel read/write pages 1765 * KR = # of kernel read only pages 1766 * UW = # of user read/write pages 1767 * UR = # of user read only pages 1768 * 1769 * KC = kernel mapping is cacheable 1770 * UC = user mapping is cacheable 1771 * 1772 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1773 * +--------------------------------------------- 1774 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1775 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1776 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1777 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1778 */ 1779 1780 static const int pmap_vac_flags[4][4] = { 1781 {-1, 0, 0, PVF_KNC}, 1782 {0, 0, PVF_NC, PVF_NC}, 1783 {0, PVF_NC, PVF_NC, PVF_NC}, 1784 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1785 }; 1786 1787 static inline int 1788 pmap_get_vac_flags(const struct vm_page_md *md) 1789 { 1790 int kidx, uidx; 1791 1792 kidx = 0; 1793 if (md->kro_mappings || md->krw_mappings > 1) 1794 kidx |= 1; 1795 if (md->krw_mappings) 1796 kidx |= 2; 1797 1798 uidx = 0; 1799 if (md->uro_mappings || md->urw_mappings > 1) 1800 uidx |= 1; 1801 if (md->urw_mappings) 1802 uidx |= 2; 1803 1804 return (pmap_vac_flags[uidx][kidx]); 1805 } 1806 1807 static inline void 1808 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1809 { 1810 int nattr; 1811 1812 nattr = pmap_get_vac_flags(md); 1813 1814 if (nattr < 0) { 1815 md->pvh_attrs &= ~PVF_NC; 1816 return; 1817 } 1818 1819 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1820 return; 1821 1822 if (pm == pmap_kernel()) 1823 pmap_vac_me_kpmap(md, pa, pm, va); 1824 else 1825 pmap_vac_me_user(md, pa, pm, va); 1826 1827 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1828 } 1829 1830 static void 1831 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1832 { 1833 u_int u_cacheable, u_entries; 1834 struct pv_entry *pv; 1835 pmap_t last_pmap = pm; 1836 1837 /* 1838 * Pass one, see if there are both kernel and user pmaps for 1839 * this page. Calculate whether there are user-writable or 1840 * kernel-writable pages. 1841 */ 1842 u_cacheable = 0; 1843 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1844 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1845 u_cacheable++; 1846 } 1847 1848 u_entries = md->urw_mappings + md->uro_mappings; 1849 1850 /* 1851 * We know we have just been updating a kernel entry, so if 1852 * all user pages are already cacheable, then there is nothing 1853 * further to do. 1854 */ 1855 if (md->k_mappings == 0 && u_cacheable == u_entries) 1856 return; 1857 1858 if (u_entries) { 1859 /* 1860 * Scan over the list again, for each entry, if it 1861 * might not be set correctly, call pmap_vac_me_user 1862 * to recalculate the settings. 1863 */ 1864 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1865 /* 1866 * We know kernel mappings will get set 1867 * correctly in other calls. We also know 1868 * that if the pmap is the same as last_pmap 1869 * then we've just handled this entry. 1870 */ 1871 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1872 continue; 1873 1874 /* 1875 * If there are kernel entries and this page 1876 * is writable but non-cacheable, then we can 1877 * skip this entry also. 1878 */ 1879 if (md->k_mappings && 1880 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1881 (PVF_NC | PVF_WRITE)) 1882 continue; 1883 1884 /* 1885 * Similarly if there are no kernel-writable 1886 * entries and the page is already 1887 * read-only/cacheable. 1888 */ 1889 if (md->krw_mappings == 0 && 1890 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1891 continue; 1892 1893 /* 1894 * For some of the remaining cases, we know 1895 * that we must recalculate, but for others we 1896 * can't tell if they are correct or not, so 1897 * we recalculate anyway. 1898 */ 1899 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1900 } 1901 1902 if (md->k_mappings == 0) 1903 return; 1904 } 1905 1906 pmap_vac_me_user(md, pa, pm, va); 1907 } 1908 1909 static void 1910 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1911 { 1912 pmap_t kpmap = pmap_kernel(); 1913 struct pv_entry *pv, *npv = NULL; 1914 u_int entries = 0; 1915 u_int writable = 0; 1916 u_int cacheable_entries = 0; 1917 u_int kern_cacheable = 0; 1918 u_int other_writable = 0; 1919 1920 /* 1921 * Count mappings and writable mappings in this pmap. 1922 * Include kernel mappings as part of our own. 1923 * Keep a pointer to the first one. 1924 */ 1925 npv = NULL; 1926 KASSERT(pmap_page_locked_p(md)); 1927 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1928 /* Count mappings in the same pmap */ 1929 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1930 if (entries++ == 0) 1931 npv = pv; 1932 1933 /* Cacheable mappings */ 1934 if ((pv->pv_flags & PVF_NC) == 0) { 1935 cacheable_entries++; 1936 if (kpmap == pv->pv_pmap) 1937 kern_cacheable++; 1938 } 1939 1940 /* Writable mappings */ 1941 if (pv->pv_flags & PVF_WRITE) 1942 ++writable; 1943 } else 1944 if (pv->pv_flags & PVF_WRITE) 1945 other_writable = 1; 1946 } 1947 1948 /* 1949 * Enable or disable caching as necessary. 1950 * Note: the first entry might be part of the kernel pmap, 1951 * so we can't assume this is indicative of the state of the 1952 * other (maybe non-kpmap) entries. 1953 */ 1954 if ((entries > 1 && writable) || 1955 (entries > 0 && pm == kpmap && other_writable)) { 1956 if (cacheable_entries == 0) { 1957 return; 1958 } 1959 1960 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1961 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1962 (pv->pv_flags & PVF_NC)) 1963 continue; 1964 1965 pv->pv_flags |= PVF_NC; 1966 1967 struct l2_bucket * const l2b 1968 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1969 KASSERTMSG(l2b != NULL, "%#lx", va); 1970 pt_entry_t * const ptep 1971 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1972 const pt_entry_t opte = *ptep; 1973 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1974 1975 if ((va != pv->pv_va || pm != pv->pv_pmap) 1976 && l2pte_valid_p(npte)) { 1977 #ifdef PMAP_CACHE_VIVT 1978 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1979 true, pv->pv_flags); 1980 #endif 1981 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1982 pv->pv_flags); 1983 } 1984 1985 l2pte_set(ptep, npte, opte); 1986 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1987 } 1988 cpu_cpwait(); 1989 } else 1990 if (entries > cacheable_entries) { 1991 /* 1992 * Turn cacheing back on for some pages. If it is a kernel 1993 * page, only do so if there are no other writable pages. 1994 */ 1995 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1996 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1997 (kpmap != pv->pv_pmap || other_writable))) 1998 continue; 1999 2000 pv->pv_flags &= ~PVF_NC; 2001 2002 struct l2_bucket * const l2b 2003 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2004 KASSERTMSG(l2b != NULL, "%#lx", va); 2005 pt_entry_t * const ptep 2006 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2007 const pt_entry_t opte = *ptep; 2008 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2009 | pte_l2_s_cache_mode; 2010 2011 if (l2pte_valid_p(opte)) { 2012 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2013 pv->pv_flags); 2014 } 2015 2016 l2pte_set(ptep, npte, opte); 2017 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2018 } 2019 } 2020 } 2021 #endif 2022 2023 #ifdef PMAP_CACHE_VIPT 2024 static void 2025 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2026 { 2027 #ifndef ARM_MMU_EXTENDED 2028 struct pv_entry *pv; 2029 vaddr_t tst_mask; 2030 bool bad_alias; 2031 const u_int 2032 rw_mappings = md->urw_mappings + md->krw_mappings, 2033 ro_mappings = md->uro_mappings + md->kro_mappings; 2034 2035 /* do we need to do anything? */ 2036 if (arm_cache_prefer_mask == 0) 2037 return; 2038 2039 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2040 md, pm, va)); 2041 2042 KASSERT(!va || pm); 2043 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2044 2045 /* Already a conflict? */ 2046 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2047 /* just an add, things are already non-cached */ 2048 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2049 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2050 bad_alias = false; 2051 if (va) { 2052 PMAPCOUNT(vac_color_none); 2053 bad_alias = true; 2054 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2055 goto fixup; 2056 } 2057 pv = SLIST_FIRST(&md->pvh_list); 2058 /* the list can't be empty because it would be cachable */ 2059 if (md->pvh_attrs & PVF_KMPAGE) { 2060 tst_mask = md->pvh_attrs; 2061 } else { 2062 KASSERT(pv); 2063 tst_mask = pv->pv_va; 2064 pv = SLIST_NEXT(pv, pv_link); 2065 } 2066 /* 2067 * Only check for a bad alias if we have writable mappings. 2068 */ 2069 tst_mask &= arm_cache_prefer_mask; 2070 if (rw_mappings > 0) { 2071 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2072 /* if there's a bad alias, stop checking. */ 2073 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2074 bad_alias = true; 2075 } 2076 md->pvh_attrs |= PVF_WRITE; 2077 if (!bad_alias) 2078 md->pvh_attrs |= PVF_DIRTY; 2079 } else { 2080 /* 2081 * We have only read-only mappings. Let's see if there 2082 * are multiple colors in use or if we mapped a KMPAGE. 2083 * If the latter, we have a bad alias. If the former, 2084 * we need to remember that. 2085 */ 2086 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2087 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2088 if (md->pvh_attrs & PVF_KMPAGE) 2089 bad_alias = true; 2090 break; 2091 } 2092 } 2093 md->pvh_attrs &= ~PVF_WRITE; 2094 /* 2095 * No KMPAGE and we exited early, so we must have 2096 * multiple color mappings. 2097 */ 2098 if (!bad_alias && pv != NULL) 2099 md->pvh_attrs |= PVF_MULTCLR; 2100 } 2101 2102 /* If no conflicting colors, set everything back to cached */ 2103 if (!bad_alias) { 2104 #ifdef DEBUG 2105 if ((md->pvh_attrs & PVF_WRITE) 2106 || ro_mappings < 2) { 2107 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2108 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2109 } 2110 #endif 2111 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2112 md->pvh_attrs |= tst_mask | PVF_COLORED; 2113 /* 2114 * Restore DIRTY bit if page is modified 2115 */ 2116 if (md->pvh_attrs & PVF_DMOD) 2117 md->pvh_attrs |= PVF_DIRTY; 2118 PMAPCOUNT(vac_color_restore); 2119 } else { 2120 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2121 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2122 } 2123 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2124 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2125 } else if (!va) { 2126 KASSERT(pmap_is_page_colored_p(md)); 2127 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2128 || (md->pvh_attrs & PVF_DIRTY)); 2129 if (rw_mappings == 0) { 2130 md->pvh_attrs &= ~PVF_WRITE; 2131 if (ro_mappings == 1 2132 && (md->pvh_attrs & PVF_MULTCLR)) { 2133 /* 2134 * If this is the last readonly mapping 2135 * but it doesn't match the current color 2136 * for the page, change the current color 2137 * to match this last readonly mapping. 2138 */ 2139 pv = SLIST_FIRST(&md->pvh_list); 2140 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2141 & arm_cache_prefer_mask; 2142 if (tst_mask) { 2143 md->pvh_attrs ^= tst_mask; 2144 PMAPCOUNT(vac_color_change); 2145 } 2146 } 2147 } 2148 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2149 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2150 return; 2151 } else if (!pmap_is_page_colored_p(md)) { 2152 /* not colored so we just use its color */ 2153 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2154 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2155 PMAPCOUNT(vac_color_new); 2156 md->pvh_attrs &= PAGE_SIZE - 1; 2157 md->pvh_attrs |= PVF_COLORED 2158 | (va & arm_cache_prefer_mask) 2159 | (rw_mappings > 0 ? PVF_WRITE : 0); 2160 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2161 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2162 return; 2163 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2164 bad_alias = false; 2165 if (rw_mappings > 0) { 2166 /* 2167 * We now have writeable mappings and if we have 2168 * readonly mappings in more than once color, we have 2169 * an aliasing problem. Regardless mark the page as 2170 * writeable. 2171 */ 2172 if (md->pvh_attrs & PVF_MULTCLR) { 2173 if (ro_mappings < 2) { 2174 /* 2175 * If we only have less than two 2176 * read-only mappings, just flush the 2177 * non-primary colors from the cache. 2178 */ 2179 pmap_flush_page(md, pa, 2180 PMAP_FLUSH_SECONDARY); 2181 } else { 2182 bad_alias = true; 2183 } 2184 } 2185 md->pvh_attrs |= PVF_WRITE; 2186 } 2187 /* If no conflicting colors, set everything back to cached */ 2188 if (!bad_alias) { 2189 #ifdef DEBUG 2190 if (rw_mappings > 0 2191 || (md->pvh_attrs & PMAP_KMPAGE)) { 2192 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2193 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2194 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2195 } 2196 #endif 2197 if (SLIST_EMPTY(&md->pvh_list)) 2198 PMAPCOUNT(vac_color_reuse); 2199 else 2200 PMAPCOUNT(vac_color_ok); 2201 2202 /* matching color, just return */ 2203 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2204 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2205 return; 2206 } 2207 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2208 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2209 2210 /* color conflict. evict from cache. */ 2211 2212 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2213 md->pvh_attrs &= ~PVF_COLORED; 2214 md->pvh_attrs |= PVF_NC; 2215 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2216 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2217 PMAPCOUNT(vac_color_erase); 2218 } else if (rw_mappings == 0 2219 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2220 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2221 2222 /* 2223 * If the page has dirty cache lines, clean it. 2224 */ 2225 if (md->pvh_attrs & PVF_DIRTY) 2226 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2227 2228 /* 2229 * If this is the first remapping (we know that there are no 2230 * writeable mappings), then this is a simple color change. 2231 * Otherwise this is a seconary r/o mapping, which means 2232 * we don't have to do anything. 2233 */ 2234 if (ro_mappings == 1) { 2235 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2236 md->pvh_attrs &= PAGE_SIZE - 1; 2237 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2238 PMAPCOUNT(vac_color_change); 2239 } else { 2240 PMAPCOUNT(vac_color_blind); 2241 } 2242 md->pvh_attrs |= PVF_MULTCLR; 2243 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2244 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2245 return; 2246 } else { 2247 if (rw_mappings > 0) 2248 md->pvh_attrs |= PVF_WRITE; 2249 2250 /* color conflict. evict from cache. */ 2251 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2252 2253 /* the list can't be empty because this was a enter/modify */ 2254 pv = SLIST_FIRST(&md->pvh_list); 2255 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2256 KASSERT(pv); 2257 /* 2258 * If there's only one mapped page, change color to the 2259 * page's new color and return. Restore the DIRTY bit 2260 * that was erased by pmap_flush_page. 2261 */ 2262 if (SLIST_NEXT(pv, pv_link) == NULL) { 2263 md->pvh_attrs &= PAGE_SIZE - 1; 2264 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2265 if (md->pvh_attrs & PVF_DMOD) 2266 md->pvh_attrs |= PVF_DIRTY; 2267 PMAPCOUNT(vac_color_change); 2268 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2269 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2270 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2271 return; 2272 } 2273 } 2274 bad_alias = true; 2275 md->pvh_attrs &= ~PVF_COLORED; 2276 md->pvh_attrs |= PVF_NC; 2277 PMAPCOUNT(vac_color_erase); 2278 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2279 } 2280 2281 fixup: 2282 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2283 2284 /* 2285 * Turn cacheing on/off for all pages. 2286 */ 2287 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2288 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2289 pv->pv_va); 2290 KASSERTMSG(l2b != NULL, "%#lx", va); 2291 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2292 const pt_entry_t opte = *ptep; 2293 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2294 if (bad_alias) { 2295 pv->pv_flags |= PVF_NC; 2296 } else { 2297 pv->pv_flags &= ~PVF_NC; 2298 npte |= pte_l2_s_cache_mode; 2299 } 2300 2301 if (opte == npte) /* only update is there's a change */ 2302 continue; 2303 2304 if (l2pte_valid_p(npte)) { 2305 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2306 } 2307 2308 l2pte_set(ptep, npte, opte); 2309 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2310 } 2311 #endif /* !ARM_MMU_EXTENDED */ 2312 } 2313 #endif /* PMAP_CACHE_VIPT */ 2314 2315 2316 /* 2317 * Modify pte bits for all ptes corresponding to the given physical address. 2318 * We use `maskbits' rather than `clearbits' because we're always passing 2319 * constants and the latter would require an extra inversion at run-time. 2320 */ 2321 static void 2322 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2323 { 2324 struct pv_entry *pv; 2325 #ifdef PMAP_CACHE_VIPT 2326 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2327 #ifdef ARM_MMU_EXTENDED 2328 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2329 #else 2330 const u_int execbits = 0; 2331 bool need_vac_me_harder = false; 2332 bool need_syncicache = false; 2333 #endif 2334 #else 2335 const u_int execbits = 0; 2336 #endif 2337 2338 NPDEBUG(PDB_BITS, 2339 printf("pmap_clearbit: md %p mask 0x%x\n", 2340 md, maskbits)); 2341 2342 #ifdef PMAP_CACHE_VIPT 2343 /* 2344 * If we might want to sync the I-cache and we've modified it, 2345 * then we know we definitely need to sync or discard it. 2346 */ 2347 if (want_syncicache) { 2348 #ifdef ARM_MMU_EXTENDED 2349 if (md->pvh_attrs & PVF_MOD) 2350 md->pvh_attrs &= ~PVF_EXEC; 2351 #else 2352 need_syncicache = md->pvh_attrs & PVF_MOD; 2353 #endif 2354 } 2355 #endif 2356 KASSERT(pmap_page_locked_p(md)); 2357 2358 /* 2359 * Clear saved attributes (modify, reference) 2360 */ 2361 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2362 2363 if (SLIST_EMPTY(&md->pvh_list)) { 2364 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2365 if (need_syncicache) { 2366 /* 2367 * No one has it mapped, so just discard it. The next 2368 * exec remapping will cause it to be synced. 2369 */ 2370 md->pvh_attrs &= ~PVF_EXEC; 2371 PMAPCOUNT(exec_discarded_clearbit); 2372 } 2373 #endif 2374 return; 2375 } 2376 2377 /* 2378 * Loop over all current mappings setting/clearing as appropos 2379 */ 2380 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2381 pmap_t pm = pv->pv_pmap; 2382 const vaddr_t va = pv->pv_va; 2383 const u_int oflags = pv->pv_flags; 2384 #ifndef ARM_MMU_EXTENDED 2385 /* 2386 * Kernel entries are unmanaged and as such not to be changed. 2387 */ 2388 if (PV_IS_KENTRY_P(oflags)) 2389 continue; 2390 #endif 2391 pv->pv_flags &= ~maskbits; 2392 2393 pmap_release_page_lock(md); 2394 pmap_acquire_pmap_lock(pm); 2395 2396 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2397 if (l2b == NULL) { 2398 pmap_release_pmap_lock(pm); 2399 pmap_acquire_page_lock(md); 2400 continue; 2401 } 2402 KASSERTMSG(l2b != NULL, "%#lx", va); 2403 2404 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2405 const pt_entry_t opte = *ptep; 2406 pt_entry_t npte = opte | execbits; 2407 2408 #ifdef ARM_MMU_EXTENDED 2409 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2410 #endif 2411 2412 NPDEBUG(PDB_BITS, 2413 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2414 __func__, pv, pm, va, oflags)); 2415 2416 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2417 #ifdef PMAP_CACHE_VIVT 2418 if ((oflags & PVF_NC)) { 2419 /* 2420 * Entry is not cacheable: 2421 * 2422 * Don't turn caching on again if this is a 2423 * modified emulation. This would be 2424 * inconsitent with the settings created by 2425 * pmap_vac_me_harder(). Otherwise, it's safe 2426 * to re-enable cacheing. 2427 * 2428 * There's no need to call pmap_vac_me_harder() 2429 * here: all pages are losing their write 2430 * permission. 2431 */ 2432 if (maskbits & PVF_WRITE) { 2433 npte |= pte_l2_s_cache_mode; 2434 pv->pv_flags &= ~PVF_NC; 2435 } 2436 } else 2437 if (l2pte_writable_p(opte)) { 2438 /* 2439 * Entry is writable/cacheable: check if pmap 2440 * is current if it is flush it, otherwise it 2441 * won't be in the cache 2442 */ 2443 pmap_cache_wbinv_page(pm, va, 2444 (maskbits & PVF_REF) != 0, 2445 oflags|PVF_WRITE); 2446 } 2447 #endif 2448 2449 /* make the pte read only */ 2450 npte = l2pte_set_readonly(npte); 2451 2452 pmap_acquire_page_lock(md); 2453 #ifdef MULTIPROCESSOR 2454 pv = pmap_find_pv(md, pm, va); 2455 #endif 2456 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2457 /* 2458 * Keep alias accounting up to date 2459 */ 2460 if (pm == pmap_kernel()) { 2461 md->krw_mappings--; 2462 md->kro_mappings++; 2463 } else { 2464 md->urw_mappings--; 2465 md->uro_mappings++; 2466 } 2467 #ifdef PMAP_CACHE_VIPT 2468 if (arm_cache_prefer_mask != 0) { 2469 if (md->urw_mappings + md->krw_mappings == 0) { 2470 md->pvh_attrs &= ~PVF_WRITE; 2471 } else { 2472 PMAP_VALIDATE_MD_PAGE(md); 2473 } 2474 } 2475 #ifndef ARM_MMU_EXTENDED 2476 if (want_syncicache) 2477 need_syncicache = true; 2478 need_vac_me_harder = true; 2479 #endif 2480 #endif /* PMAP_CACHE_VIPT */ 2481 } 2482 pmap_release_page_lock(md); 2483 } 2484 2485 if (maskbits & PVF_REF) { 2486 if (true 2487 #ifndef ARM_MMU_EXTENDED 2488 && (oflags & PVF_NC) == 0 2489 #endif 2490 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2491 && l2pte_valid_p(npte)) { 2492 #ifdef PMAP_CACHE_VIVT 2493 /* 2494 * Check npte here; we may have already 2495 * done the wbinv above, and the validity 2496 * of the PTE is the same for opte and 2497 * npte. 2498 */ 2499 pmap_cache_wbinv_page(pm, va, true, oflags); 2500 #endif 2501 } 2502 2503 /* 2504 * Make the PTE invalid so that we will take a 2505 * page fault the next time the mapping is 2506 * referenced. 2507 */ 2508 npte &= ~L2_TYPE_MASK; 2509 npte |= L2_TYPE_INV; 2510 } 2511 2512 if (npte != opte) { 2513 l2pte_set(ptep, npte, opte); 2514 PTE_SYNC(ptep); 2515 2516 /* Flush the TLB entry if a current pmap. */ 2517 pmap_tlb_flush_SE(pm, va, oflags); 2518 } 2519 2520 pmap_release_pmap_lock(pm); 2521 pmap_acquire_page_lock(md); 2522 2523 NPDEBUG(PDB_BITS, 2524 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2525 pm, va, opte, npte)); 2526 } 2527 2528 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2529 /* 2530 * If we need to sync the I-cache and we haven't done it yet, do it. 2531 */ 2532 if (need_syncicache) { 2533 pmap_release_page_lock(md); 2534 pmap_syncicache_page(md, pa); 2535 pmap_acquire_page_lock(md); 2536 PMAPCOUNT(exec_synced_clearbit); 2537 } 2538 2539 /* 2540 * If we are changing this to read-only, we need to call vac_me_harder 2541 * so we can change all the read-only pages to cacheable. We pretend 2542 * this as a page deletion. 2543 */ 2544 if (need_vac_me_harder) { 2545 if (md->pvh_attrs & PVF_NC) 2546 pmap_vac_me_harder(md, pa, NULL, 0); 2547 } 2548 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2549 } 2550 2551 /* 2552 * pmap_clean_page() 2553 * 2554 * This is a local function used to work out the best strategy to clean 2555 * a single page referenced by its entry in the PV table. It's used by 2556 * pmap_copy_page, pmap_zero page and maybe some others later on. 2557 * 2558 * Its policy is effectively: 2559 * o If there are no mappings, we don't bother doing anything with the cache. 2560 * o If there is one mapping, we clean just that page. 2561 * o If there are multiple mappings, we clean the entire cache. 2562 * 2563 * So that some functions can be further optimised, it returns 0 if it didn't 2564 * clean the entire cache, or 1 if it did. 2565 * 2566 * XXX One bug in this routine is that if the pv_entry has a single page 2567 * mapped at 0x00000000 a whole cache clean will be performed rather than 2568 * just the 1 page. Since this should not occur in everyday use and if it does 2569 * it will just result in not the most efficient clean for the page. 2570 */ 2571 #ifdef PMAP_CACHE_VIVT 2572 static bool 2573 pmap_clean_page(struct vm_page_md *md, bool is_src) 2574 { 2575 struct pv_entry *pv; 2576 pmap_t pm_to_clean = NULL; 2577 bool cache_needs_cleaning = false; 2578 vaddr_t page_to_clean = 0; 2579 u_int flags = 0; 2580 2581 /* 2582 * Since we flush the cache each time we change to a different 2583 * user vmspace, we only need to flush the page if it is in the 2584 * current pmap. 2585 */ 2586 KASSERT(pmap_page_locked_p(md)); 2587 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2588 if (pmap_is_current(pv->pv_pmap)) { 2589 flags |= pv->pv_flags; 2590 /* 2591 * The page is mapped non-cacheable in 2592 * this map. No need to flush the cache. 2593 */ 2594 if (pv->pv_flags & PVF_NC) { 2595 #ifdef DIAGNOSTIC 2596 KASSERT(!cache_needs_cleaning); 2597 #endif 2598 break; 2599 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2600 continue; 2601 if (cache_needs_cleaning) { 2602 page_to_clean = 0; 2603 break; 2604 } else { 2605 page_to_clean = pv->pv_va; 2606 pm_to_clean = pv->pv_pmap; 2607 } 2608 cache_needs_cleaning = true; 2609 } 2610 } 2611 2612 if (page_to_clean) { 2613 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2614 !is_src, flags | PVF_REF); 2615 } else if (cache_needs_cleaning) { 2616 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2617 2618 pmap_cache_wbinv_all(pm, flags); 2619 return true; 2620 } 2621 return false; 2622 } 2623 #endif 2624 2625 #ifdef PMAP_CACHE_VIPT 2626 /* 2627 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2628 * right cache alias to make sure we flush the right stuff. 2629 */ 2630 void 2631 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2632 { 2633 pmap_t kpm = pmap_kernel(); 2634 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2635 ? PAGE_SIZE 2636 : arm_pcache.icache_way_size; 2637 2638 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2639 md, md->pvh_attrs)); 2640 /* 2641 * No need to clean the page if it's non-cached. 2642 */ 2643 #ifndef ARM_MMU_EXTENDED 2644 if (md->pvh_attrs & PVF_NC) 2645 return; 2646 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2647 #endif 2648 2649 pt_entry_t * const ptep = cpu_cdst_pte(0); 2650 const vaddr_t dstp = cpu_cdstp(0); 2651 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2652 if (way_size <= PAGE_SIZE) { 2653 bool ok = false; 2654 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2655 if (ok) { 2656 cpu_icache_sync_range(vdstp, way_size); 2657 return; 2658 } 2659 } 2660 #endif 2661 2662 /* 2663 * We don't worry about the color of the exec page, we map the 2664 * same page to pages in the way and then do the icache_sync on 2665 * the entire way making sure we are cleaned. 2666 */ 2667 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2668 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2669 2670 for (size_t i = 0, j = 0; i < way_size; 2671 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2672 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2673 /* 2674 * Set up a PTE with to flush these cache lines. 2675 */ 2676 l2pte_set(ptep + j, npte, 0); 2677 } 2678 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2679 2680 /* 2681 * Flush it. 2682 */ 2683 cpu_icache_sync_range(dstp, way_size); 2684 2685 for (size_t i = 0, j = 0; i < way_size; 2686 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2687 /* 2688 * Unmap the page(s). 2689 */ 2690 l2pte_reset(ptep + j); 2691 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2692 } 2693 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2694 2695 md->pvh_attrs |= PVF_EXEC; 2696 PMAPCOUNT(exec_synced); 2697 } 2698 2699 #ifndef ARM_MMU_EXTENDED 2700 void 2701 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2702 { 2703 vsize_t va_offset, end_va; 2704 bool wbinv_p; 2705 2706 if (arm_cache_prefer_mask == 0) 2707 return; 2708 2709 switch (flush) { 2710 case PMAP_FLUSH_PRIMARY: 2711 if (md->pvh_attrs & PVF_MULTCLR) { 2712 va_offset = 0; 2713 end_va = arm_cache_prefer_mask; 2714 md->pvh_attrs &= ~PVF_MULTCLR; 2715 PMAPCOUNT(vac_flush_lots); 2716 } else { 2717 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2718 end_va = va_offset; 2719 PMAPCOUNT(vac_flush_one); 2720 } 2721 /* 2722 * Mark that the page is no longer dirty. 2723 */ 2724 md->pvh_attrs &= ~PVF_DIRTY; 2725 wbinv_p = true; 2726 break; 2727 case PMAP_FLUSH_SECONDARY: 2728 va_offset = 0; 2729 end_va = arm_cache_prefer_mask; 2730 wbinv_p = true; 2731 md->pvh_attrs &= ~PVF_MULTCLR; 2732 PMAPCOUNT(vac_flush_lots); 2733 break; 2734 case PMAP_CLEAN_PRIMARY: 2735 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2736 end_va = va_offset; 2737 wbinv_p = false; 2738 /* 2739 * Mark that the page is no longer dirty. 2740 */ 2741 if ((md->pvh_attrs & PVF_DMOD) == 0) 2742 md->pvh_attrs &= ~PVF_DIRTY; 2743 PMAPCOUNT(vac_clean_one); 2744 break; 2745 default: 2746 return; 2747 } 2748 2749 KASSERT(!(md->pvh_attrs & PVF_NC)); 2750 2751 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2752 md, md->pvh_attrs)); 2753 2754 const size_t scache_line_size = arm_scache.dcache_line_size; 2755 2756 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2757 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2758 const vaddr_t dstp = cpu_cdstp(va_offset); 2759 const pt_entry_t opte = *ptep; 2760 2761 if (flush == PMAP_FLUSH_SECONDARY 2762 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2763 continue; 2764 2765 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2766 /* 2767 * Set up a PTE with the right coloring to flush 2768 * existing cache entries. 2769 */ 2770 const pt_entry_t npte = L2_S_PROTO 2771 | pa 2772 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2773 | pte_l2_s_cache_mode; 2774 l2pte_set(ptep, npte, opte); 2775 PTE_SYNC(ptep); 2776 2777 /* 2778 * Flush it. Make sure to flush secondary cache too since 2779 * bus_dma will ignore uncached pages. 2780 */ 2781 if (scache_line_size != 0) { 2782 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2783 if (wbinv_p) { 2784 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2785 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2786 } else { 2787 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2788 } 2789 } else { 2790 if (wbinv_p) { 2791 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2792 } else { 2793 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2794 } 2795 } 2796 2797 /* 2798 * Restore the page table entry since we might have interrupted 2799 * pmap_zero_page or pmap_copy_page which was already using 2800 * this pte. 2801 */ 2802 if (opte) { 2803 l2pte_set(ptep, opte, npte); 2804 } else { 2805 l2pte_reset(ptep); 2806 } 2807 PTE_SYNC(ptep); 2808 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2809 } 2810 } 2811 #endif /* ARM_MMU_EXTENDED */ 2812 #endif /* PMAP_CACHE_VIPT */ 2813 2814 /* 2815 * Routine: pmap_page_remove 2816 * Function: 2817 * Removes this physical page from 2818 * all physical maps in which it resides. 2819 * Reflects back modify bits to the pager. 2820 */ 2821 static void 2822 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2823 { 2824 struct l2_bucket *l2b; 2825 struct pv_entry *pv; 2826 pt_entry_t *ptep; 2827 #ifndef ARM_MMU_EXTENDED 2828 bool flush = false; 2829 #endif 2830 u_int flags = 0; 2831 2832 NPDEBUG(PDB_FOLLOW, 2833 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2834 pa)); 2835 2836 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2837 pmap_acquire_page_lock(md); 2838 if (*pvp == NULL) { 2839 #ifdef PMAP_CACHE_VIPT 2840 /* 2841 * We *know* the page contents are about to be replaced. 2842 * Discard the exec contents 2843 */ 2844 if (PV_IS_EXEC_P(md->pvh_attrs)) 2845 PMAPCOUNT(exec_discarded_page_protect); 2846 md->pvh_attrs &= ~PVF_EXEC; 2847 PMAP_VALIDATE_MD_PAGE(md); 2848 #endif 2849 pmap_release_page_lock(md); 2850 return; 2851 } 2852 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2853 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2854 #endif 2855 2856 /* 2857 * Clear alias counts 2858 */ 2859 #ifdef PMAP_CACHE_VIVT 2860 md->k_mappings = 0; 2861 #endif 2862 md->urw_mappings = md->uro_mappings = 0; 2863 2864 #ifdef PMAP_CACHE_VIVT 2865 pmap_clean_page(md, false); 2866 #endif 2867 2868 while ((pv = *pvp) != NULL) { 2869 pmap_t pm = pv->pv_pmap; 2870 #ifndef ARM_MMU_EXTENDED 2871 if (flush == false && pmap_is_current(pm)) 2872 flush = true; 2873 #endif 2874 2875 if (pm == pmap_kernel()) { 2876 #ifdef PMAP_CACHE_VIPT 2877 /* 2878 * If this was unmanaged mapping, it must be preserved. 2879 * Move it back on the list and advance the end-of-list 2880 * pointer. 2881 */ 2882 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2883 *pvp = pv; 2884 pvp = &SLIST_NEXT(pv, pv_link); 2885 continue; 2886 } 2887 if (pv->pv_flags & PVF_WRITE) 2888 md->krw_mappings--; 2889 else 2890 md->kro_mappings--; 2891 #endif 2892 PMAPCOUNT(kernel_unmappings); 2893 } 2894 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2895 PMAPCOUNT(unmappings); 2896 2897 pmap_release_page_lock(md); 2898 pmap_acquire_pmap_lock(pm); 2899 2900 #ifdef ARM_MMU_EXTENDED 2901 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2902 #endif 2903 2904 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2905 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2906 2907 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2908 2909 /* 2910 * Update statistics 2911 */ 2912 --pm->pm_stats.resident_count; 2913 2914 /* Wired bit */ 2915 if (pv->pv_flags & PVF_WIRED) 2916 --pm->pm_stats.wired_count; 2917 2918 flags |= pv->pv_flags; 2919 2920 /* 2921 * Invalidate the PTEs. 2922 */ 2923 l2pte_reset(ptep); 2924 PTE_SYNC_CURRENT(pm, ptep); 2925 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2926 pmap_release_pmap_lock(pm); 2927 2928 pool_put(&pmap_pv_pool, pv); 2929 pmap_acquire_page_lock(md); 2930 #ifdef MULTIPROCESSOR 2931 /* 2932 * Restart of the beginning of the list. 2933 */ 2934 pvp = &SLIST_FIRST(&md->pvh_list); 2935 #endif 2936 } 2937 /* 2938 * if we reach the end of the list and there are still mappings, they 2939 * might be able to be cached now. And they must be kernel mappings. 2940 */ 2941 if (!SLIST_EMPTY(&md->pvh_list)) { 2942 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2943 } 2944 2945 #ifdef PMAP_CACHE_VIPT 2946 /* 2947 * Its EXEC cache is now gone. 2948 */ 2949 if (PV_IS_EXEC_P(md->pvh_attrs)) 2950 PMAPCOUNT(exec_discarded_page_protect); 2951 md->pvh_attrs &= ~PVF_EXEC; 2952 KASSERT(md->urw_mappings == 0); 2953 KASSERT(md->uro_mappings == 0); 2954 #ifndef ARM_MMU_EXTENDED 2955 if (arm_cache_prefer_mask != 0) { 2956 if (md->krw_mappings == 0) 2957 md->pvh_attrs &= ~PVF_WRITE; 2958 PMAP_VALIDATE_MD_PAGE(md); 2959 } 2960 #endif /* ARM_MMU_EXTENDED */ 2961 #endif /* PMAP_CACHE_VIPT */ 2962 pmap_release_page_lock(md); 2963 2964 #ifndef ARM_MMU_EXTENDED 2965 if (flush) { 2966 /* 2967 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2968 * would need a subsequent call to pmap_update() to ensure 2969 * curpm->pm_cstate.cs_all is reset. Our callers are not 2970 * required to do that (see pmap(9)), so we can't modify 2971 * the current pmap's state. 2972 */ 2973 if (PV_BEEN_EXECD(flags)) 2974 cpu_tlb_flushID(); 2975 else 2976 cpu_tlb_flushD(); 2977 } 2978 cpu_cpwait(); 2979 #endif /* ARM_MMU_EXTENDED */ 2980 } 2981 2982 /* 2983 * pmap_t pmap_create(void) 2984 * 2985 * Create a new pmap structure from scratch. 2986 */ 2987 pmap_t 2988 pmap_create(void) 2989 { 2990 pmap_t pm; 2991 2992 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2993 2994 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2995 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2996 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2997 2998 pm->pm_stats.wired_count = 0; 2999 pm->pm_stats.resident_count = 1; 3000 #ifdef ARM_MMU_EXTENDED 3001 #ifdef MULTIPROCESSOR 3002 kcpuset_create(&pm->pm_active, true); 3003 kcpuset_create(&pm->pm_onproc, true); 3004 #endif 3005 #else 3006 pm->pm_cstate.cs_all = 0; 3007 #endif 3008 pmap_alloc_l1(pm); 3009 3010 /* 3011 * Note: The pool cache ensures that the pm_l2[] array is already 3012 * initialised to zero. 3013 */ 3014 3015 pmap_pinit(pm); 3016 3017 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3018 3019 return (pm); 3020 } 3021 3022 u_int 3023 arm32_mmap_flags(paddr_t pa) 3024 { 3025 /* 3026 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3027 * and we're using the upper bits in page numbers to pass flags around 3028 * so we might as well use the same bits 3029 */ 3030 return (u_int)pa & PMAP_MD_MASK; 3031 } 3032 /* 3033 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3034 * u_int flags) 3035 * 3036 * Insert the given physical page (p) at 3037 * the specified virtual address (v) in the 3038 * target physical map with the protection requested. 3039 * 3040 * NB: This is the only routine which MAY NOT lazy-evaluate 3041 * or lose information. That is, this routine must actually 3042 * insert this page into the given map NOW. 3043 */ 3044 int 3045 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3046 { 3047 struct l2_bucket *l2b; 3048 struct vm_page *pg, *opg; 3049 u_int nflags; 3050 u_int oflags; 3051 const bool kpm_p = (pm == pmap_kernel()); 3052 #ifdef ARM_HAS_VBAR 3053 const bool vector_page_p = false; 3054 #else 3055 const bool vector_page_p = (va == vector_page); 3056 #endif 3057 3058 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3059 3060 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3061 pm, va, pa, prot); 3062 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3063 3064 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3065 KDASSERT(((va | pa) & PGOFSET) == 0); 3066 3067 /* 3068 * Get a pointer to the page. Later on in this function, we 3069 * test for a managed page by checking pg != NULL. 3070 */ 3071 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3072 3073 nflags = 0; 3074 if (prot & VM_PROT_WRITE) 3075 nflags |= PVF_WRITE; 3076 if (prot & VM_PROT_EXECUTE) 3077 nflags |= PVF_EXEC; 3078 if (flags & PMAP_WIRED) 3079 nflags |= PVF_WIRED; 3080 3081 pmap_acquire_pmap_lock(pm); 3082 3083 /* 3084 * Fetch the L2 bucket which maps this page, allocating one if 3085 * necessary for user pmaps. 3086 */ 3087 if (kpm_p) { 3088 l2b = pmap_get_l2_bucket(pm, va); 3089 } else { 3090 l2b = pmap_alloc_l2_bucket(pm, va); 3091 } 3092 if (l2b == NULL) { 3093 if (flags & PMAP_CANFAIL) { 3094 pmap_release_pmap_lock(pm); 3095 return (ENOMEM); 3096 } 3097 panic("pmap_enter: failed to allocate L2 bucket"); 3098 } 3099 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3100 const pt_entry_t opte = *ptep; 3101 pt_entry_t npte = pa; 3102 oflags = 0; 3103 3104 if (opte) { 3105 /* 3106 * There is already a mapping at this address. 3107 * If the physical address is different, lookup the 3108 * vm_page. 3109 */ 3110 if (l2pte_pa(opte) != pa) 3111 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3112 else 3113 opg = pg; 3114 } else 3115 opg = NULL; 3116 3117 if (pg) { 3118 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3119 3120 /* 3121 * This is to be a managed mapping. 3122 */ 3123 pmap_acquire_page_lock(md); 3124 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3125 /* 3126 * - The access type indicates that we don't need 3127 * to do referenced emulation. 3128 * OR 3129 * - The physical page has already been referenced 3130 * so no need to re-do referenced emulation here. 3131 */ 3132 npte |= l2pte_set_readonly(L2_S_PROTO); 3133 3134 nflags |= PVF_REF; 3135 3136 if ((prot & VM_PROT_WRITE) != 0 && 3137 ((flags & VM_PROT_WRITE) != 0 || 3138 (md->pvh_attrs & PVF_MOD) != 0)) { 3139 /* 3140 * This is a writable mapping, and the 3141 * page's mod state indicates it has 3142 * already been modified. Make it 3143 * writable from the outset. 3144 */ 3145 npte = l2pte_set_writable(npte); 3146 nflags |= PVF_MOD; 3147 } 3148 3149 #ifdef ARM_MMU_EXTENDED 3150 /* 3151 * If the page has been cleaned, then the pvh_attrs 3152 * will have PVF_EXEC set, so mark it execute so we 3153 * don't get an access fault when trying to execute 3154 * from it. 3155 */ 3156 if (md->pvh_attrs & nflags & PVF_EXEC) { 3157 npte &= ~L2_XS_XN; 3158 } 3159 #endif 3160 } else { 3161 /* 3162 * Need to do page referenced emulation. 3163 */ 3164 npte |= L2_TYPE_INV; 3165 } 3166 3167 if (flags & ARM32_MMAP_WRITECOMBINE) { 3168 npte |= pte_l2_s_wc_mode; 3169 } else 3170 npte |= pte_l2_s_cache_mode; 3171 3172 if (pg == opg) { 3173 /* 3174 * We're changing the attrs of an existing mapping. 3175 */ 3176 oflags = pmap_modify_pv(md, pa, pm, va, 3177 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3178 PVF_MOD | PVF_REF, nflags); 3179 3180 #ifdef PMAP_CACHE_VIVT 3181 /* 3182 * We may need to flush the cache if we're 3183 * doing rw-ro... 3184 */ 3185 if (pm->pm_cstate.cs_cache_d && 3186 (oflags & PVF_NC) == 0 && 3187 l2pte_writable_p(opte) && 3188 (prot & VM_PROT_WRITE) == 0) 3189 cpu_dcache_wb_range(va, PAGE_SIZE); 3190 #endif 3191 } else { 3192 struct pv_entry *pv; 3193 /* 3194 * New mapping, or changing the backing page 3195 * of an existing mapping. 3196 */ 3197 if (opg) { 3198 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3199 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3200 3201 /* 3202 * Replacing an existing mapping with a new one. 3203 * It is part of our managed memory so we 3204 * must remove it from the PV list 3205 */ 3206 pv = pmap_remove_pv(omd, opa, pm, va); 3207 pmap_vac_me_harder(omd, opa, pm, 0); 3208 oflags = pv->pv_flags; 3209 3210 #ifdef PMAP_CACHE_VIVT 3211 /* 3212 * If the old mapping was valid (ref/mod 3213 * emulation creates 'invalid' mappings 3214 * initially) then make sure to frob 3215 * the cache. 3216 */ 3217 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3218 pmap_cache_wbinv_page(pm, va, true, 3219 oflags); 3220 } 3221 #endif 3222 } else { 3223 pmap_release_page_lock(md); 3224 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3225 if (pv == NULL) { 3226 pmap_release_pmap_lock(pm); 3227 if ((flags & PMAP_CANFAIL) == 0) 3228 panic("pmap_enter: " 3229 "no pv entries"); 3230 3231 pmap_free_l2_bucket(pm, l2b, 0); 3232 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3233 0, 0, 0, 0); 3234 return (ENOMEM); 3235 } 3236 pmap_acquire_page_lock(md); 3237 } 3238 3239 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3240 } 3241 pmap_release_page_lock(md); 3242 } else { 3243 /* 3244 * We're mapping an unmanaged page. 3245 * These are always readable, and possibly writable, from 3246 * the get go as we don't need to track ref/mod status. 3247 */ 3248 npte |= l2pte_set_readonly(L2_S_PROTO); 3249 if (prot & VM_PROT_WRITE) 3250 npte = l2pte_set_writable(npte); 3251 3252 /* 3253 * Make sure the vector table is mapped cacheable 3254 */ 3255 if ((vector_page_p && !kpm_p) 3256 || (flags & ARM32_MMAP_CACHEABLE)) { 3257 npte |= pte_l2_s_cache_mode; 3258 #ifdef ARM_MMU_EXTENDED 3259 npte &= ~L2_XS_XN; /* and executable */ 3260 #endif 3261 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3262 npte |= pte_l2_s_wc_mode; 3263 } 3264 if (opg) { 3265 /* 3266 * Looks like there's an existing 'managed' mapping 3267 * at this address. 3268 */ 3269 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3270 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3271 3272 pmap_acquire_page_lock(omd); 3273 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3274 pmap_vac_me_harder(omd, opa, pm, 0); 3275 oflags = pv->pv_flags; 3276 pmap_release_page_lock(omd); 3277 3278 #ifdef PMAP_CACHE_VIVT 3279 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3280 pmap_cache_wbinv_page(pm, va, true, oflags); 3281 } 3282 #endif 3283 pool_put(&pmap_pv_pool, pv); 3284 } 3285 } 3286 3287 /* 3288 * Make sure userland mappings get the right permissions 3289 */ 3290 if (!vector_page_p && !kpm_p) { 3291 npte |= L2_S_PROT_U; 3292 #ifdef ARM_MMU_EXTENDED 3293 npte |= L2_XS_nG; /* user pages are not global */ 3294 #endif 3295 } 3296 3297 /* 3298 * Keep the stats up to date 3299 */ 3300 if (opte == 0) { 3301 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3302 pm->pm_stats.resident_count++; 3303 } 3304 3305 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3306 3307 #if defined(ARM_MMU_EXTENDED) 3308 /* 3309 * If exec protection was requested but the page hasn't been synced, 3310 * sync it now and allow execution from it. 3311 */ 3312 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3313 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3314 npte &= ~L2_XS_XN; 3315 pmap_syncicache_page(md, pa); 3316 PMAPCOUNT(exec_synced_map); 3317 } 3318 #endif 3319 /* 3320 * If this is just a wiring change, the two PTEs will be 3321 * identical, so there's no need to update the page table. 3322 */ 3323 if (npte != opte) { 3324 3325 l2pte_set(ptep, npte, opte); 3326 PTE_SYNC(ptep); 3327 #ifndef ARM_MMU_EXTENDED 3328 bool is_cached = pmap_is_cached(pm); 3329 if (is_cached) { 3330 /* 3331 * We only need to frob the cache/tlb if this pmap 3332 * is current 3333 */ 3334 if (!vector_page_p && l2pte_valid_p(npte)) { 3335 /* 3336 * This mapping is likely to be accessed as 3337 * soon as we return to userland. Fix up the 3338 * L1 entry to avoid taking another 3339 * page/domain fault. 3340 */ 3341 pd_entry_t *pdep = pmap_l1_kva(pm) 3342 + l1pte_index(va); 3343 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3344 | L1_C_DOM(pmap_domain(pm)); 3345 if (*pdep != pde) { 3346 l1pte_setone(pdep, pde); 3347 PTE_SYNC(pdep); 3348 } 3349 } 3350 } 3351 #endif /* !ARM_MMU_EXTENDED */ 3352 3353 pmap_tlb_flush_SE(pm, va, oflags); 3354 3355 #ifndef ARM_MMU_EXTENDED 3356 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3357 is_cached, pm->pm_cstate.cs_all, 0, 0); 3358 3359 if (pg != NULL) { 3360 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3361 3362 pmap_acquire_page_lock(md); 3363 pmap_vac_me_harder(md, pa, pm, va); 3364 pmap_release_page_lock(md); 3365 } 3366 #endif 3367 } 3368 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3369 if (pg) { 3370 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3371 3372 pmap_acquire_page_lock(md); 3373 #ifndef ARM_MMU_EXTENDED 3374 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3375 #endif 3376 PMAP_VALIDATE_MD_PAGE(md); 3377 pmap_release_page_lock(md); 3378 } 3379 #endif 3380 3381 pmap_release_pmap_lock(pm); 3382 3383 return (0); 3384 } 3385 3386 /* 3387 * pmap_remove() 3388 * 3389 * pmap_remove is responsible for nuking a number of mappings for a range 3390 * of virtual address space in the current pmap. To do this efficiently 3391 * is interesting, because in a number of cases a wide virtual address 3392 * range may be supplied that contains few actual mappings. So, the 3393 * optimisations are: 3394 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3395 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3396 * maybe do just a partial cache clean. This path of execution is 3397 * complicated by the fact that the cache must be flushed _before_ 3398 * the PTE is nuked, being a VAC :-) 3399 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3400 * all invalidations until pmap_update(), since pmap_remove_all() has 3401 * already flushed the cache. 3402 * 4. Maybe later fast-case a single page, but I don't think this is 3403 * going to make _that_ much difference overall. 3404 */ 3405 3406 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3407 3408 void 3409 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3410 { 3411 vaddr_t next_bucket; 3412 u_int cleanlist_idx, total, cnt; 3413 struct { 3414 vaddr_t va; 3415 pt_entry_t *ptep; 3416 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3417 u_int mappings; 3418 3419 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3420 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3421 3422 /* 3423 * we lock in the pmap => pv_head direction 3424 */ 3425 pmap_acquire_pmap_lock(pm); 3426 3427 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3428 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3429 #ifndef ARM_MMU_EXTENDED 3430 if (pm->pm_cstate.cs_tlb == 0) 3431 pm->pm_remove_all = true; 3432 #endif 3433 } else 3434 cleanlist_idx = 0; 3435 3436 total = 0; 3437 3438 while (sva < eva) { 3439 /* 3440 * Do one L2 bucket's worth at a time. 3441 */ 3442 next_bucket = L2_NEXT_BUCKET_VA(sva); 3443 if (next_bucket > eva) 3444 next_bucket = eva; 3445 3446 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3447 if (l2b == NULL) { 3448 sva = next_bucket; 3449 continue; 3450 } 3451 3452 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3453 3454 for (mappings = 0; 3455 sva < next_bucket; 3456 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3457 pt_entry_t opte = *ptep; 3458 3459 if (opte == 0) { 3460 /* Nothing here, move along */ 3461 continue; 3462 } 3463 3464 u_int flags = PVF_REF; 3465 paddr_t pa = l2pte_pa(opte); 3466 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3467 3468 /* 3469 * Update flags. In a number of circumstances, 3470 * we could cluster a lot of these and do a 3471 * number of sequential pages in one go. 3472 */ 3473 if (pg != NULL) { 3474 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3475 struct pv_entry *pv; 3476 3477 pmap_acquire_page_lock(md); 3478 pv = pmap_remove_pv(md, pa, pm, sva); 3479 pmap_vac_me_harder(md, pa, pm, 0); 3480 pmap_release_page_lock(md); 3481 if (pv != NULL) { 3482 if (pm->pm_remove_all == false) { 3483 flags = pv->pv_flags; 3484 } 3485 pool_put(&pmap_pv_pool, pv); 3486 } 3487 } 3488 mappings += PAGE_SIZE / L2_S_SIZE; 3489 3490 if (!l2pte_valid_p(opte)) { 3491 /* 3492 * Ref/Mod emulation is still active for this 3493 * mapping, therefore it is has not yet been 3494 * accessed. No need to frob the cache/tlb. 3495 */ 3496 l2pte_reset(ptep); 3497 PTE_SYNC_CURRENT(pm, ptep); 3498 continue; 3499 } 3500 3501 #ifdef ARM_MMU_EXTENDED 3502 if (pm == pmap_kernel()) { 3503 l2pte_reset(ptep); 3504 PTE_SYNC(ptep); 3505 pmap_tlb_flush_SE(pm, sva, flags); 3506 continue; 3507 } 3508 #endif 3509 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3510 /* Add to the clean list. */ 3511 cleanlist[cleanlist_idx].ptep = ptep; 3512 cleanlist[cleanlist_idx].va = 3513 sva | (flags & PVF_EXEC); 3514 cleanlist_idx++; 3515 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3516 /* Nuke everything if needed. */ 3517 #ifdef PMAP_CACHE_VIVT 3518 pmap_cache_wbinv_all(pm, PVF_EXEC); 3519 #endif 3520 /* 3521 * Roll back the previous PTE list, 3522 * and zero out the current PTE. 3523 */ 3524 for (cnt = 0; 3525 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3526 l2pte_reset(cleanlist[cnt].ptep); 3527 PTE_SYNC(cleanlist[cnt].ptep); 3528 } 3529 l2pte_reset(ptep); 3530 PTE_SYNC(ptep); 3531 cleanlist_idx++; 3532 pm->pm_remove_all = true; 3533 } else { 3534 l2pte_reset(ptep); 3535 PTE_SYNC(ptep); 3536 if (pm->pm_remove_all == false) { 3537 pmap_tlb_flush_SE(pm, sva, flags); 3538 } 3539 } 3540 } 3541 3542 /* 3543 * Deal with any left overs 3544 */ 3545 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3546 total += cleanlist_idx; 3547 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3548 #ifdef ARM_MMU_EXTENDED 3549 vaddr_t clva = cleanlist[cnt].va; 3550 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3551 #else 3552 vaddr_t va = cleanlist[cnt].va; 3553 if (pm->pm_cstate.cs_all != 0) { 3554 vaddr_t clva = va & ~PAGE_MASK; 3555 u_int flags = va & PVF_EXEC; 3556 #ifdef PMAP_CACHE_VIVT 3557 pmap_cache_wbinv_page(pm, clva, true, 3558 PVF_REF | PVF_WRITE | flags); 3559 #endif 3560 pmap_tlb_flush_SE(pm, clva, 3561 PVF_REF | flags); 3562 } 3563 #endif /* ARM_MMU_EXTENDED */ 3564 l2pte_reset(cleanlist[cnt].ptep); 3565 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3566 } 3567 3568 /* 3569 * If it looks like we're removing a whole bunch 3570 * of mappings, it's faster to just write-back 3571 * the whole cache now and defer TLB flushes until 3572 * pmap_update() is called. 3573 */ 3574 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3575 cleanlist_idx = 0; 3576 else { 3577 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3578 #ifdef PMAP_CACHE_VIVT 3579 pmap_cache_wbinv_all(pm, PVF_EXEC); 3580 #endif 3581 pm->pm_remove_all = true; 3582 } 3583 } 3584 3585 3586 pmap_free_l2_bucket(pm, l2b, mappings); 3587 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3588 } 3589 3590 pmap_release_pmap_lock(pm); 3591 } 3592 3593 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3594 static struct pv_entry * 3595 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3596 { 3597 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3598 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3599 struct pv_entry *pv; 3600 3601 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3602 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3603 KASSERT(pmap_page_locked_p(md)); 3604 3605 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3606 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3607 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3608 3609 /* 3610 * If we are removing a writeable mapping to a cached exec page, 3611 * if it's the last mapping then clear it execness other sync 3612 * the page to the icache. 3613 */ 3614 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3615 && (pv->pv_flags & PVF_WRITE) != 0) { 3616 if (SLIST_EMPTY(&md->pvh_list)) { 3617 md->pvh_attrs &= ~PVF_EXEC; 3618 PMAPCOUNT(exec_discarded_kremove); 3619 } else { 3620 pmap_syncicache_page(md, pa); 3621 PMAPCOUNT(exec_synced_kremove); 3622 } 3623 } 3624 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3625 3626 return pv; 3627 } 3628 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3629 3630 /* 3631 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3632 * 3633 * We assume there is already sufficient KVM space available 3634 * to do this, as we can't allocate L2 descriptor tables/metadata 3635 * from here. 3636 */ 3637 void 3638 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3639 { 3640 #ifdef PMAP_CACHE_VIVT 3641 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3642 #endif 3643 #ifdef PMAP_CACHE_VIPT 3644 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3645 struct vm_page *opg; 3646 #ifndef ARM_MMU_EXTENDED 3647 struct pv_entry *pv = NULL; 3648 #endif 3649 #endif 3650 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3651 3652 UVMHIST_FUNC(__func__); 3653 3654 if (pmap_initialized) { 3655 UVMHIST_CALLED(maphist); 3656 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3657 va, pa, prot, flags); 3658 } 3659 3660 pmap_t kpm = pmap_kernel(); 3661 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3662 const size_t l1slot __diagused = l1pte_index(va); 3663 KASSERTMSG(l2b != NULL, 3664 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3665 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3666 kpm->pm_l2[L2_IDX(l1slot)] 3667 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3668 : NULL, 3669 kpm->pm_l2[L2_IDX(l1slot)] 3670 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3671 : NULL); 3672 KASSERT(l2b->l2b_kva != NULL); 3673 3674 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3675 const pt_entry_t opte = *ptep; 3676 3677 if (opte == 0) { 3678 PMAPCOUNT(kenter_mappings); 3679 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3680 } else { 3681 PMAPCOUNT(kenter_remappings); 3682 #ifdef PMAP_CACHE_VIPT 3683 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3684 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3685 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3686 #endif 3687 if (opg && arm_cache_prefer_mask != 0) { 3688 KASSERT(opg != pg); 3689 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3690 KASSERT((flags & PMAP_KMPAGE) == 0); 3691 #ifndef ARM_MMU_EXTENDED 3692 pmap_acquire_page_lock(omd); 3693 pv = pmap_kremove_pg(opg, va); 3694 pmap_release_page_lock(omd); 3695 #endif 3696 } 3697 #endif 3698 if (l2pte_valid_p(opte)) { 3699 #ifdef PMAP_CACHE_VIVT 3700 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3701 #endif 3702 cpu_tlb_flushD_SE(va); 3703 cpu_cpwait(); 3704 } 3705 } 3706 3707 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3708 | ((flags & PMAP_NOCACHE) 3709 ? 0 3710 : ((flags & PMAP_PTE) 3711 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3712 #ifdef ARM_MMU_EXTENDED 3713 if (prot & VM_PROT_EXECUTE) 3714 npte &= ~L2_XS_XN; 3715 #endif 3716 l2pte_set(ptep, npte, opte); 3717 PTE_SYNC(ptep); 3718 3719 if (pg) { 3720 if (flags & PMAP_KMPAGE) { 3721 KASSERT(md->urw_mappings == 0); 3722 KASSERT(md->uro_mappings == 0); 3723 KASSERT(md->krw_mappings == 0); 3724 KASSERT(md->kro_mappings == 0); 3725 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3726 KASSERT(pv == NULL); 3727 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3728 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3729 /* if there is a color conflict, evict from cache. */ 3730 if (pmap_is_page_colored_p(md) 3731 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3732 PMAPCOUNT(vac_color_change); 3733 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3734 } else if (md->pvh_attrs & PVF_MULTCLR) { 3735 /* 3736 * If this page has multiple colors, expunge 3737 * them. 3738 */ 3739 PMAPCOUNT(vac_flush_lots2); 3740 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3741 } 3742 /* 3743 * Since this is a KMPAGE, there can be no contention 3744 * for this page so don't lock it. 3745 */ 3746 md->pvh_attrs &= PAGE_SIZE - 1; 3747 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3748 | (va & arm_cache_prefer_mask); 3749 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3750 md->pvh_attrs |= PVF_KMPAGE; 3751 #endif 3752 atomic_inc_32(&pmap_kmpages); 3753 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3754 } else if (arm_cache_prefer_mask != 0) { 3755 if (pv == NULL) { 3756 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3757 KASSERT(pv != NULL); 3758 } 3759 pmap_acquire_page_lock(md); 3760 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3761 PVF_WIRED | PVF_KENTRY 3762 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3763 if ((prot & VM_PROT_WRITE) 3764 && !(md->pvh_attrs & PVF_NC)) 3765 md->pvh_attrs |= PVF_DIRTY; 3766 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3767 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3768 pmap_release_page_lock(md); 3769 #endif 3770 } 3771 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3772 } else { 3773 if (pv != NULL) 3774 pool_put(&pmap_pv_pool, pv); 3775 #endif 3776 } 3777 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3778 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3779 #endif 3780 if (pmap_initialized) { 3781 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3782 ptep, opte, npte, 0); 3783 } 3784 3785 } 3786 3787 void 3788 pmap_kremove(vaddr_t va, vsize_t len) 3789 { 3790 #ifdef UVMHIST 3791 u_int total_mappings = 0; 3792 #endif 3793 3794 PMAPCOUNT(kenter_unmappings); 3795 3796 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3797 3798 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3799 3800 const vaddr_t eva = va + len; 3801 3802 while (va < eva) { 3803 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3804 if (next_bucket > eva) 3805 next_bucket = eva; 3806 3807 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3808 KDASSERT(l2b != NULL); 3809 3810 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3811 pt_entry_t *ptep = sptep; 3812 u_int mappings = 0; 3813 3814 while (va < next_bucket) { 3815 const pt_entry_t opte = *ptep; 3816 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3817 if (opg != NULL) { 3818 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3819 3820 if (omd->pvh_attrs & PVF_KMPAGE) { 3821 KASSERT(omd->urw_mappings == 0); 3822 KASSERT(omd->uro_mappings == 0); 3823 KASSERT(omd->krw_mappings == 0); 3824 KASSERT(omd->kro_mappings == 0); 3825 omd->pvh_attrs &= ~PVF_KMPAGE; 3826 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3827 if (arm_cache_prefer_mask != 0) { 3828 omd->pvh_attrs &= ~PVF_WRITE; 3829 } 3830 #endif 3831 atomic_dec_32(&pmap_kmpages); 3832 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3833 } else if (arm_cache_prefer_mask != 0) { 3834 pmap_acquire_page_lock(omd); 3835 pool_put(&pmap_pv_pool, 3836 pmap_kremove_pg(opg, va)); 3837 pmap_release_page_lock(omd); 3838 #endif 3839 } 3840 } 3841 if (l2pte_valid_p(opte)) { 3842 #ifdef PMAP_CACHE_VIVT 3843 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3844 #endif 3845 cpu_tlb_flushD_SE(va); 3846 } 3847 if (opte) { 3848 l2pte_reset(ptep); 3849 mappings += PAGE_SIZE / L2_S_SIZE; 3850 } 3851 va += PAGE_SIZE; 3852 ptep += PAGE_SIZE / L2_S_SIZE; 3853 } 3854 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3855 mappings, l2b->l2b_occupancy); 3856 l2b->l2b_occupancy -= mappings; 3857 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3858 #ifdef UVMHIST 3859 total_mappings += mappings; 3860 #endif 3861 } 3862 cpu_cpwait(); 3863 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3864 total_mappings, 0, 0, 0); 3865 } 3866 3867 bool 3868 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3869 { 3870 struct l2_dtable *l2; 3871 pd_entry_t *pdep, pde; 3872 pt_entry_t *ptep, pte; 3873 paddr_t pa; 3874 u_int l1slot; 3875 3876 pmap_acquire_pmap_lock(pm); 3877 3878 l1slot = l1pte_index(va); 3879 pdep = pmap_l1_kva(pm) + l1slot; 3880 pde = *pdep; 3881 3882 if (l1pte_section_p(pde)) { 3883 /* 3884 * These should only happen for pmap_kernel() 3885 */ 3886 KDASSERT(pm == pmap_kernel()); 3887 pmap_release_pmap_lock(pm); 3888 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3889 if (l1pte_supersection_p(pde)) { 3890 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3891 } else 3892 #endif 3893 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3894 } else { 3895 /* 3896 * Note that we can't rely on the validity of the L1 3897 * descriptor as an indication that a mapping exists. 3898 * We have to look it up in the L2 dtable. 3899 */ 3900 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3901 3902 if (l2 == NULL || 3903 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3904 pmap_release_pmap_lock(pm); 3905 return false; 3906 } 3907 3908 pte = ptep[l2pte_index(va)]; 3909 pmap_release_pmap_lock(pm); 3910 3911 if (pte == 0) 3912 return false; 3913 3914 switch (pte & L2_TYPE_MASK) { 3915 case L2_TYPE_L: 3916 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3917 break; 3918 3919 default: 3920 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3921 break; 3922 } 3923 } 3924 3925 if (pap != NULL) 3926 *pap = pa; 3927 3928 return true; 3929 } 3930 3931 void 3932 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3933 { 3934 struct l2_bucket *l2b; 3935 vaddr_t next_bucket; 3936 3937 NPDEBUG(PDB_PROTECT, 3938 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3939 pm, sva, eva, prot)); 3940 3941 if ((prot & VM_PROT_READ) == 0) { 3942 pmap_remove(pm, sva, eva); 3943 return; 3944 } 3945 3946 if (prot & VM_PROT_WRITE) { 3947 /* 3948 * If this is a read->write transition, just ignore it and let 3949 * uvm_fault() take care of it later. 3950 */ 3951 return; 3952 } 3953 3954 pmap_acquire_pmap_lock(pm); 3955 3956 const bool flush = eva - sva >= PAGE_SIZE * 4; 3957 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3958 u_int flags = 0; 3959 3960 while (sva < eva) { 3961 next_bucket = L2_NEXT_BUCKET_VA(sva); 3962 if (next_bucket > eva) 3963 next_bucket = eva; 3964 3965 l2b = pmap_get_l2_bucket(pm, sva); 3966 if (l2b == NULL) { 3967 sva = next_bucket; 3968 continue; 3969 } 3970 3971 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3972 3973 while (sva < next_bucket) { 3974 const pt_entry_t opte = *ptep; 3975 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3976 struct vm_page *pg; 3977 u_int f; 3978 3979 #ifdef PMAP_CACHE_VIVT 3980 /* 3981 * OK, at this point, we know we're doing 3982 * write-protect operation. If the pmap is 3983 * active, write-back the page. 3984 */ 3985 pmap_cache_wbinv_page(pm, sva, false, 3986 PVF_REF | PVF_WRITE); 3987 #endif 3988 3989 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3990 pt_entry_t npte = l2pte_set_readonly(opte); 3991 l2pte_set(ptep, npte, opte); 3992 PTE_SYNC(ptep); 3993 3994 if (pg != NULL) { 3995 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3996 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3997 3998 pmap_acquire_page_lock(md); 3999 f = pmap_modify_pv(md, pa, pm, sva, 4000 clr_mask, 0); 4001 pmap_vac_me_harder(md, pa, pm, sva); 4002 pmap_release_page_lock(md); 4003 } else { 4004 f = PVF_REF | PVF_EXEC; 4005 } 4006 4007 if (flush) { 4008 flags |= f; 4009 } else { 4010 pmap_tlb_flush_SE(pm, sva, f); 4011 } 4012 } 4013 4014 sva += PAGE_SIZE; 4015 ptep += PAGE_SIZE / L2_S_SIZE; 4016 } 4017 } 4018 4019 if (flush) { 4020 if (PV_BEEN_EXECD(flags)) { 4021 pmap_tlb_flushID(pm); 4022 } else if (PV_BEEN_REFD(flags)) { 4023 pmap_tlb_flushD(pm); 4024 } 4025 } 4026 4027 pmap_release_pmap_lock(pm); 4028 } 4029 4030 void 4031 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4032 { 4033 struct l2_bucket *l2b; 4034 pt_entry_t *ptep; 4035 vaddr_t next_bucket; 4036 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4037 4038 NPDEBUG(PDB_EXEC, 4039 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4040 pm, sva, eva)); 4041 4042 pmap_acquire_pmap_lock(pm); 4043 4044 while (sva < eva) { 4045 next_bucket = L2_NEXT_BUCKET_VA(sva); 4046 if (next_bucket > eva) 4047 next_bucket = eva; 4048 4049 l2b = pmap_get_l2_bucket(pm, sva); 4050 if (l2b == NULL) { 4051 sva = next_bucket; 4052 continue; 4053 } 4054 4055 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4056 sva < next_bucket; 4057 sva += page_size, 4058 ptep += PAGE_SIZE / L2_S_SIZE, 4059 page_size = PAGE_SIZE) { 4060 if (l2pte_valid_p(*ptep)) { 4061 cpu_icache_sync_range(sva, 4062 min(page_size, eva - sva)); 4063 } 4064 } 4065 } 4066 4067 pmap_release_pmap_lock(pm); 4068 } 4069 4070 void 4071 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4072 { 4073 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4074 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4075 4076 NPDEBUG(PDB_PROTECT, 4077 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4078 md, pa, prot)); 4079 4080 switch(prot) { 4081 case VM_PROT_READ|VM_PROT_WRITE: 4082 #if defined(ARM_MMU_EXTENDED) 4083 pmap_acquire_page_lock(md); 4084 pmap_clearbit(md, pa, PVF_EXEC); 4085 pmap_release_page_lock(md); 4086 break; 4087 #endif 4088 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4089 break; 4090 4091 case VM_PROT_READ: 4092 #if defined(ARM_MMU_EXTENDED) 4093 pmap_acquire_page_lock(md); 4094 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4095 pmap_release_page_lock(md); 4096 break; 4097 #endif 4098 case VM_PROT_READ|VM_PROT_EXECUTE: 4099 pmap_acquire_page_lock(md); 4100 pmap_clearbit(md, pa, PVF_WRITE); 4101 pmap_release_page_lock(md); 4102 break; 4103 4104 default: 4105 pmap_page_remove(md, pa); 4106 break; 4107 } 4108 } 4109 4110 /* 4111 * pmap_clear_modify: 4112 * 4113 * Clear the "modified" attribute for a page. 4114 */ 4115 bool 4116 pmap_clear_modify(struct vm_page *pg) 4117 { 4118 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4119 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4120 bool rv; 4121 4122 pmap_acquire_page_lock(md); 4123 4124 if (md->pvh_attrs & PVF_MOD) { 4125 rv = true; 4126 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4127 /* 4128 * If we are going to clear the modified bit and there are 4129 * no other modified bits set, flush the page to memory and 4130 * mark it clean. 4131 */ 4132 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4133 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4134 #endif 4135 pmap_clearbit(md, pa, PVF_MOD); 4136 } else { 4137 rv = false; 4138 } 4139 pmap_release_page_lock(md); 4140 4141 return rv; 4142 } 4143 4144 /* 4145 * pmap_clear_reference: 4146 * 4147 * Clear the "referenced" attribute for a page. 4148 */ 4149 bool 4150 pmap_clear_reference(struct vm_page *pg) 4151 { 4152 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4153 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4154 bool rv; 4155 4156 pmap_acquire_page_lock(md); 4157 4158 if (md->pvh_attrs & PVF_REF) { 4159 rv = true; 4160 pmap_clearbit(md, pa, PVF_REF); 4161 } else { 4162 rv = false; 4163 } 4164 pmap_release_page_lock(md); 4165 4166 return rv; 4167 } 4168 4169 /* 4170 * pmap_is_modified: 4171 * 4172 * Test if a page has the "modified" attribute. 4173 */ 4174 /* See <arm/arm32/pmap.h> */ 4175 4176 /* 4177 * pmap_is_referenced: 4178 * 4179 * Test if a page has the "referenced" attribute. 4180 */ 4181 /* See <arm/arm32/pmap.h> */ 4182 4183 #if defined(ARM_MMU_EXTENDED) && 0 4184 int 4185 pmap_prefetchabt_fixup(void *v) 4186 { 4187 struct trapframe * const tf = v; 4188 vaddr_t va = trunc_page(tf->tf_pc); 4189 int rv = ABORT_FIXUP_FAILED; 4190 4191 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4192 return rv; 4193 4194 kpreempt_disable(); 4195 pmap_t pm = curcpu()->ci_pmap_cur; 4196 const size_t l1slot = l1pte_index(va); 4197 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4198 if (l2 == NULL) 4199 goto out; 4200 4201 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4202 if (l2b->l2b_kva == NULL) 4203 goto out; 4204 4205 /* 4206 * Check the PTE itself. 4207 */ 4208 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4209 const pt_entry_t opte = *ptep; 4210 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4211 goto out; 4212 4213 paddr_t pa = l2pte_pa(pte); 4214 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4215 KASSERT(pg != NULL); 4216 4217 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4218 4219 pmap_acquire_page_lock(md); 4220 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4221 KASSERT(pv != NULL); 4222 4223 if (PV_IS_EXEC_P(pv->pv_flags)) { 4224 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4225 pmap_syncicache_page(md, pa); 4226 } 4227 rv = ABORT_FIXUP_RETURN; 4228 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4229 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4230 } 4231 pmap_release_page_lock(md); 4232 4233 out: 4234 kpreempt_enable(); 4235 return rv; 4236 } 4237 #endif 4238 4239 int 4240 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4241 { 4242 struct l2_dtable *l2; 4243 struct l2_bucket *l2b; 4244 paddr_t pa; 4245 const size_t l1slot = l1pte_index(va); 4246 int rv = 0; 4247 4248 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4249 4250 va = trunc_page(va); 4251 4252 KASSERT(!user || (pm != pmap_kernel())); 4253 4254 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4255 pm, va, ftype, user); 4256 #ifdef ARM_MMU_EXTENDED 4257 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4258 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4259 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4260 #endif 4261 4262 pmap_acquire_pmap_lock(pm); 4263 4264 /* 4265 * If there is no l2_dtable for this address, then the process 4266 * has no business accessing it. 4267 * 4268 * Note: This will catch userland processes trying to access 4269 * kernel addresses. 4270 */ 4271 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4272 if (l2 == NULL) { 4273 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4274 goto out; 4275 } 4276 4277 /* 4278 * Likewise if there is no L2 descriptor table 4279 */ 4280 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4281 if (l2b->l2b_kva == NULL) { 4282 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4283 goto out; 4284 } 4285 4286 /* 4287 * Check the PTE itself. 4288 */ 4289 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4290 pt_entry_t const opte = *ptep; 4291 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4292 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4293 goto out; 4294 } 4295 4296 #ifndef ARM_HAS_VBAR 4297 /* 4298 * Catch a userland access to the vector page mapped at 0x0 4299 */ 4300 if (user && (opte & L2_S_PROT_U) == 0) { 4301 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4302 goto out; 4303 } 4304 #endif 4305 4306 pa = l2pte_pa(opte); 4307 4308 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4309 /* 4310 * This looks like a good candidate for "page modified" 4311 * emulation... 4312 */ 4313 struct pv_entry *pv; 4314 struct vm_page *pg; 4315 4316 /* Extract the physical address of the page */ 4317 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4318 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4319 goto out; 4320 } 4321 4322 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4323 4324 /* Get the current flags for this page. */ 4325 pmap_acquire_page_lock(md); 4326 pv = pmap_find_pv(md, pm, va); 4327 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4328 pmap_release_page_lock(md); 4329 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4330 goto out; 4331 } 4332 4333 /* 4334 * Do the flags say this page is writable? If not then it 4335 * is a genuine write fault. If yes then the write fault is 4336 * our fault as we did not reflect the write access in the 4337 * PTE. Now we know a write has occurred we can correct this 4338 * and also set the modified bit 4339 */ 4340 if ((pv->pv_flags & PVF_WRITE) == 0) { 4341 pmap_release_page_lock(md); 4342 goto out; 4343 } 4344 4345 md->pvh_attrs |= PVF_REF | PVF_MOD; 4346 pv->pv_flags |= PVF_REF | PVF_MOD; 4347 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4348 /* 4349 * If there are cacheable mappings for this page, mark it dirty. 4350 */ 4351 if ((md->pvh_attrs & PVF_NC) == 0) 4352 md->pvh_attrs |= PVF_DIRTY; 4353 #endif 4354 #ifdef ARM_MMU_EXTENDED 4355 if (md->pvh_attrs & PVF_EXEC) { 4356 md->pvh_attrs &= ~PVF_EXEC; 4357 PMAPCOUNT(exec_discarded_modfixup); 4358 } 4359 #endif 4360 pmap_release_page_lock(md); 4361 4362 /* 4363 * Re-enable write permissions for the page. No need to call 4364 * pmap_vac_me_harder(), since this is just a 4365 * modified-emulation fault, and the PVF_WRITE bit isn't 4366 * changing. We've already set the cacheable bits based on 4367 * the assumption that we can write to this page. 4368 */ 4369 const pt_entry_t npte = 4370 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4371 #ifdef ARM_MMU_EXTENDED 4372 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4373 #endif 4374 | 0; 4375 l2pte_set(ptep, npte, opte); 4376 PTE_SYNC(ptep); 4377 PMAPCOUNT(fixup_mod); 4378 rv = 1; 4379 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4380 opte, npte, 0, 0); 4381 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4382 /* 4383 * This looks like a good candidate for "page referenced" 4384 * emulation. 4385 */ 4386 struct vm_page *pg; 4387 4388 /* Extract the physical address of the page */ 4389 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4390 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4391 goto out; 4392 } 4393 4394 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4395 4396 /* Get the current flags for this page. */ 4397 pmap_acquire_page_lock(md); 4398 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4399 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4400 pmap_release_page_lock(md); 4401 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4402 goto out; 4403 } 4404 4405 md->pvh_attrs |= PVF_REF; 4406 pv->pv_flags |= PVF_REF; 4407 4408 pt_entry_t npte = 4409 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4410 #ifdef ARM_MMU_EXTENDED 4411 if (pm != pmap_kernel()) { 4412 npte |= L2_XS_nG; 4413 } 4414 /* 4415 * If we got called from prefetch abort, then ftype will have 4416 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4417 * the PTE. 4418 */ 4419 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4420 /* 4421 * Is this a mapping of an executable page? 4422 */ 4423 if ((pv->pv_flags & PVF_EXEC) == 0) { 4424 pmap_release_page_lock(md); 4425 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4426 0, 0, 0, 0); 4427 goto out; 4428 } 4429 /* 4430 * If we haven't synced the page, do so now. 4431 */ 4432 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4433 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4434 pa, 0, 0, 0); 4435 pmap_syncicache_page(md, pa); 4436 PMAPCOUNT(fixup_exec); 4437 } 4438 npte &= ~L2_XS_XN; 4439 } 4440 #endif /* ARM_MMU_EXTENDED */ 4441 pmap_release_page_lock(md); 4442 l2pte_set(ptep, npte, opte); 4443 PTE_SYNC(ptep); 4444 PMAPCOUNT(fixup_ref); 4445 rv = 1; 4446 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4447 opte, npte, 0, 0); 4448 #ifdef ARM_MMU_EXTENDED 4449 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4450 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4451 if (pg == NULL) { 4452 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4453 goto out; 4454 } 4455 4456 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4457 4458 /* Get the current flags for this page. */ 4459 pmap_acquire_page_lock(md); 4460 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4461 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4462 pmap_release_page_lock(md); 4463 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4464 goto out; 4465 } 4466 4467 /* 4468 * If we haven't synced the page, do so now. 4469 */ 4470 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4471 UVMHIST_LOG(maphist, "syncicache page #%#x", 4472 pa, 0, 0, 0); 4473 pmap_syncicache_page(md, pa); 4474 } 4475 pmap_release_page_lock(md); 4476 /* 4477 * Turn off no-execute. 4478 */ 4479 KASSERT(opte & L2_XS_nG); 4480 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4481 PTE_SYNC(ptep); 4482 rv = 1; 4483 PMAPCOUNT(fixup_exec); 4484 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4485 opte, opte & ~L2_XS_XN, 0, 0); 4486 #endif 4487 } 4488 4489 #ifndef ARM_MMU_EXTENDED 4490 /* 4491 * We know there is a valid mapping here, so simply 4492 * fix up the L1 if necessary. 4493 */ 4494 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4495 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4496 if (*pdep != pde) { 4497 l1pte_setone(pdep, pde); 4498 PTE_SYNC(pdep); 4499 rv = 1; 4500 PMAPCOUNT(fixup_pdes); 4501 } 4502 #endif 4503 4504 #ifdef CPU_SA110 4505 /* 4506 * There are bugs in the rev K SA110. This is a check for one 4507 * of them. 4508 */ 4509 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4510 curcpu()->ci_arm_cpurev < 3) { 4511 /* Always current pmap */ 4512 if (l2pte_valid_p(opte)) { 4513 extern int kernel_debug; 4514 if (kernel_debug & 1) { 4515 struct proc *p = curlwp->l_proc; 4516 printf("prefetch_abort: page is already " 4517 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4518 printf("prefetch_abort: pc=%08lx proc=%p " 4519 "process=%s\n", va, p, p->p_comm); 4520 printf("prefetch_abort: far=%08x fs=%x\n", 4521 cpu_faultaddress(), cpu_faultstatus()); 4522 } 4523 #ifdef DDB 4524 if (kernel_debug & 2) 4525 Debugger(); 4526 #endif 4527 rv = 1; 4528 } 4529 } 4530 #endif /* CPU_SA110 */ 4531 4532 #ifndef ARM_MMU_EXTENDED 4533 /* 4534 * If 'rv == 0' at this point, it generally indicates that there is a 4535 * stale TLB entry for the faulting address. That might be due to a 4536 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4537 */ 4538 if (rv == 0 4539 && pm->pm_l1->l1_domain_use_count == 1 4540 && pmap_needs_pte_sync == 0) { 4541 pmap_needs_pte_sync = 1; 4542 PTE_SYNC(ptep); 4543 PMAPCOUNT(fixup_ptesync); 4544 rv = 1; 4545 } 4546 #endif 4547 4548 #if defined(DEBUG) || 1 4549 /* 4550 * If 'rv == 0' at this point, it generally indicates that there is a 4551 * stale TLB entry for the faulting address. This happens when two or 4552 * more processes are sharing an L1. Since we don't flush the TLB on 4553 * a context switch between such processes, we can take domain faults 4554 * for mappings which exist at the same VA in both processes. EVEN IF 4555 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4556 * example. 4557 * 4558 * This is extremely likely to happen if pmap_enter() updated the L1 4559 * entry for a recently entered mapping. In this case, the TLB is 4560 * flushed for the new mapping, but there may still be TLB entries for 4561 * other mappings belonging to other processes in the 1MB range 4562 * covered by the L1 entry. 4563 * 4564 * Since 'rv == 0', we know that the L1 already contains the correct 4565 * value, so the fault must be due to a stale TLB entry. 4566 * 4567 * Since we always need to flush the TLB anyway in the case where we 4568 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4569 * stale TLB entries dynamically. 4570 * 4571 * However, the above condition can ONLY happen if the current L1 is 4572 * being shared. If it happens when the L1 is unshared, it indicates 4573 * that other parts of the pmap are not doing their job WRT managing 4574 * the TLB. 4575 */ 4576 if (rv == 0 4577 #ifndef ARM_MMU_EXTENDED 4578 && pm->pm_l1->l1_domain_use_count == 1 4579 #endif 4580 && true) { 4581 #ifdef DEBUG 4582 extern int last_fault_code; 4583 #else 4584 int last_fault_code = ftype & VM_PROT_EXECUTE 4585 ? armreg_ifsr_read() 4586 : armreg_dfsr_read(); 4587 #endif 4588 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4589 pm, va, ftype); 4590 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4591 l2, l2b, ptep, opte); 4592 4593 #ifndef ARM_MMU_EXTENDED 4594 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4595 pdep, pde, last_fault_code); 4596 #else 4597 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4598 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4599 armreg_ttbcr_read()); 4600 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4601 last_fault_code, curcpu()->ci_pmap_cur, 4602 curcpu()->ci_pmap_asid_cur, 4603 armreg_contextidr_read(), armreg_dacr_read()); 4604 #ifdef _ARM_ARCH_7 4605 if (ftype & VM_PROT_WRITE) 4606 armreg_ats1cuw_write(va); 4607 else 4608 armreg_ats1cur_write(va); 4609 arm_isb(); 4610 printf("fixup: par %#x\n", armreg_par_read()); 4611 #endif 4612 #endif 4613 #ifdef DDB 4614 extern int kernel_debug; 4615 4616 if (kernel_debug & 2) { 4617 pmap_release_pmap_lock(pm); 4618 #ifdef UVMHIST 4619 KERNHIST_DUMP(maphist); 4620 #endif 4621 cpu_Debugger(); 4622 pmap_acquire_pmap_lock(pm); 4623 } 4624 #endif 4625 } 4626 #endif 4627 4628 pmap_tlb_flush_SE(pm, va, 4629 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4630 4631 rv = 1; 4632 4633 out: 4634 pmap_release_pmap_lock(pm); 4635 4636 return (rv); 4637 } 4638 4639 /* 4640 * Routine: pmap_procwr 4641 * 4642 * Function: 4643 * Synchronize caches corresponding to [addr, addr+len) in p. 4644 * 4645 */ 4646 void 4647 pmap_procwr(struct proc *p, vaddr_t va, int len) 4648 { 4649 /* We only need to do anything if it is the current process. */ 4650 if (p == curproc) 4651 cpu_icache_sync_range(va, len); 4652 } 4653 4654 /* 4655 * Routine: pmap_unwire 4656 * Function: Clear the wired attribute for a map/virtual-address pair. 4657 * 4658 * In/out conditions: 4659 * The mapping must already exist in the pmap. 4660 */ 4661 void 4662 pmap_unwire(pmap_t pm, vaddr_t va) 4663 { 4664 struct l2_bucket *l2b; 4665 pt_entry_t *ptep, pte; 4666 struct vm_page *pg; 4667 paddr_t pa; 4668 4669 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4670 4671 pmap_acquire_pmap_lock(pm); 4672 4673 l2b = pmap_get_l2_bucket(pm, va); 4674 KDASSERT(l2b != NULL); 4675 4676 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4677 pte = *ptep; 4678 4679 /* Extract the physical address of the page */ 4680 pa = l2pte_pa(pte); 4681 4682 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4683 /* Update the wired bit in the pv entry for this page. */ 4684 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4685 4686 pmap_acquire_page_lock(md); 4687 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4688 pmap_release_page_lock(md); 4689 } 4690 4691 pmap_release_pmap_lock(pm); 4692 } 4693 4694 void 4695 pmap_activate(struct lwp *l) 4696 { 4697 struct cpu_info * const ci = curcpu(); 4698 extern int block_userspace_access; 4699 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4700 #ifdef ARM_MMU_EXTENDED 4701 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4702 #endif 4703 4704 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4705 4706 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4707 4708 /* 4709 * If activating a non-current lwp or the current lwp is 4710 * already active, just return. 4711 */ 4712 if (false 4713 || l != curlwp 4714 #ifdef ARM_MMU_EXTENDED 4715 || (ci->ci_pmap_cur == npm && 4716 (npm == pmap_kernel() 4717 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4718 #else 4719 || npm->pm_activated == true 4720 #endif 4721 || false) { 4722 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4723 return; 4724 } 4725 4726 #ifndef ARM_MMU_EXTENDED 4727 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4728 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4729 4730 /* 4731 * If TTB and DACR are unchanged, short-circuit all the 4732 * TLB/cache management stuff. 4733 */ 4734 pmap_t opm = ci->ci_lastlwp 4735 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4736 : NULL; 4737 if (opm != NULL) { 4738 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4739 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4740 4741 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4742 goto all_done; 4743 } 4744 #endif /* !ARM_MMU_EXTENDED */ 4745 4746 PMAPCOUNT(activations); 4747 block_userspace_access = 1; 4748 4749 #ifndef ARM_MMU_EXTENDED 4750 /* 4751 * If switching to a user vmspace which is different to the 4752 * most recent one, and the most recent one is potentially 4753 * live in the cache, we must write-back and invalidate the 4754 * entire cache. 4755 */ 4756 pmap_t rpm = ci->ci_pmap_lastuser; 4757 #endif 4758 4759 /* 4760 * XXXSCW: There's a corner case here which can leave turds in the cache as 4761 * reported in kern/41058. They're probably left over during tear-down and 4762 * switching away from an exiting process. Until the root cause is identified 4763 * and fixed, zap the cache when switching pmaps. This will result in a few 4764 * unnecessary cache flushes, but that's better than silently corrupting data. 4765 */ 4766 #ifndef ARM_MMU_EXTENDED 4767 #if 0 4768 if (npm != pmap_kernel() && rpm && npm != rpm && 4769 rpm->pm_cstate.cs_cache) { 4770 rpm->pm_cstate.cs_cache = 0; 4771 #ifdef PMAP_CACHE_VIVT 4772 cpu_idcache_wbinv_all(); 4773 #endif 4774 } 4775 #else 4776 if (rpm) { 4777 rpm->pm_cstate.cs_cache = 0; 4778 if (npm == pmap_kernel()) 4779 ci->ci_pmap_lastuser = NULL; 4780 #ifdef PMAP_CACHE_VIVT 4781 cpu_idcache_wbinv_all(); 4782 #endif 4783 } 4784 #endif 4785 4786 /* No interrupts while we frob the TTB/DACR */ 4787 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4788 #endif /* !ARM_MMU_EXTENDED */ 4789 4790 #ifndef ARM_HAS_VBAR 4791 /* 4792 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4793 * entry corresponding to 'vector_page' in the incoming L1 table 4794 * before switching to it otherwise subsequent interrupts/exceptions 4795 * (including domain faults!) will jump into hyperspace. 4796 */ 4797 if (npm->pm_pl1vec != NULL) { 4798 cpu_tlb_flushID_SE((u_int)vector_page); 4799 cpu_cpwait(); 4800 *npm->pm_pl1vec = npm->pm_l1vec; 4801 PTE_SYNC(npm->pm_pl1vec); 4802 } 4803 #endif 4804 4805 #ifdef ARM_MMU_EXTENDED 4806 /* 4807 * Assume that TTBR1 has only global mappings and TTBR0 only has 4808 * non-global mappings. To prevent speculation from doing evil things 4809 * we disable translation table walks using TTBR0 before setting the 4810 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4811 * walks are reenabled. 4812 */ 4813 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4814 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4815 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4816 arm_isb(); 4817 pmap_tlb_asid_acquire(npm, l); 4818 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4819 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4820 /* 4821 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4822 * been updated. 4823 */ 4824 arm_isb(); 4825 if (npm != pmap_kernel()) { 4826 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4827 } 4828 cpu_cpwait(); 4829 ci->ci_pmap_asid_cur = pai->pai_asid; 4830 #else 4831 cpu_domains(ndacr); 4832 if (npm == pmap_kernel() || npm == rpm) { 4833 /* 4834 * Switching to a kernel thread, or back to the 4835 * same user vmspace as before... Simply update 4836 * the TTB (no TLB flush required) 4837 */ 4838 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4839 cpu_cpwait(); 4840 } else { 4841 /* 4842 * Otherwise, update TTB and flush TLB 4843 */ 4844 cpu_context_switch(npm->pm_l1->l1_physaddr); 4845 if (rpm != NULL) 4846 rpm->pm_cstate.cs_tlb = 0; 4847 } 4848 4849 restore_interrupts(oldirqstate); 4850 #endif /* ARM_MMU_EXTENDED */ 4851 4852 block_userspace_access = 0; 4853 4854 #ifndef ARM_MMU_EXTENDED 4855 all_done: 4856 /* 4857 * The new pmap is resident. Make sure it's marked 4858 * as resident in the cache/TLB. 4859 */ 4860 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4861 if (npm != pmap_kernel()) 4862 ci->ci_pmap_lastuser = npm; 4863 4864 /* The old pmap is not longer active */ 4865 if (opm != npm) { 4866 if (opm != NULL) 4867 opm->pm_activated = false; 4868 4869 /* But the new one is */ 4870 npm->pm_activated = true; 4871 } 4872 #endif 4873 ci->ci_pmap_cur = npm; 4874 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4875 } 4876 4877 void 4878 pmap_deactivate(struct lwp *l) 4879 { 4880 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4881 4882 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4883 4884 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4885 4886 #ifdef ARM_MMU_EXTENDED 4887 kpreempt_disable(); 4888 struct cpu_info * const ci = curcpu(); 4889 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4890 /* 4891 * Disable translation table walks from TTBR0 while no pmap has been 4892 * activated. 4893 */ 4894 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4895 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4896 arm_isb(); 4897 pmap_tlb_asid_deactivate(pm); 4898 cpu_setttb(pmap_kernel()->pm_l1_pa, pai->pai_asid); 4899 ci->ci_pmap_cur = pmap_kernel(); 4900 kpreempt_enable(); 4901 #else 4902 /* 4903 * If the process is exiting, make sure pmap_activate() does 4904 * a full MMU context-switch and cache flush, which we might 4905 * otherwise skip. See PR port-arm/38950. 4906 */ 4907 if (l->l_proc->p_sflag & PS_WEXIT) 4908 curcpu()->ci_lastlwp = NULL; 4909 4910 pm->pm_activated = false; 4911 #endif 4912 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4913 } 4914 4915 void 4916 pmap_update(pmap_t pm) 4917 { 4918 4919 if (pm->pm_remove_all) { 4920 #ifdef ARM_MMU_EXTENDED 4921 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4922 /* 4923 * Finish up the pmap_remove_all() optimisation by flushing 4924 * all our ASIDs. 4925 */ 4926 pmap_tlb_asid_release_all(pm); 4927 #else 4928 /* 4929 * Finish up the pmap_remove_all() optimisation by flushing 4930 * the TLB. 4931 */ 4932 pmap_tlb_flushID(pm); 4933 #endif 4934 pm->pm_remove_all = false; 4935 } 4936 4937 #ifdef ARM_MMU_EXTENDED 4938 4939 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4940 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4941 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4942 PMAP_COUNT(shootdown_ipis); 4943 } 4944 #endif 4945 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4946 #else 4947 if (pmap_is_current(pm)) { 4948 /* 4949 * If we're dealing with a current userland pmap, move its L1 4950 * to the end of the LRU. 4951 */ 4952 if (pm != pmap_kernel()) 4953 pmap_use_l1(pm); 4954 4955 /* 4956 * We can assume we're done with frobbing the cache/tlb for 4957 * now. Make sure any future pmap ops don't skip cache/tlb 4958 * flushes. 4959 */ 4960 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4961 } 4962 #endif 4963 4964 PMAPCOUNT(updates); 4965 4966 /* 4967 * make sure TLB/cache operations have completed. 4968 */ 4969 cpu_cpwait(); 4970 } 4971 4972 void 4973 pmap_remove_all(pmap_t pm) 4974 { 4975 4976 /* 4977 * The vmspace described by this pmap is about to be torn down. 4978 * Until pmap_update() is called, UVM will only make calls 4979 * to pmap_remove(). We can make life much simpler by flushing 4980 * the cache now, and deferring TLB invalidation to pmap_update(). 4981 */ 4982 #ifdef PMAP_CACHE_VIVT 4983 pmap_cache_wbinv_all(pm, PVF_EXEC); 4984 #endif 4985 pm->pm_remove_all = true; 4986 } 4987 4988 /* 4989 * Retire the given physical map from service. 4990 * Should only be called if the map contains no valid mappings. 4991 */ 4992 void 4993 pmap_destroy(pmap_t pm) 4994 { 4995 u_int count; 4996 4997 if (pm == NULL) 4998 return; 4999 5000 if (pm->pm_remove_all) { 5001 pmap_tlb_flushID(pm); 5002 pm->pm_remove_all = false; 5003 } 5004 5005 /* 5006 * Drop reference count 5007 */ 5008 mutex_enter(pm->pm_lock); 5009 count = --pm->pm_obj.uo_refs; 5010 mutex_exit(pm->pm_lock); 5011 if (count > 0) { 5012 #ifndef ARM_MMU_EXTENDED 5013 if (pmap_is_current(pm)) { 5014 if (pm != pmap_kernel()) 5015 pmap_use_l1(pm); 5016 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5017 } 5018 #endif 5019 return; 5020 } 5021 5022 /* 5023 * reference count is zero, free pmap resources and then free pmap. 5024 */ 5025 5026 #ifndef ARM_HAS_VBAR 5027 if (vector_page < KERNEL_BASE) { 5028 KDASSERT(!pmap_is_current(pm)); 5029 5030 /* Remove the vector page mapping */ 5031 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5032 pmap_update(pm); 5033 } 5034 #endif 5035 5036 LIST_REMOVE(pm, pm_list); 5037 5038 pmap_free_l1(pm); 5039 5040 #ifdef ARM_MMU_EXTENDED 5041 #ifdef MULTIPROCESSOR 5042 kcpuset_destroy(pm->pm_active); 5043 kcpuset_destroy(pm->pm_onproc); 5044 #endif 5045 #else 5046 struct cpu_info * const ci = curcpu(); 5047 if (ci->ci_pmap_lastuser == pm) 5048 ci->ci_pmap_lastuser = NULL; 5049 #endif 5050 5051 uvm_obj_destroy(&pm->pm_obj, false); 5052 mutex_destroy(&pm->pm_obj_lock); 5053 pool_cache_put(&pmap_cache, pm); 5054 } 5055 5056 5057 /* 5058 * void pmap_reference(pmap_t pm) 5059 * 5060 * Add a reference to the specified pmap. 5061 */ 5062 void 5063 pmap_reference(pmap_t pm) 5064 { 5065 5066 if (pm == NULL) 5067 return; 5068 5069 #ifndef ARM_MMU_EXTENDED 5070 pmap_use_l1(pm); 5071 #endif 5072 5073 mutex_enter(pm->pm_lock); 5074 pm->pm_obj.uo_refs++; 5075 mutex_exit(pm->pm_lock); 5076 } 5077 5078 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5079 5080 static struct evcnt pmap_prefer_nochange_ev = 5081 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5082 static struct evcnt pmap_prefer_change_ev = 5083 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5084 5085 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5086 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5087 5088 void 5089 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5090 { 5091 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5092 vaddr_t va = *vap; 5093 vaddr_t diff = (hint - va) & mask; 5094 if (diff == 0) { 5095 pmap_prefer_nochange_ev.ev_count++; 5096 } else { 5097 pmap_prefer_change_ev.ev_count++; 5098 if (__predict_false(td)) 5099 va -= mask + 1; 5100 *vap = va + diff; 5101 } 5102 } 5103 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5104 5105 /* 5106 * pmap_zero_page() 5107 * 5108 * Zero a given physical page by mapping it at a page hook point. 5109 * In doing the zero page op, the page we zero is mapped cachable, as with 5110 * StrongARM accesses to non-cached pages are non-burst making writing 5111 * _any_ bulk data very slow. 5112 */ 5113 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5114 void 5115 pmap_zero_page_generic(paddr_t pa) 5116 { 5117 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5118 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5119 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5120 #endif 5121 #if defined(PMAP_CACHE_VIPT) 5122 /* Choose the last page color it had, if any */ 5123 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5124 #else 5125 const vsize_t va_offset = 0; 5126 #endif 5127 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5128 /* 5129 * Is this page mapped at its natural color? 5130 * If we have all of memory mapped, then just convert PA to VA. 5131 */ 5132 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5133 || va_offset == (pa & arm_cache_prefer_mask); 5134 const vaddr_t vdstp = okcolor 5135 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5136 : cpu_cdstp(va_offset); 5137 #else 5138 const bool okcolor = false; 5139 const vaddr_t vdstp = cpu_cdstp(va_offset); 5140 #endif 5141 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5142 5143 5144 #ifdef DEBUG 5145 if (!SLIST_EMPTY(&md->pvh_list)) 5146 panic("pmap_zero_page: page has mappings"); 5147 #endif 5148 5149 KDASSERT((pa & PGOFSET) == 0); 5150 5151 if (!okcolor) { 5152 /* 5153 * Hook in the page, zero it, and purge the cache for that 5154 * zeroed page. Invalidate the TLB as needed. 5155 */ 5156 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5157 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5158 l2pte_set(ptep, npte, 0); 5159 PTE_SYNC(ptep); 5160 cpu_tlb_flushD_SE(vdstp); 5161 cpu_cpwait(); 5162 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5163 && !defined(ARM_MMU_EXTENDED) 5164 /* 5165 * If we are direct-mapped and our color isn't ok, then before 5166 * we bzero the page invalidate its contents from the cache and 5167 * reset the color to its natural color. 5168 */ 5169 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5170 md->pvh_attrs &= ~arm_cache_prefer_mask; 5171 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5172 #endif 5173 } 5174 bzero_page(vdstp); 5175 if (!okcolor) { 5176 /* 5177 * Unmap the page. 5178 */ 5179 l2pte_reset(ptep); 5180 PTE_SYNC(ptep); 5181 cpu_tlb_flushD_SE(vdstp); 5182 #ifdef PMAP_CACHE_VIVT 5183 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5184 #endif 5185 } 5186 #ifdef PMAP_CACHE_VIPT 5187 /* 5188 * This page is now cache resident so it now has a page color. 5189 * Any contents have been obliterated so clear the EXEC flag. 5190 */ 5191 #ifndef ARM_MMU_EXTENDED 5192 if (!pmap_is_page_colored_p(md)) { 5193 PMAPCOUNT(vac_color_new); 5194 md->pvh_attrs |= PVF_COLORED; 5195 } 5196 md->pvh_attrs |= PVF_DIRTY; 5197 #endif 5198 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5199 md->pvh_attrs &= ~PVF_EXEC; 5200 PMAPCOUNT(exec_discarded_zero); 5201 } 5202 #endif 5203 } 5204 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5205 5206 #if ARM_MMU_XSCALE == 1 5207 void 5208 pmap_zero_page_xscale(paddr_t pa) 5209 { 5210 #ifdef DEBUG 5211 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5212 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5213 5214 if (!SLIST_EMPTY(&md->pvh_list)) 5215 panic("pmap_zero_page: page has mappings"); 5216 #endif 5217 5218 KDASSERT((pa & PGOFSET) == 0); 5219 5220 /* 5221 * Hook in the page, zero it, and purge the cache for that 5222 * zeroed page. Invalidate the TLB as needed. 5223 */ 5224 5225 pt_entry_t npte = L2_S_PROTO | pa | 5226 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5227 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5228 l2pte_set(cdst_pte, npte, 0); 5229 PTE_SYNC(cdst_pte); 5230 cpu_tlb_flushD_SE(cdstp); 5231 cpu_cpwait(); 5232 bzero_page(cdstp); 5233 xscale_cache_clean_minidata(); 5234 l2pte_reset(cdst_pte); 5235 PTE_SYNC(cdst_pte); 5236 } 5237 #endif /* ARM_MMU_XSCALE == 1 */ 5238 5239 /* pmap_pageidlezero() 5240 * 5241 * The same as above, except that we assume that the page is not 5242 * mapped. This means we never have to flush the cache first. Called 5243 * from the idle loop. 5244 */ 5245 bool 5246 pmap_pageidlezero(paddr_t pa) 5247 { 5248 bool rv = true; 5249 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5250 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5251 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5252 #endif 5253 #ifdef PMAP_CACHE_VIPT 5254 /* Choose the last page color it had, if any */ 5255 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5256 #else 5257 const vsize_t va_offset = 0; 5258 #endif 5259 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5260 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5261 || va_offset == (pa & arm_cache_prefer_mask); 5262 const vaddr_t vdstp = okcolor 5263 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5264 : cpu_cdstp(va_offset); 5265 #else 5266 const bool okcolor = false; 5267 const vaddr_t vdstp = cpu_cdstp(va_offset); 5268 #endif 5269 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5270 5271 5272 #ifdef DEBUG 5273 if (!SLIST_EMPTY(&md->pvh_list)) 5274 panic("pmap_pageidlezero: page has mappings"); 5275 #endif 5276 5277 KDASSERT((pa & PGOFSET) == 0); 5278 5279 if (!okcolor) { 5280 /* 5281 * Hook in the page, zero it, and purge the cache for that 5282 * zeroed page. Invalidate the TLB as needed. 5283 */ 5284 const pt_entry_t npte = L2_S_PROTO | pa | 5285 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5286 l2pte_set(ptep, npte, 0); 5287 PTE_SYNC(ptep); 5288 cpu_tlb_flushD_SE(vdstp); 5289 cpu_cpwait(); 5290 } 5291 5292 uint64_t *ptr = (uint64_t *)vdstp; 5293 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5294 if (sched_curcpu_runnable_p() != 0) { 5295 /* 5296 * A process has become ready. Abort now, 5297 * so we don't keep it waiting while we 5298 * do slow memory access to finish this 5299 * page. 5300 */ 5301 rv = false; 5302 break; 5303 } 5304 *ptr++ = 0; 5305 } 5306 5307 #ifdef PMAP_CACHE_VIVT 5308 if (rv) 5309 /* 5310 * if we aborted we'll rezero this page again later so don't 5311 * purge it unless we finished it 5312 */ 5313 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5314 #elif defined(PMAP_CACHE_VIPT) 5315 /* 5316 * This page is now cache resident so it now has a page color. 5317 * Any contents have been obliterated so clear the EXEC flag. 5318 */ 5319 #ifndef ARM_MMU_EXTENDED 5320 if (!pmap_is_page_colored_p(md)) { 5321 PMAPCOUNT(vac_color_new); 5322 md->pvh_attrs |= PVF_COLORED; 5323 } 5324 #endif 5325 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5326 md->pvh_attrs &= ~PVF_EXEC; 5327 PMAPCOUNT(exec_discarded_zero); 5328 } 5329 #endif 5330 /* 5331 * Unmap the page. 5332 */ 5333 if (!okcolor) { 5334 l2pte_reset(ptep); 5335 PTE_SYNC(ptep); 5336 cpu_tlb_flushD_SE(vdstp); 5337 } 5338 5339 return rv; 5340 } 5341 5342 /* 5343 * pmap_copy_page() 5344 * 5345 * Copy one physical page into another, by mapping the pages into 5346 * hook points. The same comment regarding cachability as in 5347 * pmap_zero_page also applies here. 5348 */ 5349 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5350 void 5351 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5352 { 5353 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5354 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5355 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5356 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5357 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5358 #endif 5359 #ifdef PMAP_CACHE_VIPT 5360 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5361 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5362 #else 5363 const vsize_t src_va_offset = 0; 5364 const vsize_t dst_va_offset = 0; 5365 #endif 5366 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5367 /* 5368 * Is this page mapped at its natural color? 5369 * If we have all of memory mapped, then just convert PA to VA. 5370 */ 5371 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5372 || src_va_offset == (src & arm_cache_prefer_mask); 5373 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5374 || dst_va_offset == (dst & arm_cache_prefer_mask); 5375 const vaddr_t vsrcp = src_okcolor 5376 ? pmap_direct_mapped_phys(src, &src_okcolor, 5377 cpu_csrcp(src_va_offset)) 5378 : cpu_csrcp(src_va_offset); 5379 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5380 cpu_cdstp(dst_va_offset)); 5381 #else 5382 const bool src_okcolor = false; 5383 const bool dst_okcolor = false; 5384 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5385 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5386 #endif 5387 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5388 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5389 5390 #ifdef DEBUG 5391 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5392 panic("pmap_copy_page: dst page has mappings"); 5393 #endif 5394 5395 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5396 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5397 #endif 5398 KDASSERT((src & PGOFSET) == 0); 5399 KDASSERT((dst & PGOFSET) == 0); 5400 5401 /* 5402 * Clean the source page. Hold the source page's lock for 5403 * the duration of the copy so that no other mappings can 5404 * be created while we have a potentially aliased mapping. 5405 */ 5406 #ifdef PMAP_CACHE_VIVT 5407 pmap_acquire_page_lock(src_md); 5408 (void) pmap_clean_page(src_md, true); 5409 pmap_release_page_lock(src_md); 5410 #endif 5411 5412 /* 5413 * Map the pages into the page hook points, copy them, and purge 5414 * the cache for the appropriate page. Invalidate the TLB 5415 * as required. 5416 */ 5417 if (!src_okcolor) { 5418 const pt_entry_t nsrc_pte = L2_S_PROTO 5419 | src 5420 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5421 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5422 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5423 | pte_l2_s_cache_mode 5424 #endif 5425 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5426 l2pte_set(src_ptep, nsrc_pte, 0); 5427 PTE_SYNC(src_ptep); 5428 cpu_tlb_flushD_SE(vsrcp); 5429 cpu_cpwait(); 5430 } 5431 if (!dst_okcolor) { 5432 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5433 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5434 l2pte_set(dst_ptep, ndst_pte, 0); 5435 PTE_SYNC(dst_ptep); 5436 cpu_tlb_flushD_SE(vdstp); 5437 cpu_cpwait(); 5438 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5439 /* 5440 * If we are direct-mapped and our color isn't ok, then before 5441 * we bcopy to the new page invalidate its contents from the 5442 * cache and reset its color to its natural color. 5443 */ 5444 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5445 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5446 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5447 #endif 5448 } 5449 bcopy_page(vsrcp, vdstp); 5450 #ifdef PMAP_CACHE_VIVT 5451 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5452 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5453 #endif 5454 /* 5455 * Unmap the pages. 5456 */ 5457 if (!src_okcolor) { 5458 l2pte_reset(src_ptep); 5459 PTE_SYNC(src_ptep); 5460 cpu_tlb_flushD_SE(vsrcp); 5461 cpu_cpwait(); 5462 } 5463 if (!dst_okcolor) { 5464 l2pte_reset(dst_ptep); 5465 PTE_SYNC(dst_ptep); 5466 cpu_tlb_flushD_SE(vdstp); 5467 cpu_cpwait(); 5468 } 5469 #ifdef PMAP_CACHE_VIPT 5470 /* 5471 * Now that the destination page is in the cache, mark it as colored. 5472 * If this was an exec page, discard it. 5473 */ 5474 pmap_acquire_page_lock(dst_md); 5475 #ifndef ARM_MMU_EXTENDED 5476 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5477 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5478 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5479 } 5480 if (!pmap_is_page_colored_p(dst_md)) { 5481 PMAPCOUNT(vac_color_new); 5482 dst_md->pvh_attrs |= PVF_COLORED; 5483 } 5484 dst_md->pvh_attrs |= PVF_DIRTY; 5485 #endif 5486 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5487 dst_md->pvh_attrs &= ~PVF_EXEC; 5488 PMAPCOUNT(exec_discarded_copy); 5489 } 5490 pmap_release_page_lock(dst_md); 5491 #endif 5492 } 5493 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5494 5495 #if ARM_MMU_XSCALE == 1 5496 void 5497 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5498 { 5499 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5500 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5501 #ifdef DEBUG 5502 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5503 5504 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5505 panic("pmap_copy_page: dst page has mappings"); 5506 #endif 5507 5508 KDASSERT((src & PGOFSET) == 0); 5509 KDASSERT((dst & PGOFSET) == 0); 5510 5511 /* 5512 * Clean the source page. Hold the source page's lock for 5513 * the duration of the copy so that no other mappings can 5514 * be created while we have a potentially aliased mapping. 5515 */ 5516 #ifdef PMAP_CACHE_VIVT 5517 pmap_acquire_page_lock(src_md); 5518 (void) pmap_clean_page(src_md, true); 5519 pmap_release_page_lock(src_md); 5520 #endif 5521 5522 /* 5523 * Map the pages into the page hook points, copy them, and purge 5524 * the cache for the appropriate page. Invalidate the TLB 5525 * as required. 5526 */ 5527 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5528 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5529 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5530 l2pte_set(csrc_pte, nsrc_pte, 0); 5531 PTE_SYNC(csrc_pte); 5532 5533 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5534 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5535 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5536 l2pte_set(cdst_pte, ndst_pte, 0); 5537 PTE_SYNC(cdst_pte); 5538 5539 cpu_tlb_flushD_SE(csrcp); 5540 cpu_tlb_flushD_SE(cdstp); 5541 cpu_cpwait(); 5542 bcopy_page(csrcp, cdstp); 5543 xscale_cache_clean_minidata(); 5544 l2pte_reset(csrc_pte); 5545 l2pte_reset(cdst_pte); 5546 PTE_SYNC(csrc_pte); 5547 PTE_SYNC(cdst_pte); 5548 } 5549 #endif /* ARM_MMU_XSCALE == 1 */ 5550 5551 /* 5552 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5553 * 5554 * Return the start and end addresses of the kernel's virtual space. 5555 * These values are setup in pmap_bootstrap and are updated as pages 5556 * are allocated. 5557 */ 5558 void 5559 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5560 { 5561 *start = virtual_avail; 5562 *end = virtual_end; 5563 } 5564 5565 /* 5566 * Helper function for pmap_grow_l2_bucket() 5567 */ 5568 static inline int 5569 pmap_grow_map(vaddr_t va, paddr_t *pap) 5570 { 5571 paddr_t pa; 5572 5573 if (uvm.page_init_done == false) { 5574 #ifdef PMAP_STEAL_MEMORY 5575 pv_addr_t pv; 5576 pmap_boot_pagealloc(PAGE_SIZE, 5577 #ifdef PMAP_CACHE_VIPT 5578 arm_cache_prefer_mask, 5579 va & arm_cache_prefer_mask, 5580 #else 5581 0, 0, 5582 #endif 5583 &pv); 5584 pa = pv.pv_pa; 5585 #else 5586 if (uvm_page_physget(&pa) == false) 5587 return (1); 5588 #endif /* PMAP_STEAL_MEMORY */ 5589 } else { 5590 struct vm_page *pg; 5591 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5592 if (pg == NULL) 5593 return (1); 5594 pa = VM_PAGE_TO_PHYS(pg); 5595 /* 5596 * This new page must not have any mappings. Enter it via 5597 * pmap_kenter_pa and let that routine do the hard work. 5598 */ 5599 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5600 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5601 pmap_kenter_pa(va, pa, 5602 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5603 } 5604 5605 if (pap) 5606 *pap = pa; 5607 5608 PMAPCOUNT(pt_mappings); 5609 #ifdef DEBUG 5610 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5611 KDASSERT(l2b != NULL); 5612 5613 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5614 const pt_entry_t opte = *ptep; 5615 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5616 #endif 5617 memset((void *)va, 0, PAGE_SIZE); 5618 return (0); 5619 } 5620 5621 /* 5622 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5623 * used by pmap_growkernel(). 5624 */ 5625 static inline struct l2_bucket * 5626 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5627 { 5628 struct l2_dtable *l2; 5629 struct l2_bucket *l2b; 5630 u_short l1slot; 5631 vaddr_t nva; 5632 5633 l1slot = l1pte_index(va); 5634 5635 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5636 /* 5637 * No mapping at this address, as there is 5638 * no entry in the L1 table. 5639 * Need to allocate a new l2_dtable. 5640 */ 5641 nva = pmap_kernel_l2dtable_kva; 5642 if ((nva & PGOFSET) == 0) { 5643 /* 5644 * Need to allocate a backing page 5645 */ 5646 if (pmap_grow_map(nva, NULL)) 5647 return (NULL); 5648 } 5649 5650 l2 = (struct l2_dtable *)nva; 5651 nva += sizeof(struct l2_dtable); 5652 5653 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5654 /* 5655 * The new l2_dtable straddles a page boundary. 5656 * Map in another page to cover it. 5657 */ 5658 if (pmap_grow_map(nva, NULL)) 5659 return (NULL); 5660 } 5661 5662 pmap_kernel_l2dtable_kva = nva; 5663 5664 /* 5665 * Link it into the parent pmap 5666 */ 5667 pm->pm_l2[L2_IDX(l1slot)] = l2; 5668 } 5669 5670 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5671 5672 /* 5673 * Fetch pointer to the L2 page table associated with the address. 5674 */ 5675 if (l2b->l2b_kva == NULL) { 5676 pt_entry_t *ptep; 5677 5678 /* 5679 * No L2 page table has been allocated. Chances are, this 5680 * is because we just allocated the l2_dtable, above. 5681 */ 5682 nva = pmap_kernel_l2ptp_kva; 5683 ptep = (pt_entry_t *)nva; 5684 if ((nva & PGOFSET) == 0) { 5685 /* 5686 * Need to allocate a backing page 5687 */ 5688 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5689 return (NULL); 5690 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5691 } 5692 5693 l2->l2_occupancy++; 5694 l2b->l2b_kva = ptep; 5695 l2b->l2b_l1slot = l1slot; 5696 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5697 5698 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5699 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5700 } 5701 5702 return (l2b); 5703 } 5704 5705 vaddr_t 5706 pmap_growkernel(vaddr_t maxkvaddr) 5707 { 5708 pmap_t kpm = pmap_kernel(); 5709 #ifndef ARM_MMU_EXTENDED 5710 struct l1_ttable *l1; 5711 #endif 5712 int s; 5713 5714 if (maxkvaddr <= pmap_curmaxkvaddr) 5715 goto out; /* we are OK */ 5716 5717 NPDEBUG(PDB_GROWKERN, 5718 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5719 pmap_curmaxkvaddr, maxkvaddr)); 5720 5721 KDASSERT(maxkvaddr <= virtual_end); 5722 5723 /* 5724 * whoops! we need to add kernel PTPs 5725 */ 5726 5727 s = splhigh(); /* to be safe */ 5728 mutex_enter(kpm->pm_lock); 5729 5730 /* Map 1MB at a time */ 5731 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5732 #ifdef ARM_MMU_EXTENDED 5733 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5734 pd_entry_t *pdep = spdep; 5735 #endif 5736 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5737 #ifdef ARM_MMU_EXTENDED 5738 pdep++, 5739 #endif 5740 l1slot++) { 5741 struct l2_bucket *l2b = 5742 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5743 KASSERT(l2b != NULL); 5744 5745 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5746 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5747 #ifdef ARM_MMU_EXTENDED 5748 l1pte_setone(pdep, npde); 5749 #else 5750 /* Distribute new L1 entry to all other L1s */ 5751 SLIST_FOREACH(l1, &l1_list, l1_link) { 5752 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5753 l1pte_setone(pdep, npde); 5754 PDE_SYNC(pdep); 5755 } 5756 #endif 5757 } 5758 #ifdef ARM_MMU_EXTENDED 5759 PDE_SYNC_RANGE(spdep, pdep - spdep); 5760 #endif 5761 5762 #ifdef PMAP_CACHE_VIVT 5763 /* 5764 * flush out the cache, expensive but growkernel will happen so 5765 * rarely 5766 */ 5767 cpu_dcache_wbinv_all(); 5768 cpu_tlb_flushD(); 5769 cpu_cpwait(); 5770 #endif 5771 5772 mutex_exit(kpm->pm_lock); 5773 splx(s); 5774 5775 out: 5776 return (pmap_curmaxkvaddr); 5777 } 5778 5779 /************************ Utility routines ****************************/ 5780 5781 #ifndef ARM_HAS_VBAR 5782 /* 5783 * vector_page_setprot: 5784 * 5785 * Manipulate the protection of the vector page. 5786 */ 5787 void 5788 vector_page_setprot(int prot) 5789 { 5790 struct l2_bucket *l2b; 5791 pt_entry_t *ptep; 5792 5793 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5794 /* 5795 * If we are using VBAR to use the vectors in the kernel, then it's 5796 * already mapped in the kernel text so no need to anything here. 5797 */ 5798 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5799 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5800 return; 5801 } 5802 #endif 5803 5804 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5805 KASSERT(l2b != NULL); 5806 5807 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5808 5809 const pt_entry_t opte = *ptep; 5810 #ifdef ARM_MMU_EXTENDED 5811 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5812 | L2_S_PROT(PTE_KERNEL, prot); 5813 #else 5814 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5815 | L2_S_PROT(PTE_KERNEL, prot); 5816 #endif 5817 l2pte_set(ptep, npte, opte); 5818 PTE_SYNC(ptep); 5819 cpu_tlb_flushD_SE(vector_page); 5820 cpu_cpwait(); 5821 } 5822 #endif 5823 5824 /* 5825 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5826 * Returns true if the mapping exists, else false. 5827 * 5828 * NOTE: This function is only used by a couple of arm-specific modules. 5829 * It is not safe to take any pmap locks here, since we could be right 5830 * in the middle of debugging the pmap anyway... 5831 * 5832 * It is possible for this routine to return false even though a valid 5833 * mapping does exist. This is because we don't lock, so the metadata 5834 * state may be inconsistent. 5835 * 5836 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5837 * a "section" mapping. 5838 */ 5839 bool 5840 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5841 { 5842 struct l2_dtable *l2; 5843 pd_entry_t *pdep, pde; 5844 pt_entry_t *ptep; 5845 u_short l1slot; 5846 5847 if (pm->pm_l1 == NULL) 5848 return false; 5849 5850 l1slot = l1pte_index(va); 5851 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5852 pde = *pdep; 5853 5854 if (l1pte_section_p(pde)) { 5855 *ptp = NULL; 5856 return true; 5857 } 5858 5859 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5860 if (l2 == NULL || 5861 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5862 return false; 5863 } 5864 5865 *ptp = &ptep[l2pte_index(va)]; 5866 return true; 5867 } 5868 5869 bool 5870 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5871 { 5872 5873 if (pm->pm_l1 == NULL) 5874 return false; 5875 5876 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5877 5878 return true; 5879 } 5880 5881 /************************ Bootstrapping routines ****************************/ 5882 5883 #ifndef ARM_MMU_EXTENDED 5884 static void 5885 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5886 { 5887 int i; 5888 5889 l1->l1_kva = l1pt; 5890 l1->l1_domain_use_count = 0; 5891 l1->l1_domain_first = 0; 5892 5893 for (i = 0; i < PMAP_DOMAINS; i++) 5894 l1->l1_domain_free[i] = i + 1; 5895 5896 /* 5897 * Copy the kernel's L1 entries to each new L1. 5898 */ 5899 if (pmap_initialized) 5900 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5901 5902 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5903 &l1->l1_physaddr) == false) 5904 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5905 5906 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5907 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5908 } 5909 #endif /* !ARM_MMU_EXTENDED */ 5910 5911 /* 5912 * pmap_bootstrap() is called from the board-specific initarm() routine 5913 * once the kernel L1/L2 descriptors tables have been set up. 5914 * 5915 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5916 * spread over a number of disparate files/functions. 5917 * 5918 * We are passed the following parameters 5919 * - kernel_l1pt 5920 * This is a pointer to the base of the kernel's L1 translation table. 5921 * - vstart 5922 * 1MB-aligned start of managed kernel virtual memory. 5923 * - vend 5924 * 1MB-aligned end of managed kernel virtual memory. 5925 * 5926 * We use the first parameter to build the metadata (struct l1_ttable and 5927 * struct l2_dtable) necessary to track kernel mappings. 5928 */ 5929 #define PMAP_STATIC_L2_SIZE 16 5930 void 5931 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5932 { 5933 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5934 #ifndef ARM_MMU_EXTENDED 5935 static struct l1_ttable static_l1; 5936 struct l1_ttable *l1 = &static_l1; 5937 #endif 5938 struct l2_dtable *l2; 5939 struct l2_bucket *l2b; 5940 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5941 pmap_t pm = pmap_kernel(); 5942 pt_entry_t *ptep; 5943 paddr_t pa; 5944 vsize_t size; 5945 int nptes, l2idx, l2next = 0; 5946 5947 #ifdef ARM_MMU_EXTENDED 5948 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5949 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5950 #endif 5951 5952 #ifdef VERBOSE_INIT_ARM 5953 printf("kpm "); 5954 #endif 5955 /* 5956 * Initialise the kernel pmap object 5957 */ 5958 curcpu()->ci_pmap_cur = pm; 5959 #ifdef ARM_MMU_EXTENDED 5960 pm->pm_l1 = l1pt; 5961 pm->pm_l1_pa = kernel_l1pt.pv_pa; 5962 #ifdef VERBOSE_INIT_ARM 5963 printf("tlb0 "); 5964 #endif 5965 pmap_tlb_info_init(&pmap_tlb0_info); 5966 #ifdef MULTIPROCESSOR 5967 #ifdef VERBOSE_INIT_ARM 5968 printf("kcpusets "); 5969 #endif 5970 pm->pm_onproc = kcpuset_running; 5971 pm->pm_active = kcpuset_running; 5972 #endif 5973 #else 5974 pm->pm_l1 = l1; 5975 #endif 5976 5977 #ifdef VERBOSE_INIT_ARM 5978 printf("locks "); 5979 #endif 5980 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5981 if (arm_cache_prefer_mask != 0) { 5982 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 5983 } else { 5984 #endif 5985 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 5986 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5987 } 5988 #endif 5989 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5990 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5991 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5992 5993 #ifdef VERBOSE_INIT_ARM 5994 printf("l1pt "); 5995 #endif 5996 /* 5997 * Scan the L1 translation table created by initarm() and create 5998 * the required metadata for all valid mappings found in it. 5999 */ 6000 for (size_t l1slot = 0; 6001 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6002 l1slot++) { 6003 pd_entry_t pde = l1pt[l1slot]; 6004 6005 /* 6006 * We're only interested in Coarse mappings. 6007 * pmap_extract() can deal with section mappings without 6008 * recourse to checking L2 metadata. 6009 */ 6010 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6011 continue; 6012 6013 /* 6014 * Lookup the KVA of this L2 descriptor table 6015 */ 6016 pa = l1pte_pa(pde); 6017 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6018 if (ptep == NULL) { 6019 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6020 (u_int)l1slot << L1_S_SHIFT, pa); 6021 } 6022 6023 /* 6024 * Fetch the associated L2 metadata structure. 6025 * Allocate a new one if necessary. 6026 */ 6027 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6028 if (l2next == PMAP_STATIC_L2_SIZE) 6029 panic("pmap_bootstrap: out of static L2s"); 6030 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6031 } 6032 6033 /* 6034 * One more L1 slot tracked... 6035 */ 6036 l2->l2_occupancy++; 6037 6038 /* 6039 * Fill in the details of the L2 descriptor in the 6040 * appropriate bucket. 6041 */ 6042 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6043 l2b->l2b_kva = ptep; 6044 l2b->l2b_pa = pa; 6045 l2b->l2b_l1slot = l1slot; 6046 6047 /* 6048 * Establish an initial occupancy count for this descriptor 6049 */ 6050 for (l2idx = 0; 6051 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6052 l2idx++) { 6053 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6054 l2b->l2b_occupancy++; 6055 } 6056 } 6057 6058 /* 6059 * Make sure the descriptor itself has the correct cache mode. 6060 * If not, fix it, but whine about the problem. Port-meisters 6061 * should consider this a clue to fix up their initarm() 6062 * function. :) 6063 */ 6064 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6065 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6066 "L2 pte @ %p\n", ptep); 6067 } 6068 } 6069 6070 #ifdef VERBOSE_INIT_ARM 6071 printf("cache(l1pt) "); 6072 #endif 6073 /* 6074 * Ensure the primary (kernel) L1 has the correct cache mode for 6075 * a page table. Bitch if it is not correctly set. 6076 */ 6077 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6078 L1_TABLE_SIZE / L2_S_SIZE)) { 6079 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6080 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6081 } 6082 6083 #ifdef PMAP_CACHE_VIVT 6084 cpu_dcache_wbinv_all(); 6085 cpu_tlb_flushID(); 6086 cpu_cpwait(); 6087 #endif 6088 6089 /* 6090 * now we allocate the "special" VAs which are used for tmp mappings 6091 * by the pmap (and other modules). we allocate the VAs by advancing 6092 * virtual_avail (note that there are no pages mapped at these VAs). 6093 * 6094 * Managed KVM space start from wherever initarm() tells us. 6095 */ 6096 virtual_avail = vstart; 6097 virtual_end = vend; 6098 6099 #ifdef VERBOSE_INIT_ARM 6100 printf("specials "); 6101 #endif 6102 #ifdef PMAP_CACHE_VIPT 6103 /* 6104 * If we have a VIPT cache, we need one page/pte per possible alias 6105 * page so we won't violate cache aliasing rules. 6106 */ 6107 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6108 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6109 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6110 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6111 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6112 } 6113 #else 6114 nptes = PAGE_SIZE / L2_S_SIZE; 6115 #endif 6116 #ifdef MULTIPROCESSOR 6117 cnptes = nptes; 6118 nptes *= arm_cpu_max; 6119 #endif 6120 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6121 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6122 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6123 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6124 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6125 if (msgbufaddr == NULL) { 6126 pmap_alloc_specials(&virtual_avail, 6127 round_page(MSGBUFSIZE) / PAGE_SIZE, 6128 (void *)&msgbufaddr, NULL); 6129 } 6130 6131 /* 6132 * Allocate a range of kernel virtual address space to be used 6133 * for L2 descriptor tables and metadata allocation in 6134 * pmap_growkernel(). 6135 */ 6136 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6137 pmap_alloc_specials(&virtual_avail, 6138 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6139 &pmap_kernel_l2ptp_kva, NULL); 6140 6141 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6142 pmap_alloc_specials(&virtual_avail, 6143 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6144 &pmap_kernel_l2dtable_kva, NULL); 6145 6146 #ifndef ARM_MMU_EXTENDED 6147 /* 6148 * init the static-global locks and global pmap list. 6149 */ 6150 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6151 6152 /* 6153 * We can now initialise the first L1's metadata. 6154 */ 6155 SLIST_INIT(&l1_list); 6156 TAILQ_INIT(&l1_lru_list); 6157 pmap_init_l1(l1, l1pt); 6158 #endif /* ARM_MMU_EXTENDED */ 6159 6160 #ifndef ARM_HAS_VBAR 6161 /* Set up vector page L1 details, if necessary */ 6162 if (vector_page < KERNEL_BASE) { 6163 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6164 l2b = pmap_get_l2_bucket(pm, vector_page); 6165 KDASSERT(l2b != NULL); 6166 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6167 L1_C_DOM(pmap_domain(pm)); 6168 } else 6169 pm->pm_pl1vec = NULL; 6170 #endif 6171 6172 #ifdef VERBOSE_INIT_ARM 6173 printf("pools "); 6174 #endif 6175 /* 6176 * Initialize the pmap cache 6177 */ 6178 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6179 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6180 LIST_INIT(&pmap_pmaps); 6181 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6182 6183 /* 6184 * Initialize the pv pool. 6185 */ 6186 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6187 &pmap_bootstrap_pv_allocator, IPL_NONE); 6188 6189 /* 6190 * Initialize the L2 dtable pool and cache. 6191 */ 6192 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6193 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6194 6195 /* 6196 * Initialise the L2 descriptor table pool and cache 6197 */ 6198 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6199 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6200 pmap_l2ptp_ctor, NULL, NULL); 6201 6202 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6203 6204 cpu_dcache_wbinv_all(); 6205 } 6206 6207 static bool 6208 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6209 { 6210 #ifdef ARM_MMU_EXTENDED 6211 return false; 6212 #else 6213 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6214 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6215 return false; 6216 6217 const vaddr_t eva = va + nptes * PAGE_SIZE; 6218 int rv = 0; 6219 6220 while (va < eva) { 6221 /* 6222 * Make sure the descriptor itself has the correct cache mode 6223 */ 6224 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6225 pd_entry_t pde = *pdep; 6226 6227 if (l1pte_section_p(pde)) { 6228 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6229 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6230 *pdep = (pde & ~L1_S_CACHE_MASK) | 6231 pte_l1_s_cache_mode_pt; 6232 PDE_SYNC(pdep); 6233 cpu_dcache_wbinv_range((vaddr_t)pdep, 6234 sizeof(*pdep)); 6235 rv = 1; 6236 } 6237 return rv; 6238 } 6239 vaddr_t pa = l1pte_pa(pde); 6240 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6241 if (ptep == NULL) 6242 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6243 6244 ptep += l2pte_index(va); 6245 const pt_entry_t opte = *ptep; 6246 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6247 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6248 | pte_l2_s_cache_mode_pt; 6249 l2pte_set(ptep, npte, opte); 6250 PTE_SYNC(ptep); 6251 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6252 rv = 1; 6253 } 6254 va += PAGE_SIZE; 6255 } 6256 6257 return (rv); 6258 #endif 6259 } 6260 6261 static void 6262 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6263 { 6264 vaddr_t va = *availp; 6265 struct l2_bucket *l2b; 6266 6267 if (ptep) { 6268 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6269 if (l2b == NULL) 6270 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6271 6272 if (ptep) 6273 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6274 } 6275 6276 *vap = va; 6277 *availp = va + (PAGE_SIZE * pages); 6278 } 6279 6280 void 6281 pmap_init(void) 6282 { 6283 6284 /* 6285 * Set the available memory vars - These do not map to real memory 6286 * addresses and cannot as the physical memory is fragmented. 6287 * They are used by ps for %mem calculations. 6288 * One could argue whether this should be the entire memory or just 6289 * the memory that is useable in a user process. 6290 */ 6291 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6292 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6293 6294 /* 6295 * Now we need to free enough pv_entry structures to allow us to get 6296 * the kmem_map/kmem_object allocated and inited (done after this 6297 * function is finished). to do this we allocate one bootstrap page out 6298 * of kernel_map and use it to provide an initial pool of pv_entry 6299 * structures. we never free this page. 6300 */ 6301 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6302 6303 #ifdef ARM_MMU_EXTENDED 6304 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6305 #endif 6306 6307 pmap_initialized = true; 6308 } 6309 6310 static vaddr_t last_bootstrap_page = 0; 6311 static void *free_bootstrap_pages = NULL; 6312 6313 static void * 6314 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6315 { 6316 extern void *pool_page_alloc(struct pool *, int); 6317 vaddr_t new_page; 6318 void *rv; 6319 6320 if (pmap_initialized) 6321 return (pool_page_alloc(pp, flags)); 6322 6323 if (free_bootstrap_pages) { 6324 rv = free_bootstrap_pages; 6325 free_bootstrap_pages = *((void **)rv); 6326 return (rv); 6327 } 6328 6329 KASSERT(kernel_map != NULL); 6330 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6331 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6332 6333 KASSERT(new_page > last_bootstrap_page); 6334 last_bootstrap_page = new_page; 6335 return ((void *)new_page); 6336 } 6337 6338 static void 6339 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6340 { 6341 extern void pool_page_free(struct pool *, void *); 6342 6343 if ((vaddr_t)v <= last_bootstrap_page) { 6344 *((void **)v) = free_bootstrap_pages; 6345 free_bootstrap_pages = v; 6346 return; 6347 } 6348 6349 if (pmap_initialized) { 6350 pool_page_free(pp, v); 6351 return; 6352 } 6353 } 6354 6355 /* 6356 * pmap_postinit() 6357 * 6358 * This routine is called after the vm and kmem subsystems have been 6359 * initialised. This allows the pmap code to perform any initialisation 6360 * that can only be done one the memory allocation is in place. 6361 */ 6362 void 6363 pmap_postinit(void) 6364 { 6365 #ifndef ARM_MMU_EXTENDED 6366 extern paddr_t physical_start, physical_end; 6367 struct l1_ttable *l1; 6368 struct pglist plist; 6369 struct vm_page *m; 6370 pd_entry_t *pdep; 6371 vaddr_t va, eva; 6372 u_int loop, needed; 6373 int error; 6374 #endif 6375 6376 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6377 pool_cache_setlowat(&pmap_l2dtable_cache, 6378 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6379 6380 #ifndef ARM_MMU_EXTENDED 6381 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6382 needed -= 1; 6383 6384 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6385 6386 for (loop = 0; loop < needed; loop++, l1++) { 6387 /* Allocate a L1 page table */ 6388 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6389 if (va == 0) 6390 panic("Cannot allocate L1 KVM"); 6391 6392 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6393 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6394 if (error) 6395 panic("Cannot allocate L1 physical pages"); 6396 6397 m = TAILQ_FIRST(&plist); 6398 eva = va + L1_TABLE_SIZE; 6399 pdep = (pd_entry_t *)va; 6400 6401 while (m && va < eva) { 6402 paddr_t pa = VM_PAGE_TO_PHYS(m); 6403 6404 pmap_kenter_pa(va, pa, 6405 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6406 6407 va += PAGE_SIZE; 6408 m = TAILQ_NEXT(m, pageq.queue); 6409 } 6410 6411 #ifdef DIAGNOSTIC 6412 if (m) 6413 panic("pmap_alloc_l1pt: pglist not empty"); 6414 #endif /* DIAGNOSTIC */ 6415 6416 pmap_init_l1(l1, pdep); 6417 } 6418 6419 #ifdef DEBUG 6420 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6421 needed); 6422 #endif 6423 #endif /* !ARM_MMU_EXTENDED */ 6424 } 6425 6426 /* 6427 * Note that the following routines are used by board-specific initialisation 6428 * code to configure the initial kernel page tables. 6429 * 6430 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6431 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6432 * behaviour of the old pmap, and provides an easy migration path for 6433 * initial bring-up of the new pmap on existing ports. Fortunately, 6434 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6435 * will be deprecated. 6436 * 6437 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6438 * tables. 6439 */ 6440 6441 /* 6442 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6443 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6444 * find them as necessary. 6445 * 6446 * Note that the data on this list MUST remain valid after initarm() returns, 6447 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6448 */ 6449 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6450 6451 static vaddr_t 6452 kernel_pt_lookup(paddr_t pa) 6453 { 6454 pv_addr_t *pv; 6455 6456 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6457 if (pv->pv_pa == (pa & ~PGOFSET)) 6458 return (pv->pv_va | (pa & PGOFSET)); 6459 } 6460 return (0); 6461 } 6462 6463 /* 6464 * pmap_map_section: 6465 * 6466 * Create a single section mapping. 6467 */ 6468 void 6469 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6470 { 6471 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6472 const size_t l1slot = l1pte_index(va); 6473 pd_entry_t fl; 6474 6475 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6476 6477 switch (cache) { 6478 case PTE_NOCACHE: 6479 default: 6480 fl = 0; 6481 break; 6482 6483 case PTE_CACHE: 6484 fl = pte_l1_s_cache_mode; 6485 break; 6486 6487 case PTE_PAGETABLE: 6488 fl = pte_l1_s_cache_mode_pt; 6489 break; 6490 } 6491 6492 const pd_entry_t npde = L1_S_PROTO | pa | 6493 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6494 l1pte_setone(pdep + l1slot, npde); 6495 PDE_SYNC(pdep + l1slot); 6496 } 6497 6498 /* 6499 * pmap_map_entry: 6500 * 6501 * Create a single page mapping. 6502 */ 6503 void 6504 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6505 { 6506 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6507 const size_t l1slot = l1pte_index(va); 6508 pt_entry_t npte; 6509 pt_entry_t *ptep; 6510 6511 KASSERT(((va | pa) & PGOFSET) == 0); 6512 6513 switch (cache) { 6514 case PTE_NOCACHE: 6515 default: 6516 npte = 0; 6517 break; 6518 6519 case PTE_CACHE: 6520 npte = pte_l2_s_cache_mode; 6521 break; 6522 6523 case PTE_PAGETABLE: 6524 npte = pte_l2_s_cache_mode_pt; 6525 break; 6526 } 6527 6528 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6529 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6530 6531 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6532 if (ptep == NULL) 6533 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6534 6535 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6536 #ifdef ARM_MMU_EXTENDED 6537 if (prot & VM_PROT_EXECUTE) { 6538 npte &= ~L2_XS_XN; 6539 } 6540 #endif 6541 ptep += l2pte_index(va); 6542 l2pte_set(ptep, npte, 0); 6543 PTE_SYNC(ptep); 6544 } 6545 6546 /* 6547 * pmap_link_l2pt: 6548 * 6549 * Link the L2 page table specified by "l2pv" into the L1 6550 * page table at the slot for "va". 6551 */ 6552 void 6553 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6554 { 6555 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6556 6557 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6558 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6559 6560 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6561 | l2pv->pv_pa; 6562 6563 l1pte_set(pdep, npde); 6564 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6565 6566 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6567 } 6568 6569 /* 6570 * pmap_map_chunk: 6571 * 6572 * Map a chunk of memory using the most efficient mappings 6573 * possible (section, large page, small page) into the 6574 * provided L1 and L2 tables at the specified virtual address. 6575 */ 6576 vsize_t 6577 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6578 int prot, int cache) 6579 { 6580 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6581 pt_entry_t f1, f2s, f2l; 6582 vsize_t resid; 6583 6584 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6585 6586 if (l1pt == 0) 6587 panic("pmap_map_chunk: no L1 table provided"); 6588 6589 #ifdef VERBOSE_INIT_ARM 6590 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6591 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6592 #endif 6593 6594 switch (cache) { 6595 case PTE_NOCACHE: 6596 default: 6597 f1 = 0; 6598 f2l = 0; 6599 f2s = 0; 6600 break; 6601 6602 case PTE_CACHE: 6603 f1 = pte_l1_s_cache_mode; 6604 f2l = pte_l2_l_cache_mode; 6605 f2s = pte_l2_s_cache_mode; 6606 break; 6607 6608 case PTE_PAGETABLE: 6609 f1 = pte_l1_s_cache_mode_pt; 6610 f2l = pte_l2_l_cache_mode_pt; 6611 f2s = pte_l2_s_cache_mode_pt; 6612 break; 6613 } 6614 6615 size = resid; 6616 6617 while (resid > 0) { 6618 const size_t l1slot = l1pte_index(va); 6619 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6620 /* See if we can use a supersection mapping. */ 6621 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6622 /* Supersection are always domain 0 */ 6623 const pd_entry_t npde = L1_SS_PROTO | pa 6624 #ifdef ARM_MMU_EXTENDED_XXX 6625 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6626 #endif 6627 #ifdef ARM_MMU_EXTENDED 6628 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6629 #endif 6630 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6631 #ifdef VERBOSE_INIT_ARM 6632 printf("sS"); 6633 #endif 6634 l1pte_set(&pdep[l1slot], npde); 6635 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6636 va += L1_SS_SIZE; 6637 pa += L1_SS_SIZE; 6638 resid -= L1_SS_SIZE; 6639 continue; 6640 } 6641 #endif 6642 /* See if we can use a section mapping. */ 6643 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6644 const pd_entry_t npde = L1_S_PROTO | pa 6645 #ifdef ARM_MMU_EXTENDED_XXX 6646 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6647 #endif 6648 #ifdef ARM_MMU_EXTENDED 6649 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6650 #endif 6651 | L1_S_PROT(PTE_KERNEL, prot) | f1 6652 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6653 #ifdef VERBOSE_INIT_ARM 6654 printf("S"); 6655 #endif 6656 l1pte_set(&pdep[l1slot], npde); 6657 PDE_SYNC(&pdep[l1slot]); 6658 va += L1_S_SIZE; 6659 pa += L1_S_SIZE; 6660 resid -= L1_S_SIZE; 6661 continue; 6662 } 6663 6664 /* 6665 * Ok, we're going to use an L2 table. Make sure 6666 * one is actually in the corresponding L1 slot 6667 * for the current VA. 6668 */ 6669 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6670 panic("%s: no L2 table for VA %#lx", __func__, va); 6671 6672 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6673 if (ptep == NULL) 6674 panic("%s: can't find L2 table for VA %#lx", __func__, 6675 va); 6676 6677 ptep += l2pte_index(va); 6678 6679 /* See if we can use a L2 large page mapping. */ 6680 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6681 const pt_entry_t npte = L2_L_PROTO | pa 6682 #ifdef ARM_MMU_EXTENDED_XXX 6683 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6684 #endif 6685 #ifdef ARM_MMU_EXTENDED 6686 | (va & 0x80000000 ? 0 : L2_XS_nG) 6687 #endif 6688 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6689 #ifdef VERBOSE_INIT_ARM 6690 printf("L"); 6691 #endif 6692 l2pte_set(ptep, npte, 0); 6693 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6694 va += L2_L_SIZE; 6695 pa += L2_L_SIZE; 6696 resid -= L2_L_SIZE; 6697 continue; 6698 } 6699 6700 /* Use a small page mapping. */ 6701 #ifdef VERBOSE_INIT_ARM 6702 printf("P"); 6703 #endif 6704 const pt_entry_t npte = L2_S_PROTO | pa 6705 #ifdef ARM_MMU_EXTENDED_XXX 6706 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6707 #endif 6708 #ifdef ARM_MMU_EXTENDED 6709 | (va & 0x80000000 ? 0 : L2_XS_nG) 6710 #endif 6711 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6712 l2pte_set(ptep, npte, 0); 6713 PTE_SYNC(ptep); 6714 va += PAGE_SIZE; 6715 pa += PAGE_SIZE; 6716 resid -= PAGE_SIZE; 6717 } 6718 #ifdef VERBOSE_INIT_ARM 6719 printf("\n"); 6720 #endif 6721 return (size); 6722 } 6723 6724 /********************** Static device map routines ***************************/ 6725 6726 static const struct pmap_devmap *pmap_devmap_table; 6727 6728 /* 6729 * Register the devmap table. This is provided in case early console 6730 * initialization needs to register mappings created by bootstrap code 6731 * before pmap_devmap_bootstrap() is called. 6732 */ 6733 void 6734 pmap_devmap_register(const struct pmap_devmap *table) 6735 { 6736 6737 pmap_devmap_table = table; 6738 } 6739 6740 /* 6741 * Map all of the static regions in the devmap table, and remember 6742 * the devmap table so other parts of the kernel can look up entries 6743 * later. 6744 */ 6745 void 6746 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6747 { 6748 int i; 6749 6750 pmap_devmap_table = table; 6751 6752 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6753 #ifdef VERBOSE_INIT_ARM 6754 printf("devmap: %08lx -> %08lx @ %08lx\n", 6755 pmap_devmap_table[i].pd_pa, 6756 pmap_devmap_table[i].pd_pa + 6757 pmap_devmap_table[i].pd_size - 1, 6758 pmap_devmap_table[i].pd_va); 6759 #endif 6760 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6761 pmap_devmap_table[i].pd_pa, 6762 pmap_devmap_table[i].pd_size, 6763 pmap_devmap_table[i].pd_prot, 6764 pmap_devmap_table[i].pd_cache); 6765 } 6766 } 6767 6768 const struct pmap_devmap * 6769 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6770 { 6771 uint64_t endpa; 6772 int i; 6773 6774 if (pmap_devmap_table == NULL) 6775 return (NULL); 6776 6777 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6778 6779 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6780 if (pa >= pmap_devmap_table[i].pd_pa && 6781 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6782 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6783 return (&pmap_devmap_table[i]); 6784 } 6785 6786 return (NULL); 6787 } 6788 6789 const struct pmap_devmap * 6790 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6791 { 6792 int i; 6793 6794 if (pmap_devmap_table == NULL) 6795 return (NULL); 6796 6797 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6798 if (va >= pmap_devmap_table[i].pd_va && 6799 va + size - 1 <= pmap_devmap_table[i].pd_va + 6800 pmap_devmap_table[i].pd_size - 1) 6801 return (&pmap_devmap_table[i]); 6802 } 6803 6804 return (NULL); 6805 } 6806 6807 /********************** PTE initialization routines **************************/ 6808 6809 /* 6810 * These routines are called when the CPU type is identified to set up 6811 * the PTE prototypes, cache modes, etc. 6812 * 6813 * The variables are always here, just in case modules need to reference 6814 * them (though, they shouldn't). 6815 */ 6816 6817 pt_entry_t pte_l1_s_cache_mode; 6818 pt_entry_t pte_l1_s_wc_mode; 6819 pt_entry_t pte_l1_s_cache_mode_pt; 6820 pt_entry_t pte_l1_s_cache_mask; 6821 6822 pt_entry_t pte_l2_l_cache_mode; 6823 pt_entry_t pte_l2_l_wc_mode; 6824 pt_entry_t pte_l2_l_cache_mode_pt; 6825 pt_entry_t pte_l2_l_cache_mask; 6826 6827 pt_entry_t pte_l2_s_cache_mode; 6828 pt_entry_t pte_l2_s_wc_mode; 6829 pt_entry_t pte_l2_s_cache_mode_pt; 6830 pt_entry_t pte_l2_s_cache_mask; 6831 6832 pt_entry_t pte_l1_s_prot_u; 6833 pt_entry_t pte_l1_s_prot_w; 6834 pt_entry_t pte_l1_s_prot_ro; 6835 pt_entry_t pte_l1_s_prot_mask; 6836 6837 pt_entry_t pte_l2_s_prot_u; 6838 pt_entry_t pte_l2_s_prot_w; 6839 pt_entry_t pte_l2_s_prot_ro; 6840 pt_entry_t pte_l2_s_prot_mask; 6841 6842 pt_entry_t pte_l2_l_prot_u; 6843 pt_entry_t pte_l2_l_prot_w; 6844 pt_entry_t pte_l2_l_prot_ro; 6845 pt_entry_t pte_l2_l_prot_mask; 6846 6847 pt_entry_t pte_l1_ss_proto; 6848 pt_entry_t pte_l1_s_proto; 6849 pt_entry_t pte_l1_c_proto; 6850 pt_entry_t pte_l2_s_proto; 6851 6852 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6853 void (*pmap_zero_page_func)(paddr_t); 6854 6855 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6856 void 6857 pmap_pte_init_generic(void) 6858 { 6859 6860 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6861 pte_l1_s_wc_mode = L1_S_B; 6862 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6863 6864 pte_l2_l_cache_mode = L2_B|L2_C; 6865 pte_l2_l_wc_mode = L2_B; 6866 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6867 6868 pte_l2_s_cache_mode = L2_B|L2_C; 6869 pte_l2_s_wc_mode = L2_B; 6870 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6871 6872 /* 6873 * If we have a write-through cache, set B and C. If 6874 * we have a write-back cache, then we assume setting 6875 * only C will make those pages write-through (except for those 6876 * Cortex CPUs which can read the L1 caches). 6877 */ 6878 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6879 #if ARM_MMU_V7 > 0 6880 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6881 #endif 6882 #if ARM_MMU_V6 > 0 6883 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6884 #endif 6885 || false) { 6886 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6887 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6888 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6889 } else { 6890 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6891 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6892 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6893 } 6894 6895 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6896 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6897 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6898 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6899 6900 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6901 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6902 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6903 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6904 6905 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6906 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6907 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6908 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6909 6910 pte_l1_ss_proto = L1_SS_PROTO_generic; 6911 pte_l1_s_proto = L1_S_PROTO_generic; 6912 pte_l1_c_proto = L1_C_PROTO_generic; 6913 pte_l2_s_proto = L2_S_PROTO_generic; 6914 6915 pmap_copy_page_func = pmap_copy_page_generic; 6916 pmap_zero_page_func = pmap_zero_page_generic; 6917 } 6918 6919 #if defined(CPU_ARM8) 6920 void 6921 pmap_pte_init_arm8(void) 6922 { 6923 6924 /* 6925 * ARM8 is compatible with generic, but we need to use 6926 * the page tables uncached. 6927 */ 6928 pmap_pte_init_generic(); 6929 6930 pte_l1_s_cache_mode_pt = 0; 6931 pte_l2_l_cache_mode_pt = 0; 6932 pte_l2_s_cache_mode_pt = 0; 6933 } 6934 #endif /* CPU_ARM8 */ 6935 6936 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6937 void 6938 pmap_pte_init_arm9(void) 6939 { 6940 6941 /* 6942 * ARM9 is compatible with generic, but we want to use 6943 * write-through caching for now. 6944 */ 6945 pmap_pte_init_generic(); 6946 6947 pte_l1_s_cache_mode = L1_S_C; 6948 pte_l2_l_cache_mode = L2_C; 6949 pte_l2_s_cache_mode = L2_C; 6950 6951 pte_l1_s_wc_mode = L1_S_B; 6952 pte_l2_l_wc_mode = L2_B; 6953 pte_l2_s_wc_mode = L2_B; 6954 6955 pte_l1_s_cache_mode_pt = L1_S_C; 6956 pte_l2_l_cache_mode_pt = L2_C; 6957 pte_l2_s_cache_mode_pt = L2_C; 6958 } 6959 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6960 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6961 6962 #if defined(CPU_ARM10) 6963 void 6964 pmap_pte_init_arm10(void) 6965 { 6966 6967 /* 6968 * ARM10 is compatible with generic, but we want to use 6969 * write-through caching for now. 6970 */ 6971 pmap_pte_init_generic(); 6972 6973 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6974 pte_l2_l_cache_mode = L2_B | L2_C; 6975 pte_l2_s_cache_mode = L2_B | L2_C; 6976 6977 pte_l1_s_cache_mode = L1_S_B; 6978 pte_l2_l_cache_mode = L2_B; 6979 pte_l2_s_cache_mode = L2_B; 6980 6981 pte_l1_s_cache_mode_pt = L1_S_C; 6982 pte_l2_l_cache_mode_pt = L2_C; 6983 pte_l2_s_cache_mode_pt = L2_C; 6984 6985 } 6986 #endif /* CPU_ARM10 */ 6987 6988 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6989 void 6990 pmap_pte_init_arm11(void) 6991 { 6992 6993 /* 6994 * ARM11 is compatible with generic, but we want to use 6995 * write-through caching for now. 6996 */ 6997 pmap_pte_init_generic(); 6998 6999 pte_l1_s_cache_mode = L1_S_C; 7000 pte_l2_l_cache_mode = L2_C; 7001 pte_l2_s_cache_mode = L2_C; 7002 7003 pte_l1_s_wc_mode = L1_S_B; 7004 pte_l2_l_wc_mode = L2_B; 7005 pte_l2_s_wc_mode = L2_B; 7006 7007 pte_l1_s_cache_mode_pt = L1_S_C; 7008 pte_l2_l_cache_mode_pt = L2_C; 7009 pte_l2_s_cache_mode_pt = L2_C; 7010 } 7011 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7012 7013 #if ARM_MMU_SA1 == 1 7014 void 7015 pmap_pte_init_sa1(void) 7016 { 7017 7018 /* 7019 * The StrongARM SA-1 cache does not have a write-through 7020 * mode. So, do the generic initialization, then reset 7021 * the page table cache mode to B=1,C=1, and note that 7022 * the PTEs need to be sync'd. 7023 */ 7024 pmap_pte_init_generic(); 7025 7026 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7027 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7028 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7029 7030 pmap_needs_pte_sync = 1; 7031 } 7032 #endif /* ARM_MMU_SA1 == 1*/ 7033 7034 #if ARM_MMU_XSCALE == 1 7035 #if (ARM_NMMUS > 1) 7036 static u_int xscale_use_minidata; 7037 #endif 7038 7039 void 7040 pmap_pte_init_xscale(void) 7041 { 7042 uint32_t auxctl; 7043 int write_through = 0; 7044 7045 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7046 pte_l1_s_wc_mode = L1_S_B; 7047 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7048 7049 pte_l2_l_cache_mode = L2_B|L2_C; 7050 pte_l2_l_wc_mode = L2_B; 7051 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7052 7053 pte_l2_s_cache_mode = L2_B|L2_C; 7054 pte_l2_s_wc_mode = L2_B; 7055 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7056 7057 pte_l1_s_cache_mode_pt = L1_S_C; 7058 pte_l2_l_cache_mode_pt = L2_C; 7059 pte_l2_s_cache_mode_pt = L2_C; 7060 7061 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7062 /* 7063 * The XScale core has an enhanced mode where writes that 7064 * miss the cache cause a cache line to be allocated. This 7065 * is significantly faster than the traditional, write-through 7066 * behavior of this case. 7067 */ 7068 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7069 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7070 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7071 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7072 7073 #ifdef XSCALE_CACHE_WRITE_THROUGH 7074 /* 7075 * Some versions of the XScale core have various bugs in 7076 * their cache units, the work-around for which is to run 7077 * the cache in write-through mode. Unfortunately, this 7078 * has a major (negative) impact on performance. So, we 7079 * go ahead and run fast-and-loose, in the hopes that we 7080 * don't line up the planets in a way that will trip the 7081 * bugs. 7082 * 7083 * However, we give you the option to be slow-but-correct. 7084 */ 7085 write_through = 1; 7086 #elif defined(XSCALE_CACHE_WRITE_BACK) 7087 /* force write back cache mode */ 7088 write_through = 0; 7089 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7090 /* 7091 * Intel PXA2[15]0 processors are known to have a bug in 7092 * write-back cache on revision 4 and earlier (stepping 7093 * A[01] and B[012]). Fixed for C0 and later. 7094 */ 7095 { 7096 uint32_t id, type; 7097 7098 id = cpufunc_id(); 7099 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7100 7101 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7102 if ((id & CPU_ID_REVISION_MASK) < 5) { 7103 /* write through for stepping A0-1 and B0-2 */ 7104 write_through = 1; 7105 } 7106 } 7107 } 7108 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7109 7110 if (write_through) { 7111 pte_l1_s_cache_mode = L1_S_C; 7112 pte_l2_l_cache_mode = L2_C; 7113 pte_l2_s_cache_mode = L2_C; 7114 } 7115 7116 #if (ARM_NMMUS > 1) 7117 xscale_use_minidata = 1; 7118 #endif 7119 7120 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7121 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7122 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7123 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7124 7125 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7126 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7127 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7128 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7129 7130 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7131 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7132 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7133 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7134 7135 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7136 pte_l1_s_proto = L1_S_PROTO_xscale; 7137 pte_l1_c_proto = L1_C_PROTO_xscale; 7138 pte_l2_s_proto = L2_S_PROTO_xscale; 7139 7140 pmap_copy_page_func = pmap_copy_page_xscale; 7141 pmap_zero_page_func = pmap_zero_page_xscale; 7142 7143 /* 7144 * Disable ECC protection of page table access, for now. 7145 */ 7146 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7147 auxctl &= ~XSCALE_AUXCTL_P; 7148 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7149 } 7150 7151 /* 7152 * xscale_setup_minidata: 7153 * 7154 * Set up the mini-data cache clean area. We require the 7155 * caller to allocate the right amount of physically and 7156 * virtually contiguous space. 7157 */ 7158 void 7159 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7160 { 7161 extern vaddr_t xscale_minidata_clean_addr; 7162 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7163 pd_entry_t *pde = (pd_entry_t *) l1pt; 7164 vsize_t size; 7165 uint32_t auxctl; 7166 7167 xscale_minidata_clean_addr = va; 7168 7169 /* Round it to page size. */ 7170 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7171 7172 for (; size != 0; 7173 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7174 const size_t l1slot = l1pte_index(va); 7175 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7176 if (ptep == NULL) 7177 panic("xscale_setup_minidata: can't find L2 table for " 7178 "VA 0x%08lx", va); 7179 7180 ptep += l2pte_index(va); 7181 pt_entry_t opte = *ptep; 7182 l2pte_set(ptep, 7183 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7184 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7185 } 7186 7187 /* 7188 * Configure the mini-data cache for write-back with 7189 * read/write-allocate. 7190 * 7191 * NOTE: In order to reconfigure the mini-data cache, we must 7192 * make sure it contains no valid data! In order to do that, 7193 * we must issue a global data cache invalidate command! 7194 * 7195 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7196 * THIS IS VERY IMPORTANT! 7197 */ 7198 7199 /* Invalidate data and mini-data. */ 7200 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7201 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7202 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7203 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7204 } 7205 7206 /* 7207 * Change the PTEs for the specified kernel mappings such that they 7208 * will use the mini data cache instead of the main data cache. 7209 */ 7210 void 7211 pmap_uarea(vaddr_t va) 7212 { 7213 vaddr_t next_bucket, eva; 7214 7215 #if (ARM_NMMUS > 1) 7216 if (xscale_use_minidata == 0) 7217 return; 7218 #endif 7219 7220 eva = va + USPACE; 7221 7222 while (va < eva) { 7223 next_bucket = L2_NEXT_BUCKET_VA(va); 7224 if (next_bucket > eva) 7225 next_bucket = eva; 7226 7227 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7228 KDASSERT(l2b != NULL); 7229 7230 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7231 pt_entry_t *ptep = sptep; 7232 7233 while (va < next_bucket) { 7234 const pt_entry_t opte = *ptep; 7235 if (!l2pte_minidata_p(opte)) { 7236 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7237 cpu_tlb_flushD_SE(va); 7238 l2pte_set(ptep, opte & ~L2_B, opte); 7239 } 7240 ptep += PAGE_SIZE / L2_S_SIZE; 7241 va += PAGE_SIZE; 7242 } 7243 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7244 } 7245 cpu_cpwait(); 7246 } 7247 #endif /* ARM_MMU_XSCALE == 1 */ 7248 7249 7250 #if defined(CPU_ARM11MPCORE) 7251 7252 void 7253 pmap_pte_init_arm11mpcore(void) 7254 { 7255 7256 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7257 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7258 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7259 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7260 /* use extended small page (without APn, with TEX) */ 7261 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7262 #else 7263 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7264 #endif 7265 7266 /* write-back, write-allocate */ 7267 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7268 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7269 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7270 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7271 #else 7272 /* no TEX. read-allocate */ 7273 pte_l2_s_cache_mode = L2_C | L2_B; 7274 #endif 7275 /* 7276 * write-back, write-allocate for page tables. 7277 */ 7278 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7279 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7280 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7281 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7282 #else 7283 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7284 #endif 7285 7286 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7287 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7288 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7289 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7290 7291 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7292 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7293 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7294 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7295 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7296 7297 #else 7298 /* with AP[0..3] */ 7299 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7300 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7301 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7302 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7303 #endif 7304 7305 #ifdef ARM11MPCORE_COMPAT_MMU 7306 /* with AP[0..3] */ 7307 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7308 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7309 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7310 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7311 7312 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7313 pte_l1_s_proto = L1_S_PROTO_armv6; 7314 pte_l1_c_proto = L1_C_PROTO_armv6; 7315 pte_l2_s_proto = L2_S_PROTO_armv6c; 7316 #else 7317 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7318 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7319 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7320 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7321 7322 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7323 pte_l1_s_proto = L1_S_PROTO_armv6; 7324 pte_l1_c_proto = L1_C_PROTO_armv6; 7325 pte_l2_s_proto = L2_S_PROTO_armv6n; 7326 #endif 7327 7328 pmap_copy_page_func = pmap_copy_page_generic; 7329 pmap_zero_page_func = pmap_zero_page_generic; 7330 pmap_needs_pte_sync = 1; 7331 } 7332 #endif /* CPU_ARM11MPCORE */ 7333 7334 7335 #if ARM_MMU_V7 == 1 7336 void 7337 pmap_pte_init_armv7(void) 7338 { 7339 /* 7340 * The ARMv7-A MMU is mostly compatible with generic. If the 7341 * AP field is zero, that now means "no access" rather than 7342 * read-only. The prototypes are a little different because of 7343 * the XN bit. 7344 */ 7345 pmap_pte_init_generic(); 7346 7347 pmap_needs_pte_sync = 1; 7348 7349 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7350 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7351 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7352 7353 /* 7354 * If the core support coherent walk then updates to translation tables 7355 * do not require a clean to the point of unification to ensure 7356 * visibility by subsequent translation table walks. That means we can 7357 * map everything shareable and cached and the right thing will happen. 7358 */ 7359 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7360 pmap_needs_pte_sync = 0; 7361 7362 /* 7363 * write-back, no write-allocate, shareable for normal pages. 7364 */ 7365 pte_l1_s_cache_mode |= L1_S_V6_S; 7366 pte_l2_l_cache_mode |= L2_XS_S; 7367 pte_l2_s_cache_mode |= L2_XS_S; 7368 } 7369 7370 /* 7371 * Page tables are just all other memory. We can use write-back since 7372 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7373 */ 7374 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7375 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7376 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7377 7378 /* 7379 * Check the Memory Model Features to see if this CPU supports 7380 * the TLBIASID coproc op. 7381 */ 7382 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7383 arm_has_tlbiasid_p = true; 7384 } 7385 7386 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7387 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7388 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7389 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7390 7391 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7392 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7393 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7394 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7395 7396 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7397 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7398 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7399 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7400 7401 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7402 pte_l1_s_proto = L1_S_PROTO_armv7; 7403 pte_l1_c_proto = L1_C_PROTO_armv7; 7404 pte_l2_s_proto = L2_S_PROTO_armv7; 7405 7406 } 7407 #endif /* ARM_MMU_V7 */ 7408 7409 /* 7410 * return the PA of the current L1 table, for use when handling a crash dump 7411 */ 7412 uint32_t 7413 pmap_kernel_L1_addr(void) 7414 { 7415 #ifdef ARM_MMU_EXTENDED 7416 return pmap_kernel()->pm_l1_pa; 7417 #else 7418 return pmap_kernel()->pm_l1->l1_physaddr; 7419 #endif 7420 } 7421 7422 #if defined(DDB) 7423 /* 7424 * A couple of ddb-callable functions for dumping pmaps 7425 */ 7426 void pmap_dump_all(void); 7427 void pmap_dump(pmap_t); 7428 7429 void 7430 pmap_dump_all(void) 7431 { 7432 pmap_t pm; 7433 7434 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7435 if (pm == pmap_kernel()) 7436 continue; 7437 pmap_dump(pm); 7438 printf("\n"); 7439 } 7440 } 7441 7442 static pt_entry_t ncptes[64]; 7443 static void pmap_dump_ncpg(pmap_t); 7444 7445 void 7446 pmap_dump(pmap_t pm) 7447 { 7448 struct l2_dtable *l2; 7449 struct l2_bucket *l2b; 7450 pt_entry_t *ptep, pte; 7451 vaddr_t l2_va, l2b_va, va; 7452 int i, j, k, occ, rows = 0; 7453 7454 if (pm == pmap_kernel()) 7455 printf("pmap_kernel (%p): ", pm); 7456 else 7457 printf("user pmap (%p): ", pm); 7458 7459 #ifdef ARM_MMU_EXTENDED 7460 printf("l1 at %p\n", pmap_l1_kva(pm)); 7461 #else 7462 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7463 #endif 7464 7465 l2_va = 0; 7466 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7467 l2 = pm->pm_l2[i]; 7468 7469 if (l2 == NULL || l2->l2_occupancy == 0) 7470 continue; 7471 7472 l2b_va = l2_va; 7473 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7474 l2b = &l2->l2_bucket[j]; 7475 7476 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7477 continue; 7478 7479 ptep = l2b->l2b_kva; 7480 7481 for (k = 0; k < 256 && ptep[k] == 0; k++) 7482 ; 7483 7484 k &= ~63; 7485 occ = l2b->l2b_occupancy; 7486 va = l2b_va + (k * 4096); 7487 for (; k < 256; k++, va += 0x1000) { 7488 char ch = ' '; 7489 if ((k % 64) == 0) { 7490 if ((rows % 8) == 0) { 7491 printf( 7492 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7493 } 7494 printf("%08lx: ", va); 7495 } 7496 7497 ncptes[k & 63] = 0; 7498 pte = ptep[k]; 7499 if (pte == 0) { 7500 ch = '.'; 7501 } else { 7502 occ--; 7503 switch (pte & 0x0c) { 7504 case 0x00: 7505 ch = 'D'; /* No cache No buff */ 7506 break; 7507 case 0x04: 7508 ch = 'B'; /* No cache buff */ 7509 break; 7510 case 0x08: 7511 if (pte & 0x40) 7512 ch = 'm'; 7513 else 7514 ch = 'C'; /* Cache No buff */ 7515 break; 7516 case 0x0c: 7517 ch = 'F'; /* Cache Buff */ 7518 break; 7519 } 7520 7521 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7522 ch += 0x20; 7523 7524 if ((pte & 0xc) == 0) 7525 ncptes[k & 63] = pte; 7526 } 7527 7528 if ((k % 64) == 63) { 7529 rows++; 7530 printf("%c\n", ch); 7531 pmap_dump_ncpg(pm); 7532 if (occ == 0) 7533 break; 7534 } else 7535 printf("%c", ch); 7536 } 7537 } 7538 } 7539 } 7540 7541 static void 7542 pmap_dump_ncpg(pmap_t pm) 7543 { 7544 struct vm_page *pg; 7545 struct vm_page_md *md; 7546 struct pv_entry *pv; 7547 int i; 7548 7549 for (i = 0; i < 63; i++) { 7550 if (ncptes[i] == 0) 7551 continue; 7552 7553 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7554 if (pg == NULL) 7555 continue; 7556 md = VM_PAGE_TO_MD(pg); 7557 7558 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7559 VM_PAGE_TO_PHYS(pg), 7560 md->krw_mappings, md->kro_mappings, 7561 md->urw_mappings, md->uro_mappings); 7562 7563 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7564 printf(" %c va 0x%08lx, flags 0x%x\n", 7565 (pm == pv->pv_pmap) ? '*' : ' ', 7566 pv->pv_va, pv->pv_flags); 7567 } 7568 } 7569 } 7570 #endif 7571 7572 #ifdef PMAP_STEAL_MEMORY 7573 void 7574 pmap_boot_pageadd(pv_addr_t *newpv) 7575 { 7576 pv_addr_t *pv, *npv; 7577 7578 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7579 if (newpv->pv_pa < pv->pv_va) { 7580 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7581 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7582 newpv->pv_size += pv->pv_size; 7583 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7584 } 7585 pv = NULL; 7586 } else { 7587 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7588 pv = npv) { 7589 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7590 KASSERT(pv->pv_pa < newpv->pv_pa); 7591 if (newpv->pv_pa > npv->pv_pa) 7592 continue; 7593 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7594 pv->pv_size += newpv->pv_size; 7595 return; 7596 } 7597 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7598 break; 7599 newpv->pv_size += npv->pv_size; 7600 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7601 SLIST_REMOVE_AFTER(newpv, pv_list); 7602 return; 7603 } 7604 } 7605 } 7606 7607 if (pv) { 7608 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7609 } else { 7610 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7611 } 7612 } 7613 7614 void 7615 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7616 pv_addr_t *rpv) 7617 { 7618 pv_addr_t *pv, **pvp; 7619 struct vm_physseg *ps; 7620 size_t i; 7621 7622 KASSERT(amount & PGOFSET); 7623 KASSERT((mask & PGOFSET) == 0); 7624 KASSERT((match & PGOFSET) == 0); 7625 KASSERT(amount != 0); 7626 7627 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7628 (pv = *pvp) != NULL; 7629 pvp = &SLIST_NEXT(pv, pv_list)) { 7630 pv_addr_t *newpv; 7631 psize_t off; 7632 /* 7633 * If this entry is too small to satify the request... 7634 */ 7635 KASSERT(pv->pv_size > 0); 7636 if (pv->pv_size < amount) 7637 continue; 7638 7639 for (off = 0; off <= mask; off += PAGE_SIZE) { 7640 if (((pv->pv_pa + off) & mask) == match 7641 && off + amount <= pv->pv_size) 7642 break; 7643 } 7644 if (off > mask) 7645 continue; 7646 7647 rpv->pv_va = pv->pv_va + off; 7648 rpv->pv_pa = pv->pv_pa + off; 7649 rpv->pv_size = amount; 7650 pv->pv_size -= amount; 7651 if (pv->pv_size == 0) { 7652 KASSERT(off == 0); 7653 KASSERT((vaddr_t) pv == rpv->pv_va); 7654 *pvp = SLIST_NEXT(pv, pv_list); 7655 } else if (off == 0) { 7656 KASSERT((vaddr_t) pv == rpv->pv_va); 7657 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7658 *newpv = *pv; 7659 newpv->pv_pa += amount; 7660 newpv->pv_va += amount; 7661 *pvp = newpv; 7662 } else if (off < pv->pv_size) { 7663 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7664 *newpv = *pv; 7665 newpv->pv_size -= off; 7666 newpv->pv_pa += off + amount; 7667 newpv->pv_va += off + amount; 7668 7669 SLIST_NEXT(pv, pv_list) = newpv; 7670 pv->pv_size = off; 7671 } else { 7672 KASSERT((vaddr_t) pv != rpv->pv_va); 7673 } 7674 memset((void *)rpv->pv_va, 0, amount); 7675 return; 7676 } 7677 7678 if (vm_nphysseg == 0) 7679 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7680 7681 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7682 (pv = *pvp) != NULL; 7683 pvp = &SLIST_NEXT(pv, pv_list)) { 7684 if (SLIST_NEXT(pv, pv_list) == NULL) 7685 break; 7686 } 7687 KASSERT(mask == 0); 7688 for (i = 0; i < vm_nphysseg; i++) { 7689 ps = VM_PHYSMEM_PTR(i); 7690 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7691 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7692 rpv->pv_va = pv->pv_va; 7693 rpv->pv_pa = pv->pv_pa; 7694 rpv->pv_size = amount; 7695 *pvp = NULL; 7696 pmap_map_chunk(kernel_l1pt.pv_va, 7697 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7698 ptoa(ps->avail_start), 7699 amount - pv->pv_size, 7700 VM_PROT_READ|VM_PROT_WRITE, 7701 PTE_CACHE); 7702 ps->avail_start += atop(amount - pv->pv_size); 7703 /* 7704 * If we consumed the entire physseg, remove it. 7705 */ 7706 if (ps->avail_start == ps->avail_end) { 7707 for (--vm_nphysseg; i < vm_nphysseg; i++) 7708 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7709 } 7710 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7711 return; 7712 } 7713 } 7714 7715 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7716 } 7717 7718 vaddr_t 7719 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7720 { 7721 pv_addr_t pv; 7722 7723 pmap_boot_pagealloc(size, 0, 0, &pv); 7724 7725 return pv.pv_va; 7726 } 7727 #endif /* PMAP_STEAL_MEMORY */ 7728 7729 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7730 { 7731 sysctl_createv(clog, 0, NULL, NULL, 7732 CTLFLAG_PERMANENT, 7733 CTLTYPE_NODE, "machdep", NULL, 7734 NULL, 0, NULL, 0, 7735 CTL_MACHDEP, CTL_EOL); 7736 7737 sysctl_createv(clog, 0, NULL, NULL, 7738 CTLFLAG_PERMANENT, 7739 CTLTYPE_INT, "kmpages", 7740 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7741 NULL, 0, &pmap_kmpages, 0, 7742 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7743 } 7744 7745 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7746 struct vm_page * 7747 arm_pmap_alloc_poolpage(int flags) 7748 { 7749 /* 7750 * On some systems, only some pages may be "coherent" for dma and we 7751 * want to prefer those for pool pages (think mbufs) but fallback to 7752 * any page if none is available. But we can only fallback if we 7753 * aren't direct mapping memory or all of memory can be direct-mapped. 7754 * If that isn't true, pool changes can only come from direct-mapped 7755 * memory. 7756 */ 7757 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7758 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7759 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7760 (pmap_directbase < KERNEL_BASE 7761 ? UVM_PGA_STRAT_ONLY 7762 : UVM_PGA_STRAT_FALLBACK), 7763 #else 7764 UVM_PGA_STRAT_FALLBACK, 7765 #endif 7766 arm_poolpage_vmfreelist); 7767 } 7768 7769 return uvm_pagealloc(NULL, 0, NULL, flags); 7770 } 7771 #endif 7772 7773 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7774 void 7775 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7776 { 7777 /* nothing */ 7778 } 7779 7780 int 7781 pic_ipi_shootdown(void *arg) 7782 { 7783 #if PMAP_NEED_TLB_SHOOTDOWN 7784 pmap_tlb_shootdown_process(); 7785 #endif 7786 return 1; 7787 } 7788 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7789 7790 7791 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7792 vaddr_t 7793 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7794 { 7795 bool ok = false; 7796 if (physical_start <= pa && pa < physical_end) { 7797 #ifdef ARM_MMU_EXTENDED 7798 const vaddr_t newva = pmap_directbase + pa - physical_start; 7799 if (newva >= KERNEL_BASE) { 7800 va = newva; 7801 ok = true; 7802 } 7803 #else 7804 va = KERNEL_BASE + pa - physical_start; 7805 ok = true; 7806 #endif 7807 } 7808 KASSERT(ok_p); 7809 *ok_p = ok; 7810 return va; 7811 } 7812 7813 vaddr_t 7814 pmap_map_poolpage(paddr_t pa) 7815 { 7816 bool ok __diagused; 7817 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7818 KASSERT(ok); 7819 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7820 if (arm_cache_prefer_mask != 0) { 7821 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7822 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7823 pmap_acquire_page_lock(md); 7824 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7825 pmap_release_page_lock(md); 7826 } 7827 #endif 7828 return va; 7829 } 7830 7831 paddr_t 7832 pmap_unmap_poolpage(vaddr_t va) 7833 { 7834 KASSERT(va >= KERNEL_BASE); 7835 #if defined(ARM_MMU_EXTENDED) 7836 return va - pmap_directbase + physical_start; 7837 #else 7838 #ifdef PMAP_CACHE_VIVT 7839 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7840 #endif 7841 return va - KERNEL_BASE + physical_start; 7842 #endif 7843 } 7844 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7845
Indexes created Mon Sep 29 18:09:42 GMT 2025