pmap.c revision 1.304
1 /* $NetBSD: pmap.c,v 1.304 2014/10/20 07:13:27 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 //#include <arm/arm32/katelib.h> 218 219 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.304 2014/10/20 07:13:27 skrll Exp $"); 220 221 //#define PMAP_DEBUG 222 #ifdef PMAP_DEBUG 223 224 /* XXX need to get rid of all refs to this */ 225 int pmap_debug_level = 0; 226 227 /* 228 * for switching to potentially finer grained debugging 229 */ 230 #define PDB_FOLLOW 0x0001 231 #define PDB_INIT 0x0002 232 #define PDB_ENTER 0x0004 233 #define PDB_REMOVE 0x0008 234 #define PDB_CREATE 0x0010 235 #define PDB_PTPAGE 0x0020 236 #define PDB_GROWKERN 0x0040 237 #define PDB_BITS 0x0080 238 #define PDB_COLLECT 0x0100 239 #define PDB_PROTECT 0x0200 240 #define PDB_MAP_L1 0x0400 241 #define PDB_BOOTSTRAP 0x1000 242 #define PDB_PARANOIA 0x2000 243 #define PDB_WIRING 0x4000 244 #define PDB_PVDUMP 0x8000 245 #define PDB_VAC 0x10000 246 #define PDB_KENTER 0x20000 247 #define PDB_KREMOVE 0x40000 248 #define PDB_EXEC 0x80000 249 250 int debugmap = 1; 251 int pmapdebug = 0; 252 #define NPDEBUG(_lev_,_stat_) \ 253 if (pmapdebug & (_lev_)) \ 254 ((_stat_)) 255 256 #else /* PMAP_DEBUG */ 257 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 258 #endif /* PMAP_DEBUG */ 259 260 /* 261 * pmap_kernel() points here 262 */ 263 static struct pmap kernel_pmap_store = { 264 #ifndef ARM_MMU_EXTENDED 265 .pm_activated = true, 266 .pm_domain = PMAP_DOMAIN_KERNEL, 267 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 268 #endif 269 }; 270 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 271 #undef pmap_kernel 272 #define pmap_kernel() (&kernel_pmap_store) 273 #ifdef PMAP_NEED_ALLOC_POOLPAGE 274 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 275 #endif 276 277 /* 278 * Pool and cache that pmap structures are allocated from. 279 * We use a cache to avoid clearing the pm_l2[] array (1KB) 280 * in pmap_create(). 281 */ 282 static struct pool_cache pmap_cache; 283 static LIST_HEAD(, pmap) pmap_pmaps; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 static struct evcnt pmap_ev_exec_synced_map = 426 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 427 #ifndef ARM_MMU_EXTENDED 428 static struct evcnt pmap_ev_exec_synced_unmap = 429 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 430 static struct evcnt pmap_ev_exec_synced_remap = 431 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 432 static struct evcnt pmap_ev_exec_synced_clearbit = 433 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 440 #ifndef ARM_MMU_EXTENDED 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 /* 489 * pmap copy/zero page, and mem(5) hook point 490 */ 491 static pt_entry_t *csrc_pte, *cdst_pte; 492 static vaddr_t csrcp, cdstp; 493 #ifdef MULTIPROCESSOR 494 static size_t cnptes; 495 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 497 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 499 #else 500 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + (o)) 503 #define cpu_cdstp(o) (cdstp + (o)) 504 #endif 505 vaddr_t memhook; /* used by mem.c & others */ 506 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 507 kmutex_t pmap_lock __cacheline_aligned; 508 extern void *msgbufaddr; 509 int pmap_kmpages; 510 /* 511 * Flag to indicate if pmap_init() has done its thing 512 */ 513 bool pmap_initialized; 514 515 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 516 /* 517 * Start of direct-mapped memory 518 */ 519 vaddr_t pmap_directbase = KERNEL_BASE; 520 #endif 521 522 /* 523 * Misc. locking data structures 524 */ 525 526 static inline void 527 pmap_acquire_pmap_lock(pmap_t pm) 528 { 529 if (pm == pmap_kernel()) { 530 #ifdef MULTIPROCESSOR 531 KERNEL_LOCK(1, NULL); 532 #endif 533 } else { 534 mutex_enter(pm->pm_lock); 535 } 536 } 537 538 static inline void 539 pmap_release_pmap_lock(pmap_t pm) 540 { 541 if (pm == pmap_kernel()) { 542 #ifdef MULTIPROCESSOR 543 KERNEL_UNLOCK_ONE(NULL); 544 #endif 545 } else { 546 mutex_exit(pm->pm_lock); 547 } 548 } 549 550 static inline void 551 pmap_acquire_page_lock(struct vm_page_md *md) 552 { 553 mutex_enter(&pmap_lock); 554 } 555 556 static inline void 557 pmap_release_page_lock(struct vm_page_md *md) 558 { 559 mutex_exit(&pmap_lock); 560 } 561 562 #ifdef DIAGNOSTIC 563 static inline int 564 pmap_page_locked_p(struct vm_page_md *md) 565 { 566 return mutex_owned(&pmap_lock); 567 } 568 #endif 569 570 571 /* 572 * Metadata for L1 translation tables. 573 */ 574 #ifndef ARM_MMU_EXTENDED 575 struct l1_ttable { 576 /* Entry on the L1 Table list */ 577 SLIST_ENTRY(l1_ttable) l1_link; 578 579 /* Entry on the L1 Least Recently Used list */ 580 TAILQ_ENTRY(l1_ttable) l1_lru; 581 582 /* Track how many domains are allocated from this L1 */ 583 volatile u_int l1_domain_use_count; 584 585 /* 586 * A free-list of domain numbers for this L1. 587 * We avoid using ffs() and a bitmap to track domains since ffs() 588 * is slow on ARM. 589 */ 590 uint8_t l1_domain_first; 591 uint8_t l1_domain_free[PMAP_DOMAINS]; 592 593 /* Physical address of this L1 page table */ 594 paddr_t l1_physaddr; 595 596 /* KVA of this L1 page table */ 597 pd_entry_t *l1_kva; 598 }; 599 600 /* 601 * L1 Page Tables are tracked using a Least Recently Used list. 602 * - New L1s are allocated from the HEAD. 603 * - Freed L1s are added to the TAIl. 604 * - Recently accessed L1s (where an 'access' is some change to one of 605 * the userland pmaps which owns this L1) are moved to the TAIL. 606 */ 607 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 608 static kmutex_t l1_lru_lock __cacheline_aligned; 609 610 /* 611 * A list of all L1 tables 612 */ 613 static SLIST_HEAD(, l1_ttable) l1_list; 614 #endif /* ARM_MMU_EXTENDED */ 615 616 /* 617 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 618 * 619 * This is normally 16MB worth L2 page descriptors for any given pmap. 620 * Reference counts are maintained for L2 descriptors so they can be 621 * freed when empty. 622 */ 623 struct l2_bucket { 624 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 625 paddr_t l2b_pa; /* Physical address of same */ 626 u_short l2b_l1slot; /* This L2 table's L1 index */ 627 u_short l2b_occupancy; /* How many active descriptors */ 628 }; 629 630 struct l2_dtable { 631 /* The number of L2 page descriptors allocated to this l2_dtable */ 632 u_int l2_occupancy; 633 634 /* List of L2 page descriptors */ 635 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 636 }; 637 638 /* 639 * Given an L1 table index, calculate the corresponding l2_dtable index 640 * and bucket index within the l2_dtable. 641 */ 642 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 643 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 644 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 645 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 646 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 647 648 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 649 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 650 651 /* 652 * Given a virtual address, this macro returns the 653 * virtual address required to drop into the next L2 bucket. 654 */ 655 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 656 657 /* 658 * L2 allocation. 659 */ 660 #define pmap_alloc_l2_dtable() \ 661 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 662 #define pmap_free_l2_dtable(l2) \ 663 pool_cache_put(&pmap_l2dtable_cache, (l2)) 664 #define pmap_alloc_l2_ptp(pap) \ 665 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 666 PR_NOWAIT, (pap))) 667 668 /* 669 * We try to map the page tables write-through, if possible. However, not 670 * all CPUs have a write-through cache mode, so on those we have to sync 671 * the cache when we frob page tables. 672 * 673 * We try to evaluate this at compile time, if possible. However, it's 674 * not always possible to do that, hence this run-time var. 675 */ 676 int pmap_needs_pte_sync; 677 678 /* 679 * Real definition of pv_entry. 680 */ 681 struct pv_entry { 682 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 683 pmap_t pv_pmap; /* pmap where mapping lies */ 684 vaddr_t pv_va; /* virtual address for mapping */ 685 u_int pv_flags; /* flags */ 686 }; 687 688 /* 689 * Macros to determine if a mapping might be resident in the 690 * instruction/data cache and/or TLB 691 */ 692 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 693 /* 694 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 695 * there are no explicit accesses, so there may be always be TLB entries to 696 * flush. If we used ASIDs then this would not be a problem. 697 */ 698 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 699 #define PV_BEEN_REFD(f) (true) 700 #else 701 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 702 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 703 #endif 704 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 705 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 706 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 707 708 /* 709 * Local prototypes 710 */ 711 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 712 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 713 pt_entry_t **); 714 static bool pmap_is_current(pmap_t) __unused; 715 static bool pmap_is_cached(pmap_t); 716 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 717 pmap_t, vaddr_t, u_int); 718 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 719 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 720 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 721 u_int, u_int); 722 723 static void pmap_pinit(pmap_t); 724 static int pmap_pmap_ctor(void *, void *, int); 725 726 static void pmap_alloc_l1(pmap_t); 727 static void pmap_free_l1(pmap_t); 728 #ifndef ARM_MMU_EXTENDED 729 static void pmap_use_l1(pmap_t); 730 #endif 731 732 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 733 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 734 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 735 static int pmap_l2ptp_ctor(void *, void *, int); 736 static int pmap_l2dtable_ctor(void *, void *, int); 737 738 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 739 #ifdef PMAP_CACHE_VIVT 740 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 741 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 742 #endif 743 744 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 745 #ifdef PMAP_CACHE_VIVT 746 static bool pmap_clean_page(struct vm_page_md *, bool); 747 #endif 748 #ifdef PMAP_CACHE_VIPT 749 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 750 enum pmap_flush_op { 751 PMAP_FLUSH_PRIMARY, 752 PMAP_FLUSH_SECONDARY, 753 PMAP_CLEAN_PRIMARY 754 }; 755 #ifndef ARM_MMU_EXTENDED 756 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 757 #endif 758 #endif 759 static void pmap_page_remove(struct vm_page_md *, paddr_t); 760 761 #ifndef ARM_MMU_EXTENDED 762 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 763 #endif 764 static vaddr_t kernel_pt_lookup(paddr_t); 765 766 767 /* 768 * Misc variables 769 */ 770 vaddr_t virtual_avail; 771 vaddr_t virtual_end; 772 vaddr_t pmap_curmaxkvaddr; 773 774 paddr_t avail_start; 775 paddr_t avail_end; 776 777 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 778 pv_addr_t kernelpages; 779 pv_addr_t kernel_l1pt; 780 pv_addr_t systempage; 781 782 /* Function to set the debug level of the pmap code */ 783 784 #ifdef PMAP_DEBUG 785 void 786 pmap_debug(int level) 787 { 788 pmap_debug_level = level; 789 printf("pmap_debug: level=%d\n", pmap_debug_level); 790 } 791 #endif /* PMAP_DEBUG */ 792 793 #ifdef PMAP_CACHE_VIPT 794 #define PMAP_VALIDATE_MD_PAGE(md) \ 795 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 796 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 797 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 798 #endif /* PMAP_CACHE_VIPT */ 799 /* 800 * A bunch of routines to conditionally flush the caches/TLB depending 801 * on whether the specified pmap actually needs to be flushed at any 802 * given time. 803 */ 804 static inline void 805 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 806 { 807 #ifdef ARM_MMU_EXTENDED 808 pmap_tlb_invalidate_addr(pm, va); 809 #else 810 if (pm->pm_cstate.cs_tlb_id != 0) { 811 if (PV_BEEN_EXECD(flags)) { 812 cpu_tlb_flushID_SE(va); 813 } else if (PV_BEEN_REFD(flags)) { 814 cpu_tlb_flushD_SE(va); 815 } 816 } 817 #endif /* ARM_MMU_EXTENDED */ 818 } 819 820 static inline void 821 pmap_tlb_flushID(pmap_t pm) 822 { 823 #ifdef ARM_MMU_EXTENDED 824 pmap_tlb_asid_release_all(pm); 825 #else 826 if (pm->pm_cstate.cs_tlb_id) { 827 cpu_tlb_flushID(); 828 #if ARM_MMU_V7 == 0 829 /* 830 * Speculative loads by Cortex cores can cause TLB entries to 831 * be filled even if there are no explicit accesses, so there 832 * may be always be TLB entries to flush. If we used ASIDs 833 * then it would not be a problem. 834 * This is not true for other CPUs. 835 */ 836 pm->pm_cstate.cs_tlb = 0; 837 #endif /* ARM_MMU_V7 */ 838 } 839 #endif /* ARM_MMU_EXTENDED */ 840 } 841 842 static inline void 843 pmap_tlb_flushD(pmap_t pm) 844 { 845 #ifdef ARM_MMU_EXTENDED 846 pmap_tlb_asid_release_all(pm); 847 #else 848 if (pm->pm_cstate.cs_tlb_d) { 849 cpu_tlb_flushD(); 850 #if ARM_MMU_V7 == 0 851 /* 852 * Speculative loads by Cortex cores can cause TLB entries to 853 * be filled even if there are no explicit accesses, so there 854 * may be always be TLB entries to flush. If we used ASIDs 855 * then it would not be a problem. 856 * This is not true for other CPUs. 857 */ 858 pm->pm_cstate.cs_tlb_d = 0; 859 #endif /* ARM_MMU_V7 */ 860 } 861 #endif /* ARM_MMU_EXTENDED */ 862 } 863 864 #ifdef PMAP_CACHE_VIVT 865 static inline void 866 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 867 { 868 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 869 cpu_idcache_wbinv_range(va, PAGE_SIZE); 870 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 871 if (do_inv) { 872 if (flags & PVF_WRITE) 873 cpu_dcache_wbinv_range(va, PAGE_SIZE); 874 else 875 cpu_dcache_inv_range(va, PAGE_SIZE); 876 } else if (flags & PVF_WRITE) { 877 cpu_dcache_wb_range(va, PAGE_SIZE); 878 } 879 } 880 } 881 882 static inline void 883 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 884 { 885 if (PV_BEEN_EXECD(flags)) { 886 if (pm->pm_cstate.cs_cache_id) { 887 cpu_idcache_wbinv_all(); 888 pm->pm_cstate.cs_cache = 0; 889 } 890 } else if (pm->pm_cstate.cs_cache_d) { 891 cpu_dcache_wbinv_all(); 892 pm->pm_cstate.cs_cache_d = 0; 893 } 894 } 895 #endif /* PMAP_CACHE_VIVT */ 896 897 static inline uint8_t 898 pmap_domain(pmap_t pm) 899 { 900 #ifdef ARM_MMU_EXTENDED 901 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 902 #else 903 return pm->pm_domain; 904 #endif 905 } 906 907 static inline pd_entry_t * 908 pmap_l1_kva(pmap_t pm) 909 { 910 #ifdef ARM_MMU_EXTENDED 911 return pm->pm_l1; 912 #else 913 return pm->pm_l1->l1_kva; 914 #endif 915 } 916 917 static inline bool 918 pmap_is_current(pmap_t pm) 919 { 920 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 921 return true; 922 923 return false; 924 } 925 926 static inline bool 927 pmap_is_cached(pmap_t pm) 928 { 929 #ifdef ARM_MMU_EXTENDED 930 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 931 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 932 return true; 933 #else 934 struct cpu_info * const ci = curcpu(); 935 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 936 || ci->ci_pmap_lastuser == pm) 937 return true; 938 #endif /* ARM_MMU_EXTENDED */ 939 940 return false; 941 } 942 943 /* 944 * PTE_SYNC_CURRENT: 945 * 946 * Make sure the pte is written out to RAM. 947 * We need to do this for one of two cases: 948 * - We're dealing with the kernel pmap 949 * - There is no pmap active in the cache/tlb. 950 * - The specified pmap is 'active' in the cache/tlb. 951 */ 952 #ifdef PMAP_INCLUDE_PTE_SYNC 953 #define PTE_SYNC_CURRENT(pm, ptep) \ 954 do { \ 955 if (PMAP_NEEDS_PTE_SYNC && \ 956 pmap_is_cached(pm)) \ 957 PTE_SYNC(ptep); \ 958 } while (/*CONSTCOND*/0) 959 #else 960 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 961 #endif 962 963 /* 964 * main pv_entry manipulation functions: 965 * pmap_enter_pv: enter a mapping onto a vm_page list 966 * pmap_remove_pv: remove a mapping from a vm_page list 967 * 968 * NOTE: pmap_enter_pv expects to lock the pvh itself 969 * pmap_remove_pv expects the caller to lock the pvh before calling 970 */ 971 972 /* 973 * pmap_enter_pv: enter a mapping onto a vm_page lst 974 * 975 * => caller should hold the proper lock on pmap_main_lock 976 * => caller should have pmap locked 977 * => we will gain the lock on the vm_page and allocate the new pv_entry 978 * => caller should adjust ptp's wire_count before calling 979 * => caller should not adjust pmap's wire_count 980 */ 981 static void 982 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 983 vaddr_t va, u_int flags) 984 { 985 struct pv_entry **pvp; 986 987 NPDEBUG(PDB_PVDUMP, 988 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 989 990 pv->pv_pmap = pm; 991 pv->pv_va = va; 992 pv->pv_flags = flags; 993 994 pvp = &SLIST_FIRST(&md->pvh_list); 995 #ifdef PMAP_CACHE_VIPT 996 /* 997 * Insert unmanaged entries, writeable first, at the head of 998 * the pv list. 999 */ 1000 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1001 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1002 pvp = &SLIST_NEXT(*pvp, pv_link); 1003 } 1004 if (!PV_IS_WRITE_P(flags)) { 1005 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1006 pvp = &SLIST_NEXT(*pvp, pv_link); 1007 } 1008 #endif 1009 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1010 *pvp = pv; /* ... locked list */ 1011 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1012 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1013 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1014 md->pvh_attrs |= PVF_KMOD; 1015 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1016 md->pvh_attrs |= PVF_DIRTY; 1017 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1018 #endif 1019 if (pm == pmap_kernel()) { 1020 PMAPCOUNT(kernel_mappings); 1021 if (flags & PVF_WRITE) 1022 md->krw_mappings++; 1023 else 1024 md->kro_mappings++; 1025 } else { 1026 if (flags & PVF_WRITE) 1027 md->urw_mappings++; 1028 else 1029 md->uro_mappings++; 1030 } 1031 1032 #ifdef PMAP_CACHE_VIPT 1033 #ifndef ARM_MMU_EXTENDED 1034 /* 1035 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1036 * do it here as well to keep the mappings & KVF_WRITE consistent. 1037 */ 1038 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1039 md->pvh_attrs |= PVF_WRITE; 1040 } 1041 #endif 1042 /* 1043 * If this is an exec mapping and its the first exec mapping 1044 * for this page, make sure to sync the I-cache. 1045 */ 1046 if (PV_IS_EXEC_P(flags)) { 1047 #ifndef ARM_MMU_EXTENDED 1048 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1049 pmap_syncicache_page(md, pa); 1050 PMAPCOUNT(exec_synced_map); 1051 } 1052 #endif 1053 PMAPCOUNT(exec_mappings); 1054 } 1055 #endif 1056 1057 PMAPCOUNT(mappings); 1058 1059 if (pv->pv_flags & PVF_WIRED) 1060 ++pm->pm_stats.wired_count; 1061 } 1062 1063 /* 1064 * 1065 * pmap_find_pv: Find a pv entry 1066 * 1067 * => caller should hold lock on vm_page 1068 */ 1069 static inline struct pv_entry * 1070 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1071 { 1072 struct pv_entry *pv; 1073 1074 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1075 if (pm == pv->pv_pmap && va == pv->pv_va) 1076 break; 1077 } 1078 1079 return (pv); 1080 } 1081 1082 /* 1083 * pmap_remove_pv: try to remove a mapping from a pv_list 1084 * 1085 * => caller should hold proper lock on pmap_main_lock 1086 * => pmap should be locked 1087 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1088 * => caller should adjust ptp's wire_count and free PTP if needed 1089 * => caller should NOT adjust pmap's wire_count 1090 * => we return the removed pv 1091 */ 1092 static struct pv_entry * 1093 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1094 { 1095 struct pv_entry *pv, **prevptr; 1096 1097 NPDEBUG(PDB_PVDUMP, 1098 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1099 1100 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1101 pv = *prevptr; 1102 1103 while (pv) { 1104 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1105 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1106 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1107 if (pv->pv_flags & PVF_WIRED) { 1108 --pm->pm_stats.wired_count; 1109 } 1110 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1111 if (pm == pmap_kernel()) { 1112 PMAPCOUNT(kernel_unmappings); 1113 if (pv->pv_flags & PVF_WRITE) 1114 md->krw_mappings--; 1115 else 1116 md->kro_mappings--; 1117 } else { 1118 if (pv->pv_flags & PVF_WRITE) 1119 md->urw_mappings--; 1120 else 1121 md->uro_mappings--; 1122 } 1123 1124 PMAPCOUNT(unmappings); 1125 #ifdef PMAP_CACHE_VIPT 1126 if (!(pv->pv_flags & PVF_WRITE)) 1127 break; 1128 /* 1129 * If this page has had an exec mapping, then if 1130 * this was the last mapping, discard the contents, 1131 * otherwise sync the i-cache for this page. 1132 */ 1133 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1134 #ifdef ARM_MMU_EXTENDED 1135 md->pvh_attrs &= ~PVF_EXEC; 1136 PMAPCOUNT(exec_discarded_unmap); 1137 #else 1138 if (SLIST_EMPTY(&md->pvh_list)) { 1139 md->pvh_attrs &= ~PVF_EXEC; 1140 PMAPCOUNT(exec_discarded_unmap); 1141 } else { 1142 pmap_syncicache_page(md, pa); 1143 PMAPCOUNT(exec_synced_unmap); 1144 } 1145 #endif /* ARM_MMU_EXTENDED */ 1146 } 1147 #endif /* PMAP_CACHE_VIPT */ 1148 break; 1149 } 1150 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1151 pv = *prevptr; /* advance */ 1152 } 1153 1154 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1155 /* 1156 * If we no longer have a WRITEABLE KENTRY at the head of list, 1157 * clear the KMOD attribute from the page. 1158 */ 1159 if (SLIST_FIRST(&md->pvh_list) == NULL 1160 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1161 md->pvh_attrs &= ~PVF_KMOD; 1162 1163 /* 1164 * If this was a writeable page and there are no more writeable 1165 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1166 * the contents to memory. 1167 */ 1168 if (arm_cache_prefer_mask != 0) { 1169 if (md->krw_mappings + md->urw_mappings == 0) 1170 md->pvh_attrs &= ~PVF_WRITE; 1171 PMAP_VALIDATE_MD_PAGE(md); 1172 } 1173 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1174 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1175 1176 return(pv); /* return removed pv */ 1177 } 1178 1179 /* 1180 * 1181 * pmap_modify_pv: Update pv flags 1182 * 1183 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1184 * => caller should NOT adjust pmap's wire_count 1185 * => caller must call pmap_vac_me_harder() if writable status of a page 1186 * may have changed. 1187 * => we return the old flags 1188 * 1189 * Modify a physical-virtual mapping in the pv table 1190 */ 1191 static u_int 1192 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1193 u_int clr_mask, u_int set_mask) 1194 { 1195 struct pv_entry *npv; 1196 u_int flags, oflags; 1197 1198 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1199 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1200 1201 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1202 return (0); 1203 1204 NPDEBUG(PDB_PVDUMP, 1205 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1206 1207 /* 1208 * There is at least one VA mapping this page. 1209 */ 1210 1211 if (clr_mask & (PVF_REF | PVF_MOD)) { 1212 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1213 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1214 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1215 md->pvh_attrs |= PVF_DIRTY; 1216 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1217 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1218 } 1219 1220 oflags = npv->pv_flags; 1221 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1222 1223 if ((flags ^ oflags) & PVF_WIRED) { 1224 if (flags & PVF_WIRED) 1225 ++pm->pm_stats.wired_count; 1226 else 1227 --pm->pm_stats.wired_count; 1228 } 1229 1230 if ((flags ^ oflags) & PVF_WRITE) { 1231 if (pm == pmap_kernel()) { 1232 if (flags & PVF_WRITE) { 1233 md->krw_mappings++; 1234 md->kro_mappings--; 1235 } else { 1236 md->kro_mappings++; 1237 md->krw_mappings--; 1238 } 1239 } else { 1240 if (flags & PVF_WRITE) { 1241 md->urw_mappings++; 1242 md->uro_mappings--; 1243 } else { 1244 md->uro_mappings++; 1245 md->urw_mappings--; 1246 } 1247 } 1248 } 1249 #ifdef PMAP_CACHE_VIPT 1250 if (arm_cache_prefer_mask != 0) { 1251 if (md->urw_mappings + md->krw_mappings == 0) { 1252 md->pvh_attrs &= ~PVF_WRITE; 1253 } else { 1254 md->pvh_attrs |= PVF_WRITE; 1255 } 1256 } 1257 #ifndef ARM_MMU_EXTENDED 1258 /* 1259 * We have two cases here: the first is from enter_pv (new exec 1260 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1261 * Since in latter, pmap_enter_pv won't do anything, we just have 1262 * to do what pmap_remove_pv would do. 1263 */ 1264 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1265 || (PV_IS_EXEC_P(md->pvh_attrs) 1266 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1267 pmap_syncicache_page(md, pa); 1268 PMAPCOUNT(exec_synced_remap); 1269 } 1270 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1271 #endif /* !ARM_MMU_EXTENDED */ 1272 #endif /* PMAP_CACHE_VIPT */ 1273 1274 PMAPCOUNT(remappings); 1275 1276 return (oflags); 1277 } 1278 1279 /* 1280 * Allocate an L1 translation table for the specified pmap. 1281 * This is called at pmap creation time. 1282 */ 1283 static void 1284 pmap_alloc_l1(pmap_t pm) 1285 { 1286 #ifdef ARM_MMU_EXTENDED 1287 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1288 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1289 struct vm_page *pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1290 #else 1291 struct vm_page *pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1292 #endif 1293 bool ok __diagused; 1294 KASSERT(pg != NULL); 1295 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1296 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1297 KASSERT(ok); 1298 KASSERT(va >= KERNEL_BASE); 1299 1300 #else 1301 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1302 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1303 UVM_KMF_WIRED|UVM_KMF_ZERO); 1304 KASSERT(va); 1305 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1306 #endif 1307 pm->pm_l1 = (pd_entry_t *)va; 1308 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1309 #else 1310 struct l1_ttable *l1; 1311 uint8_t domain; 1312 1313 /* 1314 * Remove the L1 at the head of the LRU list 1315 */ 1316 mutex_spin_enter(&l1_lru_lock); 1317 l1 = TAILQ_FIRST(&l1_lru_list); 1318 KDASSERT(l1 != NULL); 1319 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1320 1321 /* 1322 * Pick the first available domain number, and update 1323 * the link to the next number. 1324 */ 1325 domain = l1->l1_domain_first; 1326 l1->l1_domain_first = l1->l1_domain_free[domain]; 1327 1328 /* 1329 * If there are still free domain numbers in this L1, 1330 * put it back on the TAIL of the LRU list. 1331 */ 1332 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1333 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1334 1335 mutex_spin_exit(&l1_lru_lock); 1336 1337 /* 1338 * Fix up the relevant bits in the pmap structure 1339 */ 1340 pm->pm_l1 = l1; 1341 pm->pm_domain = domain + 1; 1342 #endif 1343 } 1344 1345 /* 1346 * Free an L1 translation table. 1347 * This is called at pmap destruction time. 1348 */ 1349 static void 1350 pmap_free_l1(pmap_t pm) 1351 { 1352 #ifdef ARM_MMU_EXTENDED 1353 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1354 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1355 uvm_pagefree(pg); 1356 #else 1357 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1358 #endif 1359 pm->pm_l1 = NULL; 1360 pm->pm_l1_pa = 0; 1361 #else 1362 struct l1_ttable *l1 = pm->pm_l1; 1363 1364 mutex_spin_enter(&l1_lru_lock); 1365 1366 /* 1367 * If this L1 is currently on the LRU list, remove it. 1368 */ 1369 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1370 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1371 1372 /* 1373 * Free up the domain number which was allocated to the pmap 1374 */ 1375 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1376 l1->l1_domain_first = pmap_domain(pm) - 1; 1377 l1->l1_domain_use_count--; 1378 1379 /* 1380 * The L1 now must have at least 1 free domain, so add 1381 * it back to the LRU list. If the use count is zero, 1382 * put it at the head of the list, otherwise it goes 1383 * to the tail. 1384 */ 1385 if (l1->l1_domain_use_count == 0) 1386 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1387 else 1388 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1389 1390 mutex_spin_exit(&l1_lru_lock); 1391 #endif /* ARM_MMU_EXTENDED */ 1392 } 1393 1394 #ifndef ARM_MMU_EXTENDED 1395 static inline void 1396 pmap_use_l1(pmap_t pm) 1397 { 1398 struct l1_ttable *l1; 1399 1400 /* 1401 * Do nothing if we're in interrupt context. 1402 * Access to an L1 by the kernel pmap must not affect 1403 * the LRU list. 1404 */ 1405 if (cpu_intr_p() || pm == pmap_kernel()) 1406 return; 1407 1408 l1 = pm->pm_l1; 1409 1410 /* 1411 * If the L1 is not currently on the LRU list, just return 1412 */ 1413 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1414 return; 1415 1416 mutex_spin_enter(&l1_lru_lock); 1417 1418 /* 1419 * Check the use count again, now that we've acquired the lock 1420 */ 1421 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1422 mutex_spin_exit(&l1_lru_lock); 1423 return; 1424 } 1425 1426 /* 1427 * Move the L1 to the back of the LRU list 1428 */ 1429 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1430 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1431 1432 mutex_spin_exit(&l1_lru_lock); 1433 } 1434 #endif /* !ARM_MMU_EXTENDED */ 1435 1436 /* 1437 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1438 * 1439 * Free an L2 descriptor table. 1440 */ 1441 static inline void 1442 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1443 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1444 #else 1445 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1446 #endif 1447 { 1448 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1449 /* 1450 * Note: With a write-back cache, we may need to sync this 1451 * L2 table before re-using it. 1452 * This is because it may have belonged to a non-current 1453 * pmap, in which case the cache syncs would have been 1454 * skipped for the pages that were being unmapped. If the 1455 * L2 table were then to be immediately re-allocated to 1456 * the *current* pmap, it may well contain stale mappings 1457 * which have not yet been cleared by a cache write-back 1458 * and so would still be visible to the mmu. 1459 */ 1460 if (need_sync) 1461 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1462 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1463 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1464 } 1465 1466 /* 1467 * Returns a pointer to the L2 bucket associated with the specified pmap 1468 * and VA, or NULL if no L2 bucket exists for the address. 1469 */ 1470 static inline struct l2_bucket * 1471 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1472 { 1473 const size_t l1slot = l1pte_index(va); 1474 struct l2_dtable *l2; 1475 struct l2_bucket *l2b; 1476 1477 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1478 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1479 return (NULL); 1480 1481 return (l2b); 1482 } 1483 1484 /* 1485 * Returns a pointer to the L2 bucket associated with the specified pmap 1486 * and VA. 1487 * 1488 * If no L2 bucket exists, perform the necessary allocations to put an L2 1489 * bucket/page table in place. 1490 * 1491 * Note that if a new L2 bucket/page was allocated, the caller *must* 1492 * increment the bucket occupancy counter appropriately *before* 1493 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1494 * the bucket/page in the meantime. 1495 */ 1496 static struct l2_bucket * 1497 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1498 { 1499 const size_t l1slot = l1pte_index(va); 1500 struct l2_dtable *l2; 1501 1502 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1503 /* 1504 * No mapping at this address, as there is 1505 * no entry in the L1 table. 1506 * Need to allocate a new l2_dtable. 1507 */ 1508 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1509 return (NULL); 1510 1511 /* 1512 * Link it into the parent pmap 1513 */ 1514 pm->pm_l2[L2_IDX(l1slot)] = l2; 1515 } 1516 1517 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1518 1519 /* 1520 * Fetch pointer to the L2 page table associated with the address. 1521 */ 1522 if (l2b->l2b_kva == NULL) { 1523 pt_entry_t *ptep; 1524 1525 /* 1526 * No L2 page table has been allocated. Chances are, this 1527 * is because we just allocated the l2_dtable, above. 1528 */ 1529 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1530 /* 1531 * Oops, no more L2 page tables available at this 1532 * time. We may need to deallocate the l2_dtable 1533 * if we allocated a new one above. 1534 */ 1535 if (l2->l2_occupancy == 0) { 1536 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1537 pmap_free_l2_dtable(l2); 1538 } 1539 return (NULL); 1540 } 1541 1542 l2->l2_occupancy++; 1543 l2b->l2b_kva = ptep; 1544 l2b->l2b_l1slot = l1slot; 1545 1546 #ifdef ARM_MMU_EXTENDED 1547 /* 1548 * We know there will be a mapping here, so simply 1549 * enter this PTP into the L1 now. 1550 */ 1551 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1552 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1553 | L1_C_DOM(pmap_domain(pm)); 1554 KASSERT(*pdep == 0); 1555 l1pte_setone(pdep, npde); 1556 PTE_SYNC(pdep); 1557 #endif 1558 } 1559 1560 return (l2b); 1561 } 1562 1563 /* 1564 * One or more mappings in the specified L2 descriptor table have just been 1565 * invalidated. 1566 * 1567 * Garbage collect the metadata and descriptor table itself if necessary. 1568 * 1569 * The pmap lock must be acquired when this is called (not necessary 1570 * for the kernel pmap). 1571 */ 1572 static void 1573 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1574 { 1575 KDASSERT(count <= l2b->l2b_occupancy); 1576 1577 /* 1578 * Update the bucket's reference count according to how many 1579 * PTEs the caller has just invalidated. 1580 */ 1581 l2b->l2b_occupancy -= count; 1582 1583 /* 1584 * Note: 1585 * 1586 * Level 2 page tables allocated to the kernel pmap are never freed 1587 * as that would require checking all Level 1 page tables and 1588 * removing any references to the Level 2 page table. See also the 1589 * comment elsewhere about never freeing bootstrap L2 descriptors. 1590 * 1591 * We make do with just invalidating the mapping in the L2 table. 1592 * 1593 * This isn't really a big deal in practice and, in fact, leads 1594 * to a performance win over time as we don't need to continually 1595 * alloc/free. 1596 */ 1597 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1598 return; 1599 1600 /* 1601 * There are no more valid mappings in this level 2 page table. 1602 * Go ahead and NULL-out the pointer in the bucket, then 1603 * free the page table. 1604 */ 1605 const size_t l1slot = l2b->l2b_l1slot; 1606 pt_entry_t * const ptep = l2b->l2b_kva; 1607 l2b->l2b_kva = NULL; 1608 1609 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1610 pd_entry_t pde __diagused = *pdep; 1611 1612 #ifdef ARM_MMU_EXTENDED 1613 /* 1614 * Invalidate the L1 slot. 1615 */ 1616 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1617 #else 1618 /* 1619 * If the L1 slot matches the pmap's domain number, then invalidate it. 1620 */ 1621 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1622 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1623 #endif 1624 l1pte_setone(pdep, 0); 1625 PDE_SYNC(pdep); 1626 #ifndef ARM_MMU_EXTENDED 1627 } 1628 #endif 1629 1630 /* 1631 * Release the L2 descriptor table back to the pool cache. 1632 */ 1633 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1634 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1635 #else 1636 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1637 #endif 1638 1639 /* 1640 * Update the reference count in the associated l2_dtable 1641 */ 1642 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1643 if (--l2->l2_occupancy > 0) 1644 return; 1645 1646 /* 1647 * There are no more valid mappings in any of the Level 1 1648 * slots managed by this l2_dtable. Go ahead and NULL-out 1649 * the pointer in the parent pmap and free the l2_dtable. 1650 */ 1651 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1652 pmap_free_l2_dtable(l2); 1653 } 1654 1655 /* 1656 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1657 * structures. 1658 */ 1659 static int 1660 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1661 { 1662 #ifndef PMAP_INCLUDE_PTE_SYNC 1663 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1664 1665 /* 1666 * The mappings for these page tables were initially made using 1667 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1668 * mode will not be right for page table mappings. To avoid 1669 * polluting the pmap_kenter_pa() code with a special case for 1670 * page tables, we simply fix up the cache-mode here if it's not 1671 * correct. 1672 */ 1673 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1674 const struct l2_bucket * const l2b = 1675 pmap_get_l2_bucket(pmap_kernel(), va); 1676 KASSERTMSG(l2b != NULL, "%#lx", va); 1677 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1678 const pt_entry_t opte = *ptep; 1679 1680 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1681 /* 1682 * Page tables must have the cache-mode set correctly. 1683 */ 1684 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1685 | pte_l2_s_cache_mode_pt; 1686 l2pte_set(ptep, npte, opte); 1687 PTE_SYNC(ptep); 1688 cpu_tlb_flushD_SE(va); 1689 cpu_cpwait(); 1690 } 1691 } 1692 #endif 1693 1694 memset(v, 0, L2_TABLE_SIZE_REAL); 1695 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1696 return (0); 1697 } 1698 1699 static int 1700 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1701 { 1702 1703 memset(v, 0, sizeof(struct l2_dtable)); 1704 return (0); 1705 } 1706 1707 static int 1708 pmap_pmap_ctor(void *arg, void *v, int flags) 1709 { 1710 1711 memset(v, 0, sizeof(struct pmap)); 1712 return (0); 1713 } 1714 1715 static void 1716 pmap_pinit(pmap_t pm) 1717 { 1718 #ifndef ARM_HAS_VBAR 1719 struct l2_bucket *l2b; 1720 1721 if (vector_page < KERNEL_BASE) { 1722 /* 1723 * Map the vector page. 1724 */ 1725 pmap_enter(pm, vector_page, systempage.pv_pa, 1726 VM_PROT_READ | VM_PROT_EXECUTE, 1727 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1728 pmap_update(pm); 1729 1730 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1731 l2b = pmap_get_l2_bucket(pm, vector_page); 1732 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1733 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1734 L1_C_DOM(pmap_domain(pm)); 1735 } else 1736 pm->pm_pl1vec = NULL; 1737 #endif 1738 } 1739 1740 #ifdef PMAP_CACHE_VIVT 1741 /* 1742 * Since we have a virtually indexed cache, we may need to inhibit caching if 1743 * there is more than one mapping and at least one of them is writable. 1744 * Since we purge the cache on every context switch, we only need to check for 1745 * other mappings within the same pmap, or kernel_pmap. 1746 * This function is also called when a page is unmapped, to possibly reenable 1747 * caching on any remaining mappings. 1748 * 1749 * The code implements the following logic, where: 1750 * 1751 * KW = # of kernel read/write pages 1752 * KR = # of kernel read only pages 1753 * UW = # of user read/write pages 1754 * UR = # of user read only pages 1755 * 1756 * KC = kernel mapping is cacheable 1757 * UC = user mapping is cacheable 1758 * 1759 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1760 * +--------------------------------------------- 1761 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1762 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1763 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1764 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1765 */ 1766 1767 static const int pmap_vac_flags[4][4] = { 1768 {-1, 0, 0, PVF_KNC}, 1769 {0, 0, PVF_NC, PVF_NC}, 1770 {0, PVF_NC, PVF_NC, PVF_NC}, 1771 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1772 }; 1773 1774 static inline int 1775 pmap_get_vac_flags(const struct vm_page_md *md) 1776 { 1777 int kidx, uidx; 1778 1779 kidx = 0; 1780 if (md->kro_mappings || md->krw_mappings > 1) 1781 kidx |= 1; 1782 if (md->krw_mappings) 1783 kidx |= 2; 1784 1785 uidx = 0; 1786 if (md->uro_mappings || md->urw_mappings > 1) 1787 uidx |= 1; 1788 if (md->urw_mappings) 1789 uidx |= 2; 1790 1791 return (pmap_vac_flags[uidx][kidx]); 1792 } 1793 1794 static inline void 1795 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1796 { 1797 int nattr; 1798 1799 nattr = pmap_get_vac_flags(md); 1800 1801 if (nattr < 0) { 1802 md->pvh_attrs &= ~PVF_NC; 1803 return; 1804 } 1805 1806 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1807 return; 1808 1809 if (pm == pmap_kernel()) 1810 pmap_vac_me_kpmap(md, pa, pm, va); 1811 else 1812 pmap_vac_me_user(md, pa, pm, va); 1813 1814 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1815 } 1816 1817 static void 1818 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1819 { 1820 u_int u_cacheable, u_entries; 1821 struct pv_entry *pv; 1822 pmap_t last_pmap = pm; 1823 1824 /* 1825 * Pass one, see if there are both kernel and user pmaps for 1826 * this page. Calculate whether there are user-writable or 1827 * kernel-writable pages. 1828 */ 1829 u_cacheable = 0; 1830 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1831 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1832 u_cacheable++; 1833 } 1834 1835 u_entries = md->urw_mappings + md->uro_mappings; 1836 1837 /* 1838 * We know we have just been updating a kernel entry, so if 1839 * all user pages are already cacheable, then there is nothing 1840 * further to do. 1841 */ 1842 if (md->k_mappings == 0 && u_cacheable == u_entries) 1843 return; 1844 1845 if (u_entries) { 1846 /* 1847 * Scan over the list again, for each entry, if it 1848 * might not be set correctly, call pmap_vac_me_user 1849 * to recalculate the settings. 1850 */ 1851 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1852 /* 1853 * We know kernel mappings will get set 1854 * correctly in other calls. We also know 1855 * that if the pmap is the same as last_pmap 1856 * then we've just handled this entry. 1857 */ 1858 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1859 continue; 1860 1861 /* 1862 * If there are kernel entries and this page 1863 * is writable but non-cacheable, then we can 1864 * skip this entry also. 1865 */ 1866 if (md->k_mappings && 1867 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1868 (PVF_NC | PVF_WRITE)) 1869 continue; 1870 1871 /* 1872 * Similarly if there are no kernel-writable 1873 * entries and the page is already 1874 * read-only/cacheable. 1875 */ 1876 if (md->krw_mappings == 0 && 1877 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1878 continue; 1879 1880 /* 1881 * For some of the remaining cases, we know 1882 * that we must recalculate, but for others we 1883 * can't tell if they are correct or not, so 1884 * we recalculate anyway. 1885 */ 1886 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1887 } 1888 1889 if (md->k_mappings == 0) 1890 return; 1891 } 1892 1893 pmap_vac_me_user(md, pa, pm, va); 1894 } 1895 1896 static void 1897 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1898 { 1899 pmap_t kpmap = pmap_kernel(); 1900 struct pv_entry *pv, *npv = NULL; 1901 u_int entries = 0; 1902 u_int writable = 0; 1903 u_int cacheable_entries = 0; 1904 u_int kern_cacheable = 0; 1905 u_int other_writable = 0; 1906 1907 /* 1908 * Count mappings and writable mappings in this pmap. 1909 * Include kernel mappings as part of our own. 1910 * Keep a pointer to the first one. 1911 */ 1912 npv = NULL; 1913 KASSERT(pmap_page_locked_p(md)); 1914 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1915 /* Count mappings in the same pmap */ 1916 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1917 if (entries++ == 0) 1918 npv = pv; 1919 1920 /* Cacheable mappings */ 1921 if ((pv->pv_flags & PVF_NC) == 0) { 1922 cacheable_entries++; 1923 if (kpmap == pv->pv_pmap) 1924 kern_cacheable++; 1925 } 1926 1927 /* Writable mappings */ 1928 if (pv->pv_flags & PVF_WRITE) 1929 ++writable; 1930 } else 1931 if (pv->pv_flags & PVF_WRITE) 1932 other_writable = 1; 1933 } 1934 1935 /* 1936 * Enable or disable caching as necessary. 1937 * Note: the first entry might be part of the kernel pmap, 1938 * so we can't assume this is indicative of the state of the 1939 * other (maybe non-kpmap) entries. 1940 */ 1941 if ((entries > 1 && writable) || 1942 (entries > 0 && pm == kpmap && other_writable)) { 1943 if (cacheable_entries == 0) { 1944 return; 1945 } 1946 1947 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1948 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1949 (pv->pv_flags & PVF_NC)) 1950 continue; 1951 1952 pv->pv_flags |= PVF_NC; 1953 1954 struct l2_bucket * const l2b 1955 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1956 KASSERTMSG(l2b != NULL, "%#lx", va); 1957 pt_entry_t * const ptep 1958 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1959 const pt_entry_t opte = *ptep; 1960 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1961 1962 if ((va != pv->pv_va || pm != pv->pv_pmap) 1963 && l2pte_valid_p(npte)) { 1964 #ifdef PMAP_CACHE_VIVT 1965 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1966 true, pv->pv_flags); 1967 #endif 1968 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1969 pv->pv_flags); 1970 } 1971 1972 l2pte_set(ptep, npte, opte); 1973 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1974 } 1975 cpu_cpwait(); 1976 } else 1977 if (entries > cacheable_entries) { 1978 /* 1979 * Turn cacheing back on for some pages. If it is a kernel 1980 * page, only do so if there are no other writable pages. 1981 */ 1982 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1983 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1984 (kpmap != pv->pv_pmap || other_writable))) 1985 continue; 1986 1987 pv->pv_flags &= ~PVF_NC; 1988 1989 struct l2_bucket * const l2b 1990 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1991 KASSERTMSG(l2b != NULL, "%#lx", va); 1992 pt_entry_t * const ptep 1993 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1994 const pt_entry_t opte = *ptep; 1995 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1996 | pte_l2_s_cache_mode; 1997 1998 if (l2pte_valid_p(opte)) { 1999 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2000 pv->pv_flags); 2001 } 2002 2003 l2pte_set(ptep, npte, opte); 2004 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2005 } 2006 } 2007 } 2008 #endif 2009 2010 #ifdef PMAP_CACHE_VIPT 2011 static void 2012 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2013 { 2014 #ifndef ARM_MMU_EXTENDED 2015 struct pv_entry *pv; 2016 vaddr_t tst_mask; 2017 bool bad_alias; 2018 const u_int 2019 rw_mappings = md->urw_mappings + md->krw_mappings, 2020 ro_mappings = md->uro_mappings + md->kro_mappings; 2021 2022 /* do we need to do anything? */ 2023 if (arm_cache_prefer_mask == 0) 2024 return; 2025 2026 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2027 md, pm, va)); 2028 2029 KASSERT(!va || pm); 2030 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2031 2032 /* Already a conflict? */ 2033 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2034 /* just an add, things are already non-cached */ 2035 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2036 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2037 bad_alias = false; 2038 if (va) { 2039 PMAPCOUNT(vac_color_none); 2040 bad_alias = true; 2041 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2042 goto fixup; 2043 } 2044 pv = SLIST_FIRST(&md->pvh_list); 2045 /* the list can't be empty because it would be cachable */ 2046 if (md->pvh_attrs & PVF_KMPAGE) { 2047 tst_mask = md->pvh_attrs; 2048 } else { 2049 KASSERT(pv); 2050 tst_mask = pv->pv_va; 2051 pv = SLIST_NEXT(pv, pv_link); 2052 } 2053 /* 2054 * Only check for a bad alias if we have writable mappings. 2055 */ 2056 tst_mask &= arm_cache_prefer_mask; 2057 if (rw_mappings > 0) { 2058 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2059 /* if there's a bad alias, stop checking. */ 2060 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2061 bad_alias = true; 2062 } 2063 md->pvh_attrs |= PVF_WRITE; 2064 if (!bad_alias) 2065 md->pvh_attrs |= PVF_DIRTY; 2066 } else { 2067 /* 2068 * We have only read-only mappings. Let's see if there 2069 * are multiple colors in use or if we mapped a KMPAGE. 2070 * If the latter, we have a bad alias. If the former, 2071 * we need to remember that. 2072 */ 2073 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2074 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2075 if (md->pvh_attrs & PVF_KMPAGE) 2076 bad_alias = true; 2077 break; 2078 } 2079 } 2080 md->pvh_attrs &= ~PVF_WRITE; 2081 /* 2082 * No KMPAGE and we exited early, so we must have 2083 * multiple color mappings. 2084 */ 2085 if (!bad_alias && pv != NULL) 2086 md->pvh_attrs |= PVF_MULTCLR; 2087 } 2088 2089 /* If no conflicting colors, set everything back to cached */ 2090 if (!bad_alias) { 2091 #ifdef DEBUG 2092 if ((md->pvh_attrs & PVF_WRITE) 2093 || ro_mappings < 2) { 2094 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2095 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2096 } 2097 #endif 2098 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2099 md->pvh_attrs |= tst_mask | PVF_COLORED; 2100 /* 2101 * Restore DIRTY bit if page is modified 2102 */ 2103 if (md->pvh_attrs & PVF_DMOD) 2104 md->pvh_attrs |= PVF_DIRTY; 2105 PMAPCOUNT(vac_color_restore); 2106 } else { 2107 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2108 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2109 } 2110 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2111 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2112 } else if (!va) { 2113 KASSERT(pmap_is_page_colored_p(md)); 2114 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2115 || (md->pvh_attrs & PVF_DIRTY)); 2116 if (rw_mappings == 0) { 2117 md->pvh_attrs &= ~PVF_WRITE; 2118 if (ro_mappings == 1 2119 && (md->pvh_attrs & PVF_MULTCLR)) { 2120 /* 2121 * If this is the last readonly mapping 2122 * but it doesn't match the current color 2123 * for the page, change the current color 2124 * to match this last readonly mapping. 2125 */ 2126 pv = SLIST_FIRST(&md->pvh_list); 2127 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2128 & arm_cache_prefer_mask; 2129 if (tst_mask) { 2130 md->pvh_attrs ^= tst_mask; 2131 PMAPCOUNT(vac_color_change); 2132 } 2133 } 2134 } 2135 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2136 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2137 return; 2138 } else if (!pmap_is_page_colored_p(md)) { 2139 /* not colored so we just use its color */ 2140 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2141 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2142 PMAPCOUNT(vac_color_new); 2143 md->pvh_attrs &= PAGE_SIZE - 1; 2144 md->pvh_attrs |= PVF_COLORED 2145 | (va & arm_cache_prefer_mask) 2146 | (rw_mappings > 0 ? PVF_WRITE : 0); 2147 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2148 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2149 return; 2150 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2151 bad_alias = false; 2152 if (rw_mappings > 0) { 2153 /* 2154 * We now have writeable mappings and if we have 2155 * readonly mappings in more than once color, we have 2156 * an aliasing problem. Regardless mark the page as 2157 * writeable. 2158 */ 2159 if (md->pvh_attrs & PVF_MULTCLR) { 2160 if (ro_mappings < 2) { 2161 /* 2162 * If we only have less than two 2163 * read-only mappings, just flush the 2164 * non-primary colors from the cache. 2165 */ 2166 pmap_flush_page(md, pa, 2167 PMAP_FLUSH_SECONDARY); 2168 } else { 2169 bad_alias = true; 2170 } 2171 } 2172 md->pvh_attrs |= PVF_WRITE; 2173 } 2174 /* If no conflicting colors, set everything back to cached */ 2175 if (!bad_alias) { 2176 #ifdef DEBUG 2177 if (rw_mappings > 0 2178 || (md->pvh_attrs & PMAP_KMPAGE)) { 2179 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2180 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2181 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2182 } 2183 #endif 2184 if (SLIST_EMPTY(&md->pvh_list)) 2185 PMAPCOUNT(vac_color_reuse); 2186 else 2187 PMAPCOUNT(vac_color_ok); 2188 2189 /* matching color, just return */ 2190 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2191 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2192 return; 2193 } 2194 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2195 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2196 2197 /* color conflict. evict from cache. */ 2198 2199 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2200 md->pvh_attrs &= ~PVF_COLORED; 2201 md->pvh_attrs |= PVF_NC; 2202 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2203 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2204 PMAPCOUNT(vac_color_erase); 2205 } else if (rw_mappings == 0 2206 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2207 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2208 2209 /* 2210 * If the page has dirty cache lines, clean it. 2211 */ 2212 if (md->pvh_attrs & PVF_DIRTY) 2213 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2214 2215 /* 2216 * If this is the first remapping (we know that there are no 2217 * writeable mappings), then this is a simple color change. 2218 * Otherwise this is a seconary r/o mapping, which means 2219 * we don't have to do anything. 2220 */ 2221 if (ro_mappings == 1) { 2222 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2223 md->pvh_attrs &= PAGE_SIZE - 1; 2224 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2225 PMAPCOUNT(vac_color_change); 2226 } else { 2227 PMAPCOUNT(vac_color_blind); 2228 } 2229 md->pvh_attrs |= PVF_MULTCLR; 2230 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2231 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2232 return; 2233 } else { 2234 if (rw_mappings > 0) 2235 md->pvh_attrs |= PVF_WRITE; 2236 2237 /* color conflict. evict from cache. */ 2238 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2239 2240 /* the list can't be empty because this was a enter/modify */ 2241 pv = SLIST_FIRST(&md->pvh_list); 2242 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2243 KASSERT(pv); 2244 /* 2245 * If there's only one mapped page, change color to the 2246 * page's new color and return. Restore the DIRTY bit 2247 * that was erased by pmap_flush_page. 2248 */ 2249 if (SLIST_NEXT(pv, pv_link) == NULL) { 2250 md->pvh_attrs &= PAGE_SIZE - 1; 2251 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2252 if (md->pvh_attrs & PVF_DMOD) 2253 md->pvh_attrs |= PVF_DIRTY; 2254 PMAPCOUNT(vac_color_change); 2255 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2256 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2257 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2258 return; 2259 } 2260 } 2261 bad_alias = true; 2262 md->pvh_attrs &= ~PVF_COLORED; 2263 md->pvh_attrs |= PVF_NC; 2264 PMAPCOUNT(vac_color_erase); 2265 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2266 } 2267 2268 fixup: 2269 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2270 2271 /* 2272 * Turn cacheing on/off for all pages. 2273 */ 2274 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2275 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2276 pv->pv_va); 2277 KASSERTMSG(l2b != NULL, "%#lx", va); 2278 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2279 const pt_entry_t opte = *ptep; 2280 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2281 if (bad_alias) { 2282 pv->pv_flags |= PVF_NC; 2283 } else { 2284 pv->pv_flags &= ~PVF_NC; 2285 npte |= pte_l2_s_cache_mode; 2286 } 2287 2288 if (opte == npte) /* only update is there's a change */ 2289 continue; 2290 2291 if (l2pte_valid_p(npte)) { 2292 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2293 } 2294 2295 l2pte_set(ptep, npte, opte); 2296 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2297 } 2298 #endif /* !ARM_MMU_EXTENDED */ 2299 } 2300 #endif /* PMAP_CACHE_VIPT */ 2301 2302 2303 /* 2304 * Modify pte bits for all ptes corresponding to the given physical address. 2305 * We use `maskbits' rather than `clearbits' because we're always passing 2306 * constants and the latter would require an extra inversion at run-time. 2307 */ 2308 static void 2309 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2310 { 2311 struct pv_entry *pv; 2312 #ifdef PMAP_CACHE_VIPT 2313 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2314 #ifdef ARM_MMU_EXTENDED 2315 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2316 #else 2317 const u_int execbits = 0; 2318 bool need_vac_me_harder = false; 2319 bool need_syncicache = false; 2320 #endif 2321 #else 2322 const u_int execbits = 0; 2323 #endif 2324 2325 NPDEBUG(PDB_BITS, 2326 printf("pmap_clearbit: md %p mask 0x%x\n", 2327 md, maskbits)); 2328 2329 #ifdef PMAP_CACHE_VIPT 2330 /* 2331 * If we might want to sync the I-cache and we've modified it, 2332 * then we know we definitely need to sync or discard it. 2333 */ 2334 if (want_syncicache) { 2335 #ifdef ARM_MMU_EXTENDED 2336 if (md->pvh_attrs & PVF_MOD) 2337 md->pvh_attrs &= ~PVF_EXEC; 2338 #else 2339 need_syncicache = md->pvh_attrs & PVF_MOD; 2340 #endif 2341 } 2342 #endif 2343 KASSERT(pmap_page_locked_p(md)); 2344 2345 /* 2346 * Clear saved attributes (modify, reference) 2347 */ 2348 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2349 2350 if (SLIST_EMPTY(&md->pvh_list)) { 2351 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2352 if (need_syncicache) { 2353 /* 2354 * No one has it mapped, so just discard it. The next 2355 * exec remapping will cause it to be synced. 2356 */ 2357 md->pvh_attrs &= ~PVF_EXEC; 2358 PMAPCOUNT(exec_discarded_clearbit); 2359 } 2360 #endif 2361 return; 2362 } 2363 2364 /* 2365 * Loop over all current mappings setting/clearing as appropos 2366 */ 2367 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2368 pmap_t pm = pv->pv_pmap; 2369 const vaddr_t va = pv->pv_va; 2370 const u_int oflags = pv->pv_flags; 2371 #ifndef ARM_MMU_EXTENDED 2372 /* 2373 * Kernel entries are unmanaged and as such not to be changed. 2374 */ 2375 if (PV_IS_KENTRY_P(oflags)) 2376 continue; 2377 #endif 2378 pv->pv_flags &= ~maskbits; 2379 2380 pmap_release_page_lock(md); 2381 pmap_acquire_pmap_lock(pm); 2382 2383 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2384 if (l2b == NULL) { 2385 pmap_release_pmap_lock(pm); 2386 pmap_acquire_page_lock(md); 2387 continue; 2388 } 2389 KASSERTMSG(l2b != NULL, "%#lx", va); 2390 2391 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2392 const pt_entry_t opte = *ptep; 2393 pt_entry_t npte = opte | execbits; 2394 2395 #ifdef ARM_MMU_EXTENDED 2396 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2397 #endif 2398 2399 NPDEBUG(PDB_BITS, 2400 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2401 __func__, pv, pm, va, oflags)); 2402 2403 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2404 #ifdef PMAP_CACHE_VIVT 2405 if ((oflags & PVF_NC)) { 2406 /* 2407 * Entry is not cacheable: 2408 * 2409 * Don't turn caching on again if this is a 2410 * modified emulation. This would be 2411 * inconsitent with the settings created by 2412 * pmap_vac_me_harder(). Otherwise, it's safe 2413 * to re-enable cacheing. 2414 * 2415 * There's no need to call pmap_vac_me_harder() 2416 * here: all pages are losing their write 2417 * permission. 2418 */ 2419 if (maskbits & PVF_WRITE) { 2420 npte |= pte_l2_s_cache_mode; 2421 pv->pv_flags &= ~PVF_NC; 2422 } 2423 } else 2424 if (l2pte_writable_p(opte)) { 2425 /* 2426 * Entry is writable/cacheable: check if pmap 2427 * is current if it is flush it, otherwise it 2428 * won't be in the cache 2429 */ 2430 pmap_cache_wbinv_page(pm, va, 2431 (maskbits & PVF_REF) != 0, 2432 oflags|PVF_WRITE); 2433 } 2434 #endif 2435 2436 /* make the pte read only */ 2437 npte = l2pte_set_readonly(npte); 2438 2439 pmap_acquire_page_lock(md); 2440 #ifdef MULTIPROCESSOR 2441 pv = pmap_find_pv(md, pm, va); 2442 #endif 2443 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2444 /* 2445 * Keep alias accounting up to date 2446 */ 2447 if (pm == pmap_kernel()) { 2448 md->krw_mappings--; 2449 md->kro_mappings++; 2450 } else { 2451 md->urw_mappings--; 2452 md->uro_mappings++; 2453 } 2454 #ifdef PMAP_CACHE_VIPT 2455 if (arm_cache_prefer_mask != 0) { 2456 if (md->urw_mappings + md->krw_mappings == 0) { 2457 md->pvh_attrs &= ~PVF_WRITE; 2458 } else { 2459 PMAP_VALIDATE_MD_PAGE(md); 2460 } 2461 } 2462 #ifndef ARM_MMU_EXTENDED 2463 if (want_syncicache) 2464 need_syncicache = true; 2465 need_vac_me_harder = true; 2466 #endif 2467 #endif /* PMAP_CACHE_VIPT */ 2468 } 2469 pmap_release_page_lock(md); 2470 } 2471 2472 if (maskbits & PVF_REF) { 2473 if (true 2474 #ifndef ARM_MMU_EXTENDED 2475 && (oflags & PVF_NC) == 0 2476 #endif 2477 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2478 && l2pte_valid_p(npte)) { 2479 #ifdef PMAP_CACHE_VIVT 2480 /* 2481 * Check npte here; we may have already 2482 * done the wbinv above, and the validity 2483 * of the PTE is the same for opte and 2484 * npte. 2485 */ 2486 pmap_cache_wbinv_page(pm, va, true, oflags); 2487 #endif 2488 } 2489 2490 /* 2491 * Make the PTE invalid so that we will take a 2492 * page fault the next time the mapping is 2493 * referenced. 2494 */ 2495 npte &= ~L2_TYPE_MASK; 2496 npte |= L2_TYPE_INV; 2497 } 2498 2499 if (npte != opte) { 2500 l2pte_set(ptep, npte, opte); 2501 PTE_SYNC(ptep); 2502 2503 /* Flush the TLB entry if a current pmap. */ 2504 pmap_tlb_flush_SE(pm, va, oflags); 2505 } 2506 2507 pmap_release_pmap_lock(pm); 2508 pmap_acquire_page_lock(md); 2509 2510 NPDEBUG(PDB_BITS, 2511 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2512 pm, va, opte, npte)); 2513 } 2514 2515 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2516 /* 2517 * If we need to sync the I-cache and we haven't done it yet, do it. 2518 */ 2519 if (need_syncicache) { 2520 pmap_release_page_lock(md); 2521 pmap_syncicache_page(md, pa); 2522 pmap_acquire_page_lock(md); 2523 PMAPCOUNT(exec_synced_clearbit); 2524 } 2525 2526 /* 2527 * If we are changing this to read-only, we need to call vac_me_harder 2528 * so we can change all the read-only pages to cacheable. We pretend 2529 * this as a page deletion. 2530 */ 2531 if (need_vac_me_harder) { 2532 if (md->pvh_attrs & PVF_NC) 2533 pmap_vac_me_harder(md, pa, NULL, 0); 2534 } 2535 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2536 } 2537 2538 /* 2539 * pmap_clean_page() 2540 * 2541 * This is a local function used to work out the best strategy to clean 2542 * a single page referenced by its entry in the PV table. It's used by 2543 * pmap_copy_page, pmap_zero page and maybe some others later on. 2544 * 2545 * Its policy is effectively: 2546 * o If there are no mappings, we don't bother doing anything with the cache. 2547 * o If there is one mapping, we clean just that page. 2548 * o If there are multiple mappings, we clean the entire cache. 2549 * 2550 * So that some functions can be further optimised, it returns 0 if it didn't 2551 * clean the entire cache, or 1 if it did. 2552 * 2553 * XXX One bug in this routine is that if the pv_entry has a single page 2554 * mapped at 0x00000000 a whole cache clean will be performed rather than 2555 * just the 1 page. Since this should not occur in everyday use and if it does 2556 * it will just result in not the most efficient clean for the page. 2557 */ 2558 #ifdef PMAP_CACHE_VIVT 2559 static bool 2560 pmap_clean_page(struct vm_page_md *md, bool is_src) 2561 { 2562 struct pv_entry *pv; 2563 pmap_t pm_to_clean = NULL; 2564 bool cache_needs_cleaning = false; 2565 vaddr_t page_to_clean = 0; 2566 u_int flags = 0; 2567 2568 /* 2569 * Since we flush the cache each time we change to a different 2570 * user vmspace, we only need to flush the page if it is in the 2571 * current pmap. 2572 */ 2573 KASSERT(pmap_page_locked_p(md)); 2574 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2575 if (pmap_is_current(pv->pv_pmap)) { 2576 flags |= pv->pv_flags; 2577 /* 2578 * The page is mapped non-cacheable in 2579 * this map. No need to flush the cache. 2580 */ 2581 if (pv->pv_flags & PVF_NC) { 2582 #ifdef DIAGNOSTIC 2583 KASSERT(!cache_needs_cleaning); 2584 #endif 2585 break; 2586 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2587 continue; 2588 if (cache_needs_cleaning) { 2589 page_to_clean = 0; 2590 break; 2591 } else { 2592 page_to_clean = pv->pv_va; 2593 pm_to_clean = pv->pv_pmap; 2594 } 2595 cache_needs_cleaning = true; 2596 } 2597 } 2598 2599 if (page_to_clean) { 2600 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2601 !is_src, flags | PVF_REF); 2602 } else if (cache_needs_cleaning) { 2603 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2604 2605 pmap_cache_wbinv_all(pm, flags); 2606 return true; 2607 } 2608 return false; 2609 } 2610 #endif 2611 2612 #ifdef PMAP_CACHE_VIPT 2613 /* 2614 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2615 * right cache alias to make sure we flush the right stuff. 2616 */ 2617 void 2618 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2619 { 2620 pmap_t kpm = pmap_kernel(); 2621 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2622 ? PAGE_SIZE 2623 : arm_pcache.icache_way_size; 2624 2625 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2626 md, md->pvh_attrs)); 2627 /* 2628 * No need to clean the page if it's non-cached. 2629 */ 2630 #ifndef ARM_MMU_EXTENDED 2631 if (md->pvh_attrs & PVF_NC) 2632 return; 2633 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2634 #endif 2635 2636 pt_entry_t * const ptep = cpu_cdst_pte(0); 2637 const vaddr_t dstp = cpu_cdstp(0); 2638 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2639 if (way_size <= PAGE_SIZE) { 2640 bool ok = false; 2641 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2642 if (ok) { 2643 cpu_icache_sync_range(vdstp, way_size); 2644 return; 2645 } 2646 } 2647 #endif 2648 2649 /* 2650 * We don't worry about the color of the exec page, we map the 2651 * same page to pages in the way and then do the icache_sync on 2652 * the entire way making sure we are cleaned. 2653 */ 2654 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2655 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2656 2657 for (size_t i = 0, j = 0; i < way_size; 2658 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2659 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2660 /* 2661 * Set up a PTE with to flush these cache lines. 2662 */ 2663 l2pte_set(ptep + j, npte, 0); 2664 } 2665 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2666 2667 /* 2668 * Flush it. 2669 */ 2670 cpu_icache_sync_range(dstp, way_size); 2671 2672 for (size_t i = 0, j = 0; i < way_size; 2673 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2674 /* 2675 * Unmap the page(s). 2676 */ 2677 l2pte_reset(ptep + j); 2678 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2679 } 2680 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2681 2682 md->pvh_attrs |= PVF_EXEC; 2683 PMAPCOUNT(exec_synced); 2684 } 2685 2686 #ifndef ARM_MMU_EXTENDED 2687 void 2688 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2689 { 2690 vsize_t va_offset, end_va; 2691 bool wbinv_p; 2692 2693 if (arm_cache_prefer_mask == 0) 2694 return; 2695 2696 switch (flush) { 2697 case PMAP_FLUSH_PRIMARY: 2698 if (md->pvh_attrs & PVF_MULTCLR) { 2699 va_offset = 0; 2700 end_va = arm_cache_prefer_mask; 2701 md->pvh_attrs &= ~PVF_MULTCLR; 2702 PMAPCOUNT(vac_flush_lots); 2703 } else { 2704 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2705 end_va = va_offset; 2706 PMAPCOUNT(vac_flush_one); 2707 } 2708 /* 2709 * Mark that the page is no longer dirty. 2710 */ 2711 md->pvh_attrs &= ~PVF_DIRTY; 2712 wbinv_p = true; 2713 break; 2714 case PMAP_FLUSH_SECONDARY: 2715 va_offset = 0; 2716 end_va = arm_cache_prefer_mask; 2717 wbinv_p = true; 2718 md->pvh_attrs &= ~PVF_MULTCLR; 2719 PMAPCOUNT(vac_flush_lots); 2720 break; 2721 case PMAP_CLEAN_PRIMARY: 2722 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2723 end_va = va_offset; 2724 wbinv_p = false; 2725 /* 2726 * Mark that the page is no longer dirty. 2727 */ 2728 if ((md->pvh_attrs & PVF_DMOD) == 0) 2729 md->pvh_attrs &= ~PVF_DIRTY; 2730 PMAPCOUNT(vac_clean_one); 2731 break; 2732 default: 2733 return; 2734 } 2735 2736 KASSERT(!(md->pvh_attrs & PVF_NC)); 2737 2738 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2739 md, md->pvh_attrs)); 2740 2741 const size_t scache_line_size = arm_scache.dcache_line_size; 2742 2743 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2744 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2745 const vaddr_t dstp = cpu_cdstp(va_offset); 2746 const pt_entry_t opte = *ptep; 2747 2748 if (flush == PMAP_FLUSH_SECONDARY 2749 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2750 continue; 2751 2752 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2753 /* 2754 * Set up a PTE with the right coloring to flush 2755 * existing cache entries. 2756 */ 2757 const pt_entry_t npte = L2_S_PROTO 2758 | pa 2759 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2760 | pte_l2_s_cache_mode; 2761 l2pte_set(ptep, npte, opte); 2762 PTE_SYNC(ptep); 2763 2764 /* 2765 * Flush it. Make sure to flush secondary cache too since 2766 * bus_dma will ignore uncached pages. 2767 */ 2768 if (scache_line_size != 0) { 2769 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2770 if (wbinv_p) { 2771 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2772 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2773 } else { 2774 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2775 } 2776 } else { 2777 if (wbinv_p) { 2778 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2779 } else { 2780 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2781 } 2782 } 2783 2784 /* 2785 * Restore the page table entry since we might have interrupted 2786 * pmap_zero_page or pmap_copy_page which was already using 2787 * this pte. 2788 */ 2789 if (opte) { 2790 l2pte_set(ptep, opte, npte); 2791 } else { 2792 l2pte_reset(ptep); 2793 } 2794 PTE_SYNC(ptep); 2795 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2796 } 2797 } 2798 #endif /* ARM_MMU_EXTENDED */ 2799 #endif /* PMAP_CACHE_VIPT */ 2800 2801 /* 2802 * Routine: pmap_page_remove 2803 * Function: 2804 * Removes this physical page from 2805 * all physical maps in which it resides. 2806 * Reflects back modify bits to the pager. 2807 */ 2808 static void 2809 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2810 { 2811 struct l2_bucket *l2b; 2812 struct pv_entry *pv; 2813 pt_entry_t *ptep; 2814 #ifndef ARM_MMU_EXTENDED 2815 bool flush = false; 2816 #endif 2817 u_int flags = 0; 2818 2819 NPDEBUG(PDB_FOLLOW, 2820 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2821 pa)); 2822 2823 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2824 pmap_acquire_page_lock(md); 2825 if (*pvp == NULL) { 2826 #ifdef PMAP_CACHE_VIPT 2827 /* 2828 * We *know* the page contents are about to be replaced. 2829 * Discard the exec contents 2830 */ 2831 if (PV_IS_EXEC_P(md->pvh_attrs)) 2832 PMAPCOUNT(exec_discarded_page_protect); 2833 md->pvh_attrs &= ~PVF_EXEC; 2834 PMAP_VALIDATE_MD_PAGE(md); 2835 #endif 2836 pmap_release_page_lock(md); 2837 return; 2838 } 2839 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2840 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2841 #endif 2842 2843 /* 2844 * Clear alias counts 2845 */ 2846 #ifdef PMAP_CACHE_VIVT 2847 md->k_mappings = 0; 2848 #endif 2849 md->urw_mappings = md->uro_mappings = 0; 2850 2851 #ifdef PMAP_CACHE_VIVT 2852 pmap_clean_page(md, false); 2853 #endif 2854 2855 while ((pv = *pvp) != NULL) { 2856 pmap_t pm = pv->pv_pmap; 2857 #ifndef ARM_MMU_EXTENDED 2858 if (flush == false && pmap_is_current(pm)) 2859 flush = true; 2860 #endif 2861 2862 if (pm == pmap_kernel()) { 2863 #ifdef PMAP_CACHE_VIPT 2864 /* 2865 * If this was unmanaged mapping, it must be preserved. 2866 * Move it back on the list and advance the end-of-list 2867 * pointer. 2868 */ 2869 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2870 *pvp = pv; 2871 pvp = &SLIST_NEXT(pv, pv_link); 2872 continue; 2873 } 2874 if (pv->pv_flags & PVF_WRITE) 2875 md->krw_mappings--; 2876 else 2877 md->kro_mappings--; 2878 #endif 2879 PMAPCOUNT(kernel_unmappings); 2880 } 2881 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2882 PMAPCOUNT(unmappings); 2883 2884 pmap_release_page_lock(md); 2885 pmap_acquire_pmap_lock(pm); 2886 2887 #ifdef ARM_MMU_EXTENDED 2888 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2889 #endif 2890 2891 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2892 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2893 2894 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2895 2896 /* 2897 * Update statistics 2898 */ 2899 --pm->pm_stats.resident_count; 2900 2901 /* Wired bit */ 2902 if (pv->pv_flags & PVF_WIRED) 2903 --pm->pm_stats.wired_count; 2904 2905 flags |= pv->pv_flags; 2906 2907 /* 2908 * Invalidate the PTEs. 2909 */ 2910 l2pte_reset(ptep); 2911 PTE_SYNC_CURRENT(pm, ptep); 2912 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2913 pmap_release_pmap_lock(pm); 2914 2915 pool_put(&pmap_pv_pool, pv); 2916 pmap_acquire_page_lock(md); 2917 #ifdef MULTIPROCESSOR 2918 /* 2919 * Restart of the beginning of the list. 2920 */ 2921 pvp = &SLIST_FIRST(&md->pvh_list); 2922 #endif 2923 } 2924 /* 2925 * if we reach the end of the list and there are still mappings, they 2926 * might be able to be cached now. And they must be kernel mappings. 2927 */ 2928 if (!SLIST_EMPTY(&md->pvh_list)) { 2929 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2930 } 2931 2932 #ifdef PMAP_CACHE_VIPT 2933 /* 2934 * Its EXEC cache is now gone. 2935 */ 2936 if (PV_IS_EXEC_P(md->pvh_attrs)) 2937 PMAPCOUNT(exec_discarded_page_protect); 2938 md->pvh_attrs &= ~PVF_EXEC; 2939 KASSERT(md->urw_mappings == 0); 2940 KASSERT(md->uro_mappings == 0); 2941 #ifndef ARM_MMU_EXTENDED 2942 if (arm_cache_prefer_mask != 0) { 2943 if (md->krw_mappings == 0) 2944 md->pvh_attrs &= ~PVF_WRITE; 2945 PMAP_VALIDATE_MD_PAGE(md); 2946 } 2947 #endif /* ARM_MMU_EXTENDED */ 2948 #endif /* PMAP_CACHE_VIPT */ 2949 pmap_release_page_lock(md); 2950 2951 #ifndef ARM_MMU_EXTENDED 2952 if (flush) { 2953 /* 2954 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2955 * would need a subsequent call to pmap_update() to ensure 2956 * curpm->pm_cstate.cs_all is reset. Our callers are not 2957 * required to do that (see pmap(9)), so we can't modify 2958 * the current pmap's state. 2959 */ 2960 if (PV_BEEN_EXECD(flags)) 2961 cpu_tlb_flushID(); 2962 else 2963 cpu_tlb_flushD(); 2964 } 2965 cpu_cpwait(); 2966 #endif /* ARM_MMU_EXTENDED */ 2967 } 2968 2969 /* 2970 * pmap_t pmap_create(void) 2971 * 2972 * Create a new pmap structure from scratch. 2973 */ 2974 pmap_t 2975 pmap_create(void) 2976 { 2977 pmap_t pm; 2978 2979 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2980 2981 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2982 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2983 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2984 2985 pm->pm_stats.wired_count = 0; 2986 pm->pm_stats.resident_count = 1; 2987 #ifdef ARM_MMU_EXTENDED 2988 #ifdef MULTIPROCESSOR 2989 kcpuset_create(&pm->pm_active, true); 2990 kcpuset_create(&pm->pm_onproc, true); 2991 #endif 2992 #else 2993 pm->pm_cstate.cs_all = 0; 2994 #endif 2995 pmap_alloc_l1(pm); 2996 2997 /* 2998 * Note: The pool cache ensures that the pm_l2[] array is already 2999 * initialised to zero. 3000 */ 3001 3002 pmap_pinit(pm); 3003 3004 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3005 3006 return (pm); 3007 } 3008 3009 u_int 3010 arm32_mmap_flags(paddr_t pa) 3011 { 3012 /* 3013 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3014 * and we're using the upper bits in page numbers to pass flags around 3015 * so we might as well use the same bits 3016 */ 3017 return (u_int)pa & PMAP_MD_MASK; 3018 } 3019 /* 3020 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3021 * u_int flags) 3022 * 3023 * Insert the given physical page (p) at 3024 * the specified virtual address (v) in the 3025 * target physical map with the protection requested. 3026 * 3027 * NB: This is the only routine which MAY NOT lazy-evaluate 3028 * or lose information. That is, this routine must actually 3029 * insert this page into the given map NOW. 3030 */ 3031 int 3032 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3033 { 3034 struct l2_bucket *l2b; 3035 struct vm_page *pg, *opg; 3036 u_int nflags; 3037 u_int oflags; 3038 const bool kpm_p = (pm == pmap_kernel()); 3039 #ifdef ARM_HAS_VBAR 3040 const bool vector_page_p = false; 3041 #else 3042 const bool vector_page_p = (va == vector_page); 3043 #endif 3044 3045 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3046 3047 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3048 pm, va, pa, prot); 3049 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3050 3051 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3052 KDASSERT(((va | pa) & PGOFSET) == 0); 3053 3054 /* 3055 * Get a pointer to the page. Later on in this function, we 3056 * test for a managed page by checking pg != NULL. 3057 */ 3058 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3059 3060 nflags = 0; 3061 if (prot & VM_PROT_WRITE) 3062 nflags |= PVF_WRITE; 3063 if (prot & VM_PROT_EXECUTE) 3064 nflags |= PVF_EXEC; 3065 if (flags & PMAP_WIRED) 3066 nflags |= PVF_WIRED; 3067 3068 pmap_acquire_pmap_lock(pm); 3069 3070 /* 3071 * Fetch the L2 bucket which maps this page, allocating one if 3072 * necessary for user pmaps. 3073 */ 3074 if (kpm_p) { 3075 l2b = pmap_get_l2_bucket(pm, va); 3076 } else { 3077 l2b = pmap_alloc_l2_bucket(pm, va); 3078 } 3079 if (l2b == NULL) { 3080 if (flags & PMAP_CANFAIL) { 3081 pmap_release_pmap_lock(pm); 3082 return (ENOMEM); 3083 } 3084 panic("pmap_enter: failed to allocate L2 bucket"); 3085 } 3086 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3087 const pt_entry_t opte = *ptep; 3088 pt_entry_t npte = pa; 3089 oflags = 0; 3090 3091 if (opte) { 3092 /* 3093 * There is already a mapping at this address. 3094 * If the physical address is different, lookup the 3095 * vm_page. 3096 */ 3097 if (l2pte_pa(opte) != pa) 3098 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3099 else 3100 opg = pg; 3101 } else 3102 opg = NULL; 3103 3104 if (pg) { 3105 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3106 3107 /* 3108 * This is to be a managed mapping. 3109 */ 3110 pmap_acquire_page_lock(md); 3111 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3112 /* 3113 * - The access type indicates that we don't need 3114 * to do referenced emulation. 3115 * OR 3116 * - The physical page has already been referenced 3117 * so no need to re-do referenced emulation here. 3118 */ 3119 npte |= l2pte_set_readonly(L2_S_PROTO); 3120 3121 nflags |= PVF_REF; 3122 3123 if ((prot & VM_PROT_WRITE) != 0 && 3124 ((flags & VM_PROT_WRITE) != 0 || 3125 (md->pvh_attrs & PVF_MOD) != 0)) { 3126 /* 3127 * This is a writable mapping, and the 3128 * page's mod state indicates it has 3129 * already been modified. Make it 3130 * writable from the outset. 3131 */ 3132 npte = l2pte_set_writable(npte); 3133 nflags |= PVF_MOD; 3134 } 3135 3136 #ifdef ARM_MMU_EXTENDED 3137 /* 3138 * If the page has been cleaned, then the pvh_attrs 3139 * will have PVF_EXEC set, so mark it execute so we 3140 * don't get an access fault when trying to execute 3141 * from it. 3142 */ 3143 if (md->pvh_attrs & nflags & PVF_EXEC) { 3144 npte &= ~L2_XS_XN; 3145 } 3146 #endif 3147 } else { 3148 /* 3149 * Need to do page referenced emulation. 3150 */ 3151 npte |= L2_TYPE_INV; 3152 } 3153 3154 if (flags & ARM32_MMAP_WRITECOMBINE) { 3155 npte |= pte_l2_s_wc_mode; 3156 } else 3157 npte |= pte_l2_s_cache_mode; 3158 3159 if (pg == opg) { 3160 /* 3161 * We're changing the attrs of an existing mapping. 3162 */ 3163 oflags = pmap_modify_pv(md, pa, pm, va, 3164 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3165 PVF_MOD | PVF_REF, nflags); 3166 3167 #ifdef PMAP_CACHE_VIVT 3168 /* 3169 * We may need to flush the cache if we're 3170 * doing rw-ro... 3171 */ 3172 if (pm->pm_cstate.cs_cache_d && 3173 (oflags & PVF_NC) == 0 && 3174 l2pte_writable_p(opte) && 3175 (prot & VM_PROT_WRITE) == 0) 3176 cpu_dcache_wb_range(va, PAGE_SIZE); 3177 #endif 3178 } else { 3179 struct pv_entry *pv; 3180 /* 3181 * New mapping, or changing the backing page 3182 * of an existing mapping. 3183 */ 3184 if (opg) { 3185 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3186 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3187 3188 /* 3189 * Replacing an existing mapping with a new one. 3190 * It is part of our managed memory so we 3191 * must remove it from the PV list 3192 */ 3193 pv = pmap_remove_pv(omd, opa, pm, va); 3194 pmap_vac_me_harder(omd, opa, pm, 0); 3195 oflags = pv->pv_flags; 3196 3197 #ifdef PMAP_CACHE_VIVT 3198 /* 3199 * If the old mapping was valid (ref/mod 3200 * emulation creates 'invalid' mappings 3201 * initially) then make sure to frob 3202 * the cache. 3203 */ 3204 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3205 pmap_cache_wbinv_page(pm, va, true, 3206 oflags); 3207 } 3208 #endif 3209 } else { 3210 pmap_release_page_lock(md); 3211 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3212 if (pv == NULL) { 3213 pmap_release_pmap_lock(pm); 3214 if ((flags & PMAP_CANFAIL) == 0) 3215 panic("pmap_enter: " 3216 "no pv entries"); 3217 3218 pmap_free_l2_bucket(pm, l2b, 0); 3219 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3220 0, 0, 0, 0); 3221 return (ENOMEM); 3222 } 3223 pmap_acquire_page_lock(md); 3224 } 3225 3226 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3227 } 3228 pmap_release_page_lock(md); 3229 } else { 3230 /* 3231 * We're mapping an unmanaged page. 3232 * These are always readable, and possibly writable, from 3233 * the get go as we don't need to track ref/mod status. 3234 */ 3235 npte |= l2pte_set_readonly(L2_S_PROTO); 3236 if (prot & VM_PROT_WRITE) 3237 npte = l2pte_set_writable(npte); 3238 3239 /* 3240 * Make sure the vector table is mapped cacheable 3241 */ 3242 if ((vector_page_p && !kpm_p) 3243 || (flags & ARM32_MMAP_CACHEABLE)) { 3244 npte |= pte_l2_s_cache_mode; 3245 #ifdef ARM_MMU_EXTENDED 3246 npte &= ~L2_XS_XN; /* and executable */ 3247 #endif 3248 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3249 npte |= pte_l2_s_wc_mode; 3250 } 3251 if (opg) { 3252 /* 3253 * Looks like there's an existing 'managed' mapping 3254 * at this address. 3255 */ 3256 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3257 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3258 3259 pmap_acquire_page_lock(omd); 3260 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3261 pmap_vac_me_harder(omd, opa, pm, 0); 3262 oflags = pv->pv_flags; 3263 pmap_release_page_lock(omd); 3264 3265 #ifdef PMAP_CACHE_VIVT 3266 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3267 pmap_cache_wbinv_page(pm, va, true, oflags); 3268 } 3269 #endif 3270 pool_put(&pmap_pv_pool, pv); 3271 } 3272 } 3273 3274 /* 3275 * Make sure userland mappings get the right permissions 3276 */ 3277 if (!vector_page_p && !kpm_p) { 3278 npte |= L2_S_PROT_U; 3279 #ifdef ARM_MMU_EXTENDED 3280 npte |= L2_XS_nG; /* user pages are not global */ 3281 #endif 3282 } 3283 3284 /* 3285 * Keep the stats up to date 3286 */ 3287 if (opte == 0) { 3288 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3289 pm->pm_stats.resident_count++; 3290 } 3291 3292 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3293 3294 #if defined(ARM_MMU_EXTENDED) 3295 /* 3296 * If exec protection was requested but the page hasn't been synced, 3297 * sync it now and allow execution from it. 3298 */ 3299 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3300 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3301 npte &= ~L2_XS_XN; 3302 pmap_syncicache_page(md, pa); 3303 PMAPCOUNT(exec_synced_map); 3304 } 3305 #endif 3306 /* 3307 * If this is just a wiring change, the two PTEs will be 3308 * identical, so there's no need to update the page table. 3309 */ 3310 if (npte != opte) { 3311 3312 l2pte_set(ptep, npte, opte); 3313 PTE_SYNC(ptep); 3314 #ifndef ARM_MMU_EXTENDED 3315 bool is_cached = pmap_is_cached(pm); 3316 if (is_cached) { 3317 /* 3318 * We only need to frob the cache/tlb if this pmap 3319 * is current 3320 */ 3321 if (!vector_page_p && l2pte_valid_p(npte)) { 3322 /* 3323 * This mapping is likely to be accessed as 3324 * soon as we return to userland. Fix up the 3325 * L1 entry to avoid taking another 3326 * page/domain fault. 3327 */ 3328 pd_entry_t *pdep = pmap_l1_kva(pm) 3329 + l1pte_index(va); 3330 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3331 | L1_C_DOM(pmap_domain(pm)); 3332 if (*pdep != pde) { 3333 l1pte_setone(pdep, pde); 3334 PTE_SYNC(pdep); 3335 } 3336 } 3337 } 3338 #endif /* !ARM_MMU_EXTENDED */ 3339 3340 pmap_tlb_flush_SE(pm, va, oflags); 3341 3342 #ifndef ARM_MMU_EXTENDED 3343 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3344 is_cached, pm->pm_cstate.cs_all, 0, 0); 3345 3346 if (pg != NULL) { 3347 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3348 3349 pmap_acquire_page_lock(md); 3350 pmap_vac_me_harder(md, pa, pm, va); 3351 pmap_release_page_lock(md); 3352 } 3353 #endif 3354 } 3355 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3356 if (pg) { 3357 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3358 3359 pmap_acquire_page_lock(md); 3360 #ifndef ARM_MMU_EXTENDED 3361 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3362 #endif 3363 PMAP_VALIDATE_MD_PAGE(md); 3364 pmap_release_page_lock(md); 3365 } 3366 #endif 3367 3368 pmap_release_pmap_lock(pm); 3369 3370 return (0); 3371 } 3372 3373 /* 3374 * pmap_remove() 3375 * 3376 * pmap_remove is responsible for nuking a number of mappings for a range 3377 * of virtual address space in the current pmap. To do this efficiently 3378 * is interesting, because in a number of cases a wide virtual address 3379 * range may be supplied that contains few actual mappings. So, the 3380 * optimisations are: 3381 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3382 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3383 * maybe do just a partial cache clean. This path of execution is 3384 * complicated by the fact that the cache must be flushed _before_ 3385 * the PTE is nuked, being a VAC :-) 3386 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3387 * all invalidations until pmap_update(), since pmap_remove_all() has 3388 * already flushed the cache. 3389 * 4. Maybe later fast-case a single page, but I don't think this is 3390 * going to make _that_ much difference overall. 3391 */ 3392 3393 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3394 3395 void 3396 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3397 { 3398 vaddr_t next_bucket; 3399 u_int cleanlist_idx, total, cnt; 3400 struct { 3401 vaddr_t va; 3402 pt_entry_t *ptep; 3403 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3404 u_int mappings; 3405 3406 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3407 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3408 3409 /* 3410 * we lock in the pmap => pv_head direction 3411 */ 3412 pmap_acquire_pmap_lock(pm); 3413 3414 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3415 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3416 #ifndef ARM_MMU_EXTENDED 3417 if (pm->pm_cstate.cs_tlb == 0) 3418 pm->pm_remove_all = true; 3419 #endif 3420 } else 3421 cleanlist_idx = 0; 3422 3423 total = 0; 3424 3425 while (sva < eva) { 3426 /* 3427 * Do one L2 bucket's worth at a time. 3428 */ 3429 next_bucket = L2_NEXT_BUCKET_VA(sva); 3430 if (next_bucket > eva) 3431 next_bucket = eva; 3432 3433 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3434 if (l2b == NULL) { 3435 sva = next_bucket; 3436 continue; 3437 } 3438 3439 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3440 3441 for (mappings = 0; 3442 sva < next_bucket; 3443 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3444 pt_entry_t opte = *ptep; 3445 3446 if (opte == 0) { 3447 /* Nothing here, move along */ 3448 continue; 3449 } 3450 3451 u_int flags = PVF_REF; 3452 paddr_t pa = l2pte_pa(opte); 3453 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3454 3455 /* 3456 * Update flags. In a number of circumstances, 3457 * we could cluster a lot of these and do a 3458 * number of sequential pages in one go. 3459 */ 3460 if (pg != NULL) { 3461 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3462 struct pv_entry *pv; 3463 3464 pmap_acquire_page_lock(md); 3465 pv = pmap_remove_pv(md, pa, pm, sva); 3466 pmap_vac_me_harder(md, pa, pm, 0); 3467 pmap_release_page_lock(md); 3468 if (pv != NULL) { 3469 if (pm->pm_remove_all == false) { 3470 flags = pv->pv_flags; 3471 } 3472 pool_put(&pmap_pv_pool, pv); 3473 } 3474 } 3475 mappings += PAGE_SIZE / L2_S_SIZE; 3476 3477 if (!l2pte_valid_p(opte)) { 3478 /* 3479 * Ref/Mod emulation is still active for this 3480 * mapping, therefore it is has not yet been 3481 * accessed. No need to frob the cache/tlb. 3482 */ 3483 l2pte_reset(ptep); 3484 PTE_SYNC_CURRENT(pm, ptep); 3485 continue; 3486 } 3487 3488 #ifdef ARM_MMU_EXTENDED 3489 if (pm == pmap_kernel()) { 3490 l2pte_reset(ptep); 3491 PTE_SYNC(ptep); 3492 pmap_tlb_flush_SE(pm, sva, flags); 3493 continue; 3494 } 3495 #endif 3496 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3497 /* Add to the clean list. */ 3498 cleanlist[cleanlist_idx].ptep = ptep; 3499 cleanlist[cleanlist_idx].va = 3500 sva | (flags & PVF_EXEC); 3501 cleanlist_idx++; 3502 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3503 /* Nuke everything if needed. */ 3504 #ifdef PMAP_CACHE_VIVT 3505 pmap_cache_wbinv_all(pm, PVF_EXEC); 3506 #endif 3507 /* 3508 * Roll back the previous PTE list, 3509 * and zero out the current PTE. 3510 */ 3511 for (cnt = 0; 3512 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3513 l2pte_reset(cleanlist[cnt].ptep); 3514 PTE_SYNC(cleanlist[cnt].ptep); 3515 } 3516 l2pte_reset(ptep); 3517 PTE_SYNC(ptep); 3518 cleanlist_idx++; 3519 pm->pm_remove_all = true; 3520 } else { 3521 l2pte_reset(ptep); 3522 PTE_SYNC(ptep); 3523 if (pm->pm_remove_all == false) { 3524 pmap_tlb_flush_SE(pm, sva, flags); 3525 } 3526 } 3527 } 3528 3529 /* 3530 * Deal with any left overs 3531 */ 3532 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3533 total += cleanlist_idx; 3534 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3535 #ifdef ARM_MMU_EXTENDED 3536 vaddr_t clva = cleanlist[cnt].va; 3537 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3538 #else 3539 vaddr_t va = cleanlist[cnt].va; 3540 if (pm->pm_cstate.cs_all != 0) { 3541 vaddr_t clva = va & ~PAGE_MASK; 3542 u_int flags = va & PVF_EXEC; 3543 #ifdef PMAP_CACHE_VIVT 3544 pmap_cache_wbinv_page(pm, clva, true, 3545 PVF_REF | PVF_WRITE | flags); 3546 #endif 3547 pmap_tlb_flush_SE(pm, clva, 3548 PVF_REF | flags); 3549 } 3550 #endif /* ARM_MMU_EXTENDED */ 3551 l2pte_reset(cleanlist[cnt].ptep); 3552 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3553 } 3554 3555 /* 3556 * If it looks like we're removing a whole bunch 3557 * of mappings, it's faster to just write-back 3558 * the whole cache now and defer TLB flushes until 3559 * pmap_update() is called. 3560 */ 3561 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3562 cleanlist_idx = 0; 3563 else { 3564 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3565 #ifdef PMAP_CACHE_VIVT 3566 pmap_cache_wbinv_all(pm, PVF_EXEC); 3567 #endif 3568 pm->pm_remove_all = true; 3569 } 3570 } 3571 3572 3573 pmap_free_l2_bucket(pm, l2b, mappings); 3574 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3575 } 3576 3577 pmap_release_pmap_lock(pm); 3578 } 3579 3580 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3581 static struct pv_entry * 3582 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3583 { 3584 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3585 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3586 struct pv_entry *pv; 3587 3588 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3589 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3590 KASSERT(pmap_page_locked_p(md)); 3591 3592 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3593 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3594 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3595 3596 /* 3597 * If we are removing a writeable mapping to a cached exec page, 3598 * if it's the last mapping then clear it execness other sync 3599 * the page to the icache. 3600 */ 3601 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3602 && (pv->pv_flags & PVF_WRITE) != 0) { 3603 if (SLIST_EMPTY(&md->pvh_list)) { 3604 md->pvh_attrs &= ~PVF_EXEC; 3605 PMAPCOUNT(exec_discarded_kremove); 3606 } else { 3607 pmap_syncicache_page(md, pa); 3608 PMAPCOUNT(exec_synced_kremove); 3609 } 3610 } 3611 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3612 3613 return pv; 3614 } 3615 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3616 3617 /* 3618 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3619 * 3620 * We assume there is already sufficient KVM space available 3621 * to do this, as we can't allocate L2 descriptor tables/metadata 3622 * from here. 3623 */ 3624 void 3625 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3626 { 3627 #ifdef PMAP_CACHE_VIVT 3628 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3629 #endif 3630 #ifdef PMAP_CACHE_VIPT 3631 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3632 struct vm_page *opg; 3633 #ifndef ARM_MMU_EXTENDED 3634 struct pv_entry *pv = NULL; 3635 #endif 3636 #endif 3637 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3638 3639 UVMHIST_FUNC(__func__); 3640 3641 if (pmap_initialized) { 3642 UVMHIST_CALLED(maphist); 3643 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3644 va, pa, prot, flags); 3645 } 3646 3647 pmap_t kpm = pmap_kernel(); 3648 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3649 const size_t l1slot __diagused = l1pte_index(va); 3650 KASSERTMSG(l2b != NULL, 3651 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3652 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3653 kpm->pm_l2[L2_IDX(l1slot)] 3654 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3655 : NULL, 3656 kpm->pm_l2[L2_IDX(l1slot)] 3657 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3658 : NULL); 3659 KASSERT(l2b->l2b_kva != NULL); 3660 3661 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3662 const pt_entry_t opte = *ptep; 3663 3664 if (opte == 0) { 3665 PMAPCOUNT(kenter_mappings); 3666 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3667 } else { 3668 PMAPCOUNT(kenter_remappings); 3669 #ifdef PMAP_CACHE_VIPT 3670 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3671 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3672 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3673 #endif 3674 if (opg && arm_cache_prefer_mask != 0) { 3675 KASSERT(opg != pg); 3676 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3677 KASSERT((flags & PMAP_KMPAGE) == 0); 3678 #ifndef ARM_MMU_EXTENDED 3679 pmap_acquire_page_lock(omd); 3680 pv = pmap_kremove_pg(opg, va); 3681 pmap_release_page_lock(omd); 3682 #endif 3683 } 3684 #endif 3685 if (l2pte_valid_p(opte)) { 3686 #ifdef PMAP_CACHE_VIVT 3687 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3688 #endif 3689 cpu_tlb_flushD_SE(va); 3690 cpu_cpwait(); 3691 } 3692 } 3693 3694 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3695 | ((flags & PMAP_NOCACHE) 3696 ? 0 3697 : ((flags & PMAP_PTE) 3698 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3699 #ifdef ARM_MMU_EXTENDED 3700 if (prot & VM_PROT_EXECUTE) 3701 npte &= ~L2_XS_XN; 3702 #endif 3703 l2pte_set(ptep, npte, opte); 3704 PTE_SYNC(ptep); 3705 3706 if (pg) { 3707 if (flags & PMAP_KMPAGE) { 3708 KASSERT(md->urw_mappings == 0); 3709 KASSERT(md->uro_mappings == 0); 3710 KASSERT(md->krw_mappings == 0); 3711 KASSERT(md->kro_mappings == 0); 3712 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3713 KASSERT(pv == NULL); 3714 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3715 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3716 /* if there is a color conflict, evict from cache. */ 3717 if (pmap_is_page_colored_p(md) 3718 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3719 PMAPCOUNT(vac_color_change); 3720 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3721 } else if (md->pvh_attrs & PVF_MULTCLR) { 3722 /* 3723 * If this page has multiple colors, expunge 3724 * them. 3725 */ 3726 PMAPCOUNT(vac_flush_lots2); 3727 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3728 } 3729 /* 3730 * Since this is a KMPAGE, there can be no contention 3731 * for this page so don't lock it. 3732 */ 3733 md->pvh_attrs &= PAGE_SIZE - 1; 3734 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3735 | (va & arm_cache_prefer_mask); 3736 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3737 md->pvh_attrs |= PVF_KMPAGE; 3738 #endif 3739 atomic_inc_32(&pmap_kmpages); 3740 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3741 } else if (arm_cache_prefer_mask != 0) { 3742 if (pv == NULL) { 3743 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3744 KASSERT(pv != NULL); 3745 } 3746 pmap_acquire_page_lock(md); 3747 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3748 PVF_WIRED | PVF_KENTRY 3749 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3750 if ((prot & VM_PROT_WRITE) 3751 && !(md->pvh_attrs & PVF_NC)) 3752 md->pvh_attrs |= PVF_DIRTY; 3753 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3754 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3755 pmap_release_page_lock(md); 3756 #endif 3757 } 3758 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3759 } else { 3760 if (pv != NULL) 3761 pool_put(&pmap_pv_pool, pv); 3762 #endif 3763 } 3764 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3765 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3766 #endif 3767 if (pmap_initialized) { 3768 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3769 ptep, opte, npte, 0); 3770 } 3771 3772 } 3773 3774 void 3775 pmap_kremove(vaddr_t va, vsize_t len) 3776 { 3777 #ifdef UVMHIST 3778 u_int total_mappings = 0; 3779 #endif 3780 3781 PMAPCOUNT(kenter_unmappings); 3782 3783 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3784 3785 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3786 3787 const vaddr_t eva = va + len; 3788 3789 while (va < eva) { 3790 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3791 if (next_bucket > eva) 3792 next_bucket = eva; 3793 3794 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3795 KDASSERT(l2b != NULL); 3796 3797 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3798 pt_entry_t *ptep = sptep; 3799 u_int mappings = 0; 3800 3801 while (va < next_bucket) { 3802 const pt_entry_t opte = *ptep; 3803 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3804 if (opg != NULL) { 3805 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3806 3807 if (omd->pvh_attrs & PVF_KMPAGE) { 3808 KASSERT(omd->urw_mappings == 0); 3809 KASSERT(omd->uro_mappings == 0); 3810 KASSERT(omd->krw_mappings == 0); 3811 KASSERT(omd->kro_mappings == 0); 3812 omd->pvh_attrs &= ~PVF_KMPAGE; 3813 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3814 if (arm_cache_prefer_mask != 0) { 3815 omd->pvh_attrs &= ~PVF_WRITE; 3816 } 3817 #endif 3818 atomic_dec_32(&pmap_kmpages); 3819 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3820 } else if (arm_cache_prefer_mask != 0) { 3821 pmap_acquire_page_lock(omd); 3822 pool_put(&pmap_pv_pool, 3823 pmap_kremove_pg(opg, va)); 3824 pmap_release_page_lock(omd); 3825 #endif 3826 } 3827 } 3828 if (l2pte_valid_p(opte)) { 3829 #ifdef PMAP_CACHE_VIVT 3830 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3831 #endif 3832 cpu_tlb_flushD_SE(va); 3833 } 3834 if (opte) { 3835 l2pte_reset(ptep); 3836 mappings += PAGE_SIZE / L2_S_SIZE; 3837 } 3838 va += PAGE_SIZE; 3839 ptep += PAGE_SIZE / L2_S_SIZE; 3840 } 3841 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3842 mappings, l2b->l2b_occupancy); 3843 l2b->l2b_occupancy -= mappings; 3844 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3845 #ifdef UVMHIST 3846 total_mappings += mappings; 3847 #endif 3848 } 3849 cpu_cpwait(); 3850 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3851 total_mappings, 0, 0, 0); 3852 } 3853 3854 bool 3855 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3856 { 3857 struct l2_dtable *l2; 3858 pd_entry_t *pdep, pde; 3859 pt_entry_t *ptep, pte; 3860 paddr_t pa; 3861 u_int l1slot; 3862 3863 pmap_acquire_pmap_lock(pm); 3864 3865 l1slot = l1pte_index(va); 3866 pdep = pmap_l1_kva(pm) + l1slot; 3867 pde = *pdep; 3868 3869 if (l1pte_section_p(pde)) { 3870 /* 3871 * These should only happen for pmap_kernel() 3872 */ 3873 KDASSERT(pm == pmap_kernel()); 3874 pmap_release_pmap_lock(pm); 3875 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3876 if (l1pte_supersection_p(pde)) { 3877 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3878 } else 3879 #endif 3880 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3881 } else { 3882 /* 3883 * Note that we can't rely on the validity of the L1 3884 * descriptor as an indication that a mapping exists. 3885 * We have to look it up in the L2 dtable. 3886 */ 3887 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3888 3889 if (l2 == NULL || 3890 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3891 pmap_release_pmap_lock(pm); 3892 return false; 3893 } 3894 3895 pte = ptep[l2pte_index(va)]; 3896 pmap_release_pmap_lock(pm); 3897 3898 if (pte == 0) 3899 return false; 3900 3901 switch (pte & L2_TYPE_MASK) { 3902 case L2_TYPE_L: 3903 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3904 break; 3905 3906 default: 3907 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3908 break; 3909 } 3910 } 3911 3912 if (pap != NULL) 3913 *pap = pa; 3914 3915 return true; 3916 } 3917 3918 void 3919 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3920 { 3921 struct l2_bucket *l2b; 3922 vaddr_t next_bucket; 3923 3924 NPDEBUG(PDB_PROTECT, 3925 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3926 pm, sva, eva, prot)); 3927 3928 if ((prot & VM_PROT_READ) == 0) { 3929 pmap_remove(pm, sva, eva); 3930 return; 3931 } 3932 3933 if (prot & VM_PROT_WRITE) { 3934 /* 3935 * If this is a read->write transition, just ignore it and let 3936 * uvm_fault() take care of it later. 3937 */ 3938 return; 3939 } 3940 3941 pmap_acquire_pmap_lock(pm); 3942 3943 const bool flush = eva - sva >= PAGE_SIZE * 4; 3944 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3945 u_int flags = 0; 3946 3947 while (sva < eva) { 3948 next_bucket = L2_NEXT_BUCKET_VA(sva); 3949 if (next_bucket > eva) 3950 next_bucket = eva; 3951 3952 l2b = pmap_get_l2_bucket(pm, sva); 3953 if (l2b == NULL) { 3954 sva = next_bucket; 3955 continue; 3956 } 3957 3958 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3959 3960 while (sva < next_bucket) { 3961 const pt_entry_t opte = *ptep; 3962 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3963 struct vm_page *pg; 3964 u_int f; 3965 3966 #ifdef PMAP_CACHE_VIVT 3967 /* 3968 * OK, at this point, we know we're doing 3969 * write-protect operation. If the pmap is 3970 * active, write-back the page. 3971 */ 3972 pmap_cache_wbinv_page(pm, sva, false, 3973 PVF_REF | PVF_WRITE); 3974 #endif 3975 3976 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3977 pt_entry_t npte = l2pte_set_readonly(opte); 3978 l2pte_set(ptep, npte, opte); 3979 PTE_SYNC(ptep); 3980 3981 if (pg != NULL) { 3982 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3983 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3984 3985 pmap_acquire_page_lock(md); 3986 f = pmap_modify_pv(md, pa, pm, sva, 3987 clr_mask, 0); 3988 pmap_vac_me_harder(md, pa, pm, sva); 3989 pmap_release_page_lock(md); 3990 } else { 3991 f = PVF_REF | PVF_EXEC; 3992 } 3993 3994 if (flush) { 3995 flags |= f; 3996 } else { 3997 pmap_tlb_flush_SE(pm, sva, f); 3998 } 3999 } 4000 4001 sva += PAGE_SIZE; 4002 ptep += PAGE_SIZE / L2_S_SIZE; 4003 } 4004 } 4005 4006 if (flush) { 4007 if (PV_BEEN_EXECD(flags)) { 4008 pmap_tlb_flushID(pm); 4009 } else if (PV_BEEN_REFD(flags)) { 4010 pmap_tlb_flushD(pm); 4011 } 4012 } 4013 4014 pmap_release_pmap_lock(pm); 4015 } 4016 4017 void 4018 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4019 { 4020 struct l2_bucket *l2b; 4021 pt_entry_t *ptep; 4022 vaddr_t next_bucket; 4023 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4024 4025 NPDEBUG(PDB_EXEC, 4026 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4027 pm, sva, eva)); 4028 4029 pmap_acquire_pmap_lock(pm); 4030 4031 while (sva < eva) { 4032 next_bucket = L2_NEXT_BUCKET_VA(sva); 4033 if (next_bucket > eva) 4034 next_bucket = eva; 4035 4036 l2b = pmap_get_l2_bucket(pm, sva); 4037 if (l2b == NULL) { 4038 sva = next_bucket; 4039 continue; 4040 } 4041 4042 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4043 sva < next_bucket; 4044 sva += page_size, 4045 ptep += PAGE_SIZE / L2_S_SIZE, 4046 page_size = PAGE_SIZE) { 4047 if (l2pte_valid_p(*ptep)) { 4048 cpu_icache_sync_range(sva, 4049 min(page_size, eva - sva)); 4050 } 4051 } 4052 } 4053 4054 pmap_release_pmap_lock(pm); 4055 } 4056 4057 void 4058 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4059 { 4060 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4061 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4062 4063 NPDEBUG(PDB_PROTECT, 4064 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4065 md, pa, prot)); 4066 4067 switch(prot) { 4068 case VM_PROT_READ|VM_PROT_WRITE: 4069 #if defined(ARM_MMU_EXTENDED) 4070 pmap_acquire_page_lock(md); 4071 pmap_clearbit(md, pa, PVF_EXEC); 4072 pmap_release_page_lock(md); 4073 break; 4074 #endif 4075 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4076 break; 4077 4078 case VM_PROT_READ: 4079 #if defined(ARM_MMU_EXTENDED) 4080 pmap_acquire_page_lock(md); 4081 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4082 pmap_release_page_lock(md); 4083 break; 4084 #endif 4085 case VM_PROT_READ|VM_PROT_EXECUTE: 4086 pmap_acquire_page_lock(md); 4087 pmap_clearbit(md, pa, PVF_WRITE); 4088 pmap_release_page_lock(md); 4089 break; 4090 4091 default: 4092 pmap_page_remove(md, pa); 4093 break; 4094 } 4095 } 4096 4097 /* 4098 * pmap_clear_modify: 4099 * 4100 * Clear the "modified" attribute for a page. 4101 */ 4102 bool 4103 pmap_clear_modify(struct vm_page *pg) 4104 { 4105 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4106 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4107 bool rv; 4108 4109 pmap_acquire_page_lock(md); 4110 4111 if (md->pvh_attrs & PVF_MOD) { 4112 rv = true; 4113 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4114 /* 4115 * If we are going to clear the modified bit and there are 4116 * no other modified bits set, flush the page to memory and 4117 * mark it clean. 4118 */ 4119 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4120 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4121 #endif 4122 pmap_clearbit(md, pa, PVF_MOD); 4123 } else { 4124 rv = false; 4125 } 4126 pmap_release_page_lock(md); 4127 4128 return rv; 4129 } 4130 4131 /* 4132 * pmap_clear_reference: 4133 * 4134 * Clear the "referenced" attribute for a page. 4135 */ 4136 bool 4137 pmap_clear_reference(struct vm_page *pg) 4138 { 4139 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4140 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4141 bool rv; 4142 4143 pmap_acquire_page_lock(md); 4144 4145 if (md->pvh_attrs & PVF_REF) { 4146 rv = true; 4147 pmap_clearbit(md, pa, PVF_REF); 4148 } else { 4149 rv = false; 4150 } 4151 pmap_release_page_lock(md); 4152 4153 return rv; 4154 } 4155 4156 /* 4157 * pmap_is_modified: 4158 * 4159 * Test if a page has the "modified" attribute. 4160 */ 4161 /* See <arm/arm32/pmap.h> */ 4162 4163 /* 4164 * pmap_is_referenced: 4165 * 4166 * Test if a page has the "referenced" attribute. 4167 */ 4168 /* See <arm/arm32/pmap.h> */ 4169 4170 #if defined(ARM_MMU_EXTENDED) && 0 4171 int 4172 pmap_prefetchabt_fixup(void *v) 4173 { 4174 struct trapframe * const tf = v; 4175 vaddr_t va = trunc_page(tf->tf_pc); 4176 int rv = ABORT_FIXUP_FAILED; 4177 4178 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4179 return rv; 4180 4181 kpreempt_disable(); 4182 pmap_t pm = curcpu()->ci_pmap_cur; 4183 const size_t l1slot = l1pte_index(va); 4184 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4185 if (l2 == NULL) 4186 goto out; 4187 4188 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4189 if (l2b->l2b_kva == NULL) 4190 goto out; 4191 4192 /* 4193 * Check the PTE itself. 4194 */ 4195 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4196 const pt_entry_t opte = *ptep; 4197 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4198 goto out; 4199 4200 paddr_t pa = l2pte_pa(pte); 4201 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4202 KASSERT(pg != NULL); 4203 4204 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4205 4206 pmap_acquire_page_lock(md); 4207 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4208 KASSERT(pv != NULL); 4209 4210 if (PV_IS_EXEC_P(pv->pv_flags)) { 4211 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4212 pmap_syncicache_page(md, pa); 4213 } 4214 rv = ABORT_FIXUP_RETURN; 4215 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4216 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4217 } 4218 pmap_release_page_lock(md); 4219 4220 out: 4221 kpreempt_enable(); 4222 return rv; 4223 } 4224 #endif 4225 4226 int 4227 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4228 { 4229 struct l2_dtable *l2; 4230 struct l2_bucket *l2b; 4231 paddr_t pa; 4232 const size_t l1slot = l1pte_index(va); 4233 int rv = 0; 4234 4235 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4236 4237 va = trunc_page(va); 4238 4239 KASSERT(!user || (pm != pmap_kernel())); 4240 4241 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4242 pm, va, ftype, user); 4243 #ifdef ARM_MMU_EXTENDED 4244 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4245 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4246 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4247 #endif 4248 4249 pmap_acquire_pmap_lock(pm); 4250 4251 /* 4252 * If there is no l2_dtable for this address, then the process 4253 * has no business accessing it. 4254 * 4255 * Note: This will catch userland processes trying to access 4256 * kernel addresses. 4257 */ 4258 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4259 if (l2 == NULL) { 4260 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4261 goto out; 4262 } 4263 4264 /* 4265 * Likewise if there is no L2 descriptor table 4266 */ 4267 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4268 if (l2b->l2b_kva == NULL) { 4269 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4270 goto out; 4271 } 4272 4273 /* 4274 * Check the PTE itself. 4275 */ 4276 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4277 pt_entry_t const opte = *ptep; 4278 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4279 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4280 goto out; 4281 } 4282 4283 #ifndef ARM_HAS_VBAR 4284 /* 4285 * Catch a userland access to the vector page mapped at 0x0 4286 */ 4287 if (user && (opte & L2_S_PROT_U) == 0) { 4288 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4289 goto out; 4290 } 4291 #endif 4292 4293 pa = l2pte_pa(opte); 4294 4295 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4296 /* 4297 * This looks like a good candidate for "page modified" 4298 * emulation... 4299 */ 4300 struct pv_entry *pv; 4301 struct vm_page *pg; 4302 4303 /* Extract the physical address of the page */ 4304 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4305 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4306 goto out; 4307 } 4308 4309 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4310 4311 /* Get the current flags for this page. */ 4312 pmap_acquire_page_lock(md); 4313 pv = pmap_find_pv(md, pm, va); 4314 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4315 pmap_release_page_lock(md); 4316 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4317 goto out; 4318 } 4319 4320 /* 4321 * Do the flags say this page is writable? If not then it 4322 * is a genuine write fault. If yes then the write fault is 4323 * our fault as we did not reflect the write access in the 4324 * PTE. Now we know a write has occurred we can correct this 4325 * and also set the modified bit 4326 */ 4327 if ((pv->pv_flags & PVF_WRITE) == 0) { 4328 pmap_release_page_lock(md); 4329 goto out; 4330 } 4331 4332 md->pvh_attrs |= PVF_REF | PVF_MOD; 4333 pv->pv_flags |= PVF_REF | PVF_MOD; 4334 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4335 /* 4336 * If there are cacheable mappings for this page, mark it dirty. 4337 */ 4338 if ((md->pvh_attrs & PVF_NC) == 0) 4339 md->pvh_attrs |= PVF_DIRTY; 4340 #endif 4341 #ifdef ARM_MMU_EXTENDED 4342 if (md->pvh_attrs & PVF_EXEC) { 4343 md->pvh_attrs &= ~PVF_EXEC; 4344 PMAPCOUNT(exec_discarded_modfixup); 4345 } 4346 #endif 4347 pmap_release_page_lock(md); 4348 4349 /* 4350 * Re-enable write permissions for the page. No need to call 4351 * pmap_vac_me_harder(), since this is just a 4352 * modified-emulation fault, and the PVF_WRITE bit isn't 4353 * changing. We've already set the cacheable bits based on 4354 * the assumption that we can write to this page. 4355 */ 4356 const pt_entry_t npte = 4357 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4358 #ifdef ARM_MMU_EXTENDED 4359 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4360 #endif 4361 | 0; 4362 l2pte_set(ptep, npte, opte); 4363 PTE_SYNC(ptep); 4364 PMAPCOUNT(fixup_mod); 4365 rv = 1; 4366 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4367 opte, npte, 0, 0); 4368 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4369 /* 4370 * This looks like a good candidate for "page referenced" 4371 * emulation. 4372 */ 4373 struct vm_page *pg; 4374 4375 /* Extract the physical address of the page */ 4376 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4377 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4378 goto out; 4379 } 4380 4381 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4382 4383 /* Get the current flags for this page. */ 4384 pmap_acquire_page_lock(md); 4385 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4386 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4387 pmap_release_page_lock(md); 4388 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4389 goto out; 4390 } 4391 4392 md->pvh_attrs |= PVF_REF; 4393 pv->pv_flags |= PVF_REF; 4394 4395 pt_entry_t npte = 4396 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4397 #ifdef ARM_MMU_EXTENDED 4398 if (pm != pmap_kernel()) { 4399 npte |= L2_XS_nG; 4400 } 4401 /* 4402 * If we got called from prefetch abort, then ftype will have 4403 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4404 * the PTE. 4405 */ 4406 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4407 /* 4408 * Is this a mapping of an executable page? 4409 */ 4410 if ((pv->pv_flags & PVF_EXEC) == 0) { 4411 pmap_release_page_lock(md); 4412 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4413 0, 0, 0, 0); 4414 goto out; 4415 } 4416 /* 4417 * If we haven't synced the page, do so now. 4418 */ 4419 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4420 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4421 pa, 0, 0, 0); 4422 pmap_syncicache_page(md, pa); 4423 PMAPCOUNT(fixup_exec); 4424 } 4425 npte &= ~L2_XS_XN; 4426 } 4427 #endif /* ARM_MMU_EXTENDED */ 4428 pmap_release_page_lock(md); 4429 l2pte_set(ptep, npte, opte); 4430 PTE_SYNC(ptep); 4431 PMAPCOUNT(fixup_ref); 4432 rv = 1; 4433 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4434 opte, npte, 0, 0); 4435 #ifdef ARM_MMU_EXTENDED 4436 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4437 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4438 if (pg == NULL) { 4439 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4440 goto out; 4441 } 4442 4443 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4444 4445 /* Get the current flags for this page. */ 4446 pmap_acquire_page_lock(md); 4447 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4448 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4449 pmap_release_page_lock(md); 4450 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4451 goto out; 4452 } 4453 4454 /* 4455 * If we haven't synced the page, do so now. 4456 */ 4457 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4458 UVMHIST_LOG(maphist, "syncicache page #%#x", 4459 pa, 0, 0, 0); 4460 pmap_syncicache_page(md, pa); 4461 } 4462 pmap_release_page_lock(md); 4463 /* 4464 * Turn off no-execute. 4465 */ 4466 KASSERT(opte & L2_XS_nG); 4467 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4468 PTE_SYNC(ptep); 4469 rv = 1; 4470 PMAPCOUNT(fixup_exec); 4471 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4472 opte, opte & ~L2_XS_XN, 0, 0); 4473 #endif 4474 } 4475 4476 #ifndef ARM_MMU_EXTENDED 4477 /* 4478 * We know there is a valid mapping here, so simply 4479 * fix up the L1 if necessary. 4480 */ 4481 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4482 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4483 if (*pdep != pde) { 4484 l1pte_setone(pdep, pde); 4485 PTE_SYNC(pdep); 4486 rv = 1; 4487 PMAPCOUNT(fixup_pdes); 4488 } 4489 #endif 4490 4491 #ifdef CPU_SA110 4492 /* 4493 * There are bugs in the rev K SA110. This is a check for one 4494 * of them. 4495 */ 4496 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4497 curcpu()->ci_arm_cpurev < 3) { 4498 /* Always current pmap */ 4499 if (l2pte_valid_p(opte)) { 4500 extern int kernel_debug; 4501 if (kernel_debug & 1) { 4502 struct proc *p = curlwp->l_proc; 4503 printf("prefetch_abort: page is already " 4504 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4505 printf("prefetch_abort: pc=%08lx proc=%p " 4506 "process=%s\n", va, p, p->p_comm); 4507 printf("prefetch_abort: far=%08x fs=%x\n", 4508 cpu_faultaddress(), cpu_faultstatus()); 4509 } 4510 #ifdef DDB 4511 if (kernel_debug & 2) 4512 Debugger(); 4513 #endif 4514 rv = 1; 4515 } 4516 } 4517 #endif /* CPU_SA110 */ 4518 4519 #ifndef ARM_MMU_EXTENDED 4520 /* 4521 * If 'rv == 0' at this point, it generally indicates that there is a 4522 * stale TLB entry for the faulting address. That might be due to a 4523 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4524 */ 4525 if (rv == 0 4526 && pm->pm_l1->l1_domain_use_count == 1 4527 && pmap_needs_pte_sync == 0) { 4528 pmap_needs_pte_sync = 1; 4529 PTE_SYNC(ptep); 4530 PMAPCOUNT(fixup_ptesync); 4531 rv = 1; 4532 } 4533 #endif 4534 4535 #if defined(DEBUG) || 1 4536 /* 4537 * If 'rv == 0' at this point, it generally indicates that there is a 4538 * stale TLB entry for the faulting address. This happens when two or 4539 * more processes are sharing an L1. Since we don't flush the TLB on 4540 * a context switch between such processes, we can take domain faults 4541 * for mappings which exist at the same VA in both processes. EVEN IF 4542 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4543 * example. 4544 * 4545 * This is extremely likely to happen if pmap_enter() updated the L1 4546 * entry for a recently entered mapping. In this case, the TLB is 4547 * flushed for the new mapping, but there may still be TLB entries for 4548 * other mappings belonging to other processes in the 1MB range 4549 * covered by the L1 entry. 4550 * 4551 * Since 'rv == 0', we know that the L1 already contains the correct 4552 * value, so the fault must be due to a stale TLB entry. 4553 * 4554 * Since we always need to flush the TLB anyway in the case where we 4555 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4556 * stale TLB entries dynamically. 4557 * 4558 * However, the above condition can ONLY happen if the current L1 is 4559 * being shared. If it happens when the L1 is unshared, it indicates 4560 * that other parts of the pmap are not doing their job WRT managing 4561 * the TLB. 4562 */ 4563 if (rv == 0 4564 #ifndef ARM_MMU_EXTENDED 4565 && pm->pm_l1->l1_domain_use_count == 1 4566 #endif 4567 && true) { 4568 #ifdef DEBUG 4569 extern int last_fault_code; 4570 #else 4571 int last_fault_code = ftype & VM_PROT_EXECUTE 4572 ? armreg_ifsr_read() 4573 : armreg_dfsr_read(); 4574 #endif 4575 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4576 pm, va, ftype); 4577 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4578 l2, l2b, ptep, opte); 4579 4580 #ifndef ARM_MMU_EXTENDED 4581 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4582 pdep, pde, last_fault_code); 4583 #else 4584 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4585 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4586 armreg_ttbcr_read()); 4587 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4588 last_fault_code, curcpu()->ci_pmap_cur, 4589 curcpu()->ci_pmap_asid_cur, 4590 armreg_contextidr_read(), armreg_dacr_read()); 4591 #ifdef _ARM_ARCH_7 4592 if (ftype & VM_PROT_WRITE) 4593 armreg_ats1cuw_write(va); 4594 else 4595 armreg_ats1cur_write(va); 4596 arm_isb(); 4597 printf("fixup: par %#x\n", armreg_par_read()); 4598 #endif 4599 #endif 4600 #ifdef DDB 4601 extern int kernel_debug; 4602 4603 if (kernel_debug & 2) { 4604 pmap_release_pmap_lock(pm); 4605 #ifdef UVMHIST 4606 KERNHIST_DUMP(maphist); 4607 #endif 4608 cpu_Debugger(); 4609 pmap_acquire_pmap_lock(pm); 4610 } 4611 #endif 4612 } 4613 #endif 4614 4615 pmap_tlb_flush_SE(pm, va, 4616 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4617 4618 rv = 1; 4619 4620 out: 4621 pmap_release_pmap_lock(pm); 4622 4623 return (rv); 4624 } 4625 4626 /* 4627 * Routine: pmap_procwr 4628 * 4629 * Function: 4630 * Synchronize caches corresponding to [addr, addr+len) in p. 4631 * 4632 */ 4633 void 4634 pmap_procwr(struct proc *p, vaddr_t va, int len) 4635 { 4636 /* We only need to do anything if it is the current process. */ 4637 if (p == curproc) 4638 cpu_icache_sync_range(va, len); 4639 } 4640 4641 /* 4642 * Routine: pmap_unwire 4643 * Function: Clear the wired attribute for a map/virtual-address pair. 4644 * 4645 * In/out conditions: 4646 * The mapping must already exist in the pmap. 4647 */ 4648 void 4649 pmap_unwire(pmap_t pm, vaddr_t va) 4650 { 4651 struct l2_bucket *l2b; 4652 pt_entry_t *ptep, pte; 4653 struct vm_page *pg; 4654 paddr_t pa; 4655 4656 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4657 4658 pmap_acquire_pmap_lock(pm); 4659 4660 l2b = pmap_get_l2_bucket(pm, va); 4661 KDASSERT(l2b != NULL); 4662 4663 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4664 pte = *ptep; 4665 4666 /* Extract the physical address of the page */ 4667 pa = l2pte_pa(pte); 4668 4669 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4670 /* Update the wired bit in the pv entry for this page. */ 4671 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4672 4673 pmap_acquire_page_lock(md); 4674 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4675 pmap_release_page_lock(md); 4676 } 4677 4678 pmap_release_pmap_lock(pm); 4679 } 4680 4681 void 4682 pmap_activate(struct lwp *l) 4683 { 4684 struct cpu_info * const ci = curcpu(); 4685 extern int block_userspace_access; 4686 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4687 #ifdef ARM_MMU_EXTENDED 4688 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4689 #endif 4690 4691 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4692 4693 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4694 4695 /* 4696 * If activating a non-current lwp or the current lwp is 4697 * already active, just return. 4698 */ 4699 if (false 4700 || l != curlwp 4701 #ifdef ARM_MMU_EXTENDED 4702 || (ci->ci_pmap_cur == npm && 4703 (npm == pmap_kernel() 4704 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4705 #else 4706 || npm->pm_activated == true 4707 #endif 4708 || false) { 4709 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4710 return; 4711 } 4712 4713 #ifndef ARM_MMU_EXTENDED 4714 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4715 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4716 4717 /* 4718 * If TTB and DACR are unchanged, short-circuit all the 4719 * TLB/cache management stuff. 4720 */ 4721 pmap_t opm = ci->ci_lastlwp 4722 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4723 : NULL; 4724 if (opm != NULL) { 4725 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4726 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4727 4728 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4729 goto all_done; 4730 } 4731 #endif /* !ARM_MMU_EXTENDED */ 4732 4733 PMAPCOUNT(activations); 4734 block_userspace_access = 1; 4735 4736 #ifndef ARM_MMU_EXTENDED 4737 /* 4738 * If switching to a user vmspace which is different to the 4739 * most recent one, and the most recent one is potentially 4740 * live in the cache, we must write-back and invalidate the 4741 * entire cache. 4742 */ 4743 pmap_t rpm = ci->ci_pmap_lastuser; 4744 #endif 4745 4746 /* 4747 * XXXSCW: There's a corner case here which can leave turds in the cache as 4748 * reported in kern/41058. They're probably left over during tear-down and 4749 * switching away from an exiting process. Until the root cause is identified 4750 * and fixed, zap the cache when switching pmaps. This will result in a few 4751 * unnecessary cache flushes, but that's better than silently corrupting data. 4752 */ 4753 #ifndef ARM_MMU_EXTENDED 4754 #if 0 4755 if (npm != pmap_kernel() && rpm && npm != rpm && 4756 rpm->pm_cstate.cs_cache) { 4757 rpm->pm_cstate.cs_cache = 0; 4758 #ifdef PMAP_CACHE_VIVT 4759 cpu_idcache_wbinv_all(); 4760 #endif 4761 } 4762 #else 4763 if (rpm) { 4764 rpm->pm_cstate.cs_cache = 0; 4765 if (npm == pmap_kernel()) 4766 ci->ci_pmap_lastuser = NULL; 4767 #ifdef PMAP_CACHE_VIVT 4768 cpu_idcache_wbinv_all(); 4769 #endif 4770 } 4771 #endif 4772 4773 /* No interrupts while we frob the TTB/DACR */ 4774 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4775 #endif /* !ARM_MMU_EXTENDED */ 4776 4777 #ifndef ARM_HAS_VBAR 4778 /* 4779 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4780 * entry corresponding to 'vector_page' in the incoming L1 table 4781 * before switching to it otherwise subsequent interrupts/exceptions 4782 * (including domain faults!) will jump into hyperspace. 4783 */ 4784 if (npm->pm_pl1vec != NULL) { 4785 cpu_tlb_flushID_SE((u_int)vector_page); 4786 cpu_cpwait(); 4787 *npm->pm_pl1vec = npm->pm_l1vec; 4788 PTE_SYNC(npm->pm_pl1vec); 4789 } 4790 #endif 4791 4792 #ifdef ARM_MMU_EXTENDED 4793 /* 4794 * Assume that TTBR1 has only global mappings and TTBR0 only has 4795 * non-global mappings. To prevent speculation from doing evil things 4796 * we disable translation table walks using TTBR0 before setting the 4797 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4798 * walks are reenabled. 4799 */ 4800 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4801 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4802 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4803 arm_isb(); 4804 pmap_tlb_asid_acquire(npm, l); 4805 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4806 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4807 /* 4808 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4809 * been updated. 4810 */ 4811 arm_isb(); 4812 if (npm != pmap_kernel()) { 4813 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4814 } 4815 cpu_cpwait(); 4816 ci->ci_pmap_asid_cur = pai->pai_asid; 4817 #else 4818 cpu_domains(ndacr); 4819 if (npm == pmap_kernel() || npm == rpm) { 4820 /* 4821 * Switching to a kernel thread, or back to the 4822 * same user vmspace as before... Simply update 4823 * the TTB (no TLB flush required) 4824 */ 4825 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4826 cpu_cpwait(); 4827 } else { 4828 /* 4829 * Otherwise, update TTB and flush TLB 4830 */ 4831 cpu_context_switch(npm->pm_l1->l1_physaddr); 4832 if (rpm != NULL) 4833 rpm->pm_cstate.cs_tlb = 0; 4834 } 4835 4836 restore_interrupts(oldirqstate); 4837 #endif /* ARM_MMU_EXTENDED */ 4838 4839 block_userspace_access = 0; 4840 4841 #ifndef ARM_MMU_EXTENDED 4842 all_done: 4843 /* 4844 * The new pmap is resident. Make sure it's marked 4845 * as resident in the cache/TLB. 4846 */ 4847 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4848 if (npm != pmap_kernel()) 4849 ci->ci_pmap_lastuser = npm; 4850 4851 /* The old pmap is not longer active */ 4852 if (opm != npm) { 4853 if (opm != NULL) 4854 opm->pm_activated = false; 4855 4856 /* But the new one is */ 4857 npm->pm_activated = true; 4858 } 4859 #endif 4860 ci->ci_pmap_cur = npm; 4861 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4862 } 4863 4864 void 4865 pmap_deactivate(struct lwp *l) 4866 { 4867 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4868 4869 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4870 4871 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4872 4873 #ifdef ARM_MMU_EXTENDED 4874 kpreempt_disable(); 4875 struct cpu_info * const ci = curcpu(); 4876 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4877 /* 4878 * Disable translation table walks from TTBR0 while no pmap has been 4879 * activated. 4880 */ 4881 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4882 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4883 arm_isb(); 4884 pmap_tlb_asid_deactivate(pm); 4885 cpu_setttb(pmap_kernel()->pm_l1_pa, pai->pai_asid); 4886 ci->ci_pmap_cur = pmap_kernel(); 4887 kpreempt_enable(); 4888 #else 4889 /* 4890 * If the process is exiting, make sure pmap_activate() does 4891 * a full MMU context-switch and cache flush, which we might 4892 * otherwise skip. See PR port-arm/38950. 4893 */ 4894 if (l->l_proc->p_sflag & PS_WEXIT) 4895 curcpu()->ci_lastlwp = NULL; 4896 4897 pm->pm_activated = false; 4898 #endif 4899 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4900 } 4901 4902 void 4903 pmap_update(pmap_t pm) 4904 { 4905 4906 if (pm->pm_remove_all) { 4907 #ifdef ARM_MMU_EXTENDED 4908 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4909 /* 4910 * Finish up the pmap_remove_all() optimisation by flushing 4911 * all our ASIDs. 4912 */ 4913 pmap_tlb_asid_release_all(pm); 4914 #else 4915 /* 4916 * Finish up the pmap_remove_all() optimisation by flushing 4917 * the TLB. 4918 */ 4919 pmap_tlb_flushID(pm); 4920 #endif 4921 pm->pm_remove_all = false; 4922 } 4923 4924 #ifdef ARM_MMU_EXTENDED 4925 4926 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4927 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4928 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4929 PMAP_COUNT(shootdown_ipis); 4930 } 4931 #endif 4932 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4933 #else 4934 if (pmap_is_current(pm)) { 4935 /* 4936 * If we're dealing with a current userland pmap, move its L1 4937 * to the end of the LRU. 4938 */ 4939 if (pm != pmap_kernel()) 4940 pmap_use_l1(pm); 4941 4942 /* 4943 * We can assume we're done with frobbing the cache/tlb for 4944 * now. Make sure any future pmap ops don't skip cache/tlb 4945 * flushes. 4946 */ 4947 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4948 } 4949 #endif 4950 4951 PMAPCOUNT(updates); 4952 4953 /* 4954 * make sure TLB/cache operations have completed. 4955 */ 4956 cpu_cpwait(); 4957 } 4958 4959 void 4960 pmap_remove_all(pmap_t pm) 4961 { 4962 4963 /* 4964 * The vmspace described by this pmap is about to be torn down. 4965 * Until pmap_update() is called, UVM will only make calls 4966 * to pmap_remove(). We can make life much simpler by flushing 4967 * the cache now, and deferring TLB invalidation to pmap_update(). 4968 */ 4969 #ifdef PMAP_CACHE_VIVT 4970 pmap_cache_wbinv_all(pm, PVF_EXEC); 4971 #endif 4972 pm->pm_remove_all = true; 4973 } 4974 4975 /* 4976 * Retire the given physical map from service. 4977 * Should only be called if the map contains no valid mappings. 4978 */ 4979 void 4980 pmap_destroy(pmap_t pm) 4981 { 4982 u_int count; 4983 4984 if (pm == NULL) 4985 return; 4986 4987 if (pm->pm_remove_all) { 4988 pmap_tlb_flushID(pm); 4989 pm->pm_remove_all = false; 4990 } 4991 4992 /* 4993 * Drop reference count 4994 */ 4995 mutex_enter(pm->pm_lock); 4996 count = --pm->pm_obj.uo_refs; 4997 mutex_exit(pm->pm_lock); 4998 if (count > 0) { 4999 #ifndef ARM_MMU_EXTENDED 5000 if (pmap_is_current(pm)) { 5001 if (pm != pmap_kernel()) 5002 pmap_use_l1(pm); 5003 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5004 } 5005 #endif 5006 return; 5007 } 5008 5009 /* 5010 * reference count is zero, free pmap resources and then free pmap. 5011 */ 5012 5013 #ifndef ARM_HAS_VBAR 5014 if (vector_page < KERNEL_BASE) { 5015 KDASSERT(!pmap_is_current(pm)); 5016 5017 /* Remove the vector page mapping */ 5018 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5019 pmap_update(pm); 5020 } 5021 #endif 5022 5023 LIST_REMOVE(pm, pm_list); 5024 5025 pmap_free_l1(pm); 5026 5027 #ifdef ARM_MMU_EXTENDED 5028 #ifdef MULTIPROCESSOR 5029 kcpuset_destroy(pm->pm_active); 5030 kcpuset_destroy(pm->pm_onproc); 5031 #endif 5032 #else 5033 struct cpu_info * const ci = curcpu(); 5034 if (ci->ci_pmap_lastuser == pm) 5035 ci->ci_pmap_lastuser = NULL; 5036 #endif 5037 5038 uvm_obj_destroy(&pm->pm_obj, false); 5039 mutex_destroy(&pm->pm_obj_lock); 5040 pool_cache_put(&pmap_cache, pm); 5041 } 5042 5043 5044 /* 5045 * void pmap_reference(pmap_t pm) 5046 * 5047 * Add a reference to the specified pmap. 5048 */ 5049 void 5050 pmap_reference(pmap_t pm) 5051 { 5052 5053 if (pm == NULL) 5054 return; 5055 5056 #ifndef ARM_MMU_EXTENDED 5057 pmap_use_l1(pm); 5058 #endif 5059 5060 mutex_enter(pm->pm_lock); 5061 pm->pm_obj.uo_refs++; 5062 mutex_exit(pm->pm_lock); 5063 } 5064 5065 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5066 5067 static struct evcnt pmap_prefer_nochange_ev = 5068 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5069 static struct evcnt pmap_prefer_change_ev = 5070 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5071 5072 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5073 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5074 5075 void 5076 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5077 { 5078 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5079 vaddr_t va = *vap; 5080 vaddr_t diff = (hint - va) & mask; 5081 if (diff == 0) { 5082 pmap_prefer_nochange_ev.ev_count++; 5083 } else { 5084 pmap_prefer_change_ev.ev_count++; 5085 if (__predict_false(td)) 5086 va -= mask + 1; 5087 *vap = va + diff; 5088 } 5089 } 5090 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5091 5092 /* 5093 * pmap_zero_page() 5094 * 5095 * Zero a given physical page by mapping it at a page hook point. 5096 * In doing the zero page op, the page we zero is mapped cachable, as with 5097 * StrongARM accesses to non-cached pages are non-burst making writing 5098 * _any_ bulk data very slow. 5099 */ 5100 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5101 void 5102 pmap_zero_page_generic(paddr_t pa) 5103 { 5104 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5105 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5106 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5107 #endif 5108 #if defined(PMAP_CACHE_VIPT) 5109 /* Choose the last page color it had, if any */ 5110 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5111 #else 5112 const vsize_t va_offset = 0; 5113 #endif 5114 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5115 /* 5116 * Is this page mapped at its natural color? 5117 * If we have all of memory mapped, then just convert PA to VA. 5118 */ 5119 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5120 || va_offset == (pa & arm_cache_prefer_mask); 5121 const vaddr_t vdstp = okcolor 5122 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5123 : cpu_cdstp(va_offset); 5124 #else 5125 const bool okcolor = false; 5126 const vaddr_t vdstp = cpu_cdstp(va_offset); 5127 #endif 5128 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5129 5130 5131 #ifdef DEBUG 5132 if (!SLIST_EMPTY(&md->pvh_list)) 5133 panic("pmap_zero_page: page has mappings"); 5134 #endif 5135 5136 KDASSERT((pa & PGOFSET) == 0); 5137 5138 if (!okcolor) { 5139 /* 5140 * Hook in the page, zero it, and purge the cache for that 5141 * zeroed page. Invalidate the TLB as needed. 5142 */ 5143 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5144 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5145 l2pte_set(ptep, npte, 0); 5146 PTE_SYNC(ptep); 5147 cpu_tlb_flushD_SE(vdstp); 5148 cpu_cpwait(); 5149 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5150 && !defined(ARM_MMU_EXTENDED) 5151 /* 5152 * If we are direct-mapped and our color isn't ok, then before 5153 * we bzero the page invalidate its contents from the cache and 5154 * reset the color to its natural color. 5155 */ 5156 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5157 md->pvh_attrs &= ~arm_cache_prefer_mask; 5158 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5159 #endif 5160 } 5161 bzero_page(vdstp); 5162 if (!okcolor) { 5163 /* 5164 * Unmap the page. 5165 */ 5166 l2pte_reset(ptep); 5167 PTE_SYNC(ptep); 5168 cpu_tlb_flushD_SE(vdstp); 5169 #ifdef PMAP_CACHE_VIVT 5170 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5171 #endif 5172 } 5173 #ifdef PMAP_CACHE_VIPT 5174 /* 5175 * This page is now cache resident so it now has a page color. 5176 * Any contents have been obliterated so clear the EXEC flag. 5177 */ 5178 #ifndef ARM_MMU_EXTENDED 5179 if (!pmap_is_page_colored_p(md)) { 5180 PMAPCOUNT(vac_color_new); 5181 md->pvh_attrs |= PVF_COLORED; 5182 } 5183 md->pvh_attrs |= PVF_DIRTY; 5184 #endif 5185 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5186 md->pvh_attrs &= ~PVF_EXEC; 5187 PMAPCOUNT(exec_discarded_zero); 5188 } 5189 #endif 5190 } 5191 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5192 5193 #if ARM_MMU_XSCALE == 1 5194 void 5195 pmap_zero_page_xscale(paddr_t pa) 5196 { 5197 #ifdef DEBUG 5198 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5199 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5200 5201 if (!SLIST_EMPTY(&md->pvh_list)) 5202 panic("pmap_zero_page: page has mappings"); 5203 #endif 5204 5205 KDASSERT((pa & PGOFSET) == 0); 5206 5207 /* 5208 * Hook in the page, zero it, and purge the cache for that 5209 * zeroed page. Invalidate the TLB as needed. 5210 */ 5211 5212 pt_entry_t npte = L2_S_PROTO | pa | 5213 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5214 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5215 l2pte_set(cdst_pte, npte, 0); 5216 PTE_SYNC(cdst_pte); 5217 cpu_tlb_flushD_SE(cdstp); 5218 cpu_cpwait(); 5219 bzero_page(cdstp); 5220 xscale_cache_clean_minidata(); 5221 l2pte_reset(cdst_pte); 5222 PTE_SYNC(cdst_pte); 5223 } 5224 #endif /* ARM_MMU_XSCALE == 1 */ 5225 5226 /* pmap_pageidlezero() 5227 * 5228 * The same as above, except that we assume that the page is not 5229 * mapped. This means we never have to flush the cache first. Called 5230 * from the idle loop. 5231 */ 5232 bool 5233 pmap_pageidlezero(paddr_t pa) 5234 { 5235 bool rv = true; 5236 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5237 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5238 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5239 #endif 5240 #ifdef PMAP_CACHE_VIPT 5241 /* Choose the last page color it had, if any */ 5242 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5243 #else 5244 const vsize_t va_offset = 0; 5245 #endif 5246 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5247 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5248 || va_offset == (pa & arm_cache_prefer_mask); 5249 const vaddr_t vdstp = okcolor 5250 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5251 : cpu_cdstp(va_offset); 5252 #else 5253 const bool okcolor = false; 5254 const vaddr_t vdstp = cpu_cdstp(va_offset); 5255 #endif 5256 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5257 5258 5259 #ifdef DEBUG 5260 if (!SLIST_EMPTY(&md->pvh_list)) 5261 panic("pmap_pageidlezero: page has mappings"); 5262 #endif 5263 5264 KDASSERT((pa & PGOFSET) == 0); 5265 5266 if (!okcolor) { 5267 /* 5268 * Hook in the page, zero it, and purge the cache for that 5269 * zeroed page. Invalidate the TLB as needed. 5270 */ 5271 const pt_entry_t npte = L2_S_PROTO | pa | 5272 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5273 l2pte_set(ptep, npte, 0); 5274 PTE_SYNC(ptep); 5275 cpu_tlb_flushD_SE(vdstp); 5276 cpu_cpwait(); 5277 } 5278 5279 uint64_t *ptr = (uint64_t *)vdstp; 5280 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5281 if (sched_curcpu_runnable_p() != 0) { 5282 /* 5283 * A process has become ready. Abort now, 5284 * so we don't keep it waiting while we 5285 * do slow memory access to finish this 5286 * page. 5287 */ 5288 rv = false; 5289 break; 5290 } 5291 *ptr++ = 0; 5292 } 5293 5294 #ifdef PMAP_CACHE_VIVT 5295 if (rv) 5296 /* 5297 * if we aborted we'll rezero this page again later so don't 5298 * purge it unless we finished it 5299 */ 5300 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5301 #elif defined(PMAP_CACHE_VIPT) 5302 /* 5303 * This page is now cache resident so it now has a page color. 5304 * Any contents have been obliterated so clear the EXEC flag. 5305 */ 5306 #ifndef ARM_MMU_EXTENDED 5307 if (!pmap_is_page_colored_p(md)) { 5308 PMAPCOUNT(vac_color_new); 5309 md->pvh_attrs |= PVF_COLORED; 5310 } 5311 #endif 5312 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5313 md->pvh_attrs &= ~PVF_EXEC; 5314 PMAPCOUNT(exec_discarded_zero); 5315 } 5316 #endif 5317 /* 5318 * Unmap the page. 5319 */ 5320 if (!okcolor) { 5321 l2pte_reset(ptep); 5322 PTE_SYNC(ptep); 5323 cpu_tlb_flushD_SE(vdstp); 5324 } 5325 5326 return rv; 5327 } 5328 5329 /* 5330 * pmap_copy_page() 5331 * 5332 * Copy one physical page into another, by mapping the pages into 5333 * hook points. The same comment regarding cachability as in 5334 * pmap_zero_page also applies here. 5335 */ 5336 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5337 void 5338 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5339 { 5340 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5341 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5342 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5343 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5344 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5345 #endif 5346 #ifdef PMAP_CACHE_VIPT 5347 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5348 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5349 #else 5350 const vsize_t src_va_offset = 0; 5351 const vsize_t dst_va_offset = 0; 5352 #endif 5353 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5354 /* 5355 * Is this page mapped at its natural color? 5356 * If we have all of memory mapped, then just convert PA to VA. 5357 */ 5358 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5359 || src_va_offset == (src & arm_cache_prefer_mask); 5360 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5361 || dst_va_offset == (dst & arm_cache_prefer_mask); 5362 const vaddr_t vsrcp = src_okcolor 5363 ? pmap_direct_mapped_phys(src, &src_okcolor, 5364 cpu_csrcp(src_va_offset)) 5365 : cpu_csrcp(src_va_offset); 5366 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5367 cpu_cdstp(dst_va_offset)); 5368 #else 5369 const bool src_okcolor = false; 5370 const bool dst_okcolor = false; 5371 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5372 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5373 #endif 5374 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5375 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5376 5377 #ifdef DEBUG 5378 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5379 panic("pmap_copy_page: dst page has mappings"); 5380 #endif 5381 5382 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5383 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5384 #endif 5385 KDASSERT((src & PGOFSET) == 0); 5386 KDASSERT((dst & PGOFSET) == 0); 5387 5388 /* 5389 * Clean the source page. Hold the source page's lock for 5390 * the duration of the copy so that no other mappings can 5391 * be created while we have a potentially aliased mapping. 5392 */ 5393 #ifdef PMAP_CACHE_VIVT 5394 pmap_acquire_page_lock(src_md); 5395 (void) pmap_clean_page(src_md, true); 5396 pmap_release_page_lock(src_md); 5397 #endif 5398 5399 /* 5400 * Map the pages into the page hook points, copy them, and purge 5401 * the cache for the appropriate page. Invalidate the TLB 5402 * as required. 5403 */ 5404 if (!src_okcolor) { 5405 const pt_entry_t nsrc_pte = L2_S_PROTO 5406 | src 5407 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5408 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5409 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5410 | pte_l2_s_cache_mode 5411 #endif 5412 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5413 l2pte_set(src_ptep, nsrc_pte, 0); 5414 PTE_SYNC(src_ptep); 5415 cpu_tlb_flushD_SE(vsrcp); 5416 cpu_cpwait(); 5417 } 5418 if (!dst_okcolor) { 5419 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5420 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5421 l2pte_set(dst_ptep, ndst_pte, 0); 5422 PTE_SYNC(dst_ptep); 5423 cpu_tlb_flushD_SE(vdstp); 5424 cpu_cpwait(); 5425 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5426 /* 5427 * If we are direct-mapped and our color isn't ok, then before 5428 * we bcopy to the new page invalidate its contents from the 5429 * cache and reset its color to its natural color. 5430 */ 5431 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5432 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5433 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5434 #endif 5435 } 5436 bcopy_page(vsrcp, vdstp); 5437 #ifdef PMAP_CACHE_VIVT 5438 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5439 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5440 #endif 5441 /* 5442 * Unmap the pages. 5443 */ 5444 if (!src_okcolor) { 5445 l2pte_reset(src_ptep); 5446 PTE_SYNC(src_ptep); 5447 cpu_tlb_flushD_SE(vsrcp); 5448 cpu_cpwait(); 5449 } 5450 if (!dst_okcolor) { 5451 l2pte_reset(dst_ptep); 5452 PTE_SYNC(dst_ptep); 5453 cpu_tlb_flushD_SE(vdstp); 5454 cpu_cpwait(); 5455 } 5456 #ifdef PMAP_CACHE_VIPT 5457 /* 5458 * Now that the destination page is in the cache, mark it as colored. 5459 * If this was an exec page, discard it. 5460 */ 5461 pmap_acquire_page_lock(dst_md); 5462 #ifndef ARM_MMU_EXTENDED 5463 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5464 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5465 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5466 } 5467 if (!pmap_is_page_colored_p(dst_md)) { 5468 PMAPCOUNT(vac_color_new); 5469 dst_md->pvh_attrs |= PVF_COLORED; 5470 } 5471 dst_md->pvh_attrs |= PVF_DIRTY; 5472 #endif 5473 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5474 dst_md->pvh_attrs &= ~PVF_EXEC; 5475 PMAPCOUNT(exec_discarded_copy); 5476 } 5477 pmap_release_page_lock(dst_md); 5478 #endif 5479 } 5480 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5481 5482 #if ARM_MMU_XSCALE == 1 5483 void 5484 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5485 { 5486 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5487 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5488 #ifdef DEBUG 5489 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5490 5491 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5492 panic("pmap_copy_page: dst page has mappings"); 5493 #endif 5494 5495 KDASSERT((src & PGOFSET) == 0); 5496 KDASSERT((dst & PGOFSET) == 0); 5497 5498 /* 5499 * Clean the source page. Hold the source page's lock for 5500 * the duration of the copy so that no other mappings can 5501 * be created while we have a potentially aliased mapping. 5502 */ 5503 #ifdef PMAP_CACHE_VIVT 5504 pmap_acquire_page_lock(src_md); 5505 (void) pmap_clean_page(src_md, true); 5506 pmap_release_page_lock(src_md); 5507 #endif 5508 5509 /* 5510 * Map the pages into the page hook points, copy them, and purge 5511 * the cache for the appropriate page. Invalidate the TLB 5512 * as required. 5513 */ 5514 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5515 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5516 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5517 l2pte_set(csrc_pte, nsrc_pte, 0); 5518 PTE_SYNC(csrc_pte); 5519 5520 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5521 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5522 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5523 l2pte_set(cdst_pte, ndst_pte, 0); 5524 PTE_SYNC(cdst_pte); 5525 5526 cpu_tlb_flushD_SE(csrcp); 5527 cpu_tlb_flushD_SE(cdstp); 5528 cpu_cpwait(); 5529 bcopy_page(csrcp, cdstp); 5530 xscale_cache_clean_minidata(); 5531 l2pte_reset(csrc_pte); 5532 l2pte_reset(cdst_pte); 5533 PTE_SYNC(csrc_pte); 5534 PTE_SYNC(cdst_pte); 5535 } 5536 #endif /* ARM_MMU_XSCALE == 1 */ 5537 5538 /* 5539 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5540 * 5541 * Return the start and end addresses of the kernel's virtual space. 5542 * These values are setup in pmap_bootstrap and are updated as pages 5543 * are allocated. 5544 */ 5545 void 5546 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5547 { 5548 *start = virtual_avail; 5549 *end = virtual_end; 5550 } 5551 5552 /* 5553 * Helper function for pmap_grow_l2_bucket() 5554 */ 5555 static inline int 5556 pmap_grow_map(vaddr_t va, paddr_t *pap) 5557 { 5558 paddr_t pa; 5559 5560 if (uvm.page_init_done == false) { 5561 #ifdef PMAP_STEAL_MEMORY 5562 pv_addr_t pv; 5563 pmap_boot_pagealloc(PAGE_SIZE, 5564 #ifdef PMAP_CACHE_VIPT 5565 arm_cache_prefer_mask, 5566 va & arm_cache_prefer_mask, 5567 #else 5568 0, 0, 5569 #endif 5570 &pv); 5571 pa = pv.pv_pa; 5572 #else 5573 if (uvm_page_physget(&pa) == false) 5574 return (1); 5575 #endif /* PMAP_STEAL_MEMORY */ 5576 } else { 5577 struct vm_page *pg; 5578 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5579 if (pg == NULL) 5580 return (1); 5581 pa = VM_PAGE_TO_PHYS(pg); 5582 /* 5583 * This new page must not have any mappings. Enter it via 5584 * pmap_kenter_pa and let that routine do the hard work. 5585 */ 5586 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5587 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5588 pmap_kenter_pa(va, pa, 5589 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5590 } 5591 5592 if (pap) 5593 *pap = pa; 5594 5595 PMAPCOUNT(pt_mappings); 5596 #ifdef DEBUG 5597 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5598 KDASSERT(l2b != NULL); 5599 5600 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5601 const pt_entry_t opte = *ptep; 5602 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5603 #endif 5604 memset((void *)va, 0, PAGE_SIZE); 5605 return (0); 5606 } 5607 5608 /* 5609 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5610 * used by pmap_growkernel(). 5611 */ 5612 static inline struct l2_bucket * 5613 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5614 { 5615 struct l2_dtable *l2; 5616 struct l2_bucket *l2b; 5617 u_short l1slot; 5618 vaddr_t nva; 5619 5620 l1slot = l1pte_index(va); 5621 5622 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5623 /* 5624 * No mapping at this address, as there is 5625 * no entry in the L1 table. 5626 * Need to allocate a new l2_dtable. 5627 */ 5628 nva = pmap_kernel_l2dtable_kva; 5629 if ((nva & PGOFSET) == 0) { 5630 /* 5631 * Need to allocate a backing page 5632 */ 5633 if (pmap_grow_map(nva, NULL)) 5634 return (NULL); 5635 } 5636 5637 l2 = (struct l2_dtable *)nva; 5638 nva += sizeof(struct l2_dtable); 5639 5640 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5641 /* 5642 * The new l2_dtable straddles a page boundary. 5643 * Map in another page to cover it. 5644 */ 5645 if (pmap_grow_map(nva, NULL)) 5646 return (NULL); 5647 } 5648 5649 pmap_kernel_l2dtable_kva = nva; 5650 5651 /* 5652 * Link it into the parent pmap 5653 */ 5654 pm->pm_l2[L2_IDX(l1slot)] = l2; 5655 } 5656 5657 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5658 5659 /* 5660 * Fetch pointer to the L2 page table associated with the address. 5661 */ 5662 if (l2b->l2b_kva == NULL) { 5663 pt_entry_t *ptep; 5664 5665 /* 5666 * No L2 page table has been allocated. Chances are, this 5667 * is because we just allocated the l2_dtable, above. 5668 */ 5669 nva = pmap_kernel_l2ptp_kva; 5670 ptep = (pt_entry_t *)nva; 5671 if ((nva & PGOFSET) == 0) { 5672 /* 5673 * Need to allocate a backing page 5674 */ 5675 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5676 return (NULL); 5677 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5678 } 5679 5680 l2->l2_occupancy++; 5681 l2b->l2b_kva = ptep; 5682 l2b->l2b_l1slot = l1slot; 5683 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5684 5685 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5686 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5687 } 5688 5689 return (l2b); 5690 } 5691 5692 vaddr_t 5693 pmap_growkernel(vaddr_t maxkvaddr) 5694 { 5695 pmap_t kpm = pmap_kernel(); 5696 #ifndef ARM_MMU_EXTENDED 5697 struct l1_ttable *l1; 5698 #endif 5699 int s; 5700 5701 if (maxkvaddr <= pmap_curmaxkvaddr) 5702 goto out; /* we are OK */ 5703 5704 NPDEBUG(PDB_GROWKERN, 5705 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5706 pmap_curmaxkvaddr, maxkvaddr)); 5707 5708 KDASSERT(maxkvaddr <= virtual_end); 5709 5710 /* 5711 * whoops! we need to add kernel PTPs 5712 */ 5713 5714 s = splhigh(); /* to be safe */ 5715 mutex_enter(kpm->pm_lock); 5716 5717 /* Map 1MB at a time */ 5718 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5719 #ifdef ARM_MMU_EXTENDED 5720 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5721 pd_entry_t *pdep = spdep; 5722 #endif 5723 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5724 #ifdef ARM_MMU_EXTENDED 5725 pdep++, 5726 #endif 5727 l1slot++) { 5728 struct l2_bucket *l2b = 5729 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5730 KASSERT(l2b != NULL); 5731 5732 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5733 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5734 #ifdef ARM_MMU_EXTENDED 5735 l1pte_setone(pdep, npde); 5736 #else 5737 /* Distribute new L1 entry to all other L1s */ 5738 SLIST_FOREACH(l1, &l1_list, l1_link) { 5739 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5740 l1pte_setone(pdep, npde); 5741 PDE_SYNC(pdep); 5742 } 5743 #endif 5744 } 5745 #ifdef ARM_MMU_EXTENDED 5746 PDE_SYNC_RANGE(spdep, pdep - spdep); 5747 #endif 5748 5749 #ifdef PMAP_CACHE_VIVT 5750 /* 5751 * flush out the cache, expensive but growkernel will happen so 5752 * rarely 5753 */ 5754 cpu_dcache_wbinv_all(); 5755 cpu_tlb_flushD(); 5756 cpu_cpwait(); 5757 #endif 5758 5759 mutex_exit(kpm->pm_lock); 5760 splx(s); 5761 5762 out: 5763 return (pmap_curmaxkvaddr); 5764 } 5765 5766 /************************ Utility routines ****************************/ 5767 5768 #ifndef ARM_HAS_VBAR 5769 /* 5770 * vector_page_setprot: 5771 * 5772 * Manipulate the protection of the vector page. 5773 */ 5774 void 5775 vector_page_setprot(int prot) 5776 { 5777 struct l2_bucket *l2b; 5778 pt_entry_t *ptep; 5779 5780 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5781 /* 5782 * If we are using VBAR to use the vectors in the kernel, then it's 5783 * already mapped in the kernel text so no need to anything here. 5784 */ 5785 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5786 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5787 return; 5788 } 5789 #endif 5790 5791 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5792 KASSERT(l2b != NULL); 5793 5794 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5795 5796 const pt_entry_t opte = *ptep; 5797 #ifdef ARM_MMU_EXTENDED 5798 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5799 | L2_S_PROT(PTE_KERNEL, prot); 5800 #else 5801 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5802 | L2_S_PROT(PTE_KERNEL, prot); 5803 #endif 5804 l2pte_set(ptep, npte, opte); 5805 PTE_SYNC(ptep); 5806 cpu_tlb_flushD_SE(vector_page); 5807 cpu_cpwait(); 5808 } 5809 #endif 5810 5811 /* 5812 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5813 * Returns true if the mapping exists, else false. 5814 * 5815 * NOTE: This function is only used by a couple of arm-specific modules. 5816 * It is not safe to take any pmap locks here, since we could be right 5817 * in the middle of debugging the pmap anyway... 5818 * 5819 * It is possible for this routine to return false even though a valid 5820 * mapping does exist. This is because we don't lock, so the metadata 5821 * state may be inconsistent. 5822 * 5823 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5824 * a "section" mapping. 5825 */ 5826 bool 5827 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5828 { 5829 struct l2_dtable *l2; 5830 pd_entry_t *pdep, pde; 5831 pt_entry_t *ptep; 5832 u_short l1slot; 5833 5834 if (pm->pm_l1 == NULL) 5835 return false; 5836 5837 l1slot = l1pte_index(va); 5838 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5839 pde = *pdep; 5840 5841 if (l1pte_section_p(pde)) { 5842 *ptp = NULL; 5843 return true; 5844 } 5845 5846 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5847 if (l2 == NULL || 5848 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5849 return false; 5850 } 5851 5852 *ptp = &ptep[l2pte_index(va)]; 5853 return true; 5854 } 5855 5856 bool 5857 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5858 { 5859 5860 if (pm->pm_l1 == NULL) 5861 return false; 5862 5863 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5864 5865 return true; 5866 } 5867 5868 /************************ Bootstrapping routines ****************************/ 5869 5870 #ifndef ARM_MMU_EXTENDED 5871 static void 5872 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5873 { 5874 int i; 5875 5876 l1->l1_kva = l1pt; 5877 l1->l1_domain_use_count = 0; 5878 l1->l1_domain_first = 0; 5879 5880 for (i = 0; i < PMAP_DOMAINS; i++) 5881 l1->l1_domain_free[i] = i + 1; 5882 5883 /* 5884 * Copy the kernel's L1 entries to each new L1. 5885 */ 5886 if (pmap_initialized) 5887 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5888 5889 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5890 &l1->l1_physaddr) == false) 5891 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5892 5893 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5894 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5895 } 5896 #endif /* !ARM_MMU_EXTENDED */ 5897 5898 /* 5899 * pmap_bootstrap() is called from the board-specific initarm() routine 5900 * once the kernel L1/L2 descriptors tables have been set up. 5901 * 5902 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5903 * spread over a number of disparate files/functions. 5904 * 5905 * We are passed the following parameters 5906 * - kernel_l1pt 5907 * This is a pointer to the base of the kernel's L1 translation table. 5908 * - vstart 5909 * 1MB-aligned start of managed kernel virtual memory. 5910 * - vend 5911 * 1MB-aligned end of managed kernel virtual memory. 5912 * 5913 * We use the first parameter to build the metadata (struct l1_ttable and 5914 * struct l2_dtable) necessary to track kernel mappings. 5915 */ 5916 #define PMAP_STATIC_L2_SIZE 16 5917 void 5918 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5919 { 5920 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5921 #ifndef ARM_MMU_EXTENDED 5922 static struct l1_ttable static_l1; 5923 struct l1_ttable *l1 = &static_l1; 5924 #endif 5925 struct l2_dtable *l2; 5926 struct l2_bucket *l2b; 5927 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5928 pmap_t pm = pmap_kernel(); 5929 pt_entry_t *ptep; 5930 paddr_t pa; 5931 vsize_t size; 5932 int nptes, l2idx, l2next = 0; 5933 5934 #ifdef ARM_MMU_EXTENDED 5935 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5936 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5937 #endif 5938 5939 #ifdef VERBOSE_INIT_ARM 5940 printf("kpm "); 5941 #endif 5942 /* 5943 * Initialise the kernel pmap object 5944 */ 5945 curcpu()->ci_pmap_cur = pm; 5946 #ifdef ARM_MMU_EXTENDED 5947 pm->pm_l1 = l1pt; 5948 pm->pm_l1_pa = kernel_l1pt.pv_pa; 5949 #ifdef VERBOSE_INIT_ARM 5950 printf("tlb0 "); 5951 #endif 5952 pmap_tlb_info_init(&pmap_tlb0_info); 5953 #ifdef MULTIPROCESSOR 5954 #ifdef VERBOSE_INIT_ARM 5955 printf("kcpusets "); 5956 #endif 5957 pm->pm_onproc = kcpuset_running; 5958 pm->pm_active = kcpuset_running; 5959 #endif 5960 #else 5961 pm->pm_l1 = l1; 5962 #endif 5963 5964 #ifdef VERBOSE_INIT_ARM 5965 printf("locks "); 5966 #endif 5967 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5968 if (arm_cache_prefer_mask != 0) { 5969 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 5970 } else { 5971 #endif 5972 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 5973 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5974 } 5975 #endif 5976 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5977 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5978 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5979 5980 #ifdef VERBOSE_INIT_ARM 5981 printf("l1pt "); 5982 #endif 5983 /* 5984 * Scan the L1 translation table created by initarm() and create 5985 * the required metadata for all valid mappings found in it. 5986 */ 5987 for (size_t l1slot = 0; 5988 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 5989 l1slot++) { 5990 pd_entry_t pde = l1pt[l1slot]; 5991 5992 /* 5993 * We're only interested in Coarse mappings. 5994 * pmap_extract() can deal with section mappings without 5995 * recourse to checking L2 metadata. 5996 */ 5997 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5998 continue; 5999 6000 /* 6001 * Lookup the KVA of this L2 descriptor table 6002 */ 6003 pa = l1pte_pa(pde); 6004 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6005 if (ptep == NULL) { 6006 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6007 (u_int)l1slot << L1_S_SHIFT, pa); 6008 } 6009 6010 /* 6011 * Fetch the associated L2 metadata structure. 6012 * Allocate a new one if necessary. 6013 */ 6014 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6015 if (l2next == PMAP_STATIC_L2_SIZE) 6016 panic("pmap_bootstrap: out of static L2s"); 6017 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6018 } 6019 6020 /* 6021 * One more L1 slot tracked... 6022 */ 6023 l2->l2_occupancy++; 6024 6025 /* 6026 * Fill in the details of the L2 descriptor in the 6027 * appropriate bucket. 6028 */ 6029 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6030 l2b->l2b_kva = ptep; 6031 l2b->l2b_pa = pa; 6032 l2b->l2b_l1slot = l1slot; 6033 6034 /* 6035 * Establish an initial occupancy count for this descriptor 6036 */ 6037 for (l2idx = 0; 6038 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6039 l2idx++) { 6040 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6041 l2b->l2b_occupancy++; 6042 } 6043 } 6044 6045 /* 6046 * Make sure the descriptor itself has the correct cache mode. 6047 * If not, fix it, but whine about the problem. Port-meisters 6048 * should consider this a clue to fix up their initarm() 6049 * function. :) 6050 */ 6051 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6052 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6053 "L2 pte @ %p\n", ptep); 6054 } 6055 } 6056 6057 #ifdef VERBOSE_INIT_ARM 6058 printf("cache(l1pt) "); 6059 #endif 6060 /* 6061 * Ensure the primary (kernel) L1 has the correct cache mode for 6062 * a page table. Bitch if it is not correctly set. 6063 */ 6064 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6065 L1_TABLE_SIZE / L2_S_SIZE)) { 6066 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6067 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6068 } 6069 6070 #ifdef PMAP_CACHE_VIVT 6071 cpu_dcache_wbinv_all(); 6072 cpu_tlb_flushID(); 6073 cpu_cpwait(); 6074 #endif 6075 6076 /* 6077 * now we allocate the "special" VAs which are used for tmp mappings 6078 * by the pmap (and other modules). we allocate the VAs by advancing 6079 * virtual_avail (note that there are no pages mapped at these VAs). 6080 * 6081 * Managed KVM space start from wherever initarm() tells us. 6082 */ 6083 virtual_avail = vstart; 6084 virtual_end = vend; 6085 6086 #ifdef VERBOSE_INIT_ARM 6087 printf("specials "); 6088 #endif 6089 #ifdef PMAP_CACHE_VIPT 6090 /* 6091 * If we have a VIPT cache, we need one page/pte per possible alias 6092 * page so we won't violate cache aliasing rules. 6093 */ 6094 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6095 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6096 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6097 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6098 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6099 } 6100 #else 6101 nptes = PAGE_SIZE / L2_S_SIZE; 6102 #endif 6103 #ifdef MULTIPROCESSOR 6104 cnptes = nptes; 6105 nptes *= arm_cpu_max; 6106 #endif 6107 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6108 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6109 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6110 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6111 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6112 if (msgbufaddr == NULL) { 6113 pmap_alloc_specials(&virtual_avail, 6114 round_page(MSGBUFSIZE) / PAGE_SIZE, 6115 (void *)&msgbufaddr, NULL); 6116 } 6117 6118 /* 6119 * Allocate a range of kernel virtual address space to be used 6120 * for L2 descriptor tables and metadata allocation in 6121 * pmap_growkernel(). 6122 */ 6123 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6124 pmap_alloc_specials(&virtual_avail, 6125 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6126 &pmap_kernel_l2ptp_kva, NULL); 6127 6128 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6129 pmap_alloc_specials(&virtual_avail, 6130 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6131 &pmap_kernel_l2dtable_kva, NULL); 6132 6133 #ifndef ARM_MMU_EXTENDED 6134 /* 6135 * init the static-global locks and global pmap list. 6136 */ 6137 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6138 6139 /* 6140 * We can now initialise the first L1's metadata. 6141 */ 6142 SLIST_INIT(&l1_list); 6143 TAILQ_INIT(&l1_lru_list); 6144 pmap_init_l1(l1, l1pt); 6145 #endif /* ARM_MMU_EXTENDED */ 6146 6147 #ifndef ARM_HAS_VBAR 6148 /* Set up vector page L1 details, if necessary */ 6149 if (vector_page < KERNEL_BASE) { 6150 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6151 l2b = pmap_get_l2_bucket(pm, vector_page); 6152 KDASSERT(l2b != NULL); 6153 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6154 L1_C_DOM(pmap_domain(pm)); 6155 } else 6156 pm->pm_pl1vec = NULL; 6157 #endif 6158 6159 #ifdef VERBOSE_INIT_ARM 6160 printf("pools "); 6161 #endif 6162 /* 6163 * Initialize the pmap cache 6164 */ 6165 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6166 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6167 LIST_INIT(&pmap_pmaps); 6168 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6169 6170 /* 6171 * Initialize the pv pool. 6172 */ 6173 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6174 &pmap_bootstrap_pv_allocator, IPL_NONE); 6175 6176 /* 6177 * Initialize the L2 dtable pool and cache. 6178 */ 6179 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6180 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6181 6182 /* 6183 * Initialise the L2 descriptor table pool and cache 6184 */ 6185 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6186 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6187 pmap_l2ptp_ctor, NULL, NULL); 6188 6189 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6190 6191 cpu_dcache_wbinv_all(); 6192 } 6193 6194 static bool 6195 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6196 { 6197 #ifdef ARM_MMU_EXTENDED 6198 return false; 6199 #else 6200 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6201 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6202 return false; 6203 6204 const vaddr_t eva = va + nptes * PAGE_SIZE; 6205 int rv = 0; 6206 6207 while (va < eva) { 6208 /* 6209 * Make sure the descriptor itself has the correct cache mode 6210 */ 6211 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6212 pd_entry_t pde = *pdep; 6213 6214 if (l1pte_section_p(pde)) { 6215 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6216 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6217 *pdep = (pde & ~L1_S_CACHE_MASK) | 6218 pte_l1_s_cache_mode_pt; 6219 PDE_SYNC(pdep); 6220 cpu_dcache_wbinv_range((vaddr_t)pdep, 6221 sizeof(*pdep)); 6222 rv = 1; 6223 } 6224 return rv; 6225 } 6226 vaddr_t pa = l1pte_pa(pde); 6227 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6228 if (ptep == NULL) 6229 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6230 6231 ptep += l2pte_index(va); 6232 const pt_entry_t opte = *ptep; 6233 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6234 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6235 | pte_l2_s_cache_mode_pt; 6236 l2pte_set(ptep, npte, opte); 6237 PTE_SYNC(ptep); 6238 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6239 rv = 1; 6240 } 6241 va += PAGE_SIZE; 6242 } 6243 6244 return (rv); 6245 #endif 6246 } 6247 6248 static void 6249 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6250 { 6251 vaddr_t va = *availp; 6252 struct l2_bucket *l2b; 6253 6254 if (ptep) { 6255 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6256 if (l2b == NULL) 6257 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6258 6259 if (ptep) 6260 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6261 } 6262 6263 *vap = va; 6264 *availp = va + (PAGE_SIZE * pages); 6265 } 6266 6267 void 6268 pmap_init(void) 6269 { 6270 6271 /* 6272 * Set the available memory vars - These do not map to real memory 6273 * addresses and cannot as the physical memory is fragmented. 6274 * They are used by ps for %mem calculations. 6275 * One could argue whether this should be the entire memory or just 6276 * the memory that is useable in a user process. 6277 */ 6278 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6279 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6280 6281 /* 6282 * Now we need to free enough pv_entry structures to allow us to get 6283 * the kmem_map/kmem_object allocated and inited (done after this 6284 * function is finished). to do this we allocate one bootstrap page out 6285 * of kernel_map and use it to provide an initial pool of pv_entry 6286 * structures. we never free this page. 6287 */ 6288 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6289 6290 #ifdef ARM_MMU_EXTENDED 6291 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6292 #endif 6293 6294 pmap_initialized = true; 6295 } 6296 6297 static vaddr_t last_bootstrap_page = 0; 6298 static void *free_bootstrap_pages = NULL; 6299 6300 static void * 6301 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6302 { 6303 extern void *pool_page_alloc(struct pool *, int); 6304 vaddr_t new_page; 6305 void *rv; 6306 6307 if (pmap_initialized) 6308 return (pool_page_alloc(pp, flags)); 6309 6310 if (free_bootstrap_pages) { 6311 rv = free_bootstrap_pages; 6312 free_bootstrap_pages = *((void **)rv); 6313 return (rv); 6314 } 6315 6316 KASSERT(kernel_map != NULL); 6317 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6318 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6319 6320 KASSERT(new_page > last_bootstrap_page); 6321 last_bootstrap_page = new_page; 6322 return ((void *)new_page); 6323 } 6324 6325 static void 6326 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6327 { 6328 extern void pool_page_free(struct pool *, void *); 6329 6330 if ((vaddr_t)v <= last_bootstrap_page) { 6331 *((void **)v) = free_bootstrap_pages; 6332 free_bootstrap_pages = v; 6333 return; 6334 } 6335 6336 if (pmap_initialized) { 6337 pool_page_free(pp, v); 6338 return; 6339 } 6340 } 6341 6342 /* 6343 * pmap_postinit() 6344 * 6345 * This routine is called after the vm and kmem subsystems have been 6346 * initialised. This allows the pmap code to perform any initialisation 6347 * that can only be done one the memory allocation is in place. 6348 */ 6349 void 6350 pmap_postinit(void) 6351 { 6352 #ifndef ARM_MMU_EXTENDED 6353 extern paddr_t physical_start, physical_end; 6354 struct l1_ttable *l1; 6355 struct pglist plist; 6356 struct vm_page *m; 6357 pd_entry_t *pdep; 6358 vaddr_t va, eva; 6359 u_int loop, needed; 6360 int error; 6361 #endif 6362 6363 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6364 pool_cache_setlowat(&pmap_l2dtable_cache, 6365 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6366 6367 #ifndef ARM_MMU_EXTENDED 6368 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6369 needed -= 1; 6370 6371 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6372 6373 for (loop = 0; loop < needed; loop++, l1++) { 6374 /* Allocate a L1 page table */ 6375 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6376 if (va == 0) 6377 panic("Cannot allocate L1 KVM"); 6378 6379 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6380 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6381 if (error) 6382 panic("Cannot allocate L1 physical pages"); 6383 6384 m = TAILQ_FIRST(&plist); 6385 eva = va + L1_TABLE_SIZE; 6386 pdep = (pd_entry_t *)va; 6387 6388 while (m && va < eva) { 6389 paddr_t pa = VM_PAGE_TO_PHYS(m); 6390 6391 pmap_kenter_pa(va, pa, 6392 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6393 6394 va += PAGE_SIZE; 6395 m = TAILQ_NEXT(m, pageq.queue); 6396 } 6397 6398 #ifdef DIAGNOSTIC 6399 if (m) 6400 panic("pmap_alloc_l1pt: pglist not empty"); 6401 #endif /* DIAGNOSTIC */ 6402 6403 pmap_init_l1(l1, pdep); 6404 } 6405 6406 #ifdef DEBUG 6407 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6408 needed); 6409 #endif 6410 #endif /* !ARM_MMU_EXTENDED */ 6411 } 6412 6413 /* 6414 * Note that the following routines are used by board-specific initialisation 6415 * code to configure the initial kernel page tables. 6416 * 6417 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6418 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6419 * behaviour of the old pmap, and provides an easy migration path for 6420 * initial bring-up of the new pmap on existing ports. Fortunately, 6421 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6422 * will be deprecated. 6423 * 6424 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6425 * tables. 6426 */ 6427 6428 /* 6429 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6430 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6431 * find them as necessary. 6432 * 6433 * Note that the data on this list MUST remain valid after initarm() returns, 6434 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6435 */ 6436 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6437 6438 static vaddr_t 6439 kernel_pt_lookup(paddr_t pa) 6440 { 6441 pv_addr_t *pv; 6442 6443 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6444 if (pv->pv_pa == (pa & ~PGOFSET)) 6445 return (pv->pv_va | (pa & PGOFSET)); 6446 } 6447 return (0); 6448 } 6449 6450 /* 6451 * pmap_map_section: 6452 * 6453 * Create a single section mapping. 6454 */ 6455 void 6456 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6457 { 6458 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6459 const size_t l1slot = l1pte_index(va); 6460 pd_entry_t fl; 6461 6462 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6463 6464 switch (cache) { 6465 case PTE_NOCACHE: 6466 default: 6467 fl = 0; 6468 break; 6469 6470 case PTE_CACHE: 6471 fl = pte_l1_s_cache_mode; 6472 break; 6473 6474 case PTE_PAGETABLE: 6475 fl = pte_l1_s_cache_mode_pt; 6476 break; 6477 } 6478 6479 const pd_entry_t npde = L1_S_PROTO | pa | 6480 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6481 l1pte_setone(pdep + l1slot, npde); 6482 PDE_SYNC(pdep + l1slot); 6483 } 6484 6485 /* 6486 * pmap_map_entry: 6487 * 6488 * Create a single page mapping. 6489 */ 6490 void 6491 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6492 { 6493 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6494 const size_t l1slot = l1pte_index(va); 6495 pt_entry_t npte; 6496 pt_entry_t *ptep; 6497 6498 KASSERT(((va | pa) & PGOFSET) == 0); 6499 6500 switch (cache) { 6501 case PTE_NOCACHE: 6502 default: 6503 npte = 0; 6504 break; 6505 6506 case PTE_CACHE: 6507 npte = pte_l2_s_cache_mode; 6508 break; 6509 6510 case PTE_PAGETABLE: 6511 npte = pte_l2_s_cache_mode_pt; 6512 break; 6513 } 6514 6515 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6516 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6517 6518 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6519 if (ptep == NULL) 6520 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6521 6522 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6523 #ifdef ARM_MMU_EXTENDED 6524 if (prot & VM_PROT_EXECUTE) { 6525 npte &= ~L2_XS_XN; 6526 } 6527 #endif 6528 ptep += l2pte_index(va); 6529 l2pte_set(ptep, npte, 0); 6530 PTE_SYNC(ptep); 6531 } 6532 6533 /* 6534 * pmap_link_l2pt: 6535 * 6536 * Link the L2 page table specified by "l2pv" into the L1 6537 * page table at the slot for "va". 6538 */ 6539 void 6540 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6541 { 6542 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6543 6544 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6545 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6546 6547 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6548 | l2pv->pv_pa; 6549 6550 l1pte_set(pdep, npde); 6551 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6552 6553 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6554 } 6555 6556 /* 6557 * pmap_map_chunk: 6558 * 6559 * Map a chunk of memory using the most efficient mappings 6560 * possible (section, large page, small page) into the 6561 * provided L1 and L2 tables at the specified virtual address. 6562 */ 6563 vsize_t 6564 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6565 int prot, int cache) 6566 { 6567 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6568 pt_entry_t f1, f2s, f2l; 6569 vsize_t resid; 6570 6571 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6572 6573 if (l1pt == 0) 6574 panic("pmap_map_chunk: no L1 table provided"); 6575 6576 #ifdef VERBOSE_INIT_ARM 6577 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6578 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6579 #endif 6580 6581 switch (cache) { 6582 case PTE_NOCACHE: 6583 default: 6584 f1 = 0; 6585 f2l = 0; 6586 f2s = 0; 6587 break; 6588 6589 case PTE_CACHE: 6590 f1 = pte_l1_s_cache_mode; 6591 f2l = pte_l2_l_cache_mode; 6592 f2s = pte_l2_s_cache_mode; 6593 break; 6594 6595 case PTE_PAGETABLE: 6596 f1 = pte_l1_s_cache_mode_pt; 6597 f2l = pte_l2_l_cache_mode_pt; 6598 f2s = pte_l2_s_cache_mode_pt; 6599 break; 6600 } 6601 6602 size = resid; 6603 6604 while (resid > 0) { 6605 const size_t l1slot = l1pte_index(va); 6606 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6607 /* See if we can use a supersection mapping. */ 6608 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6609 /* Supersection are always domain 0 */ 6610 const pd_entry_t npde = L1_SS_PROTO | pa 6611 #ifdef ARM_MMU_EXTENDED_XXX 6612 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6613 #endif 6614 #ifdef ARM_MMU_EXTENDED 6615 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6616 #endif 6617 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6618 #ifdef VERBOSE_INIT_ARM 6619 printf("sS"); 6620 #endif 6621 l1pte_set(&pdep[l1slot], npde); 6622 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6623 va += L1_SS_SIZE; 6624 pa += L1_SS_SIZE; 6625 resid -= L1_SS_SIZE; 6626 continue; 6627 } 6628 #endif 6629 /* See if we can use a section mapping. */ 6630 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6631 const pd_entry_t npde = L1_S_PROTO | pa 6632 #ifdef ARM_MMU_EXTENDED_XXX 6633 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6634 #endif 6635 #ifdef ARM_MMU_EXTENDED 6636 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6637 #endif 6638 | L1_S_PROT(PTE_KERNEL, prot) | f1 6639 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6640 #ifdef VERBOSE_INIT_ARM 6641 printf("S"); 6642 #endif 6643 l1pte_set(&pdep[l1slot], npde); 6644 PDE_SYNC(&pdep[l1slot]); 6645 va += L1_S_SIZE; 6646 pa += L1_S_SIZE; 6647 resid -= L1_S_SIZE; 6648 continue; 6649 } 6650 6651 /* 6652 * Ok, we're going to use an L2 table. Make sure 6653 * one is actually in the corresponding L1 slot 6654 * for the current VA. 6655 */ 6656 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6657 panic("%s: no L2 table for VA %#lx", __func__, va); 6658 6659 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6660 if (ptep == NULL) 6661 panic("%s: can't find L2 table for VA %#lx", __func__, 6662 va); 6663 6664 ptep += l2pte_index(va); 6665 6666 /* See if we can use a L2 large page mapping. */ 6667 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6668 const pt_entry_t npte = L2_L_PROTO | pa 6669 #ifdef ARM_MMU_EXTENDED_XXX 6670 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6671 #endif 6672 #ifdef ARM_MMU_EXTENDED 6673 | (va & 0x80000000 ? 0 : L2_XS_nG) 6674 #endif 6675 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6676 #ifdef VERBOSE_INIT_ARM 6677 printf("L"); 6678 #endif 6679 l2pte_set(ptep, npte, 0); 6680 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6681 va += L2_L_SIZE; 6682 pa += L2_L_SIZE; 6683 resid -= L2_L_SIZE; 6684 continue; 6685 } 6686 6687 /* Use a small page mapping. */ 6688 #ifdef VERBOSE_INIT_ARM 6689 printf("P"); 6690 #endif 6691 const pt_entry_t npte = L2_S_PROTO | pa 6692 #ifdef ARM_MMU_EXTENDED_XXX 6693 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6694 #endif 6695 #ifdef ARM_MMU_EXTENDED 6696 | (va & 0x80000000 ? 0 : L2_XS_nG) 6697 #endif 6698 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6699 l2pte_set(ptep, npte, 0); 6700 PTE_SYNC(ptep); 6701 va += PAGE_SIZE; 6702 pa += PAGE_SIZE; 6703 resid -= PAGE_SIZE; 6704 } 6705 #ifdef VERBOSE_INIT_ARM 6706 printf("\n"); 6707 #endif 6708 return (size); 6709 } 6710 6711 /********************** Static device map routines ***************************/ 6712 6713 static const struct pmap_devmap *pmap_devmap_table; 6714 6715 /* 6716 * Register the devmap table. This is provided in case early console 6717 * initialization needs to register mappings created by bootstrap code 6718 * before pmap_devmap_bootstrap() is called. 6719 */ 6720 void 6721 pmap_devmap_register(const struct pmap_devmap *table) 6722 { 6723 6724 pmap_devmap_table = table; 6725 } 6726 6727 /* 6728 * Map all of the static regions in the devmap table, and remember 6729 * the devmap table so other parts of the kernel can look up entries 6730 * later. 6731 */ 6732 void 6733 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6734 { 6735 int i; 6736 6737 pmap_devmap_table = table; 6738 6739 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6740 #ifdef VERBOSE_INIT_ARM 6741 printf("devmap: %08lx -> %08lx @ %08lx\n", 6742 pmap_devmap_table[i].pd_pa, 6743 pmap_devmap_table[i].pd_pa + 6744 pmap_devmap_table[i].pd_size - 1, 6745 pmap_devmap_table[i].pd_va); 6746 #endif 6747 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6748 pmap_devmap_table[i].pd_pa, 6749 pmap_devmap_table[i].pd_size, 6750 pmap_devmap_table[i].pd_prot, 6751 pmap_devmap_table[i].pd_cache); 6752 } 6753 } 6754 6755 const struct pmap_devmap * 6756 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6757 { 6758 uint64_t endpa; 6759 int i; 6760 6761 if (pmap_devmap_table == NULL) 6762 return (NULL); 6763 6764 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6765 6766 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6767 if (pa >= pmap_devmap_table[i].pd_pa && 6768 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6769 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6770 return (&pmap_devmap_table[i]); 6771 } 6772 6773 return (NULL); 6774 } 6775 6776 const struct pmap_devmap * 6777 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6778 { 6779 int i; 6780 6781 if (pmap_devmap_table == NULL) 6782 return (NULL); 6783 6784 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6785 if (va >= pmap_devmap_table[i].pd_va && 6786 va + size - 1 <= pmap_devmap_table[i].pd_va + 6787 pmap_devmap_table[i].pd_size - 1) 6788 return (&pmap_devmap_table[i]); 6789 } 6790 6791 return (NULL); 6792 } 6793 6794 /********************** PTE initialization routines **************************/ 6795 6796 /* 6797 * These routines are called when the CPU type is identified to set up 6798 * the PTE prototypes, cache modes, etc. 6799 * 6800 * The variables are always here, just in case modules need to reference 6801 * them (though, they shouldn't). 6802 */ 6803 6804 pt_entry_t pte_l1_s_cache_mode; 6805 pt_entry_t pte_l1_s_wc_mode; 6806 pt_entry_t pte_l1_s_cache_mode_pt; 6807 pt_entry_t pte_l1_s_cache_mask; 6808 6809 pt_entry_t pte_l2_l_cache_mode; 6810 pt_entry_t pte_l2_l_wc_mode; 6811 pt_entry_t pte_l2_l_cache_mode_pt; 6812 pt_entry_t pte_l2_l_cache_mask; 6813 6814 pt_entry_t pte_l2_s_cache_mode; 6815 pt_entry_t pte_l2_s_wc_mode; 6816 pt_entry_t pte_l2_s_cache_mode_pt; 6817 pt_entry_t pte_l2_s_cache_mask; 6818 6819 pt_entry_t pte_l1_s_prot_u; 6820 pt_entry_t pte_l1_s_prot_w; 6821 pt_entry_t pte_l1_s_prot_ro; 6822 pt_entry_t pte_l1_s_prot_mask; 6823 6824 pt_entry_t pte_l2_s_prot_u; 6825 pt_entry_t pte_l2_s_prot_w; 6826 pt_entry_t pte_l2_s_prot_ro; 6827 pt_entry_t pte_l2_s_prot_mask; 6828 6829 pt_entry_t pte_l2_l_prot_u; 6830 pt_entry_t pte_l2_l_prot_w; 6831 pt_entry_t pte_l2_l_prot_ro; 6832 pt_entry_t pte_l2_l_prot_mask; 6833 6834 pt_entry_t pte_l1_ss_proto; 6835 pt_entry_t pte_l1_s_proto; 6836 pt_entry_t pte_l1_c_proto; 6837 pt_entry_t pte_l2_s_proto; 6838 6839 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6840 void (*pmap_zero_page_func)(paddr_t); 6841 6842 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6843 void 6844 pmap_pte_init_generic(void) 6845 { 6846 6847 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6848 pte_l1_s_wc_mode = L1_S_B; 6849 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6850 6851 pte_l2_l_cache_mode = L2_B|L2_C; 6852 pte_l2_l_wc_mode = L2_B; 6853 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6854 6855 pte_l2_s_cache_mode = L2_B|L2_C; 6856 pte_l2_s_wc_mode = L2_B; 6857 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6858 6859 /* 6860 * If we have a write-through cache, set B and C. If 6861 * we have a write-back cache, then we assume setting 6862 * only C will make those pages write-through (except for those 6863 * Cortex CPUs which can read the L1 caches). 6864 */ 6865 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6866 #if ARM_MMU_V7 > 0 6867 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6868 #endif 6869 #if ARM_MMU_V6 > 0 6870 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6871 #endif 6872 || false) { 6873 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6874 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6875 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6876 } else { 6877 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6878 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6879 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6880 } 6881 6882 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6883 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6884 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6885 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6886 6887 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6888 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6889 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6890 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6891 6892 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6893 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6894 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6895 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6896 6897 pte_l1_ss_proto = L1_SS_PROTO_generic; 6898 pte_l1_s_proto = L1_S_PROTO_generic; 6899 pte_l1_c_proto = L1_C_PROTO_generic; 6900 pte_l2_s_proto = L2_S_PROTO_generic; 6901 6902 pmap_copy_page_func = pmap_copy_page_generic; 6903 pmap_zero_page_func = pmap_zero_page_generic; 6904 } 6905 6906 #if defined(CPU_ARM8) 6907 void 6908 pmap_pte_init_arm8(void) 6909 { 6910 6911 /* 6912 * ARM8 is compatible with generic, but we need to use 6913 * the page tables uncached. 6914 */ 6915 pmap_pte_init_generic(); 6916 6917 pte_l1_s_cache_mode_pt = 0; 6918 pte_l2_l_cache_mode_pt = 0; 6919 pte_l2_s_cache_mode_pt = 0; 6920 } 6921 #endif /* CPU_ARM8 */ 6922 6923 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6924 void 6925 pmap_pte_init_arm9(void) 6926 { 6927 6928 /* 6929 * ARM9 is compatible with generic, but we want to use 6930 * write-through caching for now. 6931 */ 6932 pmap_pte_init_generic(); 6933 6934 pte_l1_s_cache_mode = L1_S_C; 6935 pte_l2_l_cache_mode = L2_C; 6936 pte_l2_s_cache_mode = L2_C; 6937 6938 pte_l1_s_wc_mode = L1_S_B; 6939 pte_l2_l_wc_mode = L2_B; 6940 pte_l2_s_wc_mode = L2_B; 6941 6942 pte_l1_s_cache_mode_pt = L1_S_C; 6943 pte_l2_l_cache_mode_pt = L2_C; 6944 pte_l2_s_cache_mode_pt = L2_C; 6945 } 6946 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6947 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6948 6949 #if defined(CPU_ARM10) 6950 void 6951 pmap_pte_init_arm10(void) 6952 { 6953 6954 /* 6955 * ARM10 is compatible with generic, but we want to use 6956 * write-through caching for now. 6957 */ 6958 pmap_pte_init_generic(); 6959 6960 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6961 pte_l2_l_cache_mode = L2_B | L2_C; 6962 pte_l2_s_cache_mode = L2_B | L2_C; 6963 6964 pte_l1_s_cache_mode = L1_S_B; 6965 pte_l2_l_cache_mode = L2_B; 6966 pte_l2_s_cache_mode = L2_B; 6967 6968 pte_l1_s_cache_mode_pt = L1_S_C; 6969 pte_l2_l_cache_mode_pt = L2_C; 6970 pte_l2_s_cache_mode_pt = L2_C; 6971 6972 } 6973 #endif /* CPU_ARM10 */ 6974 6975 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6976 void 6977 pmap_pte_init_arm11(void) 6978 { 6979 6980 /* 6981 * ARM11 is compatible with generic, but we want to use 6982 * write-through caching for now. 6983 */ 6984 pmap_pte_init_generic(); 6985 6986 pte_l1_s_cache_mode = L1_S_C; 6987 pte_l2_l_cache_mode = L2_C; 6988 pte_l2_s_cache_mode = L2_C; 6989 6990 pte_l1_s_wc_mode = L1_S_B; 6991 pte_l2_l_wc_mode = L2_B; 6992 pte_l2_s_wc_mode = L2_B; 6993 6994 pte_l1_s_cache_mode_pt = L1_S_C; 6995 pte_l2_l_cache_mode_pt = L2_C; 6996 pte_l2_s_cache_mode_pt = L2_C; 6997 } 6998 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6999 7000 #if ARM_MMU_SA1 == 1 7001 void 7002 pmap_pte_init_sa1(void) 7003 { 7004 7005 /* 7006 * The StrongARM SA-1 cache does not have a write-through 7007 * mode. So, do the generic initialization, then reset 7008 * the page table cache mode to B=1,C=1, and note that 7009 * the PTEs need to be sync'd. 7010 */ 7011 pmap_pte_init_generic(); 7012 7013 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7014 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7015 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7016 7017 pmap_needs_pte_sync = 1; 7018 } 7019 #endif /* ARM_MMU_SA1 == 1*/ 7020 7021 #if ARM_MMU_XSCALE == 1 7022 #if (ARM_NMMUS > 1) 7023 static u_int xscale_use_minidata; 7024 #endif 7025 7026 void 7027 pmap_pte_init_xscale(void) 7028 { 7029 uint32_t auxctl; 7030 int write_through = 0; 7031 7032 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7033 pte_l1_s_wc_mode = L1_S_B; 7034 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7035 7036 pte_l2_l_cache_mode = L2_B|L2_C; 7037 pte_l2_l_wc_mode = L2_B; 7038 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7039 7040 pte_l2_s_cache_mode = L2_B|L2_C; 7041 pte_l2_s_wc_mode = L2_B; 7042 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7043 7044 pte_l1_s_cache_mode_pt = L1_S_C; 7045 pte_l2_l_cache_mode_pt = L2_C; 7046 pte_l2_s_cache_mode_pt = L2_C; 7047 7048 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7049 /* 7050 * The XScale core has an enhanced mode where writes that 7051 * miss the cache cause a cache line to be allocated. This 7052 * is significantly faster than the traditional, write-through 7053 * behavior of this case. 7054 */ 7055 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7056 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7057 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7058 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7059 7060 #ifdef XSCALE_CACHE_WRITE_THROUGH 7061 /* 7062 * Some versions of the XScale core have various bugs in 7063 * their cache units, the work-around for which is to run 7064 * the cache in write-through mode. Unfortunately, this 7065 * has a major (negative) impact on performance. So, we 7066 * go ahead and run fast-and-loose, in the hopes that we 7067 * don't line up the planets in a way that will trip the 7068 * bugs. 7069 * 7070 * However, we give you the option to be slow-but-correct. 7071 */ 7072 write_through = 1; 7073 #elif defined(XSCALE_CACHE_WRITE_BACK) 7074 /* force write back cache mode */ 7075 write_through = 0; 7076 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7077 /* 7078 * Intel PXA2[15]0 processors are known to have a bug in 7079 * write-back cache on revision 4 and earlier (stepping 7080 * A[01] and B[012]). Fixed for C0 and later. 7081 */ 7082 { 7083 uint32_t id, type; 7084 7085 id = cpufunc_id(); 7086 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7087 7088 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7089 if ((id & CPU_ID_REVISION_MASK) < 5) { 7090 /* write through for stepping A0-1 and B0-2 */ 7091 write_through = 1; 7092 } 7093 } 7094 } 7095 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7096 7097 if (write_through) { 7098 pte_l1_s_cache_mode = L1_S_C; 7099 pte_l2_l_cache_mode = L2_C; 7100 pte_l2_s_cache_mode = L2_C; 7101 } 7102 7103 #if (ARM_NMMUS > 1) 7104 xscale_use_minidata = 1; 7105 #endif 7106 7107 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7108 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7109 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7110 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7111 7112 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7113 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7114 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7115 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7116 7117 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7118 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7119 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7120 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7121 7122 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7123 pte_l1_s_proto = L1_S_PROTO_xscale; 7124 pte_l1_c_proto = L1_C_PROTO_xscale; 7125 pte_l2_s_proto = L2_S_PROTO_xscale; 7126 7127 pmap_copy_page_func = pmap_copy_page_xscale; 7128 pmap_zero_page_func = pmap_zero_page_xscale; 7129 7130 /* 7131 * Disable ECC protection of page table access, for now. 7132 */ 7133 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7134 auxctl &= ~XSCALE_AUXCTL_P; 7135 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7136 } 7137 7138 /* 7139 * xscale_setup_minidata: 7140 * 7141 * Set up the mini-data cache clean area. We require the 7142 * caller to allocate the right amount of physically and 7143 * virtually contiguous space. 7144 */ 7145 void 7146 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7147 { 7148 extern vaddr_t xscale_minidata_clean_addr; 7149 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7150 pd_entry_t *pde = (pd_entry_t *) l1pt; 7151 vsize_t size; 7152 uint32_t auxctl; 7153 7154 xscale_minidata_clean_addr = va; 7155 7156 /* Round it to page size. */ 7157 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7158 7159 for (; size != 0; 7160 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7161 const size_t l1slot = l1pte_index(va); 7162 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7163 if (ptep == NULL) 7164 panic("xscale_setup_minidata: can't find L2 table for " 7165 "VA 0x%08lx", va); 7166 7167 ptep += l2pte_index(va); 7168 pt_entry_t opte = *ptep; 7169 l2pte_set(ptep, 7170 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7171 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7172 } 7173 7174 /* 7175 * Configure the mini-data cache for write-back with 7176 * read/write-allocate. 7177 * 7178 * NOTE: In order to reconfigure the mini-data cache, we must 7179 * make sure it contains no valid data! In order to do that, 7180 * we must issue a global data cache invalidate command! 7181 * 7182 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7183 * THIS IS VERY IMPORTANT! 7184 */ 7185 7186 /* Invalidate data and mini-data. */ 7187 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7188 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7189 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7190 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7191 } 7192 7193 /* 7194 * Change the PTEs for the specified kernel mappings such that they 7195 * will use the mini data cache instead of the main data cache. 7196 */ 7197 void 7198 pmap_uarea(vaddr_t va) 7199 { 7200 vaddr_t next_bucket, eva; 7201 7202 #if (ARM_NMMUS > 1) 7203 if (xscale_use_minidata == 0) 7204 return; 7205 #endif 7206 7207 eva = va + USPACE; 7208 7209 while (va < eva) { 7210 next_bucket = L2_NEXT_BUCKET_VA(va); 7211 if (next_bucket > eva) 7212 next_bucket = eva; 7213 7214 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7215 KDASSERT(l2b != NULL); 7216 7217 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7218 pt_entry_t *ptep = sptep; 7219 7220 while (va < next_bucket) { 7221 const pt_entry_t opte = *ptep; 7222 if (!l2pte_minidata_p(opte)) { 7223 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7224 cpu_tlb_flushD_SE(va); 7225 l2pte_set(ptep, opte & ~L2_B, opte); 7226 } 7227 ptep += PAGE_SIZE / L2_S_SIZE; 7228 va += PAGE_SIZE; 7229 } 7230 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7231 } 7232 cpu_cpwait(); 7233 } 7234 #endif /* ARM_MMU_XSCALE == 1 */ 7235 7236 7237 #if defined(CPU_ARM11MPCORE) 7238 7239 void 7240 pmap_pte_init_arm11mpcore(void) 7241 { 7242 7243 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7244 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7245 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7246 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7247 /* use extended small page (without APn, with TEX) */ 7248 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7249 #else 7250 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7251 #endif 7252 7253 /* write-back, write-allocate */ 7254 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7255 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7256 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7257 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7258 #else 7259 /* no TEX. read-allocate */ 7260 pte_l2_s_cache_mode = L2_C | L2_B; 7261 #endif 7262 /* 7263 * write-back, write-allocate for page tables. 7264 */ 7265 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7266 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7267 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7268 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7269 #else 7270 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7271 #endif 7272 7273 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7274 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7275 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7276 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7277 7278 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7279 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7280 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7281 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7282 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7283 7284 #else 7285 /* with AP[0..3] */ 7286 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7287 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7288 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7289 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7290 #endif 7291 7292 #ifdef ARM11MPCORE_COMPAT_MMU 7293 /* with AP[0..3] */ 7294 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7295 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7296 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7297 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7298 7299 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7300 pte_l1_s_proto = L1_S_PROTO_armv6; 7301 pte_l1_c_proto = L1_C_PROTO_armv6; 7302 pte_l2_s_proto = L2_S_PROTO_armv6c; 7303 #else 7304 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7305 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7306 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7307 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7308 7309 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7310 pte_l1_s_proto = L1_S_PROTO_armv6; 7311 pte_l1_c_proto = L1_C_PROTO_armv6; 7312 pte_l2_s_proto = L2_S_PROTO_armv6n; 7313 #endif 7314 7315 pmap_copy_page_func = pmap_copy_page_generic; 7316 pmap_zero_page_func = pmap_zero_page_generic; 7317 pmap_needs_pte_sync = 1; 7318 } 7319 #endif /* CPU_ARM11MPCORE */ 7320 7321 7322 #if ARM_MMU_V7 == 1 7323 void 7324 pmap_pte_init_armv7(void) 7325 { 7326 /* 7327 * The ARMv7-A MMU is mostly compatible with generic. If the 7328 * AP field is zero, that now means "no access" rather than 7329 * read-only. The prototypes are a little different because of 7330 * the XN bit. 7331 */ 7332 pmap_pte_init_generic(); 7333 7334 pmap_needs_pte_sync = 1; 7335 7336 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7337 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7338 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7339 7340 /* 7341 * If the core support coherent walk then updates to translation tables 7342 * do not require a clean to the point of unification to ensure 7343 * visibility by subsequent translation table walks. That means we can 7344 * map everything shareable and cached and the right thing will happen. 7345 */ 7346 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7347 pmap_needs_pte_sync = 0; 7348 7349 /* 7350 * write-back, no write-allocate, shareable for normal pages. 7351 */ 7352 pte_l1_s_cache_mode |= L1_S_V6_S; 7353 pte_l2_l_cache_mode |= L2_XS_S; 7354 pte_l2_s_cache_mode |= L2_XS_S; 7355 } 7356 7357 /* 7358 * Page tables are just all other memory. We can use write-back since 7359 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7360 */ 7361 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7362 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7363 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7364 7365 /* 7366 * Check the Memory Model Features to see if this CPU supports 7367 * the TLBIASID coproc op. 7368 */ 7369 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7370 arm_has_tlbiasid_p = true; 7371 } 7372 7373 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7374 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7375 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7376 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7377 7378 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7379 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7380 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7381 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7382 7383 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7384 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7385 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7386 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7387 7388 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7389 pte_l1_s_proto = L1_S_PROTO_armv7; 7390 pte_l1_c_proto = L1_C_PROTO_armv7; 7391 pte_l2_s_proto = L2_S_PROTO_armv7; 7392 7393 } 7394 #endif /* ARM_MMU_V7 */ 7395 7396 /* 7397 * return the PA of the current L1 table, for use when handling a crash dump 7398 */ 7399 uint32_t 7400 pmap_kernel_L1_addr(void) 7401 { 7402 #ifdef ARM_MMU_EXTENDED 7403 return pmap_kernel()->pm_l1_pa; 7404 #else 7405 return pmap_kernel()->pm_l1->l1_physaddr; 7406 #endif 7407 } 7408 7409 #if defined(DDB) 7410 /* 7411 * A couple of ddb-callable functions for dumping pmaps 7412 */ 7413 void pmap_dump_all(void); 7414 void pmap_dump(pmap_t); 7415 7416 void 7417 pmap_dump_all(void) 7418 { 7419 pmap_t pm; 7420 7421 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7422 if (pm == pmap_kernel()) 7423 continue; 7424 pmap_dump(pm); 7425 printf("\n"); 7426 } 7427 } 7428 7429 static pt_entry_t ncptes[64]; 7430 static void pmap_dump_ncpg(pmap_t); 7431 7432 void 7433 pmap_dump(pmap_t pm) 7434 { 7435 struct l2_dtable *l2; 7436 struct l2_bucket *l2b; 7437 pt_entry_t *ptep, pte; 7438 vaddr_t l2_va, l2b_va, va; 7439 int i, j, k, occ, rows = 0; 7440 7441 if (pm == pmap_kernel()) 7442 printf("pmap_kernel (%p): ", pm); 7443 else 7444 printf("user pmap (%p): ", pm); 7445 7446 #ifdef ARM_MMU_EXTENDED 7447 printf("l1 at %p\n", pmap_l1_kva(pm)); 7448 #else 7449 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7450 #endif 7451 7452 l2_va = 0; 7453 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7454 l2 = pm->pm_l2[i]; 7455 7456 if (l2 == NULL || l2->l2_occupancy == 0) 7457 continue; 7458 7459 l2b_va = l2_va; 7460 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7461 l2b = &l2->l2_bucket[j]; 7462 7463 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7464 continue; 7465 7466 ptep = l2b->l2b_kva; 7467 7468 for (k = 0; k < 256 && ptep[k] == 0; k++) 7469 ; 7470 7471 k &= ~63; 7472 occ = l2b->l2b_occupancy; 7473 va = l2b_va + (k * 4096); 7474 for (; k < 256; k++, va += 0x1000) { 7475 char ch = ' '; 7476 if ((k % 64) == 0) { 7477 if ((rows % 8) == 0) { 7478 printf( 7479 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7480 } 7481 printf("%08lx: ", va); 7482 } 7483 7484 ncptes[k & 63] = 0; 7485 pte = ptep[k]; 7486 if (pte == 0) { 7487 ch = '.'; 7488 } else { 7489 occ--; 7490 switch (pte & 0x0c) { 7491 case 0x00: 7492 ch = 'D'; /* No cache No buff */ 7493 break; 7494 case 0x04: 7495 ch = 'B'; /* No cache buff */ 7496 break; 7497 case 0x08: 7498 if (pte & 0x40) 7499 ch = 'm'; 7500 else 7501 ch = 'C'; /* Cache No buff */ 7502 break; 7503 case 0x0c: 7504 ch = 'F'; /* Cache Buff */ 7505 break; 7506 } 7507 7508 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7509 ch += 0x20; 7510 7511 if ((pte & 0xc) == 0) 7512 ncptes[k & 63] = pte; 7513 } 7514 7515 if ((k % 64) == 63) { 7516 rows++; 7517 printf("%c\n", ch); 7518 pmap_dump_ncpg(pm); 7519 if (occ == 0) 7520 break; 7521 } else 7522 printf("%c", ch); 7523 } 7524 } 7525 } 7526 } 7527 7528 static void 7529 pmap_dump_ncpg(pmap_t pm) 7530 { 7531 struct vm_page *pg; 7532 struct vm_page_md *md; 7533 struct pv_entry *pv; 7534 int i; 7535 7536 for (i = 0; i < 63; i++) { 7537 if (ncptes[i] == 0) 7538 continue; 7539 7540 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7541 if (pg == NULL) 7542 continue; 7543 md = VM_PAGE_TO_MD(pg); 7544 7545 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7546 VM_PAGE_TO_PHYS(pg), 7547 md->krw_mappings, md->kro_mappings, 7548 md->urw_mappings, md->uro_mappings); 7549 7550 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7551 printf(" %c va 0x%08lx, flags 0x%x\n", 7552 (pm == pv->pv_pmap) ? '*' : ' ', 7553 pv->pv_va, pv->pv_flags); 7554 } 7555 } 7556 } 7557 #endif 7558 7559 #ifdef PMAP_STEAL_MEMORY 7560 void 7561 pmap_boot_pageadd(pv_addr_t *newpv) 7562 { 7563 pv_addr_t *pv, *npv; 7564 7565 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7566 if (newpv->pv_pa < pv->pv_va) { 7567 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7568 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7569 newpv->pv_size += pv->pv_size; 7570 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7571 } 7572 pv = NULL; 7573 } else { 7574 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7575 pv = npv) { 7576 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7577 KASSERT(pv->pv_pa < newpv->pv_pa); 7578 if (newpv->pv_pa > npv->pv_pa) 7579 continue; 7580 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7581 pv->pv_size += newpv->pv_size; 7582 return; 7583 } 7584 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7585 break; 7586 newpv->pv_size += npv->pv_size; 7587 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7588 SLIST_REMOVE_AFTER(newpv, pv_list); 7589 return; 7590 } 7591 } 7592 } 7593 7594 if (pv) { 7595 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7596 } else { 7597 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7598 } 7599 } 7600 7601 void 7602 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7603 pv_addr_t *rpv) 7604 { 7605 pv_addr_t *pv, **pvp; 7606 struct vm_physseg *ps; 7607 size_t i; 7608 7609 KASSERT(amount & PGOFSET); 7610 KASSERT((mask & PGOFSET) == 0); 7611 KASSERT((match & PGOFSET) == 0); 7612 KASSERT(amount != 0); 7613 7614 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7615 (pv = *pvp) != NULL; 7616 pvp = &SLIST_NEXT(pv, pv_list)) { 7617 pv_addr_t *newpv; 7618 psize_t off; 7619 /* 7620 * If this entry is too small to satify the request... 7621 */ 7622 KASSERT(pv->pv_size > 0); 7623 if (pv->pv_size < amount) 7624 continue; 7625 7626 for (off = 0; off <= mask; off += PAGE_SIZE) { 7627 if (((pv->pv_pa + off) & mask) == match 7628 && off + amount <= pv->pv_size) 7629 break; 7630 } 7631 if (off > mask) 7632 continue; 7633 7634 rpv->pv_va = pv->pv_va + off; 7635 rpv->pv_pa = pv->pv_pa + off; 7636 rpv->pv_size = amount; 7637 pv->pv_size -= amount; 7638 if (pv->pv_size == 0) { 7639 KASSERT(off == 0); 7640 KASSERT((vaddr_t) pv == rpv->pv_va); 7641 *pvp = SLIST_NEXT(pv, pv_list); 7642 } else if (off == 0) { 7643 KASSERT((vaddr_t) pv == rpv->pv_va); 7644 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7645 *newpv = *pv; 7646 newpv->pv_pa += amount; 7647 newpv->pv_va += amount; 7648 *pvp = newpv; 7649 } else if (off < pv->pv_size) { 7650 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7651 *newpv = *pv; 7652 newpv->pv_size -= off; 7653 newpv->pv_pa += off + amount; 7654 newpv->pv_va += off + amount; 7655 7656 SLIST_NEXT(pv, pv_list) = newpv; 7657 pv->pv_size = off; 7658 } else { 7659 KASSERT((vaddr_t) pv != rpv->pv_va); 7660 } 7661 memset((void *)rpv->pv_va, 0, amount); 7662 return; 7663 } 7664 7665 if (vm_nphysseg == 0) 7666 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7667 7668 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7669 (pv = *pvp) != NULL; 7670 pvp = &SLIST_NEXT(pv, pv_list)) { 7671 if (SLIST_NEXT(pv, pv_list) == NULL) 7672 break; 7673 } 7674 KASSERT(mask == 0); 7675 for (i = 0; i < vm_nphysseg; i++) { 7676 ps = VM_PHYSMEM_PTR(i); 7677 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7678 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7679 rpv->pv_va = pv->pv_va; 7680 rpv->pv_pa = pv->pv_pa; 7681 rpv->pv_size = amount; 7682 *pvp = NULL; 7683 pmap_map_chunk(kernel_l1pt.pv_va, 7684 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7685 ptoa(ps->avail_start), 7686 amount - pv->pv_size, 7687 VM_PROT_READ|VM_PROT_WRITE, 7688 PTE_CACHE); 7689 ps->avail_start += atop(amount - pv->pv_size); 7690 /* 7691 * If we consumed the entire physseg, remove it. 7692 */ 7693 if (ps->avail_start == ps->avail_end) { 7694 for (--vm_nphysseg; i < vm_nphysseg; i++) 7695 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7696 } 7697 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7698 return; 7699 } 7700 } 7701 7702 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7703 } 7704 7705 vaddr_t 7706 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7707 { 7708 pv_addr_t pv; 7709 7710 pmap_boot_pagealloc(size, 0, 0, &pv); 7711 7712 return pv.pv_va; 7713 } 7714 #endif /* PMAP_STEAL_MEMORY */ 7715 7716 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7717 { 7718 sysctl_createv(clog, 0, NULL, NULL, 7719 CTLFLAG_PERMANENT, 7720 CTLTYPE_NODE, "machdep", NULL, 7721 NULL, 0, NULL, 0, 7722 CTL_MACHDEP, CTL_EOL); 7723 7724 sysctl_createv(clog, 0, NULL, NULL, 7725 CTLFLAG_PERMANENT, 7726 CTLTYPE_INT, "kmpages", 7727 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7728 NULL, 0, &pmap_kmpages, 0, 7729 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7730 } 7731 7732 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7733 struct vm_page * 7734 arm_pmap_alloc_poolpage(int flags) 7735 { 7736 /* 7737 * On some systems, only some pages may be "coherent" for dma and we 7738 * want to prefer those for pool pages (think mbufs) but fallback to 7739 * any page if none is available. But we can only fallback if we 7740 * aren't direct mapping memory or all of memory can be direct-mapped. 7741 * If that isn't true, pool changes can only come from direct-mapped 7742 * memory. 7743 */ 7744 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7745 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7746 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7747 (pmap_directbase < KERNEL_BASE 7748 ? UVM_PGA_STRAT_ONLY 7749 : UVM_PGA_STRAT_FALLBACK), 7750 #else 7751 UVM_PGA_STRAT_FALLBACK, 7752 #endif 7753 arm_poolpage_vmfreelist); 7754 } 7755 7756 return uvm_pagealloc(NULL, 0, NULL, flags); 7757 } 7758 #endif 7759 7760 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7761 void 7762 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7763 { 7764 /* nothing */ 7765 } 7766 7767 int 7768 pic_ipi_shootdown(void *arg) 7769 { 7770 #if PMAP_NEED_TLB_SHOOTDOWN 7771 pmap_tlb_shootdown_process(); 7772 #endif 7773 return 1; 7774 } 7775 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7776 7777 7778 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7779 vaddr_t 7780 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7781 { 7782 bool ok = false; 7783 if (physical_start <= pa && pa < physical_end) { 7784 #ifdef ARM_MMU_EXTENDED 7785 const vaddr_t newva = pmap_directbase + pa - physical_start; 7786 if (newva >= KERNEL_BASE) { 7787 va = newva; 7788 ok = true; 7789 } 7790 #else 7791 va = KERNEL_BASE + pa - physical_start; 7792 ok = true; 7793 #endif 7794 } 7795 KASSERT(ok_p); 7796 *ok_p = ok; 7797 return va; 7798 } 7799 7800 vaddr_t 7801 pmap_map_poolpage(paddr_t pa) 7802 { 7803 bool ok __diagused; 7804 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7805 KASSERT(ok); 7806 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7807 if (arm_cache_prefer_mask != 0) { 7808 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7809 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7810 pmap_acquire_page_lock(md); 7811 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7812 pmap_release_page_lock(md); 7813 } 7814 #endif 7815 return va; 7816 } 7817 7818 paddr_t 7819 pmap_unmap_poolpage(vaddr_t va) 7820 { 7821 KASSERT(va >= KERNEL_BASE); 7822 #if defined(ARM_MMU_EXTENDED) 7823 return va - pmap_directbase + physical_start; 7824 #else 7825 #ifdef PMAP_CACHE_VIVT 7826 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7827 #endif 7828 return va - KERNEL_BASE + physical_start; 7829 #endif 7830 } 7831 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7832
Indexes created Sat Sep 27 14:09:57 GMT 2025